/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5

Bug Summary

File:	dev/pci/drm/amd/amdgpu/sdma_v5_2.c
Warning:	line 105, column 50 Access to field 'data' results in a dereference of a null pointer (loaded from field 'fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name sdma_v5_2.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

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1/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/

24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>

29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"

33#include "gc/gc_10_3_0_offset.h"
34#include "gc/gc_10_3_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"

40#include "soc15_common.h"
41#include "soc15.h"
42#include "navi10_sdma_pkt_open.h"
43#include "nbio_v2_3.h"
44#include "sdma_common.h"
45#include "sdma_v5_2.h"

47MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");

50#define SDMA1_REG_OFFSET0x600 0x600
51#define SDMA3_REG_OFFSET0x400 0x400
52#define SDMA0_HYP_DEC_REG_START0x5880 0x5880
53#define SDMA0_HYP_DEC_REG_END0x5893 0x5893
54#define SDMA1_HYP_DEC_REG_OFFSET0x20 0x20

56static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
57static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
58static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
59static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);

61static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
62{
u32 base;

if (internal_offset >= SDMA0_HYP_DEC_REG_START0x5880 &&
   internal_offset <= SDMA0_HYP_DEC_REG_END0x5893) {
base = adev->reg_offset[GC_HWIP][0][1];
if (instance != 0)
	internal_offset += SDMA1_HYP_DEC_REG_OFFSET0x20 * instance;
} else {
if (instance < 2) {
	base = adev->reg_offset[GC_HWIP][0][0];
	if (instance == 1)
		internal_offset += SDMA1_REG_OFFSET0x600;
} else {
	base = adev->reg_offset[GC_HWIP][0][2];
	if (instance == 3)
		internal_offset += SDMA3_REG_OFFSET0x400;
}
}

return base + internal_offset;
83}

85static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
86{
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
break;
default:
break;
}
94}

96static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
97{
int err = 0;
const struct sdma_firmware_header_v1_0 *hdr;

err = amdgpu_ucode_validate(sdma_inst->fw);
if (err)
16
←
Assuming 'err' is 0→
17
←
Taking false branch→
return err;

hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
18
←
Access to field 'data' results in a dereference of a null pointer (loaded from field 'fw')
sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));
sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version)((__uint32_t)(hdr->ucode_feature_version));

if (sdma_inst->feature_version >= 20)
sdma_inst->burst_nop = true1;

return 0;
113}

115static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
116{
int i;

for (i = 0; i < adev->sdma.num_instances; i++) {
release_firmware(adev->sdma.instance[i].fw);
adev->sdma.instance[i].fw = NULL((void *)0);

if (adev->asic_type == CHIP_SIENNA_CICHLID)
	break;
}

memset((void*)adev->sdma.instance, 0,__builtin_memset(((void*)adev->sdma.instance), (0), (sizeof
(struct amdgpu_sdma_instance) * 8))
      sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES)__builtin_memset(((void*)adev->sdma.instance), (0), (sizeof
(struct amdgpu_sdma_instance) * 8));
129}

131/**
* sdma_v5_2_init_microcode - load ucode images from disk
*
* @adev: amdgpu_device pointer
*
* Use the firmware interface to load the ucode images into
* the driver (not loaded into hw).
* Returns 0 on success, error on failure.
*/

141// emulation only, won't work on real chip
142// navi10 real chip need to use PSP to load firmware
143static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
144{
const char *chip_name;
char fw_name[40];
int err = 0, i;
struct amdgpu_firmware_info *info = NULL((void *)0);
const struct common_firmware_header *header = NULL((void *)0);

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
4
←
Assuming the condition is false→
5
←
Taking false branch→
return 0;

DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");

switch (adev->asic_type) {
6
←
Control jumps to 'case CHIP_NAVY_FLOUNDER:'  at line 160→
case CHIP_SIENNA_CICHLID:
chip_name = "sienna_cichlid";
break;
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
7
←
 Execution continues on line 167→
default:
BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c"
, 164); } while (0);
}

snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);

err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
8
←
Calling 'request_firmware'→
12
←
Returning from 'request_firmware'→
if (err)
13
←
Assuming 'err' is 0→
14
←
Taking false branch→
goto out;

err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
15
←
Calling 'sdma_v5_2_init_inst_ctx'→
if (err)
goto out;

for (i = 1; i < adev->sdma.num_instances; i++) {
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
    adev->asic_type == CHIP_NAVY_FLOUNDER) {
	memcpy((void*)&adev->sdma.instance[i],__builtin_memcpy(((void*)&adev->sdma.instance[i]), ((void
*)&adev->sdma.instance[0]), (sizeof(struct amdgpu_sdma_instance
)))
	       (void*)&adev->sdma.instance[0],__builtin_memcpy(((void*)&adev->sdma.instance[i]), ((void
*)&adev->sdma.instance[0]), (sizeof(struct amdgpu_sdma_instance
)))
	       sizeof(struct amdgpu_sdma_instance))__builtin_memcpy(((void*)&adev->sdma.instance[i]), ((void
*)&adev->sdma.instance[0]), (sizeof(struct amdgpu_sdma_instance
)));
} else {
	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
	err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
	if (err)
		goto out;
}
}

DRM_DEBUG("psp_load == '%s'\n",__drm_dbg(DRM_UT_CORE, "psp_load == '%s'\n", adev->firmware
.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false")
  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false")__drm_dbg(DRM_UT_CORE, "psp_load == '%s'\n", adev->firmware
.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");

if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
for (i = 0; i < adev->sdma.num_instances; i++) {
	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
	info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
	info->fw = adev->sdma.instance[i].fw;
	header = (const struct common_firmware_header *)info->fw->data;
	adev->firmware.fw_size +=
		roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
}
}

209out:
if (err) {
DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name)__drm_err("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name
);
sdma_v5_2_destroy_inst_ctx(adev);
}
return err;
215}

217static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
218{
unsigned ret;

amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)(((9) & 0x000000FF) << 0));
amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr)));
amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16
)));
amdgpu_ring_write(ring, 1);
ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */

return ret;
229}

231static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
			   unsigned offset)
233{
unsigned cur;

BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c", 236, "!(offset > ring->buf_mask)"
));
BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c"
, 237, "!(ring->ring[offset] != 0x55aa55aa)"));

cur = (ring->wptr - 1) & ring->buf_mask;
if (cur > offset)
ring->ring[offset] = cur - offset;
else
ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
244}

246/**
* sdma_v5_2_ring_get_rptr - get the current read pointer
*
* @ring: amdgpu ring pointer
*
* Get the current rptr from the hardware (NAVI10+).
*/
253static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
254{
u64 *rptr;

/* XXX check if swapping is necessary on BE */
rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);

DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr)__drm_dbg(DRM_UT_CORE, "rptr before shift == 0x%016llx\n", *rptr
);
return ((*rptr) >> 2);
262}

264/**
* sdma_v5_2_ring_get_wptr - get the current write pointer
*
* @ring: amdgpu ring pointer
*
* Get the current wptr from the hardware (NAVI10+).
*/
271static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
272{
struct amdgpu_device *adev = ring->adev;
u64 wptr;

if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]))({ typeof(*((u64 *)&adev->wb.wb[ring->wptr_offs])) __tmp
 = *(volatile typeof(*((u64 *)&adev->wb.wb[ring->wptr_offs
])) *)&(*((u64 *)&adev->wb.wb[ring->wptr_offs])
); membar_datadep_consumer(); __tmp; });
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr)__drm_dbg(DRM_UT_CORE, "wptr/doorbell before shift == 0x%016llx\n"
, wptr);
} else {
wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0086)), 0);
wptr = wptr << 32;
wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0085)), 0);
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr)__drm_dbg(DRM_UT_CORE, "wptr before shift [%i] wptr == 0x%016llx\n"
, ring->me, wptr);
}

return wptr >> 2;
288}

290/**
* sdma_v5_2_ring_set_wptr - commit the write pointer
*
* @ring: amdgpu ring pointer
*
* Write the wptr back to the hardware (NAVI10+).
*/
297static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
298{
struct amdgpu_device *adev = ring->adev;

DRM_DEBUG("Setting write pointer\n")__drm_dbg(DRM_UT_CORE, "Setting write pointer\n");
if (ring->use_doorbell) {
DRM_DEBUG("Using doorbell -- "__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		"wptr_offs == 0x%08x "__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		"lower_32_bits(ring->wptr) << 2 == 0x%08x "__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		ring->wptr_offs,__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		lower_32_bits(ring->wptr << 2),__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
		upper_32_bits(ring->wptr << 2))__drm_dbg(DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
 "lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)));
/* XXX check if swapping is necessary on BE */
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2)((u32)(ring->wptr << 2));
adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2)((u32)(((ring->wptr << 2) >> 16) >> 16));
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",__drm_dbg(DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2)
		ring->doorbell_index, ring->wptr << 2)__drm_dbg(DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2);
WDOORBELL64(ring->doorbell_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr << 2));
} else {
DRM_DEBUG("Not using doorbell -- "__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		"mmSDMA%i_GFX_RB_WPTR == 0x%08x "__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		ring->me,__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		lower_32_bits(ring->wptr << 2),__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		ring->me,__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)))
		upper_32_bits(ring->wptr << 2))__drm_dbg(DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", ring->me, ((u32)(ring
->wptr << 2)), ring->me, ((u32)(((ring->wptr <<
 2) >> 16) >> 16)));
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0085)), (((u32)(ring->wptr << 2))), 0)
	lower_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0085)), (((u32)(ring->wptr << 2))), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0086)), (((u32)(((ring->wptr << 2) >>
 16) >> 16))), 0)
	upper_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring
->me, 0x0086)), (((u32)(((ring->wptr << 2) >>
 16) >> 16))), 0);
}
329}

331static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
332{
struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
int i;

for (i = 0; i < count; i++)
if (sdma && sdma->burst_nop && (i == 0))
	amdgpu_ring_write(ring, ring->funcs->nop |
		SDMA_PKT_NOP_HEADER_COUNT(count - 1)(((count - 1) & 0x00003FFF) << 16));
else
	amdgpu_ring_write(ring, ring->funcs->nop);
342}

344/**
* sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
*
* @ring: amdgpu ring pointer
* @ib: IB object to schedule
*
* Schedule an IB in the DMA ring.
*/
352static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
		   struct amdgpu_job *job,
		   struct amdgpu_ib *ib,
		   uint32_t flags)
356{
unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);

/* An IB packet must end on a 8 DW boundary--the next dword
* must be on a 8-dword boundary. Our IB packet below is 6
* dwords long, thus add x number of NOPs, such that, in
* modular arithmetic,
* wptr + 6 + x = 8k, k >= 0, which in C is,
* (wptr + 6 + x) % 8 = 0.
* The expression below, is a solution of x.
*/
sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)((u32)(ring->wptr))) & 7);

amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT)(((4) & 0x000000FF) << 0) |
	  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)(((vmid & 0xf) & 0x0000000F) << 16));
/* base must be 32 byte aligned */
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)) & 0xffffffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
amdgpu_ring_write(ring, ib->length_dw);
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)((u32)(csa_mc_addr)));
amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)((u32)(((csa_mc_addr) >> 16) >> 16)));
378}

380/**
* sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
*
* @ring: amdgpu ring pointer
*
* Emit an hdp flush packet on the requested DMA ring.
*/
387static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
388{
struct amdgpu_device *adev = ring->adev;
u32 ref_and_mask = 0;
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;

ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;

amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
	  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1)(((1) & 0x00000001) << 26) |
	  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* == */
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
amdgpu_ring_write(ring, ref_and_mask); /* reference */
amdgpu_ring_write(ring, ref_and_mask); /* mask */
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
	  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */
404}

406/**
* sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
*
* @ring: amdgpu ring pointer
* @fence: amdgpu fence object
*
* Add a DMA fence packet to the ring to write
* the fence seq number and DMA trap packet to generate
* an interrupt if needed.
*/
416static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
		      unsigned flags)
418{
bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
/* write the fence */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) |
	  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16)); /* Ucached(UC) */
/* zero in first two bits */
BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c"
, 424, "!(addr & 0x3)"));
amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));

/* optionally write high bits as well */
if (write64bit) {
addr += 4;
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) |
		  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16));
/* zero in first two bits */
BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c"
, 435, "!(addr & 0x3)"));
amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
}

if (flags & AMDGPU_FENCE_FLAG_INT(1 << 1)) {
/* generate an interrupt */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)(((6) & 0x000000FF) << 0));
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)(((0) & 0x0FFFFFFF) << 0));
}
446}


449/**
* sdma_v5_2_gfx_stop - stop the gfx async dma engines
*
* @adev: amdgpu_device pointer
*
* Stop the gfx async dma ring buffers.
*/
456static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
457{
struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
u32 rb_cntl, ib_cntl;
int i;

if ((adev->mman.buffer_funcs_ring == sdma0) ||
   (adev->mman.buffer_funcs_ring == sdma1) ||
   (adev->mman.buffer_funcs_ring == sdma2) ||
   (adev->mman.buffer_funcs_ring == sdma3))
amdgpu_ttm_set_buffer_funcs_status(adev, false0);

for (i = 0; i < adev->sdma.num_instances; i++) {
rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0080
)), 0);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((0) <<
 0x0)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0080
)), (rb_cntl), 0);
ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x008a
)), 0);
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((0) <<
 0x0)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x008a
)), (ib_cntl), 0);
}
479}

481/**
* sdma_v5_2_rlc_stop - stop the compute async dma engines
*
* @adev: amdgpu_device pointer
*
* Stop the compute async dma queues.
*/
488static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
489{
/* XXX todo */
491}

493/**
* sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
*
* @adev: amdgpu_device pointer
* @enable: enable/disable the DMA MEs context switch.
*
* Halt or unhalt the async dma engines context switch.
*/
501static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool_Bool enable)
502{
u32 f32_cntl, phase_quantum = 0;
int i;

if (amdgpu_sdma_phase_quantum) {
unsigned value = amdgpu_sdma_phase_quantum;
unsigned unit = 0;

while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >>
		SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8)) {
	value = (value + 1) >> 1;
	unit++;
}
if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >>
	    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0)) {
	value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >>
		 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8);
	unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >>
		SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0);
	WARN_ONCE(1,({ static int __warned; int __ret = !!(1); if (__ret &&
 !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); })
	"clamping sdma_phase_quantum to %uK clock cycles\n",({ static int __warned; int __ret = !!(1); if (__ret &&
 !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); })
		  value << unit)({ static int __warned; int __ret = !!(1); if (__ret &&
 !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); });
}
phase_quantum =
	value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8 |
	unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0;
}

for (i = 0; i < adev->sdma.num_instances; i++) {
f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c
)), 0);
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable
 ? 1 : 0) << 0x12)))
		AUTO_CTXSW_ENABLE, enable ? 1 : 0)(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable
 ? 1 : 0) << 0x12)));
if (enable && amdgpu_sdma_phase_quantum) {
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002c
)), (phase_quantum), 0)
	       phase_quantum)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002c
)), (phase_quantum), 0);
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002d
)), (phase_quantum), 0)
	       phase_quantum)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002d
)), (phase_quantum), 0);
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x004f
)), (phase_quantum), 0)
	       phase_quantum)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x004f
)), (phase_quantum), 0);
}
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c
)), (f32_cntl), 0);
}

545}

547/**
* sdma_v5_2_enable - stop the async dma engines
*
* @adev: amdgpu_device pointer
* @enable: enable/disable the DMA MEs.
*
* Halt or unhalt the async dma engines.
*/
555static void sdma_v5_2_enable(struct amdgpu_device *adev, bool_Bool enable)
556{
u32 f32_cntl;
int i;

if (!enable) {
sdma_v5_2_gfx_stop(adev);
sdma_v5_2_rlc_stop(adev);
}

for (i = 0; i < adev->sdma.num_instances; i++) {
f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a
)), 0);
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1)(((f32_cntl) & ~0x00000001L) | (0x00000001L & ((enable
 ? 0 : 1) << 0x0)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a
)), (f32_cntl), 0);
}
570}

572/**
* sdma_v5_2_gfx_resume - setup and start the async dma engines
*
* @adev: amdgpu_device pointer
*
* Set up the gfx DMA ring buffers and enable them.
* Returns 0 for success, error for failure.
*/
580static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
581{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
u32 rb_bufsz;
u32 wb_offset;
u32 doorbell;
u32 doorbell_offset;
u32 temp;
u32 wptr_poll_cntl;
u64 wptr_gpu_addr;
int i, r;

for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
wb_offset = (ring->rptr_offs * 4);

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0021
)), (0), 0);

/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4);
rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0080
)), 0);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz)(((rb_cntl) & ~0x0000003EL) | (0x0000003EL & ((rb_bufsz
) << 0x1)));
603#ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00000200L) | (0x00000200L & ((1) <<
 0x9)));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) <<
 0xd)))
			RPTR_WRITEBACK_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) <<
 0xd)));
607#endif
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0080
)), (rb_cntl), 0);

/* Initialize the ring buffer's read and write pointers */
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0083
)), (0), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0084
)), (0), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0085
)), (0), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0086
)), (0), 0);

/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b3
)), (((u32)(wptr_gpu_addr))), 0)
       lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b3
)), (((u32)(wptr_gpu_addr))), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b2
)), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0)
       upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b2
)), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0);
wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0087
)), 0)
					 mmSDMA0_GFX_RB_WPTR_POLL_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0087
)), 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
			       SDMA0_GFX_RB_WPTR_POLL_CNTL,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
			       F32_POLL_ENABLE, 1)(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0087
)), (wptr_poll_cntl), 0)
       wptr_poll_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0087
)), (wptr_poll_cntl), 0);

/* set the wb address whether it's enabled or not */
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0088
)), (((u32)(((adev->wb.gpu_addr + wb_offset) >> 16) >>
 16)) & 0xFFFFFFFF), 0)
       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0088
)), (((u32)(((adev->wb.gpu_addr + wb_offset) >> 16) >>
 16)) & 0xFFFFFFFF), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0089
)), (((u32)(adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC
), 0)
       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0089
)), (((u32)(adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC
), 0);

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1)(((rb_cntl) & ~0x00001000L) | (0x00001000L & ((1) <<
 0xc)));

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0081
)), (ring->gpu_addr >> 8), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0082
)), (ring->gpu_addr >> 40), 0);

ring->wptr = 0;

/* before programing wptr to a less value, need set minor_ptr_update first */
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b5
)), (1), 0);

if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* only bare-metal use register write for wptr */
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0085
)), (((u32)(ring->wptr)) << 2), 0);
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0086
)), (((u32)(((ring->wptr) >> 16) >> 16)) <<
 2), 0);
}

doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0092
)), 0);
doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00ab
)), 0);

if (ring->use_doorbell) {
	doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1)(((doorbell) & ~0x10000000L) | (0x10000000L & ((1) <<
 0x1c)));
	doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & (
(ring->doorbell_index) << 0x2)))
			OFFSET, ring->doorbell_index)(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & (
(ring->doorbell_index) << 0x2)));
} else {
	doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0)(((doorbell) & ~0x10000000L) | (0x10000000L & ((0) <<
 0x1c)));
}
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0092
)), (doorbell), 0);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00ab
)), (doorbell_offset), 0);

adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
				      ring->doorbell_index,
				      adev->doorbell_index.sdma_doorbell_range);

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
	sdma_v5_2_ring_set_wptr(ring);

/* set minor_ptr_update to 0 after wptr programed */
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b5
)), (0), 0);

/* set utc l1 enable flag always to 1 */
temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c
)), 0);
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1)(((temp) & ~0x00000002L) | (0x00000002L & ((1) <<
 0x1)));

/* enable MCBP */
temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1)(((temp) & ~0x00000020L) | (0x00000020L & ((1) <<
 0x5)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c
)), (temp), 0);

/* Set up RESP_MODE to non-copy addresses */
temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x003c
)), 0);
temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3)(((temp) & ~0x00000E00L) | (0x00000E00L & ((3) <<
 0x9)));
temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9)(((temp) & ~0x0000003EL) | (0x0000003EL & ((9) <<
 0x1)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x003c
)), (temp), 0);

/* program default cache read and write policy */
temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0048
)), 0);
/* clean read policy and write policy bits */
temp &= 0xFF0FFF;
temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
	 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
	 0x01000000);
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0048
)), (temp), 0);

if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
	/* unhalt engine */
	temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a
)), 0);
	temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0)(((temp) & ~0x00000001L) | (0x00000001L & ((0) <<
 0x0)));
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a
)), (temp), 0);
}

/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((1) <<
 0x0)));
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0080
)), (rb_cntl), 0);

ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x008a
)), 0);
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((1) <<
 0x0)));
710#ifdef __BIG_ENDIAN
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)(((ib_cntl) & ~0x00000010L) | (0x00000010L & ((1) <<
 0x4)));
712#endif
/* enable DMA IBs */
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x008a
)), (ib_cntl), 0);

ring->sched.ready = true1;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* bare-metal sequence doesn't need below to lines */
	sdma_v5_2_ctx_switch_enable(adev, true1);
	sdma_v5_2_enable(adev, true1);
}

r = amdgpu_ring_test_ring(ring)(ring)->funcs->test_ring((ring));
if (r) {
	ring->sched.ready = false0;
	return r;
}

if (adev->mman.buffer_funcs_ring == ring)
	amdgpu_ttm_set_buffer_funcs_status(adev, true1);
}

return 0;
734}

736/**
* sdma_v5_2_rlc_resume - setup and start the async dma engines
*
* @adev: amdgpu_device pointer
*
* Set up the compute DMA queues and enable them.
* Returns 0 for success, error for failure.
*/
744static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
745{
return 0;
747}

749/**
* sdma_v5_2_load_microcode - load the sDMA ME ucode
*
* @adev: amdgpu_device pointer
*
* Loads the sDMA0/1/2/3 ucode.
* Returns 0 for success, -EINVAL if the ucode is not available.
*/
757static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
758{
const struct sdma_firmware_header_v1_0 *hdr;
const __le32 *fw_data;
u32 fw_size;
int i, j;

/* halt the MEs */
sdma_v5_2_enable(adev, false0);

for (i = 0; i < adev->sdma.num_instances; i++) {
if (!adev->sdma.instance[i].fw)
	return -EINVAL22;

hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
amdgpu_ucode_print_sdma_hdr(&hdr->header);
fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4;

fw_data = (const __le32 *)
	(adev->sdma.instance[i].fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5880
)), (0), 0);

for (j = 0; j < fw_size; j++) {
	if (amdgpu_emu_mode == 1 && j % 500 == 0)
		drm_msleep(1)mdelay(1);
	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5881
)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
}

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5880
)), (adev->sdma.instance[i].fw_version), 0);
}

return 0;
791}

793/**
* sdma_v5_2_start - setup and start the async dma engines
*
* @adev: amdgpu_device pointer
*
* Set up the DMA engines and enable them.
* Returns 0 for success, error for failure.
*/
801static int sdma_v5_2_start(struct amdgpu_device *adev)
802{
int r = 0;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
sdma_v5_2_ctx_switch_enable(adev, false0);
sdma_v5_2_enable(adev, false0);

/* set RB registers */
r = sdma_v5_2_gfx_resume(adev);
return r;
}

if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
r = sdma_v5_2_load_microcode(adev);
if (r)
	return r;

/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
if (amdgpu_emu_mode == 1)
	drm_msleep(1000)mdelay(1000);
}

/* unhalt the MEs */
sdma_v5_2_enable(adev, true1);
/* enable sdma ring preemption */
sdma_v5_2_ctx_switch_enable(adev, true1);

/* start the gfx rings and rlc compute queues */
r = sdma_v5_2_gfx_resume(adev);
if (r)
return r;
r = sdma_v5_2_rlc_resume(adev);

return r;
836}

838/**
* sdma_v5_2_ring_test_ring - simple async dma engine test
*
* @ring: amdgpu_ring structure holding ring information
*
* Test the DMA engine by writing using it to write an
* value to memory.
* Returns 0 for success, error for failure.
*/
847static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
848{
struct amdgpu_device *adev = ring->adev;
unsigned i;
unsigned index;
int r;
u32 tmp;
u64 gpu_addr;

r = amdgpu_device_wb_get(adev, &index);
if (r) {
dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to allocate wb slot\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));

r = amdgpu_ring_alloc(ring, 5);
if (r) {
DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r)__drm_err("amdgpu: dma failed to lock ring %d (%d).\n", ring->
idx, r);
amdgpu_device_wb_free(adev, index);
return r;
}

amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
	  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8));
amdgpu_ring_write(ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
amdgpu_ring_write(ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0));
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);

for (i = 0; i < adev->usec_timeout; i++) {
tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
if (tmp == 0xDEADBEEF)
	break;
if (amdgpu_emu_mode == 1)
	drm_msleep(1)mdelay(1);
else
	udelay(1);
}

if (i >= adev->usec_timeout)
r = -ETIMEDOUT60;

amdgpu_device_wb_free(adev, index);

return r;
897}

899/**
* sdma_v5_2_ring_test_ib - test an IB on the DMA engine
*
* @ring: amdgpu_ring structure holding ring information
*
* Test a simple IB in the DMA ring.
* Returns 0 on success, error on failure.
*/
907static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
908{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_ib ib;
struct dma_fence *f = NULL((void *)0);
unsigned index;
long r;
u32 tmp = 0;
u64 gpu_addr;

r = amdgpu_device_wb_get(adev, &index);
if (r) {
dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%ld) failed to allocate wb slot\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));
memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
r = amdgpu_ib_get(adev, NULL((void *)0), 256, AMDGPU_IB_POOL_DIRECT, &ib);
if (r) {
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r)__drm_err("amdgpu: failed to get ib (%ld).\n", r);
goto err0;
}

ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
ib.ptr[1] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
ib.ptr[2] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0);
ib.ptr[4] = 0xDEADBEEF;
ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
ib.length_dw = 8;

r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
if (r)
goto err1;

r = dma_fence_wait_timeout(f, false0, timeout);
if (r == 0) {
DRM_ERROR("amdgpu: IB test timed out\n")__drm_err("amdgpu: IB test timed out\n");
r = -ETIMEDOUT60;
goto err1;
} else if (r < 0) {
DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r)__drm_err("amdgpu: fence wait failed (%ld).\n", r);
goto err1;
}
tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
if (tmp == 0xDEADBEEF)
r = 0;
else
r = -EINVAL22;

963err1:
amdgpu_ib_free(adev, &ib, NULL((void *)0));
dma_fence_put(f);
966err0:
amdgpu_device_wb_free(adev, index);
return r;
969}


972/**
* sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
*
* @ib: indirect buffer to fill with commands
* @pe: addr of the page entry
* @src: src addr to copy from
* @count: number of page entries to update
*
* Update PTEs by copying them from the GART using sDMA.
*/
982static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
		  uint64_t pe, uint64_t src,
		  unsigned count)
985{
unsigned bytes = count * 8;

ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8);
ib->ptr[ib->length_dw++] = bytes - 1;
ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
ib->ptr[ib->length_dw++] = lower_32_bits(src)((u32)(src));
ib->ptr[ib->length_dw++] = upper_32_bits(src)((u32)(((src) >> 16) >> 16));
ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe));
ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));

997}

999/**
* sdma_v5_2_vm_write_pte - update PTEs by writing them manually
*
* @ib: indirect buffer to fill with commands
* @pe: addr of the page entry
* @addr: dst addr to write into pe
* @count: number of page entries to update
* @incr: increase next addr by incr bytes
* @flags: access flags
*
* Update PTEs by writing them manually using sDMA.
*/
1011static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
		   uint64_t value, unsigned count,
		   uint32_t incr)
1014{
unsigned ndw = count * 2;

ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe));
ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
ib->ptr[ib->length_dw++] = ndw - 1;
for (; ndw > 0; ndw -= 2) {
ib->ptr[ib->length_dw++] = lower_32_bits(value)((u32)(value));
ib->ptr[ib->length_dw++] = upper_32_bits(value)((u32)(((value) >> 16) >> 16));
value += incr;
}
1027}

1029/**
* sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
*
* @ib: indirect buffer to fill with commands
* @pe: addr of the page entry
* @addr: dst addr to write into pe
* @count: number of page entries to update
* @incr: increase next addr by incr bytes
* @flags: access flags
*
* Update the page tables using sDMA.
*/
1041static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
		     uint64_t pe,
		     uint64_t addr, unsigned count,
		     uint32_t incr, uint64_t flags)
1045{
/* for physically contiguous pages (vram) */
ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE)(((12) & 0x000000FF) << 0);
ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); /* dst addr */
ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
ib->ptr[ib->length_dw++] = lower_32_bits(flags)((u32)(flags)); /* mask */
ib->ptr[ib->length_dw++] = upper_32_bits(flags)((u32)(((flags) >> 16) >> 16));
ib->ptr[ib->length_dw++] = lower_32_bits(addr)((u32)(addr)); /* value */
ib->ptr[ib->length_dw++] = upper_32_bits(addr)((u32)(((addr) >> 16) >> 16));
ib->ptr[ib->length_dw++] = incr; /* increment size */
ib->ptr[ib->length_dw++] = 0;
ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1057}

1059/**
* sdma_v5_2_ring_pad_ib - pad the IB
*
* @ib: indirect buffer to fill with padding
*
* Pad the IB with NOPs to a boundary multiple of 8.
*/
1066static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1067{
struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
u32 pad_count;
int i;

pad_count = (-ib->length_dw) & 0x7;
for (i = 0; i < pad_count; i++)
if (sdma && sdma->burst_nop && (i == 0))
	ib->ptr[ib->length_dw++] =
		SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0) |
		SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1)(((pad_count - 1) & 0x00003FFF) << 16);
else
	ib->ptr[ib->length_dw++] =
		SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
1081}


1084/**
* sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
*
* @ring: amdgpu_ring pointer
*
* Make sure all previous operations are completed (CIK).
*/
1091static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1092{
uint32_t seq = ring->fence_drv.sync_seq;
uint64_t addr = ring->fence_drv.gpu_addr;

/* wait for idle */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
	  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
	  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28) | /* equal */
	  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)(((1) & 0x00000001) << 31));
amdgpu_ring_write(ring, addr & 0xfffffffc);
amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xffffffff);
amdgpu_ring_write(ring, seq); /* reference */
amdgpu_ring_write(ring, 0xffffffff); /* mask */
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
	  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)(((4) & 0x0000FFFF) << 0)); /* retry count, poll interval */
1107}


1110/**
* sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
*
* @ring: amdgpu_ring pointer
* @vm: amdgpu_vm pointer
*
* Update the page table base and flush the VM TLB
* using sDMA.
*/
1119static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
			 unsigned vmid, uint64_t pd_addr)
1121{
amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
1123}

1125static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
		     uint32_t reg, uint32_t val)
1127{
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE)(((14) & 0x000000FF) << 0) |
	  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)(((0xf) & 0x0000000F) << 28));
amdgpu_ring_write(ring, reg);
amdgpu_ring_write(ring, val);
1132}

1134static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
			 uint32_t val, uint32_t mask)
1136{
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
	  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
	  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* equal */
amdgpu_ring_write(ring, reg << 2);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, val); /* reference */
amdgpu_ring_write(ring, mask); /* mask */
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
	  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0));
1146}

1148static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
				   uint32_t reg0, uint32_t reg1,
				   uint32_t ref, uint32_t mask)
1151{
amdgpu_ring_emit_wreg(ring, reg0, ref)(ring)->funcs->emit_wreg((ring), (reg0), (ref));
/* wait for a cycle to reset vm_inv_eng*_ack */
amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0)(ring)->funcs->emit_reg_wait((ring), (reg0), (0), (0));
amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask)(ring)->funcs->emit_reg_wait((ring), (reg1), (mask), (mask
));
1156}

1158static int sdma_v5_2_early_init(void *handle)
1159{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
adev->sdma.num_instances = 4;
break;
case CHIP_NAVY_FLOUNDER:
adev->sdma.num_instances = 2;
break;
default:
break;
}

sdma_v5_2_set_ring_funcs(adev);
sdma_v5_2_set_buffer_funcs(adev);
sdma_v5_2_set_vm_pte_funcs(adev);
sdma_v5_2_set_irq_funcs(adev);

return 0;
1179}

1181static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1182{
switch (seq_num) {
case 0:
return SOC15_IH_CLIENTID_SDMA0;
case 1:
return SOC15_IH_CLIENTID_SDMA1;
case 2:
return SOC15_IH_CLIENTID_SDMA2;
case 3:
return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
default:
break;
}
return -EINVAL22;
1196}

1198static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1199{
switch (seq_num) {
case 0:
return SDMA0_5_0__SRCID__SDMA_TRAP224;
case 1:
return SDMA1_5_0__SRCID__SDMA_TRAP224;
case 2:
return SDMA2_5_0__SRCID__SDMA_TRAP224;
case 3:
return SDMA3_5_0__SRCID__SDMA_TRAP224;
default:
break;
}
return -EINVAL22;
1213}

1215static int sdma_v5_2_sw_init(void *handle)
1216{
struct amdgpu_ring *ring;
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

/* SDMA trap event */
for (i = 0; i < adev->sdma.num_instances; i++) {
1
Assuming 'i' is >= field 'num_instances'→
2
←
Loop condition is false. Execution continues on line 1230→
r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
		      sdma_v5_2_seq_to_trap_id(i),
		      &adev->sdma.trap_irq);
if (r)
	return r;
}

r = sdma_v5_2_init_microcode(adev);
3
←
Calling 'sdma_v5_2_init_microcode'→
if (r) {
DRM_ERROR("Failed to load sdma firmware!\n")__drm_err("Failed to load sdma firmware!\n");
return r;
}

for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL((void *)0);
ring->use_doorbell = true1;
ring->me = i;

DRM_INFO("use_doorbell being set to: [%s]\n",printk("\0016" "[" "drm" "] " "use_doorbell being set to: [%s]\n"
, ring->use_doorbell?"true":"false")
		ring->use_doorbell?"true":"false")printk("\0016" "[" "drm" "] " "use_doorbell being set to: [%s]\n"
, ring->use_doorbell?"true":"false");

ring->doorbell_index =
	(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset

snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
		     &adev->sdma.trap_irq,
		     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
		     AMDGPU_RING_PRIO_DEFAULT1);
if (r)
	return r;
}

return r;
1258}

1260static int sdma_v5_2_sw_fini(void *handle)
1261{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;

for (i = 0; i < adev->sdma.num_instances; i++)
amdgpu_ring_fini(&adev->sdma.instance[i].ring);

sdma_v5_2_destroy_inst_ctx(adev);

return 0;
1271}

1273static int sdma_v5_2_hw_init(void *handle)
1274{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

sdma_v5_2_init_golden_registers(adev);

r = sdma_v5_2_start(adev);

return r;
1283}

1285static int sdma_v5_2_hw_fini(void *handle)
1286{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
return 0;

sdma_v5_2_ctx_switch_enable(adev, false0);
sdma_v5_2_enable(adev, false0);

return 0;
1296}

1298static int sdma_v5_2_suspend(void *handle)
1299{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

return sdma_v5_2_hw_fini(adev);
1303}

1305static int sdma_v5_2_resume(void *handle)
1306{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

return sdma_v5_2_hw_init(adev);
1310}

1312static bool_Bool sdma_v5_2_is_idle(void *handle)
1313{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 i;

for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0025
)), 0);

if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK0x00000001L))
	return false0;
}

return true1;
1325}

1327static int sdma_v5_2_wait_for_idle(void *handle)
1328{
unsigned i;
u32 sdma0, sdma1, sdma2, sdma3;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

for (i = 0; i < adev->usec_timeout; i++) {
sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x0025
)), 0);
sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 1, 0x0025
)), 0);
sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 2, 0x0025
)), 0);
sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 3, 0x0025
)), 0);

if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK0x00000001L)
	return 0;
udelay(1);
}
return -ETIMEDOUT60;
1344}

1346static int sdma_v5_2_soft_reset(void *handle)
1347{
/* todo */

return 0;
1351}

1353static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1354{
int i, r = 0;
struct amdgpu_device *adev = ring->adev;
u32 index = 0;
u64 sdma_gfx_preempt;

amdgpu_sdma_get_index_from_ring(ring, &index);
sdma_gfx_preempt =
sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT0x00b0);

/* assert preemption condition */
amdgpu_ring_set_preempt_cond_exec(ring, false0);

/* emit the trailing fence */
ring->trail_seq += 1;
amdgpu_ring_alloc(ring, 10);
sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
		  ring->trail_seq, 0);
amdgpu_ring_commit(ring);

/* assert IB preemption */
WREG32(sdma_gfx_preempt, 1)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (1), 0);

/* poll the trailing fence */
for (i = 0; i < adev->usec_timeout; i++) {
if (ring->trail_seq ==
    le32_to_cpu(*(ring->trail_fence_cpu_addr))((__uint32_t)(*(ring->trail_fence_cpu_addr))))
	break;
udelay(1);
}

if (i >= adev->usec_timeout) {
r = -EINVAL22;
DRM_ERROR("ring %d failed to be preempted\n", ring->idx)__drm_err("ring %d failed to be preempted\n", ring->idx);
}

/* deassert IB preemption */
WREG32(sdma_gfx_preempt, 0)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (0), 0);

/* deassert the preemption condition */
amdgpu_ring_set_preempt_cond_exec(ring, true1);
return r;
1396}

1398static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
			struct amdgpu_irq_src *source,
			unsigned type,
			enum amdgpu_interrupt_state state)
1402{
u32 sdma_cntl;

u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL0x001c);

sdma_cntl = RREG32(reg_offset)amdgpu_device_rreg(adev, (reg_offset), 0);
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state
 == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0)))
       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state
 == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0)));
WREG32(reg_offset, sdma_cntl)amdgpu_device_wreg(adev, (reg_offset), (sdma_cntl), 0);

return 0;
1413}

1415static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
		      struct amdgpu_irq_src *source,
		      struct amdgpu_iv_entry *entry)
1418{
DRM_DEBUG("IH: SDMA trap\n")__drm_dbg(DRM_UT_CORE, "IH: SDMA trap\n");
switch (entry->client_id) {
case SOC15_IH_CLIENTID_SDMA0:
switch (entry->ring_id) {
case 0:
	amdgpu_fence_process(&adev->sdma.instance[0].ring);
	break;
case 1:
	/* XXX compute */
	break;
case 2:
	/* XXX compute */
	break;
case 3:
	/* XXX page queue*/
	break;
}
break;
case SOC15_IH_CLIENTID_SDMA1:
switch (entry->ring_id) {
case 0:
	amdgpu_fence_process(&adev->sdma.instance[1].ring);
	break;
case 1:
	/* XXX compute */
	break;
case 2:
	/* XXX compute */
	break;
case 3:
	/* XXX page queue*/
	break;
}
break;
case SOC15_IH_CLIENTID_SDMA2:
switch (entry->ring_id) {
case 0:
	amdgpu_fence_process(&adev->sdma.instance[2].ring);
	break;
case 1:
	/* XXX compute */
	break;
case 2:
	/* XXX compute */
	break;
case 3:
	/* XXX page queue*/
	break;
}
break;
case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
switch (entry->ring_id) {
case 0:
	amdgpu_fence_process(&adev->sdma.instance[3].ring);
	break;
case 1:
	/* XXX compute */
	break;
case 2:
	/* XXX compute */
	break;
case 3:
	/* XXX page queue*/
	break;
}
break;
}
return 0;
1487}

1489static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
			      struct amdgpu_irq_src *source,
			      struct amdgpu_iv_entry *entry)
1492{
return 0;
1494}

1496static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
				       bool_Bool enable)
1498{
uint32_t data, def;
int i;

for (i = 0; i < adev->sdma.num_instances; i++) {
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG(1 << 11))) {
	/* Enable sdma clock gating */
	def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b
)), 0);
	data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x04000000L |
		  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x08000000L |
		  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x10000000L |
		  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x20000000L |
		  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x40000000L |
		  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK0x80000000L);
	if (def != data)
		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b
)), (data), 0);
} else {
	/* Disable sdma clock gating */
	def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b
)), 0);
	data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x04000000L |
		 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x08000000L |
		 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x10000000L |
		 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x20000000L |
		 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x40000000L |
		 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK0x80000000L);
	if (def != data)
		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b
)), (data), 0);
}
}
1527}

1529static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
				      bool_Bool enable)
1531{
uint32_t data, def;
int i;

for (i = 0; i < adev->sdma.num_instances; i++) {
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS(1 << 10))) {
	/* Enable sdma mem light sleep */
	def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a
)), 0);
	data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L;
	if (def != data)
		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a
)), (data), 0);

} else {
	/* Disable sdma mem light sleep */
	def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a
)), 0);
	data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L;
	if (def != data)
		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a
)), (data), 0);

}
}
1552}

1554static int sdma_v5_2_set_clockgating_state(void *handle,
			   enum amd_clockgating_state state)
1556{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
return 0;

switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
sdma_v5_2_update_medium_grain_clock_gating(adev,
		state == AMD_CG_STATE_GATE ? true1 : false0);
sdma_v5_2_update_medium_grain_light_sleep(adev,
		state == AMD_CG_STATE_GATE ? true1 : false0);
break;
default:
break;
}

return 0;
1575}

1577static int sdma_v5_2_set_powergating_state(void *handle,
			  enum amd_powergating_state state)
1579{
return 0;
1581}

1583static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1584{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
*flags = 0;

/* AMD_CG_SUPPORT_SDMA_LS */
data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL))amdgpu_kiq_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x001a
)));
if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L)
*flags |= AMD_CG_SUPPORT_SDMA_LS(1 << 10);
1595}

1597const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
.name = "sdma_v5_2",
.early_init = sdma_v5_2_early_init,
.late_init = NULL((void *)0),
.sw_init = sdma_v5_2_sw_init,
.sw_fini = sdma_v5_2_sw_fini,
.hw_init = sdma_v5_2_hw_init,
.hw_fini = sdma_v5_2_hw_fini,
.suspend = sdma_v5_2_suspend,
.resume = sdma_v5_2_resume,
.is_idle = sdma_v5_2_is_idle,
.wait_for_idle = sdma_v5_2_wait_for_idle,
.soft_reset = sdma_v5_2_soft_reset,
.set_clockgating_state = sdma_v5_2_set_clockgating_state,
.set_powergating_state = sdma_v5_2_set_powergating_state,
.get_clockgating_state = sdma_v5_2_get_clockgating_state,
1613};

1615static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
.align_mask = 0xf,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0),
.support_64bit_ptrs = true1,
.vmhub = AMDGPU_GFXHUB_00,
.get_rptr = sdma_v5_2_ring_get_rptr,
.get_wptr = sdma_v5_2_ring_get_wptr,
.set_wptr = sdma_v5_2_ring_set_wptr,
.emit_frame_size =
5 + /* sdma_v5_2_ring_init_cond_exec */
6 + /* sdma_v5_2_ring_emit_hdp_flush */
3 + /* hdp_invalidate */
6 + /* sdma_v5_2_ring_emit_pipeline_sync */
/* sdma_v5_2_ring_emit_vm_flush */
SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 6 +
10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
.emit_ib = sdma_v5_2_ring_emit_ib,
.emit_fence = sdma_v5_2_ring_emit_fence,
.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
.test_ring = sdma_v5_2_ring_test_ring,
.test_ib = sdma_v5_2_ring_test_ib,
.insert_nop = sdma_v5_2_ring_insert_nop,
.pad_ib = sdma_v5_2_ring_pad_ib,
.emit_wreg = sdma_v5_2_ring_emit_wreg,
.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
.preempt_ib = sdma_v5_2_ring_preempt_ib,
1649};

1651static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1652{
int i;

for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
adev->sdma.instance[i].ring.me = i;
}
1659}

1661static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
.set = sdma_v5_2_set_trap_irq_state,
.process = sdma_v5_2_process_trap_irq,
1664};

1666static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
.process = sdma_v5_2_process_illegal_inst_irq,
1668};

1670static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1671{
adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
			adev->sdma.num_instances;
adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1676}

1678/**
* sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
*
* @ring: amdgpu_ring structure holding ring information
* @src_offset: src GPU address
* @dst_offset: dst GPU address
* @byte_count: number of bytes to xfer
*
* Copy GPU buffers using the DMA engine.
* Used by the amdgpu ttm implementation to move pages if
* registered as the asic copy callback.
*/
1690static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
		       uint64_t src_offset,
		       uint64_t dst_offset,
		       uint32_t byte_count,
		       bool_Bool tmz)
1695{
ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8) |
SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0)(((tmz ? 1 : 0) & 0x00000001) << 18);
ib->ptr[ib->length_dw++] = byte_count - 1;
ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset)((u32)(src_offset));
ib->ptr[ib->length_dw++] = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16));
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
1705}

1707/**
* sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
*
* @ring: amdgpu_ring structure holding ring information
* @src_data: value to write to buffer
* @dst_offset: dst GPU address
* @byte_count: number of bytes to xfer
*
* Fill GPU buffers using the DMA engine.
*/
1717static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
		       uint32_t src_data,
		       uint64_t dst_offset,
		       uint32_t byte_count)
1721{
ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)(((11) & 0x000000FF) << 0);
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
ib->ptr[ib->length_dw++] = src_data;
ib->ptr[ib->length_dw++] = byte_count - 1;
1727}

1729static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
.copy_max_bytes = 0x400000,
.copy_num_dw = 7,
.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,

.fill_max_bytes = 0x400000,
.fill_num_dw = 5,
.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1737};

1739static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1740{
if (adev->mman.buffer_funcs == NULL((void *)0)) {
adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
1745}

1747static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
.copy_pte_num_dw = 7,
.copy_pte = sdma_v5_2_vm_copy_pte,
.write_pte = sdma_v5_2_vm_write_pte,
.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1752};

1754static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1755{
unsigned i;

if (adev->vm_manager.vm_pte_funcs == NULL((void *)0)) {
adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
	adev->vm_manager.vm_pte_scheds[i] =
		&adev->sdma.instance[i].ring.sched;
}
adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
}
1766}

1768const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
.type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 5,
.minor = 2,
.rev = 0,
.funcs = &sdma_v5_2_ip_funcs,
1774};

←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2 
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5 
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11 
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var))	((type)(__uintptr_t)(const void *)(var))
14#endif
15 
16struct firmware {
17	size_t size;
18	const u8 *data;
19};
20 
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23    struct device *device)
24{
25	int r;
26	struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27	    M_WAITOK0x0001 | M_ZERO0x0008);
28	r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29	if (r != 0) {
9
←
Assuming 'r' is not equal to 0→
10
←
Taking true branch→
30		free(f, M_DRM145, sizeof(struct firmware));
31		*fw = NULL((void *)0);
11
←
Null pointer value stored to field 'fw'→
32		return -r;
33	} else  {
34		*fw = f;
35		return 0;
36	}
37}
38 
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41    struct device *device)
42{
43	return request_firmware(fw, name, device);
44}
45 
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47 
48static inline void
49release_firmware(const struct firmware *fw)
50{
51	if (fw)
52		free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53	free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55 
56#endif