/usr/src/sys/dev/pci/drm/i915/display/intel_dpll

Bug Summary

File:	dev/pci/drm/i915/display/intel_dpll_mgr.c
Warning:	line 308, column 4 Access to field 'dev' results in a dereference of a null pointer
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_dpll_mgr.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1/*
* Copyright © 2006-2016 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

24#include "intel_display_types.h"
25#include "intel_dpio_phy.h"
26#include "intel_dpll_mgr.h"

28/**
* DOC: Display PLLs
*
* Display PLLs used for driving outputs vary by platform. While some have
* per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
* from a pool. In the latter scenario, it is possible that multiple pipes
* share a PLL if their configurations match.
*
* This file provides an abstraction over display PLLs. The function
* intel_shared_dpll_init() initializes the PLLs for the given platform.  The
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
* intel_reserve_shared_dplls() and previously reserved PLLs can be released
* with intel_release_shared_dplls().
* Changes to the users are first staged in the atomic state, and then made
* effective by calling intel_shared_dpll_swap_state() during the atomic
* commit phase.
*/

48struct intel_dpll_mgr {
const struct dpll_info *dpll_info;

bool_Bool (*get_dplls)(struct intel_atomic_state *state,
	  struct intel_crtc *crtc,
	  struct intel_encoder *encoder);
void (*put_dplls)(struct intel_atomic_state *state,
	  struct intel_crtc *crtc);
void (*update_active_dpll)(struct intel_atomic_state *state,
		   struct intel_crtc *crtc,
		   struct intel_encoder *encoder);
void (*update_ref_clks)(struct drm_i915_privateinteldrm_softc *i915);
void (*dump_hw_state)(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state);
62};

64static void
65intel_atomic_duplicate_dpll_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		  struct intel_shared_dpll_state *shared_dpll)
67{
enum intel_dpll_id i;

/* Copy shared dpll state */
for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];

shared_dpll[i] = pll->state;
}
76}

78static struct intel_shared_dpll_state *
79intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
80{
struct intel_atomic_state *state = to_intel_atomic_state(s)({ const __typeof( ((struct intel_atomic_state *)0)->base )
 *__mptr = (s); (struct intel_atomic_state *)( (char *)__mptr
 - __builtin_offsetof(struct intel_atomic_state, base) );});

drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex))({ int __ret = !!((!drm_modeset_is_locked(&s->dev->
mode_config.connection_mutex))); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((s->dev))->dev), "", "drm_WARN_ON("
 "!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)"
 ")"); __builtin_expect(!!(__ret), 0); });

if (!state->dpll_set) {
state->dpll_set = true1;

intel_atomic_duplicate_dpll_state(to_i915(s->dev),
				  state->shared_dpll);
}

return state->shared_dpll;
93}

95/**
* intel_get_shared_dpll_by_id - get a DPLL given its id
* @dev_priv: i915 device instance
* @id: pll id
*
* Returns:
* A pointer to the DPLL with @id
*/
103struct intel_shared_dpll *
104intel_get_shared_dpll_by_id(struct drm_i915_privateinteldrm_softc *dev_priv,
	    enum intel_dpll_id id)
106{
return &dev_priv->dpll.shared_dplls[id];
108}

110/**
* intel_get_shared_dpll_id - get the id of a DPLL
* @dev_priv: i915 device instance
* @pll: the DPLL
*
* Returns:
* The id of @pll
*/
118enum intel_dpll_id
119intel_get_shared_dpll_id(struct drm_i915_privateinteldrm_softc *dev_priv,
	 struct intel_shared_dpll *pll)
121{
long pll_idx = pll - dev_priv->dpll.shared_dplls;

if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((pll_idx < 0 || pll_idx >= dev_priv->
dpll.num_shared_dpll)); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "pll_idx < 0 || pll_idx >= dev_priv->dpll.num_shared_dpll"
 ")"); __builtin_expect(!!(__ret), 0); })
	pll_idx < 0 ||({ int __ret = !!((pll_idx < 0 || pll_idx >= dev_priv->
dpll.num_shared_dpll)); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "pll_idx < 0 || pll_idx >= dev_priv->dpll.num_shared_dpll"
 ")"); __builtin_expect(!!(__ret), 0); })
	pll_idx >= dev_priv->dpll.num_shared_dpll)({ int __ret = !!((pll_idx < 0 || pll_idx >= dev_priv->
dpll.num_shared_dpll)); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "pll_idx < 0 || pll_idx >= dev_priv->dpll.num_shared_dpll"
 ")"); __builtin_expect(!!(__ret), 0); }))
return -1;

return pll_idx;
130}

132/* For ILK+ */
133void assert_shared_dpll(struct drm_i915_privateinteldrm_softc *dev_priv,
	struct intel_shared_dpll *pll,
	bool_Bool state)
136{
bool_Bool cur_state;
struct intel_dpll_hw_state hw_state;

if (drm_WARN(&dev_priv->drm, !pll,({ int __ret = !!(!pll); if (__ret) printf("%s %s: " "asserting DPLL %s with no DPLL\n"
, dev_driver_string((&dev_priv->drm)->dev), "", onoff
(state)); __builtin_expect(!!(__ret), 0); })
     "asserting DPLL %s with no DPLL\n", onoff(state))({ int __ret = !!(!pll); if (__ret) printf("%s %s: " "asserting DPLL %s with no DPLL\n"
, dev_driver_string((&dev_priv->drm)->dev), "", onoff
(state)); __builtin_expect(!!(__ret), 0); }))
return;

cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); })
    "%s assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); })
	pll->info->name, onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, pll->info->name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); });
148}

150static i915_reg_t
151intel_combo_pll_enable_reg(struct drm_i915_privateinteldrm_softc *i915,
	   struct intel_shared_dpll *pll)
153{

if (IS_ELKHARTLAKE(i915)IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && (pll->info->id == DPLL_ID_EHL_DPLL4))
return MG_PLL_ENABLE(0)((const i915_reg_t){ .reg = (((0x46030) + ((0)) * ((0x46034) -
 (0x46030)))) });

return CNL_DPLL_ENABLE(pll->info->id)((const i915_reg_t){ .reg = (((0x46010) + (pll->info->id
) * ((0x46014) - (0x46010)))) });


161}
162/**
* intel_prepare_shared_dpll - call a dpll's prepare hook
* @crtc_state: CRTC, and its state, which has a shared dpll
*
* This calls the PLL's prepare hook if it has one and if the PLL is not
* already enabled. The prepare hook is platform specific.
*/
169void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
170{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;

if (drm_WARN_ON(&dev_priv->drm, pll == NULL)({ int __ret = !!((pll == ((void *)0))); if (__ret) printf("%s %s: "
 "%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "pll == ((void *)0)" ")"); __builtin_expect(
!!(__ret), 0); }))
return;

mutex_lock(&dev_priv->dpll.lock)rw_enter_write(&dev_priv->dpll.lock);
drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask)({ int __ret = !!((!pll->state.crtc_mask)); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "!pll->state.crtc_mask" ")"); __builtin_expect
(!!(__ret), 0); });
if (!pll->active_mask) {
drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "setting up %s\n"
, pll->info->name);
drm_WARN_ON(&dev_priv->drm, pll->on)({ int __ret = !!((pll->on)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "pll->on" ")"); __builtin_expect(!!(__ret), 0); });
assert_shared_dpll_disabled(dev_priv, pll)assert_shared_dpll(dev_priv, pll, 0);

pll->info->funcs->prepare(dev_priv, pll);
}
mutex_unlock(&dev_priv->dpll.lock)rw_exit_write(&dev_priv->dpll.lock);
188}

190/**
* intel_enable_shared_dpll - enable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
* Enable the shared DPLL used by @crtc.
*/
196void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
197{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
unsigned int old_mask;

if (drm_WARN_ON(&dev_priv->drm, pll == NULL)({ int __ret = !!((pll == ((void *)0))); if (__ret) printf("%s %s: "
 "%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "pll == ((void *)0)" ")"); __builtin_expect(
!!(__ret), 0); }))
return;

mutex_lock(&dev_priv->dpll.lock)rw_enter_write(&dev_priv->dpll.lock);
old_mask = pll->active_mask;

if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask))({ int __ret = !!((!(pll->state.crtc_mask & crtc_mask)
)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON(" "!(pll->state.crtc_mask & crtc_mask)"
 ")"); __builtin_expect(!!(__ret), 0); }) ||
   drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask)({ int __ret = !!((pll->active_mask & crtc_mask)); if (
__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "pll->active_mask & crtc_mask"
 ")"); __builtin_expect(!!(__ret), 0); }))
goto out;

pll->active_mask |= crtc_mask;

drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    "enable %s (active %x, on? %d) for crtc %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    pll->info->name, pll->active_mask, pll->on,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    crtc->base.base.id)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id);

if (old_mask) {
drm_WARN_ON(&dev_priv->drm, !pll->on)({ int __ret = !!((!pll->on)); if (__ret) printf("%s %s: "
 "%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "!pll->on" ")"); __builtin_expect(!!(__ret
), 0); });
assert_shared_dpll_enabled(dev_priv, pll)assert_shared_dpll(dev_priv, pll, 1);
goto out;
}
drm_WARN_ON(&dev_priv->drm, pll->on)({ int __ret = !!((pll->on)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "pll->on" ")"); __builtin_expect(!!(__ret), 0); });

drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling %s\n"
, pll->info->name);
pll->info->funcs->enable(dev_priv, pll);
pll->on = true1;

232out:
mutex_unlock(&dev_priv->dpll.lock)rw_exit_write(&dev_priv->dpll.lock);
234}

236/**
* intel_disable_shared_dpll - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
* Disable the shared DPLL used by @crtc.
*/
242void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
243{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int crtc_mask = drm_crtc_mask(&crtc->base);

/* PCH only available on ILK+ */
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5)
return;

if (pll == NULL((void *)0))
return;

mutex_lock(&dev_priv->dpll.lock)rw_enter_write(&dev_priv->dpll.lock);
if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask))({ int __ret = !!((!(pll->active_mask & crtc_mask))); if
 (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "!(pll->active_mask & crtc_mask)"
 ")"); __builtin_expect(!!(__ret), 0); }))
goto out;

drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    "disable %s (active %x, on? %d) for crtc %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    pll->info->name, pll->active_mask, pll->on,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id)
    crtc->base.base.id)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disable %s (active %x, on? %d) for crtc %d\n"
, pll->info->name, pll->active_mask, pll->on, crtc
->base.base.id);

assert_shared_dpll_enabled(dev_priv, pll)assert_shared_dpll(dev_priv, pll, 1);
drm_WARN_ON(&dev_priv->drm, !pll->on)({ int __ret = !!((!pll->on)); if (__ret) printf("%s %s: "
 "%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "!pll->on" ")"); __builtin_expect(!!(__ret
), 0); });

pll->active_mask &= ~crtc_mask;
if (pll->active_mask)
goto out;

drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling %s\n"
, pll->info->name);
pll->info->funcs->disable(dev_priv, pll);
pll->on = false0;

276out:
mutex_unlock(&dev_priv->dpll.lock)rw_exit_write(&dev_priv->dpll.lock);
278}

280static struct intel_shared_dpll *
281intel_find_shared_dpll(struct intel_atomic_state *state,
       const struct intel_crtc *crtc,
       const struct intel_dpll_hw_state *pll_state,
       unsigned long dpll_mask)
285{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
8
←
'dev_priv' initialized here→
struct intel_shared_dpll *pll, *unused_pll = NULL((void *)0);
struct intel_shared_dpll_state *shared_dpll;
enum intel_dpll_id i;

shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);

drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1))({ int __ret = !!((dpll_mask & ~((1UL << (9)) - 1))
); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON(" "dpll_mask & ~((1UL << (9)) - 1)"
 ")"); __builtin_expect(!!(__ret), 0); });
9
←
Taking false branch→

for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS)for ((i) = find_first_bit((&dpll_mask), (9)); (i) < (9
); (i) = find_next_bit((&dpll_mask), (9), (i) + 1)) {
10
←
Loop condition is true.  Entering loop body→
15
←
Assuming 'i' is < 9→
16
←
Loop condition is true.  Entering loop body→
22
←
Assuming 'i' is < 9→
23
←
Loop condition is true.  Entering loop body→
pll = &dev_priv->dpll.shared_dplls[i];

/* Only want to check enabled timings first */
if (shared_dpll[i].crtc_mask == 0) {
11
←
Assuming field 'crtc_mask' is equal to 0→
12
←
Taking true branch→
17
←
Assuming field 'crtc_mask' is equal to 0→
18
←
Taking true branch→
24
←
Assuming field 'crtc_mask' is not equal to 0→
25
←
Taking false branch→
	if (!unused_pll12.1
'unused_pll' is null
)
13
←
Taking true branch→
19
←
Assuming 'unused_pll' is null→
20
←
Taking true branch→
		unused_pll = pll;
	continue;
14
←
 Execution continues on line 295→
21
←
 Execution continues on line 295→
}

if (memcmp(pll_state,__builtin_memcmp((pll_state), (&shared_dpll[i].hw_state),
 (sizeof(*pll_state)))
26
←
Assuming the condition is true→
27
←
Taking true branch→
	   &shared_dpll[i].hw_state,__builtin_memcmp((pll_state), (&shared_dpll[i].hw_state),
 (sizeof(*pll_state)))
	   sizeof(*pll_state))__builtin_memcmp((pll_state), (&shared_dpll[i].hw_state),
 (sizeof(*pll_state))) == 0) {
	drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask)
28
←
Access to field 'dev' results in a dereference of a null pointer
		    "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask)
		    crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask)
		    pll->info->name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask)
		    shared_dpll[i].crtc_mask,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask)
		    pll->active_mask)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name, shared_dpll[i].crtc_mask, pll->active_mask);
	return pll;
}
}

/* Ok no matching timings, maybe there's a free one? */
if (unused_pll) {
drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] allocated %s\n"
, crtc->base.base.id, crtc->base.name, unused_pll->info
->name)
	    crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] allocated %s\n"
, crtc->base.base.id, crtc->base.name, unused_pll->info
->name)
	    unused_pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] allocated %s\n"
, crtc->base.base.id, crtc->base.name, unused_pll->info
->name);
return unused_pll;
}

return NULL((void *)0);
327}

329static void
330intel_reference_shared_dpll(struct intel_atomic_state *state,
	    const struct intel_crtc *crtc,
	    const struct intel_shared_dpll *pll,
	    const struct intel_dpll_hw_state *pll_state)
334{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll;
const enum intel_dpll_id id = pll->info->id;

shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);

if (shared_dpll[id].crtc_mask == 0)
shared_dpll[id].hw_state = *pll_state;

drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "using %s for pipe %c\n"
, pll->info->name, ((crtc->pipe) + 'A'))
pipe_name(crtc->pipe))drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "using %s for pipe %c\n"
, pll->info->name, ((crtc->pipe) + 'A'));

shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
348}

350static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
			  const struct intel_crtc *crtc,
			  const struct intel_shared_dpll *pll)
353{
struct intel_shared_dpll_state *shared_dpll;

shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
358}

360static void intel_put_dpll(struct intel_atomic_state *state,
	   struct intel_crtc *crtc)
362{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);

new_crtc_state->shared_dpll = NULL((void *)0);

if (!old_crtc_state->shared_dpll)
return;

intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
374}

376/**
* intel_shared_dpll_swap_state - make atomic DPLL configuration effective
* @state: atomic state
*
* This is the dpll version of drm_atomic_helper_swap_state() since the
* helper does not handle driver-specific global state.
*
* For consistency with atomic helpers this function does a complete swap,
* i.e. it also puts the current state into @state, even though there is no
* need for that at this moment.
*/
387void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
388{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev);
struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
enum intel_dpll_id i;

if (!state->dpll_set)
return;

for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll =
	&dev_priv->dpll.shared_dplls[i];

swap(pll->state, shared_dpll[i])do { __typeof(pll->state) __tmp = (pll->state); (pll->
state) = (shared_dpll[i]); (shared_dpll[i]) = __tmp; } while(
0);
}
402}

404static bool_Bool ibx_pch_dpll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		      struct intel_shared_dpll *pll,
		      struct intel_dpll_hw_state *hw_state)
407{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
));
hw_state->dpll = val;
hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6040 : 0xc6048) }
));
hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6044 : 0xc604c) }
));

intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return val & DPLL_VCO_ENABLE(1 << 31);
425}

427static void ibx_pch_dpll_prepare(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll)
429{
const enum intel_dpll_id id = pll->info->id;

intel_de_write(dev_priv, PCH_FP0(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6040 : 0xc6048) }
), pll->state.hw_state.fp0);
intel_de_write(dev_priv, PCH_FP1(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6044 : 0xc604c) }
), pll->state.hw_state.fp1);
434}

436static void ibx_assert_pch_refclk_enabled(struct drm_i915_privateinteldrm_softc *dev_priv)
437{
u32 val;
bool_Bool enabled;

I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)))({ int __ret_warn_on = !!((!((((dev_priv)->pch_type) == PCH_IBX
) || (((dev_priv)->pch_type) == PCH_CPT)))); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s", "WARN_ON(" "!((((dev_priv)->pch_type) == PCH_IBX) || (((dev_priv)->pch_type) == PCH_CPT))"
 ")"); __builtin_expect(!!(__ret), 0); })) __drm_err("%s", "WARN_ON("
 "!((((dev_priv)->pch_type) == PCH_IBX) || (((dev_priv)->pch_type) == PCH_CPT))"
 ")"); __builtin_expect(!!(__ret_warn_on), 0); });

val = intel_de_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }));
enabled = !!(val & (DREF_SSC_SOURCE_MASK(3 << 11) | DREF_NONSPREAD_SOURCE_MASK(3 << 9) |
	    DREF_SUPERSPREAD_SOURCE_MASK(3 << 7)));
I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n")({ int __ret_warn_on = !!(!enabled); if (__builtin_expect(!!(
__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH refclk assertion failure, should be active but is disabled\n"
); __builtin_expect(!!(__ret), 0); })) __drm_err("PCH refclk assertion failure, should be active but is disabled\n"
); __builtin_expect(!!(__ret_warn_on), 0); });
447}

449static void ibx_pch_dpll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll)
451{
const enum intel_dpll_id id = pll->info->id;

/* PCH refclock must be enabled first */
ibx_assert_pch_refclk_enabled(dev_priv);

intel_de_write(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
), pll->state.hw_state.dpll);

/* Wait for the clocks to stabilize. */
intel_de_posting_read(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
));
udelay(150);

/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
*
* So write it again.
*/
intel_de_write(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
), pll->state.hw_state.dpll);
intel_de_posting_read(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
));
udelay(200);
471}

473static void ibx_pch_dpll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll)
475{
const enum intel_dpll_id id = pll->info->id;

intel_de_write(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
), 0);
intel_de_posting_read(dev_priv, PCH_DPLL(id)((const i915_reg_t){ .reg = ((id) == 0 ? 0xc6014 : 0xc6018) }
));
udelay(200);
481}

483static bool_Bool ibx_get_dpll(struct intel_atomic_state *state,
	 struct intel_crtc *crtc,
	 struct intel_encoder *encoder)
486{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id i;

if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
pll = &dev_priv->dpll.shared_dplls[i];

drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name)
	    "[CRTC:%d:%s] using pre-allocated %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name)
	    crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name)
	    pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name);
} else {
pll = intel_find_shared_dpll(state, crtc,
			     &crtc_state->dpll_hw_state,
			     BIT(DPLL_ID_PCH_PLL_B)(1UL << (DPLL_ID_PCH_PLL_B)) |
			     BIT(DPLL_ID_PCH_PLL_A)(1UL << (DPLL_ID_PCH_PLL_A)));
}

if (!pll)
return false0;

/* reference the pll */
intel_reference_shared_dpll(state, crtc,
		    pll, &crtc_state->dpll_hw_state);

crtc_state->shared_dpll = pll;

return true1;
519}

521static void ibx_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
523{
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    "fp0: 0x%x, fp1: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    hw_state->dpll,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    hw_state->dpll_md,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    hw_state->fp0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
    hw_state->fp1)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1);
531}

533static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
.prepare = ibx_pch_dpll_prepare,
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
538};

540static const struct dpll_info pch_plls[] = {
{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
{ },
544};

546static const struct intel_dpll_mgr pch_pll_mgr = {
.dpll_info = pch_plls,
.get_dplls = ibx_get_dpll,
.put_dplls = intel_put_dpll,
.dump_hw_state = ibx_dump_hw_state,
551};

553static void hsw_ddi_wrpll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	       struct intel_shared_dpll *pll)
555{
const enum intel_dpll_id id = pll->info->id;

intel_de_write(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }), pll->state.hw_state.wrpll);
intel_de_posting_read(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }));
udelay(20);
561}

563static void hsw_ddi_spll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll)
565{
intel_de_write(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }), pll->state.hw_state.spll);
intel_de_posting_read(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }));
udelay(20);
569}

571static void hsw_ddi_wrpll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		  struct intel_shared_dpll *pll)
573{
const enum intel_dpll_id id = pll->info->id;
u32 val;

val = intel_de_read(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }));
intel_de_write(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }), val & ~WRPLL_PLL_ENABLE(1 << 31));
intel_de_posting_read(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }));

/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
if (dev_priv->pch_ssc_use & BIT(id)(1UL << (id)))
intel_init_pch_refclk(dev_priv);
587}

589static void hsw_ddi_spll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll)
591{
enum intel_dpll_id id = pll->info->id;
u32 val;

val = intel_de_read(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }));
intel_de_write(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }), val & ~SPLL_PLL_ENABLE(1 << 31));
intel_de_posting_read(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }));

/*
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
if (dev_priv->pch_ssc_use & BIT(id)(1UL << (id)))
intel_init_pch_refclk(dev_priv);
605}

607static bool_Bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		       struct intel_shared_dpll *pll,
		       struct intel_dpll_hw_state *hw_state)
610{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) -
 (0x46040)))) }));
hw_state->wrpll = val;

intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return val & WRPLL_PLL_ENABLE(1 << 31);
626}

628static bool_Bool hsw_ddi_spll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		      struct intel_shared_dpll *pll,
		      struct intel_dpll_hw_state *hw_state)
631{
intel_wakeref_t wakeref;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }));
hw_state->spll = val;

intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return val & SPLL_PLL_ENABLE(1 << 31);
646}

648#define LC_FREQ2700 2700
649#define LC_FREQ_2K2700 * 2000ULL U64_C(LC_FREQ * 2000)2700 * 2000ULL

651#define P_MIN2 2
652#define P_MAX64 64
653#define P_INC2 2

655/* Constraints for PLL good behavior */
656#define REF_MIN48 48
657#define REF_MAX400 400
658#define VCO_MIN2400 2400
659#define VCO_MAX4800 4800

661struct hsw_wrpll_rnp {
unsigned p, n2, r2;
663};

665static unsigned hsw_wrpll_get_budget_for_freq(int clock)
666{
unsigned budget;

switch (clock) {
case 25175000:
case 25200000:
case 27000000:
case 27027000:
case 37762500:
case 37800000:
case 40500000:
case 40541000:
case 54000000:
case 54054000:
case 59341000:
case 59400000:
case 72000000:
case 74176000:
case 74250000:
case 81000000:
case 81081000:
case 89012000:
case 89100000:
case 108000000:
case 108108000:
case 111264000:
case 111375000:
case 148352000:
case 148500000:
case 162000000:
case 162162000:
case 222525000:
case 222750000:
case 296703000:
case 297000000:
budget = 0;
break;
case 233500000:
case 245250000:
case 247750000:
case 253250000:
case 298000000:
budget = 1500;
break;
case 169128000:
case 169500000:
case 179500000:
case 202000000:
budget = 2000;
break;
case 256250000:
case 262500000:
case 270000000:
case 272500000:
case 273750000:
case 280750000:
case 281250000:
case 286000000:
case 291750000:
budget = 4000;
break;
case 267250000:
case 268500000:
budget = 5000;
break;
default:
budget = 1000;
break;
}

return budget;
737}

739static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
		 unsigned int r2, unsigned int n2,
		 unsigned int p,
		 struct hsw_wrpll_rnp *best)
743{
u64 a, b, c, d, diff, diff_best;

/* No best (r,n,p) yet */
if (best->p == 0) {
best->p = p;
best->n2 = n2;
best->r2 = r2;
return;
}

/*
* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
* freq2k.
*
* delta = 1e6 *
*	   abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
*	   freq2k;
*
* and we would like delta <= budget.
*
* If the discrepancy is above the PPM-based budget, always prefer to
* improve upon the previous solution.  However, if you're within the
* budget, try to maximize Ref * VCO, that is N / (P * R^2).
*/
a = freq2k * budget * p * r2;
b = freq2k * budget * best->p * best->r2;
diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2)({ typeof(freq2k * p * r2) __a = (freq2k * p * r2); typeof(2700
 * 2000ULL * n2) __b = (2700 * 2000ULL * n2); (void) (&__a
 == &__b); __a > __b ? (__a - __b) : (__b - __a); });
diff_best = abs_diff(freq2k * best->p * best->r2,({ typeof(freq2k * best->p * best->r2) __a = (freq2k * best
->p * best->r2); typeof(2700 * 2000ULL * best->n2) __b
 = (2700 * 2000ULL * best->n2); (void) (&__a == &__b
); __a > __b ? (__a - __b) : (__b - __a); })
	     LC_FREQ_2K * best->n2)({ typeof(freq2k * best->p * best->r2) __a = (freq2k * best
->p * best->r2); typeof(2700 * 2000ULL * best->n2) __b
 = (2700 * 2000ULL * best->n2); (void) (&__a == &__b
); __a > __b ? (__a - __b) : (__b - __a); });
c = 1000000 * diff;
d = 1000000 * diff_best;

if (a < c && b < d) {
/* If both are above the budget, pick the closer */
if (best->p * best->r2 * diff < p * r2 * diff_best) {
	best->p = p;
	best->n2 = n2;
	best->r2 = r2;
}
} else if (a >= c && b < d) {
/* If A is below the threshold but B is above it?  Update. */
best->p = p;
best->n2 = n2;
best->r2 = r2;
} else if (a >= c && b >= d) {
/* Both are below the limit, so pick the higher n2/(r2*r2) */
if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
	best->p = p;
	best->n2 = n2;
	best->r2 = r2;
}
}
/* Otherwise a < c && b >= d, do nothing */
797}

799static void
800hsw_ddi_calculate_wrpll(int clock /* in Hz */,
	unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
802{
u64 freq2k;
unsigned p, n2, r2;
struct hsw_wrpll_rnp best = { 0, 0, 0 };
unsigned budget;

freq2k = clock / 100;

budget = hsw_wrpll_get_budget_for_freq(clock);

/* Special case handling for 540 pixel clock: bypass WR PLL entirely
* and directly pass the LC PLL to it. */
if (freq2k == 5400000) {
*n2_out = 2;
*p_out = 1;
*r2_out = 2;
return;
}

/*
* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
* the WR PLL.
*
* We want R so that REF_MIN <= Ref <= REF_MAX.
* Injecting R2 = 2 * R gives:
*   REF_MAX * r2 > LC_FREQ * 2 and
*   REF_MIN * r2 < LC_FREQ * 2
*
* Which means the desired boundaries for r2 are:
*  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
*
*/
for (r2 = LC_FREQ2700 * 2 / REF_MAX400 + 1;
    r2 <= LC_FREQ2700 * 2 / REF_MIN48;
    r2++) {

/*
 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 *
 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 *   VCO_MAX * r2 > n2 * LC_FREQ and
 *   VCO_MIN * r2 < n2 * LC_FREQ)
 *
 * Which means the desired boundaries for n2 are:
 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 */
for (n2 = VCO_MIN2400 * r2 / LC_FREQ2700 + 1;
     n2 <= VCO_MAX4800 * r2 / LC_FREQ2700;
     n2++) {

	for (p = P_MIN2; p <= P_MAX64; p += P_INC2)
		hsw_wrpll_update_rnp(freq2k, budget,
				     r2, n2, p, &best);
}
}

*n2_out = best.n2;
*p_out = best.p;
*r2_out = best.r2;
862}

864static struct intel_shared_dpll *
865hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
       struct intel_crtc *crtc)
867{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_shared_dpll *pll;
u32 val;
unsigned int p, n2, r2;

hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);

val = WRPLL_PLL_ENABLE(1 << 31) | WRPLL_REF_LCPLL(3 << 28) |
     WRPLL_DIVIDER_REFERENCE(r2)((r2) << 0) | WRPLL_DIVIDER_FEEDBACK(n2)((n2) << 16) |
     WRPLL_DIVIDER_POST(p)((p) << 8);

crtc_state->dpll_hw_state.wrpll = val;

pll = intel_find_shared_dpll(state, crtc,
		     &crtc_state->dpll_hw_state,
		     BIT(DPLL_ID_WRPLL2)(1UL << (DPLL_ID_WRPLL2)) |
		     BIT(DPLL_ID_WRPLL1)(1UL << (DPLL_ID_WRPLL1)));

if (!pll)
return NULL((void *)0);

return pll;
891}

893static int hsw_ddi_wrpll_get_freq(struct drm_i915_privateinteldrm_softc *dev_priv,
		  const struct intel_shared_dpll *pll)
895{
int refclk;
int n, p, r;
u32 wrpll = pll->state.hw_state.wrpll;

switch (wrpll & WRPLL_REF_MASK(3 << 28)) {
case WRPLL_REF_SPECIAL_HSW(2 << 28):
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && !IS_HSW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0))) {
	refclk = dev_priv->dpll.ref_clks.nssc;
	break;
}
fallthroughdo {} while (0);
case WRPLL_REF_PCH_SSC(1 << 28):
/*
 * We could calculate spread here, but our checking
 * code only cares about 5% accuracy, and spread is a max of
 * 0.5% downspread.
 */
refclk = dev_priv->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL(3 << 28):
refclk = 2700000;
break;
default:
MISSING_CASE(wrpll)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "wrpll", (long)(wrpll)); __builtin_expect(!!(__ret), 0); });
return 0;
}

r = wrpll & WRPLL_DIVIDER_REF_MASK(0xff);
p = (wrpll & WRPLL_DIVIDER_POST_MASK(0x3f << 8)) >> WRPLL_DIVIDER_POST_SHIFT8;
n = (wrpll & WRPLL_DIVIDER_FB_MASK(0xff << 16)) >> WRPLL_DIVIDER_FB_SHIFT16;

/* Convert to KHz, p & r have a fixed point portion */
return (refclk * n / 10) / (p * r) * 2;
930}

932static struct intel_shared_dpll *
933hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
934{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;

switch (clock / 2) {
case 81000:
pll_id = DPLL_ID_LCPLL_810;
break;
case 135000:
pll_id = DPLL_ID_LCPLL_1350;
break;
case 270000:
pll_id = DPLL_ID_LCPLL_2700;
break;
default:
drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid clock for DP: %d\n"
, clock)
	    clock)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid clock for DP: %d\n"
, clock);
return NULL((void *)0);
}

pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);

if (!pll)
return NULL((void *)0);

return pll;
962}

964static int hsw_ddi_lcpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		  const struct intel_shared_dpll *pll)
966{
int link_clock = 0;

switch (pll->info->id) {
case DPLL_ID_LCPLL_810:
link_clock = 81000;
break;
case DPLL_ID_LCPLL_1350:
link_clock = 135000;
break;
case DPLL_ID_LCPLL_2700:
link_clock = 270000;
break;
default:
drm_WARN(&i915->drm, 1, "bad port clock sel\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "bad port clock sel\n"
, dev_driver_string((&i915->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); });
break;
}

return link_clock * 2;
985}

987static struct intel_shared_dpll *
988hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
      struct intel_crtc *crtc)
990{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);

if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)({ int __ret = !!((crtc_state->port_clock / 2 != 135000));
 if (__ret) printf("%s %s: " "%s", dev_driver_string(((crtc->
base.dev))->dev), "", "drm_WARN_ON(" "crtc_state->port_clock / 2 != 135000"
 ")"); __builtin_expect(!!(__ret), 0); }))
return NULL((void *)0);

crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE(1 << 31) | SPLL_FREQ_1350MHz(1 << 26) |
			 SPLL_REF_MUXED_SSC(1 << 28);

return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
		      BIT(DPLL_ID_SPLL)(1UL << (DPLL_ID_SPLL)));
1002}

1004static int hsw_ddi_spll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		 const struct intel_shared_dpll *pll)
1006{
int link_clock = 0;

switch (pll->state.hw_state.spll & SPLL_FREQ_MASK(3 << 26)) {
case SPLL_FREQ_810MHz(0 << 26):
link_clock = 81000;
break;
case SPLL_FREQ_1350MHz(1 << 26):
link_clock = 135000;
break;
case SPLL_FREQ_2700MHz(2 << 26):
link_clock = 270000;
break;
default:
drm_WARN(&i915->drm, 1, "bad spll freq\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "bad spll freq\n"
, dev_driver_string((&i915->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); });
break;
}

return link_clock * 2;
1025}

1027static bool_Bool hsw_get_dpll(struct intel_atomic_state *state,
	 struct intel_crtc *crtc,
	 struct intel_encoder *encoder)
1030{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_shared_dpll *pll;

memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)))
      sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)));

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
else if (intel_crtc_has_dp_encoder(crtc_state))
pll = hsw_ddi_lcpll_get_dpll(crtc_state);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
pll = hsw_ddi_spll_get_dpll(state, crtc);
else
return false0;

if (!pll)
return false0;

intel_reference_shared_dpll(state, crtc,
		    pll, &crtc_state->dpll_hw_state);

crtc_state->shared_dpll = pll;

return true1;
1056}

1058static void hsw_update_dpll_ref_clks(struct drm_i915_privateinteldrm_softc *i915)
1059{
i915->dpll.ref_clks.ssc = 135000;
/* Non-SSC is only used on non-ULT HSW. */
if (intel_de_read(i915, FUSE_STRAP3((const i915_reg_t){ .reg = (0x42020) })) & HSW_REF_CLK_SELECT(1 << 1))
i915->dpll.ref_clks.nssc = 24000;
else
i915->dpll.ref_clks.nssc = 135000;
1066}

1068static void hsw_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
1070{
drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n"
, hw_state->wrpll, hw_state->spll)
    hw_state->wrpll, hw_state->spll)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n"
, hw_state->wrpll, hw_state->spll);
1073}

1075static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
1080};

1082static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
.disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
.get_freq = hsw_ddi_spll_get_freq,
1087};

1089static void hsw_ddi_lcpll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll)
1091{
1092}

1094static void hsw_ddi_lcpll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		  struct intel_shared_dpll *pll)
1096{
1097}

1099static bool_Bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		       struct intel_shared_dpll *pll,
		       struct intel_dpll_hw_state *hw_state)
1102{
return true1;
1104}

1106static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
.disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
.get_freq = hsw_ddi_lcpll_get_freq,
1111};

1113static const struct dpll_info hsw_plls[] = {
{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON(1 << 0) },
{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON(1 << 0) },
{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON(1 << 0) },
{ },
1121};

1123static const struct intel_dpll_mgr hsw_pll_mgr = {
.dpll_info = hsw_plls,
.get_dplls = hsw_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = hsw_update_dpll_ref_clks,
.dump_hw_state = hsw_dump_hw_state,
1129};

1131struct skl_dpll_regs {
i915_reg_t ctl, cfgcr1, cfgcr2;
1133};

1135/* this array is indexed by the *shared* pll id */
1136static const struct skl_dpll_regs skl_dpll_regs[4] = {
{
/* DPLL 0 */
.ctl = LCPLL1_CTL((const i915_reg_t){ .reg = (0x46010) }),
/* DPLL 0 doesn't support HDMI mode */
},
{
/* DPLL 1 */
.ctl = LCPLL2_CTL((const i915_reg_t){ .reg = (0x46014) }),
.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1)((const i915_reg_t){ .reg = (((0x6C040) + ((1) - 1) * ((0x6C048
) - (0x6C040)))) }),
.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1)((const i915_reg_t){ .reg = (((0x6C044) + ((1) - 1) * ((0x6C04C
) - (0x6C044)))) }),
},
{
/* DPLL 2 */
.ctl = WRPLL_CTL(0)((const i915_reg_t){ .reg = (((0x46040) + (0) * ((0x46060) - (
0x46040)))) }),
.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2)((const i915_reg_t){ .reg = (((0x6C040) + ((2) - 1) * ((0x6C048
) - (0x6C040)))) }),
.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2)((const i915_reg_t){ .reg = (((0x6C044) + ((2) - 1) * ((0x6C04C
) - (0x6C044)))) }),
},
{
/* DPLL 3 */
.ctl = WRPLL_CTL(1)((const i915_reg_t){ .reg = (((0x46040) + (1) * ((0x46060) - (
0x46040)))) }),
.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3)((const i915_reg_t){ .reg = (((0x6C040) + ((3) - 1) * ((0x6C048
) - (0x6C040)))) }),
.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3)((const i915_reg_t){ .reg = (((0x6C044) + ((3) - 1) * ((0x6C04C
) - (0x6C044)))) }),
},
1160};

1162static void skl_ddi_pll_write_ctrl1(struct drm_i915_privateinteldrm_softc *dev_priv,
		    struct intel_shared_dpll *pll)
1164{
const enum intel_dpll_id id = pll->info->id;
u32 val;

val = intel_de_read(dev_priv, DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }));

val &= ~(DPLL_CTRL1_HDMI_MODE(id)(1 << ((id) * 6 + 5)) |
 DPLL_CTRL1_SSC(id)(1 << ((id) * 6 + 4)) |
 DPLL_CTRL1_LINK_RATE_MASK(id)(7 << ((id) * 6 + 1)));
val |= pll->state.hw_state.ctrl1 << (id * 6);

intel_de_write(dev_priv, DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }), val);
intel_de_posting_read(dev_priv, DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }));
1177}

1179static void skl_ddi_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	       struct intel_shared_dpll *pll)
1181{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;

skl_ddi_pll_write_ctrl1(dev_priv, pll);

intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
intel_de_posting_read(dev_priv, regs[id].cfgcr1);
intel_de_posting_read(dev_priv, regs[id].cfgcr2);

/* the enable bit is always bit 31 */
intel_de_write(dev_priv, regs[id].ctl,
       intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE(1 << 31));

if (intel_de_wait_for_set(dev_priv, DPLL_STATUS((const i915_reg_t){ .reg = (0x6C060) }), DPLL_LOCK(id)(1 << ((id) * 8)), 5))
drm_err(&dev_priv->drm, "DPLL %d not locked\n", id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DPLL %d not locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , id);
1198}

1200static void skl_ddi_dpll0_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll)
1202{
skl_ddi_pll_write_ctrl1(dev_priv, pll);
1204}

1206static void skl_ddi_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll)
1208{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;

/* the enable bit is always bit 31 */
intel_de_write(dev_priv, regs[id].ctl,
       intel_de_read(dev_priv, regs[id].ctl) & ~LCPLL_PLL_ENABLE(1 << 31));
intel_de_posting_read(dev_priv, regs[id].ctl);
1216}

1218static void skl_ddi_dpll0_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		  struct intel_shared_dpll *pll)
1220{
1221}

1223static bool_Bool skl_ddi_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		     struct intel_shared_dpll *pll,
		     struct intel_dpll_hw_state *hw_state)
1226{
u32 val;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
bool_Bool ret;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

ret = false0;

val = intel_de_read(dev_priv, regs[id].ctl);
if (!(val & LCPLL_PLL_ENABLE(1 << 31)))
goto out;

val = intel_de_read(dev_priv, DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }));
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;

/* avoid reading back stale values if HDMI mode is not enabled */
if (val & DPLL_CTRL1_HDMI_MODE(id)(1 << ((id) * 6 + 5))) {
hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1);
hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2);
}
ret = true1;

1254out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return ret;
1258}

1260static bool_Bool skl_ddi_dpll0_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		       struct intel_shared_dpll *pll,
		       struct intel_dpll_hw_state *hw_state)
1263{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;
bool_Bool ret;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

ret = false0;

/* DPLL0 is always enabled since it drives CDCLK */
val = intel_de_read(dev_priv, regs[id].ctl);
if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE))({ int __ret = !!((!(val & (1 << 31)))); if (__ret)
 printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!(val & (1 << 31))"
 ")"); __builtin_expect(!!(__ret), 0); }))
goto out;

val = intel_de_read(dev_priv, DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }));
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;

ret = true1;

1287out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return ret;
1291}

1293struct skl_wrpll_context {
u64 min_deviation;		/* current minimal deviation */
u64 central_freq;		/* chosen central freq */
u64 dco_freq;			/* chosen dco freq */
unsigned int p;			/* chosen divider */
1298};

1300static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1301{
memset(ctx, 0, sizeof(*ctx))__builtin_memset((ctx), (0), (sizeof(*ctx)));

ctx->min_deviation = U64_MAX0xffffffffffffffffULL;
1305}

1307/* DCO freq must be within +1%/-6%  of the DCO central freq */
1308#define SKL_DCO_MAX_PDEVIATION100	100
1309#define SKL_DCO_MAX_NDEVIATION600	600

1311static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
		  u64 central_freq,
		  u64 dco_freq,
		  unsigned int divider)
1315{
u64 deviation;

deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq)({ typeof(dco_freq) __a = (dco_freq); typeof(central_freq) __b
 = (central_freq); (void) (&__a == &__b); __a > __b
 ? (__a - __b) : (__b - __a); }),
	      central_freq);

/* positive deviation */
if (dco_freq >= central_freq) {
if (deviation < SKL_DCO_MAX_PDEVIATION100 &&
    deviation < ctx->min_deviation) {
	ctx->min_deviation = deviation;
	ctx->central_freq = central_freq;
	ctx->dco_freq = dco_freq;
	ctx->p = divider;
}
/* negative deviation */
} else if (deviation < SKL_DCO_MAX_NDEVIATION600 &&
   deviation < ctx->min_deviation) {
ctx->min_deviation = deviation;
ctx->central_freq = central_freq;
ctx->dco_freq = dco_freq;
ctx->p = divider;
}
1338}

1340static void skl_wrpll_get_multipliers(unsigned int p,
		      unsigned int *p0 /* out */,
		      unsigned int *p1 /* out */,
		      unsigned int *p2 /* out */)
1344{
/* even dividers */
if (p % 2 == 0) {
unsigned int half = p / 2;

if (half == 1 || half == 2 || half == 3 || half == 5) {
	*p0 = 2;
	*p1 = 1;
	*p2 = half;
} else if (half % 2 == 0) {
	*p0 = 2;
	*p1 = half / 2;
	*p2 = 2;
} else if (half % 3 == 0) {
	*p0 = 3;
	*p1 = half / 3;
	*p2 = 2;
} else if (half % 7 == 0) {
	*p0 = 7;
	*p1 = half / 7;
	*p2 = 2;
}
} else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
*p0 = 3;
*p1 = 1;
*p2 = p / 3;
} else if (p == 5 || p == 7) {
*p0 = p;
*p1 = 1;
*p2 = 1;
} else if (p == 15) {
*p0 = 3;
*p1 = 1;
*p2 = 5;
} else if (p == 21) {
*p0 = 7;
*p1 = 1;
*p2 = 3;
} else if (p == 35) {
*p0 = 7;
*p1 = 1;
*p2 = 5;
}
1387}

1389struct skl_wrpll_params {
u32 dco_fraction;
u32 dco_integer;
u32 qdiv_ratio;
u32 qdiv_mode;
u32 kdiv;
u32 pdiv;
u32 central_freq;
1397};

1399static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
		      u64 afe_clock,
		      int ref_clock,
		      u64 central_freq,
		      u32 p0, u32 p1, u32 p2)
1404{
u64 dco_freq;

switch (central_freq) {
case 9600000000ULL:
params->central_freq = 0;
break;
case 9000000000ULL:
params->central_freq = 1;
break;
case 8400000000ULL:
params->central_freq = 3;
}

switch (p0) {
case 1:
params->pdiv = 0;
break;
case 2:
params->pdiv = 1;
break;
case 3:
params->pdiv = 2;
break;
case 7:
params->pdiv = 4;
break;
default:
WARN(1, "Incorrect PDiv\n")({ int __ret = !!(1); if (__ret) printf("Incorrect PDiv\n"); __builtin_expect
(!!(__ret), 0); });
}

switch (p2) {
case 5:
params->kdiv = 0;
break;
case 2:
params->kdiv = 1;
break;
case 3:
params->kdiv = 2;
break;
case 1:
params->kdiv = 3;
break;
default:
WARN(1, "Incorrect KDiv\n")({ int __ret = !!(1); if (__ret) printf("Incorrect KDiv\n"); __builtin_expect
(!!(__ret), 0); });
}

params->qdiv_ratio = p1;
params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;

dco_freq = p0 * p1 * p2 * afe_clock;

/*
* Intermediate values are in Hz.
* Divide by MHz to match bsepc
*/
params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1)(1000 * (1)));
params->dco_fraction =
div_u64((div_u64(dco_freq, ref_clock / KHz(1)(1000 * (1))) -
	 params->dco_integer * MHz(1)(1000 * (1000 * (1)))) * 0x8000, MHz(1)(1000 * (1000 * (1))));
1465}

1467static bool_Bool
1468skl_ddi_calculate_wrpll(int clock /* in Hz */,
	int ref_clock,
	struct skl_wrpll_params *wrpll_params)
1471{
u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
u64 dco_central_freq[3] = { 8400000000ULL,
		    9000000000ULL,
		    9600000000ULL };
static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
			     24, 28, 30, 32, 36, 40, 42, 44,
			     48, 52, 54, 56, 60, 64, 66, 68,
			     70, 72, 76, 78, 80, 84, 88, 90,
			     92, 96, 98 };
static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
static const struct {
const int *list;
int n_dividers;
} dividers[] = {
{ even_dividers, ARRAY_SIZE(even_dividers)(sizeof((even_dividers)) / sizeof((even_dividers)[0])) },
{ odd_dividers, ARRAY_SIZE(odd_dividers)(sizeof((odd_dividers)) / sizeof((odd_dividers)[0])) },
};
struct skl_wrpll_context ctx;
unsigned int dco, d, i;
unsigned int p0, p1, p2;

skl_wrpll_context_init(&ctx);

for (d = 0; d < ARRAY_SIZE(dividers)(sizeof((dividers)) / sizeof((dividers)[0])); d++) {
for (dco = 0; dco < ARRAY_SIZE(dco_central_freq)(sizeof((dco_central_freq)) / sizeof((dco_central_freq)[0])); dco++) {
	for (i = 0; i < dividers[d].n_dividers; i++) {
		unsigned int p = dividers[d].list[i];
		u64 dco_freq = p * afe_clock;

		skl_wrpll_try_divider(&ctx,
				      dco_central_freq[dco],
				      dco_freq,
				      p);
		/*
		 * Skip the remaining dividers if we're sure to
		 * have found the definitive divider, we can't
		 * improve a 0 deviation.
		 */
		if (ctx.min_deviation == 0)
			goto skip_remaining_dividers;
	}
}

1515skip_remaining_dividers:
/*
 * If a solution is found with an even divider, prefer
 * this one.
 */
if (d == 0 && ctx.p)
	break;
}

if (!ctx.p) {
DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock)__drm_dbg(DRM_UT_DRIVER, "No valid divider found for %dHz\n",
 clock);
return false0;
}

/*
* gcc incorrectly analyses that these can be used without being
* initialized. To be fair, it's hard to guess.
*/
p0 = p1 = p2 = 0;
skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
		  ctx.central_freq, p0, p1, p2);

return true1;
1539}

1541static bool_Bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1542{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);
u32 ctrl1, cfgcr1, cfgcr2;
struct skl_wrpll_params wrpll_params = { 0, };

/*
* See comment in intel_dpll_hw_state to understand why we always use 0
* as the DPLL id in this function.
*/
ctrl1 = DPLL_CTRL1_OVERRIDE(0)(1 << ((0) * 6));

ctrl1 |= DPLL_CTRL1_HDMI_MODE(0)(1 << ((0) * 6 + 5));

if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
		     i915->dpll.ref_clks.nssc,
		     &wrpll_params))
return false0;

cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE(1 << 31) |
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction)((wrpll_params.dco_fraction) << 9) |
wrpll_params.dco_integer;

cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio)((wrpll_params.qdiv_ratio) << 8) |
DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode)((wrpll_params.qdiv_mode) << 7) |
DPLL_CFGCR2_KDIV(wrpll_params.kdiv)((wrpll_params.kdiv) << 5) |
DPLL_CFGCR2_PDIV(wrpll_params.pdiv)((wrpll_params.pdiv) << 2) |
wrpll_params.central_freq;

memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)))
      sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)));

crtc_state->dpll_hw_state.ctrl1 = ctrl1;
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
return true1;
1577}

1579static int skl_ddi_wrpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		  const struct intel_shared_dpll *pll)
1581{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
int ref_clock = i915->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;

p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK(7 << 2);
p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK(3 << 5);

if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1)((1) << 7))
p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK(0xff << 8)) >> 8;
else
p1 = 1;


switch (p0) {
case DPLL_CFGCR2_PDIV_1(0 << 2):
p0 = 1;
break;
case DPLL_CFGCR2_PDIV_2(1 << 2):
p0 = 2;
break;
case DPLL_CFGCR2_PDIV_3(2 << 2):
p0 = 3;
break;
case DPLL_CFGCR2_PDIV_7(4 << 2):
p0 = 7;
break;
}

switch (p2) {
case DPLL_CFGCR2_KDIV_5(0 << 5):
p2 = 5;
break;
case DPLL_CFGCR2_KDIV_2(1 << 5):
p2 = 2;
break;
case DPLL_CFGCR2_KDIV_3(2 << 5):
p2 = 3;
break;
case DPLL_CFGCR2_KDIV_1(3 << 5):
p2 = 1;
break;
}

dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK(0x1ff)) *
   ref_clock;

dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK(0x7fff << 9)) >> 9) *
    ref_clock / 0x8000;

if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)({ int __ret = !!((p0 == 0 || p1 == 0 || p2 == 0)); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&i915->drm
))->dev), "", "drm_WARN_ON(" "p0 == 0 || p1 == 0 || p2 == 0"
 ")"); __builtin_expect(!!(__ret), 0); }))
return 0;

return dco_freq / (p0 * p1 * p2 * 5);
1635}

1637static bool_Bool
1638skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1639{
u32 ctrl1;

/*
* See comment in intel_dpll_hw_state to understand why we always use 0
* as the DPLL id in this function.
*/
ctrl1 = DPLL_CTRL1_OVERRIDE(0)(1 << ((0) * 6));
switch (crtc_state->port_clock / 2) {
case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0)((2) << ((0) * 6 + 1));
break;
case 135000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0)((1) << ((0) * 6 + 1));
break;
case 270000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0)((0) << ((0) * 6 + 1));
break;
/* eDP 1.4 rates */
case 162000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0)((3) << ((0) * 6 + 1));
break;
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0)((4) << ((0) * 6 + 1));
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0)((5) << ((0) * 6 + 1));
break;
}

memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)))
      sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)));

crtc_state->dpll_hw_state.ctrl1 = ctrl1;

return true1;
1675}

1677static int skl_ddi_lcpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		  const struct intel_shared_dpll *pll)
1679{
int link_clock = 0;

switch ((pll->state.hw_state.ctrl1 &
 DPLL_CTRL1_LINK_RATE_MASK(0)(7 << ((0) * 6 + 1))) >>
DPLL_CTRL1_LINK_RATE_SHIFT(0)((0) * 6 + 1)) {
case DPLL_CTRL1_LINK_RATE_8102:
link_clock = 81000;
break;
case DPLL_CTRL1_LINK_RATE_10804:
link_clock = 108000;
break;
case DPLL_CTRL1_LINK_RATE_13501:
link_clock = 135000;
break;
case DPLL_CTRL1_LINK_RATE_16203:
link_clock = 162000;
break;
case DPLL_CTRL1_LINK_RATE_21605:
link_clock = 216000;
break;
case DPLL_CTRL1_LINK_RATE_27000:
link_clock = 270000;
break;
default:
drm_WARN(&i915->drm, 1, "Unsupported link rate\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "Unsupported link rate\n"
, dev_driver_string((&i915->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); });
break;
}

return link_clock * 2;
1709}

1711static bool_Bool skl_get_dpll(struct intel_atomic_state *state,
	 struct intel_crtc *crtc,
	 struct intel_encoder *encoder)
1714{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
bool_Bool bret;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
bret = skl_ddi_hdmi_pll_dividers(crtc_state);
if (!bret) {
	drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not get HDMI pll dividers.\n"
)
		    "Could not get HDMI pll dividers.\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not get HDMI pll dividers.\n"
);
	return false0;
}
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
if (!bret) {
	drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not set DP dpll HW state.\n"
)
		    "Could not set DP dpll HW state.\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not set DP dpll HW state.\n"
);
	return false0;
}
} else {
return false0;
}

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
			     &crtc_state->dpll_hw_state,
			     BIT(DPLL_ID_SKL_DPLL0)(1UL << (DPLL_ID_SKL_DPLL0)));
else
pll = intel_find_shared_dpll(state, crtc,
			     &crtc_state->dpll_hw_state,
			     BIT(DPLL_ID_SKL_DPLL3)(1UL << (DPLL_ID_SKL_DPLL3)) |
			     BIT(DPLL_ID_SKL_DPLL2)(1UL << (DPLL_ID_SKL_DPLL2)) |
			     BIT(DPLL_ID_SKL_DPLL1)(1UL << (DPLL_ID_SKL_DPLL1)));
if (!pll)
return false0;

intel_reference_shared_dpll(state, crtc,
		    pll, &crtc_state->dpll_hw_state);

crtc_state->shared_dpll = pll;

return true1;
1758}

1760static int skl_ddi_pll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		const struct intel_shared_dpll *pll)
1762{
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0)(1 << ((0) * 6 + 5)))
return skl_ddi_wrpll_get_freq(i915, pll);
else
return skl_ddi_lcpll_get_freq(i915, pll);
1771}

1773static void skl_update_dpll_ref_clks(struct drm_i915_privateinteldrm_softc *i915)
1774{
/* No SSC ref */
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
1777}

1779static void skl_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
1781{
drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1
, hw_state->cfgcr1, hw_state->cfgcr2)
      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1
, hw_state->cfgcr1, hw_state->cfgcr2)
      hw_state->ctrl1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1
, hw_state->cfgcr1, hw_state->cfgcr2)
      hw_state->cfgcr1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1
, hw_state->cfgcr1, hw_state->cfgcr2)
      hw_state->cfgcr2)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1
, hw_state->cfgcr1, hw_state->cfgcr2);
1787}

1789static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
1794};

1796static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
.disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
1801};

1803static const struct dpll_info skl_plls[] = {
{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON(1 << 0) },
{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
{ },
1809};

1811static const struct intel_dpll_mgr skl_pll_mgr = {
.dpll_info = skl_plls,
.get_dplls = skl_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = skl_update_dpll_ref_clks,
.dump_hw_state = skl_dump_hw_state,
1817};

1819static void bxt_ddi_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll)
1821{
u32 temp;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;

bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);

/* Non-SSC reference */
temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
temp |= PORT_PLL_REF_SEL(1 << 27);
intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }), temp);

if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
temp |= PORT_PLL_POWER_ENABLE(1 << 26);
intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }), temp);

if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 25))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if (((intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (
((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (1 <<
 25)))) { ret = 0; break; } if (now - base >= timeout) { ret
 = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; })
		 PORT_PLL_POWER_STATE), 200)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 25))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if (((intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (
((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (1 <<
 25)))) { ret = 0; break; } if (now - base >= timeout) { ret
 = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; }))
	drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Power state not set for PLL:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , port)
		"Power state not set for PLL:%d\n", port)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Power state not set for PLL:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , port);
}

/* Disable 10 bit clock */
temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }));
temp &= ~PORT_PLL_10BIT_CLK_ENABLE(1 << 13);
intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }), temp);

/* Write P1 & P2 */
temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) }));
temp &= ~(PORT_PLL_P1_MASK(0x07 << 13) | PORT_PLL_P2_MASK(0x1f << 8));
temp |= pll->state.hw_state.ebb0;
intel_de_write(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) }), temp);

/* Write M2 integer */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (0) * 4) }));
temp &= ~PORT_PLL_M2_MASK0xFF;
temp |= pll->state.hw_state.pll0;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (0) * 4) }), temp);

/* Write N */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (1) * 4) }));
temp &= ~PORT_PLL_N_MASK(0x0F << 8);
temp |= pll->state.hw_state.pll1;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 1)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (1) * 4) }), temp);

/* Write M2 fraction */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (2) * 4) }));
temp &= ~PORT_PLL_M2_FRAC_MASK0x3FFFFF;
temp |= pll->state.hw_state.pll2;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 2)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (2) * 4) }), temp);

/* Write M2 fraction enable */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (3) * 4) }));
temp &= ~PORT_PLL_M2_FRAC_ENABLE(1 << 16);
temp |= pll->state.hw_state.pll3;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 3)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (3) * 4) }), temp);

/* Write coeff */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (6) * 4) }));
temp &= ~PORT_PLL_PROP_COEFF_MASK0xF;
temp &= ~PORT_PLL_INT_COEFF_MASK(0x1F << 8);
temp &= ~PORT_PLL_GAIN_CTL_MASK(0x07 << 16);
temp |= pll->state.hw_state.pll6;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (6) * 4) }), temp);

/* Write calibration val */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (8) * 4) }));
temp &= ~PORT_PLL_TARGET_CNT_MASK0x3FF;
temp |= pll->state.hw_state.pll8;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 8)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (8) * 4) }), temp);

temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (9) * 4) }));
temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK(0x7 << 1);
temp |= pll->state.hw_state.pll9;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 9)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (9) * 4) }), temp);

temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (10) * 4) }));
temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H(1 << 27);
temp &= ~PORT_PLL_DCO_AMP_MASK0x3c00;
temp |= pll->state.hw_state.pll10;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (10) * 4) }), temp);

/* Recalibrate with new settings */
temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }));
temp |= PORT_PLL_RECALIBRATE(1 << 14);
intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }), temp);
temp &= ~PORT_PLL_10BIT_CLK_ENABLE(1 << 13);
temp |= pll->state.hw_state.ebb4;
intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }), temp);

/* Enable PLL */
temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
temp |= PORT_PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }), temp);
intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));

if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 30))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if (((intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (
((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (1 <<
 30)))) { ret = 0; break; } if (now - base >= timeout) { ret
 = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; })
	200)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 30))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if (((intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (
((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (1 <<
 30)))) { ret = 0; break; } if (now - base >= timeout) { ret
 = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; }))
drm_err(&dev_priv->drm, "PLL %d not locked\n", port)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d not locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , port);

if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C514) - 0x6C000) + ((ch)) * (((
0x6C914) - 0x6C000) - ((0x6C514) - 0x6C000))))) }));
temp |= DCC_DELAY_RANGE_2(1 << 8);
intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD14) - 0x6C000) + ((ch)) * (((
0x6CF14) - 0x6C000) - ((0x6CD14) - 0x6C000))))) }), temp);
}

/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
*/
temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) }));
temp &= ~LANE_STAGGER_MASK0x1F;
temp &= ~LANESTAGGER_STRAP_OVRD(1 << 6);
temp |= pll->state.hw_state.pcsdw12;
intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC30) - 0x6C000) + ((ch)) * (((
0x6CE30) - 0x6C000) - ((0x6CC30) - 0x6C000))))) }), temp);
1938}

1940static void bxt_ddi_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
			struct intel_shared_dpll *pll)
1942{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
u32 temp;

temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
temp &= ~PORT_PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }), temp);
intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));

if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
temp &= ~PORT_PLL_POWER_ENABLE(1 << 26);
intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }), temp);

if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((!(intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 25))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if ((!(intel_de_read(dev_priv, ((const i915_reg_t){ .reg =
 (((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (
<< 25)))) { ret = 0; break; } if (now - base >= timeout
) { ret = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; })
		  PORT_PLL_POWER_STATE), 200)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p(
200))) ? 1 : -1 ] __attribute__((__unused__)); if ((200) >
 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw
(), 1000ll * (((200)))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((!(intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x46074) + (port) *
 ((0x46078) - (0x46074)))) })) & (1 << 25))))) { ret__
 = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range
(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<=
 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((200
)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = ((
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64
 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"
); if ((!(intel_de_read(dev_priv, ((const i915_reg_t){ .reg =
 (((0x46074) + (port) * ((0x46078) - (0x46074)))) })) & (
<< 25)))) { ret = 0; break; } if (now - base >= timeout
) { ret = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect
(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0"
 : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu
 = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; }
); ret__; }))
	drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Power state not reset for PLL:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , port)
		"Power state not reset for PLL:%d\n", port)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Power state not reset for PLL:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , port);
}
1961}

1963static bool_Bool bxt_ddi_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
			struct intel_shared_dpll *pll,
			struct intel_dpll_hw_state *hw_state)
1966{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
enum dpio_phy phy;
enum dpio_channel ch;
u32 val;
bool_Bool ret;

bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

ret = false0;

val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
 - (0x46074)))) }));
if (!(val & PORT_PLL_ENABLE(1 << 31)))
goto out;

hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) }));
hw_state->ebb0 &= PORT_PLL_P1_MASK(0x07 << 13) | PORT_PLL_P2_MASK(0x1f << 8);

hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }));
hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE(1 << 13);

hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (0) * 4) }));
hw_state->pll0 &= PORT_PLL_M2_MASK0xFF;

hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (1) * 4) }));
hw_state->pll1 &= PORT_PLL_N_MASK(0x0F << 8);

hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (2) * 4) }));
hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK0x3FFFFF;

hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (3) * 4) }));
hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE(1 << 16);

hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (6) * 4) }));
hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK0xF |
	  PORT_PLL_INT_COEFF_MASK(0x1F << 8) |
	  PORT_PLL_GAIN_CTL_MASK(0x07 << 16);

hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (8) * 4) }));
hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK0x3FF;

hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (9) * 4) }));
hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK(0x7 << 1);

hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (10) * 4) }));
hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H(1 << 27) |
	   PORT_PLL_DCO_AMP_MASK0x3c00;

/*
* While we write to the group register to program all lanes at once we
* can read only lane registers. We configure all lanes the same way, so
* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
*/
hw_state->pcsdw12 = intel_de_read(dev_priv,
			  BXT_PORT_PCS_DW12_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) }));
if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((
0x6CA30) - 0x6C000) - ((0x6C630) - 0x6C000))))) })) != hw_state->pcsdw12)
drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n"
, hw_state->pcsdw12, intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[
(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((0x6CA30) - 0x6C000
) - ((0x6C630) - 0x6C000))))) })))
	"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n"
, hw_state->pcsdw12, intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[
(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((0x6CA30) - 0x6C000
) - ((0x6C630) - 0x6C000))))) })))
	hw_state->pcsdw12,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n"
, hw_state->pcsdw12, intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[
(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((0x6CA30) - 0x6C000
) - ((0x6C630) - 0x6C000))))) })))
	intel_de_read(dev_priv,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n"
, hw_state->pcsdw12, intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[
(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((0x6CA30) - 0x6C000
) - ((0x6C630) - 0x6C000))))) })))
		      BXT_PORT_PCS_DW12_LN23(phy, ch)))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n"
, hw_state->pcsdw12, intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[
(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((0x6CA30) - 0x6C000
) - ((0x6C630) - 0x6C000))))) })));
hw_state->pcsdw12 &= LANE_STAGGER_MASK0x1F | LANESTAGGER_STRAP_OVRD(1 << 6);

ret = true1;

2037out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return ret;
2041}

2043/* bxt clock parameters */
2044struct bxt_clk_div {
int clock;
u32 p1;
u32 p2;
u32 m2_int;
u32 m2_frac;
bool_Bool m2_frac_en;
u32 n;

int vco;
2054};

2056/* pre-calculated values for DP linkrates */
2057static const struct bxt_clk_div bxt_dp_clk_val[] = {
{162000, 4, 2, 32, 1677722, 1, 1},
{270000, 4, 1, 27,       0, 0, 1},
{540000, 2, 1, 27,       0, 0, 1},
{216000, 3, 2, 32, 1677722, 1, 1},
{243000, 4, 1, 24, 1258291, 1, 1},
{324000, 4, 1, 32, 1677722, 1, 1},
{432000, 3, 1, 32, 1677722, 1, 1}
2065};

2067static bool_Bool
2068bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
	  struct bxt_clk_div *clk_div)
2070{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct dpll best_clock;

/* Calculate HDMI div */
/*
* FIXME: tie the following calculation into
* i9xx_crtc_compute_clock
*/
if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "no PLL dividers found for clock %d pipe %c\n"
, crtc_state->port_clock, ((crtc->pipe) + 'A'))
	crtc_state->port_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "no PLL dividers found for clock %d pipe %c\n"
, crtc_state->port_clock, ((crtc->pipe) + 'A'))
	pipe_name(crtc->pipe))drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "no PLL dividers found for clock %d pipe %c\n"
, crtc_state->port_clock, ((crtc->pipe) + 'A'));
return false0;
}

clk_div->p1 = best_clock.p1;
clk_div->p2 = best_clock.p2;
drm_WARN_ON(&i915->drm, best_clock.m1 != 2)({ int __ret = !!((best_clock.m1 != 2)); if (__ret) printf("%s %s: "
 "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON("
 "best_clock.m1 != 2" ")"); __builtin_expect(!!(__ret), 0); }
);
clk_div->n = best_clock.n;
clk_div->m2_int = best_clock.m2 >> 22;
clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
clk_div->m2_frac_en = clk_div->m2_frac != 0;

clk_div->vco = best_clock.vco;

return true1;
2098}

2100static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
		    struct bxt_clk_div *clk_div)
2102{
int clock = crtc_state->port_clock;
int i;

*clk_div = bxt_dp_clk_val[0];
for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val)(sizeof((bxt_dp_clk_val)) / sizeof((bxt_dp_clk_val)[0])); ++i) {
if (bxt_dp_clk_val[i].clock == clock) {
	*clk_div = bxt_dp_clk_val[i];
	break;
}
}

clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
2115}

2117static bool_Bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
		      const struct bxt_clk_div *clk_div)
2119{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
int clock = crtc_state->port_clock;
int vco = clk_div->vco;
u32 prop_coef, int_coef, gain_ctl, targ_cnt;
u32 lanestagger;

memset(dpll_hw_state, 0, sizeof(*dpll_hw_state))__builtin_memset((dpll_hw_state), (0), (sizeof(*dpll_hw_state
)));

if (vco >= 6200000 && vco <= 6700000) {
prop_coef = 4;
int_coef = 9;
gain_ctl = 3;
targ_cnt = 8;
} else if ((vco > 5400000 && vco < 6200000) ||
	(vco >= 4800000 && vco < 5400000)) {
prop_coef = 5;
int_coef = 11;
gain_ctl = 3;
targ_cnt = 9;
} else if (vco == 5400000) {
prop_coef = 3;
int_coef = 8;
gain_ctl = 1;
targ_cnt = 9;
} else {
drm_err(&i915->drm, "Invalid VCO\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Invalid VCO\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return false0;
}

if (clock > 270000)
lanestagger = 0x18;
else if (clock > 135000)
lanestagger = 0x0d;
else if (clock > 67000)
lanestagger = 0x07;
else if (clock > 33000)
lanestagger = 0x04;
else
lanestagger = 0x02;

dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1)((clk_div->p1) << 13) | PORT_PLL_P2(clk_div->p2)((clk_div->p2) << 8);
dpll_hw_state->pll0 = clk_div->m2_int;
dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n)((clk_div->n) << 8);
dpll_hw_state->pll2 = clk_div->m2_frac;

if (clk_div->m2_frac_en)
dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE(1 << 16);

dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef)((int_coef) << 8);
dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl)((gain_ctl) << 16);

dpll_hw_state->pll8 = targ_cnt;

dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT1;

dpll_hw_state->pll10 =
PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)((15) << 10)
| PORT_PLL_DCO_AMP_OVR_EN_H(1 << 27);

dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE(1 << 13);

dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD(1 << 6) | lanestagger;

return true1;
2185}

2187static bool_Bool
2188bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2189{
struct bxt_clk_div clk_div = {};

bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);

return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2195}

2197static bool_Bool
2198bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2199{
struct bxt_clk_div clk_div = {};

bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);

return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2205}

2207static int bxt_ddi_pll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		const struct intel_shared_dpll *pll)
2209{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
struct dpll clock;

clock.m1 = 2;
clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK0xFF) << 22;
if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE(1 << 16))
clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK0x3FFFFF;
clock.n = (pll_state->pll1 & PORT_PLL_N_MASK(0x0F << 8)) >> PORT_PLL_N_SHIFT8;
clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK(0x07 << 13)) >> PORT_PLL_P1_SHIFT13;
clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK(0x1f << 8)) >> PORT_PLL_P2_SHIFT8;

return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
2222}

2224static bool_Bool bxt_get_dpll(struct intel_atomic_state *state,
	 struct intel_crtc *crtc,
	 struct intel_encoder *encoder)
2227{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id id;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
   !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
return false0;

if (intel_crtc_has_dp_encoder(crtc_state) &&
   !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
return false0;

/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
pll = intel_get_shared_dpll_by_id(dev_priv, id);

drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name)
    crtc->base.base.id, crtc->base.name, pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] using pre-allocated %s\n"
, crtc->base.base.id, crtc->base.name, pll->info->
name);

intel_reference_shared_dpll(state, crtc,
		    pll, &crtc_state->dpll_hw_state);

crtc_state->shared_dpll = pll;

return true1;
2255}

2257static void bxt_update_dpll_ref_clks(struct drm_i915_privateinteldrm_softc *i915)
2258{
i915->dpll.ref_clks.ssc = 100000;
i915->dpll.ref_clks.nssc = 100000;
/* DSI non-SSC ref 19.2MHz */
2262}

2264static void bxt_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
2266{
drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->ebb0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->ebb4,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll2,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll3,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll6,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll8,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll9,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pll10,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12)
    hw_state->pcsdw12)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n"
, hw_state->ebb0, hw_state->ebb4, hw_state->pll0, hw_state
->pll1, hw_state->pll2, hw_state->pll3, hw_state->
pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10
, hw_state->pcsdw12);
2281}

2283static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
.get_freq = bxt_ddi_pll_get_freq,
2288};

2290static const struct dpll_info bxt_plls[] = {
{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
{ "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
{ },
2295};

2297static const struct intel_dpll_mgr bxt_pll_mgr = {
.dpll_info = bxt_plls,
.get_dplls = bxt_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = bxt_update_dpll_ref_clks,
.dump_hw_state = bxt_dump_hw_state,
2303};

2305static void cnl_ddi_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	       struct intel_shared_dpll *pll)
2307{
const enum intel_dpll_id id = pll->info->id;
u32 val;

/* 1. Enable DPLL power in DPLL_ENABLE. */
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }));
val |= PLL_POWER_ENABLE(1 << 27);
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), val);

/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }),
		  PLL_POWER_STATE(1 << 26), 5))
drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not enabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , id);

/*
* 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
* select DP mode, and set DP link rate.
*/
val = pll->state.hw_state.cfgcr0;
intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x6C000) + (id) * ((0x6C080) -
 (0x6C000)))) }), val);

/* 4. Reab back to ensure writes completed */
intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x6C000) + (id) * ((0x6C080) -
 (0x6C000)))) }));

/* 3. Configure DPLL_CFGCR0 */
/* Avoid touch CFGCR1 if HDMI mode is not enabled */
if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE(1 << 30)) {
val = pll->state.hw_state.cfgcr1;
intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x6C004) + (id) * ((0x6C084) -
 (0x6C004)))) }), val);
/* 4. Reab back to ensure writes completed */
intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x6C004) + (id) * ((0x6C084) -
 (0x6C004)))) }));
}

/*
* 5. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
* Sequence Before Frequency Change
*
* Note: DVFS is actually handled via the cdclk code paths,
* hence we do nothing here.
*/

/* 6. Enable DPLL in DPLL_ENABLE. */
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }));
val |= PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), val);

/* 7. Wait for PLL lock status in DPLL_ENABLE. */
if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), PLL_LOCK(1 << 30), 5))
drm_err(&dev_priv->drm, "PLL %d not locked\n", id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d not locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , id);

/*
* 8. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
* Sequence After Frequency Change
*
* Note: DVFS is actually handled via the cdclk code paths,
* hence we do nothing here.
*/

/*
* 9. turn on the clock for the DDI and map the DPLL to the DDI
* Done at intel_ddi_clk_select
*/
2371}

2373static void cnl_ddi_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll)
2375{
const enum intel_dpll_id id = pll->info->id;
u32 val;

/*
* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
* Done at intel_ddi_post_disable
*/

/*
* 2. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
* Sequence Before Frequency Change
*
* Note: DVFS is actually handled via the cdclk code paths,
* hence we do nothing here.
*/

/* 3. Disable DPLL through DPLL_ENABLE. */
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }));
val &= ~PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), val);

/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), PLL_LOCK(1 << 30), 5))
drm_err(&dev_priv->drm, "PLL %d locked\n", id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , id);

/*
* 5. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
* Sequence After Frequency Change
*
* Note: DVFS is actually handled via the cdclk code paths,
* hence we do nothing here.
*/

/* 6. Disable DPLL power in DPLL_ENABLE. */
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }));
val &= ~PLL_POWER_ENABLE(1 << 27);
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }), val);

/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }),
		    PLL_POWER_STATE(1 << 26), 5))
drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not disabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , id);
2420}

2422static bool_Bool cnl_ddi_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		     struct intel_shared_dpll *pll,
		     struct intel_dpll_hw_state *hw_state)
2425{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
u32 val;
bool_Bool ret;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

ret = false0;

val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)((const i915_reg_t){ .reg = (((0x46010) + (id) * ((0x46014) -
 (0x46010)))) }));
if (!(val & PLL_ENABLE(1 << 31)))
goto out;

val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x6C000) + (id) * ((0x6C080) -
 (0x6C000)))) }));
hw_state->cfgcr0 = val;

/* avoid reading back stale values if HDMI mode is not enabled */
if (val & DPLL_CFGCR0_HDMI_MODE(1 << 30)) {
hw_state->cfgcr1 = intel_de_read(dev_priv,
				 CNL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x6C004) + (id) * ((0x6C084) -
 (0x6C004)))) }));
}
ret = true1;

2452out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);

return ret;
2456}

2458static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
		      int *qdiv, int *kdiv)
2460{
/* even dividers */
if (bestdiv % 2 == 0) {
if (bestdiv == 2) {
	*pdiv = 2;
	*qdiv = 1;
	*kdiv = 1;
} else if (bestdiv % 4 == 0) {
	*pdiv = 2;
	*qdiv = bestdiv / 4;
	*kdiv = 2;
} else if (bestdiv % 6 == 0) {
	*pdiv = 3;
	*qdiv = bestdiv / 6;
	*kdiv = 2;
} else if (bestdiv % 5 == 0) {
	*pdiv = 5;
	*qdiv = bestdiv / 10;
	*kdiv = 2;
} else if (bestdiv % 14 == 0) {
	*pdiv = 7;
	*qdiv = bestdiv / 14;
	*kdiv = 2;
}
} else {
if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
	*pdiv = bestdiv;
	*qdiv = 1;
	*kdiv = 1;
} else { /* 9, 15, 21 */
	*pdiv = bestdiv / 3;
	*qdiv = 1;
	*kdiv = 3;
}
}
2495}

2497static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
		      u32 dco_freq, u32 ref_freq,
		      int pdiv, int qdiv, int kdiv)
2500{
u32 dco;

switch (kdiv) {
case 1:
params->kdiv = 1;
break;
case 2:
params->kdiv = 2;
break;
case 3:
params->kdiv = 4;
break;
default:
WARN(1, "Incorrect KDiv\n")({ int __ret = !!(1); if (__ret) printf("Incorrect KDiv\n"); __builtin_expect
(!!(__ret), 0); });
}

switch (pdiv) {
case 2:
params->pdiv = 1;
break;
case 3:
params->pdiv = 2;
break;
case 5:
params->pdiv = 4;
break;
case 7:
params->pdiv = 8;
break;
default:
WARN(1, "Incorrect PDiv\n")({ int __ret = !!(1); if (__ret) printf("Incorrect PDiv\n"); __builtin_expect
(!!(__ret), 0); });
}

WARN_ON(kdiv != 2 && qdiv != 1)({ int __ret = !!((kdiv != 2 && qdiv != 1)); if (__ret
) printf("%s", "WARN_ON(" "kdiv != 2 && qdiv != 1" ")"
); __builtin_expect(!!(__ret), 0); });

params->qdiv_ratio = qdiv;
params->qdiv_mode = (qdiv == 1) ? 0 : 1;

dco = div_u64((u64)dco_freq << 15, ref_freq);

params->dco_integer = dco >> 15;
params->dco_fraction = dco & 0x7fff;
2543}

2545static bool_Bool
2546__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
	  struct skl_wrpll_params *wrpll_params,
	  int ref_clock)
2549{
u32 afe_clock = crtc_state->port_clock * 5;
u32 dco_min = 7998000;
u32 dco_max = 10000000;
u32 dco_mid = (dco_min + dco_max) / 2;
static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
			 18, 20, 24, 28, 30, 32,  36,  40,
			 42, 44, 48, 50, 52, 54,  56,  60,
			 64, 66, 68, 70, 72, 76,  78,  80,
			 84, 88, 90, 92, 96, 98, 100, 102,
			  3,  5,  7,  9, 15, 21 };
u32 dco, best_dco = 0, dco_centrality = 0;
u32 best_dco_centrality = U32_MAX0xffffffffU; /* Spec meaning of 999999 MHz */
int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;

for (d = 0; d < ARRAY_SIZE(dividers)(sizeof((dividers)) / sizeof((dividers)[0])); d++) {
dco = afe_clock * dividers[d];

if ((dco <= dco_max) && (dco >= dco_min)) {
	dco_centrality = abs(dco - dco_mid);

	if (dco_centrality < best_dco_centrality) {
		best_dco_centrality = dco_centrality;
		best_div = dividers[d];
		best_dco = dco;
	}
}
}

if (best_div == 0)
return false0;

cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
		  pdiv, qdiv, kdiv);

return true1;
2586}

2588static bool_Bool
2589cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
	struct skl_wrpll_params *wrpll_params)
2591{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);

return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
			 i915->dpll.ref_clks.nssc);
2596}

2598static bool_Bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
2599{
u32 cfgcr0, cfgcr1;
struct skl_wrpll_params wrpll_params = { 0, };

cfgcr0 = DPLL_CFGCR0_HDMI_MODE(1 << 30);

if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
return false0;

cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction)((wrpll_params.dco_fraction) << 10) |
wrpll_params.dco_integer;

cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio)((wrpll_params.qdiv_ratio) << 10) |
DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode)((wrpll_params.qdiv_mode) << 9) |
DPLL_CFGCR1_KDIV(wrpll_params.kdiv)((wrpll_params.kdiv) << 6) |
DPLL_CFGCR1_PDIV(wrpll_params.pdiv)((wrpll_params.pdiv) << 2) |
DPLL_CFGCR1_CENTRAL_FREQ(3 << 0);

memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)))
      sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)));

crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
return true1;
2623}

2625/*
* Display WA #22010492432: tgl
* Program half of the nominal DCO divider fraction value.
*/
2629static bool_Bool
2630tgl_combo_pll_div_frac_wa_needed(struct drm_i915_privateinteldrm_softc *i915)
2631{
return IS_TIGERLAKE(i915)IS_PLATFORM(i915, INTEL_TIGERLAKE) && i915->dpll.ref_clks.nssc == 38400;
2633}

2635static int __cnl_ddi_wrpll_get_freq(struct drm_i915_privateinteldrm_softc *dev_priv,
		    const struct intel_shared_dpll *pll,
		    int ref_clock)
2638{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;

p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK(0xf << 2);
p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK(7 << 6);

if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)((1) << 9))
p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK(0xff << 10)) >>
	DPLL_CFGCR1_QDIV_RATIO_SHIFT(10);
else
p1 = 1;


switch (p0) {
case DPLL_CFGCR1_PDIV_2(1 << 2):
p0 = 2;
break;
case DPLL_CFGCR1_PDIV_3(2 << 2):
p0 = 3;
break;
case DPLL_CFGCR1_PDIV_5(4 << 2):
p0 = 5;
break;
case DPLL_CFGCR1_PDIV_7(8 << 2):
p0 = 7;
break;
}

switch (p2) {
case DPLL_CFGCR1_KDIV_1(1 << 6):
p2 = 1;
break;
case DPLL_CFGCR1_KDIV_2(2 << 6):
p2 = 2;
break;
case DPLL_CFGCR1_KDIV_3(4 << 6):
p2 = 3;
break;
}

dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK(0x3ff)) *
   ref_clock;

dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK(0x7fff << 10)) >>
       DPLL_CFGCR0_DCO_FRACTION_SHIFT(10);

if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;

dco_freq += (dco_fraction * ref_clock) / 0x8000;

if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0)({ int __ret = !!((p0 == 0 || p1 == 0 || p2 == 0)); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "p0 == 0 || p1 == 0 || p2 == 0"
 ")"); __builtin_expect(!!(__ret), 0); }))
return 0;

return dco_freq / (p0 * p1 * p2 * 5);
2695}

2697static int cnl_ddi_wrpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		  const struct intel_shared_dpll *pll)
2699{
return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
2701}

2703static bool_Bool
2704cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2705{
u32 cfgcr0;

cfgcr0 = DPLL_CFGCR0_SSC_ENABLE(1 << 29);

switch (crtc_state->port_clock / 2) {
case 81000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810(2 << 25);
break;
case 135000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350(1 << 25);
break;
case 270000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700(0 << 25);
break;
/* eDP 1.4 rates */
case 162000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620(3 << 25);
break;
case 108000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080(4 << 25);
break;
case 216000:
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160(5 << 25);
break;
case 324000:
/* Some SKUs may require elevated I/O voltage to support this */
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240(6 << 25);
break;
case 405000:
/* Some SKUs may require elevated I/O voltage to support this */
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050(7 << 25);
break;
}

memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)))
      sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof
(crtc_state->dpll_hw_state)));

crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;

return true1;
2746}

2748static int cnl_ddi_lcpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		  const struct intel_shared_dpll *pll)
2750{
int link_clock = 0;

switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK(0xf << 25)) {
case DPLL_CFGCR0_LINK_RATE_810(2 << 25):
link_clock = 81000;
break;
case DPLL_CFGCR0_LINK_RATE_1080(4 << 25):
link_clock = 108000;
break;
case DPLL_CFGCR0_LINK_RATE_1350(1 << 25):
link_clock = 135000;
break;
case DPLL_CFGCR0_LINK_RATE_1620(3 << 25):
link_clock = 162000;
break;
case DPLL_CFGCR0_LINK_RATE_2160(5 << 25):
link_clock = 216000;
break;
case DPLL_CFGCR0_LINK_RATE_2700(0 << 25):
link_clock = 270000;
break;
case DPLL_CFGCR0_LINK_RATE_3240(6 << 25):
link_clock = 324000;
break;
case DPLL_CFGCR0_LINK_RATE_4050(7 << 25):
link_clock = 405000;
break;
default:
drm_WARN(&i915->drm, 1, "Unsupported link rate\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "Unsupported link rate\n"
, dev_driver_string((&i915->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); });
break;
}

return link_clock * 2;
2784}

2786static bool_Bool cnl_get_dpll(struct intel_atomic_state *state,
	 struct intel_crtc *crtc,
	 struct intel_encoder *encoder)
2789{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_shared_dpll *pll;
bool_Bool bret;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
if (!bret) {
	drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not get HDMI pll dividers.\n"
)
		    "Could not get HDMI pll dividers.\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not get HDMI pll dividers.\n"
);
	return false0;
}
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
if (!bret) {
	drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not set DP dpll HW state.\n"
)
		    "Could not set DP dpll HW state.\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Could not set DP dpll HW state.\n"
);
	return false0;
}
} else {
drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Skip DPLL setup for output_types 0x%x\n"
, crtc_state->output_types)
	    "Skip DPLL setup for output_types 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Skip DPLL setup for output_types 0x%x\n"
, crtc_state->output_types)
	    crtc_state->output_types)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Skip DPLL setup for output_types 0x%x\n"
, crtc_state->output_types);
return false0;
}

pll = intel_find_shared_dpll(state, crtc,
		     &crtc_state->dpll_hw_state,
		     BIT(DPLL_ID_SKL_DPLL2)(1UL << (DPLL_ID_SKL_DPLL2)) |
		     BIT(DPLL_ID_SKL_DPLL1)(1UL << (DPLL_ID_SKL_DPLL1)) |
		     BIT(DPLL_ID_SKL_DPLL0)(1UL << (DPLL_ID_SKL_DPLL0)));
if (!pll) {
drm_dbg_kms(&i915->drm, "No PLL selected\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "No PLL selected\n"
);
return false0;
}

intel_reference_shared_dpll(state, crtc,
		    pll, &crtc_state->dpll_hw_state);

crtc_state->shared_dpll = pll;

return true1;
2833}

2835static int cnl_ddi_pll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		const struct intel_shared_dpll *pll)
2837{
if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE(1 << 30))
return cnl_ddi_wrpll_get_freq(i915, pll);
else
return cnl_ddi_lcpll_get_freq(i915, pll);
2842}

2844static void cnl_update_dpll_ref_clks(struct drm_i915_privateinteldrm_softc *i915)
2845{
/* No SSC reference */
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
2848}

2850static void cnl_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
2852{
drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "cfgcr0: 0x%x, cfgcr1: 0x%x\n", hw_state->cfgcr0, hw_state
->cfgcr1)
    "cfgcr0: 0x%x, cfgcr1: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "cfgcr0: 0x%x, cfgcr1: 0x%x\n", hw_state->cfgcr0, hw_state
->cfgcr1)
    hw_state->cfgcr0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "cfgcr0: 0x%x, cfgcr1: 0x%x\n", hw_state->cfgcr0, hw_state
->cfgcr1)
    hw_state->cfgcr1)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: "
 "cfgcr0: 0x%x, cfgcr1: 0x%x\n", hw_state->cfgcr0, hw_state
->cfgcr1);
2857}

2859static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
.enable = cnl_ddi_pll_enable,
.disable = cnl_ddi_pll_disable,
.get_hw_state = cnl_ddi_pll_get_hw_state,
.get_freq = cnl_ddi_pll_get_freq,
2864};

2866static const struct dpll_info cnl_plls[] = {
{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
{ },
2871};

2873static const struct intel_dpll_mgr cnl_pll_mgr = {
.dpll_info = cnl_plls,
.get_dplls = cnl_get_dpll,
.put_dplls = intel_put_dpll,
.update_ref_clks = cnl_update_dpll_ref_clks,
.dump_hw_state = cnl_dump_hw_state,
2879};

2881struct icl_combo_pll_params {
int clock;
struct skl_wrpll_params wrpll;
2884};

2886/*
* These values alrea already adjusted: they're the bits we write to the
* registers, not the logical values.
*/
2890static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
{ 540000,
 { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [0]: 5.4 */
   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 270000,
 { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [1]: 2.7 */
   .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 162000,
 { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [2]: 1.62 */
   .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 324000,
 { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [3]: 3.24 */
   .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 216000,
 { .dco_integer = 0x168, .dco_fraction = 0x0000,		/* [4]: 2.16 */
   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
{ 432000,
 { .dco_integer = 0x168, .dco_fraction = 0x0000,		/* [5]: 4.32 */
   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 648000,
 { .dco_integer = 0x195, .dco_fraction = 0x0000,		/* [6]: 6.48 */
   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 810000,
 { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [7]: 8.1 */
   .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2915};


2918/* Also used for 38.4 MHz values. */
2919static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
{ 540000,
 { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [0]: 5.4 */
   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 270000,
 { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [1]: 2.7 */
   .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 162000,
 { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [2]: 1.62 */
   .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 324000,
 { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [3]: 3.24 */
   .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 216000,
 { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [4]: 2.16 */
   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
{ 432000,
 { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [5]: 4.32 */
   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 648000,
 { .dco_integer = 0x1FA, .dco_fraction = 0x2000,		/* [6]: 6.48 */
   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
{ 810000,
 { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [7]: 8.1 */
   .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2944};

2946static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
.dco_integer = 0x151, .dco_fraction = 0x4000,
.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2949};

2951static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
.dco_integer = 0x1A5, .dco_fraction = 0x7000,
.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2954};

2956static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
.dco_integer = 0x54, .dco_fraction = 0x3000,
/* the following params are unused */
.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2960};

2962static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
.dco_integer = 0x43, .dco_fraction = 0x4000,
/* the following params are unused */
2965};

2967static bool_Bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
		  struct skl_wrpll_params *pll_params)
2969{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
dev_priv->dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
int i;

for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values)(sizeof((icl_dp_combo_pll_24MHz_values)) / sizeof((icl_dp_combo_pll_24MHz_values
)[0])); i++) {
if (clock == params[i].clock) {
	*pll_params = params[i].wrpll;
	return true1;
}
}

MISSING_CASE(clock)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "clock", (long)(clock)); __builtin_expect(!!(__ret), 0); });
return false0;
2987}

2989static bool_Bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
	     struct skl_wrpll_params *pll_params)
2991{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
switch (dev_priv->dpll.ref_clks.nssc) {
default:
	MISSING_CASE(dev_priv->dpll.ref_clks.nssc)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "dev_priv->dpll.ref_clks.nssc", (long)(dev_priv->dpll
.ref_clks.nssc)); __builtin_expect(!!(__ret), 0); });
	fallthroughdo {} while (0);
case 19200:
case 38400:
	*pll_params = tgl_tbt_pll_19_2MHz_values;
	break;
case 24000:
	*pll_params = tgl_tbt_pll_24MHz_values;
	break;
}
} else {
switch (dev_priv->dpll.ref_clks.nssc) {
default:
	MISSING_CASE(dev_priv->dpll.ref_clks.nssc)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "dev_priv->dpll.ref_clks.nssc", (long)(dev_priv->dpll
.ref_clks.nssc)); __builtin_expect(!!(__ret), 0); });
	fallthroughdo {} while (0);
case 19200:
case 38400:
	*pll_params = icl_tbt_pll_19_2MHz_values;
	break;
case 24000:
	*pll_params = icl_tbt_pll_24MHz_values;
	break;
}
}

return true1;
3023}

3025static int icl_ddi_tbt_pll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		    const struct intel_shared_dpll *pll)
3027{
/*
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
*/
drm_WARN_ON(&i915->drm, 1)({ int __ret = !!((1)); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&i915->drm))->dev), "", "drm_WARN_ON(" "1" ")");
 __builtin_expect(!!(__ret), 0); });

return 0;
3035}

3037static int icl_wrpll_ref_clock(struct drm_i915_privateinteldrm_softc *i915)
3038{
int ref_clock = i915->dpll.ref_clks.nssc;

/*
* For ICL+, the spec states: if reference frequency is 38.4,
* use 19.2 because the DPLL automatically divides that by 2.
*/
if (ref_clock == 38400)
ref_clock = 19200;

return ref_clock;
3049}

3051static bool_Bool
3052icl_calc_wrpll(struct intel_crtc_state *crtc_state,
      struct skl_wrpll_params *wrpll_params)
3054{
struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev);

return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
			 icl_wrpll_ref_clock(i915));
3059}

3061static int icl_ddi_combo_pll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
		      const struct intel_shared_dpll *pll)
3063{
return __cnl_ddi_wrpll_get_freq(i915, pll,
			icl_wrpll_ref_clock(i915));
3066}

3068static void icl_calc_dpll_state(struct drm_i915_privateinteldrm_softc *i915,
		const struct skl_wrpll_params *pll_params,
		struct intel_dpll_hw_state *pll_state)
3071{
u32 dco_fraction = pll_params->dco_fraction;

memset(pll_state, 0, sizeof(*pll_state))__builtin_memset((pll_state), (0), (sizeof(*pll_state)));

if (tgl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2)(((dco_fraction) + ((2) / 2)) / (2));

pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction)((dco_fraction) << 10) |
	    pll_params->dco_integer;

pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio)((pll_params->qdiv_ratio) << 10) |
	    DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode)((pll_params->qdiv_mode) << 9) |
	    DPLL_CFGCR1_KDIV(pll_params->kdiv)((pll_params->kdiv) << 6) |
	    DPLL_CFGCR1_PDIV(pll_params->pdiv)((pll_params->pdiv) << 2);

if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 12)
pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL(0 << 0);
else
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400(3 << 0);
3091}

3093static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
3094{
return id - DPLL_ID_ICL_MGPLL1;
3096}

3098enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
3099{
return tc_port + DPLL_ID_ICL_MGPLL1;
3101}

3103static bool_Bool icl_mg_pll_find_divisors(int clock_khz, bool_Bool is_dp, bool_Bool use_ssc,
		     u32 *target_dco_khz,
		     struct intel_dpll_hw_state *state,
		     bool_Bool is_dkl)
3107{
u32 dco_min_freq, dco_max_freq;
int div1_vals[] = {7, 5, 3, 2};
unsigned int i;
int div2;

dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
dco_max_freq = is_dp ? 8100000 : 10000000;

for (i = 0; i < ARRAY_SIZE(div1_vals)(sizeof((div1_vals)) / sizeof((div1_vals)[0])); i++) {
int div1 = div1_vals[i];

for (div2 = 10; div2 > 0; div2--) {
	int dco = div1 * div2 * clock_khz * 5;
	int a_divratio, tlinedrv, inputsel;
	u32 hsdiv;

	if (dco < dco_min_freq || dco > dco_max_freq)
		continue;

	if (div2 >= 2) {
		/*
		 * Note: a_divratio not matching TGL BSpec
		 * algorithm but matching hardcoded values and
		 * working on HW for DP alt-mode at least
		 */
		a_divratio = is_dp ? 10 : 5;
		tlinedrv = is_dkl ? 1 : 2;
	} else {
		a_divratio = 5;
		tlinedrv = 0;
	}
	inputsel = is_dp ? 0 : 1;

	switch (div1) {
	default:
		MISSING_CASE(div1)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "div1", (long)(div1)); __builtin_expect(!!(__ret), 0); });
		fallthroughdo {} while (0);
	case 2:
		hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2(0 << 12);
		break;
	case 3:
		hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3(1 << 12);
		break;
	case 5:
		hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5(2 << 12);
		break;
	case 7:
		hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7(3 << 12);
		break;
	}

	*target_dco_khz = dco;

	state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1)((1) << 8);

	state->mg_clktop2_coreclkctl1 =
		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio)((a_divratio) << 8);

	state->mg_clktop2_hsclkctl =
		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv)((tlinedrv) << 14) |
		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel)((inputsel) << 16) |
		hsdiv |
		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2)((div2) << 8);

	return true1;
}
}

return false0;
3177}

3179/*
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
*/
3183static bool_Bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
		  struct intel_dpll_hw_state *pll_state)
3185{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int refclk_khz = dev_priv->dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
u32 prop_coeff, int_coeff;
u32 tdc_targetcnt, feedfwgain;
u64 ssc_stepsize, ssc_steplen, ssc_steplog;
u64 tmp;
bool_Bool use_ssc = false0;
bool_Bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
bool_Bool is_dkl = INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12;

memset(pll_state, 0, sizeof(*pll_state))__builtin_memset((pll_state), (0), (sizeof(*pll_state)));

if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
		      pll_state, is_dkl)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to find divisors for clock %d\n"
, clock)
	    "Failed to find divisors for clock %d\n", clock)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to find divisors for clock %d\n"
, clock);
return false0;
}

m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
if (m2div_int > 255) {
if (!is_dkl) {
	m1div = 4;
	m2div_int = dco_khz / (refclk_khz * m1div);
}

if (m2div_int > 255) {
	drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to find mdiv for clock %d\n"
, clock)
		    "Failed to find mdiv for clock %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to find mdiv for clock %d\n"
, clock)
		    clock)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to find mdiv for clock %d\n"
, clock);
	return false0;
}
}
m2div_rem = dco_khz % (refclk_khz * m1div);

tmp = (u64)m2div_rem * (1 << 22);
do_div(tmp, refclk_khz * m1div)({ uint32_t __base = (refclk_khz * m1div); uint32_t __rem = (
(uint64_t)(tmp)) % __base; (tmp) = ((uint64_t)(tmp)) / __base
; __rem; });
m2div_frac = tmp;

switch (refclk_khz) {
case 19200:
iref_ndiv = 1;
iref_trim = 28;
iref_pulse_w = 1;
break;
case 24000:
iref_ndiv = 1;
iref_trim = 25;
iref_pulse_w = 2;
break;
case 38400:
iref_ndiv = 2;
iref_trim = 28;
iref_pulse_w = 1;
break;
default:
MISSING_CASE(refclk_khz)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "refclk_khz", (long)(refclk_khz)); __builtin_expect(!!(__ret
), 0); });
return false0;
}

/*
* tdc_res = 0.000003
* tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
*
* The multiplication by 1000 is due to refclk MHz to KHz conversion. It
* was supposed to be a division, but we rearranged the operations of
* the formula to avoid early divisions so we don't multiply the
* rounding errors.
*
* 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
* we also rearrange to work with integers.
*
* The 0.5 transformed to 5 results in a multiplication by 10 and the
* last division by 10.
*/
tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;

/*
* Here we divide dco_khz by 10 in order to allow the dividend to fit in
* 32 bits. That's not a problem since we round the division down
* anyway.
*/
feedfwgain = (use_ssc || m2div_rem > 0) ?
m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;

if (dco_khz >= 9000000) {
prop_coeff = 5;
int_coeff = 10;
} else {
prop_coeff = 4;
int_coeff = 8;
}

if (use_ssc) {
tmp = mul_u32_u32(dco_khz, 47 * 32);
do_div(tmp, refclk_khz * m1div * 10000)({ uint32_t __base = (refclk_khz * m1div * 10000); uint32_t __rem
 = ((uint64_t)(tmp)) % __base; (tmp) = ((uint64_t)(tmp)) / __base
; __rem; });
ssc_stepsize = tmp;

tmp = mul_u32_u32(dco_khz, 1000);
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32)(((tmp) + ((32 * 2 * 32) - 1)) / (32 * 2 * 32));
} else {
ssc_stepsize = 0;
ssc_steplen = 0;
}
ssc_steplog = 4;

/* write pll_state calculations */
if (is_dkl) {
pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff)((int_coeff) << 16) |
			 DKL_PLL_DIV0_PROP_COEFF(prop_coeff)((prop_coeff) << 12) |
			 DKL_PLL_DIV0_FBPREDIV(m1div)((m1div) << (8)) |
			 DKL_PLL_DIV0_FBDIV_INT(m2div_int)((m2div_int) << 0);

pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim)((iref_trim) << 16) |
			 DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt)((tdc_targetcnt) << 0);

pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv)((iref_ndiv) << 29) |
			DKL_PLL_SSC_STEP_LEN(ssc_steplen)((ssc_steplen) << 16) |
			DKL_PLL_SSC_STEP_NUM(ssc_steplog)((ssc_steplog) << 11) |
			(use_ssc ? DKL_PLL_SSC_EN(1 << 9) : 0);

pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H(1 << 30) : 0) |
			  DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac)((m2div_frac) << (8));

pll_state->mg_pll_tdc_coldst_bias =
		DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize)((ssc_stepsize) << 8) |
		DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain)((feedfwgain) << 0);

} else {
pll_state->mg_pll_div0 =
	(m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H(1 << 30) : 0) |
	MG_PLL_DIV0_FBDIV_FRAC(m2div_frac)((m2div_frac) << 8) |
	MG_PLL_DIV0_FBDIV_INT(m2div_int)((m2div_int) << 0);

pll_state->mg_pll_div1 =
	MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv)((iref_ndiv) << 16) |
	MG_PLL_DIV1_DITHER_DIV_2(1 << 12) |
	MG_PLL_DIV1_NDIVRATIO(1)((1) << 4) |
	MG_PLL_DIV1_FBPREDIV(m1div)((m1div) << 0);

pll_state->mg_pll_lf =
	MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt)((tdc_targetcnt) << 24) |
	MG_PLL_LF_AFCCNTSEL_512(1 << 20) |
	MG_PLL_LF_GAINCTRL(1)((1) << 16) |
	MG_PLL_LF_INT_COEFF(int_coeff)((int_coeff) << 8) |
	MG_PLL_LF_PROP_COEFF(prop_coeff)((prop_coeff) << 0);

pll_state->mg_pll_frac_lock =
	MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32(1 << 18) |
	MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32(1 << 16) |
	MG_PLL_FRAC_LOCK_LOCKTHRESH(10)((10) << 11) |
	MG_PLL_FRAC_LOCK_DCODITHEREN(1 << 10) |
	MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain)((feedfwgain) << 0);
if (use_ssc || m2div_rem > 0)
	pll_state->mg_pll_frac_lock |=
		MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN(1 << 8);

pll_state->mg_pll_ssc =
	(use_ssc ? MG_PLL_SSC_EN(1 << 28) : 0) |
	MG_PLL_SSC_TYPE(2)((2) << 26) |
	MG_PLL_SSC_STEPLENGTH(ssc_steplen)((ssc_steplen) << 16) |
	MG_PLL_SSC_STEPNUM(ssc_steplog)((ssc_steplog) << 10) |
	MG_PLL_SSC_FLLEN(1 << 9) |
	MG_PLL_SSC_STEPSIZE(ssc_stepsize)((ssc_stepsize) << 0);

pll_state->mg_pll_tdc_coldst_bias =
	MG_PLL_TDC_COLDST_COLDSTART(1 << 16) |
	MG_PLL_TDC_COLDST_IREFINT_EN(1 << 27) |
	MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w)((iref_pulse_w) << 17) |
	MG_PLL_TDC_TDCOVCCORR_EN(1 << 2) |
	MG_PLL_TDC_TDCSEL(3)((3) << 0);

pll_state->mg_pll_bias =
	MG_PLL_BIAS_BIAS_GB_SEL(3)((3) << 30) |
	MG_PLL_BIAS_INIT_DCOAMP(0x3F)((0x3F) << 24) |
	MG_PLL_BIAS_BIAS_BONUS(10)((10) << 16) |
	MG_PLL_BIAS_BIASCAL_EN(1 << 15) |
	MG_PLL_BIAS_CTRIM(12)((12) << 8) |
	MG_PLL_BIAS_VREF_RDAC(4)((4) << 5) |
	MG_PLL_BIAS_IREFTRIM(iref_trim)((iref_trim) << 0);

if (refclk_khz == 38400) {
	pll_state->mg_pll_tdc_coldst_bias_mask =
		MG_PLL_TDC_COLDST_COLDSTART(1 << 16);
	pll_state->mg_pll_bias_mask = 0;
} else {
	pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
	pll_state->mg_pll_bias_mask = -1U;
}

pll_state->mg_pll_tdc_coldst_bias &=
	pll_state->mg_pll_tdc_coldst_bias_mask;
pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
}

return true1;
3386}

3388static int icl_ddi_mg_pll_get_freq(struct drm_i915_privateinteldrm_softc *dev_priv,
		   const struct intel_shared_dpll *pll)
3390{
const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;

ref_clock = dev_priv->dpll.ref_clks.nssc;

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK(0xF << (8));
m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT(8);
m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK(0xFF << 0);

if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H(1 << 30)) {
	m2_frac = pll_state->mg_pll_bias &
		  DKL_PLL_BIAS_FBDIV_FRAC_MASK(0x3FFFFF << (8));
	m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT(8);
} else {
	m2_frac = 0;
}
} else {
m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK(0xf << 0);
m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK(0xff << 0);

if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H(1 << 30)) {
	m2_frac = pll_state->mg_pll_div0 &
		  MG_PLL_DIV0_FBDIV_FRAC_MASK(0x3fffff << 8);
	m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT8;
} else {
	m2_frac = 0;
}
}

switch (pll_state->mg_clktop2_hsclkctl &
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12)) {
case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2(0 << 12):
div1 = 2;
break;
case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3(1 << 12):
div1 = 3;
break;
case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5(2 << 12):
div1 = 5;
break;
case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7(3 << 12):
div1 = 7;
break;
default:
MISSING_CASE(pll_state->mg_clktop2_hsclkctl)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "pll_state->mg_clktop2_hsclkctl", (long)(pll_state->mg_clktop2_hsclkctl
)); __builtin_expect(!!(__ret), 0); });
return 0;
}

div2 = (pll_state->mg_clktop2_hsclkctl &
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8)) >>
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT8;

/* div2 value of 0 is same as 1 means no div */
if (div2 == 0)
div2 = 1;

/*
* Adjust the original formula to delay the division by 2^22 in order to
* minimize possible rounding errors.
*/
tmp = (u64)m1 * m2_int * ref_clock +
     (((u64)m1 * m2_frac * ref_clock) >> 22);
tmp = div_u64(tmp, 5 * div1 * div2);

return tmp;
3458}

3460/**
* icl_set_active_port_dpll - select the active port DPLL for a given CRTC
* @crtc_state: state for the CRTC to select the DPLL for
* @port_dpll_id: the active @port_dpll_id to select
*
* Select the given @port_dpll_id instance from the DPLLs reserved for the
* CRTC.
*/
3468void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
	      enum icl_port_dpll_id port_dpll_id)
3470{
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[port_dpll_id];

crtc_state->shared_dpll = port_dpll->pll;
crtc_state->dpll_hw_state = port_dpll->hw_state;
3476}

3478static void icl_update_active_dpll(struct intel_atomic_state *state,
		   struct intel_crtc *crtc,
		   struct intel_encoder *encoder)
3481{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_digital_port *primary_port;
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;

primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
enc_to_mst(encoder)->primary :
enc_to_dig_port(encoder);

if (primary_port &&
   (primary_port->tc_mode == TC_PORT_DP_ALT ||
    primary_port->tc_mode == TC_PORT_LEGACY))
port_dpll_id = ICL_PORT_DPLL_MG_PHY;

icl_set_active_port_dpll(crtc_state, port_dpll_id);
3497}

3499static u32 intel_get_hti_plls(struct drm_i915_privateinteldrm_softc *i915)
3500{
if (!(i915->hti_state & HDPORT_ENABLED((u32)((1UL << (0)) + 0))))
return 0;

return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state)((u32)((typeof(((u32)((((~0UL) >> (64 - (14) - 1)) &
 ((~0UL) << (12))) + 0))))(((i915->hti_state) & (
((u32)((((~0UL) >> (64 - (14) - 1)) & ((~0UL) <<
 (12))) + 0)))) >> (__builtin_ffsll(((u32)((((~0UL) >>
 (64 - (14) - 1)) & ((~0UL) << (12))) + 0))) - 1)))
);
3505}

3507static bool_Bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
		   struct intel_crtc *crtc,
		   struct intel_encoder *encoder)
3510{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_wrpll_params pll_params = { };
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
enum port port = encoder->port;
unsigned long dpll_mask;
int ret;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
ret = icl_calc_wrpll(crtc_state, &pll_params);
else
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);

if (!ret) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate combo PHY PLL state.\n"
)
	    "Could not calculate combo PHY PLL state.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate combo PHY PLL state.\n"
);

return false0;
}

icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);

if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) {
dpll_mask =
	BIT(DPLL_ID_EHL_DPLL4)(1UL << (DPLL_ID_EHL_DPLL4)) |
	BIT(DPLL_ID_ICL_DPLL1)(1UL << (DPLL_ID_ICL_DPLL1)) |
	BIT(DPLL_ID_ICL_DPLL0)(1UL << (DPLL_ID_ICL_DPLL0));
} else if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) && port != PORT_A) {
dpll_mask =
	BIT(DPLL_ID_EHL_DPLL4)(1UL << (DPLL_ID_EHL_DPLL4)) |
	BIT(DPLL_ID_ICL_DPLL1)(1UL << (DPLL_ID_ICL_DPLL1)) |
	BIT(DPLL_ID_ICL_DPLL0)(1UL << (DPLL_ID_ICL_DPLL0));
} else {
dpll_mask = BIT(DPLL_ID_ICL_DPLL1)(1UL << (DPLL_ID_ICL_DPLL1)) | BIT(DPLL_ID_ICL_DPLL0)(1UL << (DPLL_ID_ICL_DPLL0));
}

/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_get_hti_plls(dev_priv);

port_dpll->pll = intel_find_shared_dpll(state, crtc,
				&port_dpll->hw_state,
				dpll_mask);
if (!port_dpll->pll) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No combo PHY PLL found for [ENCODER:%d:%s]\n"
, encoder->base.base.id, encoder->base.name)
	    "No combo PHY PLL found for [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No combo PHY PLL found for [ENCODER:%d:%s]\n"
, encoder->base.base.id, encoder->base.name)
	    encoder->base.base.id, encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No combo PHY PLL found for [ENCODER:%d:%s]\n"
, encoder->base.base.id, encoder->base.name);
return false0;
}

intel_reference_shared_dpll(state, crtc,
		    port_dpll->pll, &port_dpll->hw_state);

icl_update_active_dpll(state, crtc, encoder);

return true1;
3569}

3571static bool_Bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
		 struct intel_crtc *crtc,
		 struct intel_encoder *encoder)
3574{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_wrpll_params pll_params = { };
struct icl_port_dpll *port_dpll;
enum intel_dpll_id dpll_id;

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
if (!icl_calc_tbt_pll(crtc_state, &pll_params)) {
6
←
Taking false branch→
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate TBT PLL state.\n"
)
	    "Could not calculate TBT PLL state.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate TBT PLL state.\n"
);
return false0;
}

icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);

port_dpll->pll = intel_find_shared_dpll(state, crtc,
7
←
Calling 'intel_find_shared_dpll'→
				&port_dpll->hw_state,
				BIT(DPLL_ID_ICL_TBTPLL)(1UL << (DPLL_ID_ICL_TBTPLL)));
if (!port_dpll->pll) {
drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No TBT-ALT PLL found\n"
);
return false0;
}
intel_reference_shared_dpll(state, crtc,
		    port_dpll->pll, &port_dpll->hw_state);


port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate MG PHY PLL state.\n"
)
	    "Could not calculate MG PHY PLL state.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Could not calculate MG PHY PLL state.\n"
);
goto err_unreference_tbt_pll;
}

dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
					 encoder->port));
port_dpll->pll = intel_find_shared_dpll(state, crtc,
				&port_dpll->hw_state,
				BIT(dpll_id)(1UL << (dpll_id)));
if (!port_dpll->pll) {
drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No MG PHY PLL found\n"
);
goto err_unreference_tbt_pll;
}
intel_reference_shared_dpll(state, crtc,
		    port_dpll->pll, &port_dpll->hw_state);

icl_update_active_dpll(state, crtc, encoder);

return true1;

3625err_unreference_tbt_pll:
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
intel_unreference_shared_dpll(state, crtc, port_dpll->pll);

return false0;
3630}

3632static bool_Bool icl_get_dplls(struct intel_atomic_state *state,
	  struct intel_crtc *crtc,
	  struct intel_encoder *encoder)
3635{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);

if (intel_phy_is_combo(dev_priv, phy))
1
Assuming the condition is false→
2
←
Taking false branch→
return icl_get_combo_phy_dpll(state, crtc, encoder);
else if (intel_phy_is_tc(dev_priv, phy))
3
←
Assuming the condition is true→
4
←
Taking true branch→
return icl_get_tc_phy_dplls(state, crtc, encoder);
5
←
Calling 'icl_get_tc_phy_dplls'→

MISSING_CASE(phy)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "phy", (long)(phy)); __builtin_expect(!!(__ret), 0); });

return false0;
3647}

3649static void icl_put_dplls(struct intel_atomic_state *state,
	  struct intel_crtc *crtc)
3651{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
enum icl_port_dpll_id id;

new_crtc_state->shared_dpll = NULL((void *)0);

for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
const struct icl_port_dpll *old_port_dpll =
	&old_crtc_state->icl_port_dplls[id];
struct icl_port_dpll *new_port_dpll =
	&new_crtc_state->icl_port_dplls[id];

new_port_dpll->pll = NULL((void *)0);

if (!old_port_dpll->pll)
	continue;

intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
}
3673}

3675static bool_Bool mg_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		struct intel_shared_dpll *pll,
		struct intel_dpll_hw_state *hw_state)
3678{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
intel_wakeref_t wakeref;
bool_Bool ret = false0;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)((const i915_reg_t){ .reg = (((0x46030) + ((tc_port)) * ((0x46034
) - (0x46030)))) }));
if (!(val & PLL_ENABLE(1 << 31)))
goto out;

hw_state->mg_refclkin_ctl = intel_de_read(dev_priv,
				  MG_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) }));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8);

hw_state->mg_clktop2_coreclkctl1 =
intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) }));
hw_state->mg_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK(0xff << 8);

hw_state->mg_clktop2_hsclkctl =
intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) }));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK(0x3 << 14) |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK(0x1 << 16) |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12) |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8);

hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168A00) + ((tc_port)) * ((0x169A00
) - (0x168A00)))) }));
hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168A04) + ((tc_port)) * ((0x169A04
) - (0x168A04)))) }));
hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)((const i915_reg_t){ .reg = (((0x168A08) + ((tc_port)) * ((0x169A08
) - (0x168A08)))) }));
hw_state->mg_pll_frac_lock = intel_de_read(dev_priv,
				   MG_PLL_FRAC_LOCK(tc_port)((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) }));
hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168A10) + ((tc_port)) * ((0x169A10
) - (0x168A10)))) }));

hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) }));
hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) }));

if (dev_priv->dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART(1 << 16);
hw_state->mg_pll_bias_mask = 0;
} else {
hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
hw_state->mg_pll_bias_mask = -1U;
}

hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;

ret = true1;
3734out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return ret;
3737}

3739static bool_Bool dkl_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll,
		 struct intel_dpll_hw_state *hw_state)
3742{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
intel_wakeref_t wakeref;
bool_Bool ret = false0;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)((const i915_reg_t){ .reg = (((0x46030) + ((tc_port)) * ((0x46034
) - (0x46030)))) }));
if (!(val & PLL_ENABLE(1 << 31)))
goto out;

/*
* All registers read here have the same HIP_INDEX_REG even though
* they are on different building blocks
*/
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port)((const i915_reg_t){ .reg = ((tc_port) < 4 ? 0x1010A0 : 0x1010A4
) }),
       HIP_INDEX_VAL(tc_port, 0x2)((0x2) << (8 * ((tc_port) % 4))));

hw_state->mg_refclkin_ctl = intel_de_read(dev_priv,
				  DKL_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) }));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8);

hw_state->mg_clktop2_hsclkctl =
intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) }));
hw_state->mg_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK(0x3 << 14) |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK(0x1 << 16) |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12) |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8);

hw_state->mg_clktop2_coreclkctl1 =
intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) }));
hw_state->mg_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK(0xff << 8);

hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) }));
hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16) |
		  DKL_PLL_DIV0_PROP_COEFF_MASK(0xF << 12) |
		  DKL_PLL_DIV0_FBPREDIV_MASK(0xF << (8)) |
		  DKL_PLL_DIV0_FBDIV_INT_MASK(0xFF << 0));

hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) }));
hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK(0x1F << 16) |
		  DKL_PLL_DIV1_TDC_TARGET_CNT_MASK(0xFF << 0));

hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) }));
hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK(0x7 << 29) |
		 DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16) |
		 DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11) |
		 DKL_PLL_SSC_EN(1 << 9));

hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) }));
hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H(1 << 30) |
		  DKL_PLL_BIAS_FBDIV_FRAC_MASK(0x3FFFFF << (8)));

hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) }));
hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK(0xFF << 8) |
			     DKL_PLL_TDC_FEED_FWD_GAIN_MASK(0xFF << 0));

ret = true1;
3808out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return ret;
3811}

3813static bool_Bool icl_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll,
		 struct intel_dpll_hw_state *hw_state,
		 i915_reg_t enable_reg)
3817{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
bool_Bool ret = false0;
u32 val;

wakeref = intel_display_power_get_if_enabled(dev_priv,
				     POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false0;

val = intel_de_read(dev_priv, enable_reg);
if (!(val & PLL_ENABLE(1 << 31)))
goto out;

if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
				 RKL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x164284) + (id) * ((0x16428C)
 - (0x164284)))) }));
hw_state->cfgcr1 = intel_de_read(dev_priv,
				 RKL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x164288) + (id) * ((0x164290)
 - (0x164288)))) }));
} else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
				 TGL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[id])) }));
hw_state->cfgcr1 = intel_de_read(dev_priv,
				 TGL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[id])) }));
} else {
if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) && id == DPLL_ID_EHL_DPLL4) {
	hw_state->cfgcr0 = intel_de_read(dev_priv,
					 ICL_DPLL_CFGCR0(4)((const i915_reg_t){ .reg = (((0x164000) + (4) * ((0x164080) -
 (0x164000)))) }));
	hw_state->cfgcr1 = intel_de_read(dev_priv,
					 ICL_DPLL_CFGCR1(4)((const i915_reg_t){ .reg = (((0x164004) + (4) * ((0x164084) -
 (0x164004)))) }));
} else {
	hw_state->cfgcr0 = intel_de_read(dev_priv,
					 ICL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x164000) + (id) * ((0x164080)
 - (0x164000)))) }));
	hw_state->cfgcr1 = intel_de_read(dev_priv,
					 ICL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x164004) + (id) * ((0x164084)
 - (0x164004)))) }));
}
}

ret = true1;
3857out:
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return ret;
3860}

3862static bool_Bool combo_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		   struct intel_shared_dpll *pll,
		   struct intel_dpll_hw_state *hw_state)
3865{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);

return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
3869}

3871static bool_Bool tbt_pll_get_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll,
		 struct intel_dpll_hw_state *hw_state)
3874{
return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE((const i915_reg_t){ .reg = (0x46020) }));
3876}

3878static void icl_dpll_write(struct drm_i915_privateinteldrm_softc *dev_priv,
	   struct intel_shared_dpll *pll)
3880{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;

if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) {
cfgcr0_reg = RKL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x164284) + (id) * ((0x16428C)
 - (0x164284)))) });
cfgcr1_reg = RKL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x164288) + (id) * ((0x164290)
 - (0x164288)))) });
} else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[id])) });
cfgcr1_reg = TGL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[id])) });
} else {
if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) && id == DPLL_ID_EHL_DPLL4) {
	cfgcr0_reg = ICL_DPLL_CFGCR0(4)((const i915_reg_t){ .reg = (((0x164000) + (4) * ((0x164080) -
 (0x164000)))) });
	cfgcr1_reg = ICL_DPLL_CFGCR1(4)((const i915_reg_t){ .reg = (((0x164004) + (4) * ((0x164084) -
 (0x164004)))) });
} else {
	cfgcr0_reg = ICL_DPLL_CFGCR0(id)((const i915_reg_t){ .reg = (((0x164000) + (id) * ((0x164080)
 - (0x164000)))) });
	cfgcr1_reg = ICL_DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x164004) + (id) * ((0x164084)
 - (0x164004)))) });
}
}

intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
intel_de_posting_read(dev_priv, cfgcr1_reg);
3904}

3906static void icl_mg_pll_write(struct drm_i915_privateinteldrm_softc *dev_priv,
	     struct intel_shared_dpll *pll)
3908{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
u32 val;

/*
* Some of the following registers have reserved fields, so program
* these with RMW based on a mask. The mask can be fixed or generated
* during the calc/readout phase if the mask depends on some other HW
* state like refclk, see icl_calc_mg_pll_state().
*/
val = intel_de_read(dev_priv, MG_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) }));
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8);
val |= hw_state->mg_refclkin_ctl;
intel_de_write(dev_priv, MG_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) }), val);

val = intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) }));
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK(0xff << 8);
val |= hw_state->mg_clktop2_coreclkctl1;
intel_de_write(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) }), val);

val = intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) }));
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK(0x3 << 14) |
 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK(0x1 << 16) |
 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12) |
 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8));
val |= hw_state->mg_clktop2_hsclkctl;
intel_de_write(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) }), val);

intel_de_write(dev_priv, MG_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168A00) + ((tc_port)) * ((0x169A00
) - (0x168A00)))) }), hw_state->mg_pll_div0);
intel_de_write(dev_priv, MG_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168A04) + ((tc_port)) * ((0x169A04
) - (0x168A04)))) }), hw_state->mg_pll_div1);
intel_de_write(dev_priv, MG_PLL_LF(tc_port)((const i915_reg_t){ .reg = (((0x168A08) + ((tc_port)) * ((0x169A08
) - (0x168A08)))) }), hw_state->mg_pll_lf);
intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port)((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) }),
       hw_state->mg_pll_frac_lock);
intel_de_write(dev_priv, MG_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168A10) + ((tc_port)) * ((0x169A10
) - (0x168A10)))) }), hw_state->mg_pll_ssc);

val = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) }));
val &= ~hw_state->mg_pll_bias_mask;
val |= hw_state->mg_pll_bias;
intel_de_write(dev_priv, MG_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) }), val);

val = intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) }));
val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
val |= hw_state->mg_pll_tdc_coldst_bias;
intel_de_write(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) }), val);

intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) }));
3955}

3957static void dkl_pll_write(struct drm_i915_privateinteldrm_softc *dev_priv,
	  struct intel_shared_dpll *pll)
3959{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
u32 val;

/*
* All registers programmed here have the same HIP_INDEX_REG even
* though on different building block
*/
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port)((const i915_reg_t){ .reg = ((tc_port) < 4 ? 0x1010A0 : 0x1010A4
) }),
       HIP_INDEX_VAL(tc_port, 0x2)((0x2) << (8 * ((tc_port) % 4))));

/* All the registers are RMW */
val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) }));
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8);
val |= hw_state->mg_refclkin_ctl;
intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) }), val);

val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) }));
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK(0xff << 8);
val |= hw_state->mg_clktop2_coreclkctl1;
intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) }), val);

val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) }));
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK(0x3 << 14) |
 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK(0x1 << 16) |
 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12) |
 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8));
val |= hw_state->mg_clktop2_hsclkctl;
intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) }), val);

val = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) }));
val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16) |
 DKL_PLL_DIV0_PROP_COEFF_MASK(0xF << 12) |
 DKL_PLL_DIV0_FBPREDIV_MASK(0xF << (8)) |
 DKL_PLL_DIV0_FBDIV_INT_MASK(0xFF << 0));
val |= hw_state->mg_pll_div0;
intel_de_write(dev_priv, DKL_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) }), val);

val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) }));
val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK(0x1F << 16) |
 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK(0xFF << 0));
val |= hw_state->mg_pll_div1;
intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) }), val);

val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) }));
val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK(0x7 << 29) |
 DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16) |
 DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11) |
 DKL_PLL_SSC_EN(1 << 9));
val |= hw_state->mg_pll_ssc;
intel_de_write(dev_priv, DKL_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) }), val);

val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) }));
val &= ~(DKL_PLL_BIAS_FRAC_EN_H(1 << 30) |
 DKL_PLL_BIAS_FBDIV_FRAC_MASK(0x3FFFFF << (8)));
val |= hw_state->mg_pll_bias;
intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) }), val);

val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) }));
val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK(0xFF << 8) |
 DKL_PLL_TDC_FEED_FWD_GAIN_MASK(0xFF << 0));
val |= hw_state->mg_pll_tdc_coldst_bias;
intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) }), val);

intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) }));
4025}

4027static void icl_pll_power_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
		 struct intel_shared_dpll *pll,
		 i915_reg_t enable_reg)
4030{
u32 val;

val = intel_de_read(dev_priv, enable_reg);
val |= PLL_POWER_ENABLE(1 << 27);
intel_de_write(dev_priv, enable_reg, val);

/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE(1 << 26), 1))
drm_err(&dev_priv->drm, "PLL %d Power not enabled\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not enabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id)
	pll->info->id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not enabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id);
4044}

4046static void icl_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	   struct intel_shared_dpll *pll,
	   i915_reg_t enable_reg)
4049{
u32 val;

val = intel_de_read(dev_priv, enable_reg);
val |= PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, enable_reg, val);

/* Timeout is actually 600us. */
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK(1 << 30), 1))
drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d not locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id);
4059}

4061static void combo_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	     struct intel_shared_dpll *pll)
4063{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);

if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) &&
   pll->info->id == DPLL_ID_EHL_DPLL4) {

/*
 * We need to disable DC states when this DPLL is enabled.
 * This can be done by taking a reference on DPLL4 power
 * domain.
 */
pll->wakeref = intel_display_power_get(dev_priv,
				       POWER_DOMAIN_DPLL_DC_OFF);
}

icl_pll_power_enable(dev_priv, pll, enable_reg);

icl_dpll_write(dev_priv, pll);

/*
* DVFS pre sequence would be here, but in our driver the cdclk code
* paths should already be setting the appropriate voltage, hence we do
* nothing here.
*/

icl_pll_enable(dev_priv, pll, enable_reg);

/* DVFS post sequence would be here. See the comment above. */
4091}

4093static void tbt_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	   struct intel_shared_dpll *pll)
4095{
icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE((const i915_reg_t){ .reg = (0x46020) }));

icl_dpll_write(dev_priv, pll);

/*
* DVFS pre sequence would be here, but in our driver the cdclk code
* paths should already be setting the appropriate voltage, hence we do
* nothing here.
*/

icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE((const i915_reg_t){ .reg = (0x46020) }));

/* DVFS post sequence would be here. See the comment above. */
4109}

4111static void mg_pll_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
	  struct intel_shared_dpll *pll)
4113{
i915_reg_t enable_reg =
MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id))((const i915_reg_t){ .reg = (((0x46030) + ((icl_pll_id_to_tc_port
(pll->info->id))) * ((0x46034) - (0x46030)))) });

icl_pll_power_enable(dev_priv, pll, enable_reg);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12)
dkl_pll_write(dev_priv, pll);
else
icl_mg_pll_write(dev_priv, pll);

/*
* DVFS pre sequence would be here, but in our driver the cdclk code
* paths should already be setting the appropriate voltage, hence we do
* nothing here.
*/

icl_pll_enable(dev_priv, pll, enable_reg);

/* DVFS post sequence would be here. See the comment above. */
4133}

4135static void icl_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
	    struct intel_shared_dpll *pll,
	    i915_reg_t enable_reg)
4138{
u32 val;

/* The first steps are done by intel_ddi_post_disable(). */

/*
* DVFS pre sequence would be here, but in our driver the cdclk code
* paths should already be setting the appropriate voltage, hence we do
* nothign here.
*/

val = intel_de_read(dev_priv, enable_reg);
val &= ~PLL_ENABLE(1 << 31);
intel_de_write(dev_priv, enable_reg, val);

/* Timeout is actually 1us. */
if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK(1 << 30), 1))
drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d locked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id);

/* DVFS post sequence would be here. See the comment above. */

val = intel_de_read(dev_priv, enable_reg);
val &= ~PLL_POWER_ENABLE(1 << 27);
intel_de_write(dev_priv, enable_reg, val);

/*
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE(1 << 26), 1))
drm_err(&dev_priv->drm, "PLL %d Power not disabled\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not disabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id)
	pll->info->id)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d Power not disabled\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , pll->
info->id);
4170}

4172static void combo_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
	      struct intel_shared_dpll *pll)
4174{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);

icl_pll_disable(dev_priv, pll, enable_reg);

if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) &&
   pll->info->id == DPLL_ID_EHL_DPLL4)
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
			pll->wakeref);
4183}

4185static void tbt_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
	    struct intel_shared_dpll *pll)
4187{
icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE((const i915_reg_t){ .reg = (0x46020) }));
4189}

4191static void mg_pll_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
	   struct intel_shared_dpll *pll)
4193{
i915_reg_t enable_reg =
MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id))((const i915_reg_t){ .reg = (((0x46030) + ((icl_pll_id_to_tc_port
(pll->info->id))) * ((0x46034) - (0x46030)))) });

icl_pll_disable(dev_priv, pll, enable_reg);
4198}

4200static void icl_update_dpll_ref_clks(struct drm_i915_privateinteldrm_softc *i915)
4201{
/* No SSC ref */
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
4204}

4206static void icl_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
4208{
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->cfgcr0, hw_state->cfgcr1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_refclkin_ctl,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_clktop2_coreclkctl1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_clktop2_hsclkctl,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_div0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_div1,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_lf,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_frac_lock,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_ssc,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_bias,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
)
    hw_state->mg_pll_tdc_coldst_bias)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", hw_state
->cfgcr0, hw_state->cfgcr1, hw_state->mg_refclkin_ctl
, hw_state->mg_clktop2_coreclkctl1, hw_state->mg_clktop2_hsclkctl
, hw_state->mg_pll_div0, hw_state->mg_pll_div1, hw_state
->mg_pll_lf, hw_state->mg_pll_frac_lock, hw_state->mg_pll_ssc
, hw_state->mg_pll_bias, hw_state->mg_pll_tdc_coldst_bias
);
4227}

4229static const struct intel_shared_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
4234};

4236static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
.disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
4241};

4243static const struct intel_shared_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
4248};

4250static const struct dpll_info icl_plls[] = {
{ "DPLL 0",   &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
{ "DPLL 1",   &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
{ "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
{ "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
{ "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
{ "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
{ },
4259};

4261static const struct intel_dpll_mgr icl_pll_mgr = {
.dpll_info = icl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
4268};

4270static const struct dpll_info ehl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
{ },
4275};

4277static const struct intel_dpll_mgr ehl_pll_mgr = {
.dpll_info = ehl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
4283};

4285static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
4290};

4292static const struct dpll_info tgl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
{ "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
{ "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
{ "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
{ "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
{ "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
{ "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
{ },
4303};

4305static const struct intel_dpll_mgr tgl_pll_mgr = {
.dpll_info = tgl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_active_dpll = icl_update_active_dpll,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
4312};

4314static const struct dpll_info rkl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
{ },
4319};

4321static const struct intel_dpll_mgr rkl_pll_mgr = {
.dpll_info = rkl_plls,
.get_dplls = icl_get_dplls,
.put_dplls = icl_put_dplls,
.update_ref_clks = icl_update_dpll_ref_clks,
.dump_hw_state = icl_dump_hw_state,
4327};

4329/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
*
* Initialize shared DPLLs for @dev.
*/
4335void intel_shared_dpll_init(struct drm_device *dev)
4336{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
const struct intel_dpll_mgr *dpll_mgr = NULL((void *)0);
const struct dpll_info *dpll_info;
int i;

if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE))
dpll_mgr = &rkl_pll_mgr;
else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
dpll_mgr = &ehl_pll_mgr;
else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE))
dpll_mgr = &cnl_pll_mgr;
else if (IS_GEN9_BC(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) &&
 !((&(dev_priv)->__info)->is_lp)))
dpll_mgr = &skl_pll_mgr;
else if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) &&
 ((&(dev_priv)->__info)->is_lp)))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi))
dpll_mgr = &hsw_pll_mgr;
else if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) || HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT))
dpll_mgr = &pch_pll_mgr;

if (!dpll_mgr) {
dev_priv->dpll.num_shared_dpll = 0;
return;
}

dpll_info = dpll_mgr->dpll_info;

for (i = 0; dpll_info[i].name; i++) {
drm_WARN_ON(dev, i != dpll_info[i].id)({ int __ret = !!((i != dpll_info[i].id)); if (__ret) printf(
"%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON("
 "i != dpll_info[i].id" ")"); __builtin_expect(!!(__ret), 0);
 });
dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
}

dev_priv->dpll.mgr = dpll_mgr;
dev_priv->dpll.num_shared_dpll = i;
rw_init(&dev_priv->dpll.lock, "dplllk")_rw_init_flags(&dev_priv->dpll.lock, "dplllk", 0, ((void
 *)0));

BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS)((!(dev_priv->dpll.num_shared_dpll > 9)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c"
, 4377, "!(dev_priv->dpll.num_shared_dpll > 9)"));
4378}

4380/**
* intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
*
* This function reserves all required DPLLs for the given CRTC and encoder
* combination in the current atomic commit @state and the new @crtc atomic
* state.
*
* The new configuration in the atomic commit @state is made effective by
* calling intel_shared_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
* intel_release_shared_dplls().
*
* Returns:
* True if all required DPLLs were successfully reserved.
*/
4399bool_Bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
		struct intel_crtc *crtc,
		struct intel_encoder *encoder)
4402{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev);
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;

if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)({ int __ret = !!((!dpll_mgr)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "!dpll_mgr" ")"); __builtin_expect(!!(__ret), 0); }))
return false0;

return dpll_mgr->get_dplls(state, crtc, encoder);
4410}

4412/**
* intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
* This function releases all DPLLs reserved by intel_reserve_shared_dplls()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
* calling intel_shared_dpll_swap_state().
*/
4423void intel_release_shared_dplls(struct intel_atomic_state *state,
		struct intel_crtc *crtc)
4425{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev);
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;

/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
* the shared DPLL framework and intel_reserve_shared_dplls() is not
* called on those.
*/
if (!dpll_mgr)
return;

dpll_mgr->put_dplls(state, crtc);
4439}

4441/**
* intel_update_active_dpll - update the active DPLL for a CRTC/encoder
* @state: atomic state
* @crtc: the CRTC for which to update the active DPLL
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
* from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
4451void intel_update_active_dpll(struct intel_atomic_state *state,
	      struct intel_crtc *crtc,
	      struct intel_encoder *encoder)
4454{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;

if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)({ int __ret = !!((!dpll_mgr)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "!dpll_mgr" ")"); __builtin_expect(!!(__ret), 0); }))
return;

dpll_mgr->update_active_dpll(state, crtc, encoder);
4462}

4464/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
* @i915: i915 device
* @pll: DPLL for which to calculate the output frequency
*
* Return the output frequency corresponding to @pll's current state.
*/
4471int intel_dpll_get_freq(struct drm_i915_privateinteldrm_softc *i915,
	const struct intel_shared_dpll *pll)
4473{
if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)({ int __ret = !!((!pll->info->funcs->get_freq)); if
 (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915
->drm))->dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_freq"
 ")"); __builtin_expect(!!(__ret), 0); }))
return 0;

return pll->info->funcs->get_freq(i915, pll);
4478}

4480static void readout_dpll_hw_state(struct drm_i915_privateinteldrm_softc *i915,
		  struct intel_shared_dpll *pll)
4482{
struct intel_crtc *crtc;

pll->on = pll->info->funcs->get_hw_state(i915, pll,
				 &pll->state.hw_state);

if (IS_ELKHARTLAKE(i915)IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && pll->on &&
   pll->info->id == DPLL_ID_EHL_DPLL4) {
pll->wakeref = intel_display_power_get(i915,
				       POWER_DOMAIN_DPLL_DC_OFF);
}

pll->state.crtc_mask = 0;
for_each_intel_crtc(&i915->drm, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base
.head ) *__mptr = ((&(&i915->drm)->mode_config.
crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*crtc), base.head) );}); &crtc->base.head !=
 (&(&i915->drm)->mode_config.crtc_list); crtc =
 ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) *__mptr
 = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*crtc), base.head) );})) {
struct intel_crtc_state *crtc_state =
	to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *
__mptr = (crtc->base.state); (struct intel_crtc_state *)( (
char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi
) );});

if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
	pll->state.crtc_mask |= 1 << crtc->pipe;
}
pll->active_mask = pll->state.crtc_mask;

drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s hw state readout: crtc_mask 0x%08x, on %i\n"
, pll->info->name, pll->state.crtc_mask, pll->on)
    "%s hw state readout: crtc_mask 0x%08x, on %i\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s hw state readout: crtc_mask 0x%08x, on %i\n"
, pll->info->name, pll->state.crtc_mask, pll->on)
    pll->info->name, pll->state.crtc_mask, pll->on)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s hw state readout: crtc_mask 0x%08x, on %i\n"
, pll->info->name, pll->state.crtc_mask, pll->on);
4507}

4509void intel_dpll_readout_hw_state(struct drm_i915_privateinteldrm_softc *i915)
4510{
int i;

if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
i915->dpll.mgr->update_ref_clks(i915);

for (i = 0; i < i915->dpll.num_shared_dpll; i++)
readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
4518}

4520static void sanitize_dpll_state(struct drm_i915_privateinteldrm_softc *i915,
		struct intel_shared_dpll *pll)
4522{
if (!pll->on || pll->active_mask)
return;

drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s enabled but not in use, disabling\n"
, pll->info->name)
    "%s enabled but not in use, disabling\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s enabled but not in use, disabling\n"
, pll->info->name)
    pll->info->name)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s enabled but not in use, disabling\n"
, pll->info->name);

pll->info->funcs->disable(i915, pll);
pll->on = false0;
4532}

4534void intel_dpll_sanitize_state(struct drm_i915_privateinteldrm_softc *i915)
4535{
int i;

for (i = 0; i < i915->dpll.num_shared_dpll; i++)
sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
4540}

4542/**
* intel_shared_dpll_dump_hw_state - write hw_state to dmesg
* @dev_priv: i915 drm device
* @hw_state: hw state to be written to the log
*
* Write the relevant values in @hw_state to dmesg using drm_dbg_kms.
*/
4549void intel_dpll_dump_hw_state(struct drm_i915_privateinteldrm_softc *dev_priv,
	      const struct intel_dpll_hw_state *hw_state)
4551{
if (dev_priv->dpll.mgr) {
dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
 * infrastructure
 */
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    "fp0: 0x%x, fp1: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    hw_state->dpll,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    hw_state->dpll_md,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    hw_state->fp0,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1)
	    hw_state->fp1)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, hw_state->dpll_md
, hw_state->fp0, hw_state->fp1);
}
4566}