File: | dev/pci/drm/radeon/radeon_i2c.c |
Warning: | line 1190, column 3 4th function call argument is an uninitialized value |
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1 | /* | |||
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |||
3 | * Copyright 2008 Red Hat Inc. | |||
4 | * | |||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
6 | * copy of this software and associated documentation files (the "Software"), | |||
7 | * to deal in the Software without restriction, including without limitation | |||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
9 | * and/or sell copies of the Software, and to permit persons to whom the | |||
10 | * Software is furnished to do so, subject to the following conditions: | |||
11 | * | |||
12 | * The above copyright notice and this permission notice shall be included in | |||
13 | * all copies or substantial portions of the Software. | |||
14 | * | |||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
21 | * OTHER DEALINGS IN THE SOFTWARE. | |||
22 | * | |||
23 | * Authors: Dave Airlie | |||
24 | * Alex Deucher | |||
25 | */ | |||
26 | ||||
27 | #include <linux/export.h> | |||
28 | #include <linux/pci.h> | |||
29 | ||||
30 | #include <drm/drm_device.h> | |||
31 | #include <drm/drm_edid.h> | |||
32 | #include <drm/radeon_drm.h> | |||
33 | ||||
34 | #include "radeon.h" | |||
35 | #include "atom.h" | |||
36 | ||||
37 | #include <dev/i2c/i2cvar.h> | |||
38 | #include <dev/i2c/i2c_bitbang.h> | |||
39 | ||||
40 | extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |||
41 | struct i2c_msg *msgs, int num); | |||
42 | extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); | |||
43 | ||||
44 | /** | |||
45 | * radeon_ddc_probe | |||
46 | * | |||
47 | */ | |||
48 | bool_Bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool_Bool use_aux) | |||
49 | { | |||
50 | u8 out = 0x0; | |||
51 | u8 buf[8]; | |||
52 | int ret; | |||
53 | struct i2c_msg msgs[] = { | |||
54 | { | |||
55 | .addr = DDC_ADDR0x50, | |||
56 | .flags = 0, | |||
57 | .len = 1, | |||
58 | .buf = &out, | |||
59 | }, | |||
60 | { | |||
61 | .addr = DDC_ADDR0x50, | |||
62 | .flags = I2C_M_RD0x0001, | |||
63 | .len = 8, | |||
64 | .buf = buf, | |||
65 | } | |||
66 | }; | |||
67 | ||||
68 | /* on hw with routers, select right port */ | |||
69 | if (radeon_connector->router.ddc_valid) | |||
70 | radeon_router_select_ddc_port(radeon_connector); | |||
71 | ||||
72 | if (use_aux) { | |||
73 | ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); | |||
74 | } else { | |||
75 | ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); | |||
76 | } | |||
77 | ||||
78 | if (ret != 2) | |||
79 | /* Couldn't find an accessible DDC on this connector */ | |||
80 | return false0; | |||
81 | /* Probe also for valid EDID header | |||
82 | * EDID header starts with: | |||
83 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |||
84 | * Only the first 6 bytes must be valid as | |||
85 | * drm_edid_block_valid() can fix the last 2 bytes */ | |||
86 | if (drm_edid_header_is_valid(buf) < 6) { | |||
87 | /* Couldn't find an accessible EDID on this | |||
88 | * connector */ | |||
89 | return false0; | |||
90 | } | |||
91 | return true1; | |||
92 | } | |||
93 | ||||
94 | /* bit banging i2c */ | |||
95 | ||||
96 | static int pre_xfer(struct i2c_adapter *i2c_adap) | |||
97 | { | |||
98 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
99 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
100 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
101 | uint32_t temp; | |||
102 | ||||
103 | mutex_lock(&i2c->mutex)rw_enter_write(&i2c->mutex); | |||
104 | ||||
105 | /* RV410 appears to have a bug where the hw i2c in reset | |||
106 | * holds the i2c port in a bad state - switch hw i2c away before | |||
107 | * doing DDC - do this for all r200s/r300s/r400s for safety sake | |||
108 | */ | |||
109 | if (rec->hw_capable) { | |||
110 | if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) { | |||
111 | u32 reg; | |||
112 | ||||
113 | if (rdev->family >= CHIP_RV350) | |||
114 | reg = RADEON_GPIO_MONID0x0068; | |||
115 | else if ((rdev->family == CHIP_R300) || | |||
116 | (rdev->family == CHIP_R350)) | |||
117 | reg = RADEON_GPIO_DVI_DDC0x0064; | |||
118 | else | |||
119 | reg = RADEON_GPIO_CRT2_DDC0x006c; | |||
120 | ||||
121 | mutex_lock(&rdev->dc_hw_i2c_mutex)rw_enter_write(&rdev->dc_hw_i2c_mutex); | |||
122 | if (rec->a_clk_reg == reg) { | |||
123 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |r100_mm_wreg(rdev, (0x02e0), (((1 << 5) | ((0) << 3))), 0) | |||
124 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)))r100_mm_wreg(rdev, (0x02e0), (((1 << 5) | ((0) << 3))), 0); | |||
125 | } else { | |||
126 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |r100_mm_wreg(rdev, (0x02e0), (((1 << 5) | ((2) << 3))), 0) | |||
127 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)))r100_mm_wreg(rdev, (0x02e0), (((1 << 5) | ((2) << 3))), 0); | |||
128 | } | |||
129 | mutex_unlock(&rdev->dc_hw_i2c_mutex)rw_exit_write(&rdev->dc_hw_i2c_mutex); | |||
130 | } | |||
131 | } | |||
132 | ||||
133 | /* switch the pads to ddc mode */ | |||
134 | if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620)) && rec->hw_capable) { | |||
135 | temp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0); | |||
136 | temp &= ~(1 << 16); | |||
137 | WREG32(rec->mask_clk_reg, temp)r100_mm_wreg(rdev, (rec->mask_clk_reg), (temp), 0); | |||
138 | } | |||
139 | ||||
140 | /* clear the output pin values */ | |||
141 | temp = RREG32(rec->a_clk_reg)r100_mm_rreg(rdev, (rec->a_clk_reg), 0) & ~rec->a_clk_mask; | |||
142 | WREG32(rec->a_clk_reg, temp)r100_mm_wreg(rdev, (rec->a_clk_reg), (temp), 0); | |||
143 | ||||
144 | temp = RREG32(rec->a_data_reg)r100_mm_rreg(rdev, (rec->a_data_reg), 0) & ~rec->a_data_mask; | |||
145 | WREG32(rec->a_data_reg, temp)r100_mm_wreg(rdev, (rec->a_data_reg), (temp), 0); | |||
146 | ||||
147 | /* set the pins to input */ | |||
148 | temp = RREG32(rec->en_clk_reg)r100_mm_rreg(rdev, (rec->en_clk_reg), 0) & ~rec->en_clk_mask; | |||
149 | WREG32(rec->en_clk_reg, temp)r100_mm_wreg(rdev, (rec->en_clk_reg), (temp), 0); | |||
150 | ||||
151 | temp = RREG32(rec->en_data_reg)r100_mm_rreg(rdev, (rec->en_data_reg), 0) & ~rec->en_data_mask; | |||
152 | WREG32(rec->en_data_reg, temp)r100_mm_wreg(rdev, (rec->en_data_reg), (temp), 0); | |||
153 | ||||
154 | /* mask the gpio pins for software use */ | |||
155 | temp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0) | rec->mask_clk_mask; | |||
156 | WREG32(rec->mask_clk_reg, temp)r100_mm_wreg(rdev, (rec->mask_clk_reg), (temp), 0); | |||
157 | temp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0); | |||
158 | ||||
159 | temp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0) | rec->mask_data_mask; | |||
160 | WREG32(rec->mask_data_reg, temp)r100_mm_wreg(rdev, (rec->mask_data_reg), (temp), 0); | |||
161 | temp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0); | |||
162 | ||||
163 | return 0; | |||
164 | } | |||
165 | ||||
166 | static void post_xfer(struct i2c_adapter *i2c_adap) | |||
167 | { | |||
168 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
169 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
170 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
171 | uint32_t temp; | |||
172 | ||||
173 | /* unmask the gpio pins for software use */ | |||
174 | temp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0) & ~rec->mask_clk_mask; | |||
175 | WREG32(rec->mask_clk_reg, temp)r100_mm_wreg(rdev, (rec->mask_clk_reg), (temp), 0); | |||
176 | temp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0); | |||
177 | ||||
178 | temp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0) & ~rec->mask_data_mask; | |||
179 | WREG32(rec->mask_data_reg, temp)r100_mm_wreg(rdev, (rec->mask_data_reg), (temp), 0); | |||
180 | temp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0); | |||
181 | ||||
182 | mutex_unlock(&i2c->mutex)rw_exit_write(&i2c->mutex); | |||
183 | } | |||
184 | ||||
185 | static int get_clock(void *i2c_priv) | |||
186 | { | |||
187 | struct radeon_i2c_chan *i2c = i2c_priv; | |||
188 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
189 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
190 | uint32_t val; | |||
191 | ||||
192 | /* read the value off the pin */ | |||
193 | val = RREG32(rec->y_clk_reg)r100_mm_rreg(rdev, (rec->y_clk_reg), 0); | |||
194 | val &= rec->y_clk_mask; | |||
195 | ||||
196 | return (val != 0); | |||
197 | } | |||
198 | ||||
199 | ||||
200 | static int get_data(void *i2c_priv) | |||
201 | { | |||
202 | struct radeon_i2c_chan *i2c = i2c_priv; | |||
203 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
204 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
205 | uint32_t val; | |||
206 | ||||
207 | /* read the value off the pin */ | |||
208 | val = RREG32(rec->y_data_reg)r100_mm_rreg(rdev, (rec->y_data_reg), 0); | |||
209 | val &= rec->y_data_mask; | |||
210 | ||||
211 | return (val != 0); | |||
212 | } | |||
213 | ||||
214 | static void set_clock(void *i2c_priv, int clock) | |||
215 | { | |||
216 | struct radeon_i2c_chan *i2c = i2c_priv; | |||
217 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
218 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
219 | uint32_t val; | |||
220 | ||||
221 | /* set pin direction */ | |||
222 | val = RREG32(rec->en_clk_reg)r100_mm_rreg(rdev, (rec->en_clk_reg), 0) & ~rec->en_clk_mask; | |||
223 | val |= clock ? 0 : rec->en_clk_mask; | |||
224 | WREG32(rec->en_clk_reg, val)r100_mm_wreg(rdev, (rec->en_clk_reg), (val), 0); | |||
225 | } | |||
226 | ||||
227 | static void set_data(void *i2c_priv, int data) | |||
228 | { | |||
229 | struct radeon_i2c_chan *i2c = i2c_priv; | |||
230 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
231 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
232 | uint32_t val; | |||
233 | ||||
234 | /* set pin direction */ | |||
235 | val = RREG32(rec->en_data_reg)r100_mm_rreg(rdev, (rec->en_data_reg), 0) & ~rec->en_data_mask; | |||
236 | val |= data ? 0 : rec->en_data_mask; | |||
237 | WREG32(rec->en_data_reg, val)r100_mm_wreg(rdev, (rec->en_data_reg), (val), 0); | |||
238 | } | |||
239 | ||||
240 | #ifdef __OpenBSD__1 | |||
241 | ||||
242 | void radeon_bb_set_bits(void *, uint32_t); | |||
243 | void radeon_bb_set_dir(void *, uint32_t); | |||
244 | uint32_t radeon_bb_read_bits(void *); | |||
245 | ||||
246 | int radeon_acquire_bus(void *, int); | |||
247 | void radeon_release_bus(void *, int); | |||
248 | int radeon_send_start(void *, int); | |||
249 | int radeon_send_stop(void *, int); | |||
250 | int radeon_initiate_xfer(void *, i2c_addr_t, int); | |||
251 | int radeon_read_byte(void *, u_int8_t *, int); | |||
252 | int radeon_write_byte(void *, u_int8_t, int); | |||
253 | ||||
254 | #define RADEON_BB_SDA(1 << 0) (1 << I2C_BIT_SDA0) | |||
255 | #define RADEON_BB_SCL(1 << 1) (1 << I2C_BIT_SCL1) | |||
256 | ||||
257 | struct i2c_bitbang_ops radeon_bbops = { | |||
258 | radeon_bb_set_bits, | |||
259 | radeon_bb_set_dir, | |||
260 | radeon_bb_read_bits, | |||
261 | { RADEON_BB_SDA(1 << 0), RADEON_BB_SCL(1 << 1), 0, 0 } | |||
262 | }; | |||
263 | ||||
264 | void | |||
265 | radeon_bb_set_bits(void *cookie, uint32_t bits) | |||
266 | { | |||
267 | set_clock(cookie, bits & RADEON_BB_SCL(1 << 1)); | |||
268 | set_data(cookie, bits & RADEON_BB_SDA(1 << 0)); | |||
269 | } | |||
270 | ||||
271 | void | |||
272 | radeon_bb_set_dir(void *cookie, uint32_t bits) | |||
273 | { | |||
274 | } | |||
275 | ||||
276 | uint32_t | |||
277 | radeon_bb_read_bits(void *cookie) | |||
278 | { | |||
279 | uint32_t bits = 0; | |||
280 | ||||
281 | if (get_clock(cookie)) | |||
282 | bits |= RADEON_BB_SCL(1 << 1); | |||
283 | if (get_data(cookie)) | |||
284 | bits |= RADEON_BB_SDA(1 << 0); | |||
285 | ||||
286 | return bits; | |||
287 | } | |||
288 | ||||
289 | int | |||
290 | radeon_acquire_bus(void *cookie, int flags) | |||
291 | { | |||
292 | struct radeon_i2c_chan *i2c = cookie; | |||
293 | pre_xfer(&i2c->adapter); | |||
294 | return (0); | |||
295 | } | |||
296 | ||||
297 | void | |||
298 | radeon_release_bus(void *cookie, int flags) | |||
299 | { | |||
300 | struct radeon_i2c_chan *i2c = cookie; | |||
301 | post_xfer(&i2c->adapter); | |||
302 | } | |||
303 | ||||
304 | int | |||
305 | radeon_send_start(void *cookie, int flags) | |||
306 | { | |||
307 | return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); | |||
308 | } | |||
309 | ||||
310 | int | |||
311 | radeon_send_stop(void *cookie, int flags) | |||
312 | { | |||
313 | return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); | |||
314 | } | |||
315 | ||||
316 | int | |||
317 | radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) | |||
318 | { | |||
319 | return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); | |||
320 | } | |||
321 | ||||
322 | int | |||
323 | radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) | |||
324 | { | |||
325 | return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); | |||
326 | } | |||
327 | ||||
328 | int | |||
329 | radeon_write_byte(void *cookie, u_int8_t byte, int flags) | |||
330 | { | |||
331 | return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); | |||
332 | } | |||
333 | ||||
334 | #endif /* __OpenBSD__ */ | |||
335 | ||||
336 | /* hw i2c */ | |||
337 | ||||
338 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) | |||
339 | { | |||
340 | u32 sclk = rdev->pm.current_sclk; | |||
341 | u32 prescale = 0; | |||
342 | u32 nm; | |||
343 | u8 n, m, loop; | |||
344 | int i2c_clock; | |||
345 | ||||
346 | switch (rdev->family) { | |||
347 | case CHIP_R100: | |||
348 | case CHIP_RV100: | |||
349 | case CHIP_RS100: | |||
350 | case CHIP_RV200: | |||
351 | case CHIP_RS200: | |||
352 | case CHIP_R200: | |||
353 | case CHIP_RV250: | |||
354 | case CHIP_RS300: | |||
355 | case CHIP_RV280: | |||
356 | case CHIP_R300: | |||
357 | case CHIP_R350: | |||
358 | case CHIP_RV350: | |||
359 | i2c_clock = 60; | |||
360 | nm = (sclk * 10) / (i2c_clock * 4); | |||
361 | for (loop = 1; loop < 255; loop++) { | |||
362 | if ((nm / loop) < loop) | |||
363 | break; | |||
364 | } | |||
365 | n = loop - 1; | |||
366 | m = loop - 2; | |||
367 | prescale = m | (n << 8); | |||
368 | break; | |||
369 | case CHIP_RV380: | |||
370 | case CHIP_RS400: | |||
371 | case CHIP_RS480: | |||
372 | case CHIP_R420: | |||
373 | case CHIP_R423: | |||
374 | case CHIP_RV410: | |||
375 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; | |||
376 | break; | |||
377 | case CHIP_RS600: | |||
378 | case CHIP_RS690: | |||
379 | case CHIP_RS740: | |||
380 | /* todo */ | |||
381 | break; | |||
382 | case CHIP_RV515: | |||
383 | case CHIP_R520: | |||
384 | case CHIP_RV530: | |||
385 | case CHIP_RV560: | |||
386 | case CHIP_RV570: | |||
387 | case CHIP_R580: | |||
388 | i2c_clock = 50; | |||
389 | if (rdev->family == CHIP_R520) | |||
390 | prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); | |||
391 | else | |||
392 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; | |||
393 | break; | |||
394 | case CHIP_R600: | |||
395 | case CHIP_RV610: | |||
396 | case CHIP_RV630: | |||
397 | case CHIP_RV670: | |||
398 | /* todo */ | |||
399 | break; | |||
400 | case CHIP_RV620: | |||
401 | case CHIP_RV635: | |||
402 | case CHIP_RS780: | |||
403 | case CHIP_RS880: | |||
404 | case CHIP_RV770: | |||
405 | case CHIP_RV730: | |||
406 | case CHIP_RV710: | |||
407 | case CHIP_RV740: | |||
408 | /* todo */ | |||
409 | break; | |||
410 | case CHIP_CEDAR: | |||
411 | case CHIP_REDWOOD: | |||
412 | case CHIP_JUNIPER: | |||
413 | case CHIP_CYPRESS: | |||
414 | case CHIP_HEMLOCK: | |||
415 | /* todo */ | |||
416 | break; | |||
417 | default: | |||
418 | DRM_ERROR("i2c: unhandled radeon chip\n")__drm_err("i2c: unhandled radeon chip\n"); | |||
419 | break; | |||
420 | } | |||
421 | return prescale; | |||
422 | } | |||
423 | ||||
424 | ||||
425 | /* hw i2c engine for r1xx-4xx hardware | |||
426 | * hw can buffer up to 15 bytes | |||
427 | */ | |||
428 | static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |||
429 | struct i2c_msg *msgs, int num) | |||
430 | { | |||
431 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
432 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
433 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
434 | struct i2c_msg *p; | |||
435 | int i, j, k, ret = num; | |||
436 | u32 prescale; | |||
437 | u32 i2c_cntl_0, i2c_cntl_1, i2c_data; | |||
438 | u32 tmp, reg; | |||
439 | ||||
440 | mutex_lock(&rdev->dc_hw_i2c_mutex)rw_enter_write(&rdev->dc_hw_i2c_mutex); | |||
441 | /* take the pm lock since we need a constant sclk */ | |||
442 | mutex_lock(&rdev->pm.mutex)rw_enter_write(&rdev->pm.mutex); | |||
443 | ||||
444 | prescale = radeon_get_i2c_prescale(rdev); | |||
445 | ||||
446 | reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT16) | | |||
447 | RADEON_I2C_DRIVE_EN(1 << 6) | | |||
448 | RADEON_I2C_START(1 << 8) | | |||
449 | RADEON_I2C_STOP(1 << 9) | | |||
450 | RADEON_I2C_GO(1 << 12)); | |||
451 | ||||
452 | if (rdev->is_atom_bios) { | |||
453 | tmp = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); | |||
454 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE)r100_mm_wreg(rdev, (0x0028), (tmp | 0x00000200L), 0); | |||
455 | } | |||
456 | ||||
457 | if (rec->mm_i2c) { | |||
458 | i2c_cntl_0 = RADEON_I2C_CNTL_00x0090; | |||
459 | i2c_cntl_1 = RADEON_I2C_CNTL_10x0094; | |||
460 | i2c_data = RADEON_I2C_DATA0x0098; | |||
461 | } else { | |||
462 | i2c_cntl_0 = RADEON_DVI_I2C_CNTL_00x02e0; | |||
463 | i2c_cntl_1 = RADEON_DVI_I2C_CNTL_10x02e4; | |||
464 | i2c_data = RADEON_DVI_I2C_DATA0x02e8; | |||
465 | ||||
466 | switch (rdev->family) { | |||
467 | case CHIP_R100: | |||
468 | case CHIP_RV100: | |||
469 | case CHIP_RS100: | |||
470 | case CHIP_RV200: | |||
471 | case CHIP_RS200: | |||
472 | case CHIP_RS300: | |||
473 | switch (rec->mask_clk_reg) { | |||
474 | case RADEON_GPIO_DVI_DDC0x0064: | |||
475 | /* no gpio select bit */ | |||
476 | break; | |||
477 | default: | |||
478 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
479 | ret = -EINVAL22; | |||
480 | goto done; | |||
481 | } | |||
482 | break; | |||
483 | case CHIP_R200: | |||
484 | /* only bit 4 on r200 */ | |||
485 | switch (rec->mask_clk_reg) { | |||
486 | case RADEON_GPIO_DVI_DDC0x0064: | |||
487 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)((0) << 3); | |||
488 | break; | |||
489 | case RADEON_GPIO_MONID0x0068: | |||
490 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)((2) << 3); | |||
491 | break; | |||
492 | default: | |||
493 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
494 | ret = -EINVAL22; | |||
495 | goto done; | |||
496 | } | |||
497 | break; | |||
498 | case CHIP_RV250: | |||
499 | case CHIP_RV280: | |||
500 | /* bits 3 and 4 */ | |||
501 | switch (rec->mask_clk_reg) { | |||
502 | case RADEON_GPIO_DVI_DDC0x0064: | |||
503 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)((0) << 3); | |||
504 | break; | |||
505 | case RADEON_GPIO_VGA_DDC0x0060: | |||
506 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2)((1) << 3); | |||
507 | break; | |||
508 | case RADEON_GPIO_CRT2_DDC0x006c: | |||
509 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)((2) << 3); | |||
510 | break; | |||
511 | default: | |||
512 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
513 | ret = -EINVAL22; | |||
514 | goto done; | |||
515 | } | |||
516 | break; | |||
517 | case CHIP_R300: | |||
518 | case CHIP_R350: | |||
519 | /* only bit 4 on r300/r350 */ | |||
520 | switch (rec->mask_clk_reg) { | |||
521 | case RADEON_GPIO_VGA_DDC0x0060: | |||
522 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)((0) << 3); | |||
523 | break; | |||
524 | case RADEON_GPIO_DVI_DDC0x0064: | |||
525 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)((2) << 3); | |||
526 | break; | |||
527 | default: | |||
528 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
529 | ret = -EINVAL22; | |||
530 | goto done; | |||
531 | } | |||
532 | break; | |||
533 | case CHIP_RV350: | |||
534 | case CHIP_RV380: | |||
535 | case CHIP_R420: | |||
536 | case CHIP_R423: | |||
537 | case CHIP_RV410: | |||
538 | case CHIP_RS400: | |||
539 | case CHIP_RS480: | |||
540 | /* bits 3 and 4 */ | |||
541 | switch (rec->mask_clk_reg) { | |||
542 | case RADEON_GPIO_VGA_DDC0x0060: | |||
543 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)((0) << 3); | |||
544 | break; | |||
545 | case RADEON_GPIO_DVI_DDC0x0064: | |||
546 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2)((1) << 3); | |||
547 | break; | |||
548 | case RADEON_GPIO_MONID0x0068: | |||
549 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)((2) << 3); | |||
550 | break; | |||
551 | default: | |||
552 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
553 | ret = -EINVAL22; | |||
554 | goto done; | |||
555 | } | |||
556 | break; | |||
557 | default: | |||
558 | DRM_ERROR("unsupported asic\n")__drm_err("unsupported asic\n"); | |||
559 | ret = -EINVAL22; | |||
560 | goto done; | |||
561 | break; | |||
562 | } | |||
563 | } | |||
564 | ||||
565 | /* check for bus probe */ | |||
566 | p = &msgs[0]; | |||
567 | if ((num == 1) && (p->len == 0)) { | |||
568 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
569 | RADEON_I2C_NACK |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
570 | RADEON_I2C_HALT |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
571 | RADEON_I2C_SOFT_RST))r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0); | |||
572 | WREG32(i2c_data, (p->addr << 1) & 0xff)r100_mm_wreg(rdev, (i2c_data), ((p->addr << 1) & 0xff), 0); | |||
573 | WREG32(i2c_data, 0)r100_mm_wreg(rdev, (i2c_data), (0), 0); | |||
574 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
575 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
576 | RADEON_I2C_EN |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
577 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT)))r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0); | |||
578 | WREG32(i2c_cntl_0, reg)r100_mm_wreg(rdev, (i2c_cntl_0), (reg), 0); | |||
579 | for (k = 0; k < 32; k++) { | |||
580 | udelay(10); | |||
581 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
582 | if (tmp & RADEON_I2C_GO(1 << 12)) | |||
583 | continue; | |||
584 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
585 | if (tmp & RADEON_I2C_DONE(1 << 0)) | |||
586 | break; | |||
587 | else { | |||
588 | DRM_DEBUG("i2c write error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c write error 0x%08x\n", tmp); | |||
589 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT)r100_mm_wreg(rdev, (i2c_cntl_0), (tmp | (1 << 11)), 0); | |||
590 | ret = -EIO5; | |||
591 | goto done; | |||
592 | } | |||
593 | } | |||
594 | goto done; | |||
595 | } | |||
596 | ||||
597 | for (i = 0; i < num; i++) { | |||
598 | p = &msgs[i]; | |||
599 | for (j = 0; j < p->len; j++) { | |||
600 | if (p->flags & I2C_M_RD0x0001) { | |||
601 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
602 | RADEON_I2C_NACK |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
603 | RADEON_I2C_HALT |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
604 | RADEON_I2C_SOFT_RST))r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0); | |||
605 | WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1)r100_mm_wreg(rdev, (i2c_data), (((p->addr << 1) & 0xff) | 0x1), 0); | |||
606 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
607 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
608 | RADEON_I2C_EN |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
609 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT)))r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0); | |||
610 | WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE)r100_mm_wreg(rdev, (i2c_cntl_0), (reg | (1 << 10)), 0); | |||
611 | for (k = 0; k < 32; k++) { | |||
612 | udelay(10); | |||
613 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
614 | if (tmp & RADEON_I2C_GO(1 << 12)) | |||
615 | continue; | |||
616 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
617 | if (tmp & RADEON_I2C_DONE(1 << 0)) | |||
618 | break; | |||
619 | else { | |||
620 | DRM_DEBUG("i2c read error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c read error 0x%08x\n", tmp); | |||
621 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT)r100_mm_wreg(rdev, (i2c_cntl_0), (tmp | (1 << 11)), 0); | |||
622 | ret = -EIO5; | |||
623 | goto done; | |||
624 | } | |||
625 | } | |||
626 | p->buf[j] = RREG32(i2c_data)r100_mm_rreg(rdev, (i2c_data), 0) & 0xff; | |||
627 | } else { | |||
628 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
629 | RADEON_I2C_NACK |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
630 | RADEON_I2C_HALT |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
631 | RADEON_I2C_SOFT_RST))r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0); | |||
632 | WREG32(i2c_data, (p->addr << 1) & 0xff)r100_mm_wreg(rdev, (i2c_data), ((p->addr << 1) & 0xff), 0); | |||
633 | WREG32(i2c_data, p->buf[j])r100_mm_wreg(rdev, (i2c_data), (p->buf[j]), 0); | |||
634 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
635 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
636 | RADEON_I2C_EN |r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0) | |||
637 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT)))r100_mm_wreg(rdev, (i2c_cntl_1), (((1 << 0) | (1 << 4) | (1 << 17) | (48 << 24))), 0); | |||
638 | WREG32(i2c_cntl_0, reg)r100_mm_wreg(rdev, (i2c_cntl_0), (reg), 0); | |||
639 | for (k = 0; k < 32; k++) { | |||
640 | udelay(10); | |||
641 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
642 | if (tmp & RADEON_I2C_GO(1 << 12)) | |||
643 | continue; | |||
644 | tmp = RREG32(i2c_cntl_0)r100_mm_rreg(rdev, (i2c_cntl_0), 0); | |||
645 | if (tmp & RADEON_I2C_DONE(1 << 0)) | |||
646 | break; | |||
647 | else { | |||
648 | DRM_DEBUG("i2c write error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c write error 0x%08x\n", tmp); | |||
649 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT)r100_mm_wreg(rdev, (i2c_cntl_0), (tmp | (1 << 11)), 0); | |||
650 | ret = -EIO5; | |||
651 | goto done; | |||
652 | } | |||
653 | } | |||
654 | } | |||
655 | } | |||
656 | } | |||
657 | ||||
658 | done: | |||
659 | WREG32(i2c_cntl_0, 0)r100_mm_wreg(rdev, (i2c_cntl_0), (0), 0); | |||
660 | WREG32(i2c_cntl_1, 0)r100_mm_wreg(rdev, (i2c_cntl_1), (0), 0); | |||
661 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
662 | RADEON_I2C_NACK |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
663 | RADEON_I2C_HALT |r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0) | |||
664 | RADEON_I2C_SOFT_RST))r100_mm_wreg(rdev, (i2c_cntl_0), (((1 << 0) | (1 << 1) | (1 << 2) | (1 << 5))), 0); | |||
665 | ||||
666 | if (rdev->is_atom_bios) { | |||
667 | tmp = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); | |||
668 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE0x00000200L; | |||
669 | WREG32(RADEON_BIOS_6_SCRATCH, tmp)r100_mm_wreg(rdev, (0x0028), (tmp), 0); | |||
670 | } | |||
671 | ||||
672 | mutex_unlock(&rdev->pm.mutex)rw_exit_write(&rdev->pm.mutex); | |||
673 | mutex_unlock(&rdev->dc_hw_i2c_mutex)rw_exit_write(&rdev->dc_hw_i2c_mutex); | |||
674 | ||||
675 | return ret; | |||
676 | } | |||
677 | ||||
678 | /* hw i2c engine for r5xx hardware | |||
679 | * hw can buffer up to 15 bytes | |||
680 | */ | |||
681 | static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |||
682 | struct i2c_msg *msgs, int num) | |||
683 | { | |||
684 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
685 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
686 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
687 | struct i2c_msg *p; | |||
688 | int i, j, remaining, current_count, buffer_offset, ret = num; | |||
689 | u32 prescale; | |||
690 | u32 tmp, reg; | |||
691 | u32 saved1, saved2; | |||
692 | ||||
693 | mutex_lock(&rdev->dc_hw_i2c_mutex)rw_enter_write(&rdev->dc_hw_i2c_mutex); | |||
694 | /* take the pm lock since we need a constant sclk */ | |||
695 | mutex_lock(&rdev->pm.mutex)rw_enter_write(&rdev->pm.mutex); | |||
696 | ||||
697 | prescale = radeon_get_i2c_prescale(rdev); | |||
698 | ||||
699 | /* clear gpio mask bits */ | |||
700 | tmp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0); | |||
701 | tmp &= ~rec->mask_clk_mask; | |||
702 | WREG32(rec->mask_clk_reg, tmp)r100_mm_wreg(rdev, (rec->mask_clk_reg), (tmp), 0); | |||
703 | tmp = RREG32(rec->mask_clk_reg)r100_mm_rreg(rdev, (rec->mask_clk_reg), 0); | |||
704 | ||||
705 | tmp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0); | |||
706 | tmp &= ~rec->mask_data_mask; | |||
707 | WREG32(rec->mask_data_reg, tmp)r100_mm_wreg(rdev, (rec->mask_data_reg), (tmp), 0); | |||
708 | tmp = RREG32(rec->mask_data_reg)r100_mm_rreg(rdev, (rec->mask_data_reg), 0); | |||
709 | ||||
710 | /* clear pin values */ | |||
711 | tmp = RREG32(rec->a_clk_reg)r100_mm_rreg(rdev, (rec->a_clk_reg), 0); | |||
712 | tmp &= ~rec->a_clk_mask; | |||
713 | WREG32(rec->a_clk_reg, tmp)r100_mm_wreg(rdev, (rec->a_clk_reg), (tmp), 0); | |||
714 | tmp = RREG32(rec->a_clk_reg)r100_mm_rreg(rdev, (rec->a_clk_reg), 0); | |||
715 | ||||
716 | tmp = RREG32(rec->a_data_reg)r100_mm_rreg(rdev, (rec->a_data_reg), 0); | |||
717 | tmp &= ~rec->a_data_mask; | |||
718 | WREG32(rec->a_data_reg, tmp)r100_mm_wreg(rdev, (rec->a_data_reg), (tmp), 0); | |||
719 | tmp = RREG32(rec->a_data_reg)r100_mm_rreg(rdev, (rec->a_data_reg), 0); | |||
720 | ||||
721 | /* set the pins to input */ | |||
722 | tmp = RREG32(rec->en_clk_reg)r100_mm_rreg(rdev, (rec->en_clk_reg), 0); | |||
723 | tmp &= ~rec->en_clk_mask; | |||
724 | WREG32(rec->en_clk_reg, tmp)r100_mm_wreg(rdev, (rec->en_clk_reg), (tmp), 0); | |||
725 | tmp = RREG32(rec->en_clk_reg)r100_mm_rreg(rdev, (rec->en_clk_reg), 0); | |||
726 | ||||
727 | tmp = RREG32(rec->en_data_reg)r100_mm_rreg(rdev, (rec->en_data_reg), 0); | |||
728 | tmp &= ~rec->en_data_mask; | |||
729 | WREG32(rec->en_data_reg, tmp)r100_mm_wreg(rdev, (rec->en_data_reg), (tmp), 0); | |||
730 | tmp = RREG32(rec->en_data_reg)r100_mm_rreg(rdev, (rec->en_data_reg), 0); | |||
731 | ||||
732 | /* */ | |||
733 | tmp = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); | |||
734 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE)r100_mm_wreg(rdev, (0x0028), (tmp | 0x00000200L), 0); | |||
735 | saved1 = RREG32(AVIVO_DC_I2C_CONTROL1)r100_mm_rreg(rdev, (0x7d38), 0); | |||
736 | saved2 = RREG32(0x494)r100_mm_rreg(rdev, (0x494), 0); | |||
737 | WREG32(0x494, saved2 | 0x1)r100_mm_wreg(rdev, (0x494), (saved2 | 0x1), 0); | |||
738 | ||||
739 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C)r100_mm_wreg(rdev, (0x7d50), ((1 << 0)), 0); | |||
740 | for (i = 0; i < 50; i++) { | |||
741 | udelay(1); | |||
742 | if (RREG32(AVIVO_DC_I2C_ARBITRATION)r100_mm_rreg(rdev, (0x7d50), 0) & AVIVO_DC_I2C_SW_CAN_USE_I2C(1 << 1)) | |||
743 | break; | |||
744 | } | |||
745 | if (i == 50) { | |||
746 | DRM_ERROR("failed to get i2c bus\n")__drm_err("failed to get i2c bus\n"); | |||
747 | ret = -EBUSY16; | |||
748 | goto done; | |||
749 | } | |||
750 | ||||
751 | reg = AVIVO_DC_I2C_START(1 << 0) | AVIVO_DC_I2C_STOP(1 << 1) | AVIVO_DC_I2C_EN(1 << 8); | |||
752 | switch (rec->mask_clk_reg) { | |||
753 | case AVIVO_DC_GPIO_DDC1_MASK0x7e40: | |||
754 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1)((0) << 16); | |||
755 | break; | |||
756 | case AVIVO_DC_GPIO_DDC2_MASK0x7e50: | |||
757 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2)((1) << 16); | |||
758 | break; | |||
759 | case AVIVO_DC_GPIO_DDC3_MASK0x7e60: | |||
760 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3)((2) << 16); | |||
761 | break; | |||
762 | default: | |||
763 | DRM_ERROR("gpio not supported with hw i2c\n")__drm_err("gpio not supported with hw i2c\n"); | |||
764 | ret = -EINVAL22; | |||
765 | goto done; | |||
766 | } | |||
767 | ||||
768 | /* check for bus probe */ | |||
769 | p = &msgs[0]; | |||
770 | if ((num == 1) && (p->len == 0)) { | |||
771 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
772 | AVIVO_DC_I2C_NACK |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
773 | AVIVO_DC_I2C_HALT))r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0); | |||
774 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET)r100_mm_wreg(rdev, (0x7d34), ((1 << 0)), 0); | |||
775 | udelay(1); | |||
776 | WREG32(AVIVO_DC_I2C_RESET, 0)r100_mm_wreg(rdev, (0x7d34), (0), 0); | |||
777 | ||||
778 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff)r100_mm_wreg(rdev, (0x7d44), ((p->addr << 1) & 0xff ), 0); | |||
779 | WREG32(AVIVO_DC_I2C_DATA, 0)r100_mm_wreg(rdev, (0x7d44), (0), 0); | |||
780 | ||||
781 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48))r100_mm_wreg(rdev, (0x7d40), (((48) << 24)), 0); | |||
782 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((1) << 8) | (prescale << 16))), 0) | |||
783 | AVIVO_DC_I2C_DATA_COUNT(1) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((1) << 8) | (prescale << 16))), 0) | |||
784 | (prescale << 16)))r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((1) << 8) | (prescale << 16))), 0); | |||
785 | WREG32(AVIVO_DC_I2C_CONTROL1, reg)r100_mm_wreg(rdev, (0x7d38), (reg), 0); | |||
786 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO)r100_mm_wreg(rdev, (0x7d30), ((1 << 3)), 0); | |||
787 | for (j = 0; j < 200; j++) { | |||
788 | udelay(50); | |||
789 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
790 | if (tmp & AVIVO_DC_I2C_GO(1 << 3)) | |||
791 | continue; | |||
792 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
793 | if (tmp & AVIVO_DC_I2C_DONE(1 << 0)) | |||
794 | break; | |||
795 | else { | |||
796 | DRM_DEBUG("i2c write error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c write error 0x%08x\n", tmp); | |||
797 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT)r100_mm_wreg(rdev, (0x7d34), ((1 << 8)), 0); | |||
798 | ret = -EIO5; | |||
799 | goto done; | |||
800 | } | |||
801 | } | |||
802 | goto done; | |||
803 | } | |||
804 | ||||
805 | for (i = 0; i < num; i++) { | |||
806 | p = &msgs[i]; | |||
807 | remaining = p->len; | |||
808 | buffer_offset = 0; | |||
809 | if (p->flags & I2C_M_RD0x0001) { | |||
810 | while (remaining) { | |||
811 | if (remaining > 15) | |||
812 | current_count = 15; | |||
813 | else | |||
814 | current_count = remaining; | |||
815 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
816 | AVIVO_DC_I2C_NACK |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
817 | AVIVO_DC_I2C_HALT))r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0); | |||
818 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET)r100_mm_wreg(rdev, (0x7d34), ((1 << 0)), 0); | |||
819 | udelay(1); | |||
820 | WREG32(AVIVO_DC_I2C_RESET, 0)r100_mm_wreg(rdev, (0x7d34), (0), 0); | |||
821 | ||||
822 | WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1)r100_mm_wreg(rdev, (0x7d44), (((p->addr << 1) & 0xff ) | 0x1), 0); | |||
823 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48))r100_mm_wreg(rdev, (0x7d40), (((48) << 24)), 0); | |||
824 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0) | |||
825 | AVIVO_DC_I2C_DATA_COUNT(current_count) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0) | |||
826 | (prescale << 16)))r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0); | |||
827 | WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE)r100_mm_wreg(rdev, (0x7d38), (reg | (1 << 2)), 0); | |||
828 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO)r100_mm_wreg(rdev, (0x7d30), ((1 << 3)), 0); | |||
829 | for (j = 0; j < 200; j++) { | |||
830 | udelay(50); | |||
831 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
832 | if (tmp & AVIVO_DC_I2C_GO(1 << 3)) | |||
833 | continue; | |||
834 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
835 | if (tmp & AVIVO_DC_I2C_DONE(1 << 0)) | |||
836 | break; | |||
837 | else { | |||
838 | DRM_DEBUG("i2c read error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c read error 0x%08x\n", tmp); | |||
839 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT)r100_mm_wreg(rdev, (0x7d34), ((1 << 8)), 0); | |||
840 | ret = -EIO5; | |||
841 | goto done; | |||
842 | } | |||
843 | } | |||
844 | for (j = 0; j < current_count; j++) | |||
845 | p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA)r100_mm_rreg(rdev, (0x7d44), 0) & 0xff; | |||
846 | remaining -= current_count; | |||
847 | buffer_offset += current_count; | |||
848 | } | |||
849 | } else { | |||
850 | while (remaining) { | |||
851 | if (remaining > 15) | |||
852 | current_count = 15; | |||
853 | else | |||
854 | current_count = remaining; | |||
855 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
856 | AVIVO_DC_I2C_NACK |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
857 | AVIVO_DC_I2C_HALT))r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0); | |||
858 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET)r100_mm_wreg(rdev, (0x7d34), ((1 << 0)), 0); | |||
859 | udelay(1); | |||
860 | WREG32(AVIVO_DC_I2C_RESET, 0)r100_mm_wreg(rdev, (0x7d34), (0), 0); | |||
861 | ||||
862 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff)r100_mm_wreg(rdev, (0x7d44), ((p->addr << 1) & 0xff ), 0); | |||
863 | for (j = 0; j < current_count; j++) | |||
864 | WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j])r100_mm_wreg(rdev, (0x7d44), (p->buf[buffer_offset + j]), 0 ); | |||
865 | ||||
866 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48))r100_mm_wreg(rdev, (0x7d40), (((48) << 24)), 0); | |||
867 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0) | |||
868 | AVIVO_DC_I2C_DATA_COUNT(current_count) |r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0) | |||
869 | (prescale << 16)))r100_mm_wreg(rdev, (0x7d3c), ((((1) << 0) | ((current_count ) << 8) | (prescale << 16))), 0); | |||
870 | WREG32(AVIVO_DC_I2C_CONTROL1, reg)r100_mm_wreg(rdev, (0x7d38), (reg), 0); | |||
871 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO)r100_mm_wreg(rdev, (0x7d30), ((1 << 3)), 0); | |||
872 | for (j = 0; j < 200; j++) { | |||
873 | udelay(50); | |||
874 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
875 | if (tmp & AVIVO_DC_I2C_GO(1 << 3)) | |||
876 | continue; | |||
877 | tmp = RREG32(AVIVO_DC_I2C_STATUS1)r100_mm_rreg(rdev, (0x7d30), 0); | |||
878 | if (tmp & AVIVO_DC_I2C_DONE(1 << 0)) | |||
879 | break; | |||
880 | else { | |||
881 | DRM_DEBUG("i2c write error 0x%08x\n", tmp)__drm_dbg(DRM_UT_CORE, "i2c write error 0x%08x\n", tmp); | |||
882 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT)r100_mm_wreg(rdev, (0x7d34), ((1 << 8)), 0); | |||
883 | ret = -EIO5; | |||
884 | goto done; | |||
885 | } | |||
886 | } | |||
887 | remaining -= current_count; | |||
888 | buffer_offset += current_count; | |||
889 | } | |||
890 | } | |||
891 | } | |||
892 | ||||
893 | done: | |||
894 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
895 | AVIVO_DC_I2C_NACK |r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0) | |||
896 | AVIVO_DC_I2C_HALT))r100_mm_wreg(rdev, (0x7d30), (((1 << 0) | (1 << 1 ) | (1 << 2))), 0); | |||
897 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET)r100_mm_wreg(rdev, (0x7d34), ((1 << 0)), 0); | |||
898 | udelay(1); | |||
899 | WREG32(AVIVO_DC_I2C_RESET, 0)r100_mm_wreg(rdev, (0x7d34), (0), 0); | |||
900 | ||||
901 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C)r100_mm_wreg(rdev, (0x7d50), ((1 << 8)), 0); | |||
902 | WREG32(AVIVO_DC_I2C_CONTROL1, saved1)r100_mm_wreg(rdev, (0x7d38), (saved1), 0); | |||
903 | WREG32(0x494, saved2)r100_mm_wreg(rdev, (0x494), (saved2), 0); | |||
904 | tmp = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); | |||
905 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE0x00000200L; | |||
906 | WREG32(RADEON_BIOS_6_SCRATCH, tmp)r100_mm_wreg(rdev, (0x0028), (tmp), 0); | |||
907 | ||||
908 | mutex_unlock(&rdev->pm.mutex)rw_exit_write(&rdev->pm.mutex); | |||
909 | mutex_unlock(&rdev->dc_hw_i2c_mutex)rw_exit_write(&rdev->dc_hw_i2c_mutex); | |||
910 | ||||
911 | return ret; | |||
912 | } | |||
913 | ||||
914 | static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, | |||
915 | struct i2c_msg *msgs, int num) | |||
916 | { | |||
917 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
918 | struct radeon_device *rdev = i2c->dev->dev_private; | |||
919 | struct radeon_i2c_bus_rec *rec = &i2c->rec; | |||
920 | int ret = 0; | |||
921 | ||||
922 | mutex_lock(&i2c->mutex)rw_enter_write(&i2c->mutex); | |||
923 | ||||
924 | switch (rdev->family) { | |||
925 | case CHIP_R100: | |||
926 | case CHIP_RV100: | |||
927 | case CHIP_RS100: | |||
928 | case CHIP_RV200: | |||
929 | case CHIP_RS200: | |||
930 | case CHIP_R200: | |||
931 | case CHIP_RV250: | |||
932 | case CHIP_RS300: | |||
933 | case CHIP_RV280: | |||
934 | case CHIP_R300: | |||
935 | case CHIP_R350: | |||
936 | case CHIP_RV350: | |||
937 | case CHIP_RV380: | |||
938 | case CHIP_R420: | |||
939 | case CHIP_R423: | |||
940 | case CHIP_RV410: | |||
941 | case CHIP_RS400: | |||
942 | case CHIP_RS480: | |||
943 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); | |||
944 | break; | |||
945 | case CHIP_RS600: | |||
946 | case CHIP_RS690: | |||
947 | case CHIP_RS740: | |||
948 | /* XXX fill in hw i2c implementation */ | |||
949 | break; | |||
950 | case CHIP_RV515: | |||
951 | case CHIP_R520: | |||
952 | case CHIP_RV530: | |||
953 | case CHIP_RV560: | |||
954 | case CHIP_RV570: | |||
955 | case CHIP_R580: | |||
956 | if (rec->mm_i2c) | |||
957 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); | |||
958 | else | |||
959 | ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); | |||
960 | break; | |||
961 | case CHIP_R600: | |||
962 | case CHIP_RV610: | |||
963 | case CHIP_RV630: | |||
964 | case CHIP_RV670: | |||
965 | /* XXX fill in hw i2c implementation */ | |||
966 | break; | |||
967 | case CHIP_RV620: | |||
968 | case CHIP_RV635: | |||
969 | case CHIP_RS780: | |||
970 | case CHIP_RS880: | |||
971 | case CHIP_RV770: | |||
972 | case CHIP_RV730: | |||
973 | case CHIP_RV710: | |||
974 | case CHIP_RV740: | |||
975 | /* XXX fill in hw i2c implementation */ | |||
976 | break; | |||
977 | case CHIP_CEDAR: | |||
978 | case CHIP_REDWOOD: | |||
979 | case CHIP_JUNIPER: | |||
980 | case CHIP_CYPRESS: | |||
981 | case CHIP_HEMLOCK: | |||
982 | /* XXX fill in hw i2c implementation */ | |||
983 | break; | |||
984 | default: | |||
985 | DRM_ERROR("i2c: unhandled radeon chip\n")__drm_err("i2c: unhandled radeon chip\n"); | |||
986 | ret = -EIO5; | |||
987 | break; | |||
988 | } | |||
989 | ||||
990 | mutex_unlock(&i2c->mutex)rw_exit_write(&i2c->mutex); | |||
991 | ||||
992 | return ret; | |||
993 | } | |||
994 | ||||
995 | static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) | |||
996 | { | |||
997 | return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0; | |||
998 | } | |||
999 | ||||
1000 | static const struct i2c_algorithm radeon_i2c_algo = { | |||
1001 | .master_xfer = radeon_hw_i2c_xfer, | |||
1002 | .functionality = radeon_hw_i2c_func, | |||
1003 | }; | |||
1004 | ||||
1005 | static const struct i2c_algorithm radeon_atom_i2c_algo = { | |||
1006 | .master_xfer = radeon_atom_hw_i2c_xfer, | |||
1007 | .functionality = radeon_atom_hw_i2c_func, | |||
1008 | }; | |||
1009 | ||||
1010 | struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, | |||
1011 | struct radeon_i2c_bus_rec *rec, | |||
1012 | const char *name) | |||
1013 | { | |||
1014 | struct radeon_device *rdev = dev->dev_private; | |||
1015 | struct radeon_i2c_chan *i2c; | |||
1016 | int ret; | |||
1017 | ||||
1018 | /* don't add the mm_i2c bus unless hw_i2c is enabled */ | |||
1019 | if (rec->mm_i2c && (radeon_hw_i2c == 0)) | |||
1020 | return NULL((void *)0); | |||
1021 | ||||
1022 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL(0x0001 | 0x0004)); | |||
1023 | if (i2c == NULL((void *)0)) | |||
1024 | return NULL((void *)0); | |||
1025 | ||||
1026 | i2c->rec = *rec; | |||
1027 | #ifdef __linux__ | |||
1028 | i2c->adapter.owner = THIS_MODULE((void *)0); | |||
1029 | i2c->adapter.class = I2C_CLASS_DDC; | |||
1030 | i2c->adapter.dev.parent = &dev->pdev->dev; | |||
1031 | #endif | |||
1032 | i2c->dev = dev; | |||
1033 | i2c_set_adapdata(&i2c->adapter, i2c); | |||
1034 | rw_init(&i2c->mutex, "riic")_rw_init_flags(&i2c->mutex, "riic", 0, ((void *)0)); | |||
1035 | if (rec->mm_i2c || | |||
1036 | (rec->hw_capable && | |||
1037 | radeon_hw_i2c && | |||
1038 | ((rdev->family <= CHIP_RS480) || | |||
1039 | ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { | |||
1040 | /* set the radeon hw i2c adapter */ | |||
1041 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |||
1042 | "Radeon i2c hw bus %s", name); | |||
1043 | i2c->adapter.algo = &radeon_i2c_algo; | |||
1044 | ret = i2c_add_adapter(&i2c->adapter)0; | |||
1045 | if (ret) | |||
1046 | goto out_free; | |||
1047 | } else if (rec->hw_capable && | |||
1048 | radeon_hw_i2c && | |||
1049 | ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) { | |||
1050 | /* hw i2c using atom */ | |||
1051 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |||
1052 | "Radeon i2c hw bus %s", name); | |||
1053 | i2c->adapter.algo = &radeon_atom_i2c_algo; | |||
1054 | ret = i2c_add_adapter(&i2c->adapter)0; | |||
1055 | if (ret) | |||
1056 | goto out_free; | |||
1057 | } else { | |||
1058 | /* set the radeon bit adapter */ | |||
1059 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |||
1060 | "Radeon i2c bit bus %s", name); | |||
1061 | i2c->adapter.algo_data = &i2c->bit; | |||
1062 | #ifdef notyet | |||
1063 | i2c->bit.pre_xfer = pre_xfer; | |||
1064 | i2c->bit.post_xfer = post_xfer; | |||
1065 | i2c->bit.setsda = set_data; | |||
1066 | i2c->bit.setscl = set_clock; | |||
1067 | i2c->bit.getsda = get_data; | |||
1068 | i2c->bit.getscl = get_clock; | |||
1069 | i2c->bit.udelay = 10; | |||
1070 | i2c->bit.timeout = usecs_to_jiffies(2200)(((uint64_t)(2200)) * hz / 1000000); /* from VESA */ | |||
1071 | i2c->bit.data = i2c; | |||
1072 | #else | |||
1073 | i2c->bit.ic.ic_cookie = i2c; | |||
1074 | i2c->bit.ic.ic_acquire_bus = radeon_acquire_bus; | |||
1075 | i2c->bit.ic.ic_release_bus = radeon_release_bus; | |||
1076 | i2c->bit.ic.ic_send_start = radeon_send_start; | |||
1077 | i2c->bit.ic.ic_send_stop = radeon_send_stop; | |||
1078 | i2c->bit.ic.ic_initiate_xfer = radeon_initiate_xfer; | |||
1079 | i2c->bit.ic.ic_read_byte = radeon_read_byte; | |||
1080 | i2c->bit.ic.ic_write_byte = radeon_write_byte; | |||
1081 | #endif | |||
1082 | ret = i2c_bit_add_bus(&i2c->adapter); | |||
1083 | if (ret) { | |||
1084 | DRM_ERROR("Failed to register bit i2c %s\n", name)__drm_err("Failed to register bit i2c %s\n", name); | |||
1085 | goto out_free; | |||
1086 | } | |||
1087 | } | |||
1088 | ||||
1089 | return i2c; | |||
1090 | out_free: | |||
1091 | kfree(i2c); | |||
1092 | return NULL((void *)0); | |||
1093 | ||||
1094 | } | |||
1095 | ||||
1096 | void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) | |||
1097 | { | |||
1098 | if (!i2c) | |||
1099 | return; | |||
1100 | WARN_ON(i2c->has_aux)({ int __ret = !!(i2c->has_aux); if (__ret) printf("WARNING %s failed at %s:%d\n" , "i2c->has_aux", "/usr/src/sys/dev/pci/drm/radeon/radeon_i2c.c" , 1100); __builtin_expect(!!(__ret), 0); }); | |||
1101 | i2c_del_adapter(&i2c->adapter); | |||
1102 | kfree(i2c); | |||
1103 | } | |||
1104 | ||||
1105 | /* Add the default buses */ | |||
1106 | void radeon_i2c_init(struct radeon_device *rdev) | |||
1107 | { | |||
1108 | if (radeon_hw_i2c) | |||
1109 | DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n")printk("\0016" "[" "drm" "] " "hw_i2c forced on, you may experience display detection problems!\n" ); | |||
1110 | ||||
1111 | if (rdev->is_atom_bios) | |||
1112 | radeon_atombios_i2c_init(rdev); | |||
1113 | else | |||
1114 | radeon_combios_i2c_init(rdev); | |||
1115 | } | |||
1116 | ||||
1117 | /* remove all the buses */ | |||
1118 | void radeon_i2c_fini(struct radeon_device *rdev) | |||
1119 | { | |||
1120 | int i; | |||
1121 | ||||
1122 | for (i = 0; i < RADEON_MAX_I2C_BUS16; i++) { | |||
1123 | if (rdev->i2c_bus[i]) { | |||
1124 | radeon_i2c_destroy(rdev->i2c_bus[i]); | |||
1125 | rdev->i2c_bus[i] = NULL((void *)0); | |||
1126 | } | |||
1127 | } | |||
1128 | } | |||
1129 | ||||
1130 | /* Add additional buses */ | |||
1131 | void radeon_i2c_add(struct radeon_device *rdev, | |||
1132 | struct radeon_i2c_bus_rec *rec, | |||
1133 | const char *name) | |||
1134 | { | |||
1135 | struct drm_device *dev = rdev->ddev; | |||
1136 | int i; | |||
1137 | ||||
1138 | for (i = 0; i < RADEON_MAX_I2C_BUS16; i++) { | |||
1139 | if (!rdev->i2c_bus[i]) { | |||
1140 | rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); | |||
1141 | return; | |||
1142 | } | |||
1143 | } | |||
1144 | } | |||
1145 | ||||
1146 | /* looks up bus based on id */ | |||
1147 | struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, | |||
1148 | struct radeon_i2c_bus_rec *i2c_bus) | |||
1149 | { | |||
1150 | int i; | |||
1151 | ||||
1152 | for (i = 0; i < RADEON_MAX_I2C_BUS16; i++) { | |||
1153 | if (rdev->i2c_bus[i] && | |||
1154 | (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { | |||
1155 | return rdev->i2c_bus[i]; | |||
1156 | } | |||
1157 | } | |||
1158 | return NULL((void *)0); | |||
1159 | } | |||
1160 | ||||
1161 | void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, | |||
1162 | u8 slave_addr, | |||
1163 | u8 addr, | |||
1164 | u8 *val) | |||
1165 | { | |||
1166 | u8 out_buf[2]; | |||
1167 | u8 in_buf[2]; | |||
1168 | struct i2c_msg msgs[] = { | |||
1169 | { | |||
1170 | .addr = slave_addr, | |||
1171 | .flags = 0, | |||
1172 | .len = 1, | |||
1173 | .buf = out_buf, | |||
1174 | }, | |||
1175 | { | |||
1176 | .addr = slave_addr, | |||
1177 | .flags = I2C_M_RD0x0001, | |||
1178 | .len = 1, | |||
1179 | .buf = in_buf, | |||
1180 | } | |||
1181 | }; | |||
1182 | ||||
1183 | out_buf[0] = addr; | |||
1184 | out_buf[1] = 0; | |||
1185 | ||||
1186 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { | |||
1187 | *val = in_buf[0]; | |||
1188 | DRM_DEBUG("val = 0x%02x\n", *val)__drm_dbg(DRM_UT_CORE, "val = 0x%02x\n", *val); | |||
1189 | } else { | |||
1190 | DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x read failed\n", addr , *val) | |||
| ||||
1191 | addr, *val)__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x read failed\n", addr , *val); | |||
1192 | } | |||
1193 | } | |||
1194 | ||||
1195 | void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, | |||
1196 | u8 slave_addr, | |||
1197 | u8 addr, | |||
1198 | u8 val) | |||
1199 | { | |||
1200 | uint8_t out_buf[2]; | |||
1201 | struct i2c_msg msg = { | |||
1202 | .addr = slave_addr, | |||
1203 | .flags = 0, | |||
1204 | .len = 2, | |||
1205 | .buf = out_buf, | |||
1206 | }; | |||
1207 | ||||
1208 | out_buf[0] = addr; | |||
1209 | out_buf[1] = val; | |||
1210 | ||||
1211 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) | |||
1212 | DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x write failed\n", addr , val) | |||
1213 | addr, val)__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x write failed\n", addr , val); | |||
1214 | } | |||
1215 | ||||
1216 | /* ddc router switching */ | |||
1217 | void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) | |||
1218 | { | |||
1219 | u8 val; | |||
1220 | ||||
1221 | if (!radeon_connector->router.ddc_valid) | |||
1222 | return; | |||
1223 | ||||
1224 | if (!radeon_connector->router_bus) | |||
1225 | return; | |||
1226 | ||||
1227 | radeon_i2c_get_byte(radeon_connector->router_bus, | |||
1228 | radeon_connector->router.i2c_addr, | |||
1229 | 0x3, &val); | |||
1230 | val &= ~radeon_connector->router.ddc_mux_control_pin; | |||
1231 | radeon_i2c_put_byte(radeon_connector->router_bus, | |||
1232 | radeon_connector->router.i2c_addr, | |||
1233 | 0x3, val); | |||
1234 | radeon_i2c_get_byte(radeon_connector->router_bus, | |||
1235 | radeon_connector->router.i2c_addr, | |||
1236 | 0x1, &val); | |||
1237 | val &= ~radeon_connector->router.ddc_mux_control_pin; | |||
1238 | val |= radeon_connector->router.ddc_mux_state; | |||
1239 | radeon_i2c_put_byte(radeon_connector->router_bus, | |||
1240 | radeon_connector->router.i2c_addr, | |||
1241 | 0x1, val); | |||
1242 | } | |||
1243 | ||||
1244 | /* clock/data router switching */ | |||
1245 | void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) | |||
1246 | { | |||
1247 | u8 val; | |||
| ||||
1248 | ||||
1249 | if (!radeon_connector->router.cd_valid) | |||
1250 | return; | |||
1251 | ||||
1252 | if (!radeon_connector->router_bus) | |||
1253 | return; | |||
1254 | ||||
1255 | radeon_i2c_get_byte(radeon_connector->router_bus, | |||
1256 | radeon_connector->router.i2c_addr, | |||
1257 | 0x3, &val); | |||
1258 | val &= ~radeon_connector->router.cd_mux_control_pin; | |||
1259 | radeon_i2c_put_byte(radeon_connector->router_bus, | |||
1260 | radeon_connector->router.i2c_addr, | |||
1261 | 0x3, val); | |||
1262 | radeon_i2c_get_byte(radeon_connector->router_bus, | |||
1263 | radeon_connector->router.i2c_addr, | |||
1264 | 0x1, &val); | |||
1265 | val &= ~radeon_connector->router.cd_mux_control_pin; | |||
1266 | val |= radeon_connector->router.cd_mux_state; | |||
1267 | radeon_i2c_put_byte(radeon_connector->router_bus, | |||
1268 | radeon_connector->router.i2c_addr, | |||
1269 | 0x1, val); | |||
1270 | } | |||
1271 |