File: | dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c |
Warning: | line 1356, column 3 Value stored to 'value_crtc_vtotal' is never read |
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1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dm_services.h" |
27 | |
28 | /* include DCE11 register header files */ |
29 | #include "dce/dce_11_0_d.h" |
30 | #include "dce/dce_11_0_sh_mask.h" |
31 | |
32 | #include "dc_types.h" |
33 | #include "dc_bios_types.h" |
34 | #include "dc.h" |
35 | |
36 | #include "include/grph_object_id.h" |
37 | #include "include/logger_interface.h" |
38 | #include "dce110_timing_generator.h" |
39 | |
40 | #include "timing_generator.h" |
41 | |
42 | |
43 | #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET10 10 |
44 | |
45 | #define MAX_H_TOTAL(0x3fff + 1) (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK0x3fff + 1) |
46 | #define MAX_V_TOTAL(CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1) (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1) |
47 | |
48 | #define CRTC_REG(reg)(reg + tg110->offsets.crtc) (reg + tg110->offsets.crtc) |
49 | #define DCP_REG(reg)(reg + tg110->offsets.dcp) (reg + tg110->offsets.dcp) |
50 | |
51 | /* Flowing register offsets are same in files of |
52 | * dce/dce_11_0_d.h |
53 | * dce/vi_polaris10_p/vi_polaris10_d.h |
54 | * |
55 | * So we can create dce110 timing generator to use it. |
56 | */ |
57 | |
58 | |
59 | /* |
60 | * apply_front_porch_workaround |
61 | * |
62 | * This is a workaround for a bug that has existed since R5xx and has not been |
63 | * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. |
64 | */ |
65 | static void dce110_timing_generator_apply_front_porch_workaround( |
66 | struct timing_generator *tg, |
67 | struct dc_crtc_timing *timing) |
68 | { |
69 | if (timing->flags.INTERLACE == 1) { |
70 | if (timing->v_front_porch < 2) |
71 | timing->v_front_porch = 2; |
72 | } else { |
73 | if (timing->v_front_porch < 1) |
74 | timing->v_front_porch = 1; |
75 | } |
76 | } |
77 | |
78 | /** |
79 | ***************************************************************************** |
80 | * Function: is_in_vertical_blank |
81 | * |
82 | * @brief |
83 | * check the current status of CRTC to check if we are in Vertical Blank |
84 | * regioneased" state |
85 | * |
86 | * @return |
87 | * true if currently in blank region, false otherwise |
88 | * |
89 | ***************************************************************************** |
90 | */ |
91 | static bool_Bool dce110_timing_generator_is_in_vertical_blank( |
92 | struct timing_generator *tg) |
93 | { |
94 | uint32_t addr = 0; |
95 | uint32_t value = 0; |
96 | uint32_t field = 0; |
97 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
98 | |
99 | addr = CRTC_REG(mmCRTC_STATUS)(0x1ba3 + tg110->offsets.crtc); |
100 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
101 | field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK)get_reg_field_value_ex( (value), 0x1, 0x0); |
102 | return field == 1; |
103 | } |
104 | |
105 | void dce110_timing_generator_set_early_control( |
106 | struct timing_generator *tg, |
107 | uint32_t early_cntl) |
108 | { |
109 | uint32_t regval; |
110 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
111 | uint32_t address = CRTC_REG(mmCRTC_CONTROL)(0x1b9c + tg110->offsets.crtc); |
112 | |
113 | regval = dm_read_reg(tg->ctx, address)dm_read_reg_func(tg->ctx, address, __func__); |
114 | set_reg_field_value(regval, early_cntl,(regval) = set_reg_field_value_ex( (regval), (early_cntl), 0x700000 , 0x14) |
115 | CRTC_CONTROL, CRTC_HBLANK_EARLY_CONTROL)(regval) = set_reg_field_value_ex( (regval), (early_cntl), 0x700000 , 0x14); |
116 | dm_write_reg(tg->ctx, address, regval)dm_write_reg_func(tg->ctx, address, regval, __func__); |
117 | } |
118 | |
119 | /** |
120 | * Enable CRTC |
121 | * Enable CRTC - call ASIC Control Object to enable Timing generator. |
122 | */ |
123 | bool_Bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) |
124 | { |
125 | enum bp_result result; |
126 | |
127 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
128 | uint32_t value = 0; |
129 | |
130 | /* |
131 | * 3 is used to make sure V_UPDATE occurs at the beginning of the first |
132 | * line of vertical front porch |
133 | */ |
134 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
135 | value,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
136 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
137 | CRTC_MASTER_UPDATE_MODE,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
138 | MASTER_UPDATE_MODE)(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0); |
139 | |
140 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value)dm_write_reg_func(tg->ctx, (0x1bbe + tg110->offsets.crtc ), value, __func__); |
141 | |
142 | /* TODO: may want this on to catch underflow */ |
143 | value = 0; |
144 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value)dm_write_reg_func(tg->ctx, (0x1bbd + tg110->offsets.crtc ), value, __func__); |
145 | |
146 | result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true1); |
147 | |
148 | return result == BP_RESULT_OK; |
149 | } |
150 | |
151 | void dce110_timing_generator_program_blank_color( |
152 | struct timing_generator *tg, |
153 | const struct tg_color *black_color) |
154 | { |
155 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
156 | uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR)(0x1bcc + tg110->offsets.crtc); |
157 | uint32_t value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
158 | |
159 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
160 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
161 | black_color->color_b_cb,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
162 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
163 | CRTC_BLACK_COLOR_B_CB)(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0); |
164 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
165 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
166 | black_color->color_g_y,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
167 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
168 | CRTC_BLACK_COLOR_G_Y)(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa); |
169 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
170 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
171 | black_color->color_r_cr,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
172 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
173 | CRTC_BLACK_COLOR_R_CR)(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14); |
174 | |
175 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
176 | } |
177 | |
178 | /** |
179 | ***************************************************************************** |
180 | * Function: disable_stereo |
181 | * |
182 | * @brief |
183 | * Disables active stereo on controller |
184 | * Frame Packing need to be disabled in vBlank or when CRTC not running |
185 | ***************************************************************************** |
186 | */ |
187 | #if 0 |
188 | @TODOSTEREO |
189 | static void disable_stereo(struct timing_generator *tg) |
190 | { |
191 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
192 | uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL)(0x1b78 + tg110->offsets.crtc); |
193 | uint32_t value = 0; |
194 | uint32_t test = 0; |
195 | uint32_t field = 0; |
196 | uint32_t struc_en = 0; |
197 | uint32_t struc_stereo_sel_ovr = 0; |
198 | |
199 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
200 | struc_en = get_reg_field_value(get_reg_field_value_ex( (value), 0x1, 0x0) |
201 | value,get_reg_field_value_ex( (value), 0x1, 0x0) |
202 | CRTC_3D_STRUCTURE_CONTROL,get_reg_field_value_ex( (value), 0x1, 0x0) |
203 | CRTC_3D_STRUCTURE_EN)get_reg_field_value_ex( (value), 0x1, 0x0); |
204 | |
205 | struc_stereo_sel_ovr = get_reg_field_value(get_reg_field_value_ex( (value), 0x1000, 0xc) |
206 | value,get_reg_field_value_ex( (value), 0x1000, 0xc) |
207 | CRTC_3D_STRUCTURE_CONTROL,get_reg_field_value_ex( (value), 0x1000, 0xc) |
208 | CRTC_3D_STRUCTURE_STEREO_SEL_OVR)get_reg_field_value_ex( (value), 0x1000, 0xc); |
209 | |
210 | /* |
211 | * When disabling Frame Packing in 2 step mode, we need to program both |
212 | * registers at the same frame |
213 | * Programming it in the beginning of VActive makes sure we are ok |
214 | */ |
215 | |
216 | if (struc_en != 0 && struc_stereo_sel_ovr == 0) { |
217 | tg->funcs->wait_for_vblank(tg); |
218 | tg->funcs->wait_for_vactive(tg); |
219 | } |
220 | |
221 | value = 0; |
222 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
223 | |
224 | addr = tg->regs[IDX_CRTC_STEREO_CONTROL]; |
225 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
226 | } |
227 | #endif |
228 | |
229 | /** |
230 | * disable_crtc - call ASIC Control Object to disable Timing generator. |
231 | */ |
232 | bool_Bool dce110_timing_generator_disable_crtc(struct timing_generator *tg) |
233 | { |
234 | enum bp_result result; |
235 | |
236 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
237 | |
238 | result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false0); |
239 | |
240 | /* Need to make sure stereo is disabled according to the DCE5.0 spec */ |
241 | |
242 | /* |
243 | * @TODOSTEREO call this when adding stereo support |
244 | * tg->funcs->disable_stereo(tg); |
245 | */ |
246 | |
247 | return result == BP_RESULT_OK; |
248 | } |
249 | |
250 | /** |
251 | * program_horz_count_by_2 |
252 | * Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise |
253 | * |
254 | */ |
255 | static void program_horz_count_by_2( |
256 | struct timing_generator *tg, |
257 | const struct dc_crtc_timing *timing) |
258 | { |
259 | uint32_t regval; |
260 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
261 | |
262 | regval = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1ba9 + tg110->offsets.crtc ), __func__) |
263 | CRTC_REG(mmCRTC_COUNT_CONTROL))dm_read_reg_func(tg->ctx, (0x1ba9 + tg110->offsets.crtc ), __func__); |
264 | |
265 | set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,(regval) = set_reg_field_value_ex( (regval), (0), 0x1, 0x0) |
266 | CRTC_HORZ_COUNT_BY2_EN)(regval) = set_reg_field_value_ex( (regval), (0), 0x1, 0x0); |
267 | |
268 | if (timing->flags.HORZ_COUNT_BY_TWO) |
269 | set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,(regval) = set_reg_field_value_ex( (regval), (1), 0x1, 0x0) |
270 | CRTC_HORZ_COUNT_BY2_EN)(regval) = set_reg_field_value_ex( (regval), (1), 0x1, 0x0); |
271 | |
272 | dm_write_reg(tg->ctx,dm_write_reg_func(tg->ctx, (0x1ba9 + tg110->offsets.crtc ), regval, __func__) |
273 | CRTC_REG(mmCRTC_COUNT_CONTROL), regval)dm_write_reg_func(tg->ctx, (0x1ba9 + tg110->offsets.crtc ), regval, __func__); |
274 | } |
275 | |
276 | /** |
277 | * program_timing_generator |
278 | * Program CRTC Timing Registers - DxCRTC_H_*, DxCRTC_V_*, Pixel repetition. |
279 | * Call ASIC Control Object to program Timings. |
280 | */ |
281 | bool_Bool dce110_timing_generator_program_timing_generator( |
282 | struct timing_generator *tg, |
283 | const struct dc_crtc_timing *dc_crtc_timing) |
284 | { |
285 | enum bp_result result; |
286 | struct bp_hw_crtc_timing_parameters bp_params; |
287 | struct dc_crtc_timing patched_crtc_timing; |
288 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
289 | |
290 | uint32_t vsync_offset = dc_crtc_timing->v_border_bottom + |
291 | dc_crtc_timing->v_front_porch; |
292 | uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset; |
293 | |
294 | uint32_t hsync_offset = dc_crtc_timing->h_border_right + |
295 | dc_crtc_timing->h_front_porch; |
296 | uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; |
297 | |
298 | memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters))__builtin_memset((&bp_params), (0), (sizeof(struct bp_hw_crtc_timing_parameters ))); |
299 | |
300 | /* Due to an asic bug we need to apply the Front Porch workaround prior |
301 | * to programming the timing. |
302 | */ |
303 | |
304 | patched_crtc_timing = *dc_crtc_timing; |
305 | |
306 | dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing); |
307 | |
308 | bp_params.controller_id = tg110->controller_id; |
309 | |
310 | bp_params.h_total = patched_crtc_timing.h_total; |
311 | bp_params.h_addressable = |
312 | patched_crtc_timing.h_addressable; |
313 | bp_params.v_total = patched_crtc_timing.v_total; |
314 | bp_params.v_addressable = patched_crtc_timing.v_addressable; |
315 | |
316 | bp_params.h_sync_start = h_sync_start; |
317 | bp_params.h_sync_width = patched_crtc_timing.h_sync_width; |
318 | bp_params.v_sync_start = v_sync_start; |
319 | bp_params.v_sync_width = patched_crtc_timing.v_sync_width; |
320 | |
321 | /* Set overscan */ |
322 | bp_params.h_overscan_left = |
323 | patched_crtc_timing.h_border_left; |
324 | bp_params.h_overscan_right = |
325 | patched_crtc_timing.h_border_right; |
326 | bp_params.v_overscan_top = patched_crtc_timing.v_border_top; |
327 | bp_params.v_overscan_bottom = |
328 | patched_crtc_timing.v_border_bottom; |
329 | |
330 | /* Set flags */ |
331 | if (patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY == 1) |
332 | bp_params.flags.HSYNC_POSITIVE_POLARITY = 1; |
333 | |
334 | if (patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY == 1) |
335 | bp_params.flags.VSYNC_POSITIVE_POLARITY = 1; |
336 | |
337 | if (patched_crtc_timing.flags.INTERLACE == 1) |
338 | bp_params.flags.INTERLACE = 1; |
339 | |
340 | if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1) |
341 | bp_params.flags.HORZ_COUNT_BY_TWO = 1; |
342 | |
343 | result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params); |
344 | |
345 | program_horz_count_by_2(tg, &patched_crtc_timing); |
346 | |
347 | tg110->base.funcs->enable_advanced_request(tg, true1, &patched_crtc_timing); |
348 | |
349 | /* Enable stereo - only when we need to pack 3D frame. Other types |
350 | * of stereo handled in explicit call */ |
351 | |
352 | return result == BP_RESULT_OK; |
353 | } |
354 | |
355 | /** |
356 | ***************************************************************************** |
357 | * Function: set_drr |
358 | * |
359 | * @brief |
360 | * Program dynamic refresh rate registers m_DxCRTC_V_TOTAL_*. |
361 | * |
362 | * @param [in] pHwCrtcTiming: point to H |
363 | * wCrtcTiming struct |
364 | ***************************************************************************** |
365 | */ |
366 | void dce110_timing_generator_set_drr( |
367 | struct timing_generator *tg, |
368 | const struct drr_params *params) |
369 | { |
370 | /* register values */ |
371 | uint32_t v_total_min = 0; |
372 | uint32_t v_total_max = 0; |
373 | uint32_t v_total_cntl = 0; |
374 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
375 | |
376 | uint32_t addr = 0; |
377 | |
378 | addr = CRTC_REG(mmCRTC_V_TOTAL_MIN)(0x1b88 + tg110->offsets.crtc); |
379 | v_total_min = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
380 | |
381 | addr = CRTC_REG(mmCRTC_V_TOTAL_MAX)(0x1b89 + tg110->offsets.crtc); |
382 | v_total_max = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
383 | |
384 | addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL)(0x1b8a + tg110->offsets.crtc); |
385 | v_total_cntl = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
386 | |
387 | if (params != NULL((void *)0) && |
388 | params->vertical_total_max > 0 && |
389 | params->vertical_total_min > 0) { |
390 | |
391 | set_reg_field_value(v_total_max,(v_total_max) = set_reg_field_value_ex( (v_total_max), (params ->vertical_total_max - 1), 0x3fff, 0x0) |
392 | params->vertical_total_max - 1,(v_total_max) = set_reg_field_value_ex( (v_total_max), (params ->vertical_total_max - 1), 0x3fff, 0x0) |
393 | CRTC_V_TOTAL_MAX,(v_total_max) = set_reg_field_value_ex( (v_total_max), (params ->vertical_total_max - 1), 0x3fff, 0x0) |
394 | CRTC_V_TOTAL_MAX)(v_total_max) = set_reg_field_value_ex( (v_total_max), (params ->vertical_total_max - 1), 0x3fff, 0x0); |
395 | |
396 | set_reg_field_value(v_total_min,(v_total_min) = set_reg_field_value_ex( (v_total_min), (params ->vertical_total_min - 1), 0x3fff, 0x0) |
397 | params->vertical_total_min - 1,(v_total_min) = set_reg_field_value_ex( (v_total_min), (params ->vertical_total_min - 1), 0x3fff, 0x0) |
398 | CRTC_V_TOTAL_MIN,(v_total_min) = set_reg_field_value_ex( (v_total_min), (params ->vertical_total_min - 1), 0x3fff, 0x0) |
399 | CRTC_V_TOTAL_MIN)(v_total_min) = set_reg_field_value_ex( (v_total_min), (params ->vertical_total_min - 1), 0x3fff, 0x0); |
400 | |
401 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x1, 0x0) |
402 | 1,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x1, 0x0) |
403 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x1, 0x0) |
404 | CRTC_V_TOTAL_MIN_SEL)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x1, 0x0); |
405 | |
406 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x10, 0x4) |
407 | 1,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x10, 0x4) |
408 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x10, 0x4) |
409 | CRTC_V_TOTAL_MAX_SEL)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (1), 0x10, 0x4); |
410 | |
411 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
412 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
413 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
414 | CRTC_FORCE_LOCK_ON_EVENT)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8); |
415 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
416 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
417 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
418 | CRTC_FORCE_LOCK_TO_MASTER_VSYNC)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc); |
419 | |
420 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x8000, 0xf) |
421 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x8000, 0xf) |
422 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x8000, 0xf) |
423 | CRTC_SET_V_TOTAL_MIN_MASK_EN)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x8000, 0xf); |
424 | |
425 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
426 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
427 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
428 | CRTC_SET_V_TOTAL_MIN_MASK)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10); |
429 | } else { |
430 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
431 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
432 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10) |
433 | CRTC_SET_V_TOTAL_MIN_MASK)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0xffff0000, 0x10); |
434 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1, 0x0) |
435 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1, 0x0) |
436 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1, 0x0) |
437 | CRTC_V_TOTAL_MIN_SEL)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1, 0x0); |
438 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x10, 0x4) |
439 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x10, 0x4) |
440 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x10, 0x4) |
441 | CRTC_V_TOTAL_MAX_SEL)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x10, 0x4); |
442 | set_reg_field_value(v_total_min,(v_total_min) = set_reg_field_value_ex( (v_total_min), (0), 0x3fff , 0x0) |
443 | 0,(v_total_min) = set_reg_field_value_ex( (v_total_min), (0), 0x3fff , 0x0) |
444 | CRTC_V_TOTAL_MIN,(v_total_min) = set_reg_field_value_ex( (v_total_min), (0), 0x3fff , 0x0) |
445 | CRTC_V_TOTAL_MIN)(v_total_min) = set_reg_field_value_ex( (v_total_min), (0), 0x3fff , 0x0); |
446 | set_reg_field_value(v_total_max,(v_total_max) = set_reg_field_value_ex( (v_total_max), (0), 0x3fff , 0x0) |
447 | 0,(v_total_max) = set_reg_field_value_ex( (v_total_max), (0), 0x3fff , 0x0) |
448 | CRTC_V_TOTAL_MAX,(v_total_max) = set_reg_field_value_ex( (v_total_max), (0), 0x3fff , 0x0) |
449 | CRTC_V_TOTAL_MAX)(v_total_max) = set_reg_field_value_ex( (v_total_max), (0), 0x3fff , 0x0); |
450 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
451 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
452 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8) |
453 | CRTC_FORCE_LOCK_ON_EVENT)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x100, 0x8); |
454 | set_reg_field_value(v_total_cntl,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
455 | 0,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
456 | CRTC_V_TOTAL_CONTROL,(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc) |
457 | CRTC_FORCE_LOCK_TO_MASTER_VSYNC)(v_total_cntl) = set_reg_field_value_ex( (v_total_cntl), (0), 0x1000, 0xc); |
458 | } |
459 | |
460 | addr = CRTC_REG(mmCRTC_V_TOTAL_MIN)(0x1b88 + tg110->offsets.crtc); |
461 | dm_write_reg(tg->ctx, addr, v_total_min)dm_write_reg_func(tg->ctx, addr, v_total_min, __func__); |
462 | |
463 | addr = CRTC_REG(mmCRTC_V_TOTAL_MAX)(0x1b89 + tg110->offsets.crtc); |
464 | dm_write_reg(tg->ctx, addr, v_total_max)dm_write_reg_func(tg->ctx, addr, v_total_max, __func__); |
465 | |
466 | addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL)(0x1b8a + tg110->offsets.crtc); |
467 | dm_write_reg(tg->ctx, addr, v_total_cntl)dm_write_reg_func(tg->ctx, addr, v_total_cntl, __func__); |
468 | } |
469 | |
470 | void dce110_timing_generator_set_static_screen_control( |
471 | struct timing_generator *tg, |
472 | uint32_t event_triggers, |
473 | uint32_t num_frames) |
474 | { |
475 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
476 | uint32_t static_screen_cntl = 0; |
477 | uint32_t addr = 0; |
478 | |
479 | // By register spec, it only takes 8 bit value |
480 | if (num_frames > 0xFF) |
481 | num_frames = 0xFF; |
482 | |
483 | addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL)(0x1be7 + tg110->offsets.crtc); |
484 | static_screen_cntl = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
485 | |
486 | set_reg_field_value(static_screen_cntl,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (event_triggers), 0xffff, 0x0) |
487 | event_triggers,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (event_triggers), 0xffff, 0x0) |
488 | CRTC_STATIC_SCREEN_CONTROL,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (event_triggers), 0xffff, 0x0) |
489 | CRTC_STATIC_SCREEN_EVENT_MASK)(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (event_triggers), 0xffff, 0x0); |
490 | |
491 | set_reg_field_value(static_screen_cntl,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (num_frames), 0xff0000, 0x10) |
492 | num_frames,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (num_frames), 0xff0000, 0x10) |
493 | CRTC_STATIC_SCREEN_CONTROL,(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (num_frames), 0xff0000, 0x10) |
494 | CRTC_STATIC_SCREEN_FRAME_COUNT)(static_screen_cntl) = set_reg_field_value_ex( (static_screen_cntl ), (num_frames), 0xff0000, 0x10); |
495 | |
496 | dm_write_reg(tg->ctx, addr, static_screen_cntl)dm_write_reg_func(tg->ctx, addr, static_screen_cntl, __func__ ); |
497 | } |
498 | |
499 | /* |
500 | * get_vblank_counter |
501 | * |
502 | * @brief |
503 | * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which |
504 | * holds the counter of frames. |
505 | * |
506 | * @param |
507 | * struct timing_generator *tg - [in] timing generator which controls the |
508 | * desired CRTC |
509 | * |
510 | * @return |
511 | * Counter of frames, which should equal to number of vblanks. |
512 | */ |
513 | uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg) |
514 | { |
515 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
516 | uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT)(0x1ba6 + tg110->offsets.crtc); |
517 | uint32_t value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
518 | uint32_t field = get_reg_field_value(get_reg_field_value_ex( (value), 0xffffff, 0x0) |
519 | value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT)get_reg_field_value_ex( (value), 0xffffff, 0x0); |
520 | |
521 | return field; |
522 | } |
523 | |
524 | /** |
525 | ***************************************************************************** |
526 | * Function: dce110_timing_generator_get_position |
527 | * |
528 | * @brief |
529 | * Returns CRTC vertical/horizontal counters |
530 | * |
531 | * @param [out] position |
532 | ***************************************************************************** |
533 | */ |
534 | void dce110_timing_generator_get_position(struct timing_generator *tg, |
535 | struct crtc_position *position) |
536 | { |
537 | uint32_t value; |
538 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
539 | |
540 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION))dm_read_reg_func(tg->ctx, (0x1ba4 + tg110->offsets.crtc ), __func__); |
541 | |
542 | position->horizontal_count = get_reg_field_value(get_reg_field_value_ex( (value), 0x3fff0000, 0x10) |
543 | value,get_reg_field_value_ex( (value), 0x3fff0000, 0x10) |
544 | CRTC_STATUS_POSITION,get_reg_field_value_ex( (value), 0x3fff0000, 0x10) |
545 | CRTC_HORZ_COUNT)get_reg_field_value_ex( (value), 0x3fff0000, 0x10); |
546 | |
547 | position->vertical_count = get_reg_field_value(get_reg_field_value_ex( (value), 0x3fff, 0x0) |
548 | value,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
549 | CRTC_STATUS_POSITION,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
550 | CRTC_VERT_COUNT)get_reg_field_value_ex( (value), 0x3fff, 0x0); |
551 | |
552 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_NOM_VERT_POSITION))dm_read_reg_func(tg->ctx, (0x1ba5 + tg110->offsets.crtc ), __func__); |
553 | |
554 | position->nominal_vcount = get_reg_field_value(get_reg_field_value_ex( (value), 0x3fff, 0x0) |
555 | value,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
556 | CRTC_NOM_VERT_POSITION,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
557 | CRTC_VERT_COUNT_NOM)get_reg_field_value_ex( (value), 0x3fff, 0x0); |
558 | } |
559 | |
560 | /** |
561 | ***************************************************************************** |
562 | * Function: get_crtc_scanoutpos |
563 | * |
564 | * @brief |
565 | * Returns CRTC vertical/horizontal counters |
566 | * |
567 | * @param [out] vpos, hpos |
568 | ***************************************************************************** |
569 | */ |
570 | void dce110_timing_generator_get_crtc_scanoutpos( |
571 | struct timing_generator *tg, |
572 | uint32_t *v_blank_start, |
573 | uint32_t *v_blank_end, |
574 | uint32_t *h_position, |
575 | uint32_t *v_position) |
576 | { |
577 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
578 | struct crtc_position position; |
579 | |
580 | uint32_t value = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1b8d + tg110->offsets.crtc ), __func__) |
581 | CRTC_REG(mmCRTC_V_BLANK_START_END))dm_read_reg_func(tg->ctx, (0x1b8d + tg110->offsets.crtc ), __func__); |
582 | |
583 | *v_blank_start = get_reg_field_value(value,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
584 | CRTC_V_BLANK_START_END,get_reg_field_value_ex( (value), 0x3fff, 0x0) |
585 | CRTC_V_BLANK_START)get_reg_field_value_ex( (value), 0x3fff, 0x0); |
586 | *v_blank_end = get_reg_field_value(value,get_reg_field_value_ex( (value), 0x3fff0000, 0x10) |
587 | CRTC_V_BLANK_START_END,get_reg_field_value_ex( (value), 0x3fff0000, 0x10) |
588 | CRTC_V_BLANK_END)get_reg_field_value_ex( (value), 0x3fff0000, 0x10); |
589 | |
590 | dce110_timing_generator_get_position( |
591 | tg, &position); |
592 | |
593 | *h_position = position.horizontal_count; |
594 | *v_position = position.vertical_count; |
595 | } |
596 | |
597 | /* TODO: is it safe to assume that mask/shift of Primary and Underlay |
598 | * are the same? |
599 | * For example: today CRTC_H_TOTAL == CRTCV_H_TOTAL but is it always |
600 | * guaranteed? */ |
601 | void dce110_timing_generator_program_blanking( |
602 | struct timing_generator *tg, |
603 | const struct dc_crtc_timing *timing) |
604 | { |
605 | uint32_t vsync_offset = timing->v_border_bottom + |
606 | timing->v_front_porch; |
607 | uint32_t v_sync_start =timing->v_addressable + vsync_offset; |
608 | |
609 | uint32_t hsync_offset = timing->h_border_right + |
610 | timing->h_front_porch; |
611 | uint32_t h_sync_start = timing->h_addressable + hsync_offset; |
612 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
613 | |
614 | struct dc_context *ctx = tg->ctx; |
615 | uint32_t value = 0; |
616 | uint32_t addr = 0; |
617 | uint32_t tmp = 0; |
618 | |
619 | addr = CRTC_REG(mmCRTC_H_TOTAL)(0x1b80 + tg110->offsets.crtc); |
620 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
621 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (timing->h_total - 1), 0x3fff, 0x0) |
622 | value,(value) = set_reg_field_value_ex( (value), (timing->h_total - 1), 0x3fff, 0x0) |
623 | timing->h_total - 1,(value) = set_reg_field_value_ex( (value), (timing->h_total - 1), 0x3fff, 0x0) |
624 | CRTC_H_TOTAL,(value) = set_reg_field_value_ex( (value), (timing->h_total - 1), 0x3fff, 0x0) |
625 | CRTC_H_TOTAL)(value) = set_reg_field_value_ex( (value), (timing->h_total - 1), 0x3fff, 0x0); |
626 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
627 | |
628 | addr = CRTC_REG(mmCRTC_V_TOTAL)(0x1b87 + tg110->offsets.crtc); |
629 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
630 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
631 | value,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
632 | timing->v_total - 1,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
633 | CRTC_V_TOTAL,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
634 | CRTC_V_TOTAL)(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0); |
635 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
636 | |
637 | /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and |
638 | * V_TOTAL_MIN are equal to V_TOTAL. |
639 | */ |
640 | addr = CRTC_REG(mmCRTC_V_TOTAL_MAX)(0x1b89 + tg110->offsets.crtc); |
641 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
642 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
643 | value,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
644 | timing->v_total - 1,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
645 | CRTC_V_TOTAL_MAX,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
646 | CRTC_V_TOTAL_MAX)(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0); |
647 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
648 | |
649 | addr = CRTC_REG(mmCRTC_V_TOTAL_MIN)(0x1b88 + tg110->offsets.crtc); |
650 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
651 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
652 | value,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
653 | timing->v_total - 1,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
654 | CRTC_V_TOTAL_MIN,(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0) |
655 | CRTC_V_TOTAL_MIN)(value) = set_reg_field_value_ex( (value), (timing->v_total - 1), 0x3fff, 0x0); |
656 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
657 | |
658 | addr = CRTC_REG(mmCRTC_H_BLANK_START_END)(0x1b81 + tg110->offsets.crtc); |
659 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
660 | |
661 | tmp = timing->h_total - |
662 | (h_sync_start + timing->h_border_left); |
663 | |
664 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
665 | value,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
666 | tmp,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
667 | CRTC_H_BLANK_START_END,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
668 | CRTC_H_BLANK_END)(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10); |
669 | |
670 | tmp = tmp + timing->h_addressable + |
671 | timing->h_border_left + timing->h_border_right; |
672 | |
673 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
674 | value,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
675 | tmp,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
676 | CRTC_H_BLANK_START_END,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
677 | CRTC_H_BLANK_START)(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ); |
678 | |
679 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
680 | |
681 | addr = CRTC_REG(mmCRTC_V_BLANK_START_END)(0x1b8d + tg110->offsets.crtc); |
682 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
683 | |
684 | tmp = timing->v_total - (v_sync_start + timing->v_border_top); |
685 | |
686 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
687 | value,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
688 | tmp,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
689 | CRTC_V_BLANK_START_END,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10) |
690 | CRTC_V_BLANK_END)(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff0000, 0x10); |
691 | |
692 | tmp = tmp + timing->v_addressable + timing->v_border_top + |
693 | timing->v_border_bottom; |
694 | |
695 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
696 | value,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
697 | tmp,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
698 | CRTC_V_BLANK_START_END,(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ) |
699 | CRTC_V_BLANK_START)(value) = set_reg_field_value_ex( (value), (tmp), 0x3fff, 0x0 ); |
700 | |
701 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
702 | } |
703 | |
704 | void dce110_timing_generator_set_test_pattern( |
705 | struct timing_generator *tg, |
706 | /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' |
707 | * because this is not DP-specific (which is probably somewhere in DP |
708 | * encoder) */ |
709 | enum controller_dp_test_pattern test_pattern, |
710 | enum dc_color_depth color_depth) |
711 | { |
712 | struct dc_context *ctx = tg->ctx; |
713 | uint32_t value; |
714 | uint32_t addr; |
715 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
716 | enum test_pattern_color_format bit_depth; |
717 | enum test_pattern_dyn_range dyn_range; |
718 | enum test_pattern_mode mode; |
719 | /* color ramp generator mixes 16-bits color */ |
720 | uint32_t src_bpc = 16; |
721 | /* requested bpc */ |
722 | uint32_t dst_bpc; |
723 | uint32_t index; |
724 | /* RGB values of the color bars. |
725 | * Produce two RGB colors: RGB0 - white (all Fs) |
726 | * and RGB1 - black (all 0s) |
727 | * (three RGB components for two colors) |
728 | */ |
729 | uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, |
730 | 0x0000, 0x0000}; |
731 | /* dest color (converted to the specified color format) */ |
732 | uint16_t dst_color[6]; |
733 | uint32_t inc_base; |
734 | |
735 | /* translate to bit depth */ |
736 | switch (color_depth) { |
737 | case COLOR_DEPTH_666: |
738 | bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; |
739 | break; |
740 | case COLOR_DEPTH_888: |
741 | bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; |
742 | break; |
743 | case COLOR_DEPTH_101010: |
744 | bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; |
745 | break; |
746 | case COLOR_DEPTH_121212: |
747 | bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; |
748 | break; |
749 | default: |
750 | bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; |
751 | break; |
752 | } |
753 | |
754 | switch (test_pattern) { |
755 | case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: |
756 | case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: |
757 | { |
758 | dyn_range = (test_pattern == |
759 | CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? |
760 | TEST_PATTERN_DYN_RANGE_CEA : |
761 | TEST_PATTERN_DYN_RANGE_VESA); |
762 | mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; |
763 | value = 0; |
764 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS)(0x1bbb + tg110->offsets.crtc); |
765 | |
766 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
767 | value,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
768 | 6,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
769 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
770 | CRTC_TEST_PATTERN_VRES)(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8); |
771 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
772 | value,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
773 | 6,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
774 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
775 | CRTC_TEST_PATTERN_HRES)(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc); |
776 | |
777 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
778 | |
779 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL)(0x1bba + tg110->offsets.crtc); |
780 | value = 0; |
781 | |
782 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
783 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
784 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
785 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
786 | CRTC_TEST_PATTERN_EN)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
787 | |
788 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
789 | value,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
790 | mode,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
791 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
792 | CRTC_TEST_PATTERN_MODE)(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ); |
793 | |
794 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (dyn_range), 0x10000 , 0x10) |
795 | value,(value) = set_reg_field_value_ex( (value), (dyn_range), 0x10000 , 0x10) |
796 | dyn_range,(value) = set_reg_field_value_ex( (value), (dyn_range), 0x10000 , 0x10) |
797 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (dyn_range), 0x10000 , 0x10) |
798 | CRTC_TEST_PATTERN_DYNAMIC_RANGE)(value) = set_reg_field_value_ex( (value), (dyn_range), 0x10000 , 0x10); |
799 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
800 | value,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
801 | bit_depth,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
802 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
803 | CRTC_TEST_PATTERN_COLOR_FORMAT)(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18); |
804 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
805 | } |
806 | break; |
807 | |
808 | case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: |
809 | case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: |
810 | { |
811 | mode = (test_pattern == |
812 | CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? |
813 | TEST_PATTERN_MODE_VERTICALBARS : |
814 | TEST_PATTERN_MODE_HORIZONTALBARS); |
815 | |
816 | switch (bit_depth) { |
817 | case TEST_PATTERN_COLOR_FORMAT_BPC_6: |
818 | dst_bpc = 6; |
819 | break; |
820 | case TEST_PATTERN_COLOR_FORMAT_BPC_8: |
821 | dst_bpc = 8; |
822 | break; |
823 | case TEST_PATTERN_COLOR_FORMAT_BPC_10: |
824 | dst_bpc = 10; |
825 | break; |
826 | default: |
827 | dst_bpc = 8; |
828 | break; |
829 | } |
830 | |
831 | /* adjust color to the required colorFormat */ |
832 | for (index = 0; index < 6; index++) { |
833 | /* dst = 2^dstBpc * src / 2^srcBpc = src >> |
834 | * (srcBpc - dstBpc); |
835 | */ |
836 | dst_color[index] = |
837 | src_color[index] >> (src_bpc - dst_bpc); |
838 | /* CRTC_TEST_PATTERN_DATA has 16 bits, |
839 | * lowest 6 are hardwired to ZERO |
840 | * color bits should be left aligned aligned to MSB |
841 | * XXXXXXXXXX000000 for 10 bit, |
842 | * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 |
843 | */ |
844 | dst_color[index] <<= (16 - dst_bpc); |
845 | } |
846 | |
847 | value = 0; |
848 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS)(0x1bbb + tg110->offsets.crtc); |
849 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
850 | |
851 | /* We have to write the mask before data, similar to pipeline. |
852 | * For example, for 8 bpc, if we want RGB0 to be magenta, |
853 | * and RGB1 to be cyan, |
854 | * we need to make 7 writes: |
855 | * MASK DATA |
856 | * 000001 00000000 00000000 set mask to R0 |
857 | * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 |
858 | * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 |
859 | * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 |
860 | * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 |
861 | * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 |
862 | * 100000 11111111 00000000 B1 255, 0xFF00 |
863 | * |
864 | * we will make a loop of 6 in which we prepare the mask, |
865 | * then write, then prepare the color for next write. |
866 | * first iteration will write mask only, |
867 | * but each next iteration color prepared in |
868 | * previous iteration will be written within new mask, |
869 | * the last component will written separately, |
870 | * mask is not changing between 6th and 7th write |
871 | * and color will be prepared by last iteration |
872 | */ |
873 | |
874 | /* write color, color values mask in CRTC_TEST_PATTERN_MASK |
875 | * is B1, G1, R1, B0, G0, R0 |
876 | */ |
877 | value = 0; |
878 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR)(0x1bbc + tg110->offsets.crtc); |
879 | for (index = 0; index < 6; index++) { |
880 | /* prepare color mask, first write PATTERN_DATA |
881 | * will have all zeros |
882 | */ |
883 | set_reg_field_value((value) = set_reg_field_value_ex( (value), ((1 << index )), 0x3f0000, 0x10) |
884 | value,(value) = set_reg_field_value_ex( (value), ((1 << index )), 0x3f0000, 0x10) |
885 | (1 << index),(value) = set_reg_field_value_ex( (value), ((1 << index )), 0x3f0000, 0x10) |
886 | CRTC_TEST_PATTERN_COLOR,(value) = set_reg_field_value_ex( (value), ((1 << index )), 0x3f0000, 0x10) |
887 | CRTC_TEST_PATTERN_MASK)(value) = set_reg_field_value_ex( (value), ((1 << index )), 0x3f0000, 0x10); |
888 | /* write color component */ |
889 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
890 | /* prepare next color component, |
891 | * will be written in the next iteration |
892 | */ |
893 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (dst_color[index]) , 0xffff, 0x0) |
894 | value,(value) = set_reg_field_value_ex( (value), (dst_color[index]) , 0xffff, 0x0) |
895 | dst_color[index],(value) = set_reg_field_value_ex( (value), (dst_color[index]) , 0xffff, 0x0) |
896 | CRTC_TEST_PATTERN_COLOR,(value) = set_reg_field_value_ex( (value), (dst_color[index]) , 0xffff, 0x0) |
897 | CRTC_TEST_PATTERN_DATA)(value) = set_reg_field_value_ex( (value), (dst_color[index]) , 0xffff, 0x0); |
898 | } |
899 | /* write last color component, |
900 | * it's been already prepared in the loop |
901 | */ |
902 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
903 | |
904 | /* enable test pattern */ |
905 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL)(0x1bba + tg110->offsets.crtc); |
906 | value = 0; |
907 | |
908 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
909 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
910 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
911 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
912 | CRTC_TEST_PATTERN_EN)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
913 | |
914 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
915 | value,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
916 | mode,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
917 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
918 | CRTC_TEST_PATTERN_MODE)(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ); |
919 | |
920 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
921 | value,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
922 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
923 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
924 | CRTC_TEST_PATTERN_DYNAMIC_RANGE)(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ); |
925 | |
926 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
927 | value,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
928 | bit_depth,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
929 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
930 | CRTC_TEST_PATTERN_COLOR_FORMAT)(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18); |
931 | |
932 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
933 | } |
934 | break; |
935 | |
936 | case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: |
937 | { |
938 | mode = (bit_depth == |
939 | TEST_PATTERN_COLOR_FORMAT_BPC_10 ? |
940 | TEST_PATTERN_MODE_DUALRAMP_RGB : |
941 | TEST_PATTERN_MODE_SINGLERAMP_RGB); |
942 | |
943 | switch (bit_depth) { |
944 | case TEST_PATTERN_COLOR_FORMAT_BPC_6: |
945 | dst_bpc = 6; |
946 | break; |
947 | case TEST_PATTERN_COLOR_FORMAT_BPC_8: |
948 | dst_bpc = 8; |
949 | break; |
950 | case TEST_PATTERN_COLOR_FORMAT_BPC_10: |
951 | dst_bpc = 10; |
952 | break; |
953 | default: |
954 | dst_bpc = 8; |
955 | break; |
956 | } |
957 | |
958 | /* increment for the first ramp for one color gradation |
959 | * 1 gradation for 6-bit color is 2^10 |
960 | * gradations in 16-bit color |
961 | */ |
962 | inc_base = (src_bpc - dst_bpc); |
963 | |
964 | value = 0; |
965 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS)(0x1bbb + tg110->offsets.crtc); |
966 | |
967 | switch (bit_depth) { |
968 | case TEST_PATTERN_COLOR_FORMAT_BPC_6: |
969 | { |
970 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
971 | value,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
972 | inc_base,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
973 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
974 | CRTC_TEST_PATTERN_INC0)(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ); |
975 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
976 | value,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
977 | 0,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
978 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
979 | CRTC_TEST_PATTERN_INC1)(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4); |
980 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
981 | value,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
982 | 6,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
983 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc) |
984 | CRTC_TEST_PATTERN_HRES)(value) = set_reg_field_value_ex( (value), (6), 0xf000, 0xc); |
985 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
986 | value,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
987 | 6,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
988 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
989 | CRTC_TEST_PATTERN_VRES)(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8); |
990 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
991 | value,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
992 | 0,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
993 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
994 | CRTC_TEST_PATTERN_RAMP0_OFFSET)(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ); |
995 | } |
996 | break; |
997 | case TEST_PATTERN_COLOR_FORMAT_BPC_8: |
998 | { |
999 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1000 | value,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1001 | inc_base,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1002 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1003 | CRTC_TEST_PATTERN_INC0)(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ); |
1004 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
1005 | value,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
1006 | 0,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
1007 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4) |
1008 | CRTC_TEST_PATTERN_INC1)(value) = set_reg_field_value_ex( (value), (0), 0xf0, 0x4); |
1009 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1010 | value,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1011 | 8,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1012 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1013 | CRTC_TEST_PATTERN_HRES)(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc); |
1014 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
1015 | value,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
1016 | 6,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
1017 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8) |
1018 | CRTC_TEST_PATTERN_VRES)(value) = set_reg_field_value_ex( (value), (6), 0xf00, 0x8); |
1019 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
1020 | value,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
1021 | 0,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
1022 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ) |
1023 | CRTC_TEST_PATTERN_RAMP0_OFFSET)(value) = set_reg_field_value_ex( (value), (0), 0xffff0000, 0x10 ); |
1024 | } |
1025 | break; |
1026 | case TEST_PATTERN_COLOR_FORMAT_BPC_10: |
1027 | { |
1028 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1029 | value,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1030 | inc_base,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1031 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ) |
1032 | CRTC_TEST_PATTERN_INC0)(value) = set_reg_field_value_ex( (value), (inc_base), 0xf, 0x0 ); |
1033 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (inc_base + 2), 0xf0 , 0x4) |
1034 | value,(value) = set_reg_field_value_ex( (value), (inc_base + 2), 0xf0 , 0x4) |
1035 | inc_base + 2,(value) = set_reg_field_value_ex( (value), (inc_base + 2), 0xf0 , 0x4) |
1036 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (inc_base + 2), 0xf0 , 0x4) |
1037 | CRTC_TEST_PATTERN_INC1)(value) = set_reg_field_value_ex( (value), (inc_base + 2), 0xf0 , 0x4); |
1038 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1039 | value,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1040 | 8,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1041 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc) |
1042 | CRTC_TEST_PATTERN_HRES)(value) = set_reg_field_value_ex( (value), (8), 0xf000, 0xc); |
1043 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (5), 0xf00, 0x8) |
1044 | value,(value) = set_reg_field_value_ex( (value), (5), 0xf00, 0x8) |
1045 | 5,(value) = set_reg_field_value_ex( (value), (5), 0xf00, 0x8) |
1046 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (5), 0xf00, 0x8) |
1047 | CRTC_TEST_PATTERN_VRES)(value) = set_reg_field_value_ex( (value), (5), 0xf00, 0x8); |
1048 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (384 << 6), 0xffff0000 , 0x10) |
1049 | value,(value) = set_reg_field_value_ex( (value), (384 << 6), 0xffff0000 , 0x10) |
1050 | 384 << 6,(value) = set_reg_field_value_ex( (value), (384 << 6), 0xffff0000 , 0x10) |
1051 | CRTC_TEST_PATTERN_PARAMETERS,(value) = set_reg_field_value_ex( (value), (384 << 6), 0xffff0000 , 0x10) |
1052 | CRTC_TEST_PATTERN_RAMP0_OFFSET)(value) = set_reg_field_value_ex( (value), (384 << 6), 0xffff0000 , 0x10); |
1053 | } |
1054 | break; |
1055 | default: |
1056 | break; |
1057 | } |
1058 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1059 | |
1060 | value = 0; |
1061 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR)(0x1bbc + tg110->offsets.crtc); |
1062 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1063 | |
1064 | /* enable test pattern */ |
1065 | addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL)(0x1bba + tg110->offsets.crtc); |
1066 | value = 0; |
1067 | |
1068 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1069 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1070 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1071 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1072 | CRTC_TEST_PATTERN_EN)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
1073 | |
1074 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
1075 | value,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
1076 | mode,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
1077 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ) |
1078 | CRTC_TEST_PATTERN_MODE)(value) = set_reg_field_value_ex( (value), (mode), 0x700, 0x8 ); |
1079 | |
1080 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1081 | value,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1082 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1083 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1084 | CRTC_TEST_PATTERN_DYNAMIC_RANGE)(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ); |
1085 | /* add color depth translation here */ |
1086 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
1087 | value,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
1088 | bit_depth,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
1089 | CRTC_TEST_PATTERN_CONTROL,(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18) |
1090 | CRTC_TEST_PATTERN_COLOR_FORMAT)(value) = set_reg_field_value_ex( (value), (bit_depth), 0xff000000 , 0x18); |
1091 | |
1092 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1093 | } |
1094 | break; |
1095 | case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: |
1096 | { |
1097 | value = 0; |
1098 | dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL), value)dm_write_reg_func(ctx, (0x1bba + tg110->offsets.crtc), value , __func__); |
1099 | dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_COLOR), value)dm_write_reg_func(ctx, (0x1bbc + tg110->offsets.crtc), value , __func__); |
1100 | dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS),dm_write_reg_func(ctx, (0x1bbb + tg110->offsets.crtc), value , __func__) |
1101 | value)dm_write_reg_func(ctx, (0x1bbb + tg110->offsets.crtc), value , __func__); |
1102 | } |
1103 | break; |
1104 | default: |
1105 | break; |
1106 | } |
1107 | } |
1108 | |
1109 | /** |
1110 | * dce110_timing_generator_validate_timing |
1111 | * The timing generators support a maximum display size of is 8192 x 8192 pixels, |
1112 | * including both active display and blanking periods. Check H Total and V Total. |
1113 | */ |
1114 | bool_Bool dce110_timing_generator_validate_timing( |
1115 | struct timing_generator *tg, |
1116 | const struct dc_crtc_timing *timing, |
1117 | enum amd_signal_type signal) |
1118 | { |
1119 | uint32_t h_blank; |
1120 | uint32_t h_back_porch, hsync_offset, h_sync_start; |
1121 | |
1122 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1123 | |
1124 | ASSERT(timing != NULL)do { if (({ static int __warned; int __ret = !!(!(timing != ( (void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(timing != ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c" , 1124); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1125 | |
1126 | if (!timing) |
1127 | return false0; |
1128 | |
1129 | hsync_offset = timing->h_border_right + timing->h_front_porch; |
1130 | h_sync_start = timing->h_addressable + hsync_offset; |
1131 | |
1132 | /* Currently we don't support 3D, so block all 3D timings */ |
1133 | if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) |
1134 | return false0; |
1135 | |
1136 | /* Temporarily blocking interlacing mode until it's supported */ |
1137 | if (timing->flags.INTERLACE == 1) |
1138 | return false0; |
1139 | |
1140 | /* Check maximum number of pixels supported by Timing Generator |
1141 | * (Currently will never fail, in order to fail needs display which |
1142 | * needs more than 8192 horizontal and |
1143 | * more than 8192 vertical total pixels) |
1144 | */ |
1145 | if (timing->h_total > tg110->max_h_total || |
1146 | timing->v_total > tg110->max_v_total) |
1147 | return false0; |
1148 | |
1149 | h_blank = (timing->h_total - timing->h_addressable - |
1150 | timing->h_border_right - |
1151 | timing->h_border_left); |
1152 | |
1153 | if (h_blank < tg110->min_h_blank) |
1154 | return false0; |
1155 | |
1156 | if (timing->h_front_porch < tg110->min_h_front_porch) |
1157 | return false0; |
1158 | |
1159 | h_back_porch = h_blank - (h_sync_start - |
1160 | timing->h_addressable - |
1161 | timing->h_border_right - |
1162 | timing->h_sync_width); |
1163 | |
1164 | if (h_back_porch < tg110->min_h_back_porch) |
1165 | return false0; |
1166 | |
1167 | return true1; |
1168 | } |
1169 | |
1170 | /** |
1171 | * Wait till we are at the beginning of VBlank. |
1172 | */ |
1173 | void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg) |
1174 | { |
1175 | /* We want to catch beginning of VBlank here, so if the first try are |
1176 | * in VBlank, we might be very close to Active, in this case wait for |
1177 | * another frame |
1178 | */ |
1179 | while (dce110_timing_generator_is_in_vertical_blank(tg)) { |
1180 | if (!dce110_timing_generator_is_counter_moving(tg)) { |
1181 | /* error - no point to wait if counter is not moving */ |
1182 | break; |
1183 | } |
1184 | } |
1185 | |
1186 | while (!dce110_timing_generator_is_in_vertical_blank(tg)) { |
1187 | if (!dce110_timing_generator_is_counter_moving(tg)) { |
1188 | /* error - no point to wait if counter is not moving */ |
1189 | break; |
1190 | } |
1191 | } |
1192 | } |
1193 | |
1194 | /** |
1195 | * Wait till we are in VActive (anywhere in VActive) |
1196 | */ |
1197 | void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg) |
1198 | { |
1199 | while (dce110_timing_generator_is_in_vertical_blank(tg)) { |
1200 | if (!dce110_timing_generator_is_counter_moving(tg)) { |
1201 | /* error - no point to wait if counter is not moving */ |
1202 | break; |
1203 | } |
1204 | } |
1205 | } |
1206 | |
1207 | /** |
1208 | ***************************************************************************** |
1209 | * Function: dce110_timing_generator_setup_global_swap_lock |
1210 | * |
1211 | * @brief |
1212 | * Setups Global Swap Lock group for current pipe |
1213 | * Pipe can join or leave GSL group, become a TimingServer or TimingClient |
1214 | * |
1215 | * @param [in] gsl_params: setup data |
1216 | ***************************************************************************** |
1217 | */ |
1218 | |
1219 | void dce110_timing_generator_setup_global_swap_lock( |
1220 | struct timing_generator *tg, |
1221 | const struct dcp_gsl_params *gsl_params) |
1222 | { |
1223 | uint32_t value; |
1224 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1225 | uint32_t address = DCP_REG(mmDCP_GSL_CONTROL)(0x1a90 + tg110->offsets.dcp); |
1226 | uint32_t check_point = FLIP_READY_BACK_LOOKUP3; |
1227 | |
1228 | value = dm_read_reg(tg->ctx, address)dm_read_reg_func(tg->ctx, address, __func__); |
1229 | |
1230 | /* This pipe will belong to GSL Group zero. */ |
1231 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1232 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1233 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1234 | DCP_GSL0_EN)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
1235 | |
1236 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master == tg->inst), 0x10000, 0x10) |
1237 | gsl_params->gsl_master == tg->inst,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master == tg->inst), 0x10000, 0x10) |
1238 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master == tg->inst), 0x10000, 0x10) |
1239 | DCP_GSL_MASTER_EN)(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master == tg->inst), 0x10000, 0x10); |
1240 | |
1241 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (2), 0xf000, 0xc) |
1242 | HFLIP_READY_DELAY,(value) = set_reg_field_value_ex( (value), (2), 0xf000, 0xc) |
1243 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (2), 0xf000, 0xc) |
1244 | DCP_GSL_HSYNC_FLIP_FORCE_DELAY)(value) = set_reg_field_value_ex( (value), (2), 0xf000, 0xc); |
1245 | |
1246 | /* Keep signal low (pending high) during 6 lines. |
1247 | * Also defines minimum interval before re-checking signal. */ |
1248 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (6), 0xf0000000, 0x1c ) |
1249 | HFLIP_CHECK_DELAY,(value) = set_reg_field_value_ex( (value), (6), 0xf0000000, 0x1c ) |
1250 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (6), 0xf0000000, 0x1c ) |
1251 | DCP_GSL_HSYNC_FLIP_CHECK_DELAY)(value) = set_reg_field_value_ex( (value), (6), 0xf0000000, 0x1c ); |
1252 | |
1253 | dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value)dm_write_reg_func(tg->ctx, (0x1a90 + tg110->offsets.crtc ), value, __func__); |
1254 | value = 0; |
1255 | |
1256 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master ), 0x7, 0x0) |
1257 | gsl_params->gsl_master,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master ), 0x7, 0x0) |
1258 | DCIO_GSL0_CNTL,(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master ), 0x7, 0x0) |
1259 | DCIO_GSL0_VSYNC_SEL)(value) = set_reg_field_value_ex( (value), (gsl_params->gsl_master ), 0x7, 0x0); |
1260 | |
1261 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x700, 0x8) |
1262 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x700, 0x8) |
1263 | DCIO_GSL0_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x700, 0x8) |
1264 | DCIO_GSL0_TIMING_SYNC_SEL)(value) = set_reg_field_value_ex( (value), (0), 0x700, 0x8); |
1265 | |
1266 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x70000, 0x10 ) |
1267 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x70000, 0x10 ) |
1268 | DCIO_GSL0_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x70000, 0x10 ) |
1269 | DCIO_GSL0_GLOBAL_UNLOCK_SEL)(value) = set_reg_field_value_ex( (value), (0), 0x70000, 0x10 ); |
1270 | |
1271 | dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value)dm_write_reg_func(tg->ctx, (0x4826 + tg110->offsets.crtc ), value, __func__); |
1272 | |
1273 | |
1274 | { |
1275 | uint32_t value_crtc_vtotal; |
1276 | |
1277 | value_crtc_vtotal = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1b87 + tg110->offsets.crtc ), __func__) |
1278 | CRTC_REG(mmCRTC_V_TOTAL))dm_read_reg_func(tg->ctx, (0x1b87 + tg110->offsets.crtc ), __func__); |
1279 | |
1280 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1281 | 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1282 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1283 | DCP_GSL_SYNC_SOURCE)(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ); |
1284 | |
1285 | /* Checkpoint relative to end of frame */ |
1286 | check_point = get_reg_field_value(value_crtc_vtotal,get_reg_field_value_ex( (value_crtc_vtotal), 0x3fff, 0x0) |
1287 | CRTC_V_TOTAL,get_reg_field_value_ex( (value_crtc_vtotal), 0x3fff, 0x0) |
1288 | CRTC_V_TOTAL)get_reg_field_value_ex( (value_crtc_vtotal), 0x3fff, 0x0); |
1289 | |
1290 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0)dm_write_reg_func(tg->ctx, (0x1b7a + tg110->offsets.crtc ), 0, __func__); |
1291 | } |
1292 | |
1293 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x8000000, 0x1b ) |
1294 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x8000000, 0x1b ) |
1295 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x8000000, 0x1b ) |
1296 | DCP_GSL_DELAY_SURFACE_UPDATE_PENDING)(value) = set_reg_field_value_ex( (value), (1), 0x8000000, 0x1b ); |
1297 | |
1298 | dm_write_reg(tg->ctx, address, value)dm_write_reg_func(tg->ctx, address, value, __func__); |
1299 | |
1300 | /********************************************************************/ |
1301 | address = CRTC_REG(mmCRTC_GSL_CONTROL)(0x1b7b + tg110->offsets.crtc); |
1302 | |
1303 | value = dm_read_reg(tg->ctx, address)dm_read_reg_func(tg->ctx, address, __func__); |
1304 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (check_point - 3), 0x3fff, 0x0) |
1305 | check_point - FLIP_READY_BACK_LOOKUP,(value) = set_reg_field_value_ex( (value), (check_point - 3), 0x3fff, 0x0) |
1306 | CRTC_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (check_point - 3), 0x3fff, 0x0) |
1307 | CRTC_GSL_CHECK_LINE_NUM)(value) = set_reg_field_value_ex( (value), (check_point - 3), 0x3fff, 0x0); |
1308 | |
1309 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (4), 0x1f0000, 0x10 ) |
1310 | VFLIP_READY_DELAY,(value) = set_reg_field_value_ex( (value), (4), 0x1f0000, 0x10 ) |
1311 | CRTC_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (4), 0x1f0000, 0x10 ) |
1312 | CRTC_GSL_FORCE_DELAY)(value) = set_reg_field_value_ex( (value), (4), 0x1f0000, 0x10 ); |
1313 | |
1314 | dm_write_reg(tg->ctx, address, value)dm_write_reg_func(tg->ctx, address, value, __func__); |
1315 | } |
1316 | |
1317 | void dce110_timing_generator_tear_down_global_swap_lock( |
1318 | struct timing_generator *tg) |
1319 | { |
1320 | /* Clear all the register writes done by |
1321 | * dce110_timing_generator_setup_global_swap_lock |
1322 | */ |
1323 | |
1324 | uint32_t value; |
1325 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1326 | uint32_t address = DCP_REG(mmDCP_GSL_CONTROL)(0x1a90 + tg110->offsets.dcp); |
1327 | |
1328 | value = 0; |
1329 | |
1330 | /* This pipe will belong to GSL Group zero. */ |
1331 | /* Settig HW default values from reg specs */ |
1332 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
1333 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
1334 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
1335 | DCP_GSL0_EN)(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0); |
1336 | |
1337 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1338 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1339 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ) |
1340 | DCP_GSL_MASTER_EN)(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ); |
1341 | |
1342 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0x2), 0xf000, 0xc ) |
1343 | 0x2,(value) = set_reg_field_value_ex( (value), (0x2), 0xf000, 0xc ) |
1344 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0x2), 0xf000, 0xc ) |
1345 | DCP_GSL_HSYNC_FLIP_FORCE_DELAY)(value) = set_reg_field_value_ex( (value), (0x2), 0xf000, 0xc ); |
1346 | |
1347 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0x6), 0xf0000000, 0x1c) |
1348 | 0x6,(value) = set_reg_field_value_ex( (value), (0x6), 0xf0000000, 0x1c) |
1349 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0x6), 0xf0000000, 0x1c) |
1350 | DCP_GSL_HSYNC_FLIP_CHECK_DELAY)(value) = set_reg_field_value_ex( (value), (0x6), 0xf0000000, 0x1c); |
1351 | |
1352 | /* Restore DCP_GSL_PURPOSE_SURFACE_FLIP */ |
1353 | { |
1354 | uint32_t value_crtc_vtotal; |
1355 | |
1356 | value_crtc_vtotal = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1b87 + tg110->offsets.crtc ), __func__) |
Value stored to 'value_crtc_vtotal' is never read | |
1357 | CRTC_REG(mmCRTC_V_TOTAL))dm_read_reg_func(tg->ctx, (0x1b87 + tg110->offsets.crtc ), __func__); |
1358 | |
1359 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1360 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1361 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ) |
1362 | DCP_GSL_SYNC_SOURCE)(value) = set_reg_field_value_ex( (value), (0), 0x3000000, 0x18 ); |
1363 | } |
1364 | |
1365 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x8000000, 0x1b ) |
1366 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x8000000, 0x1b ) |
1367 | DCP_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x8000000, 0x1b ) |
1368 | DCP_GSL_DELAY_SURFACE_UPDATE_PENDING)(value) = set_reg_field_value_ex( (value), (0), 0x8000000, 0x1b ); |
1369 | |
1370 | dm_write_reg(tg->ctx, address, value)dm_write_reg_func(tg->ctx, address, value, __func__); |
1371 | |
1372 | /********************************************************************/ |
1373 | address = CRTC_REG(mmCRTC_GSL_CONTROL)(0x1b7b + tg110->offsets.crtc); |
1374 | |
1375 | value = 0; |
1376 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
1377 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
1378 | CRTC_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
1379 | CRTC_GSL_CHECK_LINE_NUM)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0); |
1380 | |
1381 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0x2), 0x1f0000, 0x10 ) |
1382 | 0x2,(value) = set_reg_field_value_ex( (value), (0x2), 0x1f0000, 0x10 ) |
1383 | CRTC_GSL_CONTROL,(value) = set_reg_field_value_ex( (value), (0x2), 0x1f0000, 0x10 ) |
1384 | CRTC_GSL_FORCE_DELAY)(value) = set_reg_field_value_ex( (value), (0x2), 0x1f0000, 0x10 ); |
1385 | |
1386 | dm_write_reg(tg->ctx, address, value)dm_write_reg_func(tg->ctx, address, value, __func__); |
1387 | } |
1388 | /** |
1389 | ***************************************************************************** |
1390 | * Function: is_counter_moving |
1391 | * |
1392 | * @brief |
1393 | * check if the timing generator is currently going |
1394 | * |
1395 | * @return |
1396 | * true if currently going, false if currently paused or stopped. |
1397 | * |
1398 | ***************************************************************************** |
1399 | */ |
1400 | bool_Bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg) |
1401 | { |
1402 | struct crtc_position position1, position2; |
1403 | |
1404 | tg->funcs->get_position(tg, &position1); |
1405 | tg->funcs->get_position(tg, &position2); |
1406 | |
1407 | if (position1.horizontal_count == position2.horizontal_count && |
1408 | position1.vertical_count == position2.vertical_count) |
1409 | return false0; |
1410 | else |
1411 | return true1; |
1412 | } |
1413 | |
1414 | void dce110_timing_generator_enable_advanced_request( |
1415 | struct timing_generator *tg, |
1416 | bool_Bool enable, |
1417 | const struct dc_crtc_timing *timing) |
1418 | { |
1419 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1420 | uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL)(0x1bb3 + tg110->offsets.crtc); |
1421 | uint32_t value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
1422 | |
1423 | if (enable) { |
1424 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1425 | value,(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1426 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1427 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1428 | CRTC_LEGACY_REQUESTOR_EN)(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8); |
1429 | } else { |
1430 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1431 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1432 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1433 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1434 | CRTC_LEGACY_REQUESTOR_EN)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1435 | } |
1436 | |
1437 | if ((timing->v_sync_width + timing->v_front_porch) <= 3) { |
1438 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (3), 0xff000, 0xc) |
1439 | value,(value) = set_reg_field_value_ex( (value), (3), 0xff000, 0xc) |
1440 | 3,(value) = set_reg_field_value_ex( (value), (3), 0xff000, 0xc) |
1441 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (3), 0xff000, 0xc) |
1442 | CRTC_ADVANCED_START_LINE_POSITION)(value) = set_reg_field_value_ex( (value), (3), 0xff000, 0xc); |
1443 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x4, 0x2) |
1444 | value,(value) = set_reg_field_value_ex( (value), (0), 0x4, 0x2) |
1445 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x4, 0x2) |
1446 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x4, 0x2) |
1447 | CRTC_PREFETCH_EN)(value) = set_reg_field_value_ex( (value), (0), 0x4, 0x2); |
1448 | } else { |
1449 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (4), 0xff000, 0xc) |
1450 | value,(value) = set_reg_field_value_ex( (value), (4), 0xff000, 0xc) |
1451 | 4,(value) = set_reg_field_value_ex( (value), (4), 0xff000, 0xc) |
1452 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (4), 0xff000, 0xc) |
1453 | CRTC_ADVANCED_START_LINE_POSITION)(value) = set_reg_field_value_ex( (value), (4), 0xff000, 0xc); |
1454 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x4, 0x2) |
1455 | value,(value) = set_reg_field_value_ex( (value), (1), 0x4, 0x2) |
1456 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x4, 0x2) |
1457 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x4, 0x2) |
1458 | CRTC_PREFETCH_EN)(value) = set_reg_field_value_ex( (value), (1), 0x4, 0x2); |
1459 | } |
1460 | |
1461 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1462 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1463 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1464 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
1465 | CRTC_PROGRESSIVE_START_LINE_EARLY)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
1466 | |
1467 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x2, 0x1) |
1468 | value,(value) = set_reg_field_value_ex( (value), (1), 0x2, 0x1) |
1469 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x2, 0x1) |
1470 | CRTC_START_LINE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x2, 0x1) |
1471 | CRTC_INTERLACE_START_LINE_EARLY)(value) = set_reg_field_value_ex( (value), (1), 0x2, 0x1); |
1472 | |
1473 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
1474 | } |
1475 | |
1476 | /*TODO: Figure out if we need this function. */ |
1477 | void dce110_timing_generator_set_lock_master(struct timing_generator *tg, |
1478 | bool_Bool lock) |
1479 | { |
1480 | struct dc_context *ctx = tg->ctx; |
1481 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1482 | uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK)(0x1bbd + tg110->offsets.crtc); |
1483 | uint32_t value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
1484 | |
1485 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (lock ? 1 : 0), 0x1 , 0x0) |
1486 | value,(value) = set_reg_field_value_ex( (value), (lock ? 1 : 0), 0x1 , 0x0) |
1487 | lock ? 1 : 0,(value) = set_reg_field_value_ex( (value), (lock ? 1 : 0), 0x1 , 0x0) |
1488 | CRTC_MASTER_UPDATE_LOCK,(value) = set_reg_field_value_ex( (value), (lock ? 1 : 0), 0x1 , 0x0) |
1489 | MASTER_UPDATE_LOCK)(value) = set_reg_field_value_ex( (value), (lock ? 1 : 0), 0x1 , 0x0); |
1490 | |
1491 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1492 | } |
1493 | |
1494 | void dce110_timing_generator_enable_reset_trigger( |
1495 | struct timing_generator *tg, |
1496 | int source_tg_inst) |
1497 | { |
1498 | uint32_t value; |
1499 | uint32_t rising_edge = 0; |
1500 | uint32_t falling_edge = 0; |
1501 | enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO; |
1502 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1503 | |
1504 | /* Setup trigger edge */ |
1505 | { |
1506 | uint32_t pol_value = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1b8f + tg110->offsets.crtc ), __func__) |
1507 | CRTC_REG(mmCRTC_V_SYNC_A_CNTL))dm_read_reg_func(tg->ctx, (0x1b8f + tg110->offsets.crtc ), __func__); |
1508 | |
1509 | /* Register spec has reversed definition: |
1510 | * 0 for positive, 1 for negative */ |
1511 | if (get_reg_field_value(pol_value,get_reg_field_value_ex( (pol_value), 0x1, 0x0) |
1512 | CRTC_V_SYNC_A_CNTL,get_reg_field_value_ex( (pol_value), 0x1, 0x0) |
1513 | CRTC_V_SYNC_A_POL)get_reg_field_value_ex( (pol_value), 0x1, 0x0) == 0) { |
1514 | rising_edge = 1; |
1515 | } else { |
1516 | falling_edge = 1; |
1517 | } |
1518 | } |
1519 | |
1520 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL))dm_read_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), __func__); |
1521 | |
1522 | trig_src_select = TRIGGER_SOURCE_SELECT_GSL_GROUP0; |
1523 | |
1524 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (trig_src_select), 0x1f, 0x0) |
1525 | trig_src_select,(value) = set_reg_field_value_ex( (value), (trig_src_select), 0x1f, 0x0) |
1526 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (trig_src_select), 0x1f, 0x0) |
1527 | CRTC_TRIGB_SOURCE_SELECT)(value) = set_reg_field_value_ex( (value), (trig_src_select), 0x1f, 0x0); |
1528 | |
1529 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1530 | TRIGGER_POLARITY_SELECT_LOGIC_ZERO,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1531 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1532 | CRTC_TRIGB_POLARITY_SELECT)(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5); |
1533 | |
1534 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1535 | rising_edge,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1536 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1537 | CRTC_TRIGB_RISING_EDGE_DETECT_CNTL)(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc); |
1538 | |
1539 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1540 | falling_edge,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1541 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1542 | CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL)(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10); |
1543 | |
1544 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x300000, 0x14 ) |
1545 | 0, /* send every signal */(value) = set_reg_field_value_ex( (value), (0), 0x300000, 0x14 ) |
1546 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x300000, 0x14 ) |
1547 | CRTC_TRIGB_FREQUENCY_SELECT)(value) = set_reg_field_value_ex( (value), (0), 0x300000, 0x14 ); |
1548 | |
1549 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x1f000000, 0x18 ) |
1550 | 0, /* no delay */(value) = set_reg_field_value_ex( (value), (0), 0x1f000000, 0x18 ) |
1551 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x1f000000, 0x18 ) |
1552 | CRTC_TRIGB_DELAY)(value) = set_reg_field_value_ex( (value), (0), 0x1f000000, 0x18 ); |
1553 | |
1554 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1555 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1556 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1557 | CRTC_TRIGB_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ); |
1558 | |
1559 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), value, __func__); |
1560 | |
1561 | /**************************************************************/ |
1562 | |
1563 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL))dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__); |
1564 | |
1565 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1566 | 2, /* force H count to H_TOTAL and V count to V_TOTAL */(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1567 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1568 | CRTC_FORCE_COUNT_NOW_MODE)(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0); |
1569 | |
1570 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1571 | 1, /* TriggerB - we never use TriggerA */(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1572 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1573 | CRTC_FORCE_COUNT_NOW_TRIG_SEL)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1574 | |
1575 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1576 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1577 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1578 | CRTC_FORCE_COUNT_NOW_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ); |
1579 | |
1580 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), value, __func__); |
1581 | } |
1582 | |
1583 | void dce110_timing_generator_enable_crtc_reset( |
1584 | struct timing_generator *tg, |
1585 | int source_tg_inst, |
1586 | struct crtc_trigger_info *crtc_tp) |
1587 | { |
1588 | uint32_t value = 0; |
1589 | uint32_t rising_edge = 0; |
1590 | uint32_t falling_edge = 0; |
1591 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1592 | |
1593 | /* Setup trigger edge */ |
1594 | switch (crtc_tp->event) { |
1595 | case CRTC_EVENT_VSYNC_RISING: |
1596 | rising_edge = 1; |
1597 | break; |
1598 | |
1599 | case CRTC_EVENT_VSYNC_FALLING: |
1600 | falling_edge = 1; |
1601 | break; |
1602 | } |
1603 | |
1604 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL))dm_read_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), __func__); |
1605 | |
1606 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (source_tg_inst), 0x1f , 0x0) |
1607 | source_tg_inst,(value) = set_reg_field_value_ex( (value), (source_tg_inst), 0x1f , 0x0) |
1608 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (source_tg_inst), 0x1f , 0x0) |
1609 | CRTC_TRIGB_SOURCE_SELECT)(value) = set_reg_field_value_ex( (value), (source_tg_inst), 0x1f , 0x0); |
1610 | |
1611 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1612 | TRIGGER_POLARITY_SELECT_LOGIC_ZERO,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1613 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1614 | CRTC_TRIGB_POLARITY_SELECT)(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5); |
1615 | |
1616 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1617 | rising_edge,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1618 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc) |
1619 | CRTC_TRIGB_RISING_EDGE_DETECT_CNTL)(value) = set_reg_field_value_ex( (value), (rising_edge), 0x3000 , 0xc); |
1620 | |
1621 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1622 | falling_edge,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1623 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10) |
1624 | CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL)(value) = set_reg_field_value_ex( (value), (falling_edge), 0x30000 , 0x10); |
1625 | |
1626 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1627 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1628 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1629 | CRTC_TRIGB_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ); |
1630 | |
1631 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), value, __func__); |
1632 | |
1633 | /**************************************************************/ |
1634 | |
1635 | switch (crtc_tp->delay) { |
1636 | case TRIGGER_DELAY_NEXT_LINE: |
1637 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL))dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__); |
1638 | |
1639 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1640 | 0, /* force H count to H_TOTAL and V count to V_TOTAL */(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1641 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1642 | CRTC_FORCE_COUNT_NOW_MODE)(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0); |
1643 | |
1644 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1645 | 0, /* TriggerB - we never use TriggerA */(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1646 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8) |
1647 | CRTC_FORCE_COUNT_NOW_TRIG_SEL)(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8); |
1648 | |
1649 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1650 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1651 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1652 | CRTC_FORCE_COUNT_NOW_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ); |
1653 | |
1654 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), value, __func__); |
1655 | |
1656 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL))dm_read_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), __func__); |
1657 | |
1658 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1659 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1660 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1661 | CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1662 | |
1663 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
1664 | 2,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
1665 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
1666 | CRTC_AUTO_FORCE_VSYNC_MODE)(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ); |
1667 | |
1668 | break; |
1669 | |
1670 | case TRIGGER_DELAY_NEXT_PIXEL: |
1671 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL))dm_read_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), __func__); |
1672 | |
1673 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1674 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1675 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1676 | CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1677 | |
1678 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1679 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1680 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1681 | CRTC_AUTO_FORCE_VSYNC_MODE)(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ); |
1682 | |
1683 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value)dm_write_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), value, __func__); |
1684 | |
1685 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL))dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__); |
1686 | |
1687 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1688 | 2, /* force H count to H_TOTAL and V count to V_TOTAL */(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1689 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0) |
1690 | CRTC_FORCE_COUNT_NOW_MODE)(value) = set_reg_field_value_ex( (value), (2), 0x3, 0x0); |
1691 | |
1692 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1693 | 1, /* TriggerB - we never use TriggerA */(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1694 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1695 | CRTC_FORCE_COUNT_NOW_TRIG_SEL)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1696 | |
1697 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1698 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1699 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1700 | CRTC_FORCE_COUNT_NOW_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ); |
1701 | |
1702 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), value, __func__); |
1703 | break; |
1704 | } |
1705 | |
1706 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE))dm_read_reg_func(tg->ctx, (0x1bbe + tg110->offsets.crtc ), __func__); |
1707 | |
1708 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0) |
1709 | 2,(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0) |
1710 | CRTC_MASTER_UPDATE_MODE,(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0) |
1711 | MASTER_UPDATE_MODE)(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0); |
1712 | |
1713 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value)dm_write_reg_func(tg->ctx, (0x1bbe + tg110->offsets.crtc ), value, __func__); |
1714 | } |
1715 | void dce110_timing_generator_disable_reset_trigger( |
1716 | struct timing_generator *tg) |
1717 | { |
1718 | uint32_t value; |
1719 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1720 | |
1721 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL))dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__); |
1722 | |
1723 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1724 | 0, /* force counter now mode is disabled */(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1725 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0) |
1726 | CRTC_FORCE_COUNT_NOW_MODE)(value) = set_reg_field_value_ex( (value), (0), 0x3, 0x0); |
1727 | |
1728 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1729 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1730 | CRTC_FORCE_COUNT_NOW_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ) |
1731 | CRTC_FORCE_COUNT_NOW_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x1000000, 0x18 ); |
1732 | |
1733 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), value, __func__); |
1734 | |
1735 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL))dm_read_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), __func__); |
1736 | |
1737 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1738 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1739 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
1740 | CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
1741 | |
1742 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1743 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1744 | CRTC_VERT_SYNC_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ) |
1745 | CRTC_AUTO_FORCE_VSYNC_MODE)(value) = set_reg_field_value_ex( (value), (0), 0x30000, 0x10 ); |
1746 | |
1747 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value)dm_write_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), value, __func__); |
1748 | |
1749 | /********************************************************************/ |
1750 | value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL))dm_read_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), __func__); |
1751 | |
1752 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (TRIGGER_SOURCE_SELECT_LOGIC_ZERO ), 0x1f, 0x0) |
1753 | TRIGGER_SOURCE_SELECT_LOGIC_ZERO,(value) = set_reg_field_value_ex( (value), (TRIGGER_SOURCE_SELECT_LOGIC_ZERO ), 0x1f, 0x0) |
1754 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (TRIGGER_SOURCE_SELECT_LOGIC_ZERO ), 0x1f, 0x0) |
1755 | CRTC_TRIGB_SOURCE_SELECT)(value) = set_reg_field_value_ex( (value), (TRIGGER_SOURCE_SELECT_LOGIC_ZERO ), 0x1f, 0x0); |
1756 | |
1757 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1758 | TRIGGER_POLARITY_SELECT_LOGIC_ZERO,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1759 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5) |
1760 | CRTC_TRIGB_POLARITY_SELECT)(value) = set_reg_field_value_ex( (value), (TRIGGER_POLARITY_SELECT_LOGIC_ZERO ), 0xe0, 0x5); |
1761 | |
1762 | set_reg_field_value(value,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1763 | 1, /* clear trigger status */(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1764 | CRTC_TRIGB_CNTL,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
1765 | CRTC_TRIGB_CLEAR)(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ); |
1766 | |
1767 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value)dm_write_reg_func(tg->ctx, (0x1b96 + tg110->offsets.crtc ), value, __func__); |
1768 | } |
1769 | |
1770 | /** |
1771 | ***************************************************************************** |
1772 | * @brief |
1773 | * Checks whether CRTC triggered reset occurred |
1774 | * |
1775 | * @return |
1776 | * true if triggered reset occurred, false otherwise |
1777 | ***************************************************************************** |
1778 | */ |
1779 | bool_Bool dce110_timing_generator_did_triggered_reset_occur( |
1780 | struct timing_generator *tg) |
1781 | { |
1782 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1783 | uint32_t value = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__) |
1784 | CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL))dm_read_reg_func(tg->ctx, (0x1b98 + tg110->offsets.crtc ), __func__); |
1785 | uint32_t value1 = dm_read_reg(tg->ctx,dm_read_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), __func__) |
1786 | CRTC_REG(mmCRTC_VERT_SYNC_CONTROL))dm_read_reg_func(tg->ctx, (0x1bac + tg110->offsets.crtc ), __func__); |
1787 | bool_Bool force = get_reg_field_value(value,get_reg_field_value_ex( (value), 0x10000, 0x10) |
1788 | CRTC_FORCE_COUNT_NOW_CNTL,get_reg_field_value_ex( (value), 0x10000, 0x10) |
1789 | CRTC_FORCE_COUNT_NOW_OCCURRED)get_reg_field_value_ex( (value), 0x10000, 0x10) != 0; |
1790 | bool_Bool vert_sync = get_reg_field_value(value1,get_reg_field_value_ex( (value1), 0x1, 0x0) |
1791 | CRTC_VERT_SYNC_CONTROL,get_reg_field_value_ex( (value1), 0x1, 0x0) |
1792 | CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED)get_reg_field_value_ex( (value1), 0x1, 0x0) != 0; |
1793 | |
1794 | return (force || vert_sync); |
1795 | } |
1796 | |
1797 | /** |
1798 | * dce110_timing_generator_disable_vga |
1799 | * Turn OFF VGA Mode and Timing - DxVGA_CONTROL |
1800 | * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors; |
1801 | */ |
1802 | void dce110_timing_generator_disable_vga( |
1803 | struct timing_generator *tg) |
1804 | { |
1805 | uint32_t addr = 0; |
1806 | uint32_t value = 0; |
1807 | |
1808 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1809 | |
1810 | switch (tg110->controller_id) { |
1811 | case CONTROLLER_ID_D0: |
1812 | addr = mmD1VGA_CONTROL0xcc; |
1813 | break; |
1814 | case CONTROLLER_ID_D1: |
1815 | addr = mmD2VGA_CONTROL0xce; |
1816 | break; |
1817 | case CONTROLLER_ID_D2: |
1818 | addr = mmD3VGA_CONTROL0xf8; |
1819 | break; |
1820 | case CONTROLLER_ID_D3: |
1821 | addr = mmD4VGA_CONTROL0xf9; |
1822 | break; |
1823 | case CONTROLLER_ID_D4: |
1824 | addr = mmD5VGA_CONTROL0xfa; |
1825 | break; |
1826 | case CONTROLLER_ID_D5: |
1827 | addr = mmD6VGA_CONTROL0xfb; |
1828 | break; |
1829 | default: |
1830 | break; |
1831 | } |
1832 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
1833 | |
1834 | set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE)(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0); |
1835 | set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT)(value) = set_reg_field_value_ex( (value), (0), 0x100, 0x8); |
1836 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x200, 0x9) |
1837 | value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT)(value) = set_reg_field_value_ex( (value), (0), 0x200, 0x9); |
1838 | set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN)(value) = set_reg_field_value_ex( (value), (0), 0x10000, 0x10 ); |
1839 | |
1840 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
1841 | } |
1842 | |
1843 | /** |
1844 | * set_overscan_color_black |
1845 | * |
1846 | * @param :black_color is one of the color space |
1847 | * :this routine will set overscan black color according to the color space. |
1848 | * @return none |
1849 | */ |
1850 | |
1851 | void dce110_timing_generator_set_overscan_color_black( |
1852 | struct timing_generator *tg, |
1853 | const struct tg_color *color) |
1854 | { |
1855 | struct dc_context *ctx = tg->ctx; |
1856 | uint32_t addr; |
1857 | uint32_t value = 0; |
1858 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1859 | |
1860 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (color->color_b_cb ), 0x3ff, 0x0) |
1861 | value,(value) = set_reg_field_value_ex( (value), (color->color_b_cb ), 0x3ff, 0x0) |
1862 | color->color_b_cb,(value) = set_reg_field_value_ex( (value), (color->color_b_cb ), 0x3ff, 0x0) |
1863 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (color->color_b_cb ), 0x3ff, 0x0) |
1864 | CRTC_OVERSCAN_COLOR_BLUE)(value) = set_reg_field_value_ex( (value), (color->color_b_cb ), 0x3ff, 0x0); |
1865 | |
1866 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (color->color_r_cr ), 0x3ff00000, 0x14) |
1867 | value,(value) = set_reg_field_value_ex( (value), (color->color_r_cr ), 0x3ff00000, 0x14) |
1868 | color->color_r_cr,(value) = set_reg_field_value_ex( (value), (color->color_r_cr ), 0x3ff00000, 0x14) |
1869 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (color->color_r_cr ), 0x3ff00000, 0x14) |
1870 | CRTC_OVERSCAN_COLOR_RED)(value) = set_reg_field_value_ex( (value), (color->color_r_cr ), 0x3ff00000, 0x14); |
1871 | |
1872 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (color->color_g_y ), 0xffc00, 0xa) |
1873 | value,(value) = set_reg_field_value_ex( (value), (color->color_g_y ), 0xffc00, 0xa) |
1874 | color->color_g_y,(value) = set_reg_field_value_ex( (value), (color->color_g_y ), 0xffc00, 0xa) |
1875 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (color->color_g_y ), 0xffc00, 0xa) |
1876 | CRTC_OVERSCAN_COLOR_GREEN)(value) = set_reg_field_value_ex( (value), (color->color_g_y ), 0xffc00, 0xa); |
1877 | |
1878 | addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR)(0x1bc8 + tg110->offsets.crtc); |
1879 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1880 | addr = CRTC_REG(mmCRTC_BLACK_COLOR)(0x1bcc + tg110->offsets.crtc); |
1881 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1882 | /* This is desirable to have a constant DAC output voltage during the |
1883 | * blank time that is higher than the 0 volt reference level that the |
1884 | * DAC outputs when the NBLANK signal |
1885 | * is asserted low, such as for output to an analog TV. */ |
1886 | addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR)(0x1bca + tg110->offsets.crtc); |
1887 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1888 | |
1889 | /* TO DO we have to program EXT registers and we need to know LB DATA |
1890 | * format because it is used when more 10 , i.e. 12 bits per color |
1891 | * |
1892 | * m_mmDxCRTC_OVERSCAN_COLOR_EXT |
1893 | * m_mmDxCRTC_BLACK_COLOR_EXT |
1894 | * m_mmDxCRTC_BLANK_DATA_COLOR_EXT |
1895 | */ |
1896 | |
1897 | } |
1898 | |
1899 | void dce110_tg_program_blank_color(struct timing_generator *tg, |
1900 | const struct tg_color *black_color) |
1901 | { |
1902 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1903 | uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR)(0x1bcc + tg110->offsets.crtc); |
1904 | uint32_t value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
1905 | |
1906 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
1907 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
1908 | black_color->color_b_cb,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
1909 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0) |
1910 | CRTC_BLACK_COLOR_B_CB)(value) = set_reg_field_value_ex( (value), (black_color->color_b_cb ), 0x3ff, 0x0); |
1911 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
1912 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
1913 | black_color->color_g_y,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
1914 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa) |
1915 | CRTC_BLACK_COLOR_G_Y)(value) = set_reg_field_value_ex( (value), (black_color->color_g_y ), 0xffc00, 0xa); |
1916 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
1917 | value,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
1918 | black_color->color_r_cr,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
1919 | CRTC_BLACK_COLOR,(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14) |
1920 | CRTC_BLACK_COLOR_R_CR)(value) = set_reg_field_value_ex( (value), (black_color->color_r_cr ), 0x3ff00000, 0x14); |
1921 | |
1922 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
1923 | |
1924 | addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR)(0x1bca + tg110->offsets.crtc); |
1925 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
1926 | } |
1927 | |
1928 | void dce110_tg_set_overscan_color(struct timing_generator *tg, |
1929 | const struct tg_color *overscan_color) |
1930 | { |
1931 | struct dc_context *ctx = tg->ctx; |
1932 | uint32_t value = 0; |
1933 | uint32_t addr; |
1934 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1935 | |
1936 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (overscan_color-> color_b_cb), 0x3ff, 0x0) |
1937 | value,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_b_cb), 0x3ff, 0x0) |
1938 | overscan_color->color_b_cb,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_b_cb), 0x3ff, 0x0) |
1939 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_b_cb), 0x3ff, 0x0) |
1940 | CRTC_OVERSCAN_COLOR_BLUE)(value) = set_reg_field_value_ex( (value), (overscan_color-> color_b_cb), 0x3ff, 0x0); |
1941 | |
1942 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (overscan_color-> color_g_y), 0xffc00, 0xa) |
1943 | value,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_g_y), 0xffc00, 0xa) |
1944 | overscan_color->color_g_y,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_g_y), 0xffc00, 0xa) |
1945 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_g_y), 0xffc00, 0xa) |
1946 | CRTC_OVERSCAN_COLOR_GREEN)(value) = set_reg_field_value_ex( (value), (overscan_color-> color_g_y), 0xffc00, 0xa); |
1947 | |
1948 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (overscan_color-> color_r_cr), 0x3ff00000, 0x14) |
1949 | value,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_r_cr), 0x3ff00000, 0x14) |
1950 | overscan_color->color_r_cr,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_r_cr), 0x3ff00000, 0x14) |
1951 | CRTC_OVERSCAN_COLOR,(value) = set_reg_field_value_ex( (value), (overscan_color-> color_r_cr), 0x3ff00000, 0x14) |
1952 | CRTC_OVERSCAN_COLOR_RED)(value) = set_reg_field_value_ex( (value), (overscan_color-> color_r_cr), 0x3ff00000, 0x14); |
1953 | |
1954 | addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR)(0x1bc8 + tg110->offsets.crtc); |
1955 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
1956 | } |
1957 | |
1958 | void dce110_tg_program_timing(struct timing_generator *tg, |
1959 | const struct dc_crtc_timing *timing, |
1960 | int vready_offset, |
1961 | int vstartup_start, |
1962 | int vupdate_offset, |
1963 | int vupdate_width, |
1964 | const enum amd_signal_type signal, |
1965 | bool_Bool use_vbios) |
1966 | { |
1967 | if (use_vbios) |
1968 | dce110_timing_generator_program_timing_generator(tg, timing); |
1969 | else |
1970 | dce110_timing_generator_program_blanking(tg, timing); |
1971 | } |
1972 | |
1973 | bool_Bool dce110_tg_is_blanked(struct timing_generator *tg) |
1974 | { |
1975 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1976 | uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL))dm_read_reg_func(tg->ctx, (0x1b9d + tg110->offsets.crtc ), __func__); |
1977 | |
1978 | if (get_reg_field_value(get_reg_field_value_ex( (value), 0x100, 0x8) |
1979 | value,get_reg_field_value_ex( (value), 0x100, 0x8) |
1980 | CRTC_BLANK_CONTROL,get_reg_field_value_ex( (value), 0x100, 0x8) |
1981 | CRTC_BLANK_DATA_EN)get_reg_field_value_ex( (value), 0x100, 0x8) == 1 && |
1982 | get_reg_field_value(get_reg_field_value_ex( (value), 0x1, 0x0) |
1983 | value,get_reg_field_value_ex( (value), 0x1, 0x0) |
1984 | CRTC_BLANK_CONTROL,get_reg_field_value_ex( (value), 0x1, 0x0) |
1985 | CRTC_CURRENT_BLANK_STATE)get_reg_field_value_ex( (value), 0x1, 0x0) == 1) |
1986 | return true1; |
1987 | return false0; |
1988 | } |
1989 | |
1990 | void dce110_tg_set_blank(struct timing_generator *tg, |
1991 | bool_Bool enable_blanking) |
1992 | { |
1993 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
1994 | uint32_t value = 0; |
1995 | |
1996 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x10000, 0x10 ) |
1997 | value,(value) = set_reg_field_value_ex( (value), (1), 0x10000, 0x10 ) |
1998 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x10000, 0x10 ) |
1999 | CRTC_DOUBLE_BUFFER_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x10000, 0x10 ) |
2000 | CRTC_BLANK_DATA_DOUBLE_BUFFER_EN)(value) = set_reg_field_value_ex( (value), (1), 0x10000, 0x10 ); |
2001 | |
2002 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_DOUBLE_BUFFER_CONTROL), value)dm_write_reg_func(tg->ctx, (0x1bb6 + tg110->offsets.crtc ), value, __func__); |
2003 | value = 0; |
2004 | |
2005 | if (enable_blanking) { |
2006 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
2007 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
2008 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
2009 | CRTC_BLANK_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
2010 | CRTC_BLANK_DATA_EN)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
2011 | |
2012 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), value)dm_write_reg_func(tg->ctx, (0x1b9d + tg110->offsets.crtc ), value, __func__); |
2013 | |
2014 | } else |
2015 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), 0)dm_write_reg_func(tg->ctx, (0x1b9d + tg110->offsets.crtc ), 0, __func__); |
2016 | } |
2017 | |
2018 | bool_Bool dce110_tg_validate_timing(struct timing_generator *tg, |
2019 | const struct dc_crtc_timing *timing) |
2020 | { |
2021 | return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); |
2022 | } |
2023 | |
2024 | void dce110_tg_wait_for_state(struct timing_generator *tg, |
2025 | enum crtc_state state) |
2026 | { |
2027 | switch (state) { |
2028 | case CRTC_STATE_VBLANK: |
2029 | dce110_timing_generator_wait_for_vblank(tg); |
2030 | break; |
2031 | |
2032 | case CRTC_STATE_VACTIVE: |
2033 | dce110_timing_generator_wait_for_vactive(tg); |
2034 | break; |
2035 | |
2036 | default: |
2037 | break; |
2038 | } |
2039 | } |
2040 | |
2041 | void dce110_tg_set_colors(struct timing_generator *tg, |
2042 | const struct tg_color *blank_color, |
2043 | const struct tg_color *overscan_color) |
2044 | { |
2045 | if (blank_color != NULL((void *)0)) |
2046 | dce110_tg_program_blank_color(tg, blank_color); |
2047 | if (overscan_color != NULL((void *)0)) |
2048 | dce110_tg_set_overscan_color(tg, overscan_color); |
2049 | } |
2050 | |
2051 | /* Gets first line of blank region of the display timing for CRTC |
2052 | * and programms is as a trigger to fire vertical interrupt |
2053 | */ |
2054 | bool_Bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width) |
2055 | { |
2056 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
2057 | uint32_t v_blank_start = 0; |
2058 | uint32_t v_blank_end = 0; |
2059 | uint32_t val = 0; |
2060 | uint32_t h_position, v_position; |
2061 | |
2062 | tg->funcs->get_scanoutpos( |
2063 | tg, |
2064 | &v_blank_start, |
2065 | &v_blank_end, |
2066 | &h_position, |
2067 | &v_position); |
2068 | |
2069 | if (v_blank_start == 0 || v_blank_end == 0) |
2070 | return false0; |
2071 | |
2072 | set_reg_field_value((val) = set_reg_field_value_ex( (val), (v_blank_start), 0x3fff , 0x0) |
2073 | val,(val) = set_reg_field_value_ex( (val), (v_blank_start), 0x3fff , 0x0) |
2074 | v_blank_start,(val) = set_reg_field_value_ex( (val), (v_blank_start), 0x3fff , 0x0) |
2075 | CRTC_VERTICAL_INTERRUPT0_POSITION,(val) = set_reg_field_value_ex( (val), (v_blank_start), 0x3fff , 0x0) |
2076 | CRTC_VERTICAL_INTERRUPT0_LINE_START)(val) = set_reg_field_value_ex( (val), (v_blank_start), 0x3fff , 0x0); |
2077 | |
2078 | /* Set interval width for interrupt to fire to 1 scanline */ |
2079 | set_reg_field_value((val) = set_reg_field_value_ex( (val), (v_blank_start + width ), 0x3fff0000, 0x10) |
2080 | val,(val) = set_reg_field_value_ex( (val), (v_blank_start + width ), 0x3fff0000, 0x10) |
2081 | v_blank_start + width,(val) = set_reg_field_value_ex( (val), (v_blank_start + width ), 0x3fff0000, 0x10) |
2082 | CRTC_VERTICAL_INTERRUPT0_POSITION,(val) = set_reg_field_value_ex( (val), (v_blank_start + width ), 0x3fff0000, 0x10) |
2083 | CRTC_VERTICAL_INTERRUPT0_LINE_END)(val) = set_reg_field_value_ex( (val), (v_blank_start + width ), 0x3fff0000, 0x10); |
2084 | |
2085 | dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val)dm_write_reg_func(tg->ctx, (0x1bce + tg110->offsets.crtc ), val, __func__); |
2086 | |
2087 | return true1; |
2088 | } |
2089 | |
2090 | static bool_Bool dce110_is_tg_enabled(struct timing_generator *tg) |
2091 | { |
2092 | uint32_t addr = 0; |
2093 | uint32_t value = 0; |
2094 | uint32_t field = 0; |
2095 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
2096 | |
2097 | addr = CRTC_REG(mmCRTC_CONTROL)(0x1b9c + tg110->offsets.crtc); |
2098 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
2099 | field = get_reg_field_value(value, CRTC_CONTROL,get_reg_field_value_ex( (value), 0x10000, 0x10) |
2100 | CRTC_CURRENT_MASTER_EN_STATE)get_reg_field_value_ex( (value), 0x10000, 0x10); |
2101 | return field == 1; |
2102 | } |
2103 | |
2104 | bool_Bool dce110_configure_crc(struct timing_generator *tg, |
2105 | const struct crc_params *params) |
2106 | { |
2107 | uint32_t cntl_addr = 0; |
2108 | uint32_t addr = 0; |
2109 | uint32_t value; |
2110 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
2111 | |
2112 | /* Cannot configure crc on a CRTC that is disabled */ |
2113 | if (!dce110_is_tg_enabled(tg)) |
2114 | return false0; |
2115 | |
2116 | cntl_addr = CRTC_REG(mmCRTC_CRC_CNTL)(0x1bd4 + tg110->offsets.crtc); |
2117 | |
2118 | /* First, disable CRC before we configure it. */ |
2119 | dm_write_reg(tg->ctx, cntl_addr, 0)dm_write_reg_func(tg->ctx, cntl_addr, 0, __func__); |
2120 | |
2121 | if (!params->enable) |
2122 | return true1; |
2123 | |
2124 | /* Program frame boundaries */ |
2125 | /* Window A x axis start and end. */ |
2126 | value = 0; |
2127 | addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_X_CONTROL)(0x1bd5 + tg110->offsets.crtc); |
2128 | set_reg_field_value(value, params->windowa_x_start,(value) = set_reg_field_value_ex( (value), (params->windowa_x_start ), 0x3fff, 0x0) |
2129 | CRTC_CRC0_WINDOWA_X_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowa_x_start ), 0x3fff, 0x0) |
2130 | CRTC_CRC0_WINDOWA_X_START)(value) = set_reg_field_value_ex( (value), (params->windowa_x_start ), 0x3fff, 0x0); |
2131 | set_reg_field_value(value, params->windowa_x_end,(value) = set_reg_field_value_ex( (value), (params->windowa_x_end ), 0x3fff0000, 0x10) |
2132 | CRTC_CRC0_WINDOWA_X_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowa_x_end ), 0x3fff0000, 0x10) |
2133 | CRTC_CRC0_WINDOWA_X_END)(value) = set_reg_field_value_ex( (value), (params->windowa_x_end ), 0x3fff0000, 0x10); |
2134 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
2135 | |
2136 | /* Window A y axis start and end. */ |
2137 | value = 0; |
2138 | addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_Y_CONTROL)(0x1bd6 + tg110->offsets.crtc); |
2139 | set_reg_field_value(value, params->windowa_y_start,(value) = set_reg_field_value_ex( (value), (params->windowa_y_start ), 0x3fff, 0x0) |
2140 | CRTC_CRC0_WINDOWA_Y_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowa_y_start ), 0x3fff, 0x0) |
2141 | CRTC_CRC0_WINDOWA_Y_START)(value) = set_reg_field_value_ex( (value), (params->windowa_y_start ), 0x3fff, 0x0); |
2142 | set_reg_field_value(value, params->windowa_y_end,(value) = set_reg_field_value_ex( (value), (params->windowa_y_end ), 0x3fff0000, 0x10) |
2143 | CRTC_CRC0_WINDOWA_Y_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowa_y_end ), 0x3fff0000, 0x10) |
2144 | CRTC_CRC0_WINDOWA_Y_END)(value) = set_reg_field_value_ex( (value), (params->windowa_y_end ), 0x3fff0000, 0x10); |
2145 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
2146 | |
2147 | /* Window B x axis start and end. */ |
2148 | value = 0; |
2149 | addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_X_CONTROL)(0x1bd7 + tg110->offsets.crtc); |
2150 | set_reg_field_value(value, params->windowb_x_start,(value) = set_reg_field_value_ex( (value), (params->windowb_x_start ), 0x3fff, 0x0) |
2151 | CRTC_CRC0_WINDOWB_X_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowb_x_start ), 0x3fff, 0x0) |
2152 | CRTC_CRC0_WINDOWB_X_START)(value) = set_reg_field_value_ex( (value), (params->windowb_x_start ), 0x3fff, 0x0); |
2153 | set_reg_field_value(value, params->windowb_x_end,(value) = set_reg_field_value_ex( (value), (params->windowb_x_end ), 0x3fff0000, 0x10) |
2154 | CRTC_CRC0_WINDOWB_X_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowb_x_end ), 0x3fff0000, 0x10) |
2155 | CRTC_CRC0_WINDOWB_X_END)(value) = set_reg_field_value_ex( (value), (params->windowb_x_end ), 0x3fff0000, 0x10); |
2156 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
2157 | |
2158 | /* Window B y axis start and end. */ |
2159 | value = 0; |
2160 | addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_Y_CONTROL)(0x1bd8 + tg110->offsets.crtc); |
2161 | set_reg_field_value(value, params->windowb_y_start,(value) = set_reg_field_value_ex( (value), (params->windowb_y_start ), 0x3fff, 0x0) |
2162 | CRTC_CRC0_WINDOWB_Y_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowb_y_start ), 0x3fff, 0x0) |
2163 | CRTC_CRC0_WINDOWB_Y_START)(value) = set_reg_field_value_ex( (value), (params->windowb_y_start ), 0x3fff, 0x0); |
2164 | set_reg_field_value(value, params->windowb_y_end,(value) = set_reg_field_value_ex( (value), (params->windowb_y_end ), 0x3fff0000, 0x10) |
2165 | CRTC_CRC0_WINDOWB_Y_CONTROL,(value) = set_reg_field_value_ex( (value), (params->windowb_y_end ), 0x3fff0000, 0x10) |
2166 | CRTC_CRC0_WINDOWB_Y_END)(value) = set_reg_field_value_ex( (value), (params->windowb_y_end ), 0x3fff0000, 0x10); |
2167 | dm_write_reg(tg->ctx, addr, value)dm_write_reg_func(tg->ctx, addr, value, __func__); |
2168 | |
2169 | /* Set crc mode and selection, and enable. Only using CRC0*/ |
2170 | value = 0; |
2171 | set_reg_field_value(value, params->continuous_mode ? 1 : 0,(value) = set_reg_field_value_ex( (value), (params->continuous_mode ? 1 : 0), 0x10, 0x4) |
2172 | CRTC_CRC_CNTL, CRTC_CRC_CONT_EN)(value) = set_reg_field_value_ex( (value), (params->continuous_mode ? 1 : 0), 0x10, 0x4); |
2173 | set_reg_field_value(value, params->selection,(value) = set_reg_field_value_ex( (value), (params->selection ), 0x700000, 0x14) |
2174 | CRTC_CRC_CNTL, CRTC_CRC0_SELECT)(value) = set_reg_field_value_ex( (value), (params->selection ), 0x700000, 0x14); |
2175 | set_reg_field_value(value, 1, CRTC_CRC_CNTL, CRTC_CRC_EN)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
2176 | dm_write_reg(tg->ctx, cntl_addr, value)dm_write_reg_func(tg->ctx, cntl_addr, value, __func__); |
2177 | |
2178 | return true1; |
2179 | } |
2180 | |
2181 | bool_Bool dce110_get_crc(struct timing_generator *tg, |
2182 | uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) |
2183 | { |
2184 | uint32_t addr = 0; |
2185 | uint32_t value = 0; |
2186 | uint32_t field = 0; |
2187 | struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg)({ const __typeof( ((struct dce110_timing_generator *)0)-> base ) *__mptr = (tg); (struct dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof(struct dce110_timing_generator , base) );}); |
2188 | |
2189 | addr = CRTC_REG(mmCRTC_CRC_CNTL)(0x1bd4 + tg110->offsets.crtc); |
2190 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
2191 | field = get_reg_field_value(value, CRTC_CRC_CNTL, CRTC_CRC_EN)get_reg_field_value_ex( (value), 0x1, 0x0); |
2192 | |
2193 | /* Early return if CRC is not enabled for this CRTC */ |
2194 | if (!field) |
2195 | return false0; |
2196 | |
2197 | addr = CRTC_REG(mmCRTC_CRC0_DATA_RG)(0x1bd9 + tg110->offsets.crtc); |
2198 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
2199 | *r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR)get_reg_field_value_ex( (value), 0xffff, 0x0); |
2200 | *g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y)get_reg_field_value_ex( (value), 0xffff0000, 0x10); |
2201 | |
2202 | addr = CRTC_REG(mmCRTC_CRC0_DATA_B)(0x1bda + tg110->offsets.crtc); |
2203 | value = dm_read_reg(tg->ctx, addr)dm_read_reg_func(tg->ctx, addr, __func__); |
2204 | *b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB)get_reg_field_value_ex( (value), 0xffff, 0x0); |
2205 | |
2206 | return true1; |
2207 | } |
2208 | |
2209 | static const struct timing_generator_funcs dce110_tg_funcs = { |
2210 | .validate_timing = dce110_tg_validate_timing, |
2211 | .program_timing = dce110_tg_program_timing, |
2212 | .enable_crtc = dce110_timing_generator_enable_crtc, |
2213 | .disable_crtc = dce110_timing_generator_disable_crtc, |
2214 | .is_counter_moving = dce110_timing_generator_is_counter_moving, |
2215 | .get_position = dce110_timing_generator_get_position, |
2216 | .get_frame_count = dce110_timing_generator_get_vblank_counter, |
2217 | .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, |
2218 | .set_early_control = dce110_timing_generator_set_early_control, |
2219 | .wait_for_state = dce110_tg_wait_for_state, |
2220 | .set_blank = dce110_tg_set_blank, |
2221 | .is_blanked = dce110_tg_is_blanked, |
2222 | .set_colors = dce110_tg_set_colors, |
2223 | .set_overscan_blank_color = |
2224 | dce110_timing_generator_set_overscan_color_black, |
2225 | .set_blank_color = dce110_timing_generator_program_blank_color, |
2226 | .disable_vga = dce110_timing_generator_disable_vga, |
2227 | .did_triggered_reset_occur = |
2228 | dce110_timing_generator_did_triggered_reset_occur, |
2229 | .setup_global_swap_lock = |
2230 | dce110_timing_generator_setup_global_swap_lock, |
2231 | .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, |
2232 | .enable_crtc_reset = dce110_timing_generator_enable_crtc_reset, |
2233 | .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, |
2234 | .tear_down_global_swap_lock = |
2235 | dce110_timing_generator_tear_down_global_swap_lock, |
2236 | .enable_advanced_request = |
2237 | dce110_timing_generator_enable_advanced_request, |
2238 | .set_drr = |
2239 | dce110_timing_generator_set_drr, |
2240 | .set_static_screen_control = |
2241 | dce110_timing_generator_set_static_screen_control, |
2242 | .set_test_pattern = dce110_timing_generator_set_test_pattern, |
2243 | .arm_vert_intr = dce110_arm_vert_intr, |
2244 | .is_tg_enabled = dce110_is_tg_enabled, |
2245 | .configure_crc = dce110_configure_crc, |
2246 | .get_crc = dce110_get_crc, |
2247 | }; |
2248 | |
2249 | void dce110_timing_generator_construct( |
2250 | struct dce110_timing_generator *tg110, |
2251 | struct dc_context *ctx, |
2252 | uint32_t instance, |
2253 | const struct dce110_timing_generator_offsets *offsets) |
2254 | { |
2255 | tg110->controller_id = CONTROLLER_ID_D0 + instance; |
2256 | tg110->base.inst = instance; |
2257 | |
2258 | tg110->offsets = *offsets; |
2259 | |
2260 | tg110->base.funcs = &dce110_tg_funcs; |
2261 | |
2262 | tg110->base.ctx = ctx; |
2263 | tg110->base.bp = ctx->dc_bios; |
2264 | |
2265 | tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK0x3fff + 1; |
2266 | tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK0x3fff + 1; |
2267 | |
2268 | tg110->min_h_blank = 56; |
2269 | tg110->min_h_front_porch = 4; |
2270 | tg110->min_h_back_porch = 4; |
2271 | } |