Bug Summary

File:dev/pci/drm/i915/i915_reg.h
Warning:line 191, column 2
Undefined or garbage value returned to caller

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_workarounds.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/gt/intel_workarounds.c

/usr/src/sys/dev/pci/drm/i915/gt/intel_workarounds.c

→
1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2014-2018 Intel Corporation
5 */
6
7#include "i915_drv.h"
8#include "intel_context.h"
9#include "intel_engine_pm.h"
10#include "intel_gt.h"
11#include "intel_ring.h"
12#include "intel_workarounds.h"
13
14/**
15 * DOC: Hardware workarounds
16 *
17 * This file is intended as a central place to implement most [1]_ of the
18 * required workarounds for hardware to work as originally intended. They fall
19 * in five basic categories depending on how/when they are applied:
20 *
21 * - Workarounds that touch registers that are saved/restored to/from the HW
22 * context image. The list is emitted (via Load Register Immediate commands)
23 * everytime a new context is created.
24 * - GT workarounds. The list of these WAs is applied whenever these registers
25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..).
26 * - Display workarounds. The list is applied during display clock-gating
27 * initialization.
28 * - Workarounds that whitelist a privileged register, so that UMDs can manage
29 * them directly. This is just a special case of a MMMIO workaround (as we
30 * write the list of these to/be-whitelisted registers to some special HW
31 * registers).
32 * - Workaround batchbuffers, that get executed automatically by the hardware
33 * on every HW context restore.
34 *
35 * .. [1] Please notice that there are other WAs that, due to their nature,
36 * cannot be applied from a central place. Those are peppered around the rest
37 * of the code, as needed.
38 *
39 * .. [2] Technically, some registers are powercontext saved & restored, so they
40 * survive a suspend/resume. In practice, writing them again is not too
41 * costly and simplifies things. We can revisit this in the future.
42 *
43 * Layout
44 * ~~~~~~
45 *
46 * Keep things in this file ordered by WA type, as per the above (context, GT,
47 * display, register whitelist, batchbuffer). Then, inside each type, keep the
48 * following order:
49 *
50 * - Infrastructure functions and macros
51 * - WAs per platform in standard gen/chrono order
52 * - Public functions to init or apply the given workaround type.
53 */
54
55/*
56 * KBL revision ID ordering is bizarre; higher revision ID's map to lower
57 * steppings in some cases. So rather than test against the revision ID
58 * directly, let's map that into our own range of increasing ID's that we
59 * can test against in a regular manner.
60 */
61
62const struct i915_rev_steppings kbl_revids[] = {
63 [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 },
64 [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 },
65 [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 },
66 [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 },
67 [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 },
68 [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 },
69 [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 },
70 [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
71};
72
73const struct i915_rev_steppings tgl_uy_revids[] = {
74 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
75 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
76 [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
77 [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
78};
79
80/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
81const struct i915_rev_steppings tgl_revids[] = {
82 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
83 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
84};
85
86static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
87{
88 wal->name = name;
89 wal->engine_name = engine_name;
90}
91
92#define WA_LIST_CHUNK(1 << 4) (1 << 4)
93
94static void wa_init_finish(struct i915_wa_list *wal)
95{
96 /* Trim unused entries. */
97 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)(((wal->count) & (((1 << 4)) - 1)) == 0)) {
98 struct i915_wa *list = kmemdup(wal->list,
99 wal->count * sizeof(*list),
100 GFP_KERNEL(0x0001 | 0x0004));
101
102 if (list) {
103 kfree(wal->list);
104 wal->list = list;
105 }
106 }
107
108 if (!wal->count)
109 return;
110
111 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",__drm_dbg(DRM_UT_DRIVER, "Initialized %u %s workarounds on %s\n"
, wal->wa_count, wal->name, wal->engine_name)
112 wal->wa_count, wal->name, wal->engine_name)__drm_dbg(DRM_UT_DRIVER, "Initialized %u %s workarounds on %s\n"
, wal->wa_count, wal->name, wal->engine_name);
113}
114
115static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
116{
117 unsigned int addr = i915_mmio_reg_offset(wa->reg);
118 unsigned int start = 0, end = wal->count;
119 const unsigned int grow = WA_LIST_CHUNK(1 << 4);
120 struct i915_wa *wa_;
121
122 GEM_BUG_ON(!is_power_of_2(grow))((void)0);
123
124 if (IS_ALIGNED(wal->count, grow)(((wal->count) & ((grow) - 1)) == 0)) { /* Either uninitialized or full. */
15
←
Assuming the condition is true
→
16
←
Taking true branch
→
125 struct i915_wa *list;
126
127 list = kmalloc_array(roundup2(wal->count + 1, grow)(((wal->count + 1) + ((grow) - 1)) & (~((__typeof(wal->
count + 1))(grow) - 1))), sizeof(*wa),
128 GFP_KERNEL(0x0001 | 0x0004));
129 if (!list) {
17
←
Assuming 'list' is non-null
→
18
←
Taking false branch
→
130 DRM_ERROR("No space for workaround init!\n")__drm_err("No space for workaround init!\n");
131 return;
132 }
133
134 if (wal->list) {
19
←
Assuming field 'list' is null
→
20
←
Taking false branch
→
135 memcpy(list, wal->list, sizeof(*wa) * wal->count)__builtin_memcpy((list), (wal->list), (sizeof(*wa) * wal->
count));
136 kfree(wal->list);
137 }
138
139 wal->list = list;
140 }
141
142 while (start < end) {
21
←
Assuming 'start' is < 'end'
→
22
←
Loop condition is true. Entering loop body
→
143 unsigned int mid = start + (end - start) / 2;
144
145 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
23
←
Uninitialized value stored to 'reg.reg'
→
24
←
Calling 'i915_mmio_reg_offset'
→
146 start = mid + 1;
147 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
148 end = mid;
149 } else {
150 wa_ = &wal->list[mid];
151
152 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
153 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",__drm_err("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n"
, i915_mmio_reg_offset(wa_->reg), wa_->clr, wa_->set
)
154 i915_mmio_reg_offset(wa_->reg),__drm_err("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n"
, i915_mmio_reg_offset(wa_->reg), wa_->clr, wa_->set
)
155 wa_->clr, wa_->set)__drm_err("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n"
, i915_mmio_reg_offset(wa_->reg), wa_->clr, wa_->set
);
156
157 wa_->set &= ~wa->clr;
158 }
159
160 wal->wa_count++;
161 wa_->set |= wa->set;
162 wa_->clr |= wa->clr;
163 wa_->read |= wa->read;
164 return;
165 }
166 }
167
168 wal->wa_count++;
169 wa_ = &wal->list[wal->count++];
170 *wa_ = *wa;
171
172 while (wa_-- > wal->list) {
173 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==((void)0)
174 i915_mmio_reg_offset(wa_[1].reg))((void)0);
175 if (i915_mmio_reg_offset(wa_[1].reg) >
176 i915_mmio_reg_offset(wa_[0].reg))
177 break;
178
179 swap(wa_[1], wa_[0])do { __typeof(wa_[1]) __tmp = (wa_[1]); (wa_[1]) = (wa_[0]); (
wa_[0]) = __tmp; } while(0);
180 }
181}
182
183static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
184 u32 clear, u32 set, u32 read_mask)
185{
186 struct i915_wa wa = {
187 .reg = reg,
188 .clr = clear,
189 .set = set,
190 .read = read_mask,
191 };
192
193 _wa_add(wal, &wa);
14
←
Calling '_wa_add'
→
194}
195
196static void
197wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
198{
199 wa_add(wal, reg, clear, set, clear);
13
←
Calling 'wa_add'
→
200}
201
202static void
203wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
204{
205 wa_write_masked_or(wal, reg, ~0, set);
206}
207
208static void
209wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
210{
211 wa_write_masked_or(wal, reg, set, set);
12
←
Calling 'wa_write_masked_or'
→
212}
213
214static void
215wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
216{
217 wa_write_masked_or(wal, reg, clr, 0);
218}
219
220static void
221wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
222{
223 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val)({ typeof(val) _a = (val); ({ if (__builtin_constant_p(_a)) do
{ } while (0); if (__builtin_constant_p(_a)) do { } while (0
); if (__builtin_constant_p(_a) && __builtin_constant_p
(_a)) do { } while (0); ((_a) << 16 | (_a)); }); }), val);
224}
225
226static void
227wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
228{
229 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val)(({ if (__builtin_constant_p((val))) do { } while (0); if (__builtin_constant_p
(0)) do { } while (0); if (__builtin_constant_p((val)) &&
__builtin_constant_p(0)) do { } while (0); (((val)) <<
16 | (0)); })), val);
230}
231
232#define WA_SET_BIT_MASKED(addr, mask)wa_masked_en(wal, (addr), (mask)) \
233 wa_masked_en(wal, (addr), (mask))
234
235#define WA_CLR_BIT_MASKED(addr, mask)wa_masked_dis(wal, (addr), (mask)) \
236 wa_masked_dis(wal, (addr), (mask))
237
238#define WA_SET_FIELD_MASKED(addr, mask, value)wa_write_masked_or(wal, (addr), 0, ({ if (__builtin_constant_p
((mask))) do { } while (0); if (__builtin_constant_p((value))
) do { } while (0); if (__builtin_constant_p((mask)) &&
__builtin_constant_p((value))) do { } while (0); (((mask)) <<
16 | ((value))); })) \
239 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))({ if (__builtin_constant_p((mask))) do { } while (0); if (__builtin_constant_p
((value))) do { } while (0); if (__builtin_constant_p((mask))
&& __builtin_constant_p((value))) do { } while (0); (
((mask)) << 16 | ((value))); }))
240
241static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
242 struct i915_wa_list *wal)
243{
244 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x20c0) })), (
(1 << 7)));
245}
246
247static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,
248 struct i915_wa_list *wal)
249{
250 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x20c0) })), (
(1 << 7)));
251}
252
253static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
254 struct i915_wa_list *wal)
255{
256 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x20c0) })), (
(1 << 7)));
257
258 /* WaDisableAsyncFlipPerfMode:bdw,chv */
259 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x209c) })), (
(1 << 14)));
260
261 /* WaDisablePartialInstShootdown:bdw,chv */
262 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 8)))
263 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 8)));
264
265 /* Use Force Non-Coherent whenever executing a 3D context. This is a
266 * workaround for for a possible hang in the unlikely event a TLB
267 * invalidation occurs during a PSD flush.
268 */
269 /* WaForceEnableNonCoherent:bdw,chv */
270 /* WaHdcDisableFetchWhenMasked:bdw,chv */
271 WA_SET_BIT_MASKED(HDC_CHICKEN0,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 11) | (1 << 4)))
272 HDC_DONOT_FETCH_MEM_WHEN_MASKED |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 11) | (1 << 4)))
273 HDC_FORCE_NON_COHERENT)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 11) | (1 << 4)));
274
275 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
276 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
277 * polygons in the same 8x4 pixel/sample area to be processed without
278 * stalling waiting for the earlier ones to write to Hierarchical Z
279 * buffer."
280 *
281 * This optimization is off by default for BDW and CHV; turn it on.
282 */
283 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE)wa_masked_dis(wal, (((const i915_reg_t){ .reg = (0x7000) })),
((1 << 2)));
284
285 /* Wa4x4STCOptimizationDisable:bdw,chv */
286 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7004) })), (
(1 << 6)));
287
288 /*
289 * BSpec recommends 8x4 when MSAA is used,
290 * however in practice 16x4 seems fastest.
291 *
292 * Note that PS/WM thread counts depend on the WIZ hashing
293 * disable bit, which we don't touch here, but it's good
294 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
295 */
296 WA_SET_FIELD_MASKED(GEN7_GT_MODE,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((((1) << 9) | ((1
) << 7))))) do { } while (0); if (__builtin_constant_p(
((((1) << 9) | ((0) << 7))))) do { } while (0); if
(__builtin_constant_p(((((1) << 9) | ((1) << 7))
)) && __builtin_constant_p(((((1) << 9) | ((0) <<
7))))) do { } while (0); ((((((1) << 9) | ((1) <<
7)))) << 16 | (((((1) << 9) | ((0) << 7)))
)); }))
297 GEN6_WIZ_HASHING_MASK,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((((1) << 9) | ((1
) << 7))))) do { } while (0); if (__builtin_constant_p(
((((1) << 9) | ((0) << 7))))) do { } while (0); if
(__builtin_constant_p(((((1) << 9) | ((1) << 7))
)) && __builtin_constant_p(((((1) << 9) | ((0) <<
7))))) do { } while (0); ((((((1) << 9) | ((1) <<
7)))) << 16 | (((((1) << 9) | ((0) << 7)))
)); }))
298 GEN6_WIZ_HASHING_16x4)wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((((1) << 9) | ((1
) << 7))))) do { } while (0); if (__builtin_constant_p(
((((1) << 9) | ((0) << 7))))) do { } while (0); if
(__builtin_constant_p(((((1) << 9) | ((1) << 7))
)) && __builtin_constant_p(((((1) << 9) | ((0) <<
7))))) do { } while (0); ((((((1) << 9) | ((1) <<
7)))) << 16 | (((((1) << 9) | ((0) << 7)))
)); }));
299}
300
301static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
302 struct i915_wa_list *wal)
303{
304 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
305
306 gen8_ctx_workarounds_init(engine, wal);
307
308 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
309 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 5)));
310
311 /* WaDisableDopClockGating:bdw
312 *
313 * Also see the related UCGTCL1 write in bdw_init_clock_gating()
314 * to disable EUTC clock gating.
315 */
316 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 0)))
317 DOP_CLOCK_GATING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 0)));
318
319 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe184) })), (
(1 << 1)))
320 GEN8_SAMPLER_POWER_BYPASS_DIS)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe184) })), (
(1 << 1)));
321
322 WA_SET_BIT_MASKED(HDC_CHICKEN0,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | ((IS_PLATFORM(i915, INTEL_BROADWELL) &&
(&(i915)->__info)->gt == 3) ? (1 << 14) : 0)
))
323 /* WaForceContextSaveRestoreNonCoherent:bdw */wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | ((IS_PLATFORM(i915, INTEL_BROADWELL) &&
(&(i915)->__info)->gt == 3) ? (1 << 14) : 0)
))
324 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | ((IS_PLATFORM(i915, INTEL_BROADWELL) &&
(&(i915)->__info)->gt == 3) ? (1 << 14) : 0)
))
325 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | ((IS_PLATFORM(i915, INTEL_BROADWELL) &&
(&(i915)->__info)->gt == 3) ? (1 << 14) : 0)
))
326 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0))wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | ((IS_PLATFORM(i915, INTEL_BROADWELL) &&
(&(i915)->__info)->gt == 3) ? (1 << 14) : 0)
));
327}
328
329static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
330 struct i915_wa_list *wal)
331{
332 gen8_ctx_workarounds_init(engine, wal);
333
334 /* WaDisableThreadStallDopClockGating:chv */
335 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 5)));
336
337 /* Improve HiZ throughput on CHV. */
338 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7018) })), (
(1 << 15)));
339}
340
341static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
342 struct i915_wa_list *wal)
343{
344 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
345
346 if (HAS_LLC(i915)((&(i915)->__info)->has_llc)) {
347 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
348 *
349 * Must match Display Engine. See
350 * WaCompressedResourceDisplayNewHashMode.
351 */
352 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 13)))
353 GEN9_PBE_COMPRESSED_HASH_SELECTION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 13)));
354 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe194) })), (
(1 << 8)))
355 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe194) })), (
(1 << 8)));
356 }
357
358 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
359 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
360 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 15) | (1 << 8)))
361 FLOW_CONTROL_ENABLE |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 15) | (1 << 8)))
362 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 15) | (1 << 8)));
363
364 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
365 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
366 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe194) })), (
(1 << 4) | (1 << 2)))
367 GEN9_ENABLE_YV12_BUGFIX |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe194) })), (
(1 << 4) | (1 << 2)))
368 GEN9_ENABLE_GPGPU_PREEMPTION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe194) })), (
(1 << 4) | (1 << 2)));
369
370 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
371 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
372 WA_SET_BIT_MASKED(CACHE_MODE_1,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7004) })), (
(1 << 6) | (1 << 1)))
373 GEN8_4x4_STC_OPTIMIZATION_DISABLE |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7004) })), (
(1 << 6) | (1 << 1)))
374 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7004) })), (
(1 << 6) | (1 << 1)));
375
376 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
377 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,wa_masked_dis(wal, (((const i915_reg_t){ .reg = (0xe188) })),
((1 << 3)))
378 GEN9_CCS_TLB_PREFETCH_ENABLE)wa_masked_dis(wal, (((const i915_reg_t){ .reg = (0xe188) })),
((1 << 3)));
379
380 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
381 WA_SET_BIT_MASKED(HDC_CHICKEN0,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | (1 << 15)))
382 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | (1 << 15)))
383 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 5) | (1 << 15)));
384
385 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
386 * both tied to WaForceContextSaveRestoreNonCoherent
387 * in some hsds for skl. We keep the tie for all gen9. The
388 * documentation is a bit hazy and so we want to get common behaviour,
389 * even though there is no clear evidence we would need both on kbl/bxt.
390 * This area has been source of system hangs so we play it safe
391 * and mimic the skl regardless of what bspec says.
392 *
393 * Use Force Non-Coherent whenever executing a 3D context. This
394 * is a workaround for a possible hang in the unlikely event
395 * a TLB invalidation occurs during a PSD flush.
396 */
397
398 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
399 WA_SET_BIT_MASKED(HDC_CHICKEN0,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 4)))
400 HDC_FORCE_NON_COHERENT)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7300) })), (
(1 << 4)));
401
402 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
403 if (IS_SKYLAKE(i915)IS_PLATFORM(i915, INTEL_SKYLAKE) ||
404 IS_KABYLAKE(i915)IS_PLATFORM(i915, INTEL_KABYLAKE) ||
405 IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE) ||
406 IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE))
407 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe184) })), (
(1 << 1)))
408 GEN8_SAMPLER_POWER_BYPASS_DIS)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe184) })), (
(1 << 1)));
409
410 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
411 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe180) })), (
(1 << 13)));
412
413 /*
414 * Supporting preemption with fine-granularity requires changes in the
415 * batch buffer programming. Since we can't break old userspace, we
416 * need to set our default preemption level to safe value. Userspace is
417 * still able to use more fine-grained preemption levels, since in
418 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
419 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
420 * not real HW workarounds, but merely a way to start using preemption
421 * while maintaining old contract with userspace.
422 */
423
424 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
425 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL)wa_masked_dis(wal, (((const i915_reg_t){ .reg = (0x2580) })),
((1 << 0)));
426
427 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
428 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }))
429 GEN9_PREEMPT_GPGPU_LEVEL_MASK,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }))
430 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL)wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }));
431
432 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
433 if (IS_GEN9_LP(i915)((0 + (&(i915)->__info)->gen == (9)) && ((&
(i915)->__info)->is_lp)))
434 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x5588) })), (
(1 << 9)));
435}
436
437static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
438 struct i915_wa_list *wal)
439{
440 struct intel_gt *gt = engine->gt;
441 u8 vals[3] = { 0, 0, 0 };
442 unsigned int i;
443
444 for (i = 0; i < 3; i++) {
445 u8 ss;
446
447 /*
448 * Only consider slices where one, and only one, subslice has 7
449 * EUs
450 */
451 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])(((gt->info.sseu.subslice_7eu[i]) != 0) && (((gt->
info.sseu.subslice_7eu[i]) - 1) & (gt->info.sseu.subslice_7eu
[i])) == 0))
452 continue;
453
454 /*
455 * subslice_7eu[i] != 0 (because of the check above) and
456 * ss_max == 4 (maximum number of subslices possible per slice)
457 *
458 * -> 0 <= ss <= 3;
459 */
460 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
461 vals[i] = 3 - ss;
462 }
463
464 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
465 return;
466
467 /* Tune IZ hashing. See intel_device_info_runtime_init() */
468 WA_SET_FIELD_MASKED(GEN7_GT_MODE,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
469 GEN9_IZ_HASHING_MASK(2) |wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
470 GEN9_IZ_HASHING_MASK(1) |wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
471 GEN9_IZ_HASHING_MASK(0),wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
472 GEN9_IZ_HASHING(2, vals[2]) |wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
473 GEN9_IZ_HASHING(1, vals[1]) |wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }))
474 GEN9_IZ_HASHING(0, vals[0]))wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x7008)
})), 0, ({ if (__builtin_constant_p(((0x3 << ((2) * 2)
) | (0x3 << ((1) * 2)) | (0x3 << ((0) * 2))))) do
{ } while (0); if (__builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); if (__builtin_constant_p(((0x3
<< ((2) * 2)) | (0x3 << ((1) * 2)) | (0x3 <<
((0) * 2)))) && __builtin_constant_p((((vals[2]) <<
((2) * 2)) | ((vals[1]) << ((1) * 2)) | ((vals[0]) <<
((0) * 2))))) do { } while (0); ((((0x3 << ((2) * 2)) |
(0x3 << ((1) * 2)) | (0x3 << ((0) * 2)))) <<
16 | ((((vals[2]) << ((2) * 2)) | ((vals[1]) << (
(1) * 2)) | ((vals[0]) << ((0) * 2))))); }));
475}
476
477static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
478 struct i915_wa_list *wal)
479{
480 gen9_ctx_workarounds_init(engine, wal);
481 skl_tune_iz_hashing(engine, wal);
482}
483
484static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
485 struct i915_wa_list *wal)
486{
487 gen9_ctx_workarounds_init(engine, wal);
488
489 /* WaDisableThreadStallDopClockGating:bxt */
490 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 5)))
491 STALL_DOP_GATING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 5)));
492
493 /* WaToEnableHwFixForPushConstHWBug:bxt */
494 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)))
495 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)));
496}
497
498static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
499 struct i915_wa_list *wal)
500{
501 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
502
503 gen9_ctx_workarounds_init(engine, wal);
504
505 /* WaToEnableHwFixForPushConstHWBug:kbl */
506 if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)(IS_PLATFORM(i915, INTEL_KABYLAKE) && kbl_revids[((i915
)->drm.pdev->revision)].gt_stepping >= KBL_REVID_C0 &&
kbl_revids[((i915)->drm.pdev->revision)].gt_stepping <=
0xff))
507 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)))
508 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)));
509
510 /* WaDisableSbeCacheDispatchPortSharing:kbl */
511 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe100) })), (
(1 << 4)))
512 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe100) })), (
(1 << 4)));
513}
514
515static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
516 struct i915_wa_list *wal)
517{
518 gen9_ctx_workarounds_init(engine, wal);
519
520 /* WaToEnableHwFixForPushConstHWBug:glk */
521 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)))
522 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)));
523}
524
525static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
526 struct i915_wa_list *wal)
527{
528 gen9_ctx_workarounds_init(engine, wal);
529
530 /* WaToEnableHwFixForPushConstHWBug:cfl */
531 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)))
532 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)));
533
534 /* WaDisableSbeCacheDispatchPortSharing:cfl */
535 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe100) })), (
(1 << 4)))
536 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe100) })), (
(1 << 4)));
537}
538
539static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
540 struct i915_wa_list *wal)
541{
542 /* WaForceContextSaveRestoreNonCoherent:cnl */
543 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xE5F0) })), (
(1 << 5)))
544 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xE5F0) })), (
(1 << 5)));
545
546 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
547 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)))
548 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7014) })), (
(1 << 8)));
549
550 /* WaPushConstantDereferenceHoldDisable:cnl */
551 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 8)));
552
553 /* FtrEnableFastAnisoL1BankingFix:cnl */
554 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe184) })), (
(1 << 4)));
555
556 /* WaDisable3DMidCmdPreemption:cnl */
557 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL)wa_masked_dis(wal, (((const i915_reg_t){ .reg = (0x2580) })),
((1 << 0)));
558
559 /* WaDisableGPGPUMidCmdPreemption:cnl */
560 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }))
561 GEN9_PREEMPT_GPGPU_LEVEL_MASK,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }))
562 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL)wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((1) << 2) | ((0) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((1) << 2) | ((0) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((1) << 2) | ((0) << 1)))
)); }));
563
564 /* WaDisableEarlyEOT:cnl */
565 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f0) })), (
(1 << 1)));
566}
567
568static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
569 struct i915_wa_list *wal)
570{
571 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
572
573 /* WaDisableBankHangMode:icl */
574 wa_write(wal,
575 GEN8_L3CNTLREG((const i915_reg_t){ .reg = (0x7034) }),
576 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG((const i915_reg_t){ .reg = (0x7034) })) |
577 GEN8_ERRDETBCTRL(1 << 9));
578
579 /* Wa_1604370585:icl (pre-prod)
580 * Formerly known as WaPushConstantDereferenceHoldDisable
581 */
582 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x3))))
583 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 8)))
584 PUSH_CONSTANT_DEREF_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 8)));
585
586 /* WaForceEnableNonCoherent:icl
587 * This is not the same workaround as in early Gen9 platforms, where
588 * lacking this could cause system hangs, but coherency performance
589 * overhead is high and only a few compute workloads really need it
590 * (the register is whitelisted in hardware now, so UMDs can opt in
591 * for coherency if they have a good reason).
592 */
593 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xE5F4) })), (
(1 << 4)));
594
595 /* Wa_2006611047:icl (pre-prod)
596 * Formerly known as WaDisableImprovedTdlClkGating
597 */
598 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x0))))
599 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 1)))
600 GEN11_TDL_CLOCK_GATING_FIX_DISABLE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xe4f4) })), (
(1 << 1)));
601
602 /* Wa_2006665173:icl (pre-prod) */
603 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x0))))
604 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7304) })), (
(1 << 11)))
605 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7304) })), (
(1 << 11)));
606
607 /* WaEnableFloatBlendOptimization:icl */
608 wa_write_masked_or(wal,
609 GEN10_CACHE_MODE_SS((const i915_reg_t){ .reg = (0xe420) }),
610 0, /* write-only, so skip validation */
611 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)({ typeof((1 << 4)) _a = ((1 << 4)); ({ if (__builtin_constant_p
(_a)) do { } while (0); if (__builtin_constant_p(_a)) do { } while
(0); if (__builtin_constant_p(_a) && __builtin_constant_p
(_a)) do { } while (0); ((_a) << 16 | (_a)); }); }));
612
613 /* WaDisableGPGPUMidThreadPreemption:icl */
614 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }))
615 GEN9_PREEMPT_GPGPU_LEVEL_MASK,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }))
616 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL)wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }));
617
618 /* allow headerless messages for preemptible GPGPU context */
619 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xE18C) })), (
((u32)((1UL << (5)) + 0))))
620 GEN11_SAMPLER_ENABLE_HEADLESS_MSG)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0xE18C) })), (
((u32)((1UL << (5)) + 0))));
621
622 /* Wa_1604278689:icl,ehl */
623 wa_write(wal, IVB_FBC_RT_BASE((const i915_reg_t){ .reg = (0x7020) }), 0xFFFFFFFF & ~ILK_FBC_RT_VALID(1 << 0));
624 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER((const i915_reg_t){ .reg = (0x7024) }),
625 0, /* write-only register; skip validation */
626 0xFFFFFFFF);
627
628 /* Wa_1406306137:icl,ehl */
629 wa_masked_en(wal, GEN9_ROW_CHICKEN4((const i915_reg_t){ .reg = (0xe48c) }), GEN11_DIS_PICK_2ND_EU((u32)((1UL << (7)) + 0)));
630}
631
632static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
633 struct i915_wa_list *wal)
634{
635 /*
636 * Wa_1409142259:tgl
637 * Wa_1409347922:tgl
638 * Wa_1409252684:tgl
639 * Wa_1409217633:tgl
640 * Wa_1409207793:tgl
641 * Wa_1409178076:tgl
642 * Wa_1408979724:tgl
643 * Wa_14010443199:rkl
644 * Wa_14010698770:rkl
645 */
646 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7304) })), (
(1 << 9)))
647 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE)wa_masked_en(wal, (((const i915_reg_t){ .reg = (0x7304) })), (
(1 << 9)));
648
649 /* WaDisableGPGPUMidThreadPreemption:gen12 */
650 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }))
651 GEN9_PREEMPT_GPGPU_LEVEL_MASK,wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }))
652 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL)wa_write_masked_or(wal, (((const i915_reg_t){ .reg = (0x2580)
})), 0, ({ if (__builtin_constant_p(((((1) << 2) | ((1
) << 1))))) do { } while (0); if (__builtin_constant_p(
((((0) << 2) | ((1) << 1))))) do { } while (0); if
(__builtin_constant_p(((((1) << 2) | ((1) << 1))
)) && __builtin_constant_p(((((0) << 2) | ((1) <<
1))))) do { } while (0); ((((((1) << 2) | ((1) <<
1)))) << 16 | (((((0) << 2) | ((1) << 1)))
)); }));
653}
654
655static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
656 struct i915_wa_list *wal)
657{
658 gen12_ctx_workarounds_init(engine, wal);
659
660 /*
661 * Wa_1604555607:tgl,rkl
662 *
663 * Note that the implementation of this workaround is further modified
664 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
665 * FF_MODE2 register will return the wrong value when read. The default
666 * value for this register is zero for all fields and there are no bit
667 * masks. So instead of doing a RMW we should just write the GS Timer
668 * and TDS timer values for Wa_1604555607 and Wa_16011163337.
669 */
670 wa_add(wal,
671 FF_MODE2((const i915_reg_t){ .reg = (0x6604) }),
672 FF_MODE2_GS_TIMER_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0)) | FF_MODE2_TDS_TIMER_MASK((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0)),
673 FF_MODE2_GS_TIMER_224((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (24))) + 0))))(224) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (24))) + 0)))) + 0 + 0 + 0 + 0
)) | FF_MODE2_TDS_TIMER_128((u32)((((typeof(((u32)((((~0UL) >> (64 - (23) - 1)) &
((~0UL) << (16))) + 0))))(4) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (23
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)),
674 0);
675}
676
677static void
678__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
679 struct i915_wa_list *wal,
680 const char *name)
681{
682 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
683
684 if (engine->class != RENDER_CLASS0)
685 return;
686
687 wa_init_start(wal, name, engine->name);
688
689 if (IS_ROCKETLAKE(i915)IS_PLATFORM(i915, INTEL_ROCKETLAKE) || IS_TIGERLAKE(i915)IS_PLATFORM(i915, INTEL_TIGERLAKE))
690 tgl_ctx_workarounds_init(engine, wal);
691 else if (IS_GEN(i915, 12)(0 + (&(i915)->__info)->gen == (12)))
692 gen12_ctx_workarounds_init(engine, wal);
693 else if (IS_GEN(i915, 11)(0 + (&(i915)->__info)->gen == (11)))
694 icl_ctx_workarounds_init(engine, wal);
695 else if (IS_CANNONLAKE(i915)IS_PLATFORM(i915, INTEL_CANNONLAKE))
696 cnl_ctx_workarounds_init(engine, wal);
697 else if (IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE) || IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE))
698 cfl_ctx_workarounds_init(engine, wal);
699 else if (IS_GEMINILAKE(i915)IS_PLATFORM(i915, INTEL_GEMINILAKE))
700 glk_ctx_workarounds_init(engine, wal);
701 else if (IS_KABYLAKE(i915)IS_PLATFORM(i915, INTEL_KABYLAKE))
702 kbl_ctx_workarounds_init(engine, wal);
703 else if (IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON))
704 bxt_ctx_workarounds_init(engine, wal);
705 else if (IS_SKYLAKE(i915)IS_PLATFORM(i915, INTEL_SKYLAKE))
706 skl_ctx_workarounds_init(engine, wal);
707 else if (IS_CHERRYVIEW(i915)IS_PLATFORM(i915, INTEL_CHERRYVIEW))
708 chv_ctx_workarounds_init(engine, wal);
709 else if (IS_BROADWELL(i915)IS_PLATFORM(i915, INTEL_BROADWELL))
710 bdw_ctx_workarounds_init(engine, wal);
711 else if (IS_GEN(i915, 7)(0 + (&(i915)->__info)->gen == (7)))
712 gen7_ctx_workarounds_init(engine, wal);
713 else if (IS_GEN(i915, 6)(0 + (&(i915)->__info)->gen == (6)))
714 gen6_ctx_workarounds_init(engine, wal);
715 else if (INTEL_GEN(i915)((&(i915)->__info)->gen) < 8)
716 return;
717 else
718 MISSING_CASE(INTEL_GEN(i915))({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "((&(i915)->__info)->gen)", (long)(((&(i915)->
__info)->gen))); __builtin_expect(!!(__ret), 0); });
719
720 wa_init_finish(wal);
721}
722
723void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
724{
725 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
726}
727
728int intel_engine_emit_ctx_wa(struct i915_request *rq)
729{
730 struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
731 struct i915_wa *wa;
732 unsigned int i;
733 u32 *cs;
734 int ret;
735
736 if (wal->count == 0)
737 return 0;
738
739 ret = rq->engine->emit_flush(rq, EMIT_BARRIER((1UL << (0)) | (1UL << (1))));
740 if (ret)
741 return ret;
742
743 cs = intel_ring_begin(rq, (wal->count * 2 + 2));
744 if (IS_ERR(cs))
745 return PTR_ERR(cs);
746
747 *cs++ = MI_LOAD_REGISTER_IMM(wal->count)(((0x22) << 23) | (2*(wal->count)-1));
748 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
749 *cs++ = i915_mmio_reg_offset(wa->reg);
750 *cs++ = wa->set;
751 }
752 *cs++ = MI_NOOP(((0) << 23) | (0));
753
754 intel_ring_advance(rq, cs);
755
756 ret = rq->engine->emit_flush(rq, EMIT_BARRIER((1UL << (0)) | (1UL << (1))));
757 if (ret)
758 return ret;
759
760 return 0;
761}
762
763static void
764gen4_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915,
765 struct i915_wa_list *wal)
766{
767 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
768 wa_masked_dis(wal, CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }), RC_OP_FLUSH_ENABLE(1 << 0));
769}
770
771static void
772g4x_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
773{
774 gen4_gt_workarounds_init(i915, wal);
775
776 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
777 wa_masked_en(wal, CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }), CM0_PIPELINED_RENDER_FLUSH_DISABLE(1 << 8));
778}
779
780static void
781ilk_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
782{
783 g4x_gt_workarounds_init(i915, wal);
784
785 wa_masked_en(wal, _3D_CHICKEN2((const i915_reg_t){ .reg = (0x208c) }), _3D_CHICKEN2_WM_READ_PIPELINED(1 << 14));
786}
787
788static void
789snb_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
790{
791 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
792 wa_masked_en(wal,
793 _3D_CHICKEN((const i915_reg_t){ .reg = (0x2084) }),
794 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB(1 << 10));
795
796 /* WaDisable_RenderCache_OperationalFlush:snb */
797 wa_masked_dis(wal, CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }), RC_OP_FLUSH_ENABLE(1 << 0));
798
799 /*
800 * BSpec recommends 8x4 when MSAA is used,
801 * however in practice 16x4 seems fastest.
802 *
803 * Note that PS/WM thread counts depend on the WIZ hashing
804 * disable bit, which we don't touch here, but it's good
805 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
806 */
807 wa_add(wal,
808 GEN6_GT_MODE((const i915_reg_t){ .reg = (0x20d0) }), 0,
809 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)({ if (__builtin_constant_p((((1) << 9) | ((1) <<
7)))) do { } while (0); if (__builtin_constant_p((((1) <<
9) | ((0) << 7)))) do { } while (0); if (__builtin_constant_p
((((1) << 9) | ((1) << 7))) && __builtin_constant_p
((((1) << 9) | ((0) << 7)))) do { } while (0); ((
(((1) << 9) | ((1) << 7))) << 16 | ((((1) <<
9) | ((0) << 7)))); }),
810 GEN6_WIZ_HASHING_16x4(((1) << 9) | ((0) << 7)));
811
812 wa_masked_dis(wal, CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }), CM0_STC_EVICT_DISABLE_LRA_SNB(1 << 5));
813
814 wa_masked_en(wal,
815 _3D_CHICKEN3((const i915_reg_t){ .reg = (0x2090) }),
816 /* WaStripsFansDisableFastClipPerformanceFix:snb */
817 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL(1 << 5) |
818 /*
819 * Bspec says:
820 * "This bit must be set if 3DSTATE_CLIP clip mode is set
821 * to normal and 3DSTATE_SF number of SF output attributes
822 * is more than 16."
823 */
824 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH(1 << 1));
825}
826
827static void
828ivb_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
829{
830 /* WaDisableEarlyCull:ivb */
831 wa_masked_en(wal, _3D_CHICKEN3((const i915_reg_t){ .reg = (0x2090) }), _3D_CHICKEN_SF_DISABLE_OBJEND_CULL(1 << 10));
832
833 /* WaDisablePSDDualDispatchEnable:ivb */
834 if (IS_IVB_GT1(i915)(IS_PLATFORM(i915, INTEL_IVYBRIDGE) && (&(i915)->
__info)->gt == 1))
835 wa_masked_en(wal,
836 GEN7_HALF_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0xe100) }),
837 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE(1 << 3));
838
839 /* WaDisable_RenderCache_OperationalFlush:ivb */
840 wa_masked_dis(wal, CACHE_MODE_0_GEN7((const i915_reg_t){ .reg = (0x7000) }), RC_OP_FLUSH_ENABLE(1 << 0));
841
842 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
843 wa_masked_dis(wal,
844 GEN7_COMMON_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0x7010) }),
845 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC(1 << 10));
846
847 /* WaApplyL3ControlAndL3ChickenMode:ivb */
848 wa_write(wal, GEN7_L3CNTLREG1((const i915_reg_t){ .reg = (0xB01C) }), GEN7_WA_FOR_GEN7_L3_CONTROL0x3C47FF8C);
849 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER((const i915_reg_t){ .reg = (0xB030) }), GEN7_WA_L3_CHICKEN_MODE0x20000000);
850
851 /* WaForceL3Serialization:ivb */
852 wa_write_clr(wal, GEN7_L3SQCREG4((const i915_reg_t){ .reg = (0xb034) }), L3SQ_URB_READ_CAM_MATCH_DISABLE(1 << 27));
853
854 /*
855 * WaVSThreadDispatchOverride:ivb,vlv
856 *
857 * This actually overrides the dispatch
858 * mode for all thread types.
859 */
860 wa_write_masked_or(wal, GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }),
861 GEN7_FF_SCHED_MASK0x0077070,
862 GEN7_FF_TS_SCHED_HW(0x0 << 16) |
863 GEN7_FF_VS_SCHED_HW(0x0 << 12) |
864 GEN7_FF_DS_SCHED_HW(0x0 << 4));
865
866 if (0) { /* causes HiZ corruption on ivb:gt1 */
867 /* enable HiZ Raw Stall Optimization */
868 wa_masked_dis(wal, CACHE_MODE_0_GEN7((const i915_reg_t){ .reg = (0x7000) }), HIZ_RAW_STALL_OPT_DISABLE(1 << 2));
869 }
870
871 /* WaDisable4x2SubspanOptimization:ivb */
872 wa_masked_en(wal, CACHE_MODE_1((const i915_reg_t){ .reg = (0x7004) }), PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6));
873
874 /*
875 * BSpec recommends 8x4 when MSAA is used,
876 * however in practice 16x4 seems fastest.
877 *
878 * Note that PS/WM thread counts depend on the WIZ hashing
879 * disable bit, which we don't touch here, but it's good
880 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
881 */
882 wa_add(wal, GEN7_GT_MODE((const i915_reg_t){ .reg = (0x7008) }), 0,
883 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)({ if (__builtin_constant_p((((1) << 9) | ((1) <<
7)))) do { } while (0); if (__builtin_constant_p((((1) <<
9) | ((0) << 7)))) do { } while (0); if (__builtin_constant_p
((((1) << 9) | ((1) << 7))) && __builtin_constant_p
((((1) << 9) | ((0) << 7)))) do { } while (0); ((
(((1) << 9) | ((1) << 7))) << 16 | ((((1) <<
9) | ((0) << 7)))); }),
884 GEN6_WIZ_HASHING_16x4(((1) << 9) | ((0) << 7)));
885}
886
887static void
888vlv_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
889{
890 /* WaDisableEarlyCull:vlv */
891 wa_masked_en(wal, _3D_CHICKEN3((const i915_reg_t){ .reg = (0x2090) }), _3D_CHICKEN_SF_DISABLE_OBJEND_CULL(1 << 10));
892
893 /* WaPsdDispatchEnable:vlv */
894 /* WaDisablePSDDualDispatchEnable:vlv */
895 wa_masked_en(wal,
896 GEN7_HALF_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0xe100) }),
897 GEN7_MAX_PS_THREAD_DEP(8 << 12) |
898 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE(1 << 3));
899
900 /* WaDisable_RenderCache_OperationalFlush:vlv */
901 wa_masked_dis(wal, CACHE_MODE_0_GEN7((const i915_reg_t){ .reg = (0x7000) }), RC_OP_FLUSH_ENABLE(1 << 0));
902
903 /* WaForceL3Serialization:vlv */
904 wa_write_clr(wal, GEN7_L3SQCREG4((const i915_reg_t){ .reg = (0xb034) }), L3SQ_URB_READ_CAM_MATCH_DISABLE(1 << 27));
905
906 /*
907 * WaVSThreadDispatchOverride:ivb,vlv
908 *
909 * This actually overrides the dispatch
910 * mode for all thread types.
911 */
912 wa_write_masked_or(wal,
913 GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }),
914 GEN7_FF_SCHED_MASK0x0077070,
915 GEN7_FF_TS_SCHED_HW(0x0 << 16) |
916 GEN7_FF_VS_SCHED_HW(0x0 << 12) |
917 GEN7_FF_DS_SCHED_HW(0x0 << 4));
918
919 /*
920 * BSpec says this must be set, even though
921 * WaDisable4x2SubspanOptimization isn't listed for VLV.
922 */
923 wa_masked_en(wal, CACHE_MODE_1((const i915_reg_t){ .reg = (0x7004) }), PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6));
924
925 /*
926 * BSpec recommends 8x4 when MSAA is used,
927 * however in practice 16x4 seems fastest.
928 *
929 * Note that PS/WM thread counts depend on the WIZ hashing
930 * disable bit, which we don't touch here, but it's good
931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
932 */
933 wa_add(wal, GEN7_GT_MODE((const i915_reg_t){ .reg = (0x7008) }), 0,
934 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)({ if (__builtin_constant_p((((1) << 9) | ((1) <<
7)))) do { } while (0); if (__builtin_constant_p((((1) <<
9) | ((0) << 7)))) do { } while (0); if (__builtin_constant_p
((((1) << 9) | ((1) << 7))) && __builtin_constant_p
((((1) << 9) | ((0) << 7)))) do { } while (0); ((
(((1) << 9) | ((1) << 7))) << 16 | ((((1) <<
9) | ((0) << 7)))); }),
935 GEN6_WIZ_HASHING_16x4(((1) << 9) | ((0) << 7)));
936
937 /*
938 * WaIncreaseL3CreditsForVLVB0:vlv
939 * This is the hardware default actually.
940 */
941 wa_write(wal, GEN7_L3SQCREG1((const i915_reg_t){ .reg = (0xB010) }), VLV_B0_WA_L3SQCREG1_VALUE0x00D30000);
942}
943
944static void
945hsw_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
946{
947 /* L3 caching of data atomics doesn't work -- disable it. */
948 wa_write(wal, HSW_SCRATCH1((const i915_reg_t){ .reg = (0xb038) }), HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE(1 << 27));
949
950 wa_add(wal,
951 HSW_ROW_CHICKEN3((const i915_reg_t){ .reg = (0xe49c) }), 0,
952 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)({ typeof((1 << 6)) _a = ((1 << 6)); ({ if (__builtin_constant_p
(_a)) do { } while (0); if (__builtin_constant_p(_a)) do { } while
(0); if (__builtin_constant_p(_a) && __builtin_constant_p
(_a)) do { } while (0); ((_a) << 16 | (_a)); }); }),
953 0 /* XXX does this reg exist? */);
954
955 /* WaVSRefCountFullforceMissDisable:hsw */
956 wa_write_clr(wal, GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }), GEN7_FF_VS_REF_CNT_FFME(1 << 15));
957
958 wa_masked_dis(wal,
959 CACHE_MODE_0_GEN7((const i915_reg_t){ .reg = (0x7000) }),
960 /* WaDisable_RenderCache_OperationalFlush:hsw */
961 RC_OP_FLUSH_ENABLE(1 << 0) |
962 /* enable HiZ Raw Stall Optimization */
963 HIZ_RAW_STALL_OPT_DISABLE(1 << 2));
964
965 /* WaDisable4x2SubspanOptimization:hsw */
966 wa_masked_en(wal, CACHE_MODE_1((const i915_reg_t){ .reg = (0x7004) }), PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6));
967
968 /*
969 * BSpec recommends 8x4 when MSAA is used,
970 * however in practice 16x4 seems fastest.
971 *
972 * Note that PS/WM thread counts depend on the WIZ hashing
973 * disable bit, which we don't touch here, but it's good
974 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
975 */
976 wa_add(wal, GEN7_GT_MODE((const i915_reg_t){ .reg = (0x7008) }), 0,
977 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)({ if (__builtin_constant_p((((1) << 9) | ((1) <<
7)))) do { } while (0); if (__builtin_constant_p((((1) <<
9) | ((0) << 7)))) do { } while (0); if (__builtin_constant_p
((((1) << 9) | ((1) << 7))) && __builtin_constant_p
((((1) << 9) | ((0) << 7)))) do { } while (0); ((
(((1) << 9) | ((1) << 7))) << 16 | ((((1) <<
9) | ((0) << 7)))); }),
978 GEN6_WIZ_HASHING_16x4(((1) << 9) | ((0) << 7)));
979
980 /* WaSampleCChickenBitEnable:hsw */
981 wa_masked_en(wal, HALF_SLICE_CHICKEN3((const i915_reg_t){ .reg = (0xe184) }), HSW_SAMPLE_C_PERFORMANCE(1 << 9));
982}
983
984static void
985gen9_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
986{
987 /* WaDisableKillLogic:bxt,skl,kbl */
988 if (!IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE) && !IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE))
989 wa_write_or(wal,
990 GAM_ECOCHK((const i915_reg_t){ .reg = (0x4090) }),
991 ECOCHK_DIS_TLB(1 << 8));
992
993 if (HAS_LLC(i915)((&(i915)->__info)->has_llc)) {
994 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
995 *
996 * Must match Display Engine. See
997 * WaCompressedResourceDisplayNewHashMode.
998 */
999 wa_write_or(wal,
1000 MMCD_MISC_CTRL((const i915_reg_t){ .reg = (0x4ddc) }),
1001 MMCD_PCLA(1 << 31) | MMCD_HOTSPOT_EN(1 << 27));
1002 }
1003
1004 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
1005 wa_write_or(wal,
1006 GAM_ECOCHK((const i915_reg_t){ .reg = (0x4090) }),
1007 BDW_DISABLE_HDC_INVALIDATION(1 << 25));
1008}
1009
1010static void
1011skl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1012{
1013 gen9_gt_workarounds_init(i915, wal);
1014
1015 /* WaDisableGafsUnitClkGating:skl */
1016 wa_write_or(wal,
1017 GEN7_UCGCTL4((const i915_reg_t){ .reg = (0x940c) }),
1018 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE(1 << 14));
1019
1020 /* WaInPlaceDecompressionHang:skl */
1021 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)(IS_PLATFORM(i915, INTEL_SKYLAKE) && (((i915)->drm
.pdev->revision) >= (0x7) && ((i915)->drm.pdev
->revision) <= (0xff))))
1022 wa_write_or(wal,
1023 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1024 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1025}
1026
1027static void
1028bxt_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1029{
1030 gen9_gt_workarounds_init(i915, wal);
1031
1032 /* WaInPlaceDecompressionHang:bxt */
1033 wa_write_or(wal,
1034 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1035 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1036}
1037
1038static void
1039kbl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1040{
1041 gen9_gt_workarounds_init(i915, wal);
1042
1043 /* WaDisableDynamicCreditSharing:kbl */
1044 if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)(IS_PLATFORM(i915, INTEL_KABYLAKE) && kbl_revids[((i915
)->drm.pdev->revision)].gt_stepping >= 0 && kbl_revids
[((i915)->drm.pdev->revision)].gt_stepping <= KBL_REVID_B0
))
1045 wa_write_or(wal,
1046 GAMT_CHKN_BIT_REG((const i915_reg_t){ .reg = (0x4ab8) }),
1047 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING(1 << 28));
1048
1049 /* WaDisableGafsUnitClkGating:kbl */
1050 wa_write_or(wal,
1051 GEN7_UCGCTL4((const i915_reg_t){ .reg = (0x940c) }),
1052 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE(1 << 14));
1053
1054 /* WaInPlaceDecompressionHang:kbl */
1055 wa_write_or(wal,
1056 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1057 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1058}
1059
1060static void
1061glk_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1062{
1063 gen9_gt_workarounds_init(i915, wal);
1064}
1065
1066static void
1067cfl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1068{
1069 gen9_gt_workarounds_init(i915, wal);
1070
1071 /* WaDisableGafsUnitClkGating:cfl */
1072 wa_write_or(wal,
1073 GEN7_UCGCTL4((const i915_reg_t){ .reg = (0x940c) }),
1074 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE(1 << 14));
1075
1076 /* WaInPlaceDecompressionHang:cfl */
1077 wa_write_or(wal,
1078 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1079 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1080}
1081
1082static void
1083wa_init_mcr(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1084{
1085 const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
1086 unsigned int slice, subslice;
1087 u32 l3_en, mcr, mcr_mask;
1088
1089 GEM_BUG_ON(INTEL_GEN(i915) < 10)((void)0);
1090
1091 /*
1092 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
1093 * L3Banks could be fused off in single slice scenario. If that is
1094 * the case, we might need to program MCR select to a valid L3Bank
1095 * by default, to make sure we correctly read certain registers
1096 * later on (in the range 0xB100 - 0xB3FF).
1097 *
1098 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
1099 * Before any MMIO read into slice/subslice specific registers, MCR
1100 * packet control register needs to be programmed to point to any
1101 * enabled s/ss pair. Otherwise, incorrect values will be returned.
1102 * This means each subsequent MMIO read will be forwarded to an
1103 * specific s/ss combination, but this is OK since these registers
1104 * are consistent across s/ss in almost all cases. In the rare
1105 * occasions, such as INSTDONE, where this value is dependent
1106 * on s/ss combo, the read should be done with read_subslice_reg.
1107 *
1108 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
1109 * to which subslice, or to which L3 bank, the respective mmio reads
1110 * will go, we have to find a common index which works for both
1111 * accesses.
1112 *
1113 * Case where we cannot find a common index fortunately should not
1114 * happen in production hardware, so we only emit a warning instead of
1115 * implementing something more complex that requires checking the range
1116 * of every MMIO read.
1117 */
1118
1119 if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 10 && is_power_of_2(sseu->slice_mask)(((sseu->slice_mask) != 0) && (((sseu->slice_mask
) - 1) & (sseu->slice_mask)) == 0)) {
1120 u32 l3_fuse =
1121 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3((const i915_reg_t){ .reg = (0x9118) })) &
1122 GEN10_L3BANK_MASK0x0F;
1123
1124 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse)drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "L3 fuse = %x\n"
, l3_fuse);
1125 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT4 | l3_fuse);
1126 } else {
1127 l3_en = ~0;
1128 }
1129
1130 slice = fls(sseu->slice_mask) - 1;
1131 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
1132 if (!subslice) {
1133 drm_warn(&i915->drm,printf("drm:pid%d:%s *WARNING* " "[drm] " "No common index found between subslice mask %x and L3 bank mask %x!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_sseu_get_subslices
(sseu, slice), l3_en)
1134 "No common index found between subslice mask %x and L3 bank mask %x!\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "No common index found between subslice mask %x and L3 bank mask %x!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_sseu_get_subslices
(sseu, slice), l3_en)
1135 intel_sseu_get_subslices(sseu, slice), l3_en)printf("drm:pid%d:%s *WARNING* " "[drm] " "No common index found between subslice mask %x and L3 bank mask %x!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_sseu_get_subslices
(sseu, slice), l3_en);
1136 subslice = fls(l3_en);
1137 drm_WARN_ON(&i915->drm, !subslice)({ int __ret = !!((!subslice)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON("
"!subslice" ")"); __builtin_expect(!!(__ret), 0); });
1138 }
1139 subslice--;
1140
1141 if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 11) {
1142 mcr = GEN11_MCR_SLICE(slice)(((slice) & 0xf) << 27) | GEN11_MCR_SUBSLICE(subslice)(((subslice) & 0x7) << 24);
1143 mcr_mask = GEN11_MCR_SLICE_MASK(((0xf) & 0xf) << 27) | GEN11_MCR_SUBSLICE_MASK(((0x7) & 0x7) << 24);
1144 } else {
1145 mcr = GEN8_MCR_SLICE(slice)(((slice) & 3) << 26) | GEN8_MCR_SUBSLICE(subslice)(((subslice) & 3) << 24);
1146 mcr_mask = GEN8_MCR_SLICE_MASK(((3) & 3) << 26) | GEN8_MCR_SUBSLICE_MASK(((3) & 3) << 24);
1147 }
1148
1149 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr)drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "MCR slice/subslice = %x\n"
, mcr);
1150
1151 wa_write_masked_or(wal, GEN8_MCR_SELECTOR((const i915_reg_t){ .reg = (0xfdc) }), mcr_mask, mcr);
1152}
1153
1154static void
1155cnl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1156{
1157 wa_init_mcr(i915, wal);
1158
1159 /* WaInPlaceDecompressionHang:cnl */
1160 wa_write_or(wal,
1161 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1162 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1163}
1164
1165static void
1166icl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1167{
1168 wa_init_mcr(i915, wal);
1169
1170 /* WaInPlaceDecompressionHang:icl */
1171 wa_write_or(wal,
1172 GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }),
1173 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18));
1174
1175 /* WaModifyGamTlbPartitioning:icl */
1176 wa_write_masked_or(wal,
1177 GEN11_GACB_PERF_CTRL((const i915_reg_t){ .reg = (0x4B80) }),
1178 GEN11_HASH_CTRL_MASK(0x3 << 12 | 0xf << 0),
1179 GEN11_HASH_CTRL_BIT0(1 << 0) | GEN11_HASH_CTRL_BIT4(1 << 12));
1180
1181 /* Wa_1405766107:icl
1182 * Formerly known as WaCL2SFHalfMaxAlloc
1183 */
1184 wa_write_or(wal,
1185 GEN11_LSN_UNSLCVC((const i915_reg_t){ .reg = (0xB43C) }),
1186 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC(1 << 7) |
1187 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC(1 << 9));
1188
1189 /* Wa_220166154:icl
1190 * Formerly known as WaDisCtxReload
1191 */
1192 wa_write_or(wal,
1193 GEN8_GAMW_ECO_DEV_RW_IA((const i915_reg_t){ .reg = (0x4080) }),
1194 GAMW_ECO_DEV_CTX_RELOAD_DISABLE(1 << 7));
1195
1196 /* Wa_1405779004:icl (pre-prod) */
1197 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x0))))
1198 wa_write_or(wal,
1199 SLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x94d4) }),
1200 MSCUNIT_CLKGATE_DIS(1 << 10));
1201
1202 /* Wa_1406838659:icl (pre-prod) */
1203 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x3))))
1204 wa_write_or(wal,
1205 INF_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9560) }),
1206 CGPSF_CLKGATE_DIS(1 << 3));
1207
1208 /* Wa_1406463099:icl
1209 * Formerly known as WaGamTlbPendError
1210 */
1211 wa_write_or(wal,
1212 GAMT_CHKN_BIT_REG((const i915_reg_t){ .reg = (0x4ab8) }),
1213 GAMT_CHKN_DISABLE_L3_COH_PIPE(1 << 31));
1214
1215 /* Wa_1607087056:icl,ehl,jsl */
1216 if (IS_ICELAKE(i915)IS_PLATFORM(i915, INTEL_ICELAKE) ||
1217 IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)(IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && (((i915)->
drm.pdev->revision) >= (0x0) && ((i915)->drm
.pdev->revision) <= (0x0)))) {
1218 wa_write_or(wal,
1219 SLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x94d4) }),
1220 L3_CLKGATE_DIS((u32)((1UL << (16)) + 0)) | L3_CR2X_CLKGATE_DIS((u32)((1UL << (17)) + 0)));
1221 }
1222}
1223
1224static void
1225gen12_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915,
1226 struct i915_wa_list *wal)
1227{
1228 wa_init_mcr(i915, wal);
1229}
1230
1231static void
1232tgl_gt_workarounds_init(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1233{
1234 gen12_gt_workarounds_init(i915, wal);
1235
1236 /* Wa_1409420604:tgl */
1237 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)((IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, (0)) || IS_SUBPLATFORM
(i915, INTEL_TIGERLAKE, (1))) && tgl_uy_revids->gt_stepping
>= (TGL_REVID_A0) && tgl_uy_revids->gt_stepping
<= (TGL_REVID_A0)))
1238 wa_write_or(wal,
1239 SUBSLICE_UNIT_LEVEL_CLKGATE2((const i915_reg_t){ .reg = (0x9528) }),
1240 CPSSUNIT_CLKGATE_DIS((u32)((1UL << (9)) + 0)));
1241
1242 /* Wa_1607087056:tgl also know as BUG:1409180338 */
1243 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)((IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, (0)) || IS_SUBPLATFORM
(i915, INTEL_TIGERLAKE, (1))) && tgl_uy_revids->gt_stepping
>= (TGL_REVID_A0) && tgl_uy_revids->gt_stepping
<= (TGL_REVID_A0)))
1244 wa_write_or(wal,
1245 SLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x94d4) }),
1246 L3_CLKGATE_DIS((u32)((1UL << (16)) + 0)) | L3_CR2X_CLKGATE_DIS((u32)((1UL << (17)) + 0)));
1247}
1248
1249static void
1250gt_init_workarounds(struct drm_i915_privateinteldrm_softc *i915, struct i915_wa_list *wal)
1251{
1252 if (IS_TIGERLAKE(i915)IS_PLATFORM(i915, INTEL_TIGERLAKE))
1253 tgl_gt_workarounds_init(i915, wal);
1254 else if (IS_GEN(i915, 12)(0 + (&(i915)->__info)->gen == (12)))
1255 gen12_gt_workarounds_init(i915, wal);
1256 else if (IS_GEN(i915, 11)(0 + (&(i915)->__info)->gen == (11)))
1257 icl_gt_workarounds_init(i915, wal);
1258 else if (IS_CANNONLAKE(i915)IS_PLATFORM(i915, INTEL_CANNONLAKE))
1259 cnl_gt_workarounds_init(i915, wal);
1260 else if (IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE) || IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE))
1261 cfl_gt_workarounds_init(i915, wal);
1262 else if (IS_GEMINILAKE(i915)IS_PLATFORM(i915, INTEL_GEMINILAKE))
1263 glk_gt_workarounds_init(i915, wal);
1264 else if (IS_KABYLAKE(i915)IS_PLATFORM(i915, INTEL_KABYLAKE))
1265 kbl_gt_workarounds_init(i915, wal);
1266 else if (IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON))
1267 bxt_gt_workarounds_init(i915, wal);
1268 else if (IS_SKYLAKE(i915)IS_PLATFORM(i915, INTEL_SKYLAKE))
1269 skl_gt_workarounds_init(i915, wal);
1270 else if (IS_HASWELL(i915)IS_PLATFORM(i915, INTEL_HASWELL))
1271 hsw_gt_workarounds_init(i915, wal);
1272 else if (IS_VALLEYVIEW(i915)IS_PLATFORM(i915, INTEL_VALLEYVIEW))
1273 vlv_gt_workarounds_init(i915, wal);
1274 else if (IS_IVYBRIDGE(i915)IS_PLATFORM(i915, INTEL_IVYBRIDGE))
1275 ivb_gt_workarounds_init(i915, wal);
1276 else if (IS_GEN(i915, 6)(0 + (&(i915)->__info)->gen == (6)))
1277 snb_gt_workarounds_init(i915, wal);
1278 else if (IS_GEN(i915, 5)(0 + (&(i915)->__info)->gen == (5)))
1279 ilk_gt_workarounds_init(i915, wal);
1280 else if (IS_G4X(i915)(IS_PLATFORM(i915, INTEL_G45) || IS_PLATFORM(i915, INTEL_GM45
)))
1281 g4x_gt_workarounds_init(i915, wal);
1282 else if (IS_GEN(i915, 4)(0 + (&(i915)->__info)->gen == (4)))
1283 gen4_gt_workarounds_init(i915, wal);
1284 else if (INTEL_GEN(i915)((&(i915)->__info)->gen) <= 8)
1285 return;
1286 else
1287 MISSING_CASE(INTEL_GEN(i915))({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "((&(i915)->__info)->gen)", (long)(((&(i915)->
__info)->gen))); __builtin_expect(!!(__ret), 0); });
1288}
1289
1290void intel_gt_init_workarounds(struct drm_i915_privateinteldrm_softc *i915)
1291{
1292 struct i915_wa_list *wal = &i915->gt_wa_list;
1293
1294 wa_init_start(wal, "GT", "global");
1295 gt_init_workarounds(i915, wal);
1296 wa_init_finish(wal);
1297}
1298
1299static enum forcewake_domains
1300wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1301{
1302 enum forcewake_domains fw = 0;
1303 struct i915_wa *wa;
1304 unsigned int i;
1305
1306 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1307 fw |= intel_uncore_forcewake_for_reg(uncore,
1308 wa->reg,
1309 FW_REG_READ(1) |
1310 FW_REG_WRITE(2));
1311
1312 return fw;
1313}
1314
1315static bool_Bool
1316wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
1317{
1318 if ((cur ^ wa->set) & wa->read) {
1319 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n",__drm_err("%s workaround lost on %s! (%x=%x/%x, expected %x)\n"
, name, from, i915_mmio_reg_offset(wa->reg), cur, cur &
wa->read, wa->set)
1320 name, from, i915_mmio_reg_offset(wa->reg),__drm_err("%s workaround lost on %s! (%x=%x/%x, expected %x)\n"
, name, from, i915_mmio_reg_offset(wa->reg), cur, cur &
wa->read, wa->set)
1321 cur, cur & wa->read, wa->set)__drm_err("%s workaround lost on %s! (%x=%x/%x, expected %x)\n"
, name, from, i915_mmio_reg_offset(wa->reg), cur, cur &
wa->read, wa->set);
1322
1323 return false0;
1324 }
1325
1326 return true1;
1327}
1328
1329static void
1330wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1331{
1332 enum forcewake_domains fw;
1333 unsigned long flags;
1334 struct i915_wa *wa;
1335 unsigned int i;
1336
1337 if (!wal->count)
1338 return;
1339
1340 fw = wal_get_fw_for_rmw(uncore, wal);
1341
1342 spin_lock_irqsave(&uncore->lock, flags)do { flags = 0; mtx_enter(&uncore->lock); } while (0);
1343 intel_uncore_forcewake_get__locked(uncore, fw);
1344
1345 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1346 if (wa->clr)
1347 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set);
1348 else
1349 intel_uncore_write_fw(uncore, wa->reg, wa->set)__raw_uncore_write32(uncore, wa->reg, wa->set);
1350 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)0)
1351 wa_verify(wa,
1352 intel_uncore_read_fw(uncore, wa->reg)__raw_uncore_read32(uncore, wa->reg),
1353 wal->name, "application");
1354 }
1355
1356 intel_uncore_forcewake_put__locked(uncore, fw);
1357 spin_unlock_irqrestore(&uncore->lock, flags)do { (void)(flags); mtx_leave(&uncore->lock); } while (
0);
1358}
1359
1360void intel_gt_apply_workarounds(struct intel_gt *gt)
1361{
1362 wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
1363}
1364
1365static bool_Bool wa_list_verify(struct intel_uncore *uncore,
1366 const struct i915_wa_list *wal,
1367 const char *from)
1368{
1369 struct i915_wa *wa;
1370 unsigned int i;
1371 bool_Bool ok = true1;
1372
1373 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1374 ok &= wa_verify(wa,
1375 intel_uncore_read(uncore, wa->reg),
1376 wal->name, from);
1377
1378 return ok;
1379}
1380
1381bool_Bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1382{
1383 return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
1384}
1385
1386static inline bool_Bool is_nonpriv_flags_valid(u32 flags)
1387{
1388 /* Check only valid flag bits are set */
1389 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID((3 << 0) | (3 << 28)))
1390 return false0;
1391
1392 /* NB: Only 3 out of 4 enum values are valid for access field */
1393 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK(3 << 28)) ==
1394 RING_FORCE_TO_NONPRIV_ACCESS_INVALID(3 << 28))
1395 return false0;
1396
1397 return true1;
1398}
1399
1400static void
1401whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1402{
1403 struct i915_wa wa = {
1404 .reg = reg
1405 };
1406
1407 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)({ ((void)0); 0; }))
1408 return;
1409
1410 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))({ ((void)0); 0; }))
1411 return;
1412
1413 wa.reg.reg |= flags;
1414 _wa_add(wal, &wa);
1415}
1416
1417static void
1418whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1419{
1420 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW(0 << 28));
1421}
1422
1423static void gen9_whitelist_build(struct i915_wa_list *w)
1424{
1425 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1426 whitelist_reg(w, GEN9_CTX_PREEMPT_REG((const i915_reg_t){ .reg = (0x2248) }));
1427
1428 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1429 whitelist_reg(w, GEN8_CS_CHICKEN1((const i915_reg_t){ .reg = (0x2580) }));
1430
1431 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1432 whitelist_reg(w, GEN8_HDC_CHICKEN1((const i915_reg_t){ .reg = (0x7304) }));
1433
1434 /* WaSendPushConstantsFromMMIO:skl,bxt */
1435 whitelist_reg(w, COMMON_SLICE_CHICKEN2((const i915_reg_t){ .reg = (0x7014) }));
1436}
1437
1438static void skl_whitelist_build(struct intel_engine_cs *engine)
1439{
1440 struct i915_wa_list *w = &engine->whitelist;
1441
1442 if (engine->class != RENDER_CLASS0)
1443 return;
1444
1445 gen9_whitelist_build(w);
1446
1447 /* WaDisableLSQCROPERFforOCL:skl */
1448 whitelist_reg(w, GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }));
1449}
1450
1451static void bxt_whitelist_build(struct intel_engine_cs *engine)
1452{
1453 if (engine->class != RENDER_CLASS0)
1454 return;
1455
1456 gen9_whitelist_build(&engine->whitelist);
1457}
1458
1459static void kbl_whitelist_build(struct intel_engine_cs *engine)
1460{
1461 struct i915_wa_list *w = &engine->whitelist;
1462
1463 if (engine->class != RENDER_CLASS0)
1464 return;
1465
1466 gen9_whitelist_build(w);
1467
1468 /* WaDisableLSQCROPERFforOCL:kbl */
1469 whitelist_reg(w, GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }));
1470}
1471
1472static void glk_whitelist_build(struct intel_engine_cs *engine)
1473{
1474 struct i915_wa_list *w = &engine->whitelist;
1475
1476 if (engine->class != RENDER_CLASS0)
1477 return;
1478
1479 gen9_whitelist_build(w);
1480
1481 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1482 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1((const i915_reg_t){ .reg = (0x731c) }));
1483}
1484
1485static void cfl_whitelist_build(struct intel_engine_cs *engine)
1486{
1487 struct i915_wa_list *w = &engine->whitelist;
1488
1489 if (engine->class != RENDER_CLASS0)
1490 return;
1491
1492 gen9_whitelist_build(w);
1493
1494 /*
1495 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1496 *
1497 * This covers 4 register which are next to one another :
1498 * - PS_INVOCATION_COUNT
1499 * - PS_INVOCATION_COUNT_UDW
1500 * - PS_DEPTH_COUNT
1501 * - PS_DEPTH_COUNT_UDW
1502 */
1503 whitelist_reg_ext(w, PS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2348) }),
1504 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28) |
1505 RING_FORCE_TO_NONPRIV_RANGE_4(1 << 0));
1506}
1507
1508static void cml_whitelist_build(struct intel_engine_cs *engine)
1509{
1510 struct i915_wa_list *w = &engine->whitelist;
1511
1512 if (engine->class != RENDER_CLASS0)
1513 whitelist_reg_ext(w,
1514 RING_CTX_TIMESTAMP(engine->mmio_base)((const i915_reg_t){ .reg = ((engine->mmio_base) + 0x3a8) }
),
1515 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1516
1517 cfl_whitelist_build(engine);
1518}
1519
1520static void cnl_whitelist_build(struct intel_engine_cs *engine)
1521{
1522 struct i915_wa_list *w = &engine->whitelist;
1523
1524 if (engine->class != RENDER_CLASS0)
1525 return;
1526
1527 /* WaEnablePreemptionGranularityControlByUMD:cnl */
1528 whitelist_reg(w, GEN8_CS_CHICKEN1((const i915_reg_t){ .reg = (0x2580) }));
1529}
1530
1531static void icl_whitelist_build(struct intel_engine_cs *engine)
1532{
1533 struct i915_wa_list *w = &engine->whitelist;
1534
1535 switch (engine->class) {
1536 case RENDER_CLASS0:
1537 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1538 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7((const i915_reg_t){ .reg = (0xe194) }));
1539
1540 /* WaAllowUMDToModifySamplerMode:icl */
1541 whitelist_reg(w, GEN10_SAMPLER_MODE((const i915_reg_t){ .reg = (0xE18C) }));
1542
1543 /* WaEnableStateCacheRedirectToCS:icl */
1544 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1((const i915_reg_t){ .reg = (0x731c) }));
1545
1546 /*
1547 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1548 *
1549 * This covers 4 register which are next to one another :
1550 * - PS_INVOCATION_COUNT
1551 * - PS_INVOCATION_COUNT_UDW
1552 * - PS_DEPTH_COUNT
1553 * - PS_DEPTH_COUNT_UDW
1554 */
1555 whitelist_reg_ext(w, PS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2348) }),
1556 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28) |
1557 RING_FORCE_TO_NONPRIV_RANGE_4(1 << 0));
1558 break;
1559
1560 case VIDEO_DECODE_CLASS1:
1561 /* hucStatusRegOffset */
1562 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base)((const i915_reg_t){ .reg = (0x2000 + engine->mmio_base) }
),
1563 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1564 /* hucUKernelHdrInfoRegOffset */
1565 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base)((const i915_reg_t){ .reg = (0x2014 + engine->mmio_base) }
),
1566 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1567 /* hucStatus2RegOffset */
1568 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base)((const i915_reg_t){ .reg = (0x23B0 + engine->mmio_base) }
),
1569 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1570 whitelist_reg_ext(w,
1571 RING_CTX_TIMESTAMP(engine->mmio_base)((const i915_reg_t){ .reg = ((engine->mmio_base) + 0x3a8) }
),
1572 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1573 break;
1574
1575 default:
1576 whitelist_reg_ext(w,
1577 RING_CTX_TIMESTAMP(engine->mmio_base)((const i915_reg_t){ .reg = ((engine->mmio_base) + 0x3a8) }
),
1578 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1579 break;
1580 }
1581}
1582
1583static void tgl_whitelist_build(struct intel_engine_cs *engine)
1584{
1585 struct i915_wa_list *w = &engine->whitelist;
1586
1587 switch (engine->class) {
1588 case RENDER_CLASS0:
1589 /*
1590 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
1591 * Wa_1408556865:tgl
1592 *
1593 * This covers 4 registers which are next to one another :
1594 * - PS_INVOCATION_COUNT
1595 * - PS_INVOCATION_COUNT_UDW
1596 * - PS_DEPTH_COUNT
1597 * - PS_DEPTH_COUNT_UDW
1598 */
1599 whitelist_reg_ext(w, PS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2348) }),
1600 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28) |
1601 RING_FORCE_TO_NONPRIV_RANGE_4(1 << 0));
1602
1603 /* Wa_1808121037:tgl */
1604 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0x7010) }));
1605
1606 /* Wa_1806527549:tgl */
1607 whitelist_reg(w, HIZ_CHICKEN((const i915_reg_t){ .reg = (0x7018) }));
1608 break;
1609 default:
1610 whitelist_reg_ext(w,
1611 RING_CTX_TIMESTAMP(engine->mmio_base)((const i915_reg_t){ .reg = ((engine->mmio_base) + 0x3a8) }
),
1612 RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28));
1613 break;
1614 }
1615}
1616
1617void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1618{
1619 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
1620 struct i915_wa_list *w = &engine->whitelist;
1621
1622 wa_init_start(w, "whitelist", engine->name);
1623
1624 if (IS_GEN(i915, 12)(0 + (&(i915)->__info)->gen == (12)))
1625 tgl_whitelist_build(engine);
1626 else if (IS_GEN(i915, 11)(0 + (&(i915)->__info)->gen == (11)))
1627 icl_whitelist_build(engine);
1628 else if (IS_CANNONLAKE(i915)IS_PLATFORM(i915, INTEL_CANNONLAKE))
1629 cnl_whitelist_build(engine);
1630 else if (IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE))
1631 cml_whitelist_build(engine);
1632 else if (IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE))
1633 cfl_whitelist_build(engine);
1634 else if (IS_GEMINILAKE(i915)IS_PLATFORM(i915, INTEL_GEMINILAKE))
1635 glk_whitelist_build(engine);
1636 else if (IS_KABYLAKE(i915)IS_PLATFORM(i915, INTEL_KABYLAKE))
1637 kbl_whitelist_build(engine);
1638 else if (IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON))
1639 bxt_whitelist_build(engine);
1640 else if (IS_SKYLAKE(i915)IS_PLATFORM(i915, INTEL_SKYLAKE))
1641 skl_whitelist_build(engine);
1642 else if (INTEL_GEN(i915)((&(i915)->__info)->gen) <= 8)
1643 return;
1644 else
1645 MISSING_CASE(INTEL_GEN(i915))({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "((&(i915)->__info)->gen)", (long)(((&(i915)->
__info)->gen))); __builtin_expect(!!(__ret), 0); });
1646
1647 wa_init_finish(w);
1648}
1649
1650void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1651{
1652 const struct i915_wa_list *wal = &engine->whitelist;
1653 struct intel_uncore *uncore = engine->uncore;
1654 const u32 base = engine->mmio_base;
1655 struct i915_wa *wa;
1656 unsigned int i;
1657
1658 if (!wal->count)
1659 return;
1660
1661 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1662 intel_uncore_write(uncore,
1663 RING_FORCE_TO_NONPRIV(base, i)((const i915_reg_t){ .reg = (((base) + 0x4D0) + (i) * 4) }),
1664 i915_mmio_reg_offset(wa->reg));
1665
1666 /* And clear the rest just in case of garbage */
1667 for (; i < RING_MAX_NONPRIV_SLOTS12; i++)
1668 intel_uncore_write(uncore,
1669 RING_FORCE_TO_NONPRIV(base, i)((const i915_reg_t){ .reg = (((base) + 0x4D0) + (i) * 4) }),
1670 i915_mmio_reg_offset(RING_NOPID(base)((const i915_reg_t){ .reg = ((base) + 0x94) })));
1671}
1672
1673static void
1674rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1675{
1676 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
1677
1678 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)((IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, (0)) || IS_SUBPLATFORM
(i915, INTEL_TIGERLAKE, (1))) && tgl_uy_revids->gt_stepping
>= (TGL_REVID_A0) && tgl_uy_revids->gt_stepping
<= (TGL_REVID_A0))) {
8
←
Assuming the condition is true
→
9
←
Assuming field 'gt_stepping' is <= TGL_REVID_A0
→
10
←
Taking true branch
→
1679 /*
1680 * Wa_1607138336:tgl
1681 * Wa_1607063988:tgl
1682 */
1683 wa_write_or(wal,
11
←
Calling 'wa_write_or'
→
1684 GEN9_CTX_PREEMPT_REG((const i915_reg_t){ .reg = (0x2248) }),
1685 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG((u32)((1UL << (11)) + 0)));
1686
1687 /*
1688 * Wa_1606679103:tgl
1689 * (see also Wa_1606682166:icl)
1690 */
1691 wa_write_or(wal,
1692 GEN7_SARCHKMD((const i915_reg_t){ .reg = (0xB000) }),
1693 GEN7_DISABLE_SAMPLER_PREFETCH(1 << 30));
1694
1695 /* Wa_1408615072:tgl */
1696 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2((const i915_reg_t){ .reg = (0x94e4) }),
1697 VSUNIT_CLKGATE_DIS_TGL((u32)((1UL << (19)) + 0)));
1698 }
1699
1700 if (IS_ROCKETLAKE(i915)IS_PLATFORM(i915, INTEL_ROCKETLAKE) || IS_TIGERLAKE(i915)IS_PLATFORM(i915, INTEL_TIGERLAKE)) {
1701 /* Wa_1606931601:tgl,rkl */
1702 wa_masked_en(wal, GEN7_ROW_CHICKEN2((const i915_reg_t){ .reg = (0xe4f4) }), GEN12_DISABLE_EARLY_READ((u32)((1UL << (14)) + 0)));
1703
1704 /* Wa_1409804808:tgl,rkl */
1705 wa_masked_en(wal, GEN7_ROW_CHICKEN2((const i915_reg_t){ .reg = (0xe4f4) }),
1706 GEN12_PUSH_CONST_DEREF_HOLD_DIS((u32)((1UL << (8)) + 0)));
1707
1708 /*
1709 * Wa_1409085225:tgl
1710 * Wa_14010229206:tgl,rkl
1711 */
1712 wa_masked_en(wal, GEN9_ROW_CHICKEN4((const i915_reg_t){ .reg = (0xe48c) }), GEN12_DISABLE_TDL_PUSH((u32)((1UL << (9)) + 0)));
1713
1714 /*
1715 * Wa_1407928979:tgl A*
1716 * Wa_18011464164:tgl B0+
1717 * Wa_22010931296:tgl B0+
1718 * Wa_14010919138:rkl,tgl
1719 */
1720 wa_write_or(wal, GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }),
1721 GEN12_FF_TESSELATION_DOP_GATE_DISABLE(1UL << (19)));
1722
1723 /*
1724 * Wa_1607030317:tgl
1725 * Wa_1607186500:tgl
1726 * Wa_1607297627:tgl,rkl there are multiple entries for this
1727 * WA in the BSpec; some indicate this is an A0-only WA,
1728 * others indicate it applies to all steppings.
1729 */
1730 wa_masked_en(wal,
1731 GEN6_RC_SLEEP_PSMI_CONTROL((const i915_reg_t){ .reg = (0x2050) }),
1732 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE((u32)((1UL << (7)) + 0)) |
1733 GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12));
1734
1735 /*
1736 * Wa_1606700617:tgl
1737 * Wa_22010271021:tgl,rkl
1738 */
1739 wa_masked_en(wal,
1740 GEN9_CS_DEBUG_MODE1((const i915_reg_t){ .reg = (0x20ec) }),
1741 FF_DOP_CLOCK_GATE_DISABLE((u32)((1UL << (1)) + 0)));
1742 }
1743
1744 if (IS_GEN(i915, 12)(0 + (&(i915)->__info)->gen == (12))) {
1745 /* Wa_1406941453:gen12 */
1746 wa_masked_en(wal,
1747 GEN10_SAMPLER_MODE((const i915_reg_t){ .reg = (0xE18C) }),
1748 ENABLE_SMALLPL((u32)((1UL << (15)) + 0)));
1749 }
1750
1751 if (IS_GEN(i915, 11)(0 + (&(i915)->__info)->gen == (11))) {
1752 /* This is not an Wa. Enable for better image quality */
1753 wa_masked_en(wal,
1754 _3D_CHICKEN3((const i915_reg_t){ .reg = (0x2090) }),
1755 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE(1 << 5));
1756
1757 /* WaPipelineFlushCoherentLines:icl */
1758 wa_write_or(wal,
1759 GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }),
1760 GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21));
1761
1762 /*
1763 * Wa_1405543622:icl
1764 * Formerly known as WaGAPZPriorityScheme
1765 */
1766 wa_write_or(wal,
1767 GEN8_GARBCNTL((const i915_reg_t){ .reg = (0xB004) }),
1768 GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22));
1769
1770 /*
1771 * Wa_1604223664:icl
1772 * Formerly known as WaL3BankAddressHashing
1773 */
1774 wa_write_masked_or(wal,
1775 GEN8_GARBCNTL((const i915_reg_t){ .reg = (0xB004) }),
1776 GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0),
1777 GEN11_HASH_CTRL_EXCL_BIT0(1 << 0));
1778 wa_write_masked_or(wal,
1779 GEN11_GLBLINVL((const i915_reg_t){ .reg = (0xB404) }),
1780 GEN11_BANK_HASH_ADDR_EXCL_MASK(0x7f << 5),
1781 GEN11_BANK_HASH_ADDR_EXCL_BIT0(1 << 5));
1782
1783 /*
1784 * Wa_1405733216:icl
1785 * Formerly known as WaDisableCleanEvicts
1786 */
1787 wa_write_or(wal,
1788 GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }),
1789 GEN11_LQSC_CLEAN_EVICT_DISABLE(1 << 6));
1790
1791 /* WaForwardProgressSoftReset:icl */
1792 wa_write_or(wal,
1793 GEN10_SCRATCH_LNCF2((const i915_reg_t){ .reg = (0xb0a0) }),
1794 PMFLUSHDONE_LNICRSDROP(1 << 20) |
1795 PMFLUSH_GAPL3UNBLOCK(1 << 21) |
1796 PMFLUSHDONE_LNEBLK(1 << 22));
1797
1798 /* Wa_1406609255:icl (pre-prod) */
1799 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)(IS_PLATFORM(i915, INTEL_ICELAKE) && (((i915)->drm
.pdev->revision) >= (0x0) && ((i915)->drm.pdev
->revision) <= (0x3))))
1800 wa_write_or(wal,
1801 GEN7_SARCHKMD((const i915_reg_t){ .reg = (0xB000) }),
1802 GEN7_DISABLE_DEMAND_PREFETCH(1 << 31));
1803
1804 /* Wa_1606682166:icl */
1805 wa_write_or(wal,
1806 GEN7_SARCHKMD((const i915_reg_t){ .reg = (0xB000) }),
1807 GEN7_DISABLE_SAMPLER_PREFETCH(1 << 30));
1808
1809 /* Wa_1409178092:icl */
1810 wa_write_masked_or(wal,
1811 GEN11_SCRATCH2((const i915_reg_t){ .reg = (0xb140) }),
1812 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE(1 << 19),
1813 0);
1814
1815 /* WaEnable32PlaneMode:icl */
1816 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS((const i915_reg_t){ .reg = (0x20D4) }),
1817 GEN11_ENABLE_32_PLANE_MODE(1 << 7));
1818
1819 /*
1820 * Wa_1408615072:icl,ehl (vsunit)
1821 * Wa_1407596294:icl,ehl (hsunit)
1822 */
1823 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9434) }),
1824 VSUNIT_CLKGATE_DIS((u32)((1UL << (3)) + 0)) | HSUNIT_CLKGATE_DIS((u32)((1UL << (8)) + 0)));
1825
1826 /* Wa_1407352427:icl,ehl */
1827 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2((const i915_reg_t){ .reg = (0x94e4) }),
1828 PSDUNIT_CLKGATE_DIS((u32)((1UL << (5)) + 0)));
1829
1830 /* Wa_1406680159:icl,ehl */
1831 wa_write_or(wal,
1832 SUBSLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9524) }),
1833 GWUNIT_CLKGATE_DIS(1 << 16));
1834
1835 /*
1836 * Wa_1408767742:icl[a2..forever],ehl[all]
1837 * Wa_1605460711:icl[a0..c0]
1838 */
1839 wa_write_or(wal,
1840 GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }),
1841 GEN12_FF_TESSELATION_DOP_GATE_DISABLE(1UL << (19)));
1842
1843 /* Wa_22010271021:ehl */
1844 if (IS_ELKHARTLAKE(i915)IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1845 wa_masked_en(wal,
1846 GEN9_CS_DEBUG_MODE1((const i915_reg_t){ .reg = (0x20ec) }),
1847 FF_DOP_CLOCK_GATE_DISABLE((u32)((1UL << (1)) + 0)));
1848 }
1849
1850 if (IS_GEN_RANGE(i915, 9, 12)(!!((&(i915)->__info)->gen_mask & ( 0 + 0 + (((
~0UL) >> (64 - (((12)) - 1) - 1)) & ((~0UL) <<
(((9)) - 1))))))) {
1851 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
1852 wa_masked_en(wal,
1853 GEN7_FF_SLICE_CS_CHICKEN1((const i915_reg_t){ .reg = (0x20e0) }),
1854 GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14));
1855 }
1856
1857 if (IS_SKYLAKE(i915)IS_PLATFORM(i915, INTEL_SKYLAKE) ||
1858 IS_KABYLAKE(i915)IS_PLATFORM(i915, INTEL_KABYLAKE) ||
1859 IS_COFFEELAKE(i915)IS_PLATFORM(i915, INTEL_COFFEELAKE) ||
1860 IS_COMETLAKE(i915)IS_PLATFORM(i915, INTEL_COMETLAKE)) {
1861 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1862 wa_write_or(wal,
1863 GEN8_GARBCNTL((const i915_reg_t){ .reg = (0xB004) }),
1864 GEN9_GAPS_TSV_CREDIT_DISABLE(1 << 7));
1865 }
1866
1867 if (IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON)) {
1868 /* WaDisablePooledEuLoadBalancingFix:bxt */
1869 wa_masked_en(wal,
1870 FF_SLICE_CS_CHICKEN2((const i915_reg_t){ .reg = (0x20e4) }),
1871 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE(1 << 10));
1872 }
1873
1874 if (IS_GEN(i915, 9)(0 + (&(i915)->__info)->gen == (9))) {
1875 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1876 wa_masked_en(wal,
1877 GEN9_CSFE_CHICKEN1_RCS((const i915_reg_t){ .reg = (0x20D4) }),
1878 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE(1 << 2));
1879
1880 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1881 wa_write_or(wal,
1882 BDW_SCRATCH1((const i915_reg_t){ .reg = (0xb11c) }),
1883 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE(1 << 2));
1884
1885 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1886 if (IS_GEN9_LP(i915)((0 + (&(i915)->__info)->gen == (9)) && ((&
(i915)->__info)->is_lp)))
1887 wa_write_masked_or(wal,
1888 GEN8_L3SQCREG1((const i915_reg_t){ .reg = (0xB100) }),
1889 L3_PRIO_CREDITS_MASK((0x1f << 19) | (0x1f << 14)),
1890 L3_GENERAL_PRIO_CREDITS(62)(((62) >> 1) << 19) |
1891 L3_HIGH_PRIO_CREDITS(2)(((2) >> 1) << 14));
1892
1893 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1894 wa_write_or(wal,
1895 GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }),
1896 GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21));
1897 }
1898
1899 if (IS_GEN(i915, 7)(0 + (&(i915)->__info)->gen == (7)))
1900 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1901 wa_masked_en(wal,
1902 GFX_MODE_GEN7((const i915_reg_t){ .reg = (0x229c) }),
1903 GFX_TLB_INVALIDATE_EXPLICIT(1 << 13) | GFX_REPLAY_MODE(1 << 11));
1904
1905 if (IS_GEN_RANGE(i915, 6, 7)(!!((&(i915)->__info)->gen_mask & ( 0 + 0 + (((
~0UL) >> (64 - (((7)) - 1) - 1)) & ((~0UL) <<
(((6)) - 1)))))))
1906 /*
1907 * We need to disable the AsyncFlip performance optimisations in
1908 * order to use MI_WAIT_FOR_EVENT within the CS. It should
1909 * already be programmed to '1' on all products.
1910 *
1911 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1912 */
1913 wa_masked_en(wal,
1914 MI_MODE((const i915_reg_t){ .reg = (0x209c) }),
1915 ASYNC_FLIP_PERF_DISABLE(1 << 14));
1916
1917 if (IS_GEN(i915, 6)(0 + (&(i915)->__info)->gen == (6))) {
1918 /*
1919 * Required for the hardware to program scanline values for
1920 * waiting
1921 * WaEnableFlushTlbInvalidationMode:snb
1922 */
1923 wa_masked_en(wal,
1924 GFX_MODE((const i915_reg_t){ .reg = (0x2520) }),
1925 GFX_TLB_INVALIDATE_EXPLICIT(1 << 13));
1926
1927 /*
1928 * From the Sandybridge PRM, volume 1 part 3, page 24:
1929 * "If this bit is set, STCunit will have LRA as replacement
1930 * policy. [...] This bit must be reset. LRA replacement
1931 * policy is not supported."
1932 */
1933 wa_masked_dis(wal,
1934 CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }),
1935 CM0_STC_EVICT_DISABLE_LRA_SNB(1 << 5));
1936 }
1937
1938 if (IS_GEN_RANGE(i915, 4, 6)(!!((&(i915)->__info)->gen_mask & ( 0 + 0 + (((
~0UL) >> (64 - (((6)) - 1) - 1)) & ((~0UL) <<
(((4)) - 1)))))))
1939 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1940 wa_add(wal, MI_MODE((const i915_reg_t){ .reg = (0x209c) }),
1941 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)({ typeof((1 << 6)) _a = ((1 << 6)); ({ if (__builtin_constant_p
(_a)) do { } while (0); if (__builtin_constant_p(_a)) do { } while
(0); if (__builtin_constant_p(_a) && __builtin_constant_p
(_a)) do { } while (0); ((_a) << 16 | (_a)); }); }),
1942 /* XXX bit doesn't stick on Broadwater */
1943 IS_I965G(i915)IS_PLATFORM(i915, INTEL_I965G) ? 0 : VS_TIMER_DISPATCH(1 << 6));
1944
1945 if (IS_GEN(i915, 4)(0 + (&(i915)->__info)->gen == (4)))
1946 /*
1947 * Disable CONSTANT_BUFFER before it is loaded from the context
1948 * image. For as it is loaded, it is executed and the stored
1949 * address may no longer be valid, leading to a GPU hang.
1950 *
1951 * This imposes the requirement that userspace reload their
1952 * CONSTANT_BUFFER on every batch, fortunately a requirement
1953 * they are already accustomed to from before contexts were
1954 * enabled.
1955 */
1956 wa_add(wal, ECOSKPD((const i915_reg_t){ .reg = (0x21d0) }),
1957 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)({ typeof(((u32)((1UL << (4)) + 0))) _a = (((u32)((1UL <<
(4)) + 0))); ({ if (__builtin_constant_p(_a)) do { } while (
0); if (__builtin_constant_p(_a)) do { } while (0); if (__builtin_constant_p
(_a) && __builtin_constant_p(_a)) do { } while (0); (
(_a) << 16 | (_a)); }); }),
1958 0 /* XXX bit doesn't stick on Broadwater */);
1959}
1960
1961static void
1962xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1963{
1964 struct drm_i915_privateinteldrm_softc *i915 = engine->i915;
1965
1966 /* WaKBLVECSSemaphoreWaitPoll:kbl */
1967 if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)(IS_PLATFORM(i915, INTEL_KABYLAKE) && kbl_revids[((i915
)->drm.pdev->revision)].gt_stepping >= KBL_REVID_A0 &&
kbl_revids[((i915)->drm.pdev->revision)].gt_stepping <=
KBL_REVID_E0)) {
1968 wa_write(wal,
1969 RING_SEMA_WAIT_POLL(engine->mmio_base)((const i915_reg_t){ .reg = ((engine->mmio_base) + 0x24c) }
),
1970 1);
1971 }
1972}
1973
1974static void
1975engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1976{
1977 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)0)
4
←
Taking false branch
→
1978 return;
1979
1980 if (engine->class == RENDER_CLASS0)
5
←
Assuming field 'class' is equal to RENDER_CLASS
→
6
←
Taking true branch
→
1981 rcs_engine_wa_init(engine, wal);
7
←
Calling 'rcs_engine_wa_init'
→
1982 else
1983 xcs_engine_wa_init(engine, wal);
1984}
1985
1986void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1987{
1988 struct i915_wa_list *wal = &engine->wa_list;
1989
1990 if (INTEL_GEN(engine->i915)((&(engine->i915)->__info)->gen) < 4)
1
Assuming field 'gen' is >= 4
→
2
←
Taking false branch
→
1991 return;
1992
1993 wa_init_start(wal, "engine", engine->name);
1994 engine_init_workarounds(engine, wal);
3
←
Calling 'engine_init_workarounds'
→
1995 wa_init_finish(wal);
1996}
1997
1998void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1999{
2000 wa_list_apply(engine->uncore, &engine->wa_list);
2001}
2002
2003static struct i915_vma *
2004create_scratch(struct i915_address_space *vm, int count)
2005{
2006 struct drm_i915_gem_object *obj;
2007 struct i915_vma *vma;
2008 unsigned int size;
2009 int err;
2010
2011 size = round_up(count * sizeof(u32), PAGE_SIZE)((((count * sizeof(u32)) + (((1 << 12)) - 1)) / ((1 <<
12))) * ((1 << 12)));
2012 obj = i915_gem_object_create_internal(vm->i915, size);
2013 if (IS_ERR(obj))
2014 return ERR_CAST(obj);
2015
2016 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
2017
2018 vma = i915_vma_instance(obj, vm, NULL((void *)0));
2019 if (IS_ERR(vma)) {
2020 err = PTR_ERR(vma);
2021 goto err_obj;
2022 }
2023
2024 err = i915_vma_pin(vma, 0, 0,
2025 i915_vma_is_ggtt(vma) ? PIN_GLOBAL(1ULL << (10)) : PIN_USER(1ULL << (11)));
2026 if (err)
2027 goto err_obj;
2028
2029 return vma;
2030
2031err_obj:
2032 i915_gem_object_put(obj);
2033 return ERR_PTR(err);
2034}
2035
2036static const struct {
2037 u32 start;
2038 u32 end;
2039} mcr_ranges_gen8[] = {
2040 { .start = 0x5500, .end = 0x55ff },
2041 { .start = 0x7000, .end = 0x7fff },
2042 { .start = 0x9400, .end = 0x97ff },
2043 { .start = 0xb000, .end = 0xb3ff },
2044 { .start = 0xe000, .end = 0xe7ff },
2045 {},
2046};
2047
2048static bool_Bool mcr_range(struct drm_i915_privateinteldrm_softc *i915, u32 offset)
2049{
2050 int i;
2051
2052 if (INTEL_GEN(i915)((&(i915)->__info)->gen) < 8)
2053 return false0;
2054
2055 /*
2056 * Registers in these ranges are affected by the MCR selector
2057 * which only controls CPU initiated MMIO. Routing does not
2058 * work for CS access so we cannot verify them on this path.
2059 */
2060 for (i = 0; mcr_ranges_gen8[i].start; i++)
2061 if (offset >= mcr_ranges_gen8[i].start &&
2062 offset <= mcr_ranges_gen8[i].end)
2063 return true1;
2064
2065 return false0;
2066}
2067
2068static int
2069wa_list_srm(struct i915_request *rq,
2070 const struct i915_wa_list *wal,
2071 struct i915_vma *vma)
2072{
2073 struct drm_i915_privateinteldrm_softc *i915 = rq->engine->i915;
2074 unsigned int i, count = 0;
2075 const struct i915_wa *wa;
2076 u32 srm, *cs;
2077
2078 srm = MI_STORE_REGISTER_MEM(((0x24) << 23) | (1)) | MI_SRM_LRM_GLOBAL_GTT(1<<22);
2079 if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 8)
2080 srm++;
2081
2082 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
2083 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
2084 count++;
2085 }
2086
2087 cs = intel_ring_begin(rq, 4 * count);
2088 if (IS_ERR(cs))
2089 return PTR_ERR(cs);
2090
2091 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
2092 u32 offset = i915_mmio_reg_offset(wa->reg);
2093
2094 if (mcr_range(i915, offset))
2095 continue;
2096
2097 *cs++ = srm;
2098 *cs++ = offset;
2099 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
2100 *cs++ = 0;
2101 }
2102 intel_ring_advance(rq, cs);
2103
2104 return 0;
2105}
2106
2107static int engine_wa_list_verify(struct intel_context *ce,
2108 const struct i915_wa_list * const wal,
2109 const char *from)
2110{
2111 const struct i915_wa *wa;
2112 struct i915_request *rq;
2113 struct i915_vma *vma;
2114 struct i915_gem_ww_ctx ww;
2115 unsigned int i;
2116 u32 *results;
2117 int err;
2118
2119 if (!wal->count)
2120 return 0;
2121
2122 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
2123 if (IS_ERR(vma))
2124 return PTR_ERR(vma);
2125
2126 intel_engine_pm_get(ce->engine);
2127 i915_gem_ww_ctx_init(&ww, false0);
2128retry:
2129 err = i915_gem_object_lock(vma->obj, &ww);
2130 if (err == 0)
2131 err = intel_context_pin_ww(ce, &ww);
2132 if (err)
2133 goto err_pm;
2134
2135 rq = i915_request_create(ce);
2136 if (IS_ERR(rq)) {
2137 err = PTR_ERR(rq);
2138 goto err_unpin;
2139 }
2140
2141 err = i915_request_await_object(rq, vma->obj, true1);
2142 if (err == 0)
2143 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE(1<<2));
2144 if (err == 0)
2145 err = wa_list_srm(rq, wal, vma);
2146
2147 i915_request_get(rq);
2148 if (err)
2149 i915_request_set_error_once(rq, err);
2150 i915_request_add(rq);
2151
2152 if (err)
2153 goto err_rq;
2154
2155 if (i915_request_wait(rq, 0, HZhz / 5) < 0) {
2156 err = -ETIME60;
2157 goto err_rq;
2158 }
2159
2160 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
2161 if (IS_ERR(results)) {
2162 err = PTR_ERR(results);
2163 goto err_rq;
2164 }
2165
2166 err = 0;
2167 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
2168 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
2169 continue;
2170
2171 if (!wa_verify(wa, results[i], wal->name, from))
2172 err = -ENXIO6;
2173 }
2174
2175 i915_gem_object_unpin_map(vma->obj);
2176
2177err_rq:
2178 i915_request_put(rq);
2179err_unpin:
2180 intel_context_unpin(ce);
2181err_pm:
2182 if (err == -EDEADLK11) {
2183 err = i915_gem_ww_ctx_backoff(&ww);
2184 if (!err)
2185 goto retry;
2186 }
2187 i915_gem_ww_ctx_fini(&ww);
2188 intel_engine_pm_put(ce->engine);
2189 i915_vma_unpin(vma);
2190 i915_vma_put(vma);
2191 return err;
2192}
2193
2194int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
2195 const char *from)
2196{
2197 return engine_wa_list_verify(engine->kernel_context,
2198 &engine->wa_list,
2199 from);
2200}
2201
2202#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)0
2203#include "selftest_workarounds.c"
2204#endif
←

/usr/src/sys/dev/pci/drm/i915/i915_reg.h

1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include <linux/bitfield.h>
29#include <linux/bits.h>
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119/**
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
122 *
123 * Local wrapper for BIT() to force u32, with compile time checks.
124 *
125 * @return: Value with bit @__n set.
126 */
127#define REG_BIT(__n)((u32)((1UL << (__n)) + 0)) \
128 ((u32)(BIT(__n)(1UL << (__n)) + \
129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \0
130 ((__n) < 0 || (__n) > 31))0))
131
132/**
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
136 *
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
138 *
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
140 */
141#define REG_GENMASK(__high, __low)((u32)((((~0UL) >> (64 - (__high) - 1)) & ((~0UL) <<
(__low))) + 0)) \
142 ((u32)(GENMASK(__high, __low)(((~0UL) >> (64 - (__high) - 1)) & ((~0UL) <<
(__low))) + \
143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \0
144 __is_constexpr(__low) && \0
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))0))
146
147/*
148 * Local integer constant expression version of is_power_of_2().
149 */
150#define IS_POWER_OF_2(__x)((__x) && (((__x) & ((__x) - 1)) == 0)) ((__x) && (((__x) & ((__x) - 1)) == 0))
151
152/**
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
154 * @__mask: shifted mask defining the field's length and position
155 * @__val: value to put in the field
156 *
157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159 *
160 * @return: @__val masked and shifted into the field defined by @__mask.
161 */
162#define REG_FIELD_PREP(__mask, __val)((u32)((((typeof(__mask))(__val) << (__builtin_ffsll(__mask
) - 1)) & (__mask)) + 0 + 0 + 0 + 0)) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)(__builtin_ffsll(__mask) - 1)) & (__mask)) + \
164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask))0 + \
165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX)0 + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask))))0 + \
167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))0))
168
169/**
170 * REG_FIELD_GET() - Extract a u32 bitfield value
171 * @__mask: shifted mask defining the field's length and position
172 * @__val: value to extract the bitfield value from
173 *
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176 *
177 * @return: Masked and shifted value of the field defined by @__mask in @__val.
178 */
179#define REG_FIELD_GET(__mask, __val)((u32)((typeof(__mask))(((__val) & (__mask)) >> (__builtin_ffsll
(__mask) - 1)))) ((u32)FIELD_GET(__mask, __val)((typeof(__mask))(((__val) & (__mask)) >> (__builtin_ffsll
(__mask) - 1))))
180
181typedef struct {
182 u32 reg;
183} i915_reg_t;
184
185#define _MMIO(r)((const i915_reg_t){ .reg = (r) }) ((const i915_reg_t){ .reg = (r) })
186
187#define INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) }) _MMIO(0)((const i915_reg_t){ .reg = (0) })
188
189static __always_inline__attribute__((__always_inline__)) u32 i915_mmio_reg_offset(i915_reg_t reg)
190{
191 return reg.reg;
25
←
Undefined or garbage value returned to caller
192}
193
194static inline bool_Bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195{
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197}
198
199static inline bool_Bool i915_mmio_reg_valid(i915_reg_t reg)
200{
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) }));
202}
203
204#define VLV_DISPLAY_BASE0x180000 0x180000
205#define VLV_MIPI_BASE0x180000 VLV_DISPLAY_BASE0x180000
206#define BXT_MIPI_BASE0x60000 0x60000
207
208#define DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display_mmio_offset)
209
210/*
211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212 * numbers, pick the 0-based __index'th value.
213 *
214 * Always prefer this over _PICK() if the numbers are evenly spaced.
215 */
216#define _PICK_EVEN(__index, __a, __b)((__a) + (__index) * ((__b) - (__a))) ((__a) + (__index) * ((__b) - (__a)))
217
218/*
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220 *
221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222 */
223#define _PICK(__index, ...)(((const u32 []){ ... })[__index]) (((const u32 []){ __VA_ARGS__ })[__index])
224
225/*
226 * Named helper wrappers around _PICK_EVEN() and _PICK().
227 */
228#define _PIPE(pipe, a, b)((a) + (pipe) * ((b) - (a))) _PICK_EVEN(pipe, a, b)((a) + (pipe) * ((b) - (a)))
229#define _PLANE(plane, a, b)((a) + (plane) * ((b) - (a))) _PICK_EVEN(plane, a, b)((a) + (plane) * ((b) - (a)))
230#define _TRANS(tran, a, b)((a) + (tran) * ((b) - (a))) _PICK_EVEN(tran, a, b)((a) + (tran) * ((b) - (a)))
231#define _PORT(port, a, b)((a) + (port) * ((b) - (a))) _PICK_EVEN(port, a, b)((a) + (port) * ((b) - (a)))
232#define _PLL(pll, a, b)((a) + (pll) * ((b) - (a))) _PICK_EVEN(pll, a, b)((a) + (pll) * ((b) - (a)))
233
234#define _MMIO_PIPE(pipe, a, b)((const i915_reg_t){ .reg = (((a) + (pipe) * ((b) - (a)))) }) _MMIO(_PIPE(pipe, a, b))((const i915_reg_t){ .reg = (((a) + (pipe) * ((b) - (a)))) })
235#define _MMIO_PLANE(plane, a, b)((const i915_reg_t){ .reg = (((a) + (plane) * ((b) - (a)))) }
) _MMIO(_PLANE(plane, a, b))((const i915_reg_t){ .reg = (((a) + (plane) * ((b) - (a)))) }
)
236#define _MMIO_TRANS(tran, a, b)((const i915_reg_t){ .reg = (((a) + (tran) * ((b) - (a)))) }) _MMIO(_TRANS(tran, a, b))((const i915_reg_t){ .reg = (((a) + (tran) * ((b) - (a)))) })
237#define _MMIO_PORT(port, a, b)((const i915_reg_t){ .reg = (((a) + (port) * ((b) - (a)))) }) _MMIO(_PORT(port, a, b))((const i915_reg_t){ .reg = (((a) + (port) * ((b) - (a)))) })
238#define _MMIO_PLL(pll, a, b)((const i915_reg_t){ .reg = (((a) + (pll) * ((b) - (a)))) }) _MMIO(_PLL(pll, a, b))((const i915_reg_t){ .reg = (((a) + (pll) * ((b) - (a)))) })
239
240#define _PHY3(phy, ...)(((const u32 []){ ... })[phy]) _PICK(phy, __VA_ARGS__)(((const u32 []){ __VA_ARGS__ })[phy])
241
242#define _MMIO_PIPE3(pipe, a, b, c)((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pipe
])) }) _MMIO(_PICK(pipe, a, b, c))((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pipe
])) })
243#define _MMIO_PORT3(pipe, a, b, c)((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pipe
])) }) _MMIO(_PICK(pipe, a, b, c))((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pipe
])) })
244#define _MMIO_PHY3(phy, a, b, c)((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[phy
])) }) _MMIO(_PHY3(phy, a, b, c))((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[phy
])) })
245#define _MMIO_PLL3(pll, a, b, c)((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pll
])) }) _MMIO(_PICK(pll, a, b, c))((const i915_reg_t){ .reg = ((((const u32 []){ a, b, c })[pll
])) })
246
247/*
248 * Device info offset array based helpers for groups of registers with unevenly
249 * spaced base offsets.
250 */
251#define _MMIO_PIPE2(pipe, reg)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
253 DISPLAY_MMIO_BASE(dev_priv))((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
254#define _TRANS2(tran, reg)((&(dev_priv)->__info)->trans_offsets[(tran)] - (&
(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (reg
) + ((&(dev_priv)->__info)->display_mmio_offset)) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->trans_offsets[(tran)] - \
255 INTEL_INFO(dev_priv)(&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (reg) + \
256 DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset))
257#define _MMIO_TRANS2(tran, reg)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
))) }) _MMIO(_TRANS2(tran, reg))((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
))) })
258#define _CURSOR2(pipe, reg)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
260 DISPLAY_MMIO_BASE(dev_priv))((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (reg) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
261
262#define __MASKED_FIELD(mask, value)((mask) << 16 | (value)) ((mask) << 16 | (value))
263#define _MASKED_FIELD(mask, value)({ if (__builtin_constant_p(mask)) do { } while (0); if (__builtin_constant_p
(value)) do { } while (0); if (__builtin_constant_p(mask) &&
__builtin_constant_p(value)) do { } while (0); ((mask) <<
16 | (value)); }) ({ \
264 if (__builtin_constant_p(mask)) \
265 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask")do { } while (0); \
266 if (__builtin_constant_p(value)) \
267 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value")do { } while (0); \
268 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
269 BUILD_BUG_ON_MSG((value) & ~(mask), \do { } while (0)
270 "Incorrect value for mask")do { } while (0); \
271 __MASKED_FIELD(mask, value)((mask) << 16 | (value)); })
272#define _MASKED_BIT_ENABLE(a)({ typeof(a) _a = (a); ({ if (__builtin_constant_p(_a)) do { }
while (0); if (__builtin_constant_p(_a)) do { } while (0); if
(__builtin_constant_p(_a) && __builtin_constant_p(_a
)) do { } while (0); ((_a) << 16 | (_a)); }); }) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a)({ if (__builtin_constant_p(_a)) do { } while (0); if (__builtin_constant_p
(_a)) do { } while (0); if (__builtin_constant_p(_a) &&
__builtin_constant_p(_a)) do { } while (0); ((_a) << 16
| (_a)); }); })
273#define _MASKED_BIT_DISABLE(a)(({ if (__builtin_constant_p((a))) do { } while (0); if (__builtin_constant_p
(0)) do { } while (0); if (__builtin_constant_p((a)) &&
__builtin_constant_p(0)) do { } while (0); (((a)) << 16
| (0)); })) (_MASKED_FIELD((a), 0)({ if (__builtin_constant_p((a))) do { } while (0); if (__builtin_constant_p
(0)) do { } while (0); if (__builtin_constant_p((a)) &&
__builtin_constant_p(0)) do { } while (0); (((a)) << 16
| (0)); }))
274
275/* PCI config space */
276
277#define MCHBAR_I9150x44 0x44
278#define MCHBAR_I9650x48 0x48
279#define MCHBAR_SIZE(4 * 4096) (4 * 4096)
280
281#define DEVEN0x54 0x54
282#define DEVEN_MCHBAR_EN(1 << 28) (1 << 28)
283
284/* BSM in include/drm/i915_drm.h */
285
286#define HPLLCC0xc0 0xc0 /* 85x only */
287#define GC_CLOCK_CONTROL_MASK(0x7 << 0) (0x7 << 0)
288#define GC_CLOCK_133_200(0 << 0) (0 << 0)
289#define GC_CLOCK_100_200(1 << 0) (1 << 0)
290#define GC_CLOCK_100_133(2 << 0) (2 << 0)
291#define GC_CLOCK_133_266(3 << 0) (3 << 0)
292#define GC_CLOCK_133_200_2(4 << 0) (4 << 0)
293#define GC_CLOCK_133_266_2(5 << 0) (5 << 0)
294#define GC_CLOCK_166_266(6 << 0) (6 << 0)
295#define GC_CLOCK_166_250(7 << 0) (7 << 0)
296
297#define I915_GDRST0xc0 0xc0 /* PCI config register */
298#define GRDOM_FULL(0 << 2) (0 << 2)
299#define GRDOM_RENDER(1 << 2) (1 << 2)
300#define GRDOM_MEDIA(3 << 2) (3 << 2)
301#define GRDOM_MASK(3 << 2) (3 << 2)
302#define GRDOM_RESET_STATUS(1 << 1) (1 << 1)
303#define GRDOM_RESET_ENABLE(1 << 0) (1 << 0)
304
305/* BSpec only has register offset, PCI device and bit found empirically */
306#define I830_CLOCK_GATE0xc8 0xc8 /* device 0 */
307#define I830_L2_CACHE_CLOCK_GATE_DISABLE(1 << 2) (1 << 2)
308
309#define GCDGMBUS0xcc 0xcc
310
311#define GCFGC20xda 0xda
312#define GCFGC0xf0 0xf0 /* 915+ only */
313#define GC_LOW_FREQUENCY_ENABLE(1 << 7) (1 << 7)
314#define GC_DISPLAY_CLOCK_190_200_MHZ(0 << 4) (0 << 4)
315#define GC_DISPLAY_CLOCK_333_320_MHZ(4 << 4) (4 << 4)
316#define GC_DISPLAY_CLOCK_267_MHZ_PNV(0 << 4) (0 << 4)
317#define GC_DISPLAY_CLOCK_333_MHZ_PNV(1 << 4) (1 << 4)
318#define GC_DISPLAY_CLOCK_444_MHZ_PNV(2 << 4) (2 << 4)
319#define GC_DISPLAY_CLOCK_200_MHZ_PNV(5 << 4) (5 << 4)
320#define GC_DISPLAY_CLOCK_133_MHZ_PNV(6 << 4) (6 << 4)
321#define GC_DISPLAY_CLOCK_167_MHZ_PNV(7 << 4) (7 << 4)
322#define GC_DISPLAY_CLOCK_MASK(7 << 4) (7 << 4)
323#define GM45_GC_RENDER_CLOCK_MASK(0xf << 0) (0xf << 0)
324#define GM45_GC_RENDER_CLOCK_266_MHZ(8 << 0) (8 << 0)
325#define GM45_GC_RENDER_CLOCK_320_MHZ(9 << 0) (9 << 0)
326#define GM45_GC_RENDER_CLOCK_400_MHZ(0xb << 0) (0xb << 0)
327#define GM45_GC_RENDER_CLOCK_533_MHZ(0xc << 0) (0xc << 0)
328#define I965_GC_RENDER_CLOCK_MASK(0xf << 0) (0xf << 0)
329#define I965_GC_RENDER_CLOCK_267_MHZ(2 << 0) (2 << 0)
330#define I965_GC_RENDER_CLOCK_333_MHZ(3 << 0) (3 << 0)
331#define I965_GC_RENDER_CLOCK_444_MHZ(4 << 0) (4 << 0)
332#define I965_GC_RENDER_CLOCK_533_MHZ(5 << 0) (5 << 0)
333#define I945_GC_RENDER_CLOCK_MASK(7 << 0) (7 << 0)
334#define I945_GC_RENDER_CLOCK_166_MHZ(0 << 0) (0 << 0)
335#define I945_GC_RENDER_CLOCK_200_MHZ(1 << 0) (1 << 0)
336#define I945_GC_RENDER_CLOCK_250_MHZ(3 << 0) (3 << 0)
337#define I945_GC_RENDER_CLOCK_400_MHZ(5 << 0) (5 << 0)
338#define I915_GC_RENDER_CLOCK_MASK(7 << 0) (7 << 0)
339#define I915_GC_RENDER_CLOCK_166_MHZ(0 << 0) (0 << 0)
340#define I915_GC_RENDER_CLOCK_200_MHZ(1 << 0) (1 << 0)
341#define I915_GC_RENDER_CLOCK_333_MHZ(4 << 0) (4 << 0)
342
343#define ASLE0xe4 0xe4
344#define ASLS0xfc 0xfc
345
346#define SWSCI0xe8 0xe8
347#define SWSCI_SCISEL(1 << 15) (1 << 15)
348#define SWSCI_GSSCIE(1 << 0) (1 << 0)
349
350#define LBPC0xf4 0xf4 /* legacy/combination backlight modes, also called LBB */
351
352
353#define ILK_GDSR((const i915_reg_t){ .reg = (0x10000 + 0x2ca4) }) _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)((const i915_reg_t){ .reg = (0x10000 + 0x2ca4) })
354#define ILK_GRDOM_FULL(0 << 1) (0 << 1)
355#define ILK_GRDOM_RENDER(1 << 1) (1 << 1)
356#define ILK_GRDOM_MEDIA(3 << 1) (3 << 1)
357#define ILK_GRDOM_MASK(3 << 1) (3 << 1)
358#define ILK_GRDOM_RESET_ENABLE(1 << 0) (1 << 0)
359
360#define GEN6_MBCUNIT_SNPCR((const i915_reg_t){ .reg = (0x900c) }) _MMIO(0x900c)((const i915_reg_t){ .reg = (0x900c) }) /* for LLC config */
361#define GEN6_MBC_SNPCR_SHIFT21 21
362#define GEN6_MBC_SNPCR_MASK(3 << 21) (3 << 21)
363#define GEN6_MBC_SNPCR_MAX(0 << 21) (0 << 21)
364#define GEN6_MBC_SNPCR_MED(1 << 21) (1 << 21)
365#define GEN6_MBC_SNPCR_LOW(2 << 21) (2 << 21)
366#define GEN6_MBC_SNPCR_MIN(3 << 21) (3 << 21) /* only 1/16th of the cache is shared */
367
368#define VLV_G3DCTL((const i915_reg_t){ .reg = (0x9024) }) _MMIO(0x9024)((const i915_reg_t){ .reg = (0x9024) })
369#define VLV_GSCKGCTL((const i915_reg_t){ .reg = (0x9028) }) _MMIO(0x9028)((const i915_reg_t){ .reg = (0x9028) })
370
371#define GEN6_MBCTL((const i915_reg_t){ .reg = (0x0907c) }) _MMIO(0x0907c)((const i915_reg_t){ .reg = (0x0907c) })
372#define GEN6_MBCTL_ENABLE_BOOT_FETCH(1 << 4) (1 << 4)
373#define GEN6_MBCTL_CTX_FETCH_NEEDED(1 << 3) (1 << 3)
374#define GEN6_MBCTL_BME_UPDATE_ENABLE(1 << 2) (1 << 2)
375#define GEN6_MBCTL_MAE_UPDATE_ENABLE(1 << 1) (1 << 1)
376#define GEN6_MBCTL_BOOT_FETCH_MECH(1 << 0) (1 << 0)
377
378#define GEN6_GDRST((const i915_reg_t){ .reg = (0x941c) }) _MMIO(0x941c)((const i915_reg_t){ .reg = (0x941c) })
379#define GEN6_GRDOM_FULL(1 << 0) (1 << 0)
380#define GEN6_GRDOM_RENDER(1 << 1) (1 << 1)
381#define GEN6_GRDOM_MEDIA(1 << 2) (1 << 2)
382#define GEN6_GRDOM_BLT(1 << 3) (1 << 3)
383#define GEN6_GRDOM_VECS(1 << 4) (1 << 4)
384#define GEN9_GRDOM_GUC(1 << 5) (1 << 5)
385#define GEN8_GRDOM_MEDIA2(1 << 7) (1 << 7)
386/* GEN11 changed all bit defs except for FULL & RENDER */
387#define GEN11_GRDOM_FULL(1 << 0) GEN6_GRDOM_FULL(1 << 0)
388#define GEN11_GRDOM_RENDER(1 << 1) GEN6_GRDOM_RENDER(1 << 1)
389#define GEN11_GRDOM_BLT(1 << 2) (1 << 2)
390#define GEN11_GRDOM_GUC(1 << 3) (1 << 3)
391#define GEN11_GRDOM_MEDIA(1 << 5) (1 << 5)
392#define GEN11_GRDOM_MEDIA2(1 << 6) (1 << 6)
393#define GEN11_GRDOM_MEDIA3(1 << 7) (1 << 7)
394#define GEN11_GRDOM_MEDIA4(1 << 8) (1 << 8)
395#define GEN11_GRDOM_VECS(1 << 13) (1 << 13)
396#define GEN11_GRDOM_VECS2(1 << 14) (1 << 14)
397#define GEN11_GRDOM_SFC0(1 << 17) (1 << 17)
398#define GEN11_GRDOM_SFC1(1 << 18) (1 << 18)
399
400#define GEN11_VCS_SFC_RESET_BIT(instance)((1 << 17) << ((instance) >> 1)) (GEN11_GRDOM_SFC0(1 << 17) << ((instance) >> 1))
401#define GEN11_VECS_SFC_RESET_BIT(instance)((1 << 17) << (instance)) (GEN11_GRDOM_SFC0(1 << 17) << (instance))
402
403#define GEN11_VCS_SFC_FORCED_LOCK(engine)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x88C) }
) _MMIO((engine)->mmio_base + 0x88C)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x88C) }
)
404#define GEN11_VCS_SFC_FORCED_LOCK_BIT(1 << 0) (1 << 0)
405#define GEN11_VCS_SFC_LOCK_STATUS(engine)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x890) }
) _MMIO((engine)->mmio_base + 0x890)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x890) }
)
406#define GEN11_VCS_SFC_USAGE_BIT(1 << 0) (1 << 0)
407#define GEN11_VCS_SFC_LOCK_ACK_BIT(1 << 1) (1 << 1)
408
409#define GEN11_VECS_SFC_FORCED_LOCK(engine)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x201C)
}) _MMIO((engine)->mmio_base + 0x201C)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x201C)
})
410#define GEN11_VECS_SFC_FORCED_LOCK_BIT(1 << 0) (1 << 0)
411#define GEN11_VECS_SFC_LOCK_ACK(engine)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x2018)
}) _MMIO((engine)->mmio_base + 0x2018)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x2018)
})
412#define GEN11_VECS_SFC_LOCK_ACK_BIT(1 << 0) (1 << 0)
413#define GEN11_VECS_SFC_USAGE(engine)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x2014)
}) _MMIO((engine)->mmio_base + 0x2014)((const i915_reg_t){ .reg = ((engine)->mmio_base + 0x2014)
})
414#define GEN11_VECS_SFC_USAGE_BIT(1 << 0) (1 << 0)
415
416#define GEN12_SFC_DONE(n)((const i915_reg_t){ .reg = (0x1cc000 + (n) * 0x1000) }) _MMIO(0x1cc000 + (n) * 0x1000)((const i915_reg_t){ .reg = (0x1cc000 + (n) * 0x1000) })
417#define GEN12_SFC_DONE_MAX4 4
418
419#define RING_PP_DIR_BASE(base)((const i915_reg_t){ .reg = ((base) + 0x228) }) _MMIO((base) + 0x228)((const i915_reg_t){ .reg = ((base) + 0x228) })
420#define RING_PP_DIR_BASE_READ(base)((const i915_reg_t){ .reg = ((base) + 0x518) }) _MMIO((base) + 0x518)((const i915_reg_t){ .reg = ((base) + 0x518) })
421#define RING_PP_DIR_DCLV(base)((const i915_reg_t){ .reg = ((base) + 0x220) }) _MMIO((base) + 0x220)((const i915_reg_t){ .reg = ((base) + 0x220) })
422#define PP_DIR_DCLV_2G0xffffffff 0xffffffff
423
424#define GEN8_RING_PDP_UDW(base, n)((const i915_reg_t){ .reg = ((base) + 0x270 + (n) * 8 + 4) }) _MMIO((base) + 0x270 + (n) * 8 + 4)((const i915_reg_t){ .reg = ((base) + 0x270 + (n) * 8 + 4) })
425#define GEN8_RING_PDP_LDW(base, n)((const i915_reg_t){ .reg = ((base) + 0x270 + (n) * 8) }) _MMIO((base) + 0x270 + (n) * 8)((const i915_reg_t){ .reg = ((base) + 0x270 + (n) * 8) })
426
427#define GEN8_R_PWR_CLK_STATE((const i915_reg_t){ .reg = (0x20C8) }) _MMIO(0x20C8)((const i915_reg_t){ .reg = (0x20C8) })
428#define GEN8_RPCS_ENABLE(1 << 31) (1 << 31)
429#define GEN8_RPCS_S_CNT_ENABLE(1 << 18) (1 << 18)
430#define GEN8_RPCS_S_CNT_SHIFT15 15
431#define GEN8_RPCS_S_CNT_MASK(0x7 << 15) (0x7 << GEN8_RPCS_S_CNT_SHIFT15)
432#define GEN11_RPCS_S_CNT_SHIFT12 12
433#define GEN11_RPCS_S_CNT_MASK(0x3f << 12) (0x3f << GEN11_RPCS_S_CNT_SHIFT12)
434#define GEN8_RPCS_SS_CNT_ENABLE(1 << 11) (1 << 11)
435#define GEN8_RPCS_SS_CNT_SHIFT8 8
436#define GEN8_RPCS_SS_CNT_MASK(0x7 << 8) (0x7 << GEN8_RPCS_SS_CNT_SHIFT8)
437#define GEN8_RPCS_EU_MAX_SHIFT4 4
438#define GEN8_RPCS_EU_MAX_MASK(0xf << 4) (0xf << GEN8_RPCS_EU_MAX_SHIFT4)
439#define GEN8_RPCS_EU_MIN_SHIFT0 0
440#define GEN8_RPCS_EU_MIN_MASK(0xf << 0) (0xf << GEN8_RPCS_EU_MIN_SHIFT0)
441
442#define WAIT_FOR_RC6_EXIT((const i915_reg_t){ .reg = (0x20CC) }) _MMIO(0x20CC)((const i915_reg_t){ .reg = (0x20CC) })
443/* HSW only */
444#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT2 2
445#define HSW_SELECTIVE_READ_ADDRESSING_MASK(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
446#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT4 4
447#define HSW_SELECTIVE_WRITE_ADDRESS_MASK(0x7 << 4) (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT4)
448/* HSW+ */
449#define HSW_WAIT_FOR_RC6_EXIT_ENABLE(1 << 0) (1 << 0)
450#define HSW_RCS_CONTEXT_ENABLE(1 << 7) (1 << 7)
451#define HSW_RCS_INHIBIT(1 << 8) (1 << 8)
452/* Gen8 */
453#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT4 4
454#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK(0x3 << 4) (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT4)
455#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT4 4
456#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK(0x3 << 4) (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT4)
457#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE(1 << 6) (1 << 6)
458#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT9 9
459#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK(0x3 << 9) (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT9)
460#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT11 11
461#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK(0x3 << 11) (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT11)
462#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE(1 << 13) (1 << 13)
463
464#define GAM_ECOCHK((const i915_reg_t){ .reg = (0x4090) }) _MMIO(0x4090)((const i915_reg_t){ .reg = (0x4090) })
465#define BDW_DISABLE_HDC_INVALIDATION(1 << 25) (1 << 25)
466#define ECOCHK_SNB_BIT(1 << 10) (1 << 10)
467#define ECOCHK_DIS_TLB(1 << 8) (1 << 8)
468#define HSW_ECOCHK_ARB_PRIO_SOL(1 << 6) (1 << 6)
469#define ECOCHK_PPGTT_CACHE64B(0x3 << 3) (0x3 << 3)
470#define ECOCHK_PPGTT_CACHE4B(0x0 << 3) (0x0 << 3)
471#define ECOCHK_PPGTT_GFDT_IVB(0x1 << 4) (0x1 << 4)
472#define ECOCHK_PPGTT_LLC_IVB(0x1 << 3) (0x1 << 3)
473#define ECOCHK_PPGTT_UC_HSW(0x1 << 3) (0x1 << 3)
474#define ECOCHK_PPGTT_WT_HSW(0x2 << 3) (0x2 << 3)
475#define ECOCHK_PPGTT_WB_HSW(0x3 << 3) (0x3 << 3)
476
477#define GEN8_RC6_CTX_INFO((const i915_reg_t){ .reg = (0x8504) }) _MMIO(0x8504)((const i915_reg_t){ .reg = (0x8504) })
478
479#define GAC_ECO_BITS((const i915_reg_t){ .reg = (0x14090) }) _MMIO(0x14090)((const i915_reg_t){ .reg = (0x14090) })
480#define ECOBITS_SNB_BIT(1 << 13) (1 << 13)
481#define ECOBITS_PPGTT_CACHE64B(3 << 8) (3 << 8)
482#define ECOBITS_PPGTT_CACHE4B(0 << 8) (0 << 8)
483
484#define GAB_CTL((const i915_reg_t){ .reg = (0x24000) }) _MMIO(0x24000)((const i915_reg_t){ .reg = (0x24000) })
485#define GAB_CTL_CONT_AFTER_PAGEFAULT(1 << 8) (1 << 8)
486
487#define GEN6_STOLEN_RESERVED((const i915_reg_t){ .reg = (0x1082C0) }) _MMIO(0x1082C0)((const i915_reg_t){ .reg = (0x1082C0) })
488#define GEN6_STOLEN_RESERVED_ADDR_MASK(0xFFF << 20) (0xFFF << 20)
489#define GEN7_STOLEN_RESERVED_ADDR_MASK(0x3FFF << 18) (0x3FFF << 18)
490#define GEN6_STOLEN_RESERVED_SIZE_MASK(3 << 4) (3 << 4)
491#define GEN6_STOLEN_RESERVED_1M(0 << 4) (0 << 4)
492#define GEN6_STOLEN_RESERVED_512K(1 << 4) (1 << 4)
493#define GEN6_STOLEN_RESERVED_256K(2 << 4) (2 << 4)
494#define GEN6_STOLEN_RESERVED_128K(3 << 4) (3 << 4)
495#define GEN7_STOLEN_RESERVED_SIZE_MASK(1 << 5) (1 << 5)
496#define GEN7_STOLEN_RESERVED_1M(0 << 5) (0 << 5)
497#define GEN7_STOLEN_RESERVED_256K(1 << 5) (1 << 5)
498#define GEN8_STOLEN_RESERVED_SIZE_MASK(3 << 7) (3 << 7)
499#define GEN8_STOLEN_RESERVED_1M(0 << 7) (0 << 7)
500#define GEN8_STOLEN_RESERVED_2M(1 << 7) (1 << 7)
501#define GEN8_STOLEN_RESERVED_4M(2 << 7) (2 << 7)
502#define GEN8_STOLEN_RESERVED_8M(3 << 7) (3 << 7)
503#define GEN6_STOLEN_RESERVED_ENABLE(1 << 0) (1 << 0)
504#define GEN11_STOLEN_RESERVED_ADDR_MASK(0xFFFFFFFFFFFULL << 20) (0xFFFFFFFFFFFULL << 20)
505
506/* VGA stuff */
507
508#define VGA_ST01_MDA0x3ba 0x3ba
509#define VGA_ST01_CGA0x3da 0x3da
510
511#define _VGA_MSR_WRITE((const i915_reg_t){ .reg = (0x3c2) }) _MMIO(0x3c2)((const i915_reg_t){ .reg = (0x3c2) })
512#define VGA_MSR_WRITE0x3c2 0x3c2
513#define VGA_MSR_READ0x3cc 0x3cc
514#define VGA_MSR_MEM_EN(1 << 1) (1 << 1)
515#define VGA_MSR_CGA_MODE(1 << 0) (1 << 0)
516
517#define VGA_SR_INDEX0x3c4 0x3c4
518#define SR011 1
519#define VGA_SR_DATA0x3c5 0x3c5
520
521#define VGA_AR_INDEX0x3c0 0x3c0
522#define VGA_AR_VID_EN(1 << 5) (1 << 5)
523#define VGA_AR_DATA_WRITE0x3c0 0x3c0
524#define VGA_AR_DATA_READ0x3c1 0x3c1
525
526#define VGA_GR_INDEX0x3ce 0x3ce
527#define VGA_GR_DATA0x3cf 0x3cf
528/* GR05 */
529#define VGA_GR_MEM_READ_MODE_SHIFT3 3
530#define VGA_GR_MEM_READ_MODE_PLANE1 1
531/* GR06 */
532#define VGA_GR_MEM_MODE_MASK0xc 0xc
533#define VGA_GR_MEM_MODE_SHIFT2 2
534#define VGA_GR_MEM_A0000_AFFFF0 0
535#define VGA_GR_MEM_A0000_BFFFF1 1
536#define VGA_GR_MEM_B0000_B7FFF2 2
537#define VGA_GR_MEM_B0000_BFFFF3 3
538
539#define VGA_DACMASK0x3c6 0x3c6
540#define VGA_DACRX0x3c7 0x3c7
541#define VGA_DACWX0x3c8 0x3c8
542#define VGA_DACDATA0x3c9 0x3c9
543
544#define VGA_CR_INDEX_MDA0x3b4 0x3b4
545#define VGA_CR_DATA_MDA0x3b5 0x3b5
546#define VGA_CR_INDEX_CGA0x3d4 0x3d4
547#define VGA_CR_DATA_CGA0x3d5 0x3d5
548
549#define MI_PREDICATE_SRC0((const i915_reg_t){ .reg = (0x2400) }) _MMIO(0x2400)((const i915_reg_t){ .reg = (0x2400) })
550#define MI_PREDICATE_SRC0_UDW((const i915_reg_t){ .reg = (0x2400 + 4) }) _MMIO(0x2400 + 4)((const i915_reg_t){ .reg = (0x2400 + 4) })
551#define MI_PREDICATE_SRC1((const i915_reg_t){ .reg = (0x2408) }) _MMIO(0x2408)((const i915_reg_t){ .reg = (0x2408) })
552#define MI_PREDICATE_SRC1_UDW((const i915_reg_t){ .reg = (0x2408 + 4) }) _MMIO(0x2408 + 4)((const i915_reg_t){ .reg = (0x2408 + 4) })
553#define MI_PREDICATE_DATA((const i915_reg_t){ .reg = (0x2410) }) _MMIO(0x2410)((const i915_reg_t){ .reg = (0x2410) })
554#define MI_PREDICATE_RESULT((const i915_reg_t){ .reg = (0x2418) }) _MMIO(0x2418)((const i915_reg_t){ .reg = (0x2418) })
555#define MI_PREDICATE_RESULT_1((const i915_reg_t){ .reg = (0x241c) }) _MMIO(0x241c)((const i915_reg_t){ .reg = (0x241c) })
556#define MI_PREDICATE_RESULT_2((const i915_reg_t){ .reg = (0x2214) }) _MMIO(0x2214)((const i915_reg_t){ .reg = (0x2214) })
557#define LOWER_SLICE_ENABLED(1 << 0) (1 << 0)
558#define LOWER_SLICE_DISABLED(0 << 0) (0 << 0)
559
560/*
561 * Registers used only by the command parser
562 */
563#define BCS_SWCTRL((const i915_reg_t){ .reg = (0x22200) }) _MMIO(0x22200)((const i915_reg_t){ .reg = (0x22200) })
564#define BCS_SRC_Y((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
565#define BCS_DST_Y((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
566
567/* There are 16 GPR registers */
568#define BCS_GPR(n)((const i915_reg_t){ .reg = (0x22600 + (n) * 8) }) _MMIO(0x22600 + (n) * 8)((const i915_reg_t){ .reg = (0x22600 + (n) * 8) })
569#define BCS_GPR_UDW(n)((const i915_reg_t){ .reg = (0x22600 + (n) * 8 + 4) }) _MMIO(0x22600 + (n) * 8 + 4)((const i915_reg_t){ .reg = (0x22600 + (n) * 8 + 4) })
570
571#define GPGPU_THREADS_DISPATCHED((const i915_reg_t){ .reg = (0x2290) }) _MMIO(0x2290)((const i915_reg_t){ .reg = (0x2290) })
572#define GPGPU_THREADS_DISPATCHED_UDW((const i915_reg_t){ .reg = (0x2290 + 4) }) _MMIO(0x2290 + 4)((const i915_reg_t){ .reg = (0x2290 + 4) })
573#define HS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2300) }) _MMIO(0x2300)((const i915_reg_t){ .reg = (0x2300) })
574#define HS_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2300 + 4) }) _MMIO(0x2300 + 4)((const i915_reg_t){ .reg = (0x2300 + 4) })
575#define DS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2308) }) _MMIO(0x2308)((const i915_reg_t){ .reg = (0x2308) })
576#define DS_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2308 + 4) }) _MMIO(0x2308 + 4)((const i915_reg_t){ .reg = (0x2308 + 4) })
577#define IA_VERTICES_COUNT((const i915_reg_t){ .reg = (0x2310) }) _MMIO(0x2310)((const i915_reg_t){ .reg = (0x2310) })
578#define IA_VERTICES_COUNT_UDW((const i915_reg_t){ .reg = (0x2310 + 4) }) _MMIO(0x2310 + 4)((const i915_reg_t){ .reg = (0x2310 + 4) })
579#define IA_PRIMITIVES_COUNT((const i915_reg_t){ .reg = (0x2318) }) _MMIO(0x2318)((const i915_reg_t){ .reg = (0x2318) })
580#define IA_PRIMITIVES_COUNT_UDW((const i915_reg_t){ .reg = (0x2318 + 4) }) _MMIO(0x2318 + 4)((const i915_reg_t){ .reg = (0x2318 + 4) })
581#define VS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2320) }) _MMIO(0x2320)((const i915_reg_t){ .reg = (0x2320) })
582#define VS_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2320 + 4) }) _MMIO(0x2320 + 4)((const i915_reg_t){ .reg = (0x2320 + 4) })
583#define GS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2328) }) _MMIO(0x2328)((const i915_reg_t){ .reg = (0x2328) })
584#define GS_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2328 + 4) }) _MMIO(0x2328 + 4)((const i915_reg_t){ .reg = (0x2328 + 4) })
585#define GS_PRIMITIVES_COUNT((const i915_reg_t){ .reg = (0x2330) }) _MMIO(0x2330)((const i915_reg_t){ .reg = (0x2330) })
586#define GS_PRIMITIVES_COUNT_UDW((const i915_reg_t){ .reg = (0x2330 + 4) }) _MMIO(0x2330 + 4)((const i915_reg_t){ .reg = (0x2330 + 4) })
587#define CL_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2338) }) _MMIO(0x2338)((const i915_reg_t){ .reg = (0x2338) })
588#define CL_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2338 + 4) }) _MMIO(0x2338 + 4)((const i915_reg_t){ .reg = (0x2338 + 4) })
589#define CL_PRIMITIVES_COUNT((const i915_reg_t){ .reg = (0x2340) }) _MMIO(0x2340)((const i915_reg_t){ .reg = (0x2340) })
590#define CL_PRIMITIVES_COUNT_UDW((const i915_reg_t){ .reg = (0x2340 + 4) }) _MMIO(0x2340 + 4)((const i915_reg_t){ .reg = (0x2340 + 4) })
591#define PS_INVOCATION_COUNT((const i915_reg_t){ .reg = (0x2348) }) _MMIO(0x2348)((const i915_reg_t){ .reg = (0x2348) })
592#define PS_INVOCATION_COUNT_UDW((const i915_reg_t){ .reg = (0x2348 + 4) }) _MMIO(0x2348 + 4)((const i915_reg_t){ .reg = (0x2348 + 4) })
593#define PS_DEPTH_COUNT((const i915_reg_t){ .reg = (0x2350) }) _MMIO(0x2350)((const i915_reg_t){ .reg = (0x2350) })
594#define PS_DEPTH_COUNT_UDW((const i915_reg_t){ .reg = (0x2350 + 4) }) _MMIO(0x2350 + 4)((const i915_reg_t){ .reg = (0x2350 + 4) })
595
596/* There are the 4 64-bit counter registers, one for each stream output */
597#define GEN7_SO_NUM_PRIMS_WRITTEN(n)((const i915_reg_t){ .reg = (0x5200 + (n) * 8) }) _MMIO(0x5200 + (n) * 8)((const i915_reg_t){ .reg = (0x5200 + (n) * 8) })
598#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)((const i915_reg_t){ .reg = (0x5200 + (n) * 8 + 4) }) _MMIO(0x5200 + (n) * 8 + 4)((const i915_reg_t){ .reg = (0x5200 + (n) * 8 + 4) })
599
600#define GEN7_SO_PRIM_STORAGE_NEEDED(n)((const i915_reg_t){ .reg = (0x5240 + (n) * 8) }) _MMIO(0x5240 + (n) * 8)((const i915_reg_t){ .reg = (0x5240 + (n) * 8) })
601#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)((const i915_reg_t){ .reg = (0x5240 + (n) * 8 + 4) }) _MMIO(0x5240 + (n) * 8 + 4)((const i915_reg_t){ .reg = (0x5240 + (n) * 8 + 4) })
602
603#define GEN7_3DPRIM_END_OFFSET((const i915_reg_t){ .reg = (0x2420) }) _MMIO(0x2420)((const i915_reg_t){ .reg = (0x2420) })
604#define GEN7_3DPRIM_START_VERTEX((const i915_reg_t){ .reg = (0x2430) }) _MMIO(0x2430)((const i915_reg_t){ .reg = (0x2430) })
605#define GEN7_3DPRIM_VERTEX_COUNT((const i915_reg_t){ .reg = (0x2434) }) _MMIO(0x2434)((const i915_reg_t){ .reg = (0x2434) })
606#define GEN7_3DPRIM_INSTANCE_COUNT((const i915_reg_t){ .reg = (0x2438) }) _MMIO(0x2438)((const i915_reg_t){ .reg = (0x2438) })
607#define GEN7_3DPRIM_START_INSTANCE((const i915_reg_t){ .reg = (0x243C) }) _MMIO(0x243C)((const i915_reg_t){ .reg = (0x243C) })
608#define GEN7_3DPRIM_BASE_VERTEX((const i915_reg_t){ .reg = (0x2440) }) _MMIO(0x2440)((const i915_reg_t){ .reg = (0x2440) })
609
610#define GEN7_GPGPU_DISPATCHDIMX((const i915_reg_t){ .reg = (0x2500) }) _MMIO(0x2500)((const i915_reg_t){ .reg = (0x2500) })
611#define GEN7_GPGPU_DISPATCHDIMY((const i915_reg_t){ .reg = (0x2504) }) _MMIO(0x2504)((const i915_reg_t){ .reg = (0x2504) })
612#define GEN7_GPGPU_DISPATCHDIMZ((const i915_reg_t){ .reg = (0x2508) }) _MMIO(0x2508)((const i915_reg_t){ .reg = (0x2508) })
613
614/* There are the 16 64-bit CS General Purpose Registers */
615#define HSW_CS_GPR(n)((const i915_reg_t){ .reg = (0x2600 + (n) * 8) }) _MMIO(0x2600 + (n) * 8)((const i915_reg_t){ .reg = (0x2600 + (n) * 8) })
616#define HSW_CS_GPR_UDW(n)((const i915_reg_t){ .reg = (0x2600 + (n) * 8 + 4) }) _MMIO(0x2600 + (n) * 8 + 4)((const i915_reg_t){ .reg = (0x2600 + (n) * 8 + 4) })
617
618#define GEN7_OACONTROL((const i915_reg_t){ .reg = (0x2360) }) _MMIO(0x2360)((const i915_reg_t){ .reg = (0x2360) })
619#define GEN7_OACONTROL_CTX_MASK0xFFFFF000 0xFFFFF000
620#define GEN7_OACONTROL_TIMER_PERIOD_MASK0x3F 0x3F
621#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT6 6
622#define GEN7_OACONTROL_TIMER_ENABLE(1 << 5) (1 << 5)
623#define GEN7_OACONTROL_FORMAT_A13(0 << 2) (0 << 2)
624#define GEN7_OACONTROL_FORMAT_A29(1 << 2) (1 << 2)
625#define GEN7_OACONTROL_FORMAT_A13_B8_C8(2 << 2) (2 << 2)
626#define GEN7_OACONTROL_FORMAT_A29_B8_C8(3 << 2) (3 << 2)
627#define GEN7_OACONTROL_FORMAT_B4_C8(4 << 2) (4 << 2)
628#define GEN7_OACONTROL_FORMAT_A45_B8_C8(5 << 2) (5 << 2)
629#define GEN7_OACONTROL_FORMAT_B4_C8_A16(6 << 2) (6 << 2)
630#define GEN7_OACONTROL_FORMAT_C4_B8(7 << 2) (7 << 2)
631#define GEN7_OACONTROL_FORMAT_SHIFT2 2
632#define GEN7_OACONTROL_PER_CTX_ENABLE(1 << 1) (1 << 1)
633#define GEN7_OACONTROL_ENABLE(1 << 0) (1 << 0)
634
635#define GEN8_OACTXID((const i915_reg_t){ .reg = (0x2364) }) _MMIO(0x2364)((const i915_reg_t){ .reg = (0x2364) })
636
637#define GEN8_OA_DEBUG((const i915_reg_t){ .reg = (0x2B04) }) _MMIO(0x2B04)((const i915_reg_t){ .reg = (0x2B04) })
638#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS(1 << 5) (1 << 5)
639#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO(1 << 6) (1 << 6)
640#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS(1 << 2) (1 << 2)
641#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS(1 << 1) (1 << 1)
642
643#define GEN8_OACONTROL((const i915_reg_t){ .reg = (0x2B00) }) _MMIO(0x2B00)((const i915_reg_t){ .reg = (0x2B00) })
644#define GEN8_OA_REPORT_FORMAT_A12(0 << 2) (0 << 2)
645#define GEN8_OA_REPORT_FORMAT_A12_B8_C8(2 << 2) (2 << 2)
646#define GEN8_OA_REPORT_FORMAT_A36_B8_C8(5 << 2) (5 << 2)
647#define GEN8_OA_REPORT_FORMAT_C4_B8(7 << 2) (7 << 2)
648#define GEN8_OA_REPORT_FORMAT_SHIFT2 2
649#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE(1 << 1) (1 << 1)
650#define GEN8_OA_COUNTER_ENABLE(1 << 0) (1 << 0)
651
652#define GEN8_OACTXCONTROL((const i915_reg_t){ .reg = (0x2360) }) _MMIO(0x2360)((const i915_reg_t){ .reg = (0x2360) })
653#define GEN8_OA_TIMER_PERIOD_MASK0x3F 0x3F
654#define GEN8_OA_TIMER_PERIOD_SHIFT2 2
655#define GEN8_OA_TIMER_ENABLE(1 << 1) (1 << 1)
656#define GEN8_OA_COUNTER_RESUME(1 << 0) (1 << 0)
657
658#define GEN7_OABUFFER((const i915_reg_t){ .reg = (0x23B0) }) _MMIO(0x23B0)((const i915_reg_t){ .reg = (0x23B0) }) /* R/W */
659#define GEN7_OABUFFER_OVERRUN_DISABLE(1 << 3) (1 << 3)
660#define GEN7_OABUFFER_EDGE_TRIGGER(1 << 2) (1 << 2)
661#define GEN7_OABUFFER_STOP_RESUME_ENABLE(1 << 1) (1 << 1)
662#define GEN7_OABUFFER_RESUME(1 << 0) (1 << 0)
663
664#define GEN8_OABUFFER_UDW((const i915_reg_t){ .reg = (0x23b4) }) _MMIO(0x23b4)((const i915_reg_t){ .reg = (0x23b4) })
665#define GEN8_OABUFFER((const i915_reg_t){ .reg = (0x2b14) }) _MMIO(0x2b14)((const i915_reg_t){ .reg = (0x2b14) })
666#define GEN8_OABUFFER_MEM_SELECT_GGTT(1 << 0) (1 << 0) /* 0: PPGTT, 1: GGTT */
667
668#define GEN7_OASTATUS1((const i915_reg_t){ .reg = (0x2364) }) _MMIO(0x2364)((const i915_reg_t){ .reg = (0x2364) })
669#define GEN7_OASTATUS1_TAIL_MASK0xffffffc0 0xffffffc0
670#define GEN7_OASTATUS1_COUNTER_OVERFLOW(1 << 2) (1 << 2)
671#define GEN7_OASTATUS1_OABUFFER_OVERFLOW(1 << 1) (1 << 1)
672#define GEN7_OASTATUS1_REPORT_LOST(1 << 0) (1 << 0)
673
674#define GEN7_OASTATUS2((const i915_reg_t){ .reg = (0x2368) }) _MMIO(0x2368)((const i915_reg_t){ .reg = (0x2368) })
675#define GEN7_OASTATUS2_HEAD_MASK0xffffffc0 0xffffffc0
676#define GEN7_OASTATUS2_MEM_SELECT_GGTT(1 << 0) (1 << 0) /* 0: PPGTT, 1: GGTT */
677
678#define GEN8_OASTATUS((const i915_reg_t){ .reg = (0x2b08) }) _MMIO(0x2b08)((const i915_reg_t){ .reg = (0x2b08) })
679#define GEN8_OASTATUS_TAIL_POINTER_WRAP(1 << 17) (1 << 17)
680#define GEN8_OASTATUS_HEAD_POINTER_WRAP(1 << 16) (1 << 16)
681#define GEN8_OASTATUS_OVERRUN_STATUS(1 << 3) (1 << 3)
682#define GEN8_OASTATUS_COUNTER_OVERFLOW(1 << 2) (1 << 2)
683#define GEN8_OASTATUS_OABUFFER_OVERFLOW(1 << 1) (1 << 1)
684#define GEN8_OASTATUS_REPORT_LOST(1 << 0) (1 << 0)
685
686#define GEN8_OAHEADPTR((const i915_reg_t){ .reg = (0x2B0C) }) _MMIO(0x2B0C)((const i915_reg_t){ .reg = (0x2B0C) })
687#define GEN8_OAHEADPTR_MASK0xffffffc0 0xffffffc0
688#define GEN8_OATAILPTR((const i915_reg_t){ .reg = (0x2B10) }) _MMIO(0x2B10)((const i915_reg_t){ .reg = (0x2B10) })
689#define GEN8_OATAILPTR_MASK0xffffffc0 0xffffffc0
690
691#define OABUFFER_SIZE_128K(0 << 3) (0 << 3)
692#define OABUFFER_SIZE_256K(1 << 3) (1 << 3)
693#define OABUFFER_SIZE_512K(2 << 3) (2 << 3)
694#define OABUFFER_SIZE_1M(3 << 3) (3 << 3)
695#define OABUFFER_SIZE_2M(4 << 3) (4 << 3)
696#define OABUFFER_SIZE_4M(5 << 3) (5 << 3)
697#define OABUFFER_SIZE_8M(6 << 3) (6 << 3)
698#define OABUFFER_SIZE_16M(7 << 3) (7 << 3)
699
700#define GEN12_OA_TLB_INV_CR((const i915_reg_t){ .reg = (0xceec) }) _MMIO(0xceec)((const i915_reg_t){ .reg = (0xceec) })
701
702/* Gen12 OAR unit */
703#define GEN12_OAR_OACONTROL((const i915_reg_t){ .reg = (0x2960) }) _MMIO(0x2960)((const i915_reg_t){ .reg = (0x2960) })
704#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT1 1
705#define GEN12_OAR_OACONTROL_COUNTER_ENABLE(1 << 0) (1 << 0)
706
707#define GEN12_OACTXCONTROL((const i915_reg_t){ .reg = (0x2360) }) _MMIO(0x2360)((const i915_reg_t){ .reg = (0x2360) })
708#define GEN12_OAR_OASTATUS((const i915_reg_t){ .reg = (0x2968) }) _MMIO(0x2968)((const i915_reg_t){ .reg = (0x2968) })
709
710/* Gen12 OAG unit */
711#define GEN12_OAG_OAHEADPTR((const i915_reg_t){ .reg = (0xdb00) }) _MMIO(0xdb00)((const i915_reg_t){ .reg = (0xdb00) })
712#define GEN12_OAG_OAHEADPTR_MASK0xffffffc0 0xffffffc0
713#define GEN12_OAG_OATAILPTR((const i915_reg_t){ .reg = (0xdb04) }) _MMIO(0xdb04)((const i915_reg_t){ .reg = (0xdb04) })
714#define GEN12_OAG_OATAILPTR_MASK0xffffffc0 0xffffffc0
715
716#define GEN12_OAG_OABUFFER((const i915_reg_t){ .reg = (0xdb08) }) _MMIO(0xdb08)((const i915_reg_t){ .reg = (0xdb08) })
717#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK(0x7) (0x7)
718#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT(3) (3)
719#define GEN12_OAG_OABUFFER_MEMORY_SELECT(1 << 0) (1 << 0) /* 0: PPGTT, 1: GGTT */
720
721#define GEN12_OAG_OAGLBCTXCTRL((const i915_reg_t){ .reg = (0x2b28) }) _MMIO(0x2b28)((const i915_reg_t){ .reg = (0x2b28) })
722#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT2 2
723#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE(1 << 1) (1 << 1)
724#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME(1 << 0) (1 << 0)
725
726#define GEN12_OAG_OACONTROL((const i915_reg_t){ .reg = (0xdaf4) }) _MMIO(0xdaf4)((const i915_reg_t){ .reg = (0xdaf4) })
727#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT2 2
728#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE(1 << 0) (1 << 0)
729
730#define GEN12_OAG_OA_DEBUG((const i915_reg_t){ .reg = (0xdaf8) }) _MMIO(0xdaf8)((const i915_reg_t){ .reg = (0xdaf8) })
731#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO(1 << 6) (1 << 6)
732#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS(1 << 5) (1 << 5)
733#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS(1 << 2) (1 << 2)
734#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS(1 << 1) (1 << 1)
735
736#define GEN12_OAG_OASTATUS((const i915_reg_t){ .reg = (0xdafc) }) _MMIO(0xdafc)((const i915_reg_t){ .reg = (0xdafc) })
737#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW(1 << 2) (1 << 2)
738#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW(1 << 1) (1 << 1)
739#define GEN12_OAG_OASTATUS_REPORT_LOST(1 << 0) (1 << 0)
740
741/*
742 * Flexible, Aggregate EU Counter Registers.
743 * Note: these aren't contiguous
744 */
745#define EU_PERF_CNTL0((const i915_reg_t){ .reg = (0xe458) }) _MMIO(0xe458)((const i915_reg_t){ .reg = (0xe458) })
746#define EU_PERF_CNTL1((const i915_reg_t){ .reg = (0xe558) }) _MMIO(0xe558)((const i915_reg_t){ .reg = (0xe558) })
747#define EU_PERF_CNTL2((const i915_reg_t){ .reg = (0xe658) }) _MMIO(0xe658)((const i915_reg_t){ .reg = (0xe658) })
748#define EU_PERF_CNTL3((const i915_reg_t){ .reg = (0xe758) }) _MMIO(0xe758)((const i915_reg_t){ .reg = (0xe758) })
749#define EU_PERF_CNTL4((const i915_reg_t){ .reg = (0xe45c) }) _MMIO(0xe45c)((const i915_reg_t){ .reg = (0xe45c) })
750#define EU_PERF_CNTL5((const i915_reg_t){ .reg = (0xe55c) }) _MMIO(0xe55c)((const i915_reg_t){ .reg = (0xe55c) })
751#define EU_PERF_CNTL6((const i915_reg_t){ .reg = (0xe65c) }) _MMIO(0xe65c)((const i915_reg_t){ .reg = (0xe65c) })
752
753/*
754 * OA Boolean state
755 */
756
757#define OASTARTTRIG1((const i915_reg_t){ .reg = (0x2710) }) _MMIO(0x2710)((const i915_reg_t){ .reg = (0x2710) })
758#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ0xffff0000 0xffff0000
759#define OASTARTTRIG1_THRESHOLD_MASK0xffff 0xffff
760
761#define OASTARTTRIG2((const i915_reg_t){ .reg = (0x2714) }) _MMIO(0x2714)((const i915_reg_t){ .reg = (0x2714) })
762#define OASTARTTRIG2_INVERT_A_0(1 << 0) (1 << 0)
763#define OASTARTTRIG2_INVERT_A_1(1 << 1) (1 << 1)
764#define OASTARTTRIG2_INVERT_A_2(1 << 2) (1 << 2)
765#define OASTARTTRIG2_INVERT_A_3(1 << 3) (1 << 3)
766#define OASTARTTRIG2_INVERT_A_4(1 << 4) (1 << 4)
767#define OASTARTTRIG2_INVERT_A_5(1 << 5) (1 << 5)
768#define OASTARTTRIG2_INVERT_A_6(1 << 6) (1 << 6)
769#define OASTARTTRIG2_INVERT_A_7(1 << 7) (1 << 7)
770#define OASTARTTRIG2_INVERT_A_8(1 << 8) (1 << 8)
771#define OASTARTTRIG2_INVERT_A_9(1 << 9) (1 << 9)
772#define OASTARTTRIG2_INVERT_A_10(1 << 10) (1 << 10)
773#define OASTARTTRIG2_INVERT_A_11(1 << 11) (1 << 11)
774#define OASTARTTRIG2_INVERT_A_12(1 << 12) (1 << 12)
775#define OASTARTTRIG2_INVERT_A_13(1 << 13) (1 << 13)
776#define OASTARTTRIG2_INVERT_A_14(1 << 14) (1 << 14)
777#define OASTARTTRIG2_INVERT_A_15(1 << 15) (1 << 15)
778#define OASTARTTRIG2_INVERT_B_0(1 << 16) (1 << 16)
779#define OASTARTTRIG2_INVERT_B_1(1 << 17) (1 << 17)
780#define OASTARTTRIG2_INVERT_B_2(1 << 18) (1 << 18)
781#define OASTARTTRIG2_INVERT_B_3(1 << 19) (1 << 19)
782#define OASTARTTRIG2_INVERT_C_0(1 << 20) (1 << 20)
783#define OASTARTTRIG2_INVERT_C_1(1 << 21) (1 << 21)
784#define OASTARTTRIG2_INVERT_D_0(1 << 22) (1 << 22)
785#define OASTARTTRIG2_THRESHOLD_ENABLE(1 << 23) (1 << 23)
786#define OASTARTTRIG2_START_TRIG_FLAG_MBZ(1 << 24) (1 << 24)
787#define OASTARTTRIG2_EVENT_SELECT_0(1 << 28) (1 << 28)
788#define OASTARTTRIG2_EVENT_SELECT_1(1 << 29) (1 << 29)
789#define OASTARTTRIG2_EVENT_SELECT_2(1 << 30) (1 << 30)
790#define OASTARTTRIG2_EVENT_SELECT_3(1 << 31) (1 << 31)
791
792#define OASTARTTRIG3((const i915_reg_t){ .reg = (0x2718) }) _MMIO(0x2718)((const i915_reg_t){ .reg = (0x2718) })
793#define OASTARTTRIG3_NOA_SELECT_MASK0xf 0xf
794#define OASTARTTRIG3_NOA_SELECT_8_SHIFT0 0
795#define OASTARTTRIG3_NOA_SELECT_9_SHIFT4 4
796#define OASTARTTRIG3_NOA_SELECT_10_SHIFT8 8
797#define OASTARTTRIG3_NOA_SELECT_11_SHIFT12 12
798#define OASTARTTRIG3_NOA_SELECT_12_SHIFT16 16
799#define OASTARTTRIG3_NOA_SELECT_13_SHIFT20 20
800#define OASTARTTRIG3_NOA_SELECT_14_SHIFT24 24
801#define OASTARTTRIG3_NOA_SELECT_15_SHIFT28 28
802
803#define OASTARTTRIG4((const i915_reg_t){ .reg = (0x271c) }) _MMIO(0x271c)((const i915_reg_t){ .reg = (0x271c) })
804#define OASTARTTRIG4_NOA_SELECT_MASK0xf 0xf
805#define OASTARTTRIG4_NOA_SELECT_0_SHIFT0 0
806#define OASTARTTRIG4_NOA_SELECT_1_SHIFT4 4
807#define OASTARTTRIG4_NOA_SELECT_2_SHIFT8 8
808#define OASTARTTRIG4_NOA_SELECT_3_SHIFT12 12
809#define OASTARTTRIG4_NOA_SELECT_4_SHIFT16 16
810#define OASTARTTRIG4_NOA_SELECT_5_SHIFT20 20
811#define OASTARTTRIG4_NOA_SELECT_6_SHIFT24 24
812#define OASTARTTRIG4_NOA_SELECT_7_SHIFT28 28
813
814#define OASTARTTRIG5((const i915_reg_t){ .reg = (0x2720) }) _MMIO(0x2720)((const i915_reg_t){ .reg = (0x2720) })
815#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ0xffff0000 0xffff0000
816#define OASTARTTRIG5_THRESHOLD_MASK0xffff 0xffff
817
818#define OASTARTTRIG6((const i915_reg_t){ .reg = (0x2724) }) _MMIO(0x2724)((const i915_reg_t){ .reg = (0x2724) })
819#define OASTARTTRIG6_INVERT_A_0(1 << 0) (1 << 0)
820#define OASTARTTRIG6_INVERT_A_1(1 << 1) (1 << 1)
821#define OASTARTTRIG6_INVERT_A_2(1 << 2) (1 << 2)
822#define OASTARTTRIG6_INVERT_A_3(1 << 3) (1 << 3)
823#define OASTARTTRIG6_INVERT_A_4(1 << 4) (1 << 4)
824#define OASTARTTRIG6_INVERT_A_5(1 << 5) (1 << 5)
825#define OASTARTTRIG6_INVERT_A_6(1 << 6) (1 << 6)
826#define OASTARTTRIG6_INVERT_A_7(1 << 7) (1 << 7)
827#define OASTARTTRIG6_INVERT_A_8(1 << 8) (1 << 8)
828#define OASTARTTRIG6_INVERT_A_9(1 << 9) (1 << 9)
829#define OASTARTTRIG6_INVERT_A_10(1 << 10) (1 << 10)
830#define OASTARTTRIG6_INVERT_A_11(1 << 11) (1 << 11)
831#define OASTARTTRIG6_INVERT_A_12(1 << 12) (1 << 12)
832#define OASTARTTRIG6_INVERT_A_13(1 << 13) (1 << 13)
833#define OASTARTTRIG6_INVERT_A_14(1 << 14) (1 << 14)
834#define OASTARTTRIG6_INVERT_A_15(1 << 15) (1 << 15)
835#define OASTARTTRIG6_INVERT_B_0(1 << 16) (1 << 16)
836#define OASTARTTRIG6_INVERT_B_1(1 << 17) (1 << 17)
837#define OASTARTTRIG6_INVERT_B_2(1 << 18) (1 << 18)
838#define OASTARTTRIG6_INVERT_B_3(1 << 19) (1 << 19)
839#define OASTARTTRIG6_INVERT_C_0(1 << 20) (1 << 20)
840#define OASTARTTRIG6_INVERT_C_1(1 << 21) (1 << 21)
841#define OASTARTTRIG6_INVERT_D_0(1 << 22) (1 << 22)
842#define OASTARTTRIG6_THRESHOLD_ENABLE(1 << 23) (1 << 23)
843#define OASTARTTRIG6_START_TRIG_FLAG_MBZ(1 << 24) (1 << 24)
844#define OASTARTTRIG6_EVENT_SELECT_4(1 << 28) (1 << 28)
845#define OASTARTTRIG6_EVENT_SELECT_5(1 << 29) (1 << 29)
846#define OASTARTTRIG6_EVENT_SELECT_6(1 << 30) (1 << 30)
847#define OASTARTTRIG6_EVENT_SELECT_7(1 << 31) (1 << 31)
848
849#define OASTARTTRIG7((const i915_reg_t){ .reg = (0x2728) }) _MMIO(0x2728)((const i915_reg_t){ .reg = (0x2728) })
850#define OASTARTTRIG7_NOA_SELECT_MASK0xf 0xf
851#define OASTARTTRIG7_NOA_SELECT_8_SHIFT0 0
852#define OASTARTTRIG7_NOA_SELECT_9_SHIFT4 4
853#define OASTARTTRIG7_NOA_SELECT_10_SHIFT8 8
854#define OASTARTTRIG7_NOA_SELECT_11_SHIFT12 12
855#define OASTARTTRIG7_NOA_SELECT_12_SHIFT16 16
856#define OASTARTTRIG7_NOA_SELECT_13_SHIFT20 20
857#define OASTARTTRIG7_NOA_SELECT_14_SHIFT24 24
858#define OASTARTTRIG7_NOA_SELECT_15_SHIFT28 28
859
860#define OASTARTTRIG8((const i915_reg_t){ .reg = (0x272c) }) _MMIO(0x272c)((const i915_reg_t){ .reg = (0x272c) })
861#define OASTARTTRIG8_NOA_SELECT_MASK0xf 0xf
862#define OASTARTTRIG8_NOA_SELECT_0_SHIFT0 0
863#define OASTARTTRIG8_NOA_SELECT_1_SHIFT4 4
864#define OASTARTTRIG8_NOA_SELECT_2_SHIFT8 8
865#define OASTARTTRIG8_NOA_SELECT_3_SHIFT12 12
866#define OASTARTTRIG8_NOA_SELECT_4_SHIFT16 16
867#define OASTARTTRIG8_NOA_SELECT_5_SHIFT20 20
868#define OASTARTTRIG8_NOA_SELECT_6_SHIFT24 24
869#define OASTARTTRIG8_NOA_SELECT_7_SHIFT28 28
870
871#define OAREPORTTRIG1((const i915_reg_t){ .reg = (0x2740) }) _MMIO(0x2740)((const i915_reg_t){ .reg = (0x2740) })
872#define OAREPORTTRIG1_THRESHOLD_MASK0xffff 0xffff
873#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK0xffff0000 0xffff0000 /* 0=level */
874
875#define OAREPORTTRIG2((const i915_reg_t){ .reg = (0x2744) }) _MMIO(0x2744)((const i915_reg_t){ .reg = (0x2744) })
876#define OAREPORTTRIG2_INVERT_A_0(1 << 0) (1 << 0)
877#define OAREPORTTRIG2_INVERT_A_1(1 << 1) (1 << 1)
878#define OAREPORTTRIG2_INVERT_A_2(1 << 2) (1 << 2)
879#define OAREPORTTRIG2_INVERT_A_3(1 << 3) (1 << 3)
880#define OAREPORTTRIG2_INVERT_A_4(1 << 4) (1 << 4)
881#define OAREPORTTRIG2_INVERT_A_5(1 << 5) (1 << 5)
882#define OAREPORTTRIG2_INVERT_A_6(1 << 6) (1 << 6)
883#define OAREPORTTRIG2_INVERT_A_7(1 << 7) (1 << 7)
884#define OAREPORTTRIG2_INVERT_A_8(1 << 8) (1 << 8)
885#define OAREPORTTRIG2_INVERT_A_9(1 << 9) (1 << 9)
886#define OAREPORTTRIG2_INVERT_A_10(1 << 10) (1 << 10)
887#define OAREPORTTRIG2_INVERT_A_11(1 << 11) (1 << 11)
888#define OAREPORTTRIG2_INVERT_A_12(1 << 12) (1 << 12)
889#define OAREPORTTRIG2_INVERT_A_13(1 << 13) (1 << 13)
890#define OAREPORTTRIG2_INVERT_A_14(1 << 14) (1 << 14)
891#define OAREPORTTRIG2_INVERT_A_15(1 << 15) (1 << 15)
892#define OAREPORTTRIG2_INVERT_B_0(1 << 16) (1 << 16)
893#define OAREPORTTRIG2_INVERT_B_1(1 << 17) (1 << 17)
894#define OAREPORTTRIG2_INVERT_B_2(1 << 18) (1 << 18)
895#define OAREPORTTRIG2_INVERT_B_3(1 << 19) (1 << 19)
896#define OAREPORTTRIG2_INVERT_C_0(1 << 20) (1 << 20)
897#define OAREPORTTRIG2_INVERT_C_1(1 << 21) (1 << 21)
898#define OAREPORTTRIG2_INVERT_D_0(1 << 22) (1 << 22)
899#define OAREPORTTRIG2_THRESHOLD_ENABLE(1 << 23) (1 << 23)
900#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE(1 << 31) (1 << 31)
901
902#define OAREPORTTRIG3((const i915_reg_t){ .reg = (0x2748) }) _MMIO(0x2748)((const i915_reg_t){ .reg = (0x2748) })
903#define OAREPORTTRIG3_NOA_SELECT_MASK0xf 0xf
904#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT0 0
905#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT4 4
906#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT8 8
907#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT12 12
908#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT16 16
909#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT20 20
910#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT24 24
911#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT28 28
912
913#define OAREPORTTRIG4((const i915_reg_t){ .reg = (0x274c) }) _MMIO(0x274c)((const i915_reg_t){ .reg = (0x274c) })
914#define OAREPORTTRIG4_NOA_SELECT_MASK0xf 0xf
915#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT0 0
916#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT4 4
917#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT8 8
918#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT12 12
919#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT16 16
920#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT20 20
921#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT24 24
922#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT28 28
923
924#define OAREPORTTRIG5((const i915_reg_t){ .reg = (0x2750) }) _MMIO(0x2750)((const i915_reg_t){ .reg = (0x2750) })
925#define OAREPORTTRIG5_THRESHOLD_MASK0xffff 0xffff
926#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK0xffff0000 0xffff0000 /* 0=level */
927
928#define OAREPORTTRIG6((const i915_reg_t){ .reg = (0x2754) }) _MMIO(0x2754)((const i915_reg_t){ .reg = (0x2754) })
929#define OAREPORTTRIG6_INVERT_A_0(1 << 0) (1 << 0)
930#define OAREPORTTRIG6_INVERT_A_1(1 << 1) (1 << 1)
931#define OAREPORTTRIG6_INVERT_A_2(1 << 2) (1 << 2)
932#define OAREPORTTRIG6_INVERT_A_3(1 << 3) (1 << 3)
933#define OAREPORTTRIG6_INVERT_A_4(1 << 4) (1 << 4)
934#define OAREPORTTRIG6_INVERT_A_5(1 << 5) (1 << 5)
935#define OAREPORTTRIG6_INVERT_A_6(1 << 6) (1 << 6)
936#define OAREPORTTRIG6_INVERT_A_7(1 << 7) (1 << 7)
937#define OAREPORTTRIG6_INVERT_A_8(1 << 8) (1 << 8)
938#define OAREPORTTRIG6_INVERT_A_9(1 << 9) (1 << 9)
939#define OAREPORTTRIG6_INVERT_A_10(1 << 10) (1 << 10)
940#define OAREPORTTRIG6_INVERT_A_11(1 << 11) (1 << 11)
941#define OAREPORTTRIG6_INVERT_A_12(1 << 12) (1 << 12)
942#define OAREPORTTRIG6_INVERT_A_13(1 << 13) (1 << 13)
943#define OAREPORTTRIG6_INVERT_A_14(1 << 14) (1 << 14)
944#define OAREPORTTRIG6_INVERT_A_15(1 << 15) (1 << 15)
945#define OAREPORTTRIG6_INVERT_B_0(1 << 16) (1 << 16)
946#define OAREPORTTRIG6_INVERT_B_1(1 << 17) (1 << 17)
947#define OAREPORTTRIG6_INVERT_B_2(1 << 18) (1 << 18)
948#define OAREPORTTRIG6_INVERT_B_3(1 << 19) (1 << 19)
949#define OAREPORTTRIG6_INVERT_C_0(1 << 20) (1 << 20)
950#define OAREPORTTRIG6_INVERT_C_1(1 << 21) (1 << 21)
951#define OAREPORTTRIG6_INVERT_D_0(1 << 22) (1 << 22)
952#define OAREPORTTRIG6_THRESHOLD_ENABLE(1 << 23) (1 << 23)
953#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE(1 << 31) (1 << 31)
954
955#define OAREPORTTRIG7((const i915_reg_t){ .reg = (0x2758) }) _MMIO(0x2758)((const i915_reg_t){ .reg = (0x2758) })
956#define OAREPORTTRIG7_NOA_SELECT_MASK0xf 0xf
957#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT0 0
958#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT4 4
959#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT8 8
960#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT12 12
961#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT16 16
962#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT20 20
963#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT24 24
964#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT28 28
965
966#define OAREPORTTRIG8((const i915_reg_t){ .reg = (0x275c) }) _MMIO(0x275c)((const i915_reg_t){ .reg = (0x275c) })
967#define OAREPORTTRIG8_NOA_SELECT_MASK0xf 0xf
968#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT0 0
969#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT4 4
970#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT8 8
971#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT12 12
972#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT16 16
973#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT20 20
974#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT24 24
975#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT28 28
976
977/* Same layout as OASTARTTRIGX */
978#define GEN12_OAG_OASTARTTRIG1((const i915_reg_t){ .reg = (0xd900) }) _MMIO(0xd900)((const i915_reg_t){ .reg = (0xd900) })
979#define GEN12_OAG_OASTARTTRIG2((const i915_reg_t){ .reg = (0xd904) }) _MMIO(0xd904)((const i915_reg_t){ .reg = (0xd904) })
980#define GEN12_OAG_OASTARTTRIG3((const i915_reg_t){ .reg = (0xd908) }) _MMIO(0xd908)((const i915_reg_t){ .reg = (0xd908) })
981#define GEN12_OAG_OASTARTTRIG4((const i915_reg_t){ .reg = (0xd90c) }) _MMIO(0xd90c)((const i915_reg_t){ .reg = (0xd90c) })
982#define GEN12_OAG_OASTARTTRIG5((const i915_reg_t){ .reg = (0xd910) }) _MMIO(0xd910)((const i915_reg_t){ .reg = (0xd910) })
983#define GEN12_OAG_OASTARTTRIG6((const i915_reg_t){ .reg = (0xd914) }) _MMIO(0xd914)((const i915_reg_t){ .reg = (0xd914) })
984#define GEN12_OAG_OASTARTTRIG7((const i915_reg_t){ .reg = (0xd918) }) _MMIO(0xd918)((const i915_reg_t){ .reg = (0xd918) })
985#define GEN12_OAG_OASTARTTRIG8((const i915_reg_t){ .reg = (0xd91c) }) _MMIO(0xd91c)((const i915_reg_t){ .reg = (0xd91c) })
986
987/* Same layout as OAREPORTTRIGX */
988#define GEN12_OAG_OAREPORTTRIG1((const i915_reg_t){ .reg = (0xd920) }) _MMIO(0xd920)((const i915_reg_t){ .reg = (0xd920) })
989#define GEN12_OAG_OAREPORTTRIG2((const i915_reg_t){ .reg = (0xd924) }) _MMIO(0xd924)((const i915_reg_t){ .reg = (0xd924) })
990#define GEN12_OAG_OAREPORTTRIG3((const i915_reg_t){ .reg = (0xd928) }) _MMIO(0xd928)((const i915_reg_t){ .reg = (0xd928) })
991#define GEN12_OAG_OAREPORTTRIG4((const i915_reg_t){ .reg = (0xd92c) }) _MMIO(0xd92c)((const i915_reg_t){ .reg = (0xd92c) })
992#define GEN12_OAG_OAREPORTTRIG5((const i915_reg_t){ .reg = (0xd930) }) _MMIO(0xd930)((const i915_reg_t){ .reg = (0xd930) })
993#define GEN12_OAG_OAREPORTTRIG6((const i915_reg_t){ .reg = (0xd934) }) _MMIO(0xd934)((const i915_reg_t){ .reg = (0xd934) })
994#define GEN12_OAG_OAREPORTTRIG7((const i915_reg_t){ .reg = (0xd938) }) _MMIO(0xd938)((const i915_reg_t){ .reg = (0xd938) })
995#define GEN12_OAG_OAREPORTTRIG8((const i915_reg_t){ .reg = (0xd93c) }) _MMIO(0xd93c)((const i915_reg_t){ .reg = (0xd93c) })
996
997/* CECX_0 */
998#define OACEC_COMPARE_LESS_OR_EQUAL6 6
999#define OACEC_COMPARE_NOT_EQUAL5 5
1000#define OACEC_COMPARE_LESS_THAN4 4
1001#define OACEC_COMPARE_GREATER_OR_EQUAL3 3
1002#define OACEC_COMPARE_EQUAL2 2
1003#define OACEC_COMPARE_GREATER_THAN1 1
1004#define OACEC_COMPARE_ANY_EQUAL0 0
1005
1006#define OACEC_COMPARE_VALUE_MASK0xffff 0xffff
1007#define OACEC_COMPARE_VALUE_SHIFT3 3
1008
1009#define OACEC_SELECT_NOA(0 << 19) (0 << 19)
1010#define OACEC_SELECT_PREV(1 << 19) (1 << 19)
1011#define OACEC_SELECT_BOOLEAN(2 << 19) (2 << 19)
1012
1013/* 11-bit array 0: pass-through, 1: negated */
1014#define GEN12_OASCEC_NEGATE_MASK0x7ff 0x7ff
1015#define GEN12_OASCEC_NEGATE_SHIFT21 21
1016
1017/* CECX_1 */
1018#define OACEC_MASK_MASK0xffff 0xffff
1019#define OACEC_CONSIDERATIONS_MASK0xffff 0xffff
1020#define OACEC_CONSIDERATIONS_SHIFT16 16
1021
1022#define OACEC0_0((const i915_reg_t){ .reg = (0x2770) }) _MMIO(0x2770)((const i915_reg_t){ .reg = (0x2770) })
1023#define OACEC0_1((const i915_reg_t){ .reg = (0x2774) }) _MMIO(0x2774)((const i915_reg_t){ .reg = (0x2774) })
1024#define OACEC1_0((const i915_reg_t){ .reg = (0x2778) }) _MMIO(0x2778)((const i915_reg_t){ .reg = (0x2778) })
1025#define OACEC1_1((const i915_reg_t){ .reg = (0x277c) }) _MMIO(0x277c)((const i915_reg_t){ .reg = (0x277c) })
1026#define OACEC2_0((const i915_reg_t){ .reg = (0x2780) }) _MMIO(0x2780)((const i915_reg_t){ .reg = (0x2780) })
1027#define OACEC2_1((const i915_reg_t){ .reg = (0x2784) }) _MMIO(0x2784)((const i915_reg_t){ .reg = (0x2784) })
1028#define OACEC3_0((const i915_reg_t){ .reg = (0x2788) }) _MMIO(0x2788)((const i915_reg_t){ .reg = (0x2788) })
1029#define OACEC3_1((const i915_reg_t){ .reg = (0x278c) }) _MMIO(0x278c)((const i915_reg_t){ .reg = (0x278c) })
1030#define OACEC4_0((const i915_reg_t){ .reg = (0x2790) }) _MMIO(0x2790)((const i915_reg_t){ .reg = (0x2790) })
1031#define OACEC4_1((const i915_reg_t){ .reg = (0x2794) }) _MMIO(0x2794)((const i915_reg_t){ .reg = (0x2794) })
1032#define OACEC5_0((const i915_reg_t){ .reg = (0x2798) }) _MMIO(0x2798)((const i915_reg_t){ .reg = (0x2798) })
1033#define OACEC5_1((const i915_reg_t){ .reg = (0x279c) }) _MMIO(0x279c)((const i915_reg_t){ .reg = (0x279c) })
1034#define OACEC6_0((const i915_reg_t){ .reg = (0x27a0) }) _MMIO(0x27a0)((const i915_reg_t){ .reg = (0x27a0) })
1035#define OACEC6_1((const i915_reg_t){ .reg = (0x27a4) }) _MMIO(0x27a4)((const i915_reg_t){ .reg = (0x27a4) })
1036#define OACEC7_0((const i915_reg_t){ .reg = (0x27a8) }) _MMIO(0x27a8)((const i915_reg_t){ .reg = (0x27a8) })
1037#define OACEC7_1((const i915_reg_t){ .reg = (0x27ac) }) _MMIO(0x27ac)((const i915_reg_t){ .reg = (0x27ac) })
1038
1039/* Same layout as CECX_Y */
1040#define GEN12_OAG_CEC0_0((const i915_reg_t){ .reg = (0xd940) }) _MMIO(0xd940)((const i915_reg_t){ .reg = (0xd940) })
1041#define GEN12_OAG_CEC0_1((const i915_reg_t){ .reg = (0xd944) }) _MMIO(0xd944)((const i915_reg_t){ .reg = (0xd944) })
1042#define GEN12_OAG_CEC1_0((const i915_reg_t){ .reg = (0xd948) }) _MMIO(0xd948)((const i915_reg_t){ .reg = (0xd948) })
1043#define GEN12_OAG_CEC1_1((const i915_reg_t){ .reg = (0xd94c) }) _MMIO(0xd94c)((const i915_reg_t){ .reg = (0xd94c) })
1044#define GEN12_OAG_CEC2_0((const i915_reg_t){ .reg = (0xd950) }) _MMIO(0xd950)((const i915_reg_t){ .reg = (0xd950) })
1045#define GEN12_OAG_CEC2_1((const i915_reg_t){ .reg = (0xd954) }) _MMIO(0xd954)((const i915_reg_t){ .reg = (0xd954) })
1046#define GEN12_OAG_CEC3_0((const i915_reg_t){ .reg = (0xd958) }) _MMIO(0xd958)((const i915_reg_t){ .reg = (0xd958) })
1047#define GEN12_OAG_CEC3_1((const i915_reg_t){ .reg = (0xd95c) }) _MMIO(0xd95c)((const i915_reg_t){ .reg = (0xd95c) })
1048#define GEN12_OAG_CEC4_0((const i915_reg_t){ .reg = (0xd960) }) _MMIO(0xd960)((const i915_reg_t){ .reg = (0xd960) })
1049#define GEN12_OAG_CEC4_1((const i915_reg_t){ .reg = (0xd964) }) _MMIO(0xd964)((const i915_reg_t){ .reg = (0xd964) })
1050#define GEN12_OAG_CEC5_0((const i915_reg_t){ .reg = (0xd968) }) _MMIO(0xd968)((const i915_reg_t){ .reg = (0xd968) })
1051#define GEN12_OAG_CEC5_1((const i915_reg_t){ .reg = (0xd96c) }) _MMIO(0xd96c)((const i915_reg_t){ .reg = (0xd96c) })
1052#define GEN12_OAG_CEC6_0((const i915_reg_t){ .reg = (0xd970) }) _MMIO(0xd970)((const i915_reg_t){ .reg = (0xd970) })
1053#define GEN12_OAG_CEC6_1((const i915_reg_t){ .reg = (0xd974) }) _MMIO(0xd974)((const i915_reg_t){ .reg = (0xd974) })
1054#define GEN12_OAG_CEC7_0((const i915_reg_t){ .reg = (0xd978) }) _MMIO(0xd978)((const i915_reg_t){ .reg = (0xd978) })
1055#define GEN12_OAG_CEC7_1((const i915_reg_t){ .reg = (0xd97c) }) _MMIO(0xd97c)((const i915_reg_t){ .reg = (0xd97c) })
1056
1057/* Same layout as CECX_Y + negate 11-bit array */
1058#define GEN12_OAG_SCEC0_0((const i915_reg_t){ .reg = (0xdc00) }) _MMIO(0xdc00)((const i915_reg_t){ .reg = (0xdc00) })
1059#define GEN12_OAG_SCEC0_1((const i915_reg_t){ .reg = (0xdc04) }) _MMIO(0xdc04)((const i915_reg_t){ .reg = (0xdc04) })
1060#define GEN12_OAG_SCEC1_0((const i915_reg_t){ .reg = (0xdc08) }) _MMIO(0xdc08)((const i915_reg_t){ .reg = (0xdc08) })
1061#define GEN12_OAG_SCEC1_1((const i915_reg_t){ .reg = (0xdc0c) }) _MMIO(0xdc0c)((const i915_reg_t){ .reg = (0xdc0c) })
1062#define GEN12_OAG_SCEC2_0((const i915_reg_t){ .reg = (0xdc10) }) _MMIO(0xdc10)((const i915_reg_t){ .reg = (0xdc10) })
1063#define GEN12_OAG_SCEC2_1((const i915_reg_t){ .reg = (0xdc14) }) _MMIO(0xdc14)((const i915_reg_t){ .reg = (0xdc14) })
1064#define GEN12_OAG_SCEC3_0((const i915_reg_t){ .reg = (0xdc18) }) _MMIO(0xdc18)((const i915_reg_t){ .reg = (0xdc18) })
1065#define GEN12_OAG_SCEC3_1((const i915_reg_t){ .reg = (0xdc1c) }) _MMIO(0xdc1c)((const i915_reg_t){ .reg = (0xdc1c) })
1066#define GEN12_OAG_SCEC4_0((const i915_reg_t){ .reg = (0xdc20) }) _MMIO(0xdc20)((const i915_reg_t){ .reg = (0xdc20) })
1067#define GEN12_OAG_SCEC4_1((const i915_reg_t){ .reg = (0xdc24) }) _MMIO(0xdc24)((const i915_reg_t){ .reg = (0xdc24) })
1068#define GEN12_OAG_SCEC5_0((const i915_reg_t){ .reg = (0xdc28) }) _MMIO(0xdc28)((const i915_reg_t){ .reg = (0xdc28) })
1069#define GEN12_OAG_SCEC5_1((const i915_reg_t){ .reg = (0xdc2c) }) _MMIO(0xdc2c)((const i915_reg_t){ .reg = (0xdc2c) })
1070#define GEN12_OAG_SCEC6_0((const i915_reg_t){ .reg = (0xdc30) }) _MMIO(0xdc30)((const i915_reg_t){ .reg = (0xdc30) })
1071#define GEN12_OAG_SCEC6_1((const i915_reg_t){ .reg = (0xdc34) }) _MMIO(0xdc34)((const i915_reg_t){ .reg = (0xdc34) })
1072#define GEN12_OAG_SCEC7_0((const i915_reg_t){ .reg = (0xdc38) }) _MMIO(0xdc38)((const i915_reg_t){ .reg = (0xdc38) })
1073#define GEN12_OAG_SCEC7_1((const i915_reg_t){ .reg = (0xdc3c) }) _MMIO(0xdc3c)((const i915_reg_t){ .reg = (0xdc3c) })
1074
1075/* OA perf counters */
1076#define OA_PERFCNT1_LO((const i915_reg_t){ .reg = (0x91B8) }) _MMIO(0x91B8)((const i915_reg_t){ .reg = (0x91B8) })
1077#define OA_PERFCNT1_HI((const i915_reg_t){ .reg = (0x91BC) }) _MMIO(0x91BC)((const i915_reg_t){ .reg = (0x91BC) })
1078#define OA_PERFCNT2_LO((const i915_reg_t){ .reg = (0x91C0) }) _MMIO(0x91C0)((const i915_reg_t){ .reg = (0x91C0) })
1079#define OA_PERFCNT2_HI((const i915_reg_t){ .reg = (0x91C4) }) _MMIO(0x91C4)((const i915_reg_t){ .reg = (0x91C4) })
1080#define OA_PERFCNT3_LO((const i915_reg_t){ .reg = (0x91C8) }) _MMIO(0x91C8)((const i915_reg_t){ .reg = (0x91C8) })
1081#define OA_PERFCNT3_HI((const i915_reg_t){ .reg = (0x91CC) }) _MMIO(0x91CC)((const i915_reg_t){ .reg = (0x91CC) })
1082#define OA_PERFCNT4_LO((const i915_reg_t){ .reg = (0x91D8) }) _MMIO(0x91D8)((const i915_reg_t){ .reg = (0x91D8) })
1083#define OA_PERFCNT4_HI((const i915_reg_t){ .reg = (0x91DC) }) _MMIO(0x91DC)((const i915_reg_t){ .reg = (0x91DC) })
1084
1085#define OA_PERFMATRIX_LO((const i915_reg_t){ .reg = (0x91C8) }) _MMIO(0x91C8)((const i915_reg_t){ .reg = (0x91C8) })
1086#define OA_PERFMATRIX_HI((const i915_reg_t){ .reg = (0x91CC) }) _MMIO(0x91CC)((const i915_reg_t){ .reg = (0x91CC) })
1087
1088/* RPM unit config (Gen8+) */
1089#define RPM_CONFIG0((const i915_reg_t){ .reg = (0x0D00) }) _MMIO(0x0D00)((const i915_reg_t){ .reg = (0x0D00) })
1090#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3 3
1091#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK(1 << 3) (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3)
1092#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ0 0
1093#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ1 1
1094#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3 3
1095#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK(0x7 << 3) (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3)
1096#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ0 0
1097#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ1 1
1098#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ2 2
1099#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ3 3
1100#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT1 1
1101#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK(0x3 << 1) (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT1)
1102
1103#define RPM_CONFIG1((const i915_reg_t){ .reg = (0x0D04) }) _MMIO(0x0D04)((const i915_reg_t){ .reg = (0x0D04) })
1104#define GEN10_GT_NOA_ENABLE(1 << 9) (1 << 9)
1105
1106/* GPM unit config (Gen9+) */
1107#define CTC_MODE((const i915_reg_t){ .reg = (0xA26C) }) _MMIO(0xA26C)((const i915_reg_t){ .reg = (0xA26C) })
1108#define CTC_SOURCE_PARAMETER_MASK1 1
1109#define CTC_SOURCE_CRYSTAL_CLOCK0 0
1110#define CTC_SOURCE_DIVIDE_LOGIC1 1
1111#define CTC_SHIFT_PARAMETER_SHIFT1 1
1112#define CTC_SHIFT_PARAMETER_MASK(0x3 << 1) (0x3 << CTC_SHIFT_PARAMETER_SHIFT1)
1113
1114/* RCP unit config (Gen8+) */
1115#define RCP_CONFIG((const i915_reg_t){ .reg = (0x0D08) }) _MMIO(0x0D08)((const i915_reg_t){ .reg = (0x0D08) })
1116
1117/* NOA (HSW) */
1118#define HSW_MBVID2_NOA0((const i915_reg_t){ .reg = (0x9E80) }) _MMIO(0x9E80)((const i915_reg_t){ .reg = (0x9E80) })
1119#define HSW_MBVID2_NOA1((const i915_reg_t){ .reg = (0x9E84) }) _MMIO(0x9E84)((const i915_reg_t){ .reg = (0x9E84) })
1120#define HSW_MBVID2_NOA2((const i915_reg_t){ .reg = (0x9E88) }) _MMIO(0x9E88)((const i915_reg_t){ .reg = (0x9E88) })
1121#define HSW_MBVID2_NOA3((const i915_reg_t){ .reg = (0x9E8C) }) _MMIO(0x9E8C)((const i915_reg_t){ .reg = (0x9E8C) })
1122#define HSW_MBVID2_NOA4((const i915_reg_t){ .reg = (0x9E90) }) _MMIO(0x9E90)((const i915_reg_t){ .reg = (0x9E90) })
1123#define HSW_MBVID2_NOA5((const i915_reg_t){ .reg = (0x9E94) }) _MMIO(0x9E94)((const i915_reg_t){ .reg = (0x9E94) })
1124#define HSW_MBVID2_NOA6((const i915_reg_t){ .reg = (0x9E98) }) _MMIO(0x9E98)((const i915_reg_t){ .reg = (0x9E98) })
1125#define HSW_MBVID2_NOA7((const i915_reg_t){ .reg = (0x9E9C) }) _MMIO(0x9E9C)((const i915_reg_t){ .reg = (0x9E9C) })
1126#define HSW_MBVID2_NOA8((const i915_reg_t){ .reg = (0x9EA0) }) _MMIO(0x9EA0)((const i915_reg_t){ .reg = (0x9EA0) })
1127#define HSW_MBVID2_NOA9((const i915_reg_t){ .reg = (0x9EA4) }) _MMIO(0x9EA4)((const i915_reg_t){ .reg = (0x9EA4) })
1128
1129#define HSW_MBVID2_MISR0((const i915_reg_t){ .reg = (0x9EC0) }) _MMIO(0x9EC0)((const i915_reg_t){ .reg = (0x9EC0) })
1130
1131/* NOA (Gen8+) */
1132#define NOA_CONFIG(i)((const i915_reg_t){ .reg = (0x0D0C + (i) * 4) }) _MMIO(0x0D0C + (i) * 4)((const i915_reg_t){ .reg = (0x0D0C + (i) * 4) })
1133
1134#define MICRO_BP0_0((const i915_reg_t){ .reg = (0x9800) }) _MMIO(0x9800)((const i915_reg_t){ .reg = (0x9800) })
1135#define MICRO_BP0_2((const i915_reg_t){ .reg = (0x9804) }) _MMIO(0x9804)((const i915_reg_t){ .reg = (0x9804) })
1136#define MICRO_BP0_1((const i915_reg_t){ .reg = (0x9808) }) _MMIO(0x9808)((const i915_reg_t){ .reg = (0x9808) })
1137
1138#define MICRO_BP1_0((const i915_reg_t){ .reg = (0x980C) }) _MMIO(0x980C)((const i915_reg_t){ .reg = (0x980C) })
1139#define MICRO_BP1_2((const i915_reg_t){ .reg = (0x9810) }) _MMIO(0x9810)((const i915_reg_t){ .reg = (0x9810) })
1140#define MICRO_BP1_1((const i915_reg_t){ .reg = (0x9814) }) _MMIO(0x9814)((const i915_reg_t){ .reg = (0x9814) })
1141
1142#define MICRO_BP2_0((const i915_reg_t){ .reg = (0x9818) }) _MMIO(0x9818)((const i915_reg_t){ .reg = (0x9818) })
1143#define MICRO_BP2_2((const i915_reg_t){ .reg = (0x981C) }) _MMIO(0x981C)((const i915_reg_t){ .reg = (0x981C) })
1144#define MICRO_BP2_1((const i915_reg_t){ .reg = (0x9820) }) _MMIO(0x9820)((const i915_reg_t){ .reg = (0x9820) })
1145
1146#define MICRO_BP3_0((const i915_reg_t){ .reg = (0x9824) }) _MMIO(0x9824)((const i915_reg_t){ .reg = (0x9824) })
1147#define MICRO_BP3_2((const i915_reg_t){ .reg = (0x9828) }) _MMIO(0x9828)((const i915_reg_t){ .reg = (0x9828) })
1148#define MICRO_BP3_1((const i915_reg_t){ .reg = (0x982C) }) _MMIO(0x982C)((const i915_reg_t){ .reg = (0x982C) })
1149
1150#define MICRO_BP_TRIGGER((const i915_reg_t){ .reg = (0x9830) }) _MMIO(0x9830)((const i915_reg_t){ .reg = (0x9830) })
1151#define MICRO_BP3_COUNT_STATUS01((const i915_reg_t){ .reg = (0x9834) }) _MMIO(0x9834)((const i915_reg_t){ .reg = (0x9834) })
1152#define MICRO_BP3_COUNT_STATUS23((const i915_reg_t){ .reg = (0x9838) }) _MMIO(0x9838)((const i915_reg_t){ .reg = (0x9838) })
1153#define MICRO_BP_FIRED_ARMED((const i915_reg_t){ .reg = (0x983C) }) _MMIO(0x983C)((const i915_reg_t){ .reg = (0x983C) })
1154
1155#define GEN12_OAA_DBG_REG((const i915_reg_t){ .reg = (0xdc44) }) _MMIO(0xdc44)((const i915_reg_t){ .reg = (0xdc44) })
1156#define GEN12_OAG_OA_PESS((const i915_reg_t){ .reg = (0x2b2c) }) _MMIO(0x2b2c)((const i915_reg_t){ .reg = (0x2b2c) })
1157#define GEN12_OAG_SPCTR_CNF((const i915_reg_t){ .reg = (0xdc40) }) _MMIO(0xdc40)((const i915_reg_t){ .reg = (0xdc40) })
1158
1159#define GDT_CHICKEN_BITS((const i915_reg_t){ .reg = (0x9840) }) _MMIO(0x9840)((const i915_reg_t){ .reg = (0x9840) })
1160#define GT_NOA_ENABLE0x00000080 0x00000080
1161
1162#define NOA_DATA((const i915_reg_t){ .reg = (0x986C) }) _MMIO(0x986C)((const i915_reg_t){ .reg = (0x986C) })
1163#define NOA_WRITE((const i915_reg_t){ .reg = (0x9888) }) _MMIO(0x9888)((const i915_reg_t){ .reg = (0x9888) })
1164#define GEN10_NOA_WRITE_HIGH((const i915_reg_t){ .reg = (0x9884) }) _MMIO(0x9884)((const i915_reg_t){ .reg = (0x9884) })
1165
1166#define _GEN7_PIPEA_DE_LOAD_SL0x70068 0x70068
1167#define _GEN7_PIPEB_DE_LOAD_SL0x71068 0x71068
1168#define GEN7_PIPE_DE_LOAD_SL(pipe)((const i915_reg_t){ .reg = (((0x70068) + (pipe) * ((0x71068)
- (0x70068)))) }) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)((const i915_reg_t){ .reg = (((0x70068) + (pipe) * ((0x71068)
- (0x70068)))) })
1169
1170/*
1171 * Reset registers
1172 */
1173#define DEBUG_RESET_I830((const i915_reg_t){ .reg = (0x6070) }) _MMIO(0x6070)((const i915_reg_t){ .reg = (0x6070) })
1174#define DEBUG_RESET_FULL(1 << 7) (1 << 7)
1175#define DEBUG_RESET_RENDER(1 << 8) (1 << 8)
1176#define DEBUG_RESET_DISPLAY(1 << 9) (1 << 9)
1177
1178/*
1179 * IOSF sideband
1180 */
1181#define VLV_IOSF_DOORBELL_REQ((const i915_reg_t){ .reg = (0x180000 + 0x2100) }) _MMIO(VLV_DISPLAY_BASE + 0x2100)((const i915_reg_t){ .reg = (0x180000 + 0x2100) })
1182#define IOSF_DEVFN_SHIFT24 24
1183#define IOSF_OPCODE_SHIFT16 16
1184#define IOSF_PORT_SHIFT8 8
1185#define IOSF_BYTE_ENABLES_SHIFT4 4
1186#define IOSF_BAR_SHIFT1 1
1187#define IOSF_SB_BUSY(1 << 0) (1 << 0)
1188#define IOSF_PORT_BUNIT0x03 0x03
1189#define IOSF_PORT_PUNIT0x04 0x04
1190#define IOSF_PORT_NC0x11 0x11
1191#define IOSF_PORT_DPIO0x12 0x12
1192#define IOSF_PORT_GPIO_NC0x13 0x13
1193#define IOSF_PORT_CCK0x14 0x14
1194#define IOSF_PORT_DPIO_20x1a 0x1a
1195#define IOSF_PORT_FLISDSI0x1b 0x1b
1196#define IOSF_PORT_GPIO_SC0x48 0x48
1197#define IOSF_PORT_GPIO_SUS0xa8 0xa8
1198#define IOSF_PORT_CCU0xa9 0xa9
1199#define CHV_IOSF_PORT_GPIO_N0x13 0x13
1200#define CHV_IOSF_PORT_GPIO_SE0x48 0x48
1201#define CHV_IOSF_PORT_GPIO_E0xa8 0xa8
1202#define CHV_IOSF_PORT_GPIO_SW0xb2 0xb2
1203#define VLV_IOSF_DATA((const i915_reg_t){ .reg = (0x180000 + 0x2104) }) _MMIO(VLV_DISPLAY_BASE + 0x2104)((const i915_reg_t){ .reg = (0x180000 + 0x2104) })
1204#define VLV_IOSF_ADDR((const i915_reg_t){ .reg = (0x180000 + 0x2108) }) _MMIO(VLV_DISPLAY_BASE + 0x2108)((const i915_reg_t){ .reg = (0x180000 + 0x2108) })
1205
1206/* See configdb bunit SB addr map */
1207#define BUNIT_REG_BISOC0x11 0x11
1208
1209/* PUNIT_REG_*SSPM0 */
1210#define _SSPM0_SSC(val)((val) << 0) ((val) << 0)
1211#define SSPM0_SSC_MASK((0x3) << 0) _SSPM0_SSC(0x3)((0x3) << 0)
1212#define SSPM0_SSC_PWR_ON((0x0) << 0) _SSPM0_SSC(0x0)((0x0) << 0)
1213#define SSPM0_SSC_CLK_GATE((0x1) << 0) _SSPM0_SSC(0x1)((0x1) << 0)
1214#define SSPM0_SSC_RESET((0x2) << 0) _SSPM0_SSC(0x2)((0x2) << 0)
1215#define SSPM0_SSC_PWR_GATE((0x3) << 0) _SSPM0_SSC(0x3)((0x3) << 0)
1216#define _SSPM0_SSS(val)((val) << 24) ((val) << 24)
1217#define SSPM0_SSS_MASK((0x3) << 24) _SSPM0_SSS(0x3)((0x3) << 24)
1218#define SSPM0_SSS_PWR_ON((0x0) << 24) _SSPM0_SSS(0x0)((0x0) << 24)
1219#define SSPM0_SSS_CLK_GATE((0x1) << 24) _SSPM0_SSS(0x1)((0x1) << 24)
1220#define SSPM0_SSS_RESET((0x2) << 24) _SSPM0_SSS(0x2)((0x2) << 24)
1221#define SSPM0_SSS_PWR_GATE((0x3) << 24) _SSPM0_SSS(0x3)((0x3) << 24)
1222
1223/* PUNIT_REG_*SSPM1 */
1224#define SSPM1_FREQSTAT_SHIFT24 24
1225#define SSPM1_FREQSTAT_MASK(0x1f << 24) (0x1f << SSPM1_FREQSTAT_SHIFT24)
1226#define SSPM1_FREQGUAR_SHIFT8 8
1227#define SSPM1_FREQGUAR_MASK(0x1f << 8) (0x1f << SSPM1_FREQGUAR_SHIFT8)
1228#define SSPM1_FREQ_SHIFT0 0
1229#define SSPM1_FREQ_MASK(0x1f << 0) (0x1f << SSPM1_FREQ_SHIFT0)
1230
1231#define PUNIT_REG_VEDSSPM00x32 0x32
1232#define PUNIT_REG_VEDSSPM10x33 0x33
1233
1234#define PUNIT_REG_DSPSSPM0x36 0x36
1235#define DSPFREQSTAT_SHIFT_CHV24 24
1236#define DSPFREQSTAT_MASK_CHV(0x1f << 24) (0x1f << DSPFREQSTAT_SHIFT_CHV24)
1237#define DSPFREQGUAR_SHIFT_CHV8 8
1238#define DSPFREQGUAR_MASK_CHV(0x1f << 8) (0x1f << DSPFREQGUAR_SHIFT_CHV8)
1239#define DSPFREQSTAT_SHIFT30 30
1240#define DSPFREQSTAT_MASK(0x3 << 30) (0x3 << DSPFREQSTAT_SHIFT30)
1241#define DSPFREQGUAR_SHIFT14 14
1242#define DSPFREQGUAR_MASK(0x3 << 14) (0x3 << DSPFREQGUAR_SHIFT14)
1243#define DSP_MAXFIFO_PM5_STATUS(1 << 22) (1 << 22) /* chv */
1244#define DSP_AUTO_CDCLK_GATE_DISABLE(1 << 7) (1 << 7) /* chv */
1245#define DSP_MAXFIFO_PM5_ENABLE(1 << 6) (1 << 6) /* chv */
1246#define _DP_SSC(val, pipe)((val) << (2 * (pipe))) ((val) << (2 * (pipe)))
1247#define DP_SSC_MASK(pipe)((0x3) << (2 * ((pipe)))) _DP_SSC(0x3, (pipe))((0x3) << (2 * ((pipe))))
1248#define DP_SSC_PWR_ON(pipe)((0x0) << (2 * ((pipe)))) _DP_SSC(0x0, (pipe))((0x0) << (2 * ((pipe))))
1249#define DP_SSC_CLK_GATE(pipe)((0x1) << (2 * ((pipe)))) _DP_SSC(0x1, (pipe))((0x1) << (2 * ((pipe))))
1250#define DP_SSC_RESET(pipe)((0x2) << (2 * ((pipe)))) _DP_SSC(0x2, (pipe))((0x2) << (2 * ((pipe))))
1251#define DP_SSC_PWR_GATE(pipe)((0x3) << (2 * ((pipe)))) _DP_SSC(0x3, (pipe))((0x3) << (2 * ((pipe))))
1252#define _DP_SSS(val, pipe)((val) << (2 * (pipe) + 16)) ((val) << (2 * (pipe) + 16))
1253#define DP_SSS_MASK(pipe)((0x3) << (2 * ((pipe)) + 16)) _DP_SSS(0x3, (pipe))((0x3) << (2 * ((pipe)) + 16))
1254#define DP_SSS_PWR_ON(pipe)((0x0) << (2 * ((pipe)) + 16)) _DP_SSS(0x0, (pipe))((0x0) << (2 * ((pipe)) + 16))
1255#define DP_SSS_CLK_GATE(pipe)((0x1) << (2 * ((pipe)) + 16)) _DP_SSS(0x1, (pipe))((0x1) << (2 * ((pipe)) + 16))
1256#define DP_SSS_RESET(pipe)((0x2) << (2 * ((pipe)) + 16)) _DP_SSS(0x2, (pipe))((0x2) << (2 * ((pipe)) + 16))
1257#define DP_SSS_PWR_GATE(pipe)((0x3) << (2 * ((pipe)) + 16)) _DP_SSS(0x3, (pipe))((0x3) << (2 * ((pipe)) + 16))
1258
1259#define PUNIT_REG_ISPSSPM00x39 0x39
1260#define PUNIT_REG_ISPSSPM10x3a 0x3a
1261
1262#define PUNIT_REG_PWRGT_CTRL0x60 0x60
1263#define PUNIT_REG_PWRGT_STATUS0x61 0x61
1264#define PUNIT_PWRGT_MASK(pw_idx)(3 << ((pw_idx) * 2)) (3 << ((pw_idx) * 2))
1265#define PUNIT_PWRGT_PWR_ON(pw_idx)(0 << ((pw_idx) * 2)) (0 << ((pw_idx) * 2))
1266#define PUNIT_PWRGT_CLK_GATE(pw_idx)(1 << ((pw_idx) * 2)) (1 << ((pw_idx) * 2))
1267#define PUNIT_PWRGT_RESET(pw_idx)(2 << ((pw_idx) * 2)) (2 << ((pw_idx) * 2))
1268#define PUNIT_PWRGT_PWR_GATE(pw_idx)(3 << ((pw_idx) * 2)) (3 << ((pw_idx) * 2))
1269
1270#define PUNIT_PWGT_IDX_RENDER0 0
1271#define PUNIT_PWGT_IDX_MEDIA1 1
1272#define PUNIT_PWGT_IDX_DISP2D3 3
1273#define PUNIT_PWGT_IDX_DPIO_CMN_BC5 5
1274#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_016 6
1275#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_237 7
1276#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_018 8
1277#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_239 9
1278#define PUNIT_PWGT_IDX_DPIO_RX010 10
1279#define PUNIT_PWGT_IDX_DPIO_RX111 11
1280#define PUNIT_PWGT_IDX_DPIO_CMN_D12 12
1281
1282#define PUNIT_REG_GPU_LFM0xd3 0xd3
1283#define PUNIT_REG_GPU_FREQ_REQ0xd4 0xd4
1284#define PUNIT_REG_GPU_FREQ_STS0xd8 0xd8
1285#define GPLLENABLE(1 << 4) (1 << 4)
1286#define GENFREQSTATUS(1 << 0) (1 << 0)
1287#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ0xdc 0xdc
1288#define PUNIT_REG_CZ_TIMESTAMP0xce 0xce
1289
1290#define PUNIT_FUSE_BUS20xf6 0xf6 /* bits 47:40 */
1291#define PUNIT_FUSE_BUS10xf5 0xf5 /* bits 55:48 */
1292
1293#define FB_GFX_FMAX_AT_VMAX_FUSE0x136 0x136
1294#define FB_GFX_FREQ_FUSE_MASK0xff 0xff
1295#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT24 24
1296#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT16 16
1297#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT8 8
1298
1299#define FB_GFX_FMIN_AT_VMIN_FUSE0x137 0x137
1300#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT8 8
1301
1302#define PUNIT_REG_DDR_SETUP20x139 0x139
1303#define FORCE_DDR_FREQ_REQ_ACK(1 << 8) (1 << 8)
1304#define FORCE_DDR_LOW_FREQ(1 << 1) (1 << 1)
1305#define FORCE_DDR_HIGH_FREQ(1 << 0) (1 << 0)
1306
1307#define PUNIT_GPU_STATUS_REG0xdb 0xdb
1308#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16 16
1309#define PUNIT_GPU_STATUS_MAX_FREQ_MASK0xff 0xff
1310#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT8 8
1311#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK0xff 0xff
1312
1313#define PUNIT_GPU_DUTYCYCLE_REG0xdf 0xdf
1314#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT8 8
1315#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK0xff 0xff
1316
1317#define IOSF_NC_FB_GFX_FREQ_FUSE0x1c 0x1c
1318#define FB_GFX_MAX_FREQ_FUSE_SHIFT3 3
1319#define FB_GFX_MAX_FREQ_FUSE_MASK0x000007f8 0x000007f8
1320#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT11 11
1321#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK0x0007f800 0x0007f800
1322#define IOSF_NC_FB_GFX_FMAX_FUSE_HI0x34 0x34
1323#define FB_FMAX_VMIN_FREQ_HI_MASK0x00000007 0x00000007
1324#define IOSF_NC_FB_GFX_FMAX_FUSE_LO0x30 0x30
1325#define FB_FMAX_VMIN_FREQ_LO_SHIFT27 27
1326#define FB_FMAX_VMIN_FREQ_LO_MASK0xf8000000 0xf8000000
1327
1328#define VLV_TURBO_SOC_OVERRIDE0x04 0x04
1329#define VLV_OVERRIDE_EN1 1
1330#define VLV_SOC_TDP_EN(1 << 1) (1 << 1)
1331#define VLV_BIAS_CPU_125_SOC_875(6 << 2) (6 << 2)
1332#define CHV_BIAS_CPU_50_SOC_50(3 << 2) (3 << 2)
1333
1334/* vlv2 north clock has */
1335#define CCK_FUSE_REG0x8 0x8
1336#define CCK_FUSE_HPLL_FREQ_MASK0x3 0x3
1337#define CCK_REG_DSI_PLL_FUSE0x44 0x44
1338#define CCK_REG_DSI_PLL_CONTROL0x48 0x48
1339#define DSI_PLL_VCO_EN(1 << 31) (1 << 31)
1340#define DSI_PLL_LDO_GATE(1 << 30) (1 << 30)
1341#define DSI_PLL_P1_POST_DIV_SHIFT17 17
1342#define DSI_PLL_P1_POST_DIV_MASK(0x1ff << 17) (0x1ff << 17)
1343#define DSI_PLL_P2_MUX_DSI0_DIV2(1 << 13) (1 << 13)
1344#define DSI_PLL_P3_MUX_DSI1_DIV2(1 << 12) (1 << 12)
1345#define DSI_PLL_MUX_MASK(3 << 9) (3 << 9)
1346#define DSI_PLL_MUX_DSI0_DSIPLL(0 << 10) (0 << 10)
1347#define DSI_PLL_MUX_DSI0_CCK(1 << 10) (1 << 10)
1348#define DSI_PLL_MUX_DSI1_DSIPLL(0 << 9) (0 << 9)
1349#define DSI_PLL_MUX_DSI1_CCK(1 << 9) (1 << 9)
1350#define DSI_PLL_CLK_GATE_MASK(0xf << 5) (0xf << 5)
1351#define DSI_PLL_CLK_GATE_DSI0_DSIPLL(1 << 8) (1 << 8)
1352#define DSI_PLL_CLK_GATE_DSI1_DSIPLL(1 << 7) (1 << 7)
1353#define DSI_PLL_CLK_GATE_DSI0_CCK(1 << 6) (1 << 6)
1354#define DSI_PLL_CLK_GATE_DSI1_CCK(1 << 5) (1 << 5)
1355#define DSI_PLL_LOCK(1 << 0) (1 << 0)
1356#define CCK_REG_DSI_PLL_DIVIDER0x4c 0x4c
1357#define DSI_PLL_LFSR(1 << 31) (1 << 31)
1358#define DSI_PLL_FRACTION_EN(1 << 30) (1 << 30)
1359#define DSI_PLL_FRAC_COUNTER_SHIFT27 27
1360#define DSI_PLL_FRAC_COUNTER_MASK(7 << 27) (7 << 27)
1361#define DSI_PLL_USYNC_CNT_SHIFT18 18
1362#define DSI_PLL_USYNC_CNT_MASK(0x1ff << 18) (0x1ff << 18)
1363#define DSI_PLL_N1_DIV_SHIFT16 16
1364#define DSI_PLL_N1_DIV_MASK(3 << 16) (3 << 16)
1365#define DSI_PLL_M1_DIV_SHIFT0 0
1366#define DSI_PLL_M1_DIV_MASK(0x1ff << 0) (0x1ff << 0)
1367#define CCK_CZ_CLOCK_CONTROL0x62 0x62
1368#define CCK_GPLL_CLOCK_CONTROL0x67 0x67
1369#define CCK_DISPLAY_CLOCK_CONTROL0x6b 0x6b
1370#define CCK_DISPLAY_REF_CLOCK_CONTROL0x6c 0x6c
1371#define CCK_TRUNK_FORCE_ON(1 << 17) (1 << 17)
1372#define CCK_TRUNK_FORCE_OFF(1 << 16) (1 << 16)
1373#define CCK_FREQUENCY_STATUS(0x1f << 8) (0x1f << 8)
1374#define CCK_FREQUENCY_STATUS_SHIFT8 8
1375#define CCK_FREQUENCY_VALUES(0x1f << 0) (0x1f << 0)
1376
1377/* DPIO registers */
1378#define DPIO_DEVFN0 0
1379
1380#define DPIO_CTL((const i915_reg_t){ .reg = (0x180000 + 0x2110) }) _MMIO(VLV_DISPLAY_BASE + 0x2110)((const i915_reg_t){ .reg = (0x180000 + 0x2110) })
1381#define DPIO_MODSEL1(1 << 3) (1 << 3) /* if ref clk b == 27 */
1382#define DPIO_MODSEL0(1 << 2) (1 << 2) /* if ref clk a == 27 */
1383#define DPIO_SFR_BYPASS(1 << 1) (1 << 1)
1384#define DPIO_CMNRST(1 << 0) (1 << 0)
1385
1386#define DPIO_PHY(pipe)((pipe) >> 1) ((pipe) >> 1)
1387
1388/*
1389 * Per pipe/PLL DPIO regs
1390 */
1391#define _VLV_PLL_DW3_CH00x800c 0x800c
1392#define DPIO_POST_DIV_SHIFT(28) (28) /* 3 bits */
1393#define DPIO_POST_DIV_DAC0 0
1394#define DPIO_POST_DIV_HDMIDP1 1 /* DAC 225-400M rate */
1395#define DPIO_POST_DIV_LVDS12 2
1396#define DPIO_POST_DIV_LVDS23 3
1397#define DPIO_K_SHIFT(24) (24) /* 4 bits */
1398#define DPIO_P1_SHIFT(21) (21) /* 3 bits */
1399#define DPIO_P2_SHIFT(16) (16) /* 5 bits */
1400#define DPIO_N_SHIFT(12) (12) /* 4 bits */
1401#define DPIO_ENABLE_CALIBRATION(1 << 11) (1 << 11)
1402#define DPIO_M1DIV_SHIFT(8) (8) /* 3 bits */
1403#define DPIO_M2DIV_MASK0xff 0xff
1404#define _VLV_PLL_DW3_CH10x802c 0x802c
1405#define VLV_PLL_DW3(ch)((0x800c) + (ch) * ((0x802c) - (0x800c))) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)((0x800c) + (ch) * ((0x802c) - (0x800c)))
1406
1407#define _VLV_PLL_DW5_CH00x8014 0x8014
1408#define DPIO_REFSEL_OVERRIDE27 27
1409#define DPIO_PLL_MODESEL_SHIFT24 24 /* 3 bits */
1410#define DPIO_BIAS_CURRENT_CTL_SHIFT21 21 /* 3 bits, always 0x7 */
1411#define DPIO_PLL_REFCLK_SEL_SHIFT16 16 /* 2 bits */
1412#define DPIO_PLL_REFCLK_SEL_MASK3 3
1413#define DPIO_DRIVER_CTL_SHIFT12 12 /* always set to 0x8 */
1414#define DPIO_CLK_BIAS_CTL_SHIFT8 8 /* always set to 0x5 */
1415#define _VLV_PLL_DW5_CH10x8034 0x8034
1416#define VLV_PLL_DW5(ch)((0x8014) + (ch) * ((0x8034) - (0x8014))) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)((0x8014) + (ch) * ((0x8034) - (0x8014)))
1417
1418#define _VLV_PLL_DW7_CH00x801c 0x801c
1419#define _VLV_PLL_DW7_CH10x803c 0x803c
1420#define VLV_PLL_DW7(ch)((0x801c) + (ch) * ((0x803c) - (0x801c))) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)((0x801c) + (ch) * ((0x803c) - (0x801c)))
1421
1422#define _VLV_PLL_DW8_CH00x8040 0x8040
1423#define _VLV_PLL_DW8_CH10x8060 0x8060
1424#define VLV_PLL_DW8(ch)((0x8040) + (ch) * ((0x8060) - (0x8040))) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)((0x8040) + (ch) * ((0x8060) - (0x8040)))
1425
1426#define VLV_PLL_DW9_BCAST0xc044 0xc044
1427#define _VLV_PLL_DW9_CH00x8044 0x8044
1428#define _VLV_PLL_DW9_CH10x8064 0x8064
1429#define VLV_PLL_DW9(ch)((0x8044) + (ch) * ((0x8064) - (0x8044))) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)((0x8044) + (ch) * ((0x8064) - (0x8044)))
1430
1431#define _VLV_PLL_DW10_CH00x8048 0x8048
1432#define _VLV_PLL_DW10_CH10x8068 0x8068
1433#define VLV_PLL_DW10(ch)((0x8048) + (ch) * ((0x8068) - (0x8048))) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)((0x8048) + (ch) * ((0x8068) - (0x8048)))
1434
1435#define _VLV_PLL_DW11_CH00x804c 0x804c
1436#define _VLV_PLL_DW11_CH10x806c 0x806c
1437#define VLV_PLL_DW11(ch)((0x804c) + (ch) * ((0x806c) - (0x804c))) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)((0x804c) + (ch) * ((0x806c) - (0x804c)))
1438
1439/* Spec for ref block start counts at DW10 */
1440#define VLV_REF_DW130x80ac 0x80ac
1441
1442#define VLV_CMN_DW00x8100 0x8100
1443
1444/*
1445 * Per DDI channel DPIO regs
1446 */
1447
1448#define _VLV_PCS_DW0_CH00x8200 0x8200
1449#define _VLV_PCS_DW0_CH10x8400 0x8400
1450#define DPIO_PCS_TX_LANE2_RESET(1 << 16) (1 << 16)
1451#define DPIO_PCS_TX_LANE1_RESET(1 << 7) (1 << 7)
1452#define DPIO_LEFT_TXFIFO_RST_MASTER2(1 << 4) (1 << 4)
1453#define DPIO_RIGHT_TXFIFO_RST_MASTER2(1 << 3) (1 << 3)
1454#define VLV_PCS_DW0(ch)((0x8200) + (ch) * ((0x8400) - (0x8200))) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)((0x8200) + (ch) * ((0x8400) - (0x8200)))
1455
1456#define _VLV_PCS01_DW0_CH00x200 0x200
1457#define _VLV_PCS23_DW0_CH00x400 0x400
1458#define _VLV_PCS01_DW0_CH10x2600 0x2600
1459#define _VLV_PCS23_DW0_CH10x2800 0x2800
1460#define VLV_PCS01_DW0(ch)((0x200) + (ch) * ((0x2600) - (0x200))) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)((0x200) + (ch) * ((0x2600) - (0x200)))
1461#define VLV_PCS23_DW0(ch)((0x400) + (ch) * ((0x2800) - (0x400))) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)((0x400) + (ch) * ((0x2800) - (0x400)))
1462
1463#define _VLV_PCS_DW1_CH00x8204 0x8204
1464#define _VLV_PCS_DW1_CH10x8404 0x8404
1465#define CHV_PCS_REQ_SOFTRESET_EN(1 << 23) (1 << 23)
1466#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN(1 << 22) (1 << 22)
1467#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN(1 << 21) (1 << 21)
1468#define DPIO_PCS_CLK_DATAWIDTH_SHIFT(6) (6)
1469#define DPIO_PCS_CLK_SOFT_RESET(1 << 5) (1 << 5)
1470#define VLV_PCS_DW1(ch)((0x8204) + (ch) * ((0x8404) - (0x8204))) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)((0x8204) + (ch) * ((0x8404) - (0x8204)))
1471
1472#define _VLV_PCS01_DW1_CH00x204 0x204
1473#define _VLV_PCS23_DW1_CH00x404 0x404
1474#define _VLV_PCS01_DW1_CH10x2604 0x2604
1475#define _VLV_PCS23_DW1_CH10x2804 0x2804
1476#define VLV_PCS01_DW1(ch)((0x204) + (ch) * ((0x2604) - (0x204))) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)((0x204) + (ch) * ((0x2604) - (0x204)))
1477#define VLV_PCS23_DW1(ch)((0x404) + (ch) * ((0x2804) - (0x404))) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)((0x404) + (ch) * ((0x2804) - (0x404)))
1478
1479#define _VLV_PCS_DW8_CH00x8220 0x8220
1480#define _VLV_PCS_DW8_CH10x8420 0x8420
1481#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE(1 << 20) (1 << 20)
1482#define CHV_PCS_USEDCLKCHANNEL(1 << 21) (1 << 21)
1483#define VLV_PCS_DW8(ch)((0x8220) + (ch) * ((0x8420) - (0x8220))) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)((0x8220) + (ch) * ((0x8420) - (0x8220)))
1484
1485#define _VLV_PCS01_DW8_CH00x0220 0x0220
1486#define _VLV_PCS23_DW8_CH00x0420 0x0420
1487#define _VLV_PCS01_DW8_CH10x2620 0x2620
1488#define _VLV_PCS23_DW8_CH10x2820 0x2820
1489#define VLV_PCS01_DW8(port)((0x0220) + (port) * ((0x2620) - (0x0220))) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)((0x0220) + (port) * ((0x2620) - (0x0220)))
1490#define VLV_PCS23_DW8(port)((0x0420) + (port) * ((0x2820) - (0x0420))) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)((0x0420) + (port) * ((0x2820) - (0x0420)))
1491
1492#define _VLV_PCS_DW9_CH00x8224 0x8224
1493#define _VLV_PCS_DW9_CH10x8424 0x8424
1494#define DPIO_PCS_TX2MARGIN_MASK(0x7 << 13) (0x7 << 13)
1495#define DPIO_PCS_TX2MARGIN_000(0 << 13) (0 << 13)
1496#define DPIO_PCS_TX2MARGIN_101(1 << 13) (1 << 13)
1497#define DPIO_PCS_TX1MARGIN_MASK(0x7 << 10) (0x7 << 10)
1498#define DPIO_PCS_TX1MARGIN_000(0 << 10) (0 << 10)
1499#define DPIO_PCS_TX1MARGIN_101(1 << 10) (1 << 10)
1500#define VLV_PCS_DW9(ch)((0x8224) + (ch) * ((0x8424) - (0x8224))) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)((0x8224) + (ch) * ((0x8424) - (0x8224)))
1501
1502#define _VLV_PCS01_DW9_CH00x224 0x224
1503#define _VLV_PCS23_DW9_CH00x424 0x424
1504#define _VLV_PCS01_DW9_CH10x2624 0x2624
1505#define _VLV_PCS23_DW9_CH10x2824 0x2824
1506#define VLV_PCS01_DW9(ch)((0x224) + (ch) * ((0x2624) - (0x224))) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)((0x224) + (ch) * ((0x2624) - (0x224)))
1507#define VLV_PCS23_DW9(ch)((0x424) + (ch) * ((0x2824) - (0x424))) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)((0x424) + (ch) * ((0x2824) - (0x424)))
1508
1509#define _CHV_PCS_DW10_CH00x8228 0x8228
1510#define _CHV_PCS_DW10_CH10x8428 0x8428
1511#define DPIO_PCS_SWING_CALC_TX0_TX2(1 << 30) (1 << 30)
1512#define DPIO_PCS_SWING_CALC_TX1_TX3(1 << 31) (1 << 31)
1513#define DPIO_PCS_TX2DEEMP_MASK(0xf << 24) (0xf << 24)
1514#define DPIO_PCS_TX2DEEMP_9P5(0 << 24) (0 << 24)
1515#define DPIO_PCS_TX2DEEMP_6P0(2 << 24) (2 << 24)
1516#define DPIO_PCS_TX1DEEMP_MASK(0xf << 16) (0xf << 16)
1517#define DPIO_PCS_TX1DEEMP_9P5(0 << 16) (0 << 16)
1518#define DPIO_PCS_TX1DEEMP_6P0(2 << 16) (2 << 16)
1519#define CHV_PCS_DW10(ch)((0x8228) + (ch) * ((0x8428) - (0x8228))) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)((0x8228) + (ch) * ((0x8428) - (0x8228)))
1520
1521#define _VLV_PCS01_DW10_CH00x0228 0x0228
1522#define _VLV_PCS23_DW10_CH00x0428 0x0428
1523#define _VLV_PCS01_DW10_CH10x2628 0x2628
1524#define _VLV_PCS23_DW10_CH10x2828 0x2828
1525#define VLV_PCS01_DW10(port)((0x0228) + (port) * ((0x2628) - (0x0228))) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)((0x0228) + (port) * ((0x2628) - (0x0228)))
1526#define VLV_PCS23_DW10(port)((0x0428) + (port) * ((0x2828) - (0x0428))) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)((0x0428) + (port) * ((0x2828) - (0x0428)))
1527
1528#define _VLV_PCS_DW11_CH00x822c 0x822c
1529#define _VLV_PCS_DW11_CH10x842c 0x842c
1530#define DPIO_TX2_STAGGER_MASK(x)((x) << 24) ((x) << 24)
1531#define DPIO_LANEDESKEW_STRAP_OVRD(1 << 3) (1 << 3)
1532#define DPIO_LEFT_TXFIFO_RST_MASTER(1 << 1) (1 << 1)
1533#define DPIO_RIGHT_TXFIFO_RST_MASTER(1 << 0) (1 << 0)
1534#define VLV_PCS_DW11(ch)((0x822c) + (ch) * ((0x842c) - (0x822c))) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)((0x822c) + (ch) * ((0x842c) - (0x822c)))
1535
1536#define _VLV_PCS01_DW11_CH00x022c 0x022c
1537#define _VLV_PCS23_DW11_CH00x042c 0x042c
1538#define _VLV_PCS01_DW11_CH10x262c 0x262c
1539#define _VLV_PCS23_DW11_CH10x282c 0x282c
1540#define VLV_PCS01_DW11(ch)((0x022c) + (ch) * ((0x262c) - (0x022c))) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)((0x022c) + (ch) * ((0x262c) - (0x022c)))
1541#define VLV_PCS23_DW11(ch)((0x042c) + (ch) * ((0x282c) - (0x042c))) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)((0x042c) + (ch) * ((0x282c) - (0x042c)))
1542
1543#define _VLV_PCS01_DW12_CH00x0230 0x0230
1544#define _VLV_PCS23_DW12_CH00x0430 0x0430
1545#define _VLV_PCS01_DW12_CH10x2630 0x2630
1546#define _VLV_PCS23_DW12_CH10x2830 0x2830
1547#define VLV_PCS01_DW12(ch)((0x0230) + (ch) * ((0x2630) - (0x0230))) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)((0x0230) + (ch) * ((0x2630) - (0x0230)))
1548#define VLV_PCS23_DW12(ch)((0x0430) + (ch) * ((0x2830) - (0x0430))) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)((0x0430) + (ch) * ((0x2830) - (0x0430)))
1549
1550#define _VLV_PCS_DW12_CH00x8230 0x8230
1551#define _VLV_PCS_DW12_CH10x8430 0x8430
1552#define DPIO_TX2_STAGGER_MULT(x)((x) << 20) ((x) << 20)
1553#define DPIO_TX1_STAGGER_MULT(x)((x) << 16) ((x) << 16)
1554#define DPIO_TX1_STAGGER_MASK(x)((x) << 8) ((x) << 8)
1555#define DPIO_LANESTAGGER_STRAP_OVRD(1 << 6) (1 << 6)
1556#define DPIO_LANESTAGGER_STRAP(x)((x) << 0) ((x) << 0)
1557#define VLV_PCS_DW12(ch)((0x8230) + (ch) * ((0x8430) - (0x8230))) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)((0x8230) + (ch) * ((0x8430) - (0x8230)))
1558
1559#define _VLV_PCS_DW14_CH00x8238 0x8238
1560#define _VLV_PCS_DW14_CH10x8438 0x8438
1561#define VLV_PCS_DW14(ch)((0x8238) + (ch) * ((0x8438) - (0x8238))) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)((0x8238) + (ch) * ((0x8438) - (0x8238)))
1562
1563#define _VLV_PCS_DW23_CH00x825c 0x825c
1564#define _VLV_PCS_DW23_CH10x845c 0x845c
1565#define VLV_PCS_DW23(ch)((0x825c) + (ch) * ((0x845c) - (0x825c))) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)((0x825c) + (ch) * ((0x845c) - (0x825c)))
1566
1567#define _VLV_TX_DW2_CH00x8288 0x8288
1568#define _VLV_TX_DW2_CH10x8488 0x8488
1569#define DPIO_SWING_MARGIN000_SHIFT16 16
1570#define DPIO_SWING_MARGIN000_MASK(0xff << 16) (0xff << DPIO_SWING_MARGIN000_SHIFT16)
1571#define DPIO_UNIQ_TRANS_SCALE_SHIFT8 8
1572#define VLV_TX_DW2(ch)((0x8288) + (ch) * ((0x8488) - (0x8288))) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)((0x8288) + (ch) * ((0x8488) - (0x8288)))
1573
1574#define _VLV_TX_DW3_CH00x828c 0x828c
1575#define _VLV_TX_DW3_CH10x848c 0x848c
1576/* The following bit for CHV phy */
1577#define DPIO_TX_UNIQ_TRANS_SCALE_EN(1 << 27) (1 << 27)
1578#define DPIO_SWING_MARGIN101_SHIFT16 16
1579#define DPIO_SWING_MARGIN101_MASK(0xff << 16) (0xff << DPIO_SWING_MARGIN101_SHIFT16)
1580#define VLV_TX_DW3(ch)((0x828c) + (ch) * ((0x848c) - (0x828c))) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)((0x828c) + (ch) * ((0x848c) - (0x828c)))
1581
1582#define _VLV_TX_DW4_CH00x8290 0x8290
1583#define _VLV_TX_DW4_CH10x8490 0x8490
1584#define DPIO_SWING_DEEMPH9P5_SHIFT24 24
1585#define DPIO_SWING_DEEMPH9P5_MASK(0xff << 24) (0xff << DPIO_SWING_DEEMPH9P5_SHIFT24)
1586#define DPIO_SWING_DEEMPH6P0_SHIFT16 16
1587#define DPIO_SWING_DEEMPH6P0_MASK(0xff << 16) (0xff << DPIO_SWING_DEEMPH6P0_SHIFT16)
1588#define VLV_TX_DW4(ch)((0x8290) + (ch) * ((0x8490) - (0x8290))) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)((0x8290) + (ch) * ((0x8490) - (0x8290)))
1589
1590#define _VLV_TX3_DW4_CH00x690 0x690
1591#define _VLV_TX3_DW4_CH10x2a90 0x2a90
1592#define VLV_TX3_DW4(ch)((0x690) + (ch) * ((0x2a90) - (0x690))) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)((0x690) + (ch) * ((0x2a90) - (0x690)))
1593
1594#define _VLV_TX_DW5_CH00x8294 0x8294
1595#define _VLV_TX_DW5_CH10x8494 0x8494
1596#define DPIO_TX_OCALINIT_EN(1 << 31) (1 << 31)
1597#define VLV_TX_DW5(ch)((0x8294) + (ch) * ((0x8494) - (0x8294))) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)((0x8294) + (ch) * ((0x8494) - (0x8294)))
1598
1599#define _VLV_TX_DW11_CH00x82ac 0x82ac
1600#define _VLV_TX_DW11_CH10x84ac 0x84ac
1601#define VLV_TX_DW11(ch)((0x82ac) + (ch) * ((0x84ac) - (0x82ac))) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)((0x82ac) + (ch) * ((0x84ac) - (0x82ac)))
1602
1603#define _VLV_TX_DW14_CH00x82b8 0x82b8
1604#define _VLV_TX_DW14_CH10x84b8 0x84b8
1605#define VLV_TX_DW14(ch)((0x82b8) + (ch) * ((0x84b8) - (0x82b8))) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)((0x82b8) + (ch) * ((0x84b8) - (0x82b8)))
1606
1607/* CHV dpPhy registers */
1608#define _CHV_PLL_DW0_CH00x8000 0x8000
1609#define _CHV_PLL_DW0_CH10x8180 0x8180
1610#define CHV_PLL_DW0(ch)((0x8000) + (ch) * ((0x8180) - (0x8000))) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)((0x8000) + (ch) * ((0x8180) - (0x8000)))
1611
1612#define _CHV_PLL_DW1_CH00x8004 0x8004
1613#define _CHV_PLL_DW1_CH10x8184 0x8184
1614#define DPIO_CHV_N_DIV_SHIFT8 8
1615#define DPIO_CHV_M1_DIV_BY_2(0 << 0) (0 << 0)
1616#define CHV_PLL_DW1(ch)((0x8004) + (ch) * ((0x8184) - (0x8004))) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)((0x8004) + (ch) * ((0x8184) - (0x8004)))
1617
1618#define _CHV_PLL_DW2_CH00x8008 0x8008
1619#define _CHV_PLL_DW2_CH10x8188 0x8188
1620#define CHV_PLL_DW2(ch)((0x8008) + (ch) * ((0x8188) - (0x8008))) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)((0x8008) + (ch) * ((0x8188) - (0x8008)))
1621
1622#define _CHV_PLL_DW3_CH00x800c 0x800c
1623#define _CHV_PLL_DW3_CH10x818c 0x818c
1624#define DPIO_CHV_FRAC_DIV_EN(1 << 16) (1 << 16)
1625#define DPIO_CHV_FIRST_MOD(0 << 8) (0 << 8)
1626#define DPIO_CHV_SECOND_MOD(1 << 8) (1 << 8)
1627#define DPIO_CHV_FEEDFWD_GAIN_SHIFT0 0
1628#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0) (0xF << 0)
1629#define CHV_PLL_DW3(ch)((0x800c) + (ch) * ((0x818c) - (0x800c))) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)((0x800c) + (ch) * ((0x818c) - (0x800c)))
1630
1631#define _CHV_PLL_DW6_CH00x8018 0x8018
1632#define _CHV_PLL_DW6_CH10x8198 0x8198
1633#define DPIO_CHV_GAIN_CTRL_SHIFT16 16
1634#define DPIO_CHV_INT_COEFF_SHIFT8 8
1635#define DPIO_CHV_PROP_COEFF_SHIFT0 0
1636#define CHV_PLL_DW6(ch)((0x8018) + (ch) * ((0x8198) - (0x8018))) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)((0x8018) + (ch) * ((0x8198) - (0x8018)))
1637
1638#define _CHV_PLL_DW8_CH00x8020 0x8020
1639#define _CHV_PLL_DW8_CH10x81A0 0x81A0
1640#define DPIO_CHV_TDC_TARGET_CNT_SHIFT0 0
1641#define DPIO_CHV_TDC_TARGET_CNT_MASK(0x3FF << 0) (0x3FF << 0)
1642#define CHV_PLL_DW8(ch)((0x8020) + (ch) * ((0x81A0) - (0x8020))) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)((0x8020) + (ch) * ((0x81A0) - (0x8020)))
1643
1644#define _CHV_PLL_DW9_CH00x8024 0x8024
1645#define _CHV_PLL_DW9_CH10x81A4 0x81A4
1646#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT1 1 /* 3 bits */
1647#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK(7 << 1) (7 << 1)
1648#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 1 /* 1: coarse & 0 : fine */
1649#define CHV_PLL_DW9(ch)((0x8024) + (ch) * ((0x81A4) - (0x8024))) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)((0x8024) + (ch) * ((0x81A4) - (0x8024)))
1650
1651#define _CHV_CMN_DW0_CH00x8100 0x8100
1652#define DPIO_ALLDL_POWERDOWN_SHIFT_CH019 19
1653#define DPIO_ANYDL_POWERDOWN_SHIFT_CH018 18
1654#define DPIO_ALLDL_POWERDOWN(1 << 1) (1 << 1)
1655#define DPIO_ANYDL_POWERDOWN(1 << 0) (1 << 0)
1656
1657#define _CHV_CMN_DW5_CH00x8114 0x8114
1658#define CHV_BUFRIGHTENA1_DISABLE(0 << 20) (0 << 20)
1659#define CHV_BUFRIGHTENA1_NORMAL(1 << 20) (1 << 20)
1660#define CHV_BUFRIGHTENA1_FORCE(3 << 20) (3 << 20)
1661#define CHV_BUFRIGHTENA1_MASK(3 << 20) (3 << 20)
1662#define CHV_BUFLEFTENA1_DISABLE(0 << 22) (0 << 22)
1663#define CHV_BUFLEFTENA1_NORMAL(1 << 22) (1 << 22)
1664#define CHV_BUFLEFTENA1_FORCE(3 << 22) (3 << 22)
1665#define CHV_BUFLEFTENA1_MASK(3 << 22) (3 << 22)
1666
1667#define _CHV_CMN_DW13_CH00x8134 0x8134
1668#define _CHV_CMN_DW0_CH10x8080 0x8080
1669#define DPIO_CHV_S1_DIV_SHIFT21 21
1670#define DPIO_CHV_P1_DIV_SHIFT13 13 /* 3 bits */
1671#define DPIO_CHV_P2_DIV_SHIFT8 8 /* 5 bits */
1672#define DPIO_CHV_K_DIV_SHIFT4 4
1673#define DPIO_PLL_FREQLOCK(1 << 1) (1 << 1)
1674#define DPIO_PLL_LOCK(1 << 0) (1 << 0)
1675#define CHV_CMN_DW13(ch)((0x8134) + (ch) * ((0x8080) - (0x8134))) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)((0x8134) + (ch) * ((0x8080) - (0x8134)))
1676
1677#define _CHV_CMN_DW14_CH00x8138 0x8138
1678#define _CHV_CMN_DW1_CH10x8084 0x8084
1679#define DPIO_AFC_RECAL(1 << 14) (1 << 14)
1680#define DPIO_DCLKP_EN(1 << 13) (1 << 13)
1681#define CHV_BUFLEFTENA2_DISABLE(0 << 17) (0 << 17) /* CL2 DW1 only */
1682#define CHV_BUFLEFTENA2_NORMAL(1 << 17) (1 << 17) /* CL2 DW1 only */
1683#define CHV_BUFLEFTENA2_FORCE(3 << 17) (3 << 17) /* CL2 DW1 only */
1684#define CHV_BUFLEFTENA2_MASK(3 << 17) (3 << 17) /* CL2 DW1 only */
1685#define CHV_BUFRIGHTENA2_DISABLE(0 << 19) (0 << 19) /* CL2 DW1 only */
1686#define CHV_BUFRIGHTENA2_NORMAL(1 << 19) (1 << 19) /* CL2 DW1 only */
1687#define CHV_BUFRIGHTENA2_FORCE(3 << 19) (3 << 19) /* CL2 DW1 only */
1688#define CHV_BUFRIGHTENA2_MASK(3 << 19) (3 << 19) /* CL2 DW1 only */
1689#define CHV_CMN_DW14(ch)((0x8138) + (ch) * ((0x8084) - (0x8138))) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)((0x8138) + (ch) * ((0x8084) - (0x8138)))
1690
1691#define _CHV_CMN_DW19_CH00x814c 0x814c
1692#define _CHV_CMN_DW6_CH10x8098 0x8098
1693#define DPIO_ALLDL_POWERDOWN_SHIFT_CH130 30 /* CL2 DW6 only */
1694#define DPIO_ANYDL_POWERDOWN_SHIFT_CH129 29 /* CL2 DW6 only */
1695#define DPIO_DYNPWRDOWNEN_CH1(1 << 28) (1 << 28) /* CL2 DW6 only */
1696#define CHV_CMN_USEDCLKCHANNEL(1 << 13) (1 << 13)
1697
1698#define CHV_CMN_DW19(ch)((0x814c) + (ch) * ((0x8098) - (0x814c))) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)((0x814c) + (ch) * ((0x8098) - (0x814c)))
1699
1700#define CHV_CMN_DW280x8170 0x8170
1701#define DPIO_CL1POWERDOWNEN(1 << 23) (1 << 23)
1702#define DPIO_DYNPWRDOWNEN_CH0(1 << 22) (1 << 22)
1703#define DPIO_SUS_CLK_CONFIG_ON(0 << 0) (0 << 0)
1704#define DPIO_SUS_CLK_CONFIG_CLKREQ(1 << 0) (1 << 0)
1705#define DPIO_SUS_CLK_CONFIG_GATE(2 << 0) (2 << 0)
1706#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ(3 << 0) (3 << 0)
1707
1708#define CHV_CMN_DW300x8178 0x8178
1709#define DPIO_CL2_LDOFUSE_PWRENB(1 << 6) (1 << 6)
1710#define DPIO_LRC_BYPASS(1 << 3) (1 << 3)
1711
1712#define _TXLANE(ch, lane, offset)((ch ? 0x2400 : 0) + (lane) * 0x200 + (offset)) ((ch ? 0x2400 : 0) + \
1713 (lane) * 0x200 + (offset))
1714
1715#define CHV_TX_DW0(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x80)) _TXLANE(ch, lane, 0x80)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x80))
1716#define CHV_TX_DW1(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x84)) _TXLANE(ch, lane, 0x84)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x84))
1717#define CHV_TX_DW2(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x88)) _TXLANE(ch, lane, 0x88)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x88))
1718#define CHV_TX_DW3(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x8c)) _TXLANE(ch, lane, 0x8c)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x8c))
1719#define CHV_TX_DW4(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x90)) _TXLANE(ch, lane, 0x90)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x90))
1720#define CHV_TX_DW5(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x94)) _TXLANE(ch, lane, 0x94)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x94))
1721#define CHV_TX_DW6(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x98)) _TXLANE(ch, lane, 0x98)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x98))
1722#define CHV_TX_DW7(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x9c)) _TXLANE(ch, lane, 0x9c)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0x9c))
1723#define CHV_TX_DW8(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa0)) _TXLANE(ch, lane, 0xa0)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa0))
1724#define CHV_TX_DW9(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa4)) _TXLANE(ch, lane, 0xa4)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa4))
1725#define CHV_TX_DW10(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa8)) _TXLANE(ch, lane, 0xa8)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xa8))
1726#define CHV_TX_DW11(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xac)) _TXLANE(ch, lane, 0xac)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xac))
1727#define DPIO_FRC_LATENCY_SHFIT8 8
1728#define CHV_TX_DW14(ch, lane)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xb8)) _TXLANE(ch, lane, 0xb8)((ch ? 0x2400 : 0) + (lane) * 0x200 + (0xb8))
1729#define DPIO_UPAR_SHIFT30 30
1730
1731/* BXT PHY registers */
1732#define _BXT_PHY0_BASE0x6C000 0x6C000
1733#define _BXT_PHY1_BASE0x162000 0x162000
1734#define _BXT_PHY2_BASE0x163000 0x163000
1735#define BXT_PHY_BASE(phy)(((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) _PHY3((phy), _BXT_PHY0_BASE, \(((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)])
1736 _BXT_PHY1_BASE, \(((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)])
1737 _BXT_PHY2_BASE)(((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)])
1738
1739#define _BXT_PHY(phy, reg)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) - 0x6C000 + (reg)) }) \
1740 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) - 0x6C000 + (reg)) })
1741
1742#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + (
((reg_ch0) - 0x6C000) + ((ch)) * (((reg_ch1) - 0x6C000) - ((reg_ch0
) - 0x6C000)))) \
1743 (BXT_PHY_BASE(phy)(((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \(((reg_ch0) - 0x6C000) + ((ch)) * (((reg_ch1) - 0x6C000) - ((
reg_ch0) - 0x6C000)))
1744 (reg_ch1) - _BXT_PHY0_BASE)(((reg_ch0) - 0x6C000) + ((ch)) * (((reg_ch1) - 0x6C000) - ((
reg_ch0) - 0x6C000))))
1745#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((reg_ch0) - 0x6C000) + ((ch)) * (((
reg_ch1) - 0x6C000) - ((reg_ch0) - 0x6C000))))) }) \
1746 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((reg_ch0) - 0x6C000) + ((ch)) * (((
reg_ch1) - 0x6C000) - ((reg_ch0) - 0x6C000))))) })
1747
1748#define BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }) _MMIO(0x138090)((const i915_reg_t){ .reg = (0x138090) })
1749#define MIPIO_RST_CTRL(1 << 2) (1 << 2)
1750
1751#define _BXT_PHY_CTL_DDI_A0x64C00 0x64C00
1752#define _BXT_PHY_CTL_DDI_B0x64C10 0x64C10
1753#define _BXT_PHY_CTL_DDI_C0x64C20 0x64C20
1754#define BXT_PHY_CMNLANE_POWERDOWN_ACK(1 << 10) (1 << 10)
1755#define BXT_PHY_LANE_POWERDOWN_ACK(1 << 9) (1 << 9)
1756#define BXT_PHY_LANE_ENABLED(1 << 8) (1 << 8)
1757#define BXT_PHY_CTL(port)((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C10)
- (0x64C00)))) }) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C10)
- (0x64C00)))) })
1758 _BXT_PHY_CTL_DDI_B)((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C10)
- (0x64C00)))) })
1759
1760#define _PHY_CTL_FAMILY_EDP0x64C80 0x64C80
1761#define _PHY_CTL_FAMILY_DDI0x64C90 0x64C90
1762#define _PHY_CTL_FAMILY_DDI_C0x64CA0 0x64CA0
1763#define COMMON_RESET_DIS(1 << 31) (1 << 31)
1764#define BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) }) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
1765 _PHY_CTL_FAMILY_EDP, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
1766 _PHY_CTL_FAMILY_DDI_C)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
1767
1768/* BXT PHY PLL registers */
1769#define _PORT_PLL_A0x46074 0x46074
1770#define _PORT_PLL_B0x46078 0x46078
1771#define _PORT_PLL_C0x4607c 0x4607c
1772#define PORT_PLL_ENABLE(1 << 31) (1 << 31)
1773#define PORT_PLL_LOCK(1 << 30) (1 << 30)
1774#define PORT_PLL_REF_SEL(1 << 27) (1 << 27)
1775#define PORT_PLL_POWER_ENABLE(1 << 26) (1 << 26)
1776#define PORT_PLL_POWER_STATE(1 << 25) (1 << 25)
1777#define BXT_PORT_PLL_ENABLE(port)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
- (0x46074)))) }) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)((const i915_reg_t){ .reg = (((0x46074) + (port) * ((0x46078)
- (0x46074)))) })
1778
1779#define _PORT_PLL_EBB_0_A0x162034 0x162034
1780#define _PORT_PLL_EBB_0_B0x6C034 0x6C034
1781#define _PORT_PLL_EBB_0_C0x6C340 0x6C340
1782#define PORT_PLL_P1_SHIFT13 13
1783#define PORT_PLL_P1_MASK(0x07 << 13) (0x07 << PORT_PLL_P1_SHIFT13)
1784#define PORT_PLL_P1(x)((x) << 13) ((x) << PORT_PLL_P1_SHIFT13)
1785#define PORT_PLL_P2_SHIFT8 8
1786#define PORT_PLL_P2_MASK(0x1f << 8) (0x1f << PORT_PLL_P2_SHIFT8)
1787#define PORT_PLL_P2(x)((x) << 8) ((x) << PORT_PLL_P2_SHIFT8)
1788#define BXT_PORT_PLL_EBB_0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) })
1789 _PORT_PLL_EBB_0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) })
1790 _PORT_PLL_EBB_0_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C034) - 0x6C000) + ((ch)) * (((
0x6C340) - 0x6C000) - ((0x6C034) - 0x6C000))))) })
1791
1792#define _PORT_PLL_EBB_4_A0x162038 0x162038
1793#define _PORT_PLL_EBB_4_B0x6C038 0x6C038
1794#define _PORT_PLL_EBB_4_C0x6C344 0x6C344
1795#define PORT_PLL_10BIT_CLK_ENABLE(1 << 13) (1 << 13)
1796#define PORT_PLL_RECALIBRATE(1 << 14) (1 << 14)
1797#define BXT_PORT_PLL_EBB_4(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) })
1798 _PORT_PLL_EBB_4_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) })
1799 _PORT_PLL_EBB_4_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C038) - 0x6C000) + ((ch)) * (((
0x6C344) - 0x6C000) - ((0x6C038) - 0x6C000))))) })
1800
1801#define _PORT_PLL_0_A0x162100 0x162100
1802#define _PORT_PLL_0_B0x6C100 0x6C100
1803#define _PORT_PLL_0_C0x6C380 0x6C380
1804/* PORT_PLL_0_A */
1805#define PORT_PLL_M2_MASK0xFF 0xFF
1806/* PORT_PLL_1_A */
1807#define PORT_PLL_N_SHIFT8 8
1808#define PORT_PLL_N_MASK(0x0F << 8) (0x0F << PORT_PLL_N_SHIFT8)
1809#define PORT_PLL_N(x)((x) << 8) ((x) << PORT_PLL_N_SHIFT8)
1810/* PORT_PLL_2_A */
1811#define PORT_PLL_M2_FRAC_MASK0x3FFFFF 0x3FFFFF
1812/* PORT_PLL_3_A */
1813#define PORT_PLL_M2_FRAC_ENABLE(1 << 16) (1 << 16)
1814/* PORT_PLL_6_A */
1815#define PORT_PLL_PROP_COEFF_MASK0xF 0xF
1816#define PORT_PLL_INT_COEFF_MASK(0x1F << 8) (0x1F << 8)
1817#define PORT_PLL_INT_COEFF(x)((x) << 8) ((x) << 8)
1818#define PORT_PLL_GAIN_CTL_MASK(0x07 << 16) (0x07 << 16)
1819#define PORT_PLL_GAIN_CTL(x)((x) << 16) ((x) << 16)
1820/* PORT_PLL_8_A */
1821#define PORT_PLL_TARGET_CNT_MASK0x3FF 0x3FF
1822/* PORT_PLL_9_A */
1823#define PORT_PLL_LOCK_THRESHOLD_SHIFT1 1
1824#define PORT_PLL_LOCK_THRESHOLD_MASK(0x7 << 1) (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT1)
1825/* PORT_PLL_10_A */
1826#define PORT_PLL_DCO_AMP_OVR_EN_H(1 << 27) (1 << 27)
1827#define PORT_PLL_DCO_AMP_DEFAULT15 15
1828#define PORT_PLL_DCO_AMP_MASK0x3c00 0x3c00
1829#define PORT_PLL_DCO_AMP(x)((x) << 10) ((x) << 10)
1830#define _PORT_PLL_BASE(phy, ch)((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + (
((0x6C100) - 0x6C000) + ((ch)) * (((0x6C380) - 0x6C000) - ((0x6C100
) - 0x6C000)))) _BXT_PHY_CH(phy, ch, \((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + (
((0x6C100) - 0x6C000) + ((ch)) * (((0x6C380) - 0x6C000) - ((0x6C100
) - 0x6C000))))
1831 _PORT_PLL_0_B, \((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + (
((0x6C100) - 0x6C000) + ((ch)) * (((0x6C380) - 0x6C000) - ((0x6C100
) - 0x6C000))))
1832 _PORT_PLL_0_C)((((const u32 []){ 0x6C000, 0x162000, 0x163000 })[(phy)]) + (
((0x6C100) - 0x6C000) + ((ch)) * (((0x6C380) - 0x6C000) - ((0x6C100
) - 0x6C000))))
1833#define BXT_PORT_PLL(phy, ch, idx)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (idx) * 4) }
) _MMIO(_PORT_PLL_BASE(phy, ch) + \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (idx) * 4) }
)
1834 (idx) * 4)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C100) - 0x6C000) + ((ch)) * (((
0x6C380) - 0x6C000) - ((0x6C100) - 0x6C000)))) + (idx) * 4) }
)
1835
1836/* BXT PHY common lane registers */
1837#define _PORT_CL1CM_DW0_A0x162000 0x162000
1838#define _PORT_CL1CM_DW0_BC0x6C000 0x6C000
1839#define PHY_POWER_GOOD(1 << 16) (1 << 16)
1840#define PHY_RESERVED(1 << 7) (1 << 7)
1841#define BXT_PORT_CL1CM_DW0(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C000)) }) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C000)) })
1842
1843#define _PORT_CL1CM_DW9_A0x162024 0x162024
1844#define _PORT_CL1CM_DW9_BC0x6C024 0x6C024
1845#define IREF0RC_OFFSET_SHIFT8 8
1846#define IREF0RC_OFFSET_MASK(0xFF << 8) (0xFF << IREF0RC_OFFSET_SHIFT8)
1847#define BXT_PORT_CL1CM_DW9(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C024)) }) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C024)) })
1848
1849#define _PORT_CL1CM_DW10_A0x162028 0x162028
1850#define _PORT_CL1CM_DW10_BC0x6C028 0x6C028
1851#define IREF1RC_OFFSET_SHIFT8 8
1852#define IREF1RC_OFFSET_MASK(0xFF << 8) (0xFF << IREF1RC_OFFSET_SHIFT8)
1853#define BXT_PORT_CL1CM_DW10(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C028)) }) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C028)) })
1854
1855#define _PORT_CL1CM_DW28_A0x162070 0x162070
1856#define _PORT_CL1CM_DW28_BC0x6C070 0x6C070
1857#define OCL1_POWER_DOWN_EN(1 << 23) (1 << 23)
1858#define DW28_OLDO_DYN_PWR_DOWN_EN(1 << 22) (1 << 22)
1859#define SUS_CLK_CONFIG0x3 0x3
1860#define BXT_PORT_CL1CM_DW28(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C070)) }) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C070)) })
1861
1862#define _PORT_CL1CM_DW30_A0x162078 0x162078
1863#define _PORT_CL1CM_DW30_BC0x6C078 0x6C078
1864#define OCL2_LDOFUSE_PWR_DIS(1 << 6) (1 << 6)
1865#define BXT_PORT_CL1CM_DW30(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C078)) }) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C078)) })
1866
1867/*
1868 * CNL/ICL Port/COMBO-PHY Registers
1869 */
1870#define _ICL_COMBOPHY_A0x162000 0x162000
1871#define _ICL_COMBOPHY_B0x6C000 0x6C000
1872#define _EHL_COMBOPHY_C0x160000 0x160000
1873#define _RKL_COMBOPHY_D0x161000 0x161000
1874#define _ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) _PICK(phy, _ICL_COMBOPHY_A, \(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
])
1875 _ICL_COMBOPHY_B, \(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
])
1876 _EHL_COMBOPHY_C, \(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
])
1877 _RKL_COMBOPHY_D)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
])
1878
1879/* CNL/ICL Port CL_DW registers */
1880#define _ICL_PORT_CL_DW(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
1881 4 * (dw))
1882
1883#define CNL_PORT_CL1CM_DW5((const i915_reg_t){ .reg = (0x162014) }) _MMIO(0x162014)((const i915_reg_t){ .reg = (0x162014) })
1884#define ICL_PORT_CL_DW5(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (5))) }) _MMIO(_ICL_PORT_CL_DW(5, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (5))) })
1885#define CL_POWER_DOWN_ENABLE(1 << 4) (1 << 4)
1886#define SUS_CLOCK_CONFIG(3 << 0) (3 << 0)
1887
1888#define ICL_PORT_CL_DW10(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (10))) }) _MMIO(_ICL_PORT_CL_DW(10, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (10))) })
1889#define PG_SEQ_DELAY_OVERRIDE_MASK(3 << 25) (3 << 25)
1890#define PG_SEQ_DELAY_OVERRIDE_SHIFT25 25
1891#define PG_SEQ_DELAY_OVERRIDE_ENABLE(1 << 24) (1 << 24)
1892#define PWR_UP_ALL_LANES(0x0 << 4) (0x0 << 4)
1893#define PWR_DOWN_LN_3_2_1(0xe << 4) (0xe << 4)
1894#define PWR_DOWN_LN_3_2(0xc << 4) (0xc << 4)
1895#define PWR_DOWN_LN_3(0x8 << 4) (0x8 << 4)
1896#define PWR_DOWN_LN_2_1_0(0x7 << 4) (0x7 << 4)
1897#define PWR_DOWN_LN_1_0(0x3 << 4) (0x3 << 4)
1898#define PWR_DOWN_LN_3_1(0xa << 4) (0xa << 4)
1899#define PWR_DOWN_LN_3_1_0(0xb << 4) (0xb << 4)
1900#define PWR_DOWN_LN_MASK(0xf << 4) (0xf << 4)
1901#define PWR_DOWN_LN_SHIFT4 4
1902#define EDP4K2K_MODE_OVRD_EN(1 << 3) (1 << 3)
1903#define EDP4K2K_MODE_OVRD_OPTIMIZED(1 << 2) (1 << 2)
1904
1905#define ICL_PORT_CL_DW12(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (12))) }) _MMIO(_ICL_PORT_CL_DW(12, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 4 * (12))) })
1906#define ICL_LANE_ENABLE_AUX(1 << 0) (1 << 0)
1907
1908/* CNL/ICL Port COMP_DW registers */
1909#define _ICL_PORT_COMP0x100 0x100
1910#define _ICL_PORT_COMP_DW(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 0x100 + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
1911 _ICL_PORT_COMP0x100 + 4 * (dw))
1912
1913#define CNL_PORT_COMP_DW0((const i915_reg_t){ .reg = (0x162100) }) _MMIO(0x162100)((const i915_reg_t){ .reg = (0x162100) })
1914#define ICL_PORT_COMP_DW0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (0))) }) _MMIO(_ICL_PORT_COMP_DW(0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (0))) })
1915#define COMP_INIT(1 << 31) (1 << 31)
1916
1917#define CNL_PORT_COMP_DW1((const i915_reg_t){ .reg = (0x162104) }) _MMIO(0x162104)((const i915_reg_t){ .reg = (0x162104) })
1918#define ICL_PORT_COMP_DW1(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (1))) }) _MMIO(_ICL_PORT_COMP_DW(1, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (1))) })
1919
1920#define CNL_PORT_COMP_DW3((const i915_reg_t){ .reg = (0x16210c) }) _MMIO(0x16210c)((const i915_reg_t){ .reg = (0x16210c) })
1921#define ICL_PORT_COMP_DW3(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (3))) }) _MMIO(_ICL_PORT_COMP_DW(3, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (3))) })
1922#define PROCESS_INFO_DOT_0(0 << 26) (0 << 26)
1923#define PROCESS_INFO_DOT_1(1 << 26) (1 << 26)
1924#define PROCESS_INFO_DOT_4(2 << 26) (2 << 26)
1925#define PROCESS_INFO_MASK(7 << 26) (7 << 26)
1926#define PROCESS_INFO_SHIFT26 26
1927#define VOLTAGE_INFO_0_85V(0 << 24) (0 << 24)
1928#define VOLTAGE_INFO_0_95V(1 << 24) (1 << 24)
1929#define VOLTAGE_INFO_1_05V(2 << 24) (2 << 24)
1930#define VOLTAGE_INFO_MASK(3 << 24) (3 << 24)
1931#define VOLTAGE_INFO_SHIFT24 24
1932
1933#define ICL_PORT_COMP_DW8(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (8))) }) _MMIO(_ICL_PORT_COMP_DW(8, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (8))) })
1934#define IREFGEN(1 << 24) (1 << 24)
1935
1936#define CNL_PORT_COMP_DW9((const i915_reg_t){ .reg = (0x162124) }) _MMIO(0x162124)((const i915_reg_t){ .reg = (0x162124) })
1937#define ICL_PORT_COMP_DW9(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (9))) }) _MMIO(_ICL_PORT_COMP_DW(9, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (9))) })
1938
1939#define CNL_PORT_COMP_DW10((const i915_reg_t){ .reg = (0x162128) }) _MMIO(0x162128)((const i915_reg_t){ .reg = (0x162128) })
1940#define ICL_PORT_COMP_DW10(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (10))) }) _MMIO(_ICL_PORT_COMP_DW(10, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x100 + 4 * (10))) })
1941
1942/* CNL/ICL Port PCS registers */
1943#define _CNL_PORT_PCS_DW1_GRP_AE0x162304 0x162304
1944#define _CNL_PORT_PCS_DW1_GRP_B0x162384 0x162384
1945#define _CNL_PORT_PCS_DW1_GRP_C0x162B04 0x162B04
1946#define _CNL_PORT_PCS_DW1_GRP_D0x162B84 0x162B84
1947#define _CNL_PORT_PCS_DW1_GRP_F0x162A04 0x162A04
1948#define _CNL_PORT_PCS_DW1_LN0_AE0x162404 0x162404
1949#define _CNL_PORT_PCS_DW1_LN0_B0x162604 0x162604
1950#define _CNL_PORT_PCS_DW1_LN0_C0x162C04 0x162C04
1951#define _CNL_PORT_PCS_DW1_LN0_D0x162E04 0x162E04
1952#define _CNL_PORT_PCS_DW1_LN0_F0x162804 0x162804
1953#define CNL_PORT_PCS_DW1_GRP(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) }) _MMIO(_PICK(phy, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1954 _CNL_PORT_PCS_DW1_GRP_AE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1955 _CNL_PORT_PCS_DW1_GRP_B, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1956 _CNL_PORT_PCS_DW1_GRP_C, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1957 _CNL_PORT_PCS_DW1_GRP_D, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1958 _CNL_PORT_PCS_DW1_GRP_AE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1959 _CNL_PORT_PCS_DW1_GRP_F))((const i915_reg_t){ .reg = ((((const u32 []){ 0x162304, 0x162384
, 0x162B04, 0x162B84, 0x162304, 0x162A04 })[phy])) })
1960#define CNL_PORT_PCS_DW1_LN0(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) }) _MMIO(_PICK(phy, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1961 _CNL_PORT_PCS_DW1_LN0_AE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1962 _CNL_PORT_PCS_DW1_LN0_B, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1963 _CNL_PORT_PCS_DW1_LN0_C, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1964 _CNL_PORT_PCS_DW1_LN0_D, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1965 _CNL_PORT_PCS_DW1_LN0_AE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1966 _CNL_PORT_PCS_DW1_LN0_F))((const i915_reg_t){ .reg = ((((const u32 []){ 0x162404, 0x162604
, 0x162C04, 0x162E04, 0x162404, 0x162804 })[phy])) })
1967
1968#define _ICL_PORT_PCS_AUX0x300 0x300
1969#define _ICL_PORT_PCS_GRP0x600 0x600
1970#define _ICL_PORT_PCS_LN(ln)(0x800 + (ln) * 0x100) (0x800 + (ln) * 0x100)
1971#define _ICL_PORT_PCS_DW_AUX(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 0x300 + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
1972 _ICL_PORT_PCS_AUX0x300 + 4 * (dw))
1973#define _ICL_PORT_PCS_DW_GRP(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 0x600 + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
1974 _ICL_PORT_PCS_GRP0x600 + 4 * (dw))
1975#define _ICL_PORT_PCS_DW_LN(dw, ln, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + (0x800 + (ln) * 0x100) + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
1976 _ICL_PORT_PCS_LN(ln)(0x800 + (ln) * 0x100) + 4 * (dw))
1977#define ICL_PORT_PCS_DW1_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x300 + 4 * (1))) }) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x300 + 4 * (1))) })
1978#define ICL_PORT_PCS_DW1_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x600 + 4 * (1))) }) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x600 + 4 * (1))) })
1979#define ICL_PORT_PCS_DW1_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x800 + (0) * 0x100) + 4 * (
1))) }) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x800 + (0) * 0x100) + 4 * (
1))) })
1980#define DCC_MODE_SELECT_MASK(0x3 << 20) (0x3 << 20)
1981#define DCC_MODE_SELECT_CONTINUOSLY(0x3 << 20) (0x3 << 20)
1982#define COMMON_KEEPER_EN(1 << 26) (1 << 26)
1983#define LATENCY_OPTIM_MASK(0x3 << 2) (0x3 << 2)
1984#define LATENCY_OPTIM_VAL(x)((x) << 2) ((x) << 2)
1985
1986/* CNL/ICL Port TX registers */
1987#define _CNL_PORT_TX_AE_GRP_OFFSET0x162340 0x162340
1988#define _CNL_PORT_TX_B_GRP_OFFSET0x1623C0 0x1623C0
1989#define _CNL_PORT_TX_C_GRP_OFFSET0x162B40 0x162B40
1990#define _CNL_PORT_TX_D_GRP_OFFSET0x162BC0 0x162BC0
1991#define _CNL_PORT_TX_F_GRP_OFFSET0x162A40 0x162A40
1992#define _CNL_PORT_TX_AE_LN0_OFFSET0x162440 0x162440
1993#define _CNL_PORT_TX_B_LN0_OFFSET0x162640 0x162640
1994#define _CNL_PORT_TX_C_LN0_OFFSET0x162C40 0x162C40
1995#define _CNL_PORT_TX_D_LN0_OFFSET0x162E40 0x162E40
1996#define _CNL_PORT_TX_F_LN0_OFFSET0x162840 0x162840
1997#define _CNL_PORT_TX_DW_GRP(dw, port)((((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)]) + 4 * (dw)) (_PICK((port), \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
1998 _CNL_PORT_TX_AE_GRP_OFFSET, \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
1999 _CNL_PORT_TX_B_GRP_OFFSET, \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
2000 _CNL_PORT_TX_B_GRP_OFFSET, \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
2001 _CNL_PORT_TX_D_GRP_OFFSET, \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
2002 _CNL_PORT_TX_AE_GRP_OFFSET, \(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)])
2003 _CNL_PORT_TX_F_GRP_OFFSET)(((const u32 []){ 0x162340, 0x1623C0, 0x1623C0, 0x162BC0, 0x162340
, 0x162A40 })[(port)]) + \
2004 4 * (dw))
2005#define _CNL_PORT_TX_DW_LN0(dw, port)((((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)]) + 4 * (dw)) (_PICK((port), \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2006 _CNL_PORT_TX_AE_LN0_OFFSET, \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2007 _CNL_PORT_TX_B_LN0_OFFSET, \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2008 _CNL_PORT_TX_B_LN0_OFFSET, \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2009 _CNL_PORT_TX_D_LN0_OFFSET, \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2010 _CNL_PORT_TX_AE_LN0_OFFSET, \(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)])
2011 _CNL_PORT_TX_F_LN0_OFFSET)(((const u32 []){ 0x162440, 0x162640, 0x162640, 0x162E40, 0x162440
, 0x162840 })[(port)]) + \
2012 4 * (dw))
2013
2014#define _ICL_PORT_TX_AUX0x380 0x380
2015#define _ICL_PORT_TX_GRP0x680 0x680
2016#define _ICL_PORT_TX_LN(ln)(0x880 + (ln) * 0x100) (0x880 + (ln) * 0x100)
2017
2018#define _ICL_PORT_TX_DW_AUX(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 0x380 + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
2019 _ICL_PORT_TX_AUX0x380 + 4 * (dw))
2020#define _ICL_PORT_TX_DW_GRP(dw, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + 0x680 + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
2021 _ICL_PORT_TX_GRP0x680 + 4 * (dw))
2022#define _ICL_PORT_TX_DW_LN(dw, ln, phy)((((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + (0x880 + (ln) * 0x100) + 4 * (dw)) (_ICL_COMBOPHY(phy)(((const u32 []){ 0x162000, 0x6C000, 0x160000, 0x161000 })[phy
]) + \
2023 _ICL_PORT_TX_LN(ln)(0x880 + (ln) * 0x100) + 4 * (dw))
2024
2025#define CNL_PORT_TX_DW2_GRP(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[(port)]) + 4 * (2
))) }) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[(port)]) + 4 * (2
))) })
2026#define CNL_PORT_TX_DW2_LN0(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[(port)]) + 4 * (2
))) }) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[(port)]) + 4 * (2
))) })
2027#define ICL_PORT_TX_DW2_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (2))) }) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (2))) })
2028#define ICL_PORT_TX_DW2_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (2))) }) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (2))) })
2029#define ICL_PORT_TX_DW2_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
2))) }) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
2))) })
2030#define SWING_SEL_UPPER(x)(((x) >> 3) << 15) (((x) >> 3) << 15)
2031#define SWING_SEL_UPPER_MASK(1 << 15) (1 << 15)
2032#define SWING_SEL_LOWER(x)(((x) & 0x7) << 11) (((x) & 0x7) << 11)
2033#define SWING_SEL_LOWER_MASK(0x7 << 11) (0x7 << 11)
2034#define FRC_LATENCY_OPTIM_MASK(0x7 << 8) (0x7 << 8)
2035#define FRC_LATENCY_OPTIM_VAL(x)((x) << 8) ((x) << 8)
2036#define RCOMP_SCALAR(x)((x) << 0) ((x) << 0)
2037#define RCOMP_SCALAR_MASK(0xFF << 0) (0xFF << 0)
2038
2039#define _CNL_PORT_TX_DW4_LN0_AE0x162450 0x162450
2040#define _CNL_PORT_TX_DW4_LN1_AE0x1624D0 0x1624D0
2041#define CNL_PORT_TX_DW4_GRP(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[((port))]) + 4 * (
4))) }) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[((port))]) + 4 * (
4))) })
2042#define CNL_PORT_TX_DW4_LN0(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4))) }) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4))) })
2043#define CNL_PORT_TX_DW4_LN(ln, port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4)) + ((ln) * (0x1624D0 - 0x162450))) }) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4)) + ((ln) * (0x1624D0 - 0x162450))) })
2044 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4)) + ((ln) * (0x1624D0 - 0x162450))) })
2045 _CNL_PORT_TX_DW4_LN0_AE)))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
4)) + ((ln) * (0x1624D0 - 0x162450))) })
2046#define ICL_PORT_TX_DW4_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (4))) }) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (4))) })
2047#define ICL_PORT_TX_DW4_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (4))) }) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (4))) })
2048#define ICL_PORT_TX_DW4_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
4))) }) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
4))) })
2049#define ICL_PORT_TX_DW4_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (ln) * 0x100) + 4 * (
4))) }) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (ln) * 0x100) + 4 * (
4))) })
2050#define LOADGEN_SELECT(1 << 31) (1 << 31)
2051#define POST_CURSOR_1(x)((x) << 12) ((x) << 12)
2052#define POST_CURSOR_1_MASK(0x3F << 12) (0x3F << 12)
2053#define POST_CURSOR_2(x)((x) << 6) ((x) << 6)
2054#define POST_CURSOR_2_MASK(0x3F << 6) (0x3F << 6)
2055#define CURSOR_COEFF(x)((x) << 0) ((x) << 0)
2056#define CURSOR_COEFF_MASK(0x3F << 0) (0x3F << 0)
2057
2058#define CNL_PORT_TX_DW5_GRP(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[(port)]) + 4 * (5
))) }) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[(port)]) + 4 * (5
))) })
2059#define CNL_PORT_TX_DW5_LN0(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[(port)]) + 4 * (5
))) }) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[(port)]) + 4 * (5
))) })
2060#define ICL_PORT_TX_DW5_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (5))) }) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (5))) })
2061#define ICL_PORT_TX_DW5_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (5))) }) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (5))) })
2062#define ICL_PORT_TX_DW5_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
5))) }) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
5))) })
2063#define TX_TRAINING_EN(1 << 31) (1 << 31)
2064#define TAP2_DISABLE(1 << 30) (1 << 30)
2065#define TAP3_DISABLE(1 << 29) (1 << 29)
2066#define SCALING_MODE_SEL(x)((x) << 18) ((x) << 18)
2067#define SCALING_MODE_SEL_MASK(0x7 << 18) (0x7 << 18)
2068#define RTERM_SELECT(x)((x) << 3) ((x) << 3)
2069#define RTERM_SELECT_MASK(0x7 << 3) (0x7 << 3)
2070
2071#define CNL_PORT_TX_DW7_GRP(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[((port))]) + 4 * (
7))) }) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162340, 0x1623C0
, 0x1623C0, 0x162BC0, 0x162340, 0x162A40 })[((port))]) + 4 * (
7))) })
2072#define CNL_PORT_TX_DW7_LN0(port)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
7))) }) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162440, 0x162640
, 0x162640, 0x162E40, 0x162440, 0x162840 })[((port))]) + 4 * (
7))) })
2073#define ICL_PORT_TX_DW7_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (7))) }) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (7))) })
2074#define ICL_PORT_TX_DW7_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (7))) }) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (7))) })
2075#define ICL_PORT_TX_DW7_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
7))) }) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
7))) })
2076#define ICL_PORT_TX_DW7_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (ln) * 0x100) + 4 * (
7))) }) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (ln) * 0x100) + 4 * (
7))) })
2077#define N_SCALAR(x)((x) << 24) ((x) << 24)
2078#define N_SCALAR_MASK(0x7F << 24) (0x7F << 24)
2079
2080#define ICL_PORT_TX_DW8_AUX(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (8))) }) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x380 + 4 * (8))) })
2081#define ICL_PORT_TX_DW8_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (8))) }) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + 0x680 + 4 * (8))) })
2082#define ICL_PORT_TX_DW8_LN0(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
8))) }) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[phy]) + (0x880 + (0) * 0x100) + 4 * (
8))) })
2083#define ICL_PORT_TX_DW8_ODCC_CLK_SEL((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
2084#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(29))) + 0)) REG_GENMASK(30, 29)((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(29))) + 0))
2085#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2((u32)((((typeof(((u32)((((~0UL) >> (64 - (30) - 1)) &
((~0UL) << (29))) + 0))))(0x1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (30
) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (30) - 1)) &
((~0UL) << (29))) + 0))))(0x1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (30
) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0
))
2086
2087#define _ICL_DPHY_CHKN_REG0x194 0x194
2088#define ICL_DPHY_CHKN(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[port]) + 0x194) }) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000 })[port]) + 0x194) })
2089#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP((u32)((1UL << (7)) + 0)) REG_BIT(7)((u32)((1UL << (7)) + 0))
2090
2091#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1)((const i915_reg_t){ .reg = (((ln0p1) + (tc_port) * ((ln0p2) -
(ln0p1))) + (ln) * ((ln1p1) - (ln0p1))) }) \
2092 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))((const i915_reg_t){ .reg = (((ln0p1) + (tc_port) * ((ln0p2) -
(ln0p1))) + (ln) * ((ln1p1) - (ln0p1))) })
2093
2094#define MG_TX_LINK_PARAMS_TX1LN0_PORT10x16812C 0x16812C
2095#define MG_TX_LINK_PARAMS_TX1LN1_PORT10x16852C 0x16852C
2096#define MG_TX_LINK_PARAMS_TX1LN0_PORT20x16912C 0x16912C
2097#define MG_TX_LINK_PARAMS_TX1LN1_PORT20x16952C 0x16952C
2098#define MG_TX_LINK_PARAMS_TX1LN0_PORT30x16A12C 0x16A12C
2099#define MG_TX_LINK_PARAMS_TX1LN1_PORT30x16A52C 0x16A52C
2100#define MG_TX_LINK_PARAMS_TX1LN0_PORT40x16B12C 0x16B12C
2101#define MG_TX_LINK_PARAMS_TX1LN1_PORT40x16B52C 0x16B52C
2102#define MG_TX1_LINK_PARAMS(ln, tc_port)((const i915_reg_t){ .reg = (((0x16812C) + (tc_port) * ((0x16912C
) - (0x16812C))) + (ln) * ((0x16852C) - (0x16812C))) }) \
2103 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \((const i915_reg_t){ .reg = (((0x16812C) + (tc_port) * ((0x16912C
) - (0x16812C))) + (ln) * ((0x16852C) - (0x16812C))) })
2104 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \((const i915_reg_t){ .reg = (((0x16812C) + (tc_port) * ((0x16912C
) - (0x16812C))) + (ln) * ((0x16852C) - (0x16812C))) })
2105 MG_TX_LINK_PARAMS_TX1LN1_PORT1)((const i915_reg_t){ .reg = (((0x16812C) + (tc_port) * ((0x16912C
) - (0x16812C))) + (ln) * ((0x16852C) - (0x16812C))) })
2106
2107#define MG_TX_LINK_PARAMS_TX2LN0_PORT10x1680AC 0x1680AC
2108#define MG_TX_LINK_PARAMS_TX2LN1_PORT10x1684AC 0x1684AC
2109#define MG_TX_LINK_PARAMS_TX2LN0_PORT20x1690AC 0x1690AC
2110#define MG_TX_LINK_PARAMS_TX2LN1_PORT20x1694AC 0x1694AC
2111#define MG_TX_LINK_PARAMS_TX2LN0_PORT30x16A0AC 0x16A0AC
2112#define MG_TX_LINK_PARAMS_TX2LN1_PORT30x16A4AC 0x16A4AC
2113#define MG_TX_LINK_PARAMS_TX2LN0_PORT40x16B0AC 0x16B0AC
2114#define MG_TX_LINK_PARAMS_TX2LN1_PORT40x16B4AC 0x16B4AC
2115#define MG_TX2_LINK_PARAMS(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680AC) + (tc_port) * ((0x1690AC
) - (0x1680AC))) + (ln) * ((0x1684AC) - (0x1680AC))) }) \
2116 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \((const i915_reg_t){ .reg = (((0x1680AC) + (tc_port) * ((0x1690AC
) - (0x1680AC))) + (ln) * ((0x1684AC) - (0x1680AC))) })
2117 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \((const i915_reg_t){ .reg = (((0x1680AC) + (tc_port) * ((0x1690AC
) - (0x1680AC))) + (ln) * ((0x1684AC) - (0x1680AC))) })
2118 MG_TX_LINK_PARAMS_TX2LN1_PORT1)((const i915_reg_t){ .reg = (((0x1680AC) + (tc_port) * ((0x1690AC
) - (0x1680AC))) + (ln) * ((0x1684AC) - (0x1680AC))) })
2119#define CRI_USE_FS32(1 << 5) (1 << 5)
2120
2121#define MG_TX_PISO_READLOAD_TX1LN0_PORT10x16814C 0x16814C
2122#define MG_TX_PISO_READLOAD_TX1LN1_PORT10x16854C 0x16854C
2123#define MG_TX_PISO_READLOAD_TX1LN0_PORT20x16914C 0x16914C
2124#define MG_TX_PISO_READLOAD_TX1LN1_PORT20x16954C 0x16954C
2125#define MG_TX_PISO_READLOAD_TX1LN0_PORT30x16A14C 0x16A14C
2126#define MG_TX_PISO_READLOAD_TX1LN1_PORT30x16A54C 0x16A54C
2127#define MG_TX_PISO_READLOAD_TX1LN0_PORT40x16B14C 0x16B14C
2128#define MG_TX_PISO_READLOAD_TX1LN1_PORT40x16B54C 0x16B54C
2129#define MG_TX1_PISO_READLOAD(ln, tc_port)((const i915_reg_t){ .reg = (((0x16814C) + (tc_port) * ((0x16914C
) - (0x16814C))) + (ln) * ((0x16854C) - (0x16814C))) }) \
2130 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \((const i915_reg_t){ .reg = (((0x16814C) + (tc_port) * ((0x16914C
) - (0x16814C))) + (ln) * ((0x16854C) - (0x16814C))) })
2131 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \((const i915_reg_t){ .reg = (((0x16814C) + (tc_port) * ((0x16914C
) - (0x16814C))) + (ln) * ((0x16854C) - (0x16814C))) })
2132 MG_TX_PISO_READLOAD_TX1LN1_PORT1)((const i915_reg_t){ .reg = (((0x16814C) + (tc_port) * ((0x16914C
) - (0x16814C))) + (ln) * ((0x16854C) - (0x16814C))) })
2133
2134#define MG_TX_PISO_READLOAD_TX2LN0_PORT10x1680CC 0x1680CC
2135#define MG_TX_PISO_READLOAD_TX2LN1_PORT10x1684CC 0x1684CC
2136#define MG_TX_PISO_READLOAD_TX2LN0_PORT20x1690CC 0x1690CC
2137#define MG_TX_PISO_READLOAD_TX2LN1_PORT20x1694CC 0x1694CC
2138#define MG_TX_PISO_READLOAD_TX2LN0_PORT30x16A0CC 0x16A0CC
2139#define MG_TX_PISO_READLOAD_TX2LN1_PORT30x16A4CC 0x16A4CC
2140#define MG_TX_PISO_READLOAD_TX2LN0_PORT40x16B0CC 0x16B0CC
2141#define MG_TX_PISO_READLOAD_TX2LN1_PORT40x16B4CC 0x16B4CC
2142#define MG_TX2_PISO_READLOAD(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680CC) + (tc_port) * ((0x1690CC
) - (0x1680CC))) + (ln) * ((0x1684CC) - (0x1680CC))) }) \
2143 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \((const i915_reg_t){ .reg = (((0x1680CC) + (tc_port) * ((0x1690CC
) - (0x1680CC))) + (ln) * ((0x1684CC) - (0x1680CC))) })
2144 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \((const i915_reg_t){ .reg = (((0x1680CC) + (tc_port) * ((0x1690CC
) - (0x1680CC))) + (ln) * ((0x1684CC) - (0x1680CC))) })
2145 MG_TX_PISO_READLOAD_TX2LN1_PORT1)((const i915_reg_t){ .reg = (((0x1680CC) + (tc_port) * ((0x1690CC
) - (0x1680CC))) + (ln) * ((0x1684CC) - (0x1680CC))) })
2146#define CRI_CALCINIT(1 << 1) (1 << 1)
2147
2148#define MG_TX_SWINGCTRL_TX1LN0_PORT10x168148 0x168148
2149#define MG_TX_SWINGCTRL_TX1LN1_PORT10x168548 0x168548
2150#define MG_TX_SWINGCTRL_TX1LN0_PORT20x169148 0x169148
2151#define MG_TX_SWINGCTRL_TX1LN1_PORT20x169548 0x169548
2152#define MG_TX_SWINGCTRL_TX1LN0_PORT30x16A148 0x16A148
2153#define MG_TX_SWINGCTRL_TX1LN1_PORT30x16A548 0x16A548
2154#define MG_TX_SWINGCTRL_TX1LN0_PORT40x16B148 0x16B148
2155#define MG_TX_SWINGCTRL_TX1LN1_PORT40x16B548 0x16B548
2156#define MG_TX1_SWINGCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x168148) + (tc_port) * ((0x169148
) - (0x168148))) + (ln) * ((0x168548) - (0x168148))) }) \
2157 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \((const i915_reg_t){ .reg = (((0x168148) + (tc_port) * ((0x169148
) - (0x168148))) + (ln) * ((0x168548) - (0x168148))) })
2158 MG_TX_SWINGCTRL_TX1LN0_PORT2, \((const i915_reg_t){ .reg = (((0x168148) + (tc_port) * ((0x169148
) - (0x168148))) + (ln) * ((0x168548) - (0x168148))) })
2159 MG_TX_SWINGCTRL_TX1LN1_PORT1)((const i915_reg_t){ .reg = (((0x168148) + (tc_port) * ((0x169148
) - (0x168148))) + (ln) * ((0x168548) - (0x168148))) })
2160
2161#define MG_TX_SWINGCTRL_TX2LN0_PORT10x1680C8 0x1680C8
2162#define MG_TX_SWINGCTRL_TX2LN1_PORT10x1684C8 0x1684C8
2163#define MG_TX_SWINGCTRL_TX2LN0_PORT20x1690C8 0x1690C8
2164#define MG_TX_SWINGCTRL_TX2LN1_PORT20x1694C8 0x1694C8
2165#define MG_TX_SWINGCTRL_TX2LN0_PORT30x16A0C8 0x16A0C8
2166#define MG_TX_SWINGCTRL_TX2LN1_PORT30x16A4C8 0x16A4C8
2167#define MG_TX_SWINGCTRL_TX2LN0_PORT40x16B0C8 0x16B0C8
2168#define MG_TX_SWINGCTRL_TX2LN1_PORT40x16B4C8 0x16B4C8
2169#define MG_TX2_SWINGCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680C8) + (tc_port) * ((0x1690C8
) - (0x1680C8))) + (ln) * ((0x1684C8) - (0x1680C8))) }) \
2170 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \((const i915_reg_t){ .reg = (((0x1680C8) + (tc_port) * ((0x1690C8
) - (0x1680C8))) + (ln) * ((0x1684C8) - (0x1680C8))) })
2171 MG_TX_SWINGCTRL_TX2LN0_PORT2, \((const i915_reg_t){ .reg = (((0x1680C8) + (tc_port) * ((0x1690C8
) - (0x1680C8))) + (ln) * ((0x1684C8) - (0x1680C8))) })
2172 MG_TX_SWINGCTRL_TX2LN1_PORT1)((const i915_reg_t){ .reg = (((0x1680C8) + (tc_port) * ((0x1690C8
) - (0x1680C8))) + (ln) * ((0x1684C8) - (0x1680C8))) })
2173#define CRI_TXDEEMPH_OVERRIDE_17_12(x)((x) << 0) ((x) << 0)
2174#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK(0x3F << 0) (0x3F << 0)
2175
2176#define MG_TX_DRVCTRL_TX1LN0_TXPORT10x168144 0x168144
2177#define MG_TX_DRVCTRL_TX1LN1_TXPORT10x168544 0x168544
2178#define MG_TX_DRVCTRL_TX1LN0_TXPORT20x169144 0x169144
2179#define MG_TX_DRVCTRL_TX1LN1_TXPORT20x169544 0x169544
2180#define MG_TX_DRVCTRL_TX1LN0_TXPORT30x16A144 0x16A144
2181#define MG_TX_DRVCTRL_TX1LN1_TXPORT30x16A544 0x16A544
2182#define MG_TX_DRVCTRL_TX1LN0_TXPORT40x16B144 0x16B144
2183#define MG_TX_DRVCTRL_TX1LN1_TXPORT40x16B544 0x16B544
2184#define MG_TX1_DRVCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x168144) + (tc_port) * ((0x169144
) - (0x168144))) + (ln) * ((0x168544) - (0x168144))) }) \
2185 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \((const i915_reg_t){ .reg = (((0x168144) + (tc_port) * ((0x169144
) - (0x168144))) + (ln) * ((0x168544) - (0x168144))) })
2186 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \((const i915_reg_t){ .reg = (((0x168144) + (tc_port) * ((0x169144
) - (0x168144))) + (ln) * ((0x168544) - (0x168144))) })
2187 MG_TX_DRVCTRL_TX1LN1_TXPORT1)((const i915_reg_t){ .reg = (((0x168144) + (tc_port) * ((0x169144
) - (0x168144))) + (ln) * ((0x168544) - (0x168144))) })
2188
2189#define MG_TX_DRVCTRL_TX2LN0_PORT10x1680C4 0x1680C4
2190#define MG_TX_DRVCTRL_TX2LN1_PORT10x1684C4 0x1684C4
2191#define MG_TX_DRVCTRL_TX2LN0_PORT20x1690C4 0x1690C4
2192#define MG_TX_DRVCTRL_TX2LN1_PORT20x1694C4 0x1694C4
2193#define MG_TX_DRVCTRL_TX2LN0_PORT30x16A0C4 0x16A0C4
2194#define MG_TX_DRVCTRL_TX2LN1_PORT30x16A4C4 0x16A4C4
2195#define MG_TX_DRVCTRL_TX2LN0_PORT40x16B0C4 0x16B0C4
2196#define MG_TX_DRVCTRL_TX2LN1_PORT40x16B4C4 0x16B4C4
2197#define MG_TX2_DRVCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680C4) + (tc_port) * ((0x1690C4
) - (0x1680C4))) + (ln) * ((0x1684C4) - (0x1680C4))) }) \
2198 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \((const i915_reg_t){ .reg = (((0x1680C4) + (tc_port) * ((0x1690C4
) - (0x1680C4))) + (ln) * ((0x1684C4) - (0x1680C4))) })
2199 MG_TX_DRVCTRL_TX2LN0_PORT2, \((const i915_reg_t){ .reg = (((0x1680C4) + (tc_port) * ((0x1690C4
) - (0x1680C4))) + (ln) * ((0x1684C4) - (0x1680C4))) })
2200 MG_TX_DRVCTRL_TX2LN1_PORT1)((const i915_reg_t){ .reg = (((0x1680C4) + (tc_port) * ((0x1690C4
) - (0x1680C4))) + (ln) * ((0x1684C4) - (0x1680C4))) })
2201#define CRI_TXDEEMPH_OVERRIDE_11_6(x)((x) << 24) ((x) << 24)
2202#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK(0x3F << 24) (0x3F << 24)
2203#define CRI_TXDEEMPH_OVERRIDE_EN(1 << 22) (1 << 22)
2204#define CRI_TXDEEMPH_OVERRIDE_5_0(x)((x) << 16) ((x) << 16)
2205#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK(0x3F << 16) (0x3F << 16)
2206#define CRI_LOADGEN_SEL(x)((x) << 12) ((x) << 12)
2207#define CRI_LOADGEN_SEL_MASK(0x3 << 12) (0x3 << 12)
2208
2209#define MG_CLKHUB_LN0_PORT10x16839C 0x16839C
2210#define MG_CLKHUB_LN1_PORT10x16879C 0x16879C
2211#define MG_CLKHUB_LN0_PORT20x16939C 0x16939C
2212#define MG_CLKHUB_LN1_PORT20x16979C 0x16979C
2213#define MG_CLKHUB_LN0_PORT30x16A39C 0x16A39C
2214#define MG_CLKHUB_LN1_PORT30x16A79C 0x16A79C
2215#define MG_CLKHUB_LN0_PORT40x16B39C 0x16B39C
2216#define MG_CLKHUB_LN1_PORT40x16B79C 0x16B79C
2217#define MG_CLKHUB(ln, tc_port)((const i915_reg_t){ .reg = (((0x16839C) + (tc_port) * ((0x16939C
) - (0x16839C))) + (ln) * ((0x16879C) - (0x16839C))) }) \
2218 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \((const i915_reg_t){ .reg = (((0x16839C) + (tc_port) * ((0x16939C
) - (0x16839C))) + (ln) * ((0x16879C) - (0x16839C))) })
2219 MG_CLKHUB_LN0_PORT2, \((const i915_reg_t){ .reg = (((0x16839C) + (tc_port) * ((0x16939C
) - (0x16839C))) + (ln) * ((0x16879C) - (0x16839C))) })
2220 MG_CLKHUB_LN1_PORT1)((const i915_reg_t){ .reg = (((0x16839C) + (tc_port) * ((0x16939C
) - (0x16839C))) + (ln) * ((0x16879C) - (0x16839C))) })
2221#define CFG_LOW_RATE_LKREN_EN(1 << 11) (1 << 11)
2222
2223#define MG_TX_DCC_TX1LN0_PORT10x168110 0x168110
2224#define MG_TX_DCC_TX1LN1_PORT10x168510 0x168510
2225#define MG_TX_DCC_TX1LN0_PORT20x169110 0x169110
2226#define MG_TX_DCC_TX1LN1_PORT20x169510 0x169510
2227#define MG_TX_DCC_TX1LN0_PORT30x16A110 0x16A110
2228#define MG_TX_DCC_TX1LN1_PORT30x16A510 0x16A510
2229#define MG_TX_DCC_TX1LN0_PORT40x16B110 0x16B110
2230#define MG_TX_DCC_TX1LN1_PORT40x16B510 0x16B510
2231#define MG_TX1_DCC(ln, tc_port)((const i915_reg_t){ .reg = (((0x168110) + (tc_port) * ((0x169110
) - (0x168110))) + (ln) * ((0x168510) - (0x168110))) }) \
2232 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \((const i915_reg_t){ .reg = (((0x168110) + (tc_port) * ((0x169110
) - (0x168110))) + (ln) * ((0x168510) - (0x168110))) })
2233 MG_TX_DCC_TX1LN0_PORT2, \((const i915_reg_t){ .reg = (((0x168110) + (tc_port) * ((0x169110
) - (0x168110))) + (ln) * ((0x168510) - (0x168110))) })
2234 MG_TX_DCC_TX1LN1_PORT1)((const i915_reg_t){ .reg = (((0x168110) + (tc_port) * ((0x169110
) - (0x168110))) + (ln) * ((0x168510) - (0x168110))) })
2235#define MG_TX_DCC_TX2LN0_PORT10x168090 0x168090
2236#define MG_TX_DCC_TX2LN1_PORT10x168490 0x168490
2237#define MG_TX_DCC_TX2LN0_PORT20x169090 0x169090
2238#define MG_TX_DCC_TX2LN1_PORT20x169490 0x169490
2239#define MG_TX_DCC_TX2LN0_PORT30x16A090 0x16A090
2240#define MG_TX_DCC_TX2LN1_PORT30x16A490 0x16A490
2241#define MG_TX_DCC_TX2LN0_PORT40x16B090 0x16B090
2242#define MG_TX_DCC_TX2LN1_PORT40x16B490 0x16B490
2243#define MG_TX2_DCC(ln, tc_port)((const i915_reg_t){ .reg = (((0x168090) + (tc_port) * ((0x169090
) - (0x168090))) + (ln) * ((0x168490) - (0x168090))) }) \
2244 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \((const i915_reg_t){ .reg = (((0x168090) + (tc_port) * ((0x169090
) - (0x168090))) + (ln) * ((0x168490) - (0x168090))) })
2245 MG_TX_DCC_TX2LN0_PORT2, \((const i915_reg_t){ .reg = (((0x168090) + (tc_port) * ((0x169090
) - (0x168090))) + (ln) * ((0x168490) - (0x168090))) })
2246 MG_TX_DCC_TX2LN1_PORT1)((const i915_reg_t){ .reg = (((0x168090) + (tc_port) * ((0x169090
) - (0x168090))) + (ln) * ((0x168490) - (0x168090))) })
2247#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x)((x) << 25) ((x) << 25)
2248#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK(0x3 << 25) (0x3 << 25)
2249#define CFG_AMI_CK_DIV_OVERRIDE_EN(1 << 24) (1 << 24)
2250
2251#define MG_DP_MODE_LN0_ACU_PORT10x1683A0 0x1683A0
2252#define MG_DP_MODE_LN1_ACU_PORT10x1687A0 0x1687A0
2253#define MG_DP_MODE_LN0_ACU_PORT20x1693A0 0x1693A0
2254#define MG_DP_MODE_LN1_ACU_PORT20x1697A0 0x1697A0
2255#define MG_DP_MODE_LN0_ACU_PORT30x16A3A0 0x16A3A0
2256#define MG_DP_MODE_LN1_ACU_PORT30x16A7A0 0x16A7A0
2257#define MG_DP_MODE_LN0_ACU_PORT40x16B3A0 0x16B3A0
2258#define MG_DP_MODE_LN1_ACU_PORT40x16B7A0 0x16B7A0
2259#define MG_DP_MODE(ln, tc_port)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0
) - (0x1683A0))) + (ln) * ((0x1687A0) - (0x1683A0))) }) \
2260 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0
) - (0x1683A0))) + (ln) * ((0x1687A0) - (0x1683A0))) })
2261 MG_DP_MODE_LN0_ACU_PORT2, \((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0
) - (0x1683A0))) + (ln) * ((0x1687A0) - (0x1683A0))) })
2262 MG_DP_MODE_LN1_ACU_PORT1)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0
) - (0x1683A0))) + (ln) * ((0x1687A0) - (0x1683A0))) })
2263#define MG_DP_MODE_CFG_DP_X2_MODE(1 << 7) (1 << 7)
2264#define MG_DP_MODE_CFG_DP_X1_MODE(1 << 6) (1 << 6)
2265
2266/* The spec defines this only for BXT PHY0, but lets assume that this
2267 * would exist for PHY1 too if it had a second channel.
2268 */
2269#define _PORT_CL2CM_DW6_A0x162358 0x162358
2270#define _PORT_CL2CM_DW6_BC0x6C358 0x6C358
2271#define BXT_PORT_CL2CM_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C358)) }) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C358)) })
2272#define DW6_OLDO_DYN_PWR_DOWN_EN(1 << 28) (1 << 28)
2273
2274#define FIA1_BASE0x163000 0x163000
2275#define FIA2_BASE0x16E000 0x16E000
2276#define FIA3_BASE0x16F000 0x16F000
2277#define _FIA(fia)(((const u32 []){ 0x163000, 0x16E000, 0x16F000 })[(fia)]) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)(((const u32 []){ 0x163000, 0x16E000, 0x16F000 })[(fia)])
2278#define _MMIO_FIA(fia, off)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[(fia)]) + (off)) }) _MMIO(_FIA(fia) + (off))((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[(fia)]) + (off)) })
2279
2280/* ICL PHY DFLEX registers */
2281#define PORT_TX_DFLEXDPMLE1(fia)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x008C0)) }) _MMIO_FIA((fia), 0x008C0)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x008C0)) })
2282#define DFLEXDPMLE1_DPMLETC_MASK(idx)(0xf << (4 * (idx))) (0xf << (4 * (idx)))
2283#define DFLEXDPMLE1_DPMLETC_ML0(idx)(1 << (4 * (idx))) (1 << (4 * (idx)))
2284#define DFLEXDPMLE1_DPMLETC_ML1_0(idx)(3 << (4 * (idx))) (3 << (4 * (idx)))
2285#define DFLEXDPMLE1_DPMLETC_ML3(idx)(8 << (4 * (idx))) (8 << (4 * (idx)))
2286#define DFLEXDPMLE1_DPMLETC_ML3_2(idx)(12 << (4 * (idx))) (12 << (4 * (idx)))
2287#define DFLEXDPMLE1_DPMLETC_ML3_0(idx)(15 << (4 * (idx))) (15 << (4 * (idx)))
2288
2289/* BXT PHY Ref registers */
2290#define _PORT_REF_DW3_A0x16218C 0x16218C
2291#define _PORT_REF_DW3_BC0x6C18C 0x6C18C
2292#define GRC_DONE(1 << 22) (1 << 22)
2293#define BXT_PORT_REF_DW3(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C18C)) }) _BXT_PHY((phy), _PORT_REF_DW3_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C18C)) })
2294
2295#define _PORT_REF_DW6_A0x162198 0x162198
2296#define _PORT_REF_DW6_BC0x6C198 0x6C198
2297#define GRC_CODE_SHIFT24 24
2298#define GRC_CODE_MASK(0xFF << 24) (0xFF << GRC_CODE_SHIFT24)
2299#define GRC_CODE_FAST_SHIFT16 16
2300#define GRC_CODE_FAST_MASK(0xFF << 16) (0xFF << GRC_CODE_FAST_SHIFT16)
2301#define GRC_CODE_SLOW_SHIFT8 8
2302#define GRC_CODE_SLOW_MASK(0xFF << 8) (0xFF << GRC_CODE_SLOW_SHIFT8)
2303#define GRC_CODE_NOM_MASK0xFF 0xFF
2304#define BXT_PORT_REF_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C198)) }) _BXT_PHY((phy), _PORT_REF_DW6_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C198)) })
2305
2306#define _PORT_REF_DW8_A0x1621A0 0x1621A0
2307#define _PORT_REF_DW8_BC0x6C1A0 0x6C1A0
2308#define GRC_DIS(1 << 15) (1 << 15)
2309#define GRC_RDY_OVRD(1 << 1) (1 << 1)
2310#define BXT_PORT_REF_DW8(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C1A0)) }) _BXT_PHY((phy), _PORT_REF_DW8_BC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C1A0)) })
2311
2312/* BXT PHY PCS registers */
2313#define _PORT_PCS_DW10_LN01_A0x162428 0x162428
2314#define _PORT_PCS_DW10_LN01_B0x6C428 0x6C428
2315#define _PORT_PCS_DW10_LN01_C0x6C828 0x6C828
2316#define _PORT_PCS_DW10_GRP_A0x162C28 0x162C28
2317#define _PORT_PCS_DW10_GRP_B0x6CC28 0x6CC28
2318#define _PORT_PCS_DW10_GRP_C0x6CE28 0x6CE28
2319#define BXT_PORT_PCS_DW10_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) })
2320 _PORT_PCS_DW10_LN01_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) })
2321 _PORT_PCS_DW10_LN01_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) })
2322#define BXT_PORT_PCS_DW10_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) })
2323 _PORT_PCS_DW10_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) })
2324 _PORT_PCS_DW10_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) })
2325
2326#define TX2_SWING_CALC_INIT(1 << 31) (1 << 31)
2327#define TX1_SWING_CALC_INIT(1 << 30) (1 << 30)
2328
2329#define _PORT_PCS_DW12_LN01_A0x162430 0x162430
2330#define _PORT_PCS_DW12_LN01_B0x6C430 0x6C430
2331#define _PORT_PCS_DW12_LN01_C0x6C830 0x6C830
2332#define _PORT_PCS_DW12_LN23_A0x162630 0x162630
2333#define _PORT_PCS_DW12_LN23_B0x6C630 0x6C630
2334#define _PORT_PCS_DW12_LN23_C0x6CA30 0x6CA30
2335#define _PORT_PCS_DW12_GRP_A0x162c30 0x162c30
2336#define _PORT_PCS_DW12_GRP_B0x6CC30 0x6CC30
2337#define _PORT_PCS_DW12_GRP_C0x6CE30 0x6CE30
2338#define LANESTAGGER_STRAP_OVRD(1 << 6) (1 << 6)
2339#define LANE_STAGGER_MASK0x1F 0x1F
2340#define BXT_PORT_PCS_DW12_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) })
2341 _PORT_PCS_DW12_LN01_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) })
2342 _PORT_PCS_DW12_LN01_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C430) - 0x6C000) + ((ch)) * (((
0x6C830) - 0x6C000) - ((0x6C430) - 0x6C000))))) })
2343#define BXT_PORT_PCS_DW12_LN23(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((
0x6CA30) - 0x6C000) - ((0x6C630) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((
0x6CA30) - 0x6C000) - ((0x6C630) - 0x6C000))))) })
2344 _PORT_PCS_DW12_LN23_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((
0x6CA30) - 0x6C000) - ((0x6C630) - 0x6C000))))) })
2345 _PORT_PCS_DW12_LN23_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C630) - 0x6C000) + ((ch)) * (((
0x6CA30) - 0x6C000) - ((0x6C630) - 0x6C000))))) })
2346#define BXT_PORT_PCS_DW12_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC30) - 0x6C000) + ((ch)) * (((
0x6CE30) - 0x6C000) - ((0x6CC30) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC30) - 0x6C000) + ((ch)) * (((
0x6CE30) - 0x6C000) - ((0x6CC30) - 0x6C000))))) })
2347 _PORT_PCS_DW12_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC30) - 0x6C000) + ((ch)) * (((
0x6CE30) - 0x6C000) - ((0x6CC30) - 0x6C000))))) })
2348 _PORT_PCS_DW12_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC30) - 0x6C000) + ((ch)) * (((
0x6CE30) - 0x6C000) - ((0x6CC30) - 0x6C000))))) })
2349
2350/* BXT PHY TX registers */
2351#define _BXT_LANE_OFFSET(lane)(((lane) >> 1) * 0x200 + ((lane) & 1) * 0x80) (((lane) >> 1) * 0x200 + \
2352 ((lane) & 1) * 0x80)
2353
2354#define _PORT_TX_DW2_LN0_A0x162508 0x162508
2355#define _PORT_TX_DW2_LN0_B0x6C508 0x6C508
2356#define _PORT_TX_DW2_LN0_C0x6C908 0x6C908
2357#define _PORT_TX_DW2_GRP_A0x162D08 0x162D08
2358#define _PORT_TX_DW2_GRP_B0x6CD08 0x6CD08
2359#define _PORT_TX_DW2_GRP_C0x6CF08 0x6CF08
2360#define BXT_PORT_TX_DW2_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C508) - 0x6C000) + ((ch)) * (((
0x6C908) - 0x6C000) - ((0x6C508) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C508) - 0x6C000) + ((ch)) * (((
0x6C908) - 0x6C000) - ((0x6C508) - 0x6C000))))) })
2361 _PORT_TX_DW2_LN0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C508) - 0x6C000) + ((ch)) * (((
0x6C908) - 0x6C000) - ((0x6C508) - 0x6C000))))) })
2362 _PORT_TX_DW2_LN0_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C508) - 0x6C000) + ((ch)) * (((
0x6C908) - 0x6C000) - ((0x6C508) - 0x6C000))))) })
2363#define BXT_PORT_TX_DW2_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD08) - 0x6C000) + ((ch)) * (((
0x6CF08) - 0x6C000) - ((0x6CD08) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD08) - 0x6C000) + ((ch)) * (((
0x6CF08) - 0x6C000) - ((0x6CD08) - 0x6C000))))) })
2364 _PORT_TX_DW2_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD08) - 0x6C000) + ((ch)) * (((
0x6CF08) - 0x6C000) - ((0x6CD08) - 0x6C000))))) })
2365 _PORT_TX_DW2_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD08) - 0x6C000) + ((ch)) * (((
0x6CF08) - 0x6C000) - ((0x6CD08) - 0x6C000))))) })
2366#define MARGIN_000_SHIFT16 16
2367#define MARGIN_000(0xFF << 16) (0xFF << MARGIN_000_SHIFT16)
2368#define UNIQ_TRANS_SCALE_SHIFT8 8
2369#define UNIQ_TRANS_SCALE(0xFF << 8) (0xFF << UNIQ_TRANS_SCALE_SHIFT8)
2370
2371#define _PORT_TX_DW3_LN0_A0x16250C 0x16250C
2372#define _PORT_TX_DW3_LN0_B0x6C50C 0x6C50C
2373#define _PORT_TX_DW3_LN0_C0x6C90C 0x6C90C
2374#define _PORT_TX_DW3_GRP_A0x162D0C 0x162D0C
2375#define _PORT_TX_DW3_GRP_B0x6CD0C 0x6CD0C
2376#define _PORT_TX_DW3_GRP_C0x6CF0C 0x6CF0C
2377#define BXT_PORT_TX_DW3_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C50C) - 0x6C000) + ((ch)) * (((
0x6C90C) - 0x6C000) - ((0x6C50C) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C50C) - 0x6C000) + ((ch)) * (((
0x6C90C) - 0x6C000) - ((0x6C50C) - 0x6C000))))) })
2378 _PORT_TX_DW3_LN0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C50C) - 0x6C000) + ((ch)) * (((
0x6C90C) - 0x6C000) - ((0x6C50C) - 0x6C000))))) })
2379 _PORT_TX_DW3_LN0_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C50C) - 0x6C000) + ((ch)) * (((
0x6C90C) - 0x6C000) - ((0x6C50C) - 0x6C000))))) })
2380#define BXT_PORT_TX_DW3_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD0C) - 0x6C000) + ((ch)) * (((
0x6CF0C) - 0x6C000) - ((0x6CD0C) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD0C) - 0x6C000) + ((ch)) * (((
0x6CF0C) - 0x6C000) - ((0x6CD0C) - 0x6C000))))) })
2381 _PORT_TX_DW3_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD0C) - 0x6C000) + ((ch)) * (((
0x6CF0C) - 0x6C000) - ((0x6CD0C) - 0x6C000))))) })
2382 _PORT_TX_DW3_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD0C) - 0x6C000) + ((ch)) * (((
0x6CF0C) - 0x6C000) - ((0x6CD0C) - 0x6C000))))) })
2383#define SCALE_DCOMP_METHOD(1 << 26) (1 << 26)
2384#define UNIQUE_TRANGE_EN_METHOD(1 << 27) (1 << 27)
2385
2386#define _PORT_TX_DW4_LN0_A0x162510 0x162510
2387#define _PORT_TX_DW4_LN0_B0x6C510 0x6C510
2388#define _PORT_TX_DW4_LN0_C0x6C910 0x6C910
2389#define _PORT_TX_DW4_GRP_A0x162D10 0x162D10
2390#define _PORT_TX_DW4_GRP_B0x6CD10 0x6CD10
2391#define _PORT_TX_DW4_GRP_C0x6CF10 0x6CF10
2392#define BXT_PORT_TX_DW4_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C510) - 0x6C000) + ((ch)) * (((
0x6C910) - 0x6C000) - ((0x6C510) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C510) - 0x6C000) + ((ch)) * (((
0x6C910) - 0x6C000) - ((0x6C510) - 0x6C000))))) })
2393 _PORT_TX_DW4_LN0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C510) - 0x6C000) + ((ch)) * (((
0x6C910) - 0x6C000) - ((0x6C510) - 0x6C000))))) })
2394 _PORT_TX_DW4_LN0_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C510) - 0x6C000) + ((ch)) * (((
0x6C910) - 0x6C000) - ((0x6C510) - 0x6C000))))) })
2395#define BXT_PORT_TX_DW4_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD10) - 0x6C000) + ((ch)) * (((
0x6CF10) - 0x6C000) - ((0x6CD10) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD10) - 0x6C000) + ((ch)) * (((
0x6CF10) - 0x6C000) - ((0x6CD10) - 0x6C000))))) })
2396 _PORT_TX_DW4_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD10) - 0x6C000) + ((ch)) * (((
0x6CF10) - 0x6C000) - ((0x6CD10) - 0x6C000))))) })
2397 _PORT_TX_DW4_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD10) - 0x6C000) + ((ch)) * (((
0x6CF10) - 0x6C000) - ((0x6CD10) - 0x6C000))))) })
2398#define DEEMPH_SHIFT24 24
2399#define DE_EMPHASIS(0xFF << 24) (0xFF << DEEMPH_SHIFT24)
2400
2401#define _PORT_TX_DW5_LN0_A0x162514 0x162514
2402#define _PORT_TX_DW5_LN0_B0x6C514 0x6C514
2403#define _PORT_TX_DW5_LN0_C0x6C914 0x6C914
2404#define _PORT_TX_DW5_GRP_A0x162D14 0x162D14
2405#define _PORT_TX_DW5_GRP_B0x6CD14 0x6CD14
2406#define _PORT_TX_DW5_GRP_C0x6CF14 0x6CF14
2407#define BXT_PORT_TX_DW5_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C514) - 0x6C000) + ((ch)) * (((
0x6C914) - 0x6C000) - ((0x6C514) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C514) - 0x6C000) + ((ch)) * (((
0x6C914) - 0x6C000) - ((0x6C514) - 0x6C000))))) })
2408 _PORT_TX_DW5_LN0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C514) - 0x6C000) + ((ch)) * (((
0x6C914) - 0x6C000) - ((0x6C514) - 0x6C000))))) })
2409 _PORT_TX_DW5_LN0_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C514) - 0x6C000) + ((ch)) * (((
0x6C914) - 0x6C000) - ((0x6C514) - 0x6C000))))) })
2410#define BXT_PORT_TX_DW5_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD14) - 0x6C000) + ((ch)) * (((
0x6CF14) - 0x6C000) - ((0x6CD14) - 0x6C000))))) }) _MMIO_BXT_PHY_CH(phy, ch, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD14) - 0x6C000) + ((ch)) * (((
0x6CF14) - 0x6C000) - ((0x6CD14) - 0x6C000))))) })
2411 _PORT_TX_DW5_GRP_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD14) - 0x6C000) + ((ch)) * (((
0x6CF14) - 0x6C000) - ((0x6CD14) - 0x6C000))))) })
2412 _PORT_TX_DW5_GRP_C)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD14) - 0x6C000) + ((ch)) * (((
0x6CF14) - 0x6C000) - ((0x6CD14) - 0x6C000))))) })
2413#define DCC_DELAY_RANGE_1(1 << 9) (1 << 9)
2414#define DCC_DELAY_RANGE_2(1 << 8) (1 << 8)
2415
2416#define _PORT_TX_DW14_LN0_A0x162538 0x162538
2417#define _PORT_TX_DW14_LN0_B0x6C538 0x6C538
2418#define _PORT_TX_DW14_LN0_C0x6C938 0x6C938
2419#define LATENCY_OPTIM_SHIFT30 30
2420#define LATENCY_OPTIM(1 << 30) (1 << LATENCY_OPTIM_SHIFT30)
2421#define BXT_PORT_TX_DW14_LN(phy, ch, lane)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) }) \
2422 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
2423 _PORT_TX_DW14_LN0_C) + \((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
2424 _BXT_LANE_OFFSET(lane))((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
2425
2426/* UAIMI scratch pad register 1 */
2427#define UAIMI_SPR1((const i915_reg_t){ .reg = (0x4F074) }) _MMIO(0x4F074)((const i915_reg_t){ .reg = (0x4F074) })
2428/* SKL VccIO mask */
2429#define SKL_VCCIO_MASK0x1 0x1
2430/* SKL balance leg register */
2431#define DISPIO_CR_TX_BMU_CR0((const i915_reg_t){ .reg = (0x6C00C) }) _MMIO(0x6C00C)((const i915_reg_t){ .reg = (0x6C00C) })
2432/* I_boost values */
2433#define BALANCE_LEG_SHIFT(port)(8 + 3 * (port)) (8 + 3 * (port))
2434#define BALANCE_LEG_MASK(port)(7 << (8 + 3 * (port))) (7 << (8 + 3 * (port)))
2435/* Balance leg disable bits */
2436#define BALANCE_LEG_DISABLE_SHIFT23 23
2437#define BALANCE_LEG_DISABLE(port)(1 << (23 + (port))) (1 << (23 + (port)))
2438
2439/*
2440 * Fence registers
2441 * [0-7] @ 0x2000 gen2,gen3
2442 * [8-15] @ 0x3000 945,g33,pnv
2443 *
2444 * [0-15] @ 0x3000 gen4,gen5
2445 *
2446 * [0-15] @ 0x100000 gen6,vlv,chv
2447 * [0-31] @ 0x100000 gen7+
2448 */
2449#define FENCE_REG(i)((const i915_reg_t){ .reg = (0x2000 + (((i) & 8) <<
9) + ((i) & 7) * 4) }) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)((const i915_reg_t){ .reg = (0x2000 + (((i) & 8) <<
9) + ((i) & 7) * 4) })
2450#define I830_FENCE_START_MASK0x07f80000 0x07f80000
2451#define I830_FENCE_TILING_Y_SHIFT12 12
2452#define I830_FENCE_SIZE_BITS(size)((ffs((size) >> 19) - 1) << 8) ((ffs((size) >> 19) - 1) << 8)
2453#define I830_FENCE_PITCH_SHIFT4 4
2454#define I830_FENCE_REG_VALID(1 << 0) (1 << 0)
2455#define I915_FENCE_MAX_PITCH_VAL4 4
2456#define I830_FENCE_MAX_PITCH_VAL6 6
2457#define I830_FENCE_MAX_SIZE_VAL(1 << 8) (1 << 8)
2458
2459#define I915_FENCE_START_MASK0x0ff00000 0x0ff00000
2460#define I915_FENCE_SIZE_BITS(size)((ffs((size) >> 20) - 1) << 8) ((ffs((size) >> 20) - 1) << 8)
2461
2462#define FENCE_REG_965_LO(i)((const i915_reg_t){ .reg = (0x03000 + (i) * 8) }) _MMIO(0x03000 + (i) * 8)((const i915_reg_t){ .reg = (0x03000 + (i) * 8) })
2463#define FENCE_REG_965_HI(i)((const i915_reg_t){ .reg = (0x03000 + (i) * 8 + 4) }) _MMIO(0x03000 + (i) * 8 + 4)((const i915_reg_t){ .reg = (0x03000 + (i) * 8 + 4) })
2464#define I965_FENCE_PITCH_SHIFT2 2
2465#define I965_FENCE_TILING_Y_SHIFT1 1
2466#define I965_FENCE_REG_VALID(1 << 0) (1 << 0)
2467#define I965_FENCE_MAX_PITCH_VAL0x0400 0x0400
2468
2469#define FENCE_REG_GEN6_LO(i)((const i915_reg_t){ .reg = (0x100000 + (i) * 8) }) _MMIO(0x100000 + (i) * 8)((const i915_reg_t){ .reg = (0x100000 + (i) * 8) })
2470#define FENCE_REG_GEN6_HI(i)((const i915_reg_t){ .reg = (0x100000 + (i) * 8 + 4) }) _MMIO(0x100000 + (i) * 8 + 4)((const i915_reg_t){ .reg = (0x100000 + (i) * 8 + 4) })
2471#define GEN6_FENCE_PITCH_SHIFT32 32
2472#define GEN7_FENCE_MAX_PITCH_VAL0x0800 0x0800
2473
2474
2475/* control register for cpu gtt access */
2476#define TILECTL((const i915_reg_t){ .reg = (0x101000) }) _MMIO(0x101000)((const i915_reg_t){ .reg = (0x101000) })
2477#define TILECTL_SWZCTL(1 << 0) (1 << 0)
2478#define TILECTL_TLBPF(1 << 1) (1 << 1)
2479#define TILECTL_TLB_PREFETCH_DIS(1 << 2) (1 << 2)
2480#define TILECTL_BACKSNOOP_DIS(1 << 3) (1 << 3)
2481
2482/*
2483 * Instruction and interrupt control regs
2484 */
2485#define PGTBL_CTL((const i915_reg_t){ .reg = (0x02020) }) _MMIO(0x02020)((const i915_reg_t){ .reg = (0x02020) })
2486#define PGTBL_ADDRESS_LO_MASK0xfffff000 0xfffff000 /* bits [31:12] */
2487#define PGTBL_ADDRESS_HI_MASK0x000000f0 0x000000f0 /* bits [35:32] (gen4) */
2488#define PGTBL_ER((const i915_reg_t){ .reg = (0x02024) }) _MMIO(0x02024)((const i915_reg_t){ .reg = (0x02024) })
2489#define PRB0_BASE(0x2030 - 0x30) (0x2030 - 0x30)
2490#define PRB1_BASE(0x2040 - 0x30) (0x2040 - 0x30) /* 830,gen3 */
2491#define PRB2_BASE(0x2050 - 0x30) (0x2050 - 0x30) /* gen3 */
2492#define SRB0_BASE(0x2100 - 0x30) (0x2100 - 0x30) /* gen2 */
2493#define SRB1_BASE(0x2110 - 0x30) (0x2110 - 0x30) /* gen2 */
2494#define SRB2_BASE(0x2120 - 0x30) (0x2120 - 0x30) /* 830 */
2495#define SRB3_BASE(0x2130 - 0x30) (0x2130 - 0x30) /* 830 */
2496#define RENDER_RING_BASE0x02000 0x02000
2497#define BSD_RING_BASE0x04000 0x04000
2498#define GEN6_BSD_RING_BASE0x12000 0x12000
2499#define GEN8_BSD2_RING_BASE0x1c000 0x1c000
2500#define GEN11_BSD_RING_BASE0x1c0000 0x1c0000
2501#define GEN11_BSD2_RING_BASE0x1c4000 0x1c4000
2502#define GEN11_BSD3_RING_BASE0x1d0000 0x1d0000
2503#define GEN11_BSD4_RING_BASE0x1d4000 0x1d4000
2504#define VEBOX_RING_BASE0x1a000 0x1a000
2505#define GEN11_VEBOX_RING_BASE0x1c8000 0x1c8000
2506#define GEN11_VEBOX2_RING_BASE0x1d8000 0x1d8000
2507#define BLT_RING_BASE0x22000 0x22000
2508#define RING_TAIL(base)((const i915_reg_t){ .reg = ((base) + 0x30) }) _MMIO((base) + 0x30)((const i915_reg_t){ .reg = ((base) + 0x30) })
2509#define RING_HEAD(base)((const i915_reg_t){ .reg = ((base) + 0x34) }) _MMIO((base) + 0x34)((const i915_reg_t){ .reg = ((base) + 0x34) })
2510#define RING_START(base)((const i915_reg_t){ .reg = ((base) + 0x38) }) _MMIO((base) + 0x38)((const i915_reg_t){ .reg = ((base) + 0x38) })
2511#define RING_CTL(base)((const i915_reg_t){ .reg = ((base) + 0x3c) }) _MMIO((base) + 0x3c)((const i915_reg_t){ .reg = ((base) + 0x3c) })
2512#define RING_CTL_SIZE(size)((size) - (1 << 12)) ((size) - PAGE_SIZE(1 << 12)) /* in bytes -> pages */
2513#define RING_SYNC_0(base)((const i915_reg_t){ .reg = ((base) + 0x40) }) _MMIO((base) + 0x40)((const i915_reg_t){ .reg = ((base) + 0x40) })
2514#define RING_SYNC_1(base)((const i915_reg_t){ .reg = ((base) + 0x44) }) _MMIO((base) + 0x44)((const i915_reg_t){ .reg = ((base) + 0x44) })
2515#define RING_SYNC_2(base)((const i915_reg_t){ .reg = ((base) + 0x48) }) _MMIO((base) + 0x48)((const i915_reg_t){ .reg = ((base) + 0x48) })
2516#define GEN6_RVSYNC(((const i915_reg_t){ .reg = ((0x02000) + 0x40) })) (RING_SYNC_0(RENDER_RING_BASE)((const i915_reg_t){ .reg = ((0x02000) + 0x40) }))
2517#define GEN6_RBSYNC(((const i915_reg_t){ .reg = ((0x02000) + 0x44) })) (RING_SYNC_1(RENDER_RING_BASE)((const i915_reg_t){ .reg = ((0x02000) + 0x44) }))
2518#define GEN6_RVESYNC(((const i915_reg_t){ .reg = ((0x02000) + 0x48) })) (RING_SYNC_2(RENDER_RING_BASE)((const i915_reg_t){ .reg = ((0x02000) + 0x48) }))
2519#define GEN6_VBSYNC(((const i915_reg_t){ .reg = ((0x12000) + 0x40) })) (RING_SYNC_0(GEN6_BSD_RING_BASE)((const i915_reg_t){ .reg = ((0x12000) + 0x40) }))
2520#define GEN6_VRSYNC(((const i915_reg_t){ .reg = ((0x12000) + 0x44) })) (RING_SYNC_1(GEN6_BSD_RING_BASE)((const i915_reg_t){ .reg = ((0x12000) + 0x44) }))
2521#define GEN6_VVESYNC(((const i915_reg_t){ .reg = ((0x12000) + 0x48) })) (RING_SYNC_2(GEN6_BSD_RING_BASE)((const i915_reg_t){ .reg = ((0x12000) + 0x48) }))
2522#define GEN6_BRSYNC(((const i915_reg_t){ .reg = ((0x22000) + 0x40) })) (RING_SYNC_0(BLT_RING_BASE)((const i915_reg_t){ .reg = ((0x22000) + 0x40) }))
2523#define GEN6_BVSYNC(((const i915_reg_t){ .reg = ((0x22000) + 0x44) })) (RING_SYNC_1(BLT_RING_BASE)((const i915_reg_t){ .reg = ((0x22000) + 0x44) }))
2524#define GEN6_BVESYNC(((const i915_reg_t){ .reg = ((0x22000) + 0x48) })) (RING_SYNC_2(BLT_RING_BASE)((const i915_reg_t){ .reg = ((0x22000) + 0x48) }))
2525#define GEN6_VEBSYNC(((const i915_reg_t){ .reg = ((0x1a000) + 0x40) })) (RING_SYNC_0(VEBOX_RING_BASE)((const i915_reg_t){ .reg = ((0x1a000) + 0x40) }))
2526#define GEN6_VERSYNC(((const i915_reg_t){ .reg = ((0x1a000) + 0x44) })) (RING_SYNC_1(VEBOX_RING_BASE)((const i915_reg_t){ .reg = ((0x1a000) + 0x44) }))
2527#define GEN6_VEVSYNC(((const i915_reg_t){ .reg = ((0x1a000) + 0x48) })) (RING_SYNC_2(VEBOX_RING_BASE)((const i915_reg_t){ .reg = ((0x1a000) + 0x48) }))
2528#define GEN6_NOSYNC((const i915_reg_t){ .reg = (0) }) INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) })
2529#define RING_PSMI_CTL(base)((const i915_reg_t){ .reg = ((base) + 0x50) }) _MMIO((base) + 0x50)((const i915_reg_t){ .reg = ((base) + 0x50) })
2530#define RING_MAX_IDLE(base)((const i915_reg_t){ .reg = ((base) + 0x54) }) _MMIO((base) + 0x54)((const i915_reg_t){ .reg = ((base) + 0x54) })
2531#define RING_HWS_PGA(base)((const i915_reg_t){ .reg = ((base) + 0x80) }) _MMIO((base) + 0x80)((const i915_reg_t){ .reg = ((base) + 0x80) })
2532#define RING_HWS_PGA_GEN6(base)((const i915_reg_t){ .reg = ((base) + 0x2080) }) _MMIO((base) + 0x2080)((const i915_reg_t){ .reg = ((base) + 0x2080) })
2533#define RING_RESET_CTL(base)((const i915_reg_t){ .reg = ((base) + 0xd0) }) _MMIO((base) + 0xd0)((const i915_reg_t){ .reg = ((base) + 0xd0) })
2534#define RESET_CTL_CAT_ERROR((u32)((1UL << (2)) + 0)) REG_BIT(2)((u32)((1UL << (2)) + 0))
2535#define RESET_CTL_READY_TO_RESET((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
2536#define RESET_CTL_REQUEST_RESET((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
2537
2538#define RING_SEMA_WAIT_POLL(base)((const i915_reg_t){ .reg = ((base) + 0x24c) }) _MMIO((base) + 0x24c)((const i915_reg_t){ .reg = ((base) + 0x24c) })
2539
2540#define HSW_GTT_CACHE_EN((const i915_reg_t){ .reg = (0x4024) }) _MMIO(0x4024)((const i915_reg_t){ .reg = (0x4024) })
2541#define GTT_CACHE_EN_ALL0xF0007FFF 0xF0007FFF
2542#define GEN7_WR_WATERMARK((const i915_reg_t){ .reg = (0x4028) }) _MMIO(0x4028)((const i915_reg_t){ .reg = (0x4028) })
2543#define GEN7_GFX_PRIO_CTRL((const i915_reg_t){ .reg = (0x402C) }) _MMIO(0x402C)((const i915_reg_t){ .reg = (0x402C) })
2544#define ARB_MODE((const i915_reg_t){ .reg = (0x4030) }) _MMIO(0x4030)((const i915_reg_t){ .reg = (0x4030) })
2545#define ARB_MODE_SWIZZLE_SNB(1 << 4) (1 << 4)
2546#define ARB_MODE_SWIZZLE_IVB(1 << 5) (1 << 5)
2547#define GEN7_GFX_PEND_TLB0((const i915_reg_t){ .reg = (0x4034) }) _MMIO(0x4034)((const i915_reg_t){ .reg = (0x4034) })
2548#define GEN7_GFX_PEND_TLB1((const i915_reg_t){ .reg = (0x4038) }) _MMIO(0x4038)((const i915_reg_t){ .reg = (0x4038) })
2549/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2550#define GEN7_LRA_LIMITS(i)((const i915_reg_t){ .reg = (0x403C + (i) * 4) }) _MMIO(0x403C + (i) * 4)((const i915_reg_t){ .reg = (0x403C + (i) * 4) })
2551#define GEN7_LRA_LIMITS_REG_NUM13 13
2552#define GEN7_MEDIA_MAX_REQ_COUNT((const i915_reg_t){ .reg = (0x4070) }) _MMIO(0x4070)((const i915_reg_t){ .reg = (0x4070) })
2553#define GEN7_GFX_MAX_REQ_COUNT((const i915_reg_t){ .reg = (0x4074) }) _MMIO(0x4074)((const i915_reg_t){ .reg = (0x4074) })
2554
2555#define GAMTARBMODE((const i915_reg_t){ .reg = (0x04a08) }) _MMIO(0x04a08)((const i915_reg_t){ .reg = (0x04a08) })
2556#define ARB_MODE_BWGTLB_DISABLE(1 << 9) (1 << 9)
2557#define ARB_MODE_SWIZZLE_BDW(1 << 1) (1 << 1)
2558#define RENDER_HWS_PGA_GEN7((const i915_reg_t){ .reg = (0x04080) }) _MMIO(0x04080)((const i915_reg_t){ .reg = (0x04080) })
2559#define RING_FAULT_REG(engine)((const i915_reg_t){ .reg = (0x4094 + 0x100 * (engine)->hw_id
) }) _MMIO(0x4094 + 0x100 * (engine)->hw_id)((const i915_reg_t){ .reg = (0x4094 + 0x100 * (engine)->hw_id
) })
2560#define GEN8_RING_FAULT_REG((const i915_reg_t){ .reg = (0x4094) }) _MMIO(0x4094)((const i915_reg_t){ .reg = (0x4094) })
2561#define GEN12_RING_FAULT_REG((const i915_reg_t){ .reg = (0xcec4) }) _MMIO(0xcec4)((const i915_reg_t){ .reg = (0xcec4) })
2562#define GEN8_RING_FAULT_ENGINE_ID(x)(((x) >> 12) & 0x7) (((x) >> 12) & 0x7)
2563#define RING_FAULT_GTTSEL_MASK(1 << 11) (1 << 11)
2564#define RING_FAULT_SRCID(x)(((x) >> 3) & 0xff) (((x) >> 3) & 0xff)
2565#define RING_FAULT_FAULT_TYPE(x)(((x) >> 1) & 0x3) (((x) >> 1) & 0x3)
2566#define RING_FAULT_VALID(1 << 0) (1 << 0)
2567#define DONE_REG((const i915_reg_t){ .reg = (0x40b0) }) _MMIO(0x40b0)((const i915_reg_t){ .reg = (0x40b0) })
2568#define GEN12_GAM_DONE((const i915_reg_t){ .reg = (0xcf68) }) _MMIO(0xcf68)((const i915_reg_t){ .reg = (0xcf68) })
2569#define GEN8_PRIVATE_PAT_LO((const i915_reg_t){ .reg = (0x40e0) }) _MMIO(0x40e0)((const i915_reg_t){ .reg = (0x40e0) })
2570#define GEN8_PRIVATE_PAT_HI((const i915_reg_t){ .reg = (0x40e0 + 4) }) _MMIO(0x40e0 + 4)((const i915_reg_t){ .reg = (0x40e0 + 4) })
2571#define GEN10_PAT_INDEX(index)((const i915_reg_t){ .reg = (0x40e0 + (index) * 4) }) _MMIO(0x40e0 + (index) * 4)((const i915_reg_t){ .reg = (0x40e0 + (index) * 4) })
2572#define GEN12_PAT_INDEX(index)((const i915_reg_t){ .reg = (0x4800 + (index) * 4) }) _MMIO(0x4800 + (index) * 4)((const i915_reg_t){ .reg = (0x4800 + (index) * 4) })
2573#define BSD_HWS_PGA_GEN7((const i915_reg_t){ .reg = (0x04180) }) _MMIO(0x04180)((const i915_reg_t){ .reg = (0x04180) })
2574#define GEN12_GFX_CCS_AUX_NV((const i915_reg_t){ .reg = (0x4208) }) _MMIO(0x4208)((const i915_reg_t){ .reg = (0x4208) })
2575#define GEN12_VD0_AUX_NV((const i915_reg_t){ .reg = (0x4218) }) _MMIO(0x4218)((const i915_reg_t){ .reg = (0x4218) })
2576#define GEN12_VD1_AUX_NV((const i915_reg_t){ .reg = (0x4228) }) _MMIO(0x4228)((const i915_reg_t){ .reg = (0x4228) })
2577#define GEN12_VD2_AUX_NV((const i915_reg_t){ .reg = (0x4298) }) _MMIO(0x4298)((const i915_reg_t){ .reg = (0x4298) })
2578#define GEN12_VD3_AUX_NV((const i915_reg_t){ .reg = (0x42A8) }) _MMIO(0x42A8)((const i915_reg_t){ .reg = (0x42A8) })
2579#define GEN12_VE0_AUX_NV((const i915_reg_t){ .reg = (0x4238) }) _MMIO(0x4238)((const i915_reg_t){ .reg = (0x4238) })
2580#define GEN12_VE1_AUX_NV((const i915_reg_t){ .reg = (0x42B8) }) _MMIO(0x42B8)((const i915_reg_t){ .reg = (0x42B8) })
2581#define AUX_INV((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
2582#define BLT_HWS_PGA_GEN7((const i915_reg_t){ .reg = (0x04280) }) _MMIO(0x04280)((const i915_reg_t){ .reg = (0x04280) })
2583#define VEBOX_HWS_PGA_GEN7((const i915_reg_t){ .reg = (0x04380) }) _MMIO(0x04380)((const i915_reg_t){ .reg = (0x04380) })
2584#define RING_ACTHD(base)((const i915_reg_t){ .reg = ((base) + 0x74) }) _MMIO((base) + 0x74)((const i915_reg_t){ .reg = ((base) + 0x74) })
2585#define RING_ACTHD_UDW(base)((const i915_reg_t){ .reg = ((base) + 0x5c) }) _MMIO((base) + 0x5c)((const i915_reg_t){ .reg = ((base) + 0x5c) })
2586#define RING_NOPID(base)((const i915_reg_t){ .reg = ((base) + 0x94) }) _MMIO((base) + 0x94)((const i915_reg_t){ .reg = ((base) + 0x94) })
2587#define RING_IMR(base)((const i915_reg_t){ .reg = ((base) + 0xa8) }) _MMIO((base) + 0xa8)((const i915_reg_t){ .reg = ((base) + 0xa8) })
2588#define RING_HWSTAM(base)((const i915_reg_t){ .reg = ((base) + 0x98) }) _MMIO((base) + 0x98)((const i915_reg_t){ .reg = ((base) + 0x98) })
2589#define RING_TIMESTAMP(base)((const i915_reg_t){ .reg = ((base) + 0x358) }) _MMIO((base) + 0x358)((const i915_reg_t){ .reg = ((base) + 0x358) })
2590#define RING_TIMESTAMP_UDW(base)((const i915_reg_t){ .reg = ((base) + 0x358 + 4) }) _MMIO((base) + 0x358 + 4)((const i915_reg_t){ .reg = ((base) + 0x358 + 4) })
2591#define TAIL_ADDR0x001FFFF8 0x001FFFF8
2592#define HEAD_WRAP_COUNT0xFFE00000 0xFFE00000
2593#define HEAD_WRAP_ONE0x00200000 0x00200000
2594#define HEAD_ADDR0x001FFFFC 0x001FFFFC
2595#define RING_NR_PAGES0x001FF000 0x001FF000
2596#define RING_REPORT_MASK0x00000006 0x00000006
2597#define RING_REPORT_64K0x00000002 0x00000002
2598#define RING_REPORT_128K0x00000004 0x00000004
2599#define RING_NO_REPORT0x00000000 0x00000000
2600#define RING_VALID_MASK0x00000001 0x00000001
2601#define RING_VALID0x00000001 0x00000001
2602#define RING_INVALID0x00000000 0x00000000
2603#define RING_WAIT_I8XX(1 << 0) (1 << 0) /* gen2, PRBx_HEAD */
2604#define RING_WAIT(1 << 11) (1 << 11) /* gen3+, PRBx_CTL */
2605#define RING_WAIT_SEMAPHORE(1 << 10) (1 << 10) /* gen6+ */
2606
2607/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2608#define GEN8_RING_CS_GPR(base, n)((const i915_reg_t){ .reg = ((base) + 0x600 + (n) * 8) }) _MMIO((base) + 0x600 + (n) * 8)((const i915_reg_t){ .reg = ((base) + 0x600 + (n) * 8) })
2609#define GEN8_RING_CS_GPR_UDW(base, n)((const i915_reg_t){ .reg = ((base) + 0x600 + (n) * 8 + 4) }) _MMIO((base) + 0x600 + (n) * 8 + 4)((const i915_reg_t){ .reg = ((base) + 0x600 + (n) * 8 + 4) })
2610
2611#define RING_FORCE_TO_NONPRIV(base, i)((const i915_reg_t){ .reg = (((base) + 0x4D0) + (i) * 4) }) _MMIO(((base) + 0x4D0) + (i) * 4)((const i915_reg_t){ .reg = (((base) + 0x4D0) + (i) * 4) })
2612#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) <<
(2))) + 0)) REG_GENMASK(25, 2)((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) <<
(2))) + 0))
2613#define RING_FORCE_TO_NONPRIV_ACCESS_RW(0 << 28) (0 << 28) /* CFL+ & Gen11+ */
2614#define RING_FORCE_TO_NONPRIV_ACCESS_RD(1 << 28) (1 << 28)
2615#define RING_FORCE_TO_NONPRIV_ACCESS_WR(2 << 28) (2 << 28)
2616#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID(3 << 28) (3 << 28)
2617#define RING_FORCE_TO_NONPRIV_ACCESS_MASK(3 << 28) (3 << 28)
2618#define RING_FORCE_TO_NONPRIV_RANGE_1(0 << 0) (0 << 0) /* CFL+ & Gen11+ */
2619#define RING_FORCE_TO_NONPRIV_RANGE_4(1 << 0) (1 << 0)
2620#define RING_FORCE_TO_NONPRIV_RANGE_16(2 << 0) (2 << 0)
2621#define RING_FORCE_TO_NONPRIV_RANGE_64(3 << 0) (3 << 0)
2622#define RING_FORCE_TO_NONPRIV_RANGE_MASK(3 << 0) (3 << 0)
2623#define RING_FORCE_TO_NONPRIV_MASK_VALID((3 << 0) | (3 << 28)) \
2624 (RING_FORCE_TO_NONPRIV_RANGE_MASK(3 << 0) \
2625 | RING_FORCE_TO_NONPRIV_ACCESS_MASK(3 << 28))
2626#define RING_MAX_NONPRIV_SLOTS12 12
2627
2628#define GEN7_TLB_RD_ADDR((const i915_reg_t){ .reg = (0x4700) }) _MMIO(0x4700)((const i915_reg_t){ .reg = (0x4700) })
2629
2630#define GEN9_GAMT_ECO_REG_RW_IA((const i915_reg_t){ .reg = (0x4ab0) }) _MMIO(0x4ab0)((const i915_reg_t){ .reg = (0x4ab0) })
2631#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS(1 << 18) (1 << 18)
2632
2633#define GEN8_GAMW_ECO_DEV_RW_IA((const i915_reg_t){ .reg = (0x4080) }) _MMIO(0x4080)((const i915_reg_t){ .reg = (0x4080) })
2634#define GAMW_ECO_ENABLE_64K_IPS_FIELD0xF 0xF
2635#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE(1 << 7) (1 << 7)
2636
2637#define GAMT_CHKN_BIT_REG((const i915_reg_t){ .reg = (0x4ab8) }) _MMIO(0x4ab8)((const i915_reg_t){ .reg = (0x4ab8) })
2638#define GAMT_CHKN_DISABLE_L3_COH_PIPE(1 << 31) (1 << 31)
2639#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING(1 << 28) (1 << 28)
2640#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT(1 << 24) (1 << 24)
2641
2642#if 0
2643#define PRB0_TAIL _MMIO(0x2030)((const i915_reg_t){ .reg = (0x2030) })
2644#define PRB0_HEAD _MMIO(0x2034)((const i915_reg_t){ .reg = (0x2034) })
2645#define PRB0_START _MMIO(0x2038)((const i915_reg_t){ .reg = (0x2038) })
2646#define PRB0_CTL _MMIO(0x203c)((const i915_reg_t){ .reg = (0x203c) })
2647#define PRB1_TAIL _MMIO(0x2040)((const i915_reg_t){ .reg = (0x2040) }) /* 915+ only */
2648#define PRB1_HEAD _MMIO(0x2044)((const i915_reg_t){ .reg = (0x2044) }) /* 915+ only */
2649#define PRB1_START _MMIO(0x2048)((const i915_reg_t){ .reg = (0x2048) }) /* 915+ only */
2650#define PRB1_CTL _MMIO(0x204c)((const i915_reg_t){ .reg = (0x204c) }) /* 915+ only */
2651#endif
2652#define IPEIR_I965((const i915_reg_t){ .reg = (0x2064) }) _MMIO(0x2064)((const i915_reg_t){ .reg = (0x2064) })
2653#define IPEHR_I965((const i915_reg_t){ .reg = (0x2068) }) _MMIO(0x2068)((const i915_reg_t){ .reg = (0x2068) })
2654#define GEN7_SC_INSTDONE((const i915_reg_t){ .reg = (0x7100) }) _MMIO(0x7100)((const i915_reg_t){ .reg = (0x7100) })
2655#define GEN12_SC_INSTDONE_EXTRA((const i915_reg_t){ .reg = (0x7104) }) _MMIO(0x7104)((const i915_reg_t){ .reg = (0x7104) })
2656#define GEN12_SC_INSTDONE_EXTRA2((const i915_reg_t){ .reg = (0x7108) }) _MMIO(0x7108)((const i915_reg_t){ .reg = (0x7108) })
2657#define GEN7_SAMPLER_INSTDONE((const i915_reg_t){ .reg = (0xe160) }) _MMIO(0xe160)((const i915_reg_t){ .reg = (0xe160) })
2658#define GEN7_ROW_INSTDONE((const i915_reg_t){ .reg = (0xe164) }) _MMIO(0xe164)((const i915_reg_t){ .reg = (0xe164) })
2659#define GEN8_MCR_SELECTOR((const i915_reg_t){ .reg = (0xfdc) }) _MMIO(0xfdc)((const i915_reg_t){ .reg = (0xfdc) })
2660#define GEN8_MCR_SLICE(slice)(((slice) & 3) << 26) (((slice) & 3) << 26)
2661#define GEN8_MCR_SLICE_MASK(((3) & 3) << 26) GEN8_MCR_SLICE(3)(((3) & 3) << 26)
2662#define GEN8_MCR_SUBSLICE(subslice)(((subslice) & 3) << 24) (((subslice) & 3) << 24)
2663#define GEN8_MCR_SUBSLICE_MASK(((3) & 3) << 24) GEN8_MCR_SUBSLICE(3)(((3) & 3) << 24)
2664#define GEN11_MCR_SLICE(slice)(((slice) & 0xf) << 27) (((slice) & 0xf) << 27)
2665#define GEN11_MCR_SLICE_MASK(((0xf) & 0xf) << 27) GEN11_MCR_SLICE(0xf)(((0xf) & 0xf) << 27)
2666#define GEN11_MCR_SUBSLICE(subslice)(((subslice) & 0x7) << 24) (((subslice) & 0x7) << 24)
2667#define GEN11_MCR_SUBSLICE_MASK(((0x7) & 0x7) << 24) GEN11_MCR_SUBSLICE(0x7)(((0x7) & 0x7) << 24)
2668#define RING_IPEIR(base)((const i915_reg_t){ .reg = ((base) + 0x64) }) _MMIO((base) + 0x64)((const i915_reg_t){ .reg = ((base) + 0x64) })
2669#define RING_IPEHR(base)((const i915_reg_t){ .reg = ((base) + 0x68) }) _MMIO((base) + 0x68)((const i915_reg_t){ .reg = ((base) + 0x68) })
2670#define RING_EIR(base)((const i915_reg_t){ .reg = ((base) + 0xb0) }) _MMIO((base) + 0xb0)((const i915_reg_t){ .reg = ((base) + 0xb0) })
2671#define RING_EMR(base)((const i915_reg_t){ .reg = ((base) + 0xb4) }) _MMIO((base) + 0xb4)((const i915_reg_t){ .reg = ((base) + 0xb4) })
2672#define RING_ESR(base)((const i915_reg_t){ .reg = ((base) + 0xb8) }) _MMIO((base) + 0xb8)((const i915_reg_t){ .reg = ((base) + 0xb8) })
2673/*
2674 * On GEN4, only the render ring INSTDONE exists and has a different
2675 * layout than the GEN7+ version.
2676 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2677 */
2678#define RING_INSTDONE(base)((const i915_reg_t){ .reg = ((base) + 0x6c) }) _MMIO((base) + 0x6c)((const i915_reg_t){ .reg = ((base) + 0x6c) })
2679#define RING_INSTPS(base)((const i915_reg_t){ .reg = ((base) + 0x70) }) _MMIO((base) + 0x70)((const i915_reg_t){ .reg = ((base) + 0x70) })
2680#define RING_DMA_FADD(base)((const i915_reg_t){ .reg = ((base) + 0x78) }) _MMIO((base) + 0x78)((const i915_reg_t){ .reg = ((base) + 0x78) })
2681#define RING_DMA_FADD_UDW(base)((const i915_reg_t){ .reg = ((base) + 0x60) }) _MMIO((base) + 0x60)((const i915_reg_t){ .reg = ((base) + 0x60) }) /* gen8+ */
2682#define RING_INSTPM(base)((const i915_reg_t){ .reg = ((base) + 0xc0) }) _MMIO((base) + 0xc0)((const i915_reg_t){ .reg = ((base) + 0xc0) })
2683#define RING_MI_MODE(base)((const i915_reg_t){ .reg = ((base) + 0x9c) }) _MMIO((base) + 0x9c)((const i915_reg_t){ .reg = ((base) + 0x9c) })
2684#define RING_CMD_BUF_CCTL(base)((const i915_reg_t){ .reg = ((base) + 0x84) }) _MMIO((base) + 0x84)((const i915_reg_t){ .reg = ((base) + 0x84) })
2685#define INSTPS((const i915_reg_t){ .reg = (0x2070) }) _MMIO(0x2070)((const i915_reg_t){ .reg = (0x2070) }) /* 965+ only */
2686#define GEN4_INSTDONE1((const i915_reg_t){ .reg = (0x207c) }) _MMIO(0x207c)((const i915_reg_t){ .reg = (0x207c) }) /* 965+ only, aka INSTDONE_2 on SNB */
2687#define ACTHD_I965((const i915_reg_t){ .reg = (0x2074) }) _MMIO(0x2074)((const i915_reg_t){ .reg = (0x2074) })
2688#define HWS_PGA((const i915_reg_t){ .reg = (0x2080) }) _MMIO(0x2080)((const i915_reg_t){ .reg = (0x2080) })
2689#define HWS_ADDRESS_MASK0xfffff000 0xfffff000
2690#define HWS_START_ADDRESS_SHIFT4 4
2691#define PWRCTXA((const i915_reg_t){ .reg = (0x2088) }) _MMIO(0x2088)((const i915_reg_t){ .reg = (0x2088) }) /* 965GM+ only */
2692#define PWRCTX_EN(1 << 0) (1 << 0)
2693#define IPEIR(base)((const i915_reg_t){ .reg = ((base) + 0x88) }) _MMIO((base) + 0x88)((const i915_reg_t){ .reg = ((base) + 0x88) })
2694#define IPEHR(base)((const i915_reg_t){ .reg = ((base) + 0x8c) }) _MMIO((base) + 0x8c)((const i915_reg_t){ .reg = ((base) + 0x8c) })
2695#define GEN2_INSTDONE((const i915_reg_t){ .reg = (0x2090) }) _MMIO(0x2090)((const i915_reg_t){ .reg = (0x2090) })
2696#define NOPID((const i915_reg_t){ .reg = (0x2094) }) _MMIO(0x2094)((const i915_reg_t){ .reg = (0x2094) })
2697#define HWSTAM((const i915_reg_t){ .reg = (0x2098) }) _MMIO(0x2098)((const i915_reg_t){ .reg = (0x2098) })
2698#define DMA_FADD_I8XX(base)((const i915_reg_t){ .reg = ((base) + 0xd0) }) _MMIO((base) + 0xd0)((const i915_reg_t){ .reg = ((base) + 0xd0) })
2699#define RING_BBSTATE(base)((const i915_reg_t){ .reg = ((base) + 0x110) }) _MMIO((base) + 0x110)((const i915_reg_t){ .reg = ((base) + 0x110) })
2700#define RING_BB_PPGTT(1 << 5) (1 << 5)
2701#define RING_SBBADDR(base)((const i915_reg_t){ .reg = ((base) + 0x114) }) _MMIO((base) + 0x114)((const i915_reg_t){ .reg = ((base) + 0x114) }) /* hsw+ */
2702#define RING_SBBSTATE(base)((const i915_reg_t){ .reg = ((base) + 0x118) }) _MMIO((base) + 0x118)((const i915_reg_t){ .reg = ((base) + 0x118) }) /* hsw+ */
2703#define RING_SBBADDR_UDW(base)((const i915_reg_t){ .reg = ((base) + 0x11c) }) _MMIO((base) + 0x11c)((const i915_reg_t){ .reg = ((base) + 0x11c) }) /* gen8+ */
2704#define RING_BBADDR(base)((const i915_reg_t){ .reg = ((base) + 0x140) }) _MMIO((base) + 0x140)((const i915_reg_t){ .reg = ((base) + 0x140) })
2705#define RING_BBADDR_UDW(base)((const i915_reg_t){ .reg = ((base) + 0x168) }) _MMIO((base) + 0x168)((const i915_reg_t){ .reg = ((base) + 0x168) }) /* gen8+ */
2706#define RING_BB_PER_CTX_PTR(base)((const i915_reg_t){ .reg = ((base) + 0x1c0) }) _MMIO((base) + 0x1c0)((const i915_reg_t){ .reg = ((base) + 0x1c0) }) /* gen8+ */
2707#define RING_INDIRECT_CTX(base)((const i915_reg_t){ .reg = ((base) + 0x1c4) }) _MMIO((base) + 0x1c4)((const i915_reg_t){ .reg = ((base) + 0x1c4) }) /* gen8+ */
2708#define RING_INDIRECT_CTX_OFFSET(base)((const i915_reg_t){ .reg = ((base) + 0x1c8) }) _MMIO((base) + 0x1c8)((const i915_reg_t){ .reg = ((base) + 0x1c8) }) /* gen8+ */
2709#define RING_CTX_TIMESTAMP(base)((const i915_reg_t){ .reg = ((base) + 0x3a8) }) _MMIO((base) + 0x3a8)((const i915_reg_t){ .reg = ((base) + 0x3a8) }) /* gen8+ */
2710
2711#define ERROR_GEN6((const i915_reg_t){ .reg = (0x40a0) }) _MMIO(0x40a0)((const i915_reg_t){ .reg = (0x40a0) })
2712#define GEN7_ERR_INT((const i915_reg_t){ .reg = (0x44040) }) _MMIO(0x44040)((const i915_reg_t){ .reg = (0x44040) })
2713#define ERR_INT_POISON(1 << 31) (1 << 31)
2714#define ERR_INT_MMIO_UNCLAIMED(1 << 13) (1 << 13)
2715#define ERR_INT_PIPE_CRC_DONE_C(1 << 8) (1 << 8)
2716#define ERR_INT_FIFO_UNDERRUN_C(1 << 6) (1 << 6)
2717#define ERR_INT_PIPE_CRC_DONE_B(1 << 5) (1 << 5)
2718#define ERR_INT_FIFO_UNDERRUN_B(1 << 3) (1 << 3)
2719#define ERR_INT_PIPE_CRC_DONE_A(1 << 2) (1 << 2)
2720#define ERR_INT_PIPE_CRC_DONE(pipe)(1 << (2 + (pipe) * 3)) (1 << (2 + (pipe) * 3))
2721#define ERR_INT_FIFO_UNDERRUN_A(1 << 0) (1 << 0)
2722#define ERR_INT_FIFO_UNDERRUN(pipe)(1 << ((pipe) * 3)) (1 << ((pipe) * 3))
2723
2724#define GEN8_FAULT_TLB_DATA0((const i915_reg_t){ .reg = (0x4b10) }) _MMIO(0x4b10)((const i915_reg_t){ .reg = (0x4b10) })
2725#define GEN8_FAULT_TLB_DATA1((const i915_reg_t){ .reg = (0x4b14) }) _MMIO(0x4b14)((const i915_reg_t){ .reg = (0x4b14) })
2726#define GEN12_FAULT_TLB_DATA0((const i915_reg_t){ .reg = (0xceb8) }) _MMIO(0xceb8)((const i915_reg_t){ .reg = (0xceb8) })
2727#define GEN12_FAULT_TLB_DATA1((const i915_reg_t){ .reg = (0xcebc) }) _MMIO(0xcebc)((const i915_reg_t){ .reg = (0xcebc) })
2728#define FAULT_VA_HIGH_BITS(0xf << 0) (0xf << 0)
2729#define FAULT_GTT_SEL(1 << 4) (1 << 4)
2730
2731#define GEN12_AUX_ERR_DBG((const i915_reg_t){ .reg = (0x43f4) }) _MMIO(0x43f4)((const i915_reg_t){ .reg = (0x43f4) })
2732
2733#define FPGA_DBG((const i915_reg_t){ .reg = (0x42300) }) _MMIO(0x42300)((const i915_reg_t){ .reg = (0x42300) })
2734#define FPGA_DBG_RM_NOCLAIM(1 << 31) (1 << 31)
2735
2736#define CLAIM_ER((const i915_reg_t){ .reg = (0x180000 + 0x2028) }) _MMIO(VLV_DISPLAY_BASE + 0x2028)((const i915_reg_t){ .reg = (0x180000 + 0x2028) })
2737#define CLAIM_ER_CLR(1 << 31) (1 << 31)
2738#define CLAIM_ER_OVERFLOW(1 << 16) (1 << 16)
2739#define CLAIM_ER_CTR_MASK0xffff 0xffff
2740
2741#define DERRMR((const i915_reg_t){ .reg = (0x44050) }) _MMIO(0x44050)((const i915_reg_t){ .reg = (0x44050) })
2742/* Note that HBLANK events are reserved on bdw+ */
2743#define DERRMR_PIPEA_SCANLINE(1 << 0) (1 << 0)
2744#define DERRMR_PIPEA_PRI_FLIP_DONE(1 << 1) (1 << 1)
2745#define DERRMR_PIPEA_SPR_FLIP_DONE(1 << 2) (1 << 2)
2746#define DERRMR_PIPEA_VBLANK(1 << 3) (1 << 3)
2747#define DERRMR_PIPEA_HBLANK(1 << 5) (1 << 5)
2748#define DERRMR_PIPEB_SCANLINE(1 << 8) (1 << 8)
2749#define DERRMR_PIPEB_PRI_FLIP_DONE(1 << 9) (1 << 9)
2750#define DERRMR_PIPEB_SPR_FLIP_DONE(1 << 10) (1 << 10)
2751#define DERRMR_PIPEB_VBLANK(1 << 11) (1 << 11)
2752#define DERRMR_PIPEB_HBLANK(1 << 13) (1 << 13)
2753/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2754#define DERRMR_PIPEC_SCANLINE(1 << 14) (1 << 14)
2755#define DERRMR_PIPEC_PRI_FLIP_DONE(1 << 15) (1 << 15)
2756#define DERRMR_PIPEC_SPR_FLIP_DONE(1 << 20) (1 << 20)
2757#define DERRMR_PIPEC_VBLANK(1 << 21) (1 << 21)
2758#define DERRMR_PIPEC_HBLANK(1 << 22) (1 << 22)
2759
2760
2761/* GM45+ chicken bits -- debug workaround bits that may be required
2762 * for various sorts of correct behavior. The top 16 bits of each are
2763 * the enables for writing to the corresponding low bit.
2764 */
2765#define _3D_CHICKEN((const i915_reg_t){ .reg = (0x2084) }) _MMIO(0x2084)((const i915_reg_t){ .reg = (0x2084) })
2766#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB(1 << 10) (1 << 10)
2767#define _3D_CHICKEN2((const i915_reg_t){ .reg = (0x208c) }) _MMIO(0x208c)((const i915_reg_t){ .reg = (0x208c) })
2768
2769#define FF_SLICE_CHICKEN((const i915_reg_t){ .reg = (0x2088) }) _MMIO(0x2088)((const i915_reg_t){ .reg = (0x2088) })
2770#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX(1 << 1) (1 << 1)
2771
2772/* Disables pipelining of read flushes past the SF-WIZ interface.
2773 * Required on all Ironlake steppings according to the B-Spec, but the
2774 * particular danger of not doing so is not specified.
2775 */
2776# define _3D_CHICKEN2_WM_READ_PIPELINED(1 << 14) (1 << 14)
2777#define _3D_CHICKEN3((const i915_reg_t){ .reg = (0x2090) }) _MMIO(0x2090)((const i915_reg_t){ .reg = (0x2090) })
2778#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX(1 << 12) (1 << 12)
2779#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL(1 << 10) (1 << 10)
2780#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE(1 << 5) (1 << 5)
2781#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL(1 << 5) (1 << 5)
2782#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)((x) << 1) ((x) << 1) /* gen8+ */
2783#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH(1 << 1) (1 << 1) /* gen6 */
2784
2785#define MI_MODE((const i915_reg_t){ .reg = (0x209c) }) _MMIO(0x209c)((const i915_reg_t){ .reg = (0x209c) })
2786# define VS_TIMER_DISPATCH(1 << 6) (1 << 6)
2787# define MI_FLUSH_ENABLE(1 << 12) (1 << 12)
2788# define ASYNC_FLIP_PERF_DISABLE(1 << 14) (1 << 14)
2789# define MODE_IDLE(1 << 9) (1 << 9)
2790# define STOP_RING(1 << 8) (1 << 8)
2791
2792#define GEN6_GT_MODE((const i915_reg_t){ .reg = (0x20d0) }) _MMIO(0x20d0)((const i915_reg_t){ .reg = (0x20d0) })
2793#define GEN7_GT_MODE((const i915_reg_t){ .reg = (0x7008) }) _MMIO(0x7008)((const i915_reg_t){ .reg = (0x7008) })
2794#define GEN6_WIZ_HASHING(hi, lo)(((hi) << 9) | ((lo) << 7)) (((hi) << 9) | ((lo) << 7))
2795#define GEN6_WIZ_HASHING_8x8(((0) << 9) | ((0) << 7)) GEN6_WIZ_HASHING(0, 0)(((0) << 9) | ((0) << 7))
2796#define GEN6_WIZ_HASHING_8x4(((0) << 9) | ((1) << 7)) GEN6_WIZ_HASHING(0, 1)(((0) << 9) | ((1) << 7))
2797#define GEN6_WIZ_HASHING_16x4(((1) << 9) | ((0) << 7)) GEN6_WIZ_HASHING(1, 0)(((1) << 9) | ((0) << 7))
2798#define GEN6_WIZ_HASHING_MASK(((1) << 9) | ((1) << 7)) GEN6_WIZ_HASHING(1, 1)(((1) << 9) | ((1) << 7))
2799#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE(1 << 5) (1 << 5)
2800#define GEN9_IZ_HASHING_MASK(slice)(0x3 << ((slice) * 2)) (0x3 << ((slice) * 2))
2801#define GEN9_IZ_HASHING(slice, val)((val) << ((slice) * 2)) ((val) << ((slice) * 2))
2802
2803/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2804#define GEN9_CSFE_CHICKEN1_RCS((const i915_reg_t){ .reg = (0x20D4) }) _MMIO(0x20D4)((const i915_reg_t){ .reg = (0x20D4) })
2805#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE(1 << 2) (1 << 2)
2806#define GEN11_ENABLE_32_PLANE_MODE(1 << 7) (1 << 7)
2807
2808/* WaClearTdlStateAckDirtyBits */
2809#define GEN8_STATE_ACK((const i915_reg_t){ .reg = (0x20F0) }) _MMIO(0x20F0)((const i915_reg_t){ .reg = (0x20F0) })
2810#define GEN9_STATE_ACK_SLICE1((const i915_reg_t){ .reg = (0x20F8) }) _MMIO(0x20F8)((const i915_reg_t){ .reg = (0x20F8) })
2811#define GEN9_STATE_ACK_SLICE2((const i915_reg_t){ .reg = (0x2100) }) _MMIO(0x2100)((const i915_reg_t){ .reg = (0x2100) })
2812#define GEN9_STATE_ACK_TDL0(1 << 12) (1 << 12)
2813#define GEN9_STATE_ACK_TDL1(1 << 13) (1 << 13)
2814#define GEN9_STATE_ACK_TDL2(1 << 14) (1 << 14)
2815#define GEN9_STATE_ACK_TDL3(1 << 15) (1 << 15)
2816#define GEN9_SUBSLICE_TDL_ACK_BITS((1 << 15) | (1 << 14) | (1 << 13) | (1 <<
12)) \
2817 (GEN9_STATE_ACK_TDL3(1 << 15) | GEN9_STATE_ACK_TDL2(1 << 14) | \
2818 GEN9_STATE_ACK_TDL1(1 << 13) | GEN9_STATE_ACK_TDL0(1 << 12))
2819
2820#define GFX_MODE((const i915_reg_t){ .reg = (0x2520) }) _MMIO(0x2520)((const i915_reg_t){ .reg = (0x2520) })
2821#define GFX_MODE_GEN7((const i915_reg_t){ .reg = (0x229c) }) _MMIO(0x229c)((const i915_reg_t){ .reg = (0x229c) })
2822#define RING_MODE_GEN7(base)((const i915_reg_t){ .reg = ((base) + 0x29c) }) _MMIO((base) + 0x29c)((const i915_reg_t){ .reg = ((base) + 0x29c) })
2823#define GFX_RUN_LIST_ENABLE(1 << 15) (1 << 15)
2824#define GFX_INTERRUPT_STEERING(1 << 14) (1 << 14)
2825#define GFX_TLB_INVALIDATE_EXPLICIT(1 << 13) (1 << 13)
2826#define GFX_SURFACE_FAULT_ENABLE(1 << 12) (1 << 12)
2827#define GFX_REPLAY_MODE(1 << 11) (1 << 11)
2828#define GFX_PSMI_GRANULARITY(1 << 10) (1 << 10)
2829#define GFX_PPGTT_ENABLE(1 << 9) (1 << 9)
2830#define GEN8_GFX_PPGTT_48B(1 << 7) (1 << 7)
2831
2832#define GFX_FORWARD_VBLANK_MASK(3 << 5) (3 << 5)
2833#define GFX_FORWARD_VBLANK_NEVER(0 << 5) (0 << 5)
2834#define GFX_FORWARD_VBLANK_ALWAYS(1 << 5) (1 << 5)
2835#define GFX_FORWARD_VBLANK_COND(2 << 5) (2 << 5)
2836
2837#define GEN11_GFX_DISABLE_LEGACY_MODE(1 << 3) (1 << 3)
2838
2839#define VLV_GU_CTL0((const i915_reg_t){ .reg = (0x180000 + 0x2030) }) _MMIO(VLV_DISPLAY_BASE + 0x2030)((const i915_reg_t){ .reg = (0x180000 + 0x2030) })
2840#define VLV_GU_CTL1((const i915_reg_t){ .reg = (0x180000 + 0x2034) }) _MMIO(VLV_DISPLAY_BASE + 0x2034)((const i915_reg_t){ .reg = (0x180000 + 0x2034) })
2841#define SCPD0((const i915_reg_t){ .reg = (0x209c) }) _MMIO(0x209c)((const i915_reg_t){ .reg = (0x209c) }) /* 915+ only */
2842#define SCPD_FBC_IGNORE_3D(1 << 6) (1 << 6)
2843#define CSTATE_RENDER_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
2844#define GEN2_IER((const i915_reg_t){ .reg = (0x20a0) }) _MMIO(0x20a0)((const i915_reg_t){ .reg = (0x20a0) })
2845#define GEN2_IIR((const i915_reg_t){ .reg = (0x20a4) }) _MMIO(0x20a4)((const i915_reg_t){ .reg = (0x20a4) })
2846#define GEN2_IMR((const i915_reg_t){ .reg = (0x20a8) }) _MMIO(0x20a8)((const i915_reg_t){ .reg = (0x20a8) })
2847#define GEN2_ISR((const i915_reg_t){ .reg = (0x20ac) }) _MMIO(0x20ac)((const i915_reg_t){ .reg = (0x20ac) })
2848#define VLV_GUNIT_CLOCK_GATE((const i915_reg_t){ .reg = (0x180000 + 0x2060) }) _MMIO(VLV_DISPLAY_BASE + 0x2060)((const i915_reg_t){ .reg = (0x180000 + 0x2060) })
2849#define GINT_DIS(1 << 22) (1 << 22)
2850#define GCFG_DIS(1 << 8) (1 << 8)
2851#define VLV_GUNIT_CLOCK_GATE2((const i915_reg_t){ .reg = (0x180000 + 0x2064) }) _MMIO(VLV_DISPLAY_BASE + 0x2064)((const i915_reg_t){ .reg = (0x180000 + 0x2064) })
2852#define VLV_IIR_RW((const i915_reg_t){ .reg = (0x180000 + 0x2084) }) _MMIO(VLV_DISPLAY_BASE + 0x2084)((const i915_reg_t){ .reg = (0x180000 + 0x2084) })
2853#define VLV_IER((const i915_reg_t){ .reg = (0x180000 + 0x20a0) }) _MMIO(VLV_DISPLAY_BASE + 0x20a0)((const i915_reg_t){ .reg = (0x180000 + 0x20a0) })
2854#define VLV_IIR((const i915_reg_t){ .reg = (0x180000 + 0x20a4) }) _MMIO(VLV_DISPLAY_BASE + 0x20a4)((const i915_reg_t){ .reg = (0x180000 + 0x20a4) })
2855#define VLV_IMR((const i915_reg_t){ .reg = (0x180000 + 0x20a8) }) _MMIO(VLV_DISPLAY_BASE + 0x20a8)((const i915_reg_t){ .reg = (0x180000 + 0x20a8) })
2856#define VLV_ISR((const i915_reg_t){ .reg = (0x180000 + 0x20ac) }) _MMIO(VLV_DISPLAY_BASE + 0x20ac)((const i915_reg_t){ .reg = (0x180000 + 0x20ac) })
2857#define VLV_PCBR((const i915_reg_t){ .reg = (0x180000 + 0x2120) }) _MMIO(VLV_DISPLAY_BASE + 0x2120)((const i915_reg_t){ .reg = (0x180000 + 0x2120) })
2858#define VLV_PCBR_ADDR_SHIFT12 12
2859
2860#define DISPLAY_PLANE_FLIP_PENDING(plane)(1 << (11 - (plane))) (1 << (11 - (plane))) /* A and B only */
2861#define EIR((const i915_reg_t){ .reg = (0x20b0) }) _MMIO(0x20b0)((const i915_reg_t){ .reg = (0x20b0) })
2862#define EMR((const i915_reg_t){ .reg = (0x20b4) }) _MMIO(0x20b4)((const i915_reg_t){ .reg = (0x20b4) })
2863#define ESR((const i915_reg_t){ .reg = (0x20b8) }) _MMIO(0x20b8)((const i915_reg_t){ .reg = (0x20b8) })
2864#define GM45_ERROR_PAGE_TABLE(1 << 5) (1 << 5)
2865#define GM45_ERROR_MEM_PRIV(1 << 4) (1 << 4)
2866#define I915_ERROR_PAGE_TABLE(1 << 4) (1 << 4)
2867#define GM45_ERROR_CP_PRIV(1 << 3) (1 << 3)
2868#define I915_ERROR_MEMORY_REFRESH(1 << 1) (1 << 1)
2869#define I915_ERROR_INSTRUCTION(1 << 0) (1 << 0)
2870#define INSTPM((const i915_reg_t){ .reg = (0x20c0) }) _MMIO(0x20c0)((const i915_reg_t){ .reg = (0x20c0) })
2871#define INSTPM_SELF_EN(1 << 12) (1 << 12) /* 915GM only */
2872#define INSTPM_AGPBUSY_INT_EN(1 << 11) (1 << 11) /* gen3: when disabled, pending interrupts
2873 will not assert AGPBUSY# and will only
2874 be delivered when out of C3. */
2875#define INSTPM_FORCE_ORDERING(1 << 7) (1 << 7) /* GEN6+ */
2876#define INSTPM_TLB_INVALIDATE(1 << 9) (1 << 9)
2877#define INSTPM_SYNC_FLUSH(1 << 5) (1 << 5)
2878#define ACTHD(base)((const i915_reg_t){ .reg = ((base) + 0xc8) }) _MMIO((base) + 0xc8)((const i915_reg_t){ .reg = ((base) + 0xc8) })
2879#define MEM_MODE((const i915_reg_t){ .reg = (0x20cc) }) _MMIO(0x20cc)((const i915_reg_t){ .reg = (0x20cc) })
2880#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE(1 << 3) (1 << 3) /* 830 only */
2881#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE(1 << 2) (1 << 2) /* 830/845 only */
2882#define MEM_DISPLAY_TRICKLE_FEED_DISABLE(1 << 2) (1 << 2) /* 85x only */
2883#define FW_BLC((const i915_reg_t){ .reg = (0x20d8) }) _MMIO(0x20d8)((const i915_reg_t){ .reg = (0x20d8) })
2884#define FW_BLC2((const i915_reg_t){ .reg = (0x20dc) }) _MMIO(0x20dc)((const i915_reg_t){ .reg = (0x20dc) })
2885#define FW_BLC_SELF((const i915_reg_t){ .reg = (0x20e0) }) _MMIO(0x20e0)((const i915_reg_t){ .reg = (0x20e0) }) /* 915+ only */
2886#define FW_BLC_SELF_EN_MASK(1 << 31) (1 << 31)
2887#define FW_BLC_SELF_FIFO_MASK(1 << 16) (1 << 16) /* 945 only */
2888#define FW_BLC_SELF_EN(1 << 15) (1 << 15) /* 945 only */
2889#define MM_BURST_LENGTH0x00700000 0x00700000
2890#define MM_FIFO_WATERMARK0x0001F000 0x0001F000
2891#define LM_BURST_LENGTH0x00000700 0x00000700
2892#define LM_FIFO_WATERMARK0x0000001F 0x0000001F
2893#define MI_ARB_STATE((const i915_reg_t){ .reg = (0x20e4) }) _MMIO(0x20e4)((const i915_reg_t){ .reg = (0x20e4) }) /* 915+ only */
2894
2895#define _MBUS_ABOX0_CTL0x45038 0x45038
2896#define _MBUS_ABOX1_CTL0x45048 0x45048
2897#define _MBUS_ABOX2_CTL0x4504C 0x4504C
2898#define MBUS_ABOX_CTL(x)((const i915_reg_t){ .reg = ((((const u32 []){ 0x45038, 0x45048
, 0x4504C })[x])) }) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x45038, 0x45048
, 0x4504C })[x])) })
2899 _MBUS_ABOX1_CTL, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x45038, 0x45048
, 0x4504C })[x])) })
2900 _MBUS_ABOX2_CTL))((const i915_reg_t){ .reg = ((((const u32 []){ 0x45038, 0x45048
, 0x4504C })[x])) })
2901#define MBUS_ABOX_BW_CREDIT_MASK(3 << 20) (3 << 20)
2902#define MBUS_ABOX_BW_CREDIT(x)((x) << 20) ((x) << 20)
2903#define MBUS_ABOX_B_CREDIT_MASK(0xF << 16) (0xF << 16)
2904#define MBUS_ABOX_B_CREDIT(x)((x) << 16) ((x) << 16)
2905#define MBUS_ABOX_BT_CREDIT_POOL2_MASK(0x1F << 8) (0x1F << 8)
2906#define MBUS_ABOX_BT_CREDIT_POOL2(x)((x) << 8) ((x) << 8)
2907#define MBUS_ABOX_BT_CREDIT_POOL1_MASK(0x1F << 0) (0x1F << 0)
2908#define MBUS_ABOX_BT_CREDIT_POOL1(x)((x) << 0) ((x) << 0)
2909
2910#define _PIPEA_MBUS_DBOX_CTL0x7003C 0x7003C
2911#define _PIPEB_MBUS_DBOX_CTL0x7103C 0x7103C
2912#define PIPE_MBUS_DBOX_CTL(pipe)((const i915_reg_t){ .reg = (((0x7003C) + (pipe) * ((0x7103C)
- (0x7003C)))) }) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \((const i915_reg_t){ .reg = (((0x7003C) + (pipe) * ((0x7103C)
- (0x7003C)))) })
2913 _PIPEB_MBUS_DBOX_CTL)((const i915_reg_t){ .reg = (((0x7003C) + (pipe) * ((0x7103C)
- (0x7003C)))) })
2914#define MBUS_DBOX_BW_CREDIT_MASK(3 << 14) (3 << 14)
2915#define MBUS_DBOX_BW_CREDIT(x)((x) << 14) ((x) << 14)
2916#define MBUS_DBOX_B_CREDIT_MASK(0x1F << 8) (0x1F << 8)
2917#define MBUS_DBOX_B_CREDIT(x)((x) << 8) ((x) << 8)
2918#define MBUS_DBOX_A_CREDIT_MASK(0xF << 0) (0xF << 0)
2919#define MBUS_DBOX_A_CREDIT(x)((x) << 0) ((x) << 0)
2920
2921#define MBUS_UBOX_CTL((const i915_reg_t){ .reg = (0x4503C) }) _MMIO(0x4503C)((const i915_reg_t){ .reg = (0x4503C) })
2922#define MBUS_BBOX_CTL_S1((const i915_reg_t){ .reg = (0x45040) }) _MMIO(0x45040)((const i915_reg_t){ .reg = (0x45040) })
2923#define MBUS_BBOX_CTL_S2((const i915_reg_t){ .reg = (0x45044) }) _MMIO(0x45044)((const i915_reg_t){ .reg = (0x45044) })
2924
2925#define HDPORT_STATE((const i915_reg_t){ .reg = (0x45050) }) _MMIO(0x45050)((const i915_reg_t){ .reg = (0x45050) })
2926#define HDPORT_DPLL_USED_MASK((u32)((((~0UL) >> (64 - (14) - 1)) & ((~0UL) <<
(12))) + 0)) REG_GENMASK(14, 12)((u32)((((~0UL) >> (64 - (14) - 1)) & ((~0UL) <<
(12))) + 0))
2927#define HDPORT_PHY_USED_DP(phy)((u32)((1UL << (2 * (phy) + 2)) + 0)) REG_BIT(2 * (phy) + 2)((u32)((1UL << (2 * (phy) + 2)) + 0))
2928#define HDPORT_PHY_USED_HDMI(phy)((u32)((1UL << (2 * (phy) + 1)) + 0)) REG_BIT(2 * (phy) + 1)((u32)((1UL << (2 * (phy) + 1)) + 0))
2929#define HDPORT_ENABLED((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
2930
2931/* Make render/texture TLB fetches lower priorty than associated data
2932 * fetches. This is not turned on by default
2933 */
2934#define MI_ARB_RENDER_TLB_LOW_PRIORITY(1 << 15) (1 << 15)
2935
2936/* Isoch request wait on GTT enable (Display A/B/C streams).
2937 * Make isoch requests stall on the TLB update. May cause
2938 * display underruns (test mode only)
2939 */
2940#define MI_ARB_ISOCH_WAIT_GTT(1 << 14) (1 << 14)
2941
2942/* Block grant count for isoch requests when block count is
2943 * set to a finite value.
2944 */
2945#define MI_ARB_BLOCK_GRANT_MASK(3 << 12) (3 << 12)
2946#define MI_ARB_BLOCK_GRANT_8(0 << 12) (0 << 12) /* for 3 display planes */
2947#define MI_ARB_BLOCK_GRANT_4(1 << 12) (1 << 12) /* for 2 display planes */
2948#define MI_ARB_BLOCK_GRANT_2(2 << 12) (2 << 12) /* for 1 display plane */
2949#define MI_ARB_BLOCK_GRANT_0(3 << 12) (3 << 12) /* don't use */
2950
2951/* Enable render writes to complete in C2/C3/C4 power states.
2952 * If this isn't enabled, render writes are prevented in low
2953 * power states. That seems bad to me.
2954 */
2955#define MI_ARB_C3_LP_WRITE_ENABLE(1 << 11) (1 << 11)
2956
2957/* This acknowledges an async flip immediately instead
2958 * of waiting for 2TLB fetches.
2959 */
2960#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE(1 << 10) (1 << 10)
2961
2962/* Enables non-sequential data reads through arbiter
2963 */
2964#define MI_ARB_DUAL_DATA_PHASE_DISABLE(1 << 9) (1 << 9)
2965
2966/* Disable FSB snooping of cacheable write cycles from binner/render
2967 * command stream
2968 */
2969#define MI_ARB_CACHE_SNOOP_DISABLE(1 << 8) (1 << 8)
2970
2971/* Arbiter time slice for non-isoch streams */
2972#define MI_ARB_TIME_SLICE_MASK(7 << 5) (7 << 5)
2973#define MI_ARB_TIME_SLICE_1(0 << 5) (0 << 5)
2974#define MI_ARB_TIME_SLICE_2(1 << 5) (1 << 5)
2975#define MI_ARB_TIME_SLICE_4(2 << 5) (2 << 5)
2976#define MI_ARB_TIME_SLICE_6(3 << 5) (3 << 5)
2977#define MI_ARB_TIME_SLICE_8(4 << 5) (4 << 5)
2978#define MI_ARB_TIME_SLICE_10(5 << 5) (5 << 5)
2979#define MI_ARB_TIME_SLICE_14(6 << 5) (6 << 5)
2980#define MI_ARB_TIME_SLICE_16(7 << 5) (7 << 5)
2981
2982/* Low priority grace period page size */
2983#define MI_ARB_LOW_PRIORITY_GRACE_4KB(0 << 4) (0 << 4) /* default */
2984#define MI_ARB_LOW_PRIORITY_GRACE_8KB(1 << 4) (1 << 4)
2985
2986/* Disable display A/B trickle feed */
2987#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE(1 << 2) (1 << 2)
2988
2989/* Set display plane priority */
2990#define MI_ARB_DISPLAY_PRIORITY_A_B(0 << 0) (0 << 0) /* display A > display B */
2991#define MI_ARB_DISPLAY_PRIORITY_B_A(1 << 0) (1 << 0) /* display B > display A */
2992
2993#define MI_STATE((const i915_reg_t){ .reg = (0x20e4) }) _MMIO(0x20e4)((const i915_reg_t){ .reg = (0x20e4) }) /* gen2 only */
2994#define MI_AGPBUSY_INT_EN(1 << 1) (1 << 1) /* 85x only */
2995#define MI_AGPBUSY_830_MODE(1 << 0) (1 << 0) /* 85x only */
2996
2997#define CACHE_MODE_0((const i915_reg_t){ .reg = (0x2120) }) _MMIO(0x2120)((const i915_reg_t){ .reg = (0x2120) }) /* 915+ only */
2998#define CM0_PIPELINED_RENDER_FLUSH_DISABLE(1 << 8) (1 << 8)
2999#define CM0_IZ_OPT_DISABLE(1 << 6) (1 << 6)
3000#define CM0_ZR_OPT_DISABLE(1 << 5) (1 << 5)
3001#define CM0_STC_EVICT_DISABLE_LRA_SNB(1 << 5) (1 << 5)
3002#define CM0_DEPTH_EVICT_DISABLE(1 << 4) (1 << 4)
3003#define CM0_COLOR_EVICT_DISABLE(1 << 3) (1 << 3)
3004#define CM0_DEPTH_WRITE_DISABLE(1 << 1) (1 << 1)
3005#define CM0_RC_OP_FLUSH_DISABLE(1 << 0) (1 << 0)
3006#define GFX_FLSH_CNTL((const i915_reg_t){ .reg = (0x2170) }) _MMIO(0x2170)((const i915_reg_t){ .reg = (0x2170) }) /* 915+ only */
3007#define GFX_FLSH_CNTL_GEN6((const i915_reg_t){ .reg = (0x101008) }) _MMIO(0x101008)((const i915_reg_t){ .reg = (0x101008) })
3008#define GFX_FLSH_CNTL_EN(1 << 0) (1 << 0)
3009#define ECOSKPD((const i915_reg_t){ .reg = (0x21d0) }) _MMIO(0x21d0)((const i915_reg_t){ .reg = (0x21d0) })
3010#define ECO_CONSTANT_BUFFER_SR_DISABLE((u32)((1UL << (4)) + 0)) REG_BIT(4)((u32)((1UL << (4)) + 0))
3011#define ECO_GATING_CX_ONLY(1 << 3) (1 << 3)
3012#define ECO_FLIP_DONE(1 << 0) (1 << 0)
3013
3014#define CACHE_MODE_0_GEN7((const i915_reg_t){ .reg = (0x7000) }) _MMIO(0x7000)((const i915_reg_t){ .reg = (0x7000) }) /* IVB+ */
3015#define RC_OP_FLUSH_ENABLE(1 << 0) (1 << 0)
3016#define HIZ_RAW_STALL_OPT_DISABLE(1 << 2) (1 << 2)
3017#define CACHE_MODE_1((const i915_reg_t){ .reg = (0x7004) }) _MMIO(0x7004)((const i915_reg_t){ .reg = (0x7004) }) /* IVB+ */
3018#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6) (1 << 6)
3019#define GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6) (1 << 6)
3020#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE(1 << 1) (1 << 1)
3021
3022#define GEN6_BLITTER_ECOSKPD((const i915_reg_t){ .reg = (0x221d0) }) _MMIO(0x221d0)((const i915_reg_t){ .reg = (0x221d0) })
3023#define GEN6_BLITTER_LOCK_SHIFT16 16
3024#define GEN6_BLITTER_FBC_NOTIFY(1 << 3) (1 << 3)
3025
3026#define GEN6_RC_SLEEP_PSMI_CONTROL((const i915_reg_t){ .reg = (0x2050) }) _MMIO(0x2050)((const i915_reg_t){ .reg = (0x2050) })
3027#define GEN6_PSMI_SLEEP_MSG_DISABLE(1 << 0) (1 << 0)
3028#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE((u32)((1UL << (7)) + 0)) REG_BIT(7)((u32)((1UL << (7)) + 0))
3029#define GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12) (1 << 12)
3030#define GEN8_FF_DOP_CLOCK_GATE_DISABLE(1 << 10) (1 << 10)
3031
3032#define GEN6_RCS_PWR_FSM((const i915_reg_t){ .reg = (0x22ac) }) _MMIO(0x22ac)((const i915_reg_t){ .reg = (0x22ac) })
3033#define GEN9_RCS_FE_FSM2((const i915_reg_t){ .reg = (0x22a4) }) _MMIO(0x22a4)((const i915_reg_t){ .reg = (0x22a4) })
3034
3035#define GEN10_CACHE_MODE_SS((const i915_reg_t){ .reg = (0xe420) }) _MMIO(0xe420)((const i915_reg_t){ .reg = (0xe420) })
3036#define FLOAT_BLEND_OPTIMIZATION_ENABLE(1 << 4) (1 << 4)
3037
3038/* Fuse readout registers for GT */
3039#define HSW_PAVP_FUSE1((const i915_reg_t){ .reg = (0x911C) }) _MMIO(0x911C)((const i915_reg_t){ .reg = (0x911C) })
3040#define HSW_F1_EU_DIS_SHIFT16 16
3041#define HSW_F1_EU_DIS_MASK(0x3 << 16) (0x3 << HSW_F1_EU_DIS_SHIFT16)
3042#define HSW_F1_EU_DIS_10EUS0 0
3043#define HSW_F1_EU_DIS_8EUS1 1
3044#define HSW_F1_EU_DIS_6EUS2 2
3045
3046#define CHV_FUSE_GT((const i915_reg_t){ .reg = (0x180000 + 0x2168) }) _MMIO(VLV_DISPLAY_BASE + 0x2168)((const i915_reg_t){ .reg = (0x180000 + 0x2168) })
3047#define CHV_FGT_DISABLE_SS0(1 << 10) (1 << 10)
3048#define CHV_FGT_DISABLE_SS1(1 << 11) (1 << 11)
3049#define CHV_FGT_EU_DIS_SS0_R0_SHIFT16 16
3050#define CHV_FGT_EU_DIS_SS0_R0_MASK(0xf << 16) (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT16)
3051#define CHV_FGT_EU_DIS_SS0_R1_SHIFT20 20
3052#define CHV_FGT_EU_DIS_SS0_R1_MASK(0xf << 20) (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT20)
3053#define CHV_FGT_EU_DIS_SS1_R0_SHIFT24 24
3054#define CHV_FGT_EU_DIS_SS1_R0_MASK(0xf << 24) (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT24)
3055#define CHV_FGT_EU_DIS_SS1_R1_SHIFT28 28
3056#define CHV_FGT_EU_DIS_SS1_R1_MASK(0xf << 28) (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT28)
3057
3058#define GEN8_FUSE2((const i915_reg_t){ .reg = (0x9120) }) _MMIO(0x9120)((const i915_reg_t){ .reg = (0x9120) })
3059#define GEN8_F2_SS_DIS_SHIFT21 21
3060#define GEN8_F2_SS_DIS_MASK(0x7 << 21) (0x7 << GEN8_F2_SS_DIS_SHIFT21)
3061#define GEN8_F2_S_ENA_SHIFT25 25
3062#define GEN8_F2_S_ENA_MASK(0x7 << 25) (0x7 << GEN8_F2_S_ENA_SHIFT25)
3063
3064#define GEN9_F2_SS_DIS_SHIFT20 20
3065#define GEN9_F2_SS_DIS_MASK(0xf << 20) (0xf << GEN9_F2_SS_DIS_SHIFT20)
3066
3067#define GEN10_F2_S_ENA_SHIFT22 22
3068#define GEN10_F2_S_ENA_MASK(0x3f << 22) (0x3f << GEN10_F2_S_ENA_SHIFT22)
3069#define GEN10_F2_SS_DIS_SHIFT18 18
3070#define GEN10_F2_SS_DIS_MASK(0xf << 18) (0xf << GEN10_F2_SS_DIS_SHIFT18)
3071
3072#define GEN10_MIRROR_FUSE3((const i915_reg_t){ .reg = (0x9118) }) _MMIO(0x9118)((const i915_reg_t){ .reg = (0x9118) })
3073#define GEN10_L3BANK_PAIR_COUNT4 4
3074#define GEN10_L3BANK_MASK0x0F 0x0F
3075
3076#define GEN8_EU_DISABLE0((const i915_reg_t){ .reg = (0x9134) }) _MMIO(0x9134)((const i915_reg_t){ .reg = (0x9134) })
3077#define GEN8_EU_DIS0_S0_MASK0xffffff 0xffffff
3078#define GEN8_EU_DIS0_S1_SHIFT24 24
3079#define GEN8_EU_DIS0_S1_MASK(0xff << 24) (0xff << GEN8_EU_DIS0_S1_SHIFT24)
3080
3081#define GEN8_EU_DISABLE1((const i915_reg_t){ .reg = (0x9138) }) _MMIO(0x9138)((const i915_reg_t){ .reg = (0x9138) })
3082#define GEN8_EU_DIS1_S1_MASK0xffff 0xffff
3083#define GEN8_EU_DIS1_S2_SHIFT16 16
3084#define GEN8_EU_DIS1_S2_MASK(0xffff << 16) (0xffff << GEN8_EU_DIS1_S2_SHIFT16)
3085
3086#define GEN8_EU_DISABLE2((const i915_reg_t){ .reg = (0x913c) }) _MMIO(0x913c)((const i915_reg_t){ .reg = (0x913c) })
3087#define GEN8_EU_DIS2_S2_MASK0xff 0xff
3088
3089#define GEN9_EU_DISABLE(slice)((const i915_reg_t){ .reg = (0x9134 + (slice) * 0x4) }) _MMIO(0x9134 + (slice) * 0x4)((const i915_reg_t){ .reg = (0x9134 + (slice) * 0x4) })
3090
3091#define GEN10_EU_DISABLE3((const i915_reg_t){ .reg = (0x9140) }) _MMIO(0x9140)((const i915_reg_t){ .reg = (0x9140) })
3092#define GEN10_EU_DIS_SS_MASK0xff 0xff
3093
3094#define GEN11_GT_VEBOX_VDBOX_DISABLE((const i915_reg_t){ .reg = (0x9140) }) _MMIO(0x9140)((const i915_reg_t){ .reg = (0x9140) })
3095#define GEN11_GT_VDBOX_DISABLE_MASK0xff 0xff
3096#define GEN11_GT_VEBOX_DISABLE_SHIFT16 16
3097#define GEN11_GT_VEBOX_DISABLE_MASK(0x0f << 16) (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT16)
3098
3099#define GEN11_EU_DISABLE((const i915_reg_t){ .reg = (0x9134) }) _MMIO(0x9134)((const i915_reg_t){ .reg = (0x9134) })
3100#define GEN11_EU_DIS_MASK0xFF 0xFF
3101
3102#define GEN11_GT_SLICE_ENABLE((const i915_reg_t){ .reg = (0x9138) }) _MMIO(0x9138)((const i915_reg_t){ .reg = (0x9138) })
3103#define GEN11_GT_S_ENA_MASK0xFF 0xFF
3104
3105#define GEN11_GT_SUBSLICE_DISABLE((const i915_reg_t){ .reg = (0x913C) }) _MMIO(0x913C)((const i915_reg_t){ .reg = (0x913C) })
3106
3107#define GEN12_GT_DSS_ENABLE((const i915_reg_t){ .reg = (0x913C) }) _MMIO(0x913C)((const i915_reg_t){ .reg = (0x913C) })
3108
3109#define GEN6_BSD_SLEEP_PSMI_CONTROL((const i915_reg_t){ .reg = (0x12050) }) _MMIO(0x12050)((const i915_reg_t){ .reg = (0x12050) })
3110#define GEN6_BSD_SLEEP_MSG_DISABLE(1 << 0) (1 << 0)
3111#define GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2) (1 << 2)
3112#define GEN6_BSD_SLEEP_INDICATOR(1 << 3) (1 << 3)
3113#define GEN6_BSD_GO_INDICATOR(1 << 4) (1 << 4)
3114
3115/* On modern GEN architectures interrupt control consists of two sets
3116 * of registers. The first set pertains to the ring generating the
3117 * interrupt. The second control is for the functional block generating the
3118 * interrupt. These are PM, GT, DE, etc.
3119 *
3120 * Luckily *knocks on wood* all the ring interrupt bits match up with the
3121 * GT interrupt bits, so we don't need to duplicate the defines.
3122 *
3123 * These defines should cover us well from SNB->HSW with minor exceptions
3124 * it can also work on ILK.
3125 */
3126#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT(1 << 26) (1 << 26)
3127#define GT_BLT_CS_ERROR_INTERRUPT(1 << 25) (1 << 25)
3128#define GT_BLT_USER_INTERRUPT(1 << 22) (1 << 22)
3129#define GT_BSD_CS_ERROR_INTERRUPT(1 << 15) (1 << 15)
3130#define GT_BSD_USER_INTERRUPT(1 << 12) (1 << 12)
3131#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1(1 << 11) (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3132#define GT_WAIT_SEMAPHORE_INTERRUPT((u32)((1UL << (11)) + 0)) REG_BIT(11)((u32)((1UL << (11)) + 0)) /* bdw+ */
3133#define GT_CONTEXT_SWITCH_INTERRUPT(1 << 8) (1 << 8)
3134#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT(1 << 5) (1 << 5) /* !snb */
3135#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT(1 << 4) (1 << 4)
3136#define GT_CS_MASTER_ERROR_INTERRUPT((u32)((1UL << (3)) + 0)) REG_BIT(3)((u32)((1UL << (3)) + 0))
3137#define GT_RENDER_SYNC_STATUS_INTERRUPT(1 << 2) (1 << 2)
3138#define GT_RENDER_DEBUG_INTERRUPT(1 << 1) (1 << 1)
3139#define GT_RENDER_USER_INTERRUPT(1 << 0) (1 << 0)
3140
3141#define PM_VEBOX_CS_ERROR_INTERRUPT(1 << 12) (1 << 12) /* hsw+ */
3142#define PM_VEBOX_USER_INTERRUPT(1 << 10) (1 << 10) /* hsw+ */
3143
3144#define GT_PARITY_ERROR(dev_priv)((1 << 5) | (IS_PLATFORM(dev_priv, INTEL_HASWELL) ? (1 <<
11) : 0)) \
3145 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT(1 << 5) | \
3146 (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1(1 << 11) : 0))
3147
3148/* These are all the "old" interrupts */
3149#define ILK_BSD_USER_INTERRUPT(1 << 5) (1 << 5)
3150
3151#define I915_PM_INTERRUPT(1 << 31) (1 << 31)
3152#define I915_ISP_INTERRUPT(1 << 22) (1 << 22)
3153#define I915_LPE_PIPE_B_INTERRUPT(1 << 21) (1 << 21)
3154#define I915_LPE_PIPE_A_INTERRUPT(1 << 20) (1 << 20)
3155#define I915_MIPIC_INTERRUPT(1 << 19) (1 << 19)
3156#define I915_MIPIA_INTERRUPT(1 << 18) (1 << 18)
3157#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT(1 << 18) (1 << 18)
3158#define I915_DISPLAY_PORT_INTERRUPT(1 << 17) (1 << 17)
3159#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT(1 << 16) (1 << 16)
3160#define I915_MASTER_ERROR_INTERRUPT(1 << 15) (1 << 15)
3161#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT(1 << 14) (1 << 14)
3162#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT(1 << 14) (1 << 14) /* p-state */
3163#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT(1 << 13) (1 << 13)
3164#define I915_HWB_OOM_INTERRUPT(1 << 13) (1 << 13)
3165#define I915_LPE_PIPE_C_INTERRUPT(1 << 12) (1 << 12)
3166#define I915_SYNC_STATUS_INTERRUPT(1 << 12) (1 << 12)
3167#define I915_MISC_INTERRUPT(1 << 11) (1 << 11)
3168#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT(1 << 11) (1 << 11)
3169#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT(1 << 10) (1 << 10)
3170#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT(1 << 10) (1 << 10)
3171#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT(1 << 9) (1 << 9)
3172#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT(1 << 9) (1 << 9)
3173#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT(1 << 8) (1 << 8)
3174#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT(1 << 8) (1 << 8)
3175#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT(1 << 7) (1 << 7)
3176#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT(1 << 6) (1 << 6)
3177#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT(1 << 5) (1 << 5)
3178#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT(1 << 4) (1 << 4)
3179#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT(1 << 3) (1 << 3)
3180#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT(1 << 2) (1 << 2)
3181#define I915_DEBUG_INTERRUPT(1 << 2) (1 << 2)
3182#define I915_WINVALID_INTERRUPT(1 << 1) (1 << 1)
3183#define I915_USER_INTERRUPT(1 << 1) (1 << 1)
3184#define I915_ASLE_INTERRUPT(1 << 0) (1 << 0)
3185#define I915_BSD_USER_INTERRUPT(1 << 25) (1 << 25)
3186
3187#define I915_HDMI_LPE_AUDIO_BASE(0x180000 + 0x65000) (VLV_DISPLAY_BASE0x180000 + 0x65000)
3188#define I915_HDMI_LPE_AUDIO_SIZE0x1000 0x1000
3189
3190/* DisplayPort Audio w/ LPE */
3191#define VLV_AUD_CHICKEN_BIT_REG((const i915_reg_t){ .reg = (0x180000 + 0x62F38) }) _MMIO(VLV_DISPLAY_BASE + 0x62F38)((const i915_reg_t){ .reg = (0x180000 + 0x62F38) })
3192#define VLV_CHICKEN_BIT_DBG_ENABLE(1 << 0) (1 << 0)
3193
3194#define _VLV_AUD_PORT_EN_B_DBG(0x180000 + 0x62F20) (VLV_DISPLAY_BASE0x180000 + 0x62F20)
3195#define _VLV_AUD_PORT_EN_C_DBG(0x180000 + 0x62F30) (VLV_DISPLAY_BASE0x180000 + 0x62F30)
3196#define _VLV_AUD_PORT_EN_D_DBG(0x180000 + 0x62F34) (VLV_DISPLAY_BASE0x180000 + 0x62F34)
3197#define VLV_AUD_PORT_EN_DBG(port)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x62F20
), (0x180000 + 0x62F30), (0x180000 + 0x62F34) })[(port) - PORT_B
])) }) _MMIO_PORT3((port) - PORT_B, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x62F20
), (0x180000 + 0x62F30), (0x180000 + 0x62F34) })[(port) - PORT_B
])) })
3198 _VLV_AUD_PORT_EN_B_DBG, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x62F20
), (0x180000 + 0x62F30), (0x180000 + 0x62F34) })[(port) - PORT_B
])) })
3199 _VLV_AUD_PORT_EN_C_DBG, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x62F20
), (0x180000 + 0x62F30), (0x180000 + 0x62F34) })[(port) - PORT_B
])) })
3200 _VLV_AUD_PORT_EN_D_DBG)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x62F20
), (0x180000 + 0x62F30), (0x180000 + 0x62F34) })[(port) - PORT_B
])) })
3201#define VLV_AMP_MUTE(1 << 1) (1 << 1)
3202
3203#define GEN6_BSD_RNCID((const i915_reg_t){ .reg = (0x12198) }) _MMIO(0x12198)((const i915_reg_t){ .reg = (0x12198) })
3204
3205#define GEN7_FF_THREAD_MODE((const i915_reg_t){ .reg = (0x20a0) }) _MMIO(0x20a0)((const i915_reg_t){ .reg = (0x20a0) })
3206#define GEN7_FF_SCHED_MASK0x0077070 0x0077070
3207#define GEN8_FF_DS_REF_CNT_FFME(1 << 19) (1 << 19)
3208#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE(1UL << (19)) BIT(19)(1UL << (19))
3209#define GEN7_FF_TS_SCHED_HS1(0x5 << 16) (0x5 << 16)
3210#define GEN7_FF_TS_SCHED_HS0(0x3 << 16) (0x3 << 16)
3211#define GEN7_FF_TS_SCHED_LOAD_BALANCE(0x1 << 16) (0x1 << 16)
3212#define GEN7_FF_TS_SCHED_HW(0x0 << 16) (0x0 << 16) /* Default */
3213#define GEN7_FF_VS_REF_CNT_FFME(1 << 15) (1 << 15)
3214#define GEN7_FF_VS_SCHED_HS1(0x5 << 12) (0x5 << 12)
3215#define GEN7_FF_VS_SCHED_HS0(0x3 << 12) (0x3 << 12)
3216#define GEN7_FF_VS_SCHED_LOAD_BALANCE(0x1 << 12) (0x1 << 12) /* Default */
3217#define GEN7_FF_VS_SCHED_HW(0x0 << 12) (0x0 << 12)
3218#define GEN7_FF_DS_SCHED_HS1(0x5 << 4) (0x5 << 4)
3219#define GEN7_FF_DS_SCHED_HS0(0x3 << 4) (0x3 << 4)
3220#define GEN7_FF_DS_SCHED_LOAD_BALANCE(0x1 << 4) (0x1 << 4) /* Default */
3221#define GEN7_FF_DS_SCHED_HW(0x0 << 4) (0x0 << 4)
3222
3223/*
3224 * Framebuffer compression (915+ only)
3225 */
3226
3227#define FBC_CFB_BASE((const i915_reg_t){ .reg = (0x3200) }) _MMIO(0x3200)((const i915_reg_t){ .reg = (0x3200) }) /* 4k page aligned */
3228#define FBC_LL_BASE((const i915_reg_t){ .reg = (0x3204) }) _MMIO(0x3204)((const i915_reg_t){ .reg = (0x3204) }) /* 4k page aligned */
3229#define FBC_CONTROL((const i915_reg_t){ .reg = (0x3208) }) _MMIO(0x3208)((const i915_reg_t){ .reg = (0x3208) })
3230#define FBC_CTL_EN((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
3231#define FBC_CTL_PERIODIC((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
3232#define FBC_CTL_INTERVAL_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(29, 16)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0))
3233#define FBC_CTL_INTERVAL(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (16))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (16))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
3234#define FBC_CTL_STOP_ON_MOD((u32)((1UL << (15)) + 0)) REG_BIT(15)((u32)((1UL << (15)) + 0))
3235#define FBC_CTL_UNCOMPRESSIBLE((u32)((1UL << (14)) + 0)) REG_BIT(14)((u32)((1UL << (14)) + 0)) /* i915+ */
3236#define FBC_CTL_C3_IDLE((u32)((1UL << (13)) + 0)) REG_BIT(13)((u32)((1UL << (13)) + 0)) /* i945gm */
3237#define FBC_CTL_STRIDE_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(5))) + 0)) REG_GENMASK(12, 5)((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(5))) + 0))
3238#define FBC_CTL_STRIDE(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) &
((~0UL) << (5))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(5))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (12
) - 1)) & ((~0UL) << (5))) + 0)))) + 0 + 0 + 0 + 0)
) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) &
((~0UL) << (5))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(5))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (12
) - 1)) & ((~0UL) << (5))) + 0)))) + 0 + 0 + 0 + 0)
)
3239#define FBC_CTL_FENCENO_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(3, 0)((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))
3240#define FBC_CTL_FENCENO(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
3241#define FBC_COMMAND((const i915_reg_t){ .reg = (0x320c) }) _MMIO(0x320c)((const i915_reg_t){ .reg = (0x320c) })
3242#define FBC_CMD_COMPRESS(1 << 0) (1 << 0)
3243#define FBC_STATUS((const i915_reg_t){ .reg = (0x3210) }) _MMIO(0x3210)((const i915_reg_t){ .reg = (0x3210) })
3244#define FBC_STAT_COMPRESSING(1 << 31) (1 << 31)
3245#define FBC_STAT_COMPRESSED(1 << 30) (1 << 30)
3246#define FBC_STAT_MODIFIED(1 << 29) (1 << 29)
3247#define FBC_STAT_CURRENT_LINE_SHIFT(0) (0)
3248#define FBC_CONTROL2((const i915_reg_t){ .reg = (0x3214) }) _MMIO(0x3214)((const i915_reg_t){ .reg = (0x3214) })
3249#define FBC_CTL_FENCE_DBL(0 << 4) (0 << 4)
3250#define FBC_CTL_IDLE_IMM(0 << 2) (0 << 2)
3251#define FBC_CTL_IDLE_FULL(1 << 2) (1 << 2)
3252#define FBC_CTL_IDLE_LINE(2 << 2) (2 << 2)
3253#define FBC_CTL_IDLE_DEBUG(3 << 2) (3 << 2)
3254#define FBC_CTL_CPU_FENCE(1 << 1) (1 << 1)
3255#define FBC_CTL_PLANE(plane)((plane) << 0) ((plane) << 0)
3256#define FBC_FENCE_OFF((const i915_reg_t){ .reg = (0x3218) }) _MMIO(0x3218)((const i915_reg_t){ .reg = (0x3218) }) /* BSpec typo has 321Bh */
3257#define FBC_TAG(i)((const i915_reg_t){ .reg = (0x3300 + (i) * 4) }) _MMIO(0x3300 + (i) * 4)((const i915_reg_t){ .reg = (0x3300 + (i) * 4) })
3258
3259#define FBC_LL_SIZE(1536) (1536)
3260
3261#define FBC_LLC_READ_CTRL((const i915_reg_t){ .reg = (0x9044) }) _MMIO(0x9044)((const i915_reg_t){ .reg = (0x9044) })
3262#define FBC_LLC_FULLY_OPEN(1 << 30) (1 << 30)
3263
3264/* Framebuffer compression for GM45+ */
3265#define DPFC_CB_BASE((const i915_reg_t){ .reg = (0x3200) }) _MMIO(0x3200)((const i915_reg_t){ .reg = (0x3200) })
3266#define DPFC_CONTROL((const i915_reg_t){ .reg = (0x3208) }) _MMIO(0x3208)((const i915_reg_t){ .reg = (0x3208) })
3267#define DPFC_CTL_EN(1 << 31) (1 << 31)
3268#define DPFC_CTL_PLANE(plane)((plane) << 30) ((plane) << 30)
3269#define IVB_DPFC_CTL_PLANE(plane)((plane) << 29) ((plane) << 29)
3270#define DPFC_CTL_FENCE_EN(1 << 29) (1 << 29)
3271#define IVB_DPFC_CTL_FENCE_EN(1 << 28) (1 << 28)
3272#define DPFC_CTL_PERSISTENT_MODE(1 << 25) (1 << 25)
3273#define DPFC_SR_EN(1 << 10) (1 << 10)
3274#define DPFC_CTL_LIMIT_1X(0 << 6) (0 << 6)
3275#define DPFC_CTL_LIMIT_2X(1 << 6) (1 << 6)
3276#define DPFC_CTL_LIMIT_4X(2 << 6) (2 << 6)
3277#define DPFC_RECOMP_CTL((const i915_reg_t){ .reg = (0x320c) }) _MMIO(0x320c)((const i915_reg_t){ .reg = (0x320c) })
3278#define DPFC_RECOMP_STALL_EN(1 << 27) (1 << 27)
3279#define DPFC_RECOMP_STALL_WM_SHIFT(16) (16)
3280#define DPFC_RECOMP_STALL_WM_MASK(0x07ff0000) (0x07ff0000)
3281#define DPFC_RECOMP_TIMER_COUNT_SHIFT(0) (0)
3282#define DPFC_RECOMP_TIMER_COUNT_MASK(0x0000003f) (0x0000003f)
3283#define DPFC_STATUS((const i915_reg_t){ .reg = (0x3210) }) _MMIO(0x3210)((const i915_reg_t){ .reg = (0x3210) })
3284#define DPFC_INVAL_SEG_SHIFT(16) (16)
3285#define DPFC_INVAL_SEG_MASK(0x07ff0000) (0x07ff0000)
3286#define DPFC_COMP_SEG_SHIFT(0) (0)
3287#define DPFC_COMP_SEG_MASK(0x000007ff) (0x000007ff)
3288#define DPFC_STATUS2((const i915_reg_t){ .reg = (0x3214) }) _MMIO(0x3214)((const i915_reg_t){ .reg = (0x3214) })
3289#define DPFC_FENCE_YOFF((const i915_reg_t){ .reg = (0x3218) }) _MMIO(0x3218)((const i915_reg_t){ .reg = (0x3218) })
3290#define DPFC_CHICKEN((const i915_reg_t){ .reg = (0x3224) }) _MMIO(0x3224)((const i915_reg_t){ .reg = (0x3224) })
3291#define DPFC_HT_MODIFY(1 << 31) (1 << 31)
3292
3293/* Framebuffer compression for Ironlake */
3294#define ILK_DPFC_CB_BASE((const i915_reg_t){ .reg = (0x43200) }) _MMIO(0x43200)((const i915_reg_t){ .reg = (0x43200) })
3295#define ILK_DPFC_CONTROL((const i915_reg_t){ .reg = (0x43208) }) _MMIO(0x43208)((const i915_reg_t){ .reg = (0x43208) })
3296#define FBC_CTL_FALSE_COLOR(1 << 10) (1 << 10)
3297/* The bit 28-8 is reserved */
3298#define DPFC_RESERVED(0x1FFFFF00) (0x1FFFFF00)
3299#define ILK_DPFC_RECOMP_CTL((const i915_reg_t){ .reg = (0x4320c) }) _MMIO(0x4320c)((const i915_reg_t){ .reg = (0x4320c) })
3300#define ILK_DPFC_STATUS((const i915_reg_t){ .reg = (0x43210) }) _MMIO(0x43210)((const i915_reg_t){ .reg = (0x43210) })
3301#define ILK_DPFC_COMP_SEG_MASK0x7ff 0x7ff
3302#define IVB_FBC_STATUS2((const i915_reg_t){ .reg = (0x43214) }) _MMIO(0x43214)((const i915_reg_t){ .reg = (0x43214) })
3303#define IVB_FBC_COMP_SEG_MASK0x7ff 0x7ff
3304#define BDW_FBC_COMP_SEG_MASK0xfff 0xfff
3305#define ILK_DPFC_FENCE_YOFF((const i915_reg_t){ .reg = (0x43218) }) _MMIO(0x43218)((const i915_reg_t){ .reg = (0x43218) })
3306#define ILK_DPFC_CHICKEN((const i915_reg_t){ .reg = (0x43224) }) _MMIO(0x43224)((const i915_reg_t){ .reg = (0x43224) })
3307#define ILK_DPFC_DISABLE_DUMMY0(1 << 8) (1 << 8)
3308#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL(1 << 14) (1 << 14)
3309#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION(1 << 23) (1 << 23)
3310#define ILK_FBC_RT_BASE((const i915_reg_t){ .reg = (0x2128) }) _MMIO(0x2128)((const i915_reg_t){ .reg = (0x2128) })
3311#define ILK_FBC_RT_VALID(1 << 0) (1 << 0)
3312#define SNB_FBC_FRONT_BUFFER(1 << 1) (1 << 1)
3313
3314#define ILK_DISPLAY_CHICKEN1((const i915_reg_t){ .reg = (0x42000) }) _MMIO(0x42000)((const i915_reg_t){ .reg = (0x42000) })
3315#define ILK_FBCQ_DIS(1 << 22) (1 << 22)
3316#define ILK_PABSTRETCH_DIS(1 << 21) (1 << 21)
3317
3318
3319/*
3320 * Framebuffer compression for Sandybridge
3321 *
3322 * The following two registers are of type GTTMMADR
3323 */
3324#define SNB_DPFC_CTL_SA((const i915_reg_t){ .reg = (0x100100) }) _MMIO(0x100100)((const i915_reg_t){ .reg = (0x100100) })
3325#define SNB_CPU_FENCE_ENABLE(1 << 29) (1 << 29)
3326#define DPFC_CPU_FENCE_OFFSET((const i915_reg_t){ .reg = (0x100104) }) _MMIO(0x100104)((const i915_reg_t){ .reg = (0x100104) })
3327
3328/* Framebuffer compression for Ivybridge */
3329#define IVB_FBC_RT_BASE((const i915_reg_t){ .reg = (0x7020) }) _MMIO(0x7020)((const i915_reg_t){ .reg = (0x7020) })
3330#define IVB_FBC_RT_BASE_UPPER((const i915_reg_t){ .reg = (0x7024) }) _MMIO(0x7024)((const i915_reg_t){ .reg = (0x7024) })
3331
3332#define IPS_CTL((const i915_reg_t){ .reg = (0x43408) }) _MMIO(0x43408)((const i915_reg_t){ .reg = (0x43408) })
3333#define IPS_ENABLE(1 << 31) (1 << 31)
3334
3335#define MSG_FBC_REND_STATE((const i915_reg_t){ .reg = (0x50380) }) _MMIO(0x50380)((const i915_reg_t){ .reg = (0x50380) })
3336#define FBC_REND_NUKE(1 << 2) (1 << 2)
3337#define FBC_REND_CACHE_CLEAN(1 << 1) (1 << 1)
3338
3339/*
3340 * GPIO regs
3341 */
3342#define GPIO(gpio)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5010
+ 4 * (gpio)) }) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5010
+ 4 * (gpio)) })
3343 4 * (gpio))((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5010
+ 4 * (gpio)) })
3344
3345# define GPIO_CLOCK_DIR_MASK(1 << 0) (1 << 0)
3346# define GPIO_CLOCK_DIR_IN(0 << 1) (0 << 1)
3347# define GPIO_CLOCK_DIR_OUT(1 << 1) (1 << 1)
3348# define GPIO_CLOCK_VAL_MASK(1 << 2) (1 << 2)
3349# define GPIO_CLOCK_VAL_OUT(1 << 3) (1 << 3)
3350# define GPIO_CLOCK_VAL_IN(1 << 4) (1 << 4)
3351# define GPIO_CLOCK_PULLUP_DISABLE(1 << 5) (1 << 5)
3352# define GPIO_DATA_DIR_MASK(1 << 8) (1 << 8)
3353# define GPIO_DATA_DIR_IN(0 << 9) (0 << 9)
3354# define GPIO_DATA_DIR_OUT(1 << 9) (1 << 9)
3355# define GPIO_DATA_VAL_MASK(1 << 10) (1 << 10)
3356# define GPIO_DATA_VAL_OUT(1 << 11) (1 << 11)
3357# define GPIO_DATA_VAL_IN(1 << 12) (1 << 12)
3358# define GPIO_DATA_PULLUP_DISABLE(1 << 13) (1 << 13)
3359
3360#define GMBUS0((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5100
) }) _MMIO(dev_priv->gpio_mmio_base + 0x5100)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5100
) }) /* clock/port select */
3361#define GMBUS_AKSV_SELECT(1 << 11) (1 << 11)
3362#define GMBUS_RATE_100KHZ(0 << 8) (0 << 8)
3363#define GMBUS_RATE_50KHZ(1 << 8) (1 << 8)
3364#define GMBUS_RATE_400KHZ(2 << 8) (2 << 8) /* reserved on Pineview */
3365#define GMBUS_RATE_1MHZ(3 << 8) (3 << 8) /* reserved on Pineview */
3366#define GMBUS_HOLD_EXT(1 << 7) (1 << 7) /* 300ns hold time, rsvd on Pineview */
3367#define GMBUS_BYTE_CNT_OVERRIDE(1 << 6) (1 << 6)
3368
3369#define GMBUS1((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5104
) }) _MMIO(dev_priv->gpio_mmio_base + 0x5104)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5104
) }) /* command/status */
3370#define GMBUS_SW_CLR_INT(1 << 31) (1 << 31)
3371#define GMBUS_SW_RDY(1 << 30) (1 << 30)
3372#define GMBUS_ENT(1 << 29) (1 << 29) /* enable timeout */
3373#define GMBUS_CYCLE_NONE(0 << 25) (0 << 25)
3374#define GMBUS_CYCLE_WAIT(1 << 25) (1 << 25)
3375#define GMBUS_CYCLE_INDEX(2 << 25) (2 << 25)
3376#define GMBUS_CYCLE_STOP(4 << 25) (4 << 25)
3377#define GMBUS_BYTE_COUNT_SHIFT16 16
3378#define GMBUS_BYTE_COUNT_MAX256U 256U
3379#define GEN9_GMBUS_BYTE_COUNT_MAX511U 511U
3380#define GMBUS_SLAVE_INDEX_SHIFT8 8
3381#define GMBUS_SLAVE_ADDR_SHIFT1 1
3382#define GMBUS_SLAVE_READ(1 << 0) (1 << 0)
3383#define GMBUS_SLAVE_WRITE(0 << 0) (0 << 0)
3384#define GMBUS2((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5108
) }) _MMIO(dev_priv->gpio_mmio_base + 0x5108)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5108
) }) /* status */
3385#define GMBUS_INUSE(1 << 15) (1 << 15)
3386#define GMBUS_HW_WAIT_PHASE(1 << 14) (1 << 14)
3387#define GMBUS_STALL_TIMEOUT(1 << 13) (1 << 13)
3388#define GMBUS_INT(1 << 12) (1 << 12)
3389#define GMBUS_HW_RDY(1 << 11) (1 << 11)
3390#define GMBUS_SATOER(1 << 10) (1 << 10)
3391#define GMBUS_ACTIVE(1 << 9) (1 << 9)
3392#define GMBUS3((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x510c
) }) _MMIO(dev_priv->gpio_mmio_base + 0x510c)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x510c
) }) /* data buffer bytes 3-0 */
3393#define GMBUS4((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5110
) }) _MMIO(dev_priv->gpio_mmio_base + 0x5110)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5110
) }) /* interrupt mask (Pineview+) */
3394#define GMBUS_SLAVE_TIMEOUT_EN(1 << 4) (1 << 4)
3395#define GMBUS_NAK_EN(1 << 3) (1 << 3)
3396#define GMBUS_IDLE_EN(1 << 2) (1 << 2)
3397#define GMBUS_HW_WAIT_EN(1 << 1) (1 << 1)
3398#define GMBUS_HW_RDY_EN(1 << 0) (1 << 0)
3399#define GMBUS5((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5120
) }) _MMIO(dev_priv->gpio_mmio_base + 0x5120)((const i915_reg_t){ .reg = (dev_priv->gpio_mmio_base + 0x5120
) }) /* byte index */
3400#define GMBUS_2BYTE_INDEX_EN(1 << 31) (1 << 31)
3401
3402/*
3403 * Clock control & power management
3404 */
3405#define _DPLL_A(((&(dev_priv)->__info)->display_mmio_offset) + 0x6014
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x6014)
3406#define _DPLL_B(((&(dev_priv)->__info)->display_mmio_offset) + 0x6018
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x6018)
3407#define _CHV_DPLL_C(((&(dev_priv)->__info)->display_mmio_offset) + 0x6030
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x6030)
3408#define DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
}) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
3409
3410#define VGA0((const i915_reg_t){ .reg = (0x6000) }) _MMIO(0x6000)((const i915_reg_t){ .reg = (0x6000) })
3411#define VGA1((const i915_reg_t){ .reg = (0x6004) }) _MMIO(0x6004)((const i915_reg_t){ .reg = (0x6004) })
3412#define VGA_PD((const i915_reg_t){ .reg = (0x6010) }) _MMIO(0x6010)((const i915_reg_t){ .reg = (0x6010) })
3413#define VGA0_PD_P2_DIV_4(1 << 7) (1 << 7)
3414#define VGA0_PD_P1_DIV_2(1 << 5) (1 << 5)
3415#define VGA0_PD_P1_SHIFT0 0
3416#define VGA0_PD_P1_MASK(0x1f << 0) (0x1f << 0)
3417#define VGA1_PD_P2_DIV_4(1 << 15) (1 << 15)
3418#define VGA1_PD_P1_DIV_2(1 << 13) (1 << 13)
3419#define VGA1_PD_P1_SHIFT8 8
3420#define VGA1_PD_P1_MASK(0x1f << 8) (0x1f << 8)
3421#define DPLL_VCO_ENABLE(1 << 31) (1 << 31)
3422#define DPLL_SDVO_HIGH_SPEED(1 << 30) (1 << 30)
3423#define DPLL_DVO_2X_MODE(1 << 30) (1 << 30)
3424#define DPLL_EXT_BUFFER_ENABLE_VLV(1 << 30) (1 << 30)
3425#define DPLL_SYNCLOCK_ENABLE(1 << 29) (1 << 29)
3426#define DPLL_REF_CLK_ENABLE_VLV(1 << 29) (1 << 29)
3427#define DPLL_VGA_MODE_DIS(1 << 28) (1 << 28)
3428#define DPLLB_MODE_DAC_SERIAL(1 << 26) (1 << 26) /* i915 */
3429#define DPLLB_MODE_LVDS(2 << 26) (2 << 26) /* i915 */
3430#define DPLL_MODE_MASK(3 << 26) (3 << 26)
3431#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10(0 << 24) (0 << 24) /* i915 */
3432#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24) (1 << 24) /* i915 */
3433#define DPLLB_LVDS_P2_CLOCK_DIV_14(0 << 24) (0 << 24) /* i915 */
3434#define DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24) (1 << 24) /* i915 */
3435#define DPLL_P2_CLOCK_DIV_MASK0x03000000 0x03000000 /* i915 */
3436#define DPLL_FPA01_P1_POST_DIV_MASK0x00ff0000 0x00ff0000 /* i915 */
3437#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW0x00ff8000 0x00ff8000 /* Pineview */
3438#define DPLL_LOCK_VLV(1 << 15) (1 << 15)
3439#define DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14) (1 << 14)
3440#define DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) (1 << 13)
3441#define DPLL_SSC_REF_CLK_CHV(1 << 13) (1 << 13)
3442#define DPLL_PORTC_READY_MASK(0xf << 4) (0xf << 4)
3443#define DPLL_PORTB_READY_MASK(0xf) (0xf)
3444
3445#define DPLL_FPA01_P1_POST_DIV_MASK_I8300x001f0000 0x001f0000
3446
3447/* Additional CHV pll/phy registers */
3448#define DPIO_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x6240) }) _MMIO(VLV_DISPLAY_BASE + 0x6240)((const i915_reg_t){ .reg = (0x180000 + 0x6240) })
3449#define DPLL_PORTD_READY_MASK(0xf) (0xf)
3450#define DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }) _MMIO(VLV_DISPLAY_BASE + 0x60100)((const i915_reg_t){ .reg = (0x180000 + 0x60100) })
3451#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27)) (1 << (2 * (phy) + (ch) + 27))
3452#define PHY_LDO_DELAY_0NS0x0 0x0
3453#define PHY_LDO_DELAY_200NS0x1 0x1
3454#define PHY_LDO_DELAY_600NS0x2 0x2
3455#define PHY_LDO_SEQ_DELAY(delay, phy)((delay) << (2 * (phy) + 23)) ((delay) << (2 * (phy) + 23))
3456#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)((mask) << (8 * (phy) + 4 * (ch) + 11)) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3457#define PHY_CH_SU_PSR0x1 0x1
3458#define PHY_CH_DEEP_PSR0x7 0x7
3459#define PHY_CH_POWER_MODE(mode, phy, ch)((mode) << (6 * (phy) + 3 * (ch) + 2)) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3460#define PHY_COM_LANE_RESET_DEASSERT(phy)(1 << (phy)) (1 << (phy))
3461#define DISPLAY_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x60104) }) _MMIO(VLV_DISPLAY_BASE + 0x60104)((const i915_reg_t){ .reg = (0x180000 + 0x60104) })
3462#define PHY_POWERGOOD(phy)(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3463#define PHY_STATUS_CMN_LDO(phy, ch)(1 << (6 - (6 * (phy) + 3 * (ch)))) (1 << (6 - (6 * (phy) + 3 * (ch))))
3464#define PHY_STATUS_SPLINE_LDO(phy, ch, spline)(1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3465
3466/*
3467 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3468 * this field (only one bit may be set).
3469 */
3470#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS0x003f0000 0x003f0000
3471#define DPLL_FPA01_P1_POST_DIV_SHIFT16 16
3472#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW15 15
3473/* i830, required in DVO non-gang */
3474#define PLL_P2_DIVIDE_BY_4(1 << 23) (1 << 23)
3475#define PLL_P1_DIVIDE_BY_TWO(1 << 21) (1 << 21) /* i830 */
3476#define PLL_REF_INPUT_DREFCLK(0 << 13) (0 << 13)
3477#define PLL_REF_INPUT_TVCLKINA(1 << 13) (1 << 13) /* i830 */
3478#define PLL_REF_INPUT_TVCLKINBC(2 << 13) (2 << 13) /* SDVO TVCLKIN */
3479#define PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13) (3 << 13)
3480#define PLL_REF_INPUT_MASK(3 << 13) (3 << 13)
3481#define PLL_LOAD_PULSE_PHASE_SHIFT9 9
3482/* Ironlake */
3483# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT9 9
3484# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK(7 << 9) (7 << 9)
3485# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)(((x) - 1) << 9) (((x) - 1) << 9)
3486# define DPLL_FPA1_P1_POST_DIV_SHIFT0 0
3487# define DPLL_FPA1_P1_POST_DIV_MASK0xff 0xff
3488
3489/*
3490 * Parallel to Serial Load Pulse phase selection.
3491 * Selects the phase for the 10X DPLL clock for the PCIe
3492 * digital display port. The range is 4 to 13; 10 or more
3493 * is just a flip delay. The default is 6
3494 */
3495#define PLL_LOAD_PULSE_PHASE_MASK(0xf << 9) (0xf << PLL_LOAD_PULSE_PHASE_SHIFT9)
3496#define DISPLAY_RATE_SELECT_FPA1(1 << 8) (1 << 8)
3497/*
3498 * SDVO multiplier for 945G/GM. Not used on 965.
3499 */
3500#define SDVO_MULTIPLIER_MASK0x000000ff 0x000000ff
3501#define SDVO_MULTIPLIER_SHIFT_HIRES4 4
3502#define SDVO_MULTIPLIER_SHIFT_VGA0 0
3503
3504#define _DPLL_A_MD(((&(dev_priv)->__info)->display_mmio_offset) + 0x601c
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x601c)
3505#define _DPLL_B_MD(((&(dev_priv)->__info)->display_mmio_offset) + 0x6020
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x6020)
3506#define _CHV_DPLL_C_MD(((&(dev_priv)->__info)->display_mmio_offset) + 0x603c
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x603c)
3507#define DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
}) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
})
3508
3509/*
3510 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3511 *
3512 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3513 */
3514#define DPLL_MD_UDI_DIVIDER_MASK0x3f000000 0x3f000000
3515#define DPLL_MD_UDI_DIVIDER_SHIFT24 24
3516/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3517#define DPLL_MD_VGA_UDI_DIVIDER_MASK0x003f0000 0x003f0000
3518#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT16 16
3519/*
3520 * SDVO/UDI pixel multiplier.
3521 *
3522 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3523 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3524 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3525 * dummy bytes in the datastream at an increased clock rate, with both sides of
3526 * the link knowing how many bytes are fill.
3527 *
3528 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3529 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3530 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3531 * through an SDVO command.
3532 *
3533 * This register field has values of multiplication factor minus 1, with
3534 * a maximum multiplier of 5 for SDVO.
3535 */
3536#define DPLL_MD_UDI_MULTIPLIER_MASK0x00003f00 0x00003f00
3537#define DPLL_MD_UDI_MULTIPLIER_SHIFT8 8
3538/*
3539 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3540 * This best be set to the default value (3) or the CRT won't work. No,
3541 * I don't entirely understand what this does...
3542 */
3543#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK0x0000003f 0x0000003f
3544#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT0 0
3545
3546#define RAWCLK_FREQ_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6024) }) _MMIO(VLV_DISPLAY_BASE + 0x6024)((const i915_reg_t){ .reg = (0x180000 + 0x6024) })
3547
3548#define _FPA00x6040 0x6040
3549#define _FPA10x6044 0x6044
3550#define _FPB00x6048 0x6048
3551#define _FPB10x604c 0x604c
3552#define FP0(pipe)((const i915_reg_t){ .reg = (((0x6040) + (pipe) * ((0x6048) -
(0x6040)))) }) _MMIO_PIPE(pipe, _FPA0, _FPB0)((const i915_reg_t){ .reg = (((0x6040) + (pipe) * ((0x6048) -
(0x6040)))) })
3553#define FP1(pipe)((const i915_reg_t){ .reg = (((0x6044) + (pipe) * ((0x604c) -
(0x6044)))) }) _MMIO_PIPE(pipe, _FPA1, _FPB1)((const i915_reg_t){ .reg = (((0x6044) + (pipe) * ((0x604c) -
(0x6044)))) })
3554#define FP_N_DIV_MASK0x003f0000 0x003f0000
3555#define FP_N_PINEVIEW_DIV_MASK0x00ff0000 0x00ff0000
3556#define FP_N_DIV_SHIFT16 16
3557#define FP_M1_DIV_MASK0x00003f00 0x00003f00
3558#define FP_M1_DIV_SHIFT8 8
3559#define FP_M2_DIV_MASK0x0000003f 0x0000003f
3560#define FP_M2_PINEVIEW_DIV_MASK0x000000ff 0x000000ff
3561#define FP_M2_DIV_SHIFT0 0
3562#define DPLL_TEST((const i915_reg_t){ .reg = (0x606c) }) _MMIO(0x606c)((const i915_reg_t){ .reg = (0x606c) })
3563#define DPLLB_TEST_SDVO_DIV_1(0 << 22) (0 << 22)
3564#define DPLLB_TEST_SDVO_DIV_2(1 << 22) (1 << 22)
3565#define DPLLB_TEST_SDVO_DIV_4(2 << 22) (2 << 22)
3566#define DPLLB_TEST_SDVO_DIV_MASK(3 << 22) (3 << 22)
3567#define DPLLB_TEST_N_BYPASS(1 << 19) (1 << 19)
3568#define DPLLB_TEST_M_BYPASS(1 << 18) (1 << 18)
3569#define DPLLB_INPUT_BUFFER_ENABLE(1 << 16) (1 << 16)
3570#define DPLLA_TEST_N_BYPASS(1 << 3) (1 << 3)
3571#define DPLLA_TEST_M_BYPASS(1 << 2) (1 << 2)
3572#define DPLLA_INPUT_BUFFER_ENABLE(1 << 0) (1 << 0)
3573#define D_STATE((const i915_reg_t){ .reg = (0x6104) }) _MMIO(0x6104)((const i915_reg_t){ .reg = (0x6104) })
3574#define DSTATE_GFX_RESET_I830(1 << 6) (1 << 6)
3575#define DSTATE_PLL_D3_OFF(1 << 3) (1 << 3)
3576#define DSTATE_GFX_CLOCK_GATING(1 << 1) (1 << 1)
3577#define DSTATE_DOT_CLOCK_GATING(1 << 0) (1 << 0)
3578#define DSPCLK_GATE_D((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x6200) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x6200) })
3579# define DPUNIT_B_CLOCK_GATE_DISABLE(1 << 30) (1 << 30) /* 965 */
3580# define VSUNIT_CLOCK_GATE_DISABLE(1 << 29) (1 << 29) /* 965 */
3581# define VRHUNIT_CLOCK_GATE_DISABLE(1 << 28) (1 << 28) /* 965 */
3582# define VRDUNIT_CLOCK_GATE_DISABLE(1 << 27) (1 << 27) /* 965 */
3583# define AUDUNIT_CLOCK_GATE_DISABLE(1 << 26) (1 << 26) /* 965 */
3584# define DPUNIT_A_CLOCK_GATE_DISABLE(1 << 25) (1 << 25) /* 965 */
3585# define DPCUNIT_CLOCK_GATE_DISABLE(1 << 24) (1 << 24) /* 965 */
3586# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE(1 << 24) (1 << 24) /* pnv */
3587# define TVRUNIT_CLOCK_GATE_DISABLE(1 << 23) (1 << 23) /* 915-945 */
3588# define TVCUNIT_CLOCK_GATE_DISABLE(1 << 22) (1 << 22) /* 915-945 */
3589# define TVFUNIT_CLOCK_GATE_DISABLE(1 << 21) (1 << 21) /* 915-945 */
3590# define TVEUNIT_CLOCK_GATE_DISABLE(1 << 20) (1 << 20) /* 915-945 */
3591# define DVSUNIT_CLOCK_GATE_DISABLE(1 << 19) (1 << 19) /* 915-945 */
3592# define DSSUNIT_CLOCK_GATE_DISABLE(1 << 18) (1 << 18) /* 915-945 */
3593# define DDBUNIT_CLOCK_GATE_DISABLE(1 << 17) (1 << 17) /* 915-945 */
3594# define DPRUNIT_CLOCK_GATE_DISABLE(1 << 16) (1 << 16) /* 915-945 */
3595# define DPFUNIT_CLOCK_GATE_DISABLE(1 << 15) (1 << 15) /* 915-945 */
3596# define DPBMUNIT_CLOCK_GATE_DISABLE(1 << 14) (1 << 14) /* 915-945 */
3597# define DPLSUNIT_CLOCK_GATE_DISABLE(1 << 13) (1 << 13) /* 915-945 */
3598# define DPLUNIT_CLOCK_GATE_DISABLE(1 << 12) (1 << 12) /* 915-945 */
3599# define DPOUNIT_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
3600# define DPBUNIT_CLOCK_GATE_DISABLE(1 << 10) (1 << 10)
3601# define DCUNIT_CLOCK_GATE_DISABLE(1 << 9) (1 << 9)
3602# define DPUNIT_CLOCK_GATE_DISABLE(1 << 8) (1 << 8)
3603# define VRUNIT_CLOCK_GATE_DISABLE(1 << 7) (1 << 7) /* 915+: reserved */
3604# define OVHUNIT_CLOCK_GATE_DISABLE(1 << 6) (1 << 6) /* 830-865 */
3605# define DPIOUNIT_CLOCK_GATE_DISABLE(1 << 6) (1 << 6) /* 915-945 */
3606# define OVFUNIT_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
3607# define OVBUNIT_CLOCK_GATE_DISABLE(1 << 4) (1 << 4)
3608/*
3609 * This bit must be set on the 830 to prevent hangs when turning off the
3610 * overlay scaler.
3611 */
3612# define OVRUNIT_CLOCK_GATE_DISABLE(1 << 3) (1 << 3)
3613# define OVCUNIT_CLOCK_GATE_DISABLE(1 << 2) (1 << 2)
3614# define OVUUNIT_CLOCK_GATE_DISABLE(1 << 1) (1 << 1)
3615# define ZVUNIT_CLOCK_GATE_DISABLE(1 << 0) (1 << 0) /* 830 */
3616# define OVLUNIT_CLOCK_GATE_DISABLE(1 << 0) (1 << 0) /* 845,865 */
3617
3618#define RENCLK_GATE_D1((const i915_reg_t){ .reg = (0x6204) }) _MMIO(0x6204)((const i915_reg_t){ .reg = (0x6204) })
3619# define BLITTER_CLOCK_GATE_DISABLE(1 << 13) (1 << 13) /* 945GM only */
3620# define MPEG_CLOCK_GATE_DISABLE(1 << 12) (1 << 12) /* 945GM only */
3621# define PC_FE_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
3622# define PC_BE_CLOCK_GATE_DISABLE(1 << 10) (1 << 10)
3623# define WINDOWER_CLOCK_GATE_DISABLE(1 << 9) (1 << 9)
3624# define INTERPOLATOR_CLOCK_GATE_DISABLE(1 << 8) (1 << 8)
3625# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE(1 << 7) (1 << 7)
3626# define MOTION_COMP_CLOCK_GATE_DISABLE(1 << 6) (1 << 6)
3627# define MAG_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
3628/* This bit must be unset on 855,865 */
3629# define MECI_CLOCK_GATE_DISABLE(1 << 4) (1 << 4)
3630# define DCMP_CLOCK_GATE_DISABLE(1 << 3) (1 << 3)
3631# define MEC_CLOCK_GATE_DISABLE(1 << 2) (1 << 2)
3632# define MECO_CLOCK_GATE_DISABLE(1 << 1) (1 << 1)
3633/* This bit must be set on 855,865. */
3634# define SV_CLOCK_GATE_DISABLE(1 << 0) (1 << 0)
3635# define I915_MPEG_CLOCK_GATE_DISABLE(1 << 16) (1 << 16)
3636# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE(1 << 15) (1 << 15)
3637# define I915_MOTION_COMP_CLOCK_GATE_DISABLE(1 << 14) (1 << 14)
3638# define I915_BD_BF_CLOCK_GATE_DISABLE(1 << 13) (1 << 13)
3639# define I915_SF_SE_CLOCK_GATE_DISABLE(1 << 12) (1 << 12)
3640# define I915_WM_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
3641# define I915_IZ_CLOCK_GATE_DISABLE(1 << 10) (1 << 10)
3642# define I915_PI_CLOCK_GATE_DISABLE(1 << 9) (1 << 9)
3643# define I915_DI_CLOCK_GATE_DISABLE(1 << 8) (1 << 8)
3644# define I915_SH_SV_CLOCK_GATE_DISABLE(1 << 7) (1 << 7)
3645# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE(1 << 6) (1 << 6)
3646# define I915_SC_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
3647# define I915_FL_CLOCK_GATE_DISABLE(1 << 4) (1 << 4)
3648# define I915_DM_CLOCK_GATE_DISABLE(1 << 3) (1 << 3)
3649# define I915_PS_CLOCK_GATE_DISABLE(1 << 2) (1 << 2)
3650# define I915_CC_CLOCK_GATE_DISABLE(1 << 1) (1 << 1)
3651# define I915_BY_CLOCK_GATE_DISABLE(1 << 0) (1 << 0)
3652
3653# define I965_RCZ_CLOCK_GATE_DISABLE(1 << 30) (1 << 30)
3654/* This bit must always be set on 965G/965GM */
3655# define I965_RCC_CLOCK_GATE_DISABLE(1 << 29) (1 << 29)
3656# define I965_RCPB_CLOCK_GATE_DISABLE(1 << 28) (1 << 28)
3657# define I965_DAP_CLOCK_GATE_DISABLE(1 << 27) (1 << 27)
3658# define I965_ROC_CLOCK_GATE_DISABLE(1 << 26) (1 << 26)
3659# define I965_GW_CLOCK_GATE_DISABLE(1 << 25) (1 << 25)
3660# define I965_TD_CLOCK_GATE_DISABLE(1 << 24) (1 << 24)
3661/* This bit must always be set on 965G */
3662# define I965_ISC_CLOCK_GATE_DISABLE(1 << 23) (1 << 23)
3663# define I965_IC_CLOCK_GATE_DISABLE(1 << 22) (1 << 22)
3664# define I965_EU_CLOCK_GATE_DISABLE(1 << 21) (1 << 21)
3665# define I965_IF_CLOCK_GATE_DISABLE(1 << 20) (1 << 20)
3666# define I965_TC_CLOCK_GATE_DISABLE(1 << 19) (1 << 19)
3667# define I965_SO_CLOCK_GATE_DISABLE(1 << 17) (1 << 17)
3668# define I965_FBC_CLOCK_GATE_DISABLE(1 << 16) (1 << 16)
3669# define I965_MARI_CLOCK_GATE_DISABLE(1 << 15) (1 << 15)
3670# define I965_MASF_CLOCK_GATE_DISABLE(1 << 14) (1 << 14)
3671# define I965_MAWB_CLOCK_GATE_DISABLE(1 << 13) (1 << 13)
3672# define I965_EM_CLOCK_GATE_DISABLE(1 << 12) (1 << 12)
3673# define I965_UC_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
3674# define I965_SI_CLOCK_GATE_DISABLE(1 << 6) (1 << 6)
3675# define I965_MT_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
3676# define I965_PL_CLOCK_GATE_DISABLE(1 << 4) (1 << 4)
3677# define I965_DG_CLOCK_GATE_DISABLE(1 << 3) (1 << 3)
3678# define I965_QC_CLOCK_GATE_DISABLE(1 << 2) (1 << 2)
3679# define I965_FT_CLOCK_GATE_DISABLE(1 << 1) (1 << 1)
3680# define I965_DM_CLOCK_GATE_DISABLE(1 << 0) (1 << 0)
3681
3682#define RENCLK_GATE_D2((const i915_reg_t){ .reg = (0x6208) }) _MMIO(0x6208)((const i915_reg_t){ .reg = (0x6208) })
3683#define VF_UNIT_CLOCK_GATE_DISABLE(1 << 9) (1 << 9)
3684#define GS_UNIT_CLOCK_GATE_DISABLE(1 << 7) (1 << 7)
3685#define CL_UNIT_CLOCK_GATE_DISABLE(1 << 6) (1 << 6)
3686
3687#define VDECCLK_GATE_D((const i915_reg_t){ .reg = (0x620C) }) _MMIO(0x620C)((const i915_reg_t){ .reg = (0x620C) }) /* g4x only */
3688#define VCP_UNIT_CLOCK_GATE_DISABLE(1 << 4) (1 << 4)
3689
3690#define RAMCLK_GATE_D((const i915_reg_t){ .reg = (0x6210) }) _MMIO(0x6210)((const i915_reg_t){ .reg = (0x6210) }) /* CRL only */
3691#define DEUC((const i915_reg_t){ .reg = (0x6214) }) _MMIO(0x6214)((const i915_reg_t){ .reg = (0x6214) }) /* CRL only */
3692
3693#define FW_BLC_SELF_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6500) }) _MMIO(VLV_DISPLAY_BASE + 0x6500)((const i915_reg_t){ .reg = (0x180000 + 0x6500) })
3694#define FW_CSPWRDWNEN(1 << 15) (1 << 15)
3695
3696#define MI_ARB_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6504) }) _MMIO(VLV_DISPLAY_BASE + 0x6504)((const i915_reg_t){ .reg = (0x180000 + 0x6504) })
3697
3698#define CZCLK_CDCLK_FREQ_RATIO((const i915_reg_t){ .reg = (0x180000 + 0x6508) }) _MMIO(VLV_DISPLAY_BASE + 0x6508)((const i915_reg_t){ .reg = (0x180000 + 0x6508) })
3699#define CDCLK_FREQ_SHIFT4 4
3700#define CDCLK_FREQ_MASK(0x1f << 4) (0x1f << CDCLK_FREQ_SHIFT4)
3701#define CZCLK_FREQ_MASK0xf 0xf
3702
3703#define GCI_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x650C) }) _MMIO(VLV_DISPLAY_BASE + 0x650C)((const i915_reg_t){ .reg = (0x180000 + 0x650C) })
3704#define PFI_CREDIT_63(9 << 28) (9 << 28) /* chv only */
3705#define PFI_CREDIT_31(8 << 28) (8 << 28) /* chv only */
3706#define PFI_CREDIT(x)(((x) - 8) << 28) (((x) - 8) << 28) /* 8-15 */
3707#define PFI_CREDIT_RESEND(1 << 27) (1 << 27)
3708#define VGA_FAST_MODE_DISABLE(1 << 14) (1 << 14)
3709
3710#define GMBUSFREQ_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6510) }) _MMIO(VLV_DISPLAY_BASE + 0x6510)((const i915_reg_t){ .reg = (0x180000 + 0x6510) })
3711
3712/*
3713 * Palette regs
3714 */
3715#define _PALETTE_A0xa000 0xa000
3716#define _PALETTE_B0xa800 0xa800
3717#define _CHV_PALETTE_C0xc000 0xc000
3718#define PALETTE_RED_MASK((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(23, 16)((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))
3719#define PALETTE_GREEN_MASK((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(8))) + 0)) REG_GENMASK(15, 8)((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(8))) + 0))
3720#define PALETTE_BLUE_MASK((u32)((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(7, 0)((u32)((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0))) + 0))
3721#define PALETTE(pipe, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + (((const u32 []){ 0xa000, 0xa800, 0xc000
})[(pipe)]) + (i) * 4) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + (((const u32 []){ 0xa000, 0xa800, 0xc000
})[(pipe)]) + (i) * 4) })
3722 _PICK((pipe), _PALETTE_A, \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + (((const u32 []){ 0xa000, 0xa800, 0xc000
})[(pipe)]) + (i) * 4) })
3723 _PALETTE_B, _CHV_PALETTE_C) + \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + (((const u32 []){ 0xa000, 0xa800, 0xc000
})[(pipe)]) + (i) * 4) })
3724 (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + (((const u32 []){ 0xa000, 0xa800, 0xc000
})[(pipe)]) + (i) * 4) })
3725
3726/* MCH MMIO space */
3727
3728/*
3729 * MCHBAR mirror.
3730 *
3731 * This mirrors the MCHBAR MMIO space whose location is determined by
3732 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3733 * every way. It is not accessible from the CP register read instructions.
3734 *
3735 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3736 * just read.
3737 */
3738#define MCHBAR_MIRROR_BASE0x10000 0x10000
3739
3740#define MCHBAR_MIRROR_BASE_SNB0x140000 0x140000
3741
3742#define CTG_STOLEN_RESERVED((const i915_reg_t){ .reg = (0x10000 + 0x34) }) _MMIO(MCHBAR_MIRROR_BASE + 0x34)((const i915_reg_t){ .reg = (0x10000 + 0x34) })
3743#define ELK_STOLEN_RESERVED((const i915_reg_t){ .reg = (0x10000 + 0x48) }) _MMIO(MCHBAR_MIRROR_BASE + 0x48)((const i915_reg_t){ .reg = (0x10000 + 0x48) })
3744#define G4X_STOLEN_RESERVED_ADDR1_MASK(0xFFFF << 16) (0xFFFF << 16)
3745#define G4X_STOLEN_RESERVED_ADDR2_MASK(0xFFF << 4) (0xFFF << 4)
3746#define G4X_STOLEN_RESERVED_ENABLE(1 << 0) (1 << 0)
3747
3748/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3749#define DCLK((const i915_reg_t){ .reg = (0x140000 + 0x5e04) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)((const i915_reg_t){ .reg = (0x140000 + 0x5e04) })
3750
3751/* 915-945 and GM965 MCH register controlling DRAM channel access */
3752#define DCC((const i915_reg_t){ .reg = (0x10000 + 0x200) }) _MMIO(MCHBAR_MIRROR_BASE + 0x200)((const i915_reg_t){ .reg = (0x10000 + 0x200) })
3753#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL(0 << 0) (0 << 0)
3754#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC(1 << 0) (1 << 0)
3755#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED(2 << 0) (2 << 0)
3756#define DCC_ADDRESSING_MODE_MASK(3 << 0) (3 << 0)
3757#define DCC_CHANNEL_XOR_DISABLE(1 << 10) (1 << 10)
3758#define DCC_CHANNEL_XOR_BIT_17(1 << 9) (1 << 9)
3759#define DCC2((const i915_reg_t){ .reg = (0x10000 + 0x204) }) _MMIO(MCHBAR_MIRROR_BASE + 0x204)((const i915_reg_t){ .reg = (0x10000 + 0x204) })
3760#define DCC2_MODIFIED_ENHANCED_DISABLE(1 << 20) (1 << 20)
3761
3762/* Pineview MCH register contains DDR3 setting */
3763#define CSHRDDR3CTL((const i915_reg_t){ .reg = (0x10000 + 0x1a8) }) _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)((const i915_reg_t){ .reg = (0x10000 + 0x1a8) })
3764#define CSHRDDR3CTL_DDR3(1 << 2) (1 << 2)
3765
3766/* 965 MCH register controlling DRAM channel configuration */
3767#define C0DRB3((const i915_reg_t){ .reg = (0x10000 + 0x206) }) _MMIO(MCHBAR_MIRROR_BASE + 0x206)((const i915_reg_t){ .reg = (0x10000 + 0x206) })
3768#define C1DRB3((const i915_reg_t){ .reg = (0x10000 + 0x606) }) _MMIO(MCHBAR_MIRROR_BASE + 0x606)((const i915_reg_t){ .reg = (0x10000 + 0x606) })
3769
3770/* snb MCH registers for reading the DRAM channel configuration */
3771#define MAD_DIMM_C0((const i915_reg_t){ .reg = (0x140000 + 0x5004) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)((const i915_reg_t){ .reg = (0x140000 + 0x5004) })
3772#define MAD_DIMM_C1((const i915_reg_t){ .reg = (0x140000 + 0x5008) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)((const i915_reg_t){ .reg = (0x140000 + 0x5008) })
3773#define MAD_DIMM_C2((const i915_reg_t){ .reg = (0x140000 + 0x500C) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)((const i915_reg_t){ .reg = (0x140000 + 0x500C) })
3774#define MAD_DIMM_ECC_MASK(0x3 << 24) (0x3 << 24)
3775#define MAD_DIMM_ECC_OFF(0x0 << 24) (0x0 << 24)
3776#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF(0x1 << 24) (0x1 << 24)
3777#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON(0x2 << 24) (0x2 << 24)
3778#define MAD_DIMM_ECC_ON(0x3 << 24) (0x3 << 24)
3779#define MAD_DIMM_ENH_INTERLEAVE(0x1 << 22) (0x1 << 22)
3780#define MAD_DIMM_RANK_INTERLEAVE(0x1 << 21) (0x1 << 21)
3781#define MAD_DIMM_B_WIDTH_X16(0x1 << 20) (0x1 << 20) /* X8 chips if unset */
3782#define MAD_DIMM_A_WIDTH_X16(0x1 << 19) (0x1 << 19) /* X8 chips if unset */
3783#define MAD_DIMM_B_DUAL_RANK(0x1 << 18) (0x1 << 18)
3784#define MAD_DIMM_A_DUAL_RANK(0x1 << 17) (0x1 << 17)
3785#define MAD_DIMM_A_SELECT(0x1 << 16) (0x1 << 16)
3786/* DIMM sizes are in multiples of 256mb. */
3787#define MAD_DIMM_B_SIZE_SHIFT8 8
3788#define MAD_DIMM_B_SIZE_MASK(0xff << 8) (0xff << MAD_DIMM_B_SIZE_SHIFT8)
3789#define MAD_DIMM_A_SIZE_SHIFT0 0
3790#define MAD_DIMM_A_SIZE_MASK(0xff << 0) (0xff << MAD_DIMM_A_SIZE_SHIFT0)
3791
3792/* snb MCH registers for priority tuning */
3793#define MCH_SSKPD((const i915_reg_t){ .reg = (0x140000 + 0x5d10) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)((const i915_reg_t){ .reg = (0x140000 + 0x5d10) })
3794#define MCH_SSKPD_WM0_MASK0x3f 0x3f
3795#define MCH_SSKPD_WM0_VAL0xc 0xc
3796
3797/* Clocking configuration register */
3798#define CLKCFG((const i915_reg_t){ .reg = (0x10000 + 0xc00) }) _MMIO(MCHBAR_MIRROR_BASE + 0xc00)((const i915_reg_t){ .reg = (0x10000 + 0xc00) })
3799#define CLKCFG_FSB_400(0 << 0) (0 << 0) /* hrawclk 100 */
3800#define CLKCFG_FSB_400_ALT(5 << 0) (5 << 0) /* hrawclk 100 */
3801#define CLKCFG_FSB_533(1 << 0) (1 << 0) /* hrawclk 133 */
3802#define CLKCFG_FSB_667(3 << 0) (3 << 0) /* hrawclk 166 */
3803#define CLKCFG_FSB_800(2 << 0) (2 << 0) /* hrawclk 200 */
3804#define CLKCFG_FSB_1067(6 << 0) (6 << 0) /* hrawclk 266 */
3805#define CLKCFG_FSB_1067_ALT(0 << 0) (0 << 0) /* hrawclk 266 */
3806#define CLKCFG_FSB_1333(7 << 0) (7 << 0) /* hrawclk 333 */
3807#define CLKCFG_FSB_1333_ALT(4 << 0) (4 << 0) /* hrawclk 333 */
3808#define CLKCFG_FSB_1600_ALT(6 << 0) (6 << 0) /* hrawclk 400 */
3809#define CLKCFG_FSB_MASK(7 << 0) (7 << 0)
3810#define CLKCFG_MEM_533(1 << 4) (1 << 4)
3811#define CLKCFG_MEM_667(2 << 4) (2 << 4)
3812#define CLKCFG_MEM_800(3 << 4) (3 << 4)
3813#define CLKCFG_MEM_MASK(7 << 4) (7 << 4)
3814
3815#define HPLLVCO((const i915_reg_t){ .reg = (0x10000 + 0xc38) }) _MMIO(MCHBAR_MIRROR_BASE + 0xc38)((const i915_reg_t){ .reg = (0x10000 + 0xc38) })
3816#define HPLLVCO_MOBILE((const i915_reg_t){ .reg = (0x10000 + 0xc0f) }) _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)((const i915_reg_t){ .reg = (0x10000 + 0xc0f) })
3817
3818#define TSC1((const i915_reg_t){ .reg = (0x11001) }) _MMIO(0x11001)((const i915_reg_t){ .reg = (0x11001) })
3819#define TSE(1 << 0) (1 << 0)
3820#define TR1((const i915_reg_t){ .reg = (0x11006) }) _MMIO(0x11006)((const i915_reg_t){ .reg = (0x11006) })
3821#define TSFS((const i915_reg_t){ .reg = (0x11020) }) _MMIO(0x11020)((const i915_reg_t){ .reg = (0x11020) })
3822#define TSFS_SLOPE_MASK0x0000ff00 0x0000ff00
3823#define TSFS_SLOPE_SHIFT8 8
3824#define TSFS_INTR_MASK0x000000ff 0x000000ff
3825
3826#define CRSTANDVID((const i915_reg_t){ .reg = (0x11100) }) _MMIO(0x11100)((const i915_reg_t){ .reg = (0x11100) })
3827#define PXVFREQ(fstart)((const i915_reg_t){ .reg = (0x11110 + (fstart) * 4) }) _MMIO(0x11110 + (fstart) * 4)((const i915_reg_t){ .reg = (0x11110 + (fstart) * 4) }) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3828#define PXVFREQ_PX_MASK0x7f000000 0x7f000000
3829#define PXVFREQ_PX_SHIFT24 24
3830#define VIDFREQ_BASE((const i915_reg_t){ .reg = (0x11110) }) _MMIO(0x11110)((const i915_reg_t){ .reg = (0x11110) })
3831#define VIDFREQ1((const i915_reg_t){ .reg = (0x11110) }) _MMIO(0x11110)((const i915_reg_t){ .reg = (0x11110) }) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3832#define VIDFREQ2((const i915_reg_t){ .reg = (0x11114) }) _MMIO(0x11114)((const i915_reg_t){ .reg = (0x11114) })
3833#define VIDFREQ3((const i915_reg_t){ .reg = (0x11118) }) _MMIO(0x11118)((const i915_reg_t){ .reg = (0x11118) })
3834#define VIDFREQ4((const i915_reg_t){ .reg = (0x1111c) }) _MMIO(0x1111c)((const i915_reg_t){ .reg = (0x1111c) })
3835#define VIDFREQ_P0_MASK0x1f000000 0x1f000000
3836#define VIDFREQ_P0_SHIFT24 24
3837#define VIDFREQ_P0_CSCLK_MASK0x00f00000 0x00f00000
3838#define VIDFREQ_P0_CSCLK_SHIFT20 20
3839#define VIDFREQ_P0_CRCLK_MASK0x000f0000 0x000f0000
3840#define VIDFREQ_P0_CRCLK_SHIFT16 16
3841#define VIDFREQ_P1_MASK0x00001f00 0x00001f00
3842#define VIDFREQ_P1_SHIFT8 8
3843#define VIDFREQ_P1_CSCLK_MASK0x000000f0 0x000000f0
3844#define VIDFREQ_P1_CSCLK_SHIFT4 4
3845#define VIDFREQ_P1_CRCLK_MASK0x0000000f 0x0000000f
3846#define INTTOEXT_BASE_ILK((const i915_reg_t){ .reg = (0x11300) }) _MMIO(0x11300)((const i915_reg_t){ .reg = (0x11300) })
3847#define INTTOEXT_BASE((const i915_reg_t){ .reg = (0x11120) }) _MMIO(0x11120)((const i915_reg_t){ .reg = (0x11120) }) /* INTTOEXT1-8 (0x1113c) */
3848#define INTTOEXT_MAP3_SHIFT24 24
3849#define INTTOEXT_MAP3_MASK(0x1f << 24) (0x1f << INTTOEXT_MAP3_SHIFT24)
3850#define INTTOEXT_MAP2_SHIFT16 16
3851#define INTTOEXT_MAP2_MASK(0x1f << 16) (0x1f << INTTOEXT_MAP2_SHIFT16)
3852#define INTTOEXT_MAP1_SHIFT8 8
3853#define INTTOEXT_MAP1_MASK(0x1f << 8) (0x1f << INTTOEXT_MAP1_SHIFT8)
3854#define INTTOEXT_MAP0_SHIFT0 0
3855#define INTTOEXT_MAP0_MASK(0x1f << 0) (0x1f << INTTOEXT_MAP0_SHIFT0)
3856#define MEMSWCTL((const i915_reg_t){ .reg = (0x11170) }) _MMIO(0x11170)((const i915_reg_t){ .reg = (0x11170) }) /* Ironlake only */
3857#define MEMCTL_CMD_MASK0xe000 0xe000
3858#define MEMCTL_CMD_SHIFT13 13
3859#define MEMCTL_CMD_RCLK_OFF0 0
3860#define MEMCTL_CMD_RCLK_ON1 1
3861#define MEMCTL_CMD_CHFREQ2 2
3862#define MEMCTL_CMD_CHVID3 3
3863#define MEMCTL_CMD_VMMOFF4 4
3864#define MEMCTL_CMD_VMMON5 5
3865#define MEMCTL_CMD_STS(1 << 12) (1 << 12) /* write 1 triggers command, clears
3866 when command complete */
3867#define MEMCTL_FREQ_MASK0x0f00 0x0f00 /* jitter, from 0-15 */
3868#define MEMCTL_FREQ_SHIFT8 8
3869#define MEMCTL_SFCAVM(1 << 7) (1 << 7)
3870#define MEMCTL_TGT_VID_MASK0x007f 0x007f
3871#define MEMIHYST((const i915_reg_t){ .reg = (0x1117c) }) _MMIO(0x1117c)((const i915_reg_t){ .reg = (0x1117c) })
3872#define MEMINTREN((const i915_reg_t){ .reg = (0x11180) }) _MMIO(0x11180)((const i915_reg_t){ .reg = (0x11180) }) /* 16 bits */
3873#define MEMINT_RSEXIT_EN(1 << 8) (1 << 8)
3874#define MEMINT_CX_SUPR_EN(1 << 7) (1 << 7)
3875#define MEMINT_CONT_BUSY_EN(1 << 6) (1 << 6)
3876#define MEMINT_AVG_BUSY_EN(1 << 5) (1 << 5)
3877#define MEMINT_EVAL_CHG_EN(1 << 4) (1 << 4)
3878#define MEMINT_MON_IDLE_EN(1 << 3) (1 << 3)
3879#define MEMINT_UP_EVAL_EN(1 << 2) (1 << 2)
3880#define MEMINT_DOWN_EVAL_EN(1 << 1) (1 << 1)
3881#define MEMINT_SW_CMD_EN(1 << 0) (1 << 0)
3882#define MEMINTRSTR((const i915_reg_t){ .reg = (0x11182) }) _MMIO(0x11182)((const i915_reg_t){ .reg = (0x11182) }) /* 16 bits */
3883#define MEM_RSEXIT_MASK0xc000 0xc000
3884#define MEM_RSEXIT_SHIFT14 14
3885#define MEM_CONT_BUSY_MASK0x3000 0x3000
3886#define MEM_CONT_BUSY_SHIFT12 12
3887#define MEM_AVG_BUSY_MASK0x0c00 0x0c00
3888#define MEM_AVG_BUSY_SHIFT10 10
3889#define MEM_EVAL_CHG_MASK0x0300 0x0300
3890#define MEM_EVAL_BUSY_SHIFT8 8
3891#define MEM_MON_IDLE_MASK0x00c0 0x00c0
3892#define MEM_MON_IDLE_SHIFT6 6
3893#define MEM_UP_EVAL_MASK0x0030 0x0030
3894#define MEM_UP_EVAL_SHIFT4 4
3895#define MEM_DOWN_EVAL_MASK0x000c 0x000c
3896#define MEM_DOWN_EVAL_SHIFT2 2
3897#define MEM_SW_CMD_MASK0x0003 0x0003
3898#define MEM_INT_STEER_GFX0 0
3899#define MEM_INT_STEER_CMR1 1
3900#define MEM_INT_STEER_SMI2 2
3901#define MEM_INT_STEER_SCI3 3
3902#define MEMINTRSTS((const i915_reg_t){ .reg = (0x11184) }) _MMIO(0x11184)((const i915_reg_t){ .reg = (0x11184) })
3903#define MEMINT_RSEXIT(1 << 7) (1 << 7)
3904#define MEMINT_CONT_BUSY(1 << 6) (1 << 6)
3905#define MEMINT_AVG_BUSY(1 << 5) (1 << 5)
3906#define MEMINT_EVAL_CHG(1 << 4) (1 << 4)
3907#define MEMINT_MON_IDLE(1 << 3) (1 << 3)
3908#define MEMINT_UP_EVAL(1 << 2) (1 << 2)
3909#define MEMINT_DOWN_EVAL(1 << 1) (1 << 1)
3910#define MEMINT_SW_CMD(1 << 0) (1 << 0)
3911#define MEMMODECTL((const i915_reg_t){ .reg = (0x11190) }) _MMIO(0x11190)((const i915_reg_t){ .reg = (0x11190) })
3912#define MEMMODE_BOOST_EN(1 << 31) (1 << 31)
3913#define MEMMODE_BOOST_FREQ_MASK0x0f000000 0x0f000000 /* jitter for boost, 0-15 */
3914#define MEMMODE_BOOST_FREQ_SHIFT24 24
3915#define MEMMODE_IDLE_MODE_MASK0x00030000 0x00030000
3916#define MEMMODE_IDLE_MODE_SHIFT16 16
3917#define MEMMODE_IDLE_MODE_EVAL0 0
3918#define MEMMODE_IDLE_MODE_CONT1 1
3919#define MEMMODE_HWIDLE_EN(1 << 15) (1 << 15)
3920#define MEMMODE_SWMODE_EN(1 << 14) (1 << 14)
3921#define MEMMODE_RCLK_GATE(1 << 13) (1 << 13)
3922#define MEMMODE_HW_UPDATE(1 << 12) (1 << 12)
3923#define MEMMODE_FSTART_MASK0x00000f00 0x00000f00 /* starting jitter, 0-15 */
3924#define MEMMODE_FSTART_SHIFT8 8
3925#define MEMMODE_FMAX_MASK0x000000f0 0x000000f0 /* max jitter, 0-15 */
3926#define MEMMODE_FMAX_SHIFT4 4
3927#define MEMMODE_FMIN_MASK0x0000000f 0x0000000f /* min jitter, 0-15 */
3928#define RCBMAXAVG((const i915_reg_t){ .reg = (0x1119c) }) _MMIO(0x1119c)((const i915_reg_t){ .reg = (0x1119c) })
3929#define MEMSWCTL2((const i915_reg_t){ .reg = (0x1119e) }) _MMIO(0x1119e)((const i915_reg_t){ .reg = (0x1119e) }) /* Cantiga only */
3930#define SWMEMCMD_RENDER_OFF(0 << 13) (0 << 13)
3931#define SWMEMCMD_RENDER_ON(1 << 13) (1 << 13)
3932#define SWMEMCMD_SWFREQ(2 << 13) (2 << 13)
3933#define SWMEMCMD_TARVID(3 << 13) (3 << 13)
3934#define SWMEMCMD_VRM_OFF(4 << 13) (4 << 13)
3935#define SWMEMCMD_VRM_ON(5 << 13) (5 << 13)
3936#define CMDSTS(1 << 12) (1 << 12)
3937#define SFCAVM(1 << 11) (1 << 11)
3938#define SWFREQ_MASK0x0380 0x0380 /* P0-7 */
3939#define SWFREQ_SHIFT7 7
3940#define TARVID_MASK0x001f 0x001f
3941#define MEMSTAT_CTG((const i915_reg_t){ .reg = (0x111a0) }) _MMIO(0x111a0)((const i915_reg_t){ .reg = (0x111a0) })
3942#define RCBMINAVG((const i915_reg_t){ .reg = (0x111a0) }) _MMIO(0x111a0)((const i915_reg_t){ .reg = (0x111a0) })
3943#define RCUPEI((const i915_reg_t){ .reg = (0x111b0) }) _MMIO(0x111b0)((const i915_reg_t){ .reg = (0x111b0) })
3944#define RCDNEI((const i915_reg_t){ .reg = (0x111b4) }) _MMIO(0x111b4)((const i915_reg_t){ .reg = (0x111b4) })
3945#define RSTDBYCTL((const i915_reg_t){ .reg = (0x111b8) }) _MMIO(0x111b8)((const i915_reg_t){ .reg = (0x111b8) })
3946#define RS1EN(1 << 31) (1 << 31)
3947#define RS2EN(1 << 30) (1 << 30)
3948#define RS3EN(1 << 29) (1 << 29)
3949#define D3RS3EN(1 << 28) (1 << 28) /* Display D3 imlies RS3 */
3950#define SWPROMORSX(1 << 27) (1 << 27) /* RSx promotion timers ignored */
3951#define RCWAKERW(1 << 26) (1 << 26) /* Resetwarn from PCH causes wakeup */
3952#define DPRSLPVREN(1 << 25) (1 << 25) /* Fast voltage ramp enable */
3953#define GFXTGHYST(1 << 24) (1 << 24) /* Hysteresis to allow trunk gating */
3954#define RCX_SW_EXIT(1 << 23) (1 << 23) /* Leave RSx and prevent re-entry */
3955#define RSX_STATUS_MASK(7 << 20) (7 << 20)
3956#define RSX_STATUS_ON(0 << 20) (0 << 20)
3957#define RSX_STATUS_RC1(1 << 20) (1 << 20)
3958#define RSX_STATUS_RC1E(2 << 20) (2 << 20)
3959#define RSX_STATUS_RS1(3 << 20) (3 << 20)
3960#define RSX_STATUS_RS2(4 << 20) (4 << 20) /* aka rc6 */
3961#define RSX_STATUS_RSVD(5 << 20) (5 << 20) /* deep rc6 unsupported on ilk */
3962#define RSX_STATUS_RS3(6 << 20) (6 << 20) /* rs3 unsupported on ilk */
3963#define RSX_STATUS_RSVD2(7 << 20) (7 << 20)
3964#define UWRCRSXE(1 << 19) (1 << 19) /* wake counter limit prevents rsx */
3965#define RSCRP(1 << 18) (1 << 18) /* rs requests control on rs1/2 reqs */
3966#define JRSC(1 << 17) (1 << 17) /* rsx coupled to cpu c-state */
3967#define RS2INC0(1 << 16) (1 << 16) /* allow rs2 in cpu c0 */
3968#define RS1CONTSAV_MASK(3 << 14) (3 << 14)
3969#define RS1CONTSAV_NO_RS1(0 << 14) (0 << 14) /* rs1 doesn't save/restore context */
3970#define RS1CONTSAV_RSVD(1 << 14) (1 << 14)
3971#define RS1CONTSAV_SAVE_RS1(2 << 14) (2 << 14) /* rs1 saves context */
3972#define RS1CONTSAV_FULL_RS1(3 << 14) (3 << 14) /* rs1 saves and restores context */
3973#define NORMSLEXLAT_MASK(3 << 12) (3 << 12)
3974#define SLOW_RS123(0 << 12) (0 << 12)
3975#define SLOW_RS23(1 << 12) (1 << 12)
3976#define SLOW_RS3(2 << 12) (2 << 12)
3977#define NORMAL_RS123(3 << 12) (3 << 12)
3978#define RCMODE_TIMEOUT(1 << 11) (1 << 11) /* 0 is eval interval method */
3979#define IMPROMOEN(1 << 10) (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3980#define RCENTSYNC(1 << 9) (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3981#define STATELOCK(1 << 7) (1 << 7) /* locked to rs_cstate if 0 */
3982#define RS_CSTATE_MASK(3 << 4) (3 << 4)
3983#define RS_CSTATE_C367_RS1(0 << 4) (0 << 4)
3984#define RS_CSTATE_C36_RS1_C7_RS2(1 << 4) (1 << 4)
3985#define RS_CSTATE_RSVD(2 << 4) (2 << 4)
3986#define RS_CSTATE_C367_RS2(3 << 4) (3 << 4)
3987#define REDSAVES(1 << 3) (1 << 3) /* no context save if was idle during rs0 */
3988#define REDRESTORES(1 << 2) (1 << 2) /* no restore if was idle during rs0 */
3989#define VIDCTL((const i915_reg_t){ .reg = (0x111c0) }) _MMIO(0x111c0)((const i915_reg_t){ .reg = (0x111c0) })
3990#define VIDSTS((const i915_reg_t){ .reg = (0x111c8) }) _MMIO(0x111c8)((const i915_reg_t){ .reg = (0x111c8) })
3991#define VIDSTART((const i915_reg_t){ .reg = (0x111cc) }) _MMIO(0x111cc)((const i915_reg_t){ .reg = (0x111cc) }) /* 8 bits */
3992#define MEMSTAT_ILK((const i915_reg_t){ .reg = (0x111f8) }) _MMIO(0x111f8)((const i915_reg_t){ .reg = (0x111f8) })
3993#define MEMSTAT_VID_MASK0x7f00 0x7f00
3994#define MEMSTAT_VID_SHIFT8 8
3995#define MEMSTAT_PSTATE_MASK0x00f8 0x00f8
3996#define MEMSTAT_PSTATE_SHIFT3 3
3997#define MEMSTAT_MON_ACTV(1 << 2) (1 << 2)
3998#define MEMSTAT_SRC_CTL_MASK0x0003 0x0003
3999#define MEMSTAT_SRC_CTL_CORE0 0
4000#define MEMSTAT_SRC_CTL_TRB1 1
4001#define MEMSTAT_SRC_CTL_THM2 2
4002#define MEMSTAT_SRC_CTL_STDBY3 3
4003#define RCPREVBSYTUPAVG((const i915_reg_t){ .reg = (0x113b8) }) _MMIO(0x113b8)((const i915_reg_t){ .reg = (0x113b8) })
4004#define RCPREVBSYTDNAVG((const i915_reg_t){ .reg = (0x113bc) }) _MMIO(0x113bc)((const i915_reg_t){ .reg = (0x113bc) })
4005#define PMMISC((const i915_reg_t){ .reg = (0x11214) }) _MMIO(0x11214)((const i915_reg_t){ .reg = (0x11214) })
4006#define MCPPCE_EN(1 << 0) (1 << 0) /* enable PM_MSG from PCH->MPC */
4007#define SDEW((const i915_reg_t){ .reg = (0x1124c) }) _MMIO(0x1124c)((const i915_reg_t){ .reg = (0x1124c) })
4008#define CSIEW0((const i915_reg_t){ .reg = (0x11250) }) _MMIO(0x11250)((const i915_reg_t){ .reg = (0x11250) })
4009#define CSIEW1((const i915_reg_t){ .reg = (0x11254) }) _MMIO(0x11254)((const i915_reg_t){ .reg = (0x11254) })
4010#define CSIEW2((const i915_reg_t){ .reg = (0x11258) }) _MMIO(0x11258)((const i915_reg_t){ .reg = (0x11258) })
4011#define PEW(i)((const i915_reg_t){ .reg = (0x1125c + (i) * 4) }) _MMIO(0x1125c + (i) * 4)((const i915_reg_t){ .reg = (0x1125c + (i) * 4) }) /* 5 registers */
4012#define DEW(i)((const i915_reg_t){ .reg = (0x11270 + (i) * 4) }) _MMIO(0x11270 + (i) * 4)((const i915_reg_t){ .reg = (0x11270 + (i) * 4) }) /* 3 registers */
4013#define MCHAFE((const i915_reg_t){ .reg = (0x112c0) }) _MMIO(0x112c0)((const i915_reg_t){ .reg = (0x112c0) })
4014#define CSIEC((const i915_reg_t){ .reg = (0x112e0) }) _MMIO(0x112e0)((const i915_reg_t){ .reg = (0x112e0) })
4015#define DMIEC((const i915_reg_t){ .reg = (0x112e4) }) _MMIO(0x112e4)((const i915_reg_t){ .reg = (0x112e4) })
4016#define DDREC((const i915_reg_t){ .reg = (0x112e8) }) _MMIO(0x112e8)((const i915_reg_t){ .reg = (0x112e8) })
4017#define PEG0EC((const i915_reg_t){ .reg = (0x112ec) }) _MMIO(0x112ec)((const i915_reg_t){ .reg = (0x112ec) })
4018#define PEG1EC((const i915_reg_t){ .reg = (0x112f0) }) _MMIO(0x112f0)((const i915_reg_t){ .reg = (0x112f0) })
4019#define GFXEC((const i915_reg_t){ .reg = (0x112f4) }) _MMIO(0x112f4)((const i915_reg_t){ .reg = (0x112f4) })
4020#define RPPREVBSYTUPAVG((const i915_reg_t){ .reg = (0x113b8) }) _MMIO(0x113b8)((const i915_reg_t){ .reg = (0x113b8) })
4021#define RPPREVBSYTDNAVG((const i915_reg_t){ .reg = (0x113bc) }) _MMIO(0x113bc)((const i915_reg_t){ .reg = (0x113bc) })
4022#define ECR((const i915_reg_t){ .reg = (0x11600) }) _MMIO(0x11600)((const i915_reg_t){ .reg = (0x11600) })
4023#define ECR_GPFE(1 << 31) (1 << 31)
4024#define ECR_IMONE(1 << 30) (1 << 30)
4025#define ECR_CAP_MASK0x0000001f 0x0000001f /* Event range, 0-31 */
4026#define OGW0((const i915_reg_t){ .reg = (0x11608) }) _MMIO(0x11608)((const i915_reg_t){ .reg = (0x11608) })
4027#define OGW1((const i915_reg_t){ .reg = (0x1160c) }) _MMIO(0x1160c)((const i915_reg_t){ .reg = (0x1160c) })
4028#define EG0((const i915_reg_t){ .reg = (0x11610) }) _MMIO(0x11610)((const i915_reg_t){ .reg = (0x11610) })
4029#define EG1((const i915_reg_t){ .reg = (0x11614) }) _MMIO(0x11614)((const i915_reg_t){ .reg = (0x11614) })
4030#define EG2((const i915_reg_t){ .reg = (0x11618) }) _MMIO(0x11618)((const i915_reg_t){ .reg = (0x11618) })
4031#define EG3((const i915_reg_t){ .reg = (0x1161c) }) _MMIO(0x1161c)((const i915_reg_t){ .reg = (0x1161c) })
4032#define EG4((const i915_reg_t){ .reg = (0x11620) }) _MMIO(0x11620)((const i915_reg_t){ .reg = (0x11620) })
4033#define EG5((const i915_reg_t){ .reg = (0x11624) }) _MMIO(0x11624)((const i915_reg_t){ .reg = (0x11624) })
4034#define EG6((const i915_reg_t){ .reg = (0x11628) }) _MMIO(0x11628)((const i915_reg_t){ .reg = (0x11628) })
4035#define EG7((const i915_reg_t){ .reg = (0x1162c) }) _MMIO(0x1162c)((const i915_reg_t){ .reg = (0x1162c) })
4036#define PXW(i)((const i915_reg_t){ .reg = (0x11664 + (i) * 4) }) _MMIO(0x11664 + (i) * 4)((const i915_reg_t){ .reg = (0x11664 + (i) * 4) }) /* 4 registers */
4037#define PXWL(i)((const i915_reg_t){ .reg = (0x11680 + (i) * 8) }) _MMIO(0x11680 + (i) * 8)((const i915_reg_t){ .reg = (0x11680 + (i) * 8) }) /* 8 registers */
4038#define LCFUSE02((const i915_reg_t){ .reg = (0x116c0) }) _MMIO(0x116c0)((const i915_reg_t){ .reg = (0x116c0) })
4039#define LCFUSE_HIV_MASK0x000000ff 0x000000ff
4040#define CSIPLL0((const i915_reg_t){ .reg = (0x12c10) }) _MMIO(0x12c10)((const i915_reg_t){ .reg = (0x12c10) })
4041#define DDRMPLL1((const i915_reg_t){ .reg = (0X12c20) }) _MMIO(0X12c20)((const i915_reg_t){ .reg = (0X12c20) })
4042#define PEG_BAND_GAP_DATA((const i915_reg_t){ .reg = (0x14d68) }) _MMIO(0x14d68)((const i915_reg_t){ .reg = (0x14d68) })
4043
4044#define GEN6_GT_THREAD_STATUS_REG((const i915_reg_t){ .reg = (0x13805c) }) _MMIO(0x13805c)((const i915_reg_t){ .reg = (0x13805c) })
4045#define GEN6_GT_THREAD_STATUS_CORE_MASK0x7 0x7
4046
4047#define GEN6_GT_PERF_STATUS((const i915_reg_t){ .reg = (0x140000 + 0x5948) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)((const i915_reg_t){ .reg = (0x140000 + 0x5948) })
4048#define BXT_GT_PERF_STATUS((const i915_reg_t){ .reg = (0x140000 + 0x7070) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)((const i915_reg_t){ .reg = (0x140000 + 0x7070) })
4049#define GEN6_RP_STATE_LIMITS((const i915_reg_t){ .reg = (0x140000 + 0x5994) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)((const i915_reg_t){ .reg = (0x140000 + 0x5994) })
4050#define GEN6_RP_STATE_CAP((const i915_reg_t){ .reg = (0x140000 + 0x5998) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)((const i915_reg_t){ .reg = (0x140000 + 0x5998) })
4051#define BXT_RP_STATE_CAP((const i915_reg_t){ .reg = (0x138170) }) _MMIO(0x138170)((const i915_reg_t){ .reg = (0x138170) })
4052#define GEN9_RP_STATE_LIMITS((const i915_reg_t){ .reg = (0x138148) }) _MMIO(0x138148)((const i915_reg_t){ .reg = (0x138148) })
4053
4054/*
4055 * Logical Context regs
4056 */
4057#define CCID(base)((const i915_reg_t){ .reg = ((base) + 0x180) }) _MMIO((base) + 0x180)((const i915_reg_t){ .reg = ((base) + 0x180) })
4058#define CCID_EN(1UL << (0)) BIT(0)(1UL << (0))
4059#define CCID_EXTENDED_STATE_RESTORE(1UL << (2)) BIT(2)(1UL << (2))
4060#define CCID_EXTENDED_STATE_SAVE(1UL << (3)) BIT(3)(1UL << (3))
4061/*
4062 * Notes on SNB/IVB/VLV context size:
4063 * - Power context is saved elsewhere (LLC or stolen)
4064 * - Ring/execlist context is saved on SNB, not on IVB
4065 * - Extended context size already includes render context size
4066 * - We always need to follow the extended context size.
4067 * SNB BSpec has comments indicating that we should use the
4068 * render context size instead if execlists are disabled, but
4069 * based on empirical testing that's just nonsense.
4070 * - Pipelined/VF state is saved on SNB/IVB respectively
4071 * - GT1 size just indicates how much of render context
4072 * doesn't need saving on GT1
4073 */
4074#define CXT_SIZE((const i915_reg_t){ .reg = (0x21a0) }) _MMIO(0x21a0)((const i915_reg_t){ .reg = (0x21a0) })
4075#define GEN6_CXT_POWER_SIZE(cxt_reg)(((cxt_reg) >> 24) & 0x3f) (((cxt_reg) >> 24) & 0x3f)
4076#define GEN6_CXT_RING_SIZE(cxt_reg)(((cxt_reg) >> 18) & 0x3f) (((cxt_reg) >> 18) & 0x3f)
4077#define GEN6_CXT_RENDER_SIZE(cxt_reg)(((cxt_reg) >> 12) & 0x3f) (((cxt_reg) >> 12) & 0x3f)
4078#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)(((cxt_reg) >> 6) & 0x3f) (((cxt_reg) >> 6) & 0x3f)
4079#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)(((cxt_reg) >> 0) & 0x3f) (((cxt_reg) >> 0) & 0x3f)
4080#define GEN6_CXT_TOTAL_SIZE(cxt_reg)((((cxt_reg) >> 18) & 0x3f) + (((cxt_reg) >> 6
) & 0x3f) + (((cxt_reg) >> 0) & 0x3f)) (GEN6_CXT_RING_SIZE(cxt_reg)(((cxt_reg) >> 18) & 0x3f) + \
4081 GEN6_CXT_EXTENDED_SIZE(cxt_reg)(((cxt_reg) >> 6) & 0x3f) + \
4082 GEN6_CXT_PIPELINE_SIZE(cxt_reg)(((cxt_reg) >> 0) & 0x3f))
4083#define GEN7_CXT_SIZE((const i915_reg_t){ .reg = (0x21a8) }) _MMIO(0x21a8)((const i915_reg_t){ .reg = (0x21a8) })
4084#define GEN7_CXT_POWER_SIZE(ctx_reg)(((ctx_reg) >> 25) & 0x7f) (((ctx_reg) >> 25) & 0x7f)
4085#define GEN7_CXT_RING_SIZE(ctx_reg)(((ctx_reg) >> 22) & 0x7) (((ctx_reg) >> 22) & 0x7)
4086#define GEN7_CXT_RENDER_SIZE(ctx_reg)(((ctx_reg) >> 16) & 0x3f) (((ctx_reg) >> 16) & 0x3f)
4087#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)(((ctx_reg) >> 9) & 0x7f) (((ctx_reg) >> 9) & 0x7f)
4088#define GEN7_CXT_GT1_SIZE(ctx_reg)(((ctx_reg) >> 6) & 0x7) (((ctx_reg) >> 6) & 0x7)
4089#define GEN7_CXT_VFSTATE_SIZE(ctx_reg)(((ctx_reg) >> 0) & 0x3f) (((ctx_reg) >> 0) & 0x3f)
4090#define GEN7_CXT_TOTAL_SIZE(ctx_reg)((((ctx_reg) >> 9) & 0x7f) + (((ctx_reg) >> 0
) & 0x3f)) (GEN7_CXT_EXTENDED_SIZE(ctx_reg)(((ctx_reg) >> 9) & 0x7f) + \
4091 GEN7_CXT_VFSTATE_SIZE(ctx_reg)(((ctx_reg) >> 0) & 0x3f))
4092
4093enum {
4094 INTEL_ADVANCED_CONTEXT = 0,
4095 INTEL_LEGACY_32B_CONTEXT,
4096 INTEL_ADVANCED_AD_CONTEXT,
4097 INTEL_LEGACY_64B_CONTEXT
4098};
4099
4100enum {
4101 FAULT_AND_HANG = 0,
4102 FAULT_AND_HALT, /* Debug only */
4103 FAULT_AND_STREAM,
4104 FAULT_AND_CONTINUE /* Unsupported */
4105};
4106
4107#define GEN8_CTX_VALID(1 << 0) (1 << 0)
4108#define GEN8_CTX_FORCE_PD_RESTORE(1 << 1) (1 << 1)
4109#define GEN8_CTX_FORCE_RESTORE(1 << 2) (1 << 2)
4110#define GEN8_CTX_L3LLC_COHERENT(1 << 5) (1 << 5)
4111#define GEN8_CTX_PRIVILEGE(1 << 8) (1 << 8)
4112#define GEN8_CTX_ADDRESSING_MODE_SHIFT3 3
4113
4114#define GEN8_CTX_ID_SHIFT32 32
4115#define GEN8_CTX_ID_WIDTH21 21
4116#define GEN11_SW_CTX_ID_SHIFT37 37
4117#define GEN11_SW_CTX_ID_WIDTH11 11
4118#define GEN11_ENGINE_CLASS_SHIFT61 61
4119#define GEN11_ENGINE_CLASS_WIDTH3 3
4120#define GEN11_ENGINE_INSTANCE_SHIFT48 48
4121#define GEN11_ENGINE_INSTANCE_WIDTH6 6
4122
4123#define CHV_CLK_CTL1((const i915_reg_t){ .reg = (0x101100) }) _MMIO(0x101100)((const i915_reg_t){ .reg = (0x101100) })
4124#define VLV_CLK_CTL2((const i915_reg_t){ .reg = (0x101104) }) _MMIO(0x101104)((const i915_reg_t){ .reg = (0x101104) })
4125#define CLK_CTL2_CZCOUNT_30NS_SHIFT28 28
4126
4127/*
4128 * Overlay regs
4129 */
4130
4131#define OVADD((const i915_reg_t){ .reg = (0x30000) }) _MMIO(0x30000)((const i915_reg_t){ .reg = (0x30000) })
4132#define DOVSTA((const i915_reg_t){ .reg = (0x30008) }) _MMIO(0x30008)((const i915_reg_t){ .reg = (0x30008) })
4133#define OC_BUF(0x3 << 20) (0x3 << 20)
4134#define OGAMC5((const i915_reg_t){ .reg = (0x30010) }) _MMIO(0x30010)((const i915_reg_t){ .reg = (0x30010) })
4135#define OGAMC4((const i915_reg_t){ .reg = (0x30014) }) _MMIO(0x30014)((const i915_reg_t){ .reg = (0x30014) })
4136#define OGAMC3((const i915_reg_t){ .reg = (0x30018) }) _MMIO(0x30018)((const i915_reg_t){ .reg = (0x30018) })
4137#define OGAMC2((const i915_reg_t){ .reg = (0x3001c) }) _MMIO(0x3001c)((const i915_reg_t){ .reg = (0x3001c) })
4138#define OGAMC1((const i915_reg_t){ .reg = (0x30020) }) _MMIO(0x30020)((const i915_reg_t){ .reg = (0x30020) })
4139#define OGAMC0((const i915_reg_t){ .reg = (0x30024) }) _MMIO(0x30024)((const i915_reg_t){ .reg = (0x30024) })
4140
4141/*
4142 * GEN9 clock gating regs
4143 */
4144#define GEN9_CLKGATE_DIS_0((const i915_reg_t){ .reg = (0x46530) }) _MMIO(0x46530)((const i915_reg_t){ .reg = (0x46530) })
4145#define DARBF_GATING_DIS(1 << 27) (1 << 27)
4146#define PWM2_GATING_DIS(1 << 14) (1 << 14)
4147#define PWM1_GATING_DIS(1 << 13) (1 << 13)
4148
4149#define GEN9_CLKGATE_DIS_3((const i915_reg_t){ .reg = (0x46538) }) _MMIO(0x46538)((const i915_reg_t){ .reg = (0x46538) })
4150#define TGL_VRH_GATING_DIS((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4151
4152#define GEN9_CLKGATE_DIS_4((const i915_reg_t){ .reg = (0x4653C) }) _MMIO(0x4653C)((const i915_reg_t){ .reg = (0x4653C) })
4153#define BXT_GMBUS_GATING_DIS(1 << 14) (1 << 14)
4154
4155#define _CLKGATE_DIS_PSL_A0x46520 0x46520
4156#define _CLKGATE_DIS_PSL_B0x46524 0x46524
4157#define _CLKGATE_DIS_PSL_C0x46528 0x46528
4158#define DUPS1_GATING_DIS(1 << 15) (1 << 15)
4159#define DUPS2_GATING_DIS(1 << 19) (1 << 19)
4160#define DUPS3_GATING_DIS(1 << 23) (1 << 23)
4161#define DPF_GATING_DIS(1 << 10) (1 << 10)
4162#define DPF_RAM_GATING_DIS(1 << 9) (1 << 9)
4163#define DPFR_GATING_DIS(1 << 8) (1 << 8)
4164
4165#define CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) }) \
4166 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
4167
4168/*
4169 * GEN10 clock gating regs
4170 */
4171#define SLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x94d4) }) _MMIO(0x94d4)((const i915_reg_t){ .reg = (0x94d4) })
4172#define SARBUNIT_CLKGATE_DIS(1 << 5) (1 << 5)
4173#define RCCUNIT_CLKGATE_DIS(1 << 7) (1 << 7)
4174#define MSCUNIT_CLKGATE_DIS(1 << 10) (1 << 10)
4175#define L3_CLKGATE_DIS((u32)((1UL << (16)) + 0)) REG_BIT(16)((u32)((1UL << (16)) + 0))
4176#define L3_CR2X_CLKGATE_DIS((u32)((1UL << (17)) + 0)) REG_BIT(17)((u32)((1UL << (17)) + 0))
4177
4178#define SUBSLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9524) }) _MMIO(0x9524)((const i915_reg_t){ .reg = (0x9524) })
4179#define GWUNIT_CLKGATE_DIS(1 << 16) (1 << 16)
4180
4181#define SUBSLICE_UNIT_LEVEL_CLKGATE2((const i915_reg_t){ .reg = (0x9528) }) _MMIO(0x9528)((const i915_reg_t){ .reg = (0x9528) })
4182#define CPSSUNIT_CLKGATE_DIS((u32)((1UL << (9)) + 0)) REG_BIT(9)((u32)((1UL << (9)) + 0))
4183
4184#define UNSLICE_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9434) }) _MMIO(0x9434)((const i915_reg_t){ .reg = (0x9434) })
4185#define VFUNIT_CLKGATE_DIS((u32)((1UL << (20)) + 0)) REG_BIT(20)((u32)((1UL << (20)) + 0))
4186#define HSUNIT_CLKGATE_DIS((u32)((1UL << (8)) + 0)) REG_BIT(8)((u32)((1UL << (8)) + 0))
4187#define VSUNIT_CLKGATE_DIS((u32)((1UL << (3)) + 0)) REG_BIT(3)((u32)((1UL << (3)) + 0))
4188
4189#define UNSLICE_UNIT_LEVEL_CLKGATE2((const i915_reg_t){ .reg = (0x94e4) }) _MMIO(0x94e4)((const i915_reg_t){ .reg = (0x94e4) })
4190#define VSUNIT_CLKGATE_DIS_TGL((u32)((1UL << (19)) + 0)) REG_BIT(19)((u32)((1UL << (19)) + 0))
4191#define PSDUNIT_CLKGATE_DIS((u32)((1UL << (5)) + 0)) REG_BIT(5)((u32)((1UL << (5)) + 0))
4192
4193#define INF_UNIT_LEVEL_CLKGATE((const i915_reg_t){ .reg = (0x9560) }) _MMIO(0x9560)((const i915_reg_t){ .reg = (0x9560) })
4194#define CGPSF_CLKGATE_DIS(1 << 3) (1 << 3)
4195
4196/*
4197 * Display engine regs
4198 */
4199
4200/* Pipe A CRC regs */
4201#define _PIPE_CRC_CTL_A0x60050 0x60050
4202#define PIPE_CRC_ENABLE(1 << 31) (1 << 31)
4203/* skl+ source selection */
4204#define PIPE_CRC_SOURCE_PLANE_1_SKL(0 << 28) (0 << 28)
4205#define PIPE_CRC_SOURCE_PLANE_2_SKL(2 << 28) (2 << 28)
4206#define PIPE_CRC_SOURCE_DMUX_SKL(4 << 28) (4 << 28)
4207#define PIPE_CRC_SOURCE_PLANE_3_SKL(6 << 28) (6 << 28)
4208#define PIPE_CRC_SOURCE_PLANE_4_SKL(7 << 28) (7 << 28)
4209#define PIPE_CRC_SOURCE_PLANE_5_SKL(5 << 28) (5 << 28)
4210#define PIPE_CRC_SOURCE_PLANE_6_SKL(3 << 28) (3 << 28)
4211#define PIPE_CRC_SOURCE_PLANE_7_SKL(1 << 28) (1 << 28)
4212/* ivb+ source selection */
4213#define PIPE_CRC_SOURCE_PRIMARY_IVB(0 << 29) (0 << 29)
4214#define PIPE_CRC_SOURCE_SPRITE_IVB(1 << 29) (1 << 29)
4215#define PIPE_CRC_SOURCE_PF_IVB(2 << 29) (2 << 29)
4216/* ilk+ source selection */
4217#define PIPE_CRC_SOURCE_PRIMARY_ILK(0 << 28) (0 << 28)
4218#define PIPE_CRC_SOURCE_SPRITE_ILK(1 << 28) (1 << 28)
4219#define PIPE_CRC_SOURCE_PIPE_ILK(2 << 28) (2 << 28)
4220/* embedded DP port on the north display block, reserved on ivb */
4221#define PIPE_CRC_SOURCE_PORT_A_ILK(4 << 28) (4 << 28)
4222#define PIPE_CRC_SOURCE_FDI_ILK(5 << 28) (5 << 28) /* reserved on ivb */
4223/* vlv source selection */
4224#define PIPE_CRC_SOURCE_PIPE_VLV(0 << 27) (0 << 27)
4225#define PIPE_CRC_SOURCE_HDMIB_VLV(1 << 27) (1 << 27)
4226#define PIPE_CRC_SOURCE_HDMIC_VLV(2 << 27) (2 << 27)
4227/* with DP port the pipe source is invalid */
4228#define PIPE_CRC_SOURCE_DP_D_VLV(3 << 27) (3 << 27)
4229#define PIPE_CRC_SOURCE_DP_B_VLV(6 << 27) (6 << 27)
4230#define PIPE_CRC_SOURCE_DP_C_VLV(7 << 27) (7 << 27)
4231/* gen3+ source selection */
4232#define PIPE_CRC_SOURCE_PIPE_I9XX(0 << 28) (0 << 28)
4233#define PIPE_CRC_SOURCE_SDVOB_I9XX(1 << 28) (1 << 28)
4234#define PIPE_CRC_SOURCE_SDVOC_I9XX(2 << 28) (2 << 28)
4235/* with DP/TV port the pipe source is invalid */
4236#define PIPE_CRC_SOURCE_DP_D_G4X(3 << 28) (3 << 28)
4237#define PIPE_CRC_SOURCE_TV_PRE(4 << 28) (4 << 28)
4238#define PIPE_CRC_SOURCE_TV_POST(5 << 28) (5 << 28)
4239#define PIPE_CRC_SOURCE_DP_B_G4X(6 << 28) (6 << 28)
4240#define PIPE_CRC_SOURCE_DP_C_G4X(7 << 28) (7 << 28)
4241/* gen2 doesn't have source selection bits */
4242#define PIPE_CRC_INCLUDE_BORDER_I8XX(1 << 30) (1 << 30)
4243
4244#define _PIPE_CRC_RES_1_A_IVB0x60064 0x60064
4245#define _PIPE_CRC_RES_2_A_IVB0x60068 0x60068
4246#define _PIPE_CRC_RES_3_A_IVB0x6006c 0x6006c
4247#define _PIPE_CRC_RES_4_A_IVB0x60070 0x60070
4248#define _PIPE_CRC_RES_5_A_IVB0x60074 0x60074
4249
4250#define _PIPE_CRC_RES_RED_A0x60060 0x60060
4251#define _PIPE_CRC_RES_GREEN_A0x60064 0x60064
4252#define _PIPE_CRC_RES_BLUE_A0x60068 0x60068
4253#define _PIPE_CRC_RES_RES1_A_I9150x6006c 0x6006c
4254#define _PIPE_CRC_RES_RES2_A_G4X0x60080 0x60080
4255
4256/* Pipe B CRC regs */
4257#define _PIPE_CRC_RES_1_B_IVB0x61064 0x61064
4258#define _PIPE_CRC_RES_2_B_IVB0x61068 0x61068
4259#define _PIPE_CRC_RES_3_B_IVB0x6106c 0x6106c
4260#define _PIPE_CRC_RES_4_B_IVB0x61070 0x61070
4261#define _PIPE_CRC_RES_5_B_IVB0x61074 0x61074
4262
4263#define PIPE_CRC_CTL(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60050) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60050) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4264#define PIPE_CRC_RES_1_IVB(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60064) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60064) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4265#define PIPE_CRC_RES_2_IVB(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60068) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60068) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4266#define PIPE_CRC_RES_3_IVB(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6006c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6006c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4267#define PIPE_CRC_RES_4_IVB(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60070) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60070) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4268#define PIPE_CRC_RES_5_IVB(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60074) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60074) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4269
4270#define PIPE_CRC_RES_RED(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60060) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60060) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4271#define PIPE_CRC_RES_GREEN(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60064) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60064) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4272#define PIPE_CRC_RES_BLUE(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60068) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60068) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4273#define PIPE_CRC_RES_RES1_I915(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6006c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6006c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4274#define PIPE_CRC_RES_RES2_G4X(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60080) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60080) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4275
4276/* Pipe A timing regs */
4277#define _HTOTAL_A0x60000 0x60000
4278#define _HBLANK_A0x60004 0x60004
4279#define _HSYNC_A0x60008 0x60008
4280#define _VTOTAL_A0x6000c 0x6000c
4281#define _VBLANK_A0x60010 0x60010
4282#define _VSYNC_A0x60014 0x60014
4283#define _EXITLINE_A0x60018 0x60018
4284#define _PIPEASRC0x6001c 0x6001c
4285#define _BCLRPAT_A0x60020 0x60020
4286#define _VSYNCSHIFT_A0x60028 0x60028
4287#define _PIPE_MULT_A0x6002c 0x6002c
4288
4289/* Pipe B timing regs */
4290#define _HTOTAL_B0x61000 0x61000
4291#define _HBLANK_B0x61004 0x61004
4292#define _HSYNC_B0x61008 0x61008
4293#define _VTOTAL_B0x6100c 0x6100c
4294#define _VBLANK_B0x61010 0x61010
4295#define _VSYNC_B0x61014 0x61014
4296#define _PIPEBSRC0x6101c 0x6101c
4297#define _BCLRPAT_B0x61020 0x61020
4298#define _VSYNCSHIFT_B0x61028 0x61028
4299#define _PIPE_MULT_B0x6102c 0x6102c
4300
4301/* DSI 0 timing regs */
4302#define _HTOTAL_DSI00x6b000 0x6b000
4303#define _HSYNC_DSI00x6b008 0x6b008
4304#define _VTOTAL_DSI00x6b00c 0x6b00c
4305#define _VSYNC_DSI00x6b014 0x6b014
4306#define _VSYNCSHIFT_DSI00x6b028 0x6b028
4307
4308/* DSI 1 timing regs */
4309#define _HTOTAL_DSI10x6b800 0x6b800
4310#define _HSYNC_DSI10x6b808 0x6b808
4311#define _VTOTAL_DSI10x6b80c 0x6b80c
4312#define _VSYNC_DSI10x6b814 0x6b814
4313#define _VSYNCSHIFT_DSI10x6b828 0x6b828
4314
4315#define TRANSCODER_A_OFFSET0x60000 0x60000
4316#define TRANSCODER_B_OFFSET0x61000 0x61000
4317#define TRANSCODER_C_OFFSET0x62000 0x62000
4318#define CHV_TRANSCODER_C_OFFSET0x63000 0x63000
4319#define TRANSCODER_D_OFFSET0x63000 0x63000
4320#define TRANSCODER_EDP_OFFSET0x6f000 0x6f000
4321#define TRANSCODER_DSI0_OFFSET0x6b000 0x6b000
4322#define TRANSCODER_DSI1_OFFSET0x6b800 0x6b800
4323
4324#define HTOTAL(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60000) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _HTOTAL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60000) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4325#define HBLANK(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60004) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _HBLANK_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60004) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4326#define HSYNC(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60008) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSYNC_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60008) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4327#define VTOTAL(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6000c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _VTOTAL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6000c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4328#define VBLANK(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60010) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _VBLANK_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60010) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4329#define VSYNC(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60014) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _VSYNC_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60014) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4330#define BCLRPAT(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60020) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _BCLRPAT_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60020) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4331#define VSYNCSHIFT(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60028) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60028) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4332#define PIPESRC(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _PIPEASRC)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4333#define PIPE_MULT(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6002c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _PIPE_MULT_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6002c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4334
4335#define EXITLINE(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60018) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _EXITLINE_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60018) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4336#define EXITLINE_ENABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4337#define EXITLINE_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(12, 0)((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0))
4338#define EXITLINE_SHIFT0 0
4339
4340/* VRR registers */
4341#define _TRANS_VRR_CTL_A0x60420 0x60420
4342#define _TRANS_VRR_CTL_B0x61420 0x61420
4343#define _TRANS_VRR_CTL_C0x62420 0x62420
4344#define _TRANS_VRR_CTL_D0x63420 0x63420
4345#define TRANS_VRR_CTL(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60420) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60420) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4346#define VRR_CTL_VRR_ENABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4347#define VRR_CTL_IGN_MAX_SHIFT((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
4348#define VRR_CTL_FLIP_LINE_EN((u32)((1UL << (29)) + 0)) REG_BIT(29)((u32)((1UL << (29)) + 0))
4349#define VRR_CTL_LINE_COUNT_MASK((u32)((((~0UL) >> (64 - (10) - 1)) & ((~0UL) <<
(3))) + 0)) REG_GENMASK(10, 3)((u32)((((~0UL) >> (64 - (10) - 1)) & ((~0UL) <<
(3))) + 0))
4350#define VRR_CTL_SW_FULLLINE_COUNT((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
4351
4352#define _TRANS_VRR_VMAX_A0x60424 0x60424
4353#define _TRANS_VRR_VMAX_B0x61424 0x61424
4354#define _TRANS_VRR_VMAX_C0x62424 0x62424
4355#define _TRANS_VRR_VMAX_D0x63424 0x63424
4356#define TRANS_VRR_VMAX(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60424) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60424) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4357#define VRR_VMAX_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(19, 0)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0))
4358
4359#define _TRANS_VRR_VMIN_A0x60434 0x60434
4360#define _TRANS_VRR_VMIN_B0x61434 0x61434
4361#define _TRANS_VRR_VMIN_C0x62434 0x62434
4362#define _TRANS_VRR_VMIN_D0x63434 0x63434
4363#define TRANS_VRR_VMIN(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60434) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60434) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4364#define VRR_VMIN_MASK((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(15, 0)((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0))) + 0))
4365
4366#define _TRANS_VRR_VMAXSHIFT_A0x60428 0x60428
4367#define _TRANS_VRR_VMAXSHIFT_B0x61428 0x61428
4368#define _TRANS_VRR_VMAXSHIFT_C0x62428 0x62428
4369#define _TRANS_VRR_VMAXSHIFT_D0x63428 0x63428
4370#define TRANS_VRR_VMAXSHIFT(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60428) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60428) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4371 _TRANS_VRR_VMAXSHIFT_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60428) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4372#define VRR_VMAXSHIFT_DEC_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(29, 16)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(16))) + 0))
4373#define VRR_VMAXSHIFT_DEC((u32)((1UL << (16)) + 0)) REG_BIT(16)((u32)((1UL << (16)) + 0))
4374#define VRR_VMAXSHIFT_INC_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(12, 0)((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0))
4375
4376#define _TRANS_VRR_STATUS_A0x6042C 0x6042C
4377#define _TRANS_VRR_STATUS_B0x6142C 0x6142C
4378#define _TRANS_VRR_STATUS_C0x6242C 0x6242C
4379#define _TRANS_VRR_STATUS_D0x6342C 0x6342C
4380#define TRANS_VRR_STATUS(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6042C) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6042C) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4381#define VRR_STATUS_VMAX_REACHED((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4382#define VRR_STATUS_NOFLIP_TILL_BNDR((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
4383#define VRR_STATUS_FLIP_BEF_BNDR((u32)((1UL << (29)) + 0)) REG_BIT(29)((u32)((1UL << (29)) + 0))
4384#define VRR_STATUS_NO_FLIP_FRAME((u32)((1UL << (28)) + 0)) REG_BIT(28)((u32)((1UL << (28)) + 0))
4385#define VRR_STATUS_VRR_EN_LIVE((u32)((1UL << (27)) + 0)) REG_BIT(27)((u32)((1UL << (27)) + 0))
4386#define VRR_STATUS_FLIPS_SERVICED((u32)((1UL << (26)) + 0)) REG_BIT(26)((u32)((1UL << (26)) + 0))
4387#define VRR_STATUS_VBLANK_MASK((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0)) REG_GENMASK(22, 20)((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))
4388#define STATUS_FSM_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4389#define STATUS_FSM_WAIT_TILL_FDB((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4390#define STATUS_FSM_WAIT_TILL_FS((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4391#define STATUS_FSM_WAIT_TILL_FLIP((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4392#define STATUS_FSM_PIPELINE_FILL((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(4) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(4) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4393#define STATUS_FSM_ACTIVE((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(5) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(5) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4394#define STATUS_FSM_LEGACY_VBLANK((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(6) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)((u32)((((typeof(((u32)((((~0UL) >> (64 - (22) - 1)) &
((~0UL) << (20))) + 0))))(6) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (22) - 1)) & ((~0UL) <<
(20))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (22
) - 1)) & ((~0UL) << (20))) + 0)))) + 0 + 0 + 0 + 0
))
4395
4396#define _TRANS_VRR_VTOTAL_PREV_A0x60480 0x60480
4397#define _TRANS_VRR_VTOTAL_PREV_B0x61480 0x61480
4398#define _TRANS_VRR_VTOTAL_PREV_C0x62480 0x62480
4399#define _TRANS_VRR_VTOTAL_PREV_D0x63480 0x63480
4400#define TRANS_VRR_VTOTAL_PREV(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60480) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60480) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4401 _TRANS_VRR_VTOTAL_PREV_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60480) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4402#define VRR_VTOTAL_FLIP_BEFR_BNDR((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4403#define VRR_VTOTAL_FLIP_AFTER_BNDR((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
4404#define VRR_VTOTAL_FLIP_AFTER_DBLBUF((u32)((1UL << (29)) + 0)) REG_BIT(29)((u32)((1UL << (29)) + 0))
4405#define VRR_VTOTAL_PREV_FRAME_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(19, 0)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0))
4406
4407#define _TRANS_VRR_FLIPLINE_A0x60438 0x60438
4408#define _TRANS_VRR_FLIPLINE_B0x61438 0x61438
4409#define _TRANS_VRR_FLIPLINE_C0x62438 0x62438
4410#define _TRANS_VRR_FLIPLINE_D0x63438 0x63438
4411#define TRANS_VRR_FLIPLINE(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60438) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, \((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60438) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4412 _TRANS_VRR_FLIPLINE_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60438) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4413#define VRR_FLIPLINE_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(19, 0)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0))
4414
4415#define _TRANS_VRR_STATUS2_A0x6043C 0x6043C
4416#define _TRANS_VRR_STATUS2_B0x6143C 0x6143C
4417#define _TRANS_VRR_STATUS2_C0x6243C 0x6243C
4418#define _TRANS_VRR_STATUS2_D0x6343C 0x6343C
4419#define TRANS_VRR_STATUS2(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6043C) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6043C) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4420#define VRR_STATUS2_VERT_LN_CNT_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(19, 0)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(0))) + 0))
4421
4422#define _TRANS_PUSH_A0x60A70 0x60A70
4423#define _TRANS_PUSH_B0x61A70 0x61A70
4424#define _TRANS_PUSH_C0x62A70 0x62A70
4425#define _TRANS_PUSH_D0x63A70 0x63A70
4426#define TRANS_PUSH(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60A70) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _TRANS_PUSH_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60A70) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4427#define TRANS_PUSH_EN((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4428#define TRANS_PUSH_SEND((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
4429
4430/*
4431 * HSW+ eDP PSR registers
4432 *
4433 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4434 * instance of it
4435 */
4436#define _HSW_EDP_PSR_BASE0x64800 0x64800
4437#define _SRD_CTL_A0x60800 0x60800
4438#define _SRD_CTL_EDP0x6f800 0x6f800
4439#define _PSR_ADJ(tran, reg)(((&(dev_priv)->__info)->trans_offsets[(tran)] - (&
(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (reg
) + ((&(dev_priv)->__info)->display_mmio_offset)) -
dev_priv->hsw_psr_mmio_adjust) (_TRANS2(tran, reg)((&(dev_priv)->__info)->trans_offsets[(tran)] - (&
(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (reg
) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)
4440#define EDP_PSR_CTL(tran)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) }) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })
4441#define EDP_PSR_ENABLE(1 << 31) (1 << 31)
4442#define BDW_PSR_SINGLE_FRAME(1 << 30) (1 << 30)
4443#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK(1 << 29) (1 << 29) /* SW can't modify */
4444#define EDP_PSR_LINK_STANDBY(1 << 27) (1 << 27)
4445#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK(3 << 25) (3 << 25)
4446#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES(0 << 25) (0 << 25)
4447#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES(1 << 25) (1 << 25)
4448#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES(2 << 25) (2 << 25)
4449#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES(3 << 25) (3 << 25)
4450#define EDP_PSR_MAX_SLEEP_TIME_SHIFT20 20
4451#define EDP_PSR_SKIP_AUX_EXIT(1 << 12) (1 << 12)
4452#define EDP_PSR_TP1_TP2_SEL(0 << 11) (0 << 11)
4453#define EDP_PSR_TP1_TP3_SEL(1 << 11) (1 << 11)
4454#define EDP_PSR_CRC_ENABLE(1 << 10) (1 << 10) /* BDW+ */
4455#define EDP_PSR_TP2_TP3_TIME_500us(0 << 8) (0 << 8)
4456#define EDP_PSR_TP2_TP3_TIME_100us(1 << 8) (1 << 8)
4457#define EDP_PSR_TP2_TP3_TIME_2500us(2 << 8) (2 << 8)
4458#define EDP_PSR_TP2_TP3_TIME_0us(3 << 8) (3 << 8)
4459#define EDP_PSR_TP4_TIME_0US(3 << 6) (3 << 6) /* ICL+ */
4460#define EDP_PSR_TP1_TIME_500us(0 << 4) (0 << 4)
4461#define EDP_PSR_TP1_TIME_100us(1 << 4) (1 << 4)
4462#define EDP_PSR_TP1_TIME_2500us(2 << 4) (2 << 4)
4463#define EDP_PSR_TP1_TIME_0us(3 << 4) (3 << 4)
4464#define EDP_PSR_IDLE_FRAME_SHIFT0 0
4465
4466/*
4467 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4468 * to transcoder and bits defined for each one as if using no shift (i.e. as if
4469 * it was for TRANSCODER_EDP)
4470 */
4471#define EDP_PSR_IMR((const i915_reg_t){ .reg = (0x64834) }) _MMIO(0x64834)((const i915_reg_t){ .reg = (0x64834) })
4472#define EDP_PSR_IIR((const i915_reg_t){ .reg = (0x64838) }) _MMIO(0x64838)((const i915_reg_t){ .reg = (0x64838) })
4473#define _PSR_IMR_A0x60814 0x60814
4474#define _PSR_IIR_A0x60818 0x60818
4475#define TRANS_PSR_IMR(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60814) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR_IMR_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60814) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4476#define TRANS_PSR_IIR(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60818) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR_IIR_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60818) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4477#define _EDP_PSR_TRANS_SHIFT(trans)((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A + 1)
* 8) ((trans) == TRANSCODER_EDP ? \
4478 0 : ((trans) - TRANSCODER_A + 1) * 8)
4479#define EDP_PSR_TRANS_MASK(trans)(0x7 << ((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A
+ 1) * 8)) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A + 1)
* 8))
4480#define EDP_PSR_ERROR(trans)(0x4 << ((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A
+ 1) * 8)) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A + 1)
* 8))
4481#define EDP_PSR_POST_EXIT(trans)(0x2 << ((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A
+ 1) * 8)) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A + 1)
* 8))
4482#define EDP_PSR_PRE_ENTRY(trans)(0x1 << ((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A
+ 1) * 8)) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)((trans) == TRANSCODER_EDP ? 0 : ((trans) - TRANSCODER_A + 1)
* 8))
4483
4484#define _SRD_AUX_CTL_A0x60810 0x60810
4485#define _SRD_AUX_CTL_EDP0x6f810 0x6f810
4486#define EDP_PSR_AUX_CTL(tran)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60810) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) }) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60810) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })
4487#define EDP_PSR_AUX_CTL_TIME_OUT_MASK(3 << 26) (3 << 26)
4488#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK(0x1f << 20) (0x1f << 20)
4489#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK(0xf << 16) (0xf << 16)
4490#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT(1 << 11) (1 << 11)
4491#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK(0x7ff) (0x7ff)
4492
4493#define _SRD_AUX_DATA_A0x60814 0x60814
4494#define _SRD_AUX_DATA_EDP0x6f814 0x6f814
4495#define EDP_PSR_AUX_DATA(tran, i)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60814) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust) + (
i) + 4) }) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60814) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust) + (
i) + 4) }) /* 5 registers */
4496
4497#define _SRD_STATUS_A0x60840 0x60840
4498#define _SRD_STATUS_EDP0x6f840 0x6f840
4499#define EDP_PSR_STATUS(tran)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60840) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) }) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60840) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })
4500#define EDP_PSR_STATUS_STATE_MASK(7 << 29) (7 << 29)
4501#define EDP_PSR_STATUS_STATE_SHIFT29 29
4502#define EDP_PSR_STATUS_STATE_IDLE(0 << 29) (0 << 29)
4503#define EDP_PSR_STATUS_STATE_SRDONACK(1 << 29) (1 << 29)
4504#define EDP_PSR_STATUS_STATE_SRDENT(2 << 29) (2 << 29)
4505#define EDP_PSR_STATUS_STATE_BUFOFF(3 << 29) (3 << 29)
4506#define EDP_PSR_STATUS_STATE_BUFON(4 << 29) (4 << 29)
4507#define EDP_PSR_STATUS_STATE_AUXACK(5 << 29) (5 << 29)
4508#define EDP_PSR_STATUS_STATE_SRDOFFACK(6 << 29) (6 << 29)
4509#define EDP_PSR_STATUS_LINK_MASK(3 << 26) (3 << 26)
4510#define EDP_PSR_STATUS_LINK_FULL_OFF(0 << 26) (0 << 26)
4511#define EDP_PSR_STATUS_LINK_FULL_ON(1 << 26) (1 << 26)
4512#define EDP_PSR_STATUS_LINK_STANDBY(2 << 26) (2 << 26)
4513#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT20 20
4514#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK0x1f 0x1f
4515#define EDP_PSR_STATUS_COUNT_SHIFT16 16
4516#define EDP_PSR_STATUS_COUNT_MASK0xf 0xf
4517#define EDP_PSR_STATUS_AUX_ERROR(1 << 15) (1 << 15)
4518#define EDP_PSR_STATUS_AUX_SENDING(1 << 12) (1 << 12)
4519#define EDP_PSR_STATUS_SENDING_IDLE(1 << 9) (1 << 9)
4520#define EDP_PSR_STATUS_SENDING_TP2_TP3(1 << 8) (1 << 8)
4521#define EDP_PSR_STATUS_SENDING_TP1(1 << 4) (1 << 4)
4522#define EDP_PSR_STATUS_IDLE_MASK0xf 0xf
4523
4524#define _SRD_PERF_CNT_A0x60844 0x60844
4525#define _SRD_PERF_CNT_EDP0x6f844 0x6f844
4526#define EDP_PSR_PERF_CNT(tran)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60844) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) }) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60844) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })
4527#define EDP_PSR_PERF_CNT_MASK0xffffff 0xffffff
4528
4529/* PSR_MASK on SKL+ */
4530#define _SRD_DEBUG_A0x60860 0x60860
4531#define _SRD_DEBUG_EDP0x6f860 0x6f860
4532#define EDP_PSR_DEBUG(tran)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60860) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) }) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60860) + ((&(dev_priv)->__info)->
display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })
4533#define EDP_PSR_DEBUG_MASK_MAX_SLEEP(1 << 28) (1 << 28)
4534#define EDP_PSR_DEBUG_MASK_LPSP(1 << 27) (1 << 27)
4535#define EDP_PSR_DEBUG_MASK_MEMUP(1 << 26) (1 << 26)
4536#define EDP_PSR_DEBUG_MASK_HPD(1 << 25) (1 << 25)
4537#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16) (1 << 16) /* Reserved in ICL+ */
4538#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN(1 << 15) (1 << 15) /* SKL+ */
4539
4540#define _PSR2_CTL_A0x60900 0x60900
4541#define _PSR2_CTL_EDP0x6f900 0x6f900
4542#define EDP_PSR2_CTL(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR2_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4543#define EDP_PSR2_ENABLE(1 << 31) (1 << 31)
4544#define EDP_SU_TRACK_ENABLE(1 << 30) (1 << 30)
4545#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2(0 << 28) (0 << 28)
4546#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3(1 << 28) (1 << 28)
4547#define EDP_Y_COORDINATE_VALID(1 << 26) (1 << 26) /* GLK and CNL+ */
4548#define EDP_Y_COORDINATE_ENABLE(1 << 25) (1 << 25) /* GLK and CNL+ */
4549#define EDP_MAX_SU_DISABLE_TIME(t)((t) << 20) ((t) << 20)
4550#define EDP_MAX_SU_DISABLE_TIME_MASK(0x1f << 20) (0x1f << 20)
4551#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES8 8
4552#define EDP_PSR2_IO_BUFFER_WAKE(lines)((8 - (lines)) << 13) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES8 - (lines)) << 13)
4553#define EDP_PSR2_IO_BUFFER_WAKE_MASK(3 << 13) (3 << 13)
4554#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES5 5
4555#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)(((lines) - 5) << 13) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES5) << 13)
4556#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK(7 << 13) (7 << 13)
4557#define EDP_PSR2_FAST_WAKE_MAX_LINES8 8
4558#define EDP_PSR2_FAST_WAKE(lines)((8 - (lines)) << 11) ((EDP_PSR2_FAST_WAKE_MAX_LINES8 - (lines)) << 11)
4559#define EDP_PSR2_FAST_WAKE_MASK(3 << 11) (3 << 11)
4560#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES5 5
4561#define TGL_EDP_PSR2_FAST_WAKE(lines)(((lines) - 5) << 10) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES5) << 10)
4562#define TGL_EDP_PSR2_FAST_WAKE_MASK(7 << 10) (7 << 10)
4563#define EDP_PSR2_TP2_TIME_500us(0 << 8) (0 << 8)
4564#define EDP_PSR2_TP2_TIME_100us(1 << 8) (1 << 8)
4565#define EDP_PSR2_TP2_TIME_2500us(2 << 8) (2 << 8)
4566#define EDP_PSR2_TP2_TIME_50us(3 << 8) (3 << 8)
4567#define EDP_PSR2_TP2_TIME_MASK(3 << 8) (3 << 8)
4568#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT4 4
4569#define EDP_PSR2_FRAME_BEFORE_SU_MASK(0xf << 4) (0xf << 4)
4570#define EDP_PSR2_FRAME_BEFORE_SU(a)((a) << 4) ((a) << 4)
4571#define EDP_PSR2_IDLE_FRAME_MASK0xf 0xf
4572#define EDP_PSR2_IDLE_FRAME_SHIFT0 0
4573
4574#define _PSR_EVENT_TRANS_A0x60848 0x60848
4575#define _PSR_EVENT_TRANS_B0x61848 0x61848
4576#define _PSR_EVENT_TRANS_C0x62848 0x62848
4577#define _PSR_EVENT_TRANS_D0x63848 0x63848
4578#define _PSR_EVENT_TRANS_EDP0x6f848 0x6f848
4579#define PSR_EVENT(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60848) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60848) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4580#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE(1 << 17) (1 << 17)
4581#define PSR_EVENT_PSR2_DISABLED(1 << 16) (1 << 16)
4582#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN(1 << 15) (1 << 15)
4583#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN(1 << 14) (1 << 14)
4584#define PSR_EVENT_GRAPHICS_RESET(1 << 12) (1 << 12)
4585#define PSR_EVENT_PCH_INTERRUPT(1 << 11) (1 << 11)
4586#define PSR_EVENT_MEMORY_UP(1 << 10) (1 << 10)
4587#define PSR_EVENT_FRONT_BUFFER_MODIFY(1 << 9) (1 << 9)
4588#define PSR_EVENT_WD_TIMER_EXPIRE(1 << 8) (1 << 8)
4589#define PSR_EVENT_PIPE_REGISTERS_UPDATE(1 << 6) (1 << 6)
4590#define PSR_EVENT_REGISTER_UPDATE(1 << 5) (1 << 5) /* Reserved in ICL+ */
4591#define PSR_EVENT_HDCP_ENABLE(1 << 4) (1 << 4)
4592#define PSR_EVENT_KVMR_SESSION_ENABLE(1 << 3) (1 << 3)
4593#define PSR_EVENT_VBI_ENABLE(1 << 2) (1 << 2)
4594#define PSR_EVENT_LPSP_MODE_EXIT(1 << 1) (1 << 1)
4595#define PSR_EVENT_PSR_DISABLE(1 << 0) (1 << 0)
4596
4597#define _PSR2_STATUS_A0x60940 0x60940
4598#define _PSR2_STATUS_EDP0x6f940 0x6f940
4599#define EDP_PSR2_STATUS(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60940) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR2_STATUS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60940) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4600#define EDP_PSR2_STATUS_STATE_MASK(0xf << 28) (0xf << 28)
4601#define EDP_PSR2_STATUS_STATE_SHIFT28 28
4602
4603#define _PSR2_SU_STATUS_A0x60914 0x60914
4604#define _PSR2_SU_STATUS_EDP0x6f914 0x6f914
4605#define _PSR2_SU_STATUS(tran, index)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60914) + ((&(dev_priv)->__info)->
display_mmio_offset)) + (index) * 4) }) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60914) + ((&(dev_priv)->__info)->
display_mmio_offset)) + (index) * 4) })
4606#define PSR2_SU_STATUS(tran, frame)(((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60914) + ((&(dev_priv)->__info)->
display_mmio_offset)) + ((frame) / 3) * 4) })) (_PSR2_SU_STATUS(tran, (frame) / 3)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60914) + ((&(dev_priv)->__info)->
display_mmio_offset)) + ((frame) / 3) * 4) }))
4607#define PSR2_SU_STATUS_SHIFT(frame)(((frame) % 3) * 10) (((frame) % 3) * 10)
4608#define PSR2_SU_STATUS_MASK(frame)(0x3ff << (((frame) % 3) * 10)) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)(((frame) % 3) * 10))
4609#define PSR2_SU_STATUS_FRAMES8 8
4610
4611#define _PSR2_MAN_TRK_CTL_A0x60910 0x60910
4612#define _PSR2_MAN_TRK_CTL_EDP0x6f910 0x6f910
4613#define PSR2_MAN_TRK_CTL(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60910) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60910) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
4614#define PSR2_MAN_TRK_CTL_ENABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4615#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(21))) + 0)) REG_GENMASK(30, 21)((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(21))) + 0))
4616#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)((u32)((((typeof(((u32)((((~0UL) >> (64 - (30) - 1)) &
((~0UL) << (21))) + 0))))(val) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(21))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (30
) - 1)) & ((~0UL) << (21))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)((u32)((((typeof(((u32)((((~0UL) >> (64 - (30) - 1)) &
((~0UL) << (21))) + 0))))(val) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (30) - 1)) & ((~0UL) <<
(21))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (30
) - 1)) & ((~0UL) << (21))) + 0)))) + 0 + 0 + 0 + 0
))
4617#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK((u32)((((~0UL) >> (64 - (20) - 1)) & ((~0UL) <<
(11))) + 0)) REG_GENMASK(20, 11)((u32)((((~0UL) >> (64 - (20) - 1)) & ((~0UL) <<
(11))) + 0))
4618#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)((u32)((((typeof(((u32)((((~0UL) >> (64 - (20) - 1)) &
((~0UL) << (11))) + 0))))(val) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (20) - 1)) & ((~0UL) <<
(11))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (20
) - 1)) & ((~0UL) << (11))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)((u32)((((typeof(((u32)((((~0UL) >> (64 - (20) - 1)) &
((~0UL) << (11))) + 0))))(val) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (20) - 1)) & ((~0UL) <<
(11))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (20
) - 1)) & ((~0UL) << (11))) + 0)))) + 0 + 0 + 0 + 0
))
4619#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME((u32)((1UL << (3)) + 0)) REG_BIT(3)((u32)((1UL << (3)) + 0))
4620#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME((u32)((1UL << (2)) + 0)) REG_BIT(2)((u32)((1UL << (2)) + 0))
4621#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
4622
4623/* VGA port control */
4624#define ADPA((const i915_reg_t){ .reg = (0x61100) }) _MMIO(0x61100)((const i915_reg_t){ .reg = (0x61100) })
4625#define PCH_ADPA((const i915_reg_t){ .reg = (0xe1100) }) _MMIO(0xe1100)((const i915_reg_t){ .reg = (0xe1100) })
4626#define VLV_ADPA((const i915_reg_t){ .reg = (0x180000 + 0x61100) }) _MMIO(VLV_DISPLAY_BASE + 0x61100)((const i915_reg_t){ .reg = (0x180000 + 0x61100) })
4627
4628#define ADPA_DAC_ENABLE(1 << 31) (1 << 31)
4629#define ADPA_DAC_DISABLE0 0
4630#define ADPA_PIPE_SEL_SHIFT30 30
4631#define ADPA_PIPE_SEL_MASK(1 << 30) (1 << 30)
4632#define ADPA_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
4633#define ADPA_PIPE_SEL_SHIFT_CPT29 29
4634#define ADPA_PIPE_SEL_MASK_CPT(3 << 29) (3 << 29)
4635#define ADPA_PIPE_SEL_CPT(pipe)((pipe) << 29) ((pipe) << 29)
4636#define ADPA_CRT_HOTPLUG_MASK0x03ff0000 0x03ff0000 /* bit 25-16 */
4637#define ADPA_CRT_HOTPLUG_MONITOR_NONE(0 << 24) (0 << 24)
4638#define ADPA_CRT_HOTPLUG_MONITOR_MASK(3 << 24) (3 << 24)
4639#define ADPA_CRT_HOTPLUG_MONITOR_COLOR(3 << 24) (3 << 24)
4640#define ADPA_CRT_HOTPLUG_MONITOR_MONO(2 << 24) (2 << 24)
4641#define ADPA_CRT_HOTPLUG_ENABLE(1 << 23) (1 << 23)
4642#define ADPA_CRT_HOTPLUG_PERIOD_64(0 << 22) (0 << 22)
4643#define ADPA_CRT_HOTPLUG_PERIOD_128(1 << 22) (1 << 22)
4644#define ADPA_CRT_HOTPLUG_WARMUP_5MS(0 << 21) (0 << 21)
4645#define ADPA_CRT_HOTPLUG_WARMUP_10MS(1 << 21) (1 << 21)
4646#define ADPA_CRT_HOTPLUG_SAMPLE_2S(0 << 20) (0 << 20)
4647#define ADPA_CRT_HOTPLUG_SAMPLE_4S(1 << 20) (1 << 20)
4648#define ADPA_CRT_HOTPLUG_VOLTAGE_40(0 << 18) (0 << 18)
4649#define ADPA_CRT_HOTPLUG_VOLTAGE_50(1 << 18) (1 << 18)
4650#define ADPA_CRT_HOTPLUG_VOLTAGE_60(2 << 18) (2 << 18)
4651#define ADPA_CRT_HOTPLUG_VOLTAGE_70(3 << 18) (3 << 18)
4652#define ADPA_CRT_HOTPLUG_VOLREF_325MV(0 << 17) (0 << 17)
4653#define ADPA_CRT_HOTPLUG_VOLREF_475MV(1 << 17) (1 << 17)
4654#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER(1 << 16) (1 << 16)
4655#define ADPA_USE_VGA_HVPOLARITY(1 << 15) (1 << 15)
4656#define ADPA_SETS_HVPOLARITY0 0
4657#define ADPA_VSYNC_CNTL_DISABLE(1 << 10) (1 << 10)
4658#define ADPA_VSYNC_CNTL_ENABLE0 0
4659#define ADPA_HSYNC_CNTL_DISABLE(1 << 11) (1 << 11)
4660#define ADPA_HSYNC_CNTL_ENABLE0 0
4661#define ADPA_VSYNC_ACTIVE_HIGH(1 << 4) (1 << 4)
4662#define ADPA_VSYNC_ACTIVE_LOW0 0
4663#define ADPA_HSYNC_ACTIVE_HIGH(1 << 3) (1 << 3)
4664#define ADPA_HSYNC_ACTIVE_LOW0 0
4665#define ADPA_DPMS_MASK(~(3 << 10)) (~(3 << 10))
4666#define ADPA_DPMS_ON(0 << 10) (0 << 10)
4667#define ADPA_DPMS_SUSPEND(1 << 10) (1 << 10)
4668#define ADPA_DPMS_STANDBY(2 << 10) (2 << 10)
4669#define ADPA_DPMS_OFF(3 << 10) (3 << 10)
4670
4671
4672/* Hotplug control (945+ only) */
4673#define PORT_HOTPLUG_EN((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61110) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61110) })
4674#define PORTB_HOTPLUG_INT_EN(1 << 29) (1 << 29)
4675#define PORTC_HOTPLUG_INT_EN(1 << 28) (1 << 28)
4676#define PORTD_HOTPLUG_INT_EN(1 << 27) (1 << 27)
4677#define SDVOB_HOTPLUG_INT_EN(1 << 26) (1 << 26)
4678#define SDVOC_HOTPLUG_INT_EN(1 << 25) (1 << 25)
4679#define TV_HOTPLUG_INT_EN(1 << 18) (1 << 18)
4680#define CRT_HOTPLUG_INT_EN(1 << 9) (1 << 9)
4681#define HOTPLUG_INT_EN_MASK((1 << 29) | (1 << 28) | (1 << 27) | (1 <<
25) | (1 << 26) | (1 << 9)) (PORTB_HOTPLUG_INT_EN(1 << 29) | \
4682 PORTC_HOTPLUG_INT_EN(1 << 28) | \
4683 PORTD_HOTPLUG_INT_EN(1 << 27) | \
4684 SDVOC_HOTPLUG_INT_EN(1 << 25) | \
4685 SDVOB_HOTPLUG_INT_EN(1 << 26) | \
4686 CRT_HOTPLUG_INT_EN(1 << 9))
4687#define CRT_HOTPLUG_FORCE_DETECT(1 << 3) (1 << 3)
4688#define CRT_HOTPLUG_ACTIVATION_PERIOD_32(0 << 8) (0 << 8)
4689/* must use period 64 on GM45 according to docs */
4690#define CRT_HOTPLUG_ACTIVATION_PERIOD_64(1 << 8) (1 << 8)
4691#define CRT_HOTPLUG_DAC_ON_TIME_2M(0 << 7) (0 << 7)
4692#define CRT_HOTPLUG_DAC_ON_TIME_4M(1 << 7) (1 << 7)
4693#define CRT_HOTPLUG_VOLTAGE_COMPARE_40(0 << 5) (0 << 5)
4694#define CRT_HOTPLUG_VOLTAGE_COMPARE_50(1 << 5) (1 << 5)
4695#define CRT_HOTPLUG_VOLTAGE_COMPARE_60(2 << 5) (2 << 5)
4696#define CRT_HOTPLUG_VOLTAGE_COMPARE_70(3 << 5) (3 << 5)
4697#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK(3 << 5) (3 << 5)
4698#define CRT_HOTPLUG_DETECT_DELAY_1G(0 << 4) (0 << 4)
4699#define CRT_HOTPLUG_DETECT_DELAY_2G(1 << 4) (1 << 4)
4700#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV(0 << 2) (0 << 2)
4701#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV(1 << 2) (1 << 2)
4702
4703#define PORT_HOTPLUG_STAT((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61114) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61114) })
4704/*
4705 * HDMI/DP bits are g4x+
4706 *
4707 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4708 * Please check the detailed lore in the commit message for for experimental
4709 * evidence.
4710 */
4711/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4712#define PORTD_HOTPLUG_LIVE_STATUS_GM45(1 << 29) (1 << 29)
4713#define PORTC_HOTPLUG_LIVE_STATUS_GM45(1 << 28) (1 << 28)
4714#define PORTB_HOTPLUG_LIVE_STATUS_GM45(1 << 27) (1 << 27)
4715/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4716#define PORTD_HOTPLUG_LIVE_STATUS_G4X(1 << 27) (1 << 27)
4717#define PORTC_HOTPLUG_LIVE_STATUS_G4X(1 << 28) (1 << 28)
4718#define PORTB_HOTPLUG_LIVE_STATUS_G4X(1 << 29) (1 << 29)
4719#define PORTD_HOTPLUG_INT_STATUS(3 << 21) (3 << 21)
4720#define PORTD_HOTPLUG_INT_LONG_PULSE(2 << 21) (2 << 21)
4721#define PORTD_HOTPLUG_INT_SHORT_PULSE(1 << 21) (1 << 21)
4722#define PORTC_HOTPLUG_INT_STATUS(3 << 19) (3 << 19)
4723#define PORTC_HOTPLUG_INT_LONG_PULSE(2 << 19) (2 << 19)
4724#define PORTC_HOTPLUG_INT_SHORT_PULSE(1 << 19) (1 << 19)
4725#define PORTB_HOTPLUG_INT_STATUS(3 << 17) (3 << 17)
4726#define PORTB_HOTPLUG_INT_LONG_PULSE(2 << 17) (2 << 17)
4727#define PORTB_HOTPLUG_INT_SHORT_PLUSE(1 << 17) (1 << 17)
4728/* CRT/TV common between gen3+ */
4729#define CRT_HOTPLUG_INT_STATUS(1 << 11) (1 << 11)
4730#define TV_HOTPLUG_INT_STATUS(1 << 10) (1 << 10)
4731#define CRT_HOTPLUG_MONITOR_MASK(3 << 8) (3 << 8)
4732#define CRT_HOTPLUG_MONITOR_COLOR(3 << 8) (3 << 8)
4733#define CRT_HOTPLUG_MONITOR_MONO(2 << 8) (2 << 8)
4734#define CRT_HOTPLUG_MONITOR_NONE(0 << 8) (0 << 8)
4735#define DP_AUX_CHANNEL_D_INT_STATUS_G4X(1 << 6) (1 << 6)
4736#define DP_AUX_CHANNEL_C_INT_STATUS_G4X(1 << 5) (1 << 5)
4737#define DP_AUX_CHANNEL_B_INT_STATUS_G4X(1 << 4) (1 << 4)
4738#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X(7 << 4) (7 << 4)
4739
4740/* SDVO is different across gen3/4 */
4741#define SDVOC_HOTPLUG_INT_STATUS_G4X(1 << 3) (1 << 3)
4742#define SDVOB_HOTPLUG_INT_STATUS_G4X(1 << 2) (1 << 2)
4743/*
4744 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4745 * since reality corrobates that they're the same as on gen3. But keep these
4746 * bits here (and the comment!) to help any other lost wanderers back onto the
4747 * right tracks.
4748 */
4749#define SDVOC_HOTPLUG_INT_STATUS_I965(3 << 4) (3 << 4)
4750#define SDVOB_HOTPLUG_INT_STATUS_I965(3 << 2) (3 << 2)
4751#define SDVOC_HOTPLUG_INT_STATUS_I915(1 << 7) (1 << 7)
4752#define SDVOB_HOTPLUG_INT_STATUS_I915(1 << 6) (1 << 6)
4753#define HOTPLUG_INT_STATUS_G4X((1 << 11) | (1 << 2) | (1 << 3) | (3 <<
17) | (3 << 19) | (3 << 21)) (CRT_HOTPLUG_INT_STATUS(1 << 11) | \
4754 SDVOB_HOTPLUG_INT_STATUS_G4X(1 << 2) | \
4755 SDVOC_HOTPLUG_INT_STATUS_G4X(1 << 3) | \
4756 PORTB_HOTPLUG_INT_STATUS(3 << 17) | \
4757 PORTC_HOTPLUG_INT_STATUS(3 << 19) | \
4758 PORTD_HOTPLUG_INT_STATUS(3 << 21))
4759
4760#define HOTPLUG_INT_STATUS_I915((1 << 11) | (1 << 6) | (1 << 7) | (3 <<
17) | (3 << 19) | (3 << 21)) (CRT_HOTPLUG_INT_STATUS(1 << 11) | \
4761 SDVOB_HOTPLUG_INT_STATUS_I915(1 << 6) | \
4762 SDVOC_HOTPLUG_INT_STATUS_I915(1 << 7) | \
4763 PORTB_HOTPLUG_INT_STATUS(3 << 17) | \
4764 PORTC_HOTPLUG_INT_STATUS(3 << 19) | \
4765 PORTD_HOTPLUG_INT_STATUS(3 << 21))
4766
4767/* SDVO and HDMI port control.
4768 * The same register may be used for SDVO or HDMI */
4769#define _GEN3_SDVOB0x61140 0x61140
4770#define _GEN3_SDVOC0x61160 0x61160
4771#define GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) }) _MMIO(_GEN3_SDVOB)((const i915_reg_t){ .reg = (0x61140) })
4772#define GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) }) _MMIO(_GEN3_SDVOC)((const i915_reg_t){ .reg = (0x61160) })
4773#define GEN4_HDMIB((const i915_reg_t){ .reg = (0x61140) }) GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) })
4774#define GEN4_HDMIC((const i915_reg_t){ .reg = (0x61160) }) GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) })
4775#define VLV_HDMIB((const i915_reg_t){ .reg = (0x180000 + 0x61140) }) _MMIO(VLV_DISPLAY_BASE + 0x61140)((const i915_reg_t){ .reg = (0x180000 + 0x61140) })
4776#define VLV_HDMIC((const i915_reg_t){ .reg = (0x180000 + 0x61160) }) _MMIO(VLV_DISPLAY_BASE + 0x61160)((const i915_reg_t){ .reg = (0x180000 + 0x61160) })
4777#define CHV_HDMID((const i915_reg_t){ .reg = (0x180000 + 0x6116C) }) _MMIO(VLV_DISPLAY_BASE + 0x6116C)((const i915_reg_t){ .reg = (0x180000 + 0x6116C) })
4778#define PCH_SDVOB((const i915_reg_t){ .reg = (0xe1140) }) _MMIO(0xe1140)((const i915_reg_t){ .reg = (0xe1140) })
4779#define PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) }) PCH_SDVOB((const i915_reg_t){ .reg = (0xe1140) })
4780#define PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) }) _MMIO(0xe1150)((const i915_reg_t){ .reg = (0xe1150) })
4781#define PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) }) _MMIO(0xe1160)((const i915_reg_t){ .reg = (0xe1160) })
4782
4783#define PORT_DFT_I9XX((const i915_reg_t){ .reg = (0x61150) }) _MMIO(0x61150)((const i915_reg_t){ .reg = (0x61150) })
4784#define DC_BALANCE_RESET(1 << 25) (1 << 25)
4785#define PORT_DFT2_G4X((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61154) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61154) })
4786#define DC_BALANCE_RESET_VLV(1 << 31) (1 << 31)
4787#define PIPE_SCRAMBLE_RESET_MASK((1 << 14) | (0x3 << 0)) ((1 << 14) | (0x3 << 0))
4788#define PIPE_C_SCRAMBLE_RESET(1 << 14) (1 << 14) /* chv */
4789#define PIPE_B_SCRAMBLE_RESET(1 << 1) (1 << 1)
4790#define PIPE_A_SCRAMBLE_RESET(1 << 0) (1 << 0)
4791
4792/* Gen 3 SDVO bits: */
4793#define SDVO_ENABLE(1 << 31) (1 << 31)
4794#define SDVO_PIPE_SEL_SHIFT30 30
4795#define SDVO_PIPE_SEL_MASK(1 << 30) (1 << 30)
4796#define SDVO_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
4797#define SDVO_STALL_SELECT(1 << 29) (1 << 29)
4798#define SDVO_INTERRUPT_ENABLE(1 << 26) (1 << 26)
4799/*
4800 * 915G/GM SDVO pixel multiplier.
4801 * Programmed value is multiplier - 1, up to 5x.
4802 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4803 */
4804#define SDVO_PORT_MULTIPLY_MASK(7 << 23) (7 << 23)
4805#define SDVO_PORT_MULTIPLY_SHIFT23 23
4806#define SDVO_PHASE_SELECT_MASK(15 << 19) (15 << 19)
4807#define SDVO_PHASE_SELECT_DEFAULT(6 << 19) (6 << 19)
4808#define SDVO_CLOCK_OUTPUT_INVERT(1 << 18) (1 << 18)
4809#define SDVOC_GANG_MODE(1 << 16) (1 << 16) /* Port C only */
4810#define SDVO_BORDER_ENABLE(1 << 7) (1 << 7) /* SDVO only */
4811#define SDVOB_PCIE_CONCURRENCY(1 << 3) (1 << 3) /* Port B only */
4812#define SDVO_DETECTED(1 << 2) (1 << 2)
4813/* Bits to be preserved when writing */
4814#define SDVOB_PRESERVE_MASK((1 << 17) | (1 << 16) | (1 << 14) | (1 <<
26)) ((1 << 17) | (1 << 16) | (1 << 14) | \
4815 SDVO_INTERRUPT_ENABLE(1 << 26))
4816#define SDVOC_PRESERVE_MASK((1 << 17) | (1 << 26)) ((1 << 17) | SDVO_INTERRUPT_ENABLE(1 << 26))
4817
4818/* Gen 4 SDVO/HDMI bits: */
4819#define SDVO_COLOR_FORMAT_8bpc(0 << 26) (0 << 26)
4820#define SDVO_COLOR_FORMAT_MASK(7 << 26) (7 << 26)
4821#define SDVO_ENCODING_SDVO(0 << 10) (0 << 10)
4822#define SDVO_ENCODING_HDMI(2 << 10) (2 << 10)
4823#define HDMI_MODE_SELECT_HDMI(1 << 9) (1 << 9) /* HDMI only */
4824#define HDMI_MODE_SELECT_DVI(0 << 9) (0 << 9) /* HDMI only */
4825#define HDMI_COLOR_RANGE_16_235(1 << 8) (1 << 8) /* HDMI only */
4826#define HDMI_AUDIO_ENABLE(1 << 6) (1 << 6) /* HDMI only */
4827/* VSYNC/HSYNC bits new with 965, default is to be set */
4828#define SDVO_VSYNC_ACTIVE_HIGH(1 << 4) (1 << 4)
4829#define SDVO_HSYNC_ACTIVE_HIGH(1 << 3) (1 << 3)
4830
4831/* Gen 5 (IBX) SDVO/HDMI bits: */
4832#define HDMI_COLOR_FORMAT_12bpc(3 << 26) (3 << 26) /* HDMI only */
4833#define SDVOB_HOTPLUG_ENABLE(1 << 23) (1 << 23) /* SDVO only */
4834
4835/* Gen 6 (CPT) SDVO/HDMI bits: */
4836#define SDVO_PIPE_SEL_SHIFT_CPT29 29
4837#define SDVO_PIPE_SEL_MASK_CPT(3 << 29) (3 << 29)
4838#define SDVO_PIPE_SEL_CPT(pipe)((pipe) << 29) ((pipe) << 29)
4839
4840/* CHV SDVO/HDMI bits: */
4841#define SDVO_PIPE_SEL_SHIFT_CHV24 24
4842#define SDVO_PIPE_SEL_MASK_CHV(3 << 24) (3 << 24)
4843#define SDVO_PIPE_SEL_CHV(pipe)((pipe) << 24) ((pipe) << 24)
4844
4845
4846/* DVO port control */
4847#define _DVOA0x61120 0x61120
4848#define DVOA((const i915_reg_t){ .reg = (0x61120) }) _MMIO(_DVOA)((const i915_reg_t){ .reg = (0x61120) })
4849#define _DVOB0x61140 0x61140
4850#define DVOB((const i915_reg_t){ .reg = (0x61140) }) _MMIO(_DVOB)((const i915_reg_t){ .reg = (0x61140) })
4851#define _DVOC0x61160 0x61160
4852#define DVOC((const i915_reg_t){ .reg = (0x61160) }) _MMIO(_DVOC)((const i915_reg_t){ .reg = (0x61160) })
4853#define DVO_ENABLE(1 << 31) (1 << 31)
4854#define DVO_PIPE_SEL_SHIFT30 30
4855#define DVO_PIPE_SEL_MASK(1 << 30) (1 << 30)
4856#define DVO_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
4857#define DVO_PIPE_STALL_UNUSED(0 << 28) (0 << 28)
4858#define DVO_PIPE_STALL(1 << 28) (1 << 28)
4859#define DVO_PIPE_STALL_TV(2 << 28) (2 << 28)
4860#define DVO_PIPE_STALL_MASK(3 << 28) (3 << 28)
4861#define DVO_USE_VGA_SYNC(1 << 15) (1 << 15)
4862#define DVO_DATA_ORDER_I740(0 << 14) (0 << 14)
4863#define DVO_DATA_ORDER_FP(1 << 14) (1 << 14)
4864#define DVO_VSYNC_DISABLE(1 << 11) (1 << 11)
4865#define DVO_HSYNC_DISABLE(1 << 10) (1 << 10)
4866#define DVO_VSYNC_TRISTATE(1 << 9) (1 << 9)
4867#define DVO_HSYNC_TRISTATE(1 << 8) (1 << 8)
4868#define DVO_BORDER_ENABLE(1 << 7) (1 << 7)
4869#define DVO_DATA_ORDER_GBRG(1 << 6) (1 << 6)
4870#define DVO_DATA_ORDER_RGGB(0 << 6) (0 << 6)
4871#define DVO_DATA_ORDER_GBRG_ERRATA(0 << 6) (0 << 6)
4872#define DVO_DATA_ORDER_RGGB_ERRATA(1 << 6) (1 << 6)
4873#define DVO_VSYNC_ACTIVE_HIGH(1 << 4) (1 << 4)
4874#define DVO_HSYNC_ACTIVE_HIGH(1 << 3) (1 << 3)
4875#define DVO_BLANK_ACTIVE_HIGH(1 << 2) (1 << 2)
4876#define DVO_OUTPUT_CSTATE_PIXELS(1 << 1) (1 << 1) /* SDG only */
4877#define DVO_OUTPUT_SOURCE_SIZE_PIXELS(1 << 0) (1 << 0) /* SDG only */
4878#define DVO_PRESERVE_MASK(0x7 << 24) (0x7 << 24)
4879#define DVOA_SRCDIM((const i915_reg_t){ .reg = (0x61124) }) _MMIO(0x61124)((const i915_reg_t){ .reg = (0x61124) })
4880#define DVOB_SRCDIM((const i915_reg_t){ .reg = (0x61144) }) _MMIO(0x61144)((const i915_reg_t){ .reg = (0x61144) })
4881#define DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }) _MMIO(0x61164)((const i915_reg_t){ .reg = (0x61164) })
4882#define DVO_SRCDIM_HORIZONTAL_SHIFT12 12
4883#define DVO_SRCDIM_VERTICAL_SHIFT0 0
4884
4885/* LVDS port control */
4886#define LVDS((const i915_reg_t){ .reg = (0x61180) }) _MMIO(0x61180)((const i915_reg_t){ .reg = (0x61180) })
4887/*
4888 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4889 * the DPLL semantics change when the LVDS is assigned to that pipe.
4890 */
4891#define LVDS_PORT_EN(1 << 31) (1 << 31)
4892/* Selects pipe B for LVDS data. Must be set on pre-965. */
4893#define LVDS_PIPE_SEL_SHIFT30 30
4894#define LVDS_PIPE_SEL_MASK(1 << 30) (1 << 30)
4895#define LVDS_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
4896#define LVDS_PIPE_SEL_SHIFT_CPT29 29
4897#define LVDS_PIPE_SEL_MASK_CPT(3 << 29) (3 << 29)
4898#define LVDS_PIPE_SEL_CPT(pipe)((pipe) << 29) ((pipe) << 29)
4899/* LVDS dithering flag on 965/g4x platform */
4900#define LVDS_ENABLE_DITHER(1 << 25) (1 << 25)
4901/* LVDS sync polarity flags. Set to invert (i.e. negative) */
4902#define LVDS_VSYNC_POLARITY(1 << 21) (1 << 21)
4903#define LVDS_HSYNC_POLARITY(1 << 20) (1 << 20)
4904
4905/* Enable border for unscaled (or aspect-scaled) display */
4906#define LVDS_BORDER_ENABLE(1 << 15) (1 << 15)
4907/*
4908 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4909 * pixel.
4910 */
4911#define LVDS_A0A2_CLKA_POWER_MASK(3 << 8) (3 << 8)
4912#define LVDS_A0A2_CLKA_POWER_DOWN(0 << 8) (0 << 8)
4913#define LVDS_A0A2_CLKA_POWER_UP(3 << 8) (3 << 8)
4914/*
4915 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4916 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4917 * on.
4918 */
4919#define LVDS_A3_POWER_MASK(3 << 6) (3 << 6)
4920#define LVDS_A3_POWER_DOWN(0 << 6) (0 << 6)
4921#define LVDS_A3_POWER_UP(3 << 6) (3 << 6)
4922/*
4923 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4924 * is set.
4925 */
4926#define LVDS_CLKB_POWER_MASK(3 << 4) (3 << 4)
4927#define LVDS_CLKB_POWER_DOWN(0 << 4) (0 << 4)
4928#define LVDS_CLKB_POWER_UP(3 << 4) (3 << 4)
4929/*
4930 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4931 * setting for whether we are in dual-channel mode. The B3 pair will
4932 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4933 */
4934#define LVDS_B0B3_POWER_MASK(3 << 2) (3 << 2)
4935#define LVDS_B0B3_POWER_DOWN(0 << 2) (0 << 2)
4936#define LVDS_B0B3_POWER_UP(3 << 2) (3 << 2)
4937
4938/* Video Data Island Packet control */
4939#define VIDEO_DIP_DATA((const i915_reg_t){ .reg = (0x61178) }) _MMIO(0x61178)((const i915_reg_t){ .reg = (0x61178) })
4940/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4941 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4942 * of the infoframe structure specified by CEA-861. */
4943#define VIDEO_DIP_DATA_SIZE32 32
4944#define VIDEO_DIP_GMP_DATA_SIZE36 36
4945#define VIDEO_DIP_VSC_DATA_SIZE36 36
4946#define VIDEO_DIP_PPS_DATA_SIZE132 132
4947#define VIDEO_DIP_CTL((const i915_reg_t){ .reg = (0x61170) }) _MMIO(0x61170)((const i915_reg_t){ .reg = (0x61170) })
4948/* Pre HSW: */
4949#define VIDEO_DIP_ENABLE(1 << 31) (1 << 31)
4950#define VIDEO_DIP_PORT(port)((port) << 29) ((port) << 29)
4951#define VIDEO_DIP_PORT_MASK(3 << 29) (3 << 29)
4952#define VIDEO_DIP_ENABLE_GCP(1 << 25) (1 << 25) /* ilk+ */
4953#define VIDEO_DIP_ENABLE_AVI(1 << 21) (1 << 21)
4954#define VIDEO_DIP_ENABLE_VENDOR(2 << 21) (2 << 21)
4955#define VIDEO_DIP_ENABLE_GAMUT(4 << 21) (4 << 21) /* ilk+ */
4956#define VIDEO_DIP_ENABLE_SPD(8 << 21) (8 << 21)
4957#define VIDEO_DIP_SELECT_AVI(0 << 19) (0 << 19)
4958#define VIDEO_DIP_SELECT_VENDOR(1 << 19) (1 << 19)
4959#define VIDEO_DIP_SELECT_GAMUT(2 << 19) (2 << 19)
4960#define VIDEO_DIP_SELECT_SPD(3 << 19) (3 << 19)
4961#define VIDEO_DIP_SELECT_MASK(3 << 19) (3 << 19)
4962#define VIDEO_DIP_FREQ_ONCE(0 << 16) (0 << 16)
4963#define VIDEO_DIP_FREQ_VSYNC(1 << 16) (1 << 16)
4964#define VIDEO_DIP_FREQ_2VSYNC(2 << 16) (2 << 16)
4965#define VIDEO_DIP_FREQ_MASK(3 << 16) (3 << 16)
4966/* HSW and later: */
4967#define VIDEO_DIP_ENABLE_DRM_GLK(1 << 28) (1 << 28)
4968#define PSR_VSC_BIT_7_SET(1 << 27) (1 << 27)
4969#define VSC_SELECT_MASK(0x3 << 25) (0x3 << 25)
4970#define VSC_SELECT_SHIFT25 25
4971#define VSC_DIP_HW_HEA_DATA(0 << 25) (0 << 25)
4972#define VSC_DIP_HW_HEA_SW_DATA(1 << 25) (1 << 25)
4973#define VSC_DIP_HW_DATA_SW_HEA(2 << 25) (2 << 25)
4974#define VSC_DIP_SW_HEA_DATA(3 << 25) (3 << 25)
4975#define VDIP_ENABLE_PPS(1 << 24) (1 << 24)
4976#define VIDEO_DIP_ENABLE_VSC_HSW(1 << 20) (1 << 20)
4977#define VIDEO_DIP_ENABLE_GCP_HSW(1 << 16) (1 << 16)
4978#define VIDEO_DIP_ENABLE_AVI_HSW(1 << 12) (1 << 12)
4979#define VIDEO_DIP_ENABLE_VS_HSW(1 << 8) (1 << 8)
4980#define VIDEO_DIP_ENABLE_GMP_HSW(1 << 4) (1 << 4)
4981#define VIDEO_DIP_ENABLE_SPD_HSW(1 << 0) (1 << 0)
4982
4983/* Panel power sequencing */
4984#define PPS_BASE0x61200 0x61200
4985#define VLV_PPS_BASE(0x180000 + 0x61200) (VLV_DISPLAY_BASE0x180000 + PPS_BASE0x61200)
4986#define PCH_PPS_BASE0xC7200 0xC7200
4987
4988#define _MMIO_PPS(pps_idx, reg)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (reg) + (pps_idx) * 0x100) }) _MMIO(dev_priv->pps_mmio_base - \((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (reg) + (pps_idx) * 0x100) })
4989 PPS_BASE + (reg) + \((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (reg) + (pps_idx) * 0x100) })
4990 (pps_idx) * 0x100)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (reg) + (pps_idx) * 0x100) })
4991
4992#define _PP_STATUS0x61200 0x61200
4993#define PP_STATUS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61200) + (pps_idx) * 0x100) }) _MMIO_PPS(pps_idx, _PP_STATUS)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61200) + (pps_idx) * 0x100) })
4994#define PP_ON((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
4995/*
4996 * Indicates that all dependencies of the panel are on:
4997 *
4998 * - PLL enabled
4999 * - pipe enabled
5000 * - LVDS/DVOB/DVOC on
5001 */
5002#define PP_READY((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
5003#define PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0)) REG_GENMASK(29, 28)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))
5004#define PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
))
5005#define PP_SEQUENCE_POWER_UP((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
))
5006#define PP_SEQUENCE_POWER_DOWN((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) &
((~0UL) << (28))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29
) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0
))
5007#define PP_CYCLE_DELAY_ACTIVE((u32)((1UL << (27)) + 0)) REG_BIT(27)((u32)((1UL << (27)) + 0))
5008#define PP_SEQUENCE_STATE_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(3, 0)((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))
5009#define PP_SEQUENCE_STATE_OFF_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5010#define PP_SEQUENCE_STATE_OFF_S0_1((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5011#define PP_SEQUENCE_STATE_OFF_S0_2((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5012#define PP_SEQUENCE_STATE_OFF_S0_3((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5013#define PP_SEQUENCE_STATE_ON_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x8) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x8) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5014#define PP_SEQUENCE_STATE_ON_S1_1((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x9) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0x9) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5015#define PP_SEQUENCE_STATE_ON_S1_2((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xa) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xa) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5016#define PP_SEQUENCE_STATE_ON_S1_3((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xb) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xb) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5017#define PP_SEQUENCE_STATE_RESET((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xf) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) &
((~0UL) << (0))) + 0))))(0xf) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
5018
5019#define _PP_CONTROL0x61204 0x61204
5020#define PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61204) + (pps_idx) * 0x100) }) _MMIO_PPS(pps_idx, _PP_CONTROL)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61204) + (pps_idx) * 0x100) })
5021#define PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(31, 16)((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))
5022#define PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
5023#define BXT_POWER_CYCLE_DELAY_MASK((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(4))) + 0)) REG_GENMASK(8, 4)((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(4))) + 0))
5024#define EDP_FORCE_VDD((u32)((1UL << (3)) + 0)) REG_BIT(3)((u32)((1UL << (3)) + 0))
5025#define EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)) REG_BIT(2)((u32)((1UL << (2)) + 0))
5026#define PANEL_POWER_RESET((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
5027#define PANEL_POWER_ON((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
5028
5029#define _PP_ON_DELAYS0x61208 0x61208
5030#define PP_ON_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61208) + (pps_idx) * 0x100) }) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61208) + (pps_idx) * 0x100) })
5031#define PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0)) REG_GENMASK(31, 30)((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))
5032#define PANEL_PORT_SELECT_LVDS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
5033#define PANEL_PORT_SELECT_DPA((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
5034#define PANEL_PORT_SELECT_DPC((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
5035#define PANEL_PORT_SELECT_DPD((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
5036#define PANEL_PORT_SELECT_VLV(port)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(port) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(port) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
5037#define PANEL_POWER_UP_DELAY_MASK((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(28, 16)((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) <<
(16))) + 0))
5038#define PANEL_LIGHT_ON_DELAY_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(12, 0)((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0))
5039
5040#define _PP_OFF_DELAYS0x6120C 0x6120C
5041#define PP_OFF_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x6120C) + (pps_idx) * 0x100) }) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x6120C) + (pps_idx) * 0x100) })
5042#define PANEL_POWER_DOWN_DELAY_MASK((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(28, 16)((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) <<
(16))) + 0))
5043#define PANEL_LIGHT_OFF_DELAY_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(12, 0)((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
(0))) + 0))
5044
5045#define _PP_DIVISOR0x61210 0x61210
5046#define PP_DIVISOR(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61210) + (pps_idx) * 0x100) }) _MMIO_PPS(pps_idx, _PP_DIVISOR)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61210) + (pps_idx) * 0x100) })
5047#define PP_REFERENCE_DIVIDER_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(8))) + 0)) REG_GENMASK(31, 8)((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(8))) + 0))
5048#define PANEL_POWER_CYCLE_DELAY_MASK((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(4, 0)((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) <<
(0))) + 0))
5049
5050/* Panel fitting */
5051#define PFIT_CONTROL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61230) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61230) })
5052#define PFIT_ENABLE(1 << 31) (1 << 31)
5053#define PFIT_PIPE_MASK(3 << 29) (3 << 29)
5054#define PFIT_PIPE_SHIFT29 29
5055#define PFIT_PIPE(pipe)((pipe) << 29) ((pipe) << 29)
5056#define VERT_INTERP_DISABLE(0 << 10) (0 << 10)
5057#define VERT_INTERP_BILINEAR(1 << 10) (1 << 10)
5058#define VERT_INTERP_MASK(3 << 10) (3 << 10)
5059#define VERT_AUTO_SCALE(1 << 9) (1 << 9)
5060#define HORIZ_INTERP_DISABLE(0 << 6) (0 << 6)
5061#define HORIZ_INTERP_BILINEAR(1 << 6) (1 << 6)
5062#define HORIZ_INTERP_MASK(3 << 6) (3 << 6)
5063#define HORIZ_AUTO_SCALE(1 << 5) (1 << 5)
5064#define PANEL_8TO6_DITHER_ENABLE(1 << 3) (1 << 3)
5065#define PFIT_FILTER_FUZZY(0 << 24) (0 << 24)
5066#define PFIT_SCALING_AUTO(0 << 26) (0 << 26)
5067#define PFIT_SCALING_PROGRAMMED(1 << 26) (1 << 26)
5068#define PFIT_SCALING_PILLAR(2 << 26) (2 << 26)
5069#define PFIT_SCALING_LETTER(3 << 26) (3 << 26)
5070#define PFIT_PGM_RATIOS((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61234) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61234) })
5071/* Pre-965 */
5072#define PFIT_VERT_SCALE_SHIFT20 20
5073#define PFIT_VERT_SCALE_MASK0xfff00000 0xfff00000
5074#define PFIT_HORIZ_SCALE_SHIFT4 4
5075#define PFIT_HORIZ_SCALE_MASK0x0000fff0 0x0000fff0
5076/* 965+ */
5077#define PFIT_VERT_SCALE_SHIFT_96516 16
5078#define PFIT_VERT_SCALE_MASK_9650x1fff0000 0x1fff0000
5079#define PFIT_HORIZ_SCALE_SHIFT_9650 0
5080#define PFIT_HORIZ_SCALE_MASK_9650x00001fff 0x00001fff
5081
5082#define PFIT_AUTO_RATIOS((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61238) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61238) })
5083
5084#define _VLV_BLC_PWM_CTL2_A(((&(dev_priv)->__info)->display_mmio_offset) + 0x61250
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61250)
5085#define _VLV_BLC_PWM_CTL2_B(((&(dev_priv)->__info)->display_mmio_offset) + 0x61350
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61350)
5086#define VLV_BLC_PWM_CTL2(pipe)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61250)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61350)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61250))))
) }) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61250)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61350)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61250))))
) })
5087 _VLV_BLC_PWM_CTL2_B)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61250)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61350)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61250))))
) })
5088
5089#define _VLV_BLC_PWM_CTL_A(((&(dev_priv)->__info)->display_mmio_offset) + 0x61254
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61254)
5090#define _VLV_BLC_PWM_CTL_B(((&(dev_priv)->__info)->display_mmio_offset) + 0x61354
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61354)
5091#define VLV_BLC_PWM_CTL(pipe)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61254)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61354)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61254))))
) }) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61254)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61354)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61254))))
) })
5092 _VLV_BLC_PWM_CTL_B)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61254)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61354)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61254))))
) })
5093
5094#define _VLV_BLC_HIST_CTL_A(((&(dev_priv)->__info)->display_mmio_offset) + 0x61260
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61260)
5095#define _VLV_BLC_HIST_CTL_B(((&(dev_priv)->__info)->display_mmio_offset) + 0x61360
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x61360)
5096#define VLV_BLC_HIST_CTL(pipe)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61260)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61360)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61260))))
) }) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61260)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61360)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61260))))
) })
5097 _VLV_BLC_HIST_CTL_B)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x61260)) + (pipe) * (((((&(dev_priv
)->__info)->display_mmio_offset) + 0x61360)) - ((((&
(dev_priv)->__info)->display_mmio_offset) + 0x61260))))
) })
5098
5099/* Backlight control */
5100#define BLC_PWM_CTL2((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61250) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61250) }) /* 965+ only */
5101#define BLM_PWM_ENABLE(1 << 31) (1 << 31)
5102#define BLM_COMBINATION_MODE(1 << 30) (1 << 30) /* gen4 only */
5103#define BLM_PIPE_SELECT(1 << 29) (1 << 29)
5104#define BLM_PIPE_SELECT_IVB(3 << 29) (3 << 29)
5105#define BLM_PIPE_A(0 << 29) (0 << 29)
5106#define BLM_PIPE_B(1 << 29) (1 << 29)
5107#define BLM_PIPE_C(2 << 29) (2 << 29) /* ivb + */
5108#define BLM_TRANSCODER_A(0 << 29) BLM_PIPE_A(0 << 29) /* hsw */
5109#define BLM_TRANSCODER_B(1 << 29) BLM_PIPE_B(1 << 29)
5110#define BLM_TRANSCODER_C(2 << 29) BLM_PIPE_C(2 << 29)
5111#define BLM_TRANSCODER_EDP(3 << 29) (3 << 29)
5112#define BLM_PIPE(pipe)((pipe) << 29) ((pipe) << 29)
5113#define BLM_POLARITY_I965(1 << 28) (1 << 28) /* gen4 only */
5114#define BLM_PHASE_IN_INTERUPT_STATUS(1 << 26) (1 << 26)
5115#define BLM_PHASE_IN_ENABLE(1 << 25) (1 << 25)
5116#define BLM_PHASE_IN_INTERUPT_ENABL(1 << 24) (1 << 24)
5117#define BLM_PHASE_IN_TIME_BASE_SHIFT(16) (16)
5118#define BLM_PHASE_IN_TIME_BASE_MASK(0xff << 16) (0xff << 16)
5119#define BLM_PHASE_IN_COUNT_SHIFT(8) (8)
5120#define BLM_PHASE_IN_COUNT_MASK(0xff << 8) (0xff << 8)
5121#define BLM_PHASE_IN_INCR_SHIFT(0) (0)
5122#define BLM_PHASE_IN_INCR_MASK(0xff << 0) (0xff << 0)
5123#define BLC_PWM_CTL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61254) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61254) })
5124/*
5125 * This is the most significant 15 bits of the number of backlight cycles in a
5126 * complete cycle of the modulated backlight control.
5127 *
5128 * The actual value is this field multiplied by two.
5129 */
5130#define BACKLIGHT_MODULATION_FREQ_SHIFT(17) (17)
5131#define BACKLIGHT_MODULATION_FREQ_MASK(0x7fff << 17) (0x7fff << 17)
5132#define BLM_LEGACY_MODE(1 << 16) (1 << 16) /* gen2 only */
5133/*
5134 * This is the number of cycles out of the backlight modulation cycle for which
5135 * the backlight is on.
5136 *
5137 * This field must be no greater than the number of cycles in the complete
5138 * backlight modulation cycle.
5139 */
5140#define BACKLIGHT_DUTY_CYCLE_SHIFT(0) (0)
5141#define BACKLIGHT_DUTY_CYCLE_MASK(0xffff) (0xffff)
5142#define BACKLIGHT_DUTY_CYCLE_MASK_PNV(0xfffe) (0xfffe)
5143#define BLM_POLARITY_PNV(1 << 0) (1 << 0) /* pnv only */
5144
5145#define BLC_HIST_CTL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61260) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x61260) })
5146#define BLM_HISTOGRAM_ENABLE(1 << 31) (1 << 31)
5147
5148/* New registers for PCH-split platforms. Safe where new bits show up, the
5149 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
5150#define BLC_PWM_CPU_CTL2((const i915_reg_t){ .reg = (0x48250) }) _MMIO(0x48250)((const i915_reg_t){ .reg = (0x48250) })
5151#define BLC_PWM_CPU_CTL((const i915_reg_t){ .reg = (0x48254) }) _MMIO(0x48254)((const i915_reg_t){ .reg = (0x48254) })
5152
5153#define HSW_BLC_PWM2_CTL((const i915_reg_t){ .reg = (0x48350) }) _MMIO(0x48350)((const i915_reg_t){ .reg = (0x48350) })
5154
5155/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5156 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
5157#define BLC_PWM_PCH_CTL1((const i915_reg_t){ .reg = (0xc8250) }) _MMIO(0xc8250)((const i915_reg_t){ .reg = (0xc8250) })
5158#define BLM_PCH_PWM_ENABLE(1 << 31) (1 << 31)
5159#define BLM_PCH_OVERRIDE_ENABLE(1 << 30) (1 << 30)
5160#define BLM_PCH_POLARITY(1 << 29) (1 << 29)
5161#define BLC_PWM_PCH_CTL2((const i915_reg_t){ .reg = (0xc8254) }) _MMIO(0xc8254)((const i915_reg_t){ .reg = (0xc8254) })
5162
5163#define UTIL_PIN_CTL((const i915_reg_t){ .reg = (0x48400) }) _MMIO(0x48400)((const i915_reg_t){ .reg = (0x48400) })
5164#define UTIL_PIN_ENABLE(1 << 31) (1 << 31)
5165#define UTIL_PIN_PIPE_MASK(3 << 29) (3 << 29)
5166#define UTIL_PIN_PIPE(x)((x) << 29) ((x) << 29)
5167#define UTIL_PIN_MODE_MASK(0xf << 24) (0xf << 24)
5168#define UTIL_PIN_MODE_DATA(0 << 24) (0 << 24)
5169#define UTIL_PIN_MODE_PWM(1 << 24) (1 << 24)
5170#define UTIL_PIN_MODE_VBLANK(4 << 24) (4 << 24)
5171#define UTIL_PIN_MODE_VSYNC(5 << 24) (5 << 24)
5172#define UTIL_PIN_MODE_EYE_LEVEL(8 << 24) (8 << 24)
5173#define UTIL_PIN_OUTPUT_DATA(1 << 23) (1 << 23)
5174#define UTIL_PIN_POLARITY(1 << 22) (1 << 22)
5175#define UTIL_PIN_DIRECTION_INPUT(1 << 19) (1 << 19)
5176#define UTIL_PIN_INPUT_DATA(1 << 16) (1 << 16)
5177
5178/* BXT backlight register definition. */
5179#define _BXT_BLC_PWM_CTL10xC8250 0xC8250
5180#define BXT_BLC_PWM_ENABLE(1 << 31) (1 << 31)
5181#define BXT_BLC_PWM_POLARITY(1 << 29) (1 << 29)
5182#define _BXT_BLC_PWM_FREQ10xC8254 0xC8254
5183#define _BXT_BLC_PWM_DUTY10xC8258 0xC8258
5184
5185#define _BXT_BLC_PWM_CTL20xC8350 0xC8350
5186#define _BXT_BLC_PWM_FREQ20xC8354 0xC8354
5187#define _BXT_BLC_PWM_DUTY20xC8358 0xC8358
5188
5189#define BXT_BLC_PWM_CTL(controller)((const i915_reg_t){ .reg = (((0xC8250) + (controller) * ((0xC8350
) - (0xC8250)))) }) _MMIO_PIPE(controller, \((const i915_reg_t){ .reg = (((0xC8250) + (controller) * ((0xC8350
) - (0xC8250)))) })
5190 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)((const i915_reg_t){ .reg = (((0xC8250) + (controller) * ((0xC8350
) - (0xC8250)))) })
5191#define BXT_BLC_PWM_FREQ(controller)((const i915_reg_t){ .reg = (((0xC8254) + (controller) * ((0xC8354
) - (0xC8254)))) }) _MMIO_PIPE(controller, \((const i915_reg_t){ .reg = (((0xC8254) + (controller) * ((0xC8354
) - (0xC8254)))) })
5192 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)((const i915_reg_t){ .reg = (((0xC8254) + (controller) * ((0xC8354
) - (0xC8254)))) })
5193#define BXT_BLC_PWM_DUTY(controller)((const i915_reg_t){ .reg = (((0xC8258) + (controller) * ((0xC8358
) - (0xC8258)))) }) _MMIO_PIPE(controller, \((const i915_reg_t){ .reg = (((0xC8258) + (controller) * ((0xC8358
) - (0xC8258)))) })
5194 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)((const i915_reg_t){ .reg = (((0xC8258) + (controller) * ((0xC8358
) - (0xC8258)))) })
5195
5196#define PCH_GTC_CTL((const i915_reg_t){ .reg = (0xe7000) }) _MMIO(0xe7000)((const i915_reg_t){ .reg = (0xe7000) })
5197#define PCH_GTC_ENABLE(1 << 31) (1 << 31)
5198
5199/* TV port control */
5200#define TV_CTL((const i915_reg_t){ .reg = (0x68000) }) _MMIO(0x68000)((const i915_reg_t){ .reg = (0x68000) })
5201/* Enables the TV encoder */
5202# define TV_ENC_ENABLE(1 << 31) (1 << 31)
5203/* Sources the TV encoder input from pipe B instead of A. */
5204# define TV_ENC_PIPE_SEL_SHIFT30 30
5205# define TV_ENC_PIPE_SEL_MASK(1 << 30) (1 << 30)
5206# define TV_ENC_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
5207/* Outputs composite video (DAC A only) */
5208# define TV_ENC_OUTPUT_COMPOSITE(0 << 28) (0 << 28)
5209/* Outputs SVideo video (DAC B/C) */
5210# define TV_ENC_OUTPUT_SVIDEO(1 << 28) (1 << 28)
5211/* Outputs Component video (DAC A/B/C) */
5212# define TV_ENC_OUTPUT_COMPONENT(2 << 28) (2 << 28)
5213/* Outputs Composite and SVideo (DAC A/B/C) */
5214# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE(3 << 28) (3 << 28)
5215# define TV_TRILEVEL_SYNC(1 << 21) (1 << 21)
5216/* Enables slow sync generation (945GM only) */
5217# define TV_SLOW_SYNC(1 << 20) (1 << 20)
5218/* Selects 4x oversampling for 480i and 576p */
5219# define TV_OVERSAMPLE_4X(0 << 18) (0 << 18)
5220/* Selects 2x oversampling for 720p and 1080i */
5221# define TV_OVERSAMPLE_2X(1 << 18) (1 << 18)
5222/* Selects no oversampling for 1080p */
5223# define TV_OVERSAMPLE_NONE(2 << 18) (2 << 18)
5224/* Selects 8x oversampling */
5225# define TV_OVERSAMPLE_8X(3 << 18) (3 << 18)
5226# define TV_OVERSAMPLE_MASK(3 << 18) (3 << 18)
5227/* Selects progressive mode rather than interlaced */
5228# define TV_PROGRESSIVE(1 << 17) (1 << 17)
5229/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
5230# define TV_PAL_BURST(1 << 16) (1 << 16)
5231/* Field for setting delay of Y compared to C */
5232# define TV_YC_SKEW_MASK(7 << 12) (7 << 12)
5233/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5234# define TV_ENC_SDP_FIX(1 << 11) (1 << 11)
5235/*
5236 * Enables a fix for the 915GM only.
5237 *
5238 * Not sure what it does.
5239 */
5240# define TV_ENC_C0_FIX(1 << 10) (1 << 10)
5241/* Bits that must be preserved by software */
5242# define TV_CTL_SAVE((1 << 11) | (3 << 9) | (7 << 6) | 0xf) ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5243# define TV_FUSE_STATE_MASK(3 << 4) (3 << 4)
5244/* Read-only state that reports all features enabled */
5245# define TV_FUSE_STATE_ENABLED(0 << 4) (0 << 4)
5246/* Read-only state that reports that Macrovision is disabled in hardware*/
5247# define TV_FUSE_STATE_NO_MACROVISION(1 << 4) (1 << 4)
5248/* Read-only state that reports that TV-out is disabled in hardware. */
5249# define TV_FUSE_STATE_DISABLED(2 << 4) (2 << 4)
5250/* Normal operation */
5251# define TV_TEST_MODE_NORMAL(0 << 0) (0 << 0)
5252/* Encoder test pattern 1 - combo pattern */
5253# define TV_TEST_MODE_PATTERN_1(1 << 0) (1 << 0)
5254/* Encoder test pattern 2 - full screen vertical 75% color bars */
5255# define TV_TEST_MODE_PATTERN_2(2 << 0) (2 << 0)
5256/* Encoder test pattern 3 - full screen horizontal 75% color bars */
5257# define TV_TEST_MODE_PATTERN_3(3 << 0) (3 << 0)
5258/* Encoder test pattern 4 - random noise */
5259# define TV_TEST_MODE_PATTERN_4(4 << 0) (4 << 0)
5260/* Encoder test pattern 5 - linear color ramps */
5261# define TV_TEST_MODE_PATTERN_5(5 << 0) (5 << 0)
5262/*
5263 * This test mode forces the DACs to 50% of full output.
5264 *
5265 * This is used for load detection in combination with TVDAC_SENSE_MASK
5266 */
5267# define TV_TEST_MODE_MONITOR_DETECT(7 << 0) (7 << 0)
5268# define TV_TEST_MODE_MASK(7 << 0) (7 << 0)
5269
5270#define TV_DAC((const i915_reg_t){ .reg = (0x68004) }) _MMIO(0x68004)((const i915_reg_t){ .reg = (0x68004) })
5271# define TV_DAC_SAVE0x00ffff00 0x00ffff00
5272/*
5273 * Reports that DAC state change logic has reported change (RO).
5274 *
5275 * This gets cleared when TV_DAC_STATE_EN is cleared
5276*/
5277# define TVDAC_STATE_CHG(1 << 31) (1 << 31)
5278# define TVDAC_SENSE_MASK(7 << 28) (7 << 28)
5279/* Reports that DAC A voltage is above the detect threshold */
5280# define TVDAC_A_SENSE(1 << 30) (1 << 30)
5281/* Reports that DAC B voltage is above the detect threshold */
5282# define TVDAC_B_SENSE(1 << 29) (1 << 29)
5283/* Reports that DAC C voltage is above the detect threshold */
5284# define TVDAC_C_SENSE(1 << 28) (1 << 28)
5285/*
5286 * Enables DAC state detection logic, for load-based TV detection.
5287 *
5288 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5289 * to off, for load detection to work.
5290 */
5291# define TVDAC_STATE_CHG_EN(1 << 27) (1 << 27)
5292/* Sets the DAC A sense value to high */
5293# define TVDAC_A_SENSE_CTL(1 << 26) (1 << 26)
5294/* Sets the DAC B sense value to high */
5295# define TVDAC_B_SENSE_CTL(1 << 25) (1 << 25)
5296/* Sets the DAC C sense value to high */
5297# define TVDAC_C_SENSE_CTL(1 << 24) (1 << 24)
5298/* Overrides the ENC_ENABLE and DAC voltage levels */
5299# define DAC_CTL_OVERRIDE(1 << 7) (1 << 7)
5300/* Sets the slew rate. Must be preserved in software */
5301# define ENC_TVDAC_SLEW_FAST(1 << 6) (1 << 6)
5302# define DAC_A_1_3_V(0 << 4) (0 << 4)
5303# define DAC_A_1_1_V(1 << 4) (1 << 4)
5304# define DAC_A_0_7_V(2 << 4) (2 << 4)
5305# define DAC_A_MASK(3 << 4) (3 << 4)
5306# define DAC_B_1_3_V(0 << 2) (0 << 2)
5307# define DAC_B_1_1_V(1 << 2) (1 << 2)
5308# define DAC_B_0_7_V(2 << 2) (2 << 2)
5309# define DAC_B_MASK(3 << 2) (3 << 2)
5310# define DAC_C_1_3_V(0 << 0) (0 << 0)
5311# define DAC_C_1_1_V(1 << 0) (1 << 0)
5312# define DAC_C_0_7_V(2 << 0) (2 << 0)
5313# define DAC_C_MASK(3 << 0) (3 << 0)
5314
5315/*
5316 * CSC coefficients are stored in a floating point format with 9 bits of
5317 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5318 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5319 * -1 (0x3) being the only legal negative value.
5320 */
5321#define TV_CSC_Y((const i915_reg_t){ .reg = (0x68010) }) _MMIO(0x68010)((const i915_reg_t){ .reg = (0x68010) })
5322# define TV_RY_MASK0x07ff0000 0x07ff0000
5323# define TV_RY_SHIFT16 16
5324# define TV_GY_MASK0x00000fff 0x00000fff
5325# define TV_GY_SHIFT0 0
5326
5327#define TV_CSC_Y2((const i915_reg_t){ .reg = (0x68014) }) _MMIO(0x68014)((const i915_reg_t){ .reg = (0x68014) })
5328# define TV_BY_MASK0x07ff0000 0x07ff0000
5329# define TV_BY_SHIFT16 16
5330/*
5331 * Y attenuation for component video.
5332 *
5333 * Stored in 1.9 fixed point.
5334 */
5335# define TV_AY_MASK0x000003ff 0x000003ff
5336# define TV_AY_SHIFT0 0
5337
5338#define TV_CSC_U((const i915_reg_t){ .reg = (0x68018) }) _MMIO(0x68018)((const i915_reg_t){ .reg = (0x68018) })
5339# define TV_RU_MASK0x07ff0000 0x07ff0000
5340# define TV_RU_SHIFT16 16
5341# define TV_GU_MASK0x000007ff 0x000007ff
5342# define TV_GU_SHIFT0 0
5343
5344#define TV_CSC_U2((const i915_reg_t){ .reg = (0x6801c) }) _MMIO(0x6801c)((const i915_reg_t){ .reg = (0x6801c) })
5345# define TV_BU_MASK0x07ff0000 0x07ff0000
5346# define TV_BU_SHIFT16 16
5347/*
5348 * U attenuation for component video.
5349 *
5350 * Stored in 1.9 fixed point.
5351 */
5352# define TV_AU_MASK0x000003ff 0x000003ff
5353# define TV_AU_SHIFT0 0
5354
5355#define TV_CSC_V((const i915_reg_t){ .reg = (0x68020) }) _MMIO(0x68020)((const i915_reg_t){ .reg = (0x68020) })
5356# define TV_RV_MASK0x0fff0000 0x0fff0000
5357# define TV_RV_SHIFT16 16
5358# define TV_GV_MASK0x000007ff 0x000007ff
5359# define TV_GV_SHIFT0 0
5360
5361#define TV_CSC_V2((const i915_reg_t){ .reg = (0x68024) }) _MMIO(0x68024)((const i915_reg_t){ .reg = (0x68024) })
5362# define TV_BV_MASK0x07ff0000 0x07ff0000
5363# define TV_BV_SHIFT16 16
5364/*
5365 * V attenuation for component video.
5366 *
5367 * Stored in 1.9 fixed point.
5368 */
5369# define TV_AV_MASK0x000007ff 0x000007ff
5370# define TV_AV_SHIFT0 0
5371
5372#define TV_CLR_KNOBS((const i915_reg_t){ .reg = (0x68028) }) _MMIO(0x68028)((const i915_reg_t){ .reg = (0x68028) })
5373/* 2s-complement brightness adjustment */
5374# define TV_BRIGHTNESS_MASK0xff000000 0xff000000
5375# define TV_BRIGHTNESS_SHIFT24 24
5376/* Contrast adjustment, as a 2.6 unsigned floating point number */
5377# define TV_CONTRAST_MASK0x00ff0000 0x00ff0000
5378# define TV_CONTRAST_SHIFT16 16
5379/* Saturation adjustment, as a 2.6 unsigned floating point number */
5380# define TV_SATURATION_MASK0x0000ff00 0x0000ff00
5381# define TV_SATURATION_SHIFT8 8
5382/* Hue adjustment, as an integer phase angle in degrees */
5383# define TV_HUE_MASK0x000000ff 0x000000ff
5384# define TV_HUE_SHIFT0 0
5385
5386#define TV_CLR_LEVEL((const i915_reg_t){ .reg = (0x6802c) }) _MMIO(0x6802c)((const i915_reg_t){ .reg = (0x6802c) })
5387/* Controls the DAC level for black */
5388# define TV_BLACK_LEVEL_MASK0x01ff0000 0x01ff0000
5389# define TV_BLACK_LEVEL_SHIFT16 16
5390/* Controls the DAC level for blanking */
5391# define TV_BLANK_LEVEL_MASK0x000001ff 0x000001ff
5392# define TV_BLANK_LEVEL_SHIFT0 0
5393
5394#define TV_H_CTL_1((const i915_reg_t){ .reg = (0x68030) }) _MMIO(0x68030)((const i915_reg_t){ .reg = (0x68030) })
5395/* Number of pixels in the hsync. */
5396# define TV_HSYNC_END_MASK0x1fff0000 0x1fff0000
5397# define TV_HSYNC_END_SHIFT16 16
5398/* Total number of pixels minus one in the line (display and blanking). */
5399# define TV_HTOTAL_MASK0x00001fff 0x00001fff
5400# define TV_HTOTAL_SHIFT0 0
5401
5402#define TV_H_CTL_2((const i915_reg_t){ .reg = (0x68034) }) _MMIO(0x68034)((const i915_reg_t){ .reg = (0x68034) })
5403/* Enables the colorburst (needed for non-component color) */
5404# define TV_BURST_ENA(1 << 31) (1 << 31)
5405/* Offset of the colorburst from the start of hsync, in pixels minus one. */
5406# define TV_HBURST_START_SHIFT16 16
5407# define TV_HBURST_START_MASK0x1fff0000 0x1fff0000
5408/* Length of the colorburst */
5409# define TV_HBURST_LEN_SHIFT0 0
5410# define TV_HBURST_LEN_MASK0x0001fff 0x0001fff
5411
5412#define TV_H_CTL_3((const i915_reg_t){ .reg = (0x68038) }) _MMIO(0x68038)((const i915_reg_t){ .reg = (0x68038) })
5413/* End of hblank, measured in pixels minus one from start of hsync */
5414# define TV_HBLANK_END_SHIFT16 16
5415# define TV_HBLANK_END_MASK0x1fff0000 0x1fff0000
5416/* Start of hblank, measured in pixels minus one from start of hsync */
5417# define TV_HBLANK_START_SHIFT0 0
5418# define TV_HBLANK_START_MASK0x0001fff 0x0001fff
5419
5420#define TV_V_CTL_1((const i915_reg_t){ .reg = (0x6803c) }) _MMIO(0x6803c)((const i915_reg_t){ .reg = (0x6803c) })
5421/* XXX */
5422# define TV_NBR_END_SHIFT16 16
5423# define TV_NBR_END_MASK0x07ff0000 0x07ff0000
5424/* XXX */
5425# define TV_VI_END_F1_SHIFT8 8
5426# define TV_VI_END_F1_MASK0x00003f00 0x00003f00
5427/* XXX */
5428# define TV_VI_END_F2_SHIFT0 0
5429# define TV_VI_END_F2_MASK0x0000003f 0x0000003f
5430
5431#define TV_V_CTL_2((const i915_reg_t){ .reg = (0x68040) }) _MMIO(0x68040)((const i915_reg_t){ .reg = (0x68040) })
5432/* Length of vsync, in half lines */
5433# define TV_VSYNC_LEN_MASK0x07ff0000 0x07ff0000
5434# define TV_VSYNC_LEN_SHIFT16 16
5435/* Offset of the start of vsync in field 1, measured in one less than the
5436 * number of half lines.
5437 */
5438# define TV_VSYNC_START_F1_MASK0x00007f00 0x00007f00
5439# define TV_VSYNC_START_F1_SHIFT8 8
5440/*
5441 * Offset of the start of vsync in field 2, measured in one less than the
5442 * number of half lines.
5443 */
5444# define TV_VSYNC_START_F2_MASK0x0000007f 0x0000007f
5445# define TV_VSYNC_START_F2_SHIFT0 0
5446
5447#define TV_V_CTL_3((const i915_reg_t){ .reg = (0x68044) }) _MMIO(0x68044)((const i915_reg_t){ .reg = (0x68044) })
5448/* Enables generation of the equalization signal */
5449# define TV_EQUAL_ENA(1 << 31) (1 << 31)
5450/* Length of vsync, in half lines */
5451# define TV_VEQ_LEN_MASK0x007f0000 0x007f0000
5452# define TV_VEQ_LEN_SHIFT16 16
5453/* Offset of the start of equalization in field 1, measured in one less than
5454 * the number of half lines.
5455 */
5456# define TV_VEQ_START_F1_MASK0x0007f00 0x0007f00
5457# define TV_VEQ_START_F1_SHIFT8 8
5458/*
5459 * Offset of the start of equalization in field 2, measured in one less than
5460 * the number of half lines.
5461 */
5462# define TV_VEQ_START_F2_MASK0x000007f 0x000007f
5463# define TV_VEQ_START_F2_SHIFT0 0
5464
5465#define TV_V_CTL_4((const i915_reg_t){ .reg = (0x68048) }) _MMIO(0x68048)((const i915_reg_t){ .reg = (0x68048) })
5466/*
5467 * Offset to start of vertical colorburst, measured in one less than the
5468 * number of lines from vertical start.
5469 */
5470# define TV_VBURST_START_F1_MASK0x003f0000 0x003f0000
5471# define TV_VBURST_START_F1_SHIFT16 16
5472/*
5473 * Offset to the end of vertical colorburst, measured in one less than the
5474 * number of lines from the start of NBR.
5475 */
5476# define TV_VBURST_END_F1_MASK0x000000ff 0x000000ff
5477# define TV_VBURST_END_F1_SHIFT0 0
5478
5479#define TV_V_CTL_5((const i915_reg_t){ .reg = (0x6804c) }) _MMIO(0x6804c)((const i915_reg_t){ .reg = (0x6804c) })
5480/*
5481 * Offset to start of vertical colorburst, measured in one less than the
5482 * number of lines from vertical start.
5483 */
5484# define TV_VBURST_START_F2_MASK0x003f0000 0x003f0000
5485# define TV_VBURST_START_F2_SHIFT16 16
5486/*
5487 * Offset to the end of vertical colorburst, measured in one less than the
5488 * number of lines from the start of NBR.
5489 */
5490# define TV_VBURST_END_F2_MASK0x000000ff 0x000000ff
5491# define TV_VBURST_END_F2_SHIFT0 0
5492
5493#define TV_V_CTL_6((const i915_reg_t){ .reg = (0x68050) }) _MMIO(0x68050)((const i915_reg_t){ .reg = (0x68050) })
5494/*
5495 * Offset to start of vertical colorburst, measured in one less than the
5496 * number of lines from vertical start.
5497 */
5498# define TV_VBURST_START_F3_MASK0x003f0000 0x003f0000
5499# define TV_VBURST_START_F3_SHIFT16 16
5500/*
5501 * Offset to the end of vertical colorburst, measured in one less than the
5502 * number of lines from the start of NBR.
5503 */
5504# define TV_VBURST_END_F3_MASK0x000000ff 0x000000ff
5505# define TV_VBURST_END_F3_SHIFT0 0
5506
5507#define TV_V_CTL_7((const i915_reg_t){ .reg = (0x68054) }) _MMIO(0x68054)((const i915_reg_t){ .reg = (0x68054) })
5508/*
5509 * Offset to start of vertical colorburst, measured in one less than the
5510 * number of lines from vertical start.
5511 */
5512# define TV_VBURST_START_F4_MASK0x003f0000 0x003f0000
5513# define TV_VBURST_START_F4_SHIFT16 16
5514/*
5515 * Offset to the end of vertical colorburst, measured in one less than the
5516 * number of lines from the start of NBR.
5517 */
5518# define TV_VBURST_END_F4_MASK0x000000ff 0x000000ff
5519# define TV_VBURST_END_F4_SHIFT0 0
5520
5521#define TV_SC_CTL_1((const i915_reg_t){ .reg = (0x68060) }) _MMIO(0x68060)((const i915_reg_t){ .reg = (0x68060) })
5522/* Turns on the first subcarrier phase generation DDA */
5523# define TV_SC_DDA1_EN(1 << 31) (1 << 31)
5524/* Turns on the first subcarrier phase generation DDA */
5525# define TV_SC_DDA2_EN(1 << 30) (1 << 30)
5526/* Turns on the first subcarrier phase generation DDA */
5527# define TV_SC_DDA3_EN(1 << 29) (1 << 29)
5528/* Sets the subcarrier DDA to reset frequency every other field */
5529# define TV_SC_RESET_EVERY_2(0 << 24) (0 << 24)
5530/* Sets the subcarrier DDA to reset frequency every fourth field */
5531# define TV_SC_RESET_EVERY_4(1 << 24) (1 << 24)
5532/* Sets the subcarrier DDA to reset frequency every eighth field */
5533# define TV_SC_RESET_EVERY_8(2 << 24) (2 << 24)
5534/* Sets the subcarrier DDA to never reset the frequency */
5535# define TV_SC_RESET_NEVER(3 << 24) (3 << 24)
5536/* Sets the peak amplitude of the colorburst.*/
5537# define TV_BURST_LEVEL_MASK0x00ff0000 0x00ff0000
5538# define TV_BURST_LEVEL_SHIFT16 16
5539/* Sets the increment of the first subcarrier phase generation DDA */
5540# define TV_SCDDA1_INC_MASK0x00000fff 0x00000fff
5541# define TV_SCDDA1_INC_SHIFT0 0
5542
5543#define TV_SC_CTL_2((const i915_reg_t){ .reg = (0x68064) }) _MMIO(0x68064)((const i915_reg_t){ .reg = (0x68064) })
5544/* Sets the rollover for the second subcarrier phase generation DDA */
5545# define TV_SCDDA2_SIZE_MASK0x7fff0000 0x7fff0000
5546# define TV_SCDDA2_SIZE_SHIFT16 16
5547/* Sets the increent of the second subcarrier phase generation DDA */
5548# define TV_SCDDA2_INC_MASK0x00007fff 0x00007fff
5549# define TV_SCDDA2_INC_SHIFT0 0
5550
5551#define TV_SC_CTL_3((const i915_reg_t){ .reg = (0x68068) }) _MMIO(0x68068)((const i915_reg_t){ .reg = (0x68068) })
5552/* Sets the rollover for the third subcarrier phase generation DDA */
5553# define TV_SCDDA3_SIZE_MASK0x7fff0000 0x7fff0000
5554# define TV_SCDDA3_SIZE_SHIFT16 16
5555/* Sets the increent of the third subcarrier phase generation DDA */
5556# define TV_SCDDA3_INC_MASK0x00007fff 0x00007fff
5557# define TV_SCDDA3_INC_SHIFT0 0
5558
5559#define TV_WIN_POS((const i915_reg_t){ .reg = (0x68070) }) _MMIO(0x68070)((const i915_reg_t){ .reg = (0x68070) })
5560/* X coordinate of the display from the start of horizontal active */
5561# define TV_XPOS_MASK0x1fff0000 0x1fff0000
5562# define TV_XPOS_SHIFT16 16
5563/* Y coordinate of the display from the start of vertical active (NBR) */
5564# define TV_YPOS_MASK0x00000fff 0x00000fff
5565# define TV_YPOS_SHIFT0 0
5566
5567#define TV_WIN_SIZE((const i915_reg_t){ .reg = (0x68074) }) _MMIO(0x68074)((const i915_reg_t){ .reg = (0x68074) })
5568/* Horizontal size of the display window, measured in pixels*/
5569# define TV_XSIZE_MASK0x1fff0000 0x1fff0000
5570# define TV_XSIZE_SHIFT16 16
5571/*
5572 * Vertical size of the display window, measured in pixels.
5573 *
5574 * Must be even for interlaced modes.
5575 */
5576# define TV_YSIZE_MASK0x00000fff 0x00000fff
5577# define TV_YSIZE_SHIFT0 0
5578
5579#define TV_FILTER_CTL_1((const i915_reg_t){ .reg = (0x68080) }) _MMIO(0x68080)((const i915_reg_t){ .reg = (0x68080) })
5580/*
5581 * Enables automatic scaling calculation.
5582 *
5583 * If set, the rest of the registers are ignored, and the calculated values can
5584 * be read back from the register.
5585 */
5586# define TV_AUTO_SCALE(1 << 31) (1 << 31)
5587/*
5588 * Disables the vertical filter.
5589 *
5590 * This is required on modes more than 1024 pixels wide */
5591# define TV_V_FILTER_BYPASS(1 << 29) (1 << 29)
5592/* Enables adaptive vertical filtering */
5593# define TV_VADAPT(1 << 28) (1 << 28)
5594# define TV_VADAPT_MODE_MASK(3 << 26) (3 << 26)
5595/* Selects the least adaptive vertical filtering mode */
5596# define TV_VADAPT_MODE_LEAST(0 << 26) (0 << 26)
5597/* Selects the moderately adaptive vertical filtering mode */
5598# define TV_VADAPT_MODE_MODERATE(1 << 26) (1 << 26)
5599/* Selects the most adaptive vertical filtering mode */
5600# define TV_VADAPT_MODE_MOST(3 << 26) (3 << 26)
5601/*
5602 * Sets the horizontal scaling factor.
5603 *
5604 * This should be the fractional part of the horizontal scaling factor divided
5605 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5606 *
5607 * (src width - 1) / ((oversample * dest width) - 1)
5608 */
5609# define TV_HSCALE_FRAC_MASK0x00003fff 0x00003fff
5610# define TV_HSCALE_FRAC_SHIFT0 0
5611
5612#define TV_FILTER_CTL_2((const i915_reg_t){ .reg = (0x68084) }) _MMIO(0x68084)((const i915_reg_t){ .reg = (0x68084) })
5613/*
5614 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5615 *
5616 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5617 */
5618# define TV_VSCALE_INT_MASK0x00038000 0x00038000
5619# define TV_VSCALE_INT_SHIFT15 15
5620/*
5621 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5622 *
5623 * \sa TV_VSCALE_INT_MASK
5624 */
5625# define TV_VSCALE_FRAC_MASK0x00007fff 0x00007fff
5626# define TV_VSCALE_FRAC_SHIFT0 0
5627
5628#define TV_FILTER_CTL_3((const i915_reg_t){ .reg = (0x68088) }) _MMIO(0x68088)((const i915_reg_t){ .reg = (0x68088) })
5629/*
5630 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5631 *
5632 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5633 *
5634 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5635 */
5636# define TV_VSCALE_IP_INT_MASK0x00038000 0x00038000
5637# define TV_VSCALE_IP_INT_SHIFT15 15
5638/*
5639 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5640 *
5641 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5642 *
5643 * \sa TV_VSCALE_IP_INT_MASK
5644 */
5645# define TV_VSCALE_IP_FRAC_MASK0x00007fff 0x00007fff
5646# define TV_VSCALE_IP_FRAC_SHIFT0 0
5647
5648#define TV_CC_CONTROL((const i915_reg_t){ .reg = (0x68090) }) _MMIO(0x68090)((const i915_reg_t){ .reg = (0x68090) })
5649# define TV_CC_ENABLE(1 << 31) (1 << 31)
5650/*
5651 * Specifies which field to send the CC data in.
5652 *
5653 * CC data is usually sent in field 0.
5654 */
5655# define TV_CC_FID_MASK(1 << 27) (1 << 27)
5656# define TV_CC_FID_SHIFT27 27
5657/* Sets the horizontal position of the CC data. Usually 135. */
5658# define TV_CC_HOFF_MASK0x03ff0000 0x03ff0000
5659# define TV_CC_HOFF_SHIFT16 16
5660/* Sets the vertical position of the CC data. Usually 21 */
5661# define TV_CC_LINE_MASK0x0000003f 0x0000003f
5662# define TV_CC_LINE_SHIFT0 0
5663
5664#define TV_CC_DATA((const i915_reg_t){ .reg = (0x68094) }) _MMIO(0x68094)((const i915_reg_t){ .reg = (0x68094) })
5665# define TV_CC_RDY(1 << 31) (1 << 31)
5666/* Second word of CC data to be transmitted. */
5667# define TV_CC_DATA_2_MASK0x007f0000 0x007f0000
5668# define TV_CC_DATA_2_SHIFT16 16
5669/* First word of CC data to be transmitted. */
5670# define TV_CC_DATA_1_MASK0x0000007f 0x0000007f
5671# define TV_CC_DATA_1_SHIFT0 0
5672
5673#define TV_H_LUMA(i)((const i915_reg_t){ .reg = (0x68100 + (i) * 4) }) _MMIO(0x68100 + (i) * 4)((const i915_reg_t){ .reg = (0x68100 + (i) * 4) }) /* 60 registers */
5674#define TV_H_CHROMA(i)((const i915_reg_t){ .reg = (0x68200 + (i) * 4) }) _MMIO(0x68200 + (i) * 4)((const i915_reg_t){ .reg = (0x68200 + (i) * 4) }) /* 60 registers */
5675#define TV_V_LUMA(i)((const i915_reg_t){ .reg = (0x68300 + (i) * 4) }) _MMIO(0x68300 + (i) * 4)((const i915_reg_t){ .reg = (0x68300 + (i) * 4) }) /* 43 registers */
5676#define TV_V_CHROMA(i)((const i915_reg_t){ .reg = (0x68400 + (i) * 4) }) _MMIO(0x68400 + (i) * 4)((const i915_reg_t){ .reg = (0x68400 + (i) * 4) }) /* 43 registers */
5677
5678/* Display Port */
5679#define DP_A((const i915_reg_t){ .reg = (0x64000) }) _MMIO(0x64000)((const i915_reg_t){ .reg = (0x64000) }) /* eDP */
5680#define DP_B((const i915_reg_t){ .reg = (0x64100) }) _MMIO(0x64100)((const i915_reg_t){ .reg = (0x64100) })
5681#define DP_C((const i915_reg_t){ .reg = (0x64200) }) _MMIO(0x64200)((const i915_reg_t){ .reg = (0x64200) })
5682#define DP_D((const i915_reg_t){ .reg = (0x64300) }) _MMIO(0x64300)((const i915_reg_t){ .reg = (0x64300) })
5683
5684#define VLV_DP_B((const i915_reg_t){ .reg = (0x180000 + 0x64100) }) _MMIO(VLV_DISPLAY_BASE + 0x64100)((const i915_reg_t){ .reg = (0x180000 + 0x64100) })
5685#define VLV_DP_C((const i915_reg_t){ .reg = (0x180000 + 0x64200) }) _MMIO(VLV_DISPLAY_BASE + 0x64200)((const i915_reg_t){ .reg = (0x180000 + 0x64200) })
5686#define CHV_DP_D((const i915_reg_t){ .reg = (0x180000 + 0x64300) }) _MMIO(VLV_DISPLAY_BASE + 0x64300)((const i915_reg_t){ .reg = (0x180000 + 0x64300) })
5687
5688#define DP_PORT_EN(1 << 31) (1 << 31)
5689#define DP_PIPE_SEL_SHIFT30 30
5690#define DP_PIPE_SEL_MASK(1 << 30) (1 << 30)
5691#define DP_PIPE_SEL(pipe)((pipe) << 30) ((pipe) << 30)
5692#define DP_PIPE_SEL_SHIFT_IVB29 29
5693#define DP_PIPE_SEL_MASK_IVB(3 << 29) (3 << 29)
5694#define DP_PIPE_SEL_IVB(pipe)((pipe) << 29) ((pipe) << 29)
5695#define DP_PIPE_SEL_SHIFT_CHV16 16
5696#define DP_PIPE_SEL_MASK_CHV(3 << 16) (3 << 16)
5697#define DP_PIPE_SEL_CHV(pipe)((pipe) << 16) ((pipe) << 16)
5698
5699/* Link training mode - select a suitable mode for each stage */
5700#define DP_LINK_TRAIN_PAT_1(0 << 28) (0 << 28)
5701#define DP_LINK_TRAIN_PAT_2(1 << 28) (1 << 28)
5702#define DP_LINK_TRAIN_PAT_IDLE(2 << 28) (2 << 28)
5703#define DP_LINK_TRAIN_OFF(3 << 28) (3 << 28)
5704#define DP_LINK_TRAIN_MASK(3 << 28) (3 << 28)
5705#define DP_LINK_TRAIN_SHIFT28 28
5706
5707/* CPT Link training mode */
5708#define DP_LINK_TRAIN_PAT_1_CPT(0 << 8) (0 << 8)
5709#define DP_LINK_TRAIN_PAT_2_CPT(1 << 8) (1 << 8)
5710#define DP_LINK_TRAIN_PAT_IDLE_CPT(2 << 8) (2 << 8)
5711#define DP_LINK_TRAIN_OFF_CPT(3 << 8) (3 << 8)
5712#define DP_LINK_TRAIN_MASK_CPT(7 << 8) (7 << 8)
5713#define DP_LINK_TRAIN_SHIFT_CPT8 8
5714
5715/* Signal voltages. These are mostly controlled by the other end */
5716#define DP_VOLTAGE_0_4(0 << 25) (0 << 25)
5717#define DP_VOLTAGE_0_6(1 << 25) (1 << 25)
5718#define DP_VOLTAGE_0_8(2 << 25) (2 << 25)
5719#define DP_VOLTAGE_1_2(3 << 25) (3 << 25)
5720#define DP_VOLTAGE_MASK(7 << 25) (7 << 25)
5721#define DP_VOLTAGE_SHIFT25 25
5722
5723/* Signal pre-emphasis levels, like voltages, the other end tells us what
5724 * they want
5725 */
5726#define DP_PRE_EMPHASIS_0(0 << 22) (0 << 22)
5727#define DP_PRE_EMPHASIS_3_5(1 << 22) (1 << 22)
5728#define DP_PRE_EMPHASIS_6(2 << 22) (2 << 22)
5729#define DP_PRE_EMPHASIS_9_5(3 << 22) (3 << 22)
5730#define DP_PRE_EMPHASIS_MASK(7 << 22) (7 << 22)
5731#define DP_PRE_EMPHASIS_SHIFT22 22
5732
5733/* How many wires to use. I guess 3 was too hard */
5734#define DP_PORT_WIDTH(width)(((width) - 1) << 19) (((width) - 1) << 19)
5735#define DP_PORT_WIDTH_MASK(7 << 19) (7 << 19)
5736#define DP_PORT_WIDTH_SHIFT19 19
5737
5738/* Mystic DPCD version 1.1 special mode */
5739#define DP_ENHANCED_FRAMING(1 << 18) (1 << 18)
5740
5741/* eDP */
5742#define DP_PLL_FREQ_270MHZ(0 << 16) (0 << 16)
5743#define DP_PLL_FREQ_162MHZ(1 << 16) (1 << 16)
5744#define DP_PLL_FREQ_MASK(3 << 16) (3 << 16)
5745
5746/* locked once port is enabled */
5747#define DP_PORT_REVERSAL(1 << 15) (1 << 15)
5748
5749/* eDP */
5750#define DP_PLL_ENABLE(1 << 14) (1 << 14)
5751
5752/* sends the clock on lane 15 of the PEG for debug */
5753#define DP_CLOCK_OUTPUT_ENABLE(1 << 13) (1 << 13)
5754
5755#define DP_SCRAMBLING_DISABLE(1 << 12) (1 << 12)
5756#define DP_SCRAMBLING_DISABLE_IRONLAKE(1 << 7) (1 << 7)
5757
5758/* limit RGB values to avoid confusing TVs */
5759#define DP_COLOR_RANGE_16_235(1 << 8) (1 << 8)
5760
5761/* Turn on the audio link */
5762#define DP_AUDIO_OUTPUT_ENABLE(1 << 6) (1 << 6)
5763
5764/* vs and hs sync polarity */
5765#define DP_SYNC_VS_HIGH(1 << 4) (1 << 4)
5766#define DP_SYNC_HS_HIGH(1 << 3) (1 << 3)
5767
5768/* A fantasy */
5769#define DP_DETECTED(1 << 2) (1 << 2)
5770
5771/* The aux channel provides a way to talk to the
5772 * signal sink for DDC etc. Max packet size supported
5773 * is 20 bytes in each direction, hence the 5 fixed
5774 * data registers
5775 */
5776#define _DPA_AUX_CH_CTL(((&(dev_priv)->__info)->display_mmio_offset) + 0x64010
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x64010)
5777#define _DPA_AUX_CH_DATA1(((&(dev_priv)->__info)->display_mmio_offset) + 0x64014
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x64014)
5778
5779#define _DPB_AUX_CH_CTL(((&(dev_priv)->__info)->display_mmio_offset) + 0x64110
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x64110)
5780#define _DPB_AUX_CH_DATA1(((&(dev_priv)->__info)->display_mmio_offset) + 0x64114
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x64114)
5781
5782#define DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x64010)) + (aux_ch) * (((((&
(dev_priv)->__info)->display_mmio_offset) + 0x64110)) -
((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010
))))) }) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x64010)) + (aux_ch) * (((((&
(dev_priv)->__info)->display_mmio_offset) + 0x64110)) -
((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010
))))) })
5783#define DP_AUX_CH_DATA(aux_ch, i)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x64014)) + (aux_ch) * (((((&
(dev_priv)->__info)->display_mmio_offset) + 0x64114)) -
((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014
)))) + (i) * 4) }) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display_mmio_offset) + 0x64014)) + (aux_ch) * (((((&
(dev_priv)->__info)->display_mmio_offset) + 0x64114)) -
((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014
)))) + (i) * 4) }) /* 5 registers */
5784
5785#define DP_AUX_CH_CTL_SEND_BUSY(1 << 31) (1 << 31)
5786#define DP_AUX_CH_CTL_DONE(1 << 30) (1 << 30)
5787#define DP_AUX_CH_CTL_INTERRUPT(1 << 29) (1 << 29)
5788#define DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28) (1 << 28)
5789#define DP_AUX_CH_CTL_TIME_OUT_400us(0 << 26) (0 << 26)
5790#define DP_AUX_CH_CTL_TIME_OUT_600us(1 << 26) (1 << 26)
5791#define DP_AUX_CH_CTL_TIME_OUT_800us(2 << 26) (2 << 26)
5792#define DP_AUX_CH_CTL_TIME_OUT_MAX(3 << 26) (3 << 26) /* Varies per platform */
5793#define DP_AUX_CH_CTL_TIME_OUT_MASK(3 << 26) (3 << 26)
5794#define DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25) (1 << 25)
5795#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK(0x1f << 20) (0x1f << 20)
5796#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT20 20
5797#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK(0xf << 16) (0xf << 16)
5798#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT16 16
5799#define DP_AUX_CH_CTL_AUX_AKSV_SELECT(1 << 15) (1 << 15)
5800#define DP_AUX_CH_CTL_MANCHESTER_TEST(1 << 14) (1 << 14)
5801#define DP_AUX_CH_CTL_SYNC_TEST(1 << 13) (1 << 13)
5802#define DP_AUX_CH_CTL_DEGLITCH_TEST(1 << 12) (1 << 12)
5803#define DP_AUX_CH_CTL_PRECHARGE_TEST(1 << 11) (1 << 11)
5804#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK(0x7ff) (0x7ff)
5805#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT0 0
5806#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL(1 << 14) (1 << 14)
5807#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL(1 << 13) (1 << 13)
5808#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL(1 << 12) (1 << 12)
5809#define DP_AUX_CH_CTL_TBT_IO(1 << 11) (1 << 11)
5810#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK(0x1f << 5) (0x1f << 5)
5811#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c)(((c) - 1) << 5) (((c) - 1) << 5)
5812#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)((c) - 1) ((c) - 1)
5813
5814/*
5815 * Computing GMCH M and N values for the Display Port link
5816 *
5817 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5818 *
5819 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5820 *
5821 * The GMCH value is used internally
5822 *
5823 * bytes_per_pixel is the number of bytes coming out of the plane,
5824 * which is after the LUTs, so we want the bytes for our color format.
5825 * For our current usage, this is always 3, one byte for R, G and B.
5826 */
5827#define _PIPEA_DATA_M_G4X0x70050 0x70050
5828#define _PIPEB_DATA_M_G4X0x71050 0x71050
5829
5830/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5831#define TU_SIZE(x)(((x) - 1) << 25) (((x) - 1) << 25) /* default size 64 */
5832#define TU_SIZE_SHIFT25 25
5833#define TU_SIZE_MASK(0x3f << 25) (0x3f << 25)
5834
5835#define DATA_LINK_M_N_MASK(0xffffff) (0xffffff)
5836#define DATA_LINK_N_MAX(0x800000) (0x800000)
5837
5838#define _PIPEA_DATA_N_G4X0x70054 0x70054
5839#define _PIPEB_DATA_N_G4X0x71054 0x71054
5840#define PIPE_GMCH_DATA_N_MASK(0xffffff) (0xffffff)
5841
5842/*
5843 * Computing Link M and N values for the Display Port link
5844 *
5845 * Link M / N = pixel_clock / ls_clk
5846 *
5847 * (the DP spec calls pixel_clock the 'strm_clk')
5848 *
5849 * The Link value is transmitted in the Main Stream
5850 * Attributes and VB-ID.
5851 */
5852
5853#define _PIPEA_LINK_M_G4X0x70060 0x70060
5854#define _PIPEB_LINK_M_G4X0x71060 0x71060
5855#define PIPEA_DP_LINK_M_MASK(0xffffff) (0xffffff)
5856
5857#define _PIPEA_LINK_N_G4X0x70064 0x70064
5858#define _PIPEB_LINK_N_G4X0x71064 0x71064
5859#define PIPEA_DP_LINK_N_MASK(0xffffff) (0xffffff)
5860
5861#define PIPE_DATA_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70050) + (pipe) * ((0x71050)
- (0x70050)))) }) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)((const i915_reg_t){ .reg = (((0x70050) + (pipe) * ((0x71050)
- (0x70050)))) })
5862#define PIPE_DATA_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70054) + (pipe) * ((0x71054)
- (0x70054)))) }) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)((const i915_reg_t){ .reg = (((0x70054) + (pipe) * ((0x71054)
- (0x70054)))) })
5863#define PIPE_LINK_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70060) + (pipe) * ((0x71060)
- (0x70060)))) }) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)((const i915_reg_t){ .reg = (((0x70060) + (pipe) * ((0x71060)
- (0x70060)))) })
5864#define PIPE_LINK_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70064) + (pipe) * ((0x71064)
- (0x70064)))) }) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)((const i915_reg_t){ .reg = (((0x70064) + (pipe) * ((0x71064)
- (0x70064)))) })
5865
5866/* Display & cursor control */
5867
5868/* Pipe A */
5869#define _PIPEADSL0x70000 0x70000
5870#define DSL_LINEMASK_GEN20x00000fff 0x00000fff
5871#define DSL_LINEMASK_GEN30x00001fff 0x00001fff
5872#define _PIPEACONF0x70008 0x70008
5873#define PIPECONF_ENABLE(1 << 31) (1 << 31)
5874#define PIPECONF_DISABLE0 0
5875#define PIPECONF_DOUBLE_WIDE(1 << 30) (1 << 30)
5876#define I965_PIPECONF_ACTIVE(1 << 30) (1 << 30)
5877#define PIPECONF_DSI_PLL_LOCKED(1 << 29) (1 << 29) /* vlv & pipe A only */
5878#define PIPECONF_FRAME_START_DELAY_MASK(3 << 27) (3 << 27) /* pre-hsw */
5879#define PIPECONF_FRAME_START_DELAY(x)((x) << 27) ((x) << 27) /* pre-hsw: 0-3 */
5880#define PIPECONF_SINGLE_WIDE0 0
5881#define PIPECONF_PIPE_UNLOCKED0 0
5882#define PIPECONF_PIPE_LOCKED(1 << 25) (1 << 25)
5883#define PIPECONF_FORCE_BORDER(1 << 25) (1 << 25)
5884#define PIPECONF_GAMMA_MODE_MASK_I9XX(1 << 24) (1 << 24) /* gmch */
5885#define PIPECONF_GAMMA_MODE_MASK_ILK(3 << 24) (3 << 24) /* ilk-ivb */
5886#define PIPECONF_GAMMA_MODE_8BIT(0 << 24) (0 << 24) /* gmch,ilk-ivb */
5887#define PIPECONF_GAMMA_MODE_10BIT(1 << 24) (1 << 24) /* gmch,ilk-ivb */
5888#define PIPECONF_GAMMA_MODE_12BIT(2 << 24) (2 << 24) /* ilk-ivb */
5889#define PIPECONF_GAMMA_MODE_SPLIT(3 << 24) (3 << 24) /* ivb */
5890#define PIPECONF_GAMMA_MODE(x)((x) << 24) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5891#define PIPECONF_GAMMA_MODE_SHIFT24 24
5892#define PIPECONF_INTERLACE_MASK(7 << 21) (7 << 21)
5893#define PIPECONF_INTERLACE_MASK_HSW(3 << 21) (3 << 21)
5894/* Note that pre-gen3 does not support interlaced display directly. Panel
5895 * fitting must be disabled on pre-ilk for interlaced. */
5896#define PIPECONF_PROGRESSIVE(0 << 21) (0 << 21)
5897#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL(4 << 21) (4 << 21) /* gen4 only */
5898#define PIPECONF_INTERLACE_W_SYNC_SHIFT(5 << 21) (5 << 21) /* gen4 only */
5899#define PIPECONF_INTERLACE_W_FIELD_INDICATION(6 << 21) (6 << 21)
5900#define PIPECONF_INTERLACE_FIELD_0_ONLY(7 << 21) (7 << 21) /* gen3 only */
5901/* Ironlake and later have a complete new set of values for interlaced. PFIT
5902 * means panel fitter required, PF means progressive fetch, DBL means power
5903 * saving pixel doubling. */
5904#define PIPECONF_PFIT_PF_INTERLACED_ILK(1 << 21) (1 << 21)
5905#define PIPECONF_INTERLACED_ILK(3 << 21) (3 << 21)
5906#define PIPECONF_INTERLACED_DBL_ILK(4 << 21) (4 << 21) /* ilk/snb only */
5907#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK(5 << 21) (5 << 21) /* ilk/snb only */
5908#define PIPECONF_INTERLACE_MODE_MASK(7 << 21) (7 << 21)
5909#define PIPECONF_EDP_RR_MODE_SWITCH(1 << 20) (1 << 20)
5910#define PIPECONF_CXSR_DOWNCLOCK(1 << 16) (1 << 16)
5911#define PIPECONF_EDP_RR_MODE_SWITCH_VLV(1 << 14) (1 << 14)
5912#define PIPECONF_COLOR_RANGE_SELECT(1 << 13) (1 << 13)
5913#define PIPECONF_OUTPUT_COLORSPACE_MASK(3 << 11) (3 << 11) /* ilk-ivb */
5914#define PIPECONF_OUTPUT_COLORSPACE_RGB(0 << 11) (0 << 11) /* ilk-ivb */
5915#define PIPECONF_OUTPUT_COLORSPACE_YUV601(1 << 11) (1 << 11) /* ilk-ivb */
5916#define PIPECONF_OUTPUT_COLORSPACE_YUV709(2 << 11) (2 << 11) /* ilk-ivb */
5917#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW(1 << 11) (1 << 11) /* hsw only */
5918#define PIPECONF_BPC_MASK(0x7 << 5) (0x7 << 5)
5919#define PIPECONF_8BPC(0 << 5) (0 << 5)
5920#define PIPECONF_10BPC(1 << 5) (1 << 5)
5921#define PIPECONF_6BPC(2 << 5) (2 << 5)
5922#define PIPECONF_12BPC(3 << 5) (3 << 5)
5923#define PIPECONF_DITHER_EN(1 << 4) (1 << 4)
5924#define PIPECONF_DITHER_TYPE_MASK(0x0000000c) (0x0000000c)
5925#define PIPECONF_DITHER_TYPE_SP(0 << 2) (0 << 2)
5926#define PIPECONF_DITHER_TYPE_ST1(1 << 2) (1 << 2)
5927#define PIPECONF_DITHER_TYPE_ST2(2 << 2) (2 << 2)
5928#define PIPECONF_DITHER_TYPE_TEMP(3 << 2) (3 << 2)
5929#define _PIPEASTAT0x70024 0x70024
5930#define PIPE_FIFO_UNDERRUN_STATUS(1UL << 31) (1UL << 31)
5931#define SPRITE1_FLIP_DONE_INT_EN_VLV(1UL << 30) (1UL << 30)
5932#define PIPE_CRC_ERROR_ENABLE(1UL << 29) (1UL << 29)
5933#define PIPE_CRC_DONE_ENABLE(1UL << 28) (1UL << 28)
5934#define PERF_COUNTER2_INTERRUPT_EN(1UL << 27) (1UL << 27)
5935#define PIPE_GMBUS_EVENT_ENABLE(1UL << 27) (1UL << 27)
5936#define PLANE_FLIP_DONE_INT_EN_VLV(1UL << 26) (1UL << 26)
5937#define PIPE_HOTPLUG_INTERRUPT_ENABLE(1UL << 26) (1UL << 26)
5938#define PIPE_VSYNC_INTERRUPT_ENABLE(1UL << 25) (1UL << 25)
5939#define PIPE_DISPLAY_LINE_COMPARE_ENABLE(1UL << 24) (1UL << 24)
5940#define PIPE_DPST_EVENT_ENABLE(1UL << 23) (1UL << 23)
5941#define SPRITE0_FLIP_DONE_INT_EN_VLV(1UL << 22) (1UL << 22)
5942#define PIPE_LEGACY_BLC_EVENT_ENABLE(1UL << 22) (1UL << 22)
5943#define PIPE_ODD_FIELD_INTERRUPT_ENABLE(1UL << 21) (1UL << 21)
5944#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE(1UL << 20) (1UL << 20)
5945#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV(1UL << 19) (1UL << 19)
5946#define PERF_COUNTER_INTERRUPT_EN(1UL << 19) (1UL << 19)
5947#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE(1UL << 18) (1UL << 18) /* pre-965 */
5948#define PIPE_START_VBLANK_INTERRUPT_ENABLE(1UL << 18) (1UL << 18) /* 965 or later */
5949#define PIPE_FRAMESTART_INTERRUPT_ENABLE(1UL << 17) (1UL << 17)
5950#define PIPE_VBLANK_INTERRUPT_ENABLE(1UL << 17) (1UL << 17)
5951#define PIPEA_HBLANK_INT_EN_VLV(1UL << 16) (1UL << 16)
5952#define PIPE_OVERLAY_UPDATED_ENABLE(1UL << 16) (1UL << 16)
5953#define SPRITE1_FLIP_DONE_INT_STATUS_VLV(1UL << 15) (1UL << 15)
5954#define SPRITE0_FLIP_DONE_INT_STATUS_VLV(1UL << 14) (1UL << 14)
5955#define PIPE_CRC_ERROR_INTERRUPT_STATUS(1UL << 13) (1UL << 13)
5956#define PIPE_CRC_DONE_INTERRUPT_STATUS(1UL << 12) (1UL << 12)
5957#define PERF_COUNTER2_INTERRUPT_STATUS(1UL << 11) (1UL << 11)
5958#define PIPE_GMBUS_INTERRUPT_STATUS(1UL << 11) (1UL << 11)
5959#define PLANE_FLIP_DONE_INT_STATUS_VLV(1UL << 10) (1UL << 10)
5960#define PIPE_HOTPLUG_INTERRUPT_STATUS(1UL << 10) (1UL << 10)
5961#define PIPE_VSYNC_INTERRUPT_STATUS(1UL << 9) (1UL << 9)
5962#define PIPE_DISPLAY_LINE_COMPARE_STATUS(1UL << 8) (1UL << 8)
5963#define PIPE_DPST_EVENT_STATUS(1UL << 7) (1UL << 7)
5964#define PIPE_A_PSR_STATUS_VLV(1UL << 6) (1UL << 6)
5965#define PIPE_LEGACY_BLC_EVENT_STATUS(1UL << 6) (1UL << 6)
5966#define PIPE_ODD_FIELD_INTERRUPT_STATUS(1UL << 5) (1UL << 5)
5967#define PIPE_EVEN_FIELD_INTERRUPT_STATUS(1UL << 4) (1UL << 4)
5968#define PIPE_B_PSR_STATUS_VLV(1UL << 3) (1UL << 3)
5969#define PERF_COUNTER_INTERRUPT_STATUS(1UL << 3) (1UL << 3)
5970#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS(1UL << 2) (1UL << 2) /* pre-965 */
5971#define PIPE_START_VBLANK_INTERRUPT_STATUS(1UL << 2) (1UL << 2) /* 965 or later */
5972#define PIPE_FRAMESTART_INTERRUPT_STATUS(1UL << 1) (1UL << 1)
5973#define PIPE_VBLANK_INTERRUPT_STATUS(1UL << 1) (1UL << 1)
5974#define PIPE_HBLANK_INT_STATUS(1UL << 0) (1UL << 0)
5975#define PIPE_OVERLAY_UPDATED_STATUS(1UL << 0) (1UL << 0)
5976
5977#define PIPESTAT_INT_ENABLE_MASK0x7fff0000 0x7fff0000
5978#define PIPESTAT_INT_STATUS_MASK0x0000ffff 0x0000ffff
5979
5980#define PIPE_A_OFFSET0x70000 0x70000
5981#define PIPE_B_OFFSET0x71000 0x71000
5982#define PIPE_C_OFFSET0x72000 0x72000
5983#define PIPE_D_OFFSET0x73000 0x73000
5984#define CHV_PIPE_C_OFFSET0x74000 0x74000
5985/*
5986 * There's actually no pipe EDP. Some pipe registers have
5987 * simply shifted from the pipe to the transcoder, while
5988 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5989 * to access such registers in transcoder EDP.
5990 */
5991#define PIPE_EDP_OFFSET0x7f000 0x7f000
5992
5993/* ICL DSI 0 and 1 */
5994#define PIPE_DSI0_OFFSET0x7b000 0x7b000
5995#define PIPE_DSI1_OFFSET0x7b800 0x7b800
5996
5997#define PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEACONF)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
5998#define PIPEDSL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70000) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEADSL)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70000) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
5999#define PIPEFRAME(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70040) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70040) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6000#define PIPEFRAMEPIXEL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70044) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70044) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6001#define PIPESTAT(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70024) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEASTAT)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70024) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6002
6003#define _PIPEAGCMAX0x70010 0x70010
6004#define _PIPEBGCMAX0x71010 0x71010
6005#define PIPEGCMAX(pipe, i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70010 + (i) * 4) + ((&(dev_priv)->__info
)->display_mmio_offset)) }) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70010 + (i) * 4) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
6006
6007#define _PIPE_MISC_A0x70030 0x70030
6008#define _PIPE_MISC_B0x71030 0x71030
6009#define PIPEMISC_YUV420_ENABLE(1 << 27) (1 << 27) /* glk+ */
6010#define PIPEMISC_YUV420_MODE_FULL_BLEND(1 << 26) (1 << 26) /* glk+ */
6011#define PIPEMISC_HDR_MODE_PRECISION(1 << 23) (1 << 23) /* icl+ */
6012#define PIPEMISC_OUTPUT_COLORSPACE_YUV(1 << 11) (1 << 11)
6013#define PIPEMISC_PIXEL_ROUNDING_TRUNC((u32)((1UL << (8)) + 0)) REG_BIT(8)((u32)((1UL << (8)) + 0)) /* tgl+ */
6014#define PIPEMISC_DITHER_BPC_MASK(7 << 5) (7 << 5)
6015#define PIPEMISC_DITHER_8_BPC(0 << 5) (0 << 5)
6016#define PIPEMISC_DITHER_10_BPC(1 << 5) (1 << 5)
6017#define PIPEMISC_DITHER_6_BPC(2 << 5) (2 << 5)
6018#define PIPEMISC_DITHER_12_BPC(3 << 5) (3 << 5)
6019#define PIPEMISC_DITHER_ENABLE(1 << 4) (1 << 4)
6020#define PIPEMISC_DITHER_TYPE_MASK(3 << 2) (3 << 2)
6021#define PIPEMISC_DITHER_TYPE_SP(0 << 2) (0 << 2)
6022#define PIPEMISC(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70030) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPE_MISC_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70030) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6023
6024/* Skylake+ pipe bottom (background) color */
6025#define _SKL_BOTTOM_COLOR_A0x70034 0x70034
6026#define SKL_BOTTOM_COLOR_GAMMA_ENABLE(1 << 31) (1 << 31)
6027#define SKL_BOTTOM_COLOR_CSC_ENABLE(1 << 30) (1 << 30)
6028#define SKL_BOTTOM_COLOR(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70034) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70034) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6029
6030#define VLV_DPFLIPSTAT((const i915_reg_t){ .reg = (0x180000 + 0x70028) }) _MMIO(VLV_DISPLAY_BASE + 0x70028)((const i915_reg_t){ .reg = (0x180000 + 0x70028) })
6031#define PIPEB_LINE_COMPARE_INT_EN(1 << 29) (1 << 29)
6032#define PIPEB_HLINE_INT_EN(1 << 28) (1 << 28)
6033#define PIPEB_VBLANK_INT_EN(1 << 27) (1 << 27)
6034#define SPRITED_FLIP_DONE_INT_EN(1 << 26) (1 << 26)
6035#define SPRITEC_FLIP_DONE_INT_EN(1 << 25) (1 << 25)
6036#define PLANEB_FLIP_DONE_INT_EN(1 << 24) (1 << 24)
6037#define PIPE_PSR_INT_EN(1 << 22) (1 << 22)
6038#define PIPEA_LINE_COMPARE_INT_EN(1 << 21) (1 << 21)
6039#define PIPEA_HLINE_INT_EN(1 << 20) (1 << 20)
6040#define PIPEA_VBLANK_INT_EN(1 << 19) (1 << 19)
6041#define SPRITEB_FLIP_DONE_INT_EN(1 << 18) (1 << 18)
6042#define SPRITEA_FLIP_DONE_INT_EN(1 << 17) (1 << 17)
6043#define PLANEA_FLIPDONE_INT_EN(1 << 16) (1 << 16)
6044#define PIPEC_LINE_COMPARE_INT_EN(1 << 13) (1 << 13)
6045#define PIPEC_HLINE_INT_EN(1 << 12) (1 << 12)
6046#define PIPEC_VBLANK_INT_EN(1 << 11) (1 << 11)
6047#define SPRITEF_FLIPDONE_INT_EN(1 << 10) (1 << 10)
6048#define SPRITEE_FLIPDONE_INT_EN(1 << 9) (1 << 9)
6049#define PLANEC_FLIPDONE_INT_EN(1 << 8) (1 << 8)
6050
6051#define DPINVGTT((const i915_reg_t){ .reg = (0x180000 + 0x7002c) }) _MMIO(VLV_DISPLAY_BASE + 0x7002c)((const i915_reg_t){ .reg = (0x180000 + 0x7002c) }) /* VLV/CHV only */
6052#define SPRITEF_INVALID_GTT_INT_EN(1 << 27) (1 << 27)
6053#define SPRITEE_INVALID_GTT_INT_EN(1 << 26) (1 << 26)
6054#define PLANEC_INVALID_GTT_INT_EN(1 << 25) (1 << 25)
6055#define CURSORC_INVALID_GTT_INT_EN(1 << 24) (1 << 24)
6056#define CURSORB_INVALID_GTT_INT_EN(1 << 23) (1 << 23)
6057#define CURSORA_INVALID_GTT_INT_EN(1 << 22) (1 << 22)
6058#define SPRITED_INVALID_GTT_INT_EN(1 << 21) (1 << 21)
6059#define SPRITEC_INVALID_GTT_INT_EN(1 << 20) (1 << 20)
6060#define PLANEB_INVALID_GTT_INT_EN(1 << 19) (1 << 19)
6061#define SPRITEB_INVALID_GTT_INT_EN(1 << 18) (1 << 18)
6062#define SPRITEA_INVALID_GTT_INT_EN(1 << 17) (1 << 17)
6063#define PLANEA_INVALID_GTT_INT_EN(1 << 16) (1 << 16)
6064#define DPINVGTT_EN_MASK0xff0000 0xff0000
6065#define DPINVGTT_EN_MASK_CHV0xfff0000 0xfff0000
6066#define SPRITEF_INVALID_GTT_STATUS(1 << 11) (1 << 11)
6067#define SPRITEE_INVALID_GTT_STATUS(1 << 10) (1 << 10)
6068#define PLANEC_INVALID_GTT_STATUS(1 << 9) (1 << 9)
6069#define CURSORC_INVALID_GTT_STATUS(1 << 8) (1 << 8)
6070#define CURSORB_INVALID_GTT_STATUS(1 << 7) (1 << 7)
6071#define CURSORA_INVALID_GTT_STATUS(1 << 6) (1 << 6)
6072#define SPRITED_INVALID_GTT_STATUS(1 << 5) (1 << 5)
6073#define SPRITEC_INVALID_GTT_STATUS(1 << 4) (1 << 4)
6074#define PLANEB_INVALID_GTT_STATUS(1 << 3) (1 << 3)
6075#define SPRITEB_INVALID_GTT_STATUS(1 << 2) (1 << 2)
6076#define SPRITEA_INVALID_GTT_STATUS(1 << 1) (1 << 1)
6077#define PLANEA_INVALID_GTT_STATUS(1 << 0) (1 << 0)
6078#define DPINVGTT_STATUS_MASK0xff 0xff
6079#define DPINVGTT_STATUS_MASK_CHV0xfff 0xfff
6080
6081#define DSPARB((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70030) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70030) })
6082#define DSPARB_CSTART_MASK(0x7f << 7) (0x7f << 7)
6083#define DSPARB_CSTART_SHIFT7 7
6084#define DSPARB_BSTART_MASK(0x7f) (0x7f)
6085#define DSPARB_BSTART_SHIFT0 0
6086#define DSPARB_BEND_SHIFT9 9 /* on 855 */
6087#define DSPARB_AEND_SHIFT0 0
6088#define DSPARB_SPRITEA_SHIFT_VLV0 0
6089#define DSPARB_SPRITEA_MASK_VLV(0xff << 0) (0xff << 0)
6090#define DSPARB_SPRITEB_SHIFT_VLV8 8
6091#define DSPARB_SPRITEB_MASK_VLV(0xff << 8) (0xff << 8)
6092#define DSPARB_SPRITEC_SHIFT_VLV16 16
6093#define DSPARB_SPRITEC_MASK_VLV(0xff << 16) (0xff << 16)
6094#define DSPARB_SPRITED_SHIFT_VLV24 24
6095#define DSPARB_SPRITED_MASK_VLV(0xff << 24) (0xff << 24)
6096#define DSPARB2((const i915_reg_t){ .reg = (0x180000 + 0x70060) }) _MMIO(VLV_DISPLAY_BASE + 0x70060)((const i915_reg_t){ .reg = (0x180000 + 0x70060) }) /* vlv/chv */
6097#define DSPARB_SPRITEA_HI_SHIFT_VLV0 0
6098#define DSPARB_SPRITEA_HI_MASK_VLV(0x1 << 0) (0x1 << 0)
6099#define DSPARB_SPRITEB_HI_SHIFT_VLV4 4
6100#define DSPARB_SPRITEB_HI_MASK_VLV(0x1 << 4) (0x1 << 4)
6101#define DSPARB_SPRITEC_HI_SHIFT_VLV8 8
6102#define DSPARB_SPRITEC_HI_MASK_VLV(0x1 << 8) (0x1 << 8)
6103#define DSPARB_SPRITED_HI_SHIFT_VLV12 12
6104#define DSPARB_SPRITED_HI_MASK_VLV(0x1 << 12) (0x1 << 12)
6105#define DSPARB_SPRITEE_HI_SHIFT_VLV16 16
6106#define DSPARB_SPRITEE_HI_MASK_VLV(0x1 << 16) (0x1 << 16)
6107#define DSPARB_SPRITEF_HI_SHIFT_VLV20 20
6108#define DSPARB_SPRITEF_HI_MASK_VLV(0x1 << 20) (0x1 << 20)
6109#define DSPARB3((const i915_reg_t){ .reg = (0x180000 + 0x7006c) }) _MMIO(VLV_DISPLAY_BASE + 0x7006c)((const i915_reg_t){ .reg = (0x180000 + 0x7006c) }) /* chv */
6110#define DSPARB_SPRITEE_SHIFT_VLV0 0
6111#define DSPARB_SPRITEE_MASK_VLV(0xff << 0) (0xff << 0)
6112#define DSPARB_SPRITEF_SHIFT_VLV8 8
6113#define DSPARB_SPRITEF_MASK_VLV(0xff << 8) (0xff << 8)
6114
6115/* pnv/gen4/g4x/vlv/chv */
6116#define DSPFW1((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70034) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70034) })
6117#define DSPFW_SR_SHIFT23 23
6118#define DSPFW_SR_MASK(0x1ff << 23) (0x1ff << 23)
6119#define DSPFW_CURSORB_SHIFT16 16
6120#define DSPFW_CURSORB_MASK(0x3f << 16) (0x3f << 16)
6121#define DSPFW_PLANEB_SHIFT8 8
6122#define DSPFW_PLANEB_MASK(0x7f << 8) (0x7f << 8)
6123#define DSPFW_PLANEB_MASK_VLV(0xff << 8) (0xff << 8) /* vlv/chv */
6124#define DSPFW_PLANEA_SHIFT0 0
6125#define DSPFW_PLANEA_MASK(0x7f << 0) (0x7f << 0)
6126#define DSPFW_PLANEA_MASK_VLV(0xff << 0) (0xff << 0) /* vlv/chv */
6127#define DSPFW2((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70038) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70038) })
6128#define DSPFW_FBC_SR_EN(1 << 31) (1 << 31) /* g4x */
6129#define DSPFW_FBC_SR_SHIFT28 28
6130#define DSPFW_FBC_SR_MASK(0x7 << 28) (0x7 << 28) /* g4x */
6131#define DSPFW_FBC_HPLL_SR_SHIFT24 24
6132#define DSPFW_FBC_HPLL_SR_MASK(0xf << 24) (0xf << 24) /* g4x */
6133#define DSPFW_SPRITEB_SHIFT(16) (16)
6134#define DSPFW_SPRITEB_MASK(0x7f << 16) (0x7f << 16) /* g4x */
6135#define DSPFW_SPRITEB_MASK_VLV(0xff << 16) (0xff << 16) /* vlv/chv */
6136#define DSPFW_CURSORA_SHIFT8 8
6137#define DSPFW_CURSORA_MASK(0x3f << 8) (0x3f << 8)
6138#define DSPFW_PLANEC_OLD_SHIFT0 0
6139#define DSPFW_PLANEC_OLD_MASK(0x7f << 0) (0x7f << 0) /* pre-gen4 sprite C */
6140#define DSPFW_SPRITEA_SHIFT0 0
6141#define DSPFW_SPRITEA_MASK(0x7f << 0) (0x7f << 0) /* g4x */
6142#define DSPFW_SPRITEA_MASK_VLV(0xff << 0) (0xff << 0) /* vlv/chv */
6143#define DSPFW3((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x7003c) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x7003c) })
6144#define DSPFW_HPLL_SR_EN(1 << 31) (1 << 31)
6145#define PINEVIEW_SELF_REFRESH_EN(1 << 30) (1 << 30)
6146#define DSPFW_CURSOR_SR_SHIFT24 24
6147#define DSPFW_CURSOR_SR_MASK(0x3f << 24) (0x3f << 24)
6148#define DSPFW_HPLL_CURSOR_SHIFT16 16
6149#define DSPFW_HPLL_CURSOR_MASK(0x3f << 16) (0x3f << 16)
6150#define DSPFW_HPLL_SR_SHIFT0 0
6151#define DSPFW_HPLL_SR_MASK(0x1ff << 0) (0x1ff << 0)
6152
6153/* vlv/chv */
6154#define DSPFW4((const i915_reg_t){ .reg = (0x180000 + 0x70070) }) _MMIO(VLV_DISPLAY_BASE + 0x70070)((const i915_reg_t){ .reg = (0x180000 + 0x70070) })
6155#define DSPFW_SPRITEB_WM1_SHIFT16 16
6156#define DSPFW_SPRITEB_WM1_MASK(0xff << 16) (0xff << 16)
6157#define DSPFW_CURSORA_WM1_SHIFT8 8
6158#define DSPFW_CURSORA_WM1_MASK(0x3f << 8) (0x3f << 8)
6159#define DSPFW_SPRITEA_WM1_SHIFT0 0
6160#define DSPFW_SPRITEA_WM1_MASK(0xff << 0) (0xff << 0)
6161#define DSPFW5((const i915_reg_t){ .reg = (0x180000 + 0x70074) }) _MMIO(VLV_DISPLAY_BASE + 0x70074)((const i915_reg_t){ .reg = (0x180000 + 0x70074) })
6162#define DSPFW_PLANEB_WM1_SHIFT24 24
6163#define DSPFW_PLANEB_WM1_MASK(0xff << 24) (0xff << 24)
6164#define DSPFW_PLANEA_WM1_SHIFT16 16
6165#define DSPFW_PLANEA_WM1_MASK(0xff << 16) (0xff << 16)
6166#define DSPFW_CURSORB_WM1_SHIFT8 8
6167#define DSPFW_CURSORB_WM1_MASK(0x3f << 8) (0x3f << 8)
6168#define DSPFW_CURSOR_SR_WM1_SHIFT0 0
6169#define DSPFW_CURSOR_SR_WM1_MASK(0x3f << 0) (0x3f << 0)
6170#define DSPFW6((const i915_reg_t){ .reg = (0x180000 + 0x70078) }) _MMIO(VLV_DISPLAY_BASE + 0x70078)((const i915_reg_t){ .reg = (0x180000 + 0x70078) })
6171#define DSPFW_SR_WM1_SHIFT0 0
6172#define DSPFW_SR_WM1_MASK(0x1ff << 0) (0x1ff << 0)
6173#define DSPFW7((const i915_reg_t){ .reg = (0x180000 + 0x7007c) }) _MMIO(VLV_DISPLAY_BASE + 0x7007c)((const i915_reg_t){ .reg = (0x180000 + 0x7007c) })
6174#define DSPFW7_CHV((const i915_reg_t){ .reg = (0x180000 + 0x700b4) }) _MMIO(VLV_DISPLAY_BASE + 0x700b4)((const i915_reg_t){ .reg = (0x180000 + 0x700b4) }) /* wtf #1? */
6175#define DSPFW_SPRITED_WM1_SHIFT24 24
6176#define DSPFW_SPRITED_WM1_MASK(0xff << 24) (0xff << 24)
6177#define DSPFW_SPRITED_SHIFT16 16
6178#define DSPFW_SPRITED_MASK_VLV(0xff << 16) (0xff << 16)
6179#define DSPFW_SPRITEC_WM1_SHIFT8 8
6180#define DSPFW_SPRITEC_WM1_MASK(0xff << 8) (0xff << 8)
6181#define DSPFW_SPRITEC_SHIFT0 0
6182#define DSPFW_SPRITEC_MASK_VLV(0xff << 0) (0xff << 0)
6183#define DSPFW8_CHV((const i915_reg_t){ .reg = (0x180000 + 0x700b8) }) _MMIO(VLV_DISPLAY_BASE + 0x700b8)((const i915_reg_t){ .reg = (0x180000 + 0x700b8) })
6184#define DSPFW_SPRITEF_WM1_SHIFT24 24
6185#define DSPFW_SPRITEF_WM1_MASK(0xff << 24) (0xff << 24)
6186#define DSPFW_SPRITEF_SHIFT16 16
6187#define DSPFW_SPRITEF_MASK_VLV(0xff << 16) (0xff << 16)
6188#define DSPFW_SPRITEE_WM1_SHIFT8 8
6189#define DSPFW_SPRITEE_WM1_MASK(0xff << 8) (0xff << 8)
6190#define DSPFW_SPRITEE_SHIFT0 0
6191#define DSPFW_SPRITEE_MASK_VLV(0xff << 0) (0xff << 0)
6192#define DSPFW9_CHV((const i915_reg_t){ .reg = (0x180000 + 0x7007c) }) _MMIO(VLV_DISPLAY_BASE + 0x7007c)((const i915_reg_t){ .reg = (0x180000 + 0x7007c) }) /* wtf #2? */
6193#define DSPFW_PLANEC_WM1_SHIFT24 24
6194#define DSPFW_PLANEC_WM1_MASK(0xff << 24) (0xff << 24)
6195#define DSPFW_PLANEC_SHIFT16 16
6196#define DSPFW_PLANEC_MASK_VLV(0xff << 16) (0xff << 16)
6197#define DSPFW_CURSORC_WM1_SHIFT8 8
6198#define DSPFW_CURSORC_WM1_MASK(0x3f << 16) (0x3f << 16)
6199#define DSPFW_CURSORC_SHIFT0 0
6200#define DSPFW_CURSORC_MASK(0x3f << 0) (0x3f << 0)
6201
6202/* vlv/chv high order bits */
6203#define DSPHOWM((const i915_reg_t){ .reg = (0x180000 + 0x70064) }) _MMIO(VLV_DISPLAY_BASE + 0x70064)((const i915_reg_t){ .reg = (0x180000 + 0x70064) })
6204#define DSPFW_SR_HI_SHIFT24 24
6205#define DSPFW_SR_HI_MASK(3 << 24) (3 << 24) /* 2 bits for chv, 1 for vlv */
6206#define DSPFW_SPRITEF_HI_SHIFT23 23
6207#define DSPFW_SPRITEF_HI_MASK(1 << 23) (1 << 23)
6208#define DSPFW_SPRITEE_HI_SHIFT22 22
6209#define DSPFW_SPRITEE_HI_MASK(1 << 22) (1 << 22)
6210#define DSPFW_PLANEC_HI_SHIFT21 21
6211#define DSPFW_PLANEC_HI_MASK(1 << 21) (1 << 21)
6212#define DSPFW_SPRITED_HI_SHIFT20 20
6213#define DSPFW_SPRITED_HI_MASK(1 << 20) (1 << 20)
6214#define DSPFW_SPRITEC_HI_SHIFT16 16
6215#define DSPFW_SPRITEC_HI_MASK(1 << 16) (1 << 16)
6216#define DSPFW_PLANEB_HI_SHIFT12 12
6217#define DSPFW_PLANEB_HI_MASK(1 << 12) (1 << 12)
6218#define DSPFW_SPRITEB_HI_SHIFT8 8
6219#define DSPFW_SPRITEB_HI_MASK(1 << 8) (1 << 8)
6220#define DSPFW_SPRITEA_HI_SHIFT4 4
6221#define DSPFW_SPRITEA_HI_MASK(1 << 4) (1 << 4)
6222#define DSPFW_PLANEA_HI_SHIFT0 0
6223#define DSPFW_PLANEA_HI_MASK(1 << 0) (1 << 0)
6224#define DSPHOWM1((const i915_reg_t){ .reg = (0x180000 + 0x70068) }) _MMIO(VLV_DISPLAY_BASE + 0x70068)((const i915_reg_t){ .reg = (0x180000 + 0x70068) })
6225#define DSPFW_SR_WM1_HI_SHIFT24 24
6226#define DSPFW_SR_WM1_HI_MASK(3 << 24) (3 << 24) /* 2 bits for chv, 1 for vlv */
6227#define DSPFW_SPRITEF_WM1_HI_SHIFT23 23
6228#define DSPFW_SPRITEF_WM1_HI_MASK(1 << 23) (1 << 23)
6229#define DSPFW_SPRITEE_WM1_HI_SHIFT22 22
6230#define DSPFW_SPRITEE_WM1_HI_MASK(1 << 22) (1 << 22)
6231#define DSPFW_PLANEC_WM1_HI_SHIFT21 21
6232#define DSPFW_PLANEC_WM1_HI_MASK(1 << 21) (1 << 21)
6233#define DSPFW_SPRITED_WM1_HI_SHIFT20 20
6234#define DSPFW_SPRITED_WM1_HI_MASK(1 << 20) (1 << 20)
6235#define DSPFW_SPRITEC_WM1_HI_SHIFT16 16
6236#define DSPFW_SPRITEC_WM1_HI_MASK(1 << 16) (1 << 16)
6237#define DSPFW_PLANEB_WM1_HI_SHIFT12 12
6238#define DSPFW_PLANEB_WM1_HI_MASK(1 << 12) (1 << 12)
6239#define DSPFW_SPRITEB_WM1_HI_SHIFT8 8
6240#define DSPFW_SPRITEB_WM1_HI_MASK(1 << 8) (1 << 8)
6241#define DSPFW_SPRITEA_WM1_HI_SHIFT4 4
6242#define DSPFW_SPRITEA_WM1_HI_MASK(1 << 4) (1 << 4)
6243#define DSPFW_PLANEA_WM1_HI_SHIFT0 0
6244#define DSPFW_PLANEA_WM1_HI_MASK(1 << 0) (1 << 0)
6245
6246/* drain latency register values*/
6247#define VLV_DDL(pipe)((const i915_reg_t){ .reg = (0x180000 + 0x70050 + 4 * (pipe))
}) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))((const i915_reg_t){ .reg = (0x180000 + 0x70050 + 4 * (pipe))
})
6248#define DDL_CURSOR_SHIFT24 24
6249#define DDL_SPRITE_SHIFT(sprite)(8 + 8 * (sprite)) (8 + 8 * (sprite))
6250#define DDL_PLANE_SHIFT0 0
6251#define DDL_PRECISION_HIGH(1 << 7) (1 << 7)
6252#define DDL_PRECISION_LOW(0 << 7) (0 << 7)
6253#define DRAIN_LATENCY_MASK0x7f 0x7f
6254
6255#define CBR1_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70400) }) _MMIO(VLV_DISPLAY_BASE + 0x70400)((const i915_reg_t){ .reg = (0x180000 + 0x70400) })
6256#define CBR_PND_DEADLINE_DISABLE(1 << 31) (1 << 31)
6257#define CBR_PWM_CLOCK_MUX_SELECT(1 << 30) (1 << 30)
6258
6259#define CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }) _MMIO(VLV_DISPLAY_BASE + 0x70450)((const i915_reg_t){ .reg = (0x180000 + 0x70450) })
6260#define CBR_DPLLBMD_PIPE(pipe)(1 << (7 + (pipe) * 11)) (1 << (7 + (pipe) * 11)) /* pipes B and C */
6261
6262/* FIFO watermark sizes etc */
6263#define G4X_FIFO_LINE_SIZE64 64
6264#define I915_FIFO_LINE_SIZE64 64
6265#define I830_FIFO_LINE_SIZE32 32
6266
6267#define VALLEYVIEW_FIFO_SIZE255 255
6268#define G4X_FIFO_SIZE127 127
6269#define I965_FIFO_SIZE512 512
6270#define I945_FIFO_SIZE127 127
6271#define I915_FIFO_SIZE95 95
6272#define I855GM_FIFO_SIZE127 127 /* In cachelines */
6273#define I830_FIFO_SIZE95 95
6274
6275#define VALLEYVIEW_MAX_WM0xff 0xff
6276#define G4X_MAX_WM0x3f 0x3f
6277#define I915_MAX_WM0x3f 0x3f
6278
6279#define PINEVIEW_DISPLAY_FIFO512 512 /* in 64byte unit */
6280#define PINEVIEW_FIFO_LINE_SIZE64 64
6281#define PINEVIEW_MAX_WM0x1ff 0x1ff
6282#define PINEVIEW_DFT_WM0x3f 0x3f
6283#define PINEVIEW_DFT_HPLLOFF_WM0 0
6284#define PINEVIEW_GUARD_WM10 10
6285#define PINEVIEW_CURSOR_FIFO64 64
6286#define PINEVIEW_CURSOR_MAX_WM0x3f 0x3f
6287#define PINEVIEW_CURSOR_DFT_WM0 0
6288#define PINEVIEW_CURSOR_GUARD_WM5 5
6289
6290#define VALLEYVIEW_CURSOR_MAX_WM64 64
6291#define I965_CURSOR_FIFO64 64
6292#define I965_CURSOR_MAX_WM32 32
6293#define I965_CURSOR_DFT_WM8 8
6294
6295/* Watermark register definitions for SKL */
6296#define _CUR_WM_A_00x70140 0x70140
6297#define _CUR_WM_B_00x71140 0x71140
6298#define _PLANE_WM_1_A_00x70240 0x70240
6299#define _PLANE_WM_1_B_00x71240 0x71240
6300#define _PLANE_WM_2_A_00x70340 0x70340
6301#define _PLANE_WM_2_B_00x71340 0x71340
6302#define _PLANE_WM_TRANS_1_A_00x70268 0x70268
6303#define _PLANE_WM_TRANS_1_B_00x71268 0x71268
6304#define _PLANE_WM_TRANS_2_A_00x70368 0x70368
6305#define _PLANE_WM_TRANS_2_B_00x71368 0x71368
6306#define _CUR_WM_TRANS_A_00x70168 0x70168
6307#define _CUR_WM_TRANS_B_00x71168 0x71168
6308#define PLANE_WM_EN(1 << 31) (1 << 31)
6309#define PLANE_WM_IGNORE_LINES(1 << 30) (1 << 30)
6310#define PLANE_WM_LINES_SHIFT14 14
6311#define PLANE_WM_LINES_MASK0x1f 0x1f
6312#define PLANE_WM_BLOCKS_MASK0x7ff 0x7ff /* skl+: 10 bits, icl+ 11 bits */
6313
6314#define _CUR_WM_0(pipe)((0x70140) + (pipe) * ((0x71140) - (0x70140))) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)((0x70140) + (pipe) * ((0x71140) - (0x70140)))
6315#define CUR_WM(pipe, level)((const i915_reg_t){ .reg = (((0x70140) + (pipe) * ((0x71140)
- (0x70140))) + ((4) * (level))) }) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))((const i915_reg_t){ .reg = (((0x70140) + (pipe) * ((0x71140)
- (0x70140))) + ((4) * (level))) })
6316#define CUR_WM_TRANS(pipe)((const i915_reg_t){ .reg = (((0x70168) + (pipe) * ((0x71168)
- (0x70168)))) }) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)((const i915_reg_t){ .reg = (((0x70168) + (pipe) * ((0x71168)
- (0x70168)))) })
6317
6318#define _PLANE_WM_1(pipe)((0x70240) + (pipe) * ((0x71240) - (0x70240))) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)((0x70240) + (pipe) * ((0x71240) - (0x70240)))
6319#define _PLANE_WM_2(pipe)((0x70340) + (pipe) * ((0x71340) - (0x70340))) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)((0x70340) + (pipe) * ((0x71340) - (0x70340)))
6320#define _PLANE_WM_BASE(pipe, plane)((((0x70240) + (pipe) * ((0x71240) - (0x70240)))) + (plane) *
((((0x70340) + (pipe) * ((0x71340) - (0x70340)))) - (((0x70240
) + (pipe) * ((0x71240) - (0x70240)))))) \
6321 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))((((0x70240) + (pipe) * ((0x71240) - (0x70240)))) + (plane) *
((((0x70340) + (pipe) * ((0x71340) - (0x70340)))) - (((0x70240
) + (pipe) * ((0x71240) - (0x70240))))))
6322#define PLANE_WM(pipe, plane, level)((const i915_reg_t){ .reg = (((((0x70240) + (pipe) * ((0x71240
) - (0x70240)))) + (plane) * ((((0x70340) + (pipe) * ((0x71340
) - (0x70340)))) - (((0x70240) + (pipe) * ((0x71240) - (0x70240
)))))) + ((4) * (level))) }) \
6323 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))((const i915_reg_t){ .reg = (((((0x70240) + (pipe) * ((0x71240
) - (0x70240)))) + (plane) * ((((0x70340) + (pipe) * ((0x71340
) - (0x70340)))) - (((0x70240) + (pipe) * ((0x71240) - (0x70240
)))))) + ((4) * (level))) })
6324#define _PLANE_WM_TRANS_1(pipe)((0x70268) + (pipe) * ((0x71268) - (0x70268))) \
6325 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)((0x70268) + (pipe) * ((0x71268) - (0x70268)))
6326#define _PLANE_WM_TRANS_2(pipe)((0x70368) + (pipe) * ((0x71368) - (0x70368))) \
6327 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)((0x70368) + (pipe) * ((0x71368) - (0x70368)))
6328#define PLANE_WM_TRANS(pipe, plane)((const i915_reg_t){ .reg = (((((0x70268) + (pipe) * ((0x71268
) - (0x70268)))) + (plane) * ((((0x70368) + (pipe) * ((0x71368
) - (0x70368)))) - (((0x70268) + (pipe) * ((0x71268) - (0x70268
))))))) }) \
6329 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))((const i915_reg_t){ .reg = (((((0x70268) + (pipe) * ((0x71268
) - (0x70268)))) + (plane) * ((((0x70368) + (pipe) * ((0x71368
) - (0x70368)))) - (((0x70268) + (pipe) * ((0x71268) - (0x70268
))))))) })
6330
6331/* define the Watermark register on Ironlake */
6332#define WM0_PIPEA_ILK((const i915_reg_t){ .reg = (0x45100) }) _MMIO(0x45100)((const i915_reg_t){ .reg = (0x45100) })
6333#define WM0_PIPE_PLANE_MASK(0xffff << 16) (0xffff << 16)
6334#define WM0_PIPE_PLANE_SHIFT16 16
6335#define WM0_PIPE_SPRITE_MASK(0xff << 8) (0xff << 8)
6336#define WM0_PIPE_SPRITE_SHIFT8 8
6337#define WM0_PIPE_CURSOR_MASK(0xff) (0xff)
6338
6339#define WM0_PIPEB_ILK((const i915_reg_t){ .reg = (0x45104) }) _MMIO(0x45104)((const i915_reg_t){ .reg = (0x45104) })
6340#define WM0_PIPEC_IVB((const i915_reg_t){ .reg = (0x45200) }) _MMIO(0x45200)((const i915_reg_t){ .reg = (0x45200) })
6341#define WM1_LP_ILK((const i915_reg_t){ .reg = (0x45108) }) _MMIO(0x45108)((const i915_reg_t){ .reg = (0x45108) })
6342#define WM1_LP_SR_EN(1 << 31) (1 << 31)
6343#define WM1_LP_LATENCY_SHIFT24 24
6344#define WM1_LP_LATENCY_MASK(0x7f << 24) (0x7f << 24)
6345#define WM1_LP_FBC_MASK(0xf << 20) (0xf << 20)
6346#define WM1_LP_FBC_SHIFT20 20
6347#define WM1_LP_FBC_SHIFT_BDW19 19
6348#define WM1_LP_SR_MASK(0x7ff << 8) (0x7ff << 8)
6349#define WM1_LP_SR_SHIFT8 8
6350#define WM1_LP_CURSOR_MASK(0xff) (0xff)
6351#define WM2_LP_ILK((const i915_reg_t){ .reg = (0x4510c) }) _MMIO(0x4510c)((const i915_reg_t){ .reg = (0x4510c) })
6352#define WM2_LP_EN(1 << 31) (1 << 31)
6353#define WM3_LP_ILK((const i915_reg_t){ .reg = (0x45110) }) _MMIO(0x45110)((const i915_reg_t){ .reg = (0x45110) })
6354#define WM3_LP_EN(1 << 31) (1 << 31)
6355#define WM1S_LP_ILK((const i915_reg_t){ .reg = (0x45120) }) _MMIO(0x45120)((const i915_reg_t){ .reg = (0x45120) })
6356#define WM2S_LP_IVB((const i915_reg_t){ .reg = (0x45124) }) _MMIO(0x45124)((const i915_reg_t){ .reg = (0x45124) })
6357#define WM3S_LP_IVB((const i915_reg_t){ .reg = (0x45128) }) _MMIO(0x45128)((const i915_reg_t){ .reg = (0x45128) })
6358#define WM1S_LP_EN(1 << 31) (1 << 31)
6359
6360#define HSW_WM_LP_VAL(lat, fbc, pri, cur)((1 << 31) | ((lat) << 24) | ((fbc) << 20) |
((pri) << 8) | (cur)) \
6361 (WM3_LP_EN(1 << 31) | ((lat) << WM1_LP_LATENCY_SHIFT24) | \
6362 ((fbc) << WM1_LP_FBC_SHIFT20) | ((pri) << WM1_LP_SR_SHIFT8) | (cur))
6363
6364/* Memory latency timer register */
6365#define MLTR_ILK((const i915_reg_t){ .reg = (0x11222) }) _MMIO(0x11222)((const i915_reg_t){ .reg = (0x11222) })
6366#define MLTR_WM1_SHIFT0 0
6367#define MLTR_WM2_SHIFT8 8
6368/* the unit of memory self-refresh latency time is 0.5us */
6369#define ILK_SRLT_MASK0x3f 0x3f
6370
6371
6372/* the address where we get all kinds of latency value */
6373#define SSKPD((const i915_reg_t){ .reg = (0x5d10) }) _MMIO(0x5d10)((const i915_reg_t){ .reg = (0x5d10) })
6374#define SSKPD_WM_MASK0x3f 0x3f
6375#define SSKPD_WM0_SHIFT0 0
6376#define SSKPD_WM1_SHIFT8 8
6377#define SSKPD_WM2_SHIFT16 16
6378#define SSKPD_WM3_SHIFT24 24
6379
6380/*
6381 * The two pipe frame counter registers are not synchronized, so
6382 * reading a stable value is somewhat tricky. The following code
6383 * should work:
6384 *
6385 * do {
6386 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6387 * PIPE_FRAME_HIGH_SHIFT;
6388 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6389 * PIPE_FRAME_LOW_SHIFT);
6390 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6391 * PIPE_FRAME_HIGH_SHIFT);
6392 * } while (high1 != high2);
6393 * frame = (high1 << 8) | low1;
6394 */
6395#define _PIPEAFRAMEHIGH0x70040 0x70040
6396#define PIPE_FRAME_HIGH_MASK0x0000ffff 0x0000ffff
6397#define PIPE_FRAME_HIGH_SHIFT0 0
6398#define _PIPEAFRAMEPIXEL0x70044 0x70044
6399#define PIPE_FRAME_LOW_MASK0xff000000 0xff000000
6400#define PIPE_FRAME_LOW_SHIFT24 24
6401#define PIPE_PIXEL_MASK0x00ffffff 0x00ffffff
6402#define PIPE_PIXEL_SHIFT0 0
6403/* GM45+ just has to be different */
6404#define _PIPEA_FRMCOUNT_G4X0x70040 0x70040
6405#define _PIPEA_FLIPCOUNT_G4X0x70044 0x70044
6406#define PIPE_FRMCOUNT_G4X(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70040) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70040) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6407#define PIPE_FLIPCOUNT_G4X(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70044) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70044) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6408
6409/* Cursor A & B regs */
6410#define _CURACNTR0x70080 0x70080
6411/* Old style CUR*CNTR flags (desktop 8xx) */
6412#define CURSOR_ENABLE0x80000000 0x80000000
6413#define CURSOR_GAMMA_ENABLE0x40000000 0x40000000
6414#define CURSOR_STRIDE_SHIFT28 28
6415#define CURSOR_STRIDE(x)((ffs(x) - 9) << 28) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT28) /* 256,512,1k,2k */
6416#define CURSOR_FORMAT_SHIFT24 24
6417#define CURSOR_FORMAT_MASK(0x07 << 24) (0x07 << CURSOR_FORMAT_SHIFT24)
6418#define CURSOR_FORMAT_2C(0x00 << 24) (0x00 << CURSOR_FORMAT_SHIFT24)
6419#define CURSOR_FORMAT_3C(0x01 << 24) (0x01 << CURSOR_FORMAT_SHIFT24)
6420#define CURSOR_FORMAT_4C(0x02 << 24) (0x02 << CURSOR_FORMAT_SHIFT24)
6421#define CURSOR_FORMAT_ARGB(0x04 << 24) (0x04 << CURSOR_FORMAT_SHIFT24)
6422#define CURSOR_FORMAT_XRGB(0x05 << 24) (0x05 << CURSOR_FORMAT_SHIFT24)
6423/* New style CUR*CNTR flags */
6424#define MCURSOR_MODE0x27 0x27
6425#define MCURSOR_MODE_DISABLE0x00 0x00
6426#define MCURSOR_MODE_128_32B_AX0x02 0x02
6427#define MCURSOR_MODE_256_32B_AX0x03 0x03
6428#define MCURSOR_MODE_64_32B_AX0x07 0x07
6429#define MCURSOR_MODE_128_ARGB_AX((1 << 5) | 0x02) ((1 << 5) | MCURSOR_MODE_128_32B_AX0x02)
6430#define MCURSOR_MODE_256_ARGB_AX((1 << 5) | 0x03) ((1 << 5) | MCURSOR_MODE_256_32B_AX0x03)
6431#define MCURSOR_MODE_64_ARGB_AX((1 << 5) | 0x07) ((1 << 5) | MCURSOR_MODE_64_32B_AX0x07)
6432#define MCURSOR_PIPE_SELECT_MASK(0x3 << 28) (0x3 << 28)
6433#define MCURSOR_PIPE_SELECT_SHIFT28 28
6434#define MCURSOR_PIPE_SELECT(pipe)((pipe) << 28) ((pipe) << 28)
6435#define MCURSOR_GAMMA_ENABLE(1 << 26) (1 << 26)
6436#define MCURSOR_PIPE_CSC_ENABLE(1 << 24) (1 << 24) /* ilk+ */
6437#define MCURSOR_ROTATE_180(1 << 15) (1 << 15)
6438#define MCURSOR_TRICKLE_FEED_DISABLE(1 << 14) (1 << 14)
6439#define _CURABASE0x70084 0x70084
6440#define _CURAPOS0x70088 0x70088
6441#define CURSOR_POS_MASK0x007FF 0x007FF
6442#define CURSOR_POS_SIGN0x8000 0x8000
6443#define CURSOR_X_SHIFT0 0
6444#define CURSOR_Y_SHIFT16 16
6445#define CURSIZE((const i915_reg_t){ .reg = (0x700a0) }) _MMIO(0x700a0)((const i915_reg_t){ .reg = (0x700a0) }) /* 845/865 */
6446#define _CUR_FBC_CTL_A0x700a0 0x700a0 /* ivb+ */
6447#define CUR_FBC_CTL_EN(1 << 31) (1 << 31)
6448#define _CURASURFLIVE0x700ac 0x700ac /* g4x+ */
6449#define _CURBCNTR0x700c0 0x700c0
6450#define _CURBBASE0x700c4 0x700c4
6451#define _CURBPOS0x700c8 0x700c8
6452
6453#define _CURBCNTR_IVB0x71080 0x71080
6454#define _CURBBASE_IVB0x71084 0x71084
6455#define _CURBPOS_IVB0x71088 0x71088
6456
6457#define CURCNTR(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _CURSOR2(pipe, _CURACNTR)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6458#define CURBASE(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _CURSOR2(pipe, _CURABASE)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6459#define CURPOS(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _CURSOR2(pipe, _CURAPOS)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6460#define CUR_FBC_CTL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x700a0) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _CURSOR2(pipe, _CUR_FBC_CTL_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x700a0) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6461#define CURSURFLIVE(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x700ac) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _CURSOR2(pipe, _CURASURFLIVE)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets
[PIPE_A] + (0x700ac) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6462
6463#define CURSOR_A_OFFSET0x70080 0x70080
6464#define CURSOR_B_OFFSET0x700c0 0x700c0
6465#define CHV_CURSOR_C_OFFSET0x700e0 0x700e0
6466#define IVB_CURSOR_B_OFFSET0x71080 0x71080
6467#define IVB_CURSOR_C_OFFSET0x72080 0x72080
6468#define TGL_CURSOR_D_OFFSET0x73080 0x73080
6469
6470/* Display A control */
6471#define _DSPACNTR0x70180 0x70180
6472#define DISPLAY_PLANE_ENABLE(1 << 31) (1 << 31)
6473#define DISPLAY_PLANE_DISABLE0 0
6474#define DISPPLANE_GAMMA_ENABLE(1 << 30) (1 << 30)
6475#define DISPPLANE_GAMMA_DISABLE0 0
6476#define DISPPLANE_PIXFORMAT_MASK(0xf << 26) (0xf << 26)
6477#define DISPPLANE_YUV422(0x0 << 26) (0x0 << 26)
6478#define DISPPLANE_8BPP(0x2 << 26) (0x2 << 26)
6479#define DISPPLANE_BGRA555(0x3 << 26) (0x3 << 26)
6480#define DISPPLANE_BGRX555(0x4 << 26) (0x4 << 26)
6481#define DISPPLANE_BGRX565(0x5 << 26) (0x5 << 26)
6482#define DISPPLANE_BGRX888(0x6 << 26) (0x6 << 26)
6483#define DISPPLANE_BGRA888(0x7 << 26) (0x7 << 26)
6484#define DISPPLANE_RGBX101010(0x8 << 26) (0x8 << 26)
6485#define DISPPLANE_RGBA101010(0x9 << 26) (0x9 << 26)
6486#define DISPPLANE_BGRX101010(0xa << 26) (0xa << 26)
6487#define DISPPLANE_BGRA101010(0xb << 26) (0xb << 26)
6488#define DISPPLANE_RGBX161616(0xc << 26) (0xc << 26)
6489#define DISPPLANE_RGBX888(0xe << 26) (0xe << 26)
6490#define DISPPLANE_RGBA888(0xf << 26) (0xf << 26)
6491#define DISPPLANE_STEREO_ENABLE(1 << 25) (1 << 25)
6492#define DISPPLANE_STEREO_DISABLE0 0
6493#define DISPPLANE_PIPE_CSC_ENABLE(1 << 24) (1 << 24) /* ilk+ */
6494#define DISPPLANE_SEL_PIPE_SHIFT24 24
6495#define DISPPLANE_SEL_PIPE_MASK(3 << 24) (3 << DISPPLANE_SEL_PIPE_SHIFT24)
6496#define DISPPLANE_SEL_PIPE(pipe)((pipe) << 24) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT24)
6497#define DISPPLANE_SRC_KEY_ENABLE(1 << 22) (1 << 22)
6498#define DISPPLANE_SRC_KEY_DISABLE0 0
6499#define DISPPLANE_LINE_DOUBLE(1 << 20) (1 << 20)
6500#define DISPPLANE_NO_LINE_DOUBLE0 0
6501#define DISPPLANE_STEREO_POLARITY_FIRST0 0
6502#define DISPPLANE_STEREO_POLARITY_SECOND(1 << 18) (1 << 18)
6503#define DISPPLANE_ALPHA_PREMULTIPLY(1 << 16) (1 << 16) /* CHV pipe B */
6504#define DISPPLANE_ROTATE_180(1 << 15) (1 << 15)
6505#define DISPPLANE_TRICKLE_FEED_DISABLE(1 << 14) (1 << 14) /* Ironlake */
6506#define DISPPLANE_TILED(1 << 10) (1 << 10)
6507#define DISPPLANE_MIRROR(1 << 8) (1 << 8) /* CHV pipe B */
6508#define _DSPAADDR0x70184 0x70184
6509#define _DSPASTRIDE0x70188 0x70188
6510#define _DSPAPOS0x7018C 0x7018C /* reserved */
6511#define _DSPASIZE0x70190 0x70190
6512#define _DSPASURF0x7019C 0x7019C /* 965+ only */
6513#define _DSPATILEOFF0x701A4 0x701A4 /* 965+ only */
6514#define _DSPAOFFSET0x701A4 0x701A4 /* HSW */
6515#define _DSPASURFLIVE0x701AC 0x701AC
6516#define _DSPAGAMC0x701E0 0x701E0
6517
6518#define DSPCNTR(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPACNTR)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6519#define DSPADDR(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPAADDR)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6520#define DSPSTRIDE(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPASTRIDE)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6521#define DSPPOS(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7018C) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPAPOS)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7018C) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6522#define DSPSIZE(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70190) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPASIZE)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70190) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6523#define DSPSURF(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPASURF)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6524#define DSPTILEOFF(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPATILEOFF)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6525#define DSPLINOFF(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) DSPADDR(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6526#define DSPOFFSET(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPAOFFSET)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6527#define DSPSURFLIVE(plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701AC) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(plane, _DSPASURFLIVE)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701AC) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
6528#define DSPGAMC(plane, i)((const i915_reg_t){ .reg = (_PIPE2(plane, 0x701E0) + (5 - (i
)) * 4) }) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4)((const i915_reg_t){ .reg = (_PIPE2(plane, 0x701E0) + (5 - (i
)) * 4) }) /* plane C only, 6 x u0.8 */
6529
6530/* CHV pipe B blender and primary plane */
6531#define _CHV_BLEND_A0x60a00 0x60a00
6532#define CHV_BLEND_LEGACY(0 << 30) (0 << 30)
6533#define CHV_BLEND_ANDROID(1 << 30) (1 << 30)
6534#define CHV_BLEND_MPO(2 << 30) (2 << 30)
6535#define CHV_BLEND_MASK(3 << 30) (3 << 30)
6536#define _CHV_CANVAS_A0x60a04 0x60a04
6537#define _PRIMPOS_A0x60a08 0x60a08
6538#define _PRIMSIZE_A0x60a0c 0x60a0c
6539#define _PRIMCNSTALPHA_A0x60a10 0x60a10
6540#define PRIM_CONST_ALPHA_ENABLE(1 << 31) (1 << 31)
6541
6542#define CHV_BLEND(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a00) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _CHV_BLEND_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a00) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
6543#define CHV_CANVAS(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a04) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a04) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
6544#define PRIMPOS(plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a08) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(plane, _PRIMPOS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a08) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
6545#define PRIMSIZE(plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a0c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(plane, _PRIMSIZE_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a0c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
6546#define PRIMCNSTALPHA(plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a10) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(plane)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60a10) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
6547
6548/* Display/Sprite base address macros */
6549#define DISP_BASEADDR_MASK(0xfffff000) (0xfffff000)
6550#define I915_LO_DISPBASE(val)((val) & ~(0xfffff000)) ((val) & ~DISP_BASEADDR_MASK(0xfffff000))
6551#define I915_HI_DISPBASE(val)((val) & (0xfffff000)) ((val) & DISP_BASEADDR_MASK(0xfffff000))
6552
6553/*
6554 * VBIOS flags
6555 * gen2:
6556 * [00:06] alm,mgm
6557 * [10:16] all
6558 * [30:32] alm,mgm
6559 * gen3+:
6560 * [00:0f] all
6561 * [10:1f] all
6562 * [30:32] all
6563 */
6564#define SWF0(i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70410 + (i) * 4) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x70410 + (i) * 4) })
6565#define SWF1(i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x71410 + (i) * 4) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x71410 + (i) * 4) })
6566#define SWF3(i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x72414 + (i) * 4) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x72414 + (i) * 4) })
6567#define SWF_ILK(i)((const i915_reg_t){ .reg = (0x4F000 + (i) * 4) }) _MMIO(0x4F000 + (i) * 4)((const i915_reg_t){ .reg = (0x4F000 + (i) * 4) })
6568
6569/* Pipe B */
6570#define _PIPEBDSL(((&(dev_priv)->__info)->display_mmio_offset) + 0x71000
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71000)
6571#define _PIPEBCONF(((&(dev_priv)->__info)->display_mmio_offset) + 0x71008
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71008)
6572#define _PIPEBSTAT(((&(dev_priv)->__info)->display_mmio_offset) + 0x71024
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71024)
6573#define _PIPEBFRAMEHIGH0x71040 0x71040
6574#define _PIPEBFRAMEPIXEL0x71044 0x71044
6575#define _PIPEB_FRMCOUNT_G4X(((&(dev_priv)->__info)->display_mmio_offset) + 0x71040
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71040)
6576#define _PIPEB_FLIPCOUNT_G4X(((&(dev_priv)->__info)->display_mmio_offset) + 0x71044
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71044)
6577
6578
6579/* Display B control */
6580#define _DSPBCNTR(((&(dev_priv)->__info)->display_mmio_offset) + 0x71180
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71180)
6581#define DISPPLANE_ALPHA_TRANS_ENABLE(1 << 15) (1 << 15)
6582#define DISPPLANE_ALPHA_TRANS_DISABLE0 0
6583#define DISPPLANE_SPRITE_ABOVE_DISPLAY0 0
6584#define DISPPLANE_SPRITE_ABOVE_OVERLAY(1) (1)
6585#define _DSPBADDR(((&(dev_priv)->__info)->display_mmio_offset) + 0x71184
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71184)
6586#define _DSPBSTRIDE(((&(dev_priv)->__info)->display_mmio_offset) + 0x71188
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71188)
6587#define _DSPBPOS(((&(dev_priv)->__info)->display_mmio_offset) + 0x7118C
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x7118C)
6588#define _DSPBSIZE(((&(dev_priv)->__info)->display_mmio_offset) + 0x71190
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x71190)
6589#define _DSPBSURF(((&(dev_priv)->__info)->display_mmio_offset) + 0x7119C
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x7119C)
6590#define _DSPBTILEOFF(((&(dev_priv)->__info)->display_mmio_offset) + 0x711A4
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x711A4)
6591#define _DSPBOFFSET(((&(dev_priv)->__info)->display_mmio_offset) + 0x711A4
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x711A4)
6592#define _DSPBSURFLIVE(((&(dev_priv)->__info)->display_mmio_offset) + 0x711AC
) (DISPLAY_MMIO_BASE(dev_priv)((&(dev_priv)->__info)->display_mmio_offset) + 0x711AC)
6593
6594/* ICL DSI 0 and 1 */
6595#define _PIPEDSI0CONF0x7b008 0x7b008
6596#define _PIPEDSI1CONF0x7b808 0x7b808
6597
6598/* Sprite A control */
6599#define _DVSACNTR0x72180 0x72180
6600#define DVS_ENABLE(1 << 31) (1 << 31)
6601#define DVS_GAMMA_ENABLE(1 << 30) (1 << 30)
6602#define DVS_YUV_RANGE_CORRECTION_DISABLE(1 << 27) (1 << 27)
6603#define DVS_PIXFORMAT_MASK(3 << 25) (3 << 25)
6604#define DVS_FORMAT_YUV422(0 << 25) (0 << 25)
6605#define DVS_FORMAT_RGBX101010(1 << 25) (1 << 25)
6606#define DVS_FORMAT_RGBX888(2 << 25) (2 << 25)
6607#define DVS_FORMAT_RGBX161616(3 << 25) (3 << 25)
6608#define DVS_PIPE_CSC_ENABLE(1 << 24) (1 << 24)
6609#define DVS_SOURCE_KEY(1 << 22) (1 << 22)
6610#define DVS_RGB_ORDER_XBGR(1 << 20) (1 << 20)
6611#define DVS_YUV_FORMAT_BT709(1 << 18) (1 << 18)
6612#define DVS_YUV_BYTE_ORDER_MASK(3 << 16) (3 << 16)
6613#define DVS_YUV_ORDER_YUYV(0 << 16) (0 << 16)
6614#define DVS_YUV_ORDER_UYVY(1 << 16) (1 << 16)
6615#define DVS_YUV_ORDER_YVYU(2 << 16) (2 << 16)
6616#define DVS_YUV_ORDER_VYUY(3 << 16) (3 << 16)
6617#define DVS_ROTATE_180(1 << 15) (1 << 15)
6618#define DVS_DEST_KEY(1 << 2) (1 << 2)
6619#define DVS_TRICKLE_FEED_DISABLE(1 << 14) (1 << 14)
6620#define DVS_TILED(1 << 10) (1 << 10)
6621#define _DVSALINOFF0x72184 0x72184
6622#define _DVSASTRIDE0x72188 0x72188
6623#define _DVSAPOS0x7218c 0x7218c
6624#define _DVSASIZE0x72190 0x72190
6625#define _DVSAKEYVAL0x72194 0x72194
6626#define _DVSAKEYMSK0x72198 0x72198
6627#define _DVSASURF0x7219c 0x7219c
6628#define _DVSAKEYMAXVAL0x721a0 0x721a0
6629#define _DVSATILEOFF0x721a4 0x721a4
6630#define _DVSASURFLIVE0x721ac 0x721ac
6631#define _DVSAGAMC_G4X0x721e0 0x721e0 /* g4x */
6632#define _DVSASCALE0x72204 0x72204
6633#define DVS_SCALE_ENABLE(1 << 31) (1 << 31)
6634#define DVS_FILTER_MASK(3 << 29) (3 << 29)
6635#define DVS_FILTER_MEDIUM(0 << 29) (0 << 29)
6636#define DVS_FILTER_ENHANCING(1 << 29) (1 << 29)
6637#define DVS_FILTER_SOFTENING(2 << 29) (2 << 29)
6638#define DVS_VERTICAL_OFFSET_HALF(1 << 28) (1 << 28) /* must be enabled below */
6639#define DVS_VERTICAL_OFFSET_ENABLE(1 << 27) (1 << 27)
6640#define _DVSAGAMC_ILK0x72300 0x72300 /* ilk/snb */
6641#define _DVSAGAMCMAX_ILK0x72340 0x72340 /* ilk/snb */
6642
6643#define _DVSBCNTR0x73180 0x73180
6644#define _DVSBLINOFF0x73184 0x73184
6645#define _DVSBSTRIDE0x73188 0x73188
6646#define _DVSBPOS0x7318c 0x7318c
6647#define _DVSBSIZE0x73190 0x73190
6648#define _DVSBKEYVAL0x73194 0x73194
6649#define _DVSBKEYMSK0x73198 0x73198
6650#define _DVSBSURF0x7319c 0x7319c
6651#define _DVSBKEYMAXVAL0x731a0 0x731a0
6652#define _DVSBTILEOFF0x731a4 0x731a4
6653#define _DVSBSURFLIVE0x731ac 0x731ac
6654#define _DVSBGAMC_G4X0x731e0 0x731e0 /* g4x */
6655#define _DVSBSCALE0x73204 0x73204
6656#define _DVSBGAMC_ILK0x73300 0x73300 /* ilk/snb */
6657#define _DVSBGAMCMAX_ILK0x73340 0x73340 /* ilk/snb */
6658
6659#define DVSCNTR(pipe)((const i915_reg_t){ .reg = (((0x72180) + (pipe) * ((0x73180)
- (0x72180)))) }) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)((const i915_reg_t){ .reg = (((0x72180) + (pipe) * ((0x73180)
- (0x72180)))) })
6660#define DVSLINOFF(pipe)((const i915_reg_t){ .reg = (((0x72184) + (pipe) * ((0x73184)
- (0x72184)))) }) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)((const i915_reg_t){ .reg = (((0x72184) + (pipe) * ((0x73184)
- (0x72184)))) })
6661#define DVSSTRIDE(pipe)((const i915_reg_t){ .reg = (((0x72188) + (pipe) * ((0x73188)
- (0x72188)))) }) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)((const i915_reg_t){ .reg = (((0x72188) + (pipe) * ((0x73188)
- (0x72188)))) })
6662#define DVSPOS(pipe)((const i915_reg_t){ .reg = (((0x7218c) + (pipe) * ((0x7318c)
- (0x7218c)))) }) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)((const i915_reg_t){ .reg = (((0x7218c) + (pipe) * ((0x7318c)
- (0x7218c)))) })
6663#define DVSSURF(pipe)((const i915_reg_t){ .reg = (((0x7219c) + (pipe) * ((0x7319c)
- (0x7219c)))) }) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)((const i915_reg_t){ .reg = (((0x7219c) + (pipe) * ((0x7319c)
- (0x7219c)))) })
6664#define DVSKEYMAX(pipe)((const i915_reg_t){ .reg = (((0x721a0) + (pipe) * ((0x731a0)
- (0x721a0)))) }) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)((const i915_reg_t){ .reg = (((0x721a0) + (pipe) * ((0x731a0)
- (0x721a0)))) })
6665#define DVSSIZE(pipe)((const i915_reg_t){ .reg = (((0x72190) + (pipe) * ((0x73190)
- (0x72190)))) }) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)((const i915_reg_t){ .reg = (((0x72190) + (pipe) * ((0x73190)
- (0x72190)))) })
6666#define DVSSCALE(pipe)((const i915_reg_t){ .reg = (((0x72204) + (pipe) * ((0x73204)
- (0x72204)))) }) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)((const i915_reg_t){ .reg = (((0x72204) + (pipe) * ((0x73204)
- (0x72204)))) })
6667#define DVSTILEOFF(pipe)((const i915_reg_t){ .reg = (((0x721a4) + (pipe) * ((0x731a4)
- (0x721a4)))) }) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)((const i915_reg_t){ .reg = (((0x721a4) + (pipe) * ((0x731a4)
- (0x721a4)))) })
6668#define DVSKEYVAL(pipe)((const i915_reg_t){ .reg = (((0x72194) + (pipe) * ((0x73194)
- (0x72194)))) }) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)((const i915_reg_t){ .reg = (((0x72194) + (pipe) * ((0x73194)
- (0x72194)))) })
6669#define DVSKEYMSK(pipe)((const i915_reg_t){ .reg = (((0x72198) + (pipe) * ((0x73198)
- (0x72198)))) }) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)((const i915_reg_t){ .reg = (((0x72198) + (pipe) * ((0x73198)
- (0x72198)))) })
6670#define DVSSURFLIVE(pipe)((const i915_reg_t){ .reg = (((0x721ac) + (pipe) * ((0x731ac)
- (0x721ac)))) }) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)((const i915_reg_t){ .reg = (((0x721ac) + (pipe) * ((0x731ac)
- (0x721ac)))) })
6671#define DVSGAMC_G4X(pipe, i)((const i915_reg_t){ .reg = (((0x721e0) + (pipe) * ((0x731e0)
- (0x721e0))) + (5 - (i)) * 4) }) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4)((const i915_reg_t){ .reg = (((0x721e0) + (pipe) * ((0x731e0)
- (0x721e0))) + (5 - (i)) * 4) }) /* 6 x u0.8 */
6672#define DVSGAMC_ILK(pipe, i)((const i915_reg_t){ .reg = (((0x72300) + (pipe) * ((0x73300)
- (0x72300))) + (i) * 4) }) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4)((const i915_reg_t){ .reg = (((0x72300) + (pipe) * ((0x73300)
- (0x72300))) + (i) * 4) }) /* 16 x u0.10 */
6673#define DVSGAMCMAX_ILK(pipe, i)((const i915_reg_t){ .reg = (((0x72340) + (pipe) * ((0x73340)
- (0x72340))) + (i) * 4) }) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4)((const i915_reg_t){ .reg = (((0x72340) + (pipe) * ((0x73340)
- (0x72340))) + (i) * 4) }) /* 3 x u1.10 */
6674
6675#define _SPRA_CTL0x70280 0x70280
6676#define SPRITE_ENABLE(1 << 31) (1 << 31)
6677#define SPRITE_GAMMA_ENABLE(1 << 30) (1 << 30)
6678#define SPRITE_YUV_RANGE_CORRECTION_DISABLE(1 << 28) (1 << 28)
6679#define SPRITE_PIXFORMAT_MASK(7 << 25) (7 << 25)
6680#define SPRITE_FORMAT_YUV422(0 << 25) (0 << 25)
6681#define SPRITE_FORMAT_RGBX101010(1 << 25) (1 << 25)
6682#define SPRITE_FORMAT_RGBX888(2 << 25) (2 << 25)
6683#define SPRITE_FORMAT_RGBX161616(3 << 25) (3 << 25)
6684#define SPRITE_FORMAT_YUV444(4 << 25) (4 << 25)
6685#define SPRITE_FORMAT_XR_BGR101010(5 << 25) (5 << 25) /* Extended range */
6686#define SPRITE_PIPE_CSC_ENABLE(1 << 24) (1 << 24)
6687#define SPRITE_SOURCE_KEY(1 << 22) (1 << 22)
6688#define SPRITE_RGB_ORDER_RGBX(1 << 20) (1 << 20) /* only for 888 and 161616 */
6689#define SPRITE_YUV_TO_RGB_CSC_DISABLE(1 << 19) (1 << 19)
6690#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18) (1 << 18) /* 0 is BT601 */
6691#define SPRITE_YUV_BYTE_ORDER_MASK(3 << 16) (3 << 16)
6692#define SPRITE_YUV_ORDER_YUYV(0 << 16) (0 << 16)
6693#define SPRITE_YUV_ORDER_UYVY(1 << 16) (1 << 16)
6694#define SPRITE_YUV_ORDER_YVYU(2 << 16) (2 << 16)
6695#define SPRITE_YUV_ORDER_VYUY(3 << 16) (3 << 16)
6696#define SPRITE_ROTATE_180(1 << 15) (1 << 15)
6697#define SPRITE_TRICKLE_FEED_DISABLE(1 << 14) (1 << 14)
6698#define SPRITE_INT_GAMMA_DISABLE(1 << 13) (1 << 13)
6699#define SPRITE_TILED(1 << 10) (1 << 10)
6700#define SPRITE_DEST_KEY(1 << 2) (1 << 2)
6701#define _SPRA_LINOFF0x70284 0x70284
6702#define _SPRA_STRIDE0x70288 0x70288
6703#define _SPRA_POS0x7028c 0x7028c
6704#define _SPRA_SIZE0x70290 0x70290
6705#define _SPRA_KEYVAL0x70294 0x70294
6706#define _SPRA_KEYMSK0x70298 0x70298
6707#define _SPRA_SURF0x7029c 0x7029c
6708#define _SPRA_KEYMAX0x702a0 0x702a0
6709#define _SPRA_TILEOFF0x702a4 0x702a4
6710#define _SPRA_OFFSET0x702a4 0x702a4
6711#define _SPRA_SURFLIVE0x702ac 0x702ac
6712#define _SPRA_SCALE0x70304 0x70304
6713#define SPRITE_SCALE_ENABLE(1 << 31) (1 << 31)
6714#define SPRITE_FILTER_MASK(3 << 29) (3 << 29)
6715#define SPRITE_FILTER_MEDIUM(0 << 29) (0 << 29)
6716#define SPRITE_FILTER_ENHANCING(1 << 29) (1 << 29)
6717#define SPRITE_FILTER_SOFTENING(2 << 29) (2 << 29)
6718#define SPRITE_VERTICAL_OFFSET_HALF(1 << 28) (1 << 28) /* must be enabled below */
6719#define SPRITE_VERTICAL_OFFSET_ENABLE(1 << 27) (1 << 27)
6720#define _SPRA_GAMC0x70400 0x70400
6721#define _SPRA_GAMC160x70440 0x70440
6722#define _SPRA_GAMC170x7044c 0x7044c
6723
6724#define _SPRB_CTL0x71280 0x71280
6725#define _SPRB_LINOFF0x71284 0x71284
6726#define _SPRB_STRIDE0x71288 0x71288
6727#define _SPRB_POS0x7128c 0x7128c
6728#define _SPRB_SIZE0x71290 0x71290
6729#define _SPRB_KEYVAL0x71294 0x71294
6730#define _SPRB_KEYMSK0x71298 0x71298
6731#define _SPRB_SURF0x7129c 0x7129c
6732#define _SPRB_KEYMAX0x712a0 0x712a0
6733#define _SPRB_TILEOFF0x712a4 0x712a4
6734#define _SPRB_OFFSET0x712a4 0x712a4
6735#define _SPRB_SURFLIVE0x712ac 0x712ac
6736#define _SPRB_SCALE0x71304 0x71304
6737#define _SPRB_GAMC0x71400 0x71400
6738#define _SPRB_GAMC160x71440 0x71440
6739#define _SPRB_GAMC170x7144c 0x7144c
6740
6741#define SPRCTL(pipe)((const i915_reg_t){ .reg = (((0x70280) + (pipe) * ((0x71280)
- (0x70280)))) }) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)((const i915_reg_t){ .reg = (((0x70280) + (pipe) * ((0x71280)
- (0x70280)))) })
6742#define SPRLINOFF(pipe)((const i915_reg_t){ .reg = (((0x70284) + (pipe) * ((0x71284)
- (0x70284)))) }) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)((const i915_reg_t){ .reg = (((0x70284) + (pipe) * ((0x71284)
- (0x70284)))) })
6743#define SPRSTRIDE(pipe)((const i915_reg_t){ .reg = (((0x70288) + (pipe) * ((0x71288)
- (0x70288)))) }) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)((const i915_reg_t){ .reg = (((0x70288) + (pipe) * ((0x71288)
- (0x70288)))) })
6744#define SPRPOS(pipe)((const i915_reg_t){ .reg = (((0x7028c) + (pipe) * ((0x7128c)
- (0x7028c)))) }) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)((const i915_reg_t){ .reg = (((0x7028c) + (pipe) * ((0x7128c)
- (0x7028c)))) })
6745#define SPRSIZE(pipe)((const i915_reg_t){ .reg = (((0x70290) + (pipe) * ((0x71290)
- (0x70290)))) }) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)((const i915_reg_t){ .reg = (((0x70290) + (pipe) * ((0x71290)
- (0x70290)))) })
6746#define SPRKEYVAL(pipe)((const i915_reg_t){ .reg = (((0x70294) + (pipe) * ((0x71294)
- (0x70294)))) }) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)((const i915_reg_t){ .reg = (((0x70294) + (pipe) * ((0x71294)
- (0x70294)))) })
6747#define SPRKEYMSK(pipe)((const i915_reg_t){ .reg = (((0x70298) + (pipe) * ((0x71298)
- (0x70298)))) }) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)((const i915_reg_t){ .reg = (((0x70298) + (pipe) * ((0x71298)
- (0x70298)))) })
6748#define SPRSURF(pipe)((const i915_reg_t){ .reg = (((0x7029c) + (pipe) * ((0x7129c)
- (0x7029c)))) }) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)((const i915_reg_t){ .reg = (((0x7029c) + (pipe) * ((0x7129c)
- (0x7029c)))) })
6749#define SPRKEYMAX(pipe)((const i915_reg_t){ .reg = (((0x702a0) + (pipe) * ((0x712a0)
- (0x702a0)))) }) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)((const i915_reg_t){ .reg = (((0x702a0) + (pipe) * ((0x712a0)
- (0x702a0)))) })
6750#define SPRTILEOFF(pipe)((const i915_reg_t){ .reg = (((0x702a4) + (pipe) * ((0x712a4)
- (0x702a4)))) }) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)((const i915_reg_t){ .reg = (((0x702a4) + (pipe) * ((0x712a4)
- (0x702a4)))) })
6751#define SPROFFSET(pipe)((const i915_reg_t){ .reg = (((0x702a4) + (pipe) * ((0x712a4)
- (0x702a4)))) }) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)((const i915_reg_t){ .reg = (((0x702a4) + (pipe) * ((0x712a4)
- (0x702a4)))) })
6752#define SPRSCALE(pipe)((const i915_reg_t){ .reg = (((0x70304) + (pipe) * ((0x71304)
- (0x70304)))) }) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)((const i915_reg_t){ .reg = (((0x70304) + (pipe) * ((0x71304)
- (0x70304)))) })
6753#define SPRGAMC(pipe, i)((const i915_reg_t){ .reg = (((0x70400) + (pipe) * ((0x71400)
- (0x70400))) + (i) * 4) }) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4)((const i915_reg_t){ .reg = (((0x70400) + (pipe) * ((0x71400)
- (0x70400))) + (i) * 4) }) /* 16 x u0.10 */
6754#define SPRGAMC16(pipe, i)((const i915_reg_t){ .reg = (((0x70440) + (pipe) * ((0x71440)
- (0x70440))) + (i) * 4) }) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4)((const i915_reg_t){ .reg = (((0x70440) + (pipe) * ((0x71440)
- (0x70440))) + (i) * 4) }) /* 3 x u1.10 */
6755#define SPRGAMC17(pipe, i)((const i915_reg_t){ .reg = (((0x7044c) + (pipe) * ((0x7144c)
- (0x7044c))) + (i) * 4) }) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4)((const i915_reg_t){ .reg = (((0x7044c) + (pipe) * ((0x7144c)
- (0x7044c))) + (i) * 4) }) /* 3 x u2.10 */
6756#define SPRSURFLIVE(pipe)((const i915_reg_t){ .reg = (((0x702ac) + (pipe) * ((0x712ac)
- (0x702ac)))) }) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)((const i915_reg_t){ .reg = (((0x702ac) + (pipe) * ((0x712ac)
- (0x702ac)))) })
6757
6758#define _SPACNTR(0x180000 + 0x72180) (VLV_DISPLAY_BASE0x180000 + 0x72180)
6759#define SP_ENABLE(1 << 31) (1 << 31)
6760#define SP_GAMMA_ENABLE(1 << 30) (1 << 30)
6761#define SP_PIXFORMAT_MASK(0xf << 26) (0xf << 26)
6762#define SP_FORMAT_YUV422(0x0 << 26) (0x0 << 26)
6763#define SP_FORMAT_8BPP(0x2 << 26) (0x2 << 26)
6764#define SP_FORMAT_BGR565(0x5 << 26) (0x5 << 26)
6765#define SP_FORMAT_BGRX8888(0x6 << 26) (0x6 << 26)
6766#define SP_FORMAT_BGRA8888(0x7 << 26) (0x7 << 26)
6767#define SP_FORMAT_RGBX1010102(0x8 << 26) (0x8 << 26)
6768#define SP_FORMAT_RGBA1010102(0x9 << 26) (0x9 << 26)
6769#define SP_FORMAT_BGRX1010102(0xa << 26) (0xa << 26) /* CHV pipe B */
6770#define SP_FORMAT_BGRA1010102(0xb << 26) (0xb << 26) /* CHV pipe B */
6771#define SP_FORMAT_RGBX8888(0xe << 26) (0xe << 26)
6772#define SP_FORMAT_RGBA8888(0xf << 26) (0xf << 26)
6773#define SP_ALPHA_PREMULTIPLY(1 << 23) (1 << 23) /* CHV pipe B */
6774#define SP_SOURCE_KEY(1 << 22) (1 << 22)
6775#define SP_YUV_FORMAT_BT709(1 << 18) (1 << 18)
6776#define SP_YUV_BYTE_ORDER_MASK(3 << 16) (3 << 16)
6777#define SP_YUV_ORDER_YUYV(0 << 16) (0 << 16)
6778#define SP_YUV_ORDER_UYVY(1 << 16) (1 << 16)
6779#define SP_YUV_ORDER_YVYU(2 << 16) (2 << 16)
6780#define SP_YUV_ORDER_VYUY(3 << 16) (3 << 16)
6781#define SP_ROTATE_180(1 << 15) (1 << 15)
6782#define SP_TILED(1 << 10) (1 << 10)
6783#define SP_MIRROR(1 << 8) (1 << 8) /* CHV pipe B */
6784#define _SPALINOFF(0x180000 + 0x72184) (VLV_DISPLAY_BASE0x180000 + 0x72184)
6785#define _SPASTRIDE(0x180000 + 0x72188) (VLV_DISPLAY_BASE0x180000 + 0x72188)
6786#define _SPAPOS(0x180000 + 0x7218c) (VLV_DISPLAY_BASE0x180000 + 0x7218c)
6787#define _SPASIZE(0x180000 + 0x72190) (VLV_DISPLAY_BASE0x180000 + 0x72190)
6788#define _SPAKEYMINVAL(0x180000 + 0x72194) (VLV_DISPLAY_BASE0x180000 + 0x72194)
6789#define _SPAKEYMSK(0x180000 + 0x72198) (VLV_DISPLAY_BASE0x180000 + 0x72198)
6790#define _SPASURF(0x180000 + 0x7219c) (VLV_DISPLAY_BASE0x180000 + 0x7219c)
6791#define _SPAKEYMAXVAL(0x180000 + 0x721a0) (VLV_DISPLAY_BASE0x180000 + 0x721a0)
6792#define _SPATILEOFF(0x180000 + 0x721a4) (VLV_DISPLAY_BASE0x180000 + 0x721a4)
6793#define _SPACONSTALPHA(0x180000 + 0x721a8) (VLV_DISPLAY_BASE0x180000 + 0x721a8)
6794#define SP_CONST_ALPHA_ENABLE(1 << 31) (1 << 31)
6795#define _SPACLRC0(0x180000 + 0x721d0) (VLV_DISPLAY_BASE0x180000 + 0x721d0)
6796#define SP_CONTRAST(x)((x) << 18) ((x) << 18) /* u3.6 */
6797#define SP_BRIGHTNESS(x)((x) & 0xff) ((x) & 0xff) /* s8 */
6798#define _SPACLRC1(0x180000 + 0x721d4) (VLV_DISPLAY_BASE0x180000 + 0x721d4)
6799#define SP_SH_SIN(x)(((x) & 0x7ff) << 16) (((x) & 0x7ff) << 16) /* s4.7 */
6800#define SP_SH_COS(x)(x) (x) /* u3.7 */
6801#define _SPAGAMC(0x180000 + 0x721e0) (VLV_DISPLAY_BASE0x180000 + 0x721e0)
6802
6803#define _SPBCNTR(0x180000 + 0x72280) (VLV_DISPLAY_BASE0x180000 + 0x72280)
6804#define _SPBLINOFF(0x180000 + 0x72284) (VLV_DISPLAY_BASE0x180000 + 0x72284)
6805#define _SPBSTRIDE(0x180000 + 0x72288) (VLV_DISPLAY_BASE0x180000 + 0x72288)
6806#define _SPBPOS(0x180000 + 0x7228c) (VLV_DISPLAY_BASE0x180000 + 0x7228c)
6807#define _SPBSIZE(0x180000 + 0x72290) (VLV_DISPLAY_BASE0x180000 + 0x72290)
6808#define _SPBKEYMINVAL(0x180000 + 0x72294) (VLV_DISPLAY_BASE0x180000 + 0x72294)
6809#define _SPBKEYMSK(0x180000 + 0x72298) (VLV_DISPLAY_BASE0x180000 + 0x72298)
6810#define _SPBSURF(0x180000 + 0x7229c) (VLV_DISPLAY_BASE0x180000 + 0x7229c)
6811#define _SPBKEYMAXVAL(0x180000 + 0x722a0) (VLV_DISPLAY_BASE0x180000 + 0x722a0)
6812#define _SPBTILEOFF(0x180000 + 0x722a4) (VLV_DISPLAY_BASE0x180000 + 0x722a4)
6813#define _SPBCONSTALPHA(0x180000 + 0x722a8) (VLV_DISPLAY_BASE0x180000 + 0x722a8)
6814#define _SPBCLRC0(0x180000 + 0x722d0) (VLV_DISPLAY_BASE0x180000 + 0x722d0)
6815#define _SPBCLRC1(0x180000 + 0x722d4) (VLV_DISPLAY_BASE0x180000 + 0x722d4)
6816#define _SPBGAMC(0x180000 + 0x722e0) (VLV_DISPLAY_BASE0x180000 + 0x722e0)
6817
6818#define _VLV_SPR(pipe, plane_id, reg_a, reg_b)(((reg_a)) + ((pipe) * 2 + (plane_id) - PLANE_SPRITE0) * (((reg_b
)) - ((reg_a)))) \
6819 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))(((reg_a)) + ((pipe) * 2 + (plane_id) - PLANE_SPRITE0) * (((reg_b
)) - ((reg_a))))
6820#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b)((const i915_reg_t){ .reg = (((((reg_a))) + (((pipe)) * 2 + (
(plane_id)) - PLANE_SPRITE0) * ((((reg_b))) - (((reg_a)))))) }
) \
6821 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))((const i915_reg_t){ .reg = (((((reg_a))) + (((pipe)) * 2 + (
(plane_id)) - PLANE_SPRITE0) * ((((reg_b))) - (((reg_a)))))) }
)
6822
6823#define SPCNTR(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72180)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72280)))) - ((((0x180000 + 0x72180))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72180)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72280)))) - ((((0x180000 + 0x72180))))))) })
6824#define SPLINOFF(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72184)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72284)))) - ((((0x180000 + 0x72184))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72184)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72284)))) - ((((0x180000 + 0x72184))))))) })
6825#define SPSTRIDE(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72188)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72288)))) - ((((0x180000 + 0x72188))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72188)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72288)))) - ((((0x180000 + 0x72188))))))) })
6826#define SPPOS(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x7218c)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x7228c)))) - ((((0x180000 + 0x7218c))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)((const i915_reg_t){ .reg = ((((((0x180000 + 0x7218c)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x7228c)))) - ((((0x180000 + 0x7218c))))))) })
6827#define SPSIZE(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72190)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72290)))) - ((((0x180000 + 0x72190))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72190)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72290)))) - ((((0x180000 + 0x72190))))))) })
6828#define SPKEYMINVAL(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72194)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72294)))) - ((((0x180000 + 0x72194))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72194)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72294)))) - ((((0x180000 + 0x72194))))))) })
6829#define SPKEYMSK(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72198)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72298)))) - ((((0x180000 + 0x72198))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)((const i915_reg_t){ .reg = ((((((0x180000 + 0x72198)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x72298)))) - ((((0x180000 + 0x72198))))))) })
6830#define SPSURF(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x7219c)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x7229c)))) - ((((0x180000 + 0x7219c))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)((const i915_reg_t){ .reg = ((((((0x180000 + 0x7219c)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x7229c)))) - ((((0x180000 + 0x7219c))))))) })
6831#define SPKEYMAXVAL(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a0)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a0)))) - ((((0x180000 + 0x721a0))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a0)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a0)))) - ((((0x180000 + 0x721a0))))))) })
6832#define SPTILEOFF(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a4)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a4)))) - ((((0x180000 + 0x721a4))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a4)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a4)))) - ((((0x180000 + 0x721a4))))))) })
6833#define SPCONSTALPHA(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a8)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a8)))) - ((((0x180000 + 0x721a8))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721a8)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722a8)))) - ((((0x180000 + 0x721a8))))))) })
6834#define SPCLRC0(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721d0)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722d0)))) - ((((0x180000 + 0x721d0))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721d0)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722d0)))) - ((((0x180000 + 0x721d0))))))) })
6835#define SPCLRC1(pipe, plane_id)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721d4)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722d4)))) - ((((0x180000 + 0x721d4))))))) }) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)((const i915_reg_t){ .reg = ((((((0x180000 + 0x721d4)))) + ((
((pipe))) * 2 + (((plane_id))) - PLANE_SPRITE0) * (((((0x180000
+ 0x722d4)))) - ((((0x180000 + 0x721d4))))))) })
6836#define SPGAMC(pipe, plane_id, i)((const i915_reg_t){ .reg = (((((0x180000 + 0x721e0))) + (((pipe
)) * 2 + ((plane_id)) - PLANE_SPRITE0) * ((((0x180000 + 0x722e0
))) - (((0x180000 + 0x721e0))))) + (5 - (i)) * 4) }) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4)((const i915_reg_t){ .reg = (((((0x180000 + 0x721e0))) + (((pipe
)) * 2 + ((plane_id)) - PLANE_SPRITE0) * ((((0x180000 + 0x722e0
))) - (((0x180000 + 0x721e0))))) + (5 - (i)) * 4) }) /* 6 x u0.10 */
6837
6838/*
6839 * CHV pipe B sprite CSC
6840 *
6841 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6842 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6843 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6844 */
6845#define _MMIO_CHV_SPCSC(plane_id, reg)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (reg)) }) \
6846 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (reg)) })
6847
6848#define SPCSCYGOFF(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d900)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d900)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d900)) })
6849#define SPCSCCBOFF(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d904)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d904)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d904)) })
6850#define SPCSCCROFF(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d908)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d908)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d908)) })
6851#define SPCSC_OOFF(x)(((x) & 0x7ff) << 16) (((x) & 0x7ff) << 16) /* s11 */
6852#define SPCSC_IOFF(x)(((x) & 0x7ff) << 0) (((x) & 0x7ff) << 0) /* s11 */
6853
6854#define SPCSCC01(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d90c)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d90c)) })
6855#define SPCSCC23(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d910)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d910)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d910)) })
6856#define SPCSCC45(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d914)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d914)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d914)) })
6857#define SPCSCC67(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d918)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d918)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d918)) })
6858#define SPCSCC8(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d91c)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d91c)) })
6859#define SPCSC_C1(x)(((x) & 0x7fff) << 16) (((x) & 0x7fff) << 16) /* s3.12 */
6860#define SPCSC_C0(x)(((x) & 0x7fff) << 0) (((x) & 0x7fff) << 0) /* s3.12 */
6861
6862#define SPCSCYGICLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d920)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d920)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d920)) })
6863#define SPCSCCBICLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d924)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d924)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d924)) })
6864#define SPCSCCRICLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d928)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d928)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d928)) })
6865#define SPCSC_IMAX(x)(((x) & 0x7ff) << 16) (((x) & 0x7ff) << 16) /* s11 */
6866#define SPCSC_IMIN(x)(((x) & 0x7ff) << 0) (((x) & 0x7ff) << 0) /* s11 */
6867
6868#define SPCSCYGOCLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d92c)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d92c)) })
6869#define SPCSCCBOCLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d930)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d930)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d930)) })
6870#define SPCSCCROCLAMP(plane_id)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d934)) }) _MMIO_CHV_SPCSC(plane_id, 0x6d934)((const i915_reg_t){ .reg = (0x180000 + ((plane_id) - PLANE_SPRITE0
) * 0x1000 + (0x6d934)) })
6871#define SPCSC_OMAX(x)((x) << 16) ((x) << 16) /* u10 */
6872#define SPCSC_OMIN(x)((x) << 0) ((x) << 0) /* u10 */
6873
6874/* Skylake plane registers */
6875
6876#define _PLANE_CTL_1_A0x70180 0x70180
6877#define _PLANE_CTL_2_A0x70280 0x70280
6878#define _PLANE_CTL_3_A0x70380 0x70380
6879#define PLANE_CTL_ENABLE(1 << 31) (1 << 31)
6880#define PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30) (1 << 30) /* Pre-GLK */
6881#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE(1 << 28) (1 << 28)
6882/*
6883 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6884 * expanded to include bit 23 as well. However, the shift-24 based values
6885 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6886 */
6887#define PLANE_CTL_FORMAT_MASK(0xf << 24) (0xf << 24)
6888#define PLANE_CTL_FORMAT_YUV422(0 << 24) (0 << 24)
6889#define PLANE_CTL_FORMAT_NV12(1 << 24) (1 << 24)
6890#define PLANE_CTL_FORMAT_XRGB_2101010(2 << 24) (2 << 24)
6891#define PLANE_CTL_FORMAT_P010(3 << 24) (3 << 24)
6892#define PLANE_CTL_FORMAT_XRGB_8888(4 << 24) (4 << 24)
6893#define PLANE_CTL_FORMAT_P012(5 << 24) (5 << 24)
6894#define PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24) (6 << 24)
6895#define PLANE_CTL_FORMAT_P016(7 << 24) (7 << 24)
6896#define PLANE_CTL_FORMAT_XYUV(8 << 24) (8 << 24)
6897#define PLANE_CTL_FORMAT_INDEXED(12 << 24) (12 << 24)
6898#define PLANE_CTL_FORMAT_RGB_565(14 << 24) (14 << 24)
6899#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23) (0x1f << 23)
6900#define PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) (1 << 23) /* Pre-GLK */
6901#define PLANE_CTL_FORMAT_Y210(1 << 23) (1 << 23)
6902#define PLANE_CTL_FORMAT_Y212(3 << 23) (3 << 23)
6903#define PLANE_CTL_FORMAT_Y216(5 << 23) (5 << 23)
6904#define PLANE_CTL_FORMAT_Y410(7 << 23) (7 << 23)
6905#define PLANE_CTL_FORMAT_Y412(9 << 23) (9 << 23)
6906#define PLANE_CTL_FORMAT_Y416(0xb << 23) (0xb << 23)
6907#define PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21) (0x3 << 21)
6908#define PLANE_CTL_KEY_ENABLE_SOURCE(1 << 21) (1 << 21)
6909#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21) (2 << 21)
6910#define PLANE_CTL_ORDER_BGRX(0 << 20) (0 << 20)
6911#define PLANE_CTL_ORDER_RGBX(1 << 20) (1 << 20)
6912#define PLANE_CTL_YUV420_Y_PLANE(1 << 19) (1 << 19)
6913#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18) (1 << 18)
6914#define PLANE_CTL_YUV422_ORDER_MASK(0x3 << 16) (0x3 << 16)
6915#define PLANE_CTL_YUV422_YUYV(0 << 16) (0 << 16)
6916#define PLANE_CTL_YUV422_UYVY(1 << 16) (1 << 16)
6917#define PLANE_CTL_YUV422_YVYU(2 << 16) (2 << 16)
6918#define PLANE_CTL_YUV422_VYUY(3 << 16) (3 << 16)
6919#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15) (1 << 15)
6920#define PLANE_CTL_TRICKLE_FEED_DISABLE(1 << 14) (1 << 14)
6921#define PLANE_CTL_CLEAR_COLOR_DISABLE(1 << 13) (1 << 13) /* TGL+ */
6922#define PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) (1 << 13) /* Pre-GLK */
6923#define PLANE_CTL_TILED_MASK(0x7 << 10) (0x7 << 10)
6924#define PLANE_CTL_TILED_LINEAR(0 << 10) (0 << 10)
6925#define PLANE_CTL_TILED_X(1 << 10) (1 << 10)
6926#define PLANE_CTL_TILED_Y(4 << 10) (4 << 10)
6927#define PLANE_CTL_TILED_YF(5 << 10) (5 << 10)
6928#define PLANE_CTL_FLIP_HORIZONTAL(1 << 8) (1 << 8)
6929#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE(1 << 4) (1 << 4) /* TGL+ */
6930#define PLANE_CTL_ALPHA_MASK(0x3 << 4) (0x3 << 4) /* Pre-GLK */
6931#define PLANE_CTL_ALPHA_DISABLE(0 << 4) (0 << 4)
6932#define PLANE_CTL_ALPHA_SW_PREMULTIPLY(2 << 4) (2 << 4)
6933#define PLANE_CTL_ALPHA_HW_PREMULTIPLY(3 << 4) (3 << 4)
6934#define PLANE_CTL_ROTATE_MASK0x3 0x3
6935#define PLANE_CTL_ROTATE_00x0 0x0
6936#define PLANE_CTL_ROTATE_900x1 0x1
6937#define PLANE_CTL_ROTATE_1800x2 0x2
6938#define PLANE_CTL_ROTATE_2700x3 0x3
6939#define _PLANE_STRIDE_1_A0x70188 0x70188
6940#define _PLANE_STRIDE_2_A0x70288 0x70288
6941#define _PLANE_STRIDE_3_A0x70388 0x70388
6942#define _PLANE_POS_1_A0x7018c 0x7018c
6943#define _PLANE_POS_2_A0x7028c 0x7028c
6944#define _PLANE_POS_3_A0x7038c 0x7038c
6945#define _PLANE_SIZE_1_A0x70190 0x70190
6946#define _PLANE_SIZE_2_A0x70290 0x70290
6947#define _PLANE_SIZE_3_A0x70390 0x70390
6948#define _PLANE_SURF_1_A0x7019c 0x7019c
6949#define _PLANE_SURF_2_A0x7029c 0x7029c
6950#define _PLANE_SURF_3_A0x7039c 0x7039c
6951#define _PLANE_OFFSET_1_A0x701a4 0x701a4
6952#define _PLANE_OFFSET_2_A0x702a4 0x702a4
6953#define _PLANE_OFFSET_3_A0x703a4 0x703a4
6954#define _PLANE_KEYVAL_1_A0x70194 0x70194
6955#define _PLANE_KEYVAL_2_A0x70294 0x70294
6956#define _PLANE_KEYMSK_1_A0x70198 0x70198
6957#define _PLANE_KEYMSK_2_A0x70298 0x70298
6958#define PLANE_KEYMSK_ALPHA_ENABLE(1 << 31) (1 << 31)
6959#define _PLANE_KEYMAX_1_A0x701a0 0x701a0
6960#define _PLANE_KEYMAX_2_A0x702a0 0x702a0
6961#define PLANE_KEYMAX_ALPHA(a)((a) << 24) ((a) << 24)
6962#define _PLANE_AUX_DIST_1_A0x701c0 0x701c0
6963#define _PLANE_AUX_DIST_2_A0x702c0 0x702c0
6964#define _PLANE_AUX_OFFSET_1_A0x701c4 0x701c4
6965#define _PLANE_AUX_OFFSET_2_A0x702c4 0x702c4
6966#define _PLANE_CUS_CTL_1_A0x701c8 0x701c8
6967#define _PLANE_CUS_CTL_2_A0x702c8 0x702c8
6968#define PLANE_CUS_ENABLE(1 << 31) (1 << 31)
6969#define PLANE_CUS_PLANE_4_RKL(0 << 30) (0 << 30)
6970#define PLANE_CUS_PLANE_5_RKL(1 << 30) (1 << 30)
6971#define PLANE_CUS_PLANE_6(0 << 30) (0 << 30)
6972#define PLANE_CUS_PLANE_7(1 << 30) (1 << 30)
6973#define PLANE_CUS_HPHASE_SIGN_NEGATIVE(1 << 19) (1 << 19)
6974#define PLANE_CUS_HPHASE_0(0 << 16) (0 << 16)
6975#define PLANE_CUS_HPHASE_0_25(1 << 16) (1 << 16)
6976#define PLANE_CUS_HPHASE_0_5(2 << 16) (2 << 16)
6977#define PLANE_CUS_VPHASE_SIGN_NEGATIVE(1 << 15) (1 << 15)
6978#define PLANE_CUS_VPHASE_0(0 << 12) (0 << 12)
6979#define PLANE_CUS_VPHASE_0_25(1 << 12) (1 << 12)
6980#define PLANE_CUS_VPHASE_0_5(2 << 12) (2 << 12)
6981#define _PLANE_COLOR_CTL_1_A0x701CC 0x701CC /* GLK+ */
6982#define _PLANE_COLOR_CTL_2_A0x702CC 0x702CC /* GLK+ */
6983#define _PLANE_COLOR_CTL_3_A0x703CC 0x703CC /* GLK+ */
6984#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) (1 << 30) /* Pre-ICL */
6985#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE(1 << 28) (1 << 28)
6986#define PLANE_COLOR_INPUT_CSC_ENABLE(1 << 20) (1 << 20) /* ICL+ */
6987#define PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23) (1 << 23) /* Pre-ICL */
6988#define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17) (0 << 17)
6989#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601(1 << 17) (1 << 17)
6990#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17) (2 << 17)
6991#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17) (3 << 17)
6992#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020(4 << 17) (4 << 17)
6993#define PLANE_COLOR_PLANE_GAMMA_DISABLE(1 << 13) (1 << 13)
6994#define PLANE_COLOR_ALPHA_MASK(0x3 << 4) (0x3 << 4)
6995#define PLANE_COLOR_ALPHA_DISABLE(0 << 4) (0 << 4)
6996#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY(2 << 4) (2 << 4)
6997#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY(3 << 4) (3 << 4)
6998#define _PLANE_BUF_CFG_1_A0x7027c 0x7027c
6999#define _PLANE_BUF_CFG_2_A0x7037c 0x7037c
7000#define _PLANE_NV12_BUF_CFG_1_A0x70278 0x70278
7001#define _PLANE_NV12_BUF_CFG_2_A0x70378 0x70378
7002
7003/* Input CSC Register Definitions */
7004#define _PLANE_INPUT_CSC_RY_GY_1_A0x701E0 0x701E0
7005#define _PLANE_INPUT_CSC_RY_GY_2_A0x702E0 0x702E0
7006
7007#define _PLANE_INPUT_CSC_RY_GY_1_B0x711E0 0x711E0
7008#define _PLANE_INPUT_CSC_RY_GY_2_B0x712E0 0x712E0
7009
7010#define _PLANE_INPUT_CSC_RY_GY_1(pipe)((0x701E0) + (pipe) * ((0x711E0) - (0x701E0))) \
7011 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \((0x701E0) + (pipe) * ((0x711E0) - (0x701E0)))
7012 _PLANE_INPUT_CSC_RY_GY_1_B)((0x701E0) + (pipe) * ((0x711E0) - (0x701E0)))
7013#define _PLANE_INPUT_CSC_RY_GY_2(pipe)((0x702E0) + (pipe) * ((0x712E0) - (0x702E0))) \
7014 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \((0x702E0) + (pipe) * ((0x712E0) - (0x702E0)))
7015 _PLANE_INPUT_CSC_RY_GY_2_B)((0x702E0) + (pipe) * ((0x712E0) - (0x702E0)))
7016
7017#define PLANE_INPUT_CSC_COEFF(pipe, plane, index)((const i915_reg_t){ .reg = (((((0x701E0) + (pipe) * ((0x711E0
) - (0x701E0))) + (index) * 4) + (plane) * ((((0x702E0) + (pipe
) * ((0x712E0) - (0x702E0))) + (index) * 4) - (((0x701E0) + (
pipe) * ((0x711E0) - (0x701E0))) + (index) * 4)))) }) \
7018 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \((const i915_reg_t){ .reg = (((((0x701E0) + (pipe) * ((0x711E0
) - (0x701E0))) + (index) * 4) + (plane) * ((((0x702E0) + (pipe
) * ((0x712E0) - (0x702E0))) + (index) * 4) - (((0x701E0) + (
pipe) * ((0x711E0) - (0x701E0))) + (index) * 4)))) })
7019 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)((const i915_reg_t){ .reg = (((((0x701E0) + (pipe) * ((0x711E0
) - (0x701E0))) + (index) * 4) + (plane) * ((((0x702E0) + (pipe
) * ((0x712E0) - (0x702E0))) + (index) * 4) - (((0x701E0) + (
pipe) * ((0x711E0) - (0x701E0))) + (index) * 4)))) })
7020
7021#define _PLANE_INPUT_CSC_PREOFF_HI_1_A0x701F8 0x701F8
7022#define _PLANE_INPUT_CSC_PREOFF_HI_2_A0x702F8 0x702F8
7023
7024#define _PLANE_INPUT_CSC_PREOFF_HI_1_B0x711F8 0x711F8
7025#define _PLANE_INPUT_CSC_PREOFF_HI_2_B0x712F8 0x712F8
7026
7027#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)((0x701F8) + (pipe) * ((0x711F8) - (0x701F8))) \
7028 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \((0x701F8) + (pipe) * ((0x711F8) - (0x701F8)))
7029 _PLANE_INPUT_CSC_PREOFF_HI_1_B)((0x701F8) + (pipe) * ((0x711F8) - (0x701F8)))
7030#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)((0x702F8) + (pipe) * ((0x712F8) - (0x702F8))) \
7031 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \((0x702F8) + (pipe) * ((0x712F8) - (0x702F8)))
7032 _PLANE_INPUT_CSC_PREOFF_HI_2_B)((0x702F8) + (pipe) * ((0x712F8) - (0x702F8)))
7033#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)((const i915_reg_t){ .reg = (((((0x701F8) + (pipe) * ((0x711F8
) - (0x701F8))) + (index) * 4) + (plane) * ((((0x702F8) + (pipe
) * ((0x712F8) - (0x702F8))) + (index) * 4) - (((0x701F8) + (
pipe) * ((0x711F8) - (0x701F8))) + (index) * 4)))) }) \
7034 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \((const i915_reg_t){ .reg = (((((0x701F8) + (pipe) * ((0x711F8
) - (0x701F8))) + (index) * 4) + (plane) * ((((0x702F8) + (pipe
) * ((0x712F8) - (0x702F8))) + (index) * 4) - (((0x701F8) + (
pipe) * ((0x711F8) - (0x701F8))) + (index) * 4)))) })
7035 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)((const i915_reg_t){ .reg = (((((0x701F8) + (pipe) * ((0x711F8
) - (0x701F8))) + (index) * 4) + (plane) * ((((0x702F8) + (pipe
) * ((0x712F8) - (0x702F8))) + (index) * 4) - (((0x701F8) + (
pipe) * ((0x711F8) - (0x701F8))) + (index) * 4)))) })
7036
7037#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A0x70204 0x70204
7038#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A0x70304 0x70304
7039
7040#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B0x71204 0x71204
7041#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B0x71304 0x71304
7042
7043#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)((0x70204) + (pipe) * ((0x71204) - (0x70204))) \
7044 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \((0x70204) + (pipe) * ((0x71204) - (0x70204)))
7045 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)((0x70204) + (pipe) * ((0x71204) - (0x70204)))
7046#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)((0x70304) + (pipe) * ((0x71304) - (0x70304))) \
7047 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \((0x70304) + (pipe) * ((0x71304) - (0x70304)))
7048 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)((0x70304) + (pipe) * ((0x71304) - (0x70304)))
7049#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)((const i915_reg_t){ .reg = (((((0x70204) + (pipe) * ((0x71204
) - (0x70204))) + (index) * 4) + (plane) * ((((0x70304) + (pipe
) * ((0x71304) - (0x70304))) + (index) * 4) - (((0x70204) + (
pipe) * ((0x71204) - (0x70204))) + (index) * 4)))) }) \
7050 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \((const i915_reg_t){ .reg = (((((0x70204) + (pipe) * ((0x71204
) - (0x70204))) + (index) * 4) + (plane) * ((((0x70304) + (pipe
) * ((0x71304) - (0x70304))) + (index) * 4) - (((0x70204) + (
pipe) * ((0x71204) - (0x70204))) + (index) * 4)))) })
7051 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)((const i915_reg_t){ .reg = (((((0x70204) + (pipe) * ((0x71204
) - (0x70204))) + (index) * 4) + (plane) * ((((0x70304) + (pipe
) * ((0x71304) - (0x70304))) + (index) * 4) - (((0x70204) + (
pipe) * ((0x71204) - (0x70204))) + (index) * 4)))) })
7052
7053#define _PLANE_CTL_1_B0x71180 0x71180
7054#define _PLANE_CTL_2_B0x71280 0x71280
7055#define _PLANE_CTL_3_B0x71380 0x71380
7056#define _PLANE_CTL_1(pipe)((0x70180) + (pipe) * ((0x71180) - (0x70180))) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)((0x70180) + (pipe) * ((0x71180) - (0x70180)))
7057#define _PLANE_CTL_2(pipe)((0x70280) + (pipe) * ((0x71280) - (0x70280))) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)((0x70280) + (pipe) * ((0x71280) - (0x70280)))
7058#define _PLANE_CTL_3(pipe)((0x70380) + (pipe) * ((0x71380) - (0x70380))) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)((0x70380) + (pipe) * ((0x71380) - (0x70380)))
7059#define PLANE_CTL(pipe, plane)((const i915_reg_t){ .reg = (((((0x70180) + (pipe) * ((0x71180
) - (0x70180)))) + (plane) * ((((0x70280) + (pipe) * ((0x71280
) - (0x70280)))) - (((0x70180) + (pipe) * ((0x71180) - (0x70180
))))))) }) \
7060 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))((const i915_reg_t){ .reg = (((((0x70180) + (pipe) * ((0x71180
) - (0x70180)))) + (plane) * ((((0x70280) + (pipe) * ((0x71280
) - (0x70280)))) - (((0x70180) + (pipe) * ((0x71180) - (0x70180
))))))) })
7061
7062#define _PLANE_STRIDE_1_B0x71188 0x71188
7063#define _PLANE_STRIDE_2_B0x71288 0x71288
7064#define _PLANE_STRIDE_3_B0x71388 0x71388
7065#define _PLANE_STRIDE_1(pipe)((0x70188) + (pipe) * ((0x71188) - (0x70188))) \
7066 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)((0x70188) + (pipe) * ((0x71188) - (0x70188)))
7067#define _PLANE_STRIDE_2(pipe)((0x70288) + (pipe) * ((0x71288) - (0x70288))) \
7068 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)((0x70288) + (pipe) * ((0x71288) - (0x70288)))
7069#define _PLANE_STRIDE_3(pipe)((0x70388) + (pipe) * ((0x71388) - (0x70388))) \
7070 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)((0x70388) + (pipe) * ((0x71388) - (0x70388)))
7071#define PLANE_STRIDE(pipe, plane)((const i915_reg_t){ .reg = (((((0x70188) + (pipe) * ((0x71188
) - (0x70188)))) + (plane) * ((((0x70288) + (pipe) * ((0x71288
) - (0x70288)))) - (((0x70188) + (pipe) * ((0x71188) - (0x70188
))))))) }) \
7072 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))((const i915_reg_t){ .reg = (((((0x70188) + (pipe) * ((0x71188
) - (0x70188)))) + (plane) * ((((0x70288) + (pipe) * ((0x71288
) - (0x70288)))) - (((0x70188) + (pipe) * ((0x71188) - (0x70188
))))))) })
7073
7074#define _PLANE_POS_1_B0x7118c 0x7118c
7075#define _PLANE_POS_2_B0x7128c 0x7128c
7076#define _PLANE_POS_3_B0x7138c 0x7138c
7077#define _PLANE_POS_1(pipe)((0x7018c) + (pipe) * ((0x7118c) - (0x7018c))) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)((0x7018c) + (pipe) * ((0x7118c) - (0x7018c)))
7078#define _PLANE_POS_2(pipe)((0x7028c) + (pipe) * ((0x7128c) - (0x7028c))) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)((0x7028c) + (pipe) * ((0x7128c) - (0x7028c)))
7079#define _PLANE_POS_3(pipe)((0x7038c) + (pipe) * ((0x7138c) - (0x7038c))) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)((0x7038c) + (pipe) * ((0x7138c) - (0x7038c)))
7080#define PLANE_POS(pipe, plane)((const i915_reg_t){ .reg = (((((0x7018c) + (pipe) * ((0x7118c
) - (0x7018c)))) + (plane) * ((((0x7028c) + (pipe) * ((0x7128c
) - (0x7028c)))) - (((0x7018c) + (pipe) * ((0x7118c) - (0x7018c
))))))) }) \
7081 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))((const i915_reg_t){ .reg = (((((0x7018c) + (pipe) * ((0x7118c
) - (0x7018c)))) + (plane) * ((((0x7028c) + (pipe) * ((0x7128c
) - (0x7028c)))) - (((0x7018c) + (pipe) * ((0x7118c) - (0x7018c
))))))) })
7082
7083#define _PLANE_SIZE_1_B0x71190 0x71190
7084#define _PLANE_SIZE_2_B0x71290 0x71290
7085#define _PLANE_SIZE_3_B0x71390 0x71390
7086#define _PLANE_SIZE_1(pipe)((0x70190) + (pipe) * ((0x71190) - (0x70190))) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)((0x70190) + (pipe) * ((0x71190) - (0x70190)))
7087#define _PLANE_SIZE_2(pipe)((0x70290) + (pipe) * ((0x71290) - (0x70290))) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)((0x70290) + (pipe) * ((0x71290) - (0x70290)))
7088#define _PLANE_SIZE_3(pipe)((0x70390) + (pipe) * ((0x71390) - (0x70390))) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)((0x70390) + (pipe) * ((0x71390) - (0x70390)))
7089#define PLANE_SIZE(pipe, plane)((const i915_reg_t){ .reg = (((((0x70190) + (pipe) * ((0x71190
) - (0x70190)))) + (plane) * ((((0x70290) + (pipe) * ((0x71290
) - (0x70290)))) - (((0x70190) + (pipe) * ((0x71190) - (0x70190
))))))) }) \
7090 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))((const i915_reg_t){ .reg = (((((0x70190) + (pipe) * ((0x71190
) - (0x70190)))) + (plane) * ((((0x70290) + (pipe) * ((0x71290
) - (0x70290)))) - (((0x70190) + (pipe) * ((0x71190) - (0x70190
))))))) })
7091
7092#define _PLANE_SURF_1_B0x7119c 0x7119c
7093#define _PLANE_SURF_2_B0x7129c 0x7129c
7094#define _PLANE_SURF_3_B0x7139c 0x7139c
7095#define _PLANE_SURF_1(pipe)((0x7019c) + (pipe) * ((0x7119c) - (0x7019c))) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)((0x7019c) + (pipe) * ((0x7119c) - (0x7019c)))
7096#define _PLANE_SURF_2(pipe)((0x7029c) + (pipe) * ((0x7129c) - (0x7029c))) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)((0x7029c) + (pipe) * ((0x7129c) - (0x7029c)))
7097#define _PLANE_SURF_3(pipe)((0x7039c) + (pipe) * ((0x7139c) - (0x7039c))) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)((0x7039c) + (pipe) * ((0x7139c) - (0x7039c)))
7098#define PLANE_SURF(pipe, plane)((const i915_reg_t){ .reg = (((((0x7019c) + (pipe) * ((0x7119c
) - (0x7019c)))) + (plane) * ((((0x7029c) + (pipe) * ((0x7129c
) - (0x7029c)))) - (((0x7019c) + (pipe) * ((0x7119c) - (0x7019c
))))))) }) \
7099 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))((const i915_reg_t){ .reg = (((((0x7019c) + (pipe) * ((0x7119c
) - (0x7019c)))) + (plane) * ((((0x7029c) + (pipe) * ((0x7129c
) - (0x7029c)))) - (((0x7019c) + (pipe) * ((0x7119c) - (0x7019c
))))))) })
7100
7101#define _PLANE_OFFSET_1_B0x711a4 0x711a4
7102#define _PLANE_OFFSET_2_B0x712a4 0x712a4
7103#define _PLANE_OFFSET_1(pipe)((0x701a4) + (pipe) * ((0x711a4) - (0x701a4))) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)((0x701a4) + (pipe) * ((0x711a4) - (0x701a4)))
7104#define _PLANE_OFFSET_2(pipe)((0x702a4) + (pipe) * ((0x712a4) - (0x702a4))) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)((0x702a4) + (pipe) * ((0x712a4) - (0x702a4)))
7105#define PLANE_OFFSET(pipe, plane)((const i915_reg_t){ .reg = (((((0x701a4) + (pipe) * ((0x711a4
) - (0x701a4)))) + (plane) * ((((0x702a4) + (pipe) * ((0x712a4
) - (0x702a4)))) - (((0x701a4) + (pipe) * ((0x711a4) - (0x701a4
))))))) }) \
7106 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))((const i915_reg_t){ .reg = (((((0x701a4) + (pipe) * ((0x711a4
) - (0x701a4)))) + (plane) * ((((0x702a4) + (pipe) * ((0x712a4
) - (0x702a4)))) - (((0x701a4) + (pipe) * ((0x711a4) - (0x701a4
))))))) })
7107
7108#define _PLANE_KEYVAL_1_B0x71194 0x71194
7109#define _PLANE_KEYVAL_2_B0x71294 0x71294
7110#define _PLANE_KEYVAL_1(pipe)((0x70194) + (pipe) * ((0x71194) - (0x70194))) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)((0x70194) + (pipe) * ((0x71194) - (0x70194)))
7111#define _PLANE_KEYVAL_2(pipe)((0x70294) + (pipe) * ((0x71294) - (0x70294))) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)((0x70294) + (pipe) * ((0x71294) - (0x70294)))
7112#define PLANE_KEYVAL(pipe, plane)((const i915_reg_t){ .reg = (((((0x70194) + (pipe) * ((0x71194
) - (0x70194)))) + (plane) * ((((0x70294) + (pipe) * ((0x71294
) - (0x70294)))) - (((0x70194) + (pipe) * ((0x71194) - (0x70194
))))))) }) \
7113 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))((const i915_reg_t){ .reg = (((((0x70194) + (pipe) * ((0x71194
) - (0x70194)))) + (plane) * ((((0x70294) + (pipe) * ((0x71294
) - (0x70294)))) - (((0x70194) + (pipe) * ((0x71194) - (0x70194
))))))) })
7114
7115#define _PLANE_KEYMSK_1_B0x71198 0x71198
7116#define _PLANE_KEYMSK_2_B0x71298 0x71298
7117#define _PLANE_KEYMSK_1(pipe)((0x70198) + (pipe) * ((0x71198) - (0x70198))) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)((0x70198) + (pipe) * ((0x71198) - (0x70198)))
7118#define _PLANE_KEYMSK_2(pipe)((0x70298) + (pipe) * ((0x71298) - (0x70298))) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)((0x70298) + (pipe) * ((0x71298) - (0x70298)))
7119#define PLANE_KEYMSK(pipe, plane)((const i915_reg_t){ .reg = (((((0x70198) + (pipe) * ((0x71198
) - (0x70198)))) + (plane) * ((((0x70298) + (pipe) * ((0x71298
) - (0x70298)))) - (((0x70198) + (pipe) * ((0x71198) - (0x70198
))))))) }) \
7120 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))((const i915_reg_t){ .reg = (((((0x70198) + (pipe) * ((0x71198
) - (0x70198)))) + (plane) * ((((0x70298) + (pipe) * ((0x71298
) - (0x70298)))) - (((0x70198) + (pipe) * ((0x71198) - (0x70198
))))))) })
7121
7122#define _PLANE_KEYMAX_1_B0x711a0 0x711a0
7123#define _PLANE_KEYMAX_2_B0x712a0 0x712a0
7124#define _PLANE_KEYMAX_1(pipe)((0x701a0) + (pipe) * ((0x711a0) - (0x701a0))) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)((0x701a0) + (pipe) * ((0x711a0) - (0x701a0)))
7125#define _PLANE_KEYMAX_2(pipe)((0x702a0) + (pipe) * ((0x712a0) - (0x702a0))) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)((0x702a0) + (pipe) * ((0x712a0) - (0x702a0)))
7126#define PLANE_KEYMAX(pipe, plane)((const i915_reg_t){ .reg = (((((0x701a0) + (pipe) * ((0x711a0
) - (0x701a0)))) + (plane) * ((((0x702a0) + (pipe) * ((0x712a0
) - (0x702a0)))) - (((0x701a0) + (pipe) * ((0x711a0) - (0x701a0
))))))) }) \
7127 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))((const i915_reg_t){ .reg = (((((0x701a0) + (pipe) * ((0x711a0
) - (0x701a0)))) + (plane) * ((((0x702a0) + (pipe) * ((0x712a0
) - (0x702a0)))) - (((0x701a0) + (pipe) * ((0x711a0) - (0x701a0
))))))) })
7128
7129#define _PLANE_BUF_CFG_1_B0x7127c 0x7127c
7130#define _PLANE_BUF_CFG_2_B0x7137c 0x7137c
7131#define DDB_ENTRY_MASK0x7FF 0x7FF /* skl+: 10 bits, icl+ 11 bits */
7132#define DDB_ENTRY_END_SHIFT16 16
7133#define _PLANE_BUF_CFG_1(pipe)((0x7027c) + (pipe) * ((0x7127c) - (0x7027c))) \
7134 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)((0x7027c) + (pipe) * ((0x7127c) - (0x7027c)))
7135#define _PLANE_BUF_CFG_2(pipe)((0x7037c) + (pipe) * ((0x7137c) - (0x7037c))) \
7136 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)((0x7037c) + (pipe) * ((0x7137c) - (0x7037c)))
7137#define PLANE_BUF_CFG(pipe, plane)((const i915_reg_t){ .reg = (((((0x7027c) + (pipe) * ((0x7127c
) - (0x7027c)))) + (plane) * ((((0x7037c) + (pipe) * ((0x7137c
) - (0x7037c)))) - (((0x7027c) + (pipe) * ((0x7127c) - (0x7027c
))))))) }) \
7138 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))((const i915_reg_t){ .reg = (((((0x7027c) + (pipe) * ((0x7127c
) - (0x7027c)))) + (plane) * ((((0x7037c) + (pipe) * ((0x7137c
) - (0x7037c)))) - (((0x7027c) + (pipe) * ((0x7127c) - (0x7027c
))))))) })
7139
7140#define _PLANE_NV12_BUF_CFG_1_B0x71278 0x71278
7141#define _PLANE_NV12_BUF_CFG_2_B0x71378 0x71378
7142#define _PLANE_NV12_BUF_CFG_1(pipe)((0x70278) + (pipe) * ((0x71278) - (0x70278))) \
7143 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)((0x70278) + (pipe) * ((0x71278) - (0x70278)))
7144#define _PLANE_NV12_BUF_CFG_2(pipe)((0x70378) + (pipe) * ((0x71378) - (0x70378))) \
7145 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)((0x70378) + (pipe) * ((0x71378) - (0x70378)))
7146#define PLANE_NV12_BUF_CFG(pipe, plane)((const i915_reg_t){ .reg = (((((0x70278) + (pipe) * ((0x71278
) - (0x70278)))) + (plane) * ((((0x70378) + (pipe) * ((0x71378
) - (0x70378)))) - (((0x70278) + (pipe) * ((0x71278) - (0x70278
))))))) }) \
7147 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))((const i915_reg_t){ .reg = (((((0x70278) + (pipe) * ((0x71278
) - (0x70278)))) + (plane) * ((((0x70378) + (pipe) * ((0x71378
) - (0x70378)))) - (((0x70278) + (pipe) * ((0x71278) - (0x70278
))))))) })
7148
7149#define _PLANE_AUX_DIST_1_B0x711c0 0x711c0
7150#define _PLANE_AUX_DIST_2_B0x712c0 0x712c0
7151#define _PLANE_AUX_DIST_1(pipe)((0x701c0) + (pipe) * ((0x711c0) - (0x701c0))) \
7152 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)((0x701c0) + (pipe) * ((0x711c0) - (0x701c0)))
7153#define _PLANE_AUX_DIST_2(pipe)((0x702c0) + (pipe) * ((0x712c0) - (0x702c0))) \
7154 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)((0x702c0) + (pipe) * ((0x712c0) - (0x702c0)))
7155#define PLANE_AUX_DIST(pipe, plane)((const i915_reg_t){ .reg = (((((0x701c0) + (pipe) * ((0x711c0
) - (0x701c0)))) + (plane) * ((((0x702c0) + (pipe) * ((0x712c0
) - (0x702c0)))) - (((0x701c0) + (pipe) * ((0x711c0) - (0x701c0
))))))) }) \
7156 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))((const i915_reg_t){ .reg = (((((0x701c0) + (pipe) * ((0x711c0
) - (0x701c0)))) + (plane) * ((((0x702c0) + (pipe) * ((0x712c0
) - (0x702c0)))) - (((0x701c0) + (pipe) * ((0x711c0) - (0x701c0
))))))) })
7157
7158#define _PLANE_AUX_OFFSET_1_B0x711c4 0x711c4
7159#define _PLANE_AUX_OFFSET_2_B0x712c4 0x712c4
7160#define _PLANE_AUX_OFFSET_1(pipe)((0x701c4) + (pipe) * ((0x711c4) - (0x701c4))) \
7161 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)((0x701c4) + (pipe) * ((0x711c4) - (0x701c4)))
7162#define _PLANE_AUX_OFFSET_2(pipe)((0x702c4) + (pipe) * ((0x712c4) - (0x702c4))) \
7163 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)((0x702c4) + (pipe) * ((0x712c4) - (0x702c4)))
7164#define PLANE_AUX_OFFSET(pipe, plane)((const i915_reg_t){ .reg = (((((0x701c4) + (pipe) * ((0x711c4
) - (0x701c4)))) + (plane) * ((((0x702c4) + (pipe) * ((0x712c4
) - (0x702c4)))) - (((0x701c4) + (pipe) * ((0x711c4) - (0x701c4
))))))) }) \
7165 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))((const i915_reg_t){ .reg = (((((0x701c4) + (pipe) * ((0x711c4
) - (0x701c4)))) + (plane) * ((((0x702c4) + (pipe) * ((0x712c4
) - (0x702c4)))) - (((0x701c4) + (pipe) * ((0x711c4) - (0x701c4
))))))) })
7166
7167#define _PLANE_CUS_CTL_1_B0x711c8 0x711c8
7168#define _PLANE_CUS_CTL_2_B0x712c8 0x712c8
7169#define _PLANE_CUS_CTL_1(pipe)((0x701c8) + (pipe) * ((0x711c8) - (0x701c8))) \
7170 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)((0x701c8) + (pipe) * ((0x711c8) - (0x701c8)))
7171#define _PLANE_CUS_CTL_2(pipe)((0x702c8) + (pipe) * ((0x712c8) - (0x702c8))) \
7172 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)((0x702c8) + (pipe) * ((0x712c8) - (0x702c8)))
7173#define PLANE_CUS_CTL(pipe, plane)((const i915_reg_t){ .reg = (((((0x701c8) + (pipe) * ((0x711c8
) - (0x701c8)))) + (plane) * ((((0x702c8) + (pipe) * ((0x712c8
) - (0x702c8)))) - (((0x701c8) + (pipe) * ((0x711c8) - (0x701c8
))))))) }) \
7174 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))((const i915_reg_t){ .reg = (((((0x701c8) + (pipe) * ((0x711c8
) - (0x701c8)))) + (plane) * ((((0x702c8) + (pipe) * ((0x712c8
) - (0x702c8)))) - (((0x701c8) + (pipe) * ((0x711c8) - (0x701c8
))))))) })
7175
7176#define _PLANE_COLOR_CTL_1_B0x711CC 0x711CC
7177#define _PLANE_COLOR_CTL_2_B0x712CC 0x712CC
7178#define _PLANE_COLOR_CTL_3_B0x713CC 0x713CC
7179#define _PLANE_COLOR_CTL_1(pipe)((0x701CC) + (pipe) * ((0x711CC) - (0x701CC))) \
7180 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)((0x701CC) + (pipe) * ((0x711CC) - (0x701CC)))
7181#define _PLANE_COLOR_CTL_2(pipe)((0x702CC) + (pipe) * ((0x712CC) - (0x702CC))) \
7182 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)((0x702CC) + (pipe) * ((0x712CC) - (0x702CC)))
7183#define PLANE_COLOR_CTL(pipe, plane)((const i915_reg_t){ .reg = (((((0x701CC) + (pipe) * ((0x711CC
) - (0x701CC)))) + (plane) * ((((0x702CC) + (pipe) * ((0x712CC
) - (0x702CC)))) - (((0x701CC) + (pipe) * ((0x711CC) - (0x701CC
))))))) }) \
7184 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))((const i915_reg_t){ .reg = (((((0x701CC) + (pipe) * ((0x711CC
) - (0x701CC)))) + (plane) * ((((0x702CC) + (pipe) * ((0x712CC
) - (0x702CC)))) - (((0x701CC) + (pipe) * ((0x711CC) - (0x701CC
))))))) })
7185
7186#define _SEL_FETCH_PLANE_BASE_1_A0x70890 0x70890
7187#define _SEL_FETCH_PLANE_BASE_2_A0x708B0 0x708B0
7188#define _SEL_FETCH_PLANE_BASE_3_A0x708D0 0x708D0
7189#define _SEL_FETCH_PLANE_BASE_4_A0x708F0 0x708F0
7190#define _SEL_FETCH_PLANE_BASE_5_A0x70920 0x70920
7191#define _SEL_FETCH_PLANE_BASE_6_A0x70940 0x70940
7192#define _SEL_FETCH_PLANE_BASE_7_A0x70960 0x70960
7193#define _SEL_FETCH_PLANE_BASE_CUR_A0x70880 0x70880
7194#define _SEL_FETCH_PLANE_BASE_1_B0x70990 0x70990
7195
7196#define _SEL_FETCH_PLANE_BASE_A(plane)(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane]) _PICK(plane, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7197 _SEL_FETCH_PLANE_BASE_1_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7198 _SEL_FETCH_PLANE_BASE_2_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7199 _SEL_FETCH_PLANE_BASE_3_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7200 _SEL_FETCH_PLANE_BASE_4_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7201 _SEL_FETCH_PLANE_BASE_5_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7202 _SEL_FETCH_PLANE_BASE_6_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7203 _SEL_FETCH_PLANE_BASE_7_A, \(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7204 _SEL_FETCH_PLANE_BASE_CUR_A)(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane])
7205#define _SEL_FETCH_PLANE_BASE_1(pipe)((0x70890) + (pipe) * ((0x70990) - (0x70890))) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)((0x70890) + (pipe) * ((0x70990) - (0x70890)))
7206#define _SEL_FETCH_PLANE_BASE(pipe, plane)(((0x70890) + (pipe) * ((0x70990) - (0x70890))) - 0x70890 + (
((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920,
0x70940, 0x70960, 0x70880 })[plane])) (_SEL_FETCH_PLANE_BASE_1(pipe)((0x70890) + (pipe) * ((0x70990) - (0x70890))) - \
7207 _SEL_FETCH_PLANE_BASE_1_A0x70890 + \
7208 _SEL_FETCH_PLANE_BASE_A(plane)(((const u32 []){ 0x70890, 0x708B0, 0x708D0, 0x708F0, 0x70920
, 0x70940, 0x70960, 0x70880 })[plane]))
7209
7210#define _SEL_FETCH_PLANE_CTL_1_A0x70890 0x70890
7211#define PLANE_SEL_FETCH_CTL(pipe, plane)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70890 - 0x70890) }) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70890 - 0x70890) })
7212 _SEL_FETCH_PLANE_CTL_1_A - \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70890 - 0x70890) })
7213 _SEL_FETCH_PLANE_BASE_1_A)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70890 - 0x70890) })
7214#define PLANE_SEL_FETCH_CTL_ENABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
7215
7216#define _SEL_FETCH_PLANE_POS_1_A0x70894 0x70894
7217#define PLANE_SEL_FETCH_POS(pipe, plane)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70894 - 0x70890) }) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70894 - 0x70890) })
7218 _SEL_FETCH_PLANE_POS_1_A - \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70894 - 0x70890) })
7219 _SEL_FETCH_PLANE_BASE_1_A)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70894 - 0x70890) })
7220
7221#define _SEL_FETCH_PLANE_SIZE_1_A0x70898 0x70898
7222#define PLANE_SEL_FETCH_SIZE(pipe, plane)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70898 - 0x70890) }) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70898 - 0x70890) })
7223 _SEL_FETCH_PLANE_SIZE_1_A - \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70898 - 0x70890) })
7224 _SEL_FETCH_PLANE_BASE_1_A)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x70898 - 0x70890) })
7225
7226#define _SEL_FETCH_PLANE_OFFSET_1_A0x7089C 0x7089C
7227#define PLANE_SEL_FETCH_OFFSET(pipe, plane)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x7089C - 0x70890) }) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x7089C - 0x70890) })
7228 _SEL_FETCH_PLANE_OFFSET_1_A - \((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x7089C - 0x70890) })
7229 _SEL_FETCH_PLANE_BASE_1_A)((const i915_reg_t){ .reg = ((((0x70890) + (pipe) * ((0x70990
) - (0x70890))) - 0x70890 + (((const u32 []){ 0x70890, 0x708B0
, 0x708D0, 0x708F0, 0x70920, 0x70940, 0x70960, 0x70880 })[plane
])) + 0x7089C - 0x70890) })
7230
7231/* SKL new cursor registers */
7232#define _CUR_BUF_CFG_A0x7017c 0x7017c
7233#define _CUR_BUF_CFG_B0x7117c 0x7117c
7234#define CUR_BUF_CFG(pipe)((const i915_reg_t){ .reg = (((0x7017c) + (pipe) * ((0x7117c)
- (0x7017c)))) }) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)((const i915_reg_t){ .reg = (((0x7017c) + (pipe) * ((0x7117c)
- (0x7017c)))) })
7235
7236/* VBIOS regs */
7237#define VGACNTRL((const i915_reg_t){ .reg = (0x71400) }) _MMIO(0x71400)((const i915_reg_t){ .reg = (0x71400) })
7238# define VGA_DISP_DISABLE(1 << 31) (1 << 31)
7239# define VGA_2X_MODE(1 << 30) (1 << 30)
7240# define VGA_PIPE_B_SELECT(1 << 29) (1 << 29)
7241
7242#define VLV_VGACNTRL((const i915_reg_t){ .reg = (0x180000 + 0x71400) }) _MMIO(VLV_DISPLAY_BASE + 0x71400)((const i915_reg_t){ .reg = (0x180000 + 0x71400) })
7243
7244/* Ironlake */
7245
7246#define CPU_VGACNTRL((const i915_reg_t){ .reg = (0x41000) }) _MMIO(0x41000)((const i915_reg_t){ .reg = (0x41000) })
7247
7248#define DIGITAL_PORT_HOTPLUG_CNTRL((const i915_reg_t){ .reg = (0x44030) }) _MMIO(0x44030)((const i915_reg_t){ .reg = (0x44030) })
7249#define DIGITAL_PORTA_HOTPLUG_ENABLE(1 << 4) (1 << 4)
7250#define DIGITAL_PORTA_PULSE_DURATION_2ms(0 << 2) (0 << 2) /* pre-HSW */
7251#define DIGITAL_PORTA_PULSE_DURATION_4_5ms(1 << 2) (1 << 2) /* pre-HSW */
7252#define DIGITAL_PORTA_PULSE_DURATION_6ms(2 << 2) (2 << 2) /* pre-HSW */
7253#define DIGITAL_PORTA_PULSE_DURATION_100ms(3 << 2) (3 << 2) /* pre-HSW */
7254#define DIGITAL_PORTA_PULSE_DURATION_MASK(3 << 2) (3 << 2) /* pre-HSW */
7255#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK(3 << 0) (3 << 0)
7256#define DIGITAL_PORTA_HOTPLUG_NO_DETECT(0 << 0) (0 << 0)
7257#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT(1 << 0) (1 << 0)
7258#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT(2 << 0) (2 << 0)
7259
7260/* refresh rate hardware control */
7261#define RR_HW_CTL((const i915_reg_t){ .reg = (0x45300) }) _MMIO(0x45300)((const i915_reg_t){ .reg = (0x45300) })
7262#define RR_HW_LOW_POWER_FRAMES_MASK0xff 0xff
7263#define RR_HW_HIGH_POWER_FRAMES_MASK0xff00 0xff00
7264
7265#define FDI_PLL_BIOS_0((const i915_reg_t){ .reg = (0x46000) }) _MMIO(0x46000)((const i915_reg_t){ .reg = (0x46000) })
7266#define FDI_PLL_FB_CLOCK_MASK0xff 0xff
7267#define FDI_PLL_BIOS_1((const i915_reg_t){ .reg = (0x46004) }) _MMIO(0x46004)((const i915_reg_t){ .reg = (0x46004) })
7268#define FDI_PLL_BIOS_2((const i915_reg_t){ .reg = (0x46008) }) _MMIO(0x46008)((const i915_reg_t){ .reg = (0x46008) })
7269#define DISPLAY_PORT_PLL_BIOS_0((const i915_reg_t){ .reg = (0x4600c) }) _MMIO(0x4600c)((const i915_reg_t){ .reg = (0x4600c) })
7270#define DISPLAY_PORT_PLL_BIOS_1((const i915_reg_t){ .reg = (0x46010) }) _MMIO(0x46010)((const i915_reg_t){ .reg = (0x46010) })
7271#define DISPLAY_PORT_PLL_BIOS_2((const i915_reg_t){ .reg = (0x46014) }) _MMIO(0x46014)((const i915_reg_t){ .reg = (0x46014) })
7272
7273#define PCH_3DCGDIS0((const i915_reg_t){ .reg = (0x46020) }) _MMIO(0x46020)((const i915_reg_t){ .reg = (0x46020) })
7274# define MARIUNIT_CLOCK_GATE_DISABLE(1 << 18) (1 << 18)
7275# define SVSMUNIT_CLOCK_GATE_DISABLE(1 << 1) (1 << 1)
7276
7277#define PCH_3DCGDIS1((const i915_reg_t){ .reg = (0x46024) }) _MMIO(0x46024)((const i915_reg_t){ .reg = (0x46024) })
7278# define VFMUNIT_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
7279
7280#define FDI_PLL_FREQ_CTL((const i915_reg_t){ .reg = (0x46030) }) _MMIO(0x46030)((const i915_reg_t){ .reg = (0x46030) })
7281#define FDI_PLL_FREQ_CHANGE_REQUEST(1 << 24) (1 << 24)
7282#define FDI_PLL_FREQ_LOCK_LIMIT_MASK0xfff00 0xfff00
7283#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK0xff 0xff
7284
7285
7286#define _PIPEA_DATA_M10x60030 0x60030
7287#define PIPE_DATA_M1_OFFSET0 0
7288#define _PIPEA_DATA_N10x60034 0x60034
7289#define PIPE_DATA_N1_OFFSET0 0
7290
7291#define _PIPEA_DATA_M20x60038 0x60038
7292#define PIPE_DATA_M2_OFFSET0 0
7293#define _PIPEA_DATA_N20x6003c 0x6003c
7294#define PIPE_DATA_N2_OFFSET0 0
7295
7296#define _PIPEA_LINK_M10x60040 0x60040
7297#define PIPE_LINK_M1_OFFSET0 0
7298#define _PIPEA_LINK_N10x60044 0x60044
7299#define PIPE_LINK_N1_OFFSET0 0
7300
7301#define _PIPEA_LINK_M20x60048 0x60048
7302#define PIPE_LINK_M2_OFFSET0 0
7303#define _PIPEA_LINK_N20x6004c 0x6004c
7304#define PIPE_LINK_N2_OFFSET0 0
7305
7306/* PIPEB timing regs are same start from 0x61000 */
7307
7308#define _PIPEB_DATA_M10x61030 0x61030
7309#define _PIPEB_DATA_N10x61034 0x61034
7310#define _PIPEB_DATA_M20x61038 0x61038
7311#define _PIPEB_DATA_N20x6103c 0x6103c
7312#define _PIPEB_LINK_M10x61040 0x61040
7313#define _PIPEB_LINK_N10x61044 0x61044
7314#define _PIPEB_LINK_M20x61048 0x61048
7315#define _PIPEB_LINK_N20x6104c 0x6104c
7316
7317#define PIPE_DATA_M1(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60030) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60030) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7318#define PIPE_DATA_N1(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60034) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60034) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7319#define PIPE_DATA_M2(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60038) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60038) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7320#define PIPE_DATA_N2(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6003c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6003c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7321#define PIPE_LINK_M1(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60040) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60040) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7322#define PIPE_LINK_N1(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60044) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60044) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7323#define PIPE_LINK_M2(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60048) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60048) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7324#define PIPE_LINK_N2(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6004c) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x6004c) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
7325
7326/* CPU panel fitter */
7327/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7328#define _PFA_CTL_10x68080 0x68080
7329#define _PFB_CTL_10x68880 0x68880
7330#define PF_ENABLE(1 << 31) (1 << 31)
7331#define PF_PIPE_SEL_MASK_IVB(3 << 29) (3 << 29)
7332#define PF_PIPE_SEL_IVB(pipe)((pipe) << 29) ((pipe) << 29)
7333#define PF_FILTER_MASK(3 << 23) (3 << 23)
7334#define PF_FILTER_PROGRAMMED(0 << 23) (0 << 23)
7335#define PF_FILTER_MED_3x3(1 << 23) (1 << 23)
7336#define PF_FILTER_EDGE_ENHANCE(2 << 23) (2 << 23)
7337#define PF_FILTER_EDGE_SOFTEN(3 << 23) (3 << 23)
7338#define _PFA_WIN_SZ0x68074 0x68074
7339#define _PFB_WIN_SZ0x68874 0x68874
7340#define _PFA_WIN_POS0x68070 0x68070
7341#define _PFB_WIN_POS0x68870 0x68870
7342#define _PFA_VSCALE0x68084 0x68084
7343#define _PFB_VSCALE0x68884 0x68884
7344#define _PFA_HSCALE0x68090 0x68090
7345#define _PFB_HSCALE0x68890 0x68890
7346
7347#define PF_CTL(pipe)((const i915_reg_t){ .reg = (((0x68080) + (pipe) * ((0x68880)
- (0x68080)))) }) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)((const i915_reg_t){ .reg = (((0x68080) + (pipe) * ((0x68880)
- (0x68080)))) })
7348#define PF_WIN_SZ(pipe)((const i915_reg_t){ .reg = (((0x68074) + (pipe) * ((0x68874)
- (0x68074)))) }) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)((const i915_reg_t){ .reg = (((0x68074) + (pipe) * ((0x68874)
- (0x68074)))) })
7349#define PF_WIN_POS(pipe)((const i915_reg_t){ .reg = (((0x68070) + (pipe) * ((0x68870)
- (0x68070)))) }) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)((const i915_reg_t){ .reg = (((0x68070) + (pipe) * ((0x68870)
- (0x68070)))) })
7350#define PF_VSCALE(pipe)((const i915_reg_t){ .reg = (((0x68084) + (pipe) * ((0x68884)
- (0x68084)))) }) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)((const i915_reg_t){ .reg = (((0x68084) + (pipe) * ((0x68884)
- (0x68084)))) })
7351#define PF_HSCALE(pipe)((const i915_reg_t){ .reg = (((0x68090) + (pipe) * ((0x68890)
- (0x68090)))) }) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)((const i915_reg_t){ .reg = (((0x68090) + (pipe) * ((0x68890)
- (0x68090)))) })
7352
7353#define _PSA_CTL0x68180 0x68180
7354#define _PSB_CTL0x68980 0x68980
7355#define PS_ENABLE(1 << 31) (1 << 31)
7356#define _PSA_WIN_SZ0x68174 0x68174
7357#define _PSB_WIN_SZ0x68974 0x68974
7358#define _PSA_WIN_POS0x68170 0x68170
7359#define _PSB_WIN_POS0x68970 0x68970
7360
7361#define PS_CTL(pipe)((const i915_reg_t){ .reg = (((0x68180) + (pipe) * ((0x68980)
- (0x68180)))) }) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)((const i915_reg_t){ .reg = (((0x68180) + (pipe) * ((0x68980)
- (0x68180)))) })
7362#define PS_WIN_SZ(pipe)((const i915_reg_t){ .reg = (((0x68174) + (pipe) * ((0x68974)
- (0x68174)))) }) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)((const i915_reg_t){ .reg = (((0x68174) + (pipe) * ((0x68974)
- (0x68174)))) })
7363#define PS_WIN_POS(pipe)((const i915_reg_t){ .reg = (((0x68170) + (pipe) * ((0x68970)
- (0x68170)))) }) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)((const i915_reg_t){ .reg = (((0x68170) + (pipe) * ((0x68970)
- (0x68170)))) })
7364
7365/*
7366 * Skylake scalers
7367 */
7368#define _PS_1A_CTRL0x68180 0x68180
7369#define _PS_2A_CTRL0x68280 0x68280
7370#define _PS_1B_CTRL0x68980 0x68980
7371#define _PS_2B_CTRL0x68A80 0x68A80
7372#define _PS_1C_CTRL0x69180 0x69180
7373#define PS_SCALER_EN(1 << 31) (1 << 31)
7374#define SKL_PS_SCALER_MODE_MASK(3 << 28) (3 << 28)
7375#define SKL_PS_SCALER_MODE_DYN(0 << 28) (0 << 28)
7376#define SKL_PS_SCALER_MODE_HQ(1 << 28) (1 << 28)
7377#define SKL_PS_SCALER_MODE_NV12(2 << 28) (2 << 28)
7378#define PS_SCALER_MODE_PLANAR(1 << 29) (1 << 29)
7379#define PS_SCALER_MODE_NORMAL(0 << 29) (0 << 29)
7380#define PS_PLANE_SEL_MASK(7 << 25) (7 << 25)
7381#define PS_PLANE_SEL(plane)(((plane) + 1) << 25) (((plane) + 1) << 25)
7382#define PS_FILTER_MASK(3 << 23) (3 << 23)
7383#define PS_FILTER_MEDIUM(0 << 23) (0 << 23)
7384#define PS_FILTER_EDGE_ENHANCE(2 << 23) (2 << 23)
7385#define PS_FILTER_BILINEAR(3 << 23) (3 << 23)
7386#define PS_VERT3TAP(1 << 21) (1 << 21)
7387#define PS_VERT_INT_INVERT_FIELD1(0 << 20) (0 << 20)
7388#define PS_VERT_INT_INVERT_FIELD0(1 << 20) (1 << 20)
7389#define PS_PWRUP_PROGRESS(1 << 17) (1 << 17)
7390#define PS_V_FILTER_BYPASS(1 << 8) (1 << 8)
7391#define PS_VADAPT_EN(1 << 7) (1 << 7)
7392#define PS_VADAPT_MODE_MASK(3 << 5) (3 << 5)
7393#define PS_VADAPT_MODE_LEAST_ADAPT(0 << 5) (0 << 5)
7394#define PS_VADAPT_MODE_MOD_ADAPT(1 << 5) (1 << 5)
7395#define PS_VADAPT_MODE_MOST_ADAPT(3 << 5) (3 << 5)
7396#define PS_PLANE_Y_SEL_MASK(7 << 5) (7 << 5)
7397#define PS_PLANE_Y_SEL(plane)(((plane) + 1) << 5) (((plane) + 1) << 5)
7398
7399#define _PS_PWR_GATE_1A0x68160 0x68160
7400#define _PS_PWR_GATE_2A0x68260 0x68260
7401#define _PS_PWR_GATE_1B0x68960 0x68960
7402#define _PS_PWR_GATE_2B0x68A60 0x68A60
7403#define _PS_PWR_GATE_1C0x69160 0x69160
7404#define PS_PWR_GATE_DIS_OVERRIDE(1 << 31) (1 << 31)
7405#define PS_PWR_GATE_SETTLING_TIME_32(0 << 3) (0 << 3)
7406#define PS_PWR_GATE_SETTLING_TIME_64(1 << 3) (1 << 3)
7407#define PS_PWR_GATE_SETTLING_TIME_96(2 << 3) (2 << 3)
7408#define PS_PWR_GATE_SETTLING_TIME_128(3 << 3) (3 << 3)
7409#define PS_PWR_GATE_SLPEN_80 0
7410#define PS_PWR_GATE_SLPEN_161 1
7411#define PS_PWR_GATE_SLPEN_242 2
7412#define PS_PWR_GATE_SLPEN_323 3
7413
7414#define _PS_WIN_POS_1A0x68170 0x68170
7415#define _PS_WIN_POS_2A0x68270 0x68270
7416#define _PS_WIN_POS_1B0x68970 0x68970
7417#define _PS_WIN_POS_2B0x68A70 0x68A70
7418#define _PS_WIN_POS_1C0x69170 0x69170
7419
7420#define _PS_WIN_SZ_1A0x68174 0x68174
7421#define _PS_WIN_SZ_2A0x68274 0x68274
7422#define _PS_WIN_SZ_1B0x68974 0x68974
7423#define _PS_WIN_SZ_2B0x68A74 0x68A74
7424#define _PS_WIN_SZ_1C0x69174 0x69174
7425
7426#define _PS_VSCALE_1A0x68184 0x68184
7427#define _PS_VSCALE_2A0x68284 0x68284
7428#define _PS_VSCALE_1B0x68984 0x68984
7429#define _PS_VSCALE_2B0x68A84 0x68A84
7430#define _PS_VSCALE_1C0x69184 0x69184
7431
7432#define _PS_HSCALE_1A0x68190 0x68190
7433#define _PS_HSCALE_2A0x68290 0x68290
7434#define _PS_HSCALE_1B0x68990 0x68990
7435#define _PS_HSCALE_2B0x68A90 0x68A90
7436#define _PS_HSCALE_1C0x69190 0x69190
7437
7438#define _PS_VPHASE_1A0x68188 0x68188
7439#define _PS_VPHASE_2A0x68288 0x68288
7440#define _PS_VPHASE_1B0x68988 0x68988
7441#define _PS_VPHASE_2B0x68A88 0x68A88
7442#define _PS_VPHASE_1C0x69188 0x69188
7443#define PS_Y_PHASE(x)((x) << 16) ((x) << 16)
7444#define PS_UV_RGB_PHASE(x)((x) << 0) ((x) << 0)
7445#define PS_PHASE_MASK(0x7fff << 1) (0x7fff << 1) /* u2.13 */
7446#define PS_PHASE_TRIP(1 << 0) (1 << 0)
7447
7448#define _PS_HPHASE_1A0x68194 0x68194
7449#define _PS_HPHASE_2A0x68294 0x68294
7450#define _PS_HPHASE_1B0x68994 0x68994
7451#define _PS_HPHASE_2B0x68A94 0x68A94
7452#define _PS_HPHASE_1C0x69194 0x69194
7453
7454#define _PS_ECC_STAT_1A0x681D0 0x681D0
7455#define _PS_ECC_STAT_2A0x682D0 0x682D0
7456#define _PS_ECC_STAT_1B0x689D0 0x689D0
7457#define _PS_ECC_STAT_2B0x68AD0 0x68AD0
7458#define _PS_ECC_STAT_1C0x691D0 0x691D0
7459
7460#define _ID(id, a, b)((a) + (id) * ((b) - (a))) _PICK_EVEN(id, a, b)((a) + (id) * ((b) - (a)))
7461#define SKL_PS_CTRL(pipe, id)((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280)
- (0x68180)))) + (pipe) * ((((0x68980) + (id) * ((0x68A80) -
(0x68980)))) - (((0x68180) + (id) * ((0x68280) - (0x68180)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280)
- (0x68180)))) + (pipe) * ((((0x68980) + (id) * ((0x68A80) -
(0x68980)))) - (((0x68180) + (id) * ((0x68280) - (0x68180)))
)))) })
7462 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280)
- (0x68180)))) + (pipe) * ((((0x68980) + (id) * ((0x68A80) -
(0x68980)))) - (((0x68180) + (id) * ((0x68280) - (0x68180)))
)))) })
7463 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280)
- (0x68180)))) + (pipe) * ((((0x68980) + (id) * ((0x68A80) -
(0x68980)))) - (((0x68180) + (id) * ((0x68280) - (0x68180)))
)))) })
7464#define SKL_PS_PWR_GATE(pipe, id)((const i915_reg_t){ .reg = (((((0x68160) + (id) * ((0x68260)
- (0x68160)))) + (pipe) * ((((0x68960) + (id) * ((0x68A60) -
(0x68960)))) - (((0x68160) + (id) * ((0x68260) - (0x68160)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68160) + (id) * ((0x68260)
- (0x68160)))) + (pipe) * ((((0x68960) + (id) * ((0x68A60) -
(0x68960)))) - (((0x68160) + (id) * ((0x68260) - (0x68160)))
)))) })
7465 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \((const i915_reg_t){ .reg = (((((0x68160) + (id) * ((0x68260)
- (0x68160)))) + (pipe) * ((((0x68960) + (id) * ((0x68A60) -
(0x68960)))) - (((0x68160) + (id) * ((0x68260) - (0x68160)))
)))) })
7466 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))((const i915_reg_t){ .reg = (((((0x68160) + (id) * ((0x68260)
- (0x68160)))) + (pipe) * ((((0x68960) + (id) * ((0x68A60) -
(0x68960)))) - (((0x68160) + (id) * ((0x68260) - (0x68160)))
)))) })
7467#define SKL_PS_WIN_POS(pipe, id)((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270)
- (0x68170)))) + (pipe) * ((((0x68970) + (id) * ((0x68A70) -
(0x68970)))) - (((0x68170) + (id) * ((0x68270) - (0x68170)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270)
- (0x68170)))) + (pipe) * ((((0x68970) + (id) * ((0x68A70) -
(0x68970)))) - (((0x68170) + (id) * ((0x68270) - (0x68170)))
)))) })
7468 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270)
- (0x68170)))) + (pipe) * ((((0x68970) + (id) * ((0x68A70) -
(0x68970)))) - (((0x68170) + (id) * ((0x68270) - (0x68170)))
)))) })
7469 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270)
- (0x68170)))) + (pipe) * ((((0x68970) + (id) * ((0x68A70) -
(0x68970)))) - (((0x68170) + (id) * ((0x68270) - (0x68170)))
)))) })
7470#define SKL_PS_WIN_SZ(pipe, id)((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274)
- (0x68174)))) + (pipe) * ((((0x68974) + (id) * ((0x68A74) -
(0x68974)))) - (((0x68174) + (id) * ((0x68274) - (0x68174)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274)
- (0x68174)))) + (pipe) * ((((0x68974) + (id) * ((0x68A74) -
(0x68974)))) - (((0x68174) + (id) * ((0x68274) - (0x68174)))
)))) })
7471 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274)
- (0x68174)))) + (pipe) * ((((0x68974) + (id) * ((0x68A74) -
(0x68974)))) - (((0x68174) + (id) * ((0x68274) - (0x68174)))
)))) })
7472 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274)
- (0x68174)))) + (pipe) * ((((0x68974) + (id) * ((0x68A74) -
(0x68974)))) - (((0x68174) + (id) * ((0x68274) - (0x68174)))
)))) })
7473#define SKL_PS_VSCALE(pipe, id)((const i915_reg_t){ .reg = (((((0x68184) + (id) * ((0x68284)
- (0x68184)))) + (pipe) * ((((0x68984) + (id) * ((0x68A84) -
(0x68984)))) - (((0x68184) + (id) * ((0x68284) - (0x68184)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68184) + (id) * ((0x68284)
- (0x68184)))) + (pipe) * ((((0x68984) + (id) * ((0x68A84) -
(0x68984)))) - (((0x68184) + (id) * ((0x68284) - (0x68184)))
)))) })
7474 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \((const i915_reg_t){ .reg = (((((0x68184) + (id) * ((0x68284)
- (0x68184)))) + (pipe) * ((((0x68984) + (id) * ((0x68A84) -
(0x68984)))) - (((0x68184) + (id) * ((0x68284) - (0x68184)))
)))) })
7475 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))((const i915_reg_t){ .reg = (((((0x68184) + (id) * ((0x68284)
- (0x68184)))) + (pipe) * ((((0x68984) + (id) * ((0x68A84) -
(0x68984)))) - (((0x68184) + (id) * ((0x68284) - (0x68184)))
)))) })
7476#define SKL_PS_HSCALE(pipe, id)((const i915_reg_t){ .reg = (((((0x68190) + (id) * ((0x68290)
- (0x68190)))) + (pipe) * ((((0x68990) + (id) * ((0x68A90) -
(0x68990)))) - (((0x68190) + (id) * ((0x68290) - (0x68190)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68190) + (id) * ((0x68290)
- (0x68190)))) + (pipe) * ((((0x68990) + (id) * ((0x68A90) -
(0x68990)))) - (((0x68190) + (id) * ((0x68290) - (0x68190)))
)))) })
7477 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \((const i915_reg_t){ .reg = (((((0x68190) + (id) * ((0x68290)
- (0x68190)))) + (pipe) * ((((0x68990) + (id) * ((0x68A90) -
(0x68990)))) - (((0x68190) + (id) * ((0x68290) - (0x68190)))
)))) })
7478 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))((const i915_reg_t){ .reg = (((((0x68190) + (id) * ((0x68290)
- (0x68190)))) + (pipe) * ((((0x68990) + (id) * ((0x68A90) -
(0x68990)))) - (((0x68190) + (id) * ((0x68290) - (0x68190)))
)))) })
7479#define SKL_PS_VPHASE(pipe, id)((const i915_reg_t){ .reg = (((((0x68188) + (id) * ((0x68288)
- (0x68188)))) + (pipe) * ((((0x68988) + (id) * ((0x68A88) -
(0x68988)))) - (((0x68188) + (id) * ((0x68288) - (0x68188)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68188) + (id) * ((0x68288)
- (0x68188)))) + (pipe) * ((((0x68988) + (id) * ((0x68A88) -
(0x68988)))) - (((0x68188) + (id) * ((0x68288) - (0x68188)))
)))) })
7480 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \((const i915_reg_t){ .reg = (((((0x68188) + (id) * ((0x68288)
- (0x68188)))) + (pipe) * ((((0x68988) + (id) * ((0x68A88) -
(0x68988)))) - (((0x68188) + (id) * ((0x68288) - (0x68188)))
)))) })
7481 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))((const i915_reg_t){ .reg = (((((0x68188) + (id) * ((0x68288)
- (0x68188)))) + (pipe) * ((((0x68988) + (id) * ((0x68A88) -
(0x68988)))) - (((0x68188) + (id) * ((0x68288) - (0x68188)))
)))) })
7482#define SKL_PS_HPHASE(pipe, id)((const i915_reg_t){ .reg = (((((0x68194) + (id) * ((0x68294)
- (0x68194)))) + (pipe) * ((((0x68994) + (id) * ((0x68A94) -
(0x68994)))) - (((0x68194) + (id) * ((0x68294) - (0x68194)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x68194) + (id) * ((0x68294)
- (0x68194)))) + (pipe) * ((((0x68994) + (id) * ((0x68A94) -
(0x68994)))) - (((0x68194) + (id) * ((0x68294) - (0x68194)))
)))) })
7483 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \((const i915_reg_t){ .reg = (((((0x68194) + (id) * ((0x68294)
- (0x68194)))) + (pipe) * ((((0x68994) + (id) * ((0x68A94) -
(0x68994)))) - (((0x68194) + (id) * ((0x68294) - (0x68194)))
)))) })
7484 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))((const i915_reg_t){ .reg = (((((0x68194) + (id) * ((0x68294)
- (0x68194)))) + (pipe) * ((((0x68994) + (id) * ((0x68A94) -
(0x68994)))) - (((0x68194) + (id) * ((0x68294) - (0x68194)))
)))) })
7485#define SKL_PS_ECC_STAT(pipe, id)((const i915_reg_t){ .reg = (((((0x681D0) + (id) * ((0x682D0)
- (0x681D0)))) + (pipe) * ((((0x689D0) + (id) * ((0x68AD0) -
(0x689D0)))) - (((0x681D0) + (id) * ((0x682D0) - (0x681D0)))
)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((((0x681D0) + (id) * ((0x682D0)
- (0x681D0)))) + (pipe) * ((((0x689D0) + (id) * ((0x68AD0) -
(0x689D0)))) - (((0x681D0) + (id) * ((0x682D0) - (0x681D0)))
)))) })
7486 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \((const i915_reg_t){ .reg = (((((0x681D0) + (id) * ((0x682D0)
- (0x681D0)))) + (pipe) * ((((0x689D0) + (id) * ((0x68AD0) -
(0x689D0)))) - (((0x681D0) + (id) * ((0x682D0) - (0x681D0)))
)))) })
7487 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))((const i915_reg_t){ .reg = (((((0x681D0) + (id) * ((0x682D0)
- (0x681D0)))) + (pipe) * ((((0x689D0) + (id) * ((0x68AD0) -
(0x689D0)))) - (((0x681D0) + (id) * ((0x682D0) - (0x681D0)))
)))) })
7488
7489/* legacy palette */
7490#define _LGC_PALETTE_A0x4a000 0x4a000
7491#define _LGC_PALETTE_B0x4a800 0x4a800
7492#define LGC_PALETTE_RED_MASK((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(23, 16)((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))
7493#define LGC_PALETTE_GREEN_MASK((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(8))) + 0)) REG_GENMASK(15, 8)((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(8))) + 0))
7494#define LGC_PALETTE_BLUE_MASK((u32)((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(7, 0)((u32)((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0))) + 0))
7495#define LGC_PALETTE(pipe, i)((const i915_reg_t){ .reg = (((0x4a000) + (pipe) * ((0x4a800)
- (0x4a000))) + (i) * 4) }) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x4a000) + (pipe) * ((0x4a800)
- (0x4a000))) + (i) * 4) })
7496
7497/* ilk/snb precision palette */
7498#define _PREC_PALETTE_A0x4b000 0x4b000
7499#define _PREC_PALETTE_B0x4c000 0x4c000
7500#define PREC_PALETTE_RED_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0)) REG_GENMASK(29, 20)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0))
7501#define PREC_PALETTE_GREEN_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0)) REG_GENMASK(19, 10)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0))
7502#define PREC_PALETTE_BLUE_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(9, 0)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0))
7503#define PREC_PALETTE(pipe, i)((const i915_reg_t){ .reg = (((0x4b000) + (pipe) * ((0x4c000)
- (0x4b000))) + (i) * 4) }) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x4b000) + (pipe) * ((0x4c000)
- (0x4b000))) + (i) * 4) })
7504
7505#define _PREC_PIPEAGCMAX0x4d000 0x4d000
7506#define _PREC_PIPEBGCMAX0x4d010 0x4d010
7507#define PREC_PIPEGCMAX(pipe, i)((const i915_reg_t){ .reg = (((0x70010) + (pipe) * ((0x71010)
- (0x70010))) + (i) * 4) }) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)((const i915_reg_t){ .reg = (((0x70010) + (pipe) * ((0x71010)
- (0x70010))) + (i) * 4) })
7508
7509#define _GAMMA_MODE_A0x4a480 0x4a480
7510#define _GAMMA_MODE_B0x4ac80 0x4ac80
7511#define GAMMA_MODE(pipe)((const i915_reg_t){ .reg = (((0x4a480) + (pipe) * ((0x4ac80)
- (0x4a480)))) }) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)((const i915_reg_t){ .reg = (((0x4a480) + (pipe) * ((0x4ac80)
- (0x4a480)))) })
7512#define PRE_CSC_GAMMA_ENABLE(1 << 31) (1 << 31)
7513#define POST_CSC_GAMMA_ENABLE(1 << 30) (1 << 30)
7514#define GAMMA_MODE_MODE_MASK(3 << 0) (3 << 0)
7515#define GAMMA_MODE_MODE_8BIT(0 << 0) (0 << 0)
7516#define GAMMA_MODE_MODE_10BIT(1 << 0) (1 << 0)
7517#define GAMMA_MODE_MODE_12BIT(2 << 0) (2 << 0)
7518#define GAMMA_MODE_MODE_SPLIT(3 << 0) (3 << 0) /* ivb-bdw */
7519#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED(3 << 0) (3 << 0) /* icl + */
7520
7521/* DMC/CSR */
7522#define CSR_PROGRAM(i)((const i915_reg_t){ .reg = (0x80000 + (i) * 4) }) _MMIO(0x80000 + (i) * 4)((const i915_reg_t){ .reg = (0x80000 + (i) * 4) })
7523#define CSR_SSP_BASE_ADDR_GEN90x00002FC0 0x00002FC0
7524#define CSR_HTP_ADDR_SKL0x00500034 0x00500034
7525#define CSR_SSP_BASE((const i915_reg_t){ .reg = (0x8F074) }) _MMIO(0x8F074)((const i915_reg_t){ .reg = (0x8F074) })
7526#define CSR_HTP_SKL((const i915_reg_t){ .reg = (0x8F004) }) _MMIO(0x8F004)((const i915_reg_t){ .reg = (0x8F004) })
7527#define CSR_LAST_WRITE((const i915_reg_t){ .reg = (0x8F034) }) _MMIO(0x8F034)((const i915_reg_t){ .reg = (0x8F034) })
7528#define CSR_LAST_WRITE_VALUE0xc003b400 0xc003b400
7529/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7530#define CSR_MMIO_START_RANGE0x80000 0x80000
7531#define CSR_MMIO_END_RANGE0x8FFFF 0x8FFFF
7532#define SKL_CSR_DC3_DC5_COUNT((const i915_reg_t){ .reg = (0x80030) }) _MMIO(0x80030)((const i915_reg_t){ .reg = (0x80030) })
7533#define SKL_CSR_DC5_DC6_COUNT((const i915_reg_t){ .reg = (0x8002C) }) _MMIO(0x8002C)((const i915_reg_t){ .reg = (0x8002C) })
7534#define BXT_CSR_DC3_DC5_COUNT((const i915_reg_t){ .reg = (0x80038) }) _MMIO(0x80038)((const i915_reg_t){ .reg = (0x80038) })
7535#define TGL_DMC_DEBUG_DC5_COUNT((const i915_reg_t){ .reg = (0x101084) }) _MMIO(0x101084)((const i915_reg_t){ .reg = (0x101084) })
7536#define TGL_DMC_DEBUG_DC6_COUNT((const i915_reg_t){ .reg = (0x101088) }) _MMIO(0x101088)((const i915_reg_t){ .reg = (0x101088) })
7537
7538#define DMC_DEBUG3((const i915_reg_t){ .reg = (0x101090) }) _MMIO(0x101090)((const i915_reg_t){ .reg = (0x101090) })
7539
7540/* Display Internal Timeout Register */
7541#define RM_TIMEOUT((const i915_reg_t){ .reg = (0x42060) }) _MMIO(0x42060)((const i915_reg_t){ .reg = (0x42060) })
7542#define MMIO_TIMEOUT_US(us)((us) << 0) ((us) << 0)
7543
7544/* interrupts */
7545#define DE_MASTER_IRQ_CONTROL(1 << 31) (1 << 31)
7546#define DE_SPRITEB_FLIP_DONE(1 << 29) (1 << 29)
7547#define DE_SPRITEA_FLIP_DONE(1 << 28) (1 << 28)
7548#define DE_PLANEB_FLIP_DONE(1 << 27) (1 << 27)
7549#define DE_PLANEA_FLIP_DONE(1 << 26) (1 << 26)
7550#define DE_PLANE_FLIP_DONE(plane)(1 << (26 + (plane))) (1 << (26 + (plane)))
7551#define DE_PCU_EVENT(1 << 25) (1 << 25)
7552#define DE_GTT_FAULT(1 << 24) (1 << 24)
7553#define DE_POISON(1 << 23) (1 << 23)
7554#define DE_PERFORM_COUNTER(1 << 22) (1 << 22)
7555#define DE_PCH_EVENT(1 << 21) (1 << 21)
7556#define DE_AUX_CHANNEL_A(1 << 20) (1 << 20)
7557#define DE_DP_A_HOTPLUG(1 << 19) (1 << 19)
7558#define DE_GSE(1 << 18) (1 << 18)
7559#define DE_PIPEB_VBLANK(1 << 15) (1 << 15)
7560#define DE_PIPEB_EVEN_FIELD(1 << 14) (1 << 14)
7561#define DE_PIPEB_ODD_FIELD(1 << 13) (1 << 13)
7562#define DE_PIPEB_LINE_COMPARE(1 << 12) (1 << 12)
7563#define DE_PIPEB_VSYNC(1 << 11) (1 << 11)
7564#define DE_PIPEB_CRC_DONE(1 << 10) (1 << 10)
7565#define DE_PIPEB_FIFO_UNDERRUN(1 << 8) (1 << 8)
7566#define DE_PIPEA_VBLANK(1 << 7) (1 << 7)
7567#define DE_PIPE_VBLANK(pipe)(1 << (7 + 8 * (pipe))) (1 << (7 + 8 * (pipe)))
7568#define DE_PIPEA_EVEN_FIELD(1 << 6) (1 << 6)
7569#define DE_PIPEA_ODD_FIELD(1 << 5) (1 << 5)
7570#define DE_PIPEA_LINE_COMPARE(1 << 4) (1 << 4)
7571#define DE_PIPEA_VSYNC(1 << 3) (1 << 3)
7572#define DE_PIPEA_CRC_DONE(1 << 2) (1 << 2)
7573#define DE_PIPE_CRC_DONE(pipe)(1 << (2 + 8 * (pipe))) (1 << (2 + 8 * (pipe)))
7574#define DE_PIPEA_FIFO_UNDERRUN(1 << 0) (1 << 0)
7575#define DE_PIPE_FIFO_UNDERRUN(pipe)(1 << (8 * (pipe))) (1 << (8 * (pipe)))
7576
7577/* More Ivybridge lolz */
7578#define DE_ERR_INT_IVB(1 << 30) (1 << 30)
7579#define DE_GSE_IVB(1 << 29) (1 << 29)
7580#define DE_PCH_EVENT_IVB(1 << 28) (1 << 28)
7581#define DE_DP_A_HOTPLUG_IVB(1 << 27) (1 << 27)
7582#define DE_AUX_CHANNEL_A_IVB(1 << 26) (1 << 26)
7583#define DE_EDP_PSR_INT_HSW(1 << 19) (1 << 19)
7584#define DE_SPRITEC_FLIP_DONE_IVB(1 << 14) (1 << 14)
7585#define DE_PLANEC_FLIP_DONE_IVB(1 << 13) (1 << 13)
7586#define DE_PIPEC_VBLANK_IVB(1 << 10) (1 << 10)
7587#define DE_SPRITEB_FLIP_DONE_IVB(1 << 9) (1 << 9)
7588#define DE_PLANEB_FLIP_DONE_IVB(1 << 8) (1 << 8)
7589#define DE_PIPEB_VBLANK_IVB(1 << 5) (1 << 5)
7590#define DE_SPRITEA_FLIP_DONE_IVB(1 << 4) (1 << 4)
7591#define DE_PLANEA_FLIP_DONE_IVB(1 << 3) (1 << 3)
7592#define DE_PLANE_FLIP_DONE_IVB(plane)(1 << (3 + 5 * (plane))) (1 << (3 + 5 * (plane)))
7593#define DE_PIPEA_VBLANK_IVB(1 << 0) (1 << 0)
7594#define DE_PIPE_VBLANK_IVB(pipe)(1 << ((pipe) * 5)) (1 << ((pipe) * 5))
7595
7596#define VLV_MASTER_IER((const i915_reg_t){ .reg = (0x4400c) }) _MMIO(0x4400c)((const i915_reg_t){ .reg = (0x4400c) }) /* Gunit master IER */
7597#define MASTER_INTERRUPT_ENABLE(1 << 31) (1 << 31)
7598
7599#define DEISR((const i915_reg_t){ .reg = (0x44000) }) _MMIO(0x44000)((const i915_reg_t){ .reg = (0x44000) })
7600#define DEIMR((const i915_reg_t){ .reg = (0x44004) }) _MMIO(0x44004)((const i915_reg_t){ .reg = (0x44004) })
7601#define DEIIR((const i915_reg_t){ .reg = (0x44008) }) _MMIO(0x44008)((const i915_reg_t){ .reg = (0x44008) })
7602#define DEIER((const i915_reg_t){ .reg = (0x4400c) }) _MMIO(0x4400c)((const i915_reg_t){ .reg = (0x4400c) })
7603
7604#define GTISR((const i915_reg_t){ .reg = (0x44010) }) _MMIO(0x44010)((const i915_reg_t){ .reg = (0x44010) })
7605#define GTIMR((const i915_reg_t){ .reg = (0x44014) }) _MMIO(0x44014)((const i915_reg_t){ .reg = (0x44014) })
7606#define GTIIR((const i915_reg_t){ .reg = (0x44018) }) _MMIO(0x44018)((const i915_reg_t){ .reg = (0x44018) })
7607#define GTIER((const i915_reg_t){ .reg = (0x4401c) }) _MMIO(0x4401c)((const i915_reg_t){ .reg = (0x4401c) })
7608
7609#define GEN8_MASTER_IRQ((const i915_reg_t){ .reg = (0x44200) }) _MMIO(0x44200)((const i915_reg_t){ .reg = (0x44200) })
7610#define GEN8_MASTER_IRQ_CONTROL(1 << 31) (1 << 31)
7611#define GEN8_PCU_IRQ(1 << 30) (1 << 30)
7612#define GEN8_DE_PCH_IRQ(1 << 23) (1 << 23)
7613#define GEN8_DE_MISC_IRQ(1 << 22) (1 << 22)
7614#define GEN8_DE_PORT_IRQ(1 << 20) (1 << 20)
7615#define GEN8_DE_PIPE_C_IRQ(1 << 18) (1 << 18)
7616#define GEN8_DE_PIPE_B_IRQ(1 << 17) (1 << 17)
7617#define GEN8_DE_PIPE_A_IRQ(1 << 16) (1 << 16)
7618#define GEN8_DE_PIPE_IRQ(pipe)(1 << (16 + (pipe))) (1 << (16 + (pipe)))
7619#define GEN8_GT_VECS_IRQ(1 << 6) (1 << 6)
7620#define GEN8_GT_GUC_IRQ(1 << 5) (1 << 5)
7621#define GEN8_GT_PM_IRQ(1 << 4) (1 << 4)
7622#define GEN8_GT_VCS1_IRQ(1 << 3) (1 << 3) /* NB: VCS2 in bspec! */
7623#define GEN8_GT_VCS0_IRQ(1 << 2) (1 << 2) /* NB: VCS1 in bpsec! */
7624#define GEN8_GT_BCS_IRQ(1 << 1) (1 << 1)
7625#define GEN8_GT_RCS_IRQ(1 << 0) (1 << 0)
7626
7627#define GEN8_GT_ISR(which)((const i915_reg_t){ .reg = (0x44300 + (0x10 * (which))) }) _MMIO(0x44300 + (0x10 * (which)))((const i915_reg_t){ .reg = (0x44300 + (0x10 * (which))) })
7628#define GEN8_GT_IMR(which)((const i915_reg_t){ .reg = (0x44304 + (0x10 * (which))) }) _MMIO(0x44304 + (0x10 * (which)))((const i915_reg_t){ .reg = (0x44304 + (0x10 * (which))) })
7629#define GEN8_GT_IIR(which)((const i915_reg_t){ .reg = (0x44308 + (0x10 * (which))) }) _MMIO(0x44308 + (0x10 * (which)))((const i915_reg_t){ .reg = (0x44308 + (0x10 * (which))) })
7630#define GEN8_GT_IER(which)((const i915_reg_t){ .reg = (0x4430c + (0x10 * (which))) }) _MMIO(0x4430c + (0x10 * (which)))((const i915_reg_t){ .reg = (0x4430c + (0x10 * (which))) })
7631
7632#define GEN8_RCS_IRQ_SHIFT0 0
7633#define GEN8_BCS_IRQ_SHIFT16 16
7634#define GEN8_VCS0_IRQ_SHIFT0 0 /* NB: VCS1 in bspec! */
7635#define GEN8_VCS1_IRQ_SHIFT16 16 /* NB: VCS2 in bpsec! */
7636#define GEN8_VECS_IRQ_SHIFT0 0
7637#define GEN8_WD_IRQ_SHIFT16 16
7638
7639#define GEN8_DE_PIPE_ISR(pipe)((const i915_reg_t){ .reg = (0x44400 + (0x10 * (pipe))) }) _MMIO(0x44400 + (0x10 * (pipe)))((const i915_reg_t){ .reg = (0x44400 + (0x10 * (pipe))) })
7640#define GEN8_DE_PIPE_IMR(pipe)((const i915_reg_t){ .reg = (0x44404 + (0x10 * (pipe))) }) _MMIO(0x44404 + (0x10 * (pipe)))((const i915_reg_t){ .reg = (0x44404 + (0x10 * (pipe))) })
7641#define GEN8_DE_PIPE_IIR(pipe)((const i915_reg_t){ .reg = (0x44408 + (0x10 * (pipe))) }) _MMIO(0x44408 + (0x10 * (pipe)))((const i915_reg_t){ .reg = (0x44408 + (0x10 * (pipe))) })
7642#define GEN8_DE_PIPE_IER(pipe)((const i915_reg_t){ .reg = (0x4440c + (0x10 * (pipe))) }) _MMIO(0x4440c + (0x10 * (pipe)))((const i915_reg_t){ .reg = (0x4440c + (0x10 * (pipe))) })
7643#define GEN8_PIPE_FIFO_UNDERRUN(1 << 31) (1 << 31)
7644#define GEN8_PIPE_CDCLK_CRC_ERROR(1 << 29) (1 << 29)
7645#define GEN8_PIPE_CDCLK_CRC_DONE(1 << 28) (1 << 28)
7646#define GEN8_PIPE_CURSOR_FAULT(1 << 10) (1 << 10)
7647#define GEN8_PIPE_SPRITE_FAULT(1 << 9) (1 << 9)
7648#define GEN8_PIPE_PRIMARY_FAULT(1 << 8) (1 << 8)
7649#define GEN8_PIPE_SPRITE_FLIP_DONE(1 << 5) (1 << 5)
7650#define GEN8_PIPE_PRIMARY_FLIP_DONE(1 << 4) (1 << 4)
7651#define GEN8_PIPE_SCAN_LINE_EVENT(1 << 2) (1 << 2)
7652#define GEN8_PIPE_VSYNC(1 << 1) (1 << 1)
7653#define GEN8_PIPE_VBLANK(1 << 0) (1 << 0)
7654#define GEN9_PIPE_CURSOR_FAULT(1 << 11) (1 << 11)
7655#define GEN11_PIPE_PLANE7_FAULT(1 << 22) (1 << 22)
7656#define GEN11_PIPE_PLANE6_FAULT(1 << 21) (1 << 21)
7657#define GEN11_PIPE_PLANE5_FAULT(1 << 20) (1 << 20)
7658#define GEN9_PIPE_PLANE4_FAULT(1 << 10) (1 << 10)
7659#define GEN9_PIPE_PLANE3_FAULT(1 << 9) (1 << 9)
7660#define GEN9_PIPE_PLANE2_FAULT(1 << 8) (1 << 8)
7661#define GEN9_PIPE_PLANE1_FAULT(1 << 7) (1 << 7)
7662#define GEN9_PIPE_PLANE4_FLIP_DONE(1 << 6) (1 << 6)
7663#define GEN9_PIPE_PLANE3_FLIP_DONE(1 << 5) (1 << 5)
7664#define GEN9_PIPE_PLANE2_FLIP_DONE(1 << 4) (1 << 4)
7665#define GEN9_PIPE_PLANE1_FLIP_DONE(1 << 3) (1 << 3)
7666#define GEN9_PIPE_PLANE_FLIP_DONE(p)(1 << (3 + (p))) (1 << (3 + (p)))
7667#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS((1 << 10) | (1 << 9) | (1 << 8)) \
7668 (GEN8_PIPE_CURSOR_FAULT(1 << 10) | \
7669 GEN8_PIPE_SPRITE_FAULT(1 << 9) | \
7670 GEN8_PIPE_PRIMARY_FAULT(1 << 8))
7671#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS((1 << 11) | (1 << 10) | (1 << 9) | (1 <<
8) | (1 << 7)) \
7672 (GEN9_PIPE_CURSOR_FAULT(1 << 11) | \
7673 GEN9_PIPE_PLANE4_FAULT(1 << 10) | \
7674 GEN9_PIPE_PLANE3_FAULT(1 << 9) | \
7675 GEN9_PIPE_PLANE2_FAULT(1 << 8) | \
7676 GEN9_PIPE_PLANE1_FAULT(1 << 7))
7677#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS(((1 << 11) | (1 << 10) | (1 << 9) | (1 <<
8) | (1 << 7)) | (1 << 22) | (1 << 21) | (
1 << 20)) \
7678 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS((1 << 11) | (1 << 10) | (1 << 9) | (1 <<
8) | (1 << 7)) | \
7679 GEN11_PIPE_PLANE7_FAULT(1 << 22) | \
7680 GEN11_PIPE_PLANE6_FAULT(1 << 21) | \
7681 GEN11_PIPE_PLANE5_FAULT(1 << 20))
7682#define RKL_DE_PIPE_IRQ_FAULT_ERRORS(((1 << 11) | (1 << 10) | (1 << 9) | (1 <<
8) | (1 << 7)) | (1 << 20)) \
7683 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS((1 << 11) | (1 << 10) | (1 << 9) | (1 <<
8) | (1 << 7)) | \
7684 GEN11_PIPE_PLANE5_FAULT(1 << 20))
7685
7686#define GEN8_DE_PORT_ISR((const i915_reg_t){ .reg = (0x44440) }) _MMIO(0x44440)((const i915_reg_t){ .reg = (0x44440) })
7687#define GEN8_DE_PORT_IMR((const i915_reg_t){ .reg = (0x44444) }) _MMIO(0x44444)((const i915_reg_t){ .reg = (0x44444) })
7688#define GEN8_DE_PORT_IIR((const i915_reg_t){ .reg = (0x44448) }) _MMIO(0x44448)((const i915_reg_t){ .reg = (0x44448) })
7689#define GEN8_DE_PORT_IER((const i915_reg_t){ .reg = (0x4444c) }) _MMIO(0x4444c)((const i915_reg_t){ .reg = (0x4444c) })
7690#define DSI1_NON_TE(1 << 31) (1 << 31)
7691#define DSI0_NON_TE(1 << 30) (1 << 30)
7692#define ICL_AUX_CHANNEL_E(1 << 29) (1 << 29)
7693#define CNL_AUX_CHANNEL_F(1 << 28) (1 << 28)
7694#define GEN9_AUX_CHANNEL_D(1 << 27) (1 << 27)
7695#define GEN9_AUX_CHANNEL_C(1 << 26) (1 << 26)
7696#define GEN9_AUX_CHANNEL_B(1 << 25) (1 << 25)
7697#define DSI1_TE(1 << 24) (1 << 24)
7698#define DSI0_TE(1 << 23) (1 << 23)
7699#define BXT_DE_PORT_HP_DDIC(1 << 5) (1 << 5)
7700#define BXT_DE_PORT_HP_DDIB(1 << 4) (1 << 4)
7701#define BXT_DE_PORT_HP_DDIA(1 << 3) (1 << 3)
7702#define BXT_DE_PORT_HOTPLUG_MASK((1 << 3) | (1 << 4) | (1 << 5)) (BXT_DE_PORT_HP_DDIA(1 << 3) | \
7703 BXT_DE_PORT_HP_DDIB(1 << 4) | \
7704 BXT_DE_PORT_HP_DDIC(1 << 5))
7705#define GEN8_PORT_DP_A_HOTPLUG(1 << 3) (1 << 3)
7706#define BXT_DE_PORT_GMBUS(1 << 1) (1 << 1)
7707#define GEN8_AUX_CHANNEL_A(1 << 0) (1 << 0)
7708#define TGL_DE_PORT_AUX_USBC6(1 << 13) (1 << 13)
7709#define TGL_DE_PORT_AUX_USBC5(1 << 12) (1 << 12)
7710#define TGL_DE_PORT_AUX_USBC4(1 << 11) (1 << 11)
7711#define TGL_DE_PORT_AUX_USBC3(1 << 10) (1 << 10)
7712#define TGL_DE_PORT_AUX_USBC2(1 << 9) (1 << 9)
7713#define TGL_DE_PORT_AUX_USBC1(1 << 8) (1 << 8)
7714#define TGL_DE_PORT_AUX_DDIC(1 << 2) (1 << 2)
7715#define TGL_DE_PORT_AUX_DDIB(1 << 1) (1 << 1)
7716#define TGL_DE_PORT_AUX_DDIA(1 << 0) (1 << 0)
7717
7718#define GEN8_DE_MISC_ISR((const i915_reg_t){ .reg = (0x44460) }) _MMIO(0x44460)((const i915_reg_t){ .reg = (0x44460) })
7719#define GEN8_DE_MISC_IMR((const i915_reg_t){ .reg = (0x44464) }) _MMIO(0x44464)((const i915_reg_t){ .reg = (0x44464) })
7720#define GEN8_DE_MISC_IIR((const i915_reg_t){ .reg = (0x44468) }) _MMIO(0x44468)((const i915_reg_t){ .reg = (0x44468) })
7721#define GEN8_DE_MISC_IER((const i915_reg_t){ .reg = (0x4446c) }) _MMIO(0x4446c)((const i915_reg_t){ .reg = (0x4446c) })
7722#define GEN8_DE_MISC_GSE(1 << 27) (1 << 27)
7723#define GEN8_DE_EDP_PSR(1 << 19) (1 << 19)
7724
7725#define GEN8_PCU_ISR((const i915_reg_t){ .reg = (0x444e0) }) _MMIO(0x444e0)((const i915_reg_t){ .reg = (0x444e0) })
7726#define GEN8_PCU_IMR((const i915_reg_t){ .reg = (0x444e4) }) _MMIO(0x444e4)((const i915_reg_t){ .reg = (0x444e4) })
7727#define GEN8_PCU_IIR((const i915_reg_t){ .reg = (0x444e8) }) _MMIO(0x444e8)((const i915_reg_t){ .reg = (0x444e8) })
7728#define GEN8_PCU_IER((const i915_reg_t){ .reg = (0x444ec) }) _MMIO(0x444ec)((const i915_reg_t){ .reg = (0x444ec) })
7729
7730#define GEN11_GU_MISC_ISR((const i915_reg_t){ .reg = (0x444f0) }) _MMIO(0x444f0)((const i915_reg_t){ .reg = (0x444f0) })
7731#define GEN11_GU_MISC_IMR((const i915_reg_t){ .reg = (0x444f4) }) _MMIO(0x444f4)((const i915_reg_t){ .reg = (0x444f4) })
7732#define GEN11_GU_MISC_IIR((const i915_reg_t){ .reg = (0x444f8) }) _MMIO(0x444f8)((const i915_reg_t){ .reg = (0x444f8) })
7733#define GEN11_GU_MISC_IER((const i915_reg_t){ .reg = (0x444fc) }) _MMIO(0x444fc)((const i915_reg_t){ .reg = (0x444fc) })
7734#define GEN11_GU_MISC_GSE(1 << 27) (1 << 27)
7735
7736#define GEN11_GFX_MSTR_IRQ((const i915_reg_t){ .reg = (0x190010) }) _MMIO(0x190010)((const i915_reg_t){ .reg = (0x190010) })
7737#define GEN11_MASTER_IRQ(1 << 31) (1 << 31)
7738#define GEN11_PCU_IRQ(1 << 30) (1 << 30)
7739#define GEN11_GU_MISC_IRQ(1 << 29) (1 << 29)
7740#define GEN11_DISPLAY_IRQ(1 << 16) (1 << 16)
7741#define GEN11_GT_DW_IRQ(x)(1 << (x)) (1 << (x))
7742#define GEN11_GT_DW1_IRQ(1 << 1) (1 << 1)
7743#define GEN11_GT_DW0_IRQ(1 << 0) (1 << 0)
7744
7745#define DG1_MSTR_UNIT_INTR((const i915_reg_t){ .reg = (0x190008) }) _MMIO(0x190008)((const i915_reg_t){ .reg = (0x190008) })
7746#define DG1_MSTR_IRQ((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
7747#define DG1_MSTR_UNIT(u)((u32)((1UL << (u)) + 0)) REG_BIT(u)((u32)((1UL << (u)) + 0))
7748
7749#define GEN11_DISPLAY_INT_CTL((const i915_reg_t){ .reg = (0x44200) }) _MMIO(0x44200)((const i915_reg_t){ .reg = (0x44200) })
7750#define GEN11_DISPLAY_IRQ_ENABLE(1 << 31) (1 << 31)
7751#define GEN11_AUDIO_CODEC_IRQ(1 << 24) (1 << 24)
7752#define GEN11_DE_PCH_IRQ(1 << 23) (1 << 23)
7753#define GEN11_DE_MISC_IRQ(1 << 22) (1 << 22)
7754#define GEN11_DE_HPD_IRQ(1 << 21) (1 << 21)
7755#define GEN11_DE_PORT_IRQ(1 << 20) (1 << 20)
7756#define GEN11_DE_PIPE_C(1 << 18) (1 << 18)
7757#define GEN11_DE_PIPE_B(1 << 17) (1 << 17)
7758#define GEN11_DE_PIPE_A(1 << 16) (1 << 16)
7759
7760#define GEN11_DE_HPD_ISR((const i915_reg_t){ .reg = (0x44470) }) _MMIO(0x44470)((const i915_reg_t){ .reg = (0x44470) })
7761#define GEN11_DE_HPD_IMR((const i915_reg_t){ .reg = (0x44474) }) _MMIO(0x44474)((const i915_reg_t){ .reg = (0x44474) })
7762#define GEN11_DE_HPD_IIR((const i915_reg_t){ .reg = (0x44478) }) _MMIO(0x44478)((const i915_reg_t){ .reg = (0x44478) })
7763#define GEN11_DE_HPD_IER((const i915_reg_t){ .reg = (0x4447c) }) _MMIO(0x4447c)((const i915_reg_t){ .reg = (0x4447c) })
7764#define GEN11_TC_HOTPLUG(tc_port)(1 << ((tc_port) + 16)) (1 << ((tc_port) + 16))
7765#define GEN11_DE_TC_HOTPLUG_MASK((1 << ((PORT_TC6) + 16)) | (1 << ((PORT_TC5) + 16
)) | (1 << ((PORT_TC4) + 16)) | (1 << ((PORT_TC3)
+ 16)) | (1 << ((PORT_TC2) + 16)) | (1 << ((PORT_TC1
) + 16))) (GEN11_TC_HOTPLUG(PORT_TC6)(1 << ((PORT_TC6) + 16)) | \
7766 GEN11_TC_HOTPLUG(PORT_TC5)(1 << ((PORT_TC5) + 16)) | \
7767 GEN11_TC_HOTPLUG(PORT_TC4)(1 << ((PORT_TC4) + 16)) | \
7768 GEN11_TC_HOTPLUG(PORT_TC3)(1 << ((PORT_TC3) + 16)) | \
7769 GEN11_TC_HOTPLUG(PORT_TC2)(1 << ((PORT_TC2) + 16)) | \
7770 GEN11_TC_HOTPLUG(PORT_TC1)(1 << ((PORT_TC1) + 16)))
7771#define GEN11_TBT_HOTPLUG(tc_port)(1 << (tc_port)) (1 << (tc_port))
7772#define GEN11_DE_TBT_HOTPLUG_MASK((1 << (PORT_TC6)) | (1 << (PORT_TC5)) | (1 <<
(PORT_TC4)) | (1 << (PORT_TC3)) | (1 << (PORT_TC2
)) | (1 << (PORT_TC1))) (GEN11_TBT_HOTPLUG(PORT_TC6)(1 << (PORT_TC6)) | \
7773 GEN11_TBT_HOTPLUG(PORT_TC5)(1 << (PORT_TC5)) | \
7774 GEN11_TBT_HOTPLUG(PORT_TC4)(1 << (PORT_TC4)) | \
7775 GEN11_TBT_HOTPLUG(PORT_TC3)(1 << (PORT_TC3)) | \
7776 GEN11_TBT_HOTPLUG(PORT_TC2)(1 << (PORT_TC2)) | \
7777 GEN11_TBT_HOTPLUG(PORT_TC1)(1 << (PORT_TC1)))
7778
7779#define GEN11_TBT_HOTPLUG_CTL((const i915_reg_t){ .reg = (0x44030) }) _MMIO(0x44030)((const i915_reg_t){ .reg = (0x44030) })
7780#define GEN11_TC_HOTPLUG_CTL((const i915_reg_t){ .reg = (0x44038) }) _MMIO(0x44038)((const i915_reg_t){ .reg = (0x44038) })
7781#define GEN11_HOTPLUG_CTL_ENABLE(tc_port)(8 << (tc_port) * 4) (8 << (tc_port) * 4)
7782#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)(2 << (tc_port) * 4) (2 << (tc_port) * 4)
7783#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)(1 << (tc_port) * 4) (1 << (tc_port) * 4)
7784#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)(0 << (tc_port) * 4) (0 << (tc_port) * 4)
7785
7786#define GEN11_GT_INTR_DW0((const i915_reg_t){ .reg = (0x190018) }) _MMIO(0x190018)((const i915_reg_t){ .reg = (0x190018) })
7787#define GEN11_CSME(31) (31)
7788#define GEN11_GUNIT(28) (28)
7789#define GEN11_GUC(25) (25)
7790#define GEN11_WDPERF(20) (20)
7791#define GEN11_KCR(19) (19)
7792#define GEN11_GTPM(16) (16)
7793#define GEN11_BCS(15) (15)
7794#define GEN11_RCS0(0) (0)
7795
7796#define GEN11_GT_INTR_DW1((const i915_reg_t){ .reg = (0x19001c) }) _MMIO(0x19001c)((const i915_reg_t){ .reg = (0x19001c) })
7797#define GEN11_VECS(x)(31 - (x)) (31 - (x))
7798#define GEN11_VCS(x)(x) (x)
7799
7800#define GEN11_GT_INTR_DW(x)((const i915_reg_t){ .reg = (0x190018 + ((x) * 4)) }) _MMIO(0x190018 + ((x) * 4))((const i915_reg_t){ .reg = (0x190018 + ((x) * 4)) })
7801
7802#define GEN11_INTR_IDENTITY_REG0((const i915_reg_t){ .reg = (0x190060) }) _MMIO(0x190060)((const i915_reg_t){ .reg = (0x190060) })
7803#define GEN11_INTR_IDENTITY_REG1((const i915_reg_t){ .reg = (0x190064) }) _MMIO(0x190064)((const i915_reg_t){ .reg = (0x190064) })
7804#define GEN11_INTR_DATA_VALID(1 << 31) (1 << 31)
7805#define GEN11_INTR_ENGINE_CLASS(x)(((x) & (((~0UL) >> (64 - (18) - 1)) & ((~0UL) <<
(16)))) >> 16) (((x) & GENMASK(18, 16)(((~0UL) >> (64 - (18) - 1)) & ((~0UL) << (16
)))) >> 16)
7806#define GEN11_INTR_ENGINE_INSTANCE(x)(((x) & (((~0UL) >> (64 - (25) - 1)) & ((~0UL) <<
(20)))) >> 20) (((x) & GENMASK(25, 20)(((~0UL) >> (64 - (25) - 1)) & ((~0UL) << (20
)))) >> 20)
7807#define GEN11_INTR_ENGINE_INTR(x)((x) & 0xffff) ((x) & 0xffff)
7808/* irq instances for OTHER_CLASS */
7809#define OTHER_GUC_INSTANCE0 0
7810#define OTHER_GTPM_INSTANCE1 1
7811
7812#define GEN11_INTR_IDENTITY_REG(x)((const i915_reg_t){ .reg = (0x190060 + ((x) * 4)) }) _MMIO(0x190060 + ((x) * 4))((const i915_reg_t){ .reg = (0x190060 + ((x) * 4)) })
7813
7814#define GEN11_IIR_REG0_SELECTOR((const i915_reg_t){ .reg = (0x190070) }) _MMIO(0x190070)((const i915_reg_t){ .reg = (0x190070) })
7815#define GEN11_IIR_REG1_SELECTOR((const i915_reg_t){ .reg = (0x190074) }) _MMIO(0x190074)((const i915_reg_t){ .reg = (0x190074) })
7816
7817#define GEN11_IIR_REG_SELECTOR(x)((const i915_reg_t){ .reg = (0x190070 + ((x) * 4)) }) _MMIO(0x190070 + ((x) * 4))((const i915_reg_t){ .reg = (0x190070 + ((x) * 4)) })
7818
7819#define GEN11_RENDER_COPY_INTR_ENABLE((const i915_reg_t){ .reg = (0x190030) }) _MMIO(0x190030)((const i915_reg_t){ .reg = (0x190030) })
7820#define GEN11_VCS_VECS_INTR_ENABLE((const i915_reg_t){ .reg = (0x190034) }) _MMIO(0x190034)((const i915_reg_t){ .reg = (0x190034) })
7821#define GEN11_GUC_SG_INTR_ENABLE((const i915_reg_t){ .reg = (0x190038) }) _MMIO(0x190038)((const i915_reg_t){ .reg = (0x190038) })
7822#define GEN11_GPM_WGBOXPERF_INTR_ENABLE((const i915_reg_t){ .reg = (0x19003c) }) _MMIO(0x19003c)((const i915_reg_t){ .reg = (0x19003c) })
7823#define GEN11_CRYPTO_RSVD_INTR_ENABLE((const i915_reg_t){ .reg = (0x190040) }) _MMIO(0x190040)((const i915_reg_t){ .reg = (0x190040) })
7824#define GEN11_GUNIT_CSME_INTR_ENABLE((const i915_reg_t){ .reg = (0x190044) }) _MMIO(0x190044)((const i915_reg_t){ .reg = (0x190044) })
7825
7826#define GEN11_RCS0_RSVD_INTR_MASK((const i915_reg_t){ .reg = (0x190090) }) _MMIO(0x190090)((const i915_reg_t){ .reg = (0x190090) })
7827#define GEN11_BCS_RSVD_INTR_MASK((const i915_reg_t){ .reg = (0x1900a0) }) _MMIO(0x1900a0)((const i915_reg_t){ .reg = (0x1900a0) })
7828#define GEN11_VCS0_VCS1_INTR_MASK((const i915_reg_t){ .reg = (0x1900a8) }) _MMIO(0x1900a8)((const i915_reg_t){ .reg = (0x1900a8) })
7829#define GEN11_VCS2_VCS3_INTR_MASK((const i915_reg_t){ .reg = (0x1900ac) }) _MMIO(0x1900ac)((const i915_reg_t){ .reg = (0x1900ac) })
7830#define GEN11_VECS0_VECS1_INTR_MASK((const i915_reg_t){ .reg = (0x1900d0) }) _MMIO(0x1900d0)((const i915_reg_t){ .reg = (0x1900d0) })
7831#define GEN11_GUC_SG_INTR_MASK((const i915_reg_t){ .reg = (0x1900e8) }) _MMIO(0x1900e8)((const i915_reg_t){ .reg = (0x1900e8) })
7832#define GEN11_GPM_WGBOXPERF_INTR_MASK((const i915_reg_t){ .reg = (0x1900ec) }) _MMIO(0x1900ec)((const i915_reg_t){ .reg = (0x1900ec) })
7833#define GEN11_CRYPTO_RSVD_INTR_MASK((const i915_reg_t){ .reg = (0x1900f0) }) _MMIO(0x1900f0)((const i915_reg_t){ .reg = (0x1900f0) })
7834#define GEN11_GUNIT_CSME_INTR_MASK((const i915_reg_t){ .reg = (0x1900f4) }) _MMIO(0x1900f4)((const i915_reg_t){ .reg = (0x1900f4) })
7835
7836#define ENGINE1_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(31, 16)((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))
7837#define ENGINE0_MASK((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(15, 0)((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0))) + 0))
7838
7839#define ILK_DISPLAY_CHICKEN2((const i915_reg_t){ .reg = (0x42004) }) _MMIO(0x42004)((const i915_reg_t){ .reg = (0x42004) })
7840/* Required on all Ironlake and Sandybridge according to the B-Spec. */
7841#define ILK_ELPIN_409_SELECT(1 << 25) (1 << 25)
7842#define ILK_DPARB_GATE(1 << 22) (1 << 22)
7843#define ILK_VSDPFD_FULL(1 << 21) (1 << 21)
7844#define FUSE_STRAP((const i915_reg_t){ .reg = (0x42014) }) _MMIO(0x42014)((const i915_reg_t){ .reg = (0x42014) })
7845#define ILK_INTERNAL_GRAPHICS_DISABLE(1 << 31) (1 << 31)
7846#define ILK_INTERNAL_DISPLAY_DISABLE(1 << 30) (1 << 30)
7847#define ILK_DISPLAY_DEBUG_DISABLE(1 << 29) (1 << 29)
7848#define IVB_PIPE_C_DISABLE(1 << 28) (1 << 28)
7849#define ILK_HDCP_DISABLE(1 << 25) (1 << 25)
7850#define ILK_eDP_A_DISABLE(1 << 24) (1 << 24)
7851#define HSW_CDCLK_LIMIT(1 << 24) (1 << 24)
7852#define ILK_DESKTOP(1 << 23) (1 << 23)
7853#define HSW_CPU_SSC_ENABLE(1 << 21) (1 << 21)
7854
7855#define FUSE_STRAP3((const i915_reg_t){ .reg = (0x42020) }) _MMIO(0x42020)((const i915_reg_t){ .reg = (0x42020) })
7856#define HSW_REF_CLK_SELECT(1 << 1) (1 << 1)
7857
7858#define ILK_DSPCLK_GATE_D((const i915_reg_t){ .reg = (0x42020) }) _MMIO(0x42020)((const i915_reg_t){ .reg = (0x42020) })
7859#define ILK_VRHUNIT_CLOCK_GATE_DISABLE(1 << 28) (1 << 28)
7860#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE(1 << 9) (1 << 9)
7861#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE(1 << 8) (1 << 8)
7862#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE(1 << 7) (1 << 7)
7863#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE(1 << 5) (1 << 5)
7864
7865#define IVB_CHICKEN3((const i915_reg_t){ .reg = (0x4200c) }) _MMIO(0x4200c)((const i915_reg_t){ .reg = (0x4200c) })
7866# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE(1 << 5) (1 << 5)
7867# define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2) (1 << 2)
7868
7869#define CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) }) _MMIO(0x42080)((const i915_reg_t){ .reg = (0x42080) })
7870#define DIS_RAM_BYPASS_PSR2_MAN_TRACK(1 << 16) (1 << 16)
7871#define SKL_DE_COMPRESSED_HASH_MODE(1 << 15) (1 << 15)
7872#define DPA_MASK_VBLANK_SRD(1 << 15) (1 << 15)
7873#define FORCE_ARB_IDLE_PLANES(1 << 14) (1 << 14)
7874#define SKL_EDP_PSR_FIX_RDWRAP(1 << 3) (1 << 3)
7875#define IGNORE_PSR2_HW_TRACKING(1 << 1) (1 << 1)
7876
7877#define CHICKEN_PAR2_1((const i915_reg_t){ .reg = (0x42090) }) _MMIO(0x42090)((const i915_reg_t){ .reg = (0x42090) })
7878#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT(1 << 14) (1 << 14)
7879
7880#define CHICKEN_MISC_2((const i915_reg_t){ .reg = (0x42084) }) _MMIO(0x42084)((const i915_reg_t){ .reg = (0x42084) })
7881#define CNL_COMP_PWR_DOWN(1 << 23) (1 << 23)
7882#define GLK_CL2_PWR_DOWN(1 << 12) (1 << 12)
7883#define GLK_CL1_PWR_DOWN(1 << 11) (1 << 11)
7884#define GLK_CL0_PWR_DOWN(1 << 10) (1 << 10)
7885
7886#define CHICKEN_MISC_4((const i915_reg_t){ .reg = (0x4208c) }) _MMIO(0x4208c)((const i915_reg_t){ .reg = (0x4208c) })
7887#define FBC_STRIDE_OVERRIDE(1 << 13) (1 << 13)
7888#define FBC_STRIDE_MASK0x1FFF 0x1FFF
7889
7890#define _CHICKEN_PIPESL_1_A0x420b0 0x420b0
7891#define _CHICKEN_PIPESL_1_B0x420b4 0x420b4
7892#define HSW_FBCQ_DIS(1 << 22) (1 << 22)
7893#define BDW_DPRS_MASK_VBLANK_SRD(1 << 0) (1 << 0)
7894#define CHICKEN_PIPESL_1(pipe)((const i915_reg_t){ .reg = (((0x420b0) + (pipe) * ((0x420b4)
- (0x420b0)))) }) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)((const i915_reg_t){ .reg = (((0x420b0) + (pipe) * ((0x420b4)
- (0x420b0)))) })
7895
7896#define _CHICKEN_TRANS_A0x420c0 0x420c0
7897#define _CHICKEN_TRANS_B0x420c4 0x420c4
7898#define _CHICKEN_TRANS_C0x420c8 0x420c8
7899#define _CHICKEN_TRANS_EDP0x420cc 0x420cc
7900#define _CHICKEN_TRANS_D0x420d8 0x420d8
7901#define CHICKEN_TRANS(trans)((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) }) _MMIO(_PICK((trans), \((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7902 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7903 [TRANSCODER_A] = _CHICKEN_TRANS_A, \((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7904 [TRANSCODER_B] = _CHICKEN_TRANS_B, \((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7905 [TRANSCODER_C] = _CHICKEN_TRANS_C, \((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7906 [TRANSCODER_D] = _CHICKEN_TRANS_D))((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans
)])) })
7907#define HSW_FRAME_START_DELAY_MASK(3 << 27) (3 << 27)
7908#define HSW_FRAME_START_DELAY(x)((x) << 27) ((x) << 27) /* 0-3 */
7909#define VSC_DATA_SEL_SOFTWARE_CONTROL(1 << 25) (1 << 25) /* GLK and CNL+ */
7910#define DDI_TRAINING_OVERRIDE_ENABLE(1 << 19) (1 << 19)
7911#define DDI_TRAINING_OVERRIDE_VALUE(1 << 18) (1 << 18)
7912#define DDIE_TRAINING_OVERRIDE_ENABLE(1 << 17) (1 << 17) /* CHICKEN_TRANS_A only */
7913#define DDIE_TRAINING_OVERRIDE_VALUE(1 << 16) (1 << 16) /* CHICKEN_TRANS_A only */
7914#define PSR2_ADD_VERTICAL_LINE_COUNT(1 << 15) (1 << 15)
7915#define PSR2_VSC_ENABLE_PROG_HEADER(1 << 12) (1 << 12)
7916
7917#define DISP_ARB_CTL((const i915_reg_t){ .reg = (0x45000) }) _MMIO(0x45000)((const i915_reg_t){ .reg = (0x45000) })
7918#define DISP_FBC_MEMORY_WAKE(1 << 31) (1 << 31)
7919#define DISP_TILE_SURFACE_SWIZZLING(1 << 13) (1 << 13)
7920#define DISP_FBC_WM_DIS(1 << 15) (1 << 15)
7921#define DISP_ARB_CTL2((const i915_reg_t){ .reg = (0x45004) }) _MMIO(0x45004)((const i915_reg_t){ .reg = (0x45004) })
7922#define DISP_DATA_PARTITION_5_6(1 << 6) (1 << 6)
7923#define DISP_IPC_ENABLE(1 << 3) (1 << 3)
7924#define _DBUF_CTL_S10x45008 0x45008
7925#define _DBUF_CTL_S20x44FE8 0x44FE8
7926#define DBUF_CTL_S(slice)((const i915_reg_t){ .reg = (((0x45008) + (slice) * ((0x44FE8
) - (0x45008)))) }) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))((const i915_reg_t){ .reg = (((0x45008) + (slice) * ((0x44FE8
) - (0x45008)))) })
7927#define DBUF_POWER_REQUEST(1 << 31) (1 << 31)
7928#define DBUF_POWER_STATE(1 << 30) (1 << 30)
7929#define GEN7_MSG_CTL((const i915_reg_t){ .reg = (0x45010) }) _MMIO(0x45010)((const i915_reg_t){ .reg = (0x45010) })
7930#define WAIT_FOR_PCH_RESET_ACK(1 << 1) (1 << 1)
7931#define WAIT_FOR_PCH_FLR_ACK(1 << 0) (1 << 0)
7932
7933#define _BW_BUDDY0_CTL0x45130 0x45130
7934#define _BW_BUDDY1_CTL0x45140 0x45140
7935#define BW_BUDDY_CTL(x)((const i915_reg_t){ .reg = (((0x45130) + (x) * ((0x45140) - (
0x45130)))) }) _MMIO(_PICK_EVEN(x, \((const i915_reg_t){ .reg = (((0x45130) + (x) * ((0x45140) - (
0x45130)))) })
7936 _BW_BUDDY0_CTL, \((const i915_reg_t){ .reg = (((0x45130) + (x) * ((0x45140) - (
0x45130)))) })
7937 _BW_BUDDY1_CTL))((const i915_reg_t){ .reg = (((0x45130) + (x) * ((0x45140) - (
0x45130)))) })
7938#define BW_BUDDY_DISABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
7939#define BW_BUDDY_TLB_REQ_TIMER_MASK((u32)((((~0UL) >> (64 - (21) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(21, 16)((u32)((((~0UL) >> (64 - (21) - 1)) & ((~0UL) <<
(16))) + 0))
7940#define BW_BUDDY_TLB_REQ_TIMER(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (21) - 1)) &
((~0UL) << (16))) + 0))))(x) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (21) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (21
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (21) - 1)) &
((~0UL) << (16))) + 0))))(x) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (21) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (21
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
7941
7942#define _BW_BUDDY0_PAGE_MASK0x45134 0x45134
7943#define _BW_BUDDY1_PAGE_MASK0x45144 0x45144
7944#define BW_BUDDY_PAGE_MASK(x)((const i915_reg_t){ .reg = (((0x45134) + (x) * ((0x45144) - (
0x45134)))) }) _MMIO(_PICK_EVEN(x, \((const i915_reg_t){ .reg = (((0x45134) + (x) * ((0x45144) - (
0x45134)))) })
7945 _BW_BUDDY0_PAGE_MASK, \((const i915_reg_t){ .reg = (((0x45134) + (x) * ((0x45144) - (
0x45134)))) })
7946 _BW_BUDDY1_PAGE_MASK))((const i915_reg_t){ .reg = (((0x45134) + (x) * ((0x45144) - (
0x45134)))) })
7947
7948#define HSW_NDE_RSTWRN_OPT((const i915_reg_t){ .reg = (0x46408) }) _MMIO(0x46408)((const i915_reg_t){ .reg = (0x46408) })
7949#define RESET_PCH_HANDSHAKE_ENABLE(1 << 4) (1 << 4)
7950
7951#define GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) }) _MMIO(0x46430)((const i915_reg_t){ .reg = (0x46430) })
7952#define SKL_SELECT_ALTERNATE_DC_EXIT(1 << 30) (1 << 30)
7953#define CNL_DELAY_PMRSP(1 << 22) (1 << 22)
7954#define MASK_WAKEMEM(1 << 13) (1 << 13)
7955#define CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7) (1 << 7)
7956
7957#define GEN11_CHICKEN_DCPR_2((const i915_reg_t){ .reg = (0x46434) }) _MMIO(0x46434)((const i915_reg_t){ .reg = (0x46434) })
7958#define DCPR_MASK_MAXLATENCY_MEMUP_CLR((u32)((1UL << (27)) + 0)) REG_BIT(27)((u32)((1UL << (27)) + 0))
7959#define DCPR_MASK_LPMODE((u32)((1UL << (26)) + 0)) REG_BIT(26)((u32)((1UL << (26)) + 0))
7960#define DCPR_SEND_RESP_IMM((u32)((1UL << (25)) + 0)) REG_BIT(25)((u32)((1UL << (25)) + 0))
7961#define DCPR_CLEAR_MEMSTAT_DIS((u32)((1UL << (24)) + 0)) REG_BIT(24)((u32)((1UL << (24)) + 0))
7962
7963#define SKL_DFSM((const i915_reg_t){ .reg = (0x51000) }) _MMIO(0x51000)((const i915_reg_t){ .reg = (0x51000) })
7964#define SKL_DFSM_DISPLAY_PM_DISABLE(1 << 27) (1 << 27)
7965#define SKL_DFSM_DISPLAY_HDCP_DISABLE(1 << 25) (1 << 25)
7966#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23) (3 << 23)
7967#define SKL_DFSM_CDCLK_LIMIT_675(0 << 23) (0 << 23)
7968#define SKL_DFSM_CDCLK_LIMIT_540(1 << 23) (1 << 23)
7969#define SKL_DFSM_CDCLK_LIMIT_450(2 << 23) (2 << 23)
7970#define SKL_DFSM_CDCLK_LIMIT_337_5(3 << 23) (3 << 23)
7971#define ICL_DFSM_DMC_DISABLE(1 << 23) (1 << 23)
7972#define SKL_DFSM_PIPE_A_DISABLE(1 << 30) (1 << 30)
7973#define SKL_DFSM_PIPE_B_DISABLE(1 << 21) (1 << 21)
7974#define SKL_DFSM_PIPE_C_DISABLE(1 << 28) (1 << 28)
7975#define TGL_DFSM_PIPE_D_DISABLE(1 << 22) (1 << 22)
7976#define CNL_DFSM_DISPLAY_DSC_DISABLE(1 << 7) (1 << 7)
7977
7978#define SKL_DSSM((const i915_reg_t){ .reg = (0x51004) }) _MMIO(0x51004)((const i915_reg_t){ .reg = (0x51004) })
7979#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31) (1 << 31)
7980#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK(7 << 29) (7 << 29)
7981#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz(0 << 29) (0 << 29)
7982#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz(1 << 29) (1 << 29)
7983#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz(2 << 29) (2 << 29)
7984
7985#define GEN7_FF_SLICE_CS_CHICKEN1((const i915_reg_t){ .reg = (0x20e0) }) _MMIO(0x20e0)((const i915_reg_t){ .reg = (0x20e0) })
7986#define GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14) (1 << 14)
7987
7988#define FF_SLICE_CS_CHICKEN2((const i915_reg_t){ .reg = (0x20e4) }) _MMIO(0x20e4)((const i915_reg_t){ .reg = (0x20e4) })
7989#define GEN9_TSG_BARRIER_ACK_DISABLE(1 << 8) (1 << 8)
7990#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE(1 << 10) (1 << 10)
7991
7992#define GEN9_CS_DEBUG_MODE1((const i915_reg_t){ .reg = (0x20ec) }) _MMIO(0x20ec)((const i915_reg_t){ .reg = (0x20ec) })
7993#define FF_DOP_CLOCK_GATE_DISABLE((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
7994#define GEN9_CTX_PREEMPT_REG((const i915_reg_t){ .reg = (0x2248) }) _MMIO(0x2248)((const i915_reg_t){ .reg = (0x2248) })
7995#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG((u32)((1UL << (11)) + 0)) REG_BIT(11)((u32)((1UL << (11)) + 0))
7996
7997#define GEN8_CS_CHICKEN1((const i915_reg_t){ .reg = (0x2580) }) _MMIO(0x2580)((const i915_reg_t){ .reg = (0x2580) })
7998#define GEN9_PREEMPT_3D_OBJECT_LEVEL(1 << 0) (1 << 0)
7999#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)(((hi) << 2) | ((lo) << 1)) (((hi) << 2) | ((lo) << 1))
8000#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL(((0) << 2) | ((0) << 1)) GEN9_PREEMPT_GPGPU_LEVEL(0, 0)(((0) << 2) | ((0) << 1))
8001#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL(((0) << 2) | ((1) << 1)) GEN9_PREEMPT_GPGPU_LEVEL(0, 1)(((0) << 2) | ((1) << 1))
8002#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL(((1) << 2) | ((0) << 1)) GEN9_PREEMPT_GPGPU_LEVEL(1, 0)(((1) << 2) | ((0) << 1))
8003#define GEN9_PREEMPT_GPGPU_LEVEL_MASK(((1) << 2) | ((1) << 1)) GEN9_PREEMPT_GPGPU_LEVEL(1, 1)(((1) << 2) | ((1) << 1))
8004
8005/* GEN7 chicken */
8006#define GEN7_COMMON_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0x7010) }) _MMIO(0x7010)((const i915_reg_t){ .reg = (0x7010) })
8007 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC(1 << 10) (1 << 10)
8008 #define GEN9_RHWO_OPTIMIZATION_DISABLE(1 << 14) (1 << 14)
8009
8010#define COMMON_SLICE_CHICKEN2((const i915_reg_t){ .reg = (0x7014) }) _MMIO(0x7014)((const i915_reg_t){ .reg = (0x7014) })
8011 #define GEN9_PBE_COMPRESSED_HASH_SELECTION(1 << 13) (1 << 13)
8012 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE(1 << 12) (1 << 12)
8013 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION(1 << 8) (1 << 8)
8014 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE(1 << 0) (1 << 0)
8015
8016#define GEN8_L3CNTLREG((const i915_reg_t){ .reg = (0x7034) }) _MMIO(0x7034)((const i915_reg_t){ .reg = (0x7034) })
8017 #define GEN8_ERRDETBCTRL(1 << 9) (1 << 9)
8018
8019#define GEN11_COMMON_SLICE_CHICKEN3((const i915_reg_t){ .reg = (0x7304) }) _MMIO(0x7304)((const i915_reg_t){ .reg = (0x7304) })
8020 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC(1 << 11) (1 << 11)
8021 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE(1 << 9) (1 << 9)
8022
8023#define HIZ_CHICKEN((const i915_reg_t){ .reg = (0x7018) }) _MMIO(0x7018)((const i915_reg_t){ .reg = (0x7018) })
8024# define CHV_HZ_8X8_MODE_IN_1X(1 << 15) (1 << 15)
8025# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE(1 << 3) (1 << 3)
8026
8027#define GEN9_SLICE_COMMON_ECO_CHICKEN0((const i915_reg_t){ .reg = (0x7308) }) _MMIO(0x7308)((const i915_reg_t){ .reg = (0x7308) })
8028#define DISABLE_PIXEL_MASK_CAMMING(1 << 14) (1 << 14)
8029
8030#define GEN9_SLICE_COMMON_ECO_CHICKEN1((const i915_reg_t){ .reg = (0x731c) }) _MMIO(0x731c)((const i915_reg_t){ .reg = (0x731c) })
8031#define GEN11_STATE_CACHE_REDIRECT_TO_CS(1 << 11) (1 << 11)
8032
8033#define GEN7_SARCHKMD((const i915_reg_t){ .reg = (0xB000) }) _MMIO(0xB000)((const i915_reg_t){ .reg = (0xB000) })
8034#define GEN7_DISABLE_DEMAND_PREFETCH(1 << 31) (1 << 31)
8035#define GEN7_DISABLE_SAMPLER_PREFETCH(1 << 30) (1 << 30)
8036
8037#define GEN7_L3SQCREG1((const i915_reg_t){ .reg = (0xB010) }) _MMIO(0xB010)((const i915_reg_t){ .reg = (0xB010) })
8038#define VLV_B0_WA_L3SQCREG1_VALUE0x00D30000 0x00D30000
8039
8040#define GEN8_L3SQCREG1((const i915_reg_t){ .reg = (0xB100) }) _MMIO(0xB100)((const i915_reg_t){ .reg = (0xB100) })
8041/*
8042 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8043 * Using the formula in BSpec leads to a hang, while the formula here works
8044 * fine and matches the formulas for all other platforms. A BSpec change
8045 * request has been filed to clarify this.
8046 */
8047#define L3_GENERAL_PRIO_CREDITS(x)(((x) >> 1) << 19) (((x) >> 1) << 19)
8048#define L3_HIGH_PRIO_CREDITS(x)(((x) >> 1) << 14) (((x) >> 1) << 14)
8049#define L3_PRIO_CREDITS_MASK((0x1f << 19) | (0x1f << 14)) ((0x1f << 19) | (0x1f << 14))
8050
8051#define GEN7_L3CNTLREG1((const i915_reg_t){ .reg = (0xB01C) }) _MMIO(0xB01C)((const i915_reg_t){ .reg = (0xB01C) })
8052#define GEN7_WA_FOR_GEN7_L3_CONTROL0x3C47FF8C 0x3C47FF8C
8053#define GEN7_L3AGDIS(1 << 19) (1 << 19)
8054#define GEN7_L3CNTLREG2((const i915_reg_t){ .reg = (0xB020) }) _MMIO(0xB020)((const i915_reg_t){ .reg = (0xB020) })
8055#define GEN7_L3CNTLREG3((const i915_reg_t){ .reg = (0xB024) }) _MMIO(0xB024)((const i915_reg_t){ .reg = (0xB024) })
8056
8057#define GEN7_L3_CHICKEN_MODE_REGISTER((const i915_reg_t){ .reg = (0xB030) }) _MMIO(0xB030)((const i915_reg_t){ .reg = (0xB030) })
8058#define GEN7_WA_L3_CHICKEN_MODE0x20000000 0x20000000
8059#define GEN10_L3_CHICKEN_MODE_REGISTER((const i915_reg_t){ .reg = (0xB114) }) _MMIO(0xB114)((const i915_reg_t){ .reg = (0xB114) })
8060#define GEN11_I2M_WRITE_DISABLE(1 << 28) (1 << 28)
8061
8062#define GEN7_L3SQCREG4((const i915_reg_t){ .reg = (0xb034) }) _MMIO(0xb034)((const i915_reg_t){ .reg = (0xb034) })
8063#define L3SQ_URB_READ_CAM_MATCH_DISABLE(1 << 27) (1 << 27)
8064
8065#define GEN11_SCRATCH2((const i915_reg_t){ .reg = (0xb140) }) _MMIO(0xb140)((const i915_reg_t){ .reg = (0xb140) })
8066#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE(1 << 19) (1 << 19)
8067
8068#define GEN8_L3SQCREG4((const i915_reg_t){ .reg = (0xb118) }) _MMIO(0xb118)((const i915_reg_t){ .reg = (0xb118) })
8069#define GEN11_LQSC_CLEAN_EVICT_DISABLE(1 << 6) (1 << 6)
8070#define GEN8_LQSC_RO_PERF_DIS(1 << 27) (1 << 27)
8071#define GEN8_LQSC_FLUSH_COHERENT_LINES(1 << 21) (1 << 21)
8072
8073/* GEN8 chicken */
8074#define HDC_CHICKEN0((const i915_reg_t){ .reg = (0x7300) }) _MMIO(0x7300)((const i915_reg_t){ .reg = (0x7300) })
8075#define CNL_HDC_CHICKEN0((const i915_reg_t){ .reg = (0xE5F0) }) _MMIO(0xE5F0)((const i915_reg_t){ .reg = (0xE5F0) })
8076#define ICL_HDC_MODE((const i915_reg_t){ .reg = (0xE5F4) }) _MMIO(0xE5F4)((const i915_reg_t){ .reg = (0xE5F4) })
8077#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1 << 15) (1 << 15)
8078#define HDC_FENCE_DEST_SLM_DISABLE(1 << 14) (1 << 14)
8079#define HDC_DONOT_FETCH_MEM_WHEN_MASKED(1 << 11) (1 << 11)
8080#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT(1 << 5) (1 << 5)
8081#define HDC_FORCE_NON_COHERENT(1 << 4) (1 << 4)
8082#define HDC_BARRIER_PERFORMANCE_DISABLE(1 << 10) (1 << 10)
8083
8084#define GEN8_HDC_CHICKEN1((const i915_reg_t){ .reg = (0x7304) }) _MMIO(0x7304)((const i915_reg_t){ .reg = (0x7304) })
8085
8086/* GEN9 chicken */
8087#define SLICE_ECO_CHICKEN0((const i915_reg_t){ .reg = (0x7308) }) _MMIO(0x7308)((const i915_reg_t){ .reg = (0x7308) })
8088#define PIXEL_MASK_CAMMING_DISABLE(1 << 14) (1 << 14)
8089
8090#define GEN9_WM_CHICKEN3((const i915_reg_t){ .reg = (0x5588) }) _MMIO(0x5588)((const i915_reg_t){ .reg = (0x5588) })
8091#define GEN9_FACTOR_IN_CLR_VAL_HIZ(1 << 9) (1 << 9)
8092
8093/* WaCatErrorRejectionIssue */
8094#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG((const i915_reg_t){ .reg = (0x9030) }) _MMIO(0x9030)((const i915_reg_t){ .reg = (0x9030) })
8095#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB(1 << 11) (1 << 11)
8096
8097#define HSW_SCRATCH1((const i915_reg_t){ .reg = (0xb038) }) _MMIO(0xb038)((const i915_reg_t){ .reg = (0xb038) })
8098#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE(1 << 27) (1 << 27)
8099
8100#define BDW_SCRATCH1((const i915_reg_t){ .reg = (0xb11c) }) _MMIO(0xb11c)((const i915_reg_t){ .reg = (0xb11c) })
8101#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE(1 << 2) (1 << 2)
8102
8103/*GEN11 chicken */
8104#define _PIPEA_CHICKEN0x70038 0x70038
8105#define _PIPEB_CHICKEN0x71038 0x71038
8106#define _PIPEC_CHICKEN0x72038 0x72038
8107#define PIPE_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038)
- (0x70038)))) }) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038)
- (0x70038)))) })
8108 _PIPEB_CHICKEN)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038)
- (0x70038)))) })
8109#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU(1 << 15) (1 << 15)
8110#define PER_PIXEL_ALPHA_BYPASS_EN(1 << 7) (1 << 7)
8111
8112#define FF_MODE2((const i915_reg_t){ .reg = (0x6604) }) _MMIO(0x6604)((const i915_reg_t){ .reg = (0x6604) })
8113#define FF_MODE2_GS_TIMER_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0)) REG_GENMASK(31, 24)((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0))
8114#define FF_MODE2_GS_TIMER_224((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (24))) + 0))))(224) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (24))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (24))) + 0))))(224) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(24))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (24))) + 0)))) + 0 + 0 + 0 + 0
))
8115#define FF_MODE2_TDS_TIMER_MASK((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(23, 16)((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))
8116#define FF_MODE2_TDS_TIMER_128((u32)((((typeof(((u32)((((~0UL) >> (64 - (23) - 1)) &
((~0UL) << (16))) + 0))))(4) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (23
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)((u32)((((typeof(((u32)((((~0UL) >> (64 - (23) - 1)) &
((~0UL) << (16))) + 0))))(4) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (23
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
8117
8118/* PCH */
8119
8120#define PCH_DISPLAY_BASE0xc0000u 0xc0000u
8121
8122/* south display engine interrupt: IBX */
8123#define SDE_AUDIO_POWER_D(1 << 27) (1 << 27)
8124#define SDE_AUDIO_POWER_C(1 << 26) (1 << 26)
8125#define SDE_AUDIO_POWER_B(1 << 25) (1 << 25)
8126#define SDE_AUDIO_POWER_SHIFT(25) (25)
8127#define SDE_AUDIO_POWER_MASK(7 << (25)) (7 << SDE_AUDIO_POWER_SHIFT(25))
8128#define SDE_GMBUS(1 << 24) (1 << 24)
8129#define SDE_AUDIO_HDCP_TRANSB(1 << 23) (1 << 23)
8130#define SDE_AUDIO_HDCP_TRANSA(1 << 22) (1 << 22)
8131#define SDE_AUDIO_HDCP_MASK(3 << 22) (3 << 22)
8132#define SDE_AUDIO_TRANSB(1 << 21) (1 << 21)
8133#define SDE_AUDIO_TRANSA(1 << 20) (1 << 20)
8134#define SDE_AUDIO_TRANS_MASK(3 << 20) (3 << 20)
8135#define SDE_POISON(1 << 19) (1 << 19)
8136/* 18 reserved */
8137#define SDE_FDI_RXB(1 << 17) (1 << 17)
8138#define SDE_FDI_RXA(1 << 16) (1 << 16)
8139#define SDE_FDI_MASK(3 << 16) (3 << 16)
8140#define SDE_AUXD(1 << 15) (1 << 15)
8141#define SDE_AUXC(1 << 14) (1 << 14)
8142#define SDE_AUXB(1 << 13) (1 << 13)
8143#define SDE_AUX_MASK(7 << 13) (7 << 13)
8144/* 12 reserved */
8145#define SDE_CRT_HOTPLUG(1 << 11) (1 << 11)
8146#define SDE_PORTD_HOTPLUG(1 << 10) (1 << 10)
8147#define SDE_PORTC_HOTPLUG(1 << 9) (1 << 9)
8148#define SDE_PORTB_HOTPLUG(1 << 8) (1 << 8)
8149#define SDE_SDVOB_HOTPLUG(1 << 6) (1 << 6)
8150#define SDE_HOTPLUG_MASK((1 << 11) | (1 << 6) | (1 << 8) | (1 <<
9) | (1 << 10)) (SDE_CRT_HOTPLUG(1 << 11) | \
8151 SDE_SDVOB_HOTPLUG(1 << 6) | \
8152 SDE_PORTB_HOTPLUG(1 << 8) | \
8153 SDE_PORTC_HOTPLUG(1 << 9) | \
8154 SDE_PORTD_HOTPLUG(1 << 10))
8155#define SDE_TRANSB_CRC_DONE(1 << 5) (1 << 5)
8156#define SDE_TRANSB_CRC_ERR(1 << 4) (1 << 4)
8157#define SDE_TRANSB_FIFO_UNDER(1 << 3) (1 << 3)
8158#define SDE_TRANSA_CRC_DONE(1 << 2) (1 << 2)
8159#define SDE_TRANSA_CRC_ERR(1 << 1) (1 << 1)
8160#define SDE_TRANSA_FIFO_UNDER(1 << 0) (1 << 0)
8161#define SDE_TRANS_MASK(0x3f) (0x3f)
8162
8163/* south display engine interrupt: CPT - CNP */
8164#define SDE_AUDIO_POWER_D_CPT(1 << 31) (1 << 31)
8165#define SDE_AUDIO_POWER_C_CPT(1 << 30) (1 << 30)
8166#define SDE_AUDIO_POWER_B_CPT(1 << 29) (1 << 29)
8167#define SDE_AUDIO_POWER_SHIFT_CPT29 29
8168#define SDE_AUDIO_POWER_MASK_CPT(7 << 29) (7 << 29)
8169#define SDE_AUXD_CPT(1 << 27) (1 << 27)
8170#define SDE_AUXC_CPT(1 << 26) (1 << 26)
8171#define SDE_AUXB_CPT(1 << 25) (1 << 25)
8172#define SDE_AUX_MASK_CPT(7 << 25) (7 << 25)
8173#define SDE_PORTE_HOTPLUG_SPT(1 << 25) (1 << 25)
8174#define SDE_PORTA_HOTPLUG_SPT(1 << 24) (1 << 24)
8175#define SDE_PORTD_HOTPLUG_CPT(1 << 23) (1 << 23)
8176#define SDE_PORTC_HOTPLUG_CPT(1 << 22) (1 << 22)
8177#define SDE_PORTB_HOTPLUG_CPT(1 << 21) (1 << 21)
8178#define SDE_CRT_HOTPLUG_CPT(1 << 19) (1 << 19)
8179#define SDE_SDVOB_HOTPLUG_CPT(1 << 18) (1 << 18)
8180#define SDE_HOTPLUG_MASK_CPT((1 << 19) | (1 << 18) | (1 << 23) | (1 <<
22) | (1 << 21)) (SDE_CRT_HOTPLUG_CPT(1 << 19) | \
8181 SDE_SDVOB_HOTPLUG_CPT(1 << 18) | \
8182 SDE_PORTD_HOTPLUG_CPT(1 << 23) | \
8183 SDE_PORTC_HOTPLUG_CPT(1 << 22) | \
8184 SDE_PORTB_HOTPLUG_CPT(1 << 21))
8185#define SDE_HOTPLUG_MASK_SPT((1 << 25) | (1 << 23) | (1 << 22) | (1 <<
21) | (1 << 24)) (SDE_PORTE_HOTPLUG_SPT(1 << 25) | \
8186 SDE_PORTD_HOTPLUG_CPT(1 << 23) | \
8187 SDE_PORTC_HOTPLUG_CPT(1 << 22) | \
8188 SDE_PORTB_HOTPLUG_CPT(1 << 21) | \
8189 SDE_PORTA_HOTPLUG_SPT(1 << 24))
8190#define SDE_GMBUS_CPT(1 << 17) (1 << 17)
8191#define SDE_ERROR_CPT(1 << 16) (1 << 16)
8192#define SDE_AUDIO_CP_REQ_C_CPT(1 << 10) (1 << 10)
8193#define SDE_AUDIO_CP_CHG_C_CPT(1 << 9) (1 << 9)
8194#define SDE_FDI_RXC_CPT(1 << 8) (1 << 8)
8195#define SDE_AUDIO_CP_REQ_B_CPT(1 << 6) (1 << 6)
8196#define SDE_AUDIO_CP_CHG_B_CPT(1 << 5) (1 << 5)
8197#define SDE_FDI_RXB_CPT(1 << 4) (1 << 4)
8198#define SDE_AUDIO_CP_REQ_A_CPT(1 << 2) (1 << 2)
8199#define SDE_AUDIO_CP_CHG_A_CPT(1 << 1) (1 << 1)
8200#define SDE_FDI_RXA_CPT(1 << 0) (1 << 0)
8201#define SDE_AUDIO_CP_REQ_CPT((1 << 10) | (1 << 6) | (1 << 2)) (SDE_AUDIO_CP_REQ_C_CPT(1 << 10) | \
8202 SDE_AUDIO_CP_REQ_B_CPT(1 << 6) | \
8203 SDE_AUDIO_CP_REQ_A_CPT(1 << 2))
8204#define SDE_AUDIO_CP_CHG_CPT((1 << 9) | (1 << 5) | (1 << 1)) (SDE_AUDIO_CP_CHG_C_CPT(1 << 9) | \
8205 SDE_AUDIO_CP_CHG_B_CPT(1 << 5) | \
8206 SDE_AUDIO_CP_CHG_A_CPT(1 << 1))
8207#define SDE_FDI_MASK_CPT((1 << 8) | (1 << 4) | (1 << 0)) (SDE_FDI_RXC_CPT(1 << 8) | \
8208 SDE_FDI_RXB_CPT(1 << 4) | \
8209 SDE_FDI_RXA_CPT(1 << 0))
8210
8211/* south display engine interrupt: ICP/TGP */
8212#define SDE_GMBUS_ICP(1 << 23) (1 << 23)
8213#define SDE_TC_HOTPLUG_ICP(tc_port)(1 << ((tc_port) + 24)) (1 << ((tc_port) + 24))
8214#define SDE_DDI_HOTPLUG_ICP(port)(1 << ((port) + 16)) (1 << ((port) + 16))
8215#define SDE_DDI_MASK_ICP((1 << ((PORT_B) + 16)) | (1 << ((PORT_A) + 16))) (SDE_DDI_HOTPLUG_ICP(PORT_B)(1 << ((PORT_B) + 16)) | \
8216 SDE_DDI_HOTPLUG_ICP(PORT_A)(1 << ((PORT_A) + 16)))
8217#define SDE_TC_MASK_ICP((1 << ((PORT_TC4) + 24)) | (1 << ((PORT_TC3) + 24
)) | (1 << ((PORT_TC2) + 24)) | (1 << ((PORT_TC1)
+ 24))) (SDE_TC_HOTPLUG_ICP(PORT_TC4)(1 << ((PORT_TC4) + 24)) | \
8218 SDE_TC_HOTPLUG_ICP(PORT_TC3)(1 << ((PORT_TC3) + 24)) | \
8219 SDE_TC_HOTPLUG_ICP(PORT_TC2)(1 << ((PORT_TC2) + 24)) | \
8220 SDE_TC_HOTPLUG_ICP(PORT_TC1)(1 << ((PORT_TC1) + 24)))
8221#define SDE_DDI_MASK_TGP((1 << ((PORT_C) + 16)) | (1 << ((PORT_B) + 16)) |
(1 << ((PORT_A) + 16))) (SDE_DDI_HOTPLUG_ICP(PORT_C)(1 << ((PORT_C) + 16)) | \
8222 SDE_DDI_HOTPLUG_ICP(PORT_B)(1 << ((PORT_B) + 16)) | \
8223 SDE_DDI_HOTPLUG_ICP(PORT_A)(1 << ((PORT_A) + 16)))
8224#define SDE_TC_MASK_TGP((1 << ((PORT_TC6) + 24)) | (1 << ((PORT_TC5) + 24
)) | (1 << ((PORT_TC4) + 24)) | (1 << ((PORT_TC3)
+ 24)) | (1 << ((PORT_TC2) + 24)) | (1 << ((PORT_TC1
) + 24))) (SDE_TC_HOTPLUG_ICP(PORT_TC6)(1 << ((PORT_TC6) + 24)) | \
8225 SDE_TC_HOTPLUG_ICP(PORT_TC5)(1 << ((PORT_TC5) + 24)) | \
8226 SDE_TC_HOTPLUG_ICP(PORT_TC4)(1 << ((PORT_TC4) + 24)) | \
8227 SDE_TC_HOTPLUG_ICP(PORT_TC3)(1 << ((PORT_TC3) + 24)) | \
8228 SDE_TC_HOTPLUG_ICP(PORT_TC2)(1 << ((PORT_TC2) + 24)) | \
8229 SDE_TC_HOTPLUG_ICP(PORT_TC1)(1 << ((PORT_TC1) + 24)))
8230
8231#define SDEISR((const i915_reg_t){ .reg = (0xc4000) }) _MMIO(0xc4000)((const i915_reg_t){ .reg = (0xc4000) })
8232#define SDEIMR((const i915_reg_t){ .reg = (0xc4004) }) _MMIO(0xc4004)((const i915_reg_t){ .reg = (0xc4004) })
8233#define SDEIIR((const i915_reg_t){ .reg = (0xc4008) }) _MMIO(0xc4008)((const i915_reg_t){ .reg = (0xc4008) })
8234#define SDEIER((const i915_reg_t){ .reg = (0xc400c) }) _MMIO(0xc400c)((const i915_reg_t){ .reg = (0xc400c) })
8235
8236#define SERR_INT((const i915_reg_t){ .reg = (0xc4040) }) _MMIO(0xc4040)((const i915_reg_t){ .reg = (0xc4040) })
8237#define SERR_INT_POISON(1 << 31) (1 << 31)
8238#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe)(1 << ((pipe) * 3)) (1 << ((pipe) * 3))
8239
8240/* digital port hotplug */
8241#define PCH_PORT_HOTPLUG((const i915_reg_t){ .reg = (0xc4030) }) _MMIO(0xc4030)((const i915_reg_t){ .reg = (0xc4030) }) /* SHOTPLUG_CTL */
8242#define PORTA_HOTPLUG_ENABLE(1 << 28) (1 << 28) /* LPT:LP+ & BXT */
8243#define BXT_DDIA_HPD_INVERT(1 << 27) (1 << 27)
8244#define PORTA_HOTPLUG_STATUS_MASK(3 << 24) (3 << 24) /* SPT+ & BXT */
8245#define PORTA_HOTPLUG_NO_DETECT(0 << 24) (0 << 24) /* SPT+ & BXT */
8246#define PORTA_HOTPLUG_SHORT_DETECT(1 << 24) (1 << 24) /* SPT+ & BXT */
8247#define PORTA_HOTPLUG_LONG_DETECT(2 << 24) (2 << 24) /* SPT+ & BXT */
8248#define PORTD_HOTPLUG_ENABLE(1 << 20) (1 << 20)
8249#define PORTD_PULSE_DURATION_2ms(0 << 18) (0 << 18) /* pre-LPT */
8250#define PORTD_PULSE_DURATION_4_5ms(1 << 18) (1 << 18) /* pre-LPT */
8251#define PORTD_PULSE_DURATION_6ms(2 << 18) (2 << 18) /* pre-LPT */
8252#define PORTD_PULSE_DURATION_100ms(3 << 18) (3 << 18) /* pre-LPT */
8253#define PORTD_PULSE_DURATION_MASK(3 << 18) (3 << 18) /* pre-LPT */
8254#define PORTD_HOTPLUG_STATUS_MASK(3 << 16) (3 << 16)
8255#define PORTD_HOTPLUG_NO_DETECT(0 << 16) (0 << 16)
8256#define PORTD_HOTPLUG_SHORT_DETECT(1 << 16) (1 << 16)
8257#define PORTD_HOTPLUG_LONG_DETECT(2 << 16) (2 << 16)
8258#define PORTC_HOTPLUG_ENABLE(1 << 12) (1 << 12)
8259#define BXT_DDIC_HPD_INVERT(1 << 11) (1 << 11)
8260#define PORTC_PULSE_DURATION_2ms(0 << 10) (0 << 10) /* pre-LPT */
8261#define PORTC_PULSE_DURATION_4_5ms(1 << 10) (1 << 10) /* pre-LPT */
8262#define PORTC_PULSE_DURATION_6ms(2 << 10) (2 << 10) /* pre-LPT */
8263#define PORTC_PULSE_DURATION_100ms(3 << 10) (3 << 10) /* pre-LPT */
8264#define PORTC_PULSE_DURATION_MASK(3 << 10) (3 << 10) /* pre-LPT */
8265#define PORTC_HOTPLUG_STATUS_MASK(3 << 8) (3 << 8)
8266#define PORTC_HOTPLUG_NO_DETECT(0 << 8) (0 << 8)
8267#define PORTC_HOTPLUG_SHORT_DETECT(1 << 8) (1 << 8)
8268#define PORTC_HOTPLUG_LONG_DETECT(2 << 8) (2 << 8)
8269#define PORTB_HOTPLUG_ENABLE(1 << 4) (1 << 4)
8270#define BXT_DDIB_HPD_INVERT(1 << 3) (1 << 3)
8271#define PORTB_PULSE_DURATION_2ms(0 << 2) (0 << 2) /* pre-LPT */
8272#define PORTB_PULSE_DURATION_4_5ms(1 << 2) (1 << 2) /* pre-LPT */
8273#define PORTB_PULSE_DURATION_6ms(2 << 2) (2 << 2) /* pre-LPT */
8274#define PORTB_PULSE_DURATION_100ms(3 << 2) (3 << 2) /* pre-LPT */
8275#define PORTB_PULSE_DURATION_MASK(3 << 2) (3 << 2) /* pre-LPT */
8276#define PORTB_HOTPLUG_STATUS_MASK(3 << 0) (3 << 0)
8277#define PORTB_HOTPLUG_NO_DETECT(0 << 0) (0 << 0)
8278#define PORTB_HOTPLUG_SHORT_DETECT(1 << 0) (1 << 0)
8279#define PORTB_HOTPLUG_LONG_DETECT(2 << 0) (2 << 0)
8280#define BXT_DDI_HPD_INVERT_MASK((1 << 27) | (1 << 3) | (1 << 11)) (BXT_DDIA_HPD_INVERT(1 << 27) | \
8281 BXT_DDIB_HPD_INVERT(1 << 3) | \
8282 BXT_DDIC_HPD_INVERT(1 << 11))
8283
8284#define PCH_PORT_HOTPLUG2((const i915_reg_t){ .reg = (0xc403C) }) _MMIO(0xc403C)((const i915_reg_t){ .reg = (0xc403C) }) /* SHOTPLUG_CTL2 SPT+ */
8285#define PORTE_HOTPLUG_ENABLE(1 << 4) (1 << 4)
8286#define PORTE_HOTPLUG_STATUS_MASK(3 << 0) (3 << 0)
8287#define PORTE_HOTPLUG_NO_DETECT(0 << 0) (0 << 0)
8288#define PORTE_HOTPLUG_SHORT_DETECT(1 << 0) (1 << 0)
8289#define PORTE_HOTPLUG_LONG_DETECT(2 << 0) (2 << 0)
8290
8291/* This register is a reuse of PCH_PORT_HOTPLUG register. The
8292 * functionality covered in PCH_PORT_HOTPLUG is split into
8293 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8294 */
8295
8296#define SHOTPLUG_CTL_DDI((const i915_reg_t){ .reg = (0xc4030) }) _MMIO(0xc4030)((const i915_reg_t){ .reg = (0xc4030) })
8297#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port)(0x8 << (4 * (port))) (0x8 << (4 * (port)))
8298#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)(0x3 << (4 * (port))) (0x3 << (4 * (port)))
8299#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)(0x0 << (4 * (port))) (0x0 << (4 * (port)))
8300#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)(0x1 << (4 * (port))) (0x1 << (4 * (port)))
8301#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)(0x2 << (4 * (port))) (0x2 << (4 * (port)))
8302#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)(0x3 << (4 * (port))) (0x3 << (4 * (port)))
8303
8304#define SHOTPLUG_CTL_TC((const i915_reg_t){ .reg = (0xc4034) }) _MMIO(0xc4034)((const i915_reg_t){ .reg = (0xc4034) })
8305#define ICP_TC_HPD_ENABLE(tc_port)(8 << (tc_port) * 4) (8 << (tc_port) * 4)
8306
8307#define SHPD_FILTER_CNT((const i915_reg_t){ .reg = (0xc4038) }) _MMIO(0xc4038)((const i915_reg_t){ .reg = (0xc4038) })
8308#define SHPD_FILTER_CNT_500_ADJ0x001D9 0x001D9
8309
8310/* Icelake DSC Rate Control Range Parameter Registers */
8311#define DSCA_RC_RANGE_PARAMETERS_0((const i915_reg_t){ .reg = (0x6B240) }) _MMIO(0x6B240)((const i915_reg_t){ .reg = (0x6B240) })
8312#define DSCA_RC_RANGE_PARAMETERS_0_UDW((const i915_reg_t){ .reg = (0x6B240 + 4) }) _MMIO(0x6B240 + 4)((const i915_reg_t){ .reg = (0x6B240 + 4) })
8313#define DSCC_RC_RANGE_PARAMETERS_0((const i915_reg_t){ .reg = (0x6BA40) }) _MMIO(0x6BA40)((const i915_reg_t){ .reg = (0x6BA40) })
8314#define DSCC_RC_RANGE_PARAMETERS_0_UDW((const i915_reg_t){ .reg = (0x6BA40 + 4) }) _MMIO(0x6BA40 + 4)((const i915_reg_t){ .reg = (0x6BA40 + 4) })
8315#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB(0x78208) (0x78208)
8316#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB(0x78208 + 4) (0x78208 + 4)
8317#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB(0x78308) (0x78308)
8318#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB(0x78308 + 4) (0x78308 + 4)
8319#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC(0x78408) (0x78408)
8320#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC(0x78408 + 4) (0x78408 + 4)
8321#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC(0x78508) (0x78508)
8322#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC(0x78508 + 4) (0x78508 + 4)
8323#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)((const i915_reg_t){ .reg = ((((0x78208)) + ((pipe) - PIPE_B)
* (((0x78408)) - ((0x78208))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78208)) + ((pipe) - PIPE_B)
* (((0x78408)) - ((0x78208))))) })
8324 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \((const i915_reg_t){ .reg = ((((0x78208)) + ((pipe) - PIPE_B)
* (((0x78408)) - ((0x78208))))) })
8325 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)((const i915_reg_t){ .reg = ((((0x78208)) + ((pipe) - PIPE_B)
* (((0x78408)) - ((0x78208))))) })
8326#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78208 + 4)) + ((pipe) - PIPE_B
) * (((0x78408 + 4)) - ((0x78208 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78208 + 4)) + ((pipe) - PIPE_B
) * (((0x78408 + 4)) - ((0x78208 + 4))))) })
8327 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78208 + 4)) + ((pipe) - PIPE_B
) * (((0x78408 + 4)) - ((0x78208 + 4))))) })
8328 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)((const i915_reg_t){ .reg = ((((0x78208 + 4)) + ((pipe) - PIPE_B
) * (((0x78408 + 4)) - ((0x78208 + 4))))) })
8329#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)((const i915_reg_t){ .reg = ((((0x78308)) + ((pipe) - PIPE_B)
* (((0x78508)) - ((0x78308))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78308)) + ((pipe) - PIPE_B)
* (((0x78508)) - ((0x78308))))) })
8330 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \((const i915_reg_t){ .reg = ((((0x78308)) + ((pipe) - PIPE_B)
* (((0x78508)) - ((0x78308))))) })
8331 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)((const i915_reg_t){ .reg = ((((0x78308)) + ((pipe) - PIPE_B)
* (((0x78508)) - ((0x78308))))) })
8332#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78308 + 4)) + ((pipe) - PIPE_B
) * (((0x78508 + 4)) - ((0x78308 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78308 + 4)) + ((pipe) - PIPE_B
) * (((0x78508 + 4)) - ((0x78308 + 4))))) })
8333 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78308 + 4)) + ((pipe) - PIPE_B
) * (((0x78508 + 4)) - ((0x78308 + 4))))) })
8334 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)((const i915_reg_t){ .reg = ((((0x78308 + 4)) + ((pipe) - PIPE_B
) * (((0x78508 + 4)) - ((0x78308 + 4))))) })
8335#define RC_BPG_OFFSET_SHIFT10 10
8336#define RC_MAX_QP_SHIFT5 5
8337#define RC_MIN_QP_SHIFT0 0
8338
8339#define DSCA_RC_RANGE_PARAMETERS_1((const i915_reg_t){ .reg = (0x6B248) }) _MMIO(0x6B248)((const i915_reg_t){ .reg = (0x6B248) })
8340#define DSCA_RC_RANGE_PARAMETERS_1_UDW((const i915_reg_t){ .reg = (0x6B248 + 4) }) _MMIO(0x6B248 + 4)((const i915_reg_t){ .reg = (0x6B248 + 4) })
8341#define DSCC_RC_RANGE_PARAMETERS_1((const i915_reg_t){ .reg = (0x6BA48) }) _MMIO(0x6BA48)((const i915_reg_t){ .reg = (0x6BA48) })
8342#define DSCC_RC_RANGE_PARAMETERS_1_UDW((const i915_reg_t){ .reg = (0x6BA48 + 4) }) _MMIO(0x6BA48 + 4)((const i915_reg_t){ .reg = (0x6BA48 + 4) })
8343#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB(0x78210) (0x78210)
8344#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB(0x78210 + 4) (0x78210 + 4)
8345#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB(0x78310) (0x78310)
8346#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB(0x78310 + 4) (0x78310 + 4)
8347#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC(0x78410) (0x78410)
8348#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC(0x78410 + 4) (0x78410 + 4)
8349#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC(0x78510) (0x78510)
8350#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC(0x78510 + 4) (0x78510 + 4)
8351#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)((const i915_reg_t){ .reg = ((((0x78210)) + ((pipe) - PIPE_B)
* (((0x78410)) - ((0x78210))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78210)) + ((pipe) - PIPE_B)
* (((0x78410)) - ((0x78210))))) })
8352 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \((const i915_reg_t){ .reg = ((((0x78210)) + ((pipe) - PIPE_B)
* (((0x78410)) - ((0x78210))))) })
8353 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)((const i915_reg_t){ .reg = ((((0x78210)) + ((pipe) - PIPE_B)
* (((0x78410)) - ((0x78210))))) })
8354#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78210 + 4)) + ((pipe) - PIPE_B
) * (((0x78410 + 4)) - ((0x78210 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78210 + 4)) + ((pipe) - PIPE_B
) * (((0x78410 + 4)) - ((0x78210 + 4))))) })
8355 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78210 + 4)) + ((pipe) - PIPE_B
) * (((0x78410 + 4)) - ((0x78210 + 4))))) })
8356 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)((const i915_reg_t){ .reg = ((((0x78210 + 4)) + ((pipe) - PIPE_B
) * (((0x78410 + 4)) - ((0x78210 + 4))))) })
8357#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)((const i915_reg_t){ .reg = ((((0x78310)) + ((pipe) - PIPE_B)
* (((0x78510)) - ((0x78310))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78310)) + ((pipe) - PIPE_B)
* (((0x78510)) - ((0x78310))))) })
8358 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \((const i915_reg_t){ .reg = ((((0x78310)) + ((pipe) - PIPE_B)
* (((0x78510)) - ((0x78310))))) })
8359 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)((const i915_reg_t){ .reg = ((((0x78310)) + ((pipe) - PIPE_B)
* (((0x78510)) - ((0x78310))))) })
8360#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78310 + 4)) + ((pipe) - PIPE_B
) * (((0x78510 + 4)) - ((0x78310 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78310 + 4)) + ((pipe) - PIPE_B
) * (((0x78510 + 4)) - ((0x78310 + 4))))) })
8361 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78310 + 4)) + ((pipe) - PIPE_B
) * (((0x78510 + 4)) - ((0x78310 + 4))))) })
8362 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)((const i915_reg_t){ .reg = ((((0x78310 + 4)) + ((pipe) - PIPE_B
) * (((0x78510 + 4)) - ((0x78310 + 4))))) })
8363
8364#define DSCA_RC_RANGE_PARAMETERS_2((const i915_reg_t){ .reg = (0x6B250) }) _MMIO(0x6B250)((const i915_reg_t){ .reg = (0x6B250) })
8365#define DSCA_RC_RANGE_PARAMETERS_2_UDW((const i915_reg_t){ .reg = (0x6B250 + 4) }) _MMIO(0x6B250 + 4)((const i915_reg_t){ .reg = (0x6B250 + 4) })
8366#define DSCC_RC_RANGE_PARAMETERS_2((const i915_reg_t){ .reg = (0x6BA50) }) _MMIO(0x6BA50)((const i915_reg_t){ .reg = (0x6BA50) })
8367#define DSCC_RC_RANGE_PARAMETERS_2_UDW((const i915_reg_t){ .reg = (0x6BA50 + 4) }) _MMIO(0x6BA50 + 4)((const i915_reg_t){ .reg = (0x6BA50 + 4) })
8368#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB(0x78218) (0x78218)
8369#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB(0x78218 + 4) (0x78218 + 4)
8370#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB(0x78318) (0x78318)
8371#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB(0x78318 + 4) (0x78318 + 4)
8372#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC(0x78418) (0x78418)
8373#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC(0x78418 + 4) (0x78418 + 4)
8374#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC(0x78518) (0x78518)
8375#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC(0x78518 + 4) (0x78518 + 4)
8376#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)((const i915_reg_t){ .reg = ((((0x78218)) + ((pipe) - PIPE_B)
* (((0x78418)) - ((0x78218))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78218)) + ((pipe) - PIPE_B)
* (((0x78418)) - ((0x78218))))) })
8377 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \((const i915_reg_t){ .reg = ((((0x78218)) + ((pipe) - PIPE_B)
* (((0x78418)) - ((0x78218))))) })
8378 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)((const i915_reg_t){ .reg = ((((0x78218)) + ((pipe) - PIPE_B)
* (((0x78418)) - ((0x78218))))) })
8379#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78218 + 4)) + ((pipe) - PIPE_B
) * (((0x78418 + 4)) - ((0x78218 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78218 + 4)) + ((pipe) - PIPE_B
) * (((0x78418 + 4)) - ((0x78218 + 4))))) })
8380 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78218 + 4)) + ((pipe) - PIPE_B
) * (((0x78418 + 4)) - ((0x78218 + 4))))) })
8381 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)((const i915_reg_t){ .reg = ((((0x78218 + 4)) + ((pipe) - PIPE_B
) * (((0x78418 + 4)) - ((0x78218 + 4))))) })
8382#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)((const i915_reg_t){ .reg = ((((0x78318)) + ((pipe) - PIPE_B)
* (((0x78518)) - ((0x78318))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78318)) + ((pipe) - PIPE_B)
* (((0x78518)) - ((0x78318))))) })
8383 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \((const i915_reg_t){ .reg = ((((0x78318)) + ((pipe) - PIPE_B)
* (((0x78518)) - ((0x78318))))) })
8384 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)((const i915_reg_t){ .reg = ((((0x78318)) + ((pipe) - PIPE_B)
* (((0x78518)) - ((0x78318))))) })
8385#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78318 + 4)) + ((pipe) - PIPE_B
) * (((0x78518 + 4)) - ((0x78318 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78318 + 4)) + ((pipe) - PIPE_B
) * (((0x78518 + 4)) - ((0x78318 + 4))))) })
8386 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78318 + 4)) + ((pipe) - PIPE_B
) * (((0x78518 + 4)) - ((0x78318 + 4))))) })
8387 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)((const i915_reg_t){ .reg = ((((0x78318 + 4)) + ((pipe) - PIPE_B
) * (((0x78518 + 4)) - ((0x78318 + 4))))) })
8388
8389#define DSCA_RC_RANGE_PARAMETERS_3((const i915_reg_t){ .reg = (0x6B258) }) _MMIO(0x6B258)((const i915_reg_t){ .reg = (0x6B258) })
8390#define DSCA_RC_RANGE_PARAMETERS_3_UDW((const i915_reg_t){ .reg = (0x6B258 + 4) }) _MMIO(0x6B258 + 4)((const i915_reg_t){ .reg = (0x6B258 + 4) })
8391#define DSCC_RC_RANGE_PARAMETERS_3((const i915_reg_t){ .reg = (0x6BA58) }) _MMIO(0x6BA58)((const i915_reg_t){ .reg = (0x6BA58) })
8392#define DSCC_RC_RANGE_PARAMETERS_3_UDW((const i915_reg_t){ .reg = (0x6BA58 + 4) }) _MMIO(0x6BA58 + 4)((const i915_reg_t){ .reg = (0x6BA58 + 4) })
8393#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB(0x78220) (0x78220)
8394#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB(0x78220 + 4) (0x78220 + 4)
8395#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB(0x78320) (0x78320)
8396#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB(0x78320 + 4) (0x78320 + 4)
8397#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC(0x78420) (0x78420)
8398#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC(0x78420 + 4) (0x78420 + 4)
8399#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC(0x78520) (0x78520)
8400#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC(0x78520 + 4) (0x78520 + 4)
8401#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)((const i915_reg_t){ .reg = ((((0x78220)) + ((pipe) - PIPE_B)
* (((0x78420)) - ((0x78220))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78220)) + ((pipe) - PIPE_B)
* (((0x78420)) - ((0x78220))))) })
8402 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \((const i915_reg_t){ .reg = ((((0x78220)) + ((pipe) - PIPE_B)
* (((0x78420)) - ((0x78220))))) })
8403 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)((const i915_reg_t){ .reg = ((((0x78220)) + ((pipe) - PIPE_B)
* (((0x78420)) - ((0x78220))))) })
8404#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78220 + 4)) + ((pipe) - PIPE_B
) * (((0x78420 + 4)) - ((0x78220 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78220 + 4)) + ((pipe) - PIPE_B
) * (((0x78420 + 4)) - ((0x78220 + 4))))) })
8405 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78220 + 4)) + ((pipe) - PIPE_B
) * (((0x78420 + 4)) - ((0x78220 + 4))))) })
8406 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)((const i915_reg_t){ .reg = ((((0x78220 + 4)) + ((pipe) - PIPE_B
) * (((0x78420 + 4)) - ((0x78220 + 4))))) })
8407#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)((const i915_reg_t){ .reg = ((((0x78320)) + ((pipe) - PIPE_B)
* (((0x78520)) - ((0x78320))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78320)) + ((pipe) - PIPE_B)
* (((0x78520)) - ((0x78320))))) })
8408 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \((const i915_reg_t){ .reg = ((((0x78320)) + ((pipe) - PIPE_B)
* (((0x78520)) - ((0x78320))))) })
8409 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)((const i915_reg_t){ .reg = ((((0x78320)) + ((pipe) - PIPE_B)
* (((0x78520)) - ((0x78320))))) })
8410#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78320 + 4)) + ((pipe) - PIPE_B
) * (((0x78520 + 4)) - ((0x78320 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78320 + 4)) + ((pipe) - PIPE_B
) * (((0x78520 + 4)) - ((0x78320 + 4))))) })
8411 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78320 + 4)) + ((pipe) - PIPE_B
) * (((0x78520 + 4)) - ((0x78320 + 4))))) })
8412 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)((const i915_reg_t){ .reg = ((((0x78320 + 4)) + ((pipe) - PIPE_B
) * (((0x78520 + 4)) - ((0x78320 + 4))))) })
8413
8414#define ICP_TC_HPD_LONG_DETECT(tc_port)(2 << (tc_port) * 4) (2 << (tc_port) * 4)
8415#define ICP_TC_HPD_SHORT_DETECT(tc_port)(1 << (tc_port) * 4) (1 << (tc_port) * 4)
8416
8417#define ICP_DDI_HPD_ENABLE_MASK((0x8 << (4 * (PORT_B))) | (0x8 << (4 * (PORT_A))
)) (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B)(0x8 << (4 * (PORT_B))) | \
8418 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)(0x8 << (4 * (PORT_A))))
8419#define ICP_TC_HPD_ENABLE_MASK((8 << (PORT_TC4) * 4) | (8 << (PORT_TC3) * 4) | (
8 << (PORT_TC2) * 4) | (8 << (PORT_TC1) * 4)) (ICP_TC_HPD_ENABLE(PORT_TC4)(8 << (PORT_TC4) * 4) | \
8420 ICP_TC_HPD_ENABLE(PORT_TC3)(8 << (PORT_TC3) * 4) | \
8421 ICP_TC_HPD_ENABLE(PORT_TC2)(8 << (PORT_TC2) * 4) | \
8422 ICP_TC_HPD_ENABLE(PORT_TC1)(8 << (PORT_TC1) * 4))
8423#define TGP_DDI_HPD_ENABLE_MASK((0x8 << (4 * (PORT_C))) | (0x8 << (4 * (PORT_B))
) | (0x8 << (4 * (PORT_A)))) (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C)(0x8 << (4 * (PORT_C))) | \
8424 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B)(0x8 << (4 * (PORT_B))) | \
8425 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)(0x8 << (4 * (PORT_A))))
8426#define TGP_TC_HPD_ENABLE_MASK((8 << (PORT_TC6) * 4) | (8 << (PORT_TC5) * 4) | (
(8 << (PORT_TC4) * 4) | (8 << (PORT_TC3) * 4) | (
8 << (PORT_TC2) * 4) | (8 << (PORT_TC1) * 4))) (ICP_TC_HPD_ENABLE(PORT_TC6)(8 << (PORT_TC6) * 4) | \
8427 ICP_TC_HPD_ENABLE(PORT_TC5)(8 << (PORT_TC5) * 4) | \
8428 ICP_TC_HPD_ENABLE_MASK((8 << (PORT_TC4) * 4) | (8 << (PORT_TC3) * 4) | (
8 << (PORT_TC2) * 4) | (8 << (PORT_TC1) * 4)))
8429
8430#define _PCH_DPLL_A0xc6014 0xc6014
8431#define _PCH_DPLL_B0xc6018 0xc6018
8432#define PCH_DPLL(pll)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6014 : 0xc6018) }
) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6014 : 0xc6018) }
)
8433
8434#define _PCH_FPA00xc6040 0xc6040
8435#define FP_CB_TUNE(0x3 << 22) (0x3 << 22)
8436#define _PCH_FPA10xc6044 0xc6044
8437#define _PCH_FPB00xc6048 0xc6048
8438#define _PCH_FPB10xc604c 0xc604c
8439#define PCH_FP0(pll)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6040 : 0xc6048) }
) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6040 : 0xc6048) }
)
8440#define PCH_FP1(pll)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6044 : 0xc604c) }
) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)((const i915_reg_t){ .reg = ((pll) == 0 ? 0xc6044 : 0xc604c) }
)
8441
8442#define PCH_DPLL_TEST((const i915_reg_t){ .reg = (0xc606c) }) _MMIO(0xc606c)((const i915_reg_t){ .reg = (0xc606c) })
8443
8444#define PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }) _MMIO(0xC6200)((const i915_reg_t){ .reg = (0xC6200) })
8445#define DREF_CONTROL_MASK0x7fc3 0x7fc3
8446#define DREF_CPU_SOURCE_OUTPUT_DISABLE(0 << 13) (0 << 13)
8447#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD(2 << 13) (2 << 13)
8448#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD(3 << 13) (3 << 13)
8449#define DREF_CPU_SOURCE_OUTPUT_MASK(3 << 13) (3 << 13)
8450#define DREF_SSC_SOURCE_DISABLE(0 << 11) (0 << 11)
8451#define DREF_SSC_SOURCE_ENABLE(2 << 11) (2 << 11)
8452#define DREF_SSC_SOURCE_MASK(3 << 11) (3 << 11)
8453#define DREF_NONSPREAD_SOURCE_DISABLE(0 << 9) (0 << 9)
8454#define DREF_NONSPREAD_CK505_ENABLE(1 << 9) (1 << 9)
8455#define DREF_NONSPREAD_SOURCE_ENABLE(2 << 9) (2 << 9)
8456#define DREF_NONSPREAD_SOURCE_MASK(3 << 9) (3 << 9)
8457#define DREF_SUPERSPREAD_SOURCE_DISABLE(0 << 7) (0 << 7)
8458#define DREF_SUPERSPREAD_SOURCE_ENABLE(2 << 7) (2 << 7)
8459#define DREF_SUPERSPREAD_SOURCE_MASK(3 << 7) (3 << 7)
8460#define DREF_SSC4_DOWNSPREAD(0 << 6) (0 << 6)
8461#define DREF_SSC4_CENTERSPREAD(1 << 6) (1 << 6)
8462#define DREF_SSC1_DISABLE(0 << 1) (0 << 1)
8463#define DREF_SSC1_ENABLE(1 << 1) (1 << 1)
8464#define DREF_SSC4_DISABLE(0) (0)
8465#define DREF_SSC4_ENABLE(1) (1)
8466
8467#define PCH_RAWCLK_FREQ((const i915_reg_t){ .reg = (0xc6204) }) _MMIO(0xc6204)((const i915_reg_t){ .reg = (0xc6204) })
8468#define FDL_TP1_TIMER_SHIFT12 12
8469#define FDL_TP1_TIMER_MASK(3 << 12) (3 << 12)
8470#define FDL_TP2_TIMER_SHIFT10 10
8471#define FDL_TP2_TIMER_MASK(3 << 10) (3 << 10)
8472#define RAWCLK_FREQ_MASK0x3ff 0x3ff
8473#define CNP_RAWCLK_DIV_MASK(0x3ff << 16) (0x3ff << 16)
8474#define CNP_RAWCLK_DIV(div)((div) << 16) ((div) << 16)
8475#define CNP_RAWCLK_FRAC_MASK(0xf << 26) (0xf << 26)
8476#define CNP_RAWCLK_DEN(den)((den) << 26) ((den) << 26)
8477#define ICP_RAWCLK_NUM(num)((num) << 11) ((num) << 11)
8478
8479#define PCH_DPLL_TMR_CFG((const i915_reg_t){ .reg = (0xc6208) }) _MMIO(0xc6208)((const i915_reg_t){ .reg = (0xc6208) })
8480
8481#define PCH_SSC4_PARMS((const i915_reg_t){ .reg = (0xc6210) }) _MMIO(0xc6210)((const i915_reg_t){ .reg = (0xc6210) })
8482#define PCH_SSC4_AUX_PARMS((const i915_reg_t){ .reg = (0xc6214) }) _MMIO(0xc6214)((const i915_reg_t){ .reg = (0xc6214) })
8483
8484#define PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) }) _MMIO(0xc7000)((const i915_reg_t){ .reg = (0xc7000) })
8485#define TRANS_DPLLB_SEL(pipe)(1 << ((pipe) * 4)) (1 << ((pipe) * 4))
8486#define TRANS_DPLLA_SEL(pipe)0 0
8487#define TRANS_DPLL_ENABLE(pipe)(1 << ((pipe) * 4 + 3)) (1 << ((pipe) * 4 + 3))
8488
8489/* transcoder */
8490
8491#define _PCH_TRANS_HTOTAL_A0xe0000 0xe0000
8492#define TRANS_HTOTAL_SHIFT16 16
8493#define TRANS_HACTIVE_SHIFT0 0
8494#define _PCH_TRANS_HBLANK_A0xe0004 0xe0004
8495#define TRANS_HBLANK_END_SHIFT16 16
8496#define TRANS_HBLANK_START_SHIFT0 0
8497#define _PCH_TRANS_HSYNC_A0xe0008 0xe0008
8498#define TRANS_HSYNC_END_SHIFT16 16
8499#define TRANS_HSYNC_START_SHIFT0 0
8500#define _PCH_TRANS_VTOTAL_A0xe000c 0xe000c
8501#define TRANS_VTOTAL_SHIFT16 16
8502#define TRANS_VACTIVE_SHIFT0 0
8503#define _PCH_TRANS_VBLANK_A0xe0010 0xe0010
8504#define TRANS_VBLANK_END_SHIFT16 16
8505#define TRANS_VBLANK_START_SHIFT0 0
8506#define _PCH_TRANS_VSYNC_A0xe0014 0xe0014
8507#define TRANS_VSYNC_END_SHIFT16 16
8508#define TRANS_VSYNC_START_SHIFT0 0
8509#define _PCH_TRANS_VSYNCSHIFT_A0xe0028 0xe0028
8510
8511#define _PCH_TRANSA_DATA_M10xe0030 0xe0030
8512#define _PCH_TRANSA_DATA_N10xe0034 0xe0034
8513#define _PCH_TRANSA_DATA_M20xe0038 0xe0038
8514#define _PCH_TRANSA_DATA_N20xe003c 0xe003c
8515#define _PCH_TRANSA_LINK_M10xe0040 0xe0040
8516#define _PCH_TRANSA_LINK_N10xe0044 0xe0044
8517#define _PCH_TRANSA_LINK_M20xe0048 0xe0048
8518#define _PCH_TRANSA_LINK_N20xe004c 0xe004c
8519
8520/* Per-transcoder DIP controls (PCH) */
8521#define _VIDEO_DIP_CTL_A0xe0200 0xe0200
8522#define _VIDEO_DIP_DATA_A0xe0208 0xe0208
8523#define _VIDEO_DIP_GCP_A0xe0210 0xe0210
8524#define GCP_COLOR_INDICATION(1 << 2) (1 << 2)
8525#define GCP_DEFAULT_PHASE_ENABLE(1 << 1) (1 << 1)
8526#define GCP_AV_MUTE(1 << 0) (1 << 0)
8527
8528#define _VIDEO_DIP_CTL_B0xe1200 0xe1200
8529#define _VIDEO_DIP_DATA_B0xe1208 0xe1208
8530#define _VIDEO_DIP_GCP_B0xe1210 0xe1210
8531
8532#define TVIDEO_DIP_CTL(pipe)((const i915_reg_t){ .reg = (((0xe0200) + (pipe) * ((0xe1200)
- (0xe0200)))) }) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)((const i915_reg_t){ .reg = (((0xe0200) + (pipe) * ((0xe1200)
- (0xe0200)))) })
8533#define TVIDEO_DIP_DATA(pipe)((const i915_reg_t){ .reg = (((0xe0208) + (pipe) * ((0xe1208)
- (0xe0208)))) }) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)((const i915_reg_t){ .reg = (((0xe0208) + (pipe) * ((0xe1208)
- (0xe0208)))) })
8534#define TVIDEO_DIP_GCP(pipe)((const i915_reg_t){ .reg = (((0xe0210) + (pipe) * ((0xe1210)
- (0xe0210)))) }) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)((const i915_reg_t){ .reg = (((0xe0210) + (pipe) * ((0xe1210)
- (0xe0210)))) })
8535
8536/* Per-transcoder DIP controls (VLV) */
8537#define _VLV_VIDEO_DIP_CTL_A(0x180000 + 0x60200) (VLV_DISPLAY_BASE0x180000 + 0x60200)
8538#define _VLV_VIDEO_DIP_DATA_A(0x180000 + 0x60208) (VLV_DISPLAY_BASE0x180000 + 0x60208)
8539#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A(0x180000 + 0x60210) (VLV_DISPLAY_BASE0x180000 + 0x60210)
8540
8541#define _VLV_VIDEO_DIP_CTL_B(0x180000 + 0x61170) (VLV_DISPLAY_BASE0x180000 + 0x61170)
8542#define _VLV_VIDEO_DIP_DATA_B(0x180000 + 0x61174) (VLV_DISPLAY_BASE0x180000 + 0x61174)
8543#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B(0x180000 + 0x61178) (VLV_DISPLAY_BASE0x180000 + 0x61178)
8544
8545#define _CHV_VIDEO_DIP_CTL_C(0x180000 + 0x611f0) (VLV_DISPLAY_BASE0x180000 + 0x611f0)
8546#define _CHV_VIDEO_DIP_DATA_C(0x180000 + 0x611f4) (VLV_DISPLAY_BASE0x180000 + 0x611f4)
8547#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C(0x180000 + 0x611f8) (VLV_DISPLAY_BASE0x180000 + 0x611f8)
8548
8549#define VLV_TVIDEO_DIP_CTL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60200
), (0x180000 + 0x61170), (0x180000 + 0x611f0) })[(pipe)])) }) \
8550 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60200
), (0x180000 + 0x61170), (0x180000 + 0x611f0) })[(pipe)])) })
8551 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60200
), (0x180000 + 0x61170), (0x180000 + 0x611f0) })[(pipe)])) })
8552#define VLV_TVIDEO_DIP_DATA(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60208
), (0x180000 + 0x61174), (0x180000 + 0x611f4) })[(pipe)])) }) \
8553 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60208
), (0x180000 + 0x61174), (0x180000 + 0x611f4) })[(pipe)])) })
8554 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60208
), (0x180000 + 0x61174), (0x180000 + 0x611f4) })[(pipe)])) })
8555#define VLV_TVIDEO_DIP_GCP(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60210
), (0x180000 + 0x61178), (0x180000 + 0x611f8) })[(pipe)])) }) \
8556 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60210
), (0x180000 + 0x61178), (0x180000 + 0x611f8) })[(pipe)])) })
8557 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)((const i915_reg_t){ .reg = ((((const u32 []){ (0x180000 + 0x60210
), (0x180000 + 0x61178), (0x180000 + 0x611f8) })[(pipe)])) })
8558
8559/* Haswell DIP controls */
8560
8561#define _HSW_VIDEO_DIP_CTL_A0x60200 0x60200
8562#define _HSW_VIDEO_DIP_AVI_DATA_A0x60220 0x60220
8563#define _HSW_VIDEO_DIP_VS_DATA_A0x60260 0x60260
8564#define _HSW_VIDEO_DIP_SPD_DATA_A0x602A0 0x602A0
8565#define _HSW_VIDEO_DIP_GMP_DATA_A0x602E0 0x602E0
8566#define _HSW_VIDEO_DIP_VSC_DATA_A0x60320 0x60320
8567#define _GLK_VIDEO_DIP_DRM_DATA_A0x60440 0x60440
8568#define _HSW_VIDEO_DIP_AVI_ECC_A0x60240 0x60240
8569#define _HSW_VIDEO_DIP_VS_ECC_A0x60280 0x60280
8570#define _HSW_VIDEO_DIP_SPD_ECC_A0x602C0 0x602C0
8571#define _HSW_VIDEO_DIP_GMP_ECC_A0x60300 0x60300
8572#define _HSW_VIDEO_DIP_VSC_ECC_A0x60344 0x60344
8573#define _HSW_VIDEO_DIP_GCP_A0x60210 0x60210
8574
8575#define _HSW_VIDEO_DIP_CTL_B0x61200 0x61200
8576#define _HSW_VIDEO_DIP_AVI_DATA_B0x61220 0x61220
8577#define _HSW_VIDEO_DIP_VS_DATA_B0x61260 0x61260
8578#define _HSW_VIDEO_DIP_SPD_DATA_B0x612A0 0x612A0
8579#define _HSW_VIDEO_DIP_GMP_DATA_B0x612E0 0x612E0
8580#define _HSW_VIDEO_DIP_VSC_DATA_B0x61320 0x61320
8581#define _GLK_VIDEO_DIP_DRM_DATA_B0x61440 0x61440
8582#define _HSW_VIDEO_DIP_BVI_ECC_B0x61240 0x61240
8583#define _HSW_VIDEO_DIP_VS_ECC_B0x61280 0x61280
8584#define _HSW_VIDEO_DIP_SPD_ECC_B0x612C0 0x612C0
8585#define _HSW_VIDEO_DIP_GMP_ECC_B0x61300 0x61300
8586#define _HSW_VIDEO_DIP_VSC_ECC_B0x61344 0x61344
8587#define _HSW_VIDEO_DIP_GCP_B0x61210 0x61210
8588
8589/* Icelake PPS_DATA and _ECC DIP Registers.
8590 * These are available for transcoders B,C and eDP.
8591 * Adding the _A so as to reuse the _MMIO_TRANS2
8592 * definition, with which it offsets to the right location.
8593 */
8594
8595#define _ICL_VIDEO_DIP_PPS_DATA_A0x60350 0x60350
8596#define _ICL_VIDEO_DIP_PPS_DATA_B0x61350 0x61350
8597#define _ICL_VIDEO_DIP_PPS_ECC_A0x603D4 0x603D4
8598#define _ICL_VIDEO_DIP_PPS_ECC_B0x613D4 0x613D4
8599
8600#define HSW_TVIDEO_DIP_CTL(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60200) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60200) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
8601#define HSW_TVIDEO_DIP_GCP(trans)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60210) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60210) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
8602#define HSW_TVIDEO_DIP_AVI_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60220 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60220 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8603#define HSW_TVIDEO_DIP_VS_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60260 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60260 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8604#define HSW_TVIDEO_DIP_SPD_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x602A0 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x602A0 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8605#define HSW_TVIDEO_DIP_GMP_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x602E0 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x602E0 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8606#define HSW_TVIDEO_DIP_VSC_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60320 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60320 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8607#define GLK_TVIDEO_DIP_DRM_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60440 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60440 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8608#define ICL_VIDEO_DIP_PPS_DATA(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60350 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60350 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8609#define ICL_VIDEO_DIP_PPS_ECC(trans, i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x603D4 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) }) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(trans)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x603D4 + (i) * 4) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
8610
8611#define _HSW_STEREO_3D_CTL_A0x70020 0x70020
8612#define S3D_ENABLE(1 << 31) (1 << 31)
8613#define _HSW_STEREO_3D_CTL_B0x71020 0x71020
8614
8615#define HSW_STEREO_3D_CTL(trans)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[trans] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70020) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[trans] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70020) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
8616
8617#define _PCH_TRANS_HTOTAL_B0xe1000 0xe1000
8618#define _PCH_TRANS_HBLANK_B0xe1004 0xe1004
8619#define _PCH_TRANS_HSYNC_B0xe1008 0xe1008
8620#define _PCH_TRANS_VTOTAL_B0xe100c 0xe100c
8621#define _PCH_TRANS_VBLANK_B0xe1010 0xe1010
8622#define _PCH_TRANS_VSYNC_B0xe1014 0xe1014
8623#define _PCH_TRANS_VSYNCSHIFT_B0xe1028 0xe1028
8624
8625#define PCH_TRANS_HTOTAL(pipe)((const i915_reg_t){ .reg = (((0xe0000) + (pipe) * ((0xe1000)
- (0xe0000)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)((const i915_reg_t){ .reg = (((0xe0000) + (pipe) * ((0xe1000)
- (0xe0000)))) })
8626#define PCH_TRANS_HBLANK(pipe)((const i915_reg_t){ .reg = (((0xe0004) + (pipe) * ((0xe1004)
- (0xe0004)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)((const i915_reg_t){ .reg = (((0xe0004) + (pipe) * ((0xe1004)
- (0xe0004)))) })
8627#define PCH_TRANS_HSYNC(pipe)((const i915_reg_t){ .reg = (((0xe0008) + (pipe) * ((0xe1008)
- (0xe0008)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)((const i915_reg_t){ .reg = (((0xe0008) + (pipe) * ((0xe1008)
- (0xe0008)))) })
8628#define PCH_TRANS_VTOTAL(pipe)((const i915_reg_t){ .reg = (((0xe000c) + (pipe) * ((0xe100c)
- (0xe000c)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)((const i915_reg_t){ .reg = (((0xe000c) + (pipe) * ((0xe100c)
- (0xe000c)))) })
8629#define PCH_TRANS_VBLANK(pipe)((const i915_reg_t){ .reg = (((0xe0010) + (pipe) * ((0xe1010)
- (0xe0010)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)((const i915_reg_t){ .reg = (((0xe0010) + (pipe) * ((0xe1010)
- (0xe0010)))) })
8630#define PCH_TRANS_VSYNC(pipe)((const i915_reg_t){ .reg = (((0xe0014) + (pipe) * ((0xe1014)
- (0xe0014)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)((const i915_reg_t){ .reg = (((0xe0014) + (pipe) * ((0xe1014)
- (0xe0014)))) })
8631#define PCH_TRANS_VSYNCSHIFT(pipe)((const i915_reg_t){ .reg = (((0xe0028) + (pipe) * ((0xe1028)
- (0xe0028)))) }) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)((const i915_reg_t){ .reg = (((0xe0028) + (pipe) * ((0xe1028)
- (0xe0028)))) })
8632
8633#define _PCH_TRANSB_DATA_M10xe1030 0xe1030
8634#define _PCH_TRANSB_DATA_N10xe1034 0xe1034
8635#define _PCH_TRANSB_DATA_M20xe1038 0xe1038
8636#define _PCH_TRANSB_DATA_N20xe103c 0xe103c
8637#define _PCH_TRANSB_LINK_M10xe1040 0xe1040
8638#define _PCH_TRANSB_LINK_N10xe1044 0xe1044
8639#define _PCH_TRANSB_LINK_M20xe1048 0xe1048
8640#define _PCH_TRANSB_LINK_N20xe104c 0xe104c
8641
8642#define PCH_TRANS_DATA_M1(pipe)((const i915_reg_t){ .reg = (((0xe0030) + (pipe) * ((0xe1030)
- (0xe0030)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)((const i915_reg_t){ .reg = (((0xe0030) + (pipe) * ((0xe1030)
- (0xe0030)))) })
8643#define PCH_TRANS_DATA_N1(pipe)((const i915_reg_t){ .reg = (((0xe0034) + (pipe) * ((0xe1034)
- (0xe0034)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)((const i915_reg_t){ .reg = (((0xe0034) + (pipe) * ((0xe1034)
- (0xe0034)))) })
8644#define PCH_TRANS_DATA_M2(pipe)((const i915_reg_t){ .reg = (((0xe0038) + (pipe) * ((0xe1038)
- (0xe0038)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)((const i915_reg_t){ .reg = (((0xe0038) + (pipe) * ((0xe1038)
- (0xe0038)))) })
8645#define PCH_TRANS_DATA_N2(pipe)((const i915_reg_t){ .reg = (((0xe003c) + (pipe) * ((0xe103c)
- (0xe003c)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)((const i915_reg_t){ .reg = (((0xe003c) + (pipe) * ((0xe103c)
- (0xe003c)))) })
8646#define PCH_TRANS_LINK_M1(pipe)((const i915_reg_t){ .reg = (((0xe0040) + (pipe) * ((0xe1040)
- (0xe0040)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)((const i915_reg_t){ .reg = (((0xe0040) + (pipe) * ((0xe1040)
- (0xe0040)))) })
8647#define PCH_TRANS_LINK_N1(pipe)((const i915_reg_t){ .reg = (((0xe0044) + (pipe) * ((0xe1044)
- (0xe0044)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)((const i915_reg_t){ .reg = (((0xe0044) + (pipe) * ((0xe1044)
- (0xe0044)))) })
8648#define PCH_TRANS_LINK_M2(pipe)((const i915_reg_t){ .reg = (((0xe0048) + (pipe) * ((0xe1048)
- (0xe0048)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)((const i915_reg_t){ .reg = (((0xe0048) + (pipe) * ((0xe1048)
- (0xe0048)))) })
8649#define PCH_TRANS_LINK_N2(pipe)((const i915_reg_t){ .reg = (((0xe004c) + (pipe) * ((0xe104c)
- (0xe004c)))) }) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)((const i915_reg_t){ .reg = (((0xe004c) + (pipe) * ((0xe104c)
- (0xe004c)))) })
8650
8651#define _PCH_TRANSACONF0xf0008 0xf0008
8652#define _PCH_TRANSBCONF0xf1008 0xf1008
8653#define PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008)
- (0xf0008)))) }) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008)
- (0xf0008)))) })
8654#define LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) }) PCH_TRANSCONF(PIPE_A)((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) }) /* lpt has only one transcoder */
8655#define TRANS_DISABLE(0 << 31) (0 << 31)
8656#define TRANS_ENABLE(1 << 31) (1 << 31)
8657#define TRANS_STATE_MASK(1 << 30) (1 << 30)
8658#define TRANS_STATE_DISABLE(0 << 30) (0 << 30)
8659#define TRANS_STATE_ENABLE(1 << 30) (1 << 30)
8660#define TRANS_FRAME_START_DELAY_MASK(3 << 27) (3 << 27) /* ibx */
8661#define TRANS_FRAME_START_DELAY(x)((x) << 27) ((x) << 27) /* ibx: 0-3 */
8662#define TRANS_INTERLACE_MASK(7 << 21) (7 << 21)
8663#define TRANS_PROGRESSIVE(0 << 21) (0 << 21)
8664#define TRANS_INTERLACED(3 << 21) (3 << 21)
8665#define TRANS_LEGACY_INTERLACED_ILK(2 << 21) (2 << 21)
8666#define TRANS_8BPC(0 << 5) (0 << 5)
8667#define TRANS_10BPC(1 << 5) (1 << 5)
8668#define TRANS_6BPC(2 << 5) (2 << 5)
8669#define TRANS_12BPC(3 << 5) (3 << 5)
8670
8671#define _TRANSA_CHICKEN10xf0060 0xf0060
8672#define _TRANSB_CHICKEN10xf1060 0xf1060
8673#define TRANS_CHICKEN1(pipe)((const i915_reg_t){ .reg = (((0xf0060) + (pipe) * ((0xf1060)
- (0xf0060)))) }) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)((const i915_reg_t){ .reg = (((0xf0060) + (pipe) * ((0xf1060)
- (0xf0060)))) })
8674#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE(1 << 10) (1 << 10)
8675#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE(1 << 4) (1 << 4)
8676#define _TRANSA_CHICKEN20xf0064 0xf0064
8677#define _TRANSB_CHICKEN20xf1064 0xf1064
8678#define TRANS_CHICKEN2(pipe)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064)
- (0xf0064)))) }) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064)
- (0xf0064)))) })
8679#define TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31) (1 << 31)
8680#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED(1 << 29) (1 << 29)
8681#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27) (3 << 27)
8682#define TRANS_CHICKEN2_FRAME_START_DELAY(x)((x) << 27) ((x) << 27) /* 0-3 */
8683#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER(1 << 26) (1 << 26)
8684#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH(1 << 25) (1 << 25)
8685
8686#define SOUTH_CHICKEN1((const i915_reg_t){ .reg = (0xc2000) }) _MMIO(0xc2000)((const i915_reg_t){ .reg = (0xc2000) })
8687#define FDIA_PHASE_SYNC_SHIFT_OVR19 19
8688#define FDIA_PHASE_SYNC_SHIFT_EN18 18
8689#define FDI_PHASE_SYNC_OVR(pipe)(1 << (19 - ((pipe) * 2))) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR19 - ((pipe) * 2)))
8690#define FDI_PHASE_SYNC_EN(pipe)(1 << (18 - ((pipe) * 2))) (1 << (FDIA_PHASE_SYNC_SHIFT_EN18 - ((pipe) * 2)))
8691#define FDI_BC_BIFURCATION_SELECT(1 << 12) (1 << 12)
8692#define CHASSIS_CLK_REQ_DURATION_MASK(0xf << 8) (0xf << 8)
8693#define CHASSIS_CLK_REQ_DURATION(x)((x) << 8) ((x) << 8)
8694#define SBCLK_RUN_REFCLK_DIS(1 << 7) (1 << 7)
8695#define SPT_PWM_GRANULARITY(1 << 0) (1 << 0)
8696#define SOUTH_CHICKEN2((const i915_reg_t){ .reg = (0xc2004) }) _MMIO(0xc2004)((const i915_reg_t){ .reg = (0xc2004) })
8697#define FDI_MPHY_IOSFSB_RESET_STATUS(1 << 13) (1 << 13)
8698#define FDI_MPHY_IOSFSB_RESET_CTL(1 << 12) (1 << 12)
8699#define LPT_PWM_GRANULARITY(1 << 5) (1 << 5)
8700#define DPLS_EDP_PPS_FIX_DIS(1 << 0) (1 << 0)
8701
8702#define _FDI_RXA_CHICKEN0xc200c 0xc200c
8703#define _FDI_RXB_CHICKEN0xc2010 0xc2010
8704#define FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1) (1 << 1)
8705#define FDI_RX_PHASE_SYNC_POINTER_EN(1 << 0) (1 << 0)
8706#define FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010)
- (0xc200c)))) }) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010)
- (0xc200c)))) })
8707
8708#define SOUTH_DSPCLK_GATE_D((const i915_reg_t){ .reg = (0xc2020) }) _MMIO(0xc2020)((const i915_reg_t){ .reg = (0xc2020) })
8709#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE(1 << 31) (1 << 31)
8710#define PCH_DPLUNIT_CLOCK_GATE_DISABLE(1 << 30) (1 << 30)
8711#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE(1 << 29) (1 << 29)
8712#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE(1 << 15) (1 << 15)
8713#define PCH_CPUNIT_CLOCK_GATE_DISABLE(1 << 14) (1 << 14)
8714#define CNP_PWM_CGE_GATING_DISABLE(1 << 13) (1 << 13)
8715#define PCH_LP_PARTITION_LEVEL_DISABLE(1 << 12) (1 << 12)
8716
8717/* CPU: FDI_TX */
8718#define _FDI_TXA_CTL0x60100 0x60100
8719#define _FDI_TXB_CTL0x61100 0x61100
8720#define FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) }) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
8721#define FDI_TX_DISABLE(0 << 31) (0 << 31)
8722#define FDI_TX_ENABLE(1 << 31) (1 << 31)
8723#define FDI_LINK_TRAIN_PATTERN_1(0 << 28) (0 << 28)
8724#define FDI_LINK_TRAIN_PATTERN_2(1 << 28) (1 << 28)
8725#define FDI_LINK_TRAIN_PATTERN_IDLE(2 << 28) (2 << 28)
8726#define FDI_LINK_TRAIN_NONE(3 << 28) (3 << 28)
8727#define FDI_LINK_TRAIN_VOLTAGE_0_4V(0 << 25) (0 << 25)
8728#define FDI_LINK_TRAIN_VOLTAGE_0_6V(1 << 25) (1 << 25)
8729#define FDI_LINK_TRAIN_VOLTAGE_0_8V(2 << 25) (2 << 25)
8730#define FDI_LINK_TRAIN_VOLTAGE_1_2V(3 << 25) (3 << 25)
8731#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE(0 << 22) (0 << 22)
8732#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X(1 << 22) (1 << 22)
8733#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X(2 << 22) (2 << 22)
8734#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X(3 << 22) (3 << 22)
8735/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8736 SNB has different settings. */
8737/* SNB A-stepping */
8738#define FDI_LINK_TRAIN_400MV_0DB_SNB_A(0x38 << 22) (0x38 << 22)
8739#define FDI_LINK_TRAIN_400MV_6DB_SNB_A(0x02 << 22) (0x02 << 22)
8740#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A(0x01 << 22) (0x01 << 22)
8741#define FDI_LINK_TRAIN_800MV_0DB_SNB_A(0x0 << 22) (0x0 << 22)
8742/* SNB B-stepping */
8743#define FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22) (0x0 << 22)
8744#define FDI_LINK_TRAIN_400MV_6DB_SNB_B(0x3a << 22) (0x3a << 22)
8745#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B(0x39 << 22) (0x39 << 22)
8746#define FDI_LINK_TRAIN_800MV_0DB_SNB_B(0x38 << 22) (0x38 << 22)
8747#define FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22) (0x3f << 22)
8748#define FDI_DP_PORT_WIDTH_SHIFT19 19
8749#define FDI_DP_PORT_WIDTH_MASK(7 << 19) (7 << FDI_DP_PORT_WIDTH_SHIFT19)
8750#define FDI_DP_PORT_WIDTH(width)(((width) - 1) << 19) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT19)
8751#define FDI_TX_ENHANCE_FRAME_ENABLE(1 << 18) (1 << 18)
8752/* Ironlake: hardwired to 1 */
8753#define FDI_TX_PLL_ENABLE(1 << 14) (1 << 14)
8754
8755/* Ivybridge has different bits for lolz */
8756#define FDI_LINK_TRAIN_PATTERN_1_IVB(0 << 8) (0 << 8)
8757#define FDI_LINK_TRAIN_PATTERN_2_IVB(1 << 8) (1 << 8)
8758#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB(2 << 8) (2 << 8)
8759#define FDI_LINK_TRAIN_NONE_IVB(3 << 8) (3 << 8)
8760
8761/* both Tx and Rx */
8762#define FDI_COMPOSITE_SYNC(1 << 11) (1 << 11)
8763#define FDI_LINK_TRAIN_AUTO(1 << 10) (1 << 10)
8764#define FDI_SCRAMBLING_ENABLE(0 << 7) (0 << 7)
8765#define FDI_SCRAMBLING_DISABLE(1 << 7) (1 << 7)
8766
8767/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8768#define _FDI_RXA_CTL0xf000c 0xf000c
8769#define _FDI_RXB_CTL0xf100c 0xf100c
8770#define FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) }) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
8771#define FDI_RX_ENABLE(1 << 31) (1 << 31)
8772/* train, dp width same as FDI_TX */
8773#define FDI_FS_ERRC_ENABLE(1 << 27) (1 << 27)
8774#define FDI_FE_ERRC_ENABLE(1 << 26) (1 << 26)
8775#define FDI_RX_POLARITY_REVERSED_LPT(1 << 16) (1 << 16)
8776#define FDI_8BPC(0 << 16) (0 << 16)
8777#define FDI_10BPC(1 << 16) (1 << 16)
8778#define FDI_6BPC(2 << 16) (2 << 16)
8779#define FDI_12BPC(3 << 16) (3 << 16)
8780#define FDI_RX_LINK_REVERSAL_OVERRIDE(1 << 15) (1 << 15)
8781#define FDI_DMI_LINK_REVERSE_MASK(1 << 14) (1 << 14)
8782#define FDI_RX_PLL_ENABLE(1 << 13) (1 << 13)
8783#define FDI_FS_ERR_CORRECT_ENABLE(1 << 11) (1 << 11)
8784#define FDI_FE_ERR_CORRECT_ENABLE(1 << 10) (1 << 10)
8785#define FDI_FS_ERR_REPORT_ENABLE(1 << 9) (1 << 9)
8786#define FDI_FE_ERR_REPORT_ENABLE(1 << 8) (1 << 8)
8787#define FDI_RX_ENHANCE_FRAME_ENABLE(1 << 6) (1 << 6)
8788#define FDI_PCDCLK(1 << 4) (1 << 4)
8789/* CPT */
8790#define FDI_AUTO_TRAINING(1 << 10) (1 << 10)
8791#define FDI_LINK_TRAIN_PATTERN_1_CPT(0 << 8) (0 << 8)
8792#define FDI_LINK_TRAIN_PATTERN_2_CPT(1 << 8) (1 << 8)
8793#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT(2 << 8) (2 << 8)
8794#define FDI_LINK_TRAIN_NORMAL_CPT(3 << 8) (3 << 8)
8795#define FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8) (3 << 8)
8796
8797#define _FDI_RXA_MISC0xf0010 0xf0010
8798#define _FDI_RXB_MISC0xf1010 0xf1010
8799#define FDI_RX_PWRDN_LANE1_MASK(3 << 26) (3 << 26)
8800#define FDI_RX_PWRDN_LANE1_VAL(x)((x) << 26) ((x) << 26)
8801#define FDI_RX_PWRDN_LANE0_MASK(3 << 24) (3 << 24)
8802#define FDI_RX_PWRDN_LANE0_VAL(x)((x) << 24) ((x) << 24)
8803#define FDI_RX_TP1_TO_TP2_48(2 << 20) (2 << 20)
8804#define FDI_RX_TP1_TO_TP2_64(3 << 20) (3 << 20)
8805#define FDI_RX_FDI_DELAY_90(0x90 << 0) (0x90 << 0)
8806#define FDI_RX_MISC(pipe)((const i915_reg_t){ .reg = (((0xf0010) + (pipe) * ((0xf1010)
- (0xf0010)))) }) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)((const i915_reg_t){ .reg = (((0xf0010) + (pipe) * ((0xf1010)
- (0xf0010)))) })
8807
8808#define _FDI_RXA_TUSIZE10xf0030 0xf0030
8809#define _FDI_RXA_TUSIZE20xf0038 0xf0038
8810#define _FDI_RXB_TUSIZE10xf1030 0xf1030
8811#define _FDI_RXB_TUSIZE20xf1038 0xf1038
8812#define FDI_RX_TUSIZE1(pipe)((const i915_reg_t){ .reg = (((0xf0030) + (pipe) * ((0xf1030)
- (0xf0030)))) }) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)((const i915_reg_t){ .reg = (((0xf0030) + (pipe) * ((0xf1030)
- (0xf0030)))) })
8813#define FDI_RX_TUSIZE2(pipe)((const i915_reg_t){ .reg = (((0xf0038) + (pipe) * ((0xf1038)
- (0xf0038)))) }) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)((const i915_reg_t){ .reg = (((0xf0038) + (pipe) * ((0xf1038)
- (0xf0038)))) })
8814
8815/* FDI_RX interrupt register format */
8816#define FDI_RX_INTER_LANE_ALIGN(1 << 10) (1 << 10)
8817#define FDI_RX_SYMBOL_LOCK(1 << 9) (1 << 9) /* train 2 */
8818#define FDI_RX_BIT_LOCK(1 << 8) (1 << 8) /* train 1 */
8819#define FDI_RX_TRAIN_PATTERN_2_FAIL(1 << 7) (1 << 7)
8820#define FDI_RX_FS_CODE_ERR(1 << 6) (1 << 6)
8821#define FDI_RX_FE_CODE_ERR(1 << 5) (1 << 5)
8822#define FDI_RX_SYMBOL_ERR_RATE_ABOVE(1 << 4) (1 << 4)
8823#define FDI_RX_HDCP_LINK_FAIL(1 << 3) (1 << 3)
8824#define FDI_RX_PIXEL_FIFO_OVERFLOW(1 << 2) (1 << 2)
8825#define FDI_RX_CROSS_CLOCK_OVERFLOW(1 << 1) (1 << 1)
8826#define FDI_RX_SYMBOL_QUEUE_OVERFLOW(1 << 0) (1 << 0)
8827
8828#define _FDI_RXA_IIR0xf0014 0xf0014
8829#define _FDI_RXA_IMR0xf0018 0xf0018
8830#define _FDI_RXB_IIR0xf1014 0xf1014
8831#define _FDI_RXB_IMR0xf1018 0xf1018
8832#define FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) }) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) })
8833#define FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018)
- (0xf0018)))) }) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018)
- (0xf0018)))) })
8834
8835#define FDI_PLL_CTL_1((const i915_reg_t){ .reg = (0xfe000) }) _MMIO(0xfe000)((const i915_reg_t){ .reg = (0xfe000) })
8836#define FDI_PLL_CTL_2((const i915_reg_t){ .reg = (0xfe004) }) _MMIO(0xfe004)((const i915_reg_t){ .reg = (0xfe004) })
8837
8838#define PCH_LVDS((const i915_reg_t){ .reg = (0xe1180) }) _MMIO(0xe1180)((const i915_reg_t){ .reg = (0xe1180) })
8839#define LVDS_DETECTED(1 << 1) (1 << 1)
8840
8841#define _PCH_DP_B0xe4100 0xe4100
8842#define PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) }) _MMIO(_PCH_DP_B)((const i915_reg_t){ .reg = (0xe4100) })
8843#define _PCH_DPB_AUX_CH_CTL0xe4110 0xe4110
8844#define _PCH_DPB_AUX_CH_DATA10xe4114 0xe4114
8845#define _PCH_DPB_AUX_CH_DATA20xe4118 0xe4118
8846#define _PCH_DPB_AUX_CH_DATA30xe411c 0xe411c
8847#define _PCH_DPB_AUX_CH_DATA40xe4120 0xe4120
8848#define _PCH_DPB_AUX_CH_DATA50xe4124 0xe4124
8849
8850#define _PCH_DP_C0xe4200 0xe4200
8851#define PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }) _MMIO(_PCH_DP_C)((const i915_reg_t){ .reg = (0xe4200) })
8852#define _PCH_DPC_AUX_CH_CTL0xe4210 0xe4210
8853#define _PCH_DPC_AUX_CH_DATA10xe4214 0xe4214
8854#define _PCH_DPC_AUX_CH_DATA20xe4218 0xe4218
8855#define _PCH_DPC_AUX_CH_DATA30xe421c 0xe421c
8856#define _PCH_DPC_AUX_CH_DATA40xe4220 0xe4220
8857#define _PCH_DPC_AUX_CH_DATA50xe4224 0xe4224
8858
8859#define _PCH_DP_D0xe4300 0xe4300
8860#define PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }) _MMIO(_PCH_DP_D)((const i915_reg_t){ .reg = (0xe4300) })
8861#define _PCH_DPD_AUX_CH_CTL0xe4310 0xe4310
8862#define _PCH_DPD_AUX_CH_DATA10xe4314 0xe4314
8863#define _PCH_DPD_AUX_CH_DATA20xe4318 0xe4318
8864#define _PCH_DPD_AUX_CH_DATA30xe431c 0xe431c
8865#define _PCH_DPD_AUX_CH_DATA40xe4320 0xe4320
8866#define _PCH_DPD_AUX_CH_DATA50xe4324 0xe4324
8867
8868#define PCH_DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = (((0xe4110) + ((aux_ch) - AUX_CH_B
) * ((0xe4210) - (0xe4110)))) }) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)((const i915_reg_t){ .reg = (((0xe4110) + ((aux_ch) - AUX_CH_B
) * ((0xe4210) - (0xe4110)))) })
8869#define PCH_DP_AUX_CH_DATA(aux_ch, i)((const i915_reg_t){ .reg = (((0xe4114) + ((aux_ch) - AUX_CH_B
) * ((0xe4214) - (0xe4114))) + (i) * 4) }) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4)((const i915_reg_t){ .reg = (((0xe4114) + ((aux_ch) - AUX_CH_B
) * ((0xe4214) - (0xe4114))) + (i) * 4) }) /* 5 registers */
8870
8871/* CPT */
8872#define _TRANS_DP_CTL_A0xe0300 0xe0300
8873#define _TRANS_DP_CTL_B0xe1300 0xe1300
8874#define _TRANS_DP_CTL_C0xe2300 0xe2300
8875#define TRANS_DP_CTL(pipe)((const i915_reg_t){ .reg = (((0xe0300) + (pipe) * ((0xe1300)
- (0xe0300)))) }) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)((const i915_reg_t){ .reg = (((0xe0300) + (pipe) * ((0xe1300)
- (0xe0300)))) })
8876#define TRANS_DP_OUTPUT_ENABLE(1 << 31) (1 << 31)
8877#define TRANS_DP_PORT_SEL_MASK(3 << 29) (3 << 29)
8878#define TRANS_DP_PORT_SEL_NONE(3 << 29) (3 << 29)
8879#define TRANS_DP_PORT_SEL(port)(((port) - PORT_B) << 29) (((port) - PORT_B) << 29)
8880#define TRANS_DP_AUDIO_ONLY(1 << 26) (1 << 26)
8881#define TRANS_DP_ENH_FRAMING(1 << 18) (1 << 18)
8882#define TRANS_DP_8BPC(0 << 9) (0 << 9)
8883#define TRANS_DP_10BPC(1 << 9) (1 << 9)
8884#define TRANS_DP_6BPC(2 << 9) (2 << 9)
8885#define TRANS_DP_12BPC(3 << 9) (3 << 9)
8886#define TRANS_DP_BPC_MASK(3 << 9) (3 << 9)
8887#define TRANS_DP_VSYNC_ACTIVE_HIGH(1 << 4) (1 << 4)
8888#define TRANS_DP_VSYNC_ACTIVE_LOW0 0
8889#define TRANS_DP_HSYNC_ACTIVE_HIGH(1 << 3) (1 << 3)
8890#define TRANS_DP_HSYNC_ACTIVE_LOW0 0
8891#define TRANS_DP_SYNC_MASK(3 << 3) (3 << 3)
8892
8893/* SNB eDP training params */
8894/* SNB A-stepping */
8895#define EDP_LINK_TRAIN_400MV_0DB_SNB_A(0x38 << 22) (0x38 << 22)
8896#define EDP_LINK_TRAIN_400MV_6DB_SNB_A(0x02 << 22) (0x02 << 22)
8897#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A(0x01 << 22) (0x01 << 22)
8898#define EDP_LINK_TRAIN_800MV_0DB_SNB_A(0x0 << 22) (0x0 << 22)
8899/* SNB B-stepping */
8900#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B(0x0 << 22) (0x0 << 22)
8901#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B(0x1 << 22) (0x1 << 22)
8902#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B(0x3a << 22) (0x3a << 22)
8903#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B(0x39 << 22) (0x39 << 22)
8904#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B(0x38 << 22) (0x38 << 22)
8905#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB(0x3f << 22) (0x3f << 22)
8906
8907/* IVB */
8908#define EDP_LINK_TRAIN_400MV_0DB_IVB(0x24 << 22) (0x24 << 22)
8909#define EDP_LINK_TRAIN_400MV_3_5DB_IVB(0x2a << 22) (0x2a << 22)
8910#define EDP_LINK_TRAIN_400MV_6DB_IVB(0x2f << 22) (0x2f << 22)
8911#define EDP_LINK_TRAIN_600MV_0DB_IVB(0x30 << 22) (0x30 << 22)
8912#define EDP_LINK_TRAIN_600MV_3_5DB_IVB(0x36 << 22) (0x36 << 22)
8913#define EDP_LINK_TRAIN_800MV_0DB_IVB(0x38 << 22) (0x38 << 22)
8914#define EDP_LINK_TRAIN_800MV_3_5DB_IVB(0x3e << 22) (0x3e << 22)
8915
8916/* legacy values */
8917#define EDP_LINK_TRAIN_500MV_0DB_IVB(0x00 << 22) (0x00 << 22)
8918#define EDP_LINK_TRAIN_1000MV_0DB_IVB(0x20 << 22) (0x20 << 22)
8919#define EDP_LINK_TRAIN_500MV_3_5DB_IVB(0x02 << 22) (0x02 << 22)
8920#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB(0x22 << 22) (0x22 << 22)
8921#define EDP_LINK_TRAIN_1000MV_6DB_IVB(0x23 << 22) (0x23 << 22)
8922
8923#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB(0x3f << 22) (0x3f << 22)
8924
8925#define VLV_PMWGICZ((const i915_reg_t){ .reg = (0x1300a4) }) _MMIO(0x1300a4)((const i915_reg_t){ .reg = (0x1300a4) })
8926
8927#define RC6_LOCATION((const i915_reg_t){ .reg = (0xD40) }) _MMIO(0xD40)((const i915_reg_t){ .reg = (0xD40) })
8928#define RC6_CTX_IN_DRAM(1 << 0) (1 << 0)
8929#define RC6_CTX_BASE((const i915_reg_t){ .reg = (0xD48) }) _MMIO(0xD48)((const i915_reg_t){ .reg = (0xD48) })
8930#define RC6_CTX_BASE_MASK0xFFFFFFF0 0xFFFFFFF0
8931#define PWRCTX_MAXCNT_RCSUNIT((const i915_reg_t){ .reg = (0x2054) }) _MMIO(0x2054)((const i915_reg_t){ .reg = (0x2054) })
8932#define PWRCTX_MAXCNT_VCSUNIT0((const i915_reg_t){ .reg = (0x12054) }) _MMIO(0x12054)((const i915_reg_t){ .reg = (0x12054) })
8933#define PWRCTX_MAXCNT_BCSUNIT((const i915_reg_t){ .reg = (0x22054) }) _MMIO(0x22054)((const i915_reg_t){ .reg = (0x22054) })
8934#define PWRCTX_MAXCNT_VECSUNIT((const i915_reg_t){ .reg = (0x1A054) }) _MMIO(0x1A054)((const i915_reg_t){ .reg = (0x1A054) })
8935#define PWRCTX_MAXCNT_VCSUNIT1((const i915_reg_t){ .reg = (0x1C054) }) _MMIO(0x1C054)((const i915_reg_t){ .reg = (0x1C054) })
8936#define IDLE_TIME_MASK0xFFFFF 0xFFFFF
8937#define FORCEWAKE((const i915_reg_t){ .reg = (0xA18C) }) _MMIO(0xA18C)((const i915_reg_t){ .reg = (0xA18C) })
8938#define FORCEWAKE_VLV((const i915_reg_t){ .reg = (0x1300b0) }) _MMIO(0x1300b0)((const i915_reg_t){ .reg = (0x1300b0) })
8939#define FORCEWAKE_ACK_VLV((const i915_reg_t){ .reg = (0x1300b4) }) _MMIO(0x1300b4)((const i915_reg_t){ .reg = (0x1300b4) })
8940#define FORCEWAKE_MEDIA_VLV((const i915_reg_t){ .reg = (0x1300b8) }) _MMIO(0x1300b8)((const i915_reg_t){ .reg = (0x1300b8) })
8941#define FORCEWAKE_ACK_MEDIA_VLV((const i915_reg_t){ .reg = (0x1300bc) }) _MMIO(0x1300bc)((const i915_reg_t){ .reg = (0x1300bc) })
8942#define FORCEWAKE_ACK_HSW((const i915_reg_t){ .reg = (0x130044) }) _MMIO(0x130044)((const i915_reg_t){ .reg = (0x130044) })
8943#define FORCEWAKE_ACK((const i915_reg_t){ .reg = (0x130090) }) _MMIO(0x130090)((const i915_reg_t){ .reg = (0x130090) })
8944#define VLV_GTLC_WAKE_CTRL((const i915_reg_t){ .reg = (0x130090) }) _MMIO(0x130090)((const i915_reg_t){ .reg = (0x130090) })
8945#define VLV_GTLC_RENDER_CTX_EXISTS(1 << 25) (1 << 25)
8946#define VLV_GTLC_MEDIA_CTX_EXISTS(1 << 24) (1 << 24)
8947#define VLV_GTLC_ALLOWWAKEREQ(1 << 0) (1 << 0)
8948
8949#define VLV_GTLC_PW_STATUS((const i915_reg_t){ .reg = (0x130094) }) _MMIO(0x130094)((const i915_reg_t){ .reg = (0x130094) })
8950#define VLV_GTLC_ALLOWWAKEACK(1 << 0) (1 << 0)
8951#define VLV_GTLC_ALLOWWAKEERR(1 << 1) (1 << 1)
8952#define VLV_GTLC_PW_MEDIA_STATUS_MASK(1 << 5) (1 << 5)
8953#define VLV_GTLC_PW_RENDER_STATUS_MASK(1 << 7) (1 << 7)
8954#define FORCEWAKE_MT((const i915_reg_t){ .reg = (0xa188) }) _MMIO(0xa188)((const i915_reg_t){ .reg = (0xa188) }) /* multi-threaded */
8955#define FORCEWAKE_MEDIA_GEN9((const i915_reg_t){ .reg = (0xa270) }) _MMIO(0xa270)((const i915_reg_t){ .reg = (0xa270) })
8956#define FORCEWAKE_MEDIA_VDBOX_GEN11(n)((const i915_reg_t){ .reg = (0xa540 + (n) * 4) }) _MMIO(0xa540 + (n) * 4)((const i915_reg_t){ .reg = (0xa540 + (n) * 4) })
8957#define FORCEWAKE_MEDIA_VEBOX_GEN11(n)((const i915_reg_t){ .reg = (0xa560 + (n) * 4) }) _MMIO(0xa560 + (n) * 4)((const i915_reg_t){ .reg = (0xa560 + (n) * 4) })
8958#define FORCEWAKE_RENDER_GEN9((const i915_reg_t){ .reg = (0xa278) }) _MMIO(0xa278)((const i915_reg_t){ .reg = (0xa278) })
8959#define FORCEWAKE_BLITTER_GEN9((const i915_reg_t){ .reg = (0xa188) }) _MMIO(0xa188)((const i915_reg_t){ .reg = (0xa188) })
8960#define FORCEWAKE_ACK_MEDIA_GEN9((const i915_reg_t){ .reg = (0x0D88) }) _MMIO(0x0D88)((const i915_reg_t){ .reg = (0x0D88) })
8961#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)((const i915_reg_t){ .reg = (0x0D50 + (n) * 4) }) _MMIO(0x0D50 + (n) * 4)((const i915_reg_t){ .reg = (0x0D50 + (n) * 4) })
8962#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)((const i915_reg_t){ .reg = (0x0D70 + (n) * 4) }) _MMIO(0x0D70 + (n) * 4)((const i915_reg_t){ .reg = (0x0D70 + (n) * 4) })
8963#define FORCEWAKE_ACK_RENDER_GEN9((const i915_reg_t){ .reg = (0x0D84) }) _MMIO(0x0D84)((const i915_reg_t){ .reg = (0x0D84) })
8964#define FORCEWAKE_ACK_BLITTER_GEN9((const i915_reg_t){ .reg = (0x130044) }) _MMIO(0x130044)((const i915_reg_t){ .reg = (0x130044) })
8965#define FORCEWAKE_KERNEL(1UL << (0)) BIT(0)(1UL << (0))
8966#define FORCEWAKE_USER(1UL << (1)) BIT(1)(1UL << (1))
8967#define FORCEWAKE_KERNEL_FALLBACK(1UL << (15)) BIT(15)(1UL << (15))
8968#define FORCEWAKE_MT_ACK((const i915_reg_t){ .reg = (0x130040) }) _MMIO(0x130040)((const i915_reg_t){ .reg = (0x130040) })
8969#define ECOBUS((const i915_reg_t){ .reg = (0xa180) }) _MMIO(0xa180)((const i915_reg_t){ .reg = (0xa180) })
8970#define FORCEWAKE_MT_ENABLE(1 << 5) (1 << 5)
8971#define VLV_SPAREG2H((const i915_reg_t){ .reg = (0xA194) }) _MMIO(0xA194)((const i915_reg_t){ .reg = (0xA194) })
8972#define GEN9_PWRGT_DOMAIN_STATUS((const i915_reg_t){ .reg = (0xA2A0) }) _MMIO(0xA2A0)((const i915_reg_t){ .reg = (0xA2A0) })
8973#define GEN9_PWRGT_MEDIA_STATUS_MASK(1 << 0) (1 << 0)
8974#define GEN9_PWRGT_RENDER_STATUS_MASK(1 << 1) (1 << 1)
8975
8976#define GTFIFODBG((const i915_reg_t){ .reg = (0x120000) }) _MMIO(0x120000)((const i915_reg_t){ .reg = (0x120000) })
8977#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV(0x1f << 20) (0x1f << 20)
8978#define GT_FIFO_FREE_ENTRIES_CHV(0x7f << 13) (0x7f << 13)
8979#define GT_FIFO_SBDROPERR(1 << 6) (1 << 6)
8980#define GT_FIFO_BLOBDROPERR(1 << 5) (1 << 5)
8981#define GT_FIFO_SB_READ_ABORTERR(1 << 4) (1 << 4)
8982#define GT_FIFO_DROPERR(1 << 3) (1 << 3)
8983#define GT_FIFO_OVFERR(1 << 2) (1 << 2)
8984#define GT_FIFO_IAWRERR(1 << 1) (1 << 1)
8985#define GT_FIFO_IARDERR(1 << 0) (1 << 0)
8986
8987#define GTFIFOCTL((const i915_reg_t){ .reg = (0x120008) }) _MMIO(0x120008)((const i915_reg_t){ .reg = (0x120008) })
8988#define GT_FIFO_FREE_ENTRIES_MASK0x7f 0x7f
8989#define GT_FIFO_NUM_RESERVED_ENTRIES20 20
8990#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL(1 << 12) (1 << 12)
8991#define GT_FIFO_CTL_RC6_POLICY_STALL(1 << 11) (1 << 11)
8992
8993#define HSW_IDICR((const i915_reg_t){ .reg = (0x9008) }) _MMIO(0x9008)((const i915_reg_t){ .reg = (0x9008) })
8994#define IDIHASHMSK(x)(((x) & 0x3f) << 16) (((x) & 0x3f) << 16)
8995#define HSW_EDRAM_CAP((const i915_reg_t){ .reg = (0x120010) }) _MMIO(0x120010)((const i915_reg_t){ .reg = (0x120010) })
8996#define EDRAM_ENABLED0x1 0x1
8997#define EDRAM_NUM_BANKS(cap)(((cap) >> 1) & 0xf) (((cap) >> 1) & 0xf)
8998#define EDRAM_WAYS_IDX(cap)(((cap) >> 5) & 0x7) (((cap) >> 5) & 0x7)
8999#define EDRAM_SETS_IDX(cap)(((cap) >> 8) & 0x3) (((cap) >> 8) & 0x3)
9000
9001#define GEN6_UCGCTL1((const i915_reg_t){ .reg = (0x9400) }) _MMIO(0x9400)((const i915_reg_t){ .reg = (0x9400) })
9002# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE(1 << 22) (1 << 22)
9003# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE(1 << 16) (1 << 16)
9004# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE(1 << 5) (1 << 5)
9005# define GEN6_CSUNIT_CLOCK_GATE_DISABLE(1 << 7) (1 << 7)
9006
9007#define GEN6_UCGCTL2((const i915_reg_t){ .reg = (0x9404) }) _MMIO(0x9404)((const i915_reg_t){ .reg = (0x9404) })
9008# define GEN6_VFUNIT_CLOCK_GATE_DISABLE(1 << 31) (1 << 31)
9009# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE(1 << 30) (1 << 30)
9010# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE(1 << 22) (1 << 22)
9011# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE(1 << 13) (1 << 13)
9012# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE(1 << 12) (1 << 12)
9013# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE(1 << 11) (1 << 11)
9014
9015#define GEN6_UCGCTL3((const i915_reg_t){ .reg = (0x9408) }) _MMIO(0x9408)((const i915_reg_t){ .reg = (0x9408) })
9016# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE(1 << 20) (1 << 20)
9017
9018#define GEN7_UCGCTL4((const i915_reg_t){ .reg = (0x940c) }) _MMIO(0x940c)((const i915_reg_t){ .reg = (0x940c) })
9019#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE(1 << 25) (1 << 25)
9020#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE(1 << 14) (1 << 14)
9021
9022#define GEN6_RCGCTL1((const i915_reg_t){ .reg = (0x9410) }) _MMIO(0x9410)((const i915_reg_t){ .reg = (0x9410) })
9023#define GEN6_RCGCTL2((const i915_reg_t){ .reg = (0x9414) }) _MMIO(0x9414)((const i915_reg_t){ .reg = (0x9414) })
9024#define GEN6_RSTCTL((const i915_reg_t){ .reg = (0x9420) }) _MMIO(0x9420)((const i915_reg_t){ .reg = (0x9420) })
9025
9026#define GEN8_UCGCTL6((const i915_reg_t){ .reg = (0x9430) }) _MMIO(0x9430)((const i915_reg_t){ .reg = (0x9430) })
9027#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE(1 << 24) (1 << 24)
9028#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE(1 << 14) (1 << 14)
9029#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ(1 << 28) (1 << 28)
9030
9031#define GEN6_GFXPAUSE((const i915_reg_t){ .reg = (0xA000) }) _MMIO(0xA000)((const i915_reg_t){ .reg = (0xA000) })
9032#define GEN6_RPNSWREQ((const i915_reg_t){ .reg = (0xA008) }) _MMIO(0xA008)((const i915_reg_t){ .reg = (0xA008) })
9033#define GEN6_TURBO_DISABLE(1 << 31) (1 << 31)
9034#define GEN6_FREQUENCY(x)((x) << 25) ((x) << 25)
9035#define HSW_FREQUENCY(x)((x) << 24) ((x) << 24)
9036#define GEN9_FREQUENCY(x)((x) << 23) ((x) << 23)
9037#define GEN6_OFFSET(x)((x) << 19) ((x) << 19)
9038#define GEN6_AGGRESSIVE_TURBO(0 << 15) (0 << 15)
9039#define GEN6_RC_VIDEO_FREQ((const i915_reg_t){ .reg = (0xA00C) }) _MMIO(0xA00C)((const i915_reg_t){ .reg = (0xA00C) })
9040#define GEN6_RC_CONTROL((const i915_reg_t){ .reg = (0xA090) }) _MMIO(0xA090)((const i915_reg_t){ .reg = (0xA090) })
9041#define GEN6_RC_CTL_RC6pp_ENABLE(1 << 16) (1 << 16)
9042#define GEN6_RC_CTL_RC6p_ENABLE(1 << 17) (1 << 17)
9043#define GEN6_RC_CTL_RC6_ENABLE(1 << 18) (1 << 18)
9044#define GEN6_RC_CTL_RC1e_ENABLE(1 << 20) (1 << 20)
9045#define GEN6_RC_CTL_RC7_ENABLE(1 << 22) (1 << 22)
9046#define VLV_RC_CTL_CTX_RST_PARALLEL(1 << 24) (1 << 24)
9047#define GEN7_RC_CTL_TO_MODE(1 << 28) (1 << 28)
9048#define GEN6_RC_CTL_EI_MODE(x)((x) << 27) ((x) << 27)
9049#define GEN6_RC_CTL_HW_ENABLE(1 << 31) (1 << 31)
9050#define GEN6_RP_DOWN_TIMEOUT((const i915_reg_t){ .reg = (0xA010) }) _MMIO(0xA010)((const i915_reg_t){ .reg = (0xA010) })
9051#define GEN6_RP_INTERRUPT_LIMITS((const i915_reg_t){ .reg = (0xA014) }) _MMIO(0xA014)((const i915_reg_t){ .reg = (0xA014) })
9052#define GEN6_RPSTAT1((const i915_reg_t){ .reg = (0xA01C) }) _MMIO(0xA01C)((const i915_reg_t){ .reg = (0xA01C) })
9053#define GEN6_CAGF_SHIFT8 8
9054#define HSW_CAGF_SHIFT7 7
9055#define GEN9_CAGF_SHIFT23 23
9056#define GEN6_CAGF_MASK(0x7f << 8) (0x7f << GEN6_CAGF_SHIFT8)
9057#define HSW_CAGF_MASK(0x7f << 7) (0x7f << HSW_CAGF_SHIFT7)
9058#define GEN9_CAGF_MASK(0x1ff << 23) (0x1ff << GEN9_CAGF_SHIFT23)
9059#define GEN6_RP_CONTROL((const i915_reg_t){ .reg = (0xA024) }) _MMIO(0xA024)((const i915_reg_t){ .reg = (0xA024) })
9060#define GEN6_RP_MEDIA_TURBO(1 << 11) (1 << 11)
9061#define GEN6_RP_MEDIA_MODE_MASK(3 << 9) (3 << 9)
9062#define GEN6_RP_MEDIA_HW_TURBO_MODE(3 << 9) (3 << 9)
9063#define GEN6_RP_MEDIA_HW_NORMAL_MODE(2 << 9) (2 << 9)
9064#define GEN6_RP_MEDIA_HW_MODE(1 << 9) (1 << 9)
9065#define GEN6_RP_MEDIA_SW_MODE(0 << 9) (0 << 9)
9066#define GEN6_RP_MEDIA_IS_GFX(1 << 8) (1 << 8)
9067#define GEN6_RP_ENABLE(1 << 7) (1 << 7)
9068#define GEN6_RP_UP_IDLE_MIN(0x1 << 3) (0x1 << 3)
9069#define GEN6_RP_UP_BUSY_AVG(0x2 << 3) (0x2 << 3)
9070#define GEN6_RP_UP_BUSY_CONT(0x4 << 3) (0x4 << 3)
9071#define GEN6_RP_DOWN_IDLE_AVG(0x2 << 0) (0x2 << 0)
9072#define GEN6_RP_DOWN_IDLE_CONT(0x1 << 0) (0x1 << 0)
9073#define GEN6_RP_UP_THRESHOLD((const i915_reg_t){ .reg = (0xA02C) }) _MMIO(0xA02C)((const i915_reg_t){ .reg = (0xA02C) })
9074#define GEN6_RP_DOWN_THRESHOLD((const i915_reg_t){ .reg = (0xA030) }) _MMIO(0xA030)((const i915_reg_t){ .reg = (0xA030) })
9075#define GEN6_RP_CUR_UP_EI((const i915_reg_t){ .reg = (0xA050) }) _MMIO(0xA050)((const i915_reg_t){ .reg = (0xA050) })
9076#define GEN6_RP_EI_MASK0xffffff 0xffffff
9077#define GEN6_CURICONT_MASK0xffffff GEN6_RP_EI_MASK0xffffff
9078#define GEN6_RP_CUR_UP((const i915_reg_t){ .reg = (0xA054) }) _MMIO(0xA054)((const i915_reg_t){ .reg = (0xA054) })
9079#define GEN6_CURBSYTAVG_MASK0xffffff GEN6_RP_EI_MASK0xffffff
9080#define GEN6_RP_PREV_UP((const i915_reg_t){ .reg = (0xA058) }) _MMIO(0xA058)((const i915_reg_t){ .reg = (0xA058) })
9081#define GEN6_RP_CUR_DOWN_EI((const i915_reg_t){ .reg = (0xA05C) }) _MMIO(0xA05C)((const i915_reg_t){ .reg = (0xA05C) })
9082#define GEN6_CURIAVG_MASK0xffffff GEN6_RP_EI_MASK0xffffff
9083#define GEN6_RP_CUR_DOWN((const i915_reg_t){ .reg = (0xA060) }) _MMIO(0xA060)((const i915_reg_t){ .reg = (0xA060) })
9084#define GEN6_RP_PREV_DOWN((const i915_reg_t){ .reg = (0xA064) }) _MMIO(0xA064)((const i915_reg_t){ .reg = (0xA064) })
9085#define GEN6_RP_UP_EI((const i915_reg_t){ .reg = (0xA068) }) _MMIO(0xA068)((const i915_reg_t){ .reg = (0xA068) })
9086#define GEN6_RP_DOWN_EI((const i915_reg_t){ .reg = (0xA06C) }) _MMIO(0xA06C)((const i915_reg_t){ .reg = (0xA06C) })
9087#define GEN6_RP_IDLE_HYSTERSIS((const i915_reg_t){ .reg = (0xA070) }) _MMIO(0xA070)((const i915_reg_t){ .reg = (0xA070) })
9088#define GEN6_RPDEUHWTC((const i915_reg_t){ .reg = (0xA080) }) _MMIO(0xA080)((const i915_reg_t){ .reg = (0xA080) })
9089#define GEN6_RPDEUC((const i915_reg_t){ .reg = (0xA084) }) _MMIO(0xA084)((const i915_reg_t){ .reg = (0xA084) })
9090#define GEN6_RPDEUCSW((const i915_reg_t){ .reg = (0xA088) }) _MMIO(0xA088)((const i915_reg_t){ .reg = (0xA088) })
9091#define GEN6_RC_STATE((const i915_reg_t){ .reg = (0xA094) }) _MMIO(0xA094)((const i915_reg_t){ .reg = (0xA094) })
9092#define RC_SW_TARGET_STATE_SHIFT16 16
9093#define RC_SW_TARGET_STATE_MASK(7 << 16) (7 << RC_SW_TARGET_STATE_SHIFT16)
9094#define GEN6_RC1_WAKE_RATE_LIMIT((const i915_reg_t){ .reg = (0xA098) }) _MMIO(0xA098)((const i915_reg_t){ .reg = (0xA098) })
9095#define GEN6_RC6_WAKE_RATE_LIMIT((const i915_reg_t){ .reg = (0xA09C) }) _MMIO(0xA09C)((const i915_reg_t){ .reg = (0xA09C) })
9096#define GEN6_RC6pp_WAKE_RATE_LIMIT((const i915_reg_t){ .reg = (0xA0A0) }) _MMIO(0xA0A0)((const i915_reg_t){ .reg = (0xA0A0) })
9097#define GEN10_MEDIA_WAKE_RATE_LIMIT((const i915_reg_t){ .reg = (0xA0A0) }) _MMIO(0xA0A0)((const i915_reg_t){ .reg = (0xA0A0) })
9098#define GEN6_RC_EVALUATION_INTERVAL((const i915_reg_t){ .reg = (0xA0A8) }) _MMIO(0xA0A8)((const i915_reg_t){ .reg = (0xA0A8) })
9099#define GEN6_RC_IDLE_HYSTERSIS((const i915_reg_t){ .reg = (0xA0AC) }) _MMIO(0xA0AC)((const i915_reg_t){ .reg = (0xA0AC) })
9100#define GEN6_RC_SLEEP((const i915_reg_t){ .reg = (0xA0B0) }) _MMIO(0xA0B0)((const i915_reg_t){ .reg = (0xA0B0) })
9101#define GEN6_RCUBMABDTMR((const i915_reg_t){ .reg = (0xA0B0) }) _MMIO(0xA0B0)((const i915_reg_t){ .reg = (0xA0B0) })
9102#define GEN6_RC1e_THRESHOLD((const i915_reg_t){ .reg = (0xA0B4) }) _MMIO(0xA0B4)((const i915_reg_t){ .reg = (0xA0B4) })
9103#define GEN6_RC6_THRESHOLD((const i915_reg_t){ .reg = (0xA0B8) }) _MMIO(0xA0B8)((const i915_reg_t){ .reg = (0xA0B8) })
9104#define GEN6_RC6p_THRESHOLD((const i915_reg_t){ .reg = (0xA0BC) }) _MMIO(0xA0BC)((const i915_reg_t){ .reg = (0xA0BC) })
9105#define VLV_RCEDATA((const i915_reg_t){ .reg = (0xA0BC) }) _MMIO(0xA0BC)((const i915_reg_t){ .reg = (0xA0BC) })
9106#define GEN6_RC6pp_THRESHOLD((const i915_reg_t){ .reg = (0xA0C0) }) _MMIO(0xA0C0)((const i915_reg_t){ .reg = (0xA0C0) })
9107#define GEN6_PMINTRMSK((const i915_reg_t){ .reg = (0xA168) }) _MMIO(0xA168)((const i915_reg_t){ .reg = (0xA168) })
9108#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC(1 << 31) (1 << 31)
9109#define ARAT_EXPIRED_INTRMSK(1 << 9) (1 << 9)
9110#define GEN8_MISC_CTRL0((const i915_reg_t){ .reg = (0xA180) }) _MMIO(0xA180)((const i915_reg_t){ .reg = (0xA180) })
9111#define VLV_PWRDWNUPCTL((const i915_reg_t){ .reg = (0xA294) }) _MMIO(0xA294)((const i915_reg_t){ .reg = (0xA294) })
9112#define GEN9_MEDIA_PG_IDLE_HYSTERESIS((const i915_reg_t){ .reg = (0xA0C4) }) _MMIO(0xA0C4)((const i915_reg_t){ .reg = (0xA0C4) })
9113#define GEN9_RENDER_PG_IDLE_HYSTERESIS((const i915_reg_t){ .reg = (0xA0C8) }) _MMIO(0xA0C8)((const i915_reg_t){ .reg = (0xA0C8) })
9114#define GEN9_PG_ENABLE((const i915_reg_t){ .reg = (0xA210) }) _MMIO(0xA210)((const i915_reg_t){ .reg = (0xA210) })
9115#define GEN9_RENDER_PG_ENABLE((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
9116#define GEN9_MEDIA_PG_ENABLE((u32)((1UL << (1)) + 0)) REG_BIT(1)((u32)((1UL << (1)) + 0))
9117#define GEN11_MEDIA_SAMPLER_PG_ENABLE((u32)((1UL << (2)) + 0)) REG_BIT(2)((u32)((1UL << (2)) + 0))
9118#define VDN_HCP_POWERGATE_ENABLE(n)((u32)((1UL << (3 + 2 * (n))) + 0)) REG_BIT(3 + 2 * (n))((u32)((1UL << (3 + 2 * (n))) + 0))
9119#define VDN_MFX_POWERGATE_ENABLE(n)((u32)((1UL << (4 + 2 * (n))) + 0)) REG_BIT(4 + 2 * (n))((u32)((1UL << (4 + 2 * (n))) + 0))
9120#define GEN8_PUSHBUS_CONTROL((const i915_reg_t){ .reg = (0xA248) }) _MMIO(0xA248)((const i915_reg_t){ .reg = (0xA248) })
9121#define GEN8_PUSHBUS_ENABLE((const i915_reg_t){ .reg = (0xA250) }) _MMIO(0xA250)((const i915_reg_t){ .reg = (0xA250) })
9122#define GEN8_PUSHBUS_SHIFT((const i915_reg_t){ .reg = (0xA25C) }) _MMIO(0xA25C)((const i915_reg_t){ .reg = (0xA25C) })
9123
9124#define VLV_CHICKEN_3((const i915_reg_t){ .reg = (0x180000 + 0x7040C) }) _MMIO(VLV_DISPLAY_BASE + 0x7040C)((const i915_reg_t){ .reg = (0x180000 + 0x7040C) })
9125#define PIXEL_OVERLAP_CNT_MASK(3 << 30) (3 << 30)
9126#define PIXEL_OVERLAP_CNT_SHIFT30 30
9127
9128#define GEN6_PMISR((const i915_reg_t){ .reg = (0x44020) }) _MMIO(0x44020)((const i915_reg_t){ .reg = (0x44020) })
9129#define GEN6_PMIMR((const i915_reg_t){ .reg = (0x44024) }) _MMIO(0x44024)((const i915_reg_t){ .reg = (0x44024) }) /* rps_lock */
9130#define GEN6_PMIIR((const i915_reg_t){ .reg = (0x44028) }) _MMIO(0x44028)((const i915_reg_t){ .reg = (0x44028) })
9131#define GEN6_PMIER((const i915_reg_t){ .reg = (0x4402C) }) _MMIO(0x4402C)((const i915_reg_t){ .reg = (0x4402C) })
9132#define GEN6_PM_MBOX_EVENT(1 << 25) (1 << 25)
9133#define GEN6_PM_THERMAL_EVENT(1 << 24) (1 << 24)
9134
9135/*
9136 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
9137 * registers. Shifting is handled on accessing the imr and ier.
9138 */
9139#define GEN6_PM_RP_DOWN_TIMEOUT(1 << 6) (1 << 6)
9140#define GEN6_PM_RP_UP_THRESHOLD(1 << 5) (1 << 5)
9141#define GEN6_PM_RP_DOWN_THRESHOLD(1 << 4) (1 << 4)
9142#define GEN6_PM_RP_UP_EI_EXPIRED(1 << 2) (1 << 2)
9143#define GEN6_PM_RP_DOWN_EI_EXPIRED(1 << 1) (1 << 1)
9144#define GEN6_PM_RPS_EVENTS((1 << 2) | (1 << 5) | (1 << 1) | (1 <<
4) | (1 << 6)) (GEN6_PM_RP_UP_EI_EXPIRED(1 << 2) | \
9145 GEN6_PM_RP_UP_THRESHOLD(1 << 5) | \
9146 GEN6_PM_RP_DOWN_EI_EXPIRED(1 << 1) | \
9147 GEN6_PM_RP_DOWN_THRESHOLD(1 << 4) | \
9148 GEN6_PM_RP_DOWN_TIMEOUT(1 << 6))
9149
9150#define GEN7_GT_SCRATCH(i)((const i915_reg_t){ .reg = (0x4F100 + (i) * 4) }) _MMIO(0x4F100 + (i) * 4)((const i915_reg_t){ .reg = (0x4F100 + (i) * 4) })
9151#define GEN7_GT_SCRATCH_REG_NUM8 8
9152
9153#define VLV_GTLC_SURVIVABILITY_REG((const i915_reg_t){ .reg = (0x130098) }) _MMIO(0x130098)((const i915_reg_t){ .reg = (0x130098) })
9154#define VLV_GFX_CLK_STATUS_BIT(1 << 3) (1 << 3)
9155#define VLV_GFX_CLK_FORCE_ON_BIT(1 << 2) (1 << 2)
9156
9157#define GEN6_GT_GFX_RC6_LOCKED((const i915_reg_t){ .reg = (0x138104) }) _MMIO(0x138104)((const i915_reg_t){ .reg = (0x138104) })
9158#define VLV_COUNTER_CONTROL((const i915_reg_t){ .reg = (0x138104) }) _MMIO(0x138104)((const i915_reg_t){ .reg = (0x138104) })
9159#define VLV_COUNT_RANGE_HIGH(1 << 15) (1 << 15)
9160#define VLV_MEDIA_RC0_COUNT_EN(1 << 5) (1 << 5)
9161#define VLV_RENDER_RC0_COUNT_EN(1 << 4) (1 << 4)
9162#define VLV_MEDIA_RC6_COUNT_EN(1 << 1) (1 << 1)
9163#define VLV_RENDER_RC6_COUNT_EN(1 << 0) (1 << 0)
9164#define GEN6_GT_GFX_RC6((const i915_reg_t){ .reg = (0x138108) }) _MMIO(0x138108)((const i915_reg_t){ .reg = (0x138108) })
9165#define VLV_GT_RENDER_RC6((const i915_reg_t){ .reg = (0x138108) }) _MMIO(0x138108)((const i915_reg_t){ .reg = (0x138108) })
9166#define VLV_GT_MEDIA_RC6((const i915_reg_t){ .reg = (0x13810C) }) _MMIO(0x13810C)((const i915_reg_t){ .reg = (0x13810C) })
9167
9168#define GEN6_GT_GFX_RC6p((const i915_reg_t){ .reg = (0x13810C) }) _MMIO(0x13810C)((const i915_reg_t){ .reg = (0x13810C) })
9169#define GEN6_GT_GFX_RC6pp((const i915_reg_t){ .reg = (0x138110) }) _MMIO(0x138110)((const i915_reg_t){ .reg = (0x138110) })
9170#define VLV_RENDER_C0_COUNT((const i915_reg_t){ .reg = (0x138118) }) _MMIO(0x138118)((const i915_reg_t){ .reg = (0x138118) })
9171#define VLV_MEDIA_C0_COUNT((const i915_reg_t){ .reg = (0x13811C) }) _MMIO(0x13811C)((const i915_reg_t){ .reg = (0x13811C) })
9172
9173#define GEN6_PCODE_MAILBOX((const i915_reg_t){ .reg = (0x138124) }) _MMIO(0x138124)((const i915_reg_t){ .reg = (0x138124) })
9174#define GEN6_PCODE_READY(1 << 31) (1 << 31)
9175#define GEN6_PCODE_ERROR_MASK0xFF 0xFF
9176#define GEN6_PCODE_SUCCESS0x0 0x0
9177#define GEN6_PCODE_ILLEGAL_CMD0x1 0x1
9178#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE0x2 0x2
9179#define GEN6_PCODE_TIMEOUT0x3 0x3
9180#define GEN6_PCODE_UNIMPLEMENTED_CMD0xFF 0xFF
9181#define GEN7_PCODE_TIMEOUT0x2 0x2
9182#define GEN7_PCODE_ILLEGAL_DATA0x3 0x3
9183#define GEN11_PCODE_ILLEGAL_SUBCOMMAND0x4 0x4
9184#define GEN11_PCODE_LOCKED0x6 0x6
9185#define GEN11_PCODE_REJECTED0x11 0x11
9186#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE0x10 0x10
9187#define GEN6_PCODE_WRITE_RC6VIDS0x4 0x4
9188#define GEN6_PCODE_READ_RC6VIDS0x5 0x5
9189#define GEN6_ENCODE_RC6_VID(mv)(((mv) - 245) / 5) (((mv) - 245) / 5)
9190#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245) (((vids) * 5) + 245)
9191#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ0x18 0x18
9192#define GEN9_PCODE_READ_MEM_LATENCY0x6 0x6
9193#define GEN9_MEM_LATENCY_LEVEL_MASK0xFF 0xFF
9194#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT8 8
9195#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT16 16
9196#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT24 24
9197#define SKL_PCODE_LOAD_HDCP_KEYS0x5 0x5
9198#define SKL_PCODE_CDCLK_CONTROL0x7 0x7
9199#define SKL_CDCLK_PREPARE_FOR_CHANGE0x3 0x3
9200#define SKL_CDCLK_READY_FOR_CHANGE0x1 0x1
9201#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE0x8 0x8
9202#define GEN6_PCODE_READ_MIN_FREQ_TABLE0x9 0x9
9203#define GEN6_READ_OC_PARAMS0xc 0xc
9204#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO0xd 0xd
9205#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO(0x0 << 8) (0x0 << 8)
9206#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) << 16) | (0x1 << 8)) (((point) << 16) | (0x1 << 8))
9207#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG0xe 0xe
9208#define ICL_PCODE_POINTS_RESTRICTED0x0 0x0
9209#define ICL_PCODE_POINTS_RESTRICTED_MASK0x1 0x1
9210#define GEN6_PCODE_READ_D_COMP0x10 0x10
9211#define GEN6_PCODE_WRITE_D_COMP0x11 0x11
9212#define ICL_PCODE_EXIT_TCCOLD0x12 0x12
9213#define HSW_PCODE_DE_WRITE_FREQ_REQ0x17 0x17
9214#define DISPLAY_IPS_CONTROL0x19 0x19
9215#define TGL_PCODE_TCCOLD0x26 0x26
9216#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
9217#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ0 0
9218#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ((u32)((1UL << (0)) + 0)) REG_BIT(0)((u32)((1UL << (0)) + 0))
9219 /* See also IPS_CTL */
9220#define IPS_PCODE_CONTROL(1 << 30) (1 << 30)
9221#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL0x1A 0x1A
9222#define GEN9_PCODE_SAGV_CONTROL0x21 0x21
9223#define GEN9_SAGV_DISABLE0x0 0x0
9224#define GEN9_SAGV_IS_DISABLED0x1 0x1
9225#define GEN9_SAGV_ENABLE0x3 0x3
9226#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23 0x23
9227#define GEN6_PCODE_DATA((const i915_reg_t){ .reg = (0x138128) }) _MMIO(0x138128)((const i915_reg_t){ .reg = (0x138128) })
9228#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT8 8
9229#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT16 16
9230#define GEN6_PCODE_DATA1((const i915_reg_t){ .reg = (0x13812C) }) _MMIO(0x13812C)((const i915_reg_t){ .reg = (0x13812C) })
9231
9232#define GEN6_GT_CORE_STATUS((const i915_reg_t){ .reg = (0x138060) }) _MMIO(0x138060)((const i915_reg_t){ .reg = (0x138060) })
9233#define GEN6_CORE_CPD_STATE_MASK(7 << 4) (7 << 4)
9234#define GEN6_RCn_MASK7 7
9235#define GEN6_RC00 0
9236#define GEN6_RC32 2
9237#define GEN6_RC63 3
9238#define GEN6_RC74 4
9239
9240#define GEN8_GT_SLICE_INFO((const i915_reg_t){ .reg = (0x138064) }) _MMIO(0x138064)((const i915_reg_t){ .reg = (0x138064) })
9241#define GEN8_LSLICESTAT_MASK0x7 0x7
9242
9243#define CHV_POWER_SS0_SIG1((const i915_reg_t){ .reg = (0xa720) }) _MMIO(0xa720)((const i915_reg_t){ .reg = (0xa720) })
9244#define CHV_POWER_SS1_SIG1((const i915_reg_t){ .reg = (0xa728) }) _MMIO(0xa728)((const i915_reg_t){ .reg = (0xa728) })
9245#define CHV_SS_PG_ENABLE(1 << 1) (1 << 1)
9246#define CHV_EU08_PG_ENABLE(1 << 9) (1 << 9)
9247#define CHV_EU19_PG_ENABLE(1 << 17) (1 << 17)
9248#define CHV_EU210_PG_ENABLE(1 << 25) (1 << 25)
9249
9250#define CHV_POWER_SS0_SIG2((const i915_reg_t){ .reg = (0xa724) }) _MMIO(0xa724)((const i915_reg_t){ .reg = (0xa724) })
9251#define CHV_POWER_SS1_SIG2((const i915_reg_t){ .reg = (0xa72c) }) _MMIO(0xa72c)((const i915_reg_t){ .reg = (0xa72c) })
9252#define CHV_EU311_PG_ENABLE(1 << 1) (1 << 1)
9253
9254#define GEN9_SLICE_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x804c + (slice) * 0x4) }) _MMIO(0x804c + (slice) * 0x4)((const i915_reg_t){ .reg = (0x804c + (slice) * 0x4) })
9255#define GEN10_SLICE_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x804c + ((slice) / 3) * 0x34 + (
(slice) % 3) * 0x4) }) _MMIO(0x804c + ((slice) / 3) * 0x34 + \((const i915_reg_t){ .reg = (0x804c + ((slice) / 3) * 0x34 + (
(slice) % 3) * 0x4) })
9256 ((slice) % 3) * 0x4)((const i915_reg_t){ .reg = (0x804c + ((slice) / 3) * 0x34 + (
(slice) % 3) * 0x4) })
9257#define GEN9_PGCTL_SLICE_ACK(1 << 0) (1 << 0)
9258#define GEN9_PGCTL_SS_ACK(subslice)(1 << (2 + (subslice) * 2)) (1 << (2 + (subslice) * 2))
9259#define GEN10_PGCTL_VALID_SS_MASK(slice)((slice) == 0 ? 0x7F : 0x1F) ((slice) == 0 ? 0x7F : 0x1F)
9260
9261#define GEN9_SS01_EU_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x805c + (slice) * 0x8) }) _MMIO(0x805c + (slice) * 0x8)((const i915_reg_t){ .reg = (0x805c + (slice) * 0x8) })
9262#define GEN10_SS01_EU_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x805c + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) }) _MMIO(0x805c + ((slice) / 3) * 0x30 + \((const i915_reg_t){ .reg = (0x805c + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) })
9263 ((slice) % 3) * 0x8)((const i915_reg_t){ .reg = (0x805c + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) })
9264#define GEN9_SS23_EU_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x8060 + (slice) * 0x8) }) _MMIO(0x8060 + (slice) * 0x8)((const i915_reg_t){ .reg = (0x8060 + (slice) * 0x8) })
9265#define GEN10_SS23_EU_PGCTL_ACK(slice)((const i915_reg_t){ .reg = (0x8060 + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) }) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \((const i915_reg_t){ .reg = (0x8060 + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) })
9266 ((slice) % 3) * 0x8)((const i915_reg_t){ .reg = (0x8060 + ((slice) / 3) * 0x30 + (
(slice) % 3) * 0x8) })
9267#define GEN9_PGCTL_SSA_EU08_ACK(1 << 0) (1 << 0)
9268#define GEN9_PGCTL_SSA_EU19_ACK(1 << 2) (1 << 2)
9269#define GEN9_PGCTL_SSA_EU210_ACK(1 << 4) (1 << 4)
9270#define GEN9_PGCTL_SSA_EU311_ACK(1 << 6) (1 << 6)
9271#define GEN9_PGCTL_SSB_EU08_ACK(1 << 8) (1 << 8)
9272#define GEN9_PGCTL_SSB_EU19_ACK(1 << 10) (1 << 10)
9273#define GEN9_PGCTL_SSB_EU210_ACK(1 << 12) (1 << 12)
9274#define GEN9_PGCTL_SSB_EU311_ACK(1 << 14) (1 << 14)
9275
9276#define GEN7_MISCCPCTL((const i915_reg_t){ .reg = (0x9424) }) _MMIO(0x9424)((const i915_reg_t){ .reg = (0x9424) })
9277#define GEN7_DOP_CLOCK_GATE_ENABLE(1 << 0) (1 << 0)
9278#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE(1 << 2) (1 << 2)
9279#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE(1 << 4) (1 << 4)
9280#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE(1 << 6) (1 << 6)
9281
9282#define GEN8_GARBCNTL((const i915_reg_t){ .reg = (0xB004) }) _MMIO(0xB004)((const i915_reg_t){ .reg = (0xB004) })
9283#define GEN9_GAPS_TSV_CREDIT_DISABLE(1 << 7) (1 << 7)
9284#define GEN11_ARBITRATION_PRIO_ORDER_MASK(0x3f << 22) (0x3f << 22)
9285#define GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0) (0x7f << 0)
9286#define GEN11_HASH_CTRL_EXCL_BIT0(1 << 0) (1 << 0)
9287
9288#define GEN11_GLBLINVL((const i915_reg_t){ .reg = (0xB404) }) _MMIO(0xB404)((const i915_reg_t){ .reg = (0xB404) })
9289#define GEN11_BANK_HASH_ADDR_EXCL_MASK(0x7f << 5) (0x7f << 5)
9290#define GEN11_BANK_HASH_ADDR_EXCL_BIT0(1 << 5) (1 << 5)
9291
9292#define GEN10_DFR_RATIO_EN_AND_CHICKEN((const i915_reg_t){ .reg = (0x9550) }) _MMIO(0x9550)((const i915_reg_t){ .reg = (0x9550) })
9293#define DFR_DISABLE(1 << 9) (1 << 9)
9294
9295#define GEN11_GACB_PERF_CTRL((const i915_reg_t){ .reg = (0x4B80) }) _MMIO(0x4B80)((const i915_reg_t){ .reg = (0x4B80) })
9296#define GEN11_HASH_CTRL_MASK(0x3 << 12 | 0xf << 0) (0x3 << 12 | 0xf << 0)
9297#define GEN11_HASH_CTRL_BIT0(1 << 0) (1 << 0)
9298#define GEN11_HASH_CTRL_BIT4(1 << 12) (1 << 12)
9299
9300#define GEN11_LSN_UNSLCVC((const i915_reg_t){ .reg = (0xB43C) }) _MMIO(0xB43C)((const i915_reg_t){ .reg = (0xB43C) })
9301#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC(1 << 9) (1 << 9)
9302#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC(1 << 7) (1 << 7)
9303
9304#define GEN10_SAMPLER_MODE((const i915_reg_t){ .reg = (0xE18C) }) _MMIO(0xE18C)((const i915_reg_t){ .reg = (0xE18C) })
9305#define ENABLE_SMALLPL((u32)((1UL << (15)) + 0)) REG_BIT(15)((u32)((1UL << (15)) + 0))
9306#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG((u32)((1UL << (5)) + 0)) REG_BIT(5)((u32)((1UL << (5)) + 0))
9307
9308/* IVYBRIDGE DPF */
9309#define GEN7_L3CDERRST1(slice)((const i915_reg_t){ .reg = (0xB008 + (slice) * 0x200) }) _MMIO(0xB008 + (slice) * 0x200)((const i915_reg_t){ .reg = (0xB008 + (slice) * 0x200) }) /* L3CD Error Status 1 */
9310#define GEN7_L3CDERRST1_ROW_MASK(0x7ff << 14) (0x7ff << 14)
9311#define GEN7_PARITY_ERROR_VALID(1 << 13) (1 << 13)
9312#define GEN7_L3CDERRST1_BANK_MASK(3 << 11) (3 << 11)
9313#define GEN7_L3CDERRST1_SUBBANK_MASK(7 << 8) (7 << 8)
9314#define GEN7_PARITY_ERROR_ROW(reg)(((reg) & (0x7ff << 14)) >> 14) \
9315 (((reg) & GEN7_L3CDERRST1_ROW_MASK(0x7ff << 14)) >> 14)
9316#define GEN7_PARITY_ERROR_BANK(reg)(((reg) & (3 << 11)) >> 11) \
9317 (((reg) & GEN7_L3CDERRST1_BANK_MASK(3 << 11)) >> 11)
9318#define GEN7_PARITY_ERROR_SUBBANK(reg)(((reg) & (7 << 8)) >> 8) \
9319 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK(7 << 8)) >> 8)
9320#define GEN7_L3CDERRST1_ENABLE(1 << 7) (1 << 7)
9321
9322#define GEN7_L3LOG(slice, i)((const i915_reg_t){ .reg = (0xB070 + (slice) * 0x200 + (i) *
4) }) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)((const i915_reg_t){ .reg = (0xB070 + (slice) * 0x200 + (i) *
4) })
9323#define GEN7_L3LOG_SIZE0x80 0x80
9324
9325#define GEN7_HALF_SLICE_CHICKEN1((const i915_reg_t){ .reg = (0xe100) }) _MMIO(0xe100)((const i915_reg_t){ .reg = (0xe100) }) /* IVB GT1 + VLV */
9326#define GEN7_HALF_SLICE_CHICKEN1_GT2((const i915_reg_t){ .reg = (0xf100) }) _MMIO(0xf100)((const i915_reg_t){ .reg = (0xf100) })
9327#define GEN7_MAX_PS_THREAD_DEP(8 << 12) (8 << 12)
9328#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE(1 << 10) (1 << 10)
9329#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE(1 << 4) (1 << 4)
9330#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE(1 << 3) (1 << 3)
9331
9332#define GEN9_HALF_SLICE_CHICKEN5((const i915_reg_t){ .reg = (0xe188) }) _MMIO(0xe188)((const i915_reg_t){ .reg = (0xe188) })
9333#define GEN9_DG_MIRROR_FIX_ENABLE(1 << 5) (1 << 5)
9334#define GEN9_CCS_TLB_PREFETCH_ENABLE(1 << 3) (1 << 3)
9335
9336#define GEN8_ROW_CHICKEN((const i915_reg_t){ .reg = (0xe4f0) }) _MMIO(0xe4f0)((const i915_reg_t){ .reg = (0xe4f0) })
9337#define FLOW_CONTROL_ENABLE(1 << 15) (1 << 15)
9338#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE(1 << 8) (1 << 8)
9339#define STALL_DOP_GATING_DISABLE(1 << 5) (1 << 5)
9340#define THROTTLE_12_5(7 << 2) (7 << 2)
9341#define DISABLE_EARLY_EOT(1 << 1) (1 << 1)
9342
9343#define GEN7_ROW_CHICKEN2((const i915_reg_t){ .reg = (0xe4f4) }) _MMIO(0xe4f4)((const i915_reg_t){ .reg = (0xe4f4) })
9344#define GEN12_DISABLE_EARLY_READ((u32)((1UL << (14)) + 0)) REG_BIT(14)((u32)((1UL << (14)) + 0))
9345#define GEN12_PUSH_CONST_DEREF_HOLD_DIS((u32)((1UL << (8)) + 0)) REG_BIT(8)((u32)((1UL << (8)) + 0))
9346
9347#define GEN7_ROW_CHICKEN2_GT2((const i915_reg_t){ .reg = (0xf4f4) }) _MMIO(0xf4f4)((const i915_reg_t){ .reg = (0xf4f4) })
9348#define DOP_CLOCK_GATING_DISABLE(1 << 0) (1 << 0)
9349#define PUSH_CONSTANT_DEREF_DISABLE(1 << 8) (1 << 8)
9350#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE(1 << 1) (1 << 1)
9351
9352#define GEN9_ROW_CHICKEN4((const i915_reg_t){ .reg = (0xe48c) }) _MMIO(0xe48c)((const i915_reg_t){ .reg = (0xe48c) })
9353#define GEN12_DISABLE_TDL_PUSH((u32)((1UL << (9)) + 0)) REG_BIT(9)((u32)((1UL << (9)) + 0))
9354#define GEN11_DIS_PICK_2ND_EU((u32)((1UL << (7)) + 0)) REG_BIT(7)((u32)((1UL << (7)) + 0))
9355
9356#define HSW_ROW_CHICKEN3((const i915_reg_t){ .reg = (0xe49c) }) _MMIO(0xe49c)((const i915_reg_t){ .reg = (0xe49c) })
9357#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6) (1 << 6)
9358
9359#define HALF_SLICE_CHICKEN2((const i915_reg_t){ .reg = (0xe180) }) _MMIO(0xe180)((const i915_reg_t){ .reg = (0xe180) })
9360#define GEN8_ST_PO_DISABLE(1 << 13) (1 << 13)
9361
9362#define HALF_SLICE_CHICKEN3((const i915_reg_t){ .reg = (0xe184) }) _MMIO(0xe184)((const i915_reg_t){ .reg = (0xe184) })
9363#define HSW_SAMPLE_C_PERFORMANCE(1 << 9) (1 << 9)
9364#define GEN8_CENTROID_PIXEL_OPT_DIS(1 << 8) (1 << 8)
9365#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC(1 << 5) (1 << 5)
9366#define CNL_FAST_ANISO_L1_BANKING_FIX(1 << 4) (1 << 4)
9367#define GEN8_SAMPLER_POWER_BYPASS_DIS(1 << 1) (1 << 1)
9368
9369#define GEN9_HALF_SLICE_CHICKEN7((const i915_reg_t){ .reg = (0xe194) }) _MMIO(0xe194)((const i915_reg_t){ .reg = (0xe194) })
9370#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR(1 << 8) (1 << 8)
9371#define GEN9_ENABLE_YV12_BUGFIX(1 << 4) (1 << 4)
9372#define GEN9_ENABLE_GPGPU_PREEMPTION(1 << 2) (1 << 2)
9373
9374/* Audio */
9375#define G4X_AUD_VID_DID((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x62020) }) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display_mmio_offset) + 0x62020) })
9376#define INTEL_AUDIO_DEVCL0x808629FB 0x808629FB
9377#define INTEL_AUDIO_DEVBLC0x80862801 0x80862801
9378#define INTEL_AUDIO_DEVCTG0x80862802 0x80862802
9379
9380#define G4X_AUD_CNTL_ST((const i915_reg_t){ .reg = (0x620B4) }) _MMIO(0x620B4)((const i915_reg_t){ .reg = (0x620B4) })
9381#define G4X_ELDV_DEVCL_DEVBLC(1 << 13) (1 << 13)
9382#define G4X_ELDV_DEVCTG(1 << 14) (1 << 14)
9383#define G4X_ELD_ADDR_MASK(0xf << 5) (0xf << 5)
9384#define G4X_ELD_ACK(1 << 4) (1 << 4)
9385#define G4X_HDMIW_HDMIEDID((const i915_reg_t){ .reg = (0x6210C) }) _MMIO(0x6210C)((const i915_reg_t){ .reg = (0x6210C) })
9386
9387#define _IBX_HDMIW_HDMIEDID_A0xE2050 0xE2050
9388#define _IBX_HDMIW_HDMIEDID_B0xE2150 0xE2150
9389#define IBX_HDMIW_HDMIEDID(pipe)((const i915_reg_t){ .reg = (((0xE2050) + (pipe) * ((0xE2150)
- (0xE2050)))) }) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \((const i915_reg_t){ .reg = (((0xE2050) + (pipe) * ((0xE2150)
- (0xE2050)))) })
9390 _IBX_HDMIW_HDMIEDID_B)((const i915_reg_t){ .reg = (((0xE2050) + (pipe) * ((0xE2150)
- (0xE2050)))) })
9391#define _IBX_AUD_CNTL_ST_A0xE20B4 0xE20B4
9392#define _IBX_AUD_CNTL_ST_B0xE21B4 0xE21B4
9393#define IBX_AUD_CNTL_ST(pipe)((const i915_reg_t){ .reg = (((0xE20B4) + (pipe) * ((0xE21B4)
- (0xE20B4)))) }) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \((const i915_reg_t){ .reg = (((0xE20B4) + (pipe) * ((0xE21B4)
- (0xE20B4)))) })
9394 _IBX_AUD_CNTL_ST_B)((const i915_reg_t){ .reg = (((0xE20B4) + (pipe) * ((0xE21B4)
- (0xE20B4)))) })
9395#define IBX_ELD_BUFFER_SIZE_MASK(0x1f << 10) (0x1f << 10)
9396#define IBX_ELD_ADDRESS_MASK(0x1f << 5) (0x1f << 5)
9397#define IBX_ELD_ACK(1 << 4) (1 << 4)
9398#define IBX_AUD_CNTL_ST2((const i915_reg_t){ .reg = (0xE20C0) }) _MMIO(0xE20C0)((const i915_reg_t){ .reg = (0xE20C0) })
9399#define IBX_CP_READY(port)((1 << 1) << (((port) - 1) * 4)) ((1 << 1) << (((port) - 1) * 4))
9400#define IBX_ELD_VALID(port)((1 << 0) << (((port) - 1) * 4)) ((1 << 0) << (((port) - 1) * 4))
9401
9402#define _CPT_HDMIW_HDMIEDID_A0xE5050 0xE5050
9403#define _CPT_HDMIW_HDMIEDID_B0xE5150 0xE5150
9404#define CPT_HDMIW_HDMIEDID(pipe)((const i915_reg_t){ .reg = (((0xE5050) + (pipe) * ((0xE5150)
- (0xE5050)))) }) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)((const i915_reg_t){ .reg = (((0xE5050) + (pipe) * ((0xE5150)
- (0xE5050)))) })
9405#define _CPT_AUD_CNTL_ST_A0xE50B4 0xE50B4
9406#define _CPT_AUD_CNTL_ST_B0xE51B4 0xE51B4
9407#define CPT_AUD_CNTL_ST(pipe)((const i915_reg_t){ .reg = (((0xE50B4) + (pipe) * ((0xE51B4)
- (0xE50B4)))) }) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)((const i915_reg_t){ .reg = (((0xE50B4) + (pipe) * ((0xE51B4)
- (0xE50B4)))) })
9408#define CPT_AUD_CNTRL_ST2((const i915_reg_t){ .reg = (0xE50C0) }) _MMIO(0xE50C0)((const i915_reg_t){ .reg = (0xE50C0) })
9409
9410#define _VLV_HDMIW_HDMIEDID_A(0x180000 + 0x62050) (VLV_DISPLAY_BASE0x180000 + 0x62050)
9411#define _VLV_HDMIW_HDMIEDID_B(0x180000 + 0x62150) (VLV_DISPLAY_BASE0x180000 + 0x62150)
9412#define VLV_HDMIW_HDMIEDID(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x62050)) + (pipe)
* (((0x180000 + 0x62150)) - ((0x180000 + 0x62050))))) }) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)((const i915_reg_t){ .reg = ((((0x180000 + 0x62050)) + (pipe)
* (((0x180000 + 0x62150)) - ((0x180000 + 0x62050))))) })
9413#define _VLV_AUD_CNTL_ST_A(0x180000 + 0x620B4) (VLV_DISPLAY_BASE0x180000 + 0x620B4)
9414#define _VLV_AUD_CNTL_ST_B(0x180000 + 0x621B4) (VLV_DISPLAY_BASE0x180000 + 0x621B4)
9415#define VLV_AUD_CNTL_ST(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x620B4)) + (pipe)
* (((0x180000 + 0x621B4)) - ((0x180000 + 0x620B4))))) }) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)((const i915_reg_t){ .reg = ((((0x180000 + 0x620B4)) + (pipe)
* (((0x180000 + 0x621B4)) - ((0x180000 + 0x620B4))))) })
9416#define VLV_AUD_CNTL_ST2((const i915_reg_t){ .reg = (0x180000 + 0x620C0) }) _MMIO(VLV_DISPLAY_BASE + 0x620C0)((const i915_reg_t){ .reg = (0x180000 + 0x620C0) })
9417
9418/* These are the 4 32-bit write offset registers for each stream
9419 * output buffer. It determines the offset from the
9420 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9421 */
9422#define GEN7_SO_WRITE_OFFSET(n)((const i915_reg_t){ .reg = (0x5280 + (n) * 4) }) _MMIO(0x5280 + (n) * 4)((const i915_reg_t){ .reg = (0x5280 + (n) * 4) })
9423
9424#define _IBX_AUD_CONFIG_A0xe2000 0xe2000
9425#define _IBX_AUD_CONFIG_B0xe2100 0xe2100
9426#define IBX_AUD_CFG(pipe)((const i915_reg_t){ .reg = (((0xe2000) + (pipe) * ((0xe2100)
- (0xe2000)))) }) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)((const i915_reg_t){ .reg = (((0xe2000) + (pipe) * ((0xe2100)
- (0xe2000)))) })
9427#define _CPT_AUD_CONFIG_A0xe5000 0xe5000
9428#define _CPT_AUD_CONFIG_B0xe5100 0xe5100
9429#define CPT_AUD_CFG(pipe)((const i915_reg_t){ .reg = (((0xe5000) + (pipe) * ((0xe5100)
- (0xe5000)))) }) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)((const i915_reg_t){ .reg = (((0xe5000) + (pipe) * ((0xe5100)
- (0xe5000)))) })
9430#define _VLV_AUD_CONFIG_A(0x180000 + 0x62000) (VLV_DISPLAY_BASE0x180000 + 0x62000)
9431#define _VLV_AUD_CONFIG_B(0x180000 + 0x62100) (VLV_DISPLAY_BASE0x180000 + 0x62100)
9432#define VLV_AUD_CFG(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x62000)) + (pipe)
* (((0x180000 + 0x62100)) - ((0x180000 + 0x62000))))) }) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)((const i915_reg_t){ .reg = ((((0x180000 + 0x62000)) + (pipe)
* (((0x180000 + 0x62100)) - ((0x180000 + 0x62000))))) })
9433
9434#define AUD_CONFIG_N_VALUE_INDEX(1 << 29) (1 << 29)
9435#define AUD_CONFIG_N_PROG_ENABLE(1 << 28) (1 << 28)
9436#define AUD_CONFIG_UPPER_N_SHIFT20 20
9437#define AUD_CONFIG_UPPER_N_MASK(0xff << 20) (0xff << 20)
9438#define AUD_CONFIG_LOWER_N_SHIFT4 4
9439#define AUD_CONFIG_LOWER_N_MASK(0xfff << 4) (0xfff << 4)
9440#define AUD_CONFIG_N_MASK((0xff << 20) | (0xfff << 4)) (AUD_CONFIG_UPPER_N_MASK(0xff << 20) | AUD_CONFIG_LOWER_N_MASK(0xfff << 4))
9441#define AUD_CONFIG_N(n)(((((n) >> 12) & 0xff) << 20) | (((n) & 0xfff
) << 4)) \
9442 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT20) | \
9443 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT4))
9444#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT16 16
9445#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK(0xf << 16) (0xf << 16)
9446#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175(0 << 16) (0 << 16)
9447#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200(1 << 16) (1 << 16)
9448#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000(2 << 16) (2 << 16)
9449#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027(3 << 16) (3 << 16)
9450#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000(4 << 16) (4 << 16)
9451#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054(5 << 16) (5 << 16)
9452#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176(6 << 16) (6 << 16)
9453#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250(7 << 16) (7 << 16)
9454#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352(8 << 16) (8 << 16)
9455#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500(9 << 16) (9 << 16)
9456#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703(10 << 16) (10 << 16)
9457#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000(11 << 16) (11 << 16)
9458#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407(12 << 16) (12 << 16)
9459#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000(13 << 16) (13 << 16)
9460#define AUD_CONFIG_DISABLE_NCTS(1 << 3) (1 << 3)
9461
9462/* HSW Audio */
9463#define _HSW_AUD_CONFIG_A0x65000 0x65000
9464#define _HSW_AUD_CONFIG_B0x65100 0x65100
9465#define HSW_AUD_CFG(trans)((const i915_reg_t){ .reg = (((0x65000) + (trans) * ((0x65100
) - (0x65000)))) }) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)((const i915_reg_t){ .reg = (((0x65000) + (trans) * ((0x65100
) - (0x65000)))) })
9466
9467#define _HSW_AUD_MISC_CTRL_A0x65010 0x65010
9468#define _HSW_AUD_MISC_CTRL_B0x65110 0x65110
9469#define HSW_AUD_MISC_CTRL(trans)((const i915_reg_t){ .reg = (((0x65010) + (trans) * ((0x65110
) - (0x65010)))) }) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)((const i915_reg_t){ .reg = (((0x65010) + (trans) * ((0x65110
) - (0x65010)))) })
9470
9471#define _HSW_AUD_M_CTS_ENABLE_A0x65028 0x65028
9472#define _HSW_AUD_M_CTS_ENABLE_B0x65128 0x65128
9473#define HSW_AUD_M_CTS_ENABLE(trans)((const i915_reg_t){ .reg = (((0x65028) + (trans) * ((0x65128
) - (0x65028)))) }) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)((const i915_reg_t){ .reg = (((0x65028) + (trans) * ((0x65128
) - (0x65028)))) })
9474#define AUD_M_CTS_M_VALUE_INDEX(1 << 21) (1 << 21)
9475#define AUD_M_CTS_M_PROG_ENABLE(1 << 20) (1 << 20)
9476#define AUD_CONFIG_M_MASK0xfffff 0xfffff
9477
9478#define _HSW_AUD_DIP_ELD_CTRL_ST_A0x650b4 0x650b4
9479#define _HSW_AUD_DIP_ELD_CTRL_ST_B0x651b4 0x651b4
9480#define HSW_AUD_DIP_ELD_CTRL(trans)((const i915_reg_t){ .reg = (((0x650b4) + (trans) * ((0x651b4
) - (0x650b4)))) }) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)((const i915_reg_t){ .reg = (((0x650b4) + (trans) * ((0x651b4
) - (0x650b4)))) })
9481
9482/* Audio Digital Converter */
9483#define _HSW_AUD_DIG_CNVT_10x65080 0x65080
9484#define _HSW_AUD_DIG_CNVT_20x65180 0x65180
9485#define AUD_DIG_CNVT(trans)((const i915_reg_t){ .reg = (((0x65080) + (trans) * ((0x65180
) - (0x65080)))) }) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)((const i915_reg_t){ .reg = (((0x65080) + (trans) * ((0x65180
) - (0x65080)))) })
9486#define DIP_PORT_SEL_MASK0x3 0x3
9487
9488#define _HSW_AUD_EDID_DATA_A0x65050 0x65050
9489#define _HSW_AUD_EDID_DATA_B0x65150 0x65150
9490#define HSW_AUD_EDID_DATA(trans)((const i915_reg_t){ .reg = (((0x65050) + (trans) * ((0x65150
) - (0x65050)))) }) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)((const i915_reg_t){ .reg = (((0x65050) + (trans) * ((0x65150
) - (0x65050)))) })
9491
9492#define HSW_AUD_PIPE_CONV_CFG((const i915_reg_t){ .reg = (0x6507c) }) _MMIO(0x6507c)((const i915_reg_t){ .reg = (0x6507c) })
9493#define HSW_AUD_PIN_ELD_CP_VLD((const i915_reg_t){ .reg = (0x650c0) }) _MMIO(0x650c0)((const i915_reg_t){ .reg = (0x650c0) })
9494#define AUDIO_INACTIVE(trans)((1 << 3) << ((trans) * 4)) ((1 << 3) << ((trans) * 4))
9495#define AUDIO_OUTPUT_ENABLE(trans)((1 << 2) << ((trans) * 4)) ((1 << 2) << ((trans) * 4))
9496#define AUDIO_CP_READY(trans)((1 << 1) << ((trans) * 4)) ((1 << 1) << ((trans) * 4))
9497#define AUDIO_ELD_VALID(trans)((1 << 0) << ((trans) * 4)) ((1 << 0) << ((trans) * 4))
9498
9499#define HSW_AUD_CHICKENBIT((const i915_reg_t){ .reg = (0x65f10) }) _MMIO(0x65f10)((const i915_reg_t){ .reg = (0x65f10) })
9500#define SKL_AUD_CODEC_WAKE_SIGNAL(1 << 15) (1 << 15)
9501
9502#define AUD_FREQ_CNTRL((const i915_reg_t){ .reg = (0x65900) }) _MMIO(0x65900)((const i915_reg_t){ .reg = (0x65900) })
9503#define AUD_PIN_BUF_CTL((const i915_reg_t){ .reg = (0x48414) }) _MMIO(0x48414)((const i915_reg_t){ .reg = (0x48414) })
9504#define AUD_PIN_BUF_ENABLE((u32)((1UL << (31)) + 0)) REG_BIT(31)((u32)((1UL << (31)) + 0))
9505
9506/* Display Audio Config Reg */
9507#define AUD_CONFIG_BE((const i915_reg_t){ .reg = (0x65ef0) }) _MMIO(0x65ef0)((const i915_reg_t){ .reg = (0x65ef0) })
9508#define HBLANK_EARLY_ENABLE_ICL(pipe)(0x1 << (20 - (pipe))) (0x1 << (20 - (pipe)))
9509#define HBLANK_EARLY_ENABLE_TGL(pipe)(0x1 << (24 + (pipe))) (0x1 << (24 + (pipe)))
9510#define HBLANK_START_COUNT_MASK(pipe)(0x7 << (3 + ((pipe) * 6))) (0x7 << (3 + ((pipe) * 6)))
9511#define HBLANK_START_COUNT(pipe, val)(((val) & 0x7) << (3 + ((pipe)) * 6)) (((val) & 0x7) << (3 + ((pipe)) * 6))
9512#define NUMBER_SAMPLES_PER_LINE_MASK(pipe)(0x3 << ((pipe) * 6)) (0x3 << ((pipe) * 6))
9513#define NUMBER_SAMPLES_PER_LINE(pipe, val)(((val) & 0x3) << ((pipe) * 6)) (((val) & 0x3) << ((pipe) * 6))
9514
9515#define HBLANK_START_COUNT_80 0
9516#define HBLANK_START_COUNT_161 1
9517#define HBLANK_START_COUNT_322 2
9518#define HBLANK_START_COUNT_643 3
9519#define HBLANK_START_COUNT_964 4
9520#define HBLANK_START_COUNT_1285 5
9521
9522/*
9523 * HSW - ICL power wells
9524 *
9525 * Platforms have up to 3 power well control register sets, each set
9526 * controlling up to 16 power wells via a request/status HW flag tuple:
9527 * - main (HSW_PWR_WELL_CTL[1-4])
9528 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9529 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9530 * Each control register set consists of up to 4 registers used by different
9531 * sources that can request a power well to be enabled:
9532 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9533 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9534 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9535 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9536 */
9537#define HSW_PWR_WELL_CTL1((const i915_reg_t){ .reg = (0x45400) }) _MMIO(0x45400)((const i915_reg_t){ .reg = (0x45400) })
9538#define HSW_PWR_WELL_CTL2((const i915_reg_t){ .reg = (0x45404) }) _MMIO(0x45404)((const i915_reg_t){ .reg = (0x45404) })
9539#define HSW_PWR_WELL_CTL3((const i915_reg_t){ .reg = (0x45408) }) _MMIO(0x45408)((const i915_reg_t){ .reg = (0x45408) })
9540#define HSW_PWR_WELL_CTL4((const i915_reg_t){ .reg = (0x4540C) }) _MMIO(0x4540C)((const i915_reg_t){ .reg = (0x4540C) })
9541#define HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)) (0x2 << ((pw_idx) * 2))
9542#define HSW_PWR_WELL_CTL_STATE(pw_idx)(0x1 << ((pw_idx) * 2)) (0x1 << ((pw_idx) * 2))
9543
9544/* HSW/BDW power well */
9545#define HSW_PW_CTL_IDX_GLOBAL15 15
9546
9547/* SKL/BXT/GLK/CNL power wells */
9548#define SKL_PW_CTL_IDX_PW_215 15
9549#define SKL_PW_CTL_IDX_PW_114 14
9550#define CNL_PW_CTL_IDX_AUX_F12 12
9551#define CNL_PW_CTL_IDX_AUX_D11 11
9552#define GLK_PW_CTL_IDX_AUX_C10 10
9553#define GLK_PW_CTL_IDX_AUX_B9 9
9554#define GLK_PW_CTL_IDX_AUX_A8 8
9555#define CNL_PW_CTL_IDX_DDI_F6 6
9556#define SKL_PW_CTL_IDX_DDI_D4 4
9557#define SKL_PW_CTL_IDX_DDI_C3 3
9558#define SKL_PW_CTL_IDX_DDI_B2 2
9559#define SKL_PW_CTL_IDX_DDI_A_E1 1
9560#define GLK_PW_CTL_IDX_DDI_A1 1
9561#define SKL_PW_CTL_IDX_MISC_IO0 0
9562
9563/* ICL/TGL - power wells */
9564#define TGL_PW_CTL_IDX_PW_54 4
9565#define ICL_PW_CTL_IDX_PW_43 3
9566#define ICL_PW_CTL_IDX_PW_32 2
9567#define ICL_PW_CTL_IDX_PW_21 1
9568#define ICL_PW_CTL_IDX_PW_10 0
9569
9570#define ICL_PWR_WELL_CTL_AUX1((const i915_reg_t){ .reg = (0x45440) }) _MMIO(0x45440)((const i915_reg_t){ .reg = (0x45440) })
9571#define ICL_PWR_WELL_CTL_AUX2((const i915_reg_t){ .reg = (0x45444) }) _MMIO(0x45444)((const i915_reg_t){ .reg = (0x45444) })
9572#define ICL_PWR_WELL_CTL_AUX4((const i915_reg_t){ .reg = (0x4544C) }) _MMIO(0x4544C)((const i915_reg_t){ .reg = (0x4544C) })
9573#define TGL_PW_CTL_IDX_AUX_TBT614 14
9574#define TGL_PW_CTL_IDX_AUX_TBT513 13
9575#define TGL_PW_CTL_IDX_AUX_TBT412 12
9576#define ICL_PW_CTL_IDX_AUX_TBT411 11
9577#define TGL_PW_CTL_IDX_AUX_TBT311 11
9578#define ICL_PW_CTL_IDX_AUX_TBT310 10
9579#define TGL_PW_CTL_IDX_AUX_TBT210 10
9580#define ICL_PW_CTL_IDX_AUX_TBT29 9
9581#define TGL_PW_CTL_IDX_AUX_TBT19 9
9582#define ICL_PW_CTL_IDX_AUX_TBT18 8
9583#define TGL_PW_CTL_IDX_AUX_TC68 8
9584#define TGL_PW_CTL_IDX_AUX_TC57 7
9585#define TGL_PW_CTL_IDX_AUX_TC46 6
9586#define ICL_PW_CTL_IDX_AUX_F5 5
9587#define TGL_PW_CTL_IDX_AUX_TC35 5
9588#define ICL_PW_CTL_IDX_AUX_E4 4
9589#define TGL_PW_CTL_IDX_AUX_TC24 4
9590#define ICL_PW_CTL_IDX_AUX_D3 3
9591#define TGL_PW_CTL_IDX_AUX_TC13 3
9592#define ICL_PW_CTL_IDX_AUX_C2 2
9593#define ICL_PW_CTL_IDX_AUX_B1 1
9594#define ICL_PW_CTL_IDX_AUX_A0 0
9595
9596#define ICL_PWR_WELL_CTL_DDI1((const i915_reg_t){ .reg = (0x45450) }) _MMIO(0x45450)((const i915_reg_t){ .reg = (0x45450) })
9597#define ICL_PWR_WELL_CTL_DDI2((const i915_reg_t){ .reg = (0x45454) }) _MMIO(0x45454)((const i915_reg_t){ .reg = (0x45454) })
9598#define ICL_PWR_WELL_CTL_DDI4((const i915_reg_t){ .reg = (0x4545C) }) _MMIO(0x4545C)((const i915_reg_t){ .reg = (0x4545C) })
9599#define TGL_PW_CTL_IDX_DDI_TC68 8
9600#define TGL_PW_CTL_IDX_DDI_TC57 7
9601#define TGL_PW_CTL_IDX_DDI_TC46 6
9602#define ICL_PW_CTL_IDX_DDI_F5 5
9603#define TGL_PW_CTL_IDX_DDI_TC35 5
9604#define ICL_PW_CTL_IDX_DDI_E4 4
9605#define TGL_PW_CTL_IDX_DDI_TC24 4
9606#define ICL_PW_CTL_IDX_DDI_D3 3
9607#define TGL_PW_CTL_IDX_DDI_TC13 3
9608#define ICL_PW_CTL_IDX_DDI_C2 2
9609#define ICL_PW_CTL_IDX_DDI_B1 1
9610#define ICL_PW_CTL_IDX_DDI_A0 0
9611
9612/* HSW - power well misc debug registers */
9613#define HSW_PWR_WELL_CTL5((const i915_reg_t){ .reg = (0x45410) }) _MMIO(0x45410)((const i915_reg_t){ .reg = (0x45410) })
9614#define HSW_PWR_WELL_ENABLE_SINGLE_STEP(1 << 31) (1 << 31)
9615#define HSW_PWR_WELL_PWR_GATE_OVERRIDE(1 << 20) (1 << 20)
9616#define HSW_PWR_WELL_FORCE_ON(1 << 19) (1 << 19)
9617#define HSW_PWR_WELL_CTL6((const i915_reg_t){ .reg = (0x45414) }) _MMIO(0x45414)((const i915_reg_t){ .reg = (0x45414) })
9618
9619/* SKL Fuse Status */
9620enum skl_power_gate {
9621 SKL_PG0,
9622 SKL_PG1,
9623 SKL_PG2,
9624 ICL_PG3,
9625 ICL_PG4,
9626};
9627
9628#define SKL_FUSE_STATUS((const i915_reg_t){ .reg = (0x42000) }) _MMIO(0x42000)((const i915_reg_t){ .reg = (0x42000) })
9629#define SKL_FUSE_DOWNLOAD_STATUS(1 << 31) (1 << 31)
9630/*
9631 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9632 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9633 */
9634#define SKL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 14 + SKL_PG1) \
9635 ((pw_idx) - SKL_PW_CTL_IDX_PW_114 + SKL_PG1)
9636/*
9637 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9638 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9639 */
9640#define ICL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 0 + SKL_PG1) \
9641 ((pw_idx) - ICL_PW_CTL_IDX_PW_10 + SKL_PG1)
9642#define SKL_FUSE_PG_DIST_STATUS(pg)(1 << (27 - (pg))) (1 << (27 - (pg)))
9643
9644#define _CNL_AUX_REG_IDX(pw_idx)((pw_idx) - 9) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B9)
9645#define _CNL_AUX_ANAOVRD1_B0x162250 0x162250
9646#define _CNL_AUX_ANAOVRD1_C0x162210 0x162210
9647#define _CNL_AUX_ANAOVRD1_D0x1622D0 0x1622D0
9648#define _CNL_AUX_ANAOVRD1_F0x162A90 0x162A90
9649#define CNL_AUX_ANAOVRD1(pw_idx)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) }) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) })
9650 _CNL_AUX_ANAOVRD1_B, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) })
9651 _CNL_AUX_ANAOVRD1_C, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) })
9652 _CNL_AUX_ANAOVRD1_D, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) })
9653 _CNL_AUX_ANAOVRD1_F))((const i915_reg_t){ .reg = ((((const u32 []){ 0x162250, 0x162210
, 0x1622D0, 0x162A90 })[((pw_idx) - 9)])) })
9654#define CNL_AUX_ANAOVRD1_ENABLE(1 << 16) (1 << 16)
9655#define CNL_AUX_ANAOVRD1_LDO_BYPASS(1 << 23) (1 << 23)
9656
9657#define _ICL_AUX_REG_IDX(pw_idx)((pw_idx) - 0) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A0)
9658#define _ICL_AUX_ANAOVRD1_A0x162398 0x162398
9659#define _ICL_AUX_ANAOVRD1_B0x6C398 0x6C398
9660#define ICL_AUX_ANAOVRD1(pw_idx)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) }) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) })
9661 _ICL_AUX_ANAOVRD1_A, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) })
9662 _ICL_AUX_ANAOVRD1_B))((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) })
9663#define ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7) (1 << 7)
9664#define ICL_AUX_ANAOVRD1_ENABLE(1 << 0) (1 << 0)
9665
9666/* HDCP Key Registers */
9667#define HDCP_KEY_CONF((const i915_reg_t){ .reg = (0x66c00) }) _MMIO(0x66c00)((const i915_reg_t){ .reg = (0x66c00) })
9668#define HDCP_AKSV_SEND_TRIGGER(1UL << (31)) BIT(31)(1UL << (31))
9669#define HDCP_CLEAR_KEYS_TRIGGER(1UL << (30)) BIT(30)(1UL << (30))
9670#define HDCP_KEY_LOAD_TRIGGER(1UL << (8)) BIT(8)(1UL << (8))
9671#define HDCP_KEY_STATUS((const i915_reg_t){ .reg = (0x66c04) }) _MMIO(0x66c04)((const i915_reg_t){ .reg = (0x66c04) })
9672#define HDCP_FUSE_IN_PROGRESS(1UL << (7)) BIT(7)(1UL << (7))
9673#define HDCP_FUSE_ERROR(1UL << (6)) BIT(6)(1UL << (6))
9674#define HDCP_FUSE_DONE(1UL << (5)) BIT(5)(1UL << (5))
9675#define HDCP_KEY_LOAD_STATUS(1UL << (1)) BIT(1)(1UL << (1))
9676#define HDCP_KEY_LOAD_DONE(1UL << (0)) BIT(0)(1UL << (0))
9677#define HDCP_AKSV_LO((const i915_reg_t){ .reg = (0x66c10) }) _MMIO(0x66c10)((const i915_reg_t){ .reg = (0x66c10) })
9678#define HDCP_AKSV_HI((const i915_reg_t){ .reg = (0x66c14) }) _MMIO(0x66c14)((const i915_reg_t){ .reg = (0x66c14) })
9679
9680/* HDCP Repeater Registers */
9681#define HDCP_REP_CTL((const i915_reg_t){ .reg = (0x66d00) }) _MMIO(0x66d00)((const i915_reg_t){ .reg = (0x66d00) })
9682#define HDCP_TRANSA_REP_PRESENT(1UL << (31)) BIT(31)(1UL << (31))
9683#define HDCP_TRANSB_REP_PRESENT(1UL << (30)) BIT(30)(1UL << (30))
9684#define HDCP_TRANSC_REP_PRESENT(1UL << (29)) BIT(29)(1UL << (29))
9685#define HDCP_TRANSD_REP_PRESENT(1UL << (28)) BIT(28)(1UL << (28))
9686#define HDCP_DDIB_REP_PRESENT(1UL << (30)) BIT(30)(1UL << (30))
9687#define HDCP_DDIA_REP_PRESENT(1UL << (29)) BIT(29)(1UL << (29))
9688#define HDCP_DDIC_REP_PRESENT(1UL << (28)) BIT(28)(1UL << (28))
9689#define HDCP_DDID_REP_PRESENT(1UL << (27)) BIT(27)(1UL << (27))
9690#define HDCP_DDIF_REP_PRESENT(1UL << (26)) BIT(26)(1UL << (26))
9691#define HDCP_DDIE_REP_PRESENT(1UL << (25)) BIT(25)(1UL << (25))
9692#define HDCP_TRANSA_SHA1_M0(1 << 20) (1 << 20)
9693#define HDCP_TRANSB_SHA1_M0(2 << 20) (2 << 20)
9694#define HDCP_TRANSC_SHA1_M0(3 << 20) (3 << 20)
9695#define HDCP_TRANSD_SHA1_M0(4 << 20) (4 << 20)
9696#define HDCP_DDIB_SHA1_M0(1 << 20) (1 << 20)
9697#define HDCP_DDIA_SHA1_M0(2 << 20) (2 << 20)
9698#define HDCP_DDIC_SHA1_M0(3 << 20) (3 << 20)
9699#define HDCP_DDID_SHA1_M0(4 << 20) (4 << 20)
9700#define HDCP_DDIF_SHA1_M0(5 << 20) (5 << 20)
9701#define HDCP_DDIE_SHA1_M0(6 << 20) (6 << 20) /* Bspec says 5? */
9702#define HDCP_SHA1_BUSY(1UL << (16)) BIT(16)(1UL << (16))
9703#define HDCP_SHA1_READY(1UL << (17)) BIT(17)(1UL << (17))
9704#define HDCP_SHA1_COMPLETE(1UL << (18)) BIT(18)(1UL << (18))
9705#define HDCP_SHA1_V_MATCH(1UL << (19)) BIT(19)(1UL << (19))
9706#define HDCP_SHA1_TEXT_32(1 << 1) (1 << 1)
9707#define HDCP_SHA1_COMPLETE_HASH(2 << 1) (2 << 1)
9708#define HDCP_SHA1_TEXT_24(4 << 1) (4 << 1)
9709#define HDCP_SHA1_TEXT_16(5 << 1) (5 << 1)
9710#define HDCP_SHA1_TEXT_8(6 << 1) (6 << 1)
9711#define HDCP_SHA1_TEXT_0(7 << 1) (7 << 1)
9712#define HDCP_SHA_V_PRIME_H0((const i915_reg_t){ .reg = (0x66d04) }) _MMIO(0x66d04)((const i915_reg_t){ .reg = (0x66d04) })
9713#define HDCP_SHA_V_PRIME_H1((const i915_reg_t){ .reg = (0x66d08) }) _MMIO(0x66d08)((const i915_reg_t){ .reg = (0x66d08) })
9714#define HDCP_SHA_V_PRIME_H2((const i915_reg_t){ .reg = (0x66d0C) }) _MMIO(0x66d0C)((const i915_reg_t){ .reg = (0x66d0C) })
9715#define HDCP_SHA_V_PRIME_H3((const i915_reg_t){ .reg = (0x66d10) }) _MMIO(0x66d10)((const i915_reg_t){ .reg = (0x66d10) })
9716#define HDCP_SHA_V_PRIME_H4((const i915_reg_t){ .reg = (0x66d14) }) _MMIO(0x66d14)((const i915_reg_t){ .reg = (0x66d14) })
9717#define HDCP_SHA_V_PRIME(h)((const i915_reg_t){ .reg = ((0x66d04 + (h) * 4)) }) _MMIO((0x66d04 + (h) * 4))((const i915_reg_t){ .reg = ((0x66d04 + (h) * 4)) })
9718#define HDCP_SHA_TEXT((const i915_reg_t){ .reg = (0x66d18) }) _MMIO(0x66d18)((const i915_reg_t){ .reg = (0x66d18) })
9719
9720/* HDCP Auth Registers */
9721#define _PORTA_HDCP_AUTHENC0x66800 0x66800
9722#define _PORTB_HDCP_AUTHENC0x66500 0x66500
9723#define _PORTC_HDCP_AUTHENC0x66600 0x66600
9724#define _PORTD_HDCP_AUTHENC0x66700 0x66700
9725#define _PORTE_HDCP_AUTHENC0x66A00 0x66A00
9726#define _PORTF_HDCP_AUTHENC0x66900 0x66900
9727#define _PORT_HDCP_AUTHENC(port, x)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) }) _MMIO(_PICK(port, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9728 _PORTA_HDCP_AUTHENC, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9729 _PORTB_HDCP_AUTHENC, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9730 _PORTC_HDCP_AUTHENC, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9731 _PORTD_HDCP_AUTHENC, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9732 _PORTE_HDCP_AUTHENC, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9733 _PORTF_HDCP_AUTHENC) + (x))((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (x)) })
9734#define PORT_HDCP_CONF(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x0)) }) _PORT_HDCP_AUTHENC(port, 0x0)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x0)) })
9735#define _TRANSA_HDCP_CONF0x66400 0x66400
9736#define _TRANSB_HDCP_CONF0x66500 0x66500
9737#define TRANS_HDCP_CONF(trans)((const i915_reg_t){ .reg = (((0x66400) + (trans) * ((0x66500
) - (0x66400)))) }) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \((const i915_reg_t){ .reg = (((0x66400) + (trans) * ((0x66500
) - (0x66400)))) })
9738 _TRANSB_HDCP_CONF)((const i915_reg_t){ .reg = (((0x66400) + (trans) * ((0x66500
) - (0x66400)))) })
9739#define HDCP_CONF(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66400) + (trans) * ((0x66500) - (0x66400)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x0)) })) \
9740 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9741 TRANS_HDCP_CONF(trans)((const i915_reg_t){ .reg = (((0x66400) + (trans) * ((0x66500
) - (0x66400)))) }) : \
9742 PORT_HDCP_CONF(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x0)) }))
9743
9744#define HDCP_CONF_CAPTURE_AN(1UL << (0)) BIT(0)(1UL << (0))
9745#define HDCP_CONF_AUTH_AND_ENC((1UL << (1)) | (1UL << (0))) (BIT(1)(1UL << (1)) | BIT(0)(1UL << (0)))
9746#define PORT_HDCP_ANINIT(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x4)) }) _PORT_HDCP_AUTHENC(port, 0x4)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x4)) })
9747#define _TRANSA_HDCP_ANINIT0x66404 0x66404
9748#define _TRANSB_HDCP_ANINIT0x66504 0x66504
9749#define TRANS_HDCP_ANINIT(trans)((const i915_reg_t){ .reg = (((0x66404) + (trans) * ((0x66504
) - (0x66404)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x66404) + (trans) * ((0x66504
) - (0x66404)))) })
9750 _TRANSA_HDCP_ANINIT, \((const i915_reg_t){ .reg = (((0x66404) + (trans) * ((0x66504
) - (0x66404)))) })
9751 _TRANSB_HDCP_ANINIT)((const i915_reg_t){ .reg = (((0x66404) + (trans) * ((0x66504
) - (0x66404)))) })
9752#define HDCP_ANINIT(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66404) + (trans) * ((0x66504) - (0x66404)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x4)) })) \
9753 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9754 TRANS_HDCP_ANINIT(trans)((const i915_reg_t){ .reg = (((0x66404) + (trans) * ((0x66504
) - (0x66404)))) }) : \
9755 PORT_HDCP_ANINIT(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x4)) }))
9756
9757#define PORT_HDCP_ANLO(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x8)) }) _PORT_HDCP_AUTHENC(port, 0x8)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x8)) })
9758#define _TRANSA_HDCP_ANLO0x66408 0x66408
9759#define _TRANSB_HDCP_ANLO0x66508 0x66508
9760#define TRANS_HDCP_ANLO(trans)((const i915_reg_t){ .reg = (((0x66408) + (trans) * ((0x66508
) - (0x66408)))) }) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \((const i915_reg_t){ .reg = (((0x66408) + (trans) * ((0x66508
) - (0x66408)))) })
9761 _TRANSB_HDCP_ANLO)((const i915_reg_t){ .reg = (((0x66408) + (trans) * ((0x66508
) - (0x66408)))) })
9762#define HDCP_ANLO(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66408) + (trans) * ((0x66508) - (0x66408)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x8)) })) \
9763 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9764 TRANS_HDCP_ANLO(trans)((const i915_reg_t){ .reg = (((0x66408) + (trans) * ((0x66508
) - (0x66408)))) }) : \
9765 PORT_HDCP_ANLO(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x8)) }))
9766
9767#define PORT_HDCP_ANHI(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0xC)) }) _PORT_HDCP_AUTHENC(port, 0xC)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0xC)) })
9768#define _TRANSA_HDCP_ANHI0x6640C 0x6640C
9769#define _TRANSB_HDCP_ANHI0x6650C 0x6650C
9770#define TRANS_HDCP_ANHI(trans)((const i915_reg_t){ .reg = (((0x6640C) + (trans) * ((0x6650C
) - (0x6640C)))) }) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \((const i915_reg_t){ .reg = (((0x6640C) + (trans) * ((0x6650C
) - (0x6640C)))) })
9771 _TRANSB_HDCP_ANHI)((const i915_reg_t){ .reg = (((0x6640C) + (trans) * ((0x6650C
) - (0x6640C)))) })
9772#define HDCP_ANHI(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x6640C) + (trans) * ((0x6650C) - (0x6640C)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0xC)) })) \
9773 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9774 TRANS_HDCP_ANHI(trans)((const i915_reg_t){ .reg = (((0x6640C) + (trans) * ((0x6650C
) - (0x6640C)))) }) : \
9775 PORT_HDCP_ANHI(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0xC)) }))
9776
9777#define PORT_HDCP_BKSVLO(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x10)) }) _PORT_HDCP_AUTHENC(port, 0x10)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x10)) })
9778#define _TRANSA_HDCP_BKSVLO0x66410 0x66410
9779#define _TRANSB_HDCP_BKSVLO0x66510 0x66510
9780#define TRANS_HDCP_BKSVLO(trans)((const i915_reg_t){ .reg = (((0x66410) + (trans) * ((0x66510
) - (0x66410)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x66410) + (trans) * ((0x66510
) - (0x66410)))) })
9781 _TRANSA_HDCP_BKSVLO, \((const i915_reg_t){ .reg = (((0x66410) + (trans) * ((0x66510
) - (0x66410)))) })
9782 _TRANSB_HDCP_BKSVLO)((const i915_reg_t){ .reg = (((0x66410) + (trans) * ((0x66510
) - (0x66410)))) })
9783#define HDCP_BKSVLO(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66410) + (trans) * ((0x66510) - (0x66410)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x10)) })) \
9784 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9785 TRANS_HDCP_BKSVLO(trans)((const i915_reg_t){ .reg = (((0x66410) + (trans) * ((0x66510
) - (0x66410)))) }) : \
9786 PORT_HDCP_BKSVLO(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x10)) }))
9787
9788#define PORT_HDCP_BKSVHI(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x14)) }) _PORT_HDCP_AUTHENC(port, 0x14)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x14)) })
9789#define _TRANSA_HDCP_BKSVHI0x66414 0x66414
9790#define _TRANSB_HDCP_BKSVHI0x66514 0x66514
9791#define TRANS_HDCP_BKSVHI(trans)((const i915_reg_t){ .reg = (((0x66414) + (trans) * ((0x66514
) - (0x66414)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x66414) + (trans) * ((0x66514
) - (0x66414)))) })
9792 _TRANSA_HDCP_BKSVHI, \((const i915_reg_t){ .reg = (((0x66414) + (trans) * ((0x66514
) - (0x66414)))) })
9793 _TRANSB_HDCP_BKSVHI)((const i915_reg_t){ .reg = (((0x66414) + (trans) * ((0x66514
) - (0x66414)))) })
9794#define HDCP_BKSVHI(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66414) + (trans) * ((0x66514) - (0x66414)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x14)) })) \
9795 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9796 TRANS_HDCP_BKSVHI(trans)((const i915_reg_t){ .reg = (((0x66414) + (trans) * ((0x66514
) - (0x66414)))) }) : \
9797 PORT_HDCP_BKSVHI(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x14)) }))
9798
9799#define PORT_HDCP_RPRIME(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x18)) }) _PORT_HDCP_AUTHENC(port, 0x18)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x18)) })
9800#define _TRANSA_HDCP_RPRIME0x66418 0x66418
9801#define _TRANSB_HDCP_RPRIME0x66518 0x66518
9802#define TRANS_HDCP_RPRIME(trans)((const i915_reg_t){ .reg = (((0x66418) + (trans) * ((0x66518
) - (0x66418)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x66418) + (trans) * ((0x66518
) - (0x66418)))) })
9803 _TRANSA_HDCP_RPRIME, \((const i915_reg_t){ .reg = (((0x66418) + (trans) * ((0x66518
) - (0x66418)))) })
9804 _TRANSB_HDCP_RPRIME)((const i915_reg_t){ .reg = (((0x66418) + (trans) * ((0x66518
) - (0x66418)))) })
9805#define HDCP_RPRIME(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66418) + (trans) * ((0x66518) - (0x66418)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x18)) })) \
9806 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9807 TRANS_HDCP_RPRIME(trans)((const i915_reg_t){ .reg = (((0x66418) + (trans) * ((0x66518
) - (0x66418)))) }) : \
9808 PORT_HDCP_RPRIME(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x18)) }))
9809
9810#define PORT_HDCP_STATUS(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x1C)) }) _PORT_HDCP_AUTHENC(port, 0x1C)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x1C)) })
9811#define _TRANSA_HDCP_STATUS0x6641C 0x6641C
9812#define _TRANSB_HDCP_STATUS0x6651C 0x6651C
9813#define TRANS_HDCP_STATUS(trans)((const i915_reg_t){ .reg = (((0x6641C) + (trans) * ((0x6651C
) - (0x6641C)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x6641C) + (trans) * ((0x6651C
) - (0x6641C)))) })
9814 _TRANSA_HDCP_STATUS, \((const i915_reg_t){ .reg = (((0x6641C) + (trans) * ((0x6651C
) - (0x6641C)))) })
9815 _TRANSB_HDCP_STATUS)((const i915_reg_t){ .reg = (((0x6641C) + (trans) * ((0x6651C
) - (0x6641C)))) })
9816#define HDCP_STATUS(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x6641C) + (trans) * ((0x6651C) - (0x6641C)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x1C)) })) \
9817 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9818 TRANS_HDCP_STATUS(trans)((const i915_reg_t){ .reg = (((0x6641C) + (trans) * ((0x6651C
) - (0x6641C)))) }) : \
9819 PORT_HDCP_STATUS(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[port]) + (0x1C)) }))
9820
9821#define HDCP_STATUS_STREAM_A_ENC(1UL << (31)) BIT(31)(1UL << (31))
9822#define HDCP_STATUS_STREAM_B_ENC(1UL << (30)) BIT(30)(1UL << (30))
9823#define HDCP_STATUS_STREAM_C_ENC(1UL << (29)) BIT(29)(1UL << (29))
9824#define HDCP_STATUS_STREAM_D_ENC(1UL << (28)) BIT(28)(1UL << (28))
9825#define HDCP_STATUS_AUTH(1UL << (21)) BIT(21)(1UL << (21))
9826#define HDCP_STATUS_ENC(1UL << (20)) BIT(20)(1UL << (20))
9827#define HDCP_STATUS_RI_MATCH(1UL << (19)) BIT(19)(1UL << (19))
9828#define HDCP_STATUS_R0_READY(1UL << (18)) BIT(18)(1UL << (18))
9829#define HDCP_STATUS_AN_READY(1UL << (17)) BIT(17)(1UL << (17))
9830#define HDCP_STATUS_CIPHER(1UL << (16)) BIT(16)(1UL << (16))
9831#define HDCP_STATUS_FRAME_CNT(x)(((x) >> 8) & 0xff) (((x) >> 8) & 0xff)
9832
9833/* HDCP2.2 Registers */
9834#define _PORTA_HDCP2_BASE0x66800 0x66800
9835#define _PORTB_HDCP2_BASE0x66500 0x66500
9836#define _PORTC_HDCP2_BASE0x66600 0x66600
9837#define _PORTD_HDCP2_BASE0x66700 0x66700
9838#define _PORTE_HDCP2_BASE0x66A00 0x66A00
9839#define _PORTF_HDCP2_BASE0x66900 0x66900
9840#define _PORT_HDCP2_BASE(port, x)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) }) _MMIO(_PICK((port), \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9841 _PORTA_HDCP2_BASE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9842 _PORTB_HDCP2_BASE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9843 _PORTC_HDCP2_BASE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9844 _PORTD_HDCP2_BASE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9845 _PORTE_HDCP2_BASE, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9846 _PORTF_HDCP2_BASE) + (x))((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (x)) })
9847#define PORT_HDCP2_AUTH(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0x98)) }) _PORT_HDCP2_BASE(port, 0x98)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0x98)) })
9848#define _TRANSA_HDCP2_AUTH0x66498 0x66498
9849#define _TRANSB_HDCP2_AUTH0x66598 0x66598
9850#define TRANS_HDCP2_AUTH(trans)((const i915_reg_t){ .reg = (((0x66498) + (trans) * ((0x66598
) - (0x66498)))) }) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \((const i915_reg_t){ .reg = (((0x66498) + (trans) * ((0x66598
) - (0x66498)))) })
9851 _TRANSB_HDCP2_AUTH)((const i915_reg_t){ .reg = (((0x66498) + (trans) * ((0x66598
) - (0x66498)))) })
9852#define AUTH_LINK_AUTHENTICATED(1UL << (31)) BIT(31)(1UL << (31))
9853#define AUTH_LINK_TYPE(1UL << (30)) BIT(30)(1UL << (30))
9854#define AUTH_FORCE_CLR_INPUTCTR(1UL << (19)) BIT(19)(1UL << (19))
9855#define AUTH_CLR_KEYS(1UL << (18)) BIT(18)(1UL << (18))
9856#define HDCP2_AUTH(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x66498) + (trans) * ((0x66598) - (0x66498)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0x98)) })
) \
9857 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9858 TRANS_HDCP2_AUTH(trans)((const i915_reg_t){ .reg = (((0x66498) + (trans) * ((0x66598
) - (0x66498)))) }) : \
9859 PORT_HDCP2_AUTH(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0x98)) }))
9860
9861#define PORT_HDCP2_CTL(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB0)) }) _PORT_HDCP2_BASE(port, 0xB0)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB0)) })
9862#define _TRANSA_HDCP2_CTL0x664B0 0x664B0
9863#define _TRANSB_HDCP2_CTL0x665B0 0x665B0
9864#define TRANS_HDCP2_CTL(trans)((const i915_reg_t){ .reg = (((0x664B0) + (trans) * ((0x665B0
) - (0x664B0)))) }) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \((const i915_reg_t){ .reg = (((0x664B0) + (trans) * ((0x665B0
) - (0x664B0)))) })
9865 _TRANSB_HDCP2_CTL)((const i915_reg_t){ .reg = (((0x664B0) + (trans) * ((0x665B0
) - (0x664B0)))) })
9866#define CTL_LINK_ENCRYPTION_REQ(1UL << (31)) BIT(31)(1UL << (31))
9867#define HDCP2_CTL(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x664B0) + (trans) * ((0x665B0) - (0x664B0)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB0)) })
) \
9868 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9869 TRANS_HDCP2_CTL(trans)((const i915_reg_t){ .reg = (((0x664B0) + (trans) * ((0x665B0
) - (0x664B0)))) }) : \
9870 PORT_HDCP2_CTL(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB0)) }))
9871
9872#define PORT_HDCP2_STATUS(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB4)) }) _PORT_HDCP2_BASE(port, 0xB4)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB4)) })
9873#define _TRANSA_HDCP2_STATUS0x664B4 0x664B4
9874#define _TRANSB_HDCP2_STATUS0x665B4 0x665B4
9875#define TRANS_HDCP2_STATUS(trans)((const i915_reg_t){ .reg = (((0x664B4) + (trans) * ((0x665B4
) - (0x664B4)))) }) _MMIO_TRANS(trans, \((const i915_reg_t){ .reg = (((0x664B4) + (trans) * ((0x665B4
) - (0x664B4)))) })
9876 _TRANSA_HDCP2_STATUS, \((const i915_reg_t){ .reg = (((0x664B4) + (trans) * ((0x665B4
) - (0x664B4)))) })
9877 _TRANSB_HDCP2_STATUS)((const i915_reg_t){ .reg = (((0x664B4) + (trans) * ((0x665B4
) - (0x664B4)))) })
9878#define LINK_TYPE_STATUS(1UL << (22)) BIT(22)(1UL << (22))
9879#define LINK_AUTH_STATUS(1UL << (21)) BIT(21)(1UL << (21))
9880#define LINK_ENCRYPTION_STATUS(1UL << (20)) BIT(20)(1UL << (20))
9881#define HDCP2_STATUS(dev_priv, trans, port)(((&(dev_priv)->__info)->gen) >= 12 ? ((const i915_reg_t
){ .reg = (((0x664B4) + (trans) * ((0x665B4) - (0x664B4)))) }
) : ((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB4)) })
) \
9882 (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? \
9883 TRANS_HDCP2_STATUS(trans)((const i915_reg_t){ .reg = (((0x664B4) + (trans) * ((0x665B4
) - (0x664B4)))) }) : \
9884 PORT_HDCP2_STATUS(port)((const i915_reg_t){ .reg = ((((const u32 []){ 0x66800, 0x66500
, 0x66600, 0x66700, 0x66A00, 0x66900 })[(port)]) + (0xB4)) }))
9885
9886/* Per-pipe DDI Function Control */
9887#define _TRANS_DDI_FUNC_CTL_A0x60400 0x60400
9888#define _TRANS_DDI_FUNC_CTL_B0x61400 0x61400
9889#define _TRANS_DDI_FUNC_CTL_C0x62400 0x62400
9890#define _TRANS_DDI_FUNC_CTL_D0x63400 0x63400
9891#define _TRANS_DDI_FUNC_CTL_EDP0x6F400 0x6F400
9892#define _TRANS_DDI_FUNC_CTL_DSI00x6b400 0x6b400
9893#define _TRANS_DDI_FUNC_CTL_DSI10x6bc00 0x6bc00
9894#define TRANS_DDI_FUNC_CTL(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60400) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60400) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
9895
9896#define TRANS_DDI_FUNC_ENABLE(1 << 31) (1 << 31)
9897/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9898#define TRANS_DDI_PORT_SHIFT28 28
9899#define TGL_TRANS_DDI_PORT_SHIFT27 27
9900#define TRANS_DDI_PORT_MASK(7 << 28) (7 << TRANS_DDI_PORT_SHIFT28)
9901#define TGL_TRANS_DDI_PORT_MASK(0xf << 27) (0xf << TGL_TRANS_DDI_PORT_SHIFT27)
9902#define TRANS_DDI_SELECT_PORT(x)((x) << 28) ((x) << TRANS_DDI_PORT_SHIFT28)
9903#define TGL_TRANS_DDI_SELECT_PORT(x)(((x) + 1) << 27) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT27)
9904#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)(((val) & (7 << 28)) >> 28) (((val) & TRANS_DDI_PORT_MASK(7 << 28)) >> TRANS_DDI_PORT_SHIFT28)
9905#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)((((val) & (0xf << 27)) >> 27) - 1) ((((val) & TGL_TRANS_DDI_PORT_MASK(0xf << 27)) >> TGL_TRANS_DDI_PORT_SHIFT27) - 1)
9906#define TRANS_DDI_MODE_SELECT_MASK(7 << 24) (7 << 24)
9907#define TRANS_DDI_MODE_SELECT_HDMI(0 << 24) (0 << 24)
9908#define TRANS_DDI_MODE_SELECT_DVI(1 << 24) (1 << 24)
9909#define TRANS_DDI_MODE_SELECT_DP_SST(2 << 24) (2 << 24)
9910#define TRANS_DDI_MODE_SELECT_DP_MST(3 << 24) (3 << 24)
9911#define TRANS_DDI_MODE_SELECT_FDI(4 << 24) (4 << 24)
9912#define TRANS_DDI_BPC_MASK(7 << 20) (7 << 20)
9913#define TRANS_DDI_BPC_8(0 << 20) (0 << 20)
9914#define TRANS_DDI_BPC_10(1 << 20) (1 << 20)
9915#define TRANS_DDI_BPC_6(2 << 20) (2 << 20)
9916#define TRANS_DDI_BPC_12(3 << 20) (3 << 20)
9917#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(18))) + 0)) REG_GENMASK(19, 18)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(18))) + 0)) /* bdw-cnl */
9918#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (19) - 1)) &
((~0UL) << (18))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(18))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (19
) - 1)) & ((~0UL) << (18))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (19) - 1)) &
((~0UL) << (18))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(18))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (19
) - 1)) & ((~0UL) << (18))) + 0)))) + 0 + 0 + 0 + 0
))
9919#define TRANS_DDI_PVSYNC(1 << 17) (1 << 17)
9920#define TRANS_DDI_PHSYNC(1 << 16) (1 << 16)
9921#define TRANS_DDI_PORT_SYNC_ENABLE((u32)((1UL << (15)) + 0)) REG_BIT(15)((u32)((1UL << (15)) + 0)) /* bdw-cnl */
9922#define TRANS_DDI_EDP_INPUT_MASK(7 << 12) (7 << 12)
9923#define TRANS_DDI_EDP_INPUT_A_ON(0 << 12) (0 << 12)
9924#define TRANS_DDI_EDP_INPUT_A_ONOFF(4 << 12) (4 << 12)
9925#define TRANS_DDI_EDP_INPUT_B_ONOFF(5 << 12) (5 << 12)
9926#define TRANS_DDI_EDP_INPUT_C_ONOFF(6 << 12) (6 << 12)
9927#define TRANS_DDI_EDP_INPUT_D_ONOFF(7 << 12) (7 << 12)
9928#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) <<
(10))) + 0)) REG_GENMASK(11, 10)((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) <<
(10))) + 0))
9929#define TRANS_DDI_MST_TRANSPORT_SELECT(trans)((u32)((((typeof(((u32)((((~0UL) >> (64 - (11) - 1)) &
((~0UL) << (10))) + 0))))(trans) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) <<
(10))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (11
) - 1)) & ((~0UL) << (10))) + 0)))) + 0 + 0 + 0 + 0
)) \
9930 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)((u32)((((typeof(((u32)((((~0UL) >> (64 - (11) - 1)) &
((~0UL) << (10))) + 0))))(trans) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) <<
(10))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (11
) - 1)) & ((~0UL) << (10))) + 0)))) + 0 + 0 + 0 + 0
))
9931#define TRANS_DDI_HDCP_SIGNALLING(1 << 9) (1 << 9)
9932#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC(1 << 8) (1 << 8)
9933#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE(1 << 7) (1 << 7)
9934#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ(1 << 6) (1 << 6)
9935#define TRANS_DDI_BFI_ENABLE(1 << 4) (1 << 4)
9936#define TRANS_DDI_HIGH_TMDS_CHAR_RATE(1 << 4) (1 << 4)
9937#define TRANS_DDI_HDMI_SCRAMBLING(1 << 0) (1 << 0)
9938#define TRANS_DDI_HDMI_SCRAMBLING_MASK((1 << 7) | (1 << 6) | (1 << 0)) (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE(1 << 7) \
9939 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ(1 << 6) \
9940 | TRANS_DDI_HDMI_SCRAMBLING(1 << 0))
9941
9942#define _TRANS_DDI_FUNC_CTL2_A0x60404 0x60404
9943#define _TRANS_DDI_FUNC_CTL2_B0x61404 0x61404
9944#define _TRANS_DDI_FUNC_CTL2_C0x62404 0x62404
9945#define _TRANS_DDI_FUNC_CTL2_EDP0x6f404 0x6f404
9946#define _TRANS_DDI_FUNC_CTL2_DSI00x6b404 0x6b404
9947#define _TRANS_DDI_FUNC_CTL2_DSI10x6bc04 0x6bc04
9948#define TRANS_DDI_FUNC_CTL2(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60404) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60404) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
9949#define PORT_SYNC_MODE_ENABLE((u32)((1UL << (4)) + 0)) REG_BIT(4)((u32)((1UL << (4)) + 0))
9950#define PORT_SYNC_MODE_MASTER_SELECT_MASK((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(2, 0)((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) <<
(0))) + 0))
9951#define PORT_SYNC_MODE_MASTER_SELECT(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (2) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (2)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (2) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (2)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
9952
9953/* DisplayPort Transport Control */
9954#define _DP_TP_CTL_A0x64040 0x64040
9955#define _DP_TP_CTL_B0x64140 0x64140
9956#define _TGL_DP_TP_CTL_A0x60540 0x60540
9957#define DP_TP_CTL(port)((const i915_reg_t){ .reg = (((0x64040) + (port) * ((0x64140)
- (0x64040)))) }) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)((const i915_reg_t){ .reg = (((0x64040) + (port) * ((0x64140)
- (0x64040)))) })
9958#define TGL_DP_TP_CTL(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[((tran))] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60540) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[((tran))] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60540) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
9959#define DP_TP_CTL_ENABLE(1 << 31) (1 << 31)
9960#define DP_TP_CTL_FEC_ENABLE(1 << 30) (1 << 30)
9961#define DP_TP_CTL_MODE_SST(0 << 27) (0 << 27)
9962#define DP_TP_CTL_MODE_MST(1 << 27) (1 << 27)
9963#define DP_TP_CTL_FORCE_ACT(1 << 25) (1 << 25)
9964#define DP_TP_CTL_ENHANCED_FRAME_ENABLE(1 << 18) (1 << 18)
9965#define DP_TP_CTL_FDI_AUTOTRAIN(1 << 15) (1 << 15)
9966#define DP_TP_CTL_LINK_TRAIN_MASK(7 << 8) (7 << 8)
9967#define DP_TP_CTL_LINK_TRAIN_PAT1(0 << 8) (0 << 8)
9968#define DP_TP_CTL_LINK_TRAIN_PAT2(1 << 8) (1 << 8)
9969#define DP_TP_CTL_LINK_TRAIN_PAT3(4 << 8) (4 << 8)
9970#define DP_TP_CTL_LINK_TRAIN_PAT4(5 << 8) (5 << 8)
9971#define DP_TP_CTL_LINK_TRAIN_IDLE(2 << 8) (2 << 8)
9972#define DP_TP_CTL_LINK_TRAIN_NORMAL(3 << 8) (3 << 8)
9973#define DP_TP_CTL_SCRAMBLE_DISABLE(1 << 7) (1 << 7)
9974
9975/* DisplayPort Transport Status */
9976#define _DP_TP_STATUS_A0x64044 0x64044
9977#define _DP_TP_STATUS_B0x64144 0x64144
9978#define _TGL_DP_TP_STATUS_A0x60544 0x60544
9979#define DP_TP_STATUS(port)((const i915_reg_t){ .reg = (((0x64044) + (port) * ((0x64144)
- (0x64044)))) }) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)((const i915_reg_t){ .reg = (((0x64044) + (port) * ((0x64144)
- (0x64044)))) })
9980#define TGL_DP_TP_STATUS(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[((tran))] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60544) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[((tran))] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60544) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
9981#define DP_TP_STATUS_FEC_ENABLE_LIVE(1 << 28) (1 << 28)
9982#define DP_TP_STATUS_IDLE_DONE(1 << 25) (1 << 25)
9983#define DP_TP_STATUS_ACT_SENT(1 << 24) (1 << 24)
9984#define DP_TP_STATUS_MODE_STATUS_MST(1 << 23) (1 << 23)
9985#define DP_TP_STATUS_AUTOTRAIN_DONE(1 << 12) (1 << 12)
9986#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2(3 << 8) (3 << 8)
9987#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1(3 << 4) (3 << 4)
9988#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0(3 << 0) (3 << 0)
9989
9990/* DDI Buffer Control */
9991#define _DDI_BUF_CTL_A0x64000 0x64000
9992#define _DDI_BUF_CTL_B0x64100 0x64100
9993#define DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100)
- (0x64000)))) }) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100)
- (0x64000)))) })
9994#define DDI_BUF_CTL_ENABLE(1 << 31) (1 << 31)
9995#define DDI_BUF_TRANS_SELECT(n)((n) << 24) ((n) << 24)
9996#define DDI_BUF_EMP_MASK(0xf << 24) (0xf << 24)
9997#define DDI_BUF_PORT_REVERSAL(1 << 16) (1 << 16)
9998#define DDI_BUF_IS_IDLE(1 << 7) (1 << 7)
9999#define DDI_A_4_LANES(1 << 4) (1 << 4)
10000#define DDI_PORT_WIDTH(width)(((width) - 1) << 1) (((width) - 1) << 1)
10001#define DDI_PORT_WIDTH_MASK(7 << 1) (7 << 1)
10002#define DDI_PORT_WIDTH_SHIFT1 1
10003#define DDI_INIT_DISPLAY_DETECTED(1 << 0) (1 << 0)
10004
10005/* DDI Buffer Translations */
10006#define _DDI_BUF_TRANS_A0x64E00 0x64E00
10007#define _DDI_BUF_TRANS_B0x64E60 0x64E60
10008#define DDI_BUF_TRANS_LO(port, i)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60)
- (0x64E00))) + (i) * 8) }) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60)
- (0x64E00))) + (i) * 8) })
10009#define DDI_BUF_BALANCE_LEG_ENABLE(1 << 31) (1 << 31)
10010#define DDI_BUF_TRANS_HI(port, i)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60)
- (0x64E00))) + (i) * 8 + 4) }) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60)
- (0x64E00))) + (i) * 8 + 4) })
10011
10012/* DDI DP Compliance Control */
10013#define _DDI_DP_COMP_CTL_A0x605F0 0x605F0
10014#define _DDI_DP_COMP_CTL_B0x615F0 0x615F0
10015#define DDI_DP_COMP_CTL(pipe)((const i915_reg_t){ .reg = (((0x605F0) + (pipe) * ((0x615F0)
- (0x605F0)))) }) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)((const i915_reg_t){ .reg = (((0x605F0) + (pipe) * ((0x615F0)
- (0x605F0)))) })
10016#define DDI_DP_COMP_CTL_ENABLE(1 << 31) (1 << 31)
10017#define DDI_DP_COMP_CTL_D10_2(0 << 28) (0 << 28)
10018#define DDI_DP_COMP_CTL_SCRAMBLED_0(1 << 28) (1 << 28)
10019#define DDI_DP_COMP_CTL_PRBS7(2 << 28) (2 << 28)
10020#define DDI_DP_COMP_CTL_CUSTOM80(3 << 28) (3 << 28)
10021#define DDI_DP_COMP_CTL_HBR2(4 << 28) (4 << 28)
10022#define DDI_DP_COMP_CTL_SCRAMBLED_1(5 << 28) (5 << 28)
10023#define DDI_DP_COMP_CTL_HBR2_RESET(0xFC << 0) (0xFC << 0)
10024
10025/* DDI DP Compliance Pattern */
10026#define _DDI_DP_COMP_PAT_A0x605F4 0x605F4
10027#define _DDI_DP_COMP_PAT_B0x615F4 0x615F4
10028#define DDI_DP_COMP_PAT(pipe, i)((const i915_reg_t){ .reg = (((0x605F4) + (pipe) * ((0x615F4)
- (0x605F4))) + (i) * 4) }) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x605F4) + (pipe) * ((0x615F4)
- (0x605F4))) + (i) * 4) })
10029
10030/* Sideband Interface (SBI) is programmed indirectly, via
10031 * SBI_ADDR, which contains the register offset; and SBI_DATA,
10032 * which contains the payload */
10033#define SBI_ADDR((const i915_reg_t){ .reg = (0xC6000) }) _MMIO(0xC6000)((const i915_reg_t){ .reg = (0xC6000) })
10034#define SBI_DATA((const i915_reg_t){ .reg = (0xC6004) }) _MMIO(0xC6004)((const i915_reg_t){ .reg = (0xC6004) })
10035#define SBI_CTL_STAT((const i915_reg_t){ .reg = (0xC6008) }) _MMIO(0xC6008)((const i915_reg_t){ .reg = (0xC6008) })
10036#define SBI_CTL_DEST_ICLK(0x0 << 16) (0x0 << 16)
10037#define SBI_CTL_DEST_MPHY(0x1 << 16) (0x1 << 16)
10038#define SBI_CTL_OP_IORD(0x2 << 8) (0x2 << 8)
10039#define SBI_CTL_OP_IOWR(0x3 << 8) (0x3 << 8)
10040#define SBI_CTL_OP_CRRD(0x6 << 8) (0x6 << 8)
10041#define SBI_CTL_OP_CRWR(0x7 << 8) (0x7 << 8)
10042#define SBI_RESPONSE_FAIL(0x1 << 1) (0x1 << 1)
10043#define SBI_RESPONSE_SUCCESS(0x0 << 1) (0x0 << 1)
10044#define SBI_BUSY(0x1 << 0) (0x1 << 0)
10045#define SBI_READY(0x0 << 0) (0x0 << 0)
10046
10047/* SBI offsets */
10048#define SBI_SSCDIVINTPHASE0x0200 0x0200
10049#define SBI_SSCDIVINTPHASE60x0600 0x0600
10050#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT1 1
10051#define SBI_SSCDIVINTPHASE_DIVSEL_MASK(0x7f << 1) (0x7f << 1)
10052#define SBI_SSCDIVINTPHASE_DIVSEL(x)((x) << 1) ((x) << 1)
10053#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT8 8
10054#define SBI_SSCDIVINTPHASE_INCVAL_MASK(0x7f << 8) (0x7f << 8)
10055#define SBI_SSCDIVINTPHASE_INCVAL(x)((x) << 8) ((x) << 8)
10056#define SBI_SSCDIVINTPHASE_DIR(x)((x) << 15) ((x) << 15)
10057#define SBI_SSCDIVINTPHASE_PROPAGATE(1 << 0) (1 << 0)
10058#define SBI_SSCDITHPHASE0x0204 0x0204
10059#define SBI_SSCCTL0x020c 0x020c
10060#define SBI_SSCCTL60x060C 0x060C
10061#define SBI_SSCCTL_PATHALT(1 << 3) (1 << 3)
10062#define SBI_SSCCTL_DISABLE(1 << 0) (1 << 0)
10063#define SBI_SSCAUXDIV60x0610 0x0610
10064#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT4 4
10065#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK(1 << 4) (1 << 4)
10066#define SBI_SSCAUXDIV_FINALDIV2SEL(x)((x) << 4) ((x) << 4)
10067#define SBI_DBUFF00x2a00 0x2a00
10068#define SBI_GEN00x1f00 0x1f00
10069#define SBI_GEN0_CFG_BUFFENABLE_DISABLE(1 << 0) (1 << 0)
10070
10071/* LPT PIXCLK_GATE */
10072#define PIXCLK_GATE((const i915_reg_t){ .reg = (0xC6020) }) _MMIO(0xC6020)((const i915_reg_t){ .reg = (0xC6020) })
10073#define PIXCLK_GATE_UNGATE(1 << 0) (1 << 0)
10074#define PIXCLK_GATE_GATE(0 << 0) (0 << 0)
10075
10076/* SPLL */
10077#define SPLL_CTL((const i915_reg_t){ .reg = (0x46020) }) _MMIO(0x46020)((const i915_reg_t){ .reg = (0x46020) })
10078#define SPLL_PLL_ENABLE(1 << 31) (1 << 31)
10079#define SPLL_REF_BCLK(0 << 28) (0 << 28)
10080#define SPLL_REF_MUXED_SSC(1 << 28) (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10081#define SPLL_REF_NON_SSC_HSW(2 << 28) (2 << 28)
10082#define SPLL_REF_PCH_SSC_BDW(2 << 28) (2 << 28)
10083#define SPLL_REF_LCPLL(3 << 28) (3 << 28)
10084#define SPLL_REF_MASK(3 << 28) (3 << 28)
10085#define SPLL_FREQ_810MHz(0 << 26) (0 << 26)
10086#define SPLL_FREQ_1350MHz(1 << 26) (1 << 26)
10087#define SPLL_FREQ_2700MHz(2 << 26) (2 << 26)
10088#define SPLL_FREQ_MASK(3 << 26) (3 << 26)
10089
10090/* WRPLL */
10091#define _WRPLL_CTL10x46040 0x46040
10092#define _WRPLL_CTL20x46060 0x46060
10093#define WRPLL_CTL(pll)((const i915_reg_t){ .reg = (((0x46040) + (pll) * ((0x46060) -
(0x46040)))) }) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)((const i915_reg_t){ .reg = (((0x46040) + (pll) * ((0x46060) -
(0x46040)))) })
10094#define WRPLL_PLL_ENABLE(1 << 31) (1 << 31)
10095#define WRPLL_REF_BCLK(0 << 28) (0 << 28)
10096#define WRPLL_REF_PCH_SSC(1 << 28) (1 << 28)
10097#define WRPLL_REF_MUXED_SSC_BDW(2 << 28) (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10098#define WRPLL_REF_SPECIAL_HSW(2 << 28) (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10099#define WRPLL_REF_LCPLL(3 << 28) (3 << 28)
10100#define WRPLL_REF_MASK(3 << 28) (3 << 28)
10101/* WRPLL divider programming */
10102#define WRPLL_DIVIDER_REFERENCE(x)((x) << 0) ((x) << 0)
10103#define WRPLL_DIVIDER_REF_MASK(0xff) (0xff)
10104#define WRPLL_DIVIDER_POST(x)((x) << 8) ((x) << 8)
10105#define WRPLL_DIVIDER_POST_MASK(0x3f << 8) (0x3f << 8)
10106#define WRPLL_DIVIDER_POST_SHIFT8 8
10107#define WRPLL_DIVIDER_FEEDBACK(x)((x) << 16) ((x) << 16)
10108#define WRPLL_DIVIDER_FB_SHIFT16 16
10109#define WRPLL_DIVIDER_FB_MASK(0xff << 16) (0xff << 16)
10110
10111/* Port clock selection */
10112#define _PORT_CLK_SEL_A0x46100 0x46100
10113#define _PORT_CLK_SEL_B0x46104 0x46104
10114#define PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104)
- (0x46100)))) }) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104)
- (0x46100)))) })
10115#define PORT_CLK_SEL_LCPLL_2700(0 << 29) (0 << 29)
10116#define PORT_CLK_SEL_LCPLL_1350(1 << 29) (1 << 29)
10117#define PORT_CLK_SEL_LCPLL_810(2 << 29) (2 << 29)
10118#define PORT_CLK_SEL_SPLL(3 << 29) (3 << 29)
10119#define PORT_CLK_SEL_WRPLL(pll)(((pll) + 4) << 29) (((pll) + 4) << 29)
10120#define PORT_CLK_SEL_WRPLL1(4 << 29) (4 << 29)
10121#define PORT_CLK_SEL_WRPLL2(5 << 29) (5 << 29)
10122#define PORT_CLK_SEL_NONE(7 << 29) (7 << 29)
10123#define PORT_CLK_SEL_MASK(7 << 29) (7 << 29)
10124
10125/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
10126#define DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104)
- (0x46100)))) }) PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104)
- (0x46100)))) })
10127#define DDI_CLK_SEL_NONE(0x0 << 28) (0x0 << 28)
10128#define DDI_CLK_SEL_MG(0x8 << 28) (0x8 << 28)
10129#define DDI_CLK_SEL_TBT_162(0xC << 28) (0xC << 28)
10130#define DDI_CLK_SEL_TBT_270(0xD << 28) (0xD << 28)
10131#define DDI_CLK_SEL_TBT_540(0xE << 28) (0xE << 28)
10132#define DDI_CLK_SEL_TBT_810(0xF << 28) (0xF << 28)
10133#define DDI_CLK_SEL_MASK(0xF << 28) (0xF << 28)
10134
10135/* Transcoder clock selection */
10136#define _TRANS_CLK_SEL_A0x46140 0x46140
10137#define _TRANS_CLK_SEL_B0x46144 0x46144
10138#define TRANS_CLK_SEL(tran)((const i915_reg_t){ .reg = (((0x46140) + (tran) * ((0x46144)
- (0x46140)))) }) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)((const i915_reg_t){ .reg = (((0x46140) + (tran) * ((0x46144)
- (0x46140)))) })
10139/* For each transcoder, we need to select the corresponding port clock */
10140#define TRANS_CLK_SEL_DISABLED(0x0 << 29) (0x0 << 29)
10141#define TRANS_CLK_SEL_PORT(x)(((x) + 1) << 29) (((x) + 1) << 29)
10142#define TGL_TRANS_CLK_SEL_DISABLED(0x0 << 28) (0x0 << 28)
10143#define TGL_TRANS_CLK_SEL_PORT(x)(((x) + 1) << 28) (((x) + 1) << 28)
10144
10145
10146#define CDCLK_FREQ((const i915_reg_t){ .reg = (0x46200) }) _MMIO(0x46200)((const i915_reg_t){ .reg = (0x46200) })
10147
10148#define _TRANSA_MSA_MISC0x60410 0x60410
10149#define _TRANSB_MSA_MISC0x61410 0x61410
10150#define _TRANSC_MSA_MISC0x62410 0x62410
10151#define _TRANS_EDP_MSA_MISC0x6f410 0x6f410
10152#define TRANS_MSA_MISC(tran)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60410) + ((&(dev_priv)->__info)->
display_mmio_offset))) }) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(tran)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60410) + ((&(dev_priv)->__info)->
display_mmio_offset))) })
10153/* See DP_MSA_MISC_* for the bit definitions */
10154
10155/* LCPLL Control */
10156#define LCPLL_CTL((const i915_reg_t){ .reg = (0x130040) }) _MMIO(0x130040)((const i915_reg_t){ .reg = (0x130040) })
10157#define LCPLL_PLL_DISABLE(1 << 31) (1 << 31)
10158#define LCPLL_PLL_LOCK(1 << 30) (1 << 30)
10159#define LCPLL_REF_NON_SSC(0 << 28) (0 << 28)
10160#define LCPLL_REF_BCLK(2 << 28) (2 << 28)
10161#define LCPLL_REF_PCH_SSC(3 << 28) (3 << 28)
10162#define LCPLL_REF_MASK(3 << 28) (3 << 28)
10163#define LCPLL_CLK_FREQ_MASK(3 << 26) (3 << 26)
10164#define LCPLL_CLK_FREQ_450(0 << 26) (0 << 26)
10165#define LCPLL_CLK_FREQ_54O_BDW(1 << 26) (1 << 26)
10166#define LCPLL_CLK_FREQ_337_5_BDW(2 << 26) (2 << 26)
10167#define LCPLL_CLK_FREQ_675_BDW(3 << 26) (3 << 26)
10168#define LCPLL_CD_CLOCK_DISABLE(1 << 25) (1 << 25)
10169#define LCPLL_ROOT_CD_CLOCK_DISABLE(1 << 24) (1 << 24)
10170#define LCPLL_CD2X_CLOCK_DISABLE(1 << 23) (1 << 23)
10171#define LCPLL_POWER_DOWN_ALLOW(1 << 22) (1 << 22)
10172#define LCPLL_CD_SOURCE_FCLK(1 << 21) (1 << 21)
10173#define LCPLL_CD_SOURCE_FCLK_DONE(1 << 19) (1 << 19)
10174
10175/*
10176 * SKL Clocks
10177 */
10178
10179/* CDCLK_CTL */
10180#define CDCLK_CTL((const i915_reg_t){ .reg = (0x46000) }) _MMIO(0x46000)((const i915_reg_t){ .reg = (0x46000) })
10181#define CDCLK_FREQ_SEL_MASK(3 << 26) (3 << 26)
10182#define CDCLK_FREQ_450_432(0 << 26) (0 << 26)
10183#define CDCLK_FREQ_540(1 << 26) (1 << 26)
10184#define CDCLK_FREQ_337_308(2 << 26) (2 << 26)
10185#define CDCLK_FREQ_675_617(3 << 26) (3 << 26)
10186#define BXT_CDCLK_CD2X_DIV_SEL_MASK(3 << 22) (3 << 22)
10187#define BXT_CDCLK_CD2X_DIV_SEL_1(0 << 22) (0 << 22)
10188#define BXT_CDCLK_CD2X_DIV_SEL_1_5(1 << 22) (1 << 22)
10189#define BXT_CDCLK_CD2X_DIV_SEL_2(2 << 22) (2 << 22)
10190#define BXT_CDCLK_CD2X_DIV_SEL_4(3 << 22) (3 << 22)
10191#define BXT_CDCLK_CD2X_PIPE(pipe)((pipe) << 20) ((pipe) << 20)
10192#define CDCLK_DIVMUX_CD_OVERRIDE(1 << 19) (1 << 19)
10193#define BXT_CDCLK_CD2X_PIPE_NONE((3) << 20) BXT_CDCLK_CD2X_PIPE(3)((3) << 20)
10194#define ICL_CDCLK_CD2X_PIPE(pipe)((((const u32 []){ 0, 2, 6 })[pipe]) << 19) (_PICK(pipe, 0, 2, 6)(((const u32 []){ 0, 2, 6 })[pipe]) << 19)
10195#define ICL_CDCLK_CD2X_PIPE_NONE(7 << 19) (7 << 19)
10196#define TGL_CDCLK_CD2X_PIPE(pipe)((pipe) << 20) BXT_CDCLK_CD2X_PIPE(pipe)((pipe) << 20)
10197#define TGL_CDCLK_CD2X_PIPE_NONE(7 << 19) ICL_CDCLK_CD2X_PIPE_NONE(7 << 19)
10198#define BXT_CDCLK_SSA_PRECHARGE_ENABLE(1 << 16) (1 << 16)
10199#define CDCLK_FREQ_DECIMAL_MASK(0x7ff) (0x7ff)
10200
10201/* LCPLL_CTL */
10202#define LCPLL1_CTL((const i915_reg_t){ .reg = (0x46010) }) _MMIO(0x46010)((const i915_reg_t){ .reg = (0x46010) })
10203#define LCPLL2_CTL((const i915_reg_t){ .reg = (0x46014) }) _MMIO(0x46014)((const i915_reg_t){ .reg = (0x46014) })
10204#define LCPLL_PLL_ENABLE(1 << 31) (1 << 31)
10205
10206/* DPLL control1 */
10207#define DPLL_CTRL1((const i915_reg_t){ .reg = (0x6C058) }) _MMIO(0x6C058)((const i915_reg_t){ .reg = (0x6C058) })
10208#define DPLL_CTRL1_HDMI_MODE(id)(1 << ((id) * 6 + 5)) (1 << ((id) * 6 + 5))
10209#define DPLL_CTRL1_SSC(id)(1 << ((id) * 6 + 4)) (1 << ((id) * 6 + 4))
10210#define DPLL_CTRL1_LINK_RATE_MASK(id)(7 << ((id) * 6 + 1)) (7 << ((id) * 6 + 1))
10211#define DPLL_CTRL1_LINK_RATE_SHIFT(id)((id) * 6 + 1) ((id) * 6 + 1)
10212#define DPLL_CTRL1_LINK_RATE(linkrate, id)((linkrate) << ((id) * 6 + 1)) ((linkrate) << ((id) * 6 + 1))
10213#define DPLL_CTRL1_OVERRIDE(id)(1 << ((id) * 6)) (1 << ((id) * 6))
10214#define DPLL_CTRL1_LINK_RATE_27000 0
10215#define DPLL_CTRL1_LINK_RATE_13501 1
10216#define DPLL_CTRL1_LINK_RATE_8102 2
10217#define DPLL_CTRL1_LINK_RATE_16203 3
10218#define DPLL_CTRL1_LINK_RATE_10804 4
10219#define DPLL_CTRL1_LINK_RATE_21605 5
10220
10221/* DPLL control2 */
10222#define DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) }) _MMIO(0x6C05C)((const i915_reg_t){ .reg = (0x6C05C) })
10223#define DPLL_CTRL2_DDI_CLK_OFF(port)(1 << ((port) + 15)) (1 << ((port) + 15))
10224#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port)(3 << ((port) * 3 + 1)) (3 << ((port) * 3 + 1))
10225#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)((port) * 3 + 1) ((port) * 3 + 1)
10226#define DPLL_CTRL2_DDI_CLK_SEL(clk, port)((clk) << ((port) * 3 + 1)) ((clk) << ((port) * 3 + 1))
10227#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port)(1 << ((port) * 3)) (1 << ((port) * 3))
10228
10229/* DPLL Status */
10230#define DPLL_STATUS((const i915_reg_t){ .reg = (0x6C060) }) _MMIO(0x6C060)((const i915_reg_t){ .reg = (0x6C060) })
10231#define DPLL_LOCK(id)(1 << ((id) * 8)) (1 << ((id) * 8))
10232
10233/* DPLL cfg */
10234#define _DPLL1_CFGCR10x6C040 0x6C040
10235#define _DPLL2_CFGCR10x6C048 0x6C048
10236#define _DPLL3_CFGCR10x6C050 0x6C050
10237#define DPLL_CFGCR1_FREQ_ENABLE(1 << 31) (1 << 31)
10238#define DPLL_CFGCR1_DCO_FRACTION_MASK(0x7fff << 9) (0x7fff << 9)
10239#define DPLL_CFGCR1_DCO_FRACTION(x)((x) << 9) ((x) << 9)
10240#define DPLL_CFGCR1_DCO_INTEGER_MASK(0x1ff) (0x1ff)
10241
10242#define _DPLL1_CFGCR20x6C044 0x6C044
10243#define _DPLL2_CFGCR20x6C04C 0x6C04C
10244#define _DPLL3_CFGCR20x6C054 0x6C054
10245#define DPLL_CFGCR2_QDIV_RATIO_MASK(0xff << 8) (0xff << 8)
10246#define DPLL_CFGCR2_QDIV_RATIO(x)((x) << 8) ((x) << 8)
10247#define DPLL_CFGCR2_QDIV_MODE(x)((x) << 7) ((x) << 7)
10248#define DPLL_CFGCR2_KDIV_MASK(3 << 5) (3 << 5)
10249#define DPLL_CFGCR2_KDIV(x)((x) << 5) ((x) << 5)
10250#define DPLL_CFGCR2_KDIV_5(0 << 5) (0 << 5)
10251#define DPLL_CFGCR2_KDIV_2(1 << 5) (1 << 5)
10252#define DPLL_CFGCR2_KDIV_3(2 << 5) (2 << 5)
10253#define DPLL_CFGCR2_KDIV_1(3 << 5) (3 << 5)
10254#define DPLL_CFGCR2_PDIV_MASK(7 << 2) (7 << 2)
10255#define DPLL_CFGCR2_PDIV(x)((x) << 2) ((x) << 2)
10256#define DPLL_CFGCR2_PDIV_1(0 << 2) (0 << 2)
10257#define DPLL_CFGCR2_PDIV_2(1 << 2) (1 << 2)
10258#define DPLL_CFGCR2_PDIV_3(2 << 2) (2 << 2)
10259#define DPLL_CFGCR2_PDIV_7(4 << 2) (4 << 2)
10260#define DPLL_CFGCR2_CENTRAL_FREQ_MASK(3) (3)
10261
10262#define DPLL_CFGCR1(id)((const i915_reg_t){ .reg = (((0x6C040) + ((id) - 1) * ((0x6C048
) - (0x6C040)))) }) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)((const i915_reg_t){ .reg = (((0x6C040) + ((id) - 1) * ((0x6C048
) - (0x6C040)))) })
10263#define DPLL_CFGCR2(id)((const i915_reg_t){ .reg = (((0x6C044) + ((id) - 1) * ((0x6C04C
) - (0x6C044)))) }) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)((const i915_reg_t){ .reg = (((0x6C044) + ((id) - 1) * ((0x6C04C
) - (0x6C044)))) })
10264
10265/*
10266 * CNL Clocks
10267 */
10268#define DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x6C200) }) _MMIO(0x6C200)((const i915_reg_t){ .reg = (0x6C200) })
10269#define DPCLKA_CFGCR0_DDI_CLK_OFF(port)(1 << ((port) == PORT_F ? 23 : (port) + 10)) (1 << ((port) == PORT_F ? 23 : \
10270 (port) + 10))
10271#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)((port) == PORT_F ? 21 : (port) * 2) ((port) == PORT_F ? 21 : \
10272 (port) * 2)
10273#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)(3 << ((port) == PORT_F ? 21 : (port) * 2)) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)((port) == PORT_F ? 21 : (port) * 2))
10274#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)((pll) << ((port) == PORT_F ? 21 : (port) * 2)) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)((port) == PORT_F ? 21 : (port) * 2))
10275
10276#define ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }) _MMIO(0x164280)((const i915_reg_t){ .reg = (0x164280) })
10277#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24 })[phy])) (1 << _PICK(phy, 10, 11, 24)(((const u32 []){ 10, 11, 24 })[phy]))
10278#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << ((phy) + 10)) + 0)) REG_BIT((phy) + 10)((u32)((1UL << ((phy) + 10)) + 0))
10279#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)(1 << ((tc_port) < PORT_TC4 ? (tc_port) + 12 : (tc_port
) - PORT_TC4 + 21)) (1 << ((tc_port) < PORT_TC4 ? \
10280 (tc_port) + 12 : \
10281 (tc_port) - PORT_TC4 + 21))
10282#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2) ((phy) * 2)
10283#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << ((phy) * 2)) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2))
10284#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)((pll) << ((phy) * 2)) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2))
10285#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((const u32 []){ 0, 2, 4, 27 })[phy]) _PICK(phy, 0, 2, 4, 27)(((const u32 []){ 0, 2, 4, 27 })[phy])
10286#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << (((const u32 []){ 0, 2, 4, 27 })[phy])) \
10287 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((const u32 []){ 0, 2, 4, 27 })[phy]))
10288#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)((pll) << (((const u32 []){ 0, 2, 4, 27 })[phy])) \
10289 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((const u32 []){ 0, 2, 4, 27 })[phy]))
10290
10291/* CNL PLL */
10292#define DPLL0_ENABLE0x46010 0x46010
10293#define DPLL1_ENABLE0x46014 0x46014
10294#define PLL_ENABLE(1 << 31) (1 << 31)
10295#define PLL_LOCK(1 << 30) (1 << 30)
10296#define PLL_POWER_ENABLE(1 << 27) (1 << 27)
10297#define PLL_POWER_STATE(1 << 26) (1 << 26)
10298#define CNL_DPLL_ENABLE(pll)((const i915_reg_t){ .reg = (((0x46010) + (pll) * ((0x46014) -
(0x46010)))) }) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)((const i915_reg_t){ .reg = (((0x46010) + (pll) * ((0x46014) -
(0x46010)))) })
10299
10300#define TBT_PLL_ENABLE((const i915_reg_t){ .reg = (0x46020) }) _MMIO(0x46020)((const i915_reg_t){ .reg = (0x46020) })
10301
10302#define _MG_PLL1_ENABLE0x46030 0x46030
10303#define _MG_PLL2_ENABLE0x46034 0x46034
10304#define _MG_PLL3_ENABLE0x46038 0x46038
10305#define _MG_PLL4_ENABLE0x4603C 0x4603C
10306/* Bits are the same as DPLL0_ENABLE */
10307#define MG_PLL_ENABLE(tc_port)((const i915_reg_t){ .reg = (((0x46030) + ((tc_port)) * ((0x46034
) - (0x46030)))) }) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \((const i915_reg_t){ .reg = (((0x46030) + ((tc_port)) * ((0x46034
) - (0x46030)))) })
10308 _MG_PLL2_ENABLE)((const i915_reg_t){ .reg = (((0x46030) + ((tc_port)) * ((0x46034
) - (0x46030)))) })
10309
10310#define _MG_REFCLKIN_CTL_PORT10x16892C 0x16892C
10311#define _MG_REFCLKIN_CTL_PORT20x16992C 0x16992C
10312#define _MG_REFCLKIN_CTL_PORT30x16A92C 0x16A92C
10313#define _MG_REFCLKIN_CTL_PORT40x16B92C 0x16B92C
10314#define MG_REFCLKIN_CTL_OD_2_MUX(x)((x) << 8) ((x) << 8)
10315#define MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8) (0x7 << 8)
10316#define MG_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) }) _MMIO_PORT((tc_port), \((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) })
10317 _MG_REFCLKIN_CTL_PORT1, \((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) })
10318 _MG_REFCLKIN_CTL_PORT2)((const i915_reg_t){ .reg = (((0x16892C) + ((tc_port)) * ((0x16992C
) - (0x16892C)))) })
10319
10320#define _MG_CLKTOP2_CORECLKCTL1_PORT10x1688D8 0x1688D8
10321#define _MG_CLKTOP2_CORECLKCTL1_PORT20x1698D8 0x1698D8
10322#define _MG_CLKTOP2_CORECLKCTL1_PORT30x16A8D8 0x16A8D8
10323#define _MG_CLKTOP2_CORECLKCTL1_PORT40x16B8D8 0x16B8D8
10324#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)((x) << 16) ((x) << 16)
10325#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK(0xff << 16) (0xff << 16)
10326#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)((x) << 8) ((x) << 8)
10327#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK(0xff << 8) (0xff << 8)
10328#define MG_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) }) _MMIO_PORT((tc_port), \((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) })
10329 _MG_CLKTOP2_CORECLKCTL1_PORT1, \((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) })
10330 _MG_CLKTOP2_CORECLKCTL1_PORT2)((const i915_reg_t){ .reg = (((0x1688D8) + ((tc_port)) * ((0x1698D8
) - (0x1688D8)))) })
10331
10332#define _MG_CLKTOP2_HSCLKCTL_PORT10x1688D4 0x1688D4
10333#define _MG_CLKTOP2_HSCLKCTL_PORT20x1698D4 0x1698D4
10334#define _MG_CLKTOP2_HSCLKCTL_PORT30x16A8D4 0x16A8D4
10335#define _MG_CLKTOP2_HSCLKCTL_PORT40x16B8D4 0x16B8D4
10336#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)((x) << 16) ((x) << 16)
10337#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK(0x1 << 16) (0x1 << 16)
10338#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)((x) << 14) ((x) << 14)
10339#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK(0x3 << 14) (0x3 << 14)
10340#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK(0x3 << 12) (0x3 << 12)
10341#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2(0 << 12) (0 << 12)
10342#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3(1 << 12) (1 << 12)
10343#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5(2 << 12) (2 << 12)
10344#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7(3 << 12) (3 << 12)
10345#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)((x) << 8) ((x) << 8)
10346#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT8 8
10347#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK(0xf << 8) (0xf << 8)
10348#define MG_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) }) _MMIO_PORT((tc_port), \((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) })
10349 _MG_CLKTOP2_HSCLKCTL_PORT1, \((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) })
10350 _MG_CLKTOP2_HSCLKCTL_PORT2)((const i915_reg_t){ .reg = (((0x1688D4) + ((tc_port)) * ((0x1698D4
) - (0x1688D4)))) })
10351
10352#define _MG_PLL_DIV0_PORT10x168A00 0x168A00
10353#define _MG_PLL_DIV0_PORT20x169A00 0x169A00
10354#define _MG_PLL_DIV0_PORT30x16AA00 0x16AA00
10355#define _MG_PLL_DIV0_PORT40x16BA00 0x16BA00
10356#define MG_PLL_DIV0_FRACNEN_H(1 << 30) (1 << 30)
10357#define MG_PLL_DIV0_FBDIV_FRAC_MASK(0x3fffff << 8) (0x3fffff << 8)
10358#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT8 8
10359#define MG_PLL_DIV0_FBDIV_FRAC(x)((x) << 8) ((x) << 8)
10360#define MG_PLL_DIV0_FBDIV_INT_MASK(0xff << 0) (0xff << 0)
10361#define MG_PLL_DIV0_FBDIV_INT(x)((x) << 0) ((x) << 0)
10362#define MG_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168A00) + ((tc_port)) * ((0x169A00
) - (0x168A00)))) }) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \((const i915_reg_t){ .reg = (((0x168A00) + ((tc_port)) * ((0x169A00
) - (0x168A00)))) })
10363 _MG_PLL_DIV0_PORT2)((const i915_reg_t){ .reg = (((0x168A00) + ((tc_port)) * ((0x169A00
) - (0x168A00)))) })
10364
10365#define _MG_PLL_DIV1_PORT10x168A04 0x168A04
10366#define _MG_PLL_DIV1_PORT20x169A04 0x169A04
10367#define _MG_PLL_DIV1_PORT30x16AA04 0x16AA04
10368#define _MG_PLL_DIV1_PORT40x16BA04 0x16BA04
10369#define MG_PLL_DIV1_IREF_NDIVRATIO(x)((x) << 16) ((x) << 16)
10370#define MG_PLL_DIV1_DITHER_DIV_1(0 << 12) (0 << 12)
10371#define MG_PLL_DIV1_DITHER_DIV_2(1 << 12) (1 << 12)
10372#define MG_PLL_DIV1_DITHER_DIV_4(2 << 12) (2 << 12)
10373#define MG_PLL_DIV1_DITHER_DIV_8(3 << 12) (3 << 12)
10374#define MG_PLL_DIV1_NDIVRATIO(x)((x) << 4) ((x) << 4)
10375#define MG_PLL_DIV1_FBPREDIV_MASK(0xf << 0) (0xf << 0)
10376#define MG_PLL_DIV1_FBPREDIV(x)((x) << 0) ((x) << 0)
10377#define MG_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168A04) + ((tc_port)) * ((0x169A04
) - (0x168A04)))) }) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \((const i915_reg_t){ .reg = (((0x168A04) + ((tc_port)) * ((0x169A04
) - (0x168A04)))) })
10378 _MG_PLL_DIV1_PORT2)((const i915_reg_t){ .reg = (((0x168A04) + ((tc_port)) * ((0x169A04
) - (0x168A04)))) })
10379
10380#define _MG_PLL_LF_PORT10x168A08 0x168A08
10381#define _MG_PLL_LF_PORT20x169A08 0x169A08
10382#define _MG_PLL_LF_PORT30x16AA08 0x16AA08
10383#define _MG_PLL_LF_PORT40x16BA08 0x16BA08
10384#define MG_PLL_LF_TDCTARGETCNT(x)((x) << 24) ((x) << 24)
10385#define MG_PLL_LF_AFCCNTSEL_256(0 << 20) (0 << 20)
10386#define MG_PLL_LF_AFCCNTSEL_512(1 << 20) (1 << 20)
10387#define MG_PLL_LF_GAINCTRL(x)((x) << 16) ((x) << 16)
10388#define MG_PLL_LF_INT_COEFF(x)((x) << 8) ((x) << 8)
10389#define MG_PLL_LF_PROP_COEFF(x)((x) << 0) ((x) << 0)
10390#define MG_PLL_LF(tc_port)((const i915_reg_t){ .reg = (((0x168A08) + ((tc_port)) * ((0x169A08
) - (0x168A08)))) }) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \((const i915_reg_t){ .reg = (((0x168A08) + ((tc_port)) * ((0x169A08
) - (0x168A08)))) })
10391 _MG_PLL_LF_PORT2)((const i915_reg_t){ .reg = (((0x168A08) + ((tc_port)) * ((0x169A08
) - (0x168A08)))) })
10392
10393#define _MG_PLL_FRAC_LOCK_PORT10x168A0C 0x168A0C
10394#define _MG_PLL_FRAC_LOCK_PORT20x169A0C 0x169A0C
10395#define _MG_PLL_FRAC_LOCK_PORT30x16AA0C 0x16AA0C
10396#define _MG_PLL_FRAC_LOCK_PORT40x16BA0C 0x16BA0C
10397#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32(1 << 18) (1 << 18)
10398#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32(1 << 16) (1 << 16)
10399#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x)((x) << 11) ((x) << 11)
10400#define MG_PLL_FRAC_LOCK_DCODITHEREN(1 << 10) (1 << 10)
10401#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN(1 << 8) (1 << 8)
10402#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)((x) << 0) ((x) << 0)
10403#define MG_PLL_FRAC_LOCK(tc_port)((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) }) _MMIO_PORT((tc_port), \((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) })
10404 _MG_PLL_FRAC_LOCK_PORT1, \((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) })
10405 _MG_PLL_FRAC_LOCK_PORT2)((const i915_reg_t){ .reg = (((0x168A0C) + ((tc_port)) * ((0x169A0C
) - (0x168A0C)))) })
10406
10407#define _MG_PLL_SSC_PORT10x168A10 0x168A10
10408#define _MG_PLL_SSC_PORT20x169A10 0x169A10
10409#define _MG_PLL_SSC_PORT30x16AA10 0x16AA10
10410#define _MG_PLL_SSC_PORT40x16BA10 0x16BA10
10411#define MG_PLL_SSC_EN(1 << 28) (1 << 28)
10412#define MG_PLL_SSC_TYPE(x)((x) << 26) ((x) << 26)
10413#define MG_PLL_SSC_STEPLENGTH(x)((x) << 16) ((x) << 16)
10414#define MG_PLL_SSC_STEPNUM(x)((x) << 10) ((x) << 10)
10415#define MG_PLL_SSC_FLLEN(1 << 9) (1 << 9)
10416#define MG_PLL_SSC_STEPSIZE(x)((x) << 0) ((x) << 0)
10417#define MG_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168A10) + ((tc_port)) * ((0x169A10
) - (0x168A10)))) }) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \((const i915_reg_t){ .reg = (((0x168A10) + ((tc_port)) * ((0x169A10
) - (0x168A10)))) })
10418 _MG_PLL_SSC_PORT2)((const i915_reg_t){ .reg = (((0x168A10) + ((tc_port)) * ((0x169A10
) - (0x168A10)))) })
10419
10420#define _MG_PLL_BIAS_PORT10x168A14 0x168A14
10421#define _MG_PLL_BIAS_PORT20x169A14 0x169A14
10422#define _MG_PLL_BIAS_PORT30x16AA14 0x16AA14
10423#define _MG_PLL_BIAS_PORT40x16BA14 0x16BA14
10424#define MG_PLL_BIAS_BIAS_GB_SEL(x)((x) << 30) ((x) << 30)
10425#define MG_PLL_BIAS_BIAS_GB_SEL_MASK(0x3 << 30) (0x3 << 30)
10426#define MG_PLL_BIAS_INIT_DCOAMP(x)((x) << 24) ((x) << 24)
10427#define MG_PLL_BIAS_INIT_DCOAMP_MASK(0x3f << 24) (0x3f << 24)
10428#define MG_PLL_BIAS_BIAS_BONUS(x)((x) << 16) ((x) << 16)
10429#define MG_PLL_BIAS_BIAS_BONUS_MASK(0xff << 16) (0xff << 16)
10430#define MG_PLL_BIAS_BIASCAL_EN(1 << 15) (1 << 15)
10431#define MG_PLL_BIAS_CTRIM(x)((x) << 8) ((x) << 8)
10432#define MG_PLL_BIAS_CTRIM_MASK(0x1f << 8) (0x1f << 8)
10433#define MG_PLL_BIAS_VREF_RDAC(x)((x) << 5) ((x) << 5)
10434#define MG_PLL_BIAS_VREF_RDAC_MASK(0x7 << 5) (0x7 << 5)
10435#define MG_PLL_BIAS_IREFTRIM(x)((x) << 0) ((x) << 0)
10436#define MG_PLL_BIAS_IREFTRIM_MASK(0x1f << 0) (0x1f << 0)
10437#define MG_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) }) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) })
10438 _MG_PLL_BIAS_PORT2)((const i915_reg_t){ .reg = (((0x168A14) + ((tc_port)) * ((0x169A14
) - (0x168A14)))) })
10439
10440#define _MG_PLL_TDC_COLDST_BIAS_PORT10x168A18 0x168A18
10441#define _MG_PLL_TDC_COLDST_BIAS_PORT20x169A18 0x169A18
10442#define _MG_PLL_TDC_COLDST_BIAS_PORT30x16AA18 0x16AA18
10443#define _MG_PLL_TDC_COLDST_BIAS_PORT40x16BA18 0x16BA18
10444#define MG_PLL_TDC_COLDST_IREFINT_EN(1 << 27) (1 << 27)
10445#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)((x) << 17) ((x) << 17)
10446#define MG_PLL_TDC_COLDST_COLDSTART(1 << 16) (1 << 16)
10447#define MG_PLL_TDC_TDCOVCCORR_EN(1 << 2) (1 << 2)
10448#define MG_PLL_TDC_TDCSEL(x)((x) << 0) ((x) << 0)
10449#define MG_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) }) _MMIO_PORT((tc_port), \((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) })
10450 _MG_PLL_TDC_COLDST_BIAS_PORT1, \((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) })
10451 _MG_PLL_TDC_COLDST_BIAS_PORT2)((const i915_reg_t){ .reg = (((0x168A18) + ((tc_port)) * ((0x169A18
) - (0x168A18)))) })
10452
10453#define _CNL_DPLL0_CFGCR00x6C000 0x6C000
10454#define _CNL_DPLL1_CFGCR00x6C080 0x6C080
10455#define DPLL_CFGCR0_HDMI_MODE(1 << 30) (1 << 30)
10456#define DPLL_CFGCR0_SSC_ENABLE(1 << 29) (1 << 29)
10457#define DPLL_CFGCR0_SSC_ENABLE_ICL(1 << 25) (1 << 25)
10458#define DPLL_CFGCR0_LINK_RATE_MASK(0xf << 25) (0xf << 25)
10459#define DPLL_CFGCR0_LINK_RATE_2700(0 << 25) (0 << 25)
10460#define DPLL_CFGCR0_LINK_RATE_1350(1 << 25) (1 << 25)
10461#define DPLL_CFGCR0_LINK_RATE_810(2 << 25) (2 << 25)
10462#define DPLL_CFGCR0_LINK_RATE_1620(3 << 25) (3 << 25)
10463#define DPLL_CFGCR0_LINK_RATE_1080(4 << 25) (4 << 25)
10464#define DPLL_CFGCR0_LINK_RATE_2160(5 << 25) (5 << 25)
10465#define DPLL_CFGCR0_LINK_RATE_3240(6 << 25) (6 << 25)
10466#define DPLL_CFGCR0_LINK_RATE_4050(7 << 25) (7 << 25)
10467#define DPLL_CFGCR0_DCO_FRACTION_MASK(0x7fff << 10) (0x7fff << 10)
10468#define DPLL_CFGCR0_DCO_FRACTION_SHIFT(10) (10)
10469#define DPLL_CFGCR0_DCO_FRACTION(x)((x) << 10) ((x) << 10)
10470#define DPLL_CFGCR0_DCO_INTEGER_MASK(0x3ff) (0x3ff)
10471#define CNL_DPLL_CFGCR0(pll)((const i915_reg_t){ .reg = (((0x6C000) + (pll) * ((0x6C080) -
(0x6C000)))) }) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)((const i915_reg_t){ .reg = (((0x6C000) + (pll) * ((0x6C080) -
(0x6C000)))) })
10472
10473#define _CNL_DPLL0_CFGCR10x6C004 0x6C004
10474#define _CNL_DPLL1_CFGCR10x6C084 0x6C084
10475#define DPLL_CFGCR1_QDIV_RATIO_MASK(0xff << 10) (0xff << 10)
10476#define DPLL_CFGCR1_QDIV_RATIO_SHIFT(10) (10)
10477#define DPLL_CFGCR1_QDIV_RATIO(x)((x) << 10) ((x) << 10)
10478#define DPLL_CFGCR1_QDIV_MODE_SHIFT(9) (9)
10479#define DPLL_CFGCR1_QDIV_MODE(x)((x) << 9) ((x) << 9)
10480#define DPLL_CFGCR1_KDIV_MASK(7 << 6) (7 << 6)
10481#define DPLL_CFGCR1_KDIV_SHIFT(6) (6)
10482#define DPLL_CFGCR1_KDIV(x)((x) << 6) ((x) << 6)
10483#define DPLL_CFGCR1_KDIV_1(1 << 6) (1 << 6)
10484#define DPLL_CFGCR1_KDIV_2(2 << 6) (2 << 6)
10485#define DPLL_CFGCR1_KDIV_3(4 << 6) (4 << 6)
10486#define DPLL_CFGCR1_PDIV_MASK(0xf << 2) (0xf << 2)
10487#define DPLL_CFGCR1_PDIV_SHIFT(2) (2)
10488#define DPLL_CFGCR1_PDIV(x)((x) << 2) ((x) << 2)
10489#define DPLL_CFGCR1_PDIV_2(1 << 2) (1 << 2)
10490#define DPLL_CFGCR1_PDIV_3(2 << 2) (2 << 2)
10491#define DPLL_CFGCR1_PDIV_5(4 << 2) (4 << 2)
10492#define DPLL_CFGCR1_PDIV_7(8 << 2) (8 << 2)
10493#define DPLL_CFGCR1_CENTRAL_FREQ(3 << 0) (3 << 0)
10494#define DPLL_CFGCR1_CENTRAL_FREQ_8400(3 << 0) (3 << 0)
10495#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL(0 << 0) (0 << 0)
10496#define CNL_DPLL_CFGCR1(pll)((const i915_reg_t){ .reg = (((0x6C004) + (pll) * ((0x6C084) -
(0x6C004)))) }) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)((const i915_reg_t){ .reg = (((0x6C004) + (pll) * ((0x6C084) -
(0x6C004)))) })
10497
10498#define _ICL_DPLL0_CFGCR00x164000 0x164000
10499#define _ICL_DPLL1_CFGCR00x164080 0x164080
10500#define ICL_DPLL_CFGCR0(pll)((const i915_reg_t){ .reg = (((0x164000) + (pll) * ((0x164080
) - (0x164000)))) }) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \((const i915_reg_t){ .reg = (((0x164000) + (pll) * ((0x164080
) - (0x164000)))) })
10501 _ICL_DPLL1_CFGCR0)((const i915_reg_t){ .reg = (((0x164000) + (pll) * ((0x164080
) - (0x164000)))) })
10502
10503#define _ICL_DPLL0_CFGCR10x164004 0x164004
10504#define _ICL_DPLL1_CFGCR10x164084 0x164084
10505#define ICL_DPLL_CFGCR1(pll)((const i915_reg_t){ .reg = (((0x164004) + (pll) * ((0x164084
) - (0x164004)))) }) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \((const i915_reg_t){ .reg = (((0x164004) + (pll) * ((0x164084
) - (0x164004)))) })
10506 _ICL_DPLL1_CFGCR1)((const i915_reg_t){ .reg = (((0x164004) + (pll) * ((0x164084
) - (0x164004)))) })
10507
10508#define _TGL_DPLL0_CFGCR00x164284 0x164284
10509#define _TGL_DPLL1_CFGCR00x16428C 0x16428C
10510#define _TGL_TBTPLL_CFGCR00x16429C 0x16429C
10511#define TGL_DPLL_CFGCR0(pll)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[pll])) }) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[pll])) })
10512 _TGL_DPLL1_CFGCR0, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[pll])) })
10513 _TGL_TBTPLL_CFGCR0)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164284, 0x16428C
, 0x16429C })[pll])) })
10514#define RKL_DPLL_CFGCR0(pll)((const i915_reg_t){ .reg = (((0x164284) + (pll) * ((0x16428C
) - (0x164284)))) }) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \((const i915_reg_t){ .reg = (((0x164284) + (pll) * ((0x16428C
) - (0x164284)))) })
10515 _TGL_DPLL1_CFGCR0)((const i915_reg_t){ .reg = (((0x164284) + (pll) * ((0x16428C
) - (0x164284)))) })
10516
10517#define _TGL_DPLL0_CFGCR10x164288 0x164288
10518#define _TGL_DPLL1_CFGCR10x164290 0x164290
10519#define _TGL_TBTPLL_CFGCR10x1642A0 0x1642A0
10520#define TGL_DPLL_CFGCR1(pll)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[pll])) }) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[pll])) })
10521 _TGL_DPLL1_CFGCR1, \((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[pll])) })
10522 _TGL_TBTPLL_CFGCR1)((const i915_reg_t){ .reg = ((((const u32 []){ 0x164288, 0x164290
, 0x1642A0 })[pll])) })
10523#define RKL_DPLL_CFGCR1(pll)((const i915_reg_t){ .reg = (((0x164288) + (pll) * ((0x164290
) - (0x164288)))) }) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \((const i915_reg_t){ .reg = (((0x164288) + (pll) * ((0x164290
) - (0x164288)))) })
10524 _TGL_DPLL1_CFGCR1)((const i915_reg_t){ .reg = (((0x164288) + (pll) * ((0x164290
) - (0x164288)))) })
10525
10526#define _DKL_PHY1_BASE0x168000 0x168000
10527#define _DKL_PHY2_BASE0x169000 0x169000
10528#define _DKL_PHY3_BASE0x16A000 0x16A000
10529#define _DKL_PHY4_BASE0x16B000 0x16B000
10530#define _DKL_PHY5_BASE0x16C000 0x16C000
10531#define _DKL_PHY6_BASE0x16D000 0x16D000
10532
10533/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
10534#define _DKL_PLL_DIV00x200 0x200
10535#define DKL_PLL_DIV0_INTEG_COEFF(x)((x) << 16) ((x) << 16)
10536#define DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16) (0x1F << 16)
10537#define DKL_PLL_DIV0_PROP_COEFF(x)((x) << 12) ((x) << 12)
10538#define DKL_PLL_DIV0_PROP_COEFF_MASK(0xF << 12) (0xF << 12)
10539#define DKL_PLL_DIV0_FBPREDIV_SHIFT(8) (8)
10540#define DKL_PLL_DIV0_FBPREDIV(x)((x) << (8)) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT(8))
10541#define DKL_PLL_DIV0_FBPREDIV_MASK(0xF << (8)) (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT(8))
10542#define DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0) ((x) << 0)
10543#define DKL_PLL_DIV0_FBDIV_INT_MASK(0xFF << 0) (0xFF << 0)
10544#define DKL_PLL_DIV0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) }) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) })
10545 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) })
10546 _DKL_PLL_DIV0)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x200) })
10547
10548#define _DKL_PLL_DIV10x204 0x204
10549#define DKL_PLL_DIV1_IREF_TRIM(x)((x) << 16) ((x) << 16)
10550#define DKL_PLL_DIV1_IREF_TRIM_MASK(0x1F << 16) (0x1F << 16)
10551#define DKL_PLL_DIV1_TDC_TARGET_CNT(x)((x) << 0) ((x) << 0)
10552#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK(0xFF << 0) (0xFF << 0)
10553#define DKL_PLL_DIV1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) }) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) })
10554 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) })
10555 _DKL_PLL_DIV1)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x204) })
10556
10557#define _DKL_PLL_SSC0x210 0x210
10558#define DKL_PLL_SSC_IREF_NDIV_RATIO(x)((x) << 29) ((x) << 29)
10559#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK(0x7 << 29) (0x7 << 29)
10560#define DKL_PLL_SSC_STEP_LEN(x)((x) << 16) ((x) << 16)
10561#define DKL_PLL_SSC_STEP_LEN_MASK(0xFF << 16) (0xFF << 16)
10562#define DKL_PLL_SSC_STEP_NUM(x)((x) << 11) ((x) << 11)
10563#define DKL_PLL_SSC_STEP_NUM_MASK(0x7 << 11) (0x7 << 11)
10564#define DKL_PLL_SSC_EN(1 << 9) (1 << 9)
10565#define DKL_PLL_SSC(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) }) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) })
10566 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) })
10567 _DKL_PLL_SSC)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x210) })
10568
10569#define _DKL_PLL_BIAS0x214 0x214
10570#define DKL_PLL_BIAS_FRAC_EN_H(1 << 30) (1 << 30)
10571#define DKL_PLL_BIAS_FBDIV_SHIFT(8) (8)
10572#define DKL_PLL_BIAS_FBDIV_FRAC(x)((x) << (8)) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT(8))
10573#define DKL_PLL_BIAS_FBDIV_FRAC_MASK(0x3FFFFF << (8)) (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT(8))
10574#define DKL_PLL_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) }) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) })
10575 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) })
10576 _DKL_PLL_BIAS)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x214) })
10577
10578#define _DKL_PLL_TDC_COLDST_BIAS0x218 0x218
10579#define DKL_PLL_TDC_SSC_STEP_SIZE(x)((x) << 8) ((x) << 8)
10580#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK(0xFF << 8) (0xFF << 8)
10581#define DKL_PLL_TDC_FEED_FWD_GAIN(x)((x) << 0) ((x) << 0)
10582#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK(0xFF << 0) (0xFF << 0)
10583#define DKL_PLL_TDC_COLDST_BIAS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) })
10584 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) })
10585 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) })
10586 _DKL_PLL_TDC_COLDST_BIAS)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x218) })
10587
10588#define _DKL_REFCLKIN_CTL0x12C 0x12C
10589/* Bits are the same as MG_REFCLKIN_CTL */
10590#define DKL_REFCLKIN_CTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) })
10591 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) })
10592 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) })
10593 _DKL_REFCLKIN_CTL)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x12C) })
10594
10595#define _DKL_CLKTOP2_HSCLKCTL0xD4 0xD4
10596/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
10597#define DKL_CLKTOP2_HSCLKCTL(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) })
10598 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) })
10599 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) })
10600 _DKL_CLKTOP2_HSCLKCTL)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD4) })
10601
10602#define _DKL_CLKTOP2_CORECLKCTL10xD8 0xD8
10603/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
10604#define DKL_CLKTOP2_CORECLKCTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) })
10605 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) })
10606 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) })
10607 _DKL_CLKTOP2_CORECLKCTL1)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD8) })
10608
10609#define _DKL_TX_DPCNTL00x2C0 0x2C0
10610#define DKL_TX_PRESHOOT_COEFF(x)((x) << 13) ((x) << 13)
10611#define DKL_TX_PRESHOOT_COEFF_MASK(0x1f << 13) (0x1f << 13)
10612#define DKL_TX_DE_EMPHASIS_COEFF(x)((x) << 8) ((x) << 8)
10613#define DKL_TX_DE_EMPAHSIS_COEFF_MASK(0x1f << 8) (0x1f << 8)
10614#define DKL_TX_VSWING_CONTROL(x)((x) << 0) ((x) << 0)
10615#define DKL_TX_VSWING_CONTROL_MASK(0x7 << 0) (0x7 << 0)
10616#define DKL_TX_DPCNTL0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C0) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C0) })
10617 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C0) })
10618 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C0) })
10619 _DKL_TX_DPCNTL0)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C0) })
10620
10621#define _DKL_TX_DPCNTL10x2C4 0x2C4
10622/* Bits are the same as DKL_TX_DPCNTRL0 */
10623#define DKL_TX_DPCNTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C4) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C4) })
10624 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C4) })
10625 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C4) })
10626 _DKL_TX_DPCNTL1)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C4) })
10627
10628#define _DKL_TX_DPCNTL20x2C8 0x2C8
10629#define DKL_TX_DP20BITMODE(1 << 2) (1 << 2)
10630#define DKL_TX_DPCNTL2(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C8) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C8) })
10631 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C8) })
10632 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C8) })
10633 _DKL_TX_DPCNTL2)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2C8) })
10634
10635#define _DKL_TX_FW_CALIB0x2F8 0x2F8
10636#define DKL_TX_CFG_DISABLE_WAIT_INIT(1 << 7) (1 << 7)
10637#define DKL_TX_FW_CALIB(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2F8) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2F8) })
10638 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2F8) })
10639 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2F8) })
10640 _DKL_TX_FW_CALIB)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x2F8) })
10641
10642#define _DKL_TX_PMD_LANE_SUS0xD00 0xD00
10643#define DKL_TX_PMD_LANE_SUS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD00) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD00) })
10644 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD00) })
10645 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD00) })
10646 _DKL_TX_PMD_LANE_SUS)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xD00) })
10647
10648#define _DKL_TX_DW170xDC4 0xDC4
10649#define DKL_TX_DW17(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC4) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC4) })
10650 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC4) })
10651 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC4) })
10652 _DKL_TX_DW17)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC4) })
10653
10654#define _DKL_TX_DW180xDC8 0xDC8
10655#define DKL_TX_DW18(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC8) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC8) })
10656 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC8) })
10657 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC8) })
10658 _DKL_TX_DW18)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xDC8) })
10659
10660#define _DKL_DP_MODE0xA0 0xA0
10661#define DKL_DP_MODE(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xA0) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xA0) })
10662 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xA0) })
10663 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xA0) })
10664 _DKL_DP_MODE)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0xA0) })
10665
10666#define _DKL_CMN_UC_DW270x36C 0x36C
10667#define DKL_CMN_UC_DW27_UC_HEALTH(0x1 << 15) (0x1 << 15)
10668#define DKL_CMN_UC_DW_27(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x36C) }) _MMIO(_PORT(tc_port, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x36C) })
10669 _DKL_PHY1_BASE, \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x36C) })
10670 _DKL_PHY2_BASE) + \((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x36C) })
10671 _DKL_CMN_UC_DW27)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000
) - (0x168000))) + 0x36C) })
10672
10673/*
10674 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
10675 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
10676 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
10677 * bits that point the 4KB window into the full PHY register space.
10678 */
10679#define _HIP_INDEX_REG00x1010A0 0x1010A0
10680#define _HIP_INDEX_REG10x1010A4 0x1010A4
10681#define HIP_INDEX_REG(tc_port)((const i915_reg_t){ .reg = ((tc_port) < 4 ? 0x1010A0 : 0x1010A4
) }) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \((const i915_reg_t){ .reg = ((tc_port) < 4 ? 0x1010A0 : 0x1010A4
) })
10682 : _HIP_INDEX_REG1)((const i915_reg_t){ .reg = ((tc_port) < 4 ? 0x1010A0 : 0x1010A4
) })
10683#define _HIP_INDEX_SHIFT(tc_port)(8 * ((tc_port) % 4)) (8 * ((tc_port) % 4))
10684#define HIP_INDEX_VAL(tc_port, val)((val) << (8 * ((tc_port) % 4))) ((val) << _HIP_INDEX_SHIFT(tc_port)(8 * ((tc_port) % 4)))
10685
10686/* BXT display engine PLL */
10687#define BXT_DE_PLL_CTL((const i915_reg_t){ .reg = (0x6d000) }) _MMIO(0x6d000)((const i915_reg_t){ .reg = (0x6d000) })
10688#define BXT_DE_PLL_RATIO(x)(x) (x) /* {60,65,100} * 19.2MHz */
10689#define BXT_DE_PLL_RATIO_MASK0xff 0xff
10690
10691#define BXT_DE_PLL_ENABLE((const i915_reg_t){ .reg = (0x46070) }) _MMIO(0x46070)((const i915_reg_t){ .reg = (0x46070) })
10692#define BXT_DE_PLL_PLL_ENABLE(1 << 31) (1 << 31)
10693#define BXT_DE_PLL_LOCK(1 << 30) (1 << 30)
10694#define CNL_CDCLK_PLL_RATIO(x)(x) (x)
10695#define CNL_CDCLK_PLL_RATIO_MASK0xff 0xff
10696
10697/* GEN9 DC */
10698#define DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }) _MMIO(0x45504)((const i915_reg_t){ .reg = (0x45504) })
10699#define DC_STATE_DISABLE0 0
10700#define DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0)) REG_BIT(30)((u32)((1UL << (30)) + 0))
10701#define DC_STATE_DC3CO_STATUS((u32)((1UL << (29)) + 0)) REG_BIT(29)((u32)((1UL << (29)) + 0))
10702#define DC_STATE_EN_UPTO_DC5(1 << 0) (1 << 0)
10703#define DC_STATE_EN_DC9(1 << 3) (1 << 3)
10704#define DC_STATE_EN_UPTO_DC6(2 << 0) (2 << 0)
10705#define DC_STATE_EN_UPTO_DC5_DC6_MASK0x3 0x3
10706
10707#define DC_STATE_DEBUG((const i915_reg_t){ .reg = (0x45520) }) _MMIO(0x45520)((const i915_reg_t){ .reg = (0x45520) })
10708#define DC_STATE_DEBUG_MASK_CORES(1 << 0) (1 << 0)
10709#define DC_STATE_DEBUG_MASK_MEMORY_UP(1 << 1) (1 << 1)
10710
10711#define BXT_P_CR_MC_BIOS_REQ_0_0_0((const i915_reg_t){ .reg = (0x140000 + 0x7114) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)((const i915_reg_t){ .reg = (0x140000 + 0x7114) })
10712#define BXT_REQ_DATA_MASK0x3F 0x3F
10713#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT12 12
10714#define BXT_DRAM_CHANNEL_ACTIVE_MASK(0xF << 12) (0xF << 12)
10715#define BXT_MEMORY_FREQ_MULTIPLIER_HZ133333333 133333333
10716
10717#define BXT_D_CR_DRP0_DUNIT80x1000 0x1000
10718#define BXT_D_CR_DRP0_DUNIT90x1200 0x1200
10719#define BXT_D_CR_DRP0_DUNIT_START8 8
10720#define BXT_D_CR_DRP0_DUNIT_END11 11
10721#define BXT_D_CR_DRP0_DUNIT(x)((const i915_reg_t){ .reg = (0x140000 + ((0x1000) + ((x) - 8)
* ((0x1200) - (0x1000)))) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + \((const i915_reg_t){ .reg = (0x140000 + ((0x1000) + ((x) - 8)
* ((0x1200) - (0x1000)))) })
10722 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\((const i915_reg_t){ .reg = (0x140000 + ((0x1000) + ((x) - 8)
* ((0x1200) - (0x1000)))) })
10723 BXT_D_CR_DRP0_DUNIT9))((const i915_reg_t){ .reg = (0x140000 + ((0x1000) + ((x) - 8)
* ((0x1200) - (0x1000)))) })
10724#define BXT_DRAM_RANK_MASK0x3 0x3
10725#define BXT_DRAM_RANK_SINGLE0x1 0x1
10726#define BXT_DRAM_RANK_DUAL0x3 0x3
10727#define BXT_DRAM_WIDTH_MASK(0x3 << 4) (0x3 << 4)
10728#define BXT_DRAM_WIDTH_SHIFT4 4
10729#define BXT_DRAM_WIDTH_X8(0x0 << 4) (0x0 << 4)
10730#define BXT_DRAM_WIDTH_X16(0x1 << 4) (0x1 << 4)
10731#define BXT_DRAM_WIDTH_X32(0x2 << 4) (0x2 << 4)
10732#define BXT_DRAM_WIDTH_X64(0x3 << 4) (0x3 << 4)
10733#define BXT_DRAM_SIZE_MASK(0x7 << 6) (0x7 << 6)
10734#define BXT_DRAM_SIZE_SHIFT6 6
10735#define BXT_DRAM_SIZE_4GBIT(0x0 << 6) (0x0 << 6)
10736#define BXT_DRAM_SIZE_6GBIT(0x1 << 6) (0x1 << 6)
10737#define BXT_DRAM_SIZE_8GBIT(0x2 << 6) (0x2 << 6)
10738#define BXT_DRAM_SIZE_12GBIT(0x3 << 6) (0x3 << 6)
10739#define BXT_DRAM_SIZE_16GBIT(0x4 << 6) (0x4 << 6)
10740#define BXT_DRAM_TYPE_MASK(0x7 << 22) (0x7 << 22)
10741#define BXT_DRAM_TYPE_SHIFT22 22
10742#define BXT_DRAM_TYPE_DDR3(0x0 << 22) (0x0 << 22)
10743#define BXT_DRAM_TYPE_LPDDR3(0x1 << 22) (0x1 << 22)
10744#define BXT_DRAM_TYPE_LPDDR4(0x2 << 22) (0x2 << 22)
10745#define BXT_DRAM_TYPE_DDR4(0x4 << 22) (0x4 << 22)
10746
10747#define SKL_MEMORY_FREQ_MULTIPLIER_HZ266666666 266666666
10748#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU((const i915_reg_t){ .reg = (0x140000 + 0x5E04) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)((const i915_reg_t){ .reg = (0x140000 + 0x5E04) })
10749#define SKL_REQ_DATA_MASK(0xF << 0) (0xF << 0)
10750
10751#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN((const i915_reg_t){ .reg = (0x140000 + 0x5000) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)((const i915_reg_t){ .reg = (0x140000 + 0x5000) })
10752#define SKL_DRAM_DDR_TYPE_MASK(0x3 << 0) (0x3 << 0)
10753#define SKL_DRAM_DDR_TYPE_DDR4(0 << 0) (0 << 0)
10754#define SKL_DRAM_DDR_TYPE_DDR3(1 << 0) (1 << 0)
10755#define SKL_DRAM_DDR_TYPE_LPDDR3(2 << 0) (2 << 0)
10756#define SKL_DRAM_DDR_TYPE_LPDDR4(3 << 0) (3 << 0)
10757
10758#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN((const i915_reg_t){ .reg = (0x140000 + 0x500C) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)((const i915_reg_t){ .reg = (0x140000 + 0x500C) })
10759#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN((const i915_reg_t){ .reg = (0x140000 + 0x5010) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)((const i915_reg_t){ .reg = (0x140000 + 0x5010) })
10760#define SKL_DRAM_S_SHIFT16 16
10761#define SKL_DRAM_SIZE_MASK0x3F 0x3F
10762#define SKL_DRAM_WIDTH_MASK(0x3 << 8) (0x3 << 8)
10763#define SKL_DRAM_WIDTH_SHIFT8 8
10764#define SKL_DRAM_WIDTH_X8(0x0 << 8) (0x0 << 8)
10765#define SKL_DRAM_WIDTH_X16(0x1 << 8) (0x1 << 8)
10766#define SKL_DRAM_WIDTH_X32(0x2 << 8) (0x2 << 8)
10767#define SKL_DRAM_RANK_MASK(0x1 << 10) (0x1 << 10)
10768#define SKL_DRAM_RANK_SHIFT10 10
10769#define SKL_DRAM_RANK_1(0x0 << 10) (0x0 << 10)
10770#define SKL_DRAM_RANK_2(0x1 << 10) (0x1 << 10)
10771#define SKL_DRAM_RANK_MASK(0x1 << 10) (0x1 << 10)
10772#define CNL_DRAM_SIZE_MASK0x7F 0x7F
10773#define CNL_DRAM_WIDTH_MASK(0x3 << 7) (0x3 << 7)
10774#define CNL_DRAM_WIDTH_SHIFT7 7
10775#define CNL_DRAM_WIDTH_X8(0x0 << 7) (0x0 << 7)
10776#define CNL_DRAM_WIDTH_X16(0x1 << 7) (0x1 << 7)
10777#define CNL_DRAM_WIDTH_X32(0x2 << 7) (0x2 << 7)
10778#define CNL_DRAM_RANK_MASK(0x3 << 9) (0x3 << 9)
10779#define CNL_DRAM_RANK_SHIFT9 9
10780#define CNL_DRAM_RANK_1(0x0 << 9) (0x0 << 9)
10781#define CNL_DRAM_RANK_2(0x1 << 9) (0x1 << 9)
10782#define CNL_DRAM_RANK_3(0x2 << 9) (0x2 << 9)
10783#define CNL_DRAM_RANK_4(0x3 << 9) (0x3 << 9)
10784
10785/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10786 * since on HSW we can't write to it using I915_WRITE. */
10787#define D_COMP_HSW((const i915_reg_t){ .reg = (0x140000 + 0x5F0C) }) _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)((const i915_reg_t){ .reg = (0x140000 + 0x5F0C) })
10788#define D_COMP_BDW((const i915_reg_t){ .reg = (0x138144) }) _MMIO(0x138144)((const i915_reg_t){ .reg = (0x138144) })
10789#define D_COMP_RCOMP_IN_PROGRESS(1 << 9) (1 << 9)
10790#define D_COMP_COMP_FORCE(1 << 8) (1 << 8)
10791#define D_COMP_COMP_DISABLE(1 << 0) (1 << 0)
10792
10793/* Pipe WM_LINETIME - watermark line time */
10794#define _WM_LINETIME_A0x45270 0x45270
10795#define _WM_LINETIME_B0x45274 0x45274
10796#define WM_LINETIME(pipe)((const i915_reg_t){ .reg = (((0x45270) + (pipe) * ((0x45274)
- (0x45270)))) }) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)((const i915_reg_t){ .reg = (((0x45270) + (pipe) * ((0x45274)
- (0x45270)))) })
10797#define HSW_LINETIME_MASK((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(8, 0)((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(0))) + 0))
10798#define HSW_LINETIME(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (8)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) &
((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) <<
(0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (8)
- 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))
10799#define HSW_IPS_LINETIME_MASK((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(24, 16)((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) <<
(16))) + 0))
10800#define HSW_IPS_LINETIME(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (24) - 1)) &
((~0UL) << (16))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (24
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
)) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))((u32)((((typeof(((u32)((((~0UL) >> (64 - (24) - 1)) &
((~0UL) << (16))) + 0))))((x)) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (24
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
10801
10802/* SFUSE_STRAP */
10803#define SFUSE_STRAP((const i915_reg_t){ .reg = (0xc2014) }) _MMIO(0xc2014)((const i915_reg_t){ .reg = (0xc2014) })
10804#define SFUSE_STRAP_FUSE_LOCK(1 << 13) (1 << 13)
10805#define SFUSE_STRAP_RAW_FREQUENCY(1 << 8) (1 << 8)
10806#define SFUSE_STRAP_DISPLAY_DISABLED(1 << 7) (1 << 7)
10807#define SFUSE_STRAP_CRT_DISABLED(1 << 6) (1 << 6)
10808#define SFUSE_STRAP_DDIF_DETECTED(1 << 3) (1 << 3)
10809#define SFUSE_STRAP_DDIB_DETECTED(1 << 2) (1 << 2)
10810#define SFUSE_STRAP_DDIC_DETECTED(1 << 1) (1 << 1)
10811#define SFUSE_STRAP_DDID_DETECTED(1 << 0) (1 << 0)
10812
10813#define WM_MISC((const i915_reg_t){ .reg = (0x45260) }) _MMIO(0x45260)((const i915_reg_t){ .reg = (0x45260) })
10814#define WM_MISC_DATA_PARTITION_5_6(1 << 0) (1 << 0)
10815
10816#define WM_DBG((const i915_reg_t){ .reg = (0x45280) }) _MMIO(0x45280)((const i915_reg_t){ .reg = (0x45280) })
10817#define WM_DBG_DISALLOW_MULTIPLE_LP(1 << 0) (1 << 0)
10818#define WM_DBG_DISALLOW_MAXFIFO(1 << 1) (1 << 1)
10819#define WM_DBG_DISALLOW_SPRITE(1 << 2) (1 << 2)
10820
10821/* pipe CSC */
10822#define _PIPE_A_CSC_COEFF_RY_GY0x49010 0x49010
10823#define _PIPE_A_CSC_COEFF_BY0x49014 0x49014
10824#define _PIPE_A_CSC_COEFF_RU_GU0x49018 0x49018
10825#define _PIPE_A_CSC_COEFF_BU0x4901c 0x4901c
10826#define _PIPE_A_CSC_COEFF_RV_GV0x49020 0x49020
10827#define _PIPE_A_CSC_COEFF_BV0x49024 0x49024
10828
10829#define _PIPE_A_CSC_MODE0x49028 0x49028
10830#define ICL_CSC_ENABLE(1 << 31) (1 << 31) /* icl+ */
10831#define ICL_OUTPUT_CSC_ENABLE(1 << 30) (1 << 30) /* icl+ */
10832#define CSC_BLACK_SCREEN_OFFSET(1 << 2) (1 << 2) /* ilk/snb */
10833#define CSC_POSITION_BEFORE_GAMMA(1 << 1) (1 << 1) /* pre-glk */
10834#define CSC_MODE_YUV_TO_RGB(1 << 0) (1 << 0) /* ilk/snb */
10835
10836#define _PIPE_A_CSC_PREOFF_HI0x49030 0x49030
10837#define _PIPE_A_CSC_PREOFF_ME0x49034 0x49034
10838#define _PIPE_A_CSC_PREOFF_LO0x49038 0x49038
10839#define _PIPE_A_CSC_POSTOFF_HI0x49040 0x49040
10840#define _PIPE_A_CSC_POSTOFF_ME0x49044 0x49044
10841#define _PIPE_A_CSC_POSTOFF_LO0x49048 0x49048
10842
10843#define _PIPE_B_CSC_COEFF_RY_GY0x49110 0x49110
10844#define _PIPE_B_CSC_COEFF_BY0x49114 0x49114
10845#define _PIPE_B_CSC_COEFF_RU_GU0x49118 0x49118
10846#define _PIPE_B_CSC_COEFF_BU0x4911c 0x4911c
10847#define _PIPE_B_CSC_COEFF_RV_GV0x49120 0x49120
10848#define _PIPE_B_CSC_COEFF_BV0x49124 0x49124
10849#define _PIPE_B_CSC_MODE0x49128 0x49128
10850#define _PIPE_B_CSC_PREOFF_HI0x49130 0x49130
10851#define _PIPE_B_CSC_PREOFF_ME0x49134 0x49134
10852#define _PIPE_B_CSC_PREOFF_LO0x49138 0x49138
10853#define _PIPE_B_CSC_POSTOFF_HI0x49140 0x49140
10854#define _PIPE_B_CSC_POSTOFF_ME0x49144 0x49144
10855#define _PIPE_B_CSC_POSTOFF_LO0x49148 0x49148
10856
10857#define PIPE_CSC_COEFF_RY_GY(pipe)((const i915_reg_t){ .reg = (((0x49010) + (pipe) * ((0x49110)
- (0x49010)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)((const i915_reg_t){ .reg = (((0x49010) + (pipe) * ((0x49110)
- (0x49010)))) })
10858#define PIPE_CSC_COEFF_BY(pipe)((const i915_reg_t){ .reg = (((0x49014) + (pipe) * ((0x49114)
- (0x49014)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)((const i915_reg_t){ .reg = (((0x49014) + (pipe) * ((0x49114)
- (0x49014)))) })
10859#define PIPE_CSC_COEFF_RU_GU(pipe)((const i915_reg_t){ .reg = (((0x49018) + (pipe) * ((0x49118)
- (0x49018)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)((const i915_reg_t){ .reg = (((0x49018) + (pipe) * ((0x49118)
- (0x49018)))) })
10860#define PIPE_CSC_COEFF_BU(pipe)((const i915_reg_t){ .reg = (((0x4901c) + (pipe) * ((0x4911c)
- (0x4901c)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)((const i915_reg_t){ .reg = (((0x4901c) + (pipe) * ((0x4911c)
- (0x4901c)))) })
10861#define PIPE_CSC_COEFF_RV_GV(pipe)((const i915_reg_t){ .reg = (((0x49020) + (pipe) * ((0x49120)
- (0x49020)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)((const i915_reg_t){ .reg = (((0x49020) + (pipe) * ((0x49120)
- (0x49020)))) })
10862#define PIPE_CSC_COEFF_BV(pipe)((const i915_reg_t){ .reg = (((0x49024) + (pipe) * ((0x49124)
- (0x49024)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)((const i915_reg_t){ .reg = (((0x49024) + (pipe) * ((0x49124)
- (0x49024)))) })
10863#define PIPE_CSC_MODE(pipe)((const i915_reg_t){ .reg = (((0x49028) + (pipe) * ((0x49128)
- (0x49028)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)((const i915_reg_t){ .reg = (((0x49028) + (pipe) * ((0x49128)
- (0x49028)))) })
10864#define PIPE_CSC_PREOFF_HI(pipe)((const i915_reg_t){ .reg = (((0x49030) + (pipe) * ((0x49130)
- (0x49030)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)((const i915_reg_t){ .reg = (((0x49030) + (pipe) * ((0x49130)
- (0x49030)))) })
10865#define PIPE_CSC_PREOFF_ME(pipe)((const i915_reg_t){ .reg = (((0x49034) + (pipe) * ((0x49134)
- (0x49034)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)((const i915_reg_t){ .reg = (((0x49034) + (pipe) * ((0x49134)
- (0x49034)))) })
10866#define PIPE_CSC_PREOFF_LO(pipe)((const i915_reg_t){ .reg = (((0x49038) + (pipe) * ((0x49138)
- (0x49038)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)((const i915_reg_t){ .reg = (((0x49038) + (pipe) * ((0x49138)
- (0x49038)))) })
10867#define PIPE_CSC_POSTOFF_HI(pipe)((const i915_reg_t){ .reg = (((0x49040) + (pipe) * ((0x49140)
- (0x49040)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)((const i915_reg_t){ .reg = (((0x49040) + (pipe) * ((0x49140)
- (0x49040)))) })
10868#define PIPE_CSC_POSTOFF_ME(pipe)((const i915_reg_t){ .reg = (((0x49044) + (pipe) * ((0x49144)
- (0x49044)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)((const i915_reg_t){ .reg = (((0x49044) + (pipe) * ((0x49144)
- (0x49044)))) })
10869#define PIPE_CSC_POSTOFF_LO(pipe)((const i915_reg_t){ .reg = (((0x49048) + (pipe) * ((0x49148)
- (0x49048)))) }) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)((const i915_reg_t){ .reg = (((0x49048) + (pipe) * ((0x49148)
- (0x49048)))) })
10870
10871/* Pipe Output CSC */
10872#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY0x49050 0x49050
10873#define _PIPE_A_OUTPUT_CSC_COEFF_BY0x49054 0x49054
10874#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU0x49058 0x49058
10875#define _PIPE_A_OUTPUT_CSC_COEFF_BU0x4905c 0x4905c
10876#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV0x49060 0x49060
10877#define _PIPE_A_OUTPUT_CSC_COEFF_BV0x49064 0x49064
10878#define _PIPE_A_OUTPUT_CSC_PREOFF_HI0x49068 0x49068
10879#define _PIPE_A_OUTPUT_CSC_PREOFF_ME0x4906c 0x4906c
10880#define _PIPE_A_OUTPUT_CSC_PREOFF_LO0x49070 0x49070
10881#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI0x49074 0x49074
10882#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME0x49078 0x49078
10883#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO0x4907c 0x4907c
10884
10885#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY0x49150 0x49150
10886#define _PIPE_B_OUTPUT_CSC_COEFF_BY0x49154 0x49154
10887#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU0x49158 0x49158
10888#define _PIPE_B_OUTPUT_CSC_COEFF_BU0x4915c 0x4915c
10889#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV0x49160 0x49160
10890#define _PIPE_B_OUTPUT_CSC_COEFF_BV0x49164 0x49164
10891#define _PIPE_B_OUTPUT_CSC_PREOFF_HI0x49168 0x49168
10892#define _PIPE_B_OUTPUT_CSC_PREOFF_ME0x4916c 0x4916c
10893#define _PIPE_B_OUTPUT_CSC_PREOFF_LO0x49170 0x49170
10894#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI0x49174 0x49174
10895#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME0x49178 0x49178
10896#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO0x4917c 0x4917c
10897
10898#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)((const i915_reg_t){ .reg = (((0x49050) + (pipe) * ((0x49150)
- (0x49050)))) }) _MMIO_PIPE(pipe,\((const i915_reg_t){ .reg = (((0x49050) + (pipe) * ((0x49150)
- (0x49050)))) })
10899 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\((const i915_reg_t){ .reg = (((0x49050) + (pipe) * ((0x49150)
- (0x49050)))) })
10900 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)((const i915_reg_t){ .reg = (((0x49050) + (pipe) * ((0x49150)
- (0x49050)))) })
10901#define PIPE_CSC_OUTPUT_COEFF_BY(pipe)((const i915_reg_t){ .reg = (((0x49054) + (pipe) * ((0x49154)
- (0x49054)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49054) + (pipe) * ((0x49154)
- (0x49054)))) })
10902 _PIPE_A_OUTPUT_CSC_COEFF_BY, \((const i915_reg_t){ .reg = (((0x49054) + (pipe) * ((0x49154)
- (0x49054)))) })
10903 _PIPE_B_OUTPUT_CSC_COEFF_BY)((const i915_reg_t){ .reg = (((0x49054) + (pipe) * ((0x49154)
- (0x49054)))) })
10904#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)((const i915_reg_t){ .reg = (((0x49058) + (pipe) * ((0x49158)
- (0x49058)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49058) + (pipe) * ((0x49158)
- (0x49058)))) })
10905 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \((const i915_reg_t){ .reg = (((0x49058) + (pipe) * ((0x49158)
- (0x49058)))) })
10906 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)((const i915_reg_t){ .reg = (((0x49058) + (pipe) * ((0x49158)
- (0x49058)))) })
10907#define PIPE_CSC_OUTPUT_COEFF_BU(pipe)((const i915_reg_t){ .reg = (((0x4905c) + (pipe) * ((0x4915c)
- (0x4905c)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x4905c) + (pipe) * ((0x4915c)
- (0x4905c)))) })
10908 _PIPE_A_OUTPUT_CSC_COEFF_BU, \((const i915_reg_t){ .reg = (((0x4905c) + (pipe) * ((0x4915c)
- (0x4905c)))) })
10909 _PIPE_B_OUTPUT_CSC_COEFF_BU)((const i915_reg_t){ .reg = (((0x4905c) + (pipe) * ((0x4915c)
- (0x4905c)))) })
10910#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)((const i915_reg_t){ .reg = (((0x49060) + (pipe) * ((0x49160)
- (0x49060)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49060) + (pipe) * ((0x49160)
- (0x49060)))) })
10911 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \((const i915_reg_t){ .reg = (((0x49060) + (pipe) * ((0x49160)
- (0x49060)))) })
10912 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)((const i915_reg_t){ .reg = (((0x49060) + (pipe) * ((0x49160)
- (0x49060)))) })
10913#define PIPE_CSC_OUTPUT_COEFF_BV(pipe)((const i915_reg_t){ .reg = (((0x49064) + (pipe) * ((0x49164)
- (0x49064)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49064) + (pipe) * ((0x49164)
- (0x49064)))) })
10914 _PIPE_A_OUTPUT_CSC_COEFF_BV, \((const i915_reg_t){ .reg = (((0x49064) + (pipe) * ((0x49164)
- (0x49064)))) })
10915 _PIPE_B_OUTPUT_CSC_COEFF_BV)((const i915_reg_t){ .reg = (((0x49064) + (pipe) * ((0x49164)
- (0x49064)))) })
10916#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)((const i915_reg_t){ .reg = (((0x49068) + (pipe) * ((0x49168)
- (0x49068)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49068) + (pipe) * ((0x49168)
- (0x49068)))) })
10917 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \((const i915_reg_t){ .reg = (((0x49068) + (pipe) * ((0x49168)
- (0x49068)))) })
10918 _PIPE_B_OUTPUT_CSC_PREOFF_HI)((const i915_reg_t){ .reg = (((0x49068) + (pipe) * ((0x49168)
- (0x49068)))) })
10919#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)((const i915_reg_t){ .reg = (((0x4906c) + (pipe) * ((0x4916c)
- (0x4906c)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x4906c) + (pipe) * ((0x4916c)
- (0x4906c)))) })
10920 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \((const i915_reg_t){ .reg = (((0x4906c) + (pipe) * ((0x4916c)
- (0x4906c)))) })
10921 _PIPE_B_OUTPUT_CSC_PREOFF_ME)((const i915_reg_t){ .reg = (((0x4906c) + (pipe) * ((0x4916c)
- (0x4906c)))) })
10922#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)((const i915_reg_t){ .reg = (((0x49070) + (pipe) * ((0x49170)
- (0x49070)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49070) + (pipe) * ((0x49170)
- (0x49070)))) })
10923 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \((const i915_reg_t){ .reg = (((0x49070) + (pipe) * ((0x49170)
- (0x49070)))) })
10924 _PIPE_B_OUTPUT_CSC_PREOFF_LO)((const i915_reg_t){ .reg = (((0x49070) + (pipe) * ((0x49170)
- (0x49070)))) })
10925#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)((const i915_reg_t){ .reg = (((0x49074) + (pipe) * ((0x49174)
- (0x49074)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49074) + (pipe) * ((0x49174)
- (0x49074)))) })
10926 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \((const i915_reg_t){ .reg = (((0x49074) + (pipe) * ((0x49174)
- (0x49074)))) })
10927 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)((const i915_reg_t){ .reg = (((0x49074) + (pipe) * ((0x49174)
- (0x49074)))) })
10928#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)((const i915_reg_t){ .reg = (((0x49078) + (pipe) * ((0x49178)
- (0x49078)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x49078) + (pipe) * ((0x49178)
- (0x49078)))) })
10929 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \((const i915_reg_t){ .reg = (((0x49078) + (pipe) * ((0x49178)
- (0x49078)))) })
10930 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)((const i915_reg_t){ .reg = (((0x49078) + (pipe) * ((0x49178)
- (0x49078)))) })
10931#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)((const i915_reg_t){ .reg = (((0x4907c) + (pipe) * ((0x4917c)
- (0x4907c)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x4907c) + (pipe) * ((0x4917c)
- (0x4907c)))) })
10932 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \((const i915_reg_t){ .reg = (((0x4907c) + (pipe) * ((0x4917c)
- (0x4907c)))) })
10933 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)((const i915_reg_t){ .reg = (((0x4907c) + (pipe) * ((0x4917c)
- (0x4907c)))) })
10934
10935/* pipe degamma/gamma LUTs on IVB+ */
10936#define _PAL_PREC_INDEX_A0x4A400 0x4A400
10937#define _PAL_PREC_INDEX_B0x4AC00 0x4AC00
10938#define _PAL_PREC_INDEX_C0x4B400 0x4B400
10939#define PAL_PREC_10_12_BIT(0 << 31) (0 << 31)
10940#define PAL_PREC_SPLIT_MODE(1 << 31) (1 << 31)
10941#define PAL_PREC_AUTO_INCREMENT(1 << 15) (1 << 15)
10942#define PAL_PREC_INDEX_VALUE_MASK(0x3ff << 0) (0x3ff << 0)
10943#define PAL_PREC_INDEX_VALUE(x)((x) << 0) ((x) << 0)
10944#define _PAL_PREC_DATA_A0x4A404 0x4A404
10945#define _PAL_PREC_DATA_B0x4AC04 0x4AC04
10946#define _PAL_PREC_DATA_C0x4B404 0x4B404
10947#define _PAL_PREC_GC_MAX_A0x4A410 0x4A410
10948#define _PAL_PREC_GC_MAX_B0x4AC10 0x4AC10
10949#define _PAL_PREC_GC_MAX_C0x4B410 0x4B410
10950#define PREC_PAL_DATA_RED_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0)) REG_GENMASK(29, 20)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0))
10951#define PREC_PAL_DATA_GREEN_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0)) REG_GENMASK(19, 10)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0))
10952#define PREC_PAL_DATA_BLUE_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(9, 0)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0))
10953#define _PAL_PREC_EXT_GC_MAX_A0x4A420 0x4A420
10954#define _PAL_PREC_EXT_GC_MAX_B0x4AC20 0x4AC20
10955#define _PAL_PREC_EXT_GC_MAX_C0x4B420 0x4B420
10956#define _PAL_PREC_EXT2_GC_MAX_A0x4A430 0x4A430
10957#define _PAL_PREC_EXT2_GC_MAX_B0x4AC30 0x4AC30
10958#define _PAL_PREC_EXT2_GC_MAX_C0x4B430 0x4B430
10959
10960#define PREC_PAL_INDEX(pipe)((const i915_reg_t){ .reg = (((0x4A400) + (pipe) * ((0x4AC00)
- (0x4A400)))) }) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)((const i915_reg_t){ .reg = (((0x4A400) + (pipe) * ((0x4AC00)
- (0x4A400)))) })
10961#define PREC_PAL_DATA(pipe)((const i915_reg_t){ .reg = (((0x4A404) + (pipe) * ((0x4AC04)
- (0x4A404)))) }) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)((const i915_reg_t){ .reg = (((0x4A404) + (pipe) * ((0x4AC04)
- (0x4A404)))) })
10962#define PREC_PAL_GC_MAX(pipe, i)((const i915_reg_t){ .reg = (((0x4A410) + (pipe) * ((0x4AC10)
- (0x4A410))) + (i) * 4) }) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x4A410) + (pipe) * ((0x4AC10)
- (0x4A410))) + (i) * 4) })
10963#define PREC_PAL_EXT_GC_MAX(pipe, i)((const i915_reg_t){ .reg = (((0x4A420) + (pipe) * ((0x4AC20)
- (0x4A420))) + (i) * 4) }) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x4A420) + (pipe) * ((0x4AC20)
- (0x4A420))) + (i) * 4) })
10964#define PREC_PAL_EXT2_GC_MAX(pipe, i)((const i915_reg_t){ .reg = (((0x4A430) + (pipe) * ((0x4AC30)
- (0x4A430))) + (i) * 4) }) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)((const i915_reg_t){ .reg = (((0x4A430) + (pipe) * ((0x4AC30)
- (0x4A430))) + (i) * 4) })
10965
10966#define _PRE_CSC_GAMC_INDEX_A0x4A484 0x4A484
10967#define _PRE_CSC_GAMC_INDEX_B0x4AC84 0x4AC84
10968#define _PRE_CSC_GAMC_INDEX_C0x4B484 0x4B484
10969#define PRE_CSC_GAMC_AUTO_INCREMENT(1 << 10) (1 << 10)
10970#define _PRE_CSC_GAMC_DATA_A0x4A488 0x4A488
10971#define _PRE_CSC_GAMC_DATA_B0x4AC88 0x4AC88
10972#define _PRE_CSC_GAMC_DATA_C0x4B488 0x4B488
10973
10974#define PRE_CSC_GAMC_INDEX(pipe)((const i915_reg_t){ .reg = (((0x4A484) + (pipe) * ((0x4AC84)
- (0x4A484)))) }) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)((const i915_reg_t){ .reg = (((0x4A484) + (pipe) * ((0x4AC84)
- (0x4A484)))) })
10975#define PRE_CSC_GAMC_DATA(pipe)((const i915_reg_t){ .reg = (((0x4A488) + (pipe) * ((0x4AC88)
- (0x4A488)))) }) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)((const i915_reg_t){ .reg = (((0x4A488) + (pipe) * ((0x4AC88)
- (0x4A488)))) })
10976
10977/* ICL Multi segmented gamma */
10978#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408 0x4A408
10979#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08 0x4AC08
10980#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT((u32)((1UL << (15)) + 0)) REG_BIT(15)((u32)((1UL << (15)) + 0))
10981#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(4, 0)((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) <<
(0))) + 0))
10982
10983#define _PAL_PREC_MULTI_SEG_DATA_A0x4A40C 0x4A40C
10984#define _PAL_PREC_MULTI_SEG_DATA_B0x4AC0C 0x4AC0C
10985#define PAL_PREC_MULTI_SEG_RED_LDW_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(24))) + 0)) REG_GENMASK(29, 24)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(24))) + 0))
10986#define PAL_PREC_MULTI_SEG_RED_UDW_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0)) REG_GENMASK(29, 20)((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) <<
(20))) + 0))
10987#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(14))) + 0)) REG_GENMASK(19, 14)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(14))) + 0))
10988#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0)) REG_GENMASK(19, 10)((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) <<
(10))) + 0))
10989#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(4))) + 0)) REG_GENMASK(9, 4)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(4))) + 0))
10990#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(9, 0)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0))
10991
10992#define PREC_PAL_MULTI_SEG_INDEX(pipe)((const i915_reg_t){ .reg = (((0x4A408) + (pipe) * ((0x4AC08)
- (0x4A408)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x4A408) + (pipe) * ((0x4AC08)
- (0x4A408)))) })
10993 _PAL_PREC_MULTI_SEG_INDEX_A, \((const i915_reg_t){ .reg = (((0x4A408) + (pipe) * ((0x4AC08)
- (0x4A408)))) })
10994 _PAL_PREC_MULTI_SEG_INDEX_B)((const i915_reg_t){ .reg = (((0x4A408) + (pipe) * ((0x4AC08)
- (0x4A408)))) })
10995#define PREC_PAL_MULTI_SEG_DATA(pipe)((const i915_reg_t){ .reg = (((0x4A40C) + (pipe) * ((0x4AC0C)
- (0x4A40C)))) }) _MMIO_PIPE(pipe, \((const i915_reg_t){ .reg = (((0x4A40C) + (pipe) * ((0x4AC0C)
- (0x4A40C)))) })
10996 _PAL_PREC_MULTI_SEG_DATA_A, \((const i915_reg_t){ .reg = (((0x4A40C) + (pipe) * ((0x4AC0C)
- (0x4A40C)))) })
10997 _PAL_PREC_MULTI_SEG_DATA_B)((const i915_reg_t){ .reg = (((0x4A40C) + (pipe) * ((0x4AC0C)
- (0x4A40C)))) })
10998
10999/* pipe CSC & degamma/gamma LUTs on CHV */
11000#define _CGM_PIPE_A_CSC_COEFF01(0x180000 + 0x67900) (VLV_DISPLAY_BASE0x180000 + 0x67900)
11001#define _CGM_PIPE_A_CSC_COEFF23(0x180000 + 0x67904) (VLV_DISPLAY_BASE0x180000 + 0x67904)
11002#define _CGM_PIPE_A_CSC_COEFF45(0x180000 + 0x67908) (VLV_DISPLAY_BASE0x180000 + 0x67908)
11003#define _CGM_PIPE_A_CSC_COEFF67(0x180000 + 0x6790C) (VLV_DISPLAY_BASE0x180000 + 0x6790C)
11004#define _CGM_PIPE_A_CSC_COEFF8(0x180000 + 0x67910) (VLV_DISPLAY_BASE0x180000 + 0x67910)
11005#define _CGM_PIPE_A_DEGAMMA(0x180000 + 0x66000) (VLV_DISPLAY_BASE0x180000 + 0x66000)
11006#define _CGM_PIPE_A_GAMMA(0x180000 + 0x67000) (VLV_DISPLAY_BASE0x180000 + 0x67000)
11007#define _CGM_PIPE_A_MODE(0x180000 + 0x67A00) (VLV_DISPLAY_BASE0x180000 + 0x67A00)
11008#define CGM_PIPE_MODE_GAMMA(1 << 2) (1 << 2)
11009#define CGM_PIPE_MODE_CSC(1 << 1) (1 << 1)
11010#define CGM_PIPE_MODE_DEGAMMA(1 << 0) (1 << 0)
11011#define CGM_PIPE_GAMMA_RED_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(9, 0)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0))
11012#define CGM_PIPE_GAMMA_GREEN_MASK((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) <<
(16))) + 0)) REG_GENMASK(25, 16)((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) <<
(16))) + 0))
11013#define CGM_PIPE_GAMMA_BLUE_MASK((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0)) REG_GENMASK(9, 0)((u32)((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0))) + 0))
11014
11015#define _CGM_PIPE_B_CSC_COEFF01(0x180000 + 0x69900) (VLV_DISPLAY_BASE0x180000 + 0x69900)
11016#define _CGM_PIPE_B_CSC_COEFF23(0x180000 + 0x69904) (VLV_DISPLAY_BASE0x180000 + 0x69904)
11017#define _CGM_PIPE_B_CSC_COEFF45(0x180000 + 0x69908) (VLV_DISPLAY_BASE0x180000 + 0x69908)
11018#define _CGM_PIPE_B_CSC_COEFF67(0x180000 + 0x6990C) (VLV_DISPLAY_BASE0x180000 + 0x6990C)
11019#define _CGM_PIPE_B_CSC_COEFF8(0x180000 + 0x69910) (VLV_DISPLAY_BASE0x180000 + 0x69910)
11020#define _CGM_PIPE_B_DEGAMMA(0x180000 + 0x68000) (VLV_DISPLAY_BASE0x180000 + 0x68000)
11021#define _CGM_PIPE_B_GAMMA(0x180000 + 0x69000) (VLV_DISPLAY_BASE0x180000 + 0x69000)
11022#define _CGM_PIPE_B_MODE(0x180000 + 0x69A00) (VLV_DISPLAY_BASE0x180000 + 0x69A00)
11023
11024#define CGM_PIPE_CSC_COEFF01(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67900)) + (pipe)
* (((0x180000 + 0x69900)) - ((0x180000 + 0x67900))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)((const i915_reg_t){ .reg = ((((0x180000 + 0x67900)) + (pipe)
* (((0x180000 + 0x69900)) - ((0x180000 + 0x67900))))) })
11025#define CGM_PIPE_CSC_COEFF23(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67904)) + (pipe)
* (((0x180000 + 0x69904)) - ((0x180000 + 0x67904))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)((const i915_reg_t){ .reg = ((((0x180000 + 0x67904)) + (pipe)
* (((0x180000 + 0x69904)) - ((0x180000 + 0x67904))))) })
11026#define CGM_PIPE_CSC_COEFF45(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67908)) + (pipe)
* (((0x180000 + 0x69908)) - ((0x180000 + 0x67908))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)((const i915_reg_t){ .reg = ((((0x180000 + 0x67908)) + (pipe)
* (((0x180000 + 0x69908)) - ((0x180000 + 0x67908))))) })
11027#define CGM_PIPE_CSC_COEFF67(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x6790C)) + (pipe)
* (((0x180000 + 0x6990C)) - ((0x180000 + 0x6790C))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)((const i915_reg_t){ .reg = ((((0x180000 + 0x6790C)) + (pipe)
* (((0x180000 + 0x6990C)) - ((0x180000 + 0x6790C))))) })
11028#define CGM_PIPE_CSC_COEFF8(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67910)) + (pipe)
* (((0x180000 + 0x69910)) - ((0x180000 + 0x67910))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)((const i915_reg_t){ .reg = ((((0x180000 + 0x67910)) + (pipe)
* (((0x180000 + 0x69910)) - ((0x180000 + 0x67910))))) })
11029#define CGM_PIPE_DEGAMMA(pipe, i, w)((const i915_reg_t){ .reg = ((((0x180000 + 0x66000)) + (pipe)
* (((0x180000 + 0x68000)) - ((0x180000 + 0x66000)))) + (i) *
8 + (w) * 4) }) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)((const i915_reg_t){ .reg = ((((0x180000 + 0x66000)) + (pipe)
* (((0x180000 + 0x68000)) - ((0x180000 + 0x66000)))) + (i) *
8 + (w) * 4) })
11030#define CGM_PIPE_GAMMA(pipe, i, w)((const i915_reg_t){ .reg = ((((0x180000 + 0x67000)) + (pipe)
* (((0x180000 + 0x69000)) - ((0x180000 + 0x67000)))) + (i) *
8 + (w) * 4) }) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)((const i915_reg_t){ .reg = ((((0x180000 + 0x67000)) + (pipe)
* (((0x180000 + 0x69000)) - ((0x180000 + 0x67000)))) + (i) *
8 + (w) * 4) })
11031#define CGM_PIPE_MODE(pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67A00)) + (pipe)
* (((0x180000 + 0x69A00)) - ((0x180000 + 0x67A00))))) }) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)((const i915_reg_t){ .reg = ((((0x180000 + 0x67A00)) + (pipe)
* (((0x180000 + 0x69A00)) - ((0x180000 + 0x67A00))))) })
11032
11033/* MIPI DSI registers */
11034
11035#define _MIPI_PORT(port, a, c)(((port) == PORT_A) ? a : c) (((port) == PORT_A) ? a : c) /* ports A and C only */
11036#define _MMIO_MIPI(port, a, c)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? a : c)) }) _MMIO(_MIPI_PORT(port, a, c))((const i915_reg_t){ .reg = ((((port) == PORT_A) ? a : c)) })
11037
11038/* Gen11 DSI */
11039#define _MMIO_DSI(tc, dsi0, dsi1)((const i915_reg_t){ .reg = (((dsi0) + ((tc) - TRANSCODER_DSI_0
) * ((dsi1) - (dsi0)))) }) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \((const i915_reg_t){ .reg = (((dsi0) + ((tc) - TRANSCODER_DSI_0
) * ((dsi1) - (dsi0)))) })
11040 dsi0, dsi1)((const i915_reg_t){ .reg = (((dsi0) + ((tc) - TRANSCODER_DSI_0
) * ((dsi1) - (dsi0)))) })
11041
11042#define MIPIO_TXESC_CLK_DIV1((const i915_reg_t){ .reg = (0x160004) }) _MMIO(0x160004)((const i915_reg_t){ .reg = (0x160004) })
11043#define GLK_TX_ESC_CLK_DIV1_MASK0x3FF 0x3FF
11044#define MIPIO_TXESC_CLK_DIV2((const i915_reg_t){ .reg = (0x160008) }) _MMIO(0x160008)((const i915_reg_t){ .reg = (0x160008) })
11045#define GLK_TX_ESC_CLK_DIV2_MASK0x3FF 0x3FF
11046
11047#define _ICL_DSI_ESC_CLK_DIV00x6b090 0x6b090
11048#define _ICL_DSI_ESC_CLK_DIV10x6b890 0x6b890
11049#define ICL_DSI_ESC_CLK_DIV(port)((const i915_reg_t){ .reg = (((0x6b090) + ((port)) * ((0x6b890
) - (0x6b090)))) }) _MMIO_PORT((port), \((const i915_reg_t){ .reg = (((0x6b090) + ((port)) * ((0x6b890
) - (0x6b090)))) })
11050 _ICL_DSI_ESC_CLK_DIV0, \((const i915_reg_t){ .reg = (((0x6b090) + ((port)) * ((0x6b890
) - (0x6b090)))) })
11051 _ICL_DSI_ESC_CLK_DIV1)((const i915_reg_t){ .reg = (((0x6b090) + ((port)) * ((0x6b890
) - (0x6b090)))) })
11052#define _ICL_DPHY_ESC_CLK_DIV00x162190 0x162190
11053#define _ICL_DPHY_ESC_CLK_DIV10x6C190 0x6C190
11054#define ICL_DPHY_ESC_CLK_DIV(port)((const i915_reg_t){ .reg = (((0x162190) + ((port)) * ((0x6C190
) - (0x162190)))) }) _MMIO_PORT((port), \((const i915_reg_t){ .reg = (((0x162190) + ((port)) * ((0x6C190
) - (0x162190)))) })
11055 _ICL_DPHY_ESC_CLK_DIV0, \((const i915_reg_t){ .reg = (((0x162190) + ((port)) * ((0x6C190
) - (0x162190)))) })
11056 _ICL_DPHY_ESC_CLK_DIV1)((const i915_reg_t){ .reg = (((0x162190) + ((port)) * ((0x6C190
) - (0x162190)))) })
11057#define ICL_BYTE_CLK_PER_ESC_CLK_MASK(0x1f << 16) (0x1f << 16)
11058#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT16 16
11059#define ICL_ESC_CLK_DIV_MASK0x1ff 0x1ff
11060#define ICL_ESC_CLK_DIV_SHIFT0 0
11061#define DSI_MAX_ESC_CLK20000 20000 /* in KHz */
11062
11063#define _DSI_CMD_FRMCTL_00x6b034 0x6b034
11064#define _DSI_CMD_FRMCTL_10x6b834 0x6b834
11065#define DSI_CMD_FRMCTL(port)((const i915_reg_t){ .reg = (((0x6b034) + (port) * ((0x6b834)
- (0x6b034)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b034) + (port) * ((0x6b834)
- (0x6b034)))) })
11066 _DSI_CMD_FRMCTL_0,\((const i915_reg_t){ .reg = (((0x6b034) + (port) * ((0x6b834)
- (0x6b034)))) })
11067 _DSI_CMD_FRMCTL_1)((const i915_reg_t){ .reg = (((0x6b034) + (port) * ((0x6b834)
- (0x6b034)))) })
11068#define DSI_FRAME_UPDATE_REQUEST(1 << 31) (1 << 31)
11069#define DSI_PERIODIC_FRAME_UPDATE_ENABLE(1 << 29) (1 << 29)
11070#define DSI_NULL_PACKET_ENABLE(1 << 28) (1 << 28)
11071#define DSI_FRAME_IN_PROGRESS(1 << 0) (1 << 0)
11072
11073#define _DSI_INTR_MASK_REG_00x6b070 0x6b070
11074#define _DSI_INTR_MASK_REG_10x6b870 0x6b870
11075#define DSI_INTR_MASK_REG(port)((const i915_reg_t){ .reg = (((0x6b070) + (port) * ((0x6b870)
- (0x6b070)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b070) + (port) * ((0x6b870)
- (0x6b070)))) })
11076 _DSI_INTR_MASK_REG_0,\((const i915_reg_t){ .reg = (((0x6b070) + (port) * ((0x6b870)
- (0x6b070)))) })
11077 _DSI_INTR_MASK_REG_1)((const i915_reg_t){ .reg = (((0x6b070) + (port) * ((0x6b870)
- (0x6b070)))) })
11078
11079#define _DSI_INTR_IDENT_REG_00x6b074 0x6b074
11080#define _DSI_INTR_IDENT_REG_10x6b874 0x6b874
11081#define DSI_INTR_IDENT_REG(port)((const i915_reg_t){ .reg = (((0x6b074) + (port) * ((0x6b874)
- (0x6b074)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b074) + (port) * ((0x6b874)
- (0x6b074)))) })
11082 _DSI_INTR_IDENT_REG_0,\((const i915_reg_t){ .reg = (((0x6b074) + (port) * ((0x6b874)
- (0x6b074)))) })
11083 _DSI_INTR_IDENT_REG_1)((const i915_reg_t){ .reg = (((0x6b074) + (port) * ((0x6b874)
- (0x6b074)))) })
11084#define DSI_TE_EVENT(1 << 31) (1 << 31)
11085#define DSI_RX_DATA_OR_BTA_TERMINATED(1 << 30) (1 << 30)
11086#define DSI_TX_DATA(1 << 29) (1 << 29)
11087#define DSI_ULPS_ENTRY_DONE(1 << 28) (1 << 28)
11088#define DSI_NON_TE_TRIGGER_RECEIVED(1 << 27) (1 << 27)
11089#define DSI_HOST_CHKSUM_ERROR(1 << 26) (1 << 26)
11090#define DSI_HOST_MULTI_ECC_ERROR(1 << 25) (1 << 25)
11091#define DSI_HOST_SINGL_ECC_ERROR(1 << 24) (1 << 24)
11092#define DSI_HOST_CONTENTION_DETECTED(1 << 23) (1 << 23)
11093#define DSI_HOST_FALSE_CONTROL_ERROR(1 << 22) (1 << 22)
11094#define DSI_HOST_TIMEOUT_ERROR(1 << 21) (1 << 21)
11095#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR(1 << 20) (1 << 20)
11096#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR(1 << 19) (1 << 19)
11097#define DSI_FRAME_UPDATE_DONE(1 << 16) (1 << 16)
11098#define DSI_PROTOCOL_VIOLATION_REPORTED(1 << 15) (1 << 15)
11099#define DSI_INVALID_TX_LENGTH(1 << 13) (1 << 13)
11100#define DSI_INVALID_VC(1 << 12) (1 << 12)
11101#define DSI_INVALID_DATA_TYPE(1 << 11) (1 << 11)
11102#define DSI_PERIPHERAL_CHKSUM_ERROR(1 << 10) (1 << 10)
11103#define DSI_PERIPHERAL_MULTI_ECC_ERROR(1 << 9) (1 << 9)
11104#define DSI_PERIPHERAL_SINGLE_ECC_ERROR(1 << 8) (1 << 8)
11105#define DSI_PERIPHERAL_CONTENTION_DETECTED(1 << 7) (1 << 7)
11106#define DSI_PERIPHERAL_FALSE_CTRL_ERROR(1 << 6) (1 << 6)
11107#define DSI_PERIPHERAL_TIMEOUT_ERROR(1 << 5) (1 << 5)
11108#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR(1 << 4) (1 << 4)
11109#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR(1 << 3) (1 << 3)
11110#define DSI_EOT_SYNC_ERROR(1 << 2) (1 << 2)
11111#define DSI_SOT_SYNC_ERROR(1 << 1) (1 << 1)
11112#define DSI_SOT_ERROR(1 << 0) (1 << 0)
11113
11114/* Gen4+ Timestamp and Pipe Frame time stamp registers */
11115#define GEN4_TIMESTAMP((const i915_reg_t){ .reg = (0x2358) }) _MMIO(0x2358)((const i915_reg_t){ .reg = (0x2358) })
11116#define ILK_TIMESTAMP_HI((const i915_reg_t){ .reg = (0x70070) }) _MMIO(0x70070)((const i915_reg_t){ .reg = (0x70070) })
11117#define IVB_TIMESTAMP_CTR((const i915_reg_t){ .reg = (0x44070) }) _MMIO(0x44070)((const i915_reg_t){ .reg = (0x44070) })
11118
11119#define GEN9_TIMESTAMP_OVERRIDE((const i915_reg_t){ .reg = (0x44074) }) _MMIO(0x44074)((const i915_reg_t){ .reg = (0x44074) })
11120#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT0 0
11121#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK0x3ff 0x3ff
11122#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT12 12
11123#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK(0xf << 12) (0xf << 12)
11124
11125#define _PIPE_FRMTMSTMP_A0x70048 0x70048
11126#define PIPE_FRMTMSTMP(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70048) + ((&(dev_priv)->__info)->display_mmio_offset
)) }) \
11127 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70048) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
11128
11129/* BXT MIPI clock controls */
11130#define BXT_MAX_VAR_OUTPUT_KHZ39500 39500
11131
11132#define BXT_MIPI_CLOCK_CTL((const i915_reg_t){ .reg = (0x46090) }) _MMIO(0x46090)((const i915_reg_t){ .reg = (0x46090) })
11133#define BXT_MIPI1_DIV_SHIFT26 26
11134#define BXT_MIPI2_DIV_SHIFT10 10
11135#define BXT_MIPI_DIV_SHIFT(port)(((port) == PORT_A) ? 26 : 10) \
11136 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \(((port) == PORT_A) ? 26 : 10)
11137 BXT_MIPI2_DIV_SHIFT)(((port) == PORT_A) ? 26 : 10)
11138
11139/* TX control divider to select actual TX clock output from (8x/var) */
11140#define BXT_MIPI1_TX_ESCLK_SHIFT26 26
11141#define BXT_MIPI2_TX_ESCLK_SHIFT10 10
11142#define BXT_MIPI_TX_ESCLK_SHIFT(port)(((port) == PORT_A) ? 26 : 10) \
11143 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \(((port) == PORT_A) ? 26 : 10)
11144 BXT_MIPI2_TX_ESCLK_SHIFT)(((port) == PORT_A) ? 26 : 10)
11145#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(0x3F << 26) (0x3F << 26)
11146#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(0x3F << 10) (0x3F << 10)
11147#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)(((port) == PORT_A) ? (0x3F << 26) : (0x3F << 10)
) \
11148 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \(((port) == PORT_A) ? (0x3F << 26) : (0x3F << 10)
)
11149 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)(((port) == PORT_A) ? (0x3F << 26) : (0x3F << 10)
)
11150#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val)(((val) & 0x3F) << (((port) == PORT_A) ? 26 : 10)) \
11151 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)(((port) == PORT_A) ? 26 : 10))
11152/* RX upper control divider to select actual RX clock output from 8x */
11153#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT21 21
11154#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT5 5
11155#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)(((port) == PORT_A) ? 21 : 5) \
11156 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \(((port) == PORT_A) ? 21 : 5)
11157 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)(((port) == PORT_A) ? 21 : 5)
11158#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK(3 << 21) (3 << 21)
11159#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK(3 << 5) (3 << 5)
11160#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)(((port) == PORT_A) ? (3 << 21) : (3 << 5)) \
11161 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \(((port) == PORT_A) ? (3 << 21) : (3 << 5))
11162 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)(((port) == PORT_A) ? (3 << 21) : (3 << 5))
11163#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)(((val) & 3) << (((port) == PORT_A) ? 21 : 5)) \
11164 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)(((port) == PORT_A) ? 21 : 5))
11165/* 8/3X divider to select the actual 8/3X clock output from 8x */
11166#define BXT_MIPI1_8X_BY3_SHIFT19 19
11167#define BXT_MIPI2_8X_BY3_SHIFT3 3
11168#define BXT_MIPI_8X_BY3_SHIFT(port)(((port) == PORT_A) ? 19 : 3) \
11169 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \(((port) == PORT_A) ? 19 : 3)
11170 BXT_MIPI2_8X_BY3_SHIFT)(((port) == PORT_A) ? 19 : 3)
11171#define BXT_MIPI1_8X_BY3_DIVIDER_MASK(3 << 19) (3 << 19)
11172#define BXT_MIPI2_8X_BY3_DIVIDER_MASK(3 << 3) (3 << 3)
11173#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port)(((port) == PORT_A) ? (3 << 19) : (3 << 3)) \
11174 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \(((port) == PORT_A) ? (3 << 19) : (3 << 3))
11175 BXT_MIPI2_8X_BY3_DIVIDER_MASK)(((port) == PORT_A) ? (3 << 19) : (3 << 3))
11176#define BXT_MIPI_8X_BY3_DIVIDER(port, val)(((val) & 3) << (((port) == PORT_A) ? 19 : 3)) \
11177 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)(((port) == PORT_A) ? 19 : 3))
11178/* RX lower control divider to select actual RX clock output from 8x */
11179#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT16 16
11180#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT0 0
11181#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)(((port) == PORT_A) ? 16 : 0) \
11182 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \(((port) == PORT_A) ? 16 : 0)
11183 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)(((port) == PORT_A) ? 16 : 0)
11184#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK(3 << 16) (3 << 16)
11185#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK(3 << 0) (3 << 0)
11186#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)(((port) == PORT_A) ? (3 << 16) : (3 << 0)) \
11187 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \(((port) == PORT_A) ? (3 << 16) : (3 << 0))
11188 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)(((port) == PORT_A) ? (3 << 16) : (3 << 0))
11189#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)(((val) & 3) << (((port) == PORT_A) ? 16 : 0)) \
11190 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)(((port) == PORT_A) ? 16 : 0))
11191
11192#define RX_DIVIDER_BIT_1_20x3 0x3
11193#define RX_DIVIDER_BIT_3_40xC 0xC
11194
11195/* BXT MIPI mode configure */
11196#define _BXT_MIPIA_TRANS_HACTIVE0x6B0F8 0x6B0F8
11197#define _BXT_MIPIC_TRANS_HACTIVE0x6B8F8 0x6B8F8
11198#define BXT_MIPI_TRANS_HACTIVE(tc)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0F8 : 0x6B8F8
)) }) _MMIO_MIPI(tc, \((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0F8 : 0x6B8F8
)) })
11199 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0F8 : 0x6B8F8
)) })
11200
11201#define _BXT_MIPIA_TRANS_VACTIVE0x6B0FC 0x6B0FC
11202#define _BXT_MIPIC_TRANS_VACTIVE0x6B8FC 0x6B8FC
11203#define BXT_MIPI_TRANS_VACTIVE(tc)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0FC : 0x6B8FC
)) }) _MMIO_MIPI(tc, \((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0FC : 0x6B8FC
)) })
11204 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0FC : 0x6B8FC
)) })
11205
11206#define _BXT_MIPIA_TRANS_VTOTAL0x6B100 0x6B100
11207#define _BXT_MIPIC_TRANS_VTOTAL0x6B900 0x6B900
11208#define BXT_MIPI_TRANS_VTOTAL(tc)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B100 : 0x6B900
)) }) _MMIO_MIPI(tc, \((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B100 : 0x6B900
)) })
11209 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B100 : 0x6B900
)) })
11210
11211#define BXT_DSI_PLL_CTL((const i915_reg_t){ .reg = (0x161000) }) _MMIO(0x161000)((const i915_reg_t){ .reg = (0x161000) })
11212#define BXT_DSI_PLL_PVD_RATIO_SHIFT16 16
11213#define BXT_DSI_PLL_PVD_RATIO_MASK(3 << 16) (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT16)
11214#define BXT_DSI_PLL_PVD_RATIO_1(1 << 16) (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT16)
11215#define BXT_DSIC_16X_BY1(0 << 10) (0 << 10)
11216#define BXT_DSIC_16X_BY2(1 << 10) (1 << 10)
11217#define BXT_DSIC_16X_BY3(2 << 10) (2 << 10)
11218#define BXT_DSIC_16X_BY4(3 << 10) (3 << 10)
11219#define BXT_DSIC_16X_MASK(3 << 10) (3 << 10)
11220#define BXT_DSIA_16X_BY1(0 << 8) (0 << 8)
11221#define BXT_DSIA_16X_BY2(1 << 8) (1 << 8)
11222#define BXT_DSIA_16X_BY3(2 << 8) (2 << 8)
11223#define BXT_DSIA_16X_BY4(3 << 8) (3 << 8)
11224#define BXT_DSIA_16X_MASK(3 << 8) (3 << 8)
11225#define BXT_DSI_FREQ_SEL_SHIFT8 8
11226#define BXT_DSI_FREQ_SEL_MASK(0xF << 8) (0xF << BXT_DSI_FREQ_SEL_SHIFT8)
11227
11228#define BXT_DSI_PLL_RATIO_MAX0x7D 0x7D
11229#define BXT_DSI_PLL_RATIO_MIN0x22 0x22
11230#define GLK_DSI_PLL_RATIO_MAX0x6F 0x6F
11231#define GLK_DSI_PLL_RATIO_MIN0x22 0x22
11232#define BXT_DSI_PLL_RATIO_MASK0xFF 0xFF
11233#define BXT_REF_CLOCK_KHZ19200 19200
11234
11235#define BXT_DSI_PLL_ENABLE((const i915_reg_t){ .reg = (0x46080) }) _MMIO(0x46080)((const i915_reg_t){ .reg = (0x46080) })
11236#define BXT_DSI_PLL_DO_ENABLE(1 << 31) (1 << 31)
11237#define BXT_DSI_PLL_LOCKED(1 << 30) (1 << 30)
11238
11239#define _MIPIA_PORT_CTRL(0x180000 + 0x61190) (VLV_DISPLAY_BASE0x180000 + 0x61190)
11240#define _MIPIC_PORT_CTRL(0x180000 + 0x61700) (VLV_DISPLAY_BASE0x180000 + 0x61700)
11241#define MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61190) : (0x180000 + 0x61700))) }) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61190) : (0x180000 + 0x61700))) })
11242
11243 /* BXT port control */
11244#define _BXT_MIPIA_PORT_CTRL0x6B0C0 0x6B0C0
11245#define _BXT_MIPIC_PORT_CTRL0x6B8C0 0x6B8C0
11246#define BXT_MIPI_PORT_CTRL(tc)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)((const i915_reg_t){ .reg = ((((tc) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) })
11247
11248/* ICL DSI MODE control */
11249#define _ICL_DSI_IO_MODECTL_00x6B094 0x6B094
11250#define _ICL_DSI_IO_MODECTL_10x6B894 0x6B894
11251#define ICL_DSI_IO_MODECTL(port)((const i915_reg_t){ .reg = (((0x6B094) + (port) * ((0x6B894)
- (0x6B094)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6B094) + (port) * ((0x6B894)
- (0x6B094)))) })
11252 _ICL_DSI_IO_MODECTL_0, \((const i915_reg_t){ .reg = (((0x6B094) + (port) * ((0x6B894)
- (0x6B094)))) })
11253 _ICL_DSI_IO_MODECTL_1)((const i915_reg_t){ .reg = (((0x6B094) + (port) * ((0x6B894)
- (0x6B094)))) })
11254#define COMBO_PHY_MODE_DSI(1 << 0) (1 << 0)
11255
11256/* Display Stream Splitter Control */
11257#define DSS_CTL1((const i915_reg_t){ .reg = (0x67400) }) _MMIO(0x67400)((const i915_reg_t){ .reg = (0x67400) })
11258#define SPLITTER_ENABLE(1 << 31) (1 << 31)
11259#define JOINER_ENABLE(1 << 30) (1 << 30)
11260#define DUAL_LINK_MODE_INTERLEAVE(1 << 24) (1 << 24)
11261#define DUAL_LINK_MODE_FRONTBACK(0 << 24) (0 << 24)
11262#define OVERLAP_PIXELS_MASK(0xf << 16) (0xf << 16)
11263#define OVERLAP_PIXELS(pixels)((pixels) << 16) ((pixels) << 16)
11264#define LEFT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0) (0xfff << 0)
11265#define LEFT_DL_BUF_TARGET_DEPTH(pixels)((pixels) << 0) ((pixels) << 0)
11266#define MAX_DL_BUFFER_TARGET_DEPTH0x5a0 0x5a0
11267
11268#define DSS_CTL2((const i915_reg_t){ .reg = (0x67404) }) _MMIO(0x67404)((const i915_reg_t){ .reg = (0x67404) })
11269#define LEFT_BRANCH_VDSC_ENABLE(1 << 31) (1 << 31)
11270#define RIGHT_BRANCH_VDSC_ENABLE(1 << 15) (1 << 15)
11271#define RIGHT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0) (0xfff << 0)
11272#define RIGHT_DL_BUF_TARGET_DEPTH(pixels)((pixels) << 0) ((pixels) << 0)
11273
11274#define _ICL_PIPE_DSS_CTL1_PB0x78200 0x78200
11275#define _ICL_PIPE_DSS_CTL1_PC0x78400 0x78400
11276#define ICL_PIPE_DSS_CTL1(pipe)((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) *
((0x78400) - (0x78200)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) *
((0x78400) - (0x78200)))) })
11277 _ICL_PIPE_DSS_CTL1_PB, \((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) *
((0x78400) - (0x78200)))) })
11278 _ICL_PIPE_DSS_CTL1_PC)((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) *
((0x78400) - (0x78200)))) })
11279#define BIG_JOINER_ENABLE(1 << 29) (1 << 29)
11280#define MASTER_BIG_JOINER_ENABLE(1 << 28) (1 << 28)
11281#define VGA_CENTERING_ENABLE(1 << 27) (1 << 27)
11282
11283#define _ICL_PIPE_DSS_CTL2_PB0x78204 0x78204
11284#define _ICL_PIPE_DSS_CTL2_PC0x78404 0x78404
11285#define ICL_PIPE_DSS_CTL2(pipe)((const i915_reg_t){ .reg = (((0x78204) + ((pipe) - PIPE_B) *
((0x78404) - (0x78204)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78204) + ((pipe) - PIPE_B) *
((0x78404) - (0x78204)))) })
11286 _ICL_PIPE_DSS_CTL2_PB, \((const i915_reg_t){ .reg = (((0x78204) + ((pipe) - PIPE_B) *
((0x78404) - (0x78204)))) })
11287 _ICL_PIPE_DSS_CTL2_PC)((const i915_reg_t){ .reg = (((0x78204) + ((pipe) - PIPE_B) *
((0x78404) - (0x78204)))) })
11288
11289#define BXT_P_DSI_REGULATOR_CFG((const i915_reg_t){ .reg = (0x160020) }) _MMIO(0x160020)((const i915_reg_t){ .reg = (0x160020) })
11290#define STAP_SELECT(1 << 0) (1 << 0)
11291
11292#define BXT_P_DSI_REGULATOR_TX_CTRL((const i915_reg_t){ .reg = (0x160054) }) _MMIO(0x160054)((const i915_reg_t){ .reg = (0x160054) })
11293#define HS_IO_CTRL_SELECT(1 << 0) (1 << 0)
11294
11295#define DPI_ENABLE(1 << 31) (1 << 31) /* A + C */
11296#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT27 27
11297#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 27) (0xf << 27)
11298#define DUAL_LINK_MODE_SHIFT26 26
11299#define DUAL_LINK_MODE_MASK(1 << 26) (1 << 26)
11300#define DUAL_LINK_MODE_FRONT_BACK(0 << 26) (0 << 26)
11301#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE(1 << 26) (1 << 26)
11302#define DITHERING_ENABLE(1 << 25) (1 << 25) /* A + C */
11303#define FLOPPED_HSTX(1 << 23) (1 << 23)
11304#define DE_INVERT(1 << 19) (1 << 19) /* XXX */
11305#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT18 18
11306#define MIPIA_FLISDSI_DELAY_COUNT_MASK(0xf << 18) (0xf << 18)
11307#define AFE_LATCHOUT(1 << 17) (1 << 17)
11308#define LP_OUTPUT_HOLD(1 << 16) (1 << 16)
11309#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT15 15
11310#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK(1 << 15) (1 << 15)
11311#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT11 11
11312#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 11) (0xf << 11)
11313#define CSB_SHIFT9 9
11314#define CSB_MASK(3 << 9) (3 << 9)
11315#define CSB_20MHZ(0 << 9) (0 << 9)
11316#define CSB_10MHZ(1 << 9) (1 << 9)
11317#define CSB_40MHZ(2 << 9) (2 << 9)
11318#define BANDGAP_MASK(1 << 8) (1 << 8)
11319#define BANDGAP_PNW_CIRCUIT(0 << 8) (0 << 8)
11320#define BANDGAP_LNC_CIRCUIT(1 << 8) (1 << 8)
11321#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT5 5
11322#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK(7 << 5) (7 << 5)
11323#define TEARING_EFFECT_DELAY(1 << 4) (1 << 4) /* A + C */
11324#define TEARING_EFFECT_SHIFT2 2 /* A + C */
11325#define TEARING_EFFECT_MASK(3 << 2) (3 << 2)
11326#define TEARING_EFFECT_OFF(0 << 2) (0 << 2)
11327#define TEARING_EFFECT_DSI(1 << 2) (1 << 2)
11328#define TEARING_EFFECT_GPIO(2 << 2) (2 << 2)
11329#define LANE_CONFIGURATION_SHIFT0 0
11330#define LANE_CONFIGURATION_MASK(3 << 0) (3 << 0)
11331#define LANE_CONFIGURATION_4LANE(0 << 0) (0 << 0)
11332#define LANE_CONFIGURATION_DUAL_LINK_A(1 << 0) (1 << 0)
11333#define LANE_CONFIGURATION_DUAL_LINK_B(2 << 0) (2 << 0)
11334
11335#define _MIPIA_TEARING_CTRL(0x180000 + 0x61194) (VLV_DISPLAY_BASE0x180000 + 0x61194)
11336#define _MIPIC_TEARING_CTRL(0x180000 + 0x61704) (VLV_DISPLAY_BASE0x180000 + 0x61704)
11337#define MIPI_TEARING_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61194) : (0x180000 + 0x61704))) }) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61194) : (0x180000 + 0x61704))) })
11338#define TEARING_EFFECT_DELAY_SHIFT0 0
11339#define TEARING_EFFECT_DELAY_MASK(0xffff << 0) (0xffff << 0)
11340
11341/* XXX: all bits reserved */
11342#define _MIPIA_AUTOPWG(0x180000 + 0x611a0) (VLV_DISPLAY_BASE0x180000 + 0x611a0)
11343
11344/* MIPI DSI Controller and D-PHY registers */
11345
11346#define _MIPIA_DEVICE_READY(dev_priv->mipi_mmio_base + 0xb000) (dev_priv->mipi_mmio_base + 0xb000)
11347#define _MIPIC_DEVICE_READY(dev_priv->mipi_mmio_base + 0xb800) (dev_priv->mipi_mmio_base + 0xb800)
11348#define MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb000) : (dev_priv->mipi_mmio_base + 0xb800
))) }) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb000) : (dev_priv->mipi_mmio_base + 0xb800
))) })
11349#define BUS_POSSESSION(1 << 3) (1 << 3) /* set to give bus to receiver */
11350#define ULPS_STATE_MASK(3 << 1) (3 << 1)
11351#define ULPS_STATE_ENTER(2 << 1) (2 << 1)
11352#define ULPS_STATE_EXIT(1 << 1) (1 << 1)
11353#define ULPS_STATE_NORMAL_OPERATION(0 << 1) (0 << 1)
11354#define DEVICE_READY(1 << 0) (1 << 0)
11355
11356#define _MIPIA_INTR_STAT(dev_priv->mipi_mmio_base + 0xb004) (dev_priv->mipi_mmio_base + 0xb004)
11357#define _MIPIC_INTR_STAT(dev_priv->mipi_mmio_base + 0xb804) (dev_priv->mipi_mmio_base + 0xb804)
11358#define MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb004) : (dev_priv->mipi_mmio_base + 0xb804
))) }) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb004) : (dev_priv->mipi_mmio_base + 0xb804
))) })
11359#define _MIPIA_INTR_EN(dev_priv->mipi_mmio_base + 0xb008) (dev_priv->mipi_mmio_base + 0xb008)
11360#define _MIPIC_INTR_EN(dev_priv->mipi_mmio_base + 0xb808) (dev_priv->mipi_mmio_base + 0xb808)
11361#define MIPI_INTR_EN(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb008) : (dev_priv->mipi_mmio_base + 0xb808
))) }) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb008) : (dev_priv->mipi_mmio_base + 0xb808
))) })
11362#define TEARING_EFFECT(1 << 31) (1 << 31)
11363#define SPL_PKT_SENT_INTERRUPT(1 << 30) (1 << 30)
11364#define GEN_READ_DATA_AVAIL(1 << 29) (1 << 29)
11365#define LP_GENERIC_WR_FIFO_FULL(1 << 28) (1 << 28)
11366#define HS_GENERIC_WR_FIFO_FULL(1 << 27) (1 << 27)
11367#define RX_PROT_VIOLATION(1 << 26) (1 << 26)
11368#define RX_INVALID_TX_LENGTH(1 << 25) (1 << 25)
11369#define ACK_WITH_NO_ERROR(1 << 24) (1 << 24)
11370#define TURN_AROUND_ACK_TIMEOUT(1 << 23) (1 << 23)
11371#define LP_RX_TIMEOUT(1 << 22) (1 << 22)
11372#define HS_TX_TIMEOUT(1 << 21) (1 << 21)
11373#define DPI_FIFO_UNDERRUN(1 << 20) (1 << 20)
11374#define LOW_CONTENTION(1 << 19) (1 << 19)
11375#define HIGH_CONTENTION(1 << 18) (1 << 18)
11376#define TXDSI_VC_ID_INVALID(1 << 17) (1 << 17)
11377#define TXDSI_DATA_TYPE_NOT_RECOGNISED(1 << 16) (1 << 16)
11378#define TXCHECKSUM_ERROR(1 << 15) (1 << 15)
11379#define TXECC_MULTIBIT_ERROR(1 << 14) (1 << 14)
11380#define TXECC_SINGLE_BIT_ERROR(1 << 13) (1 << 13)
11381#define TXFALSE_CONTROL_ERROR(1 << 12) (1 << 12)
11382#define RXDSI_VC_ID_INVALID(1 << 11) (1 << 11)
11383#define RXDSI_DATA_TYPE_NOT_REGOGNISED(1 << 10) (1 << 10)
11384#define RXCHECKSUM_ERROR(1 << 9) (1 << 9)
11385#define RXECC_MULTIBIT_ERROR(1 << 8) (1 << 8)
11386#define RXECC_SINGLE_BIT_ERROR(1 << 7) (1 << 7)
11387#define RXFALSE_CONTROL_ERROR(1 << 6) (1 << 6)
11388#define RXHS_RECEIVE_TIMEOUT_ERROR(1 << 5) (1 << 5)
11389#define RX_LP_TX_SYNC_ERROR(1 << 4) (1 << 4)
11390#define RXEXCAPE_MODE_ENTRY_ERROR(1 << 3) (1 << 3)
11391#define RXEOT_SYNC_ERROR(1 << 2) (1 << 2)
11392#define RXSOT_SYNC_ERROR(1 << 1) (1 << 1)
11393#define RXSOT_ERROR(1 << 0) (1 << 0)
11394
11395#define _MIPIA_DSI_FUNC_PRG(dev_priv->mipi_mmio_base + 0xb00c) (dev_priv->mipi_mmio_base + 0xb00c)
11396#define _MIPIC_DSI_FUNC_PRG(dev_priv->mipi_mmio_base + 0xb80c) (dev_priv->mipi_mmio_base + 0xb80c)
11397#define MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb00c) : (dev_priv->mipi_mmio_base + 0xb80c
))) }) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb00c) : (dev_priv->mipi_mmio_base + 0xb80c
))) })
11398#define CMD_MODE_DATA_WIDTH_MASK(7 << 13) (7 << 13)
11399#define CMD_MODE_NOT_SUPPORTED(0 << 13) (0 << 13)
11400#define CMD_MODE_DATA_WIDTH_16_BIT(1 << 13) (1 << 13)
11401#define CMD_MODE_DATA_WIDTH_9_BIT(2 << 13) (2 << 13)
11402#define CMD_MODE_DATA_WIDTH_8_BIT(3 << 13) (3 << 13)
11403#define CMD_MODE_DATA_WIDTH_OPTION1(4 << 13) (4 << 13)
11404#define CMD_MODE_DATA_WIDTH_OPTION2(5 << 13) (5 << 13)
11405#define VID_MODE_FORMAT_MASK(0xf << 7) (0xf << 7)
11406#define VID_MODE_NOT_SUPPORTED(0 << 7) (0 << 7)
11407#define VID_MODE_FORMAT_RGB565(1 << 7) (1 << 7)
11408#define VID_MODE_FORMAT_RGB666_PACKED(2 << 7) (2 << 7)
11409#define VID_MODE_FORMAT_RGB666(3 << 7) (3 << 7)
11410#define VID_MODE_FORMAT_RGB888(4 << 7) (4 << 7)
11411#define CMD_MODE_CHANNEL_NUMBER_SHIFT5 5
11412#define CMD_MODE_CHANNEL_NUMBER_MASK(3 << 5) (3 << 5)
11413#define VID_MODE_CHANNEL_NUMBER_SHIFT3 3
11414#define VID_MODE_CHANNEL_NUMBER_MASK(3 << 3) (3 << 3)
11415#define DATA_LANES_PRG_REG_SHIFT0 0
11416#define DATA_LANES_PRG_REG_MASK(7 << 0) (7 << 0)
11417
11418#define _MIPIA_HS_TX_TIMEOUT(dev_priv->mipi_mmio_base + 0xb010) (dev_priv->mipi_mmio_base + 0xb010)
11419#define _MIPIC_HS_TX_TIMEOUT(dev_priv->mipi_mmio_base + 0xb810) (dev_priv->mipi_mmio_base + 0xb810)
11420#define MIPI_HS_TX_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb010) : (dev_priv->mipi_mmio_base + 0xb810
))) }) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb010) : (dev_priv->mipi_mmio_base + 0xb810
))) })
11421#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK0xffffff 0xffffff
11422
11423#define _MIPIA_LP_RX_TIMEOUT(dev_priv->mipi_mmio_base + 0xb014) (dev_priv->mipi_mmio_base + 0xb014)
11424#define _MIPIC_LP_RX_TIMEOUT(dev_priv->mipi_mmio_base + 0xb814) (dev_priv->mipi_mmio_base + 0xb814)
11425#define MIPI_LP_RX_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb014) : (dev_priv->mipi_mmio_base + 0xb814
))) }) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb014) : (dev_priv->mipi_mmio_base + 0xb814
))) })
11426#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK0xffffff 0xffffff
11427
11428#define _MIPIA_TURN_AROUND_TIMEOUT(dev_priv->mipi_mmio_base + 0xb018) (dev_priv->mipi_mmio_base + 0xb018)
11429#define _MIPIC_TURN_AROUND_TIMEOUT(dev_priv->mipi_mmio_base + 0xb818) (dev_priv->mipi_mmio_base + 0xb818)
11430#define MIPI_TURN_AROUND_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb018) : (dev_priv->mipi_mmio_base + 0xb818
))) }) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb018) : (dev_priv->mipi_mmio_base + 0xb818
))) })
11431#define TURN_AROUND_TIMEOUT_MASK0x3f 0x3f
11432
11433#define _MIPIA_DEVICE_RESET_TIMER(dev_priv->mipi_mmio_base + 0xb01c) (dev_priv->mipi_mmio_base + 0xb01c)
11434#define _MIPIC_DEVICE_RESET_TIMER(dev_priv->mipi_mmio_base + 0xb81c) (dev_priv->mipi_mmio_base + 0xb81c)
11435#define MIPI_DEVICE_RESET_TIMER(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb01c) : (dev_priv->mipi_mmio_base + 0xb81c
))) }) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb01c) : (dev_priv->mipi_mmio_base + 0xb81c
))) })
11436#define DEVICE_RESET_TIMER_MASK0xffff 0xffff
11437
11438#define _MIPIA_DPI_RESOLUTION(dev_priv->mipi_mmio_base + 0xb020) (dev_priv->mipi_mmio_base + 0xb020)
11439#define _MIPIC_DPI_RESOLUTION(dev_priv->mipi_mmio_base + 0xb820) (dev_priv->mipi_mmio_base + 0xb820)
11440#define MIPI_DPI_RESOLUTION(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb020) : (dev_priv->mipi_mmio_base + 0xb820
))) }) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb020) : (dev_priv->mipi_mmio_base + 0xb820
))) })
11441#define VERTICAL_ADDRESS_SHIFT16 16
11442#define VERTICAL_ADDRESS_MASK(0xffff << 16) (0xffff << 16)
11443#define HORIZONTAL_ADDRESS_SHIFT0 0
11444#define HORIZONTAL_ADDRESS_MASK0xffff 0xffff
11445
11446#define _MIPIA_DBI_FIFO_THROTTLE(dev_priv->mipi_mmio_base + 0xb024) (dev_priv->mipi_mmio_base + 0xb024)
11447#define _MIPIC_DBI_FIFO_THROTTLE(dev_priv->mipi_mmio_base + 0xb824) (dev_priv->mipi_mmio_base + 0xb824)
11448#define MIPI_DBI_FIFO_THROTTLE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb024) : (dev_priv->mipi_mmio_base + 0xb824
))) }) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb024) : (dev_priv->mipi_mmio_base + 0xb824
))) })
11449#define DBI_FIFO_EMPTY_HALF(0 << 0) (0 << 0)
11450#define DBI_FIFO_EMPTY_QUARTER(1 << 0) (1 << 0)
11451#define DBI_FIFO_EMPTY_7_LOCATIONS(2 << 0) (2 << 0)
11452
11453/* regs below are bits 15:0 */
11454#define _MIPIA_HSYNC_PADDING_COUNT(dev_priv->mipi_mmio_base + 0xb028) (dev_priv->mipi_mmio_base + 0xb028)
11455#define _MIPIC_HSYNC_PADDING_COUNT(dev_priv->mipi_mmio_base + 0xb828) (dev_priv->mipi_mmio_base + 0xb828)
11456#define MIPI_HSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb028) : (dev_priv->mipi_mmio_base + 0xb828
))) }) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb028) : (dev_priv->mipi_mmio_base + 0xb828
))) })
11457
11458#define _MIPIA_HBP_COUNT(dev_priv->mipi_mmio_base + 0xb02c) (dev_priv->mipi_mmio_base + 0xb02c)
11459#define _MIPIC_HBP_COUNT(dev_priv->mipi_mmio_base + 0xb82c) (dev_priv->mipi_mmio_base + 0xb82c)
11460#define MIPI_HBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb02c) : (dev_priv->mipi_mmio_base + 0xb82c
))) }) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb02c) : (dev_priv->mipi_mmio_base + 0xb82c
))) })
11461
11462#define _MIPIA_HFP_COUNT(dev_priv->mipi_mmio_base + 0xb030) (dev_priv->mipi_mmio_base + 0xb030)
11463#define _MIPIC_HFP_COUNT(dev_priv->mipi_mmio_base + 0xb830) (dev_priv->mipi_mmio_base + 0xb830)
11464#define MIPI_HFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb030) : (dev_priv->mipi_mmio_base + 0xb830
))) }) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb030) : (dev_priv->mipi_mmio_base + 0xb830
))) })
11465
11466#define _MIPIA_HACTIVE_AREA_COUNT(dev_priv->mipi_mmio_base + 0xb034) (dev_priv->mipi_mmio_base + 0xb034)
11467#define _MIPIC_HACTIVE_AREA_COUNT(dev_priv->mipi_mmio_base + 0xb834) (dev_priv->mipi_mmio_base + 0xb834)
11468#define MIPI_HACTIVE_AREA_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb034) : (dev_priv->mipi_mmio_base + 0xb834
))) }) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb034) : (dev_priv->mipi_mmio_base + 0xb834
))) })
11469
11470#define _MIPIA_VSYNC_PADDING_COUNT(dev_priv->mipi_mmio_base + 0xb038) (dev_priv->mipi_mmio_base + 0xb038)
11471#define _MIPIC_VSYNC_PADDING_COUNT(dev_priv->mipi_mmio_base + 0xb838) (dev_priv->mipi_mmio_base + 0xb838)
11472#define MIPI_VSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb038) : (dev_priv->mipi_mmio_base + 0xb838
))) }) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb038) : (dev_priv->mipi_mmio_base + 0xb838
))) })
11473
11474#define _MIPIA_VBP_COUNT(dev_priv->mipi_mmio_base + 0xb03c) (dev_priv->mipi_mmio_base + 0xb03c)
11475#define _MIPIC_VBP_COUNT(dev_priv->mipi_mmio_base + 0xb83c) (dev_priv->mipi_mmio_base + 0xb83c)
11476#define MIPI_VBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb03c) : (dev_priv->mipi_mmio_base + 0xb83c
))) }) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb03c) : (dev_priv->mipi_mmio_base + 0xb83c
))) })
11477
11478#define _MIPIA_VFP_COUNT(dev_priv->mipi_mmio_base + 0xb040) (dev_priv->mipi_mmio_base + 0xb040)
11479#define _MIPIC_VFP_COUNT(dev_priv->mipi_mmio_base + 0xb840) (dev_priv->mipi_mmio_base + 0xb840)
11480#define MIPI_VFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb040) : (dev_priv->mipi_mmio_base + 0xb840
))) }) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb040) : (dev_priv->mipi_mmio_base + 0xb840
))) })
11481
11482#define _MIPIA_HIGH_LOW_SWITCH_COUNT(dev_priv->mipi_mmio_base + 0xb044) (dev_priv->mipi_mmio_base + 0xb044)
11483#define _MIPIC_HIGH_LOW_SWITCH_COUNT(dev_priv->mipi_mmio_base + 0xb844) (dev_priv->mipi_mmio_base + 0xb844)
11484#define MIPI_HIGH_LOW_SWITCH_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb044) : (dev_priv->mipi_mmio_base + 0xb844
))) }) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb044) : (dev_priv->mipi_mmio_base + 0xb844
))) })
11485
11486/* regs above are bits 15:0 */
11487
11488#define _MIPIA_DPI_CONTROL(dev_priv->mipi_mmio_base + 0xb048) (dev_priv->mipi_mmio_base + 0xb048)
11489#define _MIPIC_DPI_CONTROL(dev_priv->mipi_mmio_base + 0xb848) (dev_priv->mipi_mmio_base + 0xb848)
11490#define MIPI_DPI_CONTROL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb048) : (dev_priv->mipi_mmio_base + 0xb848
))) }) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb048) : (dev_priv->mipi_mmio_base + 0xb848
))) })
11491#define DPI_LP_MODE(1 << 6) (1 << 6)
11492#define BACKLIGHT_OFF(1 << 5) (1 << 5)
11493#define BACKLIGHT_ON(1 << 4) (1 << 4)
11494#define COLOR_MODE_OFF(1 << 3) (1 << 3)
11495#define COLOR_MODE_ON(1 << 2) (1 << 2)
11496#define TURN_ON(1 << 1) (1 << 1)
11497#define SHUTDOWN(1 << 0) (1 << 0)
11498
11499#define _MIPIA_DPI_DATA(dev_priv->mipi_mmio_base + 0xb04c) (dev_priv->mipi_mmio_base + 0xb04c)
11500#define _MIPIC_DPI_DATA(dev_priv->mipi_mmio_base + 0xb84c) (dev_priv->mipi_mmio_base + 0xb84c)
11501#define MIPI_DPI_DATA(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb04c) : (dev_priv->mipi_mmio_base + 0xb84c
))) }) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb04c) : (dev_priv->mipi_mmio_base + 0xb84c
))) })
11502#define COMMAND_BYTE_SHIFT0 0
11503#define COMMAND_BYTE_MASK(0x3f << 0) (0x3f << 0)
11504
11505#define _MIPIA_INIT_COUNT(dev_priv->mipi_mmio_base + 0xb050) (dev_priv->mipi_mmio_base + 0xb050)
11506#define _MIPIC_INIT_COUNT(dev_priv->mipi_mmio_base + 0xb850) (dev_priv->mipi_mmio_base + 0xb850)
11507#define MIPI_INIT_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb050) : (dev_priv->mipi_mmio_base + 0xb850
))) }) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb050) : (dev_priv->mipi_mmio_base + 0xb850
))) })
11508#define MASTER_INIT_TIMER_SHIFT0 0
11509#define MASTER_INIT_TIMER_MASK(0xffff << 0) (0xffff << 0)
11510
11511#define _MIPIA_MAX_RETURN_PKT_SIZE(dev_priv->mipi_mmio_base + 0xb054) (dev_priv->mipi_mmio_base + 0xb054)
11512#define _MIPIC_MAX_RETURN_PKT_SIZE(dev_priv->mipi_mmio_base + 0xb854) (dev_priv->mipi_mmio_base + 0xb854)
11513#define MIPI_MAX_RETURN_PKT_SIZE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb054) : (dev_priv->mipi_mmio_base + 0xb854
))) }) _MMIO_MIPI(port, \((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb054) : (dev_priv->mipi_mmio_base + 0xb854
))) })
11514 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb054) : (dev_priv->mipi_mmio_base + 0xb854
))) })
11515#define MAX_RETURN_PKT_SIZE_SHIFT0 0
11516#define MAX_RETURN_PKT_SIZE_MASK(0x3ff << 0) (0x3ff << 0)
11517
11518#define _MIPIA_VIDEO_MODE_FORMAT(dev_priv->mipi_mmio_base + 0xb058) (dev_priv->mipi_mmio_base + 0xb058)
11519#define _MIPIC_VIDEO_MODE_FORMAT(dev_priv->mipi_mmio_base + 0xb858) (dev_priv->mipi_mmio_base + 0xb858)
11520#define MIPI_VIDEO_MODE_FORMAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb058) : (dev_priv->mipi_mmio_base + 0xb858
))) }) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb058) : (dev_priv->mipi_mmio_base + 0xb858
))) })
11521#define RANDOM_DPI_DISPLAY_RESOLUTION(1 << 4) (1 << 4)
11522#define DISABLE_VIDEO_BTA(1 << 3) (1 << 3)
11523#define IP_TG_CONFIG(1 << 2) (1 << 2)
11524#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE(1 << 0) (1 << 0)
11525#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS(2 << 0) (2 << 0)
11526#define VIDEO_MODE_BURST(3 << 0) (3 << 0)
11527
11528#define _MIPIA_EOT_DISABLE(dev_priv->mipi_mmio_base + 0xb05c) (dev_priv->mipi_mmio_base + 0xb05c)
11529#define _MIPIC_EOT_DISABLE(dev_priv->mipi_mmio_base + 0xb85c) (dev_priv->mipi_mmio_base + 0xb85c)
11530#define MIPI_EOT_DISABLE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb05c) : (dev_priv->mipi_mmio_base + 0xb85c
))) }) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb05c) : (dev_priv->mipi_mmio_base + 0xb85c
))) })
11531#define BXT_DEFEATURE_DPI_FIFO_CTR(1 << 9) (1 << 9)
11532#define BXT_DPHY_DEFEATURE_EN(1 << 8) (1 << 8)
11533#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE(1 << 7) (1 << 7)
11534#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE(1 << 6) (1 << 6)
11535#define LOW_CONTENTION_RECOVERY_DISABLE(1 << 5) (1 << 5)
11536#define HIGH_CONTENTION_RECOVERY_DISABLE(1 << 4) (1 << 4)
11537#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE(1 << 3) (1 << 3)
11538#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE(1 << 2) (1 << 2)
11539#define CLOCKSTOP(1 << 1) (1 << 1)
11540#define EOT_DISABLE(1 << 0) (1 << 0)
11541
11542#define _MIPIA_LP_BYTECLK(dev_priv->mipi_mmio_base + 0xb060) (dev_priv->mipi_mmio_base + 0xb060)
11543#define _MIPIC_LP_BYTECLK(dev_priv->mipi_mmio_base + 0xb860) (dev_priv->mipi_mmio_base + 0xb860)
11544#define MIPI_LP_BYTECLK(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb060) : (dev_priv->mipi_mmio_base + 0xb860
))) }) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb060) : (dev_priv->mipi_mmio_base + 0xb860
))) })
11545#define LP_BYTECLK_SHIFT0 0
11546#define LP_BYTECLK_MASK(0xffff << 0) (0xffff << 0)
11547
11548#define _MIPIA_TLPX_TIME_COUNT(dev_priv->mipi_mmio_base + 0xb0a4) (dev_priv->mipi_mmio_base + 0xb0a4)
11549#define _MIPIC_TLPX_TIME_COUNT(dev_priv->mipi_mmio_base + 0xb8a4) (dev_priv->mipi_mmio_base + 0xb8a4)
11550#define MIPI_TLPX_TIME_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb0a4) : (dev_priv->mipi_mmio_base + 0xb8a4
))) }) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb0a4) : (dev_priv->mipi_mmio_base + 0xb8a4
))) })
11551
11552#define _MIPIA_CLK_LANE_TIMING(dev_priv->mipi_mmio_base + 0xb098) (dev_priv->mipi_mmio_base + 0xb098)
11553#define _MIPIC_CLK_LANE_TIMING(dev_priv->mipi_mmio_base + 0xb898) (dev_priv->mipi_mmio_base + 0xb898)
11554#define MIPI_CLK_LANE_TIMING(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb098) : (dev_priv->mipi_mmio_base + 0xb898
))) }) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb098) : (dev_priv->mipi_mmio_base + 0xb898
))) })
11555
11556/* bits 31:0 */
11557#define _MIPIA_LP_GEN_DATA(dev_priv->mipi_mmio_base + 0xb064) (dev_priv->mipi_mmio_base + 0xb064)
11558#define _MIPIC_LP_GEN_DATA(dev_priv->mipi_mmio_base + 0xb864) (dev_priv->mipi_mmio_base + 0xb864)
11559#define MIPI_LP_GEN_DATA(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb064) : (dev_priv->mipi_mmio_base + 0xb864
))) }) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb064) : (dev_priv->mipi_mmio_base + 0xb864
))) })
11560
11561/* bits 31:0 */
11562#define _MIPIA_HS_GEN_DATA(dev_priv->mipi_mmio_base + 0xb068) (dev_priv->mipi_mmio_base + 0xb068)
11563#define _MIPIC_HS_GEN_DATA(dev_priv->mipi_mmio_base + 0xb868) (dev_priv->mipi_mmio_base + 0xb868)
11564#define MIPI_HS_GEN_DATA(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb068) : (dev_priv->mipi_mmio_base + 0xb868
))) }) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb068) : (dev_priv->mipi_mmio_base + 0xb868
))) })
11565
11566#define _MIPIA_LP_GEN_CTRL(dev_priv->mipi_mmio_base + 0xb06c) (dev_priv->mipi_mmio_base + 0xb06c)
11567#define _MIPIC_LP_GEN_CTRL(dev_priv->mipi_mmio_base + 0xb86c) (dev_priv->mipi_mmio_base + 0xb86c)
11568#define MIPI_LP_GEN_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb06c) : (dev_priv->mipi_mmio_base + 0xb86c
))) }) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb06c) : (dev_priv->mipi_mmio_base + 0xb86c
))) })
11569#define _MIPIA_HS_GEN_CTRL(dev_priv->mipi_mmio_base + 0xb070) (dev_priv->mipi_mmio_base + 0xb070)
11570#define _MIPIC_HS_GEN_CTRL(dev_priv->mipi_mmio_base + 0xb870) (dev_priv->mipi_mmio_base + 0xb870)
11571#define MIPI_HS_GEN_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb070) : (dev_priv->mipi_mmio_base + 0xb870
))) }) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb070) : (dev_priv->mipi_mmio_base + 0xb870
))) })
11572#define LONG_PACKET_WORD_COUNT_SHIFT8 8
11573#define LONG_PACKET_WORD_COUNT_MASK(0xffff << 8) (0xffff << 8)
11574#define SHORT_PACKET_PARAM_SHIFT8 8
11575#define SHORT_PACKET_PARAM_MASK(0xffff << 8) (0xffff << 8)
11576#define VIRTUAL_CHANNEL_SHIFT6 6
11577#define VIRTUAL_CHANNEL_MASK(3 << 6) (3 << 6)
11578#define DATA_TYPE_SHIFT0 0
11579#define DATA_TYPE_MASK(0x3f << 0) (0x3f << 0)
11580/* data type values, see include/video/mipi_display.h */
11581
11582#define _MIPIA_GEN_FIFO_STAT(dev_priv->mipi_mmio_base + 0xb074) (dev_priv->mipi_mmio_base + 0xb074)
11583#define _MIPIC_GEN_FIFO_STAT(dev_priv->mipi_mmio_base + 0xb874) (dev_priv->mipi_mmio_base + 0xb874)
11584#define MIPI_GEN_FIFO_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb074) : (dev_priv->mipi_mmio_base + 0xb874
))) }) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb074) : (dev_priv->mipi_mmio_base + 0xb874
))) })
11585#define DPI_FIFO_EMPTY(1 << 28) (1 << 28)
11586#define DBI_FIFO_EMPTY(1 << 27) (1 << 27)
11587#define LP_CTRL_FIFO_EMPTY(1 << 26) (1 << 26)
11588#define LP_CTRL_FIFO_HALF_EMPTY(1 << 25) (1 << 25)
11589#define LP_CTRL_FIFO_FULL(1 << 24) (1 << 24)
11590#define HS_CTRL_FIFO_EMPTY(1 << 18) (1 << 18)
11591#define HS_CTRL_FIFO_HALF_EMPTY(1 << 17) (1 << 17)
11592#define HS_CTRL_FIFO_FULL(1 << 16) (1 << 16)
11593#define LP_DATA_FIFO_EMPTY(1 << 10) (1 << 10)
11594#define LP_DATA_FIFO_HALF_EMPTY(1 << 9) (1 << 9)
11595#define LP_DATA_FIFO_FULL(1 << 8) (1 << 8)
11596#define HS_DATA_FIFO_EMPTY(1 << 2) (1 << 2)
11597#define HS_DATA_FIFO_HALF_EMPTY(1 << 1) (1 << 1)
11598#define HS_DATA_FIFO_FULL(1 << 0) (1 << 0)
11599
11600#define _MIPIA_HS_LS_DBI_ENABLE(dev_priv->mipi_mmio_base + 0xb078) (dev_priv->mipi_mmio_base + 0xb078)
11601#define _MIPIC_HS_LS_DBI_ENABLE(dev_priv->mipi_mmio_base + 0xb878) (dev_priv->mipi_mmio_base + 0xb878)
11602#define MIPI_HS_LP_DBI_ENABLE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb078) : (dev_priv->mipi_mmio_base + 0xb878
))) }) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb078) : (dev_priv->mipi_mmio_base + 0xb878
))) })
11603#define DBI_HS_LP_MODE_MASK(1 << 0) (1 << 0)
11604#define DBI_LP_MODE(1 << 0) (1 << 0)
11605#define DBI_HS_MODE(0 << 0) (0 << 0)
11606
11607#define _MIPIA_DPHY_PARAM(dev_priv->mipi_mmio_base + 0xb080) (dev_priv->mipi_mmio_base + 0xb080)
11608#define _MIPIC_DPHY_PARAM(dev_priv->mipi_mmio_base + 0xb880) (dev_priv->mipi_mmio_base + 0xb880)
11609#define MIPI_DPHY_PARAM(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb080) : (dev_priv->mipi_mmio_base + 0xb880
))) }) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb080) : (dev_priv->mipi_mmio_base + 0xb880
))) })
11610#define EXIT_ZERO_COUNT_SHIFT24 24
11611#define EXIT_ZERO_COUNT_MASK(0x3f << 24) (0x3f << 24)
11612#define TRAIL_COUNT_SHIFT16 16
11613#define TRAIL_COUNT_MASK(0x1f << 16) (0x1f << 16)
11614#define CLK_ZERO_COUNT_SHIFT8 8
11615#define CLK_ZERO_COUNT_MASK(0xff << 8) (0xff << 8)
11616#define PREPARE_COUNT_SHIFT0 0
11617#define PREPARE_COUNT_MASK(0x3f << 0) (0x3f << 0)
11618
11619#define _ICL_DSI_T_INIT_MASTER_00x6b088 0x6b088
11620#define _ICL_DSI_T_INIT_MASTER_10x6b888 0x6b888
11621#define ICL_DSI_T_INIT_MASTER(port)((const i915_reg_t){ .reg = (((0x6b088) + (port) * ((0x6b888)
- (0x6b088)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b088) + (port) * ((0x6b888)
- (0x6b088)))) })
11622 _ICL_DSI_T_INIT_MASTER_0,\((const i915_reg_t){ .reg = (((0x6b088) + (port) * ((0x6b888)
- (0x6b088)))) })
11623 _ICL_DSI_T_INIT_MASTER_1)((const i915_reg_t){ .reg = (((0x6b088) + (port) * ((0x6b888)
- (0x6b088)))) })
11624
11625#define _DPHY_CLK_TIMING_PARAM_00x162180 0x162180
11626#define _DPHY_CLK_TIMING_PARAM_10x6c180 0x6c180
11627#define DPHY_CLK_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x162180) + (port) * ((0x6c180
) - (0x162180)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x162180) + (port) * ((0x6c180
) - (0x162180)))) })
11628 _DPHY_CLK_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x162180) + (port) * ((0x6c180
) - (0x162180)))) })
11629 _DPHY_CLK_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x162180) + (port) * ((0x6c180
) - (0x162180)))) })
11630#define _DSI_CLK_TIMING_PARAM_00x6b080 0x6b080
11631#define _DSI_CLK_TIMING_PARAM_10x6b880 0x6b880
11632#define DSI_CLK_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x6b080) + (port) * ((0x6b880)
- (0x6b080)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b080) + (port) * ((0x6b880)
- (0x6b080)))) })
11633 _DSI_CLK_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x6b080) + (port) * ((0x6b880)
- (0x6b080)))) })
11634 _DSI_CLK_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x6b080) + (port) * ((0x6b880)
- (0x6b080)))) })
11635#define CLK_PREPARE_OVERRIDE(1 << 31) (1 << 31)
11636#define CLK_PREPARE(x)((x) << 28) ((x) << 28)
11637#define CLK_PREPARE_MASK(0x7 << 28) (0x7 << 28)
11638#define CLK_PREPARE_SHIFT28 28
11639#define CLK_ZERO_OVERRIDE(1 << 27) (1 << 27)
11640#define CLK_ZERO(x)((x) << 20) ((x) << 20)
11641#define CLK_ZERO_MASK(0xf << 20) (0xf << 20)
11642#define CLK_ZERO_SHIFT20 20
11643#define CLK_PRE_OVERRIDE(1 << 19) (1 << 19)
11644#define CLK_PRE(x)((x) << 16) ((x) << 16)
11645#define CLK_PRE_MASK(0x3 << 16) (0x3 << 16)
11646#define CLK_PRE_SHIFT16 16
11647#define CLK_POST_OVERRIDE(1 << 15) (1 << 15)
11648#define CLK_POST(x)((x) << 8) ((x) << 8)
11649#define CLK_POST_MASK(0x7 << 8) (0x7 << 8)
11650#define CLK_POST_SHIFT8 8
11651#define CLK_TRAIL_OVERRIDE(1 << 7) (1 << 7)
11652#define CLK_TRAIL(x)((x) << 0) ((x) << 0)
11653#define CLK_TRAIL_MASK(0xf << 0) (0xf << 0)
11654#define CLK_TRAIL_SHIFT0 0
11655
11656#define _DPHY_DATA_TIMING_PARAM_00x162184 0x162184
11657#define _DPHY_DATA_TIMING_PARAM_10x6c184 0x6c184
11658#define DPHY_DATA_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x162184) + (port) * ((0x6c184
) - (0x162184)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x162184) + (port) * ((0x6c184
) - (0x162184)))) })
11659 _DPHY_DATA_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x162184) + (port) * ((0x6c184
) - (0x162184)))) })
11660 _DPHY_DATA_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x162184) + (port) * ((0x6c184
) - (0x162184)))) })
11661#define _DSI_DATA_TIMING_PARAM_00x6B084 0x6B084
11662#define _DSI_DATA_TIMING_PARAM_10x6B884 0x6B884
11663#define DSI_DATA_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x6B084) + (port) * ((0x6B884)
- (0x6B084)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6B084) + (port) * ((0x6B884)
- (0x6B084)))) })
11664 _DSI_DATA_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x6B084) + (port) * ((0x6B884)
- (0x6B084)))) })
11665 _DSI_DATA_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x6B084) + (port) * ((0x6B884)
- (0x6B084)))) })
11666#define HS_PREPARE_OVERRIDE(1 << 31) (1 << 31)
11667#define HS_PREPARE(x)((x) << 24) ((x) << 24)
11668#define HS_PREPARE_MASK(0x7 << 24) (0x7 << 24)
11669#define HS_PREPARE_SHIFT24 24
11670#define HS_ZERO_OVERRIDE(1 << 23) (1 << 23)
11671#define HS_ZERO(x)((x) << 16) ((x) << 16)
11672#define HS_ZERO_MASK(0xf << 16) (0xf << 16)
11673#define HS_ZERO_SHIFT16 16
11674#define HS_TRAIL_OVERRIDE(1 << 15) (1 << 15)
11675#define HS_TRAIL(x)((x) << 8) ((x) << 8)
11676#define HS_TRAIL_MASK(0x7 << 8) (0x7 << 8)
11677#define HS_TRAIL_SHIFT8 8
11678#define HS_EXIT_OVERRIDE(1 << 7) (1 << 7)
11679#define HS_EXIT(x)((x) << 0) ((x) << 0)
11680#define HS_EXIT_MASK(0x7 << 0) (0x7 << 0)
11681#define HS_EXIT_SHIFT0 0
11682
11683#define _DPHY_TA_TIMING_PARAM_00x162188 0x162188
11684#define _DPHY_TA_TIMING_PARAM_10x6c188 0x6c188
11685#define DPHY_TA_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x162188) + (port) * ((0x6c188
) - (0x162188)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x162188) + (port) * ((0x6c188
) - (0x162188)))) })
11686 _DPHY_TA_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x162188) + (port) * ((0x6c188
) - (0x162188)))) })
11687 _DPHY_TA_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x162188) + (port) * ((0x6c188
) - (0x162188)))) })
11688#define _DSI_TA_TIMING_PARAM_00x6b098 0x6b098
11689#define _DSI_TA_TIMING_PARAM_10x6b898 0x6b898
11690#define DSI_TA_TIMING_PARAM(port)((const i915_reg_t){ .reg = (((0x6b098) + (port) * ((0x6b898)
- (0x6b098)))) }) _MMIO_PORT(port, \((const i915_reg_t){ .reg = (((0x6b098) + (port) * ((0x6b898)
- (0x6b098)))) })
11691 _DSI_TA_TIMING_PARAM_0,\((const i915_reg_t){ .reg = (((0x6b098) + (port) * ((0x6b898)
- (0x6b098)))) })
11692 _DSI_TA_TIMING_PARAM_1)((const i915_reg_t){ .reg = (((0x6b098) + (port) * ((0x6b898)
- (0x6b098)))) })
11693#define TA_SURE_OVERRIDE(1 << 31) (1 << 31)
11694#define TA_SURE(x)((x) << 16) ((x) << 16)
11695#define TA_SURE_MASK(0x1f << 16) (0x1f << 16)
11696#define TA_SURE_SHIFT16 16
11697#define TA_GO_OVERRIDE(1 << 15) (1 << 15)
11698#define TA_GO(x)((x) << 8) ((x) << 8)
11699#define TA_GO_MASK(0xf << 8) (0xf << 8)
11700#define TA_GO_SHIFT8 8
11701#define TA_GET_OVERRIDE(1 << 7) (1 << 7)
11702#define TA_GET(x)((x) << 0) ((x) << 0)
11703#define TA_GET_MASK(0xf << 0) (0xf << 0)
11704#define TA_GET_SHIFT0 0
11705
11706/* DSI transcoder configuration */
11707#define _DSI_TRANS_FUNC_CONF_00x6b030 0x6b030
11708#define _DSI_TRANS_FUNC_CONF_10x6b830 0x6b830
11709#define DSI_TRANS_FUNC_CONF(tc)((const i915_reg_t){ .reg = (((0x6b030) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b830) - (0x6b030)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b030) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b830) - (0x6b030)))) })
11710 _DSI_TRANS_FUNC_CONF_0,\((const i915_reg_t){ .reg = (((0x6b030) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b830) - (0x6b030)))) })
11711 _DSI_TRANS_FUNC_CONF_1)((const i915_reg_t){ .reg = (((0x6b030) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b830) - (0x6b030)))) })
11712#define OP_MODE_MASK(0x3 << 28) (0x3 << 28)
11713#define OP_MODE_SHIFT28 28
11714#define CMD_MODE_NO_GATE(0x0 << 28) (0x0 << 28)
11715#define CMD_MODE_TE_GATE(0x1 << 28) (0x1 << 28)
11716#define VIDEO_MODE_SYNC_EVENT(0x2 << 28) (0x2 << 28)
11717#define VIDEO_MODE_SYNC_PULSE(0x3 << 28) (0x3 << 28)
11718#define TE_SOURCE_GPIO(1 << 27) (1 << 27)
11719#define LINK_READY(1 << 20) (1 << 20)
11720#define PIX_FMT_MASK(0x3 << 16) (0x3 << 16)
11721#define PIX_FMT_SHIFT16 16
11722#define PIX_FMT_RGB565(0x0 << 16) (0x0 << 16)
11723#define PIX_FMT_RGB666_PACKED(0x1 << 16) (0x1 << 16)
11724#define PIX_FMT_RGB666_LOOSE(0x2 << 16) (0x2 << 16)
11725#define PIX_FMT_RGB888(0x3 << 16) (0x3 << 16)
11726#define PIX_FMT_RGB101010(0x4 << 16) (0x4 << 16)
11727#define PIX_FMT_RGB121212(0x5 << 16) (0x5 << 16)
11728#define PIX_FMT_COMPRESSED(0x6 << 16) (0x6 << 16)
11729#define BGR_TRANSMISSION(1 << 15) (1 << 15)
11730#define PIX_VIRT_CHAN(x)((x) << 12) ((x) << 12)
11731#define PIX_VIRT_CHAN_MASK(0x3 << 12) (0x3 << 12)
11732#define PIX_VIRT_CHAN_SHIFT12 12
11733#define PIX_BUF_THRESHOLD_MASK(0x3 << 10) (0x3 << 10)
11734#define PIX_BUF_THRESHOLD_SHIFT10 10
11735#define PIX_BUF_THRESHOLD_1_4(0x0 << 10) (0x0 << 10)
11736#define PIX_BUF_THRESHOLD_1_2(0x1 << 10) (0x1 << 10)
11737#define PIX_BUF_THRESHOLD_3_4(0x2 << 10) (0x2 << 10)
11738#define PIX_BUF_THRESHOLD_FULL(0x3 << 10) (0x3 << 10)
11739#define CONTINUOUS_CLK_MASK(0x3 << 8) (0x3 << 8)
11740#define CONTINUOUS_CLK_SHIFT8 8
11741#define CLK_ENTER_LP_AFTER_DATA(0x0 << 8) (0x0 << 8)
11742#define CLK_HS_OR_LP(0x2 << 8) (0x2 << 8)
11743#define CLK_HS_CONTINUOUS(0x3 << 8) (0x3 << 8)
11744#define LINK_CALIBRATION_MASK(0x3 << 4) (0x3 << 4)
11745#define LINK_CALIBRATION_SHIFT4 4
11746#define CALIBRATION_DISABLED(0x0 << 4) (0x0 << 4)
11747#define CALIBRATION_ENABLED_INITIAL_ONLY(0x2 << 4) (0x2 << 4)
11748#define CALIBRATION_ENABLED_INITIAL_PERIODIC(0x3 << 4) (0x3 << 4)
11749#define BLANKING_PACKET_ENABLE(1 << 2) (1 << 2)
11750#define S3D_ORIENTATION_LANDSCAPE(1 << 1) (1 << 1)
11751#define EOTP_DISABLED(1 << 0) (1 << 0)
11752
11753#define _DSI_CMD_RXCTL_00x6b0d4 0x6b0d4
11754#define _DSI_CMD_RXCTL_10x6b8d4 0x6b8d4
11755#define DSI_CMD_RXCTL(tc)((const i915_reg_t){ .reg = (((0x6b0d4) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d4) - (0x6b0d4)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b0d4) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d4) - (0x6b0d4)))) })
11756 _DSI_CMD_RXCTL_0,\((const i915_reg_t){ .reg = (((0x6b0d4) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d4) - (0x6b0d4)))) })
11757 _DSI_CMD_RXCTL_1)((const i915_reg_t){ .reg = (((0x6b0d4) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d4) - (0x6b0d4)))) })
11758#define READ_UNLOADS_DW(1 << 16) (1 << 16)
11759#define RECEIVED_UNASSIGNED_TRIGGER(1 << 15) (1 << 15)
11760#define RECEIVED_ACKNOWLEDGE_TRIGGER(1 << 14) (1 << 14)
11761#define RECEIVED_TEAR_EFFECT_TRIGGER(1 << 13) (1 << 13)
11762#define RECEIVED_RESET_TRIGGER(1 << 12) (1 << 12)
11763#define RECEIVED_PAYLOAD_WAS_LOST(1 << 11) (1 << 11)
11764#define RECEIVED_CRC_WAS_LOST(1 << 10) (1 << 10)
11765#define NUMBER_RX_PLOAD_DW_MASK(0xff << 0) (0xff << 0)
11766#define NUMBER_RX_PLOAD_DW_SHIFT0 0
11767
11768#define _DSI_CMD_TXCTL_00x6b0d0 0x6b0d0
11769#define _DSI_CMD_TXCTL_10x6b8d0 0x6b8d0
11770#define DSI_CMD_TXCTL(tc)((const i915_reg_t){ .reg = (((0x6b0d0) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d0) - (0x6b0d0)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b0d0) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d0) - (0x6b0d0)))) })
11771 _DSI_CMD_TXCTL_0,\((const i915_reg_t){ .reg = (((0x6b0d0) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d0) - (0x6b0d0)))) })
11772 _DSI_CMD_TXCTL_1)((const i915_reg_t){ .reg = (((0x6b0d0) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d0) - (0x6b0d0)))) })
11773#define KEEP_LINK_IN_HS(1 << 24) (1 << 24)
11774#define FREE_HEADER_CREDIT_MASK(0x1f << 8) (0x1f << 8)
11775#define FREE_HEADER_CREDIT_SHIFT0x8 0x8
11776#define FREE_PLOAD_CREDIT_MASK(0xff << 0) (0xff << 0)
11777#define FREE_PLOAD_CREDIT_SHIFT0 0
11778#define MAX_HEADER_CREDIT0x10 0x10
11779#define MAX_PLOAD_CREDIT0x40 0x40
11780
11781#define _DSI_CMD_TXHDR_00x6b100 0x6b100
11782#define _DSI_CMD_TXHDR_10x6b900 0x6b900
11783#define DSI_CMD_TXHDR(tc)((const i915_reg_t){ .reg = (((0x6b100) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b900) - (0x6b100)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b100) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b900) - (0x6b100)))) })
11784 _DSI_CMD_TXHDR_0,\((const i915_reg_t){ .reg = (((0x6b100) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b900) - (0x6b100)))) })
11785 _DSI_CMD_TXHDR_1)((const i915_reg_t){ .reg = (((0x6b100) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b900) - (0x6b100)))) })
11786#define PAYLOAD_PRESENT(1 << 31) (1 << 31)
11787#define LP_DATA_TRANSFER(1 << 30) (1 << 30)
11788#define VBLANK_FENCE(1 << 29) (1 << 29)
11789#define PARAM_WC_MASK(0xffff << 8) (0xffff << 8)
11790#define PARAM_WC_LOWER_SHIFT8 8
11791#define PARAM_WC_UPPER_SHIFT16 16
11792#define VC_MASK(0x3 << 6) (0x3 << 6)
11793#define VC_SHIFT6 6
11794#define DT_MASK(0x3f << 0) (0x3f << 0)
11795#define DT_SHIFT0 0
11796
11797#define _DSI_CMD_TXPYLD_00x6b104 0x6b104
11798#define _DSI_CMD_TXPYLD_10x6b904 0x6b904
11799#define DSI_CMD_TXPYLD(tc)((const i915_reg_t){ .reg = (((0x6b104) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b904) - (0x6b104)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b104) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b904) - (0x6b104)))) })
11800 _DSI_CMD_TXPYLD_0,\((const i915_reg_t){ .reg = (((0x6b104) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b904) - (0x6b104)))) })
11801 _DSI_CMD_TXPYLD_1)((const i915_reg_t){ .reg = (((0x6b104) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b904) - (0x6b104)))) })
11802
11803#define _DSI_LP_MSG_00x6b0d8 0x6b0d8
11804#define _DSI_LP_MSG_10x6b8d8 0x6b8d8
11805#define DSI_LP_MSG(tc)((const i915_reg_t){ .reg = (((0x6b0d8) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d8) - (0x6b0d8)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b0d8) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d8) - (0x6b0d8)))) })
11806 _DSI_LP_MSG_0,\((const i915_reg_t){ .reg = (((0x6b0d8) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d8) - (0x6b0d8)))) })
11807 _DSI_LP_MSG_1)((const i915_reg_t){ .reg = (((0x6b0d8) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b8d8) - (0x6b0d8)))) })
11808#define LPTX_IN_PROGRESS(1 << 17) (1 << 17)
11809#define LINK_IN_ULPS(1 << 16) (1 << 16)
11810#define LINK_ULPS_TYPE_LP11(1 << 8) (1 << 8)
11811#define LINK_ENTER_ULPS(1 << 0) (1 << 0)
11812
11813/* DSI timeout registers */
11814#define _DSI_HSTX_TO_00x6b044 0x6b044
11815#define _DSI_HSTX_TO_10x6b844 0x6b844
11816#define DSI_HSTX_TO(tc)((const i915_reg_t){ .reg = (((0x6b044) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b844) - (0x6b044)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b044) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b844) - (0x6b044)))) })
11817 _DSI_HSTX_TO_0,\((const i915_reg_t){ .reg = (((0x6b044) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b844) - (0x6b044)))) })
11818 _DSI_HSTX_TO_1)((const i915_reg_t){ .reg = (((0x6b044) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b844) - (0x6b044)))) })
11819#define HSTX_TIMEOUT_VALUE_MASK(0xffff << 16) (0xffff << 16)
11820#define HSTX_TIMEOUT_VALUE_SHIFT16 16
11821#define HSTX_TIMEOUT_VALUE(x)((x) << 16) ((x) << 16)
11822#define HSTX_TIMED_OUT(1 << 0) (1 << 0)
11823
11824#define _DSI_LPRX_HOST_TO_00x6b048 0x6b048
11825#define _DSI_LPRX_HOST_TO_10x6b848 0x6b848
11826#define DSI_LPRX_HOST_TO(tc)((const i915_reg_t){ .reg = (((0x6b048) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b848) - (0x6b048)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b048) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b848) - (0x6b048)))) })
11827 _DSI_LPRX_HOST_TO_0,\((const i915_reg_t){ .reg = (((0x6b048) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b848) - (0x6b048)))) })
11828 _DSI_LPRX_HOST_TO_1)((const i915_reg_t){ .reg = (((0x6b048) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b848) - (0x6b048)))) })
11829#define LPRX_TIMED_OUT(1 << 16) (1 << 16)
11830#define LPRX_TIMEOUT_VALUE_MASK(0xffff << 0) (0xffff << 0)
11831#define LPRX_TIMEOUT_VALUE_SHIFT0 0
11832#define LPRX_TIMEOUT_VALUE(x)((x) << 0) ((x) << 0)
11833
11834#define _DSI_PWAIT_TO_00x6b040 0x6b040
11835#define _DSI_PWAIT_TO_10x6b840 0x6b840
11836#define DSI_PWAIT_TO(tc)((const i915_reg_t){ .reg = (((0x6b040) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b840) - (0x6b040)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b040) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b840) - (0x6b040)))) })
11837 _DSI_PWAIT_TO_0,\((const i915_reg_t){ .reg = (((0x6b040) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b840) - (0x6b040)))) })
11838 _DSI_PWAIT_TO_1)((const i915_reg_t){ .reg = (((0x6b040) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b840) - (0x6b040)))) })
11839#define PRESET_TIMEOUT_VALUE_MASK(0xffff << 16) (0xffff << 16)
11840#define PRESET_TIMEOUT_VALUE_SHIFT16 16
11841#define PRESET_TIMEOUT_VALUE(x)((x) << 16) ((x) << 16)
11842#define PRESPONSE_TIMEOUT_VALUE_MASK(0xffff << 0) (0xffff << 0)
11843#define PRESPONSE_TIMEOUT_VALUE_SHIFT0 0
11844#define PRESPONSE_TIMEOUT_VALUE(x)((x) << 0) ((x) << 0)
11845
11846#define _DSI_TA_TO_00x6b04c 0x6b04c
11847#define _DSI_TA_TO_10x6b84c 0x6b84c
11848#define DSI_TA_TO(tc)((const i915_reg_t){ .reg = (((0x6b04c) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b84c) - (0x6b04c)))) }) _MMIO_DSI(tc, \((const i915_reg_t){ .reg = (((0x6b04c) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b84c) - (0x6b04c)))) })
11849 _DSI_TA_TO_0,\((const i915_reg_t){ .reg = (((0x6b04c) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b84c) - (0x6b04c)))) })
11850 _DSI_TA_TO_1)((const i915_reg_t){ .reg = (((0x6b04c) + ((tc) - TRANSCODER_DSI_0
) * ((0x6b84c) - (0x6b04c)))) })
11851#define TA_TIMED_OUT(1 << 16) (1 << 16)
11852#define TA_TIMEOUT_VALUE_MASK(0xffff << 0) (0xffff << 0)
11853#define TA_TIMEOUT_VALUE_SHIFT0 0
11854#define TA_TIMEOUT_VALUE(x)((x) << 0) ((x) << 0)
11855
11856/* bits 31:0 */
11857#define _MIPIA_DBI_BW_CTRL(dev_priv->mipi_mmio_base + 0xb084) (dev_priv->mipi_mmio_base + 0xb084)
11858#define _MIPIC_DBI_BW_CTRL(dev_priv->mipi_mmio_base + 0xb884) (dev_priv->mipi_mmio_base + 0xb884)
11859#define MIPI_DBI_BW_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb084) : (dev_priv->mipi_mmio_base + 0xb884
))) }) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb084) : (dev_priv->mipi_mmio_base + 0xb884
))) })
11860
11861#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT(dev_priv->mipi_mmio_base + 0xb088) (dev_priv->mipi_mmio_base + 0xb088)
11862#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT(dev_priv->mipi_mmio_base + 0xb888) (dev_priv->mipi_mmio_base + 0xb888)
11863#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb088) : (dev_priv->mipi_mmio_base + 0xb888
))) }) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb088) : (dev_priv->mipi_mmio_base + 0xb888
))) })
11864#define LP_HS_SSW_CNT_SHIFT16 16
11865#define LP_HS_SSW_CNT_MASK(0xffff << 16) (0xffff << 16)
11866#define HS_LP_PWR_SW_CNT_SHIFT0 0
11867#define HS_LP_PWR_SW_CNT_MASK(0xffff << 0) (0xffff << 0)
11868
11869#define _MIPIA_STOP_STATE_STALL(dev_priv->mipi_mmio_base + 0xb08c) (dev_priv->mipi_mmio_base + 0xb08c)
11870#define _MIPIC_STOP_STATE_STALL(dev_priv->mipi_mmio_base + 0xb88c) (dev_priv->mipi_mmio_base + 0xb88c)
11871#define MIPI_STOP_STATE_STALL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb08c) : (dev_priv->mipi_mmio_base + 0xb88c
))) }) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb08c) : (dev_priv->mipi_mmio_base + 0xb88c
))) })
11872#define STOP_STATE_STALL_COUNTER_SHIFT0 0
11873#define STOP_STATE_STALL_COUNTER_MASK(0xff << 0) (0xff << 0)
11874
11875#define _MIPIA_INTR_STAT_REG_1(dev_priv->mipi_mmio_base + 0xb090) (dev_priv->mipi_mmio_base + 0xb090)
11876#define _MIPIC_INTR_STAT_REG_1(dev_priv->mipi_mmio_base + 0xb890) (dev_priv->mipi_mmio_base + 0xb890)
11877#define MIPI_INTR_STAT_REG_1(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb090) : (dev_priv->mipi_mmio_base + 0xb890
))) }) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb090) : (dev_priv->mipi_mmio_base + 0xb890
))) })
11878#define _MIPIA_INTR_EN_REG_1(dev_priv->mipi_mmio_base + 0xb094) (dev_priv->mipi_mmio_base + 0xb094)
11879#define _MIPIC_INTR_EN_REG_1(dev_priv->mipi_mmio_base + 0xb894) (dev_priv->mipi_mmio_base + 0xb894)
11880#define MIPI_INTR_EN_REG_1(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb094) : (dev_priv->mipi_mmio_base + 0xb894
))) }) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb094) : (dev_priv->mipi_mmio_base + 0xb894
))) })
11881#define RX_CONTENTION_DETECTED(1 << 0) (1 << 0)
11882
11883/* XXX: only pipe A ?!? */
11884#define MIPIA_DBI_TYPEC_CTRL(dev_priv->mipi_mmio_base + 0xb100) (dev_priv->mipi_mmio_base + 0xb100)
11885#define DBI_TYPEC_ENABLE(1 << 31) (1 << 31)
11886#define DBI_TYPEC_WIP(1 << 30) (1 << 30)
11887#define DBI_TYPEC_OPTION_SHIFT28 28
11888#define DBI_TYPEC_OPTION_MASK(3 << 28) (3 << 28)
11889#define DBI_TYPEC_FREQ_SHIFT24 24
11890#define DBI_TYPEC_FREQ_MASK(0xf << 24) (0xf << 24)
11891#define DBI_TYPEC_OVERRIDE(1 << 8) (1 << 8)
11892#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT0 0
11893#define DBI_TYPEC_OVERRIDE_COUNTER_MASK(0xff << 0) (0xff << 0)
11894
11895
11896/* MIPI adapter registers */
11897
11898#define _MIPIA_CTRL(dev_priv->mipi_mmio_base + 0xb104) (dev_priv->mipi_mmio_base + 0xb104)
11899#define _MIPIC_CTRL(dev_priv->mipi_mmio_base + 0xb904) (dev_priv->mipi_mmio_base + 0xb904)
11900#define MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb104) : (dev_priv->mipi_mmio_base + 0xb904
))) }) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb104) : (dev_priv->mipi_mmio_base + 0xb904
))) })
11901#define ESCAPE_CLOCK_DIVIDER_SHIFT5 5 /* A only */
11902#define ESCAPE_CLOCK_DIVIDER_MASK(3 << 5) (3 << 5)
11903#define ESCAPE_CLOCK_DIVIDER_1(0 << 5) (0 << 5)
11904#define ESCAPE_CLOCK_DIVIDER_2(1 << 5) (1 << 5)
11905#define ESCAPE_CLOCK_DIVIDER_4(2 << 5) (2 << 5)
11906#define READ_REQUEST_PRIORITY_SHIFT3 3
11907#define READ_REQUEST_PRIORITY_MASK(3 << 3) (3 << 3)
11908#define READ_REQUEST_PRIORITY_LOW(0 << 3) (0 << 3)
11909#define READ_REQUEST_PRIORITY_HIGH(3 << 3) (3 << 3)
11910#define RGB_FLIP_TO_BGR(1 << 2) (1 << 2)
11911
11912#define BXT_PIPE_SELECT_SHIFT7 7
11913#define BXT_PIPE_SELECT_MASK(7 << 7) (7 << 7)
11914#define BXT_PIPE_SELECT(pipe)((pipe) << 7) ((pipe) << 7)
11915#define GLK_PHY_STATUS_PORT_READY(1 << 31) (1 << 31) /* RO */
11916#define GLK_ULPS_NOT_ACTIVE(1 << 30) (1 << 30) /* RO */
11917#define GLK_MIPIIO_RESET_RELEASED(1 << 28) (1 << 28)
11918#define GLK_CLOCK_LANE_STOP_STATE(1 << 27) (1 << 27) /* RO */
11919#define GLK_DATA_LANE_STOP_STATE(1 << 26) (1 << 26) /* RO */
11920#define GLK_LP_WAKE(1 << 22) (1 << 22)
11921#define GLK_LP11_LOW_PWR_MODE(1 << 21) (1 << 21)
11922#define GLK_LP00_LOW_PWR_MODE(1 << 20) (1 << 20)
11923#define GLK_FIREWALL_ENABLE(1 << 16) (1 << 16)
11924#define BXT_PIXEL_OVERLAP_CNT_MASK(0xf << 10) (0xf << 10)
11925#define BXT_PIXEL_OVERLAP_CNT_SHIFT10 10
11926#define BXT_DSC_ENABLE(1 << 3) (1 << 3)
11927#define BXT_RGB_FLIP(1 << 2) (1 << 2)
11928#define GLK_MIPIIO_PORT_POWERED(1 << 1) (1 << 1) /* RO */
11929#define GLK_MIPIIO_ENABLE(1 << 0) (1 << 0)
11930
11931#define _MIPIA_DATA_ADDRESS(dev_priv->mipi_mmio_base + 0xb108) (dev_priv->mipi_mmio_base + 0xb108)
11932#define _MIPIC_DATA_ADDRESS(dev_priv->mipi_mmio_base + 0xb908) (dev_priv->mipi_mmio_base + 0xb908)
11933#define MIPI_DATA_ADDRESS(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb108) : (dev_priv->mipi_mmio_base + 0xb908
))) }) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb108) : (dev_priv->mipi_mmio_base + 0xb908
))) })
11934#define DATA_MEM_ADDRESS_SHIFT5 5
11935#define DATA_MEM_ADDRESS_MASK(0x7ffffff << 5) (0x7ffffff << 5)
11936#define DATA_VALID(1 << 0) (1 << 0)
11937
11938#define _MIPIA_DATA_LENGTH(dev_priv->mipi_mmio_base + 0xb10c) (dev_priv->mipi_mmio_base + 0xb10c)
11939#define _MIPIC_DATA_LENGTH(dev_priv->mipi_mmio_base + 0xb90c) (dev_priv->mipi_mmio_base + 0xb90c)
11940#define MIPI_DATA_LENGTH(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb10c) : (dev_priv->mipi_mmio_base + 0xb90c
))) }) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb10c) : (dev_priv->mipi_mmio_base + 0xb90c
))) })
11941#define DATA_LENGTH_SHIFT0 0
11942#define DATA_LENGTH_MASK(0xfffff << 0) (0xfffff << 0)
11943
11944#define _MIPIA_COMMAND_ADDRESS(dev_priv->mipi_mmio_base + 0xb110) (dev_priv->mipi_mmio_base + 0xb110)
11945#define _MIPIC_COMMAND_ADDRESS(dev_priv->mipi_mmio_base + 0xb910) (dev_priv->mipi_mmio_base + 0xb910)
11946#define MIPI_COMMAND_ADDRESS(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb110) : (dev_priv->mipi_mmio_base + 0xb910
))) }) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb110) : (dev_priv->mipi_mmio_base + 0xb910
))) })
11947#define COMMAND_MEM_ADDRESS_SHIFT5 5
11948#define COMMAND_MEM_ADDRESS_MASK(0x7ffffff << 5) (0x7ffffff << 5)
11949#define AUTO_PWG_ENABLE(1 << 2) (1 << 2)
11950#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING(1 << 1) (1 << 1)
11951#define COMMAND_VALID(1 << 0) (1 << 0)
11952
11953#define _MIPIA_COMMAND_LENGTH(dev_priv->mipi_mmio_base + 0xb114) (dev_priv->mipi_mmio_base + 0xb114)
11954#define _MIPIC_COMMAND_LENGTH(dev_priv->mipi_mmio_base + 0xb914) (dev_priv->mipi_mmio_base + 0xb914)
11955#define MIPI_COMMAND_LENGTH(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb114) : (dev_priv->mipi_mmio_base + 0xb914
))) }) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb114) : (dev_priv->mipi_mmio_base + 0xb914
))) })
11956#define COMMAND_LENGTH_SHIFT(n)(8 * (n)) (8 * (n)) /* n: 0...3 */
11957#define COMMAND_LENGTH_MASK(n)(0xff << (8 * (n))) (0xff << (8 * (n)))
11958
11959#define _MIPIA_READ_DATA_RETURN0(dev_priv->mipi_mmio_base + 0xb118) (dev_priv->mipi_mmio_base + 0xb118)
11960#define _MIPIC_READ_DATA_RETURN0(dev_priv->mipi_mmio_base + 0xb918) (dev_priv->mipi_mmio_base + 0xb918)
11961#define MIPI_READ_DATA_RETURN(port, n)((const i915_reg_t){ .reg = (_MIPI(port, (dev_priv->mipi_mmio_base
+ 0xb118), (dev_priv->mipi_mmio_base + 0xb918)) + 4 * (n)
) }) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n))((const i915_reg_t){ .reg = (_MIPI(port, (dev_priv->mipi_mmio_base
+ 0xb118), (dev_priv->mipi_mmio_base + 0xb918)) + 4 * (n)
) }) /* n: 0...7 */
11962
11963#define _MIPIA_READ_DATA_VALID(dev_priv->mipi_mmio_base + 0xb138) (dev_priv->mipi_mmio_base + 0xb138)
11964#define _MIPIC_READ_DATA_VALID(dev_priv->mipi_mmio_base + 0xb938) (dev_priv->mipi_mmio_base + 0xb938)
11965#define MIPI_READ_DATA_VALID(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb138) : (dev_priv->mipi_mmio_base + 0xb938
))) }) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv->
mipi_mmio_base + 0xb138) : (dev_priv->mipi_mmio_base + 0xb938
))) })
11966#define READ_DATA_VALID(n)(1 << (n)) (1 << (n))
11967
11968/* MOCS (Memory Object Control State) registers */
11969#define GEN9_LNCFCMOCS(i)((const i915_reg_t){ .reg = (0xb020 + (i) * 4) }) _MMIO(0xb020 + (i) * 4)((const i915_reg_t){ .reg = (0xb020 + (i) * 4) }) /* L3 Cache Control */
11970
11971#define __GEN9_RCS0_MOCS00xc800 0xc800
11972#define GEN9_GFX_MOCS(i)((const i915_reg_t){ .reg = (0xc800 + (i) * 4) }) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0xc800 + (i) * 4) })
11973#define __GEN9_VCS0_MOCS00xc900 0xc900
11974#define GEN9_MFX0_MOCS(i)((const i915_reg_t){ .reg = (0xc900 + (i) * 4) }) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0xc900 + (i) * 4) })
11975#define __GEN9_VCS1_MOCS00xca00 0xca00
11976#define GEN9_MFX1_MOCS(i)((const i915_reg_t){ .reg = (0xca00 + (i) * 4) }) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0xca00 + (i) * 4) })
11977#define __GEN9_VECS0_MOCS00xcb00 0xcb00
11978#define GEN9_VEBOX_MOCS(i)((const i915_reg_t){ .reg = (0xcb00 + (i) * 4) }) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0xcb00 + (i) * 4) })
11979#define __GEN9_BCS0_MOCS00xcc00 0xcc00
11980#define GEN9_BLT_MOCS(i)((const i915_reg_t){ .reg = (0xcc00 + (i) * 4) }) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0xcc00 + (i) * 4) })
11981#define __GEN11_VCS2_MOCS00x10000 0x10000
11982#define GEN11_MFX2_MOCS(i)((const i915_reg_t){ .reg = (0x10000 + (i) * 4) }) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)((const i915_reg_t){ .reg = (0x10000 + (i) * 4) })
11983
11984#define GEN10_SCRATCH_LNCF2((const i915_reg_t){ .reg = (0xb0a0) }) _MMIO(0xb0a0)((const i915_reg_t){ .reg = (0xb0a0) })
11985#define PMFLUSHDONE_LNICRSDROP(1 << 20) (1 << 20)
11986#define PMFLUSH_GAPL3UNBLOCK(1 << 21) (1 << 21)
11987#define PMFLUSHDONE_LNEBLK(1 << 22) (1 << 22)
11988
11989#define GEN12_GLOBAL_MOCS(i)((const i915_reg_t){ .reg = (0x4000 + (i) * 4) }) _MMIO(0x4000 + (i) * 4)((const i915_reg_t){ .reg = (0x4000 + (i) * 4) }) /* Global MOCS regs */
11990
11991/* gamt regs */
11992#define GEN8_L3_LRA_1_GPGPU((const i915_reg_t){ .reg = (0x4dd4) }) _MMIO(0x4dd4)((const i915_reg_t){ .reg = (0x4dd4) })
11993#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW0x67F1427F 0x67F1427F /* max/min for LRA1/2 */
11994#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV0x5FF101FF 0x5FF101FF /* max/min for LRA1/2 */
11995#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL0x67F1427F 0x67F1427F /* " " */
11996#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT0x5FF101FF 0x5FF101FF /* " " */
11997
11998#define MMCD_MISC_CTRL((const i915_reg_t){ .reg = (0x4ddc) }) _MMIO(0x4ddc)((const i915_reg_t){ .reg = (0x4ddc) }) /* skl+ */
11999#define MMCD_PCLA(1 << 31) (1 << 31)
12000#define MMCD_HOTSPOT_EN(1 << 27) (1 << 27)
12001
12002#define _ICL_PHY_MISC_A0x64C00 0x64C00
12003#define _ICL_PHY_MISC_B0x64C04 0x64C04
12004#define ICL_PHY_MISC(port)((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C04)
- (0x64C00)))) }) _MMIO_PORT(port, _ICL_PHY_MISC_A, \((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C04)
- (0x64C00)))) })
12005 _ICL_PHY_MISC_B)((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C04)
- (0x64C00)))) })
12006#define ICL_PHY_MISC_MUX_DDID(1 << 28) (1 << 28)
12007#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN(1 << 23) (1 << 23)
12008
12009/* Icelake Display Stream Compression Registers */
12010#define DSCA_PICTURE_PARAMETER_SET_0((const i915_reg_t){ .reg = (0x6B200) }) _MMIO(0x6B200)((const i915_reg_t){ .reg = (0x6B200) })
12011#define DSCC_PICTURE_PARAMETER_SET_0((const i915_reg_t){ .reg = (0x6BA00) }) _MMIO(0x6BA00)((const i915_reg_t){ .reg = (0x6BA00) })
12012#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB0x78270 0x78270
12013#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB0x78370 0x78370
12014#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC0x78470 0x78470
12015#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC0x78570 0x78570
12016#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)((const i915_reg_t){ .reg = (((0x78270) + ((pipe) - PIPE_B) *
((0x78470) - (0x78270)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78270) + ((pipe) - PIPE_B) *
((0x78470) - (0x78270)))) })
12017 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \((const i915_reg_t){ .reg = (((0x78270) + ((pipe) - PIPE_B) *
((0x78470) - (0x78270)))) })
12018 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)((const i915_reg_t){ .reg = (((0x78270) + ((pipe) - PIPE_B) *
((0x78470) - (0x78270)))) })
12019#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)((const i915_reg_t){ .reg = (((0x78370) + ((pipe) - PIPE_B) *
((0x78570) - (0x78370)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78370) + ((pipe) - PIPE_B) *
((0x78570) - (0x78370)))) })
12020 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \((const i915_reg_t){ .reg = (((0x78370) + ((pipe) - PIPE_B) *
((0x78570) - (0x78370)))) })
12021 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)((const i915_reg_t){ .reg = (((0x78370) + ((pipe) - PIPE_B) *
((0x78570) - (0x78370)))) })
12022#define DSC_VBR_ENABLE(1 << 19) (1 << 19)
12023#define DSC_422_ENABLE(1 << 18) (1 << 18)
12024#define DSC_COLOR_SPACE_CONVERSION(1 << 17) (1 << 17)
12025#define DSC_BLOCK_PREDICTION(1 << 16) (1 << 16)
12026#define DSC_LINE_BUF_DEPTH_SHIFT12 12
12027#define DSC_BPC_SHIFT8 8
12028#define DSC_VER_MIN_SHIFT4 4
12029#define DSC_VER_MAJ(0x1 << 0) (0x1 << 0)
12030
12031#define DSCA_PICTURE_PARAMETER_SET_1((const i915_reg_t){ .reg = (0x6B204) }) _MMIO(0x6B204)((const i915_reg_t){ .reg = (0x6B204) })
12032#define DSCC_PICTURE_PARAMETER_SET_1((const i915_reg_t){ .reg = (0x6BA04) }) _MMIO(0x6BA04)((const i915_reg_t){ .reg = (0x6BA04) })
12033#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB0x78274 0x78274
12034#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB0x78374 0x78374
12035#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC0x78474 0x78474
12036#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC0x78574 0x78574
12037#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)((const i915_reg_t){ .reg = (((0x78274) + ((pipe) - PIPE_B) *
((0x78474) - (0x78274)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78274) + ((pipe) - PIPE_B) *
((0x78474) - (0x78274)))) })
12038 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \((const i915_reg_t){ .reg = (((0x78274) + ((pipe) - PIPE_B) *
((0x78474) - (0x78274)))) })
12039 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)((const i915_reg_t){ .reg = (((0x78274) + ((pipe) - PIPE_B) *
((0x78474) - (0x78274)))) })
12040#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)((const i915_reg_t){ .reg = (((0x78374) + ((pipe) - PIPE_B) *
((0x78574) - (0x78374)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78374) + ((pipe) - PIPE_B) *
((0x78574) - (0x78374)))) })
12041 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \((const i915_reg_t){ .reg = (((0x78374) + ((pipe) - PIPE_B) *
((0x78574) - (0x78374)))) })
12042 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)((const i915_reg_t){ .reg = (((0x78374) + ((pipe) - PIPE_B) *
((0x78574) - (0x78374)))) })
12043#define DSC_BPP(bpp)((bpp) << 0) ((bpp) << 0)
12044
12045#define DSCA_PICTURE_PARAMETER_SET_2((const i915_reg_t){ .reg = (0x6B208) }) _MMIO(0x6B208)((const i915_reg_t){ .reg = (0x6B208) })
12046#define DSCC_PICTURE_PARAMETER_SET_2((const i915_reg_t){ .reg = (0x6BA08) }) _MMIO(0x6BA08)((const i915_reg_t){ .reg = (0x6BA08) })
12047#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB0x78278 0x78278
12048#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB0x78378 0x78378
12049#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC0x78478 0x78478
12050#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC0x78578 0x78578
12051#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)((const i915_reg_t){ .reg = (((0x78278) + ((pipe) - PIPE_B) *
((0x78478) - (0x78278)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78278) + ((pipe) - PIPE_B) *
((0x78478) - (0x78278)))) })
12052 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \((const i915_reg_t){ .reg = (((0x78278) + ((pipe) - PIPE_B) *
((0x78478) - (0x78278)))) })
12053 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)((const i915_reg_t){ .reg = (((0x78278) + ((pipe) - PIPE_B) *
((0x78478) - (0x78278)))) })
12054#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)((const i915_reg_t){ .reg = (((0x78378) + ((pipe) - PIPE_B) *
((0x78578) - (0x78378)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78378) + ((pipe) - PIPE_B) *
((0x78578) - (0x78378)))) })
12055 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \((const i915_reg_t){ .reg = (((0x78378) + ((pipe) - PIPE_B) *
((0x78578) - (0x78378)))) })
12056 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)((const i915_reg_t){ .reg = (((0x78378) + ((pipe) - PIPE_B) *
((0x78578) - (0x78378)))) })
12057#define DSC_PIC_WIDTH(pic_width)((pic_width) << 16) ((pic_width) << 16)
12058#define DSC_PIC_HEIGHT(pic_height)((pic_height) << 0) ((pic_height) << 0)
12059
12060#define DSCA_PICTURE_PARAMETER_SET_3((const i915_reg_t){ .reg = (0x6B20C) }) _MMIO(0x6B20C)((const i915_reg_t){ .reg = (0x6B20C) })
12061#define DSCC_PICTURE_PARAMETER_SET_3((const i915_reg_t){ .reg = (0x6BA0C) }) _MMIO(0x6BA0C)((const i915_reg_t){ .reg = (0x6BA0C) })
12062#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB0x7827C 0x7827C
12063#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB0x7837C 0x7837C
12064#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC0x7847C 0x7847C
12065#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC0x7857C 0x7857C
12066#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)((const i915_reg_t){ .reg = (((0x7827C) + ((pipe) - PIPE_B) *
((0x7847C) - (0x7827C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7827C) + ((pipe) - PIPE_B) *
((0x7847C) - (0x7827C)))) })
12067 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \((const i915_reg_t){ .reg = (((0x7827C) + ((pipe) - PIPE_B) *
((0x7847C) - (0x7827C)))) })
12068 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)((const i915_reg_t){ .reg = (((0x7827C) + ((pipe) - PIPE_B) *
((0x7847C) - (0x7827C)))) })
12069#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)((const i915_reg_t){ .reg = (((0x7837C) + ((pipe) - PIPE_B) *
((0x7857C) - (0x7837C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7837C) + ((pipe) - PIPE_B) *
((0x7857C) - (0x7837C)))) })
12070 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \((const i915_reg_t){ .reg = (((0x7837C) + ((pipe) - PIPE_B) *
((0x7857C) - (0x7837C)))) })
12071 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)((const i915_reg_t){ .reg = (((0x7837C) + ((pipe) - PIPE_B) *
((0x7857C) - (0x7837C)))) })
12072#define DSC_SLICE_WIDTH(slice_width)((slice_width) << 16) ((slice_width) << 16)
12073#define DSC_SLICE_HEIGHT(slice_height)((slice_height) << 0) ((slice_height) << 0)
12074
12075#define DSCA_PICTURE_PARAMETER_SET_4((const i915_reg_t){ .reg = (0x6B210) }) _MMIO(0x6B210)((const i915_reg_t){ .reg = (0x6B210) })
12076#define DSCC_PICTURE_PARAMETER_SET_4((const i915_reg_t){ .reg = (0x6BA10) }) _MMIO(0x6BA10)((const i915_reg_t){ .reg = (0x6BA10) })
12077#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB0x78280 0x78280
12078#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB0x78380 0x78380
12079#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC0x78480 0x78480
12080#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC0x78580 0x78580
12081#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)((const i915_reg_t){ .reg = (((0x78280) + ((pipe) - PIPE_B) *
((0x78480) - (0x78280)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78280) + ((pipe) - PIPE_B) *
((0x78480) - (0x78280)))) })
12082 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \((const i915_reg_t){ .reg = (((0x78280) + ((pipe) - PIPE_B) *
((0x78480) - (0x78280)))) })
12083 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)((const i915_reg_t){ .reg = (((0x78280) + ((pipe) - PIPE_B) *
((0x78480) - (0x78280)))) })
12084#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)((const i915_reg_t){ .reg = (((0x78380) + ((pipe) - PIPE_B) *
((0x78580) - (0x78380)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78380) + ((pipe) - PIPE_B) *
((0x78580) - (0x78380)))) })
12085 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \((const i915_reg_t){ .reg = (((0x78380) + ((pipe) - PIPE_B) *
((0x78580) - (0x78380)))) })
12086 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)((const i915_reg_t){ .reg = (((0x78380) + ((pipe) - PIPE_B) *
((0x78580) - (0x78380)))) })
12087#define DSC_INITIAL_DEC_DELAY(dec_delay)((dec_delay) << 16) ((dec_delay) << 16)
12088#define DSC_INITIAL_XMIT_DELAY(xmit_delay)((xmit_delay) << 0) ((xmit_delay) << 0)
12089
12090#define DSCA_PICTURE_PARAMETER_SET_5((const i915_reg_t){ .reg = (0x6B214) }) _MMIO(0x6B214)((const i915_reg_t){ .reg = (0x6B214) })
12091#define DSCC_PICTURE_PARAMETER_SET_5((const i915_reg_t){ .reg = (0x6BA14) }) _MMIO(0x6BA14)((const i915_reg_t){ .reg = (0x6BA14) })
12092#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB0x78284 0x78284
12093#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB0x78384 0x78384
12094#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC0x78484 0x78484
12095#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC0x78584 0x78584
12096#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)((const i915_reg_t){ .reg = (((0x78284) + ((pipe) - PIPE_B) *
((0x78484) - (0x78284)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78284) + ((pipe) - PIPE_B) *
((0x78484) - (0x78284)))) })
12097 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \((const i915_reg_t){ .reg = (((0x78284) + ((pipe) - PIPE_B) *
((0x78484) - (0x78284)))) })
12098 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)((const i915_reg_t){ .reg = (((0x78284) + ((pipe) - PIPE_B) *
((0x78484) - (0x78284)))) })
12099#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)((const i915_reg_t){ .reg = (((0x78384) + ((pipe) - PIPE_B) *
((0x78584) - (0x78384)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78384) + ((pipe) - PIPE_B) *
((0x78584) - (0x78384)))) })
12100 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \((const i915_reg_t){ .reg = (((0x78384) + ((pipe) - PIPE_B) *
((0x78584) - (0x78384)))) })
12101 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)((const i915_reg_t){ .reg = (((0x78384) + ((pipe) - PIPE_B) *
((0x78584) - (0x78384)))) })
12102#define DSC_SCALE_DEC_INT(scale_dec)((scale_dec) << 16) ((scale_dec) << 16)
12103#define DSC_SCALE_INC_INT(scale_inc)((scale_inc) << 0) ((scale_inc) << 0)
12104
12105#define DSCA_PICTURE_PARAMETER_SET_6((const i915_reg_t){ .reg = (0x6B218) }) _MMIO(0x6B218)((const i915_reg_t){ .reg = (0x6B218) })
12106#define DSCC_PICTURE_PARAMETER_SET_6((const i915_reg_t){ .reg = (0x6BA18) }) _MMIO(0x6BA18)((const i915_reg_t){ .reg = (0x6BA18) })
12107#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB0x78288 0x78288
12108#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB0x78388 0x78388
12109#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC0x78488 0x78488
12110#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC0x78588 0x78588
12111#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)((const i915_reg_t){ .reg = (((0x78288) + ((pipe) - PIPE_B) *
((0x78488) - (0x78288)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78288) + ((pipe) - PIPE_B) *
((0x78488) - (0x78288)))) })
12112 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \((const i915_reg_t){ .reg = (((0x78288) + ((pipe) - PIPE_B) *
((0x78488) - (0x78288)))) })
12113 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)((const i915_reg_t){ .reg = (((0x78288) + ((pipe) - PIPE_B) *
((0x78488) - (0x78288)))) })
12114#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)((const i915_reg_t){ .reg = (((0x78388) + ((pipe) - PIPE_B) *
((0x78588) - (0x78388)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78388) + ((pipe) - PIPE_B) *
((0x78588) - (0x78388)))) })
12115 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \((const i915_reg_t){ .reg = (((0x78388) + ((pipe) - PIPE_B) *
((0x78588) - (0x78388)))) })
12116 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)((const i915_reg_t){ .reg = (((0x78388) + ((pipe) - PIPE_B) *
((0x78588) - (0x78388)))) })
12117#define DSC_FLATNESS_MAX_QP(max_qp)((max_qp) << 24) ((max_qp) << 24)
12118#define DSC_FLATNESS_MIN_QP(min_qp)((min_qp) << 16) ((min_qp) << 16)
12119#define DSC_FIRST_LINE_BPG_OFFSET(offset)((offset) << 8) ((offset) << 8)
12120#define DSC_INITIAL_SCALE_VALUE(value)((value) << 0) ((value) << 0)
12121
12122#define DSCA_PICTURE_PARAMETER_SET_7((const i915_reg_t){ .reg = (0x6B21C) }) _MMIO(0x6B21C)((const i915_reg_t){ .reg = (0x6B21C) })
12123#define DSCC_PICTURE_PARAMETER_SET_7((const i915_reg_t){ .reg = (0x6BA1C) }) _MMIO(0x6BA1C)((const i915_reg_t){ .reg = (0x6BA1C) })
12124#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB0x7828C 0x7828C
12125#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB0x7838C 0x7838C
12126#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC0x7848C 0x7848C
12127#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC0x7858C 0x7858C
12128#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)((const i915_reg_t){ .reg = (((0x7828C) + ((pipe) - PIPE_B) *
((0x7848C) - (0x7828C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7828C) + ((pipe) - PIPE_B) *
((0x7848C) - (0x7828C)))) })
12129 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \((const i915_reg_t){ .reg = (((0x7828C) + ((pipe) - PIPE_B) *
((0x7848C) - (0x7828C)))) })
12130 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)((const i915_reg_t){ .reg = (((0x7828C) + ((pipe) - PIPE_B) *
((0x7848C) - (0x7828C)))) })
12131#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)((const i915_reg_t){ .reg = (((0x7838C) + ((pipe) - PIPE_B) *
((0x7858C) - (0x7838C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7838C) + ((pipe) - PIPE_B) *
((0x7858C) - (0x7838C)))) })
12132 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \((const i915_reg_t){ .reg = (((0x7838C) + ((pipe) - PIPE_B) *
((0x7858C) - (0x7838C)))) })
12133 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)((const i915_reg_t){ .reg = (((0x7838C) + ((pipe) - PIPE_B) *
((0x7858C) - (0x7838C)))) })
12134#define DSC_NFL_BPG_OFFSET(bpg_offset)((bpg_offset) << 16) ((bpg_offset) << 16)
12135#define DSC_SLICE_BPG_OFFSET(bpg_offset)((bpg_offset) << 0) ((bpg_offset) << 0)
12136
12137#define DSCA_PICTURE_PARAMETER_SET_8((const i915_reg_t){ .reg = (0x6B220) }) _MMIO(0x6B220)((const i915_reg_t){ .reg = (0x6B220) })
12138#define DSCC_PICTURE_PARAMETER_SET_8((const i915_reg_t){ .reg = (0x6BA20) }) _MMIO(0x6BA20)((const i915_reg_t){ .reg = (0x6BA20) })
12139#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB0x78290 0x78290
12140#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB0x78390 0x78390
12141#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC0x78490 0x78490
12142#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC0x78590 0x78590
12143#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)((const i915_reg_t){ .reg = (((0x78290) + ((pipe) - PIPE_B) *
((0x78490) - (0x78290)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78290) + ((pipe) - PIPE_B) *
((0x78490) - (0x78290)))) })
12144 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \((const i915_reg_t){ .reg = (((0x78290) + ((pipe) - PIPE_B) *
((0x78490) - (0x78290)))) })
12145 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)((const i915_reg_t){ .reg = (((0x78290) + ((pipe) - PIPE_B) *
((0x78490) - (0x78290)))) })
12146#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)((const i915_reg_t){ .reg = (((0x78390) + ((pipe) - PIPE_B) *
((0x78590) - (0x78390)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78390) + ((pipe) - PIPE_B) *
((0x78590) - (0x78390)))) })
12147 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \((const i915_reg_t){ .reg = (((0x78390) + ((pipe) - PIPE_B) *
((0x78590) - (0x78390)))) })
12148 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)((const i915_reg_t){ .reg = (((0x78390) + ((pipe) - PIPE_B) *
((0x78590) - (0x78390)))) })
12149#define DSC_INITIAL_OFFSET(initial_offset)((initial_offset) << 16) ((initial_offset) << 16)
12150#define DSC_FINAL_OFFSET(final_offset)((final_offset) << 0) ((final_offset) << 0)
12151
12152#define DSCA_PICTURE_PARAMETER_SET_9((const i915_reg_t){ .reg = (0x6B224) }) _MMIO(0x6B224)((const i915_reg_t){ .reg = (0x6B224) })
12153#define DSCC_PICTURE_PARAMETER_SET_9((const i915_reg_t){ .reg = (0x6BA24) }) _MMIO(0x6BA24)((const i915_reg_t){ .reg = (0x6BA24) })
12154#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB0x78294 0x78294
12155#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB0x78394 0x78394
12156#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC0x78494 0x78494
12157#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC0x78594 0x78594
12158#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)((const i915_reg_t){ .reg = (((0x78294) + ((pipe) - PIPE_B) *
((0x78494) - (0x78294)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78294) + ((pipe) - PIPE_B) *
((0x78494) - (0x78294)))) })
12159 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \((const i915_reg_t){ .reg = (((0x78294) + ((pipe) - PIPE_B) *
((0x78494) - (0x78294)))) })
12160 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)((const i915_reg_t){ .reg = (((0x78294) + ((pipe) - PIPE_B) *
((0x78494) - (0x78294)))) })
12161#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)((const i915_reg_t){ .reg = (((0x78394) + ((pipe) - PIPE_B) *
((0x78594) - (0x78394)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78394) + ((pipe) - PIPE_B) *
((0x78594) - (0x78394)))) })
12162 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \((const i915_reg_t){ .reg = (((0x78394) + ((pipe) - PIPE_B) *
((0x78594) - (0x78394)))) })
12163 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)((const i915_reg_t){ .reg = (((0x78394) + ((pipe) - PIPE_B) *
((0x78594) - (0x78394)))) })
12164#define DSC_RC_EDGE_FACTOR(rc_edge_fact)((rc_edge_fact) << 16) ((rc_edge_fact) << 16)
12165#define DSC_RC_MODEL_SIZE(rc_model_size)((rc_model_size) << 0) ((rc_model_size) << 0)
12166
12167#define DSCA_PICTURE_PARAMETER_SET_10((const i915_reg_t){ .reg = (0x6B228) }) _MMIO(0x6B228)((const i915_reg_t){ .reg = (0x6B228) })
12168#define DSCC_PICTURE_PARAMETER_SET_10((const i915_reg_t){ .reg = (0x6BA28) }) _MMIO(0x6BA28)((const i915_reg_t){ .reg = (0x6BA28) })
12169#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB0x78298 0x78298
12170#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB0x78398 0x78398
12171#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC0x78498 0x78498
12172#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC0x78598 0x78598
12173#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)((const i915_reg_t){ .reg = (((0x78298) + ((pipe) - PIPE_B) *
((0x78498) - (0x78298)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78298) + ((pipe) - PIPE_B) *
((0x78498) - (0x78298)))) })
12174 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \((const i915_reg_t){ .reg = (((0x78298) + ((pipe) - PIPE_B) *
((0x78498) - (0x78298)))) })
12175 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)((const i915_reg_t){ .reg = (((0x78298) + ((pipe) - PIPE_B) *
((0x78498) - (0x78298)))) })
12176#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)((const i915_reg_t){ .reg = (((0x78398) + ((pipe) - PIPE_B) *
((0x78598) - (0x78398)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x78398) + ((pipe) - PIPE_B) *
((0x78598) - (0x78398)))) })
12177 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \((const i915_reg_t){ .reg = (((0x78398) + ((pipe) - PIPE_B) *
((0x78598) - (0x78398)))) })
12178 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)((const i915_reg_t){ .reg = (((0x78398) + ((pipe) - PIPE_B) *
((0x78598) - (0x78398)))) })
12179#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)((rc_tgt_off_low) << 20) ((rc_tgt_off_low) << 20)
12180#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)((rc_tgt_off_high) << 16) ((rc_tgt_off_high) << 16)
12181#define DSC_RC_QUANT_INC_LIMIT1(lim)((lim) << 8) ((lim) << 8)
12182#define DSC_RC_QUANT_INC_LIMIT0(lim)((lim) << 0) ((lim) << 0)
12183
12184#define DSCA_PICTURE_PARAMETER_SET_11((const i915_reg_t){ .reg = (0x6B22C) }) _MMIO(0x6B22C)((const i915_reg_t){ .reg = (0x6B22C) })
12185#define DSCC_PICTURE_PARAMETER_SET_11((const i915_reg_t){ .reg = (0x6BA2C) }) _MMIO(0x6BA2C)((const i915_reg_t){ .reg = (0x6BA2C) })
12186#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB0x7829C 0x7829C
12187#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB0x7839C 0x7839C
12188#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC0x7849C 0x7849C
12189#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC0x7859C 0x7859C
12190#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)((const i915_reg_t){ .reg = (((0x7829C) + ((pipe) - PIPE_B) *
((0x7849C) - (0x7829C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7829C) + ((pipe) - PIPE_B) *
((0x7849C) - (0x7829C)))) })
12191 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \((const i915_reg_t){ .reg = (((0x7829C) + ((pipe) - PIPE_B) *
((0x7849C) - (0x7829C)))) })
12192 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)((const i915_reg_t){ .reg = (((0x7829C) + ((pipe) - PIPE_B) *
((0x7849C) - (0x7829C)))) })
12193#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)((const i915_reg_t){ .reg = (((0x7839C) + ((pipe) - PIPE_B) *
((0x7859C) - (0x7839C)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x7839C) + ((pipe) - PIPE_B) *
((0x7859C) - (0x7839C)))) })
12194 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \((const i915_reg_t){ .reg = (((0x7839C) + ((pipe) - PIPE_B) *
((0x7859C) - (0x7839C)))) })
12195 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)((const i915_reg_t){ .reg = (((0x7839C) + ((pipe) - PIPE_B) *
((0x7859C) - (0x7839C)))) })
12196
12197#define DSCA_PICTURE_PARAMETER_SET_12((const i915_reg_t){ .reg = (0x6B260) }) _MMIO(0x6B260)((const i915_reg_t){ .reg = (0x6B260) })
12198#define DSCC_PICTURE_PARAMETER_SET_12((const i915_reg_t){ .reg = (0x6BA60) }) _MMIO(0x6BA60)((const i915_reg_t){ .reg = (0x6BA60) })
12199#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB0x782A0 0x782A0
12200#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB0x783A0 0x783A0
12201#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC0x784A0 0x784A0
12202#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC0x785A0 0x785A0
12203#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)((const i915_reg_t){ .reg = (((0x782A0) + ((pipe) - PIPE_B) *
((0x784A0) - (0x782A0)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x782A0) + ((pipe) - PIPE_B) *
((0x784A0) - (0x782A0)))) })
12204 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \((const i915_reg_t){ .reg = (((0x782A0) + ((pipe) - PIPE_B) *
((0x784A0) - (0x782A0)))) })
12205 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)((const i915_reg_t){ .reg = (((0x782A0) + ((pipe) - PIPE_B) *
((0x784A0) - (0x782A0)))) })
12206#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)((const i915_reg_t){ .reg = (((0x783A0) + ((pipe) - PIPE_B) *
((0x785A0) - (0x783A0)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x783A0) + ((pipe) - PIPE_B) *
((0x785A0) - (0x783A0)))) })
12207 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \((const i915_reg_t){ .reg = (((0x783A0) + ((pipe) - PIPE_B) *
((0x785A0) - (0x783A0)))) })
12208 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)((const i915_reg_t){ .reg = (((0x783A0) + ((pipe) - PIPE_B) *
((0x785A0) - (0x783A0)))) })
12209
12210#define DSCA_PICTURE_PARAMETER_SET_13((const i915_reg_t){ .reg = (0x6B264) }) _MMIO(0x6B264)((const i915_reg_t){ .reg = (0x6B264) })
12211#define DSCC_PICTURE_PARAMETER_SET_13((const i915_reg_t){ .reg = (0x6BA64) }) _MMIO(0x6BA64)((const i915_reg_t){ .reg = (0x6BA64) })
12212#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB0x782A4 0x782A4
12213#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB0x783A4 0x783A4
12214#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC0x784A4 0x784A4
12215#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC0x785A4 0x785A4
12216#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)((const i915_reg_t){ .reg = (((0x782A4) + ((pipe) - PIPE_B) *
((0x784A4) - (0x782A4)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x782A4) + ((pipe) - PIPE_B) *
((0x784A4) - (0x782A4)))) })
12217 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \((const i915_reg_t){ .reg = (((0x782A4) + ((pipe) - PIPE_B) *
((0x784A4) - (0x782A4)))) })
12218 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)((const i915_reg_t){ .reg = (((0x782A4) + ((pipe) - PIPE_B) *
((0x784A4) - (0x782A4)))) })
12219#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)((const i915_reg_t){ .reg = (((0x783A4) + ((pipe) - PIPE_B) *
((0x785A4) - (0x783A4)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x783A4) + ((pipe) - PIPE_B) *
((0x785A4) - (0x783A4)))) })
12220 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \((const i915_reg_t){ .reg = (((0x783A4) + ((pipe) - PIPE_B) *
((0x785A4) - (0x783A4)))) })
12221 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)((const i915_reg_t){ .reg = (((0x783A4) + ((pipe) - PIPE_B) *
((0x785A4) - (0x783A4)))) })
12222
12223#define DSCA_PICTURE_PARAMETER_SET_14((const i915_reg_t){ .reg = (0x6B268) }) _MMIO(0x6B268)((const i915_reg_t){ .reg = (0x6B268) })
12224#define DSCC_PICTURE_PARAMETER_SET_14((const i915_reg_t){ .reg = (0x6BA68) }) _MMIO(0x6BA68)((const i915_reg_t){ .reg = (0x6BA68) })
12225#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB0x782A8 0x782A8
12226#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB0x783A8 0x783A8
12227#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC0x784A8 0x784A8
12228#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC0x785A8 0x785A8
12229#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)((const i915_reg_t){ .reg = (((0x782A8) + ((pipe) - PIPE_B) *
((0x784A8) - (0x782A8)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x782A8) + ((pipe) - PIPE_B) *
((0x784A8) - (0x782A8)))) })
12230 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \((const i915_reg_t){ .reg = (((0x782A8) + ((pipe) - PIPE_B) *
((0x784A8) - (0x782A8)))) })
12231 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)((const i915_reg_t){ .reg = (((0x782A8) + ((pipe) - PIPE_B) *
((0x784A8) - (0x782A8)))) })
12232#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)((const i915_reg_t){ .reg = (((0x783A8) + ((pipe) - PIPE_B) *
((0x785A8) - (0x783A8)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x783A8) + ((pipe) - PIPE_B) *
((0x785A8) - (0x783A8)))) })
12233 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \((const i915_reg_t){ .reg = (((0x783A8) + ((pipe) - PIPE_B) *
((0x785A8) - (0x783A8)))) })
12234 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)((const i915_reg_t){ .reg = (((0x783A8) + ((pipe) - PIPE_B) *
((0x785A8) - (0x783A8)))) })
12235
12236#define DSCA_PICTURE_PARAMETER_SET_15((const i915_reg_t){ .reg = (0x6B26C) }) _MMIO(0x6B26C)((const i915_reg_t){ .reg = (0x6B26C) })
12237#define DSCC_PICTURE_PARAMETER_SET_15((const i915_reg_t){ .reg = (0x6BA6C) }) _MMIO(0x6BA6C)((const i915_reg_t){ .reg = (0x6BA6C) })
12238#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB0x782AC 0x782AC
12239#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB0x783AC 0x783AC
12240#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC0x784AC 0x784AC
12241#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC0x785AC 0x785AC
12242#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)((const i915_reg_t){ .reg = (((0x782AC) + ((pipe) - PIPE_B) *
((0x784AC) - (0x782AC)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x782AC) + ((pipe) - PIPE_B) *
((0x784AC) - (0x782AC)))) })
12243 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \((const i915_reg_t){ .reg = (((0x782AC) + ((pipe) - PIPE_B) *
((0x784AC) - (0x782AC)))) })
12244 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)((const i915_reg_t){ .reg = (((0x782AC) + ((pipe) - PIPE_B) *
((0x784AC) - (0x782AC)))) })
12245#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)((const i915_reg_t){ .reg = (((0x783AC) + ((pipe) - PIPE_B) *
((0x785AC) - (0x783AC)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x783AC) + ((pipe) - PIPE_B) *
((0x785AC) - (0x783AC)))) })
12246 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \((const i915_reg_t){ .reg = (((0x783AC) + ((pipe) - PIPE_B) *
((0x785AC) - (0x783AC)))) })
12247 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)((const i915_reg_t){ .reg = (((0x783AC) + ((pipe) - PIPE_B) *
((0x785AC) - (0x783AC)))) })
12248
12249#define DSCA_PICTURE_PARAMETER_SET_16((const i915_reg_t){ .reg = (0x6B270) }) _MMIO(0x6B270)((const i915_reg_t){ .reg = (0x6B270) })
12250#define DSCC_PICTURE_PARAMETER_SET_16((const i915_reg_t){ .reg = (0x6BA70) }) _MMIO(0x6BA70)((const i915_reg_t){ .reg = (0x6BA70) })
12251#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB0x782B0 0x782B0
12252#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB0x783B0 0x783B0
12253#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC0x784B0 0x784B0
12254#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC0x785B0 0x785B0
12255#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)((const i915_reg_t){ .reg = (((0x782B0) + ((pipe) - PIPE_B) *
((0x784B0) - (0x782B0)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x782B0) + ((pipe) - PIPE_B) *
((0x784B0) - (0x782B0)))) })
12256 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \((const i915_reg_t){ .reg = (((0x782B0) + ((pipe) - PIPE_B) *
((0x784B0) - (0x782B0)))) })
12257 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)((const i915_reg_t){ .reg = (((0x782B0) + ((pipe) - PIPE_B) *
((0x784B0) - (0x782B0)))) })
12258#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)((const i915_reg_t){ .reg = (((0x783B0) + ((pipe) - PIPE_B) *
((0x785B0) - (0x783B0)))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = (((0x783B0) + ((pipe) - PIPE_B) *
((0x785B0) - (0x783B0)))) })
12259 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \((const i915_reg_t){ .reg = (((0x783B0) + ((pipe) - PIPE_B) *
((0x785B0) - (0x783B0)))) })
12260 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)((const i915_reg_t){ .reg = (((0x783B0) + ((pipe) - PIPE_B) *
((0x785B0) - (0x783B0)))) })
12261#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)((slice_row_per_frame) << 20) ((slice_row_per_frame) << 20)
12262#define DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16) ((slice_per_line) << 16)
12263#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)((slice_chunk_size) << 0) ((slice_chunk_size) << 0)
12264
12265/* Icelake Rate Control Buffer Threshold Registers */
12266#define DSCA_RC_BUF_THRESH_0((const i915_reg_t){ .reg = (0x6B230) }) _MMIO(0x6B230)((const i915_reg_t){ .reg = (0x6B230) })
12267#define DSCA_RC_BUF_THRESH_0_UDW((const i915_reg_t){ .reg = (0x6B230 + 4) }) _MMIO(0x6B230 + 4)((const i915_reg_t){ .reg = (0x6B230 + 4) })
12268#define DSCC_RC_BUF_THRESH_0((const i915_reg_t){ .reg = (0x6BA30) }) _MMIO(0x6BA30)((const i915_reg_t){ .reg = (0x6BA30) })
12269#define DSCC_RC_BUF_THRESH_0_UDW((const i915_reg_t){ .reg = (0x6BA30 + 4) }) _MMIO(0x6BA30 + 4)((const i915_reg_t){ .reg = (0x6BA30 + 4) })
12270#define _ICL_DSC0_RC_BUF_THRESH_0_PB(0x78254) (0x78254)
12271#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB(0x78254 + 4) (0x78254 + 4)
12272#define _ICL_DSC1_RC_BUF_THRESH_0_PB(0x78354) (0x78354)
12273#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB(0x78354 + 4) (0x78354 + 4)
12274#define _ICL_DSC0_RC_BUF_THRESH_0_PC(0x78454) (0x78454)
12275#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC(0x78454 + 4) (0x78454 + 4)
12276#define _ICL_DSC1_RC_BUF_THRESH_0_PC(0x78554) (0x78554)
12277#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC(0x78554 + 4) (0x78554 + 4)
12278#define ICL_DSC0_RC_BUF_THRESH_0(pipe)((const i915_reg_t){ .reg = ((((0x78254)) + ((pipe) - PIPE_B)
* (((0x78454)) - ((0x78254))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78254)) + ((pipe) - PIPE_B)
* (((0x78454)) - ((0x78254))))) })
12279 _ICL_DSC0_RC_BUF_THRESH_0_PB, \((const i915_reg_t){ .reg = ((((0x78254)) + ((pipe) - PIPE_B)
* (((0x78454)) - ((0x78254))))) })
12280 _ICL_DSC0_RC_BUF_THRESH_0_PC)((const i915_reg_t){ .reg = ((((0x78254)) + ((pipe) - PIPE_B)
* (((0x78454)) - ((0x78254))))) })
12281#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78254 + 4)) + ((pipe) - PIPE_B
) * (((0x78454 + 4)) - ((0x78254 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78254 + 4)) + ((pipe) - PIPE_B
) * (((0x78454 + 4)) - ((0x78254 + 4))))) })
12282 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78254 + 4)) + ((pipe) - PIPE_B
) * (((0x78454 + 4)) - ((0x78254 + 4))))) })
12283 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)((const i915_reg_t){ .reg = ((((0x78254 + 4)) + ((pipe) - PIPE_B
) * (((0x78454 + 4)) - ((0x78254 + 4))))) })
12284#define ICL_DSC1_RC_BUF_THRESH_0(pipe)((const i915_reg_t){ .reg = ((((0x78354)) + ((pipe) - PIPE_B)
* (((0x78554)) - ((0x78354))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78354)) + ((pipe) - PIPE_B)
* (((0x78554)) - ((0x78354))))) })
12285 _ICL_DSC1_RC_BUF_THRESH_0_PB, \((const i915_reg_t){ .reg = ((((0x78354)) + ((pipe) - PIPE_B)
* (((0x78554)) - ((0x78354))))) })
12286 _ICL_DSC1_RC_BUF_THRESH_0_PC)((const i915_reg_t){ .reg = ((((0x78354)) + ((pipe) - PIPE_B)
* (((0x78554)) - ((0x78354))))) })
12287#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)((const i915_reg_t){ .reg = ((((0x78354 + 4)) + ((pipe) - PIPE_B
) * (((0x78554 + 4)) - ((0x78354 + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x78354 + 4)) + ((pipe) - PIPE_B
) * (((0x78554 + 4)) - ((0x78354 + 4))))) })
12288 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \((const i915_reg_t){ .reg = ((((0x78354 + 4)) + ((pipe) - PIPE_B
) * (((0x78554 + 4)) - ((0x78354 + 4))))) })
12289 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)((const i915_reg_t){ .reg = ((((0x78354 + 4)) + ((pipe) - PIPE_B
) * (((0x78554 + 4)) - ((0x78354 + 4))))) })
12290
12291#define DSCA_RC_BUF_THRESH_1((const i915_reg_t){ .reg = (0x6B238) }) _MMIO(0x6B238)((const i915_reg_t){ .reg = (0x6B238) })
12292#define DSCA_RC_BUF_THRESH_1_UDW((const i915_reg_t){ .reg = (0x6B238 + 4) }) _MMIO(0x6B238 + 4)((const i915_reg_t){ .reg = (0x6B238 + 4) })
12293#define DSCC_RC_BUF_THRESH_1((const i915_reg_t){ .reg = (0x6BA38) }) _MMIO(0x6BA38)((const i915_reg_t){ .reg = (0x6BA38) })
12294#define DSCC_RC_BUF_THRESH_1_UDW((const i915_reg_t){ .reg = (0x6BA38 + 4) }) _MMIO(0x6BA38 + 4)((const i915_reg_t){ .reg = (0x6BA38 + 4) })
12295#define _ICL_DSC0_RC_BUF_THRESH_1_PB(0x7825C) (0x7825C)
12296#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB(0x7825C + 4) (0x7825C + 4)
12297#define _ICL_DSC1_RC_BUF_THRESH_1_PB(0x7835C) (0x7835C)
12298#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB(0x7835C + 4) (0x7835C + 4)
12299#define _ICL_DSC0_RC_BUF_THRESH_1_PC(0x7845C) (0x7845C)
12300#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC(0x7845C + 4) (0x7845C + 4)
12301#define _ICL_DSC1_RC_BUF_THRESH_1_PC(0x7855C) (0x7855C)
12302#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC(0x7855C + 4) (0x7855C + 4)
12303#define ICL_DSC0_RC_BUF_THRESH_1(pipe)((const i915_reg_t){ .reg = ((((0x7825C)) + ((pipe) - PIPE_B)
* (((0x7845C)) - ((0x7825C))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x7825C)) + ((pipe) - PIPE_B)
* (((0x7845C)) - ((0x7825C))))) })
12304 _ICL_DSC0_RC_BUF_THRESH_1_PB, \((const i915_reg_t){ .reg = ((((0x7825C)) + ((pipe) - PIPE_B)
* (((0x7845C)) - ((0x7825C))))) })
12305 _ICL_DSC0_RC_BUF_THRESH_1_PC)((const i915_reg_t){ .reg = ((((0x7825C)) + ((pipe) - PIPE_B)
* (((0x7845C)) - ((0x7825C))))) })
12306#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)((const i915_reg_t){ .reg = ((((0x7825C + 4)) + ((pipe) - PIPE_B
) * (((0x7845C + 4)) - ((0x7825C + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x7825C + 4)) + ((pipe) - PIPE_B
) * (((0x7845C + 4)) - ((0x7825C + 4))))) })
12307 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \((const i915_reg_t){ .reg = ((((0x7825C + 4)) + ((pipe) - PIPE_B
) * (((0x7845C + 4)) - ((0x7825C + 4))))) })
12308 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)((const i915_reg_t){ .reg = ((((0x7825C + 4)) + ((pipe) - PIPE_B
) * (((0x7845C + 4)) - ((0x7825C + 4))))) })
12309#define ICL_DSC1_RC_BUF_THRESH_1(pipe)((const i915_reg_t){ .reg = ((((0x7835C)) + ((pipe) - PIPE_B)
* (((0x7855C)) - ((0x7835C))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x7835C)) + ((pipe) - PIPE_B)
* (((0x7855C)) - ((0x7835C))))) })
12310 _ICL_DSC1_RC_BUF_THRESH_1_PB, \((const i915_reg_t){ .reg = ((((0x7835C)) + ((pipe) - PIPE_B)
* (((0x7855C)) - ((0x7835C))))) })
12311 _ICL_DSC1_RC_BUF_THRESH_1_PC)((const i915_reg_t){ .reg = ((((0x7835C)) + ((pipe) - PIPE_B)
* (((0x7855C)) - ((0x7835C))))) })
12312#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)((const i915_reg_t){ .reg = ((((0x7835C + 4)) + ((pipe) - PIPE_B
) * (((0x7855C + 4)) - ((0x7835C + 4))))) }) _MMIO_PIPE((pipe) - PIPE_B, \((const i915_reg_t){ .reg = ((((0x7835C + 4)) + ((pipe) - PIPE_B
) * (((0x7855C + 4)) - ((0x7835C + 4))))) })
12313 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \((const i915_reg_t){ .reg = ((((0x7835C + 4)) + ((pipe) - PIPE_B
) * (((0x7855C + 4)) - ((0x7835C + 4))))) })
12314 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)((const i915_reg_t){ .reg = ((((0x7835C + 4)) + ((pipe) - PIPE_B
) * (((0x7855C + 4)) - ((0x7835C + 4))))) })
12315
12316#define PORT_TX_DFLEXDPSP(fia)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x008A0)) }) _MMIO_FIA((fia), 0x008A0)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x008A0)) })
12317#define MODULAR_FIA_MASK(1 << 4) (1 << 4)
12318#define TC_LIVE_STATE_TBT(idx)(1 << ((idx) * 8 + 6)) (1 << ((idx) * 8 + 6))
12319#define TC_LIVE_STATE_TC(idx)(1 << ((idx) * 8 + 5)) (1 << ((idx) * 8 + 5))
12320#define DP_LANE_ASSIGNMENT_SHIFT(idx)((idx) * 8) ((idx) * 8)
12321#define DP_LANE_ASSIGNMENT_MASK(idx)(0xf << ((idx) * 8)) (0xf << ((idx) * 8))
12322#define DP_LANE_ASSIGNMENT(idx, x)((x) << ((idx) * 8)) ((x) << ((idx) * 8))
12323
12324#define PORT_TX_DFLEXDPPMS(fia)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00890)) }) _MMIO_FIA((fia), 0x00890)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00890)) })
12325#define DP_PHY_MODE_STATUS_COMPLETED(idx)(1 << (idx)) (1 << (idx))
12326
12327#define PORT_TX_DFLEXDPCSSS(fia)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00894)) }) _MMIO_FIA((fia), 0x00894)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00894)) })
12328#define DP_PHY_MODE_STATUS_NOT_SAFE(idx)(1 << (idx)) (1 << (idx))
12329
12330#define PORT_TX_DFLEXPA1(fia)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00880)) }) _MMIO_FIA((fia), 0x00880)((const i915_reg_t){ .reg = ((((const u32 []){ 0x163000, 0x16E000
, 0x16F000 })[((fia))]) + (0x00880)) })
12331#define DP_PIN_ASSIGNMENT_SHIFT(idx)((idx) * 4) ((idx) * 4)
12332#define DP_PIN_ASSIGNMENT_MASK(idx)(0xf << ((idx) * 4)) (0xf << ((idx) * 4))
12333#define DP_PIN_ASSIGNMENT(idx, x)((x) << ((idx) * 4)) ((x) << ((idx) * 4))
12334
12335/* This register controls the Display State Buffer (DSB) engines. */
12336#define _DSBSL_INSTANCE_BASE0x70B00 0x70B00
12337#define DSBSL_INSTANCE(pipe, id)(0x70B00 + (pipe) * 0x1000 + (id) * 0x100) (_DSBSL_INSTANCE_BASE0x70B00 + \
12338 (pipe) * 0x1000 + (id) * 0x100)
12339#define DSB_HEAD(pipe, id)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x0) }) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x0) })
12340#define DSB_TAIL(pipe, id)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x4) }) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x4) })
12341#define DSB_CTRL(pipe, id)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x8) }) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)((const i915_reg_t){ .reg = ((0x70B00 + (pipe) * 0x1000 + (id
) * 0x100) + 0x8) })
12342#define DSB_ENABLE(1 << 31) (1 << 31)
12343#define DSB_STATUS(1 << 0) (1 << 0)
12344
12345#define TGL_ROOT_DEVICE_ID0x9A00 0x9A00
12346#define TGL_ROOT_DEVICE_MASK0xFF00 0xFF00
12347#define TGL_ROOT_DEVICE_SKU_MASK0xF 0xF
12348#define TGL_ROOT_DEVICE_SKU_ULX0x2 0x2
12349#define TGL_ROOT_DEVICE_SKU_ULT0x4 0x4
12350
12351#endif /* _I915_REG_H_ */