Bug Summary

File:dev/pci/drm/amd/display/dc/dce112/dce112_resource.c
Warning:line 1125, column 26
Access to field 'high_sclk' results in a dereference of a null pointer (loaded from field 'bw_vbios')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dce112_resource.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c
1/*
2* Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/slab.h>
27
28#include "dm_services.h"
29
30#include "link_encoder.h"
31#include "stream_encoder.h"
32
33#include "resource.h"
34#include "include/irq_service_interface.h"
35#include "dce110/dce110_resource.h"
36#include "dce110/dce110_timing_generator.h"
37
38#include "irq/dce110/irq_service_dce110.h"
39#include "dce/dce_mem_input.h"
40#include "dce/dce_transform.h"
41#include "dce/dce_link_encoder.h"
42#include "dce/dce_stream_encoder.h"
43#include "dce/dce_audio.h"
44#include "dce/dce_opp.h"
45#include "dce/dce_ipp.h"
46#include "dce/dce_clock_source.h"
47
48#include "dce/dce_hwseq.h"
49#include "dce112/dce112_hw_sequencer.h"
50#include "dce/dce_abm.h"
51#include "dce/dce_dmcu.h"
52#include "dce/dce_aux.h"
53#include "dce/dce_i2c.h"
54#include "dce/dce_panel_cntl.h"
55
56#include "reg_helper.h"
57
58#include "dce/dce_11_2_d.h"
59#include "dce/dce_11_2_sh_mask.h"
60
61#include "dce100/dce100_resource.h"
62#define DC_LOGGERdc->ctx->logger \
63 dc->ctx->logger
64
65#ifndef mmDP_DPHY_INTERNAL_CTRL0x4aa7
66 #define mmDP_DPHY_INTERNAL_CTRL0x4aa7 0x4aa7
67 #define mmDP0_DP_DPHY_INTERNAL_CTRL0x4aa7 0x4aa7
68 #define mmDP1_DP_DPHY_INTERNAL_CTRL0x4ba7 0x4ba7
69 #define mmDP2_DP_DPHY_INTERNAL_CTRL0x4ca7 0x4ca7
70 #define mmDP3_DP_DPHY_INTERNAL_CTRL0x4da7 0x4da7
71 #define mmDP4_DP_DPHY_INTERNAL_CTRL0x4ea7 0x4ea7
72 #define mmDP5_DP_DPHY_INTERNAL_CTRL0x4fa7 0x4fa7
73 #define mmDP6_DP_DPHY_INTERNAL_CTRL0x54a7 0x54a7
74 #define mmDP7_DP_DPHY_INTERNAL_CTRL0x56a7 0x56a7
75 #define mmDP8_DP_DPHY_INTERNAL_CTRL0x57a7 0x57a7
76#endif
77
78#ifndef mmBIOS_SCRATCH_20x05CB
79 #define mmBIOS_SCRATCH_20x05CB 0x05CB
80 #define mmBIOS_SCRATCH_30x05CC 0x05CC
81 #define mmBIOS_SCRATCH_60x05CF 0x05CF
82#endif
83
84#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL0x4adc
85 #define mmDP_DPHY_BS_SR_SWAP_CNTL0x4adc 0x4ADC
86 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL0x4adc 0x4ADC
87 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL0x4bdc 0x4BDC
88 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL0x4cdc 0x4CDC
89 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL0x4ddc 0x4DDC
90 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL0x4edc 0x4EDC
91 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL0x4fdc 0x4FDC
92 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL0x54dc 0x54DC
93#endif
94
95#ifndef mmDP_DPHY_FAST_TRAINING0x4abc
96 #define mmDP_DPHY_FAST_TRAINING0x4abc 0x4ABC
97 #define mmDP0_DP_DPHY_FAST_TRAINING0x4abc 0x4ABC
98 #define mmDP1_DP_DPHY_FAST_TRAINING0x4bbc 0x4BBC
99 #define mmDP2_DP_DPHY_FAST_TRAINING0x4cbc 0x4CBC
100 #define mmDP3_DP_DPHY_FAST_TRAINING0x4dbc 0x4DBC
101 #define mmDP4_DP_DPHY_FAST_TRAINING0x4ebc 0x4EBC
102 #define mmDP5_DP_DPHY_FAST_TRAINING0x4fbc 0x4FBC
103 #define mmDP6_DP_DPHY_FAST_TRAINING0x54bc 0x54BC
104#endif
105
106enum dce112_clk_src_array_id {
107 DCE112_CLK_SRC_PLL0,
108 DCE112_CLK_SRC_PLL1,
109 DCE112_CLK_SRC_PLL2,
110 DCE112_CLK_SRC_PLL3,
111 DCE112_CLK_SRC_PLL4,
112 DCE112_CLK_SRC_PLL5,
113
114 DCE112_CLK_SRC_TOTAL
115};
116
117static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
118 {
119 .crtc = (mmCRTC0_CRTC_CONTROL0x1b9c - mmCRTC_CONTROL0x1b9c),
120 .dcp = (mmDCP0_GRPH_CONTROL0x1a01 - mmGRPH_CONTROL0x1a01),
121 },
122 {
123 .crtc = (mmCRTC1_CRTC_CONTROL0x1d9c - mmCRTC_CONTROL0x1b9c),
124 .dcp = (mmDCP1_GRPH_CONTROL0x1c01 - mmGRPH_CONTROL0x1a01),
125 },
126 {
127 .crtc = (mmCRTC2_CRTC_CONTROL0x1f9c - mmCRTC_CONTROL0x1b9c),
128 .dcp = (mmDCP2_GRPH_CONTROL0x1e01 - mmGRPH_CONTROL0x1a01),
129 },
130 {
131 .crtc = (mmCRTC3_CRTC_CONTROL0x419c - mmCRTC_CONTROL0x1b9c),
132 .dcp = (mmDCP3_GRPH_CONTROL0x4001 - mmGRPH_CONTROL0x1a01),
133 },
134 {
135 .crtc = (mmCRTC4_CRTC_CONTROL0x439c - mmCRTC_CONTROL0x1b9c),
136 .dcp = (mmDCP4_GRPH_CONTROL0x4201 - mmGRPH_CONTROL0x1a01),
137 },
138 {
139 .crtc = (mmCRTC5_CRTC_CONTROL0x459c - mmCRTC_CONTROL0x1b9c),
140 .dcp = (mmDCP5_GRPH_CONTROL0x4401 - mmGRPH_CONTROL0x1a01),
141 }
142};
143
144/* set register offset */
145#define SR(reg_name).reg_name = mmreg_name\
146 .reg_name = mm ## reg_name
147
148/* set register offset with instance */
149#define SRI(reg_name, block, id).reg_name = mmblockid_reg_name\
150 .reg_name = mm ## block ## id ## _ ## reg_name
151
152static const struct dce_dmcu_registers dmcu_regs = {
153 DMCU_DCE110_COMMON_REG_LIST().DMCU_CTRL = 0x1600, .DMCU_STATUS = 0x1601, .DMCU_RAM_ACCESS_CTRL
= 0x1608, .DMCU_IRAM_WR_CTRL = 0x160d, .DMCU_IRAM_WR_DATA = 0x160e
, .MASTER_COMM_DATA_REG1 = 0x161c, .MASTER_COMM_DATA_REG2 = 0x161d
, .MASTER_COMM_DATA_REG3 = 0x161e, .MASTER_COMM_CMD_REG = 0x161f
, .MASTER_COMM_CNTL_REG = 0x1620, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .SMU_INTERRUPT_CONTROL = 0x12e, .DC_DMCU_SCRATCH = 0x1618
, .DCI_MEM_PWR_STATUS = 0x317
154};
155
156static const struct dce_dmcu_shift dmcu_shift = {
157 DMCU_MASK_SH_LIST_DCE110(__SHIFT).DMCU_ENABLE = 0x4, .UC_IN_STOP_MODE = 0x2, .UC_IN_RESET = 0x0
, .IRAM_HOST_ACCESS_EN = 0x5, .IRAM_WR_ADDR_AUTO_INC = 0x2, .
IRAM_RD_ADDR_AUTO_INC = 0x3, .MASTER_COMM_CMD_REG_BYTE0 = 0x0
, .MASTER_COMM_INTERRUPT = 0x0, .STATIC_SCREEN1_INT_TO_UC_EN =
0x6, .STATIC_SCREEN2_INT_TO_UC_EN = 0x7, .STATIC_SCREEN3_INT_TO_UC_EN
= 0x9, .STATIC_SCREEN4_INT_TO_UC_EN = 0xa, .DC_SMU_INT_ENABLE
= 0x0, .DMCU_IRAM_MEM_PWR_STATE = 0xb
158};
159
160static const struct dce_dmcu_mask dmcu_mask = {
161 DMCU_MASK_SH_LIST_DCE110(_MASK).DMCU_ENABLE = 0x10, .UC_IN_STOP_MODE = 0x4, .UC_IN_RESET = 0x1
, .IRAM_HOST_ACCESS_EN = 0x20, .IRAM_WR_ADDR_AUTO_INC = 0x4, .
IRAM_RD_ADDR_AUTO_INC = 0x8, .MASTER_COMM_CMD_REG_BYTE0 = 0xff
, .MASTER_COMM_INTERRUPT = 0x1, .STATIC_SCREEN1_INT_TO_UC_EN =
0x40, .STATIC_SCREEN2_INT_TO_UC_EN = 0x80, .STATIC_SCREEN3_INT_TO_UC_EN
= 0x200, .STATIC_SCREEN4_INT_TO_UC_EN = 0x400, .DC_SMU_INT_ENABLE
= 0x1, .DMCU_IRAM_MEM_PWR_STATE = 0x800
162};
163
164static const struct dce_abm_registers abm_regs = {
165 ABM_DCE110_COMMON_REG_LIST().MASTER_COMM_CNTL_REG = 0x1620, .MASTER_COMM_CMD_REG = 0x161f
, .MASTER_COMM_DATA_REG1 = 0x161c, .DC_ABM1_HG_SAMPLE_RATE = 0x1654
, .DC_ABM1_LS_SAMPLE_RATE = 0x1655, .BL1_PWM_BL_UPDATE_SAMPLE_RATE
= 0x162f, .DC_ABM1_HG_MISC_CTRL = 0x164b, .DC_ABM1_IPCSC_COEFF_SEL
= 0x1639, .BL1_PWM_CURRENT_ABM_LEVEL = 0x162b, .BL1_PWM_TARGET_ABM_LEVEL
= 0x162a, .BL1_PWM_USER_LEVEL = 0x1629, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x1651, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x164a, .DC_ABM1_ACE_OFFSET_SLOPE_0
= 0x163a, .DC_ABM1_ACE_THRES_12 = 0x163f, .BIOS_SCRATCH_2 = 0x05CB
166};
167
168static const struct dce_abm_shift abm_shift = {
169 ABM_MASK_SH_LIST_DCE110(__SHIFT).MASTER_COMM_INTERRUPT = 0x0, .MASTER_COMM_CMD_REG_BYTE0 = 0x0
, .MASTER_COMM_CMD_REG_BYTE1 = 0x8, .MASTER_COMM_CMD_REG_BYTE2
= 0x10, .ABM1_HG_NUM_OF_BINS_SEL = 0x0, .ABM1_HG_VMAX_SEL = 0x8
, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x10, .ABM1_IPCSC_COEFF_SEL_R
= 0x10, .ABM1_IPCSC_COEFF_SEL_G = 0x8, .ABM1_IPCSC_COEFF_SEL_B
= 0x0, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0, .BL1_PWM_TARGET_ABM_LEVEL
= 0x0, .BL1_PWM_USER_LEVEL = 0x0, .ABM1_LS_MIN_PIXEL_VALUE_THRES
= 0x0, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x10, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR
= 0x10, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x18, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR
= 0x1f
170};
171
172static const struct dce_abm_mask abm_mask = {
173 ABM_MASK_SH_LIST_DCE110(_MASK).MASTER_COMM_INTERRUPT = 0x1, .MASTER_COMM_CMD_REG_BYTE0 = 0xff
, .MASTER_COMM_CMD_REG_BYTE1 = 0xff00, .MASTER_COMM_CMD_REG_BYTE2
= 0xff0000, .ABM1_HG_NUM_OF_BINS_SEL = 0x3, .ABM1_HG_VMAX_SEL
= 0x100, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x30000, .ABM1_IPCSC_COEFF_SEL_R
= 0xf0000, .ABM1_IPCSC_COEFF_SEL_G = 0xf00, .ABM1_IPCSC_COEFF_SEL_B
= 0xf, .BL1_PWM_CURRENT_ABM_LEVEL = 0x1ffff, .BL1_PWM_TARGET_ABM_LEVEL
= 0x1ffff, .BL1_PWM_USER_LEVEL = 0x1ffff, .ABM1_LS_MIN_PIXEL_VALUE_THRES
= 0x3ff, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x3ff0000, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR
= 0x10000, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x1000000,
.ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x80000000
174};
175
176static const struct dce110_aux_registers_shift aux_shift = {
177 DCE_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS
= 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG
= 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, .
AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW
= 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX =
0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, .
AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUXN_CALOUT_ERROR_AK
= 0xa, .AUXP_CALOUT_ERROR_AK = 0xa, .AUXN_IMPCAL_ENABLE = 0x0
, .AUXP_IMPCAL_ENABLE = 0x0, .AUXP_IMPCAL_OVERRIDE_ENABLE = 0x1c
, .AUXN_IMPCAL_OVERRIDE_ENABLE = 0x1c
178};
179
180static const struct dce110_aux_registers_mask aux_mask = {
181 DCE_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x1, .AUX_RESET = 0x10, .AUX_RESET_DONE = 0x20, .AUX_REG_RW_CNTL_STATUS
= 0xc, .AUX_SW_USE_AUX_REG_REQ = 0x10000, .AUX_SW_DONE_USING_AUX_REG
= 0x20000, .AUX_SW_START_DELAY = 0xf0, .AUX_SW_WR_BYTES = 0x1f0000
, .AUX_SW_GO = 0x1, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000
, .AUX_SW_DATA_RW = 0x1, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000
, .AUX_SW_INDEX = 0x1f0000, .AUX_SW_DATA = 0xff00, .AUX_SW_REPLY_BYTE_COUNT
= 0x1f000000, .AUX_SW_DONE = 0x1, .AUX_SW_DONE_ACK = 0x2, .AUXN_CALOUT_ERROR_AK
= 0x400, .AUXP_CALOUT_ERROR_AK = 0x400, .AUXN_IMPCAL_ENABLE =
0x1, .AUXP_IMPCAL_ENABLE = 0x1, .AUXP_IMPCAL_OVERRIDE_ENABLE
= 0x10000000, .AUXN_IMPCAL_OVERRIDE_ENABLE = 0x10000000
182};
183
184#define ipp_regs(id)[id] = { .CUR_UPDATE = mmDCPid_CUR_UPDATE, .CUR_CONTROL = mmDCPid_CUR_CONTROL
, .CUR_POSITION = mmDCPid_CUR_POSITION, .CUR_HOT_SPOT = mmDCPid_CUR_HOT_SPOT
, .CUR_COLOR1 = mmDCPid_CUR_COLOR1, .CUR_COLOR2 = mmDCPid_CUR_COLOR2
, .CUR_SIZE = mmDCPid_CUR_SIZE, .CUR_SURFACE_ADDRESS_HIGH = mmDCPid_CUR_SURFACE_ADDRESS_HIGH
, .CUR_SURFACE_ADDRESS = mmDCPid_CUR_SURFACE_ADDRESS, .PRESCALE_GRPH_CONTROL
= mmDCPid_PRESCALE_GRPH_CONTROL, .PRESCALE_VALUES_GRPH_R = mmDCPid_PRESCALE_VALUES_GRPH_R
, .PRESCALE_VALUES_GRPH_G = mmDCPid_PRESCALE_VALUES_GRPH_G, .
PRESCALE_VALUES_GRPH_B = mmDCPid_PRESCALE_VALUES_GRPH_B, .INPUT_GAMMA_CONTROL
= mmDCPid_INPUT_GAMMA_CONTROL, .DC_LUT_WRITE_EN_MASK = mmDCPid_DC_LUT_WRITE_EN_MASK
, .DC_LUT_RW_MODE = mmDCPid_DC_LUT_RW_MODE, .DC_LUT_CONTROL =
mmDCPid_DC_LUT_CONTROL, .DC_LUT_RW_INDEX = mmDCPid_DC_LUT_RW_INDEX
, .DC_LUT_SEQ_COLOR = mmDCPid_DC_LUT_SEQ_COLOR, .DEGAMMA_CONTROL
= mmDCPid_DEGAMMA_CONTROL, .DCFE_MEM_PWR_CTRL = mmDCFEid_DCFE_MEM_PWR_CTRL
}\
185[id] = {\
186 IPP_DCE110_REG_LIST_DCE_BASE(id).CUR_UPDATE = mmDCPid_CUR_UPDATE, .CUR_CONTROL = mmDCPid_CUR_CONTROL
, .CUR_POSITION = mmDCPid_CUR_POSITION, .CUR_HOT_SPOT = mmDCPid_CUR_HOT_SPOT
, .CUR_COLOR1 = mmDCPid_CUR_COLOR1, .CUR_COLOR2 = mmDCPid_CUR_COLOR2
, .CUR_SIZE = mmDCPid_CUR_SIZE, .CUR_SURFACE_ADDRESS_HIGH = mmDCPid_CUR_SURFACE_ADDRESS_HIGH
, .CUR_SURFACE_ADDRESS = mmDCPid_CUR_SURFACE_ADDRESS, .PRESCALE_GRPH_CONTROL
= mmDCPid_PRESCALE_GRPH_CONTROL, .PRESCALE_VALUES_GRPH_R = mmDCPid_PRESCALE_VALUES_GRPH_R
, .PRESCALE_VALUES_GRPH_G = mmDCPid_PRESCALE_VALUES_GRPH_G, .
PRESCALE_VALUES_GRPH_B = mmDCPid_PRESCALE_VALUES_GRPH_B, .INPUT_GAMMA_CONTROL
= mmDCPid_INPUT_GAMMA_CONTROL, .DC_LUT_WRITE_EN_MASK = mmDCPid_DC_LUT_WRITE_EN_MASK
, .DC_LUT_RW_MODE = mmDCPid_DC_LUT_RW_MODE, .DC_LUT_CONTROL =
mmDCPid_DC_LUT_CONTROL, .DC_LUT_RW_INDEX = mmDCPid_DC_LUT_RW_INDEX
, .DC_LUT_SEQ_COLOR = mmDCPid_DC_LUT_SEQ_COLOR, .DEGAMMA_CONTROL
= mmDCPid_DEGAMMA_CONTROL, .DCFE_MEM_PWR_CTRL = mmDCFEid_DCFE_MEM_PWR_CTRL\
187}
188
189static const struct dce_ipp_registers ipp_regs[] = {
190 ipp_regs(0)[0] = { .CUR_UPDATE = 0x1a6e, .CUR_CONTROL = 0x1a66, .CUR_POSITION
= 0x1a6a, .CUR_HOT_SPOT = 0x1a6b, .CUR_COLOR1 = 0x1a6c, .CUR_COLOR2
= 0x1a6d, .CUR_SIZE = 0x1a68, .CUR_SURFACE_ADDRESS_HIGH = 0x1a69
, .CUR_SURFACE_ADDRESS = 0x1a67, .PRESCALE_GRPH_CONTROL = 0x1a2d
, .PRESCALE_VALUES_GRPH_R = 0x1a2e, .PRESCALE_VALUES_GRPH_G =
0x1a2f, .PRESCALE_VALUES_GRPH_B = 0x1a30, .INPUT_GAMMA_CONTROL
= 0x1a10, .DC_LUT_WRITE_EN_MASK = 0x1a7e, .DC_LUT_RW_MODE = 0x1a78
, .DC_LUT_CONTROL = 0x1a80, .DC_LUT_RW_INDEX = 0x1a79, .DC_LUT_SEQ_COLOR
= 0x1a7a, .DEGAMMA_CONTROL = 0x1a58, .DCFE_MEM_PWR_CTRL = 0x1b03
},
191 ipp_regs(1)[1] = { .CUR_UPDATE = 0x1c6e, .CUR_CONTROL = 0x1c66, .CUR_POSITION
= 0x1c6a, .CUR_HOT_SPOT = 0x1c6b, .CUR_COLOR1 = 0x1c6c, .CUR_COLOR2
= 0x1c6d, .CUR_SIZE = 0x1c68, .CUR_SURFACE_ADDRESS_HIGH = 0x1c69
, .CUR_SURFACE_ADDRESS = 0x1c67, .PRESCALE_GRPH_CONTROL = 0x1c2d
, .PRESCALE_VALUES_GRPH_R = 0x1c2e, .PRESCALE_VALUES_GRPH_G =
0x1c2f, .PRESCALE_VALUES_GRPH_B = 0x1c30, .INPUT_GAMMA_CONTROL
= 0x1c10, .DC_LUT_WRITE_EN_MASK = 0x1c7e, .DC_LUT_RW_MODE = 0x1c78
, .DC_LUT_CONTROL = 0x1c80, .DC_LUT_RW_INDEX = 0x1c79, .DC_LUT_SEQ_COLOR
= 0x1c7a, .DEGAMMA_CONTROL = 0x1c58, .DCFE_MEM_PWR_CTRL = 0x1d03
},
192 ipp_regs(2)[2] = { .CUR_UPDATE = 0x1e6e, .CUR_CONTROL = 0x1e66, .CUR_POSITION
= 0x1e6a, .CUR_HOT_SPOT = 0x1e6b, .CUR_COLOR1 = 0x1e6c, .CUR_COLOR2
= 0x1e6d, .CUR_SIZE = 0x1e68, .CUR_SURFACE_ADDRESS_HIGH = 0x1e69
, .CUR_SURFACE_ADDRESS = 0x1e67, .PRESCALE_GRPH_CONTROL = 0x1e2d
, .PRESCALE_VALUES_GRPH_R = 0x1e2e, .PRESCALE_VALUES_GRPH_G =
0x1e2f, .PRESCALE_VALUES_GRPH_B = 0x1e30, .INPUT_GAMMA_CONTROL
= 0x1e10, .DC_LUT_WRITE_EN_MASK = 0x1e7e, .DC_LUT_RW_MODE = 0x1e78
, .DC_LUT_CONTROL = 0x1e80, .DC_LUT_RW_INDEX = 0x1e79, .DC_LUT_SEQ_COLOR
= 0x1e7a, .DEGAMMA_CONTROL = 0x1e58, .DCFE_MEM_PWR_CTRL = 0x1f03
},
193 ipp_regs(3)[3] = { .CUR_UPDATE = 0x406e, .CUR_CONTROL = 0x4066, .CUR_POSITION
= 0x406a, .CUR_HOT_SPOT = 0x406b, .CUR_COLOR1 = 0x406c, .CUR_COLOR2
= 0x406d, .CUR_SIZE = 0x4068, .CUR_SURFACE_ADDRESS_HIGH = 0x4069
, .CUR_SURFACE_ADDRESS = 0x4067, .PRESCALE_GRPH_CONTROL = 0x402d
, .PRESCALE_VALUES_GRPH_R = 0x402e, .PRESCALE_VALUES_GRPH_G =
0x402f, .PRESCALE_VALUES_GRPH_B = 0x4030, .INPUT_GAMMA_CONTROL
= 0x4010, .DC_LUT_WRITE_EN_MASK = 0x407e, .DC_LUT_RW_MODE = 0x4078
, .DC_LUT_CONTROL = 0x4080, .DC_LUT_RW_INDEX = 0x4079, .DC_LUT_SEQ_COLOR
= 0x407a, .DEGAMMA_CONTROL = 0x4058, .DCFE_MEM_PWR_CTRL = 0x4103
},
194 ipp_regs(4)[4] = { .CUR_UPDATE = 0x426e, .CUR_CONTROL = 0x4266, .CUR_POSITION
= 0x426a, .CUR_HOT_SPOT = 0x426b, .CUR_COLOR1 = 0x426c, .CUR_COLOR2
= 0x426d, .CUR_SIZE = 0x4268, .CUR_SURFACE_ADDRESS_HIGH = 0x4269
, .CUR_SURFACE_ADDRESS = 0x4267, .PRESCALE_GRPH_CONTROL = 0x422d
, .PRESCALE_VALUES_GRPH_R = 0x422e, .PRESCALE_VALUES_GRPH_G =
0x422f, .PRESCALE_VALUES_GRPH_B = 0x4230, .INPUT_GAMMA_CONTROL
= 0x4210, .DC_LUT_WRITE_EN_MASK = 0x427e, .DC_LUT_RW_MODE = 0x4278
, .DC_LUT_CONTROL = 0x4280, .DC_LUT_RW_INDEX = 0x4279, .DC_LUT_SEQ_COLOR
= 0x427a, .DEGAMMA_CONTROL = 0x4258, .DCFE_MEM_PWR_CTRL = 0x4303
},
195 ipp_regs(5)[5] = { .CUR_UPDATE = 0x446e, .CUR_CONTROL = 0x4466, .CUR_POSITION
= 0x446a, .CUR_HOT_SPOT = 0x446b, .CUR_COLOR1 = 0x446c, .CUR_COLOR2
= 0x446d, .CUR_SIZE = 0x4468, .CUR_SURFACE_ADDRESS_HIGH = 0x4469
, .CUR_SURFACE_ADDRESS = 0x4467, .PRESCALE_GRPH_CONTROL = 0x442d
, .PRESCALE_VALUES_GRPH_R = 0x442e, .PRESCALE_VALUES_GRPH_G =
0x442f, .PRESCALE_VALUES_GRPH_B = 0x4430, .INPUT_GAMMA_CONTROL
= 0x4410, .DC_LUT_WRITE_EN_MASK = 0x447e, .DC_LUT_RW_MODE = 0x4478
, .DC_LUT_CONTROL = 0x4480, .DC_LUT_RW_INDEX = 0x4479, .DC_LUT_SEQ_COLOR
= 0x447a, .DEGAMMA_CONTROL = 0x4458, .DCFE_MEM_PWR_CTRL = 0x4503
}
196};
197
198static const struct dce_ipp_shift ipp_shift = {
199 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT).CURSOR_UPDATE_LOCK = 0x10, .CURSOR_EN = 0x0, .CURSOR_MODE = 0x8
, .CURSOR_2X_MAGNIFY = 0x10, .CUR_INV_TRANS_CLAMP = 0x4, .CURSOR_X_POSITION
= 0x10, .CURSOR_Y_POSITION = 0x0, .CURSOR_HOT_SPOT_X = 0x10,
.CURSOR_HOT_SPOT_Y = 0x0, .CUR_COLOR1_BLUE = 0x0, .CUR_COLOR1_GREEN
= 0x8, .CUR_COLOR1_RED = 0x10, .CUR_COLOR2_BLUE = 0x0, .CUR_COLOR2_GREEN
= 0x8, .CUR_COLOR2_RED = 0x10, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT
= 0x0, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS
= 0x0, .GRPH_PRESCALE_BYPASS = 0x4, .GRPH_PRESCALE_SCALE_R =
0x10, .GRPH_PRESCALE_BIAS_R = 0x0, .GRPH_PRESCALE_SCALE_G = 0x10
, .GRPH_PRESCALE_BIAS_G = 0x0, .GRPH_PRESCALE_SCALE_B = 0x10,
.GRPH_PRESCALE_BIAS_B = 0x0, .GRPH_INPUT_GAMMA_MODE = 0x0, .
DC_LUT_WRITE_EN_MASK = 0x0, .DC_LUT_RW_MODE = 0x0, .DC_LUT_DATA_R_FORMAT
= 0x16, .DC_LUT_DATA_G_FORMAT = 0xe, .DC_LUT_DATA_B_FORMAT =
0x6, .DC_LUT_RW_INDEX = 0x0, .DC_LUT_SEQ_COLOR = 0x0, .GRPH_DEGAMMA_MODE
= 0x0, .CURSOR_DEGAMMA_MODE = 0xc, .CURSOR2_DEGAMMA_MODE = 0x8
, .DCP_LUT_MEM_PWR_DIS = 0x2
200};
201
202static const struct dce_ipp_mask ipp_mask = {
203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK).CURSOR_UPDATE_LOCK = 0x10000, .CURSOR_EN = 0x1, .CURSOR_MODE
= 0x300, .CURSOR_2X_MAGNIFY = 0x10000, .CUR_INV_TRANS_CLAMP =
0x10, .CURSOR_X_POSITION = 0x3fff0000, .CURSOR_Y_POSITION = 0x3fff
, .CURSOR_HOT_SPOT_X = 0x7f0000, .CURSOR_HOT_SPOT_Y = 0x7f, .
CUR_COLOR1_BLUE = 0xff, .CUR_COLOR1_GREEN = 0xff00, .CUR_COLOR1_RED
= 0xff0000, .CUR_COLOR2_BLUE = 0xff, .CUR_COLOR2_GREEN = 0xff00
, .CUR_COLOR2_RED = 0xff0000, .CURSOR_WIDTH = 0x7f0000, .CURSOR_HEIGHT
= 0x7f, .CURSOR_SURFACE_ADDRESS_HIGH = 0xff, .CURSOR_SURFACE_ADDRESS
= 0xffffffff, .GRPH_PRESCALE_BYPASS = 0x10, .GRPH_PRESCALE_SCALE_R
= 0xffff0000, .GRPH_PRESCALE_BIAS_R = 0xffff, .GRPH_PRESCALE_SCALE_G
= 0xffff0000, .GRPH_PRESCALE_BIAS_G = 0xffff, .GRPH_PRESCALE_SCALE_B
= 0xffff0000, .GRPH_PRESCALE_BIAS_B = 0xffff, .GRPH_INPUT_GAMMA_MODE
= 0x1, .DC_LUT_WRITE_EN_MASK = 0x7, .DC_LUT_RW_MODE = 0x1, .
DC_LUT_DATA_R_FORMAT = 0xc00000, .DC_LUT_DATA_G_FORMAT = 0xc000
, .DC_LUT_DATA_B_FORMAT = 0xc0, .DC_LUT_RW_INDEX = 0xff, .DC_LUT_SEQ_COLOR
= 0xffff, .GRPH_DEGAMMA_MODE = 0x3, .CURSOR_DEGAMMA_MODE = 0x3000
, .CURSOR2_DEGAMMA_MODE = 0x300, .DCP_LUT_MEM_PWR_DIS = 0x4
204};
205
206#define transform_regs(id)[id] = { .LB_DATA_FORMAT = mmLBid_LB_DATA_FORMAT, .GAMUT_REMAP_CONTROL
= mmDCPid_GAMUT_REMAP_CONTROL, .GAMUT_REMAP_C11_C12 = mmDCPid_GAMUT_REMAP_C11_C12
, .GAMUT_REMAP_C13_C14 = mmDCPid_GAMUT_REMAP_C13_C14, .GAMUT_REMAP_C21_C22
= mmDCPid_GAMUT_REMAP_C21_C22, .GAMUT_REMAP_C23_C24 = mmDCPid_GAMUT_REMAP_C23_C24
, .GAMUT_REMAP_C31_C32 = mmDCPid_GAMUT_REMAP_C31_C32, .GAMUT_REMAP_C33_C34
= mmDCPid_GAMUT_REMAP_C33_C34, .OUTPUT_CSC_C11_C12 = mmDCPid_OUTPUT_CSC_C11_C12
, .OUTPUT_CSC_C13_C14 = mmDCPid_OUTPUT_CSC_C13_C14, .OUTPUT_CSC_C21_C22
= mmDCPid_OUTPUT_CSC_C21_C22, .OUTPUT_CSC_C23_C24 = mmDCPid_OUTPUT_CSC_C23_C24
, .OUTPUT_CSC_C31_C32 = mmDCPid_OUTPUT_CSC_C31_C32, .OUTPUT_CSC_C33_C34
= mmDCPid_OUTPUT_CSC_C33_C34, .OUTPUT_CSC_CONTROL = mmDCPid_OUTPUT_CSC_CONTROL
, .REGAMMA_CNTLA_START_CNTL = mmDCPid_REGAMMA_CNTLA_START_CNTL
, .REGAMMA_CNTLA_SLOPE_CNTL = mmDCPid_REGAMMA_CNTLA_SLOPE_CNTL
, .REGAMMA_CNTLA_END_CNTL1 = mmDCPid_REGAMMA_CNTLA_END_CNTL1,
.REGAMMA_CNTLA_END_CNTL2 = mmDCPid_REGAMMA_CNTLA_END_CNTL2, .
REGAMMA_CNTLA_REGION_0_1 = mmDCPid_REGAMMA_CNTLA_REGION_0_1, .
REGAMMA_CNTLA_REGION_2_3 = mmDCPid_REGAMMA_CNTLA_REGION_2_3, .
REGAMMA_CNTLA_REGION_4_5 = mmDCPid_REGAMMA_CNTLA_REGION_4_5, .
REGAMMA_CNTLA_REGION_6_7 = mmDCPid_REGAMMA_CNTLA_REGION_6_7, .
REGAMMA_CNTLA_REGION_8_9 = mmDCPid_REGAMMA_CNTLA_REGION_8_9, .
REGAMMA_CNTLA_REGION_10_11 = mmDCPid_REGAMMA_CNTLA_REGION_10_11
, .REGAMMA_CNTLA_REGION_12_13 = mmDCPid_REGAMMA_CNTLA_REGION_12_13
, .REGAMMA_CNTLA_REGION_14_15 = mmDCPid_REGAMMA_CNTLA_REGION_14_15
, .REGAMMA_LUT_WRITE_EN_MASK = mmDCPid_REGAMMA_LUT_WRITE_EN_MASK
, .REGAMMA_LUT_INDEX = mmDCPid_REGAMMA_LUT_INDEX, .REGAMMA_LUT_DATA
= mmDCPid_REGAMMA_LUT_DATA, .REGAMMA_CONTROL = mmDCPid_REGAMMA_CONTROL
, .DENORM_CONTROL = mmDCPid_DENORM_CONTROL, .DCP_SPATIAL_DITHER_CNTL
= mmDCPid_DCP_SPATIAL_DITHER_CNTL, .OUT_ROUND_CONTROL = mmDCPid_OUT_ROUND_CONTROL
, .OUT_CLAMP_CONTROL_R_CR = mmDCPid_OUT_CLAMP_CONTROL_R_CR, .
OUT_CLAMP_CONTROL_G_Y = mmDCPid_OUT_CLAMP_CONTROL_G_Y, .OUT_CLAMP_CONTROL_B_CB
= mmDCPid_OUT_CLAMP_CONTROL_B_CB, .SCL_MODE = mmSCLid_SCL_MODE
, .SCL_TAP_CONTROL = mmSCLid_SCL_TAP_CONTROL, .SCL_CONTROL = mmSCLid_SCL_CONTROL
, .SCL_BYPASS_CONTROL = mmSCLid_SCL_BYPASS_CONTROL, .EXT_OVERSCAN_LEFT_RIGHT
= mmSCLid_EXT_OVERSCAN_LEFT_RIGHT, .EXT_OVERSCAN_TOP_BOTTOM =
mmSCLid_EXT_OVERSCAN_TOP_BOTTOM, .SCL_VERT_FILTER_CONTROL = mmSCLid_SCL_VERT_FILTER_CONTROL
, .SCL_HORZ_FILTER_CONTROL = mmSCLid_SCL_HORZ_FILTER_CONTROL,
.SCL_COEF_RAM_SELECT = mmSCLid_SCL_COEF_RAM_SELECT, .SCL_COEF_RAM_TAP_DATA
= mmSCLid_SCL_COEF_RAM_TAP_DATA, .VIEWPORT_START = mmSCLid_VIEWPORT_START
, .VIEWPORT_SIZE = mmSCLid_VIEWPORT_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO
= mmSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= mmSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_INIT
= mmSCLid_SCL_HORZ_FILTER_INIT, .SCL_VERT_FILTER_INIT = mmSCLid_SCL_VERT_FILTER_INIT
, .SCL_AUTOMATIC_MODE_CONTROL = mmSCLid_SCL_AUTOMATIC_MODE_CONTROL
, .LB_MEMORY_CTRL = mmLBid_LB_MEMORY_CTRL, .SCL_UPDATE = mmSCLid_SCL_UPDATE
, .SCL_F_SHARP_CONTROL = mmSCLid_SCL_F_SHARP_CONTROL, .DCFE_MEM_PWR_CTRL
= mmDCFEid_DCFE_MEM_PWR_CTRL, .DCFE_MEM_PWR_STATUS = mmDCFEid_DCFE_MEM_PWR_STATUS
}\
207[id] = {\
208 XFM_COMMON_REG_LIST_DCE110(id).LB_DATA_FORMAT = mmLBid_LB_DATA_FORMAT, .GAMUT_REMAP_CONTROL
= mmDCPid_GAMUT_REMAP_CONTROL, .GAMUT_REMAP_C11_C12 = mmDCPid_GAMUT_REMAP_C11_C12
, .GAMUT_REMAP_C13_C14 = mmDCPid_GAMUT_REMAP_C13_C14, .GAMUT_REMAP_C21_C22
= mmDCPid_GAMUT_REMAP_C21_C22, .GAMUT_REMAP_C23_C24 = mmDCPid_GAMUT_REMAP_C23_C24
, .GAMUT_REMAP_C31_C32 = mmDCPid_GAMUT_REMAP_C31_C32, .GAMUT_REMAP_C33_C34
= mmDCPid_GAMUT_REMAP_C33_C34, .OUTPUT_CSC_C11_C12 = mmDCPid_OUTPUT_CSC_C11_C12
, .OUTPUT_CSC_C13_C14 = mmDCPid_OUTPUT_CSC_C13_C14, .OUTPUT_CSC_C21_C22
= mmDCPid_OUTPUT_CSC_C21_C22, .OUTPUT_CSC_C23_C24 = mmDCPid_OUTPUT_CSC_C23_C24
, .OUTPUT_CSC_C31_C32 = mmDCPid_OUTPUT_CSC_C31_C32, .OUTPUT_CSC_C33_C34
= mmDCPid_OUTPUT_CSC_C33_C34, .OUTPUT_CSC_CONTROL = mmDCPid_OUTPUT_CSC_CONTROL
, .REGAMMA_CNTLA_START_CNTL = mmDCPid_REGAMMA_CNTLA_START_CNTL
, .REGAMMA_CNTLA_SLOPE_CNTL = mmDCPid_REGAMMA_CNTLA_SLOPE_CNTL
, .REGAMMA_CNTLA_END_CNTL1 = mmDCPid_REGAMMA_CNTLA_END_CNTL1,
.REGAMMA_CNTLA_END_CNTL2 = mmDCPid_REGAMMA_CNTLA_END_CNTL2, .
REGAMMA_CNTLA_REGION_0_1 = mmDCPid_REGAMMA_CNTLA_REGION_0_1, .
REGAMMA_CNTLA_REGION_2_3 = mmDCPid_REGAMMA_CNTLA_REGION_2_3, .
REGAMMA_CNTLA_REGION_4_5 = mmDCPid_REGAMMA_CNTLA_REGION_4_5, .
REGAMMA_CNTLA_REGION_6_7 = mmDCPid_REGAMMA_CNTLA_REGION_6_7, .
REGAMMA_CNTLA_REGION_8_9 = mmDCPid_REGAMMA_CNTLA_REGION_8_9, .
REGAMMA_CNTLA_REGION_10_11 = mmDCPid_REGAMMA_CNTLA_REGION_10_11
, .REGAMMA_CNTLA_REGION_12_13 = mmDCPid_REGAMMA_CNTLA_REGION_12_13
, .REGAMMA_CNTLA_REGION_14_15 = mmDCPid_REGAMMA_CNTLA_REGION_14_15
, .REGAMMA_LUT_WRITE_EN_MASK = mmDCPid_REGAMMA_LUT_WRITE_EN_MASK
, .REGAMMA_LUT_INDEX = mmDCPid_REGAMMA_LUT_INDEX, .REGAMMA_LUT_DATA
= mmDCPid_REGAMMA_LUT_DATA, .REGAMMA_CONTROL = mmDCPid_REGAMMA_CONTROL
, .DENORM_CONTROL = mmDCPid_DENORM_CONTROL, .DCP_SPATIAL_DITHER_CNTL
= mmDCPid_DCP_SPATIAL_DITHER_CNTL, .OUT_ROUND_CONTROL = mmDCPid_OUT_ROUND_CONTROL
, .OUT_CLAMP_CONTROL_R_CR = mmDCPid_OUT_CLAMP_CONTROL_R_CR, .
OUT_CLAMP_CONTROL_G_Y = mmDCPid_OUT_CLAMP_CONTROL_G_Y, .OUT_CLAMP_CONTROL_B_CB
= mmDCPid_OUT_CLAMP_CONTROL_B_CB, .SCL_MODE = mmSCLid_SCL_MODE
, .SCL_TAP_CONTROL = mmSCLid_SCL_TAP_CONTROL, .SCL_CONTROL = mmSCLid_SCL_CONTROL
, .SCL_BYPASS_CONTROL = mmSCLid_SCL_BYPASS_CONTROL, .EXT_OVERSCAN_LEFT_RIGHT
= mmSCLid_EXT_OVERSCAN_LEFT_RIGHT, .EXT_OVERSCAN_TOP_BOTTOM =
mmSCLid_EXT_OVERSCAN_TOP_BOTTOM, .SCL_VERT_FILTER_CONTROL = mmSCLid_SCL_VERT_FILTER_CONTROL
, .SCL_HORZ_FILTER_CONTROL = mmSCLid_SCL_HORZ_FILTER_CONTROL,
.SCL_COEF_RAM_SELECT = mmSCLid_SCL_COEF_RAM_SELECT, .SCL_COEF_RAM_TAP_DATA
= mmSCLid_SCL_COEF_RAM_TAP_DATA, .VIEWPORT_START = mmSCLid_VIEWPORT_START
, .VIEWPORT_SIZE = mmSCLid_VIEWPORT_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO
= mmSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= mmSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_INIT
= mmSCLid_SCL_HORZ_FILTER_INIT, .SCL_VERT_FILTER_INIT = mmSCLid_SCL_VERT_FILTER_INIT
, .SCL_AUTOMATIC_MODE_CONTROL = mmSCLid_SCL_AUTOMATIC_MODE_CONTROL
, .LB_MEMORY_CTRL = mmLBid_LB_MEMORY_CTRL, .SCL_UPDATE = mmSCLid_SCL_UPDATE
, .SCL_F_SHARP_CONTROL = mmSCLid_SCL_F_SHARP_CONTROL, .DCFE_MEM_PWR_CTRL
= mmDCFEid_DCFE_MEM_PWR_CTRL, .DCFE_MEM_PWR_STATUS = mmDCFEid_DCFE_MEM_PWR_STATUS\
209}
210
211static const struct dce_transform_registers xfm_regs[] = {
212 transform_regs(0)[0] = { .LB_DATA_FORMAT = 0x1ac0, .GAMUT_REMAP_CONTROL = 0x1a59
, .GAMUT_REMAP_C11_C12 = 0x1a5a, .GAMUT_REMAP_C13_C14 = 0x1a5b
, .GAMUT_REMAP_C21_C22 = 0x1a5c, .GAMUT_REMAP_C23_C24 = 0x1a5d
, .GAMUT_REMAP_C31_C32 = 0x1a5e, .GAMUT_REMAP_C33_C34 = 0x1a5f
, .OUTPUT_CSC_C11_C12 = 0x1a3d, .OUTPUT_CSC_C13_C14 = 0x1a3e,
.OUTPUT_CSC_C21_C22 = 0x1a3f, .OUTPUT_CSC_C23_C24 = 0x1a40, .
OUTPUT_CSC_C31_C32 = 0x1a41, .OUTPUT_CSC_C33_C34 = 0x1a42, .OUTPUT_CSC_CONTROL
= 0x1a3c, .REGAMMA_CNTLA_START_CNTL = 0x1aa4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x1aa5, .REGAMMA_CNTLA_END_CNTL1 = 0x1aa6, .REGAMMA_CNTLA_END_CNTL2
= 0x1aa7, .REGAMMA_CNTLA_REGION_0_1 = 0x1aa8, .REGAMMA_CNTLA_REGION_2_3
= 0x1aa9, .REGAMMA_CNTLA_REGION_4_5 = 0x1aaa, .REGAMMA_CNTLA_REGION_6_7
= 0x1aab, .REGAMMA_CNTLA_REGION_8_9 = 0x1aac, .REGAMMA_CNTLA_REGION_10_11
= 0x1aad, .REGAMMA_CNTLA_REGION_12_13 = 0x1aae, .REGAMMA_CNTLA_REGION_14_15
= 0x1aaf, .REGAMMA_LUT_WRITE_EN_MASK = 0x1aa3, .REGAMMA_LUT_INDEX
= 0x1aa1, .REGAMMA_LUT_DATA = 0x1aa2, .REGAMMA_CONTROL = 0x1aa0
, .DENORM_CONTROL = 0x1a50, .DCP_SPATIAL_DITHER_CNTL = 0x1a60
, .OUT_ROUND_CONTROL = 0x1a51, .OUT_CLAMP_CONTROL_R_CR = 0x1a52
, .OUT_CLAMP_CONTROL_G_Y = 0x1a9c, .OUT_CLAMP_CONTROL_B_CB = 0x1a9d
, .SCL_MODE = 0x1b42, .SCL_TAP_CONTROL = 0x1b43, .SCL_CONTROL
= 0x1b44, .SCL_BYPASS_CONTROL = 0x1b45, .EXT_OVERSCAN_LEFT_RIGHT
= 0x1b5e, .EXT_OVERSCAN_TOP_BOTTOM = 0x1b5f, .SCL_VERT_FILTER_CONTROL
= 0x1b4b, .SCL_HORZ_FILTER_CONTROL = 0x1b48, .SCL_COEF_RAM_SELECT
= 0x1b40, .SCL_COEF_RAM_TAP_DATA = 0x1b41, .VIEWPORT_START =
0x1b5c, .VIEWPORT_SIZE = 0x1b5d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x1b49, .SCL_VERT_FILTER_SCALE_RATIO = 0x1b4c, .SCL_HORZ_FILTER_INIT
= 0x1b4a, .SCL_VERT_FILTER_INIT = 0x1b4d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x1b47, .LB_MEMORY_CTRL = 0x1ac1, .SCL_UPDATE = 0x1b51, .SCL_F_SHARP_CONTROL
= 0x1b53, .DCFE_MEM_PWR_CTRL = 0x1b03, .DCFE_MEM_PWR_STATUS =
0x1b05},
213 transform_regs(1)[1] = { .LB_DATA_FORMAT = 0x1cc0, .GAMUT_REMAP_CONTROL = 0x1c59
, .GAMUT_REMAP_C11_C12 = 0x1c5a, .GAMUT_REMAP_C13_C14 = 0x1c5b
, .GAMUT_REMAP_C21_C22 = 0x1c5c, .GAMUT_REMAP_C23_C24 = 0x1c5d
, .GAMUT_REMAP_C31_C32 = 0x1c5e, .GAMUT_REMAP_C33_C34 = 0x1c5f
, .OUTPUT_CSC_C11_C12 = 0x1c3d, .OUTPUT_CSC_C13_C14 = 0x1c3e,
.OUTPUT_CSC_C21_C22 = 0x1c3f, .OUTPUT_CSC_C23_C24 = 0x1c40, .
OUTPUT_CSC_C31_C32 = 0x1c41, .OUTPUT_CSC_C33_C34 = 0x1c42, .OUTPUT_CSC_CONTROL
= 0x1c3c, .REGAMMA_CNTLA_START_CNTL = 0x1ca4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x1ca5, .REGAMMA_CNTLA_END_CNTL1 = 0x1ca6, .REGAMMA_CNTLA_END_CNTL2
= 0x1ca7, .REGAMMA_CNTLA_REGION_0_1 = 0x1ca8, .REGAMMA_CNTLA_REGION_2_3
= 0x1ca9, .REGAMMA_CNTLA_REGION_4_5 = 0x1caa, .REGAMMA_CNTLA_REGION_6_7
= 0x1cab, .REGAMMA_CNTLA_REGION_8_9 = 0x1cac, .REGAMMA_CNTLA_REGION_10_11
= 0x1cad, .REGAMMA_CNTLA_REGION_12_13 = 0x1cae, .REGAMMA_CNTLA_REGION_14_15
= 0x1caf, .REGAMMA_LUT_WRITE_EN_MASK = 0x1ca3, .REGAMMA_LUT_INDEX
= 0x1ca1, .REGAMMA_LUT_DATA = 0x1ca2, .REGAMMA_CONTROL = 0x1ca0
, .DENORM_CONTROL = 0x1c50, .DCP_SPATIAL_DITHER_CNTL = 0x1c60
, .OUT_ROUND_CONTROL = 0x1c51, .OUT_CLAMP_CONTROL_R_CR = 0x1c52
, .OUT_CLAMP_CONTROL_G_Y = 0x1c9c, .OUT_CLAMP_CONTROL_B_CB = 0x1c9d
, .SCL_MODE = 0x1d42, .SCL_TAP_CONTROL = 0x1d43, .SCL_CONTROL
= 0x1d44, .SCL_BYPASS_CONTROL = 0x1d45, .EXT_OVERSCAN_LEFT_RIGHT
= 0x1d5e, .EXT_OVERSCAN_TOP_BOTTOM = 0x1d5f, .SCL_VERT_FILTER_CONTROL
= 0x1d4b, .SCL_HORZ_FILTER_CONTROL = 0x1d48, .SCL_COEF_RAM_SELECT
= 0x1d40, .SCL_COEF_RAM_TAP_DATA = 0x1d41, .VIEWPORT_START =
0x1d5c, .VIEWPORT_SIZE = 0x1d5d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x1d49, .SCL_VERT_FILTER_SCALE_RATIO = 0x1d4c, .SCL_HORZ_FILTER_INIT
= 0x1d4a, .SCL_VERT_FILTER_INIT = 0x1d4d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x1d47, .LB_MEMORY_CTRL = 0x1cc1, .SCL_UPDATE = 0x1d51, .SCL_F_SHARP_CONTROL
= 0x1d53, .DCFE_MEM_PWR_CTRL = 0x1d03, .DCFE_MEM_PWR_STATUS =
0x1d05},
214 transform_regs(2)[2] = { .LB_DATA_FORMAT = 0x1ec0, .GAMUT_REMAP_CONTROL = 0x1e59
, .GAMUT_REMAP_C11_C12 = 0x1e5a, .GAMUT_REMAP_C13_C14 = 0x1e5b
, .GAMUT_REMAP_C21_C22 = 0x1e5c, .GAMUT_REMAP_C23_C24 = 0x1e5d
, .GAMUT_REMAP_C31_C32 = 0x1e5e, .GAMUT_REMAP_C33_C34 = 0x1e5f
, .OUTPUT_CSC_C11_C12 = 0x1e3d, .OUTPUT_CSC_C13_C14 = 0x1e3e,
.OUTPUT_CSC_C21_C22 = 0x1e3f, .OUTPUT_CSC_C23_C24 = 0x1e40, .
OUTPUT_CSC_C31_C32 = 0x1e41, .OUTPUT_CSC_C33_C34 = 0x1e42, .OUTPUT_CSC_CONTROL
= 0x1e3c, .REGAMMA_CNTLA_START_CNTL = 0x1ea4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x1ea5, .REGAMMA_CNTLA_END_CNTL1 = 0x1ea6, .REGAMMA_CNTLA_END_CNTL2
= 0x1ea7, .REGAMMA_CNTLA_REGION_0_1 = 0x1ea8, .REGAMMA_CNTLA_REGION_2_3
= 0x1ea9, .REGAMMA_CNTLA_REGION_4_5 = 0x1eaa, .REGAMMA_CNTLA_REGION_6_7
= 0x1eab, .REGAMMA_CNTLA_REGION_8_9 = 0x1eac, .REGAMMA_CNTLA_REGION_10_11
= 0x1ead, .REGAMMA_CNTLA_REGION_12_13 = 0x1eae, .REGAMMA_CNTLA_REGION_14_15
= 0x1eaf, .REGAMMA_LUT_WRITE_EN_MASK = 0x1ea3, .REGAMMA_LUT_INDEX
= 0x1ea1, .REGAMMA_LUT_DATA = 0x1ea2, .REGAMMA_CONTROL = 0x1ea0
, .DENORM_CONTROL = 0x1e50, .DCP_SPATIAL_DITHER_CNTL = 0x1e60
, .OUT_ROUND_CONTROL = 0x1e51, .OUT_CLAMP_CONTROL_R_CR = 0x1e52
, .OUT_CLAMP_CONTROL_G_Y = 0x1e9c, .OUT_CLAMP_CONTROL_B_CB = 0x1e9d
, .SCL_MODE = 0x1f42, .SCL_TAP_CONTROL = 0x1f43, .SCL_CONTROL
= 0x1f44, .SCL_BYPASS_CONTROL = 0x1f45, .EXT_OVERSCAN_LEFT_RIGHT
= 0x1f5e, .EXT_OVERSCAN_TOP_BOTTOM = 0x1f5f, .SCL_VERT_FILTER_CONTROL
= 0x1f4b, .SCL_HORZ_FILTER_CONTROL = 0x1f48, .SCL_COEF_RAM_SELECT
= 0x1f40, .SCL_COEF_RAM_TAP_DATA = 0x1f41, .VIEWPORT_START =
0x1f5c, .VIEWPORT_SIZE = 0x1f5d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x1f49, .SCL_VERT_FILTER_SCALE_RATIO = 0x1f4c, .SCL_HORZ_FILTER_INIT
= 0x1f4a, .SCL_VERT_FILTER_INIT = 0x1f4d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x1f47, .LB_MEMORY_CTRL = 0x1ec1, .SCL_UPDATE = 0x1f51, .SCL_F_SHARP_CONTROL
= 0x1f53, .DCFE_MEM_PWR_CTRL = 0x1f03, .DCFE_MEM_PWR_STATUS =
0x1f05},
215 transform_regs(3)[3] = { .LB_DATA_FORMAT = 0x40c0, .GAMUT_REMAP_CONTROL = 0x4059
, .GAMUT_REMAP_C11_C12 = 0x405a, .GAMUT_REMAP_C13_C14 = 0x405b
, .GAMUT_REMAP_C21_C22 = 0x405c, .GAMUT_REMAP_C23_C24 = 0x405d
, .GAMUT_REMAP_C31_C32 = 0x405e, .GAMUT_REMAP_C33_C34 = 0x405f
, .OUTPUT_CSC_C11_C12 = 0x403d, .OUTPUT_CSC_C13_C14 = 0x403e,
.OUTPUT_CSC_C21_C22 = 0x403f, .OUTPUT_CSC_C23_C24 = 0x4040, .
OUTPUT_CSC_C31_C32 = 0x4041, .OUTPUT_CSC_C33_C34 = 0x4042, .OUTPUT_CSC_CONTROL
= 0x403c, .REGAMMA_CNTLA_START_CNTL = 0x40a4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x40a5, .REGAMMA_CNTLA_END_CNTL1 = 0x40a6, .REGAMMA_CNTLA_END_CNTL2
= 0x40a7, .REGAMMA_CNTLA_REGION_0_1 = 0x40a8, .REGAMMA_CNTLA_REGION_2_3
= 0x40a9, .REGAMMA_CNTLA_REGION_4_5 = 0x40aa, .REGAMMA_CNTLA_REGION_6_7
= 0x40ab, .REGAMMA_CNTLA_REGION_8_9 = 0x40ac, .REGAMMA_CNTLA_REGION_10_11
= 0x40ad, .REGAMMA_CNTLA_REGION_12_13 = 0x40ae, .REGAMMA_CNTLA_REGION_14_15
= 0x40af, .REGAMMA_LUT_WRITE_EN_MASK = 0x40a3, .REGAMMA_LUT_INDEX
= 0x40a1, .REGAMMA_LUT_DATA = 0x40a2, .REGAMMA_CONTROL = 0x40a0
, .DENORM_CONTROL = 0x4050, .DCP_SPATIAL_DITHER_CNTL = 0x4060
, .OUT_ROUND_CONTROL = 0x4051, .OUT_CLAMP_CONTROL_R_CR = 0x4052
, .OUT_CLAMP_CONTROL_G_Y = 0x409c, .OUT_CLAMP_CONTROL_B_CB = 0x409d
, .SCL_MODE = 0x4142, .SCL_TAP_CONTROL = 0x4143, .SCL_CONTROL
= 0x4144, .SCL_BYPASS_CONTROL = 0x4145, .EXT_OVERSCAN_LEFT_RIGHT
= 0x415e, .EXT_OVERSCAN_TOP_BOTTOM = 0x415f, .SCL_VERT_FILTER_CONTROL
= 0x414b, .SCL_HORZ_FILTER_CONTROL = 0x4148, .SCL_COEF_RAM_SELECT
= 0x4140, .SCL_COEF_RAM_TAP_DATA = 0x4141, .VIEWPORT_START =
0x415c, .VIEWPORT_SIZE = 0x415d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x4149, .SCL_VERT_FILTER_SCALE_RATIO = 0x414c, .SCL_HORZ_FILTER_INIT
= 0x414a, .SCL_VERT_FILTER_INIT = 0x414d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x4147, .LB_MEMORY_CTRL = 0x40c1, .SCL_UPDATE = 0x4151, .SCL_F_SHARP_CONTROL
= 0x4153, .DCFE_MEM_PWR_CTRL = 0x4103, .DCFE_MEM_PWR_STATUS =
0x4105},
216 transform_regs(4)[4] = { .LB_DATA_FORMAT = 0x42c0, .GAMUT_REMAP_CONTROL = 0x4259
, .GAMUT_REMAP_C11_C12 = 0x425a, .GAMUT_REMAP_C13_C14 = 0x425b
, .GAMUT_REMAP_C21_C22 = 0x425c, .GAMUT_REMAP_C23_C24 = 0x425d
, .GAMUT_REMAP_C31_C32 = 0x425e, .GAMUT_REMAP_C33_C34 = 0x425f
, .OUTPUT_CSC_C11_C12 = 0x423d, .OUTPUT_CSC_C13_C14 = 0x423e,
.OUTPUT_CSC_C21_C22 = 0x423f, .OUTPUT_CSC_C23_C24 = 0x4240, .
OUTPUT_CSC_C31_C32 = 0x4241, .OUTPUT_CSC_C33_C34 = 0x4242, .OUTPUT_CSC_CONTROL
= 0x423c, .REGAMMA_CNTLA_START_CNTL = 0x42a4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x42a5, .REGAMMA_CNTLA_END_CNTL1 = 0x42a6, .REGAMMA_CNTLA_END_CNTL2
= 0x42a7, .REGAMMA_CNTLA_REGION_0_1 = 0x42a8, .REGAMMA_CNTLA_REGION_2_3
= 0x42a9, .REGAMMA_CNTLA_REGION_4_5 = 0x42aa, .REGAMMA_CNTLA_REGION_6_7
= 0x42ab, .REGAMMA_CNTLA_REGION_8_9 = 0x42ac, .REGAMMA_CNTLA_REGION_10_11
= 0x42ad, .REGAMMA_CNTLA_REGION_12_13 = 0x42ae, .REGAMMA_CNTLA_REGION_14_15
= 0x42af, .REGAMMA_LUT_WRITE_EN_MASK = 0x42a3, .REGAMMA_LUT_INDEX
= 0x42a1, .REGAMMA_LUT_DATA = 0x42a2, .REGAMMA_CONTROL = 0x42a0
, .DENORM_CONTROL = 0x4250, .DCP_SPATIAL_DITHER_CNTL = 0x4260
, .OUT_ROUND_CONTROL = 0x4251, .OUT_CLAMP_CONTROL_R_CR = 0x4252
, .OUT_CLAMP_CONTROL_G_Y = 0x429c, .OUT_CLAMP_CONTROL_B_CB = 0x429d
, .SCL_MODE = 0x4342, .SCL_TAP_CONTROL = 0x4343, .SCL_CONTROL
= 0x4344, .SCL_BYPASS_CONTROL = 0x4345, .EXT_OVERSCAN_LEFT_RIGHT
= 0x435e, .EXT_OVERSCAN_TOP_BOTTOM = 0x435f, .SCL_VERT_FILTER_CONTROL
= 0x434b, .SCL_HORZ_FILTER_CONTROL = 0x4348, .SCL_COEF_RAM_SELECT
= 0x4340, .SCL_COEF_RAM_TAP_DATA = 0x4341, .VIEWPORT_START =
0x435c, .VIEWPORT_SIZE = 0x435d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x4349, .SCL_VERT_FILTER_SCALE_RATIO = 0x434c, .SCL_HORZ_FILTER_INIT
= 0x434a, .SCL_VERT_FILTER_INIT = 0x434d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x4347, .LB_MEMORY_CTRL = 0x42c1, .SCL_UPDATE = 0x4351, .SCL_F_SHARP_CONTROL
= 0x4353, .DCFE_MEM_PWR_CTRL = 0x4303, .DCFE_MEM_PWR_STATUS =
0x4305},
217 transform_regs(5)[5] = { .LB_DATA_FORMAT = 0x44c0, .GAMUT_REMAP_CONTROL = 0x4459
, .GAMUT_REMAP_C11_C12 = 0x445a, .GAMUT_REMAP_C13_C14 = 0x445b
, .GAMUT_REMAP_C21_C22 = 0x445c, .GAMUT_REMAP_C23_C24 = 0x445d
, .GAMUT_REMAP_C31_C32 = 0x445e, .GAMUT_REMAP_C33_C34 = 0x445f
, .OUTPUT_CSC_C11_C12 = 0x443d, .OUTPUT_CSC_C13_C14 = 0x443e,
.OUTPUT_CSC_C21_C22 = 0x443f, .OUTPUT_CSC_C23_C24 = 0x4440, .
OUTPUT_CSC_C31_C32 = 0x4441, .OUTPUT_CSC_C33_C34 = 0x4442, .OUTPUT_CSC_CONTROL
= 0x443c, .REGAMMA_CNTLA_START_CNTL = 0x44a4, .REGAMMA_CNTLA_SLOPE_CNTL
= 0x44a5, .REGAMMA_CNTLA_END_CNTL1 = 0x44a6, .REGAMMA_CNTLA_END_CNTL2
= 0x44a7, .REGAMMA_CNTLA_REGION_0_1 = 0x44a8, .REGAMMA_CNTLA_REGION_2_3
= 0x44a9, .REGAMMA_CNTLA_REGION_4_5 = 0x44aa, .REGAMMA_CNTLA_REGION_6_7
= 0x44ab, .REGAMMA_CNTLA_REGION_8_9 = 0x44ac, .REGAMMA_CNTLA_REGION_10_11
= 0x44ad, .REGAMMA_CNTLA_REGION_12_13 = 0x44ae, .REGAMMA_CNTLA_REGION_14_15
= 0x44af, .REGAMMA_LUT_WRITE_EN_MASK = 0x44a3, .REGAMMA_LUT_INDEX
= 0x44a1, .REGAMMA_LUT_DATA = 0x44a2, .REGAMMA_CONTROL = 0x44a0
, .DENORM_CONTROL = 0x4450, .DCP_SPATIAL_DITHER_CNTL = 0x4460
, .OUT_ROUND_CONTROL = 0x4451, .OUT_CLAMP_CONTROL_R_CR = 0x4452
, .OUT_CLAMP_CONTROL_G_Y = 0x449c, .OUT_CLAMP_CONTROL_B_CB = 0x449d
, .SCL_MODE = 0x4542, .SCL_TAP_CONTROL = 0x4543, .SCL_CONTROL
= 0x4544, .SCL_BYPASS_CONTROL = 0x4545, .EXT_OVERSCAN_LEFT_RIGHT
= 0x455e, .EXT_OVERSCAN_TOP_BOTTOM = 0x455f, .SCL_VERT_FILTER_CONTROL
= 0x454b, .SCL_HORZ_FILTER_CONTROL = 0x4548, .SCL_COEF_RAM_SELECT
= 0x4540, .SCL_COEF_RAM_TAP_DATA = 0x4541, .VIEWPORT_START =
0x455c, .VIEWPORT_SIZE = 0x455d, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x4549, .SCL_VERT_FILTER_SCALE_RATIO = 0x454c, .SCL_HORZ_FILTER_INIT
= 0x454a, .SCL_VERT_FILTER_INIT = 0x454d, .SCL_AUTOMATIC_MODE_CONTROL
= 0x4547, .LB_MEMORY_CTRL = 0x44c1, .SCL_UPDATE = 0x4551, .SCL_F_SHARP_CONTROL
= 0x4553, .DCFE_MEM_PWR_CTRL = 0x4503, .DCFE_MEM_PWR_STATUS =
0x4505}
218};
219
220static const struct dce_transform_shift xfm_shift = {
221 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT).OUT_CLAMP_MIN_B_CB = 0x10, .OUT_CLAMP_MAX_B_CB = 0x0, .OUT_CLAMP_MIN_G_Y
= 0x10, .OUT_CLAMP_MAX_G_Y = 0x0, .OUT_CLAMP_MIN_R_CR = 0x10
, .OUT_CLAMP_MAX_R_CR = 0x0, .OUT_ROUND_TRUNC_MODE = 0x0, .DCP_SPATIAL_DITHER_EN
= 0x0, .DCP_SPATIAL_DITHER_MODE = 0x4, .DCP_SPATIAL_DITHER_DEPTH
= 0x6, .DCP_FRAME_RANDOM_ENABLE = 0x8, .DCP_RGB_RANDOM_ENABLE
= 0x9, .DCP_HIGHPASS_RANDOM_ENABLE = 0xa, .DENORM_MODE = 0x0
, .PIXEL_DEPTH = 0x0, .PIXEL_EXPAN_MODE = 0x2, .GAMUT_REMAP_C11
= 0x0, .GAMUT_REMAP_C12 = 0x10, .GAMUT_REMAP_C13 = 0x0, .GAMUT_REMAP_C14
= 0x10, .GAMUT_REMAP_C21 = 0x0, .GAMUT_REMAP_C22 = 0x10, .GAMUT_REMAP_C23
= 0x0, .GAMUT_REMAP_C24 = 0x10, .GAMUT_REMAP_C31 = 0x0, .GAMUT_REMAP_C32
= 0x10, .GAMUT_REMAP_C33 = 0x0, .GAMUT_REMAP_C34 = 0x10, .GRPH_GAMUT_REMAP_MODE
= 0x0, .OUTPUT_CSC_C11 = 0x0, .OUTPUT_CSC_C12 = 0x10, .OUTPUT_CSC_GRPH_MODE
= 0x0, .REGAMMA_CNTLA_EXP_REGION_START = 0x0, .REGAMMA_CNTLA_EXP_REGION_START_SEGMENT
= 0x14, .REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE = 0x0, .REGAMMA_CNTLA_EXP_REGION_END
= 0x0, .REGAMMA_CNTLA_EXP_REGION_END_BASE = 0x10, .REGAMMA_CNTLA_EXP_REGION_END_SLOPE
= 0x0, .REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET = 0x0, .REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS
= 0xc, .REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET = 0x10, .REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .REGAMMA_LUT_WRITE_EN_MASK = 0x0, .GRPH_REGAMMA_MODE
= 0x0, .SCL_MODE = 0x0, .SCL_H_NUM_OF_TAPS = 0x8, .SCL_V_NUM_OF_TAPS
= 0x0, .SCL_BOUNDARY_MODE = 0x0, .SCL_BYPASS_MODE = 0x0, .EXT_OVERSCAN_LEFT
= 0x10, .EXT_OVERSCAN_RIGHT = 0x0, .EXT_OVERSCAN_TOP = 0x10,
.EXT_OVERSCAN_BOTTOM = 0x0, .SCL_C_RAM_FILTER_TYPE = 0x10, .
SCL_C_RAM_PHASE = 0x8, .SCL_C_RAM_TAP_PAIR_IDX = 0x0, .SCL_C_RAM_EVEN_TAP_COEF_EN
= 0xf, .SCL_C_RAM_EVEN_TAP_COEF = 0x0, .SCL_C_RAM_ODD_TAP_COEF_EN
= 0x1f, .SCL_C_RAM_ODD_TAP_COEF = 0x10, .VIEWPORT_X_START = 0x10
, .VIEWPORT_Y_START = 0x0, .VIEWPORT_HEIGHT = 0x0, .VIEWPORT_WIDTH
= 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO = 0x0, .
SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC = 0x0, .SCL_V_INIT_INT
= 0x18, .SCL_V_INIT_FRAC = 0x0, .LB_MEMORY_CONFIG = 0x14, .LB_MEMORY_SIZE
= 0x0, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x8, .SCL_H_2TAP_HARDCODE_COEF_EN
= 0x8, .SCL_COEF_UPDATE_COMPLETE = 0x18, .ALPHA_EN = 0x1f, .
SCL_COEFF_MEM_PWR_DIS = 0x8, .SCL_COEFF_MEM_PWR_STATE = 0x4, .
DCP_REGAMMA_MEM_PWR_DIS = 0x5, .DCP_LUT_MEM_PWR_DIS = 0x2, .DCP_REGAMMA_MEM_PWR_STATE
= 0x2, .SCL_PSCL_EN = 0x4
222};
223
224static const struct dce_transform_mask xfm_mask = {
225 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK).OUT_CLAMP_MIN_B_CB = 0x3fff0000, .OUT_CLAMP_MAX_B_CB = 0x3fff
, .OUT_CLAMP_MIN_G_Y = 0x3fff0000, .OUT_CLAMP_MAX_G_Y = 0x3fff
, .OUT_CLAMP_MIN_R_CR = 0x3fff0000, .OUT_CLAMP_MAX_R_CR = 0x3fff
, .OUT_ROUND_TRUNC_MODE = 0xf, .DCP_SPATIAL_DITHER_EN = 0x1, .
DCP_SPATIAL_DITHER_MODE = 0x30, .DCP_SPATIAL_DITHER_DEPTH = 0xc0
, .DCP_FRAME_RANDOM_ENABLE = 0x100, .DCP_RGB_RANDOM_ENABLE = 0x200
, .DCP_HIGHPASS_RANDOM_ENABLE = 0x400, .DENORM_MODE = 0x7, .PIXEL_DEPTH
= 0x3, .PIXEL_EXPAN_MODE = 0x4, .GAMUT_REMAP_C11 = 0xffff, .
GAMUT_REMAP_C12 = 0xffff0000, .GAMUT_REMAP_C13 = 0xffff, .GAMUT_REMAP_C14
= 0xffff0000, .GAMUT_REMAP_C21 = 0xffff, .GAMUT_REMAP_C22 = 0xffff0000
, .GAMUT_REMAP_C23 = 0xffff, .GAMUT_REMAP_C24 = 0xffff0000, .
GAMUT_REMAP_C31 = 0xffff, .GAMUT_REMAP_C32 = 0xffff0000, .GAMUT_REMAP_C33
= 0xffff, .GAMUT_REMAP_C34 = 0xffff0000, .GRPH_GAMUT_REMAP_MODE
= 0x3, .OUTPUT_CSC_C11 = 0xffff, .OUTPUT_CSC_C12 = 0xffff0000
, .OUTPUT_CSC_GRPH_MODE = 0x7, .REGAMMA_CNTLA_EXP_REGION_START
= 0x3ffff, .REGAMMA_CNTLA_EXP_REGION_START_SEGMENT = 0x7f00000
, .REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE = 0x3ffff, .REGAMMA_CNTLA_EXP_REGION_END
= 0xffff, .REGAMMA_CNTLA_EXP_REGION_END_BASE = 0xffff0000, .
REGAMMA_CNTLA_EXP_REGION_END_SLOPE = 0xffff, .REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET
= 0x1ff, .REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS = 0x7000, .
REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET = 0x1ff0000, .REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS
= 0x70000000, .REGAMMA_LUT_WRITE_EN_MASK = 0x7, .GRPH_REGAMMA_MODE
= 0x7, .SCL_MODE = 0x3, .SCL_H_NUM_OF_TAPS = 0xf00, .SCL_V_NUM_OF_TAPS
= 0x7, .SCL_BOUNDARY_MODE = 0x1, .SCL_BYPASS_MODE = 0x3, .EXT_OVERSCAN_LEFT
= 0x1fff0000, .EXT_OVERSCAN_RIGHT = 0x1fff, .EXT_OVERSCAN_TOP
= 0x1fff0000, .EXT_OVERSCAN_BOTTOM = 0x1fff, .SCL_C_RAM_FILTER_TYPE
= 0x70000, .SCL_C_RAM_PHASE = 0xf00, .SCL_C_RAM_TAP_PAIR_IDX
= 0xf, .SCL_C_RAM_EVEN_TAP_COEF_EN = 0x8000, .SCL_C_RAM_EVEN_TAP_COEF
= 0x3fff, .SCL_C_RAM_ODD_TAP_COEF_EN = 0x80000000, .SCL_C_RAM_ODD_TAP_COEF
= 0x3fff0000, .VIEWPORT_X_START = 0x3fff0000, .VIEWPORT_Y_START
= 0x3fff, .VIEWPORT_HEIGHT = 0x3fff, .VIEWPORT_WIDTH = 0x3fff0000
, .SCL_H_SCALE_RATIO = 0x3ffffff, .SCL_V_SCALE_RATIO = 0x3ffffff
, .SCL_H_INIT_INT = 0xf000000, .SCL_H_INIT_FRAC = 0xffffff, .
SCL_V_INIT_INT = 0x7000000, .SCL_V_INIT_FRAC = 0xffffff, .LB_MEMORY_CONFIG
= 0x300000, .LB_MEMORY_SIZE = 0x1fff, .SCL_V_2TAP_HARDCODE_COEF_EN
= 0x100, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x100, .SCL_COEF_UPDATE_COMPLETE
= 0x1000000, .ALPHA_EN = 0x80000000, .SCL_COEFF_MEM_PWR_DIS =
0x100, .SCL_COEFF_MEM_PWR_STATE = 0x30, .DCP_REGAMMA_MEM_PWR_DIS
= 0x20, .DCP_LUT_MEM_PWR_DIS = 0x4, .DCP_REGAMMA_MEM_PWR_STATE
= 0xc, .SCL_PSCL_EN = 0x10
226};
227
228#define aux_regs(id)[id] = { .AUX_CONTROL = mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0
= mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = mmDP_AUXid_AUX_DPHY_RX_CONTROL1
}\
229[id] = {\
230 AUX_REG_LIST(id).AUX_CONTROL = mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 =
mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = mmDP_AUXid_AUX_DPHY_RX_CONTROL1\
231}
232
233static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 aux_regs(0)[0] = { .AUX_CONTROL = 0x5c00, .AUX_DPHY_RX_CONTROL0 = 0x5c0a
, .AUX_DPHY_RX_CONTROL1 = 0x5c0b},
235 aux_regs(1)[1] = { .AUX_CONTROL = 0x5c1c, .AUX_DPHY_RX_CONTROL0 = 0x5c26
, .AUX_DPHY_RX_CONTROL1 = 0x5c27},
236 aux_regs(2)[2] = { .AUX_CONTROL = 0x5c38, .AUX_DPHY_RX_CONTROL0 = 0x5c42
, .AUX_DPHY_RX_CONTROL1 = 0x5c43},
237 aux_regs(3)[3] = { .AUX_CONTROL = 0x5c54, .AUX_DPHY_RX_CONTROL0 = 0x5c5e
, .AUX_DPHY_RX_CONTROL1 = 0x5c5f},
238 aux_regs(4)[4] = { .AUX_CONTROL = 0x5c70, .AUX_DPHY_RX_CONTROL0 = 0x5c7a
, .AUX_DPHY_RX_CONTROL1 = 0x5c7b},
239 aux_regs(5)[5] = { .AUX_CONTROL = 0x5c8c, .AUX_DPHY_RX_CONTROL0 = 0x5c96
, .AUX_DPHY_RX_CONTROL1 = 0x5c97}
240};
241
242static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
243 { DCE_PANEL_CNTL_REG_LIST().PWRSEQ_CNTL = 0x481b, .PWRSEQ_STATE = 0x481c, .PWRSEQ_REF_DIV
= 0x481d, .BL_PWM_CNTL = 0x4820, .BL_PWM_CNTL2 = 0x4821, .BL_PWM_PERIOD_CNTL
= 0x4822, .BL_PWM_GRP1_REG_LOCK = 0x4823, .BIOS_SCRATCH_2 = 0x05CB }
244};
245
246static const struct dce_panel_cntl_shift panel_cntl_shift = {
247 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT).LVTMA_BLON = 0x18, .LVTMA_BLON_OVRD = 0x19, .LVTMA_DIGON = 0x10
, .LVTMA_DIGON_OVRD = 0x11, .LVTMA_PWRSEQ_TARGET_STATE = 0x4,
.LVTMA_PWRSEQ_TARGET_STATE_R = 0x0, .BL_PWM_REF_DIV = 0x10, .
BL_PWM_PERIOD = 0x0, .BL_PWM_PERIOD_BITCNT = 0x10, .BL_ACTIVE_INT_FRAC_CNT
= 0x0, .BL_PWM_FRACTIONAL_EN = 0x1e, .BL_PWM_EN = 0x1f, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN
= 0x1f, .BL_PWM_GRP1_REG_LOCK = 0x0, .BL_PWM_GRP1_REG_UPDATE_PENDING
= 0x8
248};
249
250static const struct dce_panel_cntl_mask panel_cntl_mask = {
251 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK).LVTMA_BLON = 0x1000000, .LVTMA_BLON_OVRD = 0x2000000, .LVTMA_DIGON
= 0x10000, .LVTMA_DIGON_OVRD = 0x20000, .LVTMA_PWRSEQ_TARGET_STATE
= 0x10, .LVTMA_PWRSEQ_TARGET_STATE_R = 0x1, .BL_PWM_REF_DIV =
0xffff0000, .BL_PWM_PERIOD = 0xffff, .BL_PWM_PERIOD_BITCNT =
0xf0000, .BL_ACTIVE_INT_FRAC_CNT = 0xffff, .BL_PWM_FRACTIONAL_EN
= 0x40000000, .BL_PWM_EN = 0x80000000, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN
= 0x80000000, .BL_PWM_GRP1_REG_LOCK = 0x1, .BL_PWM_GRP1_REG_UPDATE_PENDING
= 0x100
252};
253
254#define hpd_regs(id)[id] = { .DC_HPD_CONTROL = mmHPDid_DC_HPD_CONTROL}\
255[id] = {\
256 HPD_REG_LIST(id).DC_HPD_CONTROL = mmHPDid_DC_HPD_CONTROL\
257}
258
259static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
260 hpd_regs(0)[0] = { .DC_HPD_CONTROL = 0x189a},
261 hpd_regs(1)[1] = { .DC_HPD_CONTROL = 0x18a2},
262 hpd_regs(2)[2] = { .DC_HPD_CONTROL = 0x18aa},
263 hpd_regs(3)[3] = { .DC_HPD_CONTROL = 0x18b2},
264 hpd_regs(4)[4] = { .DC_HPD_CONTROL = 0x18ba},
265 hpd_regs(5)[5] = { .DC_HPD_CONTROL = 0x18c2}
266};
267
268#define link_regs(id)[id] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL =
0x160f, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK
= 0x1616, .DIG_BE_CNTL = mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL
= mmDIGid_DIG_BE_EN_CNTL, .DP_CONFIG = mmDPid_DP_CONFIG, .DP_DPHY_CNTL
= mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = mmDPid_DP_DPHY_PRBS_CNTL
, .DP_DPHY_SCRAM_CNTL = mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0
= mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = mmDPid_DP_DPHY_SYM1, .
DP_DPHY_SYM2 = mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL
= mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = mmDPid_DP_LINK_CNTL
, .DP_LINK_FRAMING_CNTL = mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0
= mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2
= mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = mmDPid_DP_MSE_SAT_UPDATE
, .DP_SEC_CNTL = mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = mmDPid_DP_VID_STREAM_CNTL
, .DP_DPHY_FAST_TRAINING = mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1
= mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = mmDPid_DP_DPHY_BS_SR_SWAP_CNTL
, .DP_DPHY_INTERNAL_CTRL = mmDPid_DP_DPHY_INTERNAL_CTRL, .DP_DPHY_HBR2_PATTERN_CONTROL
= mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .DCI_MEM_PWR_STATUS =
0x317}\
269[id] = {\
270 LE_DCE110_REG_LIST(id).DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f, .
DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK = 0x1616
, .DIG_BE_CNTL = mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = mmDIGid_DIG_BE_EN_CNTL
, .DP_CONFIG = mmDPid_DP_CONFIG, .DP_DPHY_CNTL = mmDPid_DP_DPHY_CNTL
, .DP_DPHY_PRBS_CNTL = mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL
= mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = mmDPid_DP_DPHY_SYM0
, .DP_DPHY_SYM1 = mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = mmDPid_DP_DPHY_SYM2
, .DP_DPHY_TRAINING_PATTERN_SEL = mmDPid_DP_DPHY_TRAINING_PATTERN_SEL
, .DP_LINK_CNTL = mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL =
mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = mmDPid_DP_MSE_SAT0
, .DP_MSE_SAT1 = mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = mmDPid_DP_MSE_SAT2
, .DP_MSE_SAT_UPDATE = mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL
= mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = mmDPid_DP_VID_STREAM_CNTL
, .DP_DPHY_FAST_TRAINING = mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1
= mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = mmDPid_DP_DPHY_BS_SR_SWAP_CNTL
, .DP_DPHY_INTERNAL_CTRL = mmDPid_DP_DPHY_INTERNAL_CTRL, .DP_DPHY_HBR2_PATTERN_CONTROL
= mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .DCI_MEM_PWR_STATUS =
0x317\
271}
272
273static const struct dce110_link_enc_registers link_enc_regs[] = {
274 link_regs(0)[0] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4a47, .DIG_BE_EN_CNTL = 0x4a48, .DP_CONFIG
= 0x4aa3, .DP_DPHY_CNTL = 0x4aaf, .DP_DPHY_PRBS_CNTL = 0x4ab5
, .DP_DPHY_SCRAM_CNTL = 0x4ab6, .DP_DPHY_SYM0 = 0x4ab1, .DP_DPHY_SYM1
= 0x4ab2, .DP_DPHY_SYM2 = 0x4ab3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4ab0, .DP_LINK_CNTL = 0x4aa0, .DP_LINK_FRAMING_CNTL = 0x4aab
, .DP_MSE_SAT0 = 0x4ad2, .DP_MSE_SAT1 = 0x4ad3, .DP_MSE_SAT2 =
0x4ad4, .DP_MSE_SAT_UPDATE = 0x4ad5, .DP_SEC_CNTL = 0x4ac3, .
DP_VID_STREAM_CNTL = 0x4aa4, .DP_DPHY_FAST_TRAINING = 0x4abc,
.DP_SEC_CNTL1 = 0x4ac4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4adc, .
DP_DPHY_INTERNAL_CTRL = 0x4aa7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4add, .DCI_MEM_PWR_STATUS = 0x317},
275 link_regs(1)[1] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4b47, .DIG_BE_EN_CNTL = 0x4b48, .DP_CONFIG
= 0x4ba3, .DP_DPHY_CNTL = 0x4baf, .DP_DPHY_PRBS_CNTL = 0x4bb5
, .DP_DPHY_SCRAM_CNTL = 0x4bb6, .DP_DPHY_SYM0 = 0x4bb1, .DP_DPHY_SYM1
= 0x4bb2, .DP_DPHY_SYM2 = 0x4bb3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4bb0, .DP_LINK_CNTL = 0x4ba0, .DP_LINK_FRAMING_CNTL = 0x4bab
, .DP_MSE_SAT0 = 0x4bd2, .DP_MSE_SAT1 = 0x4bd3, .DP_MSE_SAT2 =
0x4bd4, .DP_MSE_SAT_UPDATE = 0x4bd5, .DP_SEC_CNTL = 0x4bc3, .
DP_VID_STREAM_CNTL = 0x4ba4, .DP_DPHY_FAST_TRAINING = 0x4bbc,
.DP_SEC_CNTL1 = 0x4bc4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4bdc, .
DP_DPHY_INTERNAL_CTRL = 0x4ba7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4bdd, .DCI_MEM_PWR_STATUS = 0x317},
276 link_regs(2)[2] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4c47, .DIG_BE_EN_CNTL = 0x4c48, .DP_CONFIG
= 0x4ca3, .DP_DPHY_CNTL = 0x4caf, .DP_DPHY_PRBS_CNTL = 0x4cb5
, .DP_DPHY_SCRAM_CNTL = 0x4cb6, .DP_DPHY_SYM0 = 0x4cb1, .DP_DPHY_SYM1
= 0x4cb2, .DP_DPHY_SYM2 = 0x4cb3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4cb0, .DP_LINK_CNTL = 0x4ca0, .DP_LINK_FRAMING_CNTL = 0x4cab
, .DP_MSE_SAT0 = 0x4cd2, .DP_MSE_SAT1 = 0x4cd3, .DP_MSE_SAT2 =
0x4cd4, .DP_MSE_SAT_UPDATE = 0x4cd5, .DP_SEC_CNTL = 0x4cc3, .
DP_VID_STREAM_CNTL = 0x4ca4, .DP_DPHY_FAST_TRAINING = 0x4cbc,
.DP_SEC_CNTL1 = 0x4cc4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4cdc, .
DP_DPHY_INTERNAL_CTRL = 0x4ca7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4cdd, .DCI_MEM_PWR_STATUS = 0x317},
277 link_regs(3)[3] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4d47, .DIG_BE_EN_CNTL = 0x4d48, .DP_CONFIG
= 0x4da3, .DP_DPHY_CNTL = 0x4daf, .DP_DPHY_PRBS_CNTL = 0x4db5
, .DP_DPHY_SCRAM_CNTL = 0x4db6, .DP_DPHY_SYM0 = 0x4db1, .DP_DPHY_SYM1
= 0x4db2, .DP_DPHY_SYM2 = 0x4db3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4db0, .DP_LINK_CNTL = 0x4da0, .DP_LINK_FRAMING_CNTL = 0x4dab
, .DP_MSE_SAT0 = 0x4dd2, .DP_MSE_SAT1 = 0x4dd3, .DP_MSE_SAT2 =
0x4dd4, .DP_MSE_SAT_UPDATE = 0x4dd5, .DP_SEC_CNTL = 0x4dc3, .
DP_VID_STREAM_CNTL = 0x4da4, .DP_DPHY_FAST_TRAINING = 0x4dbc,
.DP_SEC_CNTL1 = 0x4dc4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4ddc, .
DP_DPHY_INTERNAL_CTRL = 0x4da7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4ddd, .DCI_MEM_PWR_STATUS = 0x317},
278 link_regs(4)[4] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4e47, .DIG_BE_EN_CNTL = 0x4e48, .DP_CONFIG
= 0x4ea3, .DP_DPHY_CNTL = 0x4eaf, .DP_DPHY_PRBS_CNTL = 0x4eb5
, .DP_DPHY_SCRAM_CNTL = 0x4eb6, .DP_DPHY_SYM0 = 0x4eb1, .DP_DPHY_SYM1
= 0x4eb2, .DP_DPHY_SYM2 = 0x4eb3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4eb0, .DP_LINK_CNTL = 0x4ea0, .DP_LINK_FRAMING_CNTL = 0x4eab
, .DP_MSE_SAT0 = 0x4ed2, .DP_MSE_SAT1 = 0x4ed3, .DP_MSE_SAT2 =
0x4ed4, .DP_MSE_SAT_UPDATE = 0x4ed5, .DP_SEC_CNTL = 0x4ec3, .
DP_VID_STREAM_CNTL = 0x4ea4, .DP_DPHY_FAST_TRAINING = 0x4ebc,
.DP_SEC_CNTL1 = 0x4ec4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4edc, .
DP_DPHY_INTERNAL_CTRL = 0x4ea7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4edd, .DCI_MEM_PWR_STATUS = 0x317},
279 link_regs(5)[5] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x4f47, .DIG_BE_EN_CNTL = 0x4f48, .DP_CONFIG
= 0x4fa3, .DP_DPHY_CNTL = 0x4faf, .DP_DPHY_PRBS_CNTL = 0x4fb5
, .DP_DPHY_SCRAM_CNTL = 0x4fb6, .DP_DPHY_SYM0 = 0x4fb1, .DP_DPHY_SYM1
= 0x4fb2, .DP_DPHY_SYM2 = 0x4fb3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x4fb0, .DP_LINK_CNTL = 0x4fa0, .DP_LINK_FRAMING_CNTL = 0x4fab
, .DP_MSE_SAT0 = 0x4fd2, .DP_MSE_SAT1 = 0x4fd3, .DP_MSE_SAT2 =
0x4fd4, .DP_MSE_SAT_UPDATE = 0x4fd5, .DP_SEC_CNTL = 0x4fc3, .
DP_VID_STREAM_CNTL = 0x4fa4, .DP_DPHY_FAST_TRAINING = 0x4fbc,
.DP_SEC_CNTL1 = 0x4fc4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x4fdc, .
DP_DPHY_INTERNAL_CTRL = 0x4fa7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x4fdd, .DCI_MEM_PWR_STATUS = 0x317},
280 link_regs(6)[6] = { .DMCU_RAM_ACCESS_CTRL = 0x1608, .DMCU_IRAM_RD_CTRL = 0x160f
, .DMCU_IRAM_RD_DATA = 0x1610, .DMCU_INTERRUPT_TO_UC_EN_MASK =
0x1616, .DIG_BE_CNTL = 0x5447, .DIG_BE_EN_CNTL = 0x5448, .DP_CONFIG
= 0x54a3, .DP_DPHY_CNTL = 0x54af, .DP_DPHY_PRBS_CNTL = 0x54b5
, .DP_DPHY_SCRAM_CNTL = 0x54b6, .DP_DPHY_SYM0 = 0x54b1, .DP_DPHY_SYM1
= 0x54b2, .DP_DPHY_SYM2 = 0x54b3, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x54b0, .DP_LINK_CNTL = 0x54a0, .DP_LINK_FRAMING_CNTL = 0x54ab
, .DP_MSE_SAT0 = 0x54d2, .DP_MSE_SAT1 = 0x54d3, .DP_MSE_SAT2 =
0x54d4, .DP_MSE_SAT_UPDATE = 0x54d5, .DP_SEC_CNTL = 0x54c3, .
DP_VID_STREAM_CNTL = 0x54a4, .DP_DPHY_FAST_TRAINING = 0x54bc,
.DP_SEC_CNTL1 = 0x54c4, .DP_DPHY_BS_SR_SWAP_CNTL = 0x54dc, .
DP_DPHY_INTERNAL_CTRL = 0x54a7, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x54dd, .DCI_MEM_PWR_STATUS = 0x317},
281};
282
283#define stream_enc_regs(id)[id] = { .AFMT_GENERIC_0 = mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1
= mmDIGid_AFMT_GENERIC_1, .AFMT_GENERIC_2 = mmDIGid_AFMT_GENERIC_2
, .AFMT_GENERIC_3 = mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 =
mmDIGid_AFMT_GENERIC_4, .AFMT_GENERIC_5 = mmDIGid_AFMT_GENERIC_5
, .AFMT_GENERIC_6 = mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 =
mmDIGid_AFMT_GENERIC_7, .AFMT_GENERIC_HDR = mmDIGid_AFMT_GENERIC_HDR
, .AFMT_INFOFRAME_CONTROL0 = mmDIGid_AFMT_INFOFRAME_CONTROL0,
.AFMT_VBI_PACKET_CONTROL = mmDIGid_AFMT_VBI_PACKET_CONTROL, .
AFMT_AUDIO_PACKET_CONTROL = mmDIGid_AFMT_AUDIO_PACKET_CONTROL
, .AFMT_AUDIO_PACKET_CONTROL2 = mmDIGid_AFMT_AUDIO_PACKET_CONTROL2
, .AFMT_AUDIO_SRC_CONTROL = mmDIGid_AFMT_AUDIO_SRC_CONTROL, .
AFMT_60958_0 = mmDIGid_AFMT_60958_0, .AFMT_60958_1 = mmDIGid_AFMT_60958_1
, .AFMT_60958_2 = mmDIGid_AFMT_60958_2, .DIG_FE_CNTL = mmDIGid_DIG_FE_CNTL
, .HDMI_CONTROL = mmDIGid_HDMI_CONTROL, .HDMI_GC = mmDIGid_HDMI_GC
, .HDMI_GENERIC_PACKET_CONTROL0 = mmDIGid_HDMI_GENERIC_PACKET_CONTROL0
, .HDMI_GENERIC_PACKET_CONTROL1 = mmDIGid_HDMI_GENERIC_PACKET_CONTROL1
, .HDMI_INFOFRAME_CONTROL0 = mmDIGid_HDMI_INFOFRAME_CONTROL0,
.HDMI_INFOFRAME_CONTROL1 = mmDIGid_HDMI_INFOFRAME_CONTROL1, .
HDMI_VBI_PACKET_CONTROL = mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL
= mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL
= mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = mmDIGid_HDMI_ACR_32_0
, .HDMI_ACR_32_1 = mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = mmDIGid_HDMI_ACR_44_0
, .HDMI_ACR_44_1 = mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = mmDIGid_HDMI_ACR_48_0
, .HDMI_ACR_48_1 = mmDIGid_HDMI_ACR_48_1, .TMDS_CNTL = mmDIGid_TMDS_CNTL
, .DP_MSE_RATE_CNTL = mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE
= mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = mmDPid_DP_PIXEL_FORMAT
, .DP_SEC_CNTL = mmDPid_DP_SEC_CNTL, .DP_STEER_FIFO = mmDPid_DP_STEER_FIFO
, .DP_VID_M = mmDPid_DP_VID_M, .DP_VID_N = mmDPid_DP_VID_N, .
DP_VID_STREAM_CNTL = mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING
= mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = mmDPid_DP_SEC_AUD_N,
.DP_SEC_TIMESTAMP = mmDPid_DP_SEC_TIMESTAMP, .AFMT_AVI_INFO0
= mmDIGid_AFMT_AVI_INFO0, .AFMT_AVI_INFO1 = mmDIGid_AFMT_AVI_INFO1
, .AFMT_AVI_INFO2 = mmDIGid_AFMT_AVI_INFO2, .AFMT_AVI_INFO3 =
mmDIGid_AFMT_AVI_INFO3, .AFMT_CNTL = mmDIGid_AFMT_CNTL, .TMDS_CNTL
= 0,}\
284[id] = {\
285 SE_COMMON_REG_LIST(id).AFMT_GENERIC_0 = mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1 = mmDIGid_AFMT_GENERIC_1
, .AFMT_GENERIC_2 = mmDIGid_AFMT_GENERIC_2, .AFMT_GENERIC_3 =
mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 = mmDIGid_AFMT_GENERIC_4
, .AFMT_GENERIC_5 = mmDIGid_AFMT_GENERIC_5, .AFMT_GENERIC_6 =
mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 = mmDIGid_AFMT_GENERIC_7
, .AFMT_GENERIC_HDR = mmDIGid_AFMT_GENERIC_HDR, .AFMT_INFOFRAME_CONTROL0
= mmDIGid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL =
mmDIGid_AFMT_VBI_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL =
mmDIGid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2
= mmDIGid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL
= mmDIGid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = mmDIGid_AFMT_60958_0
, .AFMT_60958_1 = mmDIGid_AFMT_60958_1, .AFMT_60958_2 = mmDIGid_AFMT_60958_2
, .DIG_FE_CNTL = mmDIGid_DIG_FE_CNTL, .HDMI_CONTROL = mmDIGid_HDMI_CONTROL
, .HDMI_GC = mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 =
mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1
= mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_INFOFRAME_CONTROL0
= mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 =
mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = mmDIGid_HDMI_VBI_PACKET_CONTROL
, .HDMI_AUDIO_PACKET_CONTROL = mmDIGid_HDMI_AUDIO_PACKET_CONTROL
, .HDMI_ACR_PACKET_CONTROL = mmDIGid_HDMI_ACR_PACKET_CONTROL,
.HDMI_ACR_32_0 = mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = mmDIGid_HDMI_ACR_32_1
, .HDMI_ACR_44_0 = mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = mmDIGid_HDMI_ACR_44_1
, .HDMI_ACR_48_0 = mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = mmDIGid_HDMI_ACR_48_1
, .TMDS_CNTL = mmDIGid_TMDS_CNTL, .DP_MSE_RATE_CNTL = mmDPid_DP_MSE_RATE_CNTL
, .DP_MSE_RATE_UPDATE = mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT
= mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = mmDPid_DP_SEC_CNTL,
.DP_STEER_FIFO = mmDPid_DP_STEER_FIFO, .DP_VID_M = mmDPid_DP_VID_M
, .DP_VID_N = mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = mmDPid_DP_VID_STREAM_CNTL
, .DP_VID_TIMING = mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = mmDPid_DP_SEC_AUD_N
, .DP_SEC_TIMESTAMP = mmDPid_DP_SEC_TIMESTAMP, .AFMT_AVI_INFO0
= mmDIGid_AFMT_AVI_INFO0, .AFMT_AVI_INFO1 = mmDIGid_AFMT_AVI_INFO1
, .AFMT_AVI_INFO2 = mmDIGid_AFMT_AVI_INFO2, .AFMT_AVI_INFO3 =
mmDIGid_AFMT_AVI_INFO3, .AFMT_CNTL = mmDIGid_AFMT_CNTL,\
286 .TMDS_CNTL = 0,\
287}
288
289static const struct dce110_stream_enc_registers stream_enc_regs[] = {
290 stream_enc_regs(0)[0] = { .AFMT_GENERIC_0 = 0x4a25, .AFMT_GENERIC_1 = 0x4a26, .
AFMT_GENERIC_2 = 0x4a27, .AFMT_GENERIC_3 = 0x4a28, .AFMT_GENERIC_4
= 0x4a29, .AFMT_GENERIC_5 = 0x4a2a, .AFMT_GENERIC_6 = 0x4a2b
, .AFMT_GENERIC_7 = 0x4a2c, .AFMT_GENERIC_HDR = 0x4a24, .AFMT_INFOFRAME_CONTROL0
= 0x4a44, .AFMT_VBI_PACKET_CONTROL = 0x4a43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4a42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4a14, .AFMT_AUDIO_SRC_CONTROL
= 0x4a45, .AFMT_60958_0 = 0x4a38, .AFMT_60958_1 = 0x4a39, .AFMT_60958_2
= 0x4a3f, .DIG_FE_CNTL = 0x4a00, .HDMI_CONTROL = 0x4a09, .HDMI_GC
= 0x4a13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4a10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4a2d, .HDMI_INFOFRAME_CONTROL0 = 0x4a0e, .HDMI_INFOFRAME_CONTROL1
= 0x4a0f, .HDMI_VBI_PACKET_CONTROL = 0x4a0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4a0b, .HDMI_ACR_PACKET_CONTROL = 0x4a0c, .HDMI_ACR_32_0 =
0x4a2e, .HDMI_ACR_32_1 = 0x4a2f, .HDMI_ACR_44_0 = 0x4a30, .HDMI_ACR_44_1
= 0x4a31, .HDMI_ACR_48_0 = 0x4a32, .HDMI_ACR_48_1 = 0x4a33, .
TMDS_CNTL = 0x4a6b, .DP_MSE_RATE_CNTL = 0x4acf, .DP_MSE_RATE_UPDATE
= 0x4ad1, .DP_PIXEL_FORMAT = 0x4aa1, .DP_SEC_CNTL = 0x4ac3, .
DP_STEER_FIFO = 0x4aa5, .DP_VID_M = 0x4aaa, .DP_VID_N = 0x4aa9
, .DP_VID_STREAM_CNTL = 0x4aa4, .DP_VID_TIMING = 0x4aa8, .DP_SEC_AUD_N
= 0x4ac9, .DP_SEC_TIMESTAMP = 0x4acd, .AFMT_AVI_INFO0 = 0x4a1e
, .AFMT_AVI_INFO1 = 0x4a1f, .AFMT_AVI_INFO2 = 0x4a20, .AFMT_AVI_INFO3
= 0x4a21, .AFMT_CNTL = 0x4a7e, .TMDS_CNTL = 0,},
291 stream_enc_regs(1)[1] = { .AFMT_GENERIC_0 = 0x4b25, .AFMT_GENERIC_1 = 0x4b26, .
AFMT_GENERIC_2 = 0x4b27, .AFMT_GENERIC_3 = 0x4b28, .AFMT_GENERIC_4
= 0x4b29, .AFMT_GENERIC_5 = 0x4b2a, .AFMT_GENERIC_6 = 0x4b2b
, .AFMT_GENERIC_7 = 0x4b2c, .AFMT_GENERIC_HDR = 0x4b24, .AFMT_INFOFRAME_CONTROL0
= 0x4b44, .AFMT_VBI_PACKET_CONTROL = 0x4b43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4b42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4b14, .AFMT_AUDIO_SRC_CONTROL
= 0x4b45, .AFMT_60958_0 = 0x4b38, .AFMT_60958_1 = 0x4b39, .AFMT_60958_2
= 0x4b3f, .DIG_FE_CNTL = 0x4b00, .HDMI_CONTROL = 0x4b09, .HDMI_GC
= 0x4b13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4b10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4b2d, .HDMI_INFOFRAME_CONTROL0 = 0x4b0e, .HDMI_INFOFRAME_CONTROL1
= 0x4b0f, .HDMI_VBI_PACKET_CONTROL = 0x4b0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4b0b, .HDMI_ACR_PACKET_CONTROL = 0x4b0c, .HDMI_ACR_32_0 =
0x4b2e, .HDMI_ACR_32_1 = 0x4b2f, .HDMI_ACR_44_0 = 0x4b30, .HDMI_ACR_44_1
= 0x4b31, .HDMI_ACR_48_0 = 0x4b32, .HDMI_ACR_48_1 = 0x4b33, .
TMDS_CNTL = 0x4b6b, .DP_MSE_RATE_CNTL = 0x4bcf, .DP_MSE_RATE_UPDATE
= 0x4bd1, .DP_PIXEL_FORMAT = 0x4ba1, .DP_SEC_CNTL = 0x4bc3, .
DP_STEER_FIFO = 0x4ba5, .DP_VID_M = 0x4baa, .DP_VID_N = 0x4ba9
, .DP_VID_STREAM_CNTL = 0x4ba4, .DP_VID_TIMING = 0x4ba8, .DP_SEC_AUD_N
= 0x4bc9, .DP_SEC_TIMESTAMP = 0x4bcd, .AFMT_AVI_INFO0 = 0x4b1e
, .AFMT_AVI_INFO1 = 0x4b1f, .AFMT_AVI_INFO2 = 0x4b20, .AFMT_AVI_INFO3
= 0x4b21, .AFMT_CNTL = 0x4b7e, .TMDS_CNTL = 0,},
292 stream_enc_regs(2)[2] = { .AFMT_GENERIC_0 = 0x4c25, .AFMT_GENERIC_1 = 0x4c26, .
AFMT_GENERIC_2 = 0x4c27, .AFMT_GENERIC_3 = 0x4c28, .AFMT_GENERIC_4
= 0x4c29, .AFMT_GENERIC_5 = 0x4c2a, .AFMT_GENERIC_6 = 0x4c2b
, .AFMT_GENERIC_7 = 0x4c2c, .AFMT_GENERIC_HDR = 0x4c24, .AFMT_INFOFRAME_CONTROL0
= 0x4c44, .AFMT_VBI_PACKET_CONTROL = 0x4c43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4c42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4c14, .AFMT_AUDIO_SRC_CONTROL
= 0x4c45, .AFMT_60958_0 = 0x4c38, .AFMT_60958_1 = 0x4c39, .AFMT_60958_2
= 0x4c3f, .DIG_FE_CNTL = 0x4c00, .HDMI_CONTROL = 0x4c09, .HDMI_GC
= 0x4c13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4c10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4c2d, .HDMI_INFOFRAME_CONTROL0 = 0x4c0e, .HDMI_INFOFRAME_CONTROL1
= 0x4c0f, .HDMI_VBI_PACKET_CONTROL = 0x4c0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4c0b, .HDMI_ACR_PACKET_CONTROL = 0x4c0c, .HDMI_ACR_32_0 =
0x4c2e, .HDMI_ACR_32_1 = 0x4c2f, .HDMI_ACR_44_0 = 0x4c30, .HDMI_ACR_44_1
= 0x4c31, .HDMI_ACR_48_0 = 0x4c32, .HDMI_ACR_48_1 = 0x4c33, .
TMDS_CNTL = 0x4c6b, .DP_MSE_RATE_CNTL = 0x4ccf, .DP_MSE_RATE_UPDATE
= 0x4cd1, .DP_PIXEL_FORMAT = 0x4ca1, .DP_SEC_CNTL = 0x4cc3, .
DP_STEER_FIFO = 0x4ca5, .DP_VID_M = 0x4caa, .DP_VID_N = 0x4ca9
, .DP_VID_STREAM_CNTL = 0x4ca4, .DP_VID_TIMING = 0x4ca8, .DP_SEC_AUD_N
= 0x4cc9, .DP_SEC_TIMESTAMP = 0x4ccd, .AFMT_AVI_INFO0 = 0x4c1e
, .AFMT_AVI_INFO1 = 0x4c1f, .AFMT_AVI_INFO2 = 0x4c20, .AFMT_AVI_INFO3
= 0x4c21, .AFMT_CNTL = 0x4c7e, .TMDS_CNTL = 0,},
293 stream_enc_regs(3)[3] = { .AFMT_GENERIC_0 = 0x4d25, .AFMT_GENERIC_1 = 0x4d26, .
AFMT_GENERIC_2 = 0x4d27, .AFMT_GENERIC_3 = 0x4d28, .AFMT_GENERIC_4
= 0x4d29, .AFMT_GENERIC_5 = 0x4d2a, .AFMT_GENERIC_6 = 0x4d2b
, .AFMT_GENERIC_7 = 0x4d2c, .AFMT_GENERIC_HDR = 0x4d24, .AFMT_INFOFRAME_CONTROL0
= 0x4d44, .AFMT_VBI_PACKET_CONTROL = 0x4d43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4d42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4d14, .AFMT_AUDIO_SRC_CONTROL
= 0x4d45, .AFMT_60958_0 = 0x4d38, .AFMT_60958_1 = 0x4d39, .AFMT_60958_2
= 0x4d3f, .DIG_FE_CNTL = 0x4d00, .HDMI_CONTROL = 0x4d09, .HDMI_GC
= 0x4d13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4d10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4d2d, .HDMI_INFOFRAME_CONTROL0 = 0x4d0e, .HDMI_INFOFRAME_CONTROL1
= 0x4d0f, .HDMI_VBI_PACKET_CONTROL = 0x4d0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4d0b, .HDMI_ACR_PACKET_CONTROL = 0x4d0c, .HDMI_ACR_32_0 =
0x4d2e, .HDMI_ACR_32_1 = 0x4d2f, .HDMI_ACR_44_0 = 0x4d30, .HDMI_ACR_44_1
= 0x4d31, .HDMI_ACR_48_0 = 0x4d32, .HDMI_ACR_48_1 = 0x4d33, .
TMDS_CNTL = 0x4d6b, .DP_MSE_RATE_CNTL = 0x4dcf, .DP_MSE_RATE_UPDATE
= 0x4dd1, .DP_PIXEL_FORMAT = 0x4da1, .DP_SEC_CNTL = 0x4dc3, .
DP_STEER_FIFO = 0x4da5, .DP_VID_M = 0x4daa, .DP_VID_N = 0x4da9
, .DP_VID_STREAM_CNTL = 0x4da4, .DP_VID_TIMING = 0x4da8, .DP_SEC_AUD_N
= 0x4dc9, .DP_SEC_TIMESTAMP = 0x4dcd, .AFMT_AVI_INFO0 = 0x4d1e
, .AFMT_AVI_INFO1 = 0x4d1f, .AFMT_AVI_INFO2 = 0x4d20, .AFMT_AVI_INFO3
= 0x4d21, .AFMT_CNTL = 0x4d7e, .TMDS_CNTL = 0,},
294 stream_enc_regs(4)[4] = { .AFMT_GENERIC_0 = 0x4e25, .AFMT_GENERIC_1 = 0x4e26, .
AFMT_GENERIC_2 = 0x4e27, .AFMT_GENERIC_3 = 0x4e28, .AFMT_GENERIC_4
= 0x4e29, .AFMT_GENERIC_5 = 0x4e2a, .AFMT_GENERIC_6 = 0x4e2b
, .AFMT_GENERIC_7 = 0x4e2c, .AFMT_GENERIC_HDR = 0x4e24, .AFMT_INFOFRAME_CONTROL0
= 0x4e44, .AFMT_VBI_PACKET_CONTROL = 0x4e43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4e42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4e14, .AFMT_AUDIO_SRC_CONTROL
= 0x4e45, .AFMT_60958_0 = 0x4e38, .AFMT_60958_1 = 0x4e39, .AFMT_60958_2
= 0x4e3f, .DIG_FE_CNTL = 0x4e00, .HDMI_CONTROL = 0x4e09, .HDMI_GC
= 0x4e13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4e10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4e2d, .HDMI_INFOFRAME_CONTROL0 = 0x4e0e, .HDMI_INFOFRAME_CONTROL1
= 0x4e0f, .HDMI_VBI_PACKET_CONTROL = 0x4e0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4e0b, .HDMI_ACR_PACKET_CONTROL = 0x4e0c, .HDMI_ACR_32_0 =
0x4e2e, .HDMI_ACR_32_1 = 0x4e2f, .HDMI_ACR_44_0 = 0x4e30, .HDMI_ACR_44_1
= 0x4e31, .HDMI_ACR_48_0 = 0x4e32, .HDMI_ACR_48_1 = 0x4e33, .
TMDS_CNTL = 0x4e6b, .DP_MSE_RATE_CNTL = 0x4ecf, .DP_MSE_RATE_UPDATE
= 0x4ed1, .DP_PIXEL_FORMAT = 0x4ea1, .DP_SEC_CNTL = 0x4ec3, .
DP_STEER_FIFO = 0x4ea5, .DP_VID_M = 0x4eaa, .DP_VID_N = 0x4ea9
, .DP_VID_STREAM_CNTL = 0x4ea4, .DP_VID_TIMING = 0x4ea8, .DP_SEC_AUD_N
= 0x4ec9, .DP_SEC_TIMESTAMP = 0x4ecd, .AFMT_AVI_INFO0 = 0x4e1e
, .AFMT_AVI_INFO1 = 0x4e1f, .AFMT_AVI_INFO2 = 0x4e20, .AFMT_AVI_INFO3
= 0x4e21, .AFMT_CNTL = 0x4e7e, .TMDS_CNTL = 0,},
295 stream_enc_regs(5)[5] = { .AFMT_GENERIC_0 = 0x4f25, .AFMT_GENERIC_1 = 0x4f26, .
AFMT_GENERIC_2 = 0x4f27, .AFMT_GENERIC_3 = 0x4f28, .AFMT_GENERIC_4
= 0x4f29, .AFMT_GENERIC_5 = 0x4f2a, .AFMT_GENERIC_6 = 0x4f2b
, .AFMT_GENERIC_7 = 0x4f2c, .AFMT_GENERIC_HDR = 0x4f24, .AFMT_INFOFRAME_CONTROL0
= 0x4f44, .AFMT_VBI_PACKET_CONTROL = 0x4f43, .AFMT_AUDIO_PACKET_CONTROL
= 0x4f42, .AFMT_AUDIO_PACKET_CONTROL2 = 0x4f14, .AFMT_AUDIO_SRC_CONTROL
= 0x4f45, .AFMT_60958_0 = 0x4f38, .AFMT_60958_1 = 0x4f39, .AFMT_60958_2
= 0x4f3f, .DIG_FE_CNTL = 0x4f00, .HDMI_CONTROL = 0x4f09, .HDMI_GC
= 0x4f13, .HDMI_GENERIC_PACKET_CONTROL0 = 0x4f10, .HDMI_GENERIC_PACKET_CONTROL1
= 0x4f2d, .HDMI_INFOFRAME_CONTROL0 = 0x4f0e, .HDMI_INFOFRAME_CONTROL1
= 0x4f0f, .HDMI_VBI_PACKET_CONTROL = 0x4f0d, .HDMI_AUDIO_PACKET_CONTROL
= 0x4f0b, .HDMI_ACR_PACKET_CONTROL = 0x4f0c, .HDMI_ACR_32_0 =
0x4f2e, .HDMI_ACR_32_1 = 0x4f2f, .HDMI_ACR_44_0 = 0x4f30, .HDMI_ACR_44_1
= 0x4f31, .HDMI_ACR_48_0 = 0x4f32, .HDMI_ACR_48_1 = 0x4f33, .
TMDS_CNTL = 0x4f6b, .DP_MSE_RATE_CNTL = 0x4fcf, .DP_MSE_RATE_UPDATE
= 0x4fd1, .DP_PIXEL_FORMAT = 0x4fa1, .DP_SEC_CNTL = 0x4fc3, .
DP_STEER_FIFO = 0x4fa5, .DP_VID_M = 0x4faa, .DP_VID_N = 0x4fa9
, .DP_VID_STREAM_CNTL = 0x4fa4, .DP_VID_TIMING = 0x4fa8, .DP_SEC_AUD_N
= 0x4fc9, .DP_SEC_TIMESTAMP = 0x4fcd, .AFMT_AVI_INFO0 = 0x4f1e
, .AFMT_AVI_INFO1 = 0x4f1f, .AFMT_AVI_INFO2 = 0x4f20, .AFMT_AVI_INFO3
= 0x4f21, .AFMT_CNTL = 0x4f7e, .TMDS_CNTL = 0,}
296};
297
298static const struct dce_stream_encoder_shift se_shift = {
299 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT).AFMT_GENERIC_INDEX = 0x1e, .AFMT_GENERIC0_UPDATE = 0x2, .AFMT_GENERIC2_UPDATE
= 0x3, .AFMT_GENERIC_HB0 = 0x0, .AFMT_GENERIC_HB1 = 0x8, .AFMT_GENERIC_HB2
= 0x10, .AFMT_GENERIC_HB3 = 0x18, .HDMI_GENERIC0_CONT = 0x1,
.HDMI_GENERIC0_SEND = 0x0, .HDMI_GENERIC0_LINE = 0x10, .HDMI_GENERIC1_CONT
= 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC1_LINE = 0x18
, .DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .DP_DYN_RANGE
= 0x8, .DP_YCBCR_RANGE = 0x10, .HDMI_PACKET_GEN_VERSION = 0x4
, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18, .
HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_GC_CONT = 0x5, .HDMI_GC_SEND
= 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_AUDIO_INFO_SEND = 0x4, .
AFMT_AUDIO_INFO_UPDATE = 0x7, .HDMI_AUDIO_INFO_LINE = 0x8, .HDMI_GC_AVMUTE
= 0x0, .DP_MSE_RATE_X = 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING
= 0x0, .AFMT_AVI_INFO_VERSION = 0x18, .HDMI_AVI_INFO_SEND = 0x0
, .HDMI_AVI_INFO_CONT = 0x1, .HDMI_AVI_INFO_LINE = 0x0, .DP_SEC_GSP0_ENABLE
= 0x14, .DP_SEC_STREAM_ENABLE = 0x0, .DP_SEC_GSP1_ENABLE = 0x15
, .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE = 0x17, .DP_SEC_AVI_ENABLE
= 0x18, .DP_SEC_MPG_ENABLE = 0x1c, .DP_VID_STREAM_DIS_DEFER =
0x8, .DP_VID_STREAM_ENABLE = 0x0, .DP_VID_STREAM_STATUS = 0x10
, .DP_STEER_FIFO_RESET = 0x0, .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N
= 0x0, .DP_VID_M = 0x0, .DIG_START = 0xa, .DIG_STEREOSYNC_SELECT
= 0x4, .DIG_STEREOSYNC_GATE_EN = 0x8, .AFMT_AUDIO_SRC_SELECT
= 0x0, .AFMT_AUDIO_CHANNEL_ENABLE = 0x8, .HDMI_AUDIO_PACKETS_PER_LINE
= 0x10, .HDMI_AUDIO_DELAY_EN = 0x4, .AFMT_60958_CS_UPDATE = 0x1a
, .AFMT_AUDIO_LAYOUT_OVRD = 0x0, .AFMT_60958_OSF_OVRD = 0x1c,
.HDMI_ACR_AUTO_SEND = 0xc, .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY
= 0x1f, .HDMI_ACR_CTS_32 = 0xc, .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44
= 0xc, .HDMI_ACR_N_44 = 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48
= 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x14, .AFMT_60958_CS_CLOCK_ACCURACY
= 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2
= 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4
= 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6
= 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x14, .DP_SEC_AUD_N
= 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, .DP_SEC_ASP_ENABLE = 0x4
, .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .DP_SEC_ACM_ENABLE
= 0x10, .AFMT_AUDIO_SAMPLE_SEND = 0x0, .DIG_SOURCE_SELECT = 0x0
, .AFMT_AUDIO_CLOCK_EN = 0x0, .HDMI_CLOCK_CHANNEL_RATE = 0x2,
.HDMI_DATA_SCRAMBLE_EN = 0x1, .TMDS_PIXEL_ENCODING = 0x1c, .
TMDS_COLOR_FORMAT = 0x1e, .DP_VID_M_DOUBLE_VALUE_EN = 0x9
300};
301
302static const struct dce_stream_encoder_mask se_mask = {
303 SE_COMMON_MASK_SH_LIST_DCE112(_MASK).AFMT_GENERIC_INDEX = 0xc0000000, .AFMT_GENERIC0_UPDATE = 0x4
, .AFMT_GENERIC2_UPDATE = 0x8, .AFMT_GENERIC_HB0 = 0xff, .AFMT_GENERIC_HB1
= 0xff00, .AFMT_GENERIC_HB2 = 0xff0000, .AFMT_GENERIC_HB3 = 0xff000000
, .HDMI_GENERIC0_CONT = 0x2, .HDMI_GENERIC0_SEND = 0x1, .HDMI_GENERIC0_LINE
= 0x3f0000, .HDMI_GENERIC1_CONT = 0x20, .HDMI_GENERIC1_SEND =
0x10, .HDMI_GENERIC1_LINE = 0x3f000000, .DP_PIXEL_ENCODING =
0x7, .DP_COMPONENT_DEPTH = 0x7000000, .DP_DYN_RANGE = 0x100,
.DP_YCBCR_RANGE = 0x10000, .HDMI_PACKET_GEN_VERSION = 0x10, .
HDMI_KEEPOUT_MODE = 0x1, .HDMI_DEEP_COLOR_ENABLE = 0x1000000,
.HDMI_DEEP_COLOR_DEPTH = 0x30000000, .HDMI_GC_CONT = 0x20, .
HDMI_GC_SEND = 0x10, .HDMI_NULL_SEND = 0x1, .HDMI_AUDIO_INFO_SEND
= 0x10, .AFMT_AUDIO_INFO_UPDATE = 0x80, .HDMI_AUDIO_INFO_LINE
= 0x3f00, .HDMI_GC_AVMUTE = 0x1, .DP_MSE_RATE_X = 0xfc000000
, .DP_MSE_RATE_Y = 0x3ffffff, .DP_MSE_RATE_UPDATE_PENDING = 0x1
, .AFMT_AVI_INFO_VERSION = 0xff000000, .HDMI_AVI_INFO_SEND = 0x1
, .HDMI_AVI_INFO_CONT = 0x2, .HDMI_AVI_INFO_LINE = 0x3f, .DP_SEC_GSP0_ENABLE
= 0x100000, .DP_SEC_STREAM_ENABLE = 0x1, .DP_SEC_GSP1_ENABLE
= 0x200000, .DP_SEC_GSP2_ENABLE = 0x400000, .DP_SEC_GSP3_ENABLE
= 0x800000, .DP_SEC_AVI_ENABLE = 0x1000000, .DP_SEC_MPG_ENABLE
= 0x10000000, .DP_VID_STREAM_DIS_DEFER = 0x300, .DP_VID_STREAM_ENABLE
= 0x1, .DP_VID_STREAM_STATUS = 0x10000, .DP_STEER_FIFO_RESET
= 0x1, .DP_VID_M_N_GEN_EN = 0x100, .DP_VID_N = 0xffffff, .DP_VID_M
= 0xffffff, .DIG_START = 0x400, .DIG_STEREOSYNC_SELECT = 0x70
, .DIG_STEREOSYNC_GATE_EN = 0x100, .AFMT_AUDIO_SRC_SELECT = 0x7
, .AFMT_AUDIO_CHANNEL_ENABLE = 0xff00, .HDMI_AUDIO_PACKETS_PER_LINE
= 0x1f0000, .HDMI_AUDIO_DELAY_EN = 0x30, .AFMT_60958_CS_UPDATE
= 0x4000000, .AFMT_AUDIO_LAYOUT_OVRD = 0x1, .AFMT_60958_OSF_OVRD
= 0x10000000, .HDMI_ACR_AUTO_SEND = 0x1000, .HDMI_ACR_SOURCE
= 0x100, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000, .HDMI_ACR_CTS_32
= 0xfffff000, .HDMI_ACR_N_32 = 0xfffff, .HDMI_ACR_CTS_44 = 0xfffff000
, .HDMI_ACR_N_44 = 0xfffff, .HDMI_ACR_CTS_48 = 0xfffff000, .HDMI_ACR_N_48
= 0xfffff, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0xf00000, .AFMT_60958_CS_CLOCK_ACCURACY
= 0x30000000, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0xf00000, .AFMT_60958_CS_CHANNEL_NUMBER_2
= 0xf, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0xf0, .AFMT_60958_CS_CHANNEL_NUMBER_4
= 0xf00, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xf000, .AFMT_60958_CS_CHANNEL_NUMBER_6
= 0xf0000, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0xf00000, .DP_SEC_AUD_N
= 0xffffff, .DP_SEC_TIMESTAMP_MODE = 0x1, .DP_SEC_ASP_ENABLE
= 0x10, .DP_SEC_ATP_ENABLE = 0x100, .DP_SEC_AIP_ENABLE = 0x1000
, .DP_SEC_ACM_ENABLE = 0x10000, .AFMT_AUDIO_SAMPLE_SEND = 0x1
, .DIG_SOURCE_SELECT = 0x7, .AFMT_AUDIO_CLOCK_EN = 0x1, .HDMI_CLOCK_CHANNEL_RATE
= 0x4, .HDMI_DATA_SCRAMBLE_EN = 0x2, .TMDS_PIXEL_ENCODING = 0x10000000
, .TMDS_COLOR_FORMAT = 0xc0000000, .DP_VID_M_DOUBLE_VALUE_EN =
0x200
304};
305
306#define opp_regs(id)[id] = { .FMT_DYNAMIC_EXP_CNTL = mmFMTid_FMT_DYNAMIC_EXP_CNTL
, .FMT_BIT_DEPTH_CONTROL = mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL
= mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = mmFMTid_FMT_DITHER_RAND_R_SEED
, .FMT_DITHER_RAND_G_SEED = mmFMTid_FMT_DITHER_RAND_G_SEED, .
FMT_DITHER_RAND_B_SEED = mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL
= mmFMTid_FMT_CLAMP_CNTL, .FMT_CLAMP_COMPONENT_R = mmFMTid_FMT_CLAMP_COMPONENT_R
, .FMT_CLAMP_COMPONENT_G = mmFMTid_FMT_CLAMP_COMPONENT_G, .FMT_CLAMP_COMPONENT_B
= mmFMTid_FMT_CLAMP_COMPONENT_B, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL
= mmFMTid_FMT_TEMPORAL_DITHER_PATTERN_CONTROL, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= mmFMTid_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX,
.FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX = mmFMTid_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
, .CONTROL = mmFMT_MEMORYid_CONTROL,}\
307[id] = {\
308 OPP_DCE_112_REG_LIST(id).FMT_DYNAMIC_EXP_CNTL = mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_BIT_DEPTH_CONTROL
= mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = mmFMTid_FMT_CONTROL
, .FMT_DITHER_RAND_R_SEED = mmFMTid_FMT_DITHER_RAND_R_SEED, .
FMT_DITHER_RAND_G_SEED = mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED
= mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = mmFMTid_FMT_CLAMP_CNTL
, .FMT_CLAMP_COMPONENT_R = mmFMTid_FMT_CLAMP_COMPONENT_R, .FMT_CLAMP_COMPONENT_G
= mmFMTid_FMT_CLAMP_COMPONENT_G, .FMT_CLAMP_COMPONENT_B = mmFMTid_FMT_CLAMP_COMPONENT_B
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = mmFMTid_FMT_TEMPORAL_DITHER_PATTERN_CONTROL
, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX = mmFMTid_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX = mmFMTid_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
, .CONTROL = mmFMT_MEMORYid_CONTROL,\
309}
310
311static const struct dce_opp_registers opp_regs[] = {
312 opp_regs(0)[0] = { .FMT_DYNAMIC_EXP_CNTL = 0x1bed, .FMT_BIT_DEPTH_CONTROL
= 0x1bf2, .FMT_CONTROL = 0x1bee, .FMT_DITHER_RAND_R_SEED = 0x1bf3
, .FMT_DITHER_RAND_G_SEED = 0x1bf4, .FMT_DITHER_RAND_B_SEED =
0x1bf5, .FMT_CLAMP_CNTL = 0x1bf9, .FMT_CLAMP_COMPONENT_R = 0x1be8
, .FMT_CLAMP_COMPONENT_G = 0x1be9, .FMT_CLAMP_COMPONENT_B = 0x1bea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x1bf6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x1bf7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x1bf8, .CONTROL = 0x1888,},
313 opp_regs(1)[1] = { .FMT_DYNAMIC_EXP_CNTL = 0x1ded, .FMT_BIT_DEPTH_CONTROL
= 0x1df2, .FMT_CONTROL = 0x1dee, .FMT_DITHER_RAND_R_SEED = 0x1df3
, .FMT_DITHER_RAND_G_SEED = 0x1df4, .FMT_DITHER_RAND_B_SEED =
0x1df5, .FMT_CLAMP_CNTL = 0x1df9, .FMT_CLAMP_COMPONENT_R = 0x1de8
, .FMT_CLAMP_COMPONENT_G = 0x1de9, .FMT_CLAMP_COMPONENT_B = 0x1dea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x1df6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x1df7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x1df8, .CONTROL = 0x1889,},
314 opp_regs(2)[2] = { .FMT_DYNAMIC_EXP_CNTL = 0x1fed, .FMT_BIT_DEPTH_CONTROL
= 0x1ff2, .FMT_CONTROL = 0x1fee, .FMT_DITHER_RAND_R_SEED = 0x1ff3
, .FMT_DITHER_RAND_G_SEED = 0x1ff4, .FMT_DITHER_RAND_B_SEED =
0x1ff5, .FMT_CLAMP_CNTL = 0x1ff9, .FMT_CLAMP_COMPONENT_R = 0x1fe8
, .FMT_CLAMP_COMPONENT_G = 0x1fe9, .FMT_CLAMP_COMPONENT_B = 0x1fea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x1ff6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x1ff7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x1ff8, .CONTROL = 0x188a,},
315 opp_regs(3)[3] = { .FMT_DYNAMIC_EXP_CNTL = 0x41ed, .FMT_BIT_DEPTH_CONTROL
= 0x41f2, .FMT_CONTROL = 0x41ee, .FMT_DITHER_RAND_R_SEED = 0x41f3
, .FMT_DITHER_RAND_G_SEED = 0x41f4, .FMT_DITHER_RAND_B_SEED =
0x41f5, .FMT_CLAMP_CNTL = 0x41f9, .FMT_CLAMP_COMPONENT_R = 0x41e8
, .FMT_CLAMP_COMPONENT_G = 0x41e9, .FMT_CLAMP_COMPONENT_B = 0x41ea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x41f6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x41f7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x41f8, .CONTROL = 0x188b,},
316 opp_regs(4)[4] = { .FMT_DYNAMIC_EXP_CNTL = 0x43ed, .FMT_BIT_DEPTH_CONTROL
= 0x43f2, .FMT_CONTROL = 0x43ee, .FMT_DITHER_RAND_R_SEED = 0x43f3
, .FMT_DITHER_RAND_G_SEED = 0x43f4, .FMT_DITHER_RAND_B_SEED =
0x43f5, .FMT_CLAMP_CNTL = 0x43f9, .FMT_CLAMP_COMPONENT_R = 0x43e8
, .FMT_CLAMP_COMPONENT_G = 0x43e9, .FMT_CLAMP_COMPONENT_B = 0x43ea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x43f6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x43f7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x43f8, .CONTROL = 0x188c,},
317 opp_regs(5)[5] = { .FMT_DYNAMIC_EXP_CNTL = 0x45ed, .FMT_BIT_DEPTH_CONTROL
= 0x45f2, .FMT_CONTROL = 0x45ee, .FMT_DITHER_RAND_R_SEED = 0x45f3
, .FMT_DITHER_RAND_G_SEED = 0x45f4, .FMT_DITHER_RAND_B_SEED =
0x45f5, .FMT_CLAMP_CNTL = 0x45f9, .FMT_CLAMP_COMPONENT_R = 0x45e8
, .FMT_CLAMP_COMPONENT_G = 0x45e9, .FMT_CLAMP_COMPONENT_B = 0x45ea
, .FMT_TEMPORAL_DITHER_PATTERN_CONTROL = 0x45f6, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX
= 0x45f7, .FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX
= 0x45f8, .CONTROL = 0x188d,}
318};
319
320static const struct dce_opp_shift opp_shift = {
321 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT).FMT_DYNAMIC_EXP_EN = 0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_TRUNCATE_EN
= 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE = 0x1, .
FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_DEPTH = 0xb,
.FMT_SPATIAL_DITHER_MODE = 0x9, .FMT_HIGHPASS_RANDOM_ENABLE =
0xf, .FMT_FRAME_RANDOM_ENABLE = 0xd, .FMT_RGB_RANDOM_ENABLE =
0xe, .FMT_TEMPORAL_DITHER_EN = 0x10, .FMT_RAND_R_SEED = 0x0,
.FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_TEMPORAL_DITHER_EN
= 0x10, .FMT_TEMPORAL_DITHER_RESET = 0x19, .FMT_TEMPORAL_DITHER_OFFSET
= 0x15, .FMT_TEMPORAL_DITHER_DEPTH = 0x11, .FMT_TEMPORAL_LEVEL
= 0x18, .FMT_25FRC_SEL = 0x1a, .FMT_50FRC_SEL = 0x1c, .FMT_75FRC_SEL
= 0x1e, .FMT_SRC_SELECT = 0x18, .FMT_CLAMP_DATA_EN = 0x0, .FMT_CLAMP_COLOR_FORMAT
= 0x10, .FMT_CLAMP_LOWER_R = 0x0, .FMT_CLAMP_UPPER_R = 0x10,
.FMT_CLAMP_LOWER_G = 0x0, .FMT_CLAMP_UPPER_G = 0x10, .FMT_CLAMP_LOWER_B
= 0x0, .FMT_CLAMP_UPPER_B = 0x10, .FMT_PIXEL_ENCODING = 0x10
, .FMT_SUBSAMPLING_MODE = 0x12, .FMT_SUBSAMPLING_ORDER = 0x14
, .FMT420_MEM0_SOURCE_SEL = 0x0, .FMT420_MEM0_PWR_FORCE = 0x4
, .FMT_420_PIXEL_PHASE_LOCKED_CLEAR = 0x1f, .FMT_420_PIXEL_PHASE_LOCKED
= 0x1e, .FMT_CBCR_BIT_REDUCTION_BYPASS = 0x15, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX
= 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_STEREOSYNC_OVERRIDE
= 0x0
322};
323
324static const struct dce_opp_mask opp_mask = {
325 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK).FMT_DYNAMIC_EXP_EN = 0x1, .FMT_DYNAMIC_EXP_MODE = 0x10, .FMT_TRUNCATE_EN
= 0x1, .FMT_TRUNCATE_DEPTH = 0x30, .FMT_TRUNCATE_MODE = 0x2,
.FMT_SPATIAL_DITHER_EN = 0x100, .FMT_SPATIAL_DITHER_DEPTH = 0x1800
, .FMT_SPATIAL_DITHER_MODE = 0x600, .FMT_HIGHPASS_RANDOM_ENABLE
= 0x8000, .FMT_FRAME_RANDOM_ENABLE = 0x2000, .FMT_RGB_RANDOM_ENABLE
= 0x4000, .FMT_TEMPORAL_DITHER_EN = 0x10000, .FMT_RAND_R_SEED
= 0xff, .FMT_RAND_G_SEED = 0xff, .FMT_RAND_B_SEED = 0xff, .FMT_TEMPORAL_DITHER_EN
= 0x10000, .FMT_TEMPORAL_DITHER_RESET = 0x2000000, .FMT_TEMPORAL_DITHER_OFFSET
= 0x600000, .FMT_TEMPORAL_DITHER_DEPTH = 0x60000, .FMT_TEMPORAL_LEVEL
= 0x1000000, .FMT_25FRC_SEL = 0xc000000, .FMT_50FRC_SEL = 0x30000000
, .FMT_75FRC_SEL = 0xc0000000, .FMT_SRC_SELECT = 0x7000000, .
FMT_CLAMP_DATA_EN = 0x1, .FMT_CLAMP_COLOR_FORMAT = 0x70000, .
FMT_CLAMP_LOWER_R = 0xffff, .FMT_CLAMP_UPPER_R = 0xffff0000, .
FMT_CLAMP_LOWER_G = 0xffff, .FMT_CLAMP_UPPER_G = 0xffff0000, .
FMT_CLAMP_LOWER_B = 0xffff, .FMT_CLAMP_UPPER_B = 0xffff0000, .
FMT_PIXEL_ENCODING = 0x30000, .FMT_SUBSAMPLING_MODE = 0xc0000
, .FMT_SUBSAMPLING_ORDER = 0x100000, .FMT420_MEM0_SOURCE_SEL =
0x7, .FMT420_MEM0_PWR_FORCE = 0x30, .FMT_420_PIXEL_PHASE_LOCKED_CLEAR
= 0x80000000, .FMT_420_PIXEL_PHASE_LOCKED = 0x40000000, .FMT_CBCR_BIT_REDUCTION_BYPASS
= 0x200000, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0xf00, .
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x3000, .FMT_STEREOSYNC_OVERRIDE
= 0x1
326};
327
328#define aux_engine_regs(id)[id] = { .AUX_CONTROL = mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL
= mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = mmDP_AUXid_AUX_SW_DATA
, .AUX_SW_CONTROL = mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL
= mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_SW_STATUS = mmDP_AUXid_AUX_SW_STATUS
, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL = 0x483b, .AUX_RESET_MASK
= 0 }\
329[id] = {\
330 AUX_COMMON_REG_LIST(id).AUX_CONTROL = mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = mmDP_AUXid_AUX_ARB_CONTROL
, .AUX_SW_DATA = mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = mmDP_AUXid_AUX_SW_CONTROL
, .AUX_INTERRUPT_CONTROL = mmDP_AUXid_AUX_INTERRUPT_CONTROL, .
AUX_SW_STATUS = mmDP_AUXid_AUX_SW_STATUS, .AUXN_IMPCAL = 0x483c
, .AUXP_IMPCAL = 0x483b, \
331 .AUX_RESET_MASK = 0 \
332}
333
334static const struct dce110_aux_registers aux_engine_regs[] = {
335 aux_engine_regs(0)[0] = { .AUX_CONTROL = 0x5c00, .AUX_ARB_CONTROL = 0x5c02, .AUX_SW_DATA
= 0x5c06, .AUX_SW_CONTROL = 0x5c01, .AUX_INTERRUPT_CONTROL =
0x5c03, .AUX_SW_STATUS = 0x5c04, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 },
336 aux_engine_regs(1)[1] = { .AUX_CONTROL = 0x5c1c, .AUX_ARB_CONTROL = 0x5c1e, .AUX_SW_DATA
= 0x5c22, .AUX_SW_CONTROL = 0x5c1d, .AUX_INTERRUPT_CONTROL =
0x5c1f, .AUX_SW_STATUS = 0x5c20, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 },
337 aux_engine_regs(2)[2] = { .AUX_CONTROL = 0x5c38, .AUX_ARB_CONTROL = 0x5c3a, .AUX_SW_DATA
= 0x5c3e, .AUX_SW_CONTROL = 0x5c39, .AUX_INTERRUPT_CONTROL =
0x5c3b, .AUX_SW_STATUS = 0x5c3c, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 },
338 aux_engine_regs(3)[3] = { .AUX_CONTROL = 0x5c54, .AUX_ARB_CONTROL = 0x5c56, .AUX_SW_DATA
= 0x5c5a, .AUX_SW_CONTROL = 0x5c55, .AUX_INTERRUPT_CONTROL =
0x5c57, .AUX_SW_STATUS = 0x5c58, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 },
339 aux_engine_regs(4)[4] = { .AUX_CONTROL = 0x5c70, .AUX_ARB_CONTROL = 0x5c72, .AUX_SW_DATA
= 0x5c76, .AUX_SW_CONTROL = 0x5c71, .AUX_INTERRUPT_CONTROL =
0x5c73, .AUX_SW_STATUS = 0x5c74, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 },
340 aux_engine_regs(5)[5] = { .AUX_CONTROL = 0x5c8c, .AUX_ARB_CONTROL = 0x5c8e, .AUX_SW_DATA
= 0x5c92, .AUX_SW_CONTROL = 0x5c8d, .AUX_INTERRUPT_CONTROL =
0x5c8f, .AUX_SW_STATUS = 0x5c90, .AUXN_IMPCAL = 0x483c, .AUXP_IMPCAL
= 0x483b, .AUX_RESET_MASK = 0 }
341};
342
343#define audio_regs(id)[id] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX
, .AZALIA_F0_CODEC_ENDPOINT_DATA = mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x182e
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x182d
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x182f, .
DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE = 0x16d
, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE = 0x16f
, .DCCG_AUDIO_DTO1_PHASE = 0x16e}\
344[id] = {\
345 AUD_COMMON_REG_LIST(id).AZALIA_F0_CODEC_ENDPOINT_INDEX = mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX
, .AZALIA_F0_CODEC_ENDPOINT_DATA = mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x182e
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x182d
, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x182f, .
DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE = 0x16d
, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE = 0x16f
, .DCCG_AUDIO_DTO1_PHASE = 0x16e\
346}
347
348static const struct dce_audio_registers audio_regs[] = {
349 audio_regs(0)[0] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17a8, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17a9, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e},
350 audio_regs(1)[1] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17ac, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17ad, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e},
351 audio_regs(2)[2] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17b0, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17b1, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e},
352 audio_regs(3)[3] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17b4, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17b5, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e},
353 audio_regs(4)[4] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17b8, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17b9, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e},
354 audio_regs(5)[5] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x17bc, .AZALIA_F0_CODEC_ENDPOINT_DATA
= 0x17bd, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x182e, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x182d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES =
0x182f, .DCCG_AUDIO_DTO_SOURCE = 0x16b, .DCCG_AUDIO_DTO0_MODULE
= 0x16d, .DCCG_AUDIO_DTO0_PHASE = 0x16c, .DCCG_AUDIO_DTO1_MODULE
= 0x16f, .DCCG_AUDIO_DTO1_PHASE = 0x16e}
355};
356
357static const struct dce_audio_shift audio_shift = {
358 AUD_COMMON_MASK_SH_LIST(__SHIFT).DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL = 0x4,
.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO
= 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE
= 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE
= 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES
= 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f, .AZALIA_ENDPOINT_REG_INDEX
= 0x0, .AZALIA_ENDPOINT_REG_DATA = 0x0
359};
360
361static const struct dce_audio_mask audio_mask = {
362 AUD_COMMON_MASK_SH_LIST(_MASK).DCCG_AUDIO_DTO0_SOURCE_SEL = 0x7, .DCCG_AUDIO_DTO_SEL = 0x30
, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x100000, .DCCG_AUDIO_DTO0_USE_512FBR_DTO
= 0x1000000, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x10000000, .
DCCG_AUDIO_DTO0_MODULE = 0xffffffff, .DCCG_AUDIO_DTO0_PHASE =
0xffffffff, .DCCG_AUDIO_DTO1_MODULE = 0xffffffff, .DCCG_AUDIO_DTO1_PHASE
= 0xffffffff, .AUDIO_RATE_CAPABILITIES = 0xfff, .CLKSTOP = 0x40000000
, .EPSS = 0x80000000, .AZALIA_ENDPOINT_REG_INDEX = 0x3fff, .AZALIA_ENDPOINT_REG_DATA
= 0xffffffff
363};
364
365#define clk_src_regs(index, id)[index] = { .PIXCLK_RESYNC_CNTL = mmPHYPLLid_PIXCLK_RESYNC_CNTL
,}\
366[index] = {\
367 CS_COMMON_REG_LIST_DCE_112(id).PIXCLK_RESYNC_CNTL = mmPHYPLLid_PIXCLK_RESYNC_CNTL,\
368}
369
370static const struct dce110_clk_src_regs clk_src_regs[] = {
371 clk_src_regs(0, A)[0] = { .PIXCLK_RESYNC_CNTL = 0x100,},
372 clk_src_regs(1, B)[1] = { .PIXCLK_RESYNC_CNTL = 0x101,},
373 clk_src_regs(2, C)[2] = { .PIXCLK_RESYNC_CNTL = 0x102,},
374 clk_src_regs(3, D)[3] = { .PIXCLK_RESYNC_CNTL = 0x103,},
375 clk_src_regs(4, E)[4] = { .PIXCLK_RESYNC_CNTL = 0x10c,},
376 clk_src_regs(5, F)[5] = { .PIXCLK_RESYNC_CNTL = 0x13e,}
377};
378
379static const struct dce110_clk_src_shift cs_shift = {
380 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT).PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x4, .PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE
= 0x9
381};
382
383static const struct dce110_clk_src_mask cs_mask = {
384 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK).PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x30, .PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE
= 0x200
385};
386
387static const struct bios_registers bios_regs = {
388 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_30x05CC,
389 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_60x05CF
390};
391
392static const struct resource_caps polaris_10_resource_cap = {
393 .num_timing_generator = 6,
394 .num_audio = 6,
395 .num_stream_encoder = 6,
396 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
397 .num_ddc = 6,
398};
399
400static const struct resource_caps polaris_11_resource_cap = {
401 .num_timing_generator = 5,
402 .num_audio = 5,
403 .num_stream_encoder = 5,
404 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
405 .num_ddc = 5,
406};
407
408static const struct dc_plane_cap plane_cap = {
409 .type = DC_PLANE_TYPE_DCE_RGB,
410
411 .pixel_format_support = {
412 .argb8888 = true1,
413 .nv12 = false0,
414 .fp16 = true1
415 },
416
417 .max_upscale_factor = {
418 .argb8888 = 16000,
419 .nv12 = 1,
420 .fp16 = 1
421 },
422
423 .max_downscale_factor = {
424 .argb8888 = 250,
425 .nv12 = 1,
426 .fp16 = 1
427 },
428 64,
429 64
430};
431
432#define CTXctx ctx
433#define REG(reg)mmreg mm ## reg
434
435#ifndef mmCC_DC_HDMI_STRAPS0x4819
436#define mmCC_DC_HDMI_STRAPS0x4819 0x4819
437#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK0x40 0x40
438#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT0x6 0x6
439#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK0x700 0x700
440#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT0x8 0x8
441#endif
442
443static int map_transmitter_id_to_phy_instance(
444 enum transmitter transmitter)
445{
446 switch (transmitter) {
447 case TRANSMITTER_UNIPHY_A:
448 return 0;
449 break;
450 case TRANSMITTER_UNIPHY_B:
451 return 1;
452 break;
453 case TRANSMITTER_UNIPHY_C:
454 return 2;
455 break;
456 case TRANSMITTER_UNIPHY_D:
457 return 3;
458 break;
459 case TRANSMITTER_UNIPHY_E:
460 return 4;
461 break;
462 case TRANSMITTER_UNIPHY_F:
463 return 5;
464 break;
465 case TRANSMITTER_UNIPHY_G:
466 return 6;
467 break;
468 default:
469 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c"
, 469); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
470 return 0;
471 }
472}
473
474static void read_dce_straps(
475 struct dc_context *ctx,
476 struct resource_straps *straps)
477{
478 REG_GET_2(CC_DC_HDMI_STRAPS,generic_reg_get2(ctx, 0x4819, 0x6, 0x40, &straps->hdmi_disable
, 0x8, 0x700, &straps->audio_stream_number)
479 HDMI_DISABLE, &straps->hdmi_disable,generic_reg_get2(ctx, 0x4819, 0x6, 0x40, &straps->hdmi_disable
, 0x8, 0x700, &straps->audio_stream_number)
480 AUDIO_STREAM_NUMBER, &straps->audio_stream_number)generic_reg_get2(ctx, 0x4819, 0x6, 0x40, &straps->hdmi_disable
, 0x8, 0x700, &straps->audio_stream_number);
481
482 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio)generic_reg_get(ctx, 0x4818, 0xe, 0xc000, &straps->dc_pinstraps_audio
);
483}
484
485static struct audio *create_audio(
486 struct dc_context *ctx, unsigned int inst)
487{
488 return dce_audio_create(ctx, inst,
489 &audio_regs[inst], &audio_shift, &audio_mask);
490}
491
492
493static struct timing_generator *dce112_timing_generator_create(
494 struct dc_context *ctx,
495 uint32_t instance,
496 const struct dce110_timing_generator_offsets *offsets)
497{
498 struct dce110_timing_generator *tg110 =
499 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL(0x0001 | 0x0004));
500
501 if (!tg110)
502 return NULL((void *)0);
503
504 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
505 return &tg110->base;
506}
507
508static struct stream_encoder *dce112_stream_encoder_create(
509 enum engine_id eng_id,
510 struct dc_context *ctx)
511{
512 struct dce110_stream_encoder *enc110 =
513 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL(0x0001 | 0x0004));
514
515 if (!enc110)
516 return NULL((void *)0);
517
518 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
519 &stream_enc_regs[eng_id],
520 &se_shift, &se_mask);
521 return &enc110->base;
522}
523
524#define SRII(reg_name, block, id).reg_name[id] = mmblockid_reg_name\
525 .reg_name[id] = mm ## block ## id ## _ ## reg_name
526
527static const struct dce_hwseq_registers hwseq_reg = {
528 HWSEQ_DCE112_REG_LIST().DCFE_CLOCK_CONTROL[0] = 0x1b00, .DCFE_CLOCK_CONTROL[1] = 0x1d00
, .DCFE_CLOCK_CONTROL[2] = 0x1f00, .DCFE_CLOCK_CONTROL[3] = 0x4100
, .DCFE_CLOCK_CONTROL[4] = 0x4300, .DCFE_CLOCK_CONTROL[5] = 0x4500
, .DC_MEM_GLOBAL_PWR_REQ_CNTL = 0x132, .BLND_V_UPDATE_LOCK[0]
= 0x1b73, .BLND_V_UPDATE_LOCK[1] = 0x1d73, .BLND_V_UPDATE_LOCK
[2] = 0x1f73, .BLND_V_UPDATE_LOCK[3] = 0x4173, .BLND_V_UPDATE_LOCK
[4] = 0x4373, .BLND_V_UPDATE_LOCK[5] = 0x4573, .BLND_CONTROL[
0] = 0x1b6d, .BLND_CONTROL[1] = 0x1d6d, .BLND_CONTROL[2] = 0x1f6d
, .BLND_CONTROL[3] = 0x416d, .BLND_CONTROL[4] = 0x436d, .BLND_CONTROL
[5] = 0x456d, .PIXEL_RATE_CNTL[0] = 0x140, .PIXEL_RATE_CNTL[1
] = 0x144, .PIXEL_RATE_CNTL[2] = 0x148, .PIXEL_RATE_CNTL[3] =
0x14c, .PIXEL_RATE_CNTL[4] = 0x150, .PIXEL_RATE_CNTL[5] = 0x154
, .PIXEL_RATE_CNTL[0] = 0x140, .PIXEL_RATE_CNTL[1] = 0x144, .
PIXEL_RATE_CNTL[2] = 0x148, .PIXEL_RATE_CNTL[3] = 0x14c, .PIXEL_RATE_CNTL
[4] = 0x150, .PIXEL_RATE_CNTL[5] = 0x154, .PHYPLL_PIXEL_RATE_CNTL
[0] = 0x143, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x147, .PHYPLL_PIXEL_RATE_CNTL
[2] = 0x14b, .PHYPLL_PIXEL_RATE_CNTL[3] = 0x14f, .PHYPLL_PIXEL_RATE_CNTL
[4] = 0x153, .PHYPLL_PIXEL_RATE_CNTL[5] = 0x157
529};
530
531static const struct dce_hwseq_shift hwseq_shift = {
532 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT).DCFE_CLOCK_ENABLE = 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .
BLND_DCP_GRPH_V_UPDATE_LOCK = 0x0, .BLND_SCL_V_UPDATE_LOCK = 0x1c
, .BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = 0x1, .BLND_BLND_V_UPDATE_LOCK
= 0x1d, .BLND_V_UPDATE_LOCK_MODE = 0x1f, .BLND_FEEDTHROUGH_EN
= 0xd, .BLND_ALPHA_MODE = 0x10, .BLND_MODE = 0x8, .BLND_MULTIPLIED_MODE
= 0x14, .PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE
= 0x0, .PIXEL_RATE_PLL_SOURCE = 0x4
533};
534
535static const struct dce_hwseq_mask hwseq_mask = {
536 HWSEQ_DCE112_MASK_SH_LIST(_MASK).DCFE_CLOCK_ENABLE = 0x80000000, .DC_MEM_GLOBAL_PWR_REQ_DIS =
0x1, .BLND_DCP_GRPH_V_UPDATE_LOCK = 0x1, .BLND_SCL_V_UPDATE_LOCK
= 0x10000000, .BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = 0x2, .BLND_BLND_V_UPDATE_LOCK
= 0x20000000, .BLND_V_UPDATE_LOCK_MODE = 0x80000000, .BLND_FEEDTHROUGH_EN
= 0x2000, .BLND_ALPHA_MODE = 0x30000, .BLND_MODE = 0x300, .BLND_MULTIPLIED_MODE
= 0x100000, .PIXEL_RATE_SOURCE = 0x3, .DP_DTO0_ENABLE = 0x10
, .PHYPLL_PIXEL_RATE_SOURCE = 0x7, .PIXEL_RATE_PLL_SOURCE = 0x10
537};
538
539static struct dce_hwseq *dce112_hwseq_create(
540 struct dc_context *ctx)
541{
542 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL(0x0001 | 0x0004));
543
544 if (hws) {
545 hws->ctx = ctx;
546 hws->regs = &hwseq_reg;
547 hws->shifts = &hwseq_shift;
548 hws->masks = &hwseq_mask;
549 }
550 return hws;
551}
552
553static const struct resource_create_funcs res_create_funcs = {
554 .read_dce_straps = read_dce_straps,
555 .create_audio = create_audio,
556 .create_stream_encoder = dce112_stream_encoder_create,
557 .create_hwseq = dce112_hwseq_create,
558};
559
560#define mi_inst_regs(id){ .GRPH_ENABLE = mmDCPid_GRPH_ENABLE, .GRPH_CONTROL = mmDCPid_GRPH_CONTROL
, .GRPH_X_START = mmDCPid_GRPH_X_START, .GRPH_Y_START = mmDCPid_GRPH_Y_START
, .GRPH_X_END = mmDCPid_GRPH_X_END, .GRPH_Y_END = mmDCPid_GRPH_Y_END
, .GRPH_PITCH = mmDCPid_GRPH_PITCH, .HW_ROTATION = mmDCPid_HW_ROTATION
, .GRPH_SWAP_CNTL = mmDCPid_GRPH_SWAP_CNTL, .PRESCALE_GRPH_CONTROL
= mmDCPid_PRESCALE_GRPH_CONTROL, .GRPH_UPDATE = mmDCPid_GRPH_UPDATE
, .GRPH_FLIP_CONTROL = mmDCPid_GRPH_FLIP_CONTROL, .GRPH_PRIMARY_SURFACE_ADDRESS
= mmDCPid_GRPH_PRIMARY_SURFACE_ADDRESS, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
= mmDCPid_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, .GRPH_SECONDARY_SURFACE_ADDRESS
= mmDCPid_GRPH_SECONDARY_SURFACE_ADDRESS, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
= mmDCPid_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, .DPG_PIPE_ARBITRATION_CONTROL1
= mmDMIF_PGid_DPG_PIPE_ARBITRATION_CONTROL1, .DPG_WATERMARK_MASK_CONTROL
= mmDMIF_PGid_DPG_WATERMARK_MASK_CONTROL, .DPG_PIPE_URGENCY_CONTROL
= mmDMIF_PGid_DPG_PIPE_URGENCY_CONTROL, .DPG_PIPE_STUTTER_CONTROL
= mmDMIF_PGid_DPG_PIPE_STUTTER_CONTROL, .DMIF_BUFFER_CONTROL
= mmPIPEid_DMIF_BUFFER_CONTROL, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL
= mmDMIF_PGid_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= mmDCPid_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT } { MI_DCE11_2_REG_LIST(id).GRPH_ENABLE = mmDCPid_GRPH_ENABLE, .GRPH_CONTROL = mmDCPid_GRPH_CONTROL
, .GRPH_X_START = mmDCPid_GRPH_X_START, .GRPH_Y_START = mmDCPid_GRPH_Y_START
, .GRPH_X_END = mmDCPid_GRPH_X_END, .GRPH_Y_END = mmDCPid_GRPH_Y_END
, .GRPH_PITCH = mmDCPid_GRPH_PITCH, .HW_ROTATION = mmDCPid_HW_ROTATION
, .GRPH_SWAP_CNTL = mmDCPid_GRPH_SWAP_CNTL, .PRESCALE_GRPH_CONTROL
= mmDCPid_PRESCALE_GRPH_CONTROL, .GRPH_UPDATE = mmDCPid_GRPH_UPDATE
, .GRPH_FLIP_CONTROL = mmDCPid_GRPH_FLIP_CONTROL, .GRPH_PRIMARY_SURFACE_ADDRESS
= mmDCPid_GRPH_PRIMARY_SURFACE_ADDRESS, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
= mmDCPid_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, .GRPH_SECONDARY_SURFACE_ADDRESS
= mmDCPid_GRPH_SECONDARY_SURFACE_ADDRESS, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
= mmDCPid_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, .DPG_PIPE_ARBITRATION_CONTROL1
= mmDMIF_PGid_DPG_PIPE_ARBITRATION_CONTROL1, .DPG_WATERMARK_MASK_CONTROL
= mmDMIF_PGid_DPG_WATERMARK_MASK_CONTROL, .DPG_PIPE_URGENCY_CONTROL
= mmDMIF_PGid_DPG_PIPE_URGENCY_CONTROL, .DPG_PIPE_STUTTER_CONTROL
= mmDMIF_PGid_DPG_PIPE_STUTTER_CONTROL, .DMIF_BUFFER_CONTROL
= mmPIPEid_DMIF_BUFFER_CONTROL, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL
= mmDMIF_PGid_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= mmDCPid_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT }
561static const struct dce_mem_input_registers mi_regs[] = {
562 mi_inst_regs(0){ .GRPH_ENABLE = 0x1a00, .GRPH_CONTROL = 0x1a01, .GRPH_X_START
= 0x1a0b, .GRPH_Y_START = 0x1a0c, .GRPH_X_END = 0x1a0d, .GRPH_Y_END
= 0x1a0e, .GRPH_PITCH = 0x1a06, .HW_ROTATION = 0x1a9e, .GRPH_SWAP_CNTL
= 0x1a03, .PRESCALE_GRPH_CONTROL = 0x1a2d, .GRPH_UPDATE = 0x1a11
, .GRPH_FLIP_CONTROL = 0x1a12, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x1a04, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x1a07, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x1a05, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x1a08, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x1b30, .DPG_WATERMARK_MASK_CONTROL = 0x1b32, .DPG_PIPE_URGENCY_CONTROL
= 0x1b33, .DPG_PIPE_STUTTER_CONTROL = 0x1b35, .DMIF_BUFFER_CONTROL
= 0x321, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x1b36, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x1a1c },
563 mi_inst_regs(1){ .GRPH_ENABLE = 0x1c00, .GRPH_CONTROL = 0x1c01, .GRPH_X_START
= 0x1c0b, .GRPH_Y_START = 0x1c0c, .GRPH_X_END = 0x1c0d, .GRPH_Y_END
= 0x1c0e, .GRPH_PITCH = 0x1c06, .HW_ROTATION = 0x1c9e, .GRPH_SWAP_CNTL
= 0x1c03, .PRESCALE_GRPH_CONTROL = 0x1c2d, .GRPH_UPDATE = 0x1c11
, .GRPH_FLIP_CONTROL = 0x1c12, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x1c04, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x1c07, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x1c05, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x1c08, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x1d30, .DPG_WATERMARK_MASK_CONTROL = 0x1d32, .DPG_PIPE_URGENCY_CONTROL
= 0x1d33, .DPG_PIPE_STUTTER_CONTROL = 0x1d35, .DMIF_BUFFER_CONTROL
= 0x322, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x1d36, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x1c1c },
564 mi_inst_regs(2){ .GRPH_ENABLE = 0x1e00, .GRPH_CONTROL = 0x1e01, .GRPH_X_START
= 0x1e0b, .GRPH_Y_START = 0x1e0c, .GRPH_X_END = 0x1e0d, .GRPH_Y_END
= 0x1e0e, .GRPH_PITCH = 0x1e06, .HW_ROTATION = 0x1e9e, .GRPH_SWAP_CNTL
= 0x1e03, .PRESCALE_GRPH_CONTROL = 0x1e2d, .GRPH_UPDATE = 0x1e11
, .GRPH_FLIP_CONTROL = 0x1e12, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x1e04, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x1e07, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x1e05, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x1e08, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x1f30, .DPG_WATERMARK_MASK_CONTROL = 0x1f32, .DPG_PIPE_URGENCY_CONTROL
= 0x1f33, .DPG_PIPE_STUTTER_CONTROL = 0x1f35, .DMIF_BUFFER_CONTROL
= 0x323, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x1f36, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x1e1c },
565 mi_inst_regs(3){ .GRPH_ENABLE = 0x4000, .GRPH_CONTROL = 0x4001, .GRPH_X_START
= 0x400b, .GRPH_Y_START = 0x400c, .GRPH_X_END = 0x400d, .GRPH_Y_END
= 0x400e, .GRPH_PITCH = 0x4006, .HW_ROTATION = 0x409e, .GRPH_SWAP_CNTL
= 0x4003, .PRESCALE_GRPH_CONTROL = 0x402d, .GRPH_UPDATE = 0x4011
, .GRPH_FLIP_CONTROL = 0x4012, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x4004, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x4007, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x4005, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x4008, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x4130, .DPG_WATERMARK_MASK_CONTROL = 0x4132, .DPG_PIPE_URGENCY_CONTROL
= 0x4133, .DPG_PIPE_STUTTER_CONTROL = 0x4135, .DMIF_BUFFER_CONTROL
= 0x324, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x4136, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x401c },
566 mi_inst_regs(4){ .GRPH_ENABLE = 0x4200, .GRPH_CONTROL = 0x4201, .GRPH_X_START
= 0x420b, .GRPH_Y_START = 0x420c, .GRPH_X_END = 0x420d, .GRPH_Y_END
= 0x420e, .GRPH_PITCH = 0x4206, .HW_ROTATION = 0x429e, .GRPH_SWAP_CNTL
= 0x4203, .PRESCALE_GRPH_CONTROL = 0x422d, .GRPH_UPDATE = 0x4211
, .GRPH_FLIP_CONTROL = 0x4212, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x4204, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x4207, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x4205, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x4208, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x4330, .DPG_WATERMARK_MASK_CONTROL = 0x4332, .DPG_PIPE_URGENCY_CONTROL
= 0x4333, .DPG_PIPE_STUTTER_CONTROL = 0x4335, .DMIF_BUFFER_CONTROL
= 0x325, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x4336, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x421c },
567 mi_inst_regs(5){ .GRPH_ENABLE = 0x4400, .GRPH_CONTROL = 0x4401, .GRPH_X_START
= 0x440b, .GRPH_Y_START = 0x440c, .GRPH_X_END = 0x440d, .GRPH_Y_END
= 0x440e, .GRPH_PITCH = 0x4406, .HW_ROTATION = 0x449e, .GRPH_SWAP_CNTL
= 0x4403, .PRESCALE_GRPH_CONTROL = 0x442d, .GRPH_UPDATE = 0x4411
, .GRPH_FLIP_CONTROL = 0x4412, .GRPH_PRIMARY_SURFACE_ADDRESS =
0x4404, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0x4407, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0x4405, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0x4408, .DPG_PIPE_ARBITRATION_CONTROL1
= 0x4530, .DPG_WATERMARK_MASK_CONTROL = 0x4532, .DPG_PIPE_URGENCY_CONTROL
= 0x4533, .DPG_PIPE_STUTTER_CONTROL = 0x4535, .DMIF_BUFFER_CONTROL
= 0x326, .DPG_PIPE_NB_PSTATE_CHANGE_CONTROL = 0x4536, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT
= 0x441c },
568};
569
570static const struct dce_mem_input_shift mi_shifts = {
571 MI_DCE11_2_MASK_SH_LIST(__SHIFT).GRPH_ENABLE = 0x0, .GRPH_DEPTH = 0x0, .GRPH_FORMAT = 0x8, .GRPH_NUM_BANKS
= 0x2, .GRPH_X_START = 0x0, .GRPH_Y_START = 0x0, .GRPH_X_END
= 0x0, .GRPH_Y_END = 0x0, .GRPH_PITCH = 0x0, .GRPH_ROTATION_ANGLE
= 0x0, .GRPH_RED_CROSSBAR = 0x4, .GRPH_BLUE_CROSSBAR = 0x8, .
GRPH_PRESCALE_SELECT = 0x0, .GRPH_PRESCALE_R_SIGN = 0x1, .GRPH_PRESCALE_G_SIGN
= 0x2, .GRPH_PRESCALE_B_SIGN = 0x3, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x0, .GRPH_SECONDARY_SURFACE_ADDRESS = 0x8, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
= 0x0, .GRPH_PRIMARY_SURFACE_ADDRESS = 0x8, .GRPH_SURFACE_UPDATE_PENDING
= 0x2, .GRPH_UPDATE_LOCK = 0x10, .GRPH_SURFACE_UPDATE_H_RETRACE_EN
= 0x0, .PIXEL_DURATION = 0x0, .URGENCY_WATERMARK_MASK = 0x8,
.STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK = 0x0, .URGENCY_LOW_WATERMARK
= 0x0, .URGENCY_HIGH_WATERMARK = 0x10, .STUTTER_ENABLE = 0x0
, .STUTTER_IGNORE_FBC = 0x7, .DMIF_BUFFERS_ALLOCATED = 0x0, .
DMIF_BUFFERS_ALLOCATION_COMPLETED = 0x4, .STUTTER_EXIT_SELF_REFRESH_WATERMARK
= 0x10, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x10, .NB_PSTATE_CHANGE_ENABLE
= 0x0, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x4, .NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST
= 0x8, .NB_PSTATE_CHANGE_WATERMARK = 0xf, .GRPH_NUM_BANKS = 0x2
, .GRPH_BANK_WIDTH = 0x6, .GRPH_BANK_HEIGHT = 0xb, .GRPH_MACRO_TILE_ASPECT
= 0x12, .GRPH_TILE_SPLIT = 0xd, .GRPH_MICRO_TILE_MODE = 0x1d
, .GRPH_PIPE_CONFIG = 0x18, .GRPH_ARRAY_MODE = 0x14, .GRPH_COLOR_EXPANSION_MODE
= 0x1f, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT = 0x0
572};
573
574static const struct dce_mem_input_mask mi_masks = {
575 MI_DCE11_2_MASK_SH_LIST(_MASK).GRPH_ENABLE = 0x1, .GRPH_DEPTH = 0x3, .GRPH_FORMAT = 0x700, .
GRPH_NUM_BANKS = 0xc, .GRPH_X_START = 0x3fff, .GRPH_Y_START =
0x3fff, .GRPH_X_END = 0x7fff, .GRPH_Y_END = 0x7fff, .GRPH_PITCH
= 0x7fff, .GRPH_ROTATION_ANGLE = 0x7, .GRPH_RED_CROSSBAR = 0x30
, .GRPH_BLUE_CROSSBAR = 0x300, .GRPH_PRESCALE_SELECT = 0x1, .
GRPH_PRESCALE_R_SIGN = 0x2, .GRPH_PRESCALE_G_SIGN = 0x4, .GRPH_PRESCALE_B_SIGN
= 0x8, .GRPH_SECONDARY_SURFACE_ADDRESS_HIGH = 0xff, .GRPH_SECONDARY_SURFACE_ADDRESS
= 0xffffff00, .GRPH_PRIMARY_SURFACE_ADDRESS_HIGH = 0xff, .GRPH_PRIMARY_SURFACE_ADDRESS
= 0xffffff00, .GRPH_SURFACE_UPDATE_PENDING = 0x4, .GRPH_UPDATE_LOCK
= 0x10000, .GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0x1, .PIXEL_DURATION
= 0xffff, .URGENCY_WATERMARK_MASK = 0x700, .STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK
= 0x7, .URGENCY_LOW_WATERMARK = 0xffff, .URGENCY_HIGH_WATERMARK
= 0xffff0000, .STUTTER_ENABLE = 0x1, .STUTTER_IGNORE_FBC = 0x80
, .DMIF_BUFFERS_ALLOCATED = 0x7, .DMIF_BUFFERS_ALLOCATION_COMPLETED
= 0x10, .STUTTER_EXIT_SELF_REFRESH_WATERMARK = 0xffff0000, .
NB_PSTATE_CHANGE_WATERMARK_MASK = 0x70000, .NB_PSTATE_CHANGE_ENABLE
= 0x1, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x10, .NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST
= 0x100, .NB_PSTATE_CHANGE_WATERMARK = 0xffff8000, .GRPH_NUM_BANKS
= 0xc, .GRPH_BANK_WIDTH = 0xc0, .GRPH_BANK_HEIGHT = 0x1800, .
GRPH_MACRO_TILE_ASPECT = 0xc0000, .GRPH_TILE_SPLIT = 0xe000, .
GRPH_MICRO_TILE_MODE = 0x60000000, .GRPH_PIPE_CONFIG = 0x1f000000
, .GRPH_ARRAY_MODE = 0xf00000, .GRPH_COLOR_EXPANSION_MODE = 0x80000000
, .GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT = 0xff
576};
577
578static struct mem_input *dce112_mem_input_create(
579 struct dc_context *ctx,
580 uint32_t inst)
581{
582 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
583 GFP_KERNEL(0x0001 | 0x0004));
584
585 if (!dce_mi) {
586 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 586); do
{} while (0); } while (0);
587 return NULL((void *)0);
588 }
589
590 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
591 return &dce_mi->base;
592}
593
594static void dce112_transform_destroy(struct transform **xfm)
595{
596 kfree(TO_DCE_TRANSFORM(*xfm)({ const __typeof( ((struct dce_transform *)0)->base ) *__mptr
= (*xfm); (struct dce_transform *)( (char *)__mptr - __builtin_offsetof
(struct dce_transform, base) );}));
597 *xfm = NULL((void *)0);
598}
599
600static struct transform *dce112_transform_create(
601 struct dc_context *ctx,
602 uint32_t inst)
603{
604 struct dce_transform *transform =
605 kzalloc(sizeof(struct dce_transform), GFP_KERNEL(0x0001 | 0x0004));
606
607 if (!transform)
608 return NULL((void *)0);
609
610 dce_transform_construct(transform, ctx, inst,
611 &xfm_regs[inst], &xfm_shift, &xfm_mask);
612 transform->lb_memory_size = 0x1404; /*5124*/
613 return &transform->base;
614}
615
616static const struct encoder_feature_support link_enc_feature = {
617 .max_hdmi_deep_color = COLOR_DEPTH_121212,
618 .max_hdmi_pixel_clock = 600000,
619 .hdmi_ycbcr420_supported = true1,
620 .dp_ycbcr420_supported = false0,
621 .flags.bits.IS_HBR2_CAPABLE = true1,
622 .flags.bits.IS_HBR3_CAPABLE = true1,
623 .flags.bits.IS_TPS3_CAPABLE = true1,
624 .flags.bits.IS_TPS4_CAPABLE = true1
625};
626
627struct link_encoder *dce112_link_encoder_create(
628 const struct encoder_init_data *enc_init_data)
629{
630 struct dce110_link_encoder *enc110 =
631 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL(0x0001 | 0x0004));
632 int link_regs_id;
633
634 if (!enc110)
635 return NULL((void *)0);
636
637 link_regs_id =
638 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
639
640 dce110_link_encoder_construct(enc110,
641 enc_init_data,
642 &link_enc_feature,
643 &link_enc_regs[link_regs_id],
644 &link_enc_aux_regs[enc_init_data->channel - 1],
645 &link_enc_hpd_regs[enc_init_data->hpd_source]);
646 return &enc110->base;
647}
648
649static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
650{
651 struct dce_panel_cntl *panel_cntl =
652 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL(0x0001 | 0x0004));
653
654 if (!panel_cntl)
655 return NULL((void *)0);
656
657 dce_panel_cntl_construct(panel_cntl,
658 init_data,
659 &panel_cntl_regs[init_data->inst],
660 &panel_cntl_shift,
661 &panel_cntl_mask);
662
663 return &panel_cntl->base;
664}
665
666static struct input_pixel_processor *dce112_ipp_create(
667 struct dc_context *ctx, uint32_t inst)
668{
669 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL(0x0001 | 0x0004));
670
671 if (!ipp) {
672 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 672); do
{} while (0); } while (0);
673 return NULL((void *)0);
674 }
675
676 dce_ipp_construct(ipp, ctx, inst,
677 &ipp_regs[inst], &ipp_shift, &ipp_mask);
678 return &ipp->base;
679}
680
681struct output_pixel_processor *dce112_opp_create(
682 struct dc_context *ctx,
683 uint32_t inst)
684{
685 struct dce110_opp *opp =
686 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL(0x0001 | 0x0004));
687
688 if (!opp)
689 return NULL((void *)0);
690
691 dce110_opp_construct(opp,
692 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
693 return &opp->base;
694}
695
696struct dce_aux *dce112_aux_engine_create(
697 struct dc_context *ctx,
698 uint32_t inst)
699{
700 struct aux_engine_dce110 *aux_engine =
701 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL(0x0001 | 0x0004));
702
703 if (!aux_engine)
704 return NULL((void *)0);
705
706 dce110_aux_engine_construct(aux_engine, ctx, inst,
707 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
708 &aux_engine_regs[inst],
709 &aux_mask,
710 &aux_shift,
711 ctx->dc->caps.extended_aux_timeout_support);
712
713 return &aux_engine->base;
714}
715#define i2c_inst_regs(id){ .SETUP = mmDC_I2C_DDCid_SETUP, .SPEED = mmDC_I2C_DDCid_SPEED
, .HW_STATUS = mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION =
0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b } { I2C_HW_ENGINE_COMMON_REG_LIST(id).SETUP = mmDC_I2C_DDCid_SETUP, .SPEED = mmDC_I2C_DDCid_SPEED,
.HW_STATUS = mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION =
0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b }
716
717static const struct dce_i2c_registers i2c_hw_regs[] = {
718 i2c_inst_regs(1){ .SETUP = 0x16df, .SPEED = 0x16de, .HW_STATUS = 0x16d8, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
719 i2c_inst_regs(2){ .SETUP = 0x16e1, .SPEED = 0x16e0, .HW_STATUS = 0x16d9, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
720 i2c_inst_regs(3){ .SETUP = 0x16e3, .SPEED = 0x16e2, .HW_STATUS = 0x16da, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
721 i2c_inst_regs(4){ .SETUP = 0x16e5, .SPEED = 0x16e4, .HW_STATUS = 0x16db, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
722 i2c_inst_regs(5){ .SETUP = 0x16e7, .SPEED = 0x16e6, .HW_STATUS = 0x16dc, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
723 i2c_inst_regs(6){ .SETUP = 0x16e9, .SPEED = 0x16e8, .HW_STATUS = 0x16dd, .DC_I2C_ARBITRATION
= 0x16d5, .DC_I2C_CONTROL = 0x16d4, .DC_I2C_SW_STATUS = 0x16d7
, .DC_I2C_TRANSACTION0 = 0x16ea, .DC_I2C_TRANSACTION1 = 0x16eb
, .DC_I2C_TRANSACTION2 = 0x16ec, .DC_I2C_TRANSACTION3 = 0x16ed
, .DC_I2C_DATA = 0x16ee, .MICROSECOND_TIME_BASE_DIV = 0x13b },
724};
725
726static const struct dce_i2c_shift i2c_shifts = {
727 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN
= 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL
= 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY
= 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ
= 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO
= 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, .
DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET
= 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT =
0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0
, .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5,
.DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS
= 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0
= 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW
= 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE
= 0x1f, .XTAL_REF_DIV = 0x8, .DC_I2C_REG_RW_CNTL_STATUS = 0x2
, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x8
728};
729
730static const struct dce_i2c_mask i2c_masks = {
731 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK).DC_I2C_DDC1_ENABLE = 0x40, .DC_I2C_DDC1_TIME_LIMIT = 0xff000000
, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x1, .DC_I2C_DDC1_CLK_DRIVE_EN
= 0x80, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x2, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY
= 0xff0000, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0xff00, .DC_I2C_DDC1_HW_STATUS
= 0x3, .DC_I2C_SW_USE_I2C_REG_REQ = 0x100000, .DC_I2C_SW_DONE_USING_I2C_REG
= 0x200000, .DC_I2C_NO_QUEUED_SW_GO = 0x10, .DC_I2C_SW_PRIORITY
= 0x3, .DC_I2C_SOFT_RESET = 0x2, .DC_I2C_SW_STATUS_RESET = 0x8
, .DC_I2C_GO = 0x1, .DC_I2C_SEND_RESET = 0x4, .DC_I2C_TRANSACTION_COUNT
= 0x300000, .DC_I2C_DDC_SELECT = 0x700, .DC_I2C_DDC1_PRESCALE
= 0xffff0000, .DC_I2C_DDC1_THRESHOLD = 0x3, .DC_I2C_SW_STOPPED_ON_NACK
= 0x100, .DC_I2C_SW_TIMEOUT = 0x20, .DC_I2C_SW_ABORTED = 0x10
, .DC_I2C_SW_DONE = 0x4, .DC_I2C_SW_STATUS = 0x3, .DC_I2C_STOP_ON_NACK0
= 0x100, .DC_I2C_START0 = 0x1000, .DC_I2C_RW0 = 0x1, .DC_I2C_STOP0
= 0x2000, .DC_I2C_COUNT0 = 0x3ff0000, .DC_I2C_DATA_RW = 0x1,
.DC_I2C_DATA = 0xff00, .DC_I2C_INDEX = 0x3ff0000, .DC_I2C_INDEX_WRITE
= 0x80000000, .XTAL_REF_DIV = 0x7f00, .DC_I2C_REG_RW_CNTL_STATUS
= 0xc, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x300
732};
733
734struct dce_i2c_hw *dce112_i2c_hw_create(
735 struct dc_context *ctx,
736 uint32_t inst)
737{
738 struct dce_i2c_hw *dce_i2c_hw =
739 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL(0x0001 | 0x0004));
740
741 if (!dce_i2c_hw)
742 return NULL((void *)0);
743
744 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
745 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
746
747 return dce_i2c_hw;
748}
749struct clock_source *dce112_clock_source_create(
750 struct dc_context *ctx,
751 struct dc_bios *bios,
752 enum clock_source_id id,
753 const struct dce110_clk_src_regs *regs,
754 bool_Bool dp_clk_src)
755{
756 struct dce110_clk_src *clk_src =
757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL(0x0001 | 0x0004));
758
759 if (!clk_src)
760 return NULL((void *)0);
761
762 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
763 regs, &cs_shift, &cs_mask)) {
764 clk_src->base.dp_clk_src = dp_clk_src;
765 return &clk_src->base;
766 }
767
768 kfree(clk_src);
769 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 769); do
{} while (0); } while (0);
770 return NULL((void *)0);
771}
772
773void dce112_clock_source_destroy(struct clock_source **clk_src)
774{
775 kfree(TO_DCE110_CLK_SRC(*clk_src)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr
= (*clk_src); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof
(struct dce110_clk_src, base) );}));
776 *clk_src = NULL((void *)0);
777}
778
779static void dce112_resource_destruct(struct dce110_resource_pool *pool)
780{
781 unsigned int i;
782
783 for (i = 0; i < pool->base.pipe_count; i++) {
784 if (pool->base.opps[i] != NULL((void *)0))
785 dce110_opp_destroy(&pool->base.opps[i]);
786
787 if (pool->base.transforms[i] != NULL((void *)0))
788 dce112_transform_destroy(&pool->base.transforms[i]);
789
790 if (pool->base.ipps[i] != NULL((void *)0))
791 dce_ipp_destroy(&pool->base.ipps[i]);
792
793 if (pool->base.mis[i] != NULL((void *)0)) {
794 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr
= (pool->base.mis[i]); (struct dce_mem_input *)( (char *)
__mptr - __builtin_offsetof(struct dce_mem_input, base) );}));
795 pool->base.mis[i] = NULL((void *)0);
796 }
797
798 if (pool->base.timing_generators[i] != NULL((void *)0)) {
799 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct dce110_timing_generator *)0)->
base ) *__mptr = (pool->base.timing_generators[i]); (struct
dce110_timing_generator *)( (char *)__mptr - __builtin_offsetof
(struct dce110_timing_generator, base) );}));
800 pool->base.timing_generators[i] = NULL((void *)0);
801 }
802 }
803
804 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
805 if (pool->base.engines[i] != NULL((void *)0))
806 dce110_engine_destroy(&pool->base.engines[i]);
807 if (pool->base.hw_i2cs[i] != NULL((void *)0)) {
808 kfree(pool->base.hw_i2cs[i]);
809 pool->base.hw_i2cs[i] = NULL((void *)0);
810 }
811 if (pool->base.sw_i2cs[i] != NULL((void *)0)) {
812 kfree(pool->base.sw_i2cs[i]);
813 pool->base.sw_i2cs[i] = NULL((void *)0);
814 }
815 }
816
817 for (i = 0; i < pool->base.stream_enc_count; i++) {
818 if (pool->base.stream_enc[i] != NULL((void *)0))
819 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (pool->base.stream_enc[i]); (struct dce110_stream_encoder
*)( (char *)__mptr - __builtin_offsetof(struct dce110_stream_encoder
, base) );}));
820 }
821
822 for (i = 0; i < pool->base.clk_src_count; i++) {
823 if (pool->base.clock_sources[i] != NULL((void *)0)) {
824 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
825 }
826 }
827
828 if (pool->base.dp_clock_source != NULL((void *)0))
829 dce112_clock_source_destroy(&pool->base.dp_clock_source);
830
831 for (i = 0; i < pool->base.audio_count; i++) {
832 if (pool->base.audios[i] != NULL((void *)0)) {
833 dce_aud_destroy(&pool->base.audios[i]);
834 }
835 }
836
837 if (pool->base.abm != NULL((void *)0))
838 dce_abm_destroy(&pool->base.abm);
839
840 if (pool->base.dmcu != NULL((void *)0))
841 dce_dmcu_destroy(&pool->base.dmcu);
842
843 if (pool->base.irqs != NULL((void *)0)) {
844 dal_irq_service_destroy(&pool->base.irqs);
845 }
846}
847
848static struct clock_source *find_matching_pll(
849 struct resource_context *res_ctx,
850 const struct resource_pool *pool,
851 const struct dc_stream_state *const stream)
852{
853 switch (stream->link->link_enc->transmitter) {
854 case TRANSMITTER_UNIPHY_A:
855 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
856 case TRANSMITTER_UNIPHY_B:
857 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
858 case TRANSMITTER_UNIPHY_C:
859 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
860 case TRANSMITTER_UNIPHY_D:
861 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
862 case TRANSMITTER_UNIPHY_E:
863 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
864 case TRANSMITTER_UNIPHY_F:
865 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
866 default:
867 return NULL((void *)0);
868 };
869
870 return 0;
871}
872
873static enum dc_status build_mapped_resource(
874 const struct dc *dc,
875 struct dc_state *context,
876 struct dc_stream_state *stream)
877{
878 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
879
880 if (!pipe_ctx)
881 return DC_ERROR_UNEXPECTED;
882
883 dce110_resource_build_pipe_hw_param(pipe_ctx);
884
885 resource_build_info_frame(pipe_ctx);
886
887 return DC_OK;
888}
889
890bool_Bool dce112_validate_bandwidth(
891 struct dc *dc,
892 struct dc_state *context,
893 bool_Bool fast_validate)
894{
895 bool_Bool result = false0;
896
897 DC_LOG_BANDWIDTH_CALCS(do { } while(0)
898 "%s: start",do { } while(0)
899 __func__)do { } while(0);
900
901 if (bw_calcs(
902 dc->ctx,
903 dc->bw_dceip,
904 dc->bw_vbios,
905 context->res_ctx.pipe_ctx,
906 dc->res_pool->pipe_count,
907 &context->bw_ctx.bw.dce))
908 result = true1;
909
910 if (!result)
911 DC_LOG_BANDWIDTH_VALIDATION(__drm_dbg(DRM_UT_KMS, "%s: Bandwidth validation failed!", __func__
)
912 "%s: Bandwidth validation failed!",__drm_dbg(DRM_UT_KMS, "%s: Bandwidth validation failed!", __func__
)
913 __func__)__drm_dbg(DRM_UT_KMS, "%s: Bandwidth validation failed!", __func__
);
914
915 if (memcmp(&dc->current_state->bw_ctx.bw.dce,__builtin_memcmp((&dc->current_state->bw_ctx.bw.dce
), (&context->bw_ctx.bw.dce), (sizeof(context->bw_ctx
.bw.dce)))
916 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))__builtin_memcmp((&dc->current_state->bw_ctx.bw.dce
), (&context->bw_ctx.bw.dce), (sizeof(context->bw_ctx
.bw.dce)))) {
917
918 DC_LOG_BANDWIDTH_CALCS(do { } while(0)
919 "%s: finish,\n"do { } while(0)
920 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"do { } while(0)
921 "stutMark_b: %d stutMark_a: %d\n"do { } while(0)
922 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"do { } while(0)
923 "stutMark_b: %d stutMark_a: %d\n"do { } while(0)
924 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"do { } while(0)
925 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"do { } while(0)
926 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"do { } while(0)
927 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"do { } while(0)
928 ,do { } while(0)
929 __func__,do { } while(0)
930 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,do { } while(0)
931 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,do { } while(0)
932 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,do { } while(0)
933 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,do { } while(0)
934 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,do { } while(0)
935 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,do { } while(0)
936 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,do { } while(0)
937 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,do { } while(0)
938 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,do { } while(0)
939 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,do { } while(0)
940 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,do { } while(0)
941 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,do { } while(0)
942 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,do { } while(0)
943 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,do { } while(0)
944 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,do { } while(0)
945 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,do { } while(0)
946 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,do { } while(0)
947 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,do { } while(0)
948 context->bw_ctx.bw.dce.stutter_mode_enable,do { } while(0)
949 context->bw_ctx.bw.dce.cpuc_state_change_enable,do { } while(0)
950 context->bw_ctx.bw.dce.cpup_state_change_enable,do { } while(0)
951 context->bw_ctx.bw.dce.nbp_state_change_enable,do { } while(0)
952 context->bw_ctx.bw.dce.all_displays_in_sync,do { } while(0)
953 context->bw_ctx.bw.dce.dispclk_khz,do { } while(0)
954 context->bw_ctx.bw.dce.sclk_khz,do { } while(0)
955 context->bw_ctx.bw.dce.sclk_deep_sleep_khz,do { } while(0)
956 context->bw_ctx.bw.dce.yclk_khz,do { } while(0)
957 context->bw_ctx.bw.dce.blackout_recovery_time_us)do { } while(0);
958 }
959 return result;
960}
961
962enum dc_status resource_map_phy_clock_resources(
963 const struct dc *dc,
964 struct dc_state *context,
965 struct dc_stream_state *stream)
966{
967
968 /* acquire new resources */
969 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
970 &context->res_ctx, stream);
971
972 if (!pipe_ctx)
973 return DC_ERROR_UNEXPECTED;
974
975 if (dc_is_dp_signal(pipe_ctx->stream->signal)
976 || dc_is_virtual_signal(pipe_ctx->stream->signal))
977 pipe_ctx->clock_source =
978 dc->res_pool->dp_clock_source;
979 else
980 pipe_ctx->clock_source = find_matching_pll(
981 &context->res_ctx, dc->res_pool,
982 stream);
983
984 if (pipe_ctx->clock_source == NULL((void *)0))
985 return DC_NO_CLOCK_SOURCE_RESOURCE;
986
987 resource_reference_clock_source(
988 &context->res_ctx,
989 dc->res_pool,
990 pipe_ctx->clock_source);
991
992 return DC_OK;
993}
994
995static bool_Bool dce112_validate_surface_sets(
996 struct dc_state *context)
997{
998 int i;
999
1000 for (i = 0; i < context->stream_count; i++) {
1001 if (context->stream_status[i].plane_count == 0)
1002 continue;
1003
1004 if (context->stream_status[i].plane_count > 1)
1005 return false0;
1006
1007 if (context->stream_status[i].plane_states[0]->format
1008 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1009 return false0;
1010 }
1011
1012 return true1;
1013}
1014
1015enum dc_status dce112_add_stream_to_ctx(
1016 struct dc *dc,
1017 struct dc_state *new_ctx,
1018 struct dc_stream_state *dc_stream)
1019{
1020 enum dc_status result;
1021
1022 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1023
1024 if (result == DC_OK)
1025 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1026
1027
1028 if (result == DC_OK)
1029 result = build_mapped_resource(dc, new_ctx, dc_stream);
1030
1031 return result;
1032}
1033
1034enum dc_status dce112_validate_global(
1035 struct dc *dc,
1036 struct dc_state *context)
1037{
1038 if (!dce112_validate_surface_sets(context))
1039 return DC_FAIL_SURFACE_VALIDATE;
1040
1041 return DC_OK;
1042}
1043
1044static void dce112_destroy_resource_pool(struct resource_pool **pool)
1045{
1046 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool)({ const __typeof( ((struct dce110_resource_pool *)0)->base
) *__mptr = (*pool); (struct dce110_resource_pool *)( (char *
)__mptr - __builtin_offsetof(struct dce110_resource_pool, base
) );});
1047
1048 dce112_resource_destruct(dce110_pool);
1049 kfree(dce110_pool);
1050 *pool = NULL((void *)0);
1051}
1052
1053static const struct resource_funcs dce112_res_pool_funcs = {
1054 .destroy = dce112_destroy_resource_pool,
1055 .link_enc_create = dce112_link_encoder_create,
1056 .panel_cntl_create = dce112_panel_cntl_create,
1057 .validate_bandwidth = dce112_validate_bandwidth,
1058 .validate_plane = dce100_validate_plane,
1059 .add_stream_to_ctx = dce112_add_stream_to_ctx,
1060 .validate_global = dce112_validate_global,
1061 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1062};
1063
1064static void bw_calcs_data_update_from_pplib(struct dc *dc)
1065{
1066 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1067 struct dm_pp_clock_levels_with_latency mem_clks = {0};
1068 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1069 struct dm_pp_clock_levels clks = {0};
1070 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ4;
1071
1072 if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
1
Assuming field 'bw_vbios' is null
→
1073 memory_type_multiplier = MEMORY_TYPE_HBM2;
1074
1075 /*do system clock TODO PPLIB: after PPLIB implement,
1076 * then remove old way
1077 */
1078 if (!dm_pp_get_clock_levels_by_type_with_latency(
2
←
Assuming the condition is false
→
3
←
Taking false branch
→
1079 dc->ctx,
1080 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1081 &eng_clks)) {
1082
1083 /* This is only for temporary */
1084 dm_pp_get_clock_levels_by_type(
1085 dc->ctx,
1086 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1087 &clks);
1088 /* convert all the clock fro kHz to fix point mHz */
1089 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1090 clks.clocks_in_khz[clks.num_levels-1], 1000);
1091 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1092 clks.clocks_in_khz[clks.num_levels/8], 1000);
1093 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1094 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1095 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1096 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1097 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1098 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1099 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1100 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1101 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1102 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1103 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1104 clks.clocks_in_khz[0], 1000);
1105
1106 /*do memory clock*/
1107 dm_pp_get_clock_levels_by_type(
1108 dc->ctx,
1109 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1110 &clks);
1111
1112 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1113 clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1114 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1115 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1116 1000);
1117 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1118 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1119 1000);
1120
1121 return;
1122 }
1123
1124 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1125 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
4
←
Access to field 'high_sclk' results in a dereference of a null pointer (loaded from field 'bw_vbios')
1126 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1127 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1128 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1129 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1130 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1131 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1132 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1133 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1134 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1135 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1136 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1137 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1138 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1139 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1140 eng_clks.data[0].clocks_in_khz, 1000);
1141
1142 /*do memory clock*/
1143 dm_pp_get_clock_levels_by_type_with_latency(
1144 dc->ctx,
1145 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1146 &mem_clks);
1147
1148 /* we don't need to call PPLIB for validation clock since they
1149 * also give us the highest sclk and highest mclk (UMA clock).
1150 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1151 * YCLK = UMACLK*m_memoryTypeMultiplier
1152 */
1153 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1154 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1155 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1156 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1157 1000);
1158 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1159 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1160 1000);
1161
1162 /* Now notify PPLib/SMU about which Watermarks sets they should select
1163 * depending on DPM state they are in. And update BW MGR GFX Engine and
1164 * Memory clock member variables for Watermarks calculations for each
1165 * Watermark Set
1166 */
1167 clk_ranges.num_wm_sets = 4;
1168 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1169 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1170 eng_clks.data[0].clocks_in_khz;
1171 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1172 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1173 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1174 mem_clks.data[0].clocks_in_khz;
1175 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1176 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1177
1178 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1179 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1180 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1181 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1182 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1183 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1184 mem_clks.data[0].clocks_in_khz;
1185 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1186 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1187
1188 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1189 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1190 eng_clks.data[0].clocks_in_khz;
1191 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1192 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1193 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1194 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1195 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1196 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1197
1198 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1199 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1200 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1201 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1202 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1203 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1204 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1205 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1206 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1207
1208 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1209 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1210}
1211
1212const struct resource_caps *dce112_resource_cap(
1213 struct hw_asic_id *asic_id)
1214{
1215 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev)((asic_id->hw_internal_rev >= 90) && (asic_id->
hw_internal_rev < 100)) ||
1216 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)((asic_id->hw_internal_rev >= 100) && (asic_id->
hw_internal_rev < 110)))
1217 return &polaris_11_resource_cap;
1218 else
1219 return &polaris_10_resource_cap;
1220}
1221
1222static bool_Bool dce112_resource_construct(
1223 uint8_t num_virtual_links,
1224 struct dc *dc,
1225 struct dce110_resource_pool *pool)
1226{
1227 unsigned int i;
1228 struct dc_context *ctx = dc->ctx;
1229
1230 ctx->dc_bios->regs = &bios_regs;
1231
1232 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1233 pool->base.funcs = &dce112_res_pool_funcs;
1234
1235 /*************************************************
1236 * Resource + asic cap harcoding *
1237 *************************************************/
1238 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1;
1239 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1240 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1241 dc->caps.max_downscale_ratio = 200;
1242 dc->caps.i2c_speed_in_khz = 100;
1243 dc->caps.max_cursor_size = 128;
1244 dc->caps.dual_link_dvi = true1;
1245 dc->caps.extended_aux_timeout_support = false0;
1246
1247 /*************************************************
1248 * Create resources *
1249 *************************************************/
1250
1251 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1252 dce112_clock_source_create(
1253 ctx, ctx->dc_bios,
1254 CLOCK_SOURCE_COMBO_PHY_PLL0,
1255 &clk_src_regs[0], false0);
1256 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1257 dce112_clock_source_create(
1258 ctx, ctx->dc_bios,
1259 CLOCK_SOURCE_COMBO_PHY_PLL1,
1260 &clk_src_regs[1], false0);
1261 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1262 dce112_clock_source_create(
1263 ctx, ctx->dc_bios,
1264 CLOCK_SOURCE_COMBO_PHY_PLL2,
1265 &clk_src_regs[2], false0);
1266 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1267 dce112_clock_source_create(
1268 ctx, ctx->dc_bios,
1269 CLOCK_SOURCE_COMBO_PHY_PLL3,
1270 &clk_src_regs[3], false0);
1271 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1272 dce112_clock_source_create(
1273 ctx, ctx->dc_bios,
1274 CLOCK_SOURCE_COMBO_PHY_PLL4,
1275 &clk_src_regs[4], false0);
1276 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1277 dce112_clock_source_create(
1278 ctx, ctx->dc_bios,
1279 CLOCK_SOURCE_COMBO_PHY_PLL5,
1280 &clk_src_regs[5], false0);
1281 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1282
1283 pool->base.dp_clock_source = dce112_clock_source_create(
1284 ctx, ctx->dc_bios,
1285 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true1);
1286
1287
1288 for (i = 0; i < pool->base.clk_src_count; i++) {
1289 if (pool->base.clock_sources[i] == NULL((void *)0)) {
1290 dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n");
1291 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1291); do
{} while (0); } while (0);
1292 goto res_create_fail;
1293 }
1294 }
1295
1296 pool->base.dmcu = dce_dmcu_create(ctx,
1297 &dmcu_regs,
1298 &dmcu_shift,
1299 &dmcu_mask);
1300 if (pool->base.dmcu == NULL((void *)0)) {
1301 dm_error("DC: failed to create dmcu!\n")__drm_err("DC: failed to create dmcu!\n");
1302 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1302); do
{} while (0); } while (0);
1303 goto res_create_fail;
1304 }
1305
1306 pool->base.abm = dce_abm_create(ctx,
1307 &abm_regs,
1308 &abm_shift,
1309 &abm_mask);
1310 if (pool->base.abm == NULL((void *)0)) {
1311 dm_error("DC: failed to create abm!\n")__drm_err("DC: failed to create abm!\n");
1312 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1312); do
{} while (0); } while (0);
1313 goto res_create_fail;
1314 }
1315
1316 {
1317 struct irq_service_init_data init_data;
1318 init_data.ctx = dc->ctx;
1319 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1320 if (!pool->base.irqs)
1321 goto res_create_fail;
1322 }
1323
1324 for (i = 0; i < pool->base.pipe_count; i++) {
1325 pool->base.timing_generators[i] =
1326 dce112_timing_generator_create(
1327 ctx,
1328 i,
1329 &dce112_tg_offsets[i]);
1330 if (pool->base.timing_generators[i] == NULL((void *)0)) {
1331 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1331); do
{} while (0); } while (0);
1332 dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n");
1333 goto res_create_fail;
1334 }
1335
1336 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1337 if (pool->base.mis[i] == NULL((void *)0)) {
1338 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1338); do
{} while (0); } while (0);
1339 dm_error(__drm_err("DC: failed to create memory input!\n")
1340 "DC: failed to create memory input!\n")__drm_err("DC: failed to create memory input!\n");
1341 goto res_create_fail;
1342 }
1343
1344 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1345 if (pool->base.ipps[i] == NULL((void *)0)) {
1346 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1346); do
{} while (0); } while (0);
1347 dm_error(__drm_err("DC:failed to create input pixel processor!\n")
1348 "DC:failed to create input pixel processor!\n")__drm_err("DC:failed to create input pixel processor!\n");
1349 goto res_create_fail;
1350 }
1351
1352 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1353 if (pool->base.transforms[i] == NULL((void *)0)) {
1354 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1354); do
{} while (0); } while (0);
1355 dm_error(__drm_err("DC: failed to create transform!\n")
1356 "DC: failed to create transform!\n")__drm_err("DC: failed to create transform!\n");
1357 goto res_create_fail;
1358 }
1359
1360 pool->base.opps[i] = dce112_opp_create(
1361 ctx,
1362 i);
1363 if (pool->base.opps[i] == NULL((void *)0)) {
1364 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1364); do
{} while (0); } while (0);
1365 dm_error(__drm_err("DC:failed to create output pixel processor!\n")
1366 "DC:failed to create output pixel processor!\n")__drm_err("DC:failed to create output pixel processor!\n");
1367 goto res_create_fail;
1368 }
1369 }
1370
1371 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1372 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1373 if (pool->base.engines[i] == NULL((void *)0)) {
1374 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1374); do
{} while (0); } while (0);
1375 dm_error(__drm_err("DC:failed to create aux engine!!\n")
1376 "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n");
1377 goto res_create_fail;
1378 }
1379 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1380 if (pool->base.hw_i2cs[i] == NULL((void *)0)) {
1381 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1381); do
{} while (0); } while (0);
1382 dm_error(__drm_err("DC:failed to create i2c engine!!\n")
1383 "DC:failed to create i2c engine!!\n")__drm_err("DC:failed to create i2c engine!!\n");
1384 goto res_create_fail;
1385 }
1386 pool->base.sw_i2cs[i] = NULL((void *)0);
1387 }
1388
1389 if (!resource_construct(num_virtual_links, dc, &pool->base,
1390 &res_create_funcs))
1391 goto res_create_fail;
1392
1393 dc->caps.max_planes = pool->base.pipe_count;
1394
1395 for (i = 0; i < dc->caps.max_planes; ++i)
1396 dc->caps.planes[i] = plane_cap;
1397
1398 /* Create hardware sequencer */
1399 dce112_hw_sequencer_construct(dc);
1400
1401 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1402
1403 bw_calcs_data_update_from_pplib(dc);
1404
1405 return true1;
1406
1407res_create_fail:
1408 dce112_resource_destruct(pool);
1409 return false0;
1410}
1411
1412struct resource_pool *dce112_create_resource_pool(
1413 uint8_t num_virtual_links,
1414 struct dc *dc)
1415{
1416 struct dce110_resource_pool *pool =
1417 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL(0x0001 | 0x0004));
1418
1419 if (!pool)
1420 return NULL((void *)0);
1421
1422 if (dce112_resource_construct(num_virtual_links, dc, pool))
1423 return &pool->base;
1424
1425 kfree(pool);
1426 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1426); do
{} while (0); } while (0);
1427 return NULL((void *)0);
1428}