File: | dev/mii/brgphy.c |
Warning: | line 241, column 8 Access to field 'bnx_chipid' results in a dereference of a null pointer (loaded from variable 'bnx_sc') |
Press '?' to see keyboard shortcuts
Keyboard shortcuts:
1 | /* $OpenBSD: brgphy.c,v 1.107 2021/06/17 09:30:32 kettenis Exp $ */ | |||
2 | ||||
3 | /* | |||
4 | * Copyright (c) 2000 | |||
5 | * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. | |||
6 | * | |||
7 | * Redistribution and use in source and binary forms, with or without | |||
8 | * modification, are permitted provided that the following conditions | |||
9 | * are met: | |||
10 | * 1. Redistributions of source code must retain the above copyright | |||
11 | * notice, this list of conditions and the following disclaimer. | |||
12 | * 2. Redistributions in binary form must reproduce the above copyright | |||
13 | * notice, this list of conditions and the following disclaimer in the | |||
14 | * documentation and/or other materials provided with the distribution. | |||
15 | * 3. All advertising materials mentioning features or use of this software | |||
16 | * must display the following acknowledgement: | |||
17 | * This product includes software developed by Bill Paul. | |||
18 | * 4. Neither the name of the author nor the names of any co-contributors | |||
19 | * may be used to endorse or promote products derived from this software | |||
20 | * without specific prior written permission. | |||
21 | * | |||
22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND | |||
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |||
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD | |||
26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |||
29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |||
30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |||
31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |||
32 | * THE POSSIBILITY OF SUCH DAMAGE. | |||
33 | * | |||
34 | * $FreeBSD: brgphy.c,v 1.8 2002/03/22 06:38:52 wpaul Exp $ | |||
35 | */ | |||
36 | ||||
37 | #include <sys/param.h> | |||
38 | #include <sys/systm.h> | |||
39 | #include <sys/kernel.h> | |||
40 | #include <sys/device.h> | |||
41 | #include <sys/socket.h> | |||
42 | #include <sys/errno.h> | |||
43 | ||||
44 | #include <machine/bus.h> | |||
45 | ||||
46 | #include <net/if.h> | |||
47 | #include <net/if_media.h> | |||
48 | ||||
49 | #include <netinet/in.h> | |||
50 | #include <netinet/if_ether.h> | |||
51 | ||||
52 | #include <dev/pci/pcivar.h> | |||
53 | ||||
54 | #include <dev/mii/mii.h> | |||
55 | #include <dev/mii/miivar.h> | |||
56 | #include <dev/mii/miidevs.h> | |||
57 | ||||
58 | #include <dev/mii/brgphyreg.h> | |||
59 | ||||
60 | #include <dev/pci/if_bgereg.h> | |||
61 | #include <dev/pci/if_bnxreg.h> | |||
62 | ||||
63 | int brgphy_probe(struct device *, void *, void *); | |||
64 | void brgphy_attach(struct device *, struct device *, void *); | |||
65 | ||||
66 | struct cfattach brgphy_ca = { | |||
67 | sizeof(struct mii_softc), brgphy_probe, brgphy_attach, mii_phy_detach | |||
68 | }; | |||
69 | ||||
70 | struct cfdriver brgphy_cd = { | |||
71 | NULL((void *)0), "brgphy", DV_DULL | |||
72 | }; | |||
73 | ||||
74 | int brgphy_service(struct mii_softc *, struct mii_data *, int); | |||
75 | void brgphy_copper_status(struct mii_softc *); | |||
76 | void brgphy_fiber_status(struct mii_softc *); | |||
77 | void brgphy_5708s_status(struct mii_softc *); | |||
78 | void brgphy_5709s_status(struct mii_softc *); | |||
79 | int brgphy_mii_phy_auto(struct mii_softc *); | |||
80 | void brgphy_loop(struct mii_softc *); | |||
81 | void brgphy_reset(struct mii_softc *); | |||
82 | void brgphy_reset_bge(struct mii_softc *); | |||
83 | void brgphy_reset_bnx(struct mii_softc *); | |||
84 | void brgphy_bcm5401_dspcode(struct mii_softc *); | |||
85 | void brgphy_bcm5411_dspcode(struct mii_softc *); | |||
86 | void brgphy_bcm5421_dspcode(struct mii_softc *); | |||
87 | void brgphy_bcm54k2_dspcode(struct mii_softc *); | |||
88 | void brgphy_adc_bug(struct mii_softc *); | |||
89 | void brgphy_5704_a0_bug(struct mii_softc *); | |||
90 | void brgphy_ber_bug(struct mii_softc *); | |||
91 | void brgphy_crc_bug(struct mii_softc *); | |||
92 | void brgphy_disable_early_dac(struct mii_softc *sc); | |||
93 | void brgphy_jumbo_settings(struct mii_softc *); | |||
94 | void brgphy_eth_wirespeed(struct mii_softc *); | |||
95 | void brgphy_bcm54xx_clock_delay(struct mii_softc *); | |||
96 | ||||
97 | const struct mii_phy_funcs brgphy_copper_funcs = { | |||
98 | brgphy_service, brgphy_copper_status, brgphy_reset, | |||
99 | }; | |||
100 | ||||
101 | const struct mii_phy_funcs brgphy_fiber_funcs = { | |||
102 | brgphy_service, brgphy_fiber_status, brgphy_reset, | |||
103 | }; | |||
104 | ||||
105 | const struct mii_phy_funcs brgphy_5708s_funcs = { | |||
106 | brgphy_service, brgphy_5708s_status, brgphy_reset, | |||
107 | }; | |||
108 | ||||
109 | const struct mii_phy_funcs brgphy_5709s_funcs = { | |||
110 | brgphy_service, brgphy_5709s_status, brgphy_reset, | |||
111 | }; | |||
112 | ||||
113 | static const struct mii_phydesc brgphys[] = { | |||
114 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54000x0004, | |||
115 | MII_STR_xxBROADCOM_BCM5400"BCM5400 1000baseT PHY" }, | |||
116 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54010x0005, | |||
117 | MII_STR_xxBROADCOM_BCM5401"BCM5401 10/100/1000baseT PHY" }, | |||
118 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54110x0007, | |||
119 | MII_STR_xxBROADCOM_BCM5411"BCM5411 10/100/1000baseT PHY" }, | |||
120 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54210x000e, | |||
121 | MII_STR_xxBROADCOM_BCM5421"BCM5421 10/100/1000baseT PHY" }, | |||
122 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54K20x002e, | |||
123 | MII_STR_xxBROADCOM_BCM54K2"BCM54K2 10/100/1000baseT PHY" }, | |||
124 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54610x000c, | |||
125 | MII_STR_xxBROADCOM_BCM5461"BCM5461 10/100/1000baseT PHY" }, | |||
126 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54620x000d, | |||
127 | MII_STR_xxBROADCOM_BCM5462"BCM5462 10/100/1000baseT PHY" }, | |||
128 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM54640x000b, | |||
129 | MII_STR_xxBROADCOM_BCM5464"BCM5464 10/100/1000baseT PHY" }, | |||
130 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57010x0011, | |||
131 | MII_STR_xxBROADCOM_BCM5701"BCM5701 10/100/1000baseT PHY" }, | |||
132 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57030x0016, | |||
133 | MII_STR_xxBROADCOM_BCM5703"BCM5703 10/100/1000baseT PHY" }, | |||
134 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57040x0019, | |||
135 | MII_STR_xxBROADCOM_BCM5704"BCM5704 10/100/1000baseT PHY" }, | |||
136 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57050x001a, | |||
137 | MII_STR_xxBROADCOM_BCM5705"BCM5705 10/100/1000baseT PHY" }, | |||
138 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57140x0034, | |||
139 | MII_STR_xxBROADCOM_BCM5714"BCM5714 10/100/1000baseT/SX PHY" }, | |||
140 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57500x0018, | |||
141 | MII_STR_xxBROADCOM_BCM5750"BCM5750 10/100/1000baseT PHY" }, | |||
142 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57520x0010, | |||
143 | MII_STR_xxBROADCOM_BCM5752"BCM5752 10/100/1000baseT PHY" }, | |||
144 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57800x0035, | |||
145 | MII_STR_xxBROADCOM_BCM5780"BCM5780 10/100/1000baseT/SX PHY" }, | |||
146 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM54XX0x0007, | |||
147 | MII_STR_xxBROADCOM2_BCM54XX"BCM54XX 10/100/1000baseT PHY" }, | |||
148 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM54810x000a, | |||
149 | MII_STR_xxBROADCOM2_BCM5481"BCM5481 10/100/1000baseT PHY" }, | |||
150 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM54820x000b, | |||
151 | MII_STR_xxBROADCOM2_BCM5482"BCM5482 10/100/1000baseT PHY" }, | |||
152 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM57220x002d, | |||
153 | MII_STR_xxBROADCOM2_BCM5722"BCM5722 10/100/1000baseT PHY" }, | |||
154 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM57550x000c, | |||
155 | MII_STR_xxBROADCOM2_BCM5755"BCM5755 10/100/1000baseT PHY" }, | |||
156 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM57610x003d, | |||
157 | MII_STR_xxBROADCOM2_BCM5761"BCM5761 10/100/1000baseT PHY" }, | |||
158 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM57840x003a, | |||
159 | MII_STR_xxBROADCOM2_BCM5784"BCM5784 10/100/1000baseT PHY" }, | |||
160 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM57870x000e, | |||
161 | MII_STR_xxBROADCOM2_BCM5787"BCM5787 10/100/1000baseT PHY" }, | |||
162 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM57060x0015, | |||
163 | MII_STR_xxBROADCOM_BCM5706"BCM5706 10/100/1000baseT/SX PHY" }, | |||
164 | { MII_OUI_xxBROADCOM0x000818, MII_MODEL_xxBROADCOM_BCM5708C0x0036, | |||
165 | MII_STR_xxBROADCOM_BCM5708C"BCM5708C 10/100/1000baseT PHY" }, | |||
166 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM5708S0x0015, | |||
167 | MII_STR_xxBROADCOM2_BCM5708S"BCM5708S 1000/2500baseSX PHY" }, | |||
168 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM5709C0x003c, | |||
169 | MII_STR_xxBROADCOM2_BCM5709C"BCM5709 10/100/1000baseT PHY" }, | |||
170 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM5709S0x003f, | |||
171 | MII_STR_xxBROADCOM2_BCM5709S"BCM5709S 1000/2500baseSX PHY" }, | |||
172 | { MII_OUI_xxBROADCOM20x0050ef, MII_MODEL_xxBROADCOM2_BCM5709CAX0x002c, | |||
173 | MII_STR_xxBROADCOM2_BCM5709CAX"BCM5709CAX 10/100/1000baseT PHY" }, | |||
174 | { MII_OUI_xxBROADCOM30x00d897, MII_MODEL_xxBROADCOM3_BCM5717C0x0020, | |||
175 | MII_STR_xxBROADCOM3_BCM5717C"BCM5717C 10/100/1000baseT PHY" }, | |||
176 | { MII_OUI_xxBROADCOM30x00d897, MII_MODEL_xxBROADCOM3_BCM5719C0x0022, | |||
177 | MII_STR_xxBROADCOM3_BCM5719C"BCM5719C 10/100/1000baseT PHY" }, | |||
178 | { MII_OUI_xxBROADCOM30x00d897, MII_MODEL_xxBROADCOM3_BCM5720C0x0036, | |||
179 | MII_STR_xxBROADCOM3_BCM5720C"BCM5720C 10/100/1000baseT PHY" }, | |||
180 | { MII_OUI_xxBROADCOM30x00d897, MII_MODEL_xxBROADCOM3_BCM577650x0024, | |||
181 | MII_STR_xxBROADCOM3_BCM57765"BCM57765 10/100/1000baseT PHY" }, | |||
182 | { MII_OUI_xxBROADCOM30x00d897, MII_MODEL_xxBROADCOM3_BCM577800x0019, | |||
183 | MII_STR_xxBROADCOM3_BCM57780"BCM57780 10/100/1000baseT PHY" }, | |||
184 | { MII_OUI_xxBROADCOM40x180361, MII_MODEL_xxBROADCOM4_BCM54210E0x000a, | |||
185 | MII_STR_xxBROADCOM4_BCM54210E"BCM54210E 10/100/1000baseT PHY" }, | |||
186 | { MII_OUI_xxBROADCOM40x180361, MII_MODEL_xxBROADCOM4_BCM57250x0038, | |||
187 | MII_STR_xxBROADCOM4_BCM5725"BCM5725 10/100/1000baseT PHY" }, | |||
188 | { MII_OUI_BROADCOM20x000af7, MII_MODEL_BROADCOM2_BCM59060x0004, | |||
189 | MII_STR_BROADCOM2_BCM5906"BCM5906 10/100baseTX PHY" }, | |||
190 | ||||
191 | { 0, 0, | |||
192 | NULL((void *)0) }, | |||
193 | }; | |||
194 | ||||
195 | int | |||
196 | brgphy_probe(struct device *parent, void *match, void *aux) | |||
197 | { | |||
198 | struct mii_attach_args *ma = aux; | |||
199 | ||||
200 | if (mii_phy_match(ma, brgphys) != NULL((void *)0)) | |||
201 | return (10); | |||
202 | ||||
203 | return (0); | |||
204 | } | |||
205 | ||||
206 | void | |||
207 | brgphy_attach(struct device *parent, struct device *self, void *aux) | |||
208 | { | |||
209 | struct mii_softc *sc = (struct mii_softc *)self; | |||
210 | struct bge_softc *bge_sc = NULL((void *)0); | |||
211 | struct bnx_softc *bnx_sc = NULL((void *)0); | |||
| ||||
212 | struct mii_attach_args *ma = aux; | |||
213 | struct mii_data *mii = ma->mii_data; | |||
214 | const struct mii_phydesc *mpd; | |||
215 | char *devname; | |||
216 | int fast_ether = 0; | |||
217 | ||||
218 | devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; | |||
219 | ||||
220 | if (strcmp(devname, "bge") == 0) { | |||
221 | bge_sc = mii->mii_ifp->if_softc; | |||
222 | ||||
223 | if (bge_sc->bge_phy_flags & BGE_PHY_10_100_ONLY0x00000002) | |||
224 | fast_ether = 1; | |||
225 | } else if (strcmp(devname, "bnx") == 0) | |||
226 | bnx_sc = mii->mii_ifp->if_softc; | |||
227 | ||||
228 | mpd = mii_phy_match(ma, brgphys); | |||
229 | printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)((ma->mii_id2) & 0x000f)); | |||
230 | ||||
231 | sc->mii_inst = mii->mii_instance; | |||
232 | sc->mii_phy = ma->mii_phyno; | |||
233 | sc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2)(((ma->mii_id1) << 6) | ((ma->mii_id2) >> 10 )); | |||
234 | sc->mii_model = MII_MODEL(ma->mii_id2)(((ma->mii_id2) & 0x03f0) >> 4); | |||
235 | sc->mii_rev = MII_REV(ma->mii_id2)((ma->mii_id2) & 0x000f); | |||
236 | sc->mii_pdata = mii; | |||
237 | sc->mii_flags = ma->mii_flags; | |||
238 | ||||
239 | if (sc->mii_flags & MIIF_HAVEFIBER0x0020) { | |||
240 | if (strcmp(devname, "bnx") == 0) { | |||
241 | if (BNX_CHIP_NUM(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xffff0000) == BNX_CHIP_NUM_57080x57080000) | |||
| ||||
242 | sc->mii_funcs = &brgphy_5708s_funcs; | |||
243 | else if (BNX_CHIP_NUM(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xffff0000) == BNX_CHIP_NUM_57090x57090000) | |||
244 | sc->mii_funcs = &brgphy_5709s_funcs; | |||
245 | else | |||
246 | sc->mii_funcs = &brgphy_fiber_funcs; | |||
247 | } else | |||
248 | sc->mii_funcs = &brgphy_fiber_funcs; | |||
249 | } else | |||
250 | sc->mii_funcs = &brgphy_copper_funcs; | |||
251 | ||||
252 | if (fast_ether == 1) | |||
253 | sc->mii_anegticks = MII_ANEGTICKS5; | |||
254 | else | |||
255 | sc->mii_anegticks = MII_ANEGTICKS_GIGE10; | |||
256 | ||||
257 | sc->mii_flags |= MIIF_NOISOLATE0x0002 | MIIF_NOLOOP0x0004; | |||
258 | ||||
259 | PHY_RESET(sc)(*(sc)->mii_funcs->pf_reset)((sc)); | |||
260 | ||||
261 | sc->mii_capabilities = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) & ma->mii_capmask; | |||
262 | if (sc->mii_capabilities & BMSR_EXTSTAT0x0100) | |||
263 | sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0f)); | |||
264 | ||||
265 | #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL((void *)0)) | |||
266 | ||||
267 | /* Create an instance of Ethernet media. */ | |||
268 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst)((0x0000000000000100ULL) | (2ULL) | (0) | ((uint64_t)(sc-> mii_inst) << 56)), BMCR_ISO0x0400); | |||
269 | ||||
270 | /* Add the supported media types */ | |||
271 | if (sc->mii_flags & MIIF_HAVEFIBER0x0020) { | |||
272 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst)((0x0000000000000100ULL) | (11) | (0x0000010000000000ULL) | ( (uint64_t)(sc->mii_inst) << 56)), | |||
273 | BMCR_S10000x0040 | BMCR_FDX0x0100); | |||
274 | ||||
275 | /* | |||
276 | * 2.5Gb support is a software enabled feature on the | |||
277 | * BCM5708S and BCM5709S controllers. | |||
278 | */ | |||
279 | if (strcmp(devname, "bnx") == 0) { | |||
280 | if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG0x008) | |||
281 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX,((0x0000000000000100ULL) | (21) | (0x0000010000000000ULL) | ( (uint64_t)(sc->mii_inst) << 56)) | |||
282 | IFM_FDX, sc->mii_inst)((0x0000000000000100ULL) | (21) | (0x0000010000000000ULL) | ( (uint64_t)(sc->mii_inst) << 56)), 0); | |||
283 | } | |||
284 | } else { | |||
285 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst)((0x0000000000000100ULL) | (3) | (0) | ((uint64_t)(sc->mii_inst ) << 56)), | |||
286 | BMCR_S100x0000); | |||
287 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst)((0x0000000000000100ULL) | (3) | (0x0000010000000000ULL) | (( uint64_t)(sc->mii_inst) << 56)), | |||
288 | BMCR_S100x0000 | BMCR_FDX0x0100); | |||
289 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst)((0x0000000000000100ULL) | (6) | (0) | ((uint64_t)(sc->mii_inst ) << 56)), | |||
290 | BMCR_S1000x2000); | |||
291 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst)((0x0000000000000100ULL) | (6) | (0x0000010000000000ULL) | (( uint64_t)(sc->mii_inst) << 56)), | |||
292 | BMCR_S1000x2000 | BMCR_FDX0x0100); | |||
293 | ||||
294 | if (fast_ether == 0) { | |||
295 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,((0x0000000000000100ULL) | (16) | (0) | ((uint64_t)(sc->mii_inst ) << 56)) | |||
296 | sc->mii_inst)((0x0000000000000100ULL) | (16) | (0) | ((uint64_t)(sc->mii_inst ) << 56)), BMCR_S10000x0040); | |||
297 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX,((0x0000000000000100ULL) | (16) | (0x0000010000000000ULL) | ( (uint64_t)(sc->mii_inst) << 56)) | |||
298 | sc->mii_inst)((0x0000000000000100ULL) | (16) | (0x0000010000000000ULL) | ( (uint64_t)(sc->mii_inst) << 56)), BMCR_S10000x0040 | BMCR_FDX0x0100); | |||
299 | } | |||
300 | } | |||
301 | ||||
302 | ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst)((0x0000000000000100ULL) | (0ULL) | (0) | ((uint64_t)(sc-> mii_inst) << 56)), 0); | |||
303 | ||||
304 | #undef ADD | |||
305 | } | |||
306 | ||||
307 | int | |||
308 | brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) | |||
309 | { | |||
310 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; | |||
311 | int reg, speed = 0, gig; | |||
312 | ||||
313 | if ((sc->mii_dev.dv_flags & DVF_ACTIVE0x0001) == 0) | |||
314 | return (ENXIO6); | |||
315 | ||||
316 | switch (cmd) { | |||
317 | case MII_POLLSTAT3: | |||
318 | /* | |||
319 | * If we're not polling our PHY instance, just return. | |||
320 | */ | |||
321 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) | |||
322 | return (0); | |||
323 | break; | |||
324 | ||||
325 | case MII_MEDIACHG2: | |||
326 | /* | |||
327 | * If the media indicates a different PHY instance, | |||
328 | * isolate ourselves. | |||
329 | */ | |||
330 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) { | |||
331 | reg = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); | |||
332 | PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (reg | 0x0400)); | |||
333 | return (0); | |||
334 | } | |||
335 | ||||
336 | /* | |||
337 | * If the interface is not up, don't do anything. | |||
338 | */ | |||
339 | if ((mii->mii_ifp->if_flags & IFF_UP0x1) == 0) | |||
340 | break; | |||
341 | ||||
342 | PHY_RESET(sc)(*(sc)->mii_funcs->pf_reset)((sc)); /* XXX hardware bug work-around */ | |||
343 | ||||
344 | switch (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL)) { | |||
345 | case IFM_AUTO0ULL: | |||
346 | (void) brgphy_mii_phy_auto(sc); | |||
347 | break; | |||
348 | case IFM_2500_SX21: | |||
349 | speed = BRGPHY_5708S_BMCR_25000x20; | |||
350 | goto setit; | |||
351 | case IFM_1000_T16: | |||
352 | speed = BMCR_S10000x0040; | |||
353 | goto setit; | |||
354 | case IFM_100_TX6: | |||
355 | speed = BMCR_S1000x2000; | |||
356 | goto setit; | |||
357 | case IFM_10_T3: | |||
358 | speed = BMCR_S100x0000; | |||
359 | setit: | |||
360 | brgphy_loop(sc); | |||
361 | if ((ife->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL) { | |||
362 | speed |= BMCR_FDX0x0100; | |||
363 | gig = GTCR_ADV_1000TFDX0x0200; | |||
364 | } else { | |||
365 | gig = GTCR_ADV_1000THDX0x0100; | |||
366 | } | |||
367 | ||||
368 | PHY_WRITE(sc, MII_100T2CR, 0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (0)); | |||
369 | PHY_WRITE(sc, MII_ANAR, ANAR_CSMA)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04), (0x0001)); | |||
370 | PHY_WRITE(sc, MII_BMCR, speed)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (speed)); | |||
371 | ||||
372 | if ((IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL) != IFM_1000_T16) && | |||
373 | (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL) != IFM_1000_SX11) && | |||
374 | (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL) != IFM_2500_SX21)) | |||
375 | break; | |||
376 | ||||
377 | PHY_WRITE(sc, MII_100T2CR, gig)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (gig)); | |||
378 | PHY_WRITE(sc, MII_BMCR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (speed|0x1000|0x0200)) | |||
379 | speed|BMCR_AUTOEN|BMCR_STARTNEG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (speed|0x1000|0x0200)); | |||
380 | ||||
381 | if (sc->mii_oui != MII_OUI_xxBROADCOM0x000818 || | |||
382 | sc->mii_model != MII_MODEL_xxBROADCOM_BCM57010x0011) | |||
383 | break; | |||
384 | ||||
385 | if (mii->mii_media.ifm_media & IFM_ETH_MASTER0x0000000000010000ULL) | |||
386 | gig |= GTCR_MAN_MS0x1000|GTCR_ADV_MS0x0800; | |||
387 | PHY_WRITE(sc, MII_100T2CR, gig)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (gig)); | |||
388 | break; | |||
389 | default: | |||
390 | return (EINVAL22); | |||
391 | } | |||
392 | break; | |||
393 | ||||
394 | case MII_TICK1: | |||
395 | /* | |||
396 | * If we're not currently selected, just return. | |||
397 | */ | |||
398 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) | |||
399 | return (0); | |||
400 | ||||
401 | /* | |||
402 | * Is the interface even up? | |||
403 | */ | |||
404 | if ((mii->mii_ifp->if_flags & IFF_UP0x1) == 0) | |||
405 | return (0); | |||
406 | ||||
407 | /* | |||
408 | * Only used for autonegotiation. | |||
409 | */ | |||
410 | if (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL) != IFM_AUTO0ULL) | |||
411 | break; | |||
412 | ||||
413 | /* | |||
414 | * Check to see if we have link. If we do, we don't | |||
415 | * need to restart the autonegotiation process. Read | |||
416 | * the BMSR twice in case it's latched. | |||
417 | */ | |||
418 | reg = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
419 | if (reg & BMSR_LINK0x0004) { | |||
420 | sc->mii_ticks = 0; /* Reset autoneg timer. */ | |||
421 | break; | |||
422 | } | |||
423 | ||||
424 | /* | |||
425 | * Only retry autonegotiation every mii_anegticks seconds. | |||
426 | */ | |||
427 | if (++sc->mii_ticks <= sc->mii_anegticks) | |||
428 | break; | |||
429 | ||||
430 | sc->mii_ticks = 0; | |||
431 | brgphy_mii_phy_auto(sc); | |||
432 | break; | |||
433 | } | |||
434 | ||||
435 | /* Update the media status. */ | |||
436 | mii_phy_status(sc); | |||
437 | ||||
438 | /* | |||
439 | * Callback if something changed. Note that we need to poke the DSP on | |||
440 | * the Broadcom PHYs if the media changes. | |||
441 | */ | |||
442 | if (sc->mii_media_active != mii->mii_media_active || | |||
443 | sc->mii_media_status != mii->mii_media_status || | |||
444 | cmd == MII_MEDIACHG2) { | |||
445 | switch (sc->mii_oui) { | |||
446 | case MII_OUI_BROADCOM0x001018: | |||
447 | switch (sc->mii_model) { | |||
448 | case MII_MODEL_BROADCOM_BCM54000x0004: | |||
449 | brgphy_bcm5401_dspcode(sc); | |||
450 | break; | |||
451 | } | |||
452 | break; | |||
453 | case MII_OUI_xxBROADCOM0x000818: | |||
454 | switch (sc->mii_model) { | |||
455 | case MII_MODEL_xxBROADCOM_BCM54010x0005: | |||
456 | if (sc->mii_rev == 1 || sc->mii_rev == 3) | |||
457 | brgphy_bcm5401_dspcode(sc); | |||
458 | break; | |||
459 | case MII_MODEL_xxBROADCOM_BCM54110x0007: | |||
460 | brgphy_bcm5411_dspcode(sc); | |||
461 | break; | |||
462 | } | |||
463 | break; | |||
464 | } | |||
465 | } | |||
466 | ||||
467 | /* Callback if something changed. */ | |||
468 | mii_phy_update(sc, cmd); | |||
469 | ||||
470 | return (0); | |||
471 | } | |||
472 | ||||
473 | void | |||
474 | brgphy_copper_status(struct mii_softc *sc) | |||
475 | { | |||
476 | struct mii_data *mii = sc->mii_pdata; | |||
477 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; | |||
478 | int bmcr, bmsr; | |||
479 | ||||
480 | mii->mii_media_status = IFM_AVALID0x0000000000000001ULL; | |||
481 | mii->mii_media_active = IFM_ETHER0x0000000000000100ULL; | |||
482 | ||||
483 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
484 | if (bmsr & BMSR_LINK0x0004) | |||
485 | mii->mii_media_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
486 | ||||
487 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); | |||
488 | if (bmcr & BMCR_LOOP0x4000) | |||
489 | mii->mii_media_active |= IFM_LOOP0x0000800000000000ULL; | |||
490 | ||||
491 | if (bmcr & BMCR_AUTOEN0x1000) { | |||
492 | int auxsts; | |||
493 | ||||
494 | if ((bmsr & BMSR_ACOMP0x0020) == 0) { | |||
495 | /* Erg, still trying, I guess... */ | |||
496 | mii->mii_media_active |= IFM_NONE2ULL; | |||
497 | return; | |||
498 | } | |||
499 | ||||
500 | auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x19)); | |||
501 | ||||
502 | switch (auxsts & BRGPHY_AUXSTS_AN_RES0x0700) { | |||
503 | case BRGPHY_RES_1000FD0x0700: | |||
504 | mii->mii_media_active |= IFM_1000_T16 | IFM_FDX0x0000010000000000ULL; | |||
505 | break; | |||
506 | case BRGPHY_RES_1000HD0x0600: | |||
507 | mii->mii_media_active |= IFM_1000_T16 | IFM_HDX0x0000020000000000ULL; | |||
508 | break; | |||
509 | case BRGPHY_RES_100FD0x0500: | |||
510 | mii->mii_media_active |= IFM_100_TX6 | IFM_FDX0x0000010000000000ULL; | |||
511 | break; | |||
512 | case BRGPHY_RES_100T40x0400: | |||
513 | mii->mii_media_active |= IFM_100_T48 | IFM_HDX0x0000020000000000ULL; | |||
514 | break; | |||
515 | case BRGPHY_RES_100HD0x0300: | |||
516 | mii->mii_media_active |= IFM_100_TX6 | IFM_HDX0x0000020000000000ULL; | |||
517 | break; | |||
518 | case BRGPHY_RES_10FD0x0200: | |||
519 | mii->mii_media_active |= IFM_10_T3 | IFM_FDX0x0000010000000000ULL; | |||
520 | break; | |||
521 | case BRGPHY_RES_10HD0x0100: | |||
522 | mii->mii_media_active |= IFM_10_T3 | IFM_HDX0x0000020000000000ULL; | |||
523 | break; | |||
524 | default: | |||
525 | if (sc->mii_oui == MII_OUI_BROADCOM20x000af7 && | |||
526 | sc->mii_model == MII_MODEL_BROADCOM2_BCM59060x0004) { | |||
527 | mii->mii_media_active |= (auxsts & | |||
528 | BRGPHY_RES_1000x0008) ? IFM_100_TX6 : IFM_10_T3; | |||
529 | mii->mii_media_active |= (auxsts & | |||
530 | BRGPHY_RES_FULL0x0001) ? IFM_FDX0x0000010000000000ULL : IFM_HDX0x0000020000000000ULL; | |||
531 | break; | |||
532 | } | |||
533 | mii->mii_media_active |= IFM_NONE2ULL; | |||
534 | return; | |||
535 | } | |||
536 | ||||
537 | if (mii->mii_media_active & IFM_FDX0x0000010000000000ULL) | |||
538 | mii->mii_media_active |= mii_phy_flowstatus(sc); | |||
539 | ||||
540 | if (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_1000_T16) { | |||
541 | if (PHY_READ(sc, MII_100T2SR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0a)) & GTSR_MS_RES0x4000) | |||
542 | mii->mii_media_active |= IFM_ETH_MASTER0x0000000000010000ULL; | |||
543 | } | |||
544 | } else | |||
545 | mii->mii_media_active = ife->ifm_media; | |||
546 | } | |||
547 | ||||
548 | void | |||
549 | brgphy_fiber_status(struct mii_softc *sc) | |||
550 | { | |||
551 | struct mii_data *mii = sc->mii_pdata; | |||
552 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; | |||
553 | int bmcr, bmsr; | |||
554 | ||||
555 | mii->mii_media_status = IFM_AVALID0x0000000000000001ULL; | |||
556 | mii->mii_media_active = IFM_ETHER0x0000000000000100ULL; | |||
557 | ||||
558 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
559 | if (bmsr & BMSR_LINK0x0004) | |||
560 | mii->mii_media_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
561 | ||||
562 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); | |||
563 | if (bmcr & BMCR_LOOP0x4000) | |||
564 | mii->mii_media_active |= IFM_LOOP0x0000800000000000ULL; | |||
565 | ||||
566 | if (bmcr & BMCR_AUTOEN0x1000) { | |||
567 | int val; | |||
568 | ||||
569 | if ((bmsr & BMSR_ACOMP0x0020) == 0) { | |||
570 | /* Erg, still trying, I guess... */ | |||
571 | mii->mii_media_active |= IFM_NONE2ULL; | |||
572 | return; | |||
573 | } | |||
574 | ||||
575 | mii->mii_media_active |= IFM_1000_SX11; | |||
576 | ||||
577 | val = PHY_READ(sc, MII_ANAR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04)) & PHY_READ(sc, MII_ANLPAR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x05)); | |||
578 | ||||
579 | if (val & ANAR_X_FD0x0020) | |||
580 | mii->mii_media_active |= IFM_FDX0x0000010000000000ULL; | |||
581 | else | |||
582 | mii->mii_media_active |= IFM_HDX0x0000020000000000ULL; | |||
583 | ||||
584 | if (mii->mii_media_active & IFM_FDX0x0000010000000000ULL) | |||
585 | mii->mii_media_active |= mii_phy_flowstatus(sc); | |||
586 | } else | |||
587 | mii->mii_media_active = ife->ifm_media; | |||
588 | } | |||
589 | ||||
590 | void | |||
591 | brgphy_5708s_status(struct mii_softc *sc) | |||
592 | { | |||
593 | struct mii_data *mii = sc->mii_pdata; | |||
594 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; | |||
595 | int bmcr, bmsr; | |||
596 | ||||
597 | mii->mii_media_status = IFM_AVALID0x0000000000000001ULL; | |||
598 | mii->mii_media_active = IFM_ETHER0x0000000000000100ULL; | |||
599 | ||||
600 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
601 | if (bmsr & BMSR_LINK0x0004) | |||
602 | mii->mii_media_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
603 | ||||
604 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); | |||
605 | if (bmcr & BMCR_LOOP0x4000) | |||
606 | mii->mii_media_active |= IFM_LOOP0x0000800000000000ULL; | |||
607 | ||||
608 | if (bmcr & BMCR_AUTOEN0x1000) { | |||
609 | int xstat; | |||
610 | ||||
611 | if ((bmsr & BMSR_ACOMP0x0020) == 0) { | |||
612 | /* Erg, still trying, I guess... */ | |||
613 | mii->mii_media_active |= IFM_NONE2ULL; | |||
614 | return; | |||
615 | } | |||
616 | ||||
617 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)) | |||
618 | BRGPHY_5708S_DIG_PG0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)); | |||
619 | ||||
620 | xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x14)); | |||
621 | ||||
622 | switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK0x0018) { | |||
623 | case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10(0x0 << 3): | |||
624 | mii->mii_media_active |= IFM_10_FL13; | |||
625 | break; | |||
626 | case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100(0x1 << 3): | |||
627 | mii->mii_media_active |= IFM_100_FX7; | |||
628 | break; | |||
629 | case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G(0x2 << 3): | |||
630 | mii->mii_media_active |= IFM_1000_SX11; | |||
631 | break; | |||
632 | case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G(0x3 << 3): | |||
633 | mii->mii_media_active |= IFM_2500_SX21; | |||
634 | break; | |||
635 | } | |||
636 | ||||
637 | if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX0x0004) | |||
638 | mii->mii_media_active |= IFM_FDX0x0000010000000000ULL; | |||
639 | else | |||
640 | mii->mii_media_active |= IFM_HDX0x0000020000000000ULL; | |||
641 | ||||
642 | if (mii->mii_media_active & IFM_FDX0x0000010000000000ULL) { | |||
643 | if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE0x0020) | |||
644 | mii->mii_media_active |= IFM_FLOW0x0000040000000000ULL | IFM_ETH_TXPAUSE0x0000000000040000ULL; | |||
645 | if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE0x0040) | |||
646 | mii->mii_media_active |= IFM_FLOW0x0000040000000000ULL | IFM_ETH_RXPAUSE0x0000000000020000ULL; | |||
647 | } | |||
648 | } else | |||
649 | mii->mii_media_active = ife->ifm_media; | |||
650 | } | |||
651 | ||||
652 | void | |||
653 | brgphy_5709s_status(struct mii_softc *sc) | |||
654 | { | |||
655 | struct mii_data *mii = sc->mii_pdata; | |||
656 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; | |||
657 | int bmcr, bmsr; | |||
658 | ||||
659 | mii->mii_media_status = IFM_AVALID0x0000000000000001ULL; | |||
660 | mii->mii_media_active = IFM_ETHER0x0000000000000100ULL; | |||
661 | ||||
662 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
663 | if (bmsr & BMSR_LINK0x0004) | |||
664 | mii->mii_media_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
665 | ||||
666 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); | |||
667 | if (bmcr & BMCR_LOOP0x4000) | |||
668 | mii->mii_media_active |= IFM_LOOP0x0000800000000000ULL; | |||
669 | ||||
670 | if (bmcr & BMCR_AUTOEN0x1000) { | |||
671 | int xstat; | |||
672 | ||||
673 | if ((bmsr & BMSR_ACOMP0x0020) == 0) { | |||
674 | /* Erg, still trying, I guess... */ | |||
675 | mii->mii_media_active |= IFM_NONE2ULL; | |||
676 | return; | |||
677 | } | |||
678 | ||||
679 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8120)) | |||
680 | BRGPHY_BLOCK_ADDR_GP_STATUS)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8120)); | |||
681 | ||||
682 | xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1B)); | |||
683 | ||||
684 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0xFFE0)) | |||
685 | BRGPHY_BLOCK_ADDR_COMBO_IEEE0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0xFFE0)); | |||
686 | ||||
687 | switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK0x3F00) { | |||
688 | case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100x0000: | |||
689 | mii->mii_media_active |= IFM_10_FL13; | |||
690 | break; | |||
691 | case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1000x0100: | |||
692 | mii->mii_media_active |= IFM_100_FX7; | |||
693 | break; | |||
694 | case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G0x0200: | |||
695 | mii->mii_media_active |= IFM_1000_SX11; | |||
696 | break; | |||
697 | case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G0x0300: | |||
698 | mii->mii_media_active |= IFM_2500_SX21; | |||
699 | break; | |||
700 | } | |||
701 | ||||
702 | if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX0x0008) | |||
703 | mii->mii_media_active |= IFM_FDX0x0000010000000000ULL; | |||
704 | else | |||
705 | mii->mii_media_active |= IFM_HDX0x0000020000000000ULL; | |||
706 | ||||
707 | if (mii->mii_media_active & IFM_FDX0x0000010000000000ULL) | |||
708 | mii->mii_media_active |= mii_phy_flowstatus(sc); | |||
709 | } else | |||
710 | mii->mii_media_active = ife->ifm_media; | |||
711 | } | |||
712 | ||||
713 | int | |||
714 | brgphy_mii_phy_auto(struct mii_softc *sc) | |||
715 | { | |||
716 | int anar, ktcr = 0; | |||
717 | ||||
718 | PHY_RESET(sc)(*(sc)->mii_funcs->pf_reset)((sc)); | |||
719 | ||||
720 | if (sc->mii_flags & MIIF_HAVEFIBER0x0020) { | |||
721 | anar = ANAR_X_FD0x0020 | ANAR_X_HD0x0040; | |||
722 | if (sc->mii_flags & MIIF_DOPAUSE0x0100) | |||
723 | anar |= ANAR_X_PAUSE_TOWARDS(3 << 7); | |||
724 | PHY_WRITE(sc, MII_ANAR, anar)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04), (anar)); | |||
725 | } else { | |||
726 | anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities)(((sc->mii_capabilities) & (0x8000|0x4000|0x2000| 0x1000 |0x0800|0x0400|0x0200)) >> 6) | ANAR_CSMA0x0001; | |||
727 | if (sc->mii_flags & MIIF_DOPAUSE0x0100) | |||
728 | anar |= ANAR_PAUSE_ASYM(2 << 10) | ANAR_FC0x0400; | |||
729 | PHY_WRITE(sc, MII_ANAR, anar)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04), (anar)); | |||
730 | } | |||
731 | ||||
732 | /* Enable speed in the 1000baseT control register */ | |||
733 | ktcr = GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
734 | if (sc->mii_oui == MII_OUI_xxBROADCOM0x000818 && | |||
735 | sc->mii_model == MII_MODEL_xxBROADCOM_BCM57010x0011) | |||
736 | ktcr |= GTCR_MAN_MS0x1000 | GTCR_ADV_MS0x0800; | |||
737 | PHY_WRITE(sc, MII_100T2CR, ktcr)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (ktcr)); | |||
738 | ktcr = PHY_READ(sc, MII_100T2CR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09)); | |||
739 | ||||
740 | /* Start autonegotiation */ | |||
741 | PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (0x1000 | 0x0200)); | |||
742 | PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1B), (0xFF00)); | |||
743 | ||||
744 | return (EJUSTRETURN-2); | |||
745 | } | |||
746 | ||||
747 | /* Enable loopback to force the link down. */ | |||
748 | void | |||
749 | brgphy_loop(struct mii_softc *sc) | |||
750 | { | |||
751 | u_int32_t bmsr; | |||
752 | int i; | |||
753 | ||||
754 | PHY_WRITE(sc, MII_BMCR, BMCR_LOOP)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (0x4000)); | |||
755 | for (i = 0; i < 15000; i++) { | |||
756 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); | |||
757 | if (!(bmsr & BMSR_LINK0x0004)) | |||
758 | break; | |||
759 | DELAY(10)(*delay_func)(10); | |||
760 | } | |||
761 | } | |||
762 | ||||
763 | void | |||
764 | brgphy_reset(struct mii_softc *sc) | |||
765 | { | |||
766 | char *devname; | |||
767 | ||||
768 | devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; | |||
769 | ||||
770 | mii_phy_reset(sc); | |||
771 | ||||
772 | switch (sc->mii_oui) { | |||
773 | case MII_OUI_BROADCOM0x001018: | |||
774 | switch (sc->mii_model) { | |||
775 | case MII_MODEL_BROADCOM_BCM54000x0004: | |||
776 | brgphy_bcm5401_dspcode(sc); | |||
777 | break; | |||
778 | case MII_MODEL_BROADCOM_BCM54010x0005: | |||
779 | if (sc->mii_rev == 1 || sc->mii_rev == 3) | |||
780 | brgphy_bcm5401_dspcode(sc); | |||
781 | break; | |||
782 | case MII_MODEL_BROADCOM_BCM54110x0007: | |||
783 | brgphy_bcm5411_dspcode(sc); | |||
784 | break; | |||
785 | } | |||
786 | break; | |||
787 | case MII_OUI_xxBROADCOM0x000818: | |||
788 | switch (sc->mii_model) { | |||
789 | case MII_MODEL_xxBROADCOM_BCM54210x000e: | |||
790 | brgphy_bcm5421_dspcode(sc); | |||
791 | break; | |||
792 | case MII_MODEL_xxBROADCOM_BCM54K20x002e: | |||
793 | brgphy_bcm54k2_dspcode(sc); | |||
794 | break; | |||
795 | } | |||
796 | break; | |||
797 | case MII_OUI_xxBROADCOM40x180361: | |||
798 | switch (sc->mii_model) { | |||
799 | case MII_MODEL_xxBROADCOM4_BCM54210E0x000a: | |||
800 | brgphy_bcm54xx_clock_delay(sc); | |||
801 | break; | |||
802 | } | |||
803 | } | |||
804 | ||||
805 | /* Handle any bge (NetXtreme/NetLink) workarounds. */ | |||
806 | if (strcmp(devname, "bge") == 0) | |||
807 | brgphy_reset_bge(sc); | |||
808 | /* Handle any bnx (NetXtreme II) workarounds. */ | |||
809 | else if (strcmp(devname, "bnx") == 0) | |||
810 | brgphy_reset_bnx(sc); | |||
811 | } | |||
812 | ||||
813 | void | |||
814 | brgphy_reset_bge(struct mii_softc *sc) | |||
815 | { | |||
816 | struct bge_softc *bge_sc = sc->mii_pdata->mii_ifp->if_softc; | |||
817 | ||||
818 | if (sc->mii_flags & MIIF_HAVEFIBER0x0020) | |||
819 | return; | |||
820 | ||||
821 | switch (sc->mii_oui) { | |||
822 | case MII_OUI_xxBROADCOM30x00d897: | |||
823 | switch (sc->mii_model) { | |||
824 | case MII_MODEL_xxBROADCOM3_BCM5717C0x0020: | |||
825 | case MII_MODEL_xxBROADCOM3_BCM5719C0x0022: | |||
826 | case MII_MODEL_xxBROADCOM3_BCM5720C0x0036: | |||
827 | case MII_MODEL_xxBROADCOM3_BCM577650x0024: | |||
828 | return; | |||
829 | } | |||
830 | } | |||
831 | ||||
832 | if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG0x00000008) | |||
833 | brgphy_adc_bug(sc); | |||
834 | if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG0x00008010) | |||
835 | brgphy_5704_a0_bug(sc); | |||
836 | if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG0x00000040) | |||
837 | brgphy_ber_bug(sc); | |||
838 | else if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG0x00000020) { | |||
839 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x0c00)); | |||
840 | PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (0x000a)); | |||
841 | ||||
842 | if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM0x00000080) { | |||
843 | PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), (0x110b)); | |||
844 | PHY_WRITE(sc, BRGPHY_TEST1, BRGPHY_TEST1_TRIM_EN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1E), (0x0010 | 0x4)) | |||
845 | 0x4)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1E), (0x0010 | 0x4)); | |||
846 | } else | |||
847 | PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), (0x010b)); | |||
848 | ||||
849 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x0400)); | |||
850 | } | |||
851 | ||||
852 | if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG0x00000004) | |||
853 | brgphy_crc_bug(sc); | |||
854 | ||||
855 | /* Set Jumbo frame settings in the PHY. */ | |||
856 | if (bge_sc->bge_flags & BGE_JUMBO_CAPABLE0x00000100) | |||
857 | brgphy_jumbo_settings(sc); | |||
858 | ||||
859 | /* Adjust output voltage */ | |||
860 | if (sc->mii_oui == MII_OUI_BROADCOM20x000af7 && | |||
861 | sc->mii_model == MII_MODEL_BROADCOM2_BCM59060x0004) | |||
862 | PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (0x12)); | |||
863 | ||||
864 | /* Enable Ethernet@Wirespeed */ | |||
865 | if (!(bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED0x00000100)) | |||
866 | brgphy_eth_wirespeed(sc); | |||
867 | ||||
868 | /* Enable Link LED on Dell boxes */ | |||
869 | if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED0x00000001) { | |||
870 | PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) & ~0x0002)) | |||
871 | PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) & ~0x0002)) | |||
872 | & ~BRGPHY_PHY_EXTCTL_3_LED)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) & ~0x0002)); | |||
873 | } | |||
874 | } | |||
875 | ||||
876 | void | |||
877 | brgphy_reset_bnx(struct mii_softc *sc) | |||
878 | { | |||
879 | struct bnx_softc *bnx_sc = sc->mii_pdata->mii_ifp->if_softc; | |||
880 | ||||
881 | if (BNX_CHIP_NUM(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xffff0000) == BNX_CHIP_NUM_57080x57080000 && | |||
882 | sc->mii_flags & MIIF_HAVEFIBER0x0020) { | |||
883 | /* Store autoneg capabilities/results in digital block (Page 0) */ | |||
884 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0002)); | |||
885 | PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), (0x0001)) | |||
886 | BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), (0x0001)); | |||
887 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)); | |||
888 | ||||
889 | /* Enable fiber mode and autodetection */ | |||
890 | PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0010 | 0x0001)) | |||
891 | PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0010 | 0x0001)) | |||
892 | BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0010 | 0x0001)) | |||
893 | BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0010 | 0x0001)); | |||
894 | ||||
895 | /* Enable parallel detection */ | |||
896 | PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x11), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x11)) | 0x0001 )) | |||
897 | PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x11), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x11)) | 0x0001 )) | |||
898 | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x11), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x11)) | 0x0001 )); | |||
899 | ||||
900 | /* Advertise 2.5G support through next page during autoneg */ | |||
901 | if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG0x008) { | |||
902 | PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0B), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0B)) | 0x0001 )) | |||
903 | PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0B), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0B)) | 0x0001 )) | |||
904 | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0B), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0B)) | 0x0001 )); | |||
905 | } | |||
906 | ||||
907 | /* Increase TX signal amplitude */ | |||
908 | if ((BNX_CHIP_ID(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xfffffff0) == BNX_CHIP_ID_5708_A00x57080000) || | |||
909 | (BNX_CHIP_ID(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xfffffff0) == BNX_CHIP_ID_5708_B00x57081000) || | |||
910 | (BNX_CHIP_ID(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xfffffff0) == BNX_CHIP_ID_5708_B10x57081010)) { | |||
911 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0005)) | |||
912 | BRGPHY_5708S_TX_MISC_PG5)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0005)); | |||
913 | PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x15)) & ~0x30)) | |||
914 | PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x15)) & ~0x30)) | |||
915 | ~BRGPHY_5708S_PG5_TXACTL1_VCM)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x15)) & ~0x30)); | |||
916 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)) | |||
917 | BRGPHY_5708S_DIG_PG0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)); | |||
918 | } | |||
919 | ||||
920 | /* Backplanes use special driver/pre-driver/pre-emphasis values. */ | |||
921 | if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE0x40) && | |||
922 | (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK0x0000ffff)) { | |||
923 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0005)) | |||
924 | BRGPHY_5708S_TX_MISC_PG5)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0005)); | |||
925 | PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (bnx_sc->bnx_port_hw_cfg & 0x0000ffff)) | |||
926 | bnx_sc->bnx_port_hw_cfg &(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (bnx_sc->bnx_port_hw_cfg & 0x0000ffff)) | |||
927 | BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (bnx_sc->bnx_port_hw_cfg & 0x0000ffff)); | |||
928 | PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)) | |||
929 | BRGPHY_5708S_DIG_PG0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1f), (0x0000)); | |||
930 | } | |||
931 | } else if (BNX_CHIP_NUM(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xffff0000) == BNX_CHIP_NUM_57090x57090000 && | |||
932 | sc->mii_flags & MIIF_HAVEFIBER0x0020) { | |||
933 | /* Select the SerDes Digital block of the AN MMD. */ | |||
934 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8300)); | |||
935 | ||||
936 | PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0010), (((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0010)) & ~0x0010) | 0x0001)) | |||
937 | (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) &(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0010), (((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0010)) & ~0x0010) | 0x0001)) | |||
938 | ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0010), (((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0010)) & ~0x0010) | 0x0001)) | |||
939 | BRGPHY_SD_DIG_1000X_CTL1_FIBER)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0010), (((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x0010)) & ~0x0010) | 0x0001)); | |||
940 | ||||
941 | if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG0x008) { | |||
942 | /* Select the Over 1G block of the AN MMD. */ | |||
943 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8320)) | |||
944 | BRGPHY_BLOCK_ADDR_OVER_1G)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8320)); | |||
945 | ||||
946 | /* | |||
947 | * Enable autoneg "Next Page" to advertise | |||
948 | * 2.5G support. | |||
949 | */ | |||
950 | PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x19), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x19)) | 0x0001 )) | |||
951 | PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x19), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x19)) | 0x0001 )) | |||
952 | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x19), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x19)) | 0x0001 )); | |||
953 | } | |||
954 | ||||
955 | /* | |||
956 | * Select the Multi-Rate Backplane Ethernet block of | |||
957 | * the AN MMD. | |||
958 | */ | |||
959 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8350)); | |||
960 | ||||
961 | /* Enable MRBE speed autoneg. */ | |||
962 | PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0001 | 0x0001)) | |||
963 | PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0001 | 0x0001)) | |||
964 | BRGPHY_MRBE_MSG_PG5_NP_MBRE |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0001 | 0x0001)) | |||
965 | BRGPHY_MRBE_MSG_PG5_NP_T2)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), ((*(sc)->mii_pdata->mii_readreg )((sc)->mii_dev.dv_parent, (sc)->mii_phy, (0x10)) | 0x0001 | 0x0001)); | |||
966 | ||||
967 | /* Select the Clause 73 User B0 block of the AN MMD. */ | |||
968 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8370)) | |||
969 | BRGPHY_BLOCK_ADDR_CL73_USER_B0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0x8370)); | |||
970 | ||||
971 | /* Enable MRBE speed autoneg. */ | |||
972 | PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x12), (0x2000 | 0x4000 | 0x8000)) | |||
973 | BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x12), (0x2000 | 0x4000 | 0x8000)) | |||
974 | BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x12), (0x2000 | 0x4000 | 0x8000)) | |||
975 | BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x12), (0x2000 | 0x4000 | 0x8000)); | |||
976 | ||||
977 | PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0xFFE0)) | |||
978 | BRGPHY_BLOCK_ADDR_COMBO_IEEE0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1F), (0xFFE0)); | |||
979 | } else if (BNX_CHIP_NUM(bnx_sc)(((bnx_sc)->bnx_chipid) & 0xffff0000) == BNX_CHIP_NUM_57090x57090000) { | |||
980 | if (BNX_CHIP_REV(bnx_sc)(((bnx_sc)->bnx_chipid) & 0x0000f000) == BNX_CHIP_REV_Ax0x00000000 || | |||
981 | BNX_CHIP_REV(bnx_sc)(((bnx_sc)->bnx_chipid) & 0x0000f000) == BNX_CHIP_REV_Bx0x00001000) | |||
982 | brgphy_disable_early_dac(sc); | |||
983 | ||||
984 | /* Set Jumbo frame settings in the PHY. */ | |||
985 | brgphy_jumbo_settings(sc); | |||
986 | ||||
987 | /* Enable Ethernet@Wirespeed */ | |||
988 | brgphy_eth_wirespeed(sc); | |||
989 | } else if ((sc->mii_flags & MIIF_HAVEFIBER0x0020) == 0) { | |||
990 | brgphy_ber_bug(sc); | |||
991 | ||||
992 | /* Set Jumbo frame settings in the PHY. */ | |||
993 | brgphy_jumbo_settings(sc); | |||
994 | ||||
995 | /* Enable Ethernet@Wirespeed */ | |||
996 | brgphy_eth_wirespeed(sc); | |||
997 | } | |||
998 | } | |||
999 | ||||
1000 | /* Disable tap power management */ | |||
1001 | void | |||
1002 | brgphy_bcm5401_dspcode(struct mii_softc *sc) | |||
1003 | { | |||
1004 | static const struct { | |||
1005 | int reg; | |||
1006 | uint16_t val; | |||
1007 | } dspcode[] = { | |||
1008 | { BRGPHY_MII_AUXCTL0x18, 0x0c20 }, | |||
1009 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x0012 }, | |||
1010 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x1804 }, | |||
1011 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x0013 }, | |||
1012 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x1204 }, | |||
1013 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x8006 }, | |||
1014 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x0132 }, | |||
1015 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x8006 }, | |||
1016 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x0232 }, | |||
1017 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x201f }, | |||
1018 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x0a20 }, | |||
1019 | { 0, 0 }, | |||
1020 | }; | |||
1021 | int i; | |||
1022 | ||||
1023 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1024 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1025 | DELAY(40)(*delay_func)(40); | |||
1026 | } | |||
1027 | ||||
1028 | /* Setting some undocumented voltage */ | |||
1029 | void | |||
1030 | brgphy_bcm5411_dspcode(struct mii_softc *sc) | |||
1031 | { | |||
1032 | static const struct { | |||
1033 | int reg; | |||
1034 | uint16_t val; | |||
1035 | } dspcode[] = { | |||
1036 | { 0x1c, 0x8c23 }, | |||
1037 | { 0x1c, 0x8ca3 }, | |||
1038 | { 0x1c, 0x8c23 }, | |||
1039 | { 0, 0 }, | |||
1040 | }; | |||
1041 | int i; | |||
1042 | ||||
1043 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1044 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1045 | } | |||
1046 | ||||
1047 | void | |||
1048 | brgphy_bcm5421_dspcode(struct mii_softc *sc) | |||
1049 | { | |||
1050 | uint16_t data; | |||
1051 | ||||
1052 | /* Set Class A mode */ | |||
1053 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x1007)); | |||
1054 | data = PHY_READ(sc, BRGPHY_MII_AUXCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18)); | |||
1055 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (data | 0x0400)); | |||
1056 | ||||
1057 | /* Set FFE gamma override to -0.125 */ | |||
1058 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x0007)); | |||
1059 | data = PHY_READ(sc, BRGPHY_MII_AUXCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18)); | |||
1060 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (data | 0x0800)); | |||
1061 | PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (0x000a)); | |||
1062 | data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15)); | |||
1063 | PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), (data | 0x0200)); | |||
1064 | } | |||
1065 | ||||
1066 | void | |||
1067 | brgphy_bcm54k2_dspcode(struct mii_softc *sc) | |||
1068 | { | |||
1069 | static const struct { | |||
1070 | int reg; | |||
1071 | uint16_t val; | |||
1072 | } dspcode[] = { | |||
1073 | { 4, 0x01e1 }, | |||
1074 | { 9, 0x0300 }, | |||
1075 | { 0, 0 }, | |||
1076 | }; | |||
1077 | int i; | |||
1078 | ||||
1079 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1080 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1081 | } | |||
1082 | ||||
1083 | void | |||
1084 | brgphy_adc_bug(struct mii_softc *sc) | |||
1085 | { | |||
1086 | static const struct { | |||
1087 | int reg; | |||
1088 | uint16_t val; | |||
1089 | } dspcode[] = { | |||
1090 | { BRGPHY_MII_AUXCTL0x18, 0x0c00 }, | |||
1091 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x201f }, | |||
1092 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x2aaa }, | |||
1093 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x000a }, | |||
1094 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x0323 }, | |||
1095 | { BRGPHY_MII_AUXCTL0x18, 0x0400 }, | |||
1096 | { 0, 0 }, | |||
1097 | }; | |||
1098 | int i; | |||
1099 | ||||
1100 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1101 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1102 | } | |||
1103 | ||||
1104 | void | |||
1105 | brgphy_5704_a0_bug(struct mii_softc *sc) | |||
1106 | { | |||
1107 | static const struct { | |||
1108 | int reg; | |||
1109 | uint16_t val; | |||
1110 | } dspcode[] = { | |||
1111 | { 0x1c, 0x8d68 }, | |||
1112 | { 0x1c, 0x8d68 }, | |||
1113 | { 0, 0 }, | |||
1114 | }; | |||
1115 | int i; | |||
1116 | ||||
1117 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1118 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1119 | } | |||
1120 | ||||
1121 | void | |||
1122 | brgphy_ber_bug(struct mii_softc *sc) | |||
1123 | { | |||
1124 | static const struct { | |||
1125 | int reg; | |||
1126 | uint16_t val; | |||
1127 | } dspcode[] = { | |||
1128 | { BRGPHY_MII_AUXCTL0x18, 0x0c00 }, | |||
1129 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x000a }, | |||
1130 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x310b }, | |||
1131 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x201f }, | |||
1132 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x9506 }, | |||
1133 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x401f }, | |||
1134 | { BRGPHY_MII_DSP_RW_PORT0x15, 0x14e2 }, | |||
1135 | { BRGPHY_MII_AUXCTL0x18, 0x0400 }, | |||
1136 | { 0, 0 }, | |||
1137 | }; | |||
1138 | int i; | |||
1139 | ||||
1140 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1141 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1142 | } | |||
1143 | ||||
1144 | /* BCM5701 A0/B0 CRC bug workaround */ | |||
1145 | void | |||
1146 | brgphy_crc_bug(struct mii_softc *sc) | |||
1147 | { | |||
1148 | static const struct { | |||
1149 | int reg; | |||
1150 | uint16_t val; | |||
1151 | } dspcode[] = { | |||
1152 | { BRGPHY_MII_DSP_ADDR_REG0x17, 0x0a75 }, | |||
1153 | { 0x1c, 0x8c68 }, | |||
1154 | { 0x1c, 0x8d68 }, | |||
1155 | { 0x1c, 0x8c68 }, | |||
1156 | { 0, 0 }, | |||
1157 | }; | |||
1158 | int i; | |||
1159 | ||||
1160 | for (i = 0; dspcode[i].reg != 0; i++) | |||
1161 | PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (dspcode[i].reg), (dspcode[i].val)); | |||
1162 | } | |||
1163 | ||||
1164 | void | |||
1165 | brgphy_disable_early_dac(struct mii_softc *sc) | |||
1166 | { | |||
1167 | uint32_t val; | |||
1168 | ||||
1169 | PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x17), (0x0f08)); | |||
1170 | val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15)); | |||
1171 | val &= ~(1 << 8); | |||
1172 | PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x15), (val)); | |||
1173 | ||||
1174 | } | |||
1175 | ||||
1176 | void | |||
1177 | brgphy_jumbo_settings(struct mii_softc *sc) | |||
1178 | { | |||
1179 | u_int32_t val; | |||
1180 | ||||
1181 | /* Set Jumbo frame settings in the PHY. */ | |||
1182 | if (sc->mii_oui == MII_OUI_BROADCOM0x001018 && | |||
1183 | sc->mii_model == MII_MODEL_BROADCOM_BCM54010x0005) { | |||
1184 | /* Cannot do read-modify-write on the BCM5401 */ | |||
1185 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x4c20)); | |||
1186 | } else { | |||
1187 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x7)); | |||
1188 | val = PHY_READ(sc, BRGPHY_MII_AUXCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18)); | |||
1189 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (val | 0x4000)) | |||
1190 | val | BRGPHY_AUXCTL_LONG_PKT)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (val | 0x4000)); | |||
1191 | } | |||
1192 | ||||
1193 | val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10)); | |||
1194 | PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), (val | 0x0001)) | |||
1195 | val | BRGPHY_PHY_EXTCTL_HIGH_LA)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), (val | 0x0001)); | |||
1196 | } | |||
1197 | ||||
1198 | void | |||
1199 | brgphy_eth_wirespeed(struct mii_softc *sc) | |||
1200 | { | |||
1201 | uint16_t val; | |||
1202 | ||||
1203 | /* Enable Ethernet@Wirespeed */ | |||
1204 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x07 | 0x07 << 12)) | |||
1205 | BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x07 | 0x07 << 12)); | |||
1206 | val = PHY_READ(sc, BRGPHY_MII_AUXCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18)) & BRGPHY_AUXCTL_MISC_DATA_MASK0x7ff8; | |||
1207 | val |= BRGPHY_AUXCTL_MISC_WIRESPEED_EN0x0010; | |||
1208 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x8000 | 0x07 | val)) | |||
1209 | BRGPHY_AUXCTL_SHADOW_MISC | val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x8000 | 0x07 | val)); | |||
1210 | } | |||
1211 | ||||
1212 | void | |||
1213 | brgphy_bcm54xx_clock_delay(struct mii_softc *sc) | |||
1214 | { | |||
1215 | uint16_t val; | |||
1216 | ||||
1217 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x07 | 0x07 << 12)) | |||
1218 | BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x07 | 0x07 << 12)); | |||
1219 | val = PHY_READ(sc, BRGPHY_MII_AUXCTL)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18)) & BRGPHY_AUXCTL_MISC_DATA_MASK0x7ff8; | |||
1220 | if (sc->mii_flags & MIIF_RXID0x0800) | |||
1221 | val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN0x0200; | |||
1222 | else | |||
1223 | val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN0x0200; | |||
1224 | PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x8000 | 0x07 | val)) | |||
1225 | BRGPHY_AUXCTL_SHADOW_MISC | val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x18), (0x8000 | 0x07 | val)); | |||
1226 | ||||
1227 | PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1C), ((0x03 << 10))); | |||
1228 | val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1C)) & BRGPHY_SHADOW_1C_DATA_MASK0x03FF; | |||
1229 | if (sc->mii_flags & MIIF_TXID0x1000) | |||
1230 | val |= BRGPHY_SHADOW_1C_GTXCLK_EN0x0200; | |||
1231 | else | |||
1232 | val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN0x0200; | |||
1233 | PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1C), (0x8000 | (0x03 << 10) | val )) | |||
1234 | BRGPHY_SHADOW_1C_CLK_CTRL | val)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x1C), (0x8000 | (0x03 << 10) | val )); | |||
1235 | } |