Bug Summary

File:dev/pci/drm/radeon/r600.c
Warning:line 2593, column 14
Access to field 'size' results in a dereference of a null pointer (loaded from field 'smc_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name r600.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/radeon/r600.c

/usr/src/sys/dev/pci/drm/radeon/r600.c

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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/firmware.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/slab.h>
33#include <linux/seq_file.h>
34
35#include <drm/drm_debugfs.h>
36#include <drm/drm_device.h>
37#include <drm/drm_vblank.h>
38#include <drm/radeon_drm.h>
39
40#include "atom.h"
41#include "avivod.h"
42#include "r600d.h"
43#include "radeon.h"
44#include "radeon_asic.h"
45#include "radeon_audio.h"
46#include "radeon_mode.h"
47#include "radeon_ucode.h"
48
49/* Firmware Names */
50MODULE_FIRMWARE("radeon/R600_pfp.bin");
51MODULE_FIRMWARE("radeon/R600_me.bin");
52MODULE_FIRMWARE("radeon/RV610_pfp.bin");
53MODULE_FIRMWARE("radeon/RV610_me.bin");
54MODULE_FIRMWARE("radeon/RV630_pfp.bin");
55MODULE_FIRMWARE("radeon/RV630_me.bin");
56MODULE_FIRMWARE("radeon/RV620_pfp.bin");
57MODULE_FIRMWARE("radeon/RV620_me.bin");
58MODULE_FIRMWARE("radeon/RV635_pfp.bin");
59MODULE_FIRMWARE("radeon/RV635_me.bin");
60MODULE_FIRMWARE("radeon/RV670_pfp.bin");
61MODULE_FIRMWARE("radeon/RV670_me.bin");
62MODULE_FIRMWARE("radeon/RS780_pfp.bin");
63MODULE_FIRMWARE("radeon/RS780_me.bin");
64MODULE_FIRMWARE("radeon/RV770_pfp.bin");
65MODULE_FIRMWARE("radeon/RV770_me.bin");
66MODULE_FIRMWARE("radeon/RV770_smc.bin");
67MODULE_FIRMWARE("radeon/RV730_pfp.bin");
68MODULE_FIRMWARE("radeon/RV730_me.bin");
69MODULE_FIRMWARE("radeon/RV730_smc.bin");
70MODULE_FIRMWARE("radeon/RV740_smc.bin");
71MODULE_FIRMWARE("radeon/RV710_pfp.bin");
72MODULE_FIRMWARE("radeon/RV710_me.bin");
73MODULE_FIRMWARE("radeon/RV710_smc.bin");
74MODULE_FIRMWARE("radeon/R600_rlc.bin");
75MODULE_FIRMWARE("radeon/R700_rlc.bin");
76MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
77MODULE_FIRMWARE("radeon/CEDAR_me.bin");
78MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
79MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
80MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
84MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
85MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
86MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
87MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
88MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
89MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
90MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
91MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
92MODULE_FIRMWARE("radeon/PALM_pfp.bin");
93MODULE_FIRMWARE("radeon/PALM_me.bin");
94MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
95MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
96MODULE_FIRMWARE("radeon/SUMO_me.bin");
97MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
98MODULE_FIRMWARE("radeon/SUMO2_me.bin");
99
100static const u32 crtc_offsets[2] =
101{
102 0,
103 AVIVO_D2CRTC_H_TOTAL0x6800 - AVIVO_D1CRTC_H_TOTAL0x6000
104};
105
106int r600_debugfs_mc_info_init(struct radeon_device *rdev);
107
108/* r600,rv610,rv630,rv620,rv635,rv670 */
109int r600_mc_wait_for_idle(struct radeon_device *rdev);
110static void r600_gpu_init(struct radeon_device *rdev);
111void r600_fini(struct radeon_device *rdev);
112void r600_irq_disable(struct radeon_device *rdev);
113static void r600_pcie_gen2_enable(struct radeon_device *rdev);
114extern int evergreen_rlc_resume(struct radeon_device *rdev);
115extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
116
117/*
118 * Indirect registers accessor
119 */
120u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
121{
122 unsigned long flags;
123 u32 r;
124
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->rcu_idx_lock); } while
(0);
126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff))r100_mm_wreg(rdev, (0x0100), (((reg) & 0x1fff)), 0);
127 r = RREG32(R600_RCU_DATA)r100_mm_rreg(rdev, (0x0104), 0);
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->rcu_idx_lock); } while
(0);
129 return r;
130}
131
132void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->rcu_idx_lock); } while
(0);
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff))r100_mm_wreg(rdev, (0x0100), (((reg) & 0x1fff)), 0);
138 WREG32(R600_RCU_DATA, (v))r100_mm_wreg(rdev, (0x0104), ((v)), 0);
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->rcu_idx_lock); } while
(0);
140}
141
142u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
143{
144 unsigned long flags;
145 u32 r;
146
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->uvd_idx_lock); } while
(0);
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff))r100_mm_wreg(rdev, (0xf4a0), (((reg) & 0x1ff)), 0);
149 r = RREG32(R600_UVD_CTX_DATA)r100_mm_rreg(rdev, (0xf4a4), 0);
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->uvd_idx_lock); } while
(0);
151 return r;
152}
153
154void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
155{
156 unsigned long flags;
157
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->uvd_idx_lock); } while
(0);
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff))r100_mm_wreg(rdev, (0xf4a0), (((reg) & 0x1ff)), 0);
160 WREG32(R600_UVD_CTX_DATA, (v))r100_mm_wreg(rdev, (0xf4a4), ((v)), 0);
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->uvd_idx_lock); } while
(0);
162}
163
164/**
165 * r600_get_allowed_info_register - fetch the register for the info ioctl
166 *
167 * @rdev: radeon_device pointer
168 * @reg: register offset in bytes
169 * @val: register value
170 *
171 * Returns 0 for success or -EINVAL for an invalid register
172 *
173 */
174int r600_get_allowed_info_register(struct radeon_device *rdev,
175 u32 reg, u32 *val)
176{
177 switch (reg) {
178 case GRBM_STATUS0x8010:
179 case GRBM_STATUS20x8014:
180 case R_000E50_SRBM_STATUS0x0E50:
181 case DMA_STATUS_REG0xd034:
182 case UVD_STATUS0xf6bc:
183 *val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0);
184 return 0;
185 default:
186 return -EINVAL22;
187 }
188}
189
190/**
191 * r600_get_xclk - get the xclk
192 *
193 * @rdev: radeon_device pointer
194 *
195 * Returns the reference clock used by the gfx engine
196 * (r6xx, IGPs, APUs).
197 */
198u32 r600_get_xclk(struct radeon_device *rdev)
199{
200 return rdev->clock.spll.reference_freq;
201}
202
203int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
204{
205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
206 int r;
207
208 /* bypass vclk and dclk with bclk */
209 WREG32_P(CG_UPLL_FUNC_CNTL_2,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((1) << 20) | (
(1) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0)
210 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((1) << 20) | (
(1) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0)
211 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK))do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((1) << 20) | (
(1) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0);
212
213 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
214 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~( 0x00000001 | 0x00000002 | 0x00000008)); tmp_ |= ((0x00000004
) & ~(~( 0x00000001 | 0x00000002 | 0x00000008))); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0)
215 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK))do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~( 0x00000001 | 0x00000002 | 0x00000008)); tmp_ |= ((0x00000004
) & ~(~( 0x00000001 | 0x00000002 | 0x00000008))); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
216
217 if (rdev->family >= CHIP_RS780)
218 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x30c0), 0); tmp_ &=
(~(1 << 1)); tmp_ |= (((1 << 1)) & ~(~(1 <<
1))); r100_mm_wreg(rdev, (0x30c0), (tmp_), 0); } while (0)
219 ~UPLL_BYPASS_CNTL)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x30c0), 0); tmp_ &=
(~(1 << 1)); tmp_ |= (((1 << 1)) & ~(~(1 <<
1))); r100_mm_wreg(rdev, (0x30c0), (tmp_), 0); } while (0);
220
221 if (!vclk || !dclk) {
222 /* keep the Bypass mode, put PLL to sleep */
223 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x00000002); tmp_ |= ((0x00000002) & ~(~0x00000002)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
224 return 0;
225 }
226
227 if (rdev->clock.spll.reference_freq == 10000)
228 ref_div = 34;
229 else
230 ref_div = 4;
231
232 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
233 ref_div + 1, 0xFFF, 2, 30, ~0,
234 &fb_div, &vclk_div, &dclk_div);
235 if (r)
236 return r;
237
238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
239 fb_div >>= 1;
240 else
241 fb_div |= 1;
242
243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL0x7e0);
244 if (r)
245 return r;
246
247 /* assert PLL_RESET */
248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x00000001); tmp_ |= ((0x00000001) & ~(~0x00000001)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
249
250 /* For RS780 we have to choose ref clk */
251 if (rdev->family >= CHIP_RS780)
252 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x20000000); tmp_ |= ((0x20000000) & ~(~0x20000000)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0)
253 ~UPLL_REFCLK_SRC_SEL_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x20000000); tmp_ |= ((0x20000000) & ~(~0x20000000)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
254
255 /* set the required fb, ref and post divder values */
256 WREG32_P(CG_UPLL_FUNC_CNTL,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~(0x0000FFF0 | 0x003F0000)); tmp_ |= ((((fb_div) << 4
) | ((ref_div) << 16)) & ~(~(0x0000FFF0 | 0x003F0000
))); r100_mm_wreg(rdev, (0x7e0), (tmp_), 0); } while (0)
257 UPLL_FB_DIV(fb_div) |do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~(0x0000FFF0 | 0x003F0000)); tmp_ |= ((((fb_div) << 4
) | ((ref_div) << 16)) & ~(~(0x0000FFF0 | 0x003F0000
))); r100_mm_wreg(rdev, (0x7e0), (tmp_), 0); } while (0)
258 UPLL_REF_DIV(ref_div),do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~(0x0000FFF0 | 0x003F0000)); tmp_ |= ((((fb_div) << 4
) | ((ref_div) << 16)) & ~(~(0x0000FFF0 | 0x003F0000
))); r100_mm_wreg(rdev, (0x7e0), (tmp_), 0); } while (0)
259 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK))do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~(0x0000FFF0 | 0x003F0000)); tmp_ |= ((((fb_div) << 4
) | ((ref_div) << 16)) & ~(~(0x0000FFF0 | 0x003F0000
))); r100_mm_wreg(rdev, (0x7e0), (tmp_), 0); } while (0);
260 WREG32_P(CG_UPLL_FUNC_CNTL_2,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
261 UPLL_SW_HILEN(vclk_div >> 1) |do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
263 UPLL_SW_HILEN2(dclk_div >> 1) |do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
264 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
265 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0)
266 ~UPLL_SW_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~0x0003FFFF); tmp_ |= ((((vclk_div >> 1) << 0) |
(((vclk_div >> 1) + (vclk_div & 1)) << 4) | (
(dclk_div >> 1) << 8) | (((dclk_div >> 1) +
(dclk_div & 1)) << 12) | 0x00010000 | 0x00020000) &
~(~0x0003FFFF)); r100_mm_wreg(rdev, (0x7e4), (tmp_), 0); } while
(0);
267
268 /* give the PLL some time to settle */
269 mdelay(15);
270
271 /* deassert PLL_RESET */
272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x00000001); tmp_ |= ((0) & ~(~0x00000001)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
273
274 mdelay(15);
275
276 /* deassert BYPASS EN */
277 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e0), 0); tmp_ &=
(~0x00000004); tmp_ |= ((0) & ~(~0x00000004)); r100_mm_wreg
(rdev, (0x7e0), (tmp_), 0); } while (0);
278
279 if (rdev->family >= CHIP_RS780)
280 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x30c0), 0); tmp_ &=
(~(1 << 1)); tmp_ |= ((0) & ~(~(1 << 1))); r100_mm_wreg
(rdev, (0x30c0), (tmp_), 0); } while (0);
281
282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL0x7e0);
283 if (r)
284 return r;
285
286 /* switch VCLK and DCLK selection */
287 WREG32_P(CG_UPLL_FUNC_CNTL_2,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((2) << 20) | (
(2) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0)
288 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((2) << 20) | (
(2) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0)
289 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK))do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x7e4), 0); tmp_ &=
(~(0x01F00000 | 0x3E000000)); tmp_ |= ((((2) << 20) | (
(2) << 25)) & ~(~(0x01F00000 | 0x3E000000))); r100_mm_wreg
(rdev, (0x7e4), (tmp_), 0); } while (0);
290
291 mdelay(100);
292
293 return 0;
294}
295
296void dce3_program_fmt(struct drm_encoder *encoder)
297{
298 struct drm_device *dev = encoder->dev;
299 struct radeon_device *rdev = dev->dev_private;
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
301 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
- __builtin_offsetof(struct radeon_crtc, base) );});
302 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
303 int bpc = 0;
304 u32 tmp = 0;
305 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
306
307 if (connector) {
308 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
309 bpc = radeon_get_monitor_bpc(connector);
310 dither = radeon_connector->dither;
311 }
312
313 /* LVDS FMT is set up by atom */
314 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))
315 return;
316
317 /* not needed for analog */
318 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15) ||
319 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16))
320 return;
321
322 if (bpc == 0)
323 return;
324
325 switch (bpc) {
326 case 6:
327 if (dither == RADEON_FMT_DITHER_ENABLE)
328 /* XXX sort out optimal dither settings */
329 tmp |= FMT_SPATIAL_DITHER_EN(1 << 8);
330 else
331 tmp |= FMT_TRUNCATE_EN(1 << 0);
332 break;
333 case 8:
334 if (dither == RADEON_FMT_DITHER_ENABLE)
335 /* XXX sort out optimal dither settings */
336 tmp |= (FMT_SPATIAL_DITHER_EN(1 << 8) | FMT_SPATIAL_DITHER_DEPTH(1 << 12));
337 else
338 tmp |= (FMT_TRUNCATE_EN(1 << 0) | FMT_TRUNCATE_DEPTH(1 << 4));
339 break;
340 case 10:
341 default:
342 /* not needed */
343 break;
344 }
345
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x6710 + radeon_crtc->crtc_offset), (tmp
), 0);
347}
348
349/* get temperature in millidegrees */
350int rv6xx_get_temp(struct radeon_device *rdev)
351{
352 u32 temp = (RREG32(CG_THERMAL_STATUS)r100_mm_rreg(rdev, (0x7F4), 0) & ASIC_T_MASK0x1FF) >>
353 ASIC_T_SHIFT0;
354 int actual_temp = temp & 0xff;
355
356 if (temp & 0x100)
357 actual_temp -= 256;
358
359 return actual_temp * 1000;
360}
361
362void r600_pm_get_dynpm_state(struct radeon_device *rdev)
363{
364 int i;
365
366 rdev->pm.dynpm_can_upclock = true1;
367 rdev->pm.dynpm_can_downclock = true1;
368
369 /* power state array is low to high, default is first */
370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
371 int min_power_state_index = 0;
372
373 if (rdev->pm.num_power_states > 2)
374 min_power_state_index = 1;
375
376 switch (rdev->pm.dynpm_planned_action) {
377 case DYNPM_ACTION_MINIMUM:
378 rdev->pm.requested_power_state_index = min_power_state_index;
379 rdev->pm.requested_clock_mode_index = 0;
380 rdev->pm.dynpm_can_downclock = false0;
381 break;
382 case DYNPM_ACTION_DOWNCLOCK:
383 if (rdev->pm.current_power_state_index == min_power_state_index) {
384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
385 rdev->pm.dynpm_can_downclock = false0;
386 } else {
387 if (rdev->pm.active_crtc_count > 1) {
388 for (i = 0; i < rdev->pm.num_power_states; i++) {
389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0))
390 continue;
391 else if (i >= rdev->pm.current_power_state_index) {
392 rdev->pm.requested_power_state_index =
393 rdev->pm.current_power_state_index;
394 break;
395 } else {
396 rdev->pm.requested_power_state_index = i;
397 break;
398 }
399 }
400 } else {
401 if (rdev->pm.current_power_state_index == 0)
402 rdev->pm.requested_power_state_index =
403 rdev->pm.num_power_states - 1;
404 else
405 rdev->pm.requested_power_state_index =
406 rdev->pm.current_power_state_index - 1;
407 }
408 }
409 rdev->pm.requested_clock_mode_index = 0;
410 /* don't use the power state if crtcs are active and no display flag is set */
411 if ((rdev->pm.active_crtc_count > 0) &&
412 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
413 clock_info[rdev->pm.requested_clock_mode_index].flags &
414 RADEON_PM_MODE_NO_DISPLAY(1 << 0))) {
415 rdev->pm.requested_power_state_index++;
416 }
417 break;
418 case DYNPM_ACTION_UPCLOCK:
419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
421 rdev->pm.dynpm_can_upclock = false0;
422 } else {
423 if (rdev->pm.active_crtc_count > 1) {
424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0))
426 continue;
427 else if (i <= rdev->pm.current_power_state_index) {
428 rdev->pm.requested_power_state_index =
429 rdev->pm.current_power_state_index;
430 break;
431 } else {
432 rdev->pm.requested_power_state_index = i;
433 break;
434 }
435 }
436 } else
437 rdev->pm.requested_power_state_index =
438 rdev->pm.current_power_state_index + 1;
439 }
440 rdev->pm.requested_clock_mode_index = 0;
441 break;
442 case DYNPM_ACTION_DEFAULT:
443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
444 rdev->pm.requested_clock_mode_index = 0;
445 rdev->pm.dynpm_can_upclock = false0;
446 break;
447 case DYNPM_ACTION_NONE:
448 default:
449 DRM_ERROR("Requested mode for not defined action\n")__drm_err("Requested mode for not defined action\n");
450 return;
451 }
452 } else {
453 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
454 /* for now just select the first power state and switch between clock modes */
455 /* power state array is low to high, default is first (0) */
456 if (rdev->pm.active_crtc_count > 1) {
457 rdev->pm.requested_power_state_index = -1;
458 /* start at 1 as we don't want the default mode */
459 for (i = 1; i < rdev->pm.num_power_states; i++) {
460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0))
461 continue;
462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
464 rdev->pm.requested_power_state_index = i;
465 break;
466 }
467 }
468 /* if nothing selected, grab the default state. */
469 if (rdev->pm.requested_power_state_index == -1)
470 rdev->pm.requested_power_state_index = 0;
471 } else
472 rdev->pm.requested_power_state_index = 1;
473
474 switch (rdev->pm.dynpm_planned_action) {
475 case DYNPM_ACTION_MINIMUM:
476 rdev->pm.requested_clock_mode_index = 0;
477 rdev->pm.dynpm_can_downclock = false0;
478 break;
479 case DYNPM_ACTION_DOWNCLOCK:
480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
481 if (rdev->pm.current_clock_mode_index == 0) {
482 rdev->pm.requested_clock_mode_index = 0;
483 rdev->pm.dynpm_can_downclock = false0;
484 } else
485 rdev->pm.requested_clock_mode_index =
486 rdev->pm.current_clock_mode_index - 1;
487 } else {
488 rdev->pm.requested_clock_mode_index = 0;
489 rdev->pm.dynpm_can_downclock = false0;
490 }
491 /* don't use the power state if crtcs are active and no display flag is set */
492 if ((rdev->pm.active_crtc_count > 0) &&
493 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
494 clock_info[rdev->pm.requested_clock_mode_index].flags &
495 RADEON_PM_MODE_NO_DISPLAY(1 << 0))) {
496 rdev->pm.requested_clock_mode_index++;
497 }
498 break;
499 case DYNPM_ACTION_UPCLOCK:
500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
501 if (rdev->pm.current_clock_mode_index ==
502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
504 rdev->pm.dynpm_can_upclock = false0;
505 } else
506 rdev->pm.requested_clock_mode_index =
507 rdev->pm.current_clock_mode_index + 1;
508 } else {
509 rdev->pm.requested_clock_mode_index =
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
511 rdev->pm.dynpm_can_upclock = false0;
512 }
513 break;
514 case DYNPM_ACTION_DEFAULT:
515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
516 rdev->pm.requested_clock_mode_index = 0;
517 rdev->pm.dynpm_can_upclock = false0;
518 break;
519 case DYNPM_ACTION_NONE:
520 default:
521 DRM_ERROR("Requested mode for not defined action\n")__drm_err("Requested mode for not defined action\n");
522 return;
523 }
524 }
525
526 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
527 rdev->pm.power_state[rdev->pm.requested_power_state_index].__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
528 clock_info[rdev->pm.requested_clock_mode_index].sclk,__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
529 rdev->pm.power_state[rdev->pm.requested_power_state_index].__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
530 clock_info[rdev->pm.requested_clock_mode_index].mclk,__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
531 rdev->pm.power_state[rdev->pm.requested_power_state_index].__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes)
532 pcie_lanes)__drm_dbg(DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n", rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
pcie_lanes);
533}
534
535void rs780_pm_init_profile(struct radeon_device *rdev)
536{
537 if (rdev->pm.num_power_states == 2) {
538 /* default */
539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0;
543 /* low sh */
544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 0;
546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
548 /* mid sh */
549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 0;
550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 0;
551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0;
553 /* high sh */
554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = 1;
556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0;
558 /* low mh */
559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 0;
560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = 0;
561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
563 /* mid mh */
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = 0;
566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0;
568 /* high mh */
569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 0;
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = 1;
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0;
573 } else if (rdev->pm.num_power_states == 3) {
574 /* default */
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0;
579 /* low sh */
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 1;
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 1;
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
584 /* mid sh */
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 1;
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 1;
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0;
589 /* high sh */
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 1;
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = 2;
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0;
594 /* low mh */
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 1;
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = 1;
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
599 /* mid mh */
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 1;
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = 1;
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0;
604 /* high mh */
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 1;
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = 2;
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0;
609 } else {
610 /* default */
611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0;
615 /* low sh */
616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 2;
617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 2;
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
620 /* mid sh */
621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 2;
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 2;
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0;
625 /* high sh */
626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 2;
627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = 3;
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0;
630 /* low mh */
631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 2;
632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = 0;
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
635 /* mid mh */
636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 2;
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = 0;
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0;
640 /* high mh */
641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 2;
642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = 3;
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0;
645 }
646}
647
648void r600_pm_init_profile(struct radeon_device *rdev)
649{
650 int idx;
651
652 if (rdev->family == CHIP_R600) {
653 /* XXX */
654 /* default */
655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0;
659 /* low sh */
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = rdev->pm.default_power_state_index;
661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = rdev->pm.default_power_state_index;
662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
664 /* mid sh */
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = rdev->pm.default_power_state_index;
666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = rdev->pm.default_power_state_index;
667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0;
669 /* high sh */
670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = rdev->pm.default_power_state_index;
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = rdev->pm.default_power_state_index;
672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0;
674 /* low mh */
675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = rdev->pm.default_power_state_index;
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
679 /* mid mh */
680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = rdev->pm.default_power_state_index;
681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = rdev->pm.default_power_state_index;
682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0;
684 /* high mh */
685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = rdev->pm.default_power_state_index;
686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = rdev->pm.default_power_state_index;
687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0;
689 } else {
690 if (rdev->pm.num_power_states < 4) {
691 /* default */
692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 2;
696 /* low sh */
697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 1;
698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 1;
699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
701 /* mid sh */
702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 1;
703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 1;
704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 1;
706 /* high sh */
707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 1;
708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = 1;
709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 2;
711 /* low mh */
712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 2;
713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = 2;
714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
716 /* low mh */
717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 2;
718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = 2;
719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 1;
721 /* high mh */
722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 2;
723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = 2;
724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 2;
726 } else {
727 /* default */
728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 2;
732 /* low sh */
733 if (rdev->flags & RADEON_IS_MOBILITY)
734 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
735 else
736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = idx;
738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = idx;
739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
741 /* mid sh */
742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = idx;
743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = idx;
744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 1;
746 /* high sh */
747 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = idx;
749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = idx;
750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 2;
752 /* low mh */
753 if (rdev->flags & RADEON_IS_MOBILITY)
754 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
755 else
756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = idx;
758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = idx;
759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
761 /* mid mh */
762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = idx;
763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = idx;
764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 1;
766 /* high mh */
767 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = idx;
769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = idx;
770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 2;
772 }
773 }
774}
775
776void r600_pm_misc(struct radeon_device *rdev)
777{
778 int req_ps_idx = rdev->pm.requested_power_state_index;
779 int req_cm_idx = rdev->pm.requested_clock_mode_index;
780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
781 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
782
783 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
784 /* 0xff01 is a flag rather then an actual voltage */
785 if (voltage->voltage == 0xff01)
786 return;
787 if (voltage->voltage != rdev->pm.current_vddc) {
788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC1);
789 rdev->pm.current_vddc = voltage->voltage;
790 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage)__drm_dbg(DRM_UT_DRIVER, "Setting: v: %d\n", voltage->voltage
);
791 }
792 }
793}
794
795bool_Bool r600_gui_idle(struct radeon_device *rdev)
796{
797 if (RREG32(GRBM_STATUS)r100_mm_rreg(rdev, (0x8010), 0) & GUI_ACTIVE(1<<31))
798 return false0;
799 else
800 return true1;
801}
802
803/* hpd for digital panel detect/disconnect */
804bool_Bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
805{
806 bool_Bool connected = false0;
807
808 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
809 switch (hpd) {
810 case RADEON_HPD_1:
811 if (RREG32(DC_HPD1_INT_STATUS)r100_mm_rreg(rdev, (0x7d00), 0) & DC_HPDx_SENSE(1 << 1))
812 connected = true1;
813 break;
814 case RADEON_HPD_2:
815 if (RREG32(DC_HPD2_INT_STATUS)r100_mm_rreg(rdev, (0x7d0c), 0) & DC_HPDx_SENSE(1 << 1))
816 connected = true1;
817 break;
818 case RADEON_HPD_3:
819 if (RREG32(DC_HPD3_INT_STATUS)r100_mm_rreg(rdev, (0x7d18), 0) & DC_HPDx_SENSE(1 << 1))
820 connected = true1;
821 break;
822 case RADEON_HPD_4:
823 if (RREG32(DC_HPD4_INT_STATUS)r100_mm_rreg(rdev, (0x7d24), 0) & DC_HPDx_SENSE(1 << 1))
824 connected = true1;
825 break;
826 /* DCE 3.2 */
827 case RADEON_HPD_5:
828 if (RREG32(DC_HPD5_INT_STATUS)r100_mm_rreg(rdev, (0x7dc0), 0) & DC_HPDx_SENSE(1 << 1))
829 connected = true1;
830 break;
831 case RADEON_HPD_6:
832 if (RREG32(DC_HPD6_INT_STATUS)r100_mm_rreg(rdev, (0x7df4), 0) & DC_HPDx_SENSE(1 << 1))
833 connected = true1;
834 break;
835 default:
836 break;
837 }
838 } else {
839 switch (hpd) {
840 case RADEON_HPD_1:
841 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS)r100_mm_rreg(rdev, (0x7d04), 0) & DC_HOT_PLUG_DETECTx_SENSE(1 << 1))
842 connected = true1;
843 break;
844 case RADEON_HPD_2:
845 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS)r100_mm_rreg(rdev, (0x7d14), 0) & DC_HOT_PLUG_DETECTx_SENSE(1 << 1))
846 connected = true1;
847 break;
848 case RADEON_HPD_3:
849 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS)r100_mm_rreg(rdev, (0x7d28), 0) & DC_HOT_PLUG_DETECTx_SENSE(1 << 1))
850 connected = true1;
851 break;
852 default:
853 break;
854 }
855 }
856 return connected;
857}
858
859void r600_hpd_set_polarity(struct radeon_device *rdev,
860 enum radeon_hpd_id hpd)
861{
862 u32 tmp;
863 bool_Bool connected = r600_hpd_sense(rdev, hpd);
864
865 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
866 switch (hpd) {
867 case RADEON_HPD_1:
868 tmp = RREG32(DC_HPD1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d04), 0);
869 if (connected)
870 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
871 else
872 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
873 WREG32(DC_HPD1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d04), (tmp), 0);
874 break;
875 case RADEON_HPD_2:
876 tmp = RREG32(DC_HPD2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d10), 0);
877 if (connected)
878 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
879 else
880 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
881 WREG32(DC_HPD2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d10), (tmp), 0);
882 break;
883 case RADEON_HPD_3:
884 tmp = RREG32(DC_HPD3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d1c), 0);
885 if (connected)
886 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
887 else
888 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
889 WREG32(DC_HPD3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d1c), (tmp), 0);
890 break;
891 case RADEON_HPD_4:
892 tmp = RREG32(DC_HPD4_INT_CONTROL)r100_mm_rreg(rdev, (0x7d28), 0);
893 if (connected)
894 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
895 else
896 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
897 WREG32(DC_HPD4_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d28), (tmp), 0);
898 break;
899 case RADEON_HPD_5:
900 tmp = RREG32(DC_HPD5_INT_CONTROL)r100_mm_rreg(rdev, (0x7dc4), 0);
901 if (connected)
902 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
903 else
904 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
905 WREG32(DC_HPD5_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7dc4), (tmp), 0);
906 break;
907 /* DCE 3.2 */
908 case RADEON_HPD_6:
909 tmp = RREG32(DC_HPD6_INT_CONTROL)r100_mm_rreg(rdev, (0x7df8), 0);
910 if (connected)
911 tmp &= ~DC_HPDx_INT_POLARITY(1 << 8);
912 else
913 tmp |= DC_HPDx_INT_POLARITY(1 << 8);
914 WREG32(DC_HPD6_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7df8), (tmp), 0);
915 break;
916 default:
917 break;
918 }
919 } else {
920 switch (hpd) {
921 case RADEON_HPD_1:
922 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d08), 0);
923 if (connected)
924 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
925 else
926 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
927 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d08), (tmp), 0);
928 break;
929 case RADEON_HPD_2:
930 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d18), 0);
931 if (connected)
932 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
933 else
934 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
935 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d18), (tmp), 0);
936 break;
937 case RADEON_HPD_3:
938 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d2c), 0);
939 if (connected)
940 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
941 else
942 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
943 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d2c), (tmp), 0);
944 break;
945 default:
946 break;
947 }
948 }
949}
950
951void r600_hpd_init(struct radeon_device *rdev)
952{
953 struct drm_device *dev = rdev->ddev;
954 struct drm_connector *connector;
955 unsigned enable = 0;
956
957 list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
(&dev->mode_config.connector_list); connector = ({ const
__typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*connector), head) );})) {
958 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
959
960 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14 ||
961 connector->connector_type == DRM_MODE_CONNECTOR_LVDS7) {
962 /* don't try to enable hpd on eDP or LVDS avoid breaking the
963 * aux dp channel on imac and help (but not completely fix)
964 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
965 */
966 continue;
967 }
968 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
969 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4)((0x9c4) << 0) | DC_HPDx_RX_INT_TIMER(0xfa)((0xfa) << 16);
970 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730)))
971 tmp |= DC_HPDx_EN(1 << 28);
972
973 switch (radeon_connector->hpd.hpd) {
974 case RADEON_HPD_1:
975 WREG32(DC_HPD1_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d08), (tmp), 0);
976 break;
977 case RADEON_HPD_2:
978 WREG32(DC_HPD2_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d14), (tmp), 0);
979 break;
980 case RADEON_HPD_3:
981 WREG32(DC_HPD3_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d20), (tmp), 0);
982 break;
983 case RADEON_HPD_4:
984 WREG32(DC_HPD4_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d2c), (tmp), 0);
985 break;
986 /* DCE 3.2 */
987 case RADEON_HPD_5:
988 WREG32(DC_HPD5_CONTROL, tmp)r100_mm_wreg(rdev, (0x7dc8), (tmp), 0);
989 break;
990 case RADEON_HPD_6:
991 WREG32(DC_HPD6_CONTROL, tmp)r100_mm_wreg(rdev, (0x7dfc), (tmp), 0);
992 break;
993 default:
994 break;
995 }
996 } else {
997 switch (radeon_connector->hpd.hpd) {
998 case RADEON_HPD_1:
999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN)r100_mm_wreg(rdev, (0x7d00), ((1 << 0)), 0);
1000 break;
1001 case RADEON_HPD_2:
1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN)r100_mm_wreg(rdev, (0x7d10), ((1 << 0)), 0);
1003 break;
1004 case RADEON_HPD_3:
1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN)r100_mm_wreg(rdev, (0x7d24), ((1 << 0)), 0);
1006 break;
1007 default:
1008 break;
1009 }
1010 }
1011 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1012 enable |= 1 << radeon_connector->hpd.hpd;
1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd)(rdev)->asic->hpd.set_polarity((rdev), (radeon_connector
->hpd.hpd));
1014 }
1015 radeon_irq_kms_enable_hpd(rdev, enable);
1016}
1017
1018void r600_hpd_fini(struct radeon_device *rdev)
1019{
1020 struct drm_device *dev = rdev->ddev;
1021 struct drm_connector *connector;
1022 unsigned disable = 0;
1023
1024 list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
(&dev->mode_config.connector_list); connector = ({ const
__typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*connector), head) );})) {
1025 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
1026 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
1027 switch (radeon_connector->hpd.hpd) {
1028 case RADEON_HPD_1:
1029 WREG32(DC_HPD1_CONTROL, 0)r100_mm_wreg(rdev, (0x7d08), (0), 0);
1030 break;
1031 case RADEON_HPD_2:
1032 WREG32(DC_HPD2_CONTROL, 0)r100_mm_wreg(rdev, (0x7d14), (0), 0);
1033 break;
1034 case RADEON_HPD_3:
1035 WREG32(DC_HPD3_CONTROL, 0)r100_mm_wreg(rdev, (0x7d20), (0), 0);
1036 break;
1037 case RADEON_HPD_4:
1038 WREG32(DC_HPD4_CONTROL, 0)r100_mm_wreg(rdev, (0x7d2c), (0), 0);
1039 break;
1040 /* DCE 3.2 */
1041 case RADEON_HPD_5:
1042 WREG32(DC_HPD5_CONTROL, 0)r100_mm_wreg(rdev, (0x7dc8), (0), 0);
1043 break;
1044 case RADEON_HPD_6:
1045 WREG32(DC_HPD6_CONTROL, 0)r100_mm_wreg(rdev, (0x7dfc), (0), 0);
1046 break;
1047 default:
1048 break;
1049 }
1050 } else {
1051 switch (radeon_connector->hpd.hpd) {
1052 case RADEON_HPD_1:
1053 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0)r100_mm_wreg(rdev, (0x7d00), (0), 0);
1054 break;
1055 case RADEON_HPD_2:
1056 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0)r100_mm_wreg(rdev, (0x7d10), (0), 0);
1057 break;
1058 case RADEON_HPD_3:
1059 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0)r100_mm_wreg(rdev, (0x7d24), (0), 0);
1060 break;
1061 default:
1062 break;
1063 }
1064 }
1065 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1066 disable |= 1 << radeon_connector->hpd.hpd;
1067 }
1068 radeon_irq_kms_disable_hpd(rdev, disable);
1069}
1070
1071/*
1072 * R600 PCIE GART
1073 */
1074void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1075{
1076 unsigned i;
1077 u32 tmp;
1078
1079 /* flush hdp cache so updates hit vram */
1080 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1081 !(rdev->flags & RADEON_IS_AGP)) {
1082 void __iomem *ptr = (void *)rdev->gart.ptr;
1083 u32 tmp;
1084
1085 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
1086 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1087 * This seems to cause problems on some AGP cards. Just use the old
1088 * method for them.
1089 */
1090 WREG32(HDP_DEBUG1, 0)r100_mm_wreg(rdev, (0x2F34), (0), 0);
1091 tmp = readl((void __iomem *)ptr)ioread32((void *)ptr);
1092 } else
1093 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1)r100_mm_wreg(rdev, (0x5480), (0x1), 0);
1094
1095 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12)r100_mm_wreg(rdev, (0x1490), (rdev->mc.gtt_start >> 12
), 0);
1096 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12)r100_mm_wreg(rdev, (0x14B0), ((rdev->mc.gtt_end - 1) >>
12), 0);
1097 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1))r100_mm_wreg(rdev, (0x1470), ((((1) & 0xf) << 0)), 0
);
1098 for (i = 0; i < rdev->usec_timeout; i++) {
1099 /* read MC_STATUS */
1100 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE)r100_mm_rreg(rdev, (0x1470), 0);
1101 tmp = (tmp & RESPONSE_TYPE_MASK0x000000F0) >> RESPONSE_TYPE_SHIFT4;
1102 if (tmp == 2) {
1103 pr_warn("[drm] r600 flush TLB failed\n")printk("\0014" "[drm] r600 flush TLB failed\n");
1104 return;
1105 }
1106 if (tmp) {
1107 return;
1108 }
1109 udelay(1);
1110 }
1111}
1112
1113int r600_pcie_gart_init(struct radeon_device *rdev)
1114{
1115 int r;
1116
1117 if (rdev->gart.robj) {
1118 WARN(1, "R600 PCIE GART already initialized\n")({ int __ret = !!(1); if (__ret) printf("R600 PCIE GART already initialized\n"
); __builtin_expect(!!(__ret), 0); });
1119 return 0;
1120 }
1121 /* Initialize common gart structure */
1122 r = radeon_gart_init(rdev);
1123 if (r)
1124 return r;
1125 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1126 return radeon_gart_table_vram_alloc(rdev);
1127}
1128
1129static int r600_pcie_gart_enable(struct radeon_device *rdev)
1130{
1131 u32 tmp;
1132 int r, i;
1133
1134 if (rdev->gart.robj == NULL((void *)0)) {
1135 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n")printf("drm:pid%d:%s *ERROR* " "No VRAM object for PCIE GART.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1136 return -EINVAL22;
1137 }
1138 r = radeon_gart_table_vram_pin(rdev);
1139 if (r)
1140 return r;
1141
1142 /* Setup L2 cache */
1143 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0)
1144 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0)
1145 EFFECTIVE_L2_QUEUE_SIZE(7))r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0);
1146 WREG32(VM_L2_CNTL2, 0)r100_mm_wreg(rdev, (0x1404), (0), 0);
1147 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1))r100_mm_wreg(rdev, (0x1408), ((((0) & 0x1f) << 0) |
(((1) & 0x1f) << 5)), 0);
1148 /* Setup TLB control */
1149 tmp = ENABLE_L1_TLB(1 << 0) | ENABLE_L1_FRAGMENT_PROCESSING(1 << 1) |
1150 SYSTEM_ACCESS_MODE_NOT_IN_SYS(3 << 6) |
1151 EFFECTIVE_L1_TLB_SIZE(5)(((5) & 7) << 12) | EFFECTIVE_L1_QUEUE_SIZE(5)(((5) & 7) << 15) |
1152 ENABLE_WAIT_L2_QUERY(1 << 11);
1153 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2200), (tmp), 0);
1154 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2214), (tmp), 0);
1155 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING)r100_mm_wreg(rdev, (0x2204), (tmp | (1 << 2)), 0);
1156 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp)r100_mm_wreg(rdev, (0x2218), (tmp), 0);
1157 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp)r100_mm_wreg(rdev, (0x219C), (tmp), 0);
1158 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp)r100_mm_wreg(rdev, (0x21A4), (tmp), 0);
1159 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A0), (tmp), 0);
1160 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A8), (tmp), 0);
1161 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x21FC), (tmp), 0);
1162 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x2210), (tmp), 0);
1163 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x2208), (tmp), 0);
1164 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x221C), (tmp), 0);
1165 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp)r100_mm_wreg(rdev, (0x2124), (tmp), 0);
1166 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp)r100_mm_wreg(rdev, (0x212c), (tmp), 0);
1167 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE)r100_mm_wreg(rdev, (0x220C), (tmp | (1 << 10)), 0);
1168 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE)r100_mm_wreg(rdev, (0x2220), (tmp | (1 << 10)), 0);
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12)r100_mm_wreg(rdev, (0x1594), (rdev->mc.gtt_start >> 12
), 0);
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12)r100_mm_wreg(rdev, (0x15B4), (rdev->mc.gtt_end >> 12
), 0);
1171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12)r100_mm_wreg(rdev, (0x1574), (rdev->gart.table_addr >>
12), 0);
1172 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |r100_mm_wreg(rdev, (0x1410), ((1 << 0) | (((0) & 3)
<< 1) | (1 << 4)), 0)
1173 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)r100_mm_wreg(rdev, (0x1410), ((1 << 0) | (((0) & 3)
<< 1) | (1 << 4)), 0);
1174 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,r100_mm_wreg(rdev, (0x1554), ((u32)(rdev->dummy_page.addr >>
12)), 0)
1175 (u32)(rdev->dummy_page.addr >> 12))r100_mm_wreg(rdev, (0x1554), ((u32)(rdev->dummy_page.addr >>
12)), 0);
1176 for (i = 1; i < 7; i++)
1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0)r100_mm_wreg(rdev, (0x1410 + (i * 4)), (0), 0);
1178
1179 r600_pcie_gart_tlb_flush(rdev);
1180 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr)
1181 (unsigned)(rdev->mc.gtt_size >> 20),printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr)
1182 (unsigned long long)rdev->gart.table_addr)printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr);
1183 rdev->gart.ready = true1;
1184 return 0;
1185}
1186
1187static void r600_pcie_gart_disable(struct radeon_device *rdev)
1188{
1189 u32 tmp;
1190 int i;
1191
1192 /* Disable all tables */
1193 for (i = 0; i < 7; i++)
1194 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0)r100_mm_wreg(rdev, (0x1410 + (i * 4)), (0), 0);
1195
1196 /* Disable L2 cache */
1197 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x1400), ((1 << 1) | (((7) & 7)
<< 13)), 0)
1198 EFFECTIVE_L2_QUEUE_SIZE(7))r100_mm_wreg(rdev, (0x1400), ((1 << 1) | (((7) & 7)
<< 13)), 0);
1199 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1))r100_mm_wreg(rdev, (0x1408), ((((0) & 0x1f) << 0) |
(((1) & 0x1f) << 5)), 0);
1200 /* Setup L1 TLB control */
1201 tmp = EFFECTIVE_L1_TLB_SIZE(5)(((5) & 7) << 12) | EFFECTIVE_L1_QUEUE_SIZE(5)(((5) & 7) << 15) |
1202 ENABLE_WAIT_L2_QUERY(1 << 11);
1203 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp)r100_mm_wreg(rdev, (0x219C), (tmp), 0);
1204 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp)r100_mm_wreg(rdev, (0x21A4), (tmp), 0);
1205 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A0), (tmp), 0);
1206 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A8), (tmp), 0);
1207 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x21FC), (tmp), 0);
1208 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x2210), (tmp), 0);
1209 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x2208), (tmp), 0);
1210 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x221C), (tmp), 0);
1211 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp)r100_mm_wreg(rdev, (0x220C), (tmp), 0);
1212 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp)r100_mm_wreg(rdev, (0x2220), (tmp), 0);
1213 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2200), (tmp), 0);
1214 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2214), (tmp), 0);
1215 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp)r100_mm_wreg(rdev, (0x2204), (tmp), 0);
1216 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp)r100_mm_wreg(rdev, (0x2218), (tmp), 0);
1217 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp)r100_mm_wreg(rdev, (0x2124), (tmp), 0);
1218 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp)r100_mm_wreg(rdev, (0x212c), (tmp), 0);
1219 radeon_gart_table_vram_unpin(rdev);
1220}
1221
1222static void r600_pcie_gart_fini(struct radeon_device *rdev)
1223{
1224 radeon_gart_fini(rdev);
1225 r600_pcie_gart_disable(rdev);
1226 radeon_gart_table_vram_free(rdev);
1227}
1228
1229static void r600_agp_enable(struct radeon_device *rdev)
1230{
1231 u32 tmp;
1232 int i;
1233
1234 /* Setup L2 cache */
1235 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0)
1236 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0)
1237 EFFECTIVE_L2_QUEUE_SIZE(7))r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
| (1 << 9) | (((7) & 7) << 13)), 0);
1238 WREG32(VM_L2_CNTL2, 0)r100_mm_wreg(rdev, (0x1404), (0), 0);
1239 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1))r100_mm_wreg(rdev, (0x1408), ((((0) & 0x1f) << 0) |
(((1) & 0x1f) << 5)), 0);
1240 /* Setup TLB control */
1241 tmp = ENABLE_L1_TLB(1 << 0) | ENABLE_L1_FRAGMENT_PROCESSING(1 << 1) |
1242 SYSTEM_ACCESS_MODE_NOT_IN_SYS(3 << 6) |
1243 EFFECTIVE_L1_TLB_SIZE(5)(((5) & 7) << 12) | EFFECTIVE_L1_QUEUE_SIZE(5)(((5) & 7) << 15) |
1244 ENABLE_WAIT_L2_QUERY(1 << 11);
1245 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2200), (tmp), 0);
1246 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp)r100_mm_wreg(rdev, (0x2214), (tmp), 0);
1247 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING)r100_mm_wreg(rdev, (0x2204), (tmp | (1 << 2)), 0);
1248 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp)r100_mm_wreg(rdev, (0x2218), (tmp), 0);
1249 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp)r100_mm_wreg(rdev, (0x219C), (tmp), 0);
1250 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp)r100_mm_wreg(rdev, (0x21A4), (tmp), 0);
1251 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A0), (tmp), 0);
1252 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp)r100_mm_wreg(rdev, (0x21A8), (tmp), 0);
1253 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x21FC), (tmp), 0);
1254 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp)r100_mm_wreg(rdev, (0x2210), (tmp), 0);
1255 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x2208), (tmp), 0);
1256 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp)r100_mm_wreg(rdev, (0x221C), (tmp), 0);
1257 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE)r100_mm_wreg(rdev, (0x220C), (tmp | (1 << 10)), 0);
1258 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE)r100_mm_wreg(rdev, (0x2220), (tmp | (1 << 10)), 0);
1259 for (i = 0; i < 7; i++)
1260 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0)r100_mm_wreg(rdev, (0x1410 + (i * 4)), (0), 0);
1261}
1262
1263int r600_mc_wait_for_idle(struct radeon_device *rdev)
1264{
1265 unsigned i;
1266 u32 tmp;
1267
1268 for (i = 0; i < rdev->usec_timeout; i++) {
1269 /* read MC_STATUS */
1270 tmp = RREG32(R_000E50_SRBM_STATUS)r100_mm_rreg(rdev, (0x0E50), 0) & 0x3F00;
1271 if (!tmp)
1272 return 0;
1273 udelay(1);
1274 }
1275 return -1;
1276}
1277
1278uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1279{
1280 unsigned long flags;
1281 uint32_t r;
1282
1283 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0);
1284 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg))r100_mm_wreg(rdev, (0x28F8), ((((reg) & 0x1FF) << 0
)), 0);
1285 r = RREG32(R_0028FC_MC_DATA)r100_mm_rreg(rdev, (0x28FC), 0);
1286 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR)r100_mm_wreg(rdev, (0x28F8), (~0xFFFFFE00), 0);
1287 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0);
1288 return r;
1289}
1290
1291void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1292{
1293 unsigned long flags;
1294
1295 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0);
1296 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |r100_mm_wreg(rdev, (0x28F8), ((((reg) & 0x1FF) << 0
) | (((1) & 0x1) << 9)), 0)
1297 S_0028F8_MC_IND_WR_EN(1))r100_mm_wreg(rdev, (0x28F8), ((((reg) & 0x1FF) << 0
) | (((1) & 0x1) << 9)), 0);
1298 WREG32(R_0028FC_MC_DATA, v)r100_mm_wreg(rdev, (0x28FC), (v), 0);
1299 WREG32(R_0028F8_MC_INDEX, 0x7F)r100_mm_wreg(rdev, (0x28F8), (0x7F), 0);
1300 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0);
1301}
1302
1303static void r600_mc_program(struct radeon_device *rdev)
1304{
1305 struct rv515_mc_save save;
1306 u32 tmp;
1307 int i, j;
1308
1309 /* Initialize HDP */
1310 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1311 WREG32((0x2c14 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c14 + j)), (0x00000000), 0);
1312 WREG32((0x2c18 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c18 + j)), (0x00000000), 0);
1313 WREG32((0x2c1c + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c1c + j)), (0x00000000), 0);
1314 WREG32((0x2c20 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c20 + j)), (0x00000000), 0);
1315 WREG32((0x2c24 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c24 + j)), (0x00000000), 0);
1316 }
1317 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0)r100_mm_wreg(rdev, (0x54A0), (0), 0);
1318
1319 rv515_mc_stop(rdev, &save);
1320 if (r600_mc_wait_for_idle(rdev)) {
1321 dev_warn(rdev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1322 }
1323 /* Lockout access through VGA aperture (doesn't exist before R600) */
1324 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE)r100_mm_wreg(rdev, (0x328), ((1 << 4)), 0);
1325 /* Update configuration */
1326 if (rdev->flags & RADEON_IS_AGP) {
1327 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1328 /* VRAM before AGP */
1329 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,r100_mm_wreg(rdev, (0x2190), (rdev->mc.vram_start >>
12), 0)
1330 rdev->mc.vram_start >> 12)r100_mm_wreg(rdev, (0x2190), (rdev->mc.vram_start >>
12), 0);
1331 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,r100_mm_wreg(rdev, (0x2194), (rdev->mc.gtt_end >> 12
), 0)
1332 rdev->mc.gtt_end >> 12)r100_mm_wreg(rdev, (0x2194), (rdev->mc.gtt_end >> 12
), 0);
1333 } else {
1334 /* VRAM after AGP */
1335 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,r100_mm_wreg(rdev, (0x2190), (rdev->mc.gtt_start >> 12
), 0)
1336 rdev->mc.gtt_start >> 12)r100_mm_wreg(rdev, (0x2190), (rdev->mc.gtt_start >> 12
), 0);
1337 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,r100_mm_wreg(rdev, (0x2194), (rdev->mc.vram_end >> 12
), 0)
1338 rdev->mc.vram_end >> 12)r100_mm_wreg(rdev, (0x2194), (rdev->mc.vram_end >> 12
), 0);
1339 }
1340 } else {
1341 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12)r100_mm_wreg(rdev, (0x2190), (rdev->mc.vram_start >>
12), 0);
1342 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12)r100_mm_wreg(rdev, (0x2194), (rdev->mc.vram_end >> 12
), 0);
1343 }
1344 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12)r100_mm_wreg(rdev, (0x2198), (rdev->vram_scratch.gpu_addr >>
12), 0);
1345 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1346 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1347 WREG32(MC_VM_FB_LOCATION, tmp)r100_mm_wreg(rdev, (0x2180), (tmp), 0);
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8))r100_mm_wreg(rdev, (0x2C04), ((rdev->mc.vram_start >>
8)), 0);
1349 WREG32(HDP_NONSURFACE_INFO, (2 << 7))r100_mm_wreg(rdev, (0x2C08), ((2 << 7)), 0);
1350 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF)r100_mm_wreg(rdev, (0x2C0C), (0x3FFFFFFF), 0);
1351 if (rdev->flags & RADEON_IS_AGP) {
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22)r100_mm_wreg(rdev, (0x2184), (rdev->mc.gtt_end >> 22
), 0);
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22)r100_mm_wreg(rdev, (0x2188), (rdev->mc.gtt_start >> 22
), 0);
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22)r100_mm_wreg(rdev, (0x218C), (rdev->mc.agp_base >> 22
), 0);
1355 } else {
1356 WREG32(MC_VM_AGP_BASE, 0)r100_mm_wreg(rdev, (0x218C), (0), 0);
1357 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF)r100_mm_wreg(rdev, (0x2184), (0x0FFFFFFF), 0);
1358 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF)r100_mm_wreg(rdev, (0x2188), (0x0FFFFFFF), 0);
1359 }
1360 if (r600_mc_wait_for_idle(rdev)) {
1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1362 }
1363 rv515_mc_resume(rdev, &save);
1364 /* we need to own VRAM, so turn off the VGA renderer here
1365 * to stop it overwriting our objects */
1366 rv515_vga_render_disable(rdev);
1367}
1368
1369/**
1370 * r600_vram_gtt_location - try to find VRAM & GTT location
1371 * @rdev: radeon device structure holding all necessary informations
1372 * @mc: memory controller structure holding memory informations
1373 *
1374 * Function will place try to place VRAM at same place as in CPU (PCI)
1375 * address space as some GPU seems to have issue when we reprogram at
1376 * different address space.
1377 *
1378 * If there is not enough space to fit the unvisible VRAM after the
1379 * aperture then we limit the VRAM size to the aperture.
1380 *
1381 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1382 * them to be in one from GPU point of view so that we can program GPU to
1383 * catch access outside them (weird GPU policy see ??).
1384 *
1385 * This function will never fails, worst case are limiting VRAM or GTT.
1386 *
1387 * Note: GTT start, end, size should be initialized before calling this
1388 * function on AGP platform.
1389 */
1390static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1391{
1392 u64 size_bf, size_af;
1393
1394 if (mc->mc_vram_size > 0xE0000000) {
1395 /* leave room for at least 512M GTT */
1396 dev_warn(rdev->dev, "limiting VRAM\n")printf("drm:pid%d:%s *WARNING* " "limiting VRAM\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__);
1397 mc->real_vram_size = 0xE0000000;
1398 mc->mc_vram_size = 0xE0000000;
1399 }
1400 if (rdev->flags & RADEON_IS_AGP) {
1401 size_bf = mc->gtt_start;
1402 size_af = mc->mc_mask - mc->gtt_end;
1403 if (size_bf > size_af) {
1404 if (mc->mc_vram_size > size_bf) {
1405 dev_warn(rdev->dev, "limiting VRAM\n")printf("drm:pid%d:%s *WARNING* " "limiting VRAM\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__);
1406 mc->real_vram_size = size_bf;
1407 mc->mc_vram_size = size_bf;
1408 }
1409 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1410 } else {
1411 if (mc->mc_vram_size > size_af) {
1412 dev_warn(rdev->dev, "limiting VRAM\n")printf("drm:pid%d:%s *WARNING* " "limiting VRAM\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__);
1413 mc->real_vram_size = size_af;
1414 mc->mc_vram_size = size_af;
1415 }
1416 mc->vram_start = mc->gtt_end + 1;
1417 }
1418 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1419 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",do { } while(0)
1420 mc->mc_vram_size >> 20, mc->vram_start,do { } while(0)
1421 mc->vram_end, mc->real_vram_size >> 20)do { } while(0);
1422 } else {
1423 u64 base = 0;
1424 if (rdev->flags & RADEON_IS_IGP) {
1425 base = RREG32(MC_VM_FB_LOCATION)r100_mm_rreg(rdev, (0x2180), 0) & 0xFFFF;
1426 base <<= 24;
1427 }
1428 radeon_vram_location(rdev, &rdev->mc, base);
1429 rdev->mc.gtt_base_align = 0;
1430 radeon_gtt_location(rdev, mc);
1431 }
1432}
1433
1434static int r600_mc_init(struct radeon_device *rdev)
1435{
1436 u32 tmp;
1437 int chansize, numchan;
1438 uint32_t h_addr, l_addr;
1439 unsigned long long k8_addr;
1440
1441 /* Get VRAM informations */
1442 rdev->mc.vram_is_ddr = true1;
1443 tmp = RREG32(RAMCFG)r100_mm_rreg(rdev, (0x2408), 0);
19
←
Calling 'r100_mm_rreg'
→
24
←
Returning from 'r100_mm_rreg'
→
1444 if (tmp & CHANSIZE_OVERRIDE(1 << 10)) {
25
←
Assuming the condition is false
→
26
←
Taking false branch
→
1445 chansize = 16;
1446 } else if (tmp & CHANSIZE_MASK0x00000080) {
27
←
Assuming the condition is false
→
28
←
Taking false branch
→
1447 chansize = 64;
1448 } else {
1449 chansize = 32;
1450 }
1451 tmp = RREG32(CHMAP)r100_mm_rreg(rdev, (0x2004), 0);
29
←
Calling 'r100_mm_rreg'
→
34
←
Returning from 'r100_mm_rreg'
→
1452 switch ((tmp & NOOFCHAN_MASK0x00003000) >> NOOFCHAN_SHIFT12) {
35
←
Control jumps to 'case 2:' at line 1460
→
1453 case 0:
1454 default:
1455 numchan = 1;
1456 break;
1457 case 1:
1458 numchan = 2;
1459 break;
1460 case 2:
1461 numchan = 4;
1462 break;
36
←
 Execution continues on line 1467
→
1463 case 3:
1464 numchan = 8;
1465 break;
1466 }
1467 rdev->mc.vram_width = numchan * chansize;
1468 /* Could aper size report 0 ? */
1469 rdev->mc.aper_base = rdev->fb_aper_offset;
1470 rdev->mc.aper_size = rdev->fb_aper_size;
1471 /* Setup GPU memory space */
1472 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x5428), 0);
37
←
Calling 'r100_mm_rreg'
→
41
←
Returning from 'r100_mm_rreg'
→
1473 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x5428), 0);
1474 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1475 r600_vram_gtt_location(rdev, &rdev->mc);
1476
1477 if (rdev->flags & RADEON_IS_IGP) {
42
←
Assuming the condition is false
→
43
←
Taking false branch
→
1478 rs690_pm_info(rdev);
1479 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1480
1481 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1482 /* Use K8 direct mapping for fast fb access. */
1483 rdev->fastfb_working = false0;
1484 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL))(((rdev->mc_rreg(rdev, (0x12))) >> 0) & 0xFF);
1485 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION)rdev->mc_rreg(rdev, (0x11));
1486 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1487#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1488 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1489#endif
1490 {
1491 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1492 * memory is present.
1493 */
1494 if (rdev->mc.igp_sideport_enabled == false0 && radeon_fastfb == 1) {
1495 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",printk("\0016" "[" "drm" "] " "Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n"
, (unsigned long long)rdev->mc.aper_base, k8_addr)
1496 (unsigned long long)rdev->mc.aper_base, k8_addr)printk("\0016" "[" "drm" "] " "Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n"
, (unsigned long long)rdev->mc.aper_base, k8_addr);
1497 rdev->mc.aper_base = (resource_size_t)k8_addr;
1498 rdev->fastfb_working = true1;
1499 }
1500 }
1501 }
1502 }
1503
1504 radeon_update_bandwidth_info(rdev);
1505 return 0;
1506}
1507
1508int r600_vram_scratch_init(struct radeon_device *rdev)
1509{
1510 int r;
1511
1512 if (rdev->vram_scratch.robj == NULL((void *)0)) {
1513 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE4096,
1514 PAGE_SIZE(1 << 12), true1, RADEON_GEM_DOMAIN_VRAM0x4,
1515 0, NULL((void *)0), NULL((void *)0), &rdev->vram_scratch.robj);
1516 if (r) {
1517 return r;
1518 }
1519 }
1520
1521 r = radeon_bo_reserve(rdev->vram_scratch.robj, false0);
1522 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
1523 return r;
1524 r = radeon_bo_pin(rdev->vram_scratch.robj,
1525 RADEON_GEM_DOMAIN_VRAM0x4, &rdev->vram_scratch.gpu_addr);
1526 if (r) {
1527 radeon_bo_unreserve(rdev->vram_scratch.robj);
1528 return r;
1529 }
1530 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1531 (void **)&rdev->vram_scratch.ptr);
1532 if (r)
1533 radeon_bo_unpin(rdev->vram_scratch.robj);
1534 radeon_bo_unreserve(rdev->vram_scratch.robj);
1535
1536 return r;
1537}
1538
1539void r600_vram_scratch_fini(struct radeon_device *rdev)
1540{
1541 int r;
1542
1543 if (rdev->vram_scratch.robj == NULL((void *)0)) {
1544 return;
1545 }
1546 r = radeon_bo_reserve(rdev->vram_scratch.robj, false0);
1547 if (likely(r == 0)__builtin_expect(!!(r == 0), 1)) {
1548 radeon_bo_kunmap(rdev->vram_scratch.robj);
1549 radeon_bo_unpin(rdev->vram_scratch.robj);
1550 radeon_bo_unreserve(rdev->vram_scratch.robj);
1551 }
1552 radeon_bo_unref(&rdev->vram_scratch.robj);
1553}
1554
1555void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool_Bool hung)
1556{
1557 u32 tmp = RREG32(R600_BIOS_3_SCRATCH)r100_mm_rreg(rdev, (0x1730), 0);
1558
1559 if (hung)
1560 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG0x20000000L;
1561 else
1562 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG0x20000000L;
1563
1564 WREG32(R600_BIOS_3_SCRATCH, tmp)r100_mm_wreg(rdev, (0x1730), (tmp), 0);
1565}
1566
1567static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1568{
1569 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",do { } while(0)
1570 RREG32(R_008010_GRBM_STATUS))do { } while(0);
1571 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",do { } while(0)
1572 RREG32(R_008014_GRBM_STATUS2))do { } while(0);
1573 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",do { } while(0)
1574 RREG32(R_000E50_SRBM_STATUS))do { } while(0);
1575 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",do { } while(0)
1576 RREG32(CP_STALLED_STAT1))do { } while(0);
1577 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",do { } while(0)
1578 RREG32(CP_STALLED_STAT2))do { } while(0);
1579 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",do { } while(0)
1580 RREG32(CP_BUSY_STAT))do { } while(0);
1581 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",do { } while(0)
1582 RREG32(CP_STAT))do { } while(0);
1583 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",do { } while(0)
1584 RREG32(DMA_STATUS_REG))do { } while(0);
1585}
1586
1587static bool_Bool r600_is_display_hung(struct radeon_device *rdev)
1588{
1589 u32 crtc_hung = 0;
1590 u32 crtc_status[2];
1591 u32 i, j, tmp;
1592
1593 for (i = 0; i < rdev->num_crtc; i++) {
1594 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[i]), 0) & AVIVO_CRTC_EN(1 << 0)) {
1595 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i])r100_mm_rreg(rdev, (0x60ac + crtc_offsets[i]), 0);
1596 crtc_hung |= (1 << i);
1597 }
1598 }
1599
1600 for (j = 0; j < 10; j++) {
1601 for (i = 0; i < rdev->num_crtc; i++) {
1602 if (crtc_hung & (1 << i)) {
1603 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i])r100_mm_rreg(rdev, (0x60ac + crtc_offsets[i]), 0);
1604 if (tmp != crtc_status[i])
1605 crtc_hung &= ~(1 << i);
1606 }
1607 }
1608 if (crtc_hung == 0)
1609 return false0;
1610 udelay(100);
1611 }
1612
1613 return true1;
1614}
1615
1616u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1617{
1618 u32 reset_mask = 0;
1619 u32 tmp;
1620
1621 /* GRBM_STATUS */
1622 tmp = RREG32(R_008010_GRBM_STATUS)r100_mm_rreg(rdev, (0x8010), 0);
1623 if (rdev->family >= CHIP_RV770) {
1624 if (G_008010_PA_BUSY(tmp)(((tmp) >> 25) & 1) | G_008010_SC_BUSY(tmp)(((tmp) >> 24) & 1) |
1625 G_008010_SH_BUSY(tmp)(((tmp) >> 21) & 1) | G_008010_SX_BUSY(tmp)(((tmp) >> 20) & 1) |
1626 G_008010_TA_BUSY(tmp)(((tmp) >> 14) & 1) | G_008010_VGT_BUSY(tmp)(((tmp) >> 17) & 1) |
1627 G_008010_DB03_BUSY(tmp)(((tmp) >> 26) & 1) | G_008010_CB03_BUSY(tmp)(((tmp) >> 30) & 1) |
1628 G_008010_SPI03_BUSY(tmp)(((tmp) >> 22) & 1) | G_008010_VGT_BUSY_NO_DMA(tmp)(((tmp) >> 16) & 1))
1629 reset_mask |= RADEON_RESET_GFX(1 << 0);
1630 } else {
1631 if (G_008010_PA_BUSY(tmp)(((tmp) >> 25) & 1) | G_008010_SC_BUSY(tmp)(((tmp) >> 24) & 1) |
1632 G_008010_SH_BUSY(tmp)(((tmp) >> 21) & 1) | G_008010_SX_BUSY(tmp)(((tmp) >> 20) & 1) |
1633 G_008010_TA03_BUSY(tmp)(((tmp) >> 18) & 1) | G_008010_VGT_BUSY(tmp)(((tmp) >> 17) & 1) |
1634 G_008010_DB03_BUSY(tmp)(((tmp) >> 26) & 1) | G_008010_CB03_BUSY(tmp)(((tmp) >> 30) & 1) |
1635 G_008010_SPI03_BUSY(tmp)(((tmp) >> 22) & 1) | G_008010_VGT_BUSY_NO_DMA(tmp)(((tmp) >> 16) & 1))
1636 reset_mask |= RADEON_RESET_GFX(1 << 0);
1637 }
1638
1639 if (G_008010_CF_RQ_PENDING(tmp)(((tmp) >> 7) & 1) | G_008010_PF_RQ_PENDING(tmp)(((tmp) >> 8) & 1) |
1640 G_008010_CP_BUSY(tmp)(((tmp) >> 29) & 1) | G_008010_CP_COHERENCY_BUSY(tmp)(((tmp) >> 28) & 1))
1641 reset_mask |= RADEON_RESET_CP(1 << 3);
1642
1643 if (G_008010_GRBM_EE_BUSY(tmp)(((tmp) >> 10) & 1))
1644 reset_mask |= RADEON_RESET_GRBM(1 << 4) | RADEON_RESET_GFX(1 << 0) | RADEON_RESET_CP(1 << 3);
1645
1646 /* DMA_STATUS_REG */
1647 tmp = RREG32(DMA_STATUS_REG)r100_mm_rreg(rdev, (0xd034), 0);
1648 if (!(tmp & DMA_IDLE(1 << 0)))
1649 reset_mask |= RADEON_RESET_DMA(1 << 2);
1650
1651 /* SRBM_STATUS */
1652 tmp = RREG32(R_000E50_SRBM_STATUS)r100_mm_rreg(rdev, (0x0E50), 0);
1653 if (G_000E50_RLC_RQ_PENDING(tmp)(((tmp) >> 3) & 1) | G_000E50_RLC_BUSY(tmp)(((tmp) >> 15) & 1))
1654 reset_mask |= RADEON_RESET_RLC(1 << 6);
1655
1656 if (G_000E50_IH_BUSY(tmp)(((tmp) >> 17) & 1))
1657 reset_mask |= RADEON_RESET_IH(1 << 8);
1658
1659 if (G_000E50_SEM_BUSY(tmp)(((tmp) >> 14) & 1))
1660 reset_mask |= RADEON_RESET_SEM(1 << 7);
1661
1662 if (G_000E50_GRBM_RQ_PENDING(tmp)(((tmp) >> 5) & 1))
1663 reset_mask |= RADEON_RESET_GRBM(1 << 4);
1664
1665 if (G_000E50_VMC_BUSY(tmp)(((tmp) >> 8) & 1))
1666 reset_mask |= RADEON_RESET_VMC(1 << 9);
1667
1668 if (G_000E50_MCB_BUSY(tmp)(((tmp) >> 9) & 1) | G_000E50_MCDZ_BUSY(tmp)(((tmp) >> 10) & 1) |
1669 G_000E50_MCDY_BUSY(tmp)(((tmp) >> 11) & 1) | G_000E50_MCDX_BUSY(tmp)(((tmp) >> 12) & 1) |
1670 G_000E50_MCDW_BUSY(tmp)(((tmp) >> 13) & 1))
1671 reset_mask |= RADEON_RESET_MC(1 << 10);
1672
1673 if (r600_is_display_hung(rdev))
1674 reset_mask |= RADEON_RESET_DISPLAY(1 << 11);
1675
1676 /* Skip MC reset as it's mostly likely not hung, just busy */
1677 if (reset_mask & RADEON_RESET_MC(1 << 10)) {
1678 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask)__drm_dbg(DRM_UT_CORE, "MC busy: 0x%08X, clearing.\n", reset_mask
);
1679 reset_mask &= ~RADEON_RESET_MC(1 << 10);
1680 }
1681
1682 return reset_mask;
1683}
1684
1685static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1686{
1687 struct rv515_mc_save save;
1688 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1689 u32 tmp;
1690
1691 if (reset_mask == 0)
1692 return;
1693
1694 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask)do { } while(0);
1695
1696 r600_print_gpu_status_regs(rdev);
1697
1698 /* Disable CP parsing/prefetching */
1699 if (rdev->family >= CHIP_RV770)
1700 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1))r100_mm_wreg(rdev, (0x86D8), ((((1) & 1)<<28) | (((
1) & 1)<<26)), 0);
1701 else
1702 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1))r100_mm_wreg(rdev, (0x86D8), ((((1) & 1)<<28)), 0);
1703
1704 /* disable the RLC */
1705 WREG32(RLC_CNTL, 0)r100_mm_wreg(rdev, (0x3f00), (0), 0);
1706
1707 if (reset_mask & RADEON_RESET_DMA(1 << 2)) {
1708 /* Disable DMA */
1709 tmp = RREG32(DMA_RB_CNTL)r100_mm_rreg(rdev, (0xd000), 0);
1710 tmp &= ~DMA_RB_ENABLE(1 << 0);
1711 WREG32(DMA_RB_CNTL, tmp)r100_mm_wreg(rdev, (0xd000), (tmp), 0);
1712 }
1713
1714 mdelay(50);
1715
1716 rv515_mc_stop(rdev, &save);
1717 if (r600_mc_wait_for_idle(rdev)) {
1718 dev_warn(rdev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1719 }
1720
1721 if (reset_mask & (RADEON_RESET_GFX(1 << 0) | RADEON_RESET_COMPUTE(1 << 1))) {
1722 if (rdev->family >= CHIP_RV770)
1723 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1)(((1) & 1) << 3) |
1724 S_008020_SOFT_RESET_CB(1)(((1) & 1) << 1) |
1725 S_008020_SOFT_RESET_PA(1)(((1) & 1) << 5) |
1726 S_008020_SOFT_RESET_SC(1)(((1) & 1) << 6) |
1727 S_008020_SOFT_RESET_SPI(1)(((1) & 1) << 8) |
1728 S_008020_SOFT_RESET_SX(1)(((1) & 1) << 10) |
1729 S_008020_SOFT_RESET_SH(1)(((1) & 1) << 9) |
1730 S_008020_SOFT_RESET_TC(1)(((1) & 1) << 11) |
1731 S_008020_SOFT_RESET_TA(1)(((1) & 1) << 12) |
1732 S_008020_SOFT_RESET_VC(1)(((1) & 1) << 13) |
1733 S_008020_SOFT_RESET_VGT(1)(((1) & 1) << 14);
1734 else
1735 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1)(((1) & 1) << 2) |
1736 S_008020_SOFT_RESET_DB(1)(((1) & 1) << 3) |
1737 S_008020_SOFT_RESET_CB(1)(((1) & 1) << 1) |
1738 S_008020_SOFT_RESET_PA(1)(((1) & 1) << 5) |
1739 S_008020_SOFT_RESET_SC(1)(((1) & 1) << 6) |
1740 S_008020_SOFT_RESET_SMX(1)(((1) & 1) << 7) |
1741 S_008020_SOFT_RESET_SPI(1)(((1) & 1) << 8) |
1742 S_008020_SOFT_RESET_SX(1)(((1) & 1) << 10) |
1743 S_008020_SOFT_RESET_SH(1)(((1) & 1) << 9) |
1744 S_008020_SOFT_RESET_TC(1)(((1) & 1) << 11) |
1745 S_008020_SOFT_RESET_TA(1)(((1) & 1) << 12) |
1746 S_008020_SOFT_RESET_VC(1)(((1) & 1) << 13) |
1747 S_008020_SOFT_RESET_VGT(1)(((1) & 1) << 14);
1748 }
1749
1750 if (reset_mask & RADEON_RESET_CP(1 << 3)) {
1751 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1)(((1) & 1) << 0) |
1752 S_008020_SOFT_RESET_VGT(1)(((1) & 1) << 14);
1753
1754 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1)(((1) & 1) << 8);
1755 }
1756
1757 if (reset_mask & RADEON_RESET_DMA(1 << 2)) {
1758 if (rdev->family >= CHIP_RV770)
1759 srbm_soft_reset |= RV770_SOFT_RESET_DMA(1 << 20);
1760 else
1761 srbm_soft_reset |= SOFT_RESET_DMA(1 << 12);
1762 }
1763
1764 if (reset_mask & RADEON_RESET_RLC(1 << 6))
1765 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1)(((1) & 1) << 13);
1766
1767 if (reset_mask & RADEON_RESET_SEM(1 << 7))
1768 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1)(((1) & 1) << 15);
1769
1770 if (reset_mask & RADEON_RESET_IH(1 << 8))
1771 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1)(((1) & 1) << 10);
1772
1773 if (reset_mask & RADEON_RESET_GRBM(1 << 4))
1774 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1)(((1) & 1) << 8);
1775
1776 if (!(rdev->flags & RADEON_IS_IGP)) {
1777 if (reset_mask & RADEON_RESET_MC(1 << 10))
1778 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1)(((1) & 1) << 11);
1779 }
1780
1781 if (reset_mask & RADEON_RESET_VMC(1 << 9))
1782 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1)(((1) & 1) << 17);
1783
1784 if (grbm_soft_reset) {
1785 tmp = RREG32(R_008020_GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
1786 tmp |= grbm_soft_reset;
1787 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
1788 WREG32(R_008020_GRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x8020), (tmp), 0);
1789 tmp = RREG32(R_008020_GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
1790
1791 udelay(50);
1792
1793 tmp &= ~grbm_soft_reset;
1794 WREG32(R_008020_GRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x8020), (tmp), 0);
1795 tmp = RREG32(R_008020_GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
1796 }
1797
1798 if (srbm_soft_reset) {
1799 tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0xe60), 0);
1800 tmp |= srbm_soft_reset;
1801 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
1802 WREG32(SRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0xe60), (tmp), 0);
1803 tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0xe60), 0);
1804
1805 udelay(50);
1806
1807 tmp &= ~srbm_soft_reset;
1808 WREG32(SRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0xe60), (tmp), 0);
1809 tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0xe60), 0);
1810 }
1811
1812 /* Wait a little for things to settle down */
1813 mdelay(1);
1814
1815 rv515_mc_resume(rdev, &save);
1816 udelay(50);
1817
1818 r600_print_gpu_status_regs(rdev);
1819}
1820
1821static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1822{
1823 struct rv515_mc_save save;
1824 u32 tmp, i;
1825
1826 dev_info(rdev->dev, "GPU pci config reset\n")do { } while(0);
1827
1828 /* disable dpm? */
1829
1830 /* Disable CP parsing/prefetching */
1831 if (rdev->family >= CHIP_RV770)
1832 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1))r100_mm_wreg(rdev, (0x86D8), ((((1) & 1)<<28) | (((
1) & 1)<<26)), 0);
1833 else
1834 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1))r100_mm_wreg(rdev, (0x86D8), ((((1) & 1)<<28)), 0);
1835
1836 /* disable the RLC */
1837 WREG32(RLC_CNTL, 0)r100_mm_wreg(rdev, (0x3f00), (0), 0);
1838
1839 /* Disable DMA */
1840 tmp = RREG32(DMA_RB_CNTL)r100_mm_rreg(rdev, (0xd000), 0);
1841 tmp &= ~DMA_RB_ENABLE(1 << 0);
1842 WREG32(DMA_RB_CNTL, tmp)r100_mm_wreg(rdev, (0xd000), (tmp), 0);
1843
1844 mdelay(50);
1845
1846 /* set mclk/sclk to bypass */
1847 if (rdev->family >= CHIP_RV770)
1848 rv770_set_clk_bypass_mode(rdev);
1849 /* disable BM */
1850 pci_clear_master(rdev->pdev);
1851 /* disable mem access */
1852 rv515_mc_stop(rdev, &save);
1853 if (r600_mc_wait_for_idle(rdev)) {
1854 dev_warn(rdev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1855 }
1856
1857 /* BIF reset workaround. Not sure if this is needed on 6xx */
1858 tmp = RREG32(BUS_CNTL)r100_mm_rreg(rdev, (0x5420), 0);
1859 tmp |= VGA_COHE_SPEC_TIMER_DIS(1 << 9);
1860 WREG32(BUS_CNTL, tmp)r100_mm_wreg(rdev, (0x5420), (tmp), 0);
1861
1862 tmp = RREG32(BIF_SCRATCH0)r100_mm_rreg(rdev, (0x5438), 0);
1863
1864 /* reset */
1865 radeon_pci_config_reset(rdev);
1866 mdelay(1);
1867
1868 /* BIF reset workaround. Not sure if this is needed on 6xx */
1869 tmp = SOFT_RESET_BIF(1 << 1);
1870 WREG32(SRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0xe60), (tmp), 0);
1871 mdelay(1);
1872 WREG32(SRBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0xe60), (0), 0);
1873
1874 /* wait for asic to come out of reset */
1875 for (i = 0; i < rdev->usec_timeout; i++) {
1876 if (RREG32(CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x5428), 0) != 0xffffffff)
1877 break;
1878 udelay(1);
1879 }
1880}
1881
1882int r600_asic_reset(struct radeon_device *rdev, bool_Bool hard)
1883{
1884 u32 reset_mask;
1885
1886 if (hard) {
1887 r600_gpu_pci_config_reset(rdev);
1888 return 0;
1889 }
1890
1891 reset_mask = r600_gpu_check_soft_reset(rdev);
1892
1893 if (reset_mask)
1894 r600_set_bios_scratch_engine_hung(rdev, true1);
1895
1896 /* try soft reset */
1897 r600_gpu_soft_reset(rdev, reset_mask);
1898
1899 reset_mask = r600_gpu_check_soft_reset(rdev);
1900
1901 /* try pci config reset */
1902 if (reset_mask && radeon_hard_reset)
1903 r600_gpu_pci_config_reset(rdev);
1904
1905 reset_mask = r600_gpu_check_soft_reset(rdev);
1906
1907 if (!reset_mask)
1908 r600_set_bios_scratch_engine_hung(rdev, false0);
1909
1910 return 0;
1911}
1912
1913/**
1914 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1915 *
1916 * @rdev: radeon_device pointer
1917 * @ring: radeon_ring structure holding ring information
1918 *
1919 * Check if the GFX engine is locked up.
1920 * Returns true if the engine appears to be locked up, false if not.
1921 */
1922bool_Bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1923{
1924 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1925
1926 if (!(reset_mask & (RADEON_RESET_GFX(1 << 0) |
1927 RADEON_RESET_COMPUTE(1 << 1) |
1928 RADEON_RESET_CP(1 << 3)))) {
1929 radeon_ring_lockup_update(rdev, ring);
1930 return false0;
1931 }
1932 return radeon_ring_test_lockup(rdev, ring);
1933}
1934
1935u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1936 u32 tiling_pipe_num,
1937 u32 max_rb_num,
1938 u32 total_max_rb_num,
1939 u32 disabled_rb_mask)
1940{
1941 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1942 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1943 u32 data = 0, mask = 1 << (max_rb_num - 1);
1944 unsigned i, j;
1945
1946 /* mask out the RBs that don't exist on that asic */
1947 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1948 /* make sure at least one RB is available */
1949 if ((tmp & 0xff) != 0xff)
1950 disabled_rb_mask = tmp;
1951
1952 rendering_pipe_num = 1 << tiling_pipe_num;
1953 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1954 BUG_ON(rendering_pipe_num < req_rb_num)((!(rendering_pipe_num < req_rb_num)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/radeon/r600.c", 1954
, "!(rendering_pipe_num < req_rb_num)"));
1955
1956 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1957 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1958
1959 if (rdev->family <= CHIP_RV740) {
1960 /* r6xx/r7xx */
1961 rb_num_width = 2;
1962 } else {
1963 /* eg+ */
1964 rb_num_width = 4;
1965 }
1966
1967 for (i = 0; i < max_rb_num; i++) {
1968 if (!(mask & disabled_rb_mask)) {
1969 for (j = 0; j < pipe_rb_ratio; j++) {
1970 data <<= rb_num_width;
1971 data |= max_rb_num - i - 1;
1972 }
1973 if (pipe_rb_remain) {
1974 data <<= rb_num_width;
1975 data |= max_rb_num - i - 1;
1976 pipe_rb_remain--;
1977 }
1978 }
1979 mask >>= 1;
1980 }
1981
1982 return data;
1983}
1984
1985int r600_count_pipe_bits(uint32_t val)
1986{
1987 return hweight32(val);
1988}
1989
1990static void r600_gpu_init(struct radeon_device *rdev)
1991{
1992 u32 tiling_config;
1993 u32 ramcfg;
1994 u32 cc_gc_shader_pipe_config;
1995 u32 tmp;
1996 int i, j;
1997 u32 sq_config;
1998 u32 sq_gpr_resource_mgmt_1 = 0;
1999 u32 sq_gpr_resource_mgmt_2 = 0;
2000 u32 sq_thread_resource_mgmt = 0;
2001 u32 sq_stack_resource_mgmt_1 = 0;
2002 u32 sq_stack_resource_mgmt_2 = 0;
2003 u32 disabled_rb_mask;
2004
2005 rdev->config.r600.tiling_group_size = 256;
2006 switch (rdev->family) {
2007 case CHIP_R600:
2008 rdev->config.r600.max_pipes = 4;
2009 rdev->config.r600.max_tile_pipes = 8;
2010 rdev->config.r600.max_simds = 4;
2011 rdev->config.r600.max_backends = 4;
2012 rdev->config.r600.max_gprs = 256;
2013 rdev->config.r600.max_threads = 192;
2014 rdev->config.r600.max_stack_entries = 256;
2015 rdev->config.r600.max_hw_contexts = 8;
2016 rdev->config.r600.max_gs_threads = 16;
2017 rdev->config.r600.sx_max_export_size = 128;
2018 rdev->config.r600.sx_max_export_pos_size = 16;
2019 rdev->config.r600.sx_max_export_smx_size = 128;
2020 rdev->config.r600.sq_num_cf_insts = 2;
2021 break;
2022 case CHIP_RV630:
2023 case CHIP_RV635:
2024 rdev->config.r600.max_pipes = 2;
2025 rdev->config.r600.max_tile_pipes = 2;
2026 rdev->config.r600.max_simds = 3;
2027 rdev->config.r600.max_backends = 1;
2028 rdev->config.r600.max_gprs = 128;
2029 rdev->config.r600.max_threads = 192;
2030 rdev->config.r600.max_stack_entries = 128;
2031 rdev->config.r600.max_hw_contexts = 8;
2032 rdev->config.r600.max_gs_threads = 4;
2033 rdev->config.r600.sx_max_export_size = 128;
2034 rdev->config.r600.sx_max_export_pos_size = 16;
2035 rdev->config.r600.sx_max_export_smx_size = 128;
2036 rdev->config.r600.sq_num_cf_insts = 2;
2037 break;
2038 case CHIP_RV610:
2039 case CHIP_RV620:
2040 case CHIP_RS780:
2041 case CHIP_RS880:
2042 rdev->config.r600.max_pipes = 1;
2043 rdev->config.r600.max_tile_pipes = 1;
2044 rdev->config.r600.max_simds = 2;
2045 rdev->config.r600.max_backends = 1;
2046 rdev->config.r600.max_gprs = 128;
2047 rdev->config.r600.max_threads = 192;
2048 rdev->config.r600.max_stack_entries = 128;
2049 rdev->config.r600.max_hw_contexts = 4;
2050 rdev->config.r600.max_gs_threads = 4;
2051 rdev->config.r600.sx_max_export_size = 128;
2052 rdev->config.r600.sx_max_export_pos_size = 16;
2053 rdev->config.r600.sx_max_export_smx_size = 128;
2054 rdev->config.r600.sq_num_cf_insts = 1;
2055 break;
2056 case CHIP_RV670:
2057 rdev->config.r600.max_pipes = 4;
2058 rdev->config.r600.max_tile_pipes = 4;
2059 rdev->config.r600.max_simds = 4;
2060 rdev->config.r600.max_backends = 4;
2061 rdev->config.r600.max_gprs = 192;
2062 rdev->config.r600.max_threads = 192;
2063 rdev->config.r600.max_stack_entries = 256;
2064 rdev->config.r600.max_hw_contexts = 8;
2065 rdev->config.r600.max_gs_threads = 16;
2066 rdev->config.r600.sx_max_export_size = 128;
2067 rdev->config.r600.sx_max_export_pos_size = 16;
2068 rdev->config.r600.sx_max_export_smx_size = 128;
2069 rdev->config.r600.sq_num_cf_insts = 2;
2070 break;
2071 default:
2072 break;
2073 }
2074
2075 /* Initialize HDP */
2076 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2077 WREG32((0x2c14 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c14 + j)), (0x00000000), 0);
2078 WREG32((0x2c18 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c18 + j)), (0x00000000), 0);
2079 WREG32((0x2c1c + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c1c + j)), (0x00000000), 0);
2080 WREG32((0x2c20 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c20 + j)), (0x00000000), 0);
2081 WREG32((0x2c24 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c24 + j)), (0x00000000), 0);
2082 }
2083
2084 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff))r100_mm_wreg(rdev, (0x8000), (((0xff) << 0)), 0);
2085
2086 /* Setup tiling */
2087 tiling_config = 0;
2088 ramcfg = RREG32(RAMCFG)r100_mm_rreg(rdev, (0x2408), 0);
2089 switch (rdev->config.r600.max_tile_pipes) {
2090 case 1:
2091 tiling_config |= PIPE_TILING(0)((0) << 1);
2092 break;
2093 case 2:
2094 tiling_config |= PIPE_TILING(1)((1) << 1);
2095 break;
2096 case 4:
2097 tiling_config |= PIPE_TILING(2)((2) << 1);
2098 break;
2099 case 8:
2100 tiling_config |= PIPE_TILING(3)((3) << 1);
2101 break;
2102 default:
2103 break;
2104 }
2105 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2106 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK0x00000001) >> NOOFBANK_SHIFT0);
2107 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)(((ramcfg & 0x00000001) >> 0) << 4);
2108 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)(((ramcfg & 0x00000100) >> 8) << 6);
2109
2110 tmp = (ramcfg & NOOFROWS_MASK0x0000001C) >> NOOFROWS_SHIFT2;
2111 if (tmp > 3) {
2112 tiling_config |= ROW_TILING(3)((3) << 8);
2113 tiling_config |= SAMPLE_SPLIT(3)((3) << 14);
2114 } else {
2115 tiling_config |= ROW_TILING(tmp)((tmp) << 8);
2116 tiling_config |= SAMPLE_SPLIT(tmp)((tmp) << 14);
2117 }
2118 tiling_config |= BANK_SWAPS(1)((1) << 11);
2119
2120 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG)r100_mm_rreg(rdev, (0x8950), 0) & 0x00ffff00;
2121 tmp = rdev->config.r600.max_simds -
2122 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK0xff);
2123 rdev->config.r600.active_simds = tmp;
2124
2125 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE)r100_mm_rreg(rdev, (0x98F4), 0) >> 16) & R6XX_MAX_BACKENDS_MASK0xff;
2126 tmp = 0;
2127 for (i = 0; i < rdev->config.r600.max_backends; i++)
2128 tmp |= (1 << i);
2129 /* if all the backends are disabled, fix it up here */
2130 if ((disabled_rb_mask & tmp) == tmp) {
2131 for (i = 0; i < rdev->config.r600.max_backends; i++)
2132 disabled_rb_mask &= ~(1 << i);
2133 }
2134 tmp = (tiling_config & PIPE_TILING__MASK0x0000000e) >> PIPE_TILING__SHIFT1;
2135 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2136 R6XX_MAX_BACKENDS8, disabled_rb_mask);
2137 tiling_config |= tmp << 16;
2138 rdev->config.r600.backend_map = tmp;
2139
2140 rdev->config.r600.tile_config = tiling_config;
2141 WREG32(GB_TILING_CONFIG, tiling_config)r100_mm_wreg(rdev, (0x98F0), (tiling_config), 0);
2142 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff)r100_mm_wreg(rdev, (0x6CA0), (tiling_config & 0xffff), 0);
2143 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff)r100_mm_wreg(rdev, (0x2F3C), (tiling_config & 0xffff), 0);
2144 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff)r100_mm_wreg(rdev, (0x3ec4), (tiling_config & 0xffff), 0);
2145
2146 tmp = R6XX_MAX_PIPES8 - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK0x0000FF00) >> 8);
2147 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK)r100_mm_wreg(rdev, (0x28C5C), ((tmp * 4) & 0x0000007F), 0
);
2148 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK)r100_mm_wreg(rdev, (0x28C58), (((tmp * 4) - 2) & 0x000000FF
), 0);
2149
2150 /* Setup some CP states */
2151 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)))r100_mm_wreg(rdev, (0x8760), ((((0x16) << 0) | ((0x2b) <<
8))), 0);
2152 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)))r100_mm_wreg(rdev, (0x8764), ((((0x40) << 16) | ((0x40)
<< 24))), 0);
2153
2154 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |r100_mm_wreg(rdev, (0x9508), (((1 << 1) | (1 << 24
) | (1 << 25) | (1 << 26))), 0)
2155 SYNC_WALKER | SYNC_ALIGNER))r100_mm_wreg(rdev, (0x9508), (((1 << 1) | (1 << 24
) | (1 << 25) | (1 << 26))), 0);
2156 /* Setup various GPU states */
2157 if (rdev->family == CHIP_RV670)
2158 WREG32(ARB_GDEC_RD_CNTL, 0x00000021)r100_mm_wreg(rdev, (0x246C), (0x00000021), 0);
2159
2160 tmp = RREG32(SX_DEBUG_1)r100_mm_rreg(rdev, (0x9054), 0);
2161 tmp |= SMX_EVENT_RELEASE(1 << 0);
2162 if ((rdev->family > CHIP_R600))
2163 tmp |= ENABLE_NEW_SMX_ADDRESS(1 << 16);
2164 WREG32(SX_DEBUG_1, tmp)r100_mm_wreg(rdev, (0x9054), (tmp), 0);
2165
2166 if (((rdev->family) == CHIP_R600) ||
2167 ((rdev->family) == CHIP_RV630) ||
2168 ((rdev->family) == CHIP_RV610) ||
2169 ((rdev->family) == CHIP_RV620) ||
2170 ((rdev->family) == CHIP_RS780) ||
2171 ((rdev->family) == CHIP_RS880)) {
2172 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE)r100_mm_wreg(rdev, (0x9830), ((1 << 31)), 0);
2173 } else {
2174 WREG32(DB_DEBUG, 0)r100_mm_wreg(rdev, (0x9830), (0), 0);
2175 }
2176 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |r100_mm_wreg(rdev, (0x9838), ((((4) << 0) | ((16) <<
20) | ((16) << 5) | ((4) << 15))), 0)
2177 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)))r100_mm_wreg(rdev, (0x9838), ((((4) << 0) | ((16) <<
20) | ((16) << 5) | ((4) << 15))), 0);
2178
2179 WREG32(PA_SC_MULTI_CHIP_CNTL, 0)r100_mm_wreg(rdev, (0x8B20), (0), 0);
2180 WREG32(VGT_NUM_INSTANCES, 0)r100_mm_wreg(rdev, (0x8974), (0), 0);
2181
2182 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0))r100_mm_wreg(rdev, (0x9100), (((0) << 0)), 0);
2183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0))r100_mm_wreg(rdev, (0x913C), (((0) << 0)), 0);
2184
2185 tmp = RREG32(SQ_MS_FIFO_SIZES)r100_mm_rreg(rdev, (0x8CF0), 0);
2186 if (((rdev->family) == CHIP_RV610) ||
2187 ((rdev->family) == CHIP_RV620) ||
2188 ((rdev->family) == CHIP_RS780) ||
2189 ((rdev->family) == CHIP_RS880)) {
2190 tmp = (CACHE_FIFO_SIZE(0xa)((0xa) << 0) |
2191 FETCH_FIFO_HIWATER(0xa)((0xa) << 8) |
2192 DONE_FIFO_HIWATER(0xe0)((0xe0) << 16) |
2193 ALU_UPDATE_FIFO_HIWATER(0x8)((0x8) << 24));
2194 } else if (((rdev->family) == CHIP_R600) ||
2195 ((rdev->family) == CHIP_RV630)) {
2196 tmp &= ~DONE_FIFO_HIWATER(0xff)((0xff) << 16);
2197 tmp |= DONE_FIFO_HIWATER(0x4)((0x4) << 16);
2198 }
2199 WREG32(SQ_MS_FIFO_SIZES, tmp)r100_mm_wreg(rdev, (0x8CF0), (tmp), 0);
2200
2201 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2202 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2203 */
2204 sq_config = RREG32(SQ_CONFIG)r100_mm_rreg(rdev, (0x8c00), 0);
2205 sq_config &= ~(PS_PRIO(3)((3) << 24) |
2206 VS_PRIO(3)((3) << 26) |
2207 GS_PRIO(3)((3) << 28) |
2208 ES_PRIO(3)((3) << 30));
2209 sq_config |= (DX9_CONSTS(1 << 2) |
2210 VC_ENABLE(1 << 0) |
2211 PS_PRIO(0)((0) << 24) |
2212 VS_PRIO(1)((1) << 26) |
2213 GS_PRIO(2)((2) << 28) |
2214 ES_PRIO(3)((3) << 30));
2215
2216 if ((rdev->family) == CHIP_R600) {
2217 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124)((124) << 0) |
2218 NUM_VS_GPRS(124)((124) << 16) |
2219 NUM_CLAUSE_TEMP_GPRS(4)((4) << 28));
2220 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0)((0) << 0) |
2221 NUM_ES_GPRS(0)((0) << 16));
2222 sq_thread_resource_mgmt = (NUM_PS_THREADS(136)((136) << 0) |
2223 NUM_VS_THREADS(48)((48) << 8) |
2224 NUM_GS_THREADS(4)((4) << 16) |
2225 NUM_ES_THREADS(4)((4) << 24));
2226 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128)((128) << 0) |
2227 NUM_VS_STACK_ENTRIES(128)((128) << 16));
2228 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0)((0) << 0) |
2229 NUM_ES_STACK_ENTRIES(0)((0) << 16));
2230 } else if (((rdev->family) == CHIP_RV610) ||
2231 ((rdev->family) == CHIP_RV620) ||
2232 ((rdev->family) == CHIP_RS780) ||
2233 ((rdev->family) == CHIP_RS880)) {
2234 /* no vertex cache */
2235 sq_config &= ~VC_ENABLE(1 << 0);
2236
2237 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44)((44) << 0) |
2238 NUM_VS_GPRS(44)((44) << 16) |
2239 NUM_CLAUSE_TEMP_GPRS(2)((2) << 28));
2240 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17)((17) << 0) |
2241 NUM_ES_GPRS(17)((17) << 16));
2242 sq_thread_resource_mgmt = (NUM_PS_THREADS(79)((79) << 0) |
2243 NUM_VS_THREADS(78)((78) << 8) |
2244 NUM_GS_THREADS(4)((4) << 16) |
2245 NUM_ES_THREADS(31)((31) << 24));
2246 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40)((40) << 0) |
2247 NUM_VS_STACK_ENTRIES(40)((40) << 16));
2248 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32)((32) << 0) |
2249 NUM_ES_STACK_ENTRIES(16)((16) << 16));
2250 } else if (((rdev->family) == CHIP_RV630) ||
2251 ((rdev->family) == CHIP_RV635)) {
2252 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44)((44) << 0) |
2253 NUM_VS_GPRS(44)((44) << 16) |
2254 NUM_CLAUSE_TEMP_GPRS(2)((2) << 28));
2255 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18)((18) << 0) |
2256 NUM_ES_GPRS(18)((18) << 16));
2257 sq_thread_resource_mgmt = (NUM_PS_THREADS(79)((79) << 0) |
2258 NUM_VS_THREADS(78)((78) << 8) |
2259 NUM_GS_THREADS(4)((4) << 16) |
2260 NUM_ES_THREADS(31)((31) << 24));
2261 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40)((40) << 0) |
2262 NUM_VS_STACK_ENTRIES(40)((40) << 16));
2263 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32)((32) << 0) |
2264 NUM_ES_STACK_ENTRIES(16)((16) << 16));
2265 } else if ((rdev->family) == CHIP_RV670) {
2266 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44)((44) << 0) |
2267 NUM_VS_GPRS(44)((44) << 16) |
2268 NUM_CLAUSE_TEMP_GPRS(2)((2) << 28));
2269 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17)((17) << 0) |
2270 NUM_ES_GPRS(17)((17) << 16));
2271 sq_thread_resource_mgmt = (NUM_PS_THREADS(79)((79) << 0) |
2272 NUM_VS_THREADS(78)((78) << 8) |
2273 NUM_GS_THREADS(4)((4) << 16) |
2274 NUM_ES_THREADS(31)((31) << 24));
2275 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64)((64) << 0) |
2276 NUM_VS_STACK_ENTRIES(64)((64) << 16));
2277 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64)((64) << 0) |
2278 NUM_ES_STACK_ENTRIES(64)((64) << 16));
2279 }
2280
2281 WREG32(SQ_CONFIG, sq_config)r100_mm_wreg(rdev, (0x8c00), (sq_config), 0);
2282 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1)r100_mm_wreg(rdev, (0x8c04), (sq_gpr_resource_mgmt_1), 0);
2283 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2)r100_mm_wreg(rdev, (0x8c08), (sq_gpr_resource_mgmt_2), 0);
2284 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt)r100_mm_wreg(rdev, (0x8c0c), (sq_thread_resource_mgmt), 0);
2285 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1)r100_mm_wreg(rdev, (0x8c10), (sq_stack_resource_mgmt_1), 0);
2286 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2)r100_mm_wreg(rdev, (0x8c14), (sq_stack_resource_mgmt_2), 0);
2287
2288 if (((rdev->family) == CHIP_RV610) ||
2289 ((rdev->family) == CHIP_RV620) ||
2290 ((rdev->family) == CHIP_RS780) ||
2291 ((rdev->family) == CHIP_RS880)) {
2292 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY))r100_mm_wreg(rdev, (0x88C4), (((1)<<0)), 0);
2293 } else {
2294 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC))r100_mm_wreg(rdev, (0x88C4), (((2)<<0)), 0);
2295 }
2296
2297 /* More default values. 2D/3D driver should adjust as needed */
2298 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |r100_mm_wreg(rdev, (0x8B40), ((((0xc) << 0) | ((0x4) <<
4) | ((0x4) << 8) | ((0xc) << 12))), 0)
2299 S1_X(0x4) | S1_Y(0xc)))r100_mm_wreg(rdev, (0x8B40), ((((0xc) << 0) | ((0x4) <<
4) | ((0x4) << 8) | ((0xc) << 12))), 0);
2300 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |r100_mm_wreg(rdev, (0x8B44), ((((0xe) << 0) | ((0xe) <<
4) | ((0x2) << 8) | ((0x2) << 12) | ((0xa) <<
16) | ((0x6) << 20) | ((0x6) << 24) | ((0xa) <<
28))), 0)
2301 S1_X(0x2) | S1_Y(0x2) |r100_mm_wreg(rdev, (0x8B44), ((((0xe) << 0) | ((0xe) <<
4) | ((0x2) << 8) | ((0x2) << 12) | ((0xa) <<
16) | ((0x6) << 20) | ((0x6) << 24) | ((0xa) <<
28))), 0)
2302 S2_X(0xa) | S2_Y(0x6) |r100_mm_wreg(rdev, (0x8B44), ((((0xe) << 0) | ((0xe) <<
4) | ((0x2) << 8) | ((0x2) << 12) | ((0xa) <<
16) | ((0x6) << 20) | ((0x6) << 24) | ((0xa) <<
28))), 0)
2303 S3_X(0x6) | S3_Y(0xa)))r100_mm_wreg(rdev, (0x8B44), ((((0xe) << 0) | ((0xe) <<
4) | ((0x2) << 8) | ((0x2) << 12) | ((0xa) <<
16) | ((0x6) << 20) | ((0x6) << 24) | ((0xa) <<
28))), 0);
2304 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |r100_mm_wreg(rdev, (0x8B48), ((((0xe) << 0) | ((0xb) <<
4) | ((0x4) << 8) | ((0xc) << 12) | ((0x1) <<
16) | ((0x6) << 20) | ((0xa) << 24) | ((0xe) <<
28))), 0)
2305 S1_X(0x4) | S1_Y(0xc) |r100_mm_wreg(rdev, (0x8B48), ((((0xe) << 0) | ((0xb) <<
4) | ((0x4) << 8) | ((0xc) << 12) | ((0x1) <<
16) | ((0x6) << 20) | ((0xa) << 24) | ((0xe) <<
28))), 0)
2306 S2_X(0x1) | S2_Y(0x6) |r100_mm_wreg(rdev, (0x8B48), ((((0xe) << 0) | ((0xb) <<
4) | ((0x4) << 8) | ((0xc) << 12) | ((0x1) <<
16) | ((0x6) << 20) | ((0xa) << 24) | ((0xe) <<
28))), 0)
2307 S3_X(0xa) | S3_Y(0xe)))r100_mm_wreg(rdev, (0x8B48), ((((0xe) << 0) | ((0xb) <<
4) | ((0x4) << 8) | ((0xc) << 12) | ((0x1) <<
16) | ((0x6) << 20) | ((0xa) << 24) | ((0xe) <<
28))), 0);
2308 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |r100_mm_wreg(rdev, (0x8B4C), ((((0x6) << 0) | ((0x1) <<
4) | ((0x0) << 8) | ((0x0) << 12) | ((0xb) <<
16) | ((0x4) << 20) | ((0x7) << 24) | ((0x8) <<
28))), 0)
2309 S5_X(0x0) | S5_Y(0x0) |r100_mm_wreg(rdev, (0x8B4C), ((((0x6) << 0) | ((0x1) <<
4) | ((0x0) << 8) | ((0x0) << 12) | ((0xb) <<
16) | ((0x4) << 20) | ((0x7) << 24) | ((0x8) <<
28))), 0)
2310 S6_X(0xb) | S6_Y(0x4) |r100_mm_wreg(rdev, (0x8B4C), ((((0x6) << 0) | ((0x1) <<
4) | ((0x0) << 8) | ((0x0) << 12) | ((0xb) <<
16) | ((0x4) << 20) | ((0x7) << 24) | ((0x8) <<
28))), 0)
2311 S7_X(0x7) | S7_Y(0x8)))r100_mm_wreg(rdev, (0x8B4C), ((((0x6) << 0) | ((0x1) <<
4) | ((0x0) << 8) | ((0x0) << 12) | ((0xb) <<
16) | ((0x4) << 20) | ((0x7) << 24) | ((0x8) <<
28))), 0);
2312
2313 WREG32(VGT_STRMOUT_EN, 0)r100_mm_wreg(rdev, (0x28AB0), (0), 0);
2314 tmp = rdev->config.r600.max_pipes * 16;
2315 switch (rdev->family) {
2316 case CHIP_RV610:
2317 case CHIP_RV620:
2318 case CHIP_RS780:
2319 case CHIP_RS880:
2320 tmp += 32;
2321 break;
2322 case CHIP_RV670:
2323 tmp += 128;
2324 break;
2325 default:
2326 break;
2327 }
2328 if (tmp > 256) {
2329 tmp = 256;
2330 }
2331 WREG32(VGT_ES_PER_GS, 128)r100_mm_wreg(rdev, (0x88CC), (128), 0);
2332 WREG32(VGT_GS_PER_ES, tmp)r100_mm_wreg(rdev, (0x88C8), (tmp), 0);
2333 WREG32(VGT_GS_PER_VS, 2)r100_mm_wreg(rdev, (0x88E8), (2), 0);
2334 WREG32(VGT_GS_VERTEX_REUSE, 16)r100_mm_wreg(rdev, (0x88D4), (16), 0);
2335
2336 /* more default values. 2D/3D driver should adjust as needed */
2337 WREG32(PA_SC_LINE_STIPPLE_STATE, 0)r100_mm_wreg(rdev, (0x8B10), (0), 0);
2338 WREG32(VGT_STRMOUT_EN, 0)r100_mm_wreg(rdev, (0x28AB0), (0), 0);
2339 WREG32(SX_MISC, 0)r100_mm_wreg(rdev, (0x28350), (0), 0);
2340 WREG32(PA_SC_MODE_CNTL, 0)r100_mm_wreg(rdev, (0x28A4C), (0), 0);
2341 WREG32(PA_SC_AA_CONFIG, 0)r100_mm_wreg(rdev, (0x28C04), (0), 0);
2342 WREG32(PA_SC_LINE_STIPPLE, 0)r100_mm_wreg(rdev, (0x28A0C), (0), 0);
2343 WREG32(SPI_INPUT_Z, 0)r100_mm_wreg(rdev, (0x286D8), (0), 0);
2344 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2))r100_mm_wreg(rdev, (0x286CC), (((2)<<0)), 0);
2345 WREG32(CB_COLOR7_FRAG, 0)r100_mm_wreg(rdev, (0x280FC), (0), 0);
2346
2347 /* Clear render buffer base addresses */
2348 WREG32(CB_COLOR0_BASE, 0)r100_mm_wreg(rdev, (0x28040), (0), 0);
2349 WREG32(CB_COLOR1_BASE, 0)r100_mm_wreg(rdev, (0x28044), (0), 0);
2350 WREG32(CB_COLOR2_BASE, 0)r100_mm_wreg(rdev, (0x28048), (0), 0);
2351 WREG32(CB_COLOR3_BASE, 0)r100_mm_wreg(rdev, (0x2804C), (0), 0);
2352 WREG32(CB_COLOR4_BASE, 0)r100_mm_wreg(rdev, (0x28050), (0), 0);
2353 WREG32(CB_COLOR5_BASE, 0)r100_mm_wreg(rdev, (0x28054), (0), 0);
2354 WREG32(CB_COLOR6_BASE, 0)r100_mm_wreg(rdev, (0x28058), (0), 0);
2355 WREG32(CB_COLOR7_BASE, 0)r100_mm_wreg(rdev, (0x2805C), (0), 0);
2356 WREG32(CB_COLOR7_FRAG, 0)r100_mm_wreg(rdev, (0x280FC), (0), 0);
2357
2358 switch (rdev->family) {
2359 case CHIP_RV610:
2360 case CHIP_RV620:
2361 case CHIP_RS780:
2362 case CHIP_RS880:
2363 tmp = TC_L2_SIZE(8)((8)<<5);
2364 break;
2365 case CHIP_RV630:
2366 case CHIP_RV635:
2367 tmp = TC_L2_SIZE(4)((4)<<5);
2368 break;
2369 case CHIP_R600:
2370 tmp = TC_L2_SIZE(0)((0)<<5) | L2_DISABLE_LATE_HIT(1<<9);
2371 break;
2372 default:
2373 tmp = TC_L2_SIZE(0)((0)<<5);
2374 break;
2375 }
2376 WREG32(TC_CNTL, tmp)r100_mm_wreg(rdev, (0x9608), (tmp), 0);
2377
2378 tmp = RREG32(HDP_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x2C00), 0);
2379 WREG32(HDP_HOST_PATH_CNTL, tmp)r100_mm_wreg(rdev, (0x2C00), (tmp), 0);
2380
2381 tmp = RREG32(ARB_POP)r100_mm_rreg(rdev, (0x2418), 0);
2382 tmp |= ENABLE_TC128(1 << 30);
2383 WREG32(ARB_POP, tmp)r100_mm_wreg(rdev, (0x2418), (tmp), 0);
2384
2385 WREG32(PA_SC_MULTI_CHIP_CNTL, 0)r100_mm_wreg(rdev, (0x8B20), (0), 0);
2386 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |r100_mm_wreg(rdev, (0x8A14), (((1 << 0) | ((3) <<
1))), 0)
2387 NUM_CLIP_SEQ(3)))r100_mm_wreg(rdev, (0x8A14), (((1 << 0) | ((3) <<
1))), 0);
2388 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095))r100_mm_wreg(rdev, (0x8BF0), (((4095) << 0)), 0);
2389 WREG32(VC_ENHANCE, 0)r100_mm_wreg(rdev, (0x9714), (0), 0);
2390}
2391
2392
2393/*
2394 * Indirect registers accessor
2395 */
2396u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2397{
2398 unsigned long flags;
2399 u32 r;
2400
2401 spin_lock_irqsave(&rdev->pciep_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->pciep_idx_lock); } while
(0);
2402 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff))r100_mm_wreg(rdev, (0x0038), (((reg) & 0xff)), 0);
2403 (void)RREG32(PCIE_PORT_INDEX)r100_mm_rreg(rdev, (0x0038), 0);
2404 r = RREG32(PCIE_PORT_DATA)r100_mm_rreg(rdev, (0x003C), 0);
2405 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->pciep_idx_lock); }
while (0);
2406 return r;
2407}
2408
2409void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2410{
2411 unsigned long flags;
2412
2413 spin_lock_irqsave(&rdev->pciep_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->pciep_idx_lock); } while
(0);
2414 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff))r100_mm_wreg(rdev, (0x0038), (((reg) & 0xff)), 0);
2415 (void)RREG32(PCIE_PORT_INDEX)r100_mm_rreg(rdev, (0x0038), 0);
2416 WREG32(PCIE_PORT_DATA, (v))r100_mm_wreg(rdev, (0x003C), ((v)), 0);
2417 (void)RREG32(PCIE_PORT_DATA)r100_mm_rreg(rdev, (0x003C), 0);
2418 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->pciep_idx_lock); }
while (0);
2419}
2420
2421/*
2422 * CP & Ring
2423 */
2424void r600_cp_stop(struct radeon_device *rdev)
2425{
2426 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX0)
2427 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2428 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1))r100_mm_wreg(rdev, (0x86D8), ((((1) & 1)<<28)), 0);
2429 WREG32(SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x8540), (0), 0);
2430 rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = false0;
2431}
2432
2433int r600_init_microcode(struct radeon_device *rdev)
2434{
2435 const char *chip_name;
2436 const char *rlc_chip_name;
2437 const char *smc_chip_name = "RV770";
2438 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2439 char fw_name[30];
2440 int err;
2441
2442 DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");
2443
2444 switch (rdev->family) {
53
←
Control jumps to 'case CHIP_JUNIPER:' at line 2510
→
2445 case CHIP_R600:
2446 chip_name = "R600";
2447 rlc_chip_name = "R600";
2448 break;
2449 case CHIP_RV610:
2450 chip_name = "RV610";
2451 rlc_chip_name = "R600";
2452 break;
2453 case CHIP_RV630:
2454 chip_name = "RV630";
2455 rlc_chip_name = "R600";
2456 break;
2457 case CHIP_RV620:
2458 chip_name = "RV620";
2459 rlc_chip_name = "R600";
2460 break;
2461 case CHIP_RV635:
2462 chip_name = "RV635";
2463 rlc_chip_name = "R600";
2464 break;
2465 case CHIP_RV670:
2466 chip_name = "RV670";
2467 rlc_chip_name = "R600";
2468 break;
2469 case CHIP_RS780:
2470 case CHIP_RS880:
2471 chip_name = "RS780";
2472 rlc_chip_name = "R600";
2473 break;
2474 case CHIP_RV770:
2475 chip_name = "RV770";
2476 rlc_chip_name = "R700";
2477 smc_chip_name = "RV770";
2478 smc_req_size = roundup2(RV770_SMC_UCODE_SIZE, 4)(((0x410d) + ((4) - 1)) & (~((__typeof(0x410d))(4) - 1)));
2479 break;
2480 case CHIP_RV730:
2481 chip_name = "RV730";
2482 rlc_chip_name = "R700";
2483 smc_chip_name = "RV730";
2484 smc_req_size = roundup2(RV730_SMC_UCODE_SIZE, 4)(((0x412c) + ((4) - 1)) & (~((__typeof(0x412c))(4) - 1)));
2485 break;
2486 case CHIP_RV710:
2487 chip_name = "RV710";
2488 rlc_chip_name = "R700";
2489 smc_chip_name = "RV710";
2490 smc_req_size = roundup2(RV710_SMC_UCODE_SIZE, 4)(((0x3f1f) + ((4) - 1)) & (~((__typeof(0x3f1f))(4) - 1)));
2491 break;
2492 case CHIP_RV740:
2493 chip_name = "RV730";
2494 rlc_chip_name = "R700";
2495 smc_chip_name = "RV740";
2496 smc_req_size = roundup2(RV740_SMC_UCODE_SIZE, 4)(((0x41c5) + ((4) - 1)) & (~((__typeof(0x41c5))(4) - 1)));
2497 break;
2498 case CHIP_CEDAR:
2499 chip_name = "CEDAR";
2500 rlc_chip_name = "CEDAR";
2501 smc_chip_name = "CEDAR";
2502 smc_req_size = roundup2(CEDAR_SMC_UCODE_SIZE, 4)(((0x5d50) + ((4) - 1)) & (~((__typeof(0x5d50))(4) - 1)));
2503 break;
2504 case CHIP_REDWOOD:
2505 chip_name = "REDWOOD";
2506 rlc_chip_name = "REDWOOD";
2507 smc_chip_name = "REDWOOD";
2508 smc_req_size = roundup2(REDWOOD_SMC_UCODE_SIZE, 4)(((0x5f0a) + ((4) - 1)) & (~((__typeof(0x5f0a))(4) - 1)));
2509 break;
2510 case CHIP_JUNIPER:
2511 chip_name = "JUNIPER";
2512 rlc_chip_name = "JUNIPER";
2513 smc_chip_name = "JUNIPER";
2514 smc_req_size = roundup2(JUNIPER_SMC_UCODE_SIZE, 4)(((0x5f1f) + ((4) - 1)) & (~((__typeof(0x5f1f))(4) - 1)));
2515 break;
54
←
 Execution continues on line 2538
→
2516 case CHIP_CYPRESS:
2517 case CHIP_HEMLOCK:
2518 chip_name = "CYPRESS";
2519 rlc_chip_name = "CYPRESS";
2520 smc_chip_name = "CYPRESS";
2521 smc_req_size = roundup2(CYPRESS_SMC_UCODE_SIZE, 4)(((0x61f7) + ((4) - 1)) & (~((__typeof(0x61f7))(4) - 1)));
2522 break;
2523 case CHIP_PALM:
2524 chip_name = "PALM";
2525 rlc_chip_name = "SUMO";
2526 break;
2527 case CHIP_SUMO:
2528 chip_name = "SUMO";
2529 rlc_chip_name = "SUMO";
2530 break;
2531 case CHIP_SUMO2:
2532 chip_name = "SUMO2";
2533 rlc_chip_name = "SUMO";
2534 break;
2535 default: BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/radeon/r600.c"
, 2535); } while (0);
2536 }
2537
2538 if (rdev->family
54.1
Field 'family' is >= CHIP_CEDAR
54.1
Field 'family' is >= CHIP_CEDAR
54.1
Field 'family' is >= CHIP_CEDAR
 >= CHIP_CEDAR) {
55
←
Taking true branch
→
2539 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE1120 * 4;
2540 me_req_size = EVERGREEN_PM4_UCODE_SIZE1376 * 4;
2541 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE768 * 4;
2542 } else if (rdev->family >= CHIP_RV770) {
2543 pfp_req_size = R700_PFP_UCODE_SIZE848 * 4;
2544 me_req_size = R700_PM4_UCODE_SIZE1360 * 4;
2545 rlc_req_size = R700_RLC_UCODE_SIZE1024 * 4;
2546 } else {
2547 pfp_req_size = R600_PFP_UCODE_SIZE576 * 4;
2548 me_req_size = R600_PM4_UCODE_SIZE1792 * 12;
2549 rlc_req_size = R600_RLC_UCODE_SIZE768 * 4;
2550 }
2551
2552 DRM_INFO("Loading %s Microcode\n", chip_name)printk("\0016" "[" "drm" "] " "Loading %s Microcode\n", chip_name
);
2553
2554 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2555 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
56
←
Calling 'request_firmware'
→
60
←
Returning from 'request_firmware'
→
2556 if (err
60.1
'err' is 0
60.1
'err' is 0
60.1
'err' is 0
)
61
←
Taking false branch
→
2557 goto out;
2558 if (rdev->pfp_fw->size != pfp_req_size) {
62
←
Assuming 'pfp_req_size' is equal to field 'size'
→
63
←
Taking false branch
→
2559 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "r600_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->pfp_fw->size, fw_name)
2560 rdev->pfp_fw->size, fw_name)printk("\0013" "r600_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->pfp_fw->size, fw_name);
2561 err = -EINVAL22;
2562 goto out;
2563 }
2564
2565 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2566 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
64
←
Calling 'request_firmware'
→
68
←
Returning from 'request_firmware'
→
2567 if (err
68.1
'err' is 0
68.1
'err' is 0
68.1
'err' is 0
)
69
←
Taking false branch
→
2568 goto out;
2569 if (rdev->me_fw->size != me_req_size) {
70
←
Assuming 'me_req_size' is equal to field 'size'
→
71
←
Taking false branch
→
2570 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "r600_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name)
2571 rdev->me_fw->size, fw_name)printk("\0013" "r600_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name);
2572 err = -EINVAL22;
2573 }
2574
2575 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2576 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
72
←
Calling 'request_firmware'
→
76
←
Returning from 'request_firmware'
→
2577 if (err
76.1
'err' is 0
76.1
'err' is 0
76.1
'err' is 0
)
77
←
Taking false branch
→
2578 goto out;
2579 if (rdev->rlc_fw->size != rlc_req_size) {
78
←
Assuming 'rlc_req_size' is equal to field 'size'
→
79
←
Taking false branch
→
2580 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "r600_rlc: Bogus length %zu in firmware \"%s\"\n"
, rdev->rlc_fw->size, fw_name)
2581 rdev->rlc_fw->size, fw_name)printk("\0013" "r600_rlc: Bogus length %zu in firmware \"%s\"\n"
, rdev->rlc_fw->size, fw_name);
2582 err = -EINVAL22;
2583 }
2584
2585 if ((rdev->family
79.1
Field 'family' is >= CHIP_RV770
79.1
Field 'family' is >= CHIP_RV770
79.1
Field 'family' is >= CHIP_RV770
 >= CHIP_RV770) && (rdev->family
79.2
Field 'family' is <= CHIP_HEMLOCK
79.2
Field 'family' is <= CHIP_HEMLOCK
79.2
Field 'family' is <= CHIP_HEMLOCK
 <= CHIP_HEMLOCK)) {
80
←
Taking true branch
→
2586 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2587 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
81
←
Calling 'request_firmware'
→
85
←
Returning from 'request_firmware'
→
2588 if (err) {
86
←
Assuming 'err' is 0
→
87
←
Taking false branch
→
2589 pr_err("smc: error loading firmware \"%s\"\n", fw_name)printk("\0013" "smc: error loading firmware \"%s\"\n", fw_name
);
2590 release_firmware(rdev->smc_fw);
2591 rdev->smc_fw = NULL((void *)0);
2592 err = 0;
2593 } else if (rdev->smc_fw->size != smc_req_size) {
88
←
Access to field 'size' results in a dereference of a null pointer (loaded from field 'smc_fw')
2594 pr_err("smc: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "smc: Bogus length %zu in firmware \"%s\"\n", rdev
->smc_fw->size, fw_name)
2595 rdev->smc_fw->size, fw_name)printk("\0013" "smc: Bogus length %zu in firmware \"%s\"\n", rdev
->smc_fw->size, fw_name);
2596 err = -EINVAL22;
2597 }
2598 }
2599
2600out:
2601 if (err) {
2602 if (err != -EINVAL22)
2603 pr_err("r600_cp: Failed to load firmware \"%s\"\n",printk("\0013" "r600_cp: Failed to load firmware \"%s\"\n", fw_name
)
2604 fw_name)printk("\0013" "r600_cp: Failed to load firmware \"%s\"\n", fw_name
);
2605 release_firmware(rdev->pfp_fw);
2606 rdev->pfp_fw = NULL((void *)0);
2607 release_firmware(rdev->me_fw);
2608 rdev->me_fw = NULL((void *)0);
2609 release_firmware(rdev->rlc_fw);
2610 rdev->rlc_fw = NULL((void *)0);
2611 release_firmware(rdev->smc_fw);
2612 rdev->smc_fw = NULL((void *)0);
2613 }
2614 return err;
2615}
2616
2617u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2618 struct radeon_ring *ring)
2619{
2620 u32 rptr;
2621
2622 if (rdev->wb.enabled)
2623 rptr = rdev->wb.wb[ring->rptr_offs/4];
2624 else
2625 rptr = RREG32(R600_CP_RB_RPTR)r100_mm_rreg(rdev, (0x8700), 0);
2626
2627 return rptr;
2628}
2629
2630u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2631 struct radeon_ring *ring)
2632{
2633 return RREG32(R600_CP_RB_WPTR)r100_mm_rreg(rdev, (0xc114), 0);
2634}
2635
2636void r600_gfx_set_wptr(struct radeon_device *rdev,
2637 struct radeon_ring *ring)
2638{
2639 WREG32(R600_CP_RB_WPTR, ring->wptr)r100_mm_wreg(rdev, (0xc114), (ring->wptr), 0);
2640 (void)RREG32(R600_CP_RB_WPTR)r100_mm_rreg(rdev, (0xc114), 0);
2641}
2642
2643static int r600_cp_load_microcode(struct radeon_device *rdev)
2644{
2645 const __be32 *fw_data;
2646 int i;
2647
2648 if (!rdev->me_fw || !rdev->pfp_fw)
2649 return -EINVAL22;
2650
2651 r600_cp_stop(rdev);
2652
2653 WREG32(CP_RB_CNTL,r100_mm_wreg(rdev, (0xC104), (ifdef __BIG_ENDIAN (2 << 16
) |endif (1 << 27) | ((15) << 8) | ((3) << 0
)), 0)
2654#ifdef __BIG_ENDIANr100_mm_wreg(rdev, (0xC104), (ifdef __BIG_ENDIAN (2 << 16
) |endif (1 << 27) | ((15) << 8) | ((3) << 0
)), 0)
2655 BUF_SWAP_32BIT |r100_mm_wreg(rdev, (0xC104), (ifdef __BIG_ENDIAN (2 << 16
) |endif (1 << 27) | ((15) << 8) | ((3) << 0
)), 0)
2656#endifr100_mm_wreg(rdev, (0xC104), (ifdef __BIG_ENDIAN (2 << 16
) |endif (1 << 27) | ((15) << 8) | ((3) << 0
)), 0)
2657 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3))r100_mm_wreg(rdev, (0xC104), (ifdef __BIG_ENDIAN (2 << 16
) |endif (1 << 27) | ((15) << 8) | ((3) << 0
)), 0);
2658
2659 /* Reset cp */
2660 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP)r100_mm_wreg(rdev, (0x8020), ((1<<0)), 0);
2661 RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
2662 mdelay(15);
2663 WREG32(GRBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x8020), (0), 0);
2664
2665 WREG32(CP_ME_RAM_WADDR, 0)r100_mm_wreg(rdev, (0xC15C), (0), 0);
2666
2667 fw_data = (const __be32 *)rdev->me_fw->data;
2668 WREG32(CP_ME_RAM_WADDR, 0)r100_mm_wreg(rdev, (0xC15C), (0), 0);
2669 for (i = 0; i < R600_PM4_UCODE_SIZE1792 * 3; i++)
2670 WREG32(CP_ME_RAM_DATA,r100_mm_wreg(rdev, (0xC160), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0)
2671 be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0xC160), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);
2672
2673 fw_data = (const __be32 *)rdev->pfp_fw->data;
2674 WREG32(CP_PFP_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0xC150), (0), 0);
2675 for (i = 0; i < R600_PFP_UCODE_SIZE576; i++)
2676 WREG32(CP_PFP_UCODE_DATA,r100_mm_wreg(rdev, (0xC154), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0)
2677 be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0xC154), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);
2678
2679 WREG32(CP_PFP_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0xC150), (0), 0);
2680 WREG32(CP_ME_RAM_WADDR, 0)r100_mm_wreg(rdev, (0xC15C), (0), 0);
2681 WREG32(CP_ME_RAM_RADDR, 0)r100_mm_wreg(rdev, (0xC158), (0), 0);
2682 return 0;
2683}
2684
2685int r600_cp_start(struct radeon_device *rdev)
2686{
2687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
2688 int r;
2689 uint32_t cp_me;
2690
2691 r = radeon_ring_lock(rdev, ring, 7);
2692 if (r) {
2693 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r)__drm_err("radeon: cp failed to lock ring (%d).\n", r);
2694 return r;
2695 }
2696 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)((3 << 30) | (((0x44) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
2697 radeon_ring_write(ring, 0x1);
2698 if (rdev->family >= CHIP_RV770) {
2699 radeon_ring_write(ring, 0x0);
2700 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2701 } else {
2702 radeon_ring_write(ring, 0x3);
2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2704 }
2705 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)((1) << 16));
2706 radeon_ring_write(ring, 0);
2707 radeon_ring_write(ring, 0);
2708 radeon_ring_unlock_commit(rdev, ring, false0);
2709
2710 cp_me = 0xff;
2711 WREG32(R_0086D8_CP_ME_CNTL, cp_me)r100_mm_wreg(rdev, (0x86D8), (cp_me), 0);
2712 return 0;
2713}
2714
2715int r600_cp_resume(struct radeon_device *rdev)
2716{
2717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
2718 u32 tmp;
2719 u32 rb_bufsz;
2720 int r;
2721
2722 /* Reset cp */
2723 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP)r100_mm_wreg(rdev, (0x8020), ((1<<0)), 0);
2724 RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
2725 mdelay(15);
2726 WREG32(GRBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x8020), (0), 0);
2727
2728 /* Set ring buffer size */
2729 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
2730 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8)drm_order(4096/8) << 8) | rb_bufsz;
2731#ifdef __BIG_ENDIAN
2732 tmp |= BUF_SWAP_32BIT(2 << 16);
2733#endif
2734 WREG32(CP_RB_CNTL, tmp)r100_mm_wreg(rdev, (0xC104), (tmp), 0);
2735 WREG32(CP_SEM_WAIT_TIMER, 0x0)r100_mm_wreg(rdev, (0x85BC), (0x0), 0);
2736
2737 /* Set the write pointer delay */
2738 WREG32(CP_RB_WPTR_DELAY, 0)r100_mm_wreg(rdev, (0x8704), (0), 0);
2739
2740 /* Initialize the ring buffer's read and write pointers */
2741 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA)r100_mm_wreg(rdev, (0xC104), (tmp | (1 << 31)), 0);
2742 WREG32(CP_RB_RPTR_WR, 0)r100_mm_wreg(rdev, (0xC108), (0), 0);
2743 ring->wptr = 0;
2744 WREG32(CP_RB_WPTR, ring->wptr)r100_mm_wreg(rdev, (0xC114), (ring->wptr), 0);
2745
2746 /* set the wb address whether it's enabled or not */
2747 WREG32(CP_RB_RPTR_ADDR,r100_mm_wreg(rdev, (0xC10C), (((rdev->wb.gpu_addr + 1024) &
0xFFFFFFFC)), 0)
2748 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC))r100_mm_wreg(rdev, (0xC10C), (((rdev->wb.gpu_addr + 1024) &
0xFFFFFFFC)), 0);
2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF)r100_mm_wreg(rdev, (0xC110), (((u32)(((rdev->wb.gpu_addr +
1024) >> 16) >> 16)) & 0xFF), 0);
2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF)r100_mm_wreg(rdev, (0x8544), (((rdev->wb.gpu_addr + 0) >>
8) & 0xFFFFFFFF), 0);
2751
2752 if (rdev->wb.enabled)
2753 WREG32(SCRATCH_UMSK, 0xff)r100_mm_wreg(rdev, (0x8540), (0xff), 0);
2754 else {
2755 tmp |= RB_NO_UPDATE(1 << 27);
2756 WREG32(SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x8540), (0), 0);
2757 }
2758
2759 mdelay(1);
2760 WREG32(CP_RB_CNTL, tmp)r100_mm_wreg(rdev, (0xC104), (tmp), 0);
2761
2762 WREG32(CP_RB_BASE, ring->gpu_addr >> 8)r100_mm_wreg(rdev, (0xC100), (ring->gpu_addr >> 8), 0
);
2763 WREG32(CP_DEBUG, (1 << 27) | (1 << 28))r100_mm_wreg(rdev, (0xC1FC), ((1 << 27) | (1 << 28
)), 0);
2764
2765 r600_cp_start(rdev);
2766 ring->ready = true1;
2767 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring)(rdev)->asic->ring[(0)]->ring_test((rdev), (ring));
2768 if (r) {
2769 ring->ready = false0;
2770 return r;
2771 }
2772
2773 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX0)
2774 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2775
2776 return 0;
2777}
2778
2779void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2780{
2781 u32 rb_bufsz;
2782 int r;
2783
2784 /* Align ring size */
2785 rb_bufsz = order_base_2(ring_size / 8)drm_order(ring_size / 8);
2786 ring_size = (1 << (rb_bufsz + 1)) * 4;
2787 ring->ring_size = ring_size;
2788 ring->align_mask = 16 - 1;
2789
2790 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2791 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2792 if (r) {
2793 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r)__drm_err("failed to get scratch reg for rptr save (%d).\n", r
);
2794 ring->rptr_save_reg = 0;
2795 }
2796 }
2797}
2798
2799void r600_cp_fini(struct radeon_device *rdev)
2800{
2801 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
2802 r600_cp_stop(rdev);
2803 radeon_ring_fini(rdev, ring);
2804 radeon_scratch_free(rdev, ring->rptr_save_reg);
2805}
2806
2807/*
2808 * GPU scratch registers helpers function.
2809 */
2810void r600_scratch_init(struct radeon_device *rdev)
2811{
2812 int i;
2813
2814 rdev->scratch.num_reg = 7;
2815 rdev->scratch.reg_base = SCRATCH_REG00x8500;
2816 for (i = 0; i < rdev->scratch.num_reg; i++) {
2817 rdev->scratch.free[i] = true1;
2818 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2819 }
2820}
2821
2822int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2823{
2824 uint32_t scratch;
2825 uint32_t tmp = 0;
2826 unsigned i;
2827 int r;
2828
2829 r = radeon_scratch_get(rdev, &scratch);
2830 if (r) {
2831 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r)__drm_err("radeon: cp failed to get scratch reg (%d).\n", r);
2832 return r;
2833 }
2834 WREG32(scratch, 0xCAFEDEAD)r100_mm_wreg(rdev, (scratch), (0xCAFEDEAD), 0);
2835 r = radeon_ring_lock(rdev, ring, 3);
2836 if (r) {
2837 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r)__drm_err("radeon: cp failed to lock ring %d (%d).\n", ring->
idx, r);
2838 radeon_scratch_free(rdev, scratch);
2839 return r;
2840 }
2841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
2842 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2));
2843 radeon_ring_write(ring, 0xDEADBEEF);
2844 radeon_ring_unlock_commit(rdev, ring, false0);
2845 for (i = 0; i < rdev->usec_timeout; i++) {
2846 tmp = RREG32(scratch)r100_mm_rreg(rdev, (scratch), 0);
2847 if (tmp == 0xDEADBEEF)
2848 break;
2849 udelay(1);
2850 }
2851 if (i < rdev->usec_timeout) {
2852 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i)printk("\0016" "[" "drm" "] " "ring test on %d succeeded in %d usecs\n"
, ring->idx, i);
2853 } else {
2854 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",__drm_err("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n"
, ring->idx, scratch, tmp)
2855 ring->idx, scratch, tmp)__drm_err("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n"
, ring->idx, scratch, tmp);
2856 r = -EINVAL22;
2857 }
2858 radeon_scratch_free(rdev, scratch);
2859 return r;
2860}
2861
2862/*
2863 * CP fences/semaphores
2864 */
2865
2866void r600_fence_ring_emit(struct radeon_device *rdev,
2867 struct radeon_fence *fence)
2868{
2869 struct radeon_ring *ring = &rdev->ring[fence->ring];
2870 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA(1 << 23) | PACKET3_VC_ACTION_ENA(1 << 24) |
2871 PACKET3_SH_ACTION_ENA(1 << 27);
2872
2873 if (rdev->family >= CHIP_RV770)
2874 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA(1 << 20);
2875
2876 if (rdev->wb.use_event) {
2877 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2878 /* flush read cache over gart */
2879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)((3 << 30) | (((0x43) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
2880 radeon_ring_write(ring, cp_coher_cntl);
2881 radeon_ring_write(ring, 0xFFFFFFFF);
2882 radeon_ring_write(ring, 0);
2883 radeon_ring_write(ring, 10); /* poll interval */
2884 /* EVENT_WRITE_EOP - flush caches, send int */
2885 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)((3 << 30) | (((0x47) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
2886 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS)(((0x14 << 0)) << 0) | EVENT_INDEX(5)((5) << 8));
2887 radeon_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
2888 radeon_ring_write(ring, (upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xff) | DATA_SEL(1)((1) << 29) | INT_SEL(2)((2) << 24));
2889 radeon_ring_write(ring, fence->seq);
2890 radeon_ring_write(ring, 0);
2891 } else {
2892 /* flush read cache over gart */
2893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)((3 << 30) | (((0x43) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
2894 radeon_ring_write(ring, cp_coher_cntl);
2895 radeon_ring_write(ring, 0xFFFFFFFF);
2896 radeon_ring_write(ring, 0);
2897 radeon_ring_write(ring, 10); /* poll interval */
2898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
2899 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT)(((0x16 << 0)) << 0) | EVENT_INDEX(0)((0) << 8));
2900 /* wait for 3D idle clean */
2901 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
2902 radeon_ring_write(ring, (WAIT_UNTIL0x8040 - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2);
2903 radeon_ring_write(ring, WAIT_3D_IDLE_bit(1 << 15) | WAIT_3D_IDLECLEAN_bit(1 << 17));
2904 /* Emit fence sequence & fire IRQ */
2905 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
2906 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2));
2907 radeon_ring_write(ring, fence->seq);
2908 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2909 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)((0 << 30) | (((0xc128) >> 2) & 0xFFFF) | ((0
) & 0x3FFF) << 16));
2910 radeon_ring_write(ring, RB_INT_STAT(1 << 31));
2911 }
2912}
2913
2914/**
2915 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2916 *
2917 * @rdev: radeon_device pointer
2918 * @ring: radeon ring buffer object
2919 * @semaphore: radeon semaphore object
2920 * @emit_wait: Is this a sempahore wait?
2921 *
2922 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2923 * from running ahead of semaphore waits.
2924 */
2925bool_Bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2926 struct radeon_ring *ring,
2927 struct radeon_semaphore *semaphore,
2928 bool_Bool emit_wait)
2929{
2930 uint64_t addr = semaphore->gpu_addr;
2931 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT(0x7 << 29) : PACKET3_SEM_SEL_SIGNAL(0x6 << 29);
2932
2933 if (rdev->family < CHIP_CAYMAN)
2934 sel |= PACKET3_SEM_WAIT_ON_SIGNAL(0x1 << 12);
2935
2936 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)((3 << 30) | (((0x39) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
2937 radeon_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
2938 radeon_ring_write(ring, (upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xff) | sel);
2939
2940 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2941 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2942 /* Prevent the PFP from running ahead of the semaphore wait */
2943 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)((3 << 30) | (((0x42) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
2944 radeon_ring_write(ring, 0x0);
2945 }
2946
2947 return true1;
2948}
2949
2950/**
2951 * r600_copy_cpdma - copy pages using the CP DMA engine
2952 *
2953 * @rdev: radeon_device pointer
2954 * @src_offset: src GPU address
2955 * @dst_offset: dst GPU address
2956 * @num_gpu_pages: number of GPU pages to xfer
2957 * @fence: radeon fence object
2958 *
2959 * Copy GPU paging using the CP DMA engine (r6xx+).
2960 * Used by the radeon ttm implementation to move pages if
2961 * registered as the asic copy callback.
2962 */
2963struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2964 uint64_t src_offset, uint64_t dst_offset,
2965 unsigned num_gpu_pages,
2966 struct dma_resv *resv)
2967{
2968 struct radeon_fence *fence;
2969 struct radeon_sync sync;
2970 int ring_index = rdev->asic->copy.blit_ring_index;
2971 struct radeon_ring *ring = &rdev->ring[ring_index];
2972 u32 size_in_bytes, cur_size_in_bytes, tmp;
2973 int i, num_loops;
2974 int r = 0;
2975
2976 radeon_sync_create(&sync);
2977
2978 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT12);
2979 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff)(((size_in_bytes) + ((0x1fffff) - 1)) / (0x1fffff));
2980 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2981 if (r) {
2982 DRM_ERROR("radeon: moving bo (%d).\n", r)__drm_err("radeon: moving bo (%d).\n", r);
2983 radeon_sync_free(rdev, &sync, NULL((void *)0));
2984 return ERR_PTR(r);
2985 }
2986
2987 radeon_sync_resv(rdev, &sync, resv, false0);
2988 radeon_sync_rings(rdev, &sync, ring->idx);
2989
2990 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
2991 radeon_ring_write(ring, (WAIT_UNTIL0x8040 - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2);
2992 radeon_ring_write(ring, WAIT_3D_IDLE_bit(1 << 15));
2993 for (i = 0; i < num_loops; i++) {
2994 cur_size_in_bytes = size_in_bytes;
2995 if (cur_size_in_bytes > 0x1fffff)
2996 cur_size_in_bytes = 0x1fffff;
2997 size_in_bytes -= cur_size_in_bytes;
2998 tmp = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16)) & 0xff;
2999 if (size_in_bytes == 0)
3000 tmp |= PACKET3_CP_DMA_CP_SYNC(1 << 31);
3001 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)((3 << 30) | (((0x41) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
3002 radeon_ring_write(ring, lower_32_bits(src_offset)((u32)(src_offset)));
3003 radeon_ring_write(ring, tmp);
3004 radeon_ring_write(ring, lower_32_bits(dst_offset)((u32)(dst_offset)));
3005 radeon_ring_write(ring, upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16)) & 0xff);
3006 radeon_ring_write(ring, cur_size_in_bytes);
3007 src_offset += cur_size_in_bytes;
3008 dst_offset += cur_size_in_bytes;
3009 }
3010 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3011 radeon_ring_write(ring, (WAIT_UNTIL0x8040 - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2);
3012 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit(1 << 8));
3013
3014 r = radeon_fence_emit(rdev, &fence, ring->idx);
3015 if (r) {
3016 radeon_ring_unlock_undo(rdev, ring);
3017 radeon_sync_free(rdev, &sync, NULL((void *)0));
3018 return ERR_PTR(r);
3019 }
3020
3021 radeon_ring_unlock_commit(rdev, ring, false0);
3022 radeon_sync_free(rdev, &sync, fence);
3023
3024 return fence;
3025}
3026
3027int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3028 uint32_t tiling_flags, uint32_t pitch,
3029 uint32_t offset, uint32_t obj_size)
3030{
3031 /* FIXME: implement */
3032 return 0;
3033}
3034
3035void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3036{
3037 /* FIXME: implement */
3038}
3039
3040static void r600_uvd_init(struct radeon_device *rdev)
3041{
3042 int r;
3043
3044 if (!rdev->has_uvd)
3045 return;
3046
3047 r = radeon_uvd_init(rdev);
3048 if (r) {
3049 dev_err(rdev->dev, "failed UVD (%d) init.\n", r)printf("drm:pid%d:%s *ERROR* " "failed UVD (%d) init.\n", ({struct
cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__ , r);
3050 /*
3051 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3052 * to early fails uvd_v1_0_resume() and thus nothing happens
3053 * there. So it is pointless to try to go through that code
3054 * hence why we disable uvd here.
3055 */
3056 rdev->has_uvd = false0;
3057 return;
3058 }
3059 rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_obj = NULL((void *)0);
3060 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX5], 4096);
3061}
3062
3063static void r600_uvd_start(struct radeon_device *rdev)
3064{
3065 int r;
3066
3067 if (!rdev->has_uvd)
3068 return;
3069
3070 r = uvd_v1_0_resume(rdev);
3071 if (r) {
3072 dev_err(rdev->dev, "failed UVD resume (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed UVD resume (%d).\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3073 goto error;
3074 }
3075 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX5);
3076 if (r) {
3077 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3078 goto error;
3079 }
3080 return;
3081
3082error:
3083 rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_size = 0;
3084}
3085
3086static void r600_uvd_resume(struct radeon_device *rdev)
3087{
3088 struct radeon_ring *ring;
3089 int r;
3090
3091 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_size)
3092 return;
3093
3094 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX5];
3095 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)((0 << 30) | (((0xeffc) >> 2) & 0xFFFF) | ((0
) & 0x3FFF) << 16));
3096 if (r) {
3097 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD ring (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3098 return;
3099 }
3100 r = uvd_v1_0_init(rdev);
3101 if (r) {
3102 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3103 return;
3104 }
3105}
3106
3107static int r600_startup(struct radeon_device *rdev)
3108{
3109 struct radeon_ring *ring;
3110 int r;
3111
3112 /* enable pcie gen2 link */
3113 r600_pcie_gen2_enable(rdev);
3114
3115 /* scratch needs to be initialized before MC */
3116 r = r600_vram_scratch_init(rdev);
3117 if (r)
3118 return r;
3119
3120 r600_mc_program(rdev);
3121
3122 if (rdev->flags & RADEON_IS_AGP) {
3123 r600_agp_enable(rdev);
3124 } else {
3125 r = r600_pcie_gart_enable(rdev);
3126 if (r)
3127 return r;
3128 }
3129 r600_gpu_init(rdev);
3130
3131 /* allocate wb buffer */
3132 r = radeon_wb_init(rdev);
3133 if (r)
3134 return r;
3135
3136 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0);
3137 if (r) {
3138 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3139 return r;
3140 }
3141
3142 r600_uvd_start(rdev);
3143
3144 /* Enable IRQ */
3145 if (!rdev->irq.installed) {
3146 r = radeon_irq_kms_init(rdev);
3147 if (r)
3148 return r;
3149 }
3150
3151 r = r600_irq_init(rdev);
3152 if (r) {
3153 DRM_ERROR("radeon: IH init failed (%d).\n", r)__drm_err("radeon: IH init failed (%d).\n", r);
3154 radeon_irq_kms_fini(rdev);
3155 return r;
3156 }
3157 r600_irq_set(rdev);
3158
3159 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
3160 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET1024,
3161 RADEON_CP_PACKET20x80000000);
3162 if (r)
3163 return r;
3164
3165 r = r600_cp_load_microcode(rdev);
3166 if (r)
3167 return r;
3168 r = r600_cp_resume(rdev);
3169 if (r)
3170 return r;
3171
3172 r600_uvd_resume(rdev);
3173
3174 r = radeon_ib_pool_init(rdev);
3175 if (r) {
3176 dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
3177 return r;
3178 }
3179
3180 r = radeon_audio_init(rdev);
3181 if (r) {
3182 DRM_ERROR("radeon: audio init failed\n")__drm_err("radeon: audio init failed\n");
3183 return r;
3184 }
3185
3186 return 0;
3187}
3188
3189void r600_vga_set_state(struct radeon_device *rdev, bool_Bool state)
3190{
3191 uint32_t temp;
3192
3193 temp = RREG32(CONFIG_CNTL)r100_mm_rreg(rdev, (0x5424), 0);
3194 if (!state) {
3195 temp &= ~(1<<0);
3196 temp |= (1<<1);
3197 } else {
3198 temp &= ~(1<<1);
3199 }
3200 WREG32(CONFIG_CNTL, temp)r100_mm_wreg(rdev, (0x5424), (temp), 0);
3201}
3202
3203int r600_resume(struct radeon_device *rdev)
3204{
3205 int r;
3206
3207 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3208 * posting will perform necessary task to bring back GPU into good
3209 * shape.
3210 */
3211 /* post card */
3212 atom_asic_init(rdev->mode_info.atom_context);
3213
3214 if (rdev->pm.pm_method == PM_METHOD_DPM)
3215 radeon_pm_resume(rdev);
3216
3217 rdev->accel_working = true1;
3218 r = r600_startup(rdev);
3219 if (r) {
3220 DRM_ERROR("r600 startup failed on resume\n")__drm_err("r600 startup failed on resume\n");
3221 rdev->accel_working = false0;
3222 return r;
3223 }
3224
3225 return r;
3226}
3227
3228int r600_suspend(struct radeon_device *rdev)
3229{
3230 radeon_pm_suspend(rdev);
3231 radeon_audio_fini(rdev);
3232 r600_cp_stop(rdev);
3233 if (rdev->has_uvd) {
3234 uvd_v1_0_fini(rdev);
3235 radeon_uvd_suspend(rdev);
3236 }
3237 r600_irq_suspend(rdev);
3238 radeon_wb_disable(rdev);
3239 r600_pcie_gart_disable(rdev);
3240
3241 return 0;
3242}
3243
3244/* Plan is to move initialization in that function and use
3245 * helper function so that radeon_device_init pretty much
3246 * do nothing more than calling asic specific function. This
3247 * should also allow to remove a bunch of callback function
3248 * like vram_info.
3249 */
3250int r600_init(struct radeon_device *rdev)
3251{
3252 int r;
3253
3254 if (r600_debugfs_mc_info_init(rdev)) {
1
Calling 'r600_debugfs_mc_info_init'
→
4
←
Returning from 'r600_debugfs_mc_info_init'
→
5
←
Taking false branch
→
3255 DRM_ERROR("Failed to register debugfs file for mc !\n")__drm_err("Failed to register debugfs file for mc !\n");
3256 }
3257 /* Read BIOS */
3258 if (!radeon_get_bios(rdev)) {
6
←
Assuming the condition is false
→
7
←
Taking false branch
→
3259 if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
3260 return -EINVAL22;
3261 }
3262 /* Must be an ATOMBIOS */
3263 if (!rdev->is_atom_bios) {
8
←
Assuming field 'is_atom_bios' is true
→
9
←
Taking false branch
→
3264 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n")printf("drm:pid%d:%s *ERROR* " "Expecting atombios for R600 GPU\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
3265 return -EINVAL22;
3266 }
3267 r = radeon_atombios_init(rdev);
3268 if (r)
10
←
Assuming 'r' is 0
→
11
←
Taking false branch
→
3269 return r;
3270 /* Post card if necessary */
3271 if (!radeon_card_posted(rdev)) {
12
←
Assuming the condition is false
→
13
←
Taking false branch
→
3272 if (!rdev->bios) {
3273 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n")printf("drm:pid%d:%s *ERROR* " "Card not posted and no BIOS - ignoring\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
3274 return -EINVAL22;
3275 }
3276 DRM_INFO("GPU not posted. posting now...\n")printk("\0016" "[" "drm" "] " "GPU not posted. posting now...\n"
);
3277 atom_asic_init(rdev->mode_info.atom_context);
3278 }
3279 /* Initialize scratch registers */
3280 r600_scratch_init(rdev);
3281 /* Initialize surface registers */
3282 radeon_surface_init(rdev);
3283 /* Initialize clocks */
3284 radeon_get_clock_info(rdev->ddev);
3285 /* Fence driver */
3286 r = radeon_fence_driver_init(rdev);
3287 if (r)
14
←
Assuming 'r' is 0
→
15
←
Taking false branch
→
3288 return r;
3289 if (rdev->flags & RADEON_IS_AGP) {
16
←
Assuming the condition is false
→
17
←
Taking false branch
→
3290 r = radeon_agp_init(rdev);
3291 if (r)
3292 radeon_agp_disable(rdev);
3293 }
3294 r = r600_mc_init(rdev);
18
←
Calling 'r600_mc_init'
→
44
←
Returning from 'r600_mc_init'
→
3295 if (r
44.1
'r' is 0
44.1
'r' is 0
44.1
'r' is 0
)
45
←
Taking false branch
→
3296 return r;
3297 /* Memory manager */
3298 r = radeon_bo_init(rdev);
3299 if (r)
46
←
Assuming 'r' is 0
→
47
←
Taking false branch
→
3300 return r;
3301
3302 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
48
←
Assuming field 'me_fw' is non-null
→
49
←
Assuming field 'pfp_fw' is non-null
→
50
←
Assuming field 'rlc_fw' is null
→
51
←
Taking true branch
→
3303 r = r600_init_microcode(rdev);
52
←
Calling 'r600_init_microcode'
→
3304 if (r) {
3305 DRM_ERROR("Failed to load firmware!\n")__drm_err("Failed to load firmware!\n");
3306 return r;
3307 }
3308 }
3309
3310 /* Initialize power management */
3311 radeon_pm_init(rdev);
3312
3313 rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ring_obj = NULL((void *)0);
3314 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0], 1024 * 1024);
3315
3316 r600_uvd_init(rdev);
3317
3318 rdev->ih.ring_obj = NULL((void *)0);
3319 r600_ih_ring_init(rdev, 64 * 1024);
3320
3321 r = r600_pcie_gart_init(rdev);
3322 if (r)
3323 return r;
3324
3325 rdev->accel_working = true1;
3326 r = r600_startup(rdev);
3327 if (r) {
3328 dev_err(rdev->dev, "disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "disabling GPU acceleration\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
3329 r600_cp_fini(rdev);
3330 r600_irq_fini(rdev);
3331 radeon_wb_fini(rdev);
3332 radeon_ib_pool_fini(rdev);
3333 radeon_irq_kms_fini(rdev);
3334 r600_pcie_gart_fini(rdev);
3335 rdev->accel_working = false0;
3336 }
3337
3338 return 0;
3339}
3340
3341void r600_fini(struct radeon_device *rdev)
3342{
3343 radeon_pm_fini(rdev);
3344 radeon_audio_fini(rdev);
3345 r600_cp_fini(rdev);
3346 r600_irq_fini(rdev);
3347 if (rdev->has_uvd) {
3348 uvd_v1_0_fini(rdev);
3349 radeon_uvd_fini(rdev);
3350 }
3351 radeon_wb_fini(rdev);
3352 radeon_ib_pool_fini(rdev);
3353 radeon_irq_kms_fini(rdev);
3354 r600_pcie_gart_fini(rdev);
3355 r600_vram_scratch_fini(rdev);
3356 radeon_agp_fini(rdev);
3357 radeon_gem_fini(rdev);
3358 radeon_fence_driver_fini(rdev);
3359 radeon_bo_fini(rdev);
3360 radeon_atombios_fini(rdev);
3361 kfree(rdev->bios);
3362 rdev->bios = NULL((void *)0);
3363}
3364
3365
3366/*
3367 * CS stuff
3368 */
3369void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3370{
3371 struct radeon_ring *ring = &rdev->ring[ib->ring];
3372 u32 next_rptr;
3373
3374 if (ring->rptr_save_reg) {
3375 next_rptr = ring->wptr + 3 + 4;
3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3377 radeon_ring_write(ring, ((ring->rptr_save_reg -
3378 PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2));
3379 radeon_ring_write(ring, next_rptr);
3380 } else if (rdev->wb.enabled) {
3381 next_rptr = ring->wptr + 5 + 4;
3382 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)((3 << 30) | (((0x3D) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
3383 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3384 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr)((u32)(((ring->next_rptr_gpu_addr) >> 16) >> 16
)) & 0xff) | (1 << 18));
3385 radeon_ring_write(ring, next_rptr);
3386 radeon_ring_write(ring, 0);
3387 }
3388
3389 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x32) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
3390 radeon_ring_write(ring,
3391#ifdef __BIG_ENDIAN
3392 (2 << 0) |
3393#endif
3394 (ib->gpu_addr & 0xFFFFFFFC));
3395 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)) & 0xFF);
3396 radeon_ring_write(ring, ib->length_dw);
3397}
3398
3399int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3400{
3401 struct radeon_ib ib;
3402 uint32_t scratch;
3403 uint32_t tmp = 0;
3404 unsigned i;
3405 int r;
3406
3407 r = radeon_scratch_get(rdev, &scratch);
3408 if (r) {
3409 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r)__drm_err("radeon: failed to get scratch reg (%d).\n", r);
3410 return r;
3411 }
3412 WREG32(scratch, 0xCAFEDEAD)r100_mm_wreg(rdev, (scratch), (0xCAFEDEAD), 0);
3413 r = radeon_ib_get(rdev, ring->idx, &ib, NULL((void *)0), 256);
3414 if (r) {
3415 DRM_ERROR("radeon: failed to get ib (%d).\n", r)__drm_err("radeon: failed to get ib (%d).\n", r);
3416 goto free_scratch;
3417 }
3418 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16);
3419 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET0x00008000) >> 2);
3420 ib.ptr[2] = 0xDEADBEEF;
3421 ib.length_dw = 3;
3422 r = radeon_ib_schedule(rdev, &ib, NULL((void *)0), false0);
3423 if (r) {
3424 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r)__drm_err("radeon: failed to schedule ib (%d).\n", r);
3425 goto free_ib;
3426 }
3427 r = radeon_fence_wait_timeout(ib.fence, false0, usecs_to_jiffies((((uint64_t)(1000000)) * hz / 1000000)
3428 RADEON_USEC_IB_TEST_TIMEOUT)(((uint64_t)(1000000)) * hz / 1000000));
3429 if (r < 0) {
3430 DRM_ERROR("radeon: fence wait failed (%d).\n", r)__drm_err("radeon: fence wait failed (%d).\n", r);
3431 goto free_ib;
3432 } else if (r == 0) {
3433 DRM_ERROR("radeon: fence wait timed out.\n")__drm_err("radeon: fence wait timed out.\n");
3434 r = -ETIMEDOUT60;
3435 goto free_ib;
3436 }
3437 r = 0;
3438 for (i = 0; i < rdev->usec_timeout; i++) {
3439 tmp = RREG32(scratch)r100_mm_rreg(rdev, (scratch), 0);
3440 if (tmp == 0xDEADBEEF)
3441 break;
3442 udelay(1);
3443 }
3444 if (i < rdev->usec_timeout) {
3445 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i)printk("\0016" "[" "drm" "] " "ib test on ring %d succeeded in %u usecs\n"
, ib.fence->ring, i);
3446 } else {
3447 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",__drm_err("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp)
3448 scratch, tmp)__drm_err("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp);
3449 r = -EINVAL22;
3450 }
3451free_ib:
3452 radeon_ib_free(rdev, &ib);
3453free_scratch:
3454 radeon_scratch_free(rdev, scratch);
3455 return r;
3456}
3457
3458/*
3459 * Interrupts
3460 *
3461 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3462 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3463 * writing to the ring and the GPU consuming, the GPU writes to the ring
3464 * and host consumes. As the host irq handler processes interrupts, it
3465 * increments the rptr. When the rptr catches up with the wptr, all the
3466 * current interrupts have been processed.
3467 */
3468
3469void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3470{
3471 u32 rb_bufsz;
3472
3473 /* Align ring size */
3474 rb_bufsz = order_base_2(ring_size / 4)drm_order(ring_size / 4);
3475 ring_size = (1 << rb_bufsz) * 4;
3476 rdev->ih.ring_size = ring_size;
3477 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3478 rdev->ih.rptr = 0;
3479}
3480
3481int r600_ih_ring_alloc(struct radeon_device *rdev)
3482{
3483 int r;
3484
3485 /* Allocate ring buffer */
3486 if (rdev->ih.ring_obj == NULL((void *)0)) {
3487 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3488 PAGE_SIZE(1 << 12), true1,
3489 RADEON_GEM_DOMAIN_GTT0x2, 0,
3490 NULL((void *)0), NULL((void *)0), &rdev->ih.ring_obj);
3491 if (r) {
3492 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r)__drm_err("radeon: failed to create ih ring buffer (%d).\n", r
);
3493 return r;
3494 }
3495 r = radeon_bo_reserve(rdev->ih.ring_obj, false0);
3496 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
3497 return r;
3498 r = radeon_bo_pin(rdev->ih.ring_obj,
3499 RADEON_GEM_DOMAIN_GTT0x2,
3500 &rdev->ih.gpu_addr);
3501 if (r) {
3502 radeon_bo_unreserve(rdev->ih.ring_obj);
3503 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r)__drm_err("radeon: failed to pin ih ring buffer (%d).\n", r);
3504 return r;
3505 }
3506 r = radeon_bo_kmap(rdev->ih.ring_obj,
3507 (void **)&rdev->ih.ring);
3508 radeon_bo_unreserve(rdev->ih.ring_obj);
3509 if (r) {
3510 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r)__drm_err("radeon: failed to map ih ring buffer (%d).\n", r);
3511 return r;
3512 }
3513 }
3514 return 0;
3515}
3516
3517void r600_ih_ring_fini(struct radeon_device *rdev)
3518{
3519 int r;
3520 if (rdev->ih.ring_obj) {
3521 r = radeon_bo_reserve(rdev->ih.ring_obj, false0);
3522 if (likely(r == 0)__builtin_expect(!!(r == 0), 1)) {
3523 radeon_bo_kunmap(rdev->ih.ring_obj);
3524 radeon_bo_unpin(rdev->ih.ring_obj);
3525 radeon_bo_unreserve(rdev->ih.ring_obj);
3526 }
3527 radeon_bo_unref(&rdev->ih.ring_obj);
3528 rdev->ih.ring = NULL((void *)0);
3529 rdev->ih.ring_obj = NULL((void *)0);
3530 }
3531}
3532
3533void r600_rlc_stop(struct radeon_device *rdev)
3534{
3535
3536 if ((rdev->family >= CHIP_RV770) &&
3537 (rdev->family <= CHIP_RV740)) {
3538 /* r7xx asics need to soft reset RLC before halting */
3539 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC)r100_mm_wreg(rdev, (0xe60), ((1 << 13)), 0);
3540 RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0xe60), 0);
3541 mdelay(15);
3542 WREG32(SRBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0xe60), (0), 0);
3543 RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0xe60), 0);
3544 }
3545
3546 WREG32(RLC_CNTL, 0)r100_mm_wreg(rdev, (0x3f00), (0), 0);
3547}
3548
3549static void r600_rlc_start(struct radeon_device *rdev)
3550{
3551 WREG32(RLC_CNTL, RLC_ENABLE)r100_mm_wreg(rdev, (0x3f00), ((1 << 0)), 0);
3552}
3553
3554static int r600_rlc_resume(struct radeon_device *rdev)
3555{
3556 u32 i;
3557 const __be32 *fw_data;
3558
3559 if (!rdev->rlc_fw)
3560 return -EINVAL22;
3561
3562 r600_rlc_stop(rdev);
3563
3564 WREG32(RLC_HB_CNTL, 0)r100_mm_wreg(rdev, (0x3f0c), (0), 0);
3565
3566 WREG32(RLC_HB_BASE, 0)r100_mm_wreg(rdev, (0x3f10), (0), 0);
3567 WREG32(RLC_HB_RPTR, 0)r100_mm_wreg(rdev, (0x3f20), (0), 0);
3568 WREG32(RLC_HB_WPTR, 0)r100_mm_wreg(rdev, (0x3f1c), (0), 0);
3569 WREG32(RLC_HB_WPTR_LSB_ADDR, 0)r100_mm_wreg(rdev, (0x3f14), (0), 0);
3570 WREG32(RLC_HB_WPTR_MSB_ADDR, 0)r100_mm_wreg(rdev, (0x3f18), (0), 0);
3571 WREG32(RLC_MC_CNTL, 0)r100_mm_wreg(rdev, (0x3f44), (0), 0);
3572 WREG32(RLC_UCODE_CNTL, 0)r100_mm_wreg(rdev, (0x3f48), (0), 0);
3573
3574 fw_data = (const __be32 *)rdev->rlc_fw->data;
3575 if (rdev->family >= CHIP_RV770) {
3576 for (i = 0; i < R700_RLC_UCODE_SIZE1024; i++) {
3577 WREG32(RLC_UCODE_ADDR, i)r100_mm_wreg(rdev, (0x3f2c), (i), 0);
3578 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0x3f30), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);
3579 }
3580 } else {
3581 for (i = 0; i < R600_RLC_UCODE_SIZE768; i++) {
3582 WREG32(RLC_UCODE_ADDR, i)r100_mm_wreg(rdev, (0x3f2c), (i), 0);
3583 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0x3f30), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
*)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);
3584 }
3585 }
3586 WREG32(RLC_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0x3f2c), (0), 0);
3587
3588 r600_rlc_start(rdev);
3589
3590 return 0;
3591}
3592
3593static void r600_enable_interrupts(struct radeon_device *rdev)
3594{
3595 u32 ih_cntl = RREG32(IH_CNTL)r100_mm_rreg(rdev, (0x3e18), 0);
3596 u32 ih_rb_cntl = RREG32(IH_RB_CNTL)r100_mm_rreg(rdev, (0x3e00), 0);
3597
3598 ih_cntl |= ENABLE_INTR(1 << 0);
3599 ih_rb_cntl |= IH_RB_ENABLE(1 << 0);
3600 WREG32(IH_CNTL, ih_cntl)r100_mm_wreg(rdev, (0x3e18), (ih_cntl), 0);
3601 WREG32(IH_RB_CNTL, ih_rb_cntl)r100_mm_wreg(rdev, (0x3e00), (ih_rb_cntl), 0);
3602 rdev->ih.enabled = true1;
3603}
3604
3605void r600_disable_interrupts(struct radeon_device *rdev)
3606{
3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL)r100_mm_rreg(rdev, (0x3e00), 0);
3608 u32 ih_cntl = RREG32(IH_CNTL)r100_mm_rreg(rdev, (0x3e18), 0);
3609
3610 ih_rb_cntl &= ~IH_RB_ENABLE(1 << 0);
3611 ih_cntl &= ~ENABLE_INTR(1 << 0);
3612 WREG32(IH_RB_CNTL, ih_rb_cntl)r100_mm_wreg(rdev, (0x3e00), (ih_rb_cntl), 0);
3613 WREG32(IH_CNTL, ih_cntl)r100_mm_wreg(rdev, (0x3e18), (ih_cntl), 0);
3614 /* set rptr, wptr to 0 */
3615 WREG32(IH_RB_RPTR, 0)r100_mm_wreg(rdev, (0x3e08), (0), 0);
3616 WREG32(IH_RB_WPTR, 0)r100_mm_wreg(rdev, (0x3e0c), (0), 0);
3617 rdev->ih.enabled = false0;
3618 rdev->ih.rptr = 0;
3619}
3620
3621static void r600_disable_interrupt_state(struct radeon_device *rdev)
3622{
3623 u32 tmp;
3624
3625 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE)r100_mm_wreg(rdev, (0xc124), ((1 << 19) | (1 << 20
)), 0);
3626 tmp = RREG32(DMA_CNTL)r100_mm_rreg(rdev, (0xd02c), 0) & ~TRAP_ENABLE(1 << 0);
3627 WREG32(DMA_CNTL, tmp)r100_mm_wreg(rdev, (0xd02c), (tmp), 0);
3628 WREG32(GRBM_INT_CNTL, 0)r100_mm_wreg(rdev, (0x8060), (0), 0);
3629 WREG32(DxMODE_INT_MASK, 0)r100_mm_wreg(rdev, (0x6540), (0), 0);
3630 WREG32(D1GRPH_INTERRUPT_CONTROL, 0)r100_mm_wreg(rdev, (0x615c), (0), 0);
3631 WREG32(D2GRPH_INTERRUPT_CONTROL, 0)r100_mm_wreg(rdev, (0x695c), (0), 0);
3632 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3633 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0)r100_mm_wreg(rdev, (0x7038), (0), 0);
3634 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0)r100_mm_wreg(rdev, (0x7138), (0), 0);
3635 tmp = RREG32(DC_HPD1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d04), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3636 WREG32(DC_HPD1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d04), (tmp), 0);
3637 tmp = RREG32(DC_HPD2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d10), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3638 WREG32(DC_HPD2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d10), (tmp), 0);
3639 tmp = RREG32(DC_HPD3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d1c), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3640 WREG32(DC_HPD3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d1c), (tmp), 0);
3641 tmp = RREG32(DC_HPD4_INT_CONTROL)r100_mm_rreg(rdev, (0x7d28), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3642 WREG32(DC_HPD4_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d28), (tmp), 0);
3643 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
3644 tmp = RREG32(DC_HPD5_INT_CONTROL)r100_mm_rreg(rdev, (0x7dc4), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3645 WREG32(DC_HPD5_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7dc4), (tmp), 0);
3646 tmp = RREG32(DC_HPD6_INT_CONTROL)r100_mm_rreg(rdev, (0x7df8), 0) & DC_HPDx_INT_POLARITY(1 << 8);
3647 WREG32(DC_HPD6_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7df8), (tmp), 0);
3648 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0)r100_mm_rreg(rdev, (0x7604 + (0x7400 - 0x7400)), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3649 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp)r100_mm_wreg(rdev, (0x7604 + (0x7400 - 0x7400)), (tmp), 0);
3650 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1)r100_mm_rreg(rdev, (0x7604 + (0x7800 - 0x7400)), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3651 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp)r100_mm_wreg(rdev, (0x7604 + (0x7800 - 0x7400)), (tmp), 0);
3652 } else {
3653 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7408), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3654 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7408), (tmp), 0);
3655 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7808), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3656 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7808), (tmp), 0);
3657 }
3658 } else {
3659 WREG32(DACA_AUTODETECT_INT_CONTROL, 0)r100_mm_wreg(rdev, (0x7838), (0), 0);
3660 WREG32(DACB_AUTODETECT_INT_CONTROL, 0)r100_mm_wreg(rdev, (0x7a38), (0), 0);
3661 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d08), 0) & DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
3662 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d08), (tmp), 0);
3663 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d18), 0) & DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
3664 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d18), (tmp), 0);
3665 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d2c), 0) & DC_HOT_PLUG_DETECTx_INT_POLARITY(1 << 8);
3666 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d2c), (tmp), 0);
3667 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7408), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3668 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7408), (tmp), 0);
3669 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7708), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3670 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7708), (tmp), 0);
3671 }
3672}
3673
3674int r600_irq_init(struct radeon_device *rdev)
3675{
3676 int ret = 0;
3677 int rb_bufsz;
3678 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3679
3680 /* allocate ring */
3681 ret = r600_ih_ring_alloc(rdev);
3682 if (ret)
3683 return ret;
3684
3685 /* disable irqs */
3686 r600_disable_interrupts(rdev);
3687
3688 /* init rlc */
3689 if (rdev->family >= CHIP_CEDAR)
3690 ret = evergreen_rlc_resume(rdev);
3691 else
3692 ret = r600_rlc_resume(rdev);
3693 if (ret) {
3694 r600_ih_ring_fini(rdev);
3695 return ret;
3696 }
3697
3698 /* setup interrupt control */
3699 /* set dummy read address to dummy page address */
3700 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8)r100_mm_wreg(rdev, (0x546c), (rdev->dummy_page.addr >>
8), 0);
3701 interrupt_cntl = RREG32(INTERRUPT_CNTL)r100_mm_rreg(rdev, (0x5468), 0);
3702 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3703 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3704 */
3705 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE(1 << 0);
3706 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3707 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN(1 << 3);
3708 WREG32(INTERRUPT_CNTL, interrupt_cntl)r100_mm_wreg(rdev, (0x5468), (interrupt_cntl), 0);
3709
3710 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8)r100_mm_wreg(rdev, (0x3e04), (rdev->ih.gpu_addr >> 8
), 0);
3711 rb_bufsz = order_base_2(rdev->ih.ring_size / 4)drm_order(rdev->ih.ring_size / 4);
3712
3713 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE(1 << 16) |
3714 IH_WPTR_OVERFLOW_CLEAR(1 << 31) |
3715 (rb_bufsz << 1));
3716
3717 if (rdev->wb.enabled)
3718 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE(1 << 8);
3719
3720 /* set the writeback address whether it's enabled or not */
3721 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC)r100_mm_wreg(rdev, (0x3e14), ((rdev->wb.gpu_addr + 2048) &
0xFFFFFFFC), 0);
3722 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF)r100_mm_wreg(rdev, (0x3e10), (((u32)(((rdev->wb.gpu_addr +
2048) >> 16) >> 16)) & 0xFF), 0);
3723
3724 WREG32(IH_RB_CNTL, ih_rb_cntl)r100_mm_wreg(rdev, (0x3e00), (ih_rb_cntl), 0);
3725
3726 /* set rptr, wptr to 0 */
3727 WREG32(IH_RB_RPTR, 0)r100_mm_wreg(rdev, (0x3e08), (0), 0);
3728 WREG32(IH_RB_WPTR, 0)r100_mm_wreg(rdev, (0x3e0c), (0), 0);
3729
3730 /* Default settings for IH_CNTL (disabled at first) */
3731 ih_cntl = MC_WRREQ_CREDIT(0x10)((0x10) << 15) | MC_WR_CLEAN_CNT(0x10)((0x10) << 20);
3732 /* RPTR_REARM only works if msi's are enabled */
3733 if (rdev->msi_enabled)
3734 ih_cntl |= RPTR_REARM(1 << 4);
3735 WREG32(IH_CNTL, ih_cntl)r100_mm_wreg(rdev, (0x3e18), (ih_cntl), 0);
3736
3737 /* force the active interrupt state to all disabled */
3738 if (rdev->family >= CHIP_CEDAR)
3739 evergreen_disable_interrupt_state(rdev);
3740 else
3741 r600_disable_interrupt_state(rdev);
3742
3743 /* at this point everything should be setup correctly to enable master */
3744 pci_set_master(rdev->pdev);
3745
3746 /* enable irqs */
3747 r600_enable_interrupts(rdev);
3748
3749 return ret;
3750}
3751
3752void r600_irq_suspend(struct radeon_device *rdev)
3753{
3754 r600_irq_disable(rdev);
3755 r600_rlc_stop(rdev);
3756}
3757
3758void r600_irq_fini(struct radeon_device *rdev)
3759{
3760 r600_irq_suspend(rdev);
3761 r600_ih_ring_fini(rdev);
3762}
3763
3764int r600_irq_set(struct radeon_device *rdev)
3765{
3766 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE(1 << 19) | CNTX_EMPTY_INT_ENABLE(1 << 20);
3767 u32 mode_int = 0;
3768 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3769 u32 grbm_int_cntl = 0;
3770 u32 hdmi0, hdmi1;
3771 u32 dma_cntl;
3772 u32 thermal_int = 0;
3773
3774 if (!rdev->irq.installed) {
3775 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n")({ int __ret = !!(1); if (__ret) printf("Can't enable IRQ/MSI because no handler is installed\n"
); __builtin_expect(!!(__ret), 0); });
3776 return -EINVAL22;
3777 }
3778 /* don't enable anything if the ih is disabled */
3779 if (!rdev->ih.enabled) {
3780 r600_disable_interrupts(rdev);
3781 /* force the active interrupt state to all disabled */
3782 r600_disable_interrupt_state(rdev);
3783 return 0;
3784 }
3785
3786 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3787 hpd1 = RREG32(DC_HPD1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d04), 0) & ~DC_HPDx_INT_EN(1 << 16);
3788 hpd2 = RREG32(DC_HPD2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d10), 0) & ~DC_HPDx_INT_EN(1 << 16);
3789 hpd3 = RREG32(DC_HPD3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d1c), 0) & ~DC_HPDx_INT_EN(1 << 16);
3790 hpd4 = RREG32(DC_HPD4_INT_CONTROL)r100_mm_rreg(rdev, (0x7d28), 0) & ~DC_HPDx_INT_EN(1 << 16);
3791 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
3792 hpd5 = RREG32(DC_HPD5_INT_CONTROL)r100_mm_rreg(rdev, (0x7dc4), 0) & ~DC_HPDx_INT_EN(1 << 16);
3793 hpd6 = RREG32(DC_HPD6_INT_CONTROL)r100_mm_rreg(rdev, (0x7df8), 0) & ~DC_HPDx_INT_EN(1 << 16);
3794 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0)r100_mm_rreg(rdev, (0x7604 + (0x7400 - 0x7400)), 0) & ~AFMT_AZ_FORMAT_WTRIG_MASK(1 << 28);
3795 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1)r100_mm_rreg(rdev, (0x7604 + (0x7800 - 0x7400)), 0) & ~AFMT_AZ_FORMAT_WTRIG_MASK(1 << 28);
3796 } else {
3797 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7408), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3798 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7808), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3799 }
3800 } else {
3801 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d08), 0) & ~DC_HPDx_INT_EN(1 << 16);
3802 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d18), 0) & ~DC_HPDx_INT_EN(1 << 16);
3803 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d2c), 0) & ~DC_HPDx_INT_EN(1 << 16);
3804 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7408), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3805 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7708), 0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3806 }
3807
3808 dma_cntl = RREG32(DMA_CNTL)r100_mm_rreg(rdev, (0xd02c), 0) & ~TRAP_ENABLE(1 << 0);
3809
3810 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3811 thermal_int = RREG32(CG_THERMAL_INT)r100_mm_rreg(rdev, (0x7F8), 0) &
3812 ~(THERM_INT_MASK_HIGH(1 << 24) | THERM_INT_MASK_LOW(1 << 25));
3813 } else if (rdev->family >= CHIP_RV770) {
3814 thermal_int = RREG32(RV770_CG_THERMAL_INT)r100_mm_rreg(rdev, (0x734), 0) &
3815 ~(THERM_INT_MASK_HIGH(1 << 24) | THERM_INT_MASK_LOW(1 << 25));
3816 }
3817 if (rdev->irq.dpm_thermal) {
3818 DRM_DEBUG("dpm thermal\n")__drm_dbg(DRM_UT_CORE, "dpm thermal\n");
3819 thermal_int |= THERM_INT_MASK_HIGH(1 << 24) | THERM_INT_MASK_LOW(1 << 25);
3820 }
3821
3822 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])({ typeof(*(&rdev->irq.ring_int[0])) __tmp = *(volatile
typeof(*(&rdev->irq.ring_int[0])) *)&(*(&rdev
->irq.ring_int[0])); membar_datadep_consumer(); __tmp; })) {
3823 DRM_DEBUG("r600_irq_set: sw int\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: sw int\n");
3824 cp_int_cntl |= RB_INT_ENABLE(1 << 31);
3825 cp_int_cntl |= TIME_STAMP_INT_ENABLE(1 << 26);
3826 }
3827
3828 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])({ typeof(*(&rdev->irq.ring_int[3])) __tmp = *(volatile
typeof(*(&rdev->irq.ring_int[3])) *)&(*(&rdev
->irq.ring_int[3])); membar_datadep_consumer(); __tmp; })) {
3829 DRM_DEBUG("r600_irq_set: sw int dma\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: sw int dma\n");
3830 dma_cntl |= TRAP_ENABLE(1 << 0);
3831 }
3832
3833 if (rdev->irq.crtc_vblank_int[0] ||
3834 atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; })) {
3835 DRM_DEBUG("r600_irq_set: vblank 0\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: vblank 0\n");
3836 mode_int |= D1MODE_VBLANK_INT_MASK(1 << 0);
3837 }
3838 if (rdev->irq.crtc_vblank_int[1] ||
3839 atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; })) {
3840 DRM_DEBUG("r600_irq_set: vblank 1\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: vblank 1\n");
3841 mode_int |= D2MODE_VBLANK_INT_MASK(1 << 8);
3842 }
3843 if (rdev->irq.hpd[0]) {
3844 DRM_DEBUG("r600_irq_set: hpd 1\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 1\n");
3845 hpd1 |= DC_HPDx_INT_EN(1 << 16);
3846 }
3847 if (rdev->irq.hpd[1]) {
3848 DRM_DEBUG("r600_irq_set: hpd 2\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 2\n");
3849 hpd2 |= DC_HPDx_INT_EN(1 << 16);
3850 }
3851 if (rdev->irq.hpd[2]) {
3852 DRM_DEBUG("r600_irq_set: hpd 3\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 3\n");
3853 hpd3 |= DC_HPDx_INT_EN(1 << 16);
3854 }
3855 if (rdev->irq.hpd[3]) {
3856 DRM_DEBUG("r600_irq_set: hpd 4\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 4\n");
3857 hpd4 |= DC_HPDx_INT_EN(1 << 16);
3858 }
3859 if (rdev->irq.hpd[4]) {
3860 DRM_DEBUG("r600_irq_set: hpd 5\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 5\n");
3861 hpd5 |= DC_HPDx_INT_EN(1 << 16);
3862 }
3863 if (rdev->irq.hpd[5]) {
3864 DRM_DEBUG("r600_irq_set: hpd 6\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hpd 6\n");
3865 hpd6 |= DC_HPDx_INT_EN(1 << 16);
3866 }
3867 if (rdev->irq.afmt[0]) {
3868 DRM_DEBUG("r600_irq_set: hdmi 0\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hdmi 0\n");
3869 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3870 }
3871 if (rdev->irq.afmt[1]) {
3872 DRM_DEBUG("r600_irq_set: hdmi 0\n")__drm_dbg(DRM_UT_CORE, "r600_irq_set: hdmi 0\n");
3873 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK(1 << 28);
3874 }
3875
3876 WREG32(CP_INT_CNTL, cp_int_cntl)r100_mm_wreg(rdev, (0xc124), (cp_int_cntl), 0);
3877 WREG32(DMA_CNTL, dma_cntl)r100_mm_wreg(rdev, (0xd02c), (dma_cntl), 0);
3878 WREG32(DxMODE_INT_MASK, mode_int)r100_mm_wreg(rdev, (0x6540), (mode_int), 0);
3879 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK)r100_mm_wreg(rdev, (0x615c), ((1 << 0)), 0);
3880 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK)r100_mm_wreg(rdev, (0x695c), ((1 << 0)), 0);
3881 WREG32(GRBM_INT_CNTL, grbm_int_cntl)r100_mm_wreg(rdev, (0x8060), (grbm_int_cntl), 0);
3882 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3883 WREG32(DC_HPD1_INT_CONTROL, hpd1)r100_mm_wreg(rdev, (0x7d04), (hpd1), 0);
3884 WREG32(DC_HPD2_INT_CONTROL, hpd2)r100_mm_wreg(rdev, (0x7d10), (hpd2), 0);
3885 WREG32(DC_HPD3_INT_CONTROL, hpd3)r100_mm_wreg(rdev, (0x7d1c), (hpd3), 0);
3886 WREG32(DC_HPD4_INT_CONTROL, hpd4)r100_mm_wreg(rdev, (0x7d28), (hpd4), 0);
3887 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
3888 WREG32(DC_HPD5_INT_CONTROL, hpd5)r100_mm_wreg(rdev, (0x7dc4), (hpd5), 0);
3889 WREG32(DC_HPD6_INT_CONTROL, hpd6)r100_mm_wreg(rdev, (0x7df8), (hpd6), 0);
3890 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0)r100_mm_wreg(rdev, (0x7604 + (0x7400 - 0x7400)), (hdmi0), 0);
3891 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1)r100_mm_wreg(rdev, (0x7604 + (0x7800 - 0x7400)), (hdmi1), 0);
3892 } else {
3893 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0)r100_mm_wreg(rdev, (0x7408), (hdmi0), 0);
3894 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1)r100_mm_wreg(rdev, (0x7808), (hdmi1), 0);
3895 }
3896 } else {
3897 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1)r100_mm_wreg(rdev, (0x7d08), (hpd1), 0);
3898 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2)r100_mm_wreg(rdev, (0x7d18), (hpd2), 0);
3899 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3)r100_mm_wreg(rdev, (0x7d2c), (hpd3), 0);
3900 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0)r100_mm_wreg(rdev, (0x7408), (hdmi0), 0);
3901 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1)r100_mm_wreg(rdev, (0x7708), (hdmi1), 0);
3902 }
3903 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3904 WREG32(CG_THERMAL_INT, thermal_int)r100_mm_wreg(rdev, (0x7F8), (thermal_int), 0);
3905 } else if (rdev->family >= CHIP_RV770) {
3906 WREG32(RV770_CG_THERMAL_INT, thermal_int)r100_mm_wreg(rdev, (0x734), (thermal_int), 0);
3907 }
3908
3909 /* posting read */
3910 RREG32(R_000E50_SRBM_STATUS)r100_mm_rreg(rdev, (0x0E50), 0);
3911
3912 return 0;
3913}
3914
3915static void r600_irq_ack(struct radeon_device *rdev)
3916{
3917 u32 tmp;
3918
3919 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3920 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS)r100_mm_rreg(rdev, (0x7ddc), 0);
3921 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE)r100_mm_rreg(rdev, (0x7de8), 0);
3922 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2)r100_mm_rreg(rdev, (0x7dec), 0);
3923 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0)r100_mm_rreg(rdev, (0x7600 + (0x7400 - 0x7400)), 0);
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1)r100_mm_rreg(rdev, (0x7600 + (0x7800 - 0x7400)), 0);
3926 } else {
3927 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS)r100_mm_rreg(rdev, (0x7404), 0);
3928 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS)r100_mm_rreg(rdev, (0x7804), 0);
3929 }
3930 } else {
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS)r100_mm_rreg(rdev, (0x7edc), 0);
3932 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE)r100_mm_rreg(rdev, (0x7ee8), 0);
3933 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3934 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS)r100_mm_rreg(rdev, (0x7404), 0);
3935 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS)r100_mm_rreg(rdev, (0x7704), 0);
3936 }
3937 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS)r100_mm_rreg(rdev, (0x6158), 0);
3938 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS)r100_mm_rreg(rdev, (0x6958), 0);
3939
3940 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED(1 << 0))
3941 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR)r100_mm_wreg(rdev, (0x6158), ((1 << 8)), 0);
3942 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED(1 << 0))
3943 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR)r100_mm_wreg(rdev, (0x6958), ((1 << 8)), 0);
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT(1 << 4))
3945 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK)r100_mm_wreg(rdev, (0x6534), ((1 << 4)), 0);
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT(1 << 2))
3947 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK)r100_mm_wreg(rdev, (0x653c), ((1 << 4)), 0);
3948 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT(1 << 5))
3949 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK)r100_mm_wreg(rdev, (0x6d34), ((1 << 4)), 0);
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT(1 << 3))
3951 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK)r100_mm_wreg(rdev, (0x6d3c), ((1 << 4)), 0);
3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT(1 << 18)) {
3953 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3954 tmp = RREG32(DC_HPD1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d04), 0);
3955 tmp |= DC_HPDx_INT_ACK(1 << 0);
3956 WREG32(DC_HPD1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d04), (tmp), 0);
3957 } else {
3958 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x7d08), 0);
3959 tmp |= DC_HPDx_INT_ACK(1 << 0);
3960 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d08), (tmp), 0);
3961 }
3962 }
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT(1 << 19)) {
3964 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3965 tmp = RREG32(DC_HPD2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d10), 0);
3966 tmp |= DC_HPDx_INT_ACK(1 << 0);
3967 WREG32(DC_HPD2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d10), (tmp), 0);
3968 } else {
3969 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x7d18), 0);
3970 tmp |= DC_HPDx_INT_ACK(1 << 0);
3971 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d18), (tmp), 0);
3972 }
3973 }
3974 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT(1 << 28)) {
3975 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
3976 tmp = RREG32(DC_HPD3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d1c), 0);
3977 tmp |= DC_HPDx_INT_ACK(1 << 0);
3978 WREG32(DC_HPD3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d1c), (tmp), 0);
3979 } else {
3980 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL)r100_mm_rreg(rdev, (0x7d2c), 0);
3981 tmp |= DC_HPDx_INT_ACK(1 << 0);
3982 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d2c), (tmp), 0);
3983 }
3984 }
3985 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT(1 << 14)) {
3986 tmp = RREG32(DC_HPD4_INT_CONTROL)r100_mm_rreg(rdev, (0x7d28), 0);
3987 tmp |= DC_HPDx_INT_ACK(1 << 0);
3988 WREG32(DC_HPD4_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7d28), (tmp), 0);
3989 }
3990 if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT(1 << 19)) {
3992 tmp = RREG32(DC_HPD5_INT_CONTROL)r100_mm_rreg(rdev, (0x7dc4), 0);
3993 tmp |= DC_HPDx_INT_ACK(1 << 0);
3994 WREG32(DC_HPD5_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7dc4), (tmp), 0);
3995 }
3996 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT(1 << 21)) {
3997 tmp = RREG32(DC_HPD6_INT_CONTROL)r100_mm_rreg(rdev, (0x7df8), 0);
3998 tmp |= DC_HPDx_INT_ACK(1 << 0);
3999 WREG32(DC_HPD6_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x7df8), (tmp), 0);
4000 }
4001 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG(1 << 28)) {
4002 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0)r100_mm_rreg(rdev, (0x7604 + (0x7400 - 0x7400)), 0);
4003 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK(1 << 29);
4004 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp)r100_mm_wreg(rdev, (0x7604 + (0x7400 - 0x7400)), (tmp), 0);
4005 }
4006 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG(1 << 28)) {
4007 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1)r100_mm_rreg(rdev, (0x7604 + (0x7800 - 0x7400)), 0);
4008 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK(1 << 29);
4009 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp)r100_mm_wreg(rdev, (0x7604 + (0x7800 - 0x7400)), (tmp), 0);
4010 }
4011 } else {
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG(1 << 28)) {
4013 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7408), 0);
4014 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK(1 << 29);
4015 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7408), (tmp), 0);
4016 }
4017 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG(1 << 28)) {
4018 if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
4019 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7808), 0);
4020 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK(1 << 29);
4021 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7808), (tmp), 0);
4022 } else {
4023 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x7708), 0);
4024 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK(1 << 29);
4025 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x7708), (tmp), 0);
4026 }
4027 }
4028 }
4029}
4030
4031void r600_irq_disable(struct radeon_device *rdev)
4032{
4033 r600_disable_interrupts(rdev);
4034 /* Wait and acknowledge irq */
4035 mdelay(1);
4036 r600_irq_ack(rdev);
4037 r600_disable_interrupt_state(rdev);
4038}
4039
4040static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4041{
4042 u32 wptr, tmp;
4043
4044 if (rdev->wb.enabled)
4045 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4])((__uint32_t)(rdev->wb.wb[2048/4]));
4046 else
4047 wptr = RREG32(IH_RB_WPTR)r100_mm_rreg(rdev, (0x3e0c), 0);
4048
4049 if (wptr & RB_OVERFLOW(1 << 0)) {
4050 wptr &= ~RB_OVERFLOW(1 << 0);
4051 /* When a ring buffer overflow happen start parsing interrupt
4052 * from the last not overwritten vector (wptr + 16). Hopefully
4053 * this should allow us to catchup.
4054 */
4055 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , wptr, rdev
->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask)
4056 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask)printf("drm:pid%d:%s *WARNING* " "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , wptr, rdev
->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4057 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4058 tmp = RREG32(IH_RB_CNTL)r100_mm_rreg(rdev, (0x3e00), 0);
4059 tmp |= IH_WPTR_OVERFLOW_CLEAR(1 << 31);
4060 WREG32(IH_RB_CNTL, tmp)r100_mm_wreg(rdev, (0x3e00), (tmp), 0);
4061 }
4062 return (wptr & rdev->ih.ptr_mask);
4063}
4064
4065/* r600 IV Ring
4066 * Each IV ring entry is 128 bits:
4067 * [7:0] - interrupt source id
4068 * [31:8] - reserved
4069 * [59:32] - interrupt source data
4070 * [127:60] - reserved
4071 *
4072 * The basic interrupt vector entries
4073 * are decoded as follows:
4074 * src_id src_data description
4075 * 1 0 D1 Vblank
4076 * 1 1 D1 Vline
4077 * 5 0 D2 Vblank
4078 * 5 1 D2 Vline
4079 * 19 0 FP Hot plug detection A
4080 * 19 1 FP Hot plug detection B
4081 * 19 2 DAC A auto-detection
4082 * 19 3 DAC B auto-detection
4083 * 21 4 HDMI block A
4084 * 21 5 HDMI block B
4085 * 176 - CP_INT RB
4086 * 177 - CP_INT IB1
4087 * 178 - CP_INT IB2
4088 * 181 - EOP Interrupt
4089 * 233 - GUI Idle
4090 *
4091 * Note, these are based on r600 and may need to be
4092 * adjusted or added to on newer asics
4093 */
4094
4095int r600_irq_process(struct radeon_device *rdev)
4096{
4097 u32 wptr;
4098 u32 rptr;
4099 u32 src_id, src_data;
4100 u32 ring_index;
4101 bool_Bool queue_hotplug = false0;
4102 bool_Bool queue_hdmi = false0;
4103 bool_Bool queue_thermal = false0;
4104
4105 if (!rdev->ih.enabled || rdev->shutdown)
4106 return IRQ_NONE;
4107
4108 /* No MSIs, need a dummy read to flush PCI DMAs */
4109 if (!rdev->msi_enabled)
4110 RREG32(IH_RB_WPTR)r100_mm_rreg(rdev, (0x3e0c), 0);
4111
4112 wptr = r600_get_ih_wptr(rdev);
4113
4114 if (wptr == rdev->ih.rptr)
4115 return IRQ_NONE;
4116restart_ih:
4117 /* is somebody else already processing irqs? */
4118 if (atomic_xchg(&rdev->ih.lock, 1))
4119 return IRQ_NONE;
4120
4121 rptr = rdev->ih.rptr;
4122 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr)__drm_dbg(DRM_UT_CORE, "r600_irq_process start: rptr %d, wptr %d\n"
, rptr, wptr);
4123
4124 /* Order reading of wptr vs. reading of IH ring data */
4125 rmb()do { __asm volatile("lfence" ::: "memory"); } while (0);
4126
4127 /* display interrupts */
4128 r600_irq_ack(rdev);
4129
4130 while (rptr != wptr) {
4131 /* wptr/rptr are in bytes! */
4132 ring_index = rptr / 4;
4133 src_id = le32_to_cpu(rdev->ih.ring[ring_index])((__uint32_t)(rdev->ih.ring[ring_index])) & 0xff;
4134 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1])((__uint32_t)(rdev->ih.ring[ring_index + 1])) & 0xfffffff;
4135
4136 switch (src_id) {
4137 case 1: /* D1 vblank/vline */
4138 switch (src_data) {
4139 case 0: /* D1 vblank */
4140 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT(1 << 4)))
4141 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: D1 vblank - IH event w/o asserted irq bit?\n"
);
4142
4143 if (rdev->irq.crtc_vblank_int[0]) {
4144 drm_handle_vblank(rdev->ddev, 0);
4145 rdev->pm.vblank_sync = true1;
4146 wake_up(&rdev->irq.vblank_queue);
4147 }
4148 if (atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; }))
4149 radeon_crtc_handle_vblank(rdev, 0);
4150 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT(1 << 4);
4151 DRM_DEBUG("IH: D1 vblank\n")__drm_dbg(DRM_UT_CORE, "IH: D1 vblank\n");
4152
4153 break;
4154 case 1: /* D1 vline */
4155 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT(1 << 2)))
4156 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: D1 vline - IH event w/o asserted irq bit?\n"
);
4157
4158 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT(1 << 2);
4159 DRM_DEBUG("IH: D1 vline\n")__drm_dbg(DRM_UT_CORE, "IH: D1 vline\n");
4160
4161 break;
4162 default:
4163 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data)__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", src_id
, src_data);
4164 break;
4165 }
4166 break;
4167 case 5: /* D2 vblank/vline */
4168 switch (src_data) {
4169 case 0: /* D2 vblank */
4170 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT(1 << 5)))
4171 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: D2 vblank - IH event w/o asserted irq bit?\n"
);
4172
4173 if (rdev->irq.crtc_vblank_int[1]) {
4174 drm_handle_vblank(rdev->ddev, 1);
4175 rdev->pm.vblank_sync = true1;
4176 wake_up(&rdev->irq.vblank_queue);
4177 }
4178 if (atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; }))
4179 radeon_crtc_handle_vblank(rdev, 1);
4180 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT(1 << 5);
4181 DRM_DEBUG("IH: D2 vblank\n")__drm_dbg(DRM_UT_CORE, "IH: D2 vblank\n");
4182
4183 break;
4184 case 1: /* D1 vline */
4185 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT(1 << 3)))
4186 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: D2 vline - IH event w/o asserted irq bit?\n"
);
4187
4188 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT(1 << 3);
4189 DRM_DEBUG("IH: D2 vline\n")__drm_dbg(DRM_UT_CORE, "IH: D2 vline\n");
4190
4191 break;
4192 default:
4193 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data)__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", src_id
, src_data);
4194 break;
4195 }
4196 break;
4197 case 9: /* D1 pflip */
4198 DRM_DEBUG("IH: D1 flip\n")__drm_dbg(DRM_UT_CORE, "IH: D1 flip\n");
4199 if (radeon_use_pflipirq > 0)
4200 radeon_crtc_handle_flip(rdev, 0);
4201 break;
4202 case 11: /* D2 pflip */
4203 DRM_DEBUG("IH: D2 flip\n")__drm_dbg(DRM_UT_CORE, "IH: D2 flip\n");
4204 if (radeon_use_pflipirq > 0)
4205 radeon_crtc_handle_flip(rdev, 1);
4206 break;
4207 case 19: /* HPD/DAC hotplug */
4208 switch (src_data) {
4209 case 0:
4210 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT(1 << 18)))
4211 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD1 - IH event w/o asserted irq bit?\n"
);
4212
4213 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT(1 << 18);
4214 queue_hotplug = true1;
4215 DRM_DEBUG("IH: HPD1\n")__drm_dbg(DRM_UT_CORE, "IH: HPD1\n");
4216 break;
4217 case 1:
4218 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT(1 << 19)))
4219 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD2 - IH event w/o asserted irq bit?\n"
);
4220
4221 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT(1 << 19);
4222 queue_hotplug = true1;
4223 DRM_DEBUG("IH: HPD2\n")__drm_dbg(DRM_UT_CORE, "IH: HPD2\n");
4224 break;
4225 case 4:
4226 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT(1 << 28)))
4227 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD3 - IH event w/o asserted irq bit?\n"
);
4228
4229 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT(1 << 28);
4230 queue_hotplug = true1;
4231 DRM_DEBUG("IH: HPD3\n")__drm_dbg(DRM_UT_CORE, "IH: HPD3\n");
4232 break;
4233 case 5:
4234 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT(1 << 14)))
4235 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD4 - IH event w/o asserted irq bit?\n"
);
4236
4237 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT(1 << 14);
4238 queue_hotplug = true1;
4239 DRM_DEBUG("IH: HPD4\n")__drm_dbg(DRM_UT_CORE, "IH: HPD4\n");
4240 break;
4241 case 10:
4242 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT(1 << 19)))
4243 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD5 - IH event w/o asserted irq bit?\n"
);
4244
4245 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT(1 << 19);
4246 queue_hotplug = true1;
4247 DRM_DEBUG("IH: HPD5\n")__drm_dbg(DRM_UT_CORE, "IH: HPD5\n");
4248 break;
4249 case 12:
4250 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT(1 << 21)))
4251 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HPD6 - IH event w/o asserted irq bit?\n"
);
4252
4253 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT(1 << 21);
4254 queue_hotplug = true1;
4255 DRM_DEBUG("IH: HPD6\n")__drm_dbg(DRM_UT_CORE, "IH: HPD6\n");
4256
4257 break;
4258 default:
4259 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data)__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", src_id
, src_data);
4260 break;
4261 }
4262 break;
4263 case 21: /* hdmi */
4264 switch (src_data) {
4265 case 4:
4266 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG(1 << 28)))
4267 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HDMI0 - IH event w/o asserted irq bit?\n"
);
4268
4269 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG(1 << 28);
4270 queue_hdmi = true1;
4271 DRM_DEBUG("IH: HDMI0\n")__drm_dbg(DRM_UT_CORE, "IH: HDMI0\n");
4272
4273 break;
4274 case 5:
4275 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG(1 << 28)))
4276 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: HDMI1 - IH event w/o asserted irq bit?\n"
);
4277
4278 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG(1 << 28);
4279 queue_hdmi = true1;
4280 DRM_DEBUG("IH: HDMI1\n")__drm_dbg(DRM_UT_CORE, "IH: HDMI1\n");
4281
4282 break;
4283 default:
4284 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data)__drm_err("Unhandled interrupt: %d %d\n", src_id, src_data);
4285 break;
4286 }
4287 break;
4288 case 124: /* UVD */
4289 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data)__drm_dbg(DRM_UT_CORE, "IH: UVD int: 0x%08x\n", src_data);
4290 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX5);
4291 break;
4292 case 176: /* CP_INT in ring buffer */
4293 case 177: /* CP_INT in IB1 */
4294 case 178: /* CP_INT in IB2 */
4295 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data)__drm_dbg(DRM_UT_CORE, "IH: CP int: 0x%08x\n", src_data);
4296 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX0);
4297 break;
4298 case 181: /* CP EOP event */
4299 DRM_DEBUG("IH: CP EOP\n")__drm_dbg(DRM_UT_CORE, "IH: CP EOP\n");
4300 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX0);
4301 break;
4302 case 224: /* DMA trap event */
4303 DRM_DEBUG("IH: DMA trap\n")__drm_dbg(DRM_UT_CORE, "IH: DMA trap\n");
4304 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX3);
4305 break;
4306 case 230: /* thermal low to high */
4307 DRM_DEBUG("IH: thermal low to high\n")__drm_dbg(DRM_UT_CORE, "IH: thermal low to high\n");
4308 rdev->pm.dpm.thermal.high_to_low = false0;
4309 queue_thermal = true1;
4310 break;
4311 case 231: /* thermal high to low */
4312 DRM_DEBUG("IH: thermal high to low\n")__drm_dbg(DRM_UT_CORE, "IH: thermal high to low\n");
4313 rdev->pm.dpm.thermal.high_to_low = true1;
4314 queue_thermal = true1;
4315 break;
4316 case 233: /* GUI IDLE */
4317 DRM_DEBUG("IH: GUI idle\n")__drm_dbg(DRM_UT_CORE, "IH: GUI idle\n");
4318 break;
4319 default:
4320 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data)__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", src_id
, src_data);
4321 break;
4322 }
4323
4324 /* wptr/rptr are in bytes! */
4325 rptr += 16;
4326 rptr &= rdev->ih.ptr_mask;
4327 WREG32(IH_RB_RPTR, rptr)r100_mm_wreg(rdev, (0x3e08), (rptr), 0);
4328 }
4329 if (queue_hotplug)
4330 schedule_delayed_work(&rdev->hotplug_work, 0);
4331 if (queue_hdmi)
4332 schedule_work(&rdev->audio_work);
4333 if (queue_thermal && rdev->pm.dpm_enabled)
4334 schedule_work(&rdev->pm.dpm.thermal.work);
4335 rdev->ih.rptr = rptr;
4336 atomic_set(&rdev->ih.lock, 0)({ typeof(*(&rdev->ih.lock)) __tmp = ((0)); *(volatile
typeof(*(&rdev->ih.lock)) *)&(*(&rdev->ih.
lock)) = __tmp; __tmp; });
4337
4338 /* make sure wptr hasn't changed while processing */
4339 wptr = r600_get_ih_wptr(rdev);
4340 if (wptr != rptr)
4341 goto restart_ih;
4342
4343 return IRQ_HANDLED;
4344}
4345
4346/*
4347 * Debugfs info
4348 */
4349#if defined(CONFIG_DEBUG_FS)
4350
4351static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4352{
4353 struct drm_info_node *node = (struct drm_info_node *) m->private;
4354 struct drm_device *dev = node->minor->dev;
4355 struct radeon_device *rdev = dev->dev_private;
4356
4357 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS)seq_printf((m), "R_000E50_SRBM_STATUS" " : 0x%08X\n", r100_mm_rreg
((rdev), (0x0E50), 0));
4358 DREG32_SYS(m, rdev, VM_L2_STATUS)seq_printf((m), "VM_L2_STATUS" " : 0x%08X\n", r100_mm_rreg((rdev
), (0x140C), 0));
4359 return 0;
4360}
4361
4362static struct drm_info_list r600_mc_info_list[] = {
4363 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL((void *)0)},
4364};
4365#endif
4366
4367int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4368{
4369#if defined(CONFIG_DEBUG_FS)
4370 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)(sizeof((r600_mc_info_list)) / sizeof((r600_mc_info_list)[0])
));
4371#else
4372 return 0;
2
←
Returning without writing to 'rdev->family', which participates in a condition later
→
3
←
Returning without writing to 'rdev->smc_fw'
→
4373#endif
4374}
4375
4376/**
4377 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4378 * rdev: radeon device structure
4379 *
4380 * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4381 * through the ring buffer. This leads to corruption in rendering, see
4382 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4383 * directly perform the HDP flush by writing the register through MMIO.
4384 */
4385void r600_mmio_hdp_flush(struct radeon_device *rdev)
4386{
4387 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4388 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4389 * This seems to cause problems on some AGP cards. Just use the old
4390 * method for them.
4391 */
4392 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4393 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4394 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4395 u32 tmp;
4396
4397 WREG32(HDP_DEBUG1, 0)r100_mm_wreg(rdev, (0x2F34), (0), 0);
4398 tmp = readl((void __iomem *)ptr)ioread32((void *)ptr);
4399 } else
4400 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1)r100_mm_wreg(rdev, (0x5480), (0x1), 0);
4401}
4402
4403void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4404{
4405 u32 link_width_cntl, mask;
4406
4407 if (rdev->flags & RADEON_IS_IGP)
4408 return;
4409
4410 if (!(rdev->flags & RADEON_IS_PCIE))
4411 return;
4412
4413 /* x2 cards have a special sequence */
4414 if (ASIC_IS_X2(rdev)((rdev->ddev->pdev->device == 0x9441) || (rdev->ddev
->pdev->device == 0x9443) || (rdev->ddev->pdev->
device == 0x944B) || (rdev->ddev->pdev->device == 0x9506
) || (rdev->ddev->pdev->device == 0x9509) || (rdev->
ddev->pdev->device == 0x950F) || (rdev->ddev->pdev
->device == 0x689C) || (rdev->ddev->pdev->device ==
0x689D)))
4415 return;
4416
4417 radeon_gui_idle(rdev)(rdev)->asic->gui_idle((rdev));
4418
4419 switch (lanes) {
4420 case 0:
4421 mask = RADEON_PCIE_LC_LINK_WIDTH_X00;
4422 break;
4423 case 1:
4424 mask = RADEON_PCIE_LC_LINK_WIDTH_X11;
4425 break;
4426 case 2:
4427 mask = RADEON_PCIE_LC_LINK_WIDTH_X22;
4428 break;
4429 case 4:
4430 mask = RADEON_PCIE_LC_LINK_WIDTH_X43;
4431 break;
4432 case 8:
4433 mask = RADEON_PCIE_LC_LINK_WIDTH_X84;
4434 break;
4435 case 12:
4436 /* not actually supported */
4437 mask = RADEON_PCIE_LC_LINK_WIDTH_X125;
4438 break;
4439 case 16:
4440 mask = RADEON_PCIE_LC_LINK_WIDTH_X166;
4441 break;
4442 default:
4443 DRM_ERROR("invalid pcie lane request: %d\n", lanes)__drm_err("invalid pcie lane request: %d\n", lanes);
4444 return;
4445 }
4446
4447 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL)rdev->pciep_rreg(rdev, (0xa2));
4448 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK0x7;
4449 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT0;
4450 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW(1 << 8) |
4451 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE(1 << 7));
4452
4453 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl)rdev->pciep_wreg(rdev, (0xa2), (link_width_cntl));
4454}
4455
4456int r600_get_pcie_lanes(struct radeon_device *rdev)
4457{
4458 u32 link_width_cntl;
4459
4460 if (rdev->flags & RADEON_IS_IGP)
4461 return 0;
4462
4463 if (!(rdev->flags & RADEON_IS_PCIE))
4464 return 0;
4465
4466 /* x2 cards have a special sequence */
4467 if (ASIC_IS_X2(rdev)((rdev->ddev->pdev->device == 0x9441) || (rdev->ddev
->pdev->device == 0x9443) || (rdev->ddev->pdev->
device == 0x944B) || (rdev->ddev->pdev->device == 0x9506
) || (rdev->ddev->pdev->device == 0x9509) || (rdev->
ddev->pdev->device == 0x950F) || (rdev->ddev->pdev
->device == 0x689C) || (rdev->ddev->pdev->device ==
0x689D)))
4468 return 0;
4469
4470 radeon_gui_idle(rdev)(rdev)->asic->gui_idle((rdev));
4471
4472 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL)rdev->pciep_rreg(rdev, (0xa2));
4473
4474 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK0x70) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT4) {
4475 case RADEON_PCIE_LC_LINK_WIDTH_X11:
4476 return 1;
4477 case RADEON_PCIE_LC_LINK_WIDTH_X22:
4478 return 2;
4479 case RADEON_PCIE_LC_LINK_WIDTH_X43:
4480 return 4;
4481 case RADEON_PCIE_LC_LINK_WIDTH_X84:
4482 return 8;
4483 case RADEON_PCIE_LC_LINK_WIDTH_X125:
4484 /* not actually supported */
4485 return 12;
4486 case RADEON_PCIE_LC_LINK_WIDTH_X00:
4487 case RADEON_PCIE_LC_LINK_WIDTH_X166:
4488 default:
4489 return 16;
4490 }
4491}
4492
4493static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4494{
4495 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4496 u16 link_cntl2;
4497 enum pci_bus_speed max_bus_speed;
4498
4499 if (radeon_pcie_gen2 == 0)
4500 return;
4501
4502 if (rdev->flags & RADEON_IS_IGP)
4503 return;
4504
4505 if (!(rdev->flags & RADEON_IS_PCIE))
4506 return;
4507
4508 /* x2 cards have a special sequence */
4509 if (ASIC_IS_X2(rdev)((rdev->ddev->pdev->device == 0x9441) || (rdev->ddev
->pdev->device == 0x9443) || (rdev->ddev->pdev->
device == 0x944B) || (rdev->ddev->pdev->device == 0x9506
) || (rdev->ddev->pdev->device == 0x9509) || (rdev->
ddev->pdev->device == 0x950F) || (rdev->ddev->pdev
->device == 0x689C) || (rdev->ddev->pdev->device ==
0x689D)))
4510 return;
4511
4512 /* only RV6xx+ chips are supported */
4513 if (rdev->family <= CHIP_R600)
4514 return;
4515
4516 max_bus_speed = pcie_get_speed_cap(rdev->pdev->bus->self);
4517 if ((max_bus_speed != PCIE_SPEED_5_0GT) &&
4518 (max_bus_speed != PCIE_SPEED_8_0GT))
4519 return;
4520
4521 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL)rdev->pciep_rreg(rdev, (0xa4));
4522 if (speed_cntl & LC_CURRENT_DATA_RATE(1 << 11)) {
4523 DRM_INFO("PCIE gen 2 link speeds already enabled\n")printk("\0016" "[" "drm" "] " "PCIE gen 2 link speeds already enabled\n"
);
4524 return;
4525 }
4526
4527 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n")printk("\0016" "[" "drm" "] " "enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"
);
4528
4529 /* 55 nm r6xx asics */
4530 if ((rdev->family == CHIP_RV670) ||
4531 (rdev->family == CHIP_RV620) ||
4532 (rdev->family == CHIP_RV635)) {
4533 /* advertise upconfig capability */
4534 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL)rdev->pciep_rreg(rdev, (0xa2));
4535 link_width_cntl &= ~LC_UPCONFIGURE_DIS(1 << 13);
4536 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl)rdev->pciep_wreg(rdev, (0xa2), (link_width_cntl));
4537 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL)rdev->pciep_rreg(rdev, (0xa2));
4538 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT(1 << 9)) {
4539 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK0x70) >> LC_LINK_WIDTH_RD_SHIFT4;
4540 link_width_cntl &= ~(LC_LINK_WIDTH_MASK0x7 |
4541 LC_RECONFIG_ARC_MISSING_ESCAPE(1 << 7));
4542 link_width_cntl |= lanes | LC_RECONFIG_NOW(1 << 8) | LC_RENEGOTIATE_EN(1 << 10);
4543 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl)rdev->pciep_wreg(rdev, (0xa2), (link_width_cntl));
4544 } else {
4545 link_width_cntl |= LC_UPCONFIGURE_DIS(1 << 13);
4546 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl)rdev->pciep_wreg(rdev, (0xa2), (link_width_cntl));
4547 }
4548 }
4549
4550 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL)rdev->pciep_rreg(rdev, (0xa4));
4551 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2(1 << 23)) &&
4552 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2(1 << 24))) {
4553
4554 /* 55 nm r6xx asics */
4555 if ((rdev->family == CHIP_RV670) ||
4556 (rdev->family == CHIP_RV620) ||
4557 (rdev->family == CHIP_RV635)) {
4558 WREG32(MM_CFGREGS_CNTL, 0x8)r100_mm_wreg(rdev, (0x544c), (0x8), 0);
4559 link_cntl2 = RREG32(0x4088)r100_mm_rreg(rdev, (0x4088), 0);
4560 WREG32(MM_CFGREGS_CNTL, 0)r100_mm_wreg(rdev, (0x544c), (0), 0);
4561 /* not supported yet */
4562 if (link_cntl2 & SELECTABLE_DEEMPHASIS(1 << 6))
4563 return;
4564 }
4565
4566 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK(0x3 << 8);
4567 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT3);
4568 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK(0xf << 14);
4569 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE(1 << 6);
4570 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE(1 << 5);
4571 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl)rdev->pciep_wreg(rdev, (0xa4), (speed_cntl));
4572
4573 tmp = RREG32(0x541c)r100_mm_rreg(rdev, (0x541c), 0);
4574 WREG32(0x541c, tmp | 0x8)r100_mm_wreg(rdev, (0x541c), (tmp | 0x8), 0);
4575 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN)r100_mm_wreg(rdev, (0x544c), ((1 << 3)), 0);
4576 link_cntl2 = RREG16(0x4088)ioread16((rdev->rmmio) + (0x4088));
4577 link_cntl2 &= ~TARGET_LINK_SPEED_MASK(0xf << 0);
4578 link_cntl2 |= 0x2;
4579 WREG16(0x4088, link_cntl2)iowrite16(link_cntl2, (rdev->rmmio) + (0x4088));
4580 WREG32(MM_CFGREGS_CNTL, 0)r100_mm_wreg(rdev, (0x544c), (0), 0);
4581
4582 if ((rdev->family == CHIP_RV670) ||
4583 (rdev->family == CHIP_RV620) ||
4584 (rdev->family == CHIP_RV635)) {
4585 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL)rdev->pciep_rreg(rdev, (0xa1));
4586 training_cntl &= ~LC_POINT_7_PLUS_EN(1 << 6);
4587 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl)rdev->pciep_wreg(rdev, (0xa1), (training_cntl));
4588 } else {
4589 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL)rdev->pciep_rreg(rdev, (0xa4));
4590 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN(1 << 1);
4591 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl)rdev->pciep_wreg(rdev, (0xa4), (speed_cntl));
4592 }
4593
4594 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL)rdev->pciep_rreg(rdev, (0xa4));
4595 speed_cntl |= LC_GEN2_EN_STRAP(1 << 0);
4596 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl)rdev->pciep_wreg(rdev, (0xa4), (speed_cntl));
4597
4598 } else {
4599 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL)rdev->pciep_rreg(rdev, (0xa2));
4600 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4601 if (1)
4602 link_width_cntl |= LC_UPCONFIGURE_DIS(1 << 13);
4603 else
4604 link_width_cntl &= ~LC_UPCONFIGURE_DIS(1 << 13);
4605 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl)rdev->pciep_wreg(rdev, (0xa2), (link_width_cntl));
4606 }
4607}
4608
4609/**
4610 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4611 *
4612 * @rdev: radeon_device pointer
4613 *
4614 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4615 * Returns the 64 bit clock counter snapshot.
4616 */
4617uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4618{
4619 uint64_t clock;
4620
4621 mutex_lock(&rdev->gpu_clock_mutex)rw_enter_write(&rdev->gpu_clock_mutex);
4622 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1)r100_mm_wreg(rdev, (0x3f40), (1), 0);
4623 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB)r100_mm_rreg(rdev, (0x3f38), 0) |
4624 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB)r100_mm_rreg(rdev, (0x3f3c), 0) << 32ULL);
4625 mutex_unlock(&rdev->gpu_clock_mutex)rw_exit_write(&rdev->gpu_clock_mutex);
4626 return clock;
4627}
←

/usr/src/sys/dev/pci/drm/radeon/radeon.h

→
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/dma-fence.h>
70
71#ifdef CONFIG_MMU_NOTIFIER
72#include <linux/mmu_notifier.h>
73#endif
74
75#include <drm/ttm/ttm_bo_api.h>
76#include <drm/ttm/ttm_bo_driver.h>
77#include <drm/ttm/ttm_placement.h>
78#include <drm/ttm/ttm_module.h>
79#include <drm/ttm/ttm_execbuf_util.h>
80
81#include <drm/drm_gem.h>
82#include <drm/drm_legacy.h>
83
84#include <dev/wscons/wsconsio.h>
85#include <dev/wscons/wsdisplayvar.h>
86#include <dev/rasops/rasops.h>
87
88#include <dev/pci/pcivar.h>
89
90#ifdef __sparc64__
91#include <machine/fbvar.h>
92#endif
93
94#include "radeon_family.h"
95#include "radeon_mode.h"
96#include "radeon_reg.h"
97
98/*
99 * Modules parameters.
100 */
101extern int radeon_no_wb;
102extern int radeon_modeset;
103extern int radeon_dynclks;
104extern int radeon_r4xx_atom;
105extern int radeon_agpmode;
106extern int radeon_vram_limit;
107extern int radeon_gart_size;
108extern int radeon_benchmarking;
109extern int radeon_testing;
110extern int radeon_connector_table;
111extern int radeon_tv;
112extern int radeon_audio;
113extern int radeon_disp_priority;
114extern int radeon_hw_i2c;
115extern int radeon_pcie_gen2;
116extern int radeon_msi;
117extern int radeon_lockup_timeout;
118extern int radeon_fastfb;
119extern int radeon_dpm;
120extern int radeon_aspm;
121extern int radeon_runtime_pm;
122extern int radeon_hard_reset;
123extern int radeon_vm_size;
124extern int radeon_vm_block_size;
125extern int radeon_deep_color;
126extern int radeon_use_pflipirq;
127extern int radeon_bapm;
128extern int radeon_backlight;
129extern int radeon_auxch;
130extern int radeon_mst;
131extern int radeon_uvd;
132extern int radeon_vce;
133extern int radeon_si_support;
134extern int radeon_cik_support;
135
136/*
137 * Copy from radeon_drv.h so we don't have to include both and have conflicting
138 * symbol;
139 */
140#define RADEON_MAX_USEC_TIMEOUT100000 100000 /* 100 ms */
141#define RADEON_FENCE_JIFFIES_TIMEOUT(hz / 2) (HZhz / 2)
142#define RADEON_USEC_IB_TEST_TIMEOUT1000000 1000000 /* 1s */
143/* RADEON_IB_POOL_SIZE must be a power of 2 */
144#define RADEON_IB_POOL_SIZE16 16
145#define RADEON_DEBUGFS_MAX_COMPONENTS32 32
146#define RADEONFB_CONN_LIMIT4 4
147#define RADEON_BIOS_NUM_SCRATCH8 8
148
149/* internal ring indices */
150/* r1xx+ has gfx CP ring */
151#define RADEON_RING_TYPE_GFX_INDEX0 0
152
153/* cayman has 2 compute CP rings */
154#define CAYMAN_RING_TYPE_CP1_INDEX1 1
155#define CAYMAN_RING_TYPE_CP2_INDEX2 2
156
157/* R600+ has an async dma ring */
158#define R600_RING_TYPE_DMA_INDEX3 3
159/* cayman add a second async dma ring */
160#define CAYMAN_RING_TYPE_DMA1_INDEX4 4
161
162/* R600+ */
163#define R600_RING_TYPE_UVD_INDEX5 5
164
165/* TN+ */
166#define TN_RING_TYPE_VCE1_INDEX6 6
167#define TN_RING_TYPE_VCE2_INDEX7 7
168
169/* max number of rings */
170#define RADEON_NUM_RINGS8 8
171
172/* number of hw syncs before falling back on blocking */
173#define RADEON_NUM_SYNCS4 4
174
175/* hardcode those limit for now */
176#define RADEON_VA_IB_OFFSET(1 << 20) (1 << 20)
177#define RADEON_VA_RESERVED_SIZE(8 << 20) (8 << 20)
178#define RADEON_IB_VM_MAX_SIZE(64 << 10) (64 << 10)
179
180/* hard reset data */
181#define RADEON_ASIC_RESET_DATA0x39d5e86b 0x39d5e86b
182
183/* reset flags */
184#define RADEON_RESET_GFX(1 << 0) (1 << 0)
185#define RADEON_RESET_COMPUTE(1 << 1) (1 << 1)
186#define RADEON_RESET_DMA(1 << 2) (1 << 2)
187#define RADEON_RESET_CP(1 << 3) (1 << 3)
188#define RADEON_RESET_GRBM(1 << 4) (1 << 4)
189#define RADEON_RESET_DMA1(1 << 5) (1 << 5)
190#define RADEON_RESET_RLC(1 << 6) (1 << 6)
191#define RADEON_RESET_SEM(1 << 7) (1 << 7)
192#define RADEON_RESET_IH(1 << 8) (1 << 8)
193#define RADEON_RESET_VMC(1 << 9) (1 << 9)
194#define RADEON_RESET_MC(1 << 10) (1 << 10)
195#define RADEON_RESET_DISPLAY(1 << 11) (1 << 11)
196
197/* CG block flags */
198#define RADEON_CG_BLOCK_GFX(1 << 0) (1 << 0)
199#define RADEON_CG_BLOCK_MC(1 << 1) (1 << 1)
200#define RADEON_CG_BLOCK_SDMA(1 << 2) (1 << 2)
201#define RADEON_CG_BLOCK_UVD(1 << 3) (1 << 3)
202#define RADEON_CG_BLOCK_VCE(1 << 4) (1 << 4)
203#define RADEON_CG_BLOCK_HDP(1 << 5) (1 << 5)
204#define RADEON_CG_BLOCK_BIF(1 << 6) (1 << 6)
205
206/* CG flags */
207#define RADEON_CG_SUPPORT_GFX_MGCG(1 << 0) (1 << 0)
208#define RADEON_CG_SUPPORT_GFX_MGLS(1 << 1) (1 << 1)
209#define RADEON_CG_SUPPORT_GFX_CGCG(1 << 2) (1 << 2)
210#define RADEON_CG_SUPPORT_GFX_CGLS(1 << 3) (1 << 3)
211#define RADEON_CG_SUPPORT_GFX_CGTS(1 << 4) (1 << 4)
212#define RADEON_CG_SUPPORT_GFX_CGTS_LS(1 << 5) (1 << 5)
213#define RADEON_CG_SUPPORT_GFX_CP_LS(1 << 6) (1 << 6)
214#define RADEON_CG_SUPPORT_GFX_RLC_LS(1 << 7) (1 << 7)
215#define RADEON_CG_SUPPORT_MC_LS(1 << 8) (1 << 8)
216#define RADEON_CG_SUPPORT_MC_MGCG(1 << 9) (1 << 9)
217#define RADEON_CG_SUPPORT_SDMA_LS(1 << 10) (1 << 10)
218#define RADEON_CG_SUPPORT_SDMA_MGCG(1 << 11) (1 << 11)
219#define RADEON_CG_SUPPORT_BIF_LS(1 << 12) (1 << 12)
220#define RADEON_CG_SUPPORT_UVD_MGCG(1 << 13) (1 << 13)
221#define RADEON_CG_SUPPORT_VCE_MGCG(1 << 14) (1 << 14)
222#define RADEON_CG_SUPPORT_HDP_LS(1 << 15) (1 << 15)
223#define RADEON_CG_SUPPORT_HDP_MGCG(1 << 16) (1 << 16)
224
225/* PG flags */
226#define RADEON_PG_SUPPORT_GFX_PG(1 << 0) (1 << 0)
227#define RADEON_PG_SUPPORT_GFX_SMG(1 << 1) (1 << 1)
228#define RADEON_PG_SUPPORT_GFX_DMG(1 << 2) (1 << 2)
229#define RADEON_PG_SUPPORT_UVD(1 << 3) (1 << 3)
230#define RADEON_PG_SUPPORT_VCE(1 << 4) (1 << 4)
231#define RADEON_PG_SUPPORT_CP(1 << 5) (1 << 5)
232#define RADEON_PG_SUPPORT_GDS(1 << 6) (1 << 6)
233#define RADEON_PG_SUPPORT_RLC_SMU_HS(1 << 7) (1 << 7)
234#define RADEON_PG_SUPPORT_SDMA(1 << 8) (1 << 8)
235#define RADEON_PG_SUPPORT_ACP(1 << 9) (1 << 9)
236#define RADEON_PG_SUPPORT_SAMU(1 << 10) (1 << 10)
237
238/* max cursor sizes (in pixels) */
239#define CURSOR_WIDTH64 64
240#define CURSOR_HEIGHT64 64
241
242#define CIK_CURSOR_WIDTH128 128
243#define CIK_CURSOR_HEIGHT128 128
244
245/*
246 * Errata workarounds.
247 */
248enum radeon_pll_errata {
249 CHIP_ERRATA_R300_CG = 0x00000001,
250 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
251 CHIP_ERRATA_PLL_DELAY = 0x00000004
252};
253
254
255struct radeon_device;
256
257
258/*
259 * BIOS.
260 */
261bool_Bool radeon_get_bios(struct radeon_device *rdev);
262
263/*
264 * Dummy page
265 */
266struct radeon_dummy_page {
267 uint64_t entry;
268 struct drm_dmamem *dmah;
269 dma_addr_t addr;
270};
271int radeon_dummy_page_init(struct radeon_device *rdev);
272void radeon_dummy_page_fini(struct radeon_device *rdev);
273
274
275/*
276 * Clocks
277 */
278struct radeon_clock {
279 struct radeon_pll p1pll;
280 struct radeon_pll p2pll;
281 struct radeon_pll dcpll;
282 struct radeon_pll spll;
283 struct radeon_pll mpll;
284 /* 10 Khz units */
285 uint32_t default_mclk;
286 uint32_t default_sclk;
287 uint32_t default_dispclk;
288 uint32_t current_dispclk;
289 uint32_t dp_extclk;
290 uint32_t max_pixel_clock;
291 uint32_t vco_freq;
292};
293
294/*
295 * Power management
296 */
297int radeon_pm_init(struct radeon_device *rdev);
298int radeon_pm_late_init(struct radeon_device *rdev);
299void radeon_pm_fini(struct radeon_device *rdev);
300void radeon_pm_compute_clocks(struct radeon_device *rdev);
301void radeon_pm_suspend(struct radeon_device *rdev);
302void radeon_pm_resume(struct radeon_device *rdev);
303void radeon_combios_get_power_modes(struct radeon_device *rdev);
304void radeon_atombios_get_power_modes(struct radeon_device *rdev);
305int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
306 u8 clock_type,
307 u32 clock,
308 bool_Bool strobe_mode,
309 struct atom_clock_dividers *dividers);
310int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
311 u32 clock,
312 bool_Bool strobe_mode,
313 struct atom_mpll_param *mpll_param);
314void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
315int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
316 u16 voltage_level, u8 voltage_type,
317 u32 *gpio_value, u32 *gpio_mask);
318void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
319 u32 eng_clock, u32 mem_clock);
320int radeon_atom_get_voltage_step(struct radeon_device *rdev,
321 u8 voltage_type, u16 *voltage_step);
322int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
323 u16 voltage_id, u16 *voltage);
324int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
325 u16 *voltage,
326 u16 leakage_idx);
327int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
328 u16 *leakage_id);
329int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
330 u16 *vddc, u16 *vddci,
331 u16 virtual_voltage_id,
332 u16 vbios_voltage_id);
333int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
334 u16 virtual_voltage_id,
335 u16 *voltage);
336int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
337 u8 voltage_type,
338 u16 nominal_voltage,
339 u16 *true_voltage);
340int radeon_atom_get_min_voltage(struct radeon_device *rdev,
341 u8 voltage_type, u16 *min_voltage);
342int radeon_atom_get_max_voltage(struct radeon_device *rdev,
343 u8 voltage_type, u16 *max_voltage);
344int radeon_atom_get_voltage_table(struct radeon_device *rdev,
345 u8 voltage_type, u8 voltage_mode,
346 struct atom_voltage_table *voltage_table);
347bool_Bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
348 u8 voltage_type, u8 voltage_mode);
349int radeon_atom_get_svi2_info(struct radeon_device *rdev,
350 u8 voltage_type,
351 u8 *svd_gpio_id, u8 *svc_gpio_id);
352void radeon_atom_update_memory_dll(struct radeon_device *rdev,
353 u32 mem_clock);
354void radeon_atom_set_ac_timing(struct radeon_device *rdev,
355 u32 mem_clock);
356int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
357 u8 module_index,
358 struct atom_mc_reg_table *reg_table);
359int radeon_atom_get_memory_info(struct radeon_device *rdev,
360 u8 module_index, struct atom_memory_info *mem_info);
361int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
362 bool_Bool gddr5, u8 module_index,
363 struct atom_memory_clock_range_table *mclk_range_table);
364int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
365 u16 voltage_id, u16 *voltage);
366void rs690_pm_info(struct radeon_device *rdev);
367extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
368 unsigned *bankh, unsigned *mtaspect,
369 unsigned *tile_split);
370
371/*
372 * Fences.
373 */
374struct radeon_fence_driver {
375 struct radeon_device *rdev;
376 uint32_t scratch_reg;
377 uint64_t gpu_addr;
378 volatile uint32_t *cpu_addr;
379 /* sync_seq is protected by ring emission lock */
380 uint64_t sync_seq[RADEON_NUM_RINGS8];
381 atomic64_t last_seq;
382 bool_Bool initialized, delayed_irq;
383 struct delayed_work lockup_work;
384};
385
386struct radeon_fence {
387 struct dma_fence base;
388
389 struct radeon_device *rdev;
390 uint64_t seq;
391 /* RB, DMA, etc. */
392 unsigned ring;
393 bool_Bool is_vm_update;
394
395 wait_queue_entry_t fence_wake;
396};
397
398int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
399int radeon_fence_driver_init(struct radeon_device *rdev);
400void radeon_fence_driver_fini(struct radeon_device *rdev);
401void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
402int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
403void radeon_fence_process(struct radeon_device *rdev, int ring);
404bool_Bool radeon_fence_signaled(struct radeon_fence *fence);
405long radeon_fence_wait_timeout(struct radeon_fence *fence, bool_Bool interruptible, long timeout);
406int radeon_fence_wait(struct radeon_fence *fence, bool_Bool interruptible);
407int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
408int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
409int radeon_fence_wait_any(struct radeon_device *rdev,
410 struct radeon_fence **fences,
411 bool_Bool intr);
412struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
413void radeon_fence_unref(struct radeon_fence **fence);
414unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
415bool_Bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
416void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
417static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
418 struct radeon_fence *b)
419{
420 if (!a) {
421 return b;
422 }
423
424 if (!b) {
425 return a;
426 }
427
428 BUG_ON(a->ring != b->ring)((!(a->ring != b->ring)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/radeon/radeon.h", 428, "!(a->ring != b->ring)"
));
429
430 if (a->seq > b->seq) {
431 return a;
432 } else {
433 return b;
434 }
435}
436
437static inline bool_Bool radeon_fence_is_earlier(struct radeon_fence *a,
438 struct radeon_fence *b)
439{
440 if (!a) {
441 return false0;
442 }
443
444 if (!b) {
445 return true1;
446 }
447
448 BUG_ON(a->ring != b->ring)((!(a->ring != b->ring)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/radeon/radeon.h", 448, "!(a->ring != b->ring)"
));
449
450 return a->seq < b->seq;
451}
452
453/*
454 * Tiling registers
455 */
456struct radeon_surface_reg {
457 struct radeon_bo *bo;
458};
459
460#define RADEON_GEM_MAX_SURFACES8 8
461
462/*
463 * TTM.
464 */
465struct radeon_mman {
466 struct ttm_bo_device bdev;
467 bool_Bool initialized;
468
469#if defined(CONFIG_DEBUG_FS)
470 struct dentry *vram;
471 struct dentry *gtt;
472#endif
473};
474
475struct radeon_bo_list {
476 struct radeon_bo *robj;
477 struct ttm_validate_buffer tv;
478 uint64_t gpu_offset;
479 unsigned preferred_domains;
480 unsigned allowed_domains;
481 uint32_t tiling_flags;
482};
483
484/* bo virtual address in a specific vm */
485struct radeon_bo_va {
486 /* protected by bo being reserved */
487 struct list_head bo_list;
488 uint32_t flags;
489 struct radeon_fence *last_pt_update;
490 unsigned ref_count;
491
492 /* protected by vm mutex */
493 struct interval_tree_node it;
494 struct list_head vm_status;
495
496 /* constant after initialization */
497 struct radeon_vm *vm;
498 struct radeon_bo *bo;
499};
500
501struct radeon_bo {
502 /* Protected by gem.mutex */
503 struct list_head list;
504 /* Protected by tbo.reserved */
505 u32 initial_domain;
506 struct ttm_place placements[4];
507 struct ttm_placement placement;
508 struct ttm_buffer_object tbo;
509 struct ttm_bo_kmap_obj kmap;
510 u32 flags;
511 unsigned pin_count;
512 void *kptr;
513 u32 tiling_flags;
514 u32 pitch;
515 int surface_reg;
516 unsigned prime_shared_count;
517 /* list of all virtual address to which this bo
518 * is associated to
519 */
520 struct list_head va;
521 /* Constant after initialization */
522 struct radeon_device *rdev;
523
524 struct ttm_bo_kmap_obj dma_buf_vmap;
525 pid_t pid;
526
527#ifdef CONFIG_MMU_NOTIFIER
528 struct mmu_interval_notifier notifier;
529#endif
530};
531#define gem_to_radeon_bo(gobj)({ const __typeof( ((struct radeon_bo *)0)->tbo.base ) *__mptr
= ((gobj)); (struct radeon_bo *)( (char *)__mptr - __builtin_offsetof
(struct radeon_bo, tbo.base) );}) container_of((gobj), struct radeon_bo, tbo.base)({ const __typeof( ((struct radeon_bo *)0)->tbo.base ) *__mptr
= ((gobj)); (struct radeon_bo *)( (char *)__mptr - __builtin_offsetof
(struct radeon_bo, tbo.base) );})
532
533int radeon_gem_debugfs_init(struct radeon_device *rdev);
534
535/* sub-allocation manager, it has to be protected by another lock.
536 * By conception this is an helper for other part of the driver
537 * like the indirect buffer or semaphore, which both have their
538 * locking.
539 *
540 * Principe is simple, we keep a list of sub allocation in offset
541 * order (first entry has offset == 0, last entry has the highest
542 * offset).
543 *
544 * When allocating new object we first check if there is room at
545 * the end total_size - (last_object_offset + last_object_size) >=
546 * alloc_size. If so we allocate new object there.
547 *
548 * When there is not enough room at the end, we start waiting for
549 * each sub object until we reach object_offset+object_size >=
550 * alloc_size, this object then become the sub object we return.
551 *
552 * Alignment can't be bigger than page size.
553 *
554 * Hole are not considered for allocation to keep things simple.
555 * Assumption is that there won't be hole (all object on same
556 * alignment).
557 */
558struct radeon_sa_manager {
559 wait_queue_head_t wq;
560 struct radeon_bo *bo;
561 struct list_head *hole;
562 struct list_head flist[RADEON_NUM_RINGS8];
563 struct list_head olist;
564 unsigned size;
565 uint64_t gpu_addr;
566 void *cpu_ptr;
567 uint32_t domain;
568 uint32_t align;
569};
570
571struct radeon_sa_bo;
572
573/* sub-allocation buffer */
574struct radeon_sa_bo {
575 struct list_head olist;
576 struct list_head flist;
577 struct radeon_sa_manager *manager;
578 unsigned soffset;
579 unsigned eoffset;
580 struct radeon_fence *fence;
581};
582
583/*
584 * GEM objects.
585 */
586struct radeon_gem {
587 struct rwlock mutex;
588 struct list_head objects;
589};
590
591int radeon_gem_init(struct radeon_device *rdev);
592void radeon_gem_fini(struct radeon_device *rdev);
593int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
594 int alignment, int initial_domain,
595 u32 flags, bool_Bool kernel,
596 struct drm_gem_object **obj);
597
598int radeon_mode_dumb_create(struct drm_file *file_priv,
599 struct drm_device *dev,
600 struct drm_mode_create_dumb *args);
601int radeon_mode_dumb_mmap(struct drm_file *filp,
602 struct drm_device *dev,
603 uint32_t handle, uint64_t *offset_p);
604
605/*
606 * Semaphores.
607 */
608struct radeon_semaphore {
609 struct radeon_sa_bo *sa_bo;
610 signed waiters;
611 uint64_t gpu_addr;
612};
613
614int radeon_semaphore_create(struct radeon_device *rdev,
615 struct radeon_semaphore **semaphore);
616bool_Bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
617 struct radeon_semaphore *semaphore);
618bool_Bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
619 struct radeon_semaphore *semaphore);
620void radeon_semaphore_free(struct radeon_device *rdev,
621 struct radeon_semaphore **semaphore,
622 struct radeon_fence *fence);
623
624/*
625 * Synchronization
626 */
627struct radeon_sync {
628 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS4];
629 struct radeon_fence *sync_to[RADEON_NUM_RINGS8];
630 struct radeon_fence *last_vm_update;
631};
632
633void radeon_sync_create(struct radeon_sync *sync);
634void radeon_sync_fence(struct radeon_sync *sync,
635 struct radeon_fence *fence);
636int radeon_sync_resv(struct radeon_device *rdev,
637 struct radeon_sync *sync,
638 struct dma_resv *resv,
639 bool_Bool shared);
640int radeon_sync_rings(struct radeon_device *rdev,
641 struct radeon_sync *sync,
642 int waiting_ring);
643void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
644 struct radeon_fence *fence);
645
646/*
647 * GART structures, functions & helpers
648 */
649struct radeon_mc;
650
651#define RADEON_GPU_PAGE_SIZE4096 4096
652#define RADEON_GPU_PAGE_MASK(4096 - 1) (RADEON_GPU_PAGE_SIZE4096 - 1)
653#define RADEON_GPU_PAGE_SHIFT12 12
654#define RADEON_GPU_PAGE_ALIGN(a)(((a) + (4096 - 1)) & ~(4096 - 1)) (((a) + RADEON_GPU_PAGE_MASK(4096 - 1)) & ~RADEON_GPU_PAGE_MASK(4096 - 1))
655
656#define RADEON_GART_PAGE_DUMMY0 0
657#define RADEON_GART_PAGE_VALID(1 << 0) (1 << 0)
658#define RADEON_GART_PAGE_READ(1 << 1) (1 << 1)
659#define RADEON_GART_PAGE_WRITE(1 << 2) (1 << 2)
660#define RADEON_GART_PAGE_SNOOP(1 << 3) (1 << 3)
661
662struct radeon_gart {
663 dma_addr_t table_addr;
664 struct drm_dmamem *dmah;
665 struct radeon_bo *robj;
666 void *ptr;
667 unsigned num_gpu_pages;
668 unsigned num_cpu_pages;
669 unsigned table_size;
670 struct vm_page **pages;
671 uint64_t *pages_entry;
672 bool_Bool ready;
673};
674
675int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
676void radeon_gart_table_ram_free(struct radeon_device *rdev);
677int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
678void radeon_gart_table_vram_free(struct radeon_device *rdev);
679int radeon_gart_table_vram_pin(struct radeon_device *rdev);
680void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
681int radeon_gart_init(struct radeon_device *rdev);
682void radeon_gart_fini(struct radeon_device *rdev);
683void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
684 int pages);
685int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
686 int pages, struct vm_page **pagelist,
687 dma_addr_t *dma_addr, uint32_t flags);
688
689
690/*
691 * GPU MC structures, functions & helpers
692 */
693struct radeon_mc {
694 resource_size_t aper_size;
695 resource_size_t aper_base;
696 resource_size_t agp_base;
697 /* for some chips with <= 32MB we need to lie
698 * about vram size near mc fb location */
699 u64 mc_vram_size;
700 u64 visible_vram_size;
701 u64 gtt_size;
702 u64 gtt_start;
703 u64 gtt_end;
704 u64 vram_start;
705 u64 vram_end;
706 unsigned vram_width;
707 u64 real_vram_size;
708 int vram_mtrr;
709 bool_Bool vram_is_ddr;
710 bool_Bool igp_sideport_enabled;
711 u64 gtt_base_align;
712 u64 mc_mask;
713};
714
715bool_Bool radeon_combios_sideport_present(struct radeon_device *rdev);
716bool_Bool radeon_atombios_sideport_present(struct radeon_device *rdev);
717
718/*
719 * GPU scratch registers structures, functions & helpers
720 */
721struct radeon_scratch {
722 unsigned num_reg;
723 uint32_t reg_base;
724 bool_Bool free[32];
725 uint32_t reg[32];
726};
727
728int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
729void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
730
731/*
732 * GPU doorbell structures, functions & helpers
733 */
734#define RADEON_MAX_DOORBELLS1024 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
735
736struct radeon_doorbell {
737 /* doorbell mmio */
738 resource_size_t base;
739 resource_size_t size;
740 u32 __iomem *ptr;
741 bus_space_handle_t bsh;
742 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
743 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS)unsigned long used[((((1024)) + ((8 * sizeof(long)) - 1)) / (
8 * sizeof(long)))];;
744};
745
746int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
747void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
748
749/*
750 * IRQS.
751 */
752
753struct radeon_flip_work {
754 struct work_struct flip_work;
755 struct work_struct unpin_work;
756 struct radeon_device *rdev;
757 int crtc_id;
758 u32 target_vblank;
759 uint64_t base;
760 struct drm_pending_vblank_event *event;
761 struct radeon_bo *old_rbo;
762 struct dma_fence *fence;
763 bool_Bool async;
764};
765
766struct r500_irq_stat_regs {
767 u32 disp_int;
768 u32 hdmi0_status;
769};
770
771struct r600_irq_stat_regs {
772 u32 disp_int;
773 u32 disp_int_cont;
774 u32 disp_int_cont2;
775 u32 d1grph_int;
776 u32 d2grph_int;
777 u32 hdmi0_status;
778 u32 hdmi1_status;
779};
780
781struct evergreen_irq_stat_regs {
782 u32 disp_int[6];
783 u32 grph_int[6];
784 u32 afmt_status[6];
785};
786
787struct cik_irq_stat_regs {
788 u32 disp_int;
789 u32 disp_int_cont;
790 u32 disp_int_cont2;
791 u32 disp_int_cont3;
792 u32 disp_int_cont4;
793 u32 disp_int_cont5;
794 u32 disp_int_cont6;
795 u32 d1grph_int;
796 u32 d2grph_int;
797 u32 d3grph_int;
798 u32 d4grph_int;
799 u32 d5grph_int;
800 u32 d6grph_int;
801};
802
803union radeon_irq_stat_regs {
804 struct r500_irq_stat_regs r500;
805 struct r600_irq_stat_regs r600;
806 struct evergreen_irq_stat_regs evergreen;
807 struct cik_irq_stat_regs cik;
808};
809
810struct radeon_irq {
811 bool_Bool installed;
812 spinlock_t lock;
813 atomic_t ring_int[RADEON_NUM_RINGS8];
814 bool_Bool crtc_vblank_int[RADEON_MAX_CRTCS6];
815 atomic_t pflip[RADEON_MAX_CRTCS6];
816 wait_queue_head_t vblank_queue;
817 bool_Bool hpd[RADEON_MAX_HPD_PINS7];
818 bool_Bool afmt[RADEON_MAX_AFMT_BLOCKS7];
819 union radeon_irq_stat_regs stat_regs;
820 bool_Bool dpm_thermal;
821};
822
823int radeon_irq_kms_init(struct radeon_device *rdev);
824void radeon_irq_kms_fini(struct radeon_device *rdev);
825void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
826bool_Bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
827void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
828void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
829void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
830void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
831void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
832void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
833void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
834
835/*
836 * CP & rings.
837 */
838
839struct radeon_ib {
840 struct radeon_sa_bo *sa_bo;
841 uint32_t length_dw;
842 uint64_t gpu_addr;
843 uint32_t *ptr;
844 int ring;
845 struct radeon_fence *fence;
846 struct radeon_vm *vm;
847 bool_Bool is_const_ib;
848 struct radeon_sync sync;
849};
850
851struct radeon_ring {
852 struct radeon_bo *ring_obj;
853 volatile uint32_t *ring;
854 unsigned rptr_offs;
855 unsigned rptr_save_reg;
856 u64 next_rptr_gpu_addr;
857 volatile u32 *next_rptr_cpu_addr;
858 unsigned wptr;
859 unsigned wptr_old;
860 unsigned ring_size;
861 unsigned ring_free_dw;
862 int count_dw;
863 atomic_t last_rptr;
864 atomic64_t last_activity;
865 uint64_t gpu_addr;
866 uint32_t align_mask;
867 uint32_t ptr_mask;
868 bool_Bool ready;
869 u32 nop;
870 u32 idx;
871 u64 last_semaphore_signal_addr;
872 u64 last_semaphore_wait_addr;
873 /* for CIK queues */
874 u32 me;
875 u32 pipe;
876 u32 queue;
877 struct radeon_bo *mqd_obj;
878 u32 doorbell_index;
879 unsigned wptr_offs;
880};
881
882struct radeon_mec {
883 struct radeon_bo *hpd_eop_obj;
884 u64 hpd_eop_gpu_addr;
885 u32 num_pipe;
886 u32 num_mec;
887 u32 num_queue;
888};
889
890/*
891 * VM
892 */
893
894/* maximum number of VMIDs */
895#define RADEON_NUM_VM16 16
896
897/* number of entries in page table */
898#define RADEON_VM_PTE_COUNT(1 << radeon_vm_block_size) (1 << radeon_vm_block_size)
899
900/* PTBs (Page Table Blocks) need to be aligned to 32K */
901#define RADEON_VM_PTB_ALIGN_SIZE32768 32768
902#define RADEON_VM_PTB_ALIGN_MASK(32768 - 1) (RADEON_VM_PTB_ALIGN_SIZE32768 - 1)
903#define RADEON_VM_PTB_ALIGN(a)(((a) + (32768 - 1)) & ~(32768 - 1)) (((a) + RADEON_VM_PTB_ALIGN_MASK(32768 - 1)) & ~RADEON_VM_PTB_ALIGN_MASK(32768 - 1))
904
905#define R600_PTE_VALID(1 << 0) (1 << 0)
906#define R600_PTE_SYSTEM(1 << 1) (1 << 1)
907#define R600_PTE_SNOOPED(1 << 2) (1 << 2)
908#define R600_PTE_READABLE(1 << 5) (1 << 5)
909#define R600_PTE_WRITEABLE(1 << 6) (1 << 6)
910
911/* PTE (Page Table Entry) fragment field for different page sizes */
912#define R600_PTE_FRAG_4KB(0 << 7) (0 << 7)
913#define R600_PTE_FRAG_64KB(4 << 7) (4 << 7)
914#define R600_PTE_FRAG_256KB(6 << 7) (6 << 7)
915
916/* flags needed to be set so we can copy directly from the GART table */
917#define R600_PTE_GART_MASK( (1 << 5) | (1 << 6) | (1 << 1) | (1 <<
0) ) ( R600_PTE_READABLE(1 << 5) | R600_PTE_WRITEABLE(1 << 6) | \
918 R600_PTE_SYSTEM(1 << 1) | R600_PTE_VALID(1 << 0) )
919
920struct radeon_vm_pt {
921 struct radeon_bo *bo;
922 uint64_t addr;
923};
924
925struct radeon_vm_id {
926 unsigned id;
927 uint64_t pd_gpu_addr;
928 /* last flushed PD/PT update */
929 struct radeon_fence *flushed_updates;
930 /* last use of vmid */
931 struct radeon_fence *last_id_use;
932};
933
934struct radeon_vm {
935 struct rwlock mutex;
936
937 struct rb_root_cached va;
938
939 /* protecting invalidated and freed */
940 spinlock_t status_lock;
941
942 /* BOs moved, but not yet updated in the PT */
943 struct list_head invalidated;
944
945 /* BOs freed, but not yet updated in the PT */
946 struct list_head freed;
947
948 /* BOs cleared in the PT */
949 struct list_head cleared;
950
951 /* contains the page directory */
952 struct radeon_bo *page_directory;
953 unsigned max_pde_used;
954
955 /* array of page tables, one for each page directory entry */
956 struct radeon_vm_pt *page_tables;
957
958 struct radeon_bo_va *ib_bo_va;
959
960 /* for id and flush management per ring */
961 struct radeon_vm_id ids[RADEON_NUM_RINGS8];
962};
963
964struct radeon_vm_manager {
965 struct radeon_fence *active[RADEON_NUM_VM16];
966 uint32_t max_pfn;
967 /* number of VMIDs */
968 unsigned nvm;
969 /* vram base address for page table entry */
970 u64 vram_base_offset;
971 /* is vm enabled? */
972 bool_Bool enabled;
973 /* for hw to save the PD addr on suspend/resume */
974 uint32_t saved_table_addr[RADEON_NUM_VM16];
975};
976
977/*
978 * file private structure
979 */
980struct radeon_fpriv {
981 struct radeon_vm vm;
982};
983
984/*
985 * R6xx+ IH ring
986 */
987struct r600_ih {
988 struct radeon_bo *ring_obj;
989 volatile uint32_t *ring;
990 unsigned rptr;
991 unsigned ring_size;
992 uint64_t gpu_addr;
993 uint32_t ptr_mask;
994 atomic_t lock;
995 bool_Bool enabled;
996};
997
998/*
999 * RLC stuff
1000 */
1001#include "clearstate_defs.h"
1002
1003struct radeon_rlc {
1004 /* for power gating */
1005 struct radeon_bo *save_restore_obj;
1006 uint64_t save_restore_gpu_addr;
1007 volatile uint32_t *sr_ptr;
1008 const u32 *reg_list;
1009 u32 reg_list_size;
1010 /* for clear state */
1011 struct radeon_bo *clear_state_obj;
1012 uint64_t clear_state_gpu_addr;
1013 volatile uint32_t *cs_ptr;
1014 const struct cs_section_def *cs_data;
1015 u32 clear_state_size;
1016 /* for cp tables */
1017 struct radeon_bo *cp_table_obj;
1018 uint64_t cp_table_gpu_addr;
1019 volatile uint32_t *cp_table_ptr;
1020 u32 cp_table_size;
1021};
1022
1023int radeon_ib_get(struct radeon_device *rdev, int ring,
1024 struct radeon_ib *ib, struct radeon_vm *vm,
1025 unsigned size);
1026void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1027int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1028 struct radeon_ib *const_ib, bool_Bool hdp_flush);
1029int radeon_ib_pool_init(struct radeon_device *rdev);
1030void radeon_ib_pool_fini(struct radeon_device *rdev);
1031int radeon_ib_ring_tests(struct radeon_device *rdev);
1032/* Ring access between begin & end cannot sleep */
1033bool_Bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1034 struct radeon_ring *ring);
1035void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1036int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1037int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1038void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1039 bool_Bool hdp_flush);
1040void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1041 bool_Bool hdp_flush);
1042void radeon_ring_undo(struct radeon_ring *ring);
1043void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1044int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1045void radeon_ring_lockup_update(struct radeon_device *rdev,
1046 struct radeon_ring *ring);
1047bool_Bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1048unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1049 uint32_t **data);
1050int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1051 unsigned size, uint32_t *data);
1052int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1053 unsigned rptr_offs, u32 nop);
1054void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1055
1056
1057/* r600 async dma */
1058void r600_dma_stop(struct radeon_device *rdev);
1059int r600_dma_resume(struct radeon_device *rdev);
1060void r600_dma_fini(struct radeon_device *rdev);
1061
1062void cayman_dma_stop(struct radeon_device *rdev);
1063int cayman_dma_resume(struct radeon_device *rdev);
1064void cayman_dma_fini(struct radeon_device *rdev);
1065
1066/*
1067 * CS.
1068 */
1069struct radeon_cs_chunk {
1070 uint32_t length_dw;
1071 uint32_t *kdata;
1072 void __user *user_ptr;
1073};
1074
1075struct radeon_cs_parser {
1076 struct device *dev;
1077 struct radeon_device *rdev;
1078 struct drm_file *filp;
1079 /* chunks */
1080 unsigned nchunks;
1081 struct radeon_cs_chunk *chunks;
1082 uint64_t *chunks_array;
1083 /* IB */
1084 unsigned idx;
1085 /* relocations */
1086 unsigned nrelocs;
1087 struct radeon_bo_list *relocs;
1088 struct radeon_bo_list *vm_bos;
1089 struct list_head validated;
1090 unsigned dma_reloc_idx;
1091 /* indices of various chunks */
1092 struct radeon_cs_chunk *chunk_ib;
1093 struct radeon_cs_chunk *chunk_relocs;
1094 struct radeon_cs_chunk *chunk_flags;
1095 struct radeon_cs_chunk *chunk_const_ib;
1096 struct radeon_ib ib;
1097 struct radeon_ib const_ib;
1098 void *track;
1099 unsigned family;
1100 int parser_error;
1101 u32 cs_flags;
1102 u32 ring;
1103 s32 priority;
1104 struct ww_acquire_ctx ticket;
1105};
1106
1107static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1108{
1109 struct radeon_cs_chunk *ibc = p->chunk_ib;
1110
1111 if (ibc->kdata)
1112 return ibc->kdata[idx];
1113 return p->ib.ptr[idx];
1114}
1115
1116
1117struct radeon_cs_packet {
1118 unsigned idx;
1119 unsigned type;
1120 unsigned reg;
1121 unsigned opcode;
1122 int count;
1123 unsigned one_reg_wr;
1124};
1125
1126typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1127 struct radeon_cs_packet *pkt,
1128 unsigned idx, unsigned reg);
1129typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1130 struct radeon_cs_packet *pkt);
1131
1132
1133/*
1134 * AGP
1135 */
1136int radeon_agp_init(struct radeon_device *rdev);
1137void radeon_agp_resume(struct radeon_device *rdev);
1138void radeon_agp_suspend(struct radeon_device *rdev);
1139void radeon_agp_fini(struct radeon_device *rdev);
1140
1141
1142/*
1143 * Writeback
1144 */
1145struct radeon_wb {
1146 struct radeon_bo *wb_obj;
1147 volatile uint32_t *wb;
1148 uint64_t gpu_addr;
1149 bool_Bool enabled;
1150 bool_Bool use_event;
1151};
1152
1153#define RADEON_WB_SCRATCH_OFFSET0 0
1154#define RADEON_WB_RING0_NEXT_RPTR256 256
1155#define RADEON_WB_CP_RPTR_OFFSET1024 1024
1156#define RADEON_WB_CP1_RPTR_OFFSET1280 1280
1157#define RADEON_WB_CP2_RPTR_OFFSET1536 1536
1158#define R600_WB_DMA_RPTR_OFFSET1792 1792
1159#define R600_WB_IH_WPTR_OFFSET2048 2048
1160#define CAYMAN_WB_DMA1_RPTR_OFFSET2304 2304
1161#define R600_WB_EVENT_OFFSET3072 3072
1162#define CIK_WB_CP1_WPTR_OFFSET3328 3328
1163#define CIK_WB_CP2_WPTR_OFFSET3584 3584
1164#define R600_WB_DMA_RING_TEST_OFFSET3588 3588
1165#define CAYMAN_WB_DMA1_RING_TEST_OFFSET3592 3592
1166
1167/**
1168 * struct radeon_pm - power management datas
1169 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1170 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1172 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1173 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1174 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1175 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1176 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1177 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1178 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1179 * @needed_bandwidth: current bandwidth needs
1180 *
1181 * It keeps track of various data needed to take powermanagement decision.
1182 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1183 * Equation between gpu/memory clock and available bandwidth is hw dependent
1184 * (type of memory, bus size, efficiency, ...)
1185 */
1186
1187enum radeon_pm_method {
1188 PM_METHOD_PROFILE,
1189 PM_METHOD_DYNPM,
1190 PM_METHOD_DPM,
1191};
1192
1193enum radeon_dynpm_state {
1194 DYNPM_STATE_DISABLED,
1195 DYNPM_STATE_MINIMUM,
1196 DYNPM_STATE_PAUSED,
1197 DYNPM_STATE_ACTIVE,
1198 DYNPM_STATE_SUSPENDED,
1199};
1200enum radeon_dynpm_action {
1201 DYNPM_ACTION_NONE,
1202 DYNPM_ACTION_MINIMUM,
1203 DYNPM_ACTION_DOWNCLOCK,
1204 DYNPM_ACTION_UPCLOCK,
1205 DYNPM_ACTION_DEFAULT
1206};
1207
1208enum radeon_voltage_type {
1209 VOLTAGE_NONE = 0,
1210 VOLTAGE_GPIO,
1211 VOLTAGE_VDDC,
1212 VOLTAGE_SW
1213};
1214
1215enum radeon_pm_state_type {
1216 /* not used for dpm */
1217 POWER_STATE_TYPE_DEFAULT,
1218 POWER_STATE_TYPE_POWERSAVE,
1219 /* user selectable states */
1220 POWER_STATE_TYPE_BATTERY,
1221 POWER_STATE_TYPE_BALANCED,
1222 POWER_STATE_TYPE_PERFORMANCE,
1223 /* internal states */
1224 POWER_STATE_TYPE_INTERNAL_UVD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1226 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1227 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1228 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1229 POWER_STATE_TYPE_INTERNAL_BOOT,
1230 POWER_STATE_TYPE_INTERNAL_THERMAL,
1231 POWER_STATE_TYPE_INTERNAL_ACPI,
1232 POWER_STATE_TYPE_INTERNAL_ULV,
1233 POWER_STATE_TYPE_INTERNAL_3DPERF,
1234};
1235
1236enum radeon_pm_profile_type {
1237 PM_PROFILE_DEFAULT,
1238 PM_PROFILE_AUTO,
1239 PM_PROFILE_LOW,
1240 PM_PROFILE_MID,
1241 PM_PROFILE_HIGH,
1242};
1243
1244#define PM_PROFILE_DEFAULT_IDX0 0
1245#define PM_PROFILE_LOW_SH_IDX1 1
1246#define PM_PROFILE_MID_SH_IDX2 2
1247#define PM_PROFILE_HIGH_SH_IDX3 3
1248#define PM_PROFILE_LOW_MH_IDX4 4
1249#define PM_PROFILE_MID_MH_IDX5 5
1250#define PM_PROFILE_HIGH_MH_IDX6 6
1251#define PM_PROFILE_MAX7 7
1252
1253struct radeon_pm_profile {
1254 int dpms_off_ps_idx;
1255 int dpms_on_ps_idx;
1256 int dpms_off_cm_idx;
1257 int dpms_on_cm_idx;
1258};
1259
1260enum radeon_int_thermal_type {
1261 THERMAL_TYPE_NONE,
1262 THERMAL_TYPE_EXTERNAL,
1263 THERMAL_TYPE_EXTERNAL_GPIO,
1264 THERMAL_TYPE_RV6XX,
1265 THERMAL_TYPE_RV770,
1266 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1267 THERMAL_TYPE_EVERGREEN,
1268 THERMAL_TYPE_SUMO,
1269 THERMAL_TYPE_NI,
1270 THERMAL_TYPE_SI,
1271 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1272 THERMAL_TYPE_CI,
1273 THERMAL_TYPE_KV,
1274};
1275
1276struct radeon_voltage {
1277 enum radeon_voltage_type type;
1278 /* gpio voltage */
1279 struct radeon_gpio_rec gpio;
1280 u32 delay; /* delay in usec from voltage drop to sclk change */
1281 bool_Bool active_high; /* voltage drop is active when bit is high */
1282 /* VDDC voltage */
1283 u8 vddc_id; /* index into vddc voltage table */
1284 u8 vddci_id; /* index into vddci voltage table */
1285 bool_Bool vddci_enabled;
1286 /* r6xx+ sw */
1287 u16 voltage;
1288 /* evergreen+ vddci */
1289 u16 vddci;
1290};
1291
1292/* clock mode flags */
1293#define RADEON_PM_MODE_NO_DISPLAY(1 << 0) (1 << 0)
1294
1295struct radeon_pm_clock_info {
1296 /* memory clock */
1297 u32 mclk;
1298 /* engine clock */
1299 u32 sclk;
1300 /* voltage info */
1301 struct radeon_voltage voltage;
1302 /* standardized clock flags */
1303 u32 flags;
1304};
1305
1306/* state flags */
1307#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0) (1 << 0)
1308
1309struct radeon_power_state {
1310 enum radeon_pm_state_type type;
1311 struct radeon_pm_clock_info *clock_info;
1312 /* number of valid clock modes in this power state */
1313 int num_clock_modes;
1314 struct radeon_pm_clock_info *default_clock_mode;
1315 /* standardized state flags */
1316 u32 flags;
1317 u32 misc; /* vbios specific flags */
1318 u32 misc2; /* vbios specific flags */
1319 int pcie_lanes; /* pcie lanes */
1320};
1321
1322/*
1323 * Some modes are overclocked by very low value, accept them
1324 */
1325#define RADEON_MODE_OVERCLOCK_MARGIN500 500 /* 5 MHz */
1326
1327enum radeon_dpm_auto_throttle_src {
1328 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1329 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1330};
1331
1332enum radeon_dpm_event_src {
1333 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1334 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1335 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1336 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1337 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1338};
1339
1340#define RADEON_MAX_VCE_LEVELS6 6
1341
1342enum radeon_vce_level {
1343 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1344 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1345 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1346 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1347 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1348 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1349};
1350
1351struct radeon_ps {
1352 u32 caps; /* vbios flags */
1353 u32 class; /* vbios flags */
1354 u32 class2; /* vbios flags */
1355 /* UVD clocks */
1356 u32 vclk;
1357 u32 dclk;
1358 /* VCE clocks */
1359 u32 evclk;
1360 u32 ecclk;
1361 bool_Bool vce_active;
1362 enum radeon_vce_level vce_level;
1363 /* asic priv */
1364 void *ps_priv;
1365};
1366
1367struct radeon_dpm_thermal {
1368 /* thermal interrupt work */
1369 struct work_struct work;
1370 /* low temperature threshold */
1371 int min_temp;
1372 /* high temperature threshold */
1373 int max_temp;
1374 /* was interrupt low to high or high to low */
1375 bool_Bool high_to_low;
1376};
1377
1378enum radeon_clk_action
1379{
1380 RADEON_SCLK_UP = 1,
1381 RADEON_SCLK_DOWN
1382};
1383
1384struct radeon_blacklist_clocks
1385{
1386 u32 sclk;
1387 u32 mclk;
1388 enum radeon_clk_action action;
1389};
1390
1391struct radeon_clock_and_voltage_limits {
1392 u32 sclk;
1393 u32 mclk;
1394 u16 vddc;
1395 u16 vddci;
1396};
1397
1398struct radeon_clock_array {
1399 u32 count;
1400 u32 *values;
1401};
1402
1403struct radeon_clock_voltage_dependency_entry {
1404 u32 clk;
1405 u16 v;
1406};
1407
1408struct radeon_clock_voltage_dependency_table {
1409 u32 count;
1410 struct radeon_clock_voltage_dependency_entry *entries;
1411};
1412
1413union radeon_cac_leakage_entry {
1414 struct {
1415 u16 vddc;
1416 u32 leakage;
1417 };
1418 struct {
1419 u16 vddc1;
1420 u16 vddc2;
1421 u16 vddc3;
1422 };
1423};
1424
1425struct radeon_cac_leakage_table {
1426 u32 count;
1427 union radeon_cac_leakage_entry *entries;
1428};
1429
1430struct radeon_phase_shedding_limits_entry {
1431 u16 voltage;
1432 u32 sclk;
1433 u32 mclk;
1434};
1435
1436struct radeon_phase_shedding_limits_table {
1437 u32 count;
1438 struct radeon_phase_shedding_limits_entry *entries;
1439};
1440
1441struct radeon_uvd_clock_voltage_dependency_entry {
1442 u32 vclk;
1443 u32 dclk;
1444 u16 v;
1445};
1446
1447struct radeon_uvd_clock_voltage_dependency_table {
1448 u8 count;
1449 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1450};
1451
1452struct radeon_vce_clock_voltage_dependency_entry {
1453 u32 ecclk;
1454 u32 evclk;
1455 u16 v;
1456};
1457
1458struct radeon_vce_clock_voltage_dependency_table {
1459 u8 count;
1460 struct radeon_vce_clock_voltage_dependency_entry *entries;
1461};
1462
1463struct radeon_ppm_table {
1464 u8 ppm_design;
1465 u16 cpu_core_number;
1466 u32 platform_tdp;
1467 u32 small_ac_platform_tdp;
1468 u32 platform_tdc;
1469 u32 small_ac_platform_tdc;
1470 u32 apu_tdp;
1471 u32 dgpu_tdp;
1472 u32 dgpu_ulv_power;
1473 u32 tj_max;
1474};
1475
1476struct radeon_cac_tdp_table {
1477 u16 tdp;
1478 u16 configurable_tdp;
1479 u16 tdc;
1480 u16 battery_power_limit;
1481 u16 small_power_limit;
1482 u16 low_cac_leakage;
1483 u16 high_cac_leakage;
1484 u16 maximum_power_delivery_limit;
1485};
1486
1487struct radeon_dpm_dynamic_state {
1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1489 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1491 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1493 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1494 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1495 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1496 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1497 struct radeon_clock_array valid_sclk_values;
1498 struct radeon_clock_array valid_mclk_values;
1499 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1500 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1501 u32 mclk_sclk_ratio;
1502 u32 sclk_mclk_delta;
1503 u16 vddc_vddci_delta;
1504 u16 min_vddc_for_pcie_gen2;
1505 struct radeon_cac_leakage_table cac_leakage_table;
1506 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1507 struct radeon_ppm_table *ppm_table;
1508 struct radeon_cac_tdp_table *cac_tdp_table;
1509};
1510
1511struct radeon_dpm_fan {
1512 u16 t_min;
1513 u16 t_med;
1514 u16 t_high;
1515 u16 pwm_min;
1516 u16 pwm_med;
1517 u16 pwm_high;
1518 u8 t_hyst;
1519 u32 cycle_delay;
1520 u16 t_max;
1521 u8 control_mode;
1522 u16 default_max_fan_pwm;
1523 u16 default_fan_output_sensitivity;
1524 u16 fan_output_sensitivity;
1525 bool_Bool ucode_fan_control;
1526};
1527
1528enum radeon_pcie_gen {
1529 RADEON_PCIE_GEN1 = 0,
1530 RADEON_PCIE_GEN2 = 1,
1531 RADEON_PCIE_GEN3 = 2,
1532 RADEON_PCIE_GEN_INVALID = 0xffff
1533};
1534
1535enum radeon_dpm_forced_level {
1536 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1537 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1538 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1539};
1540
1541struct radeon_vce_state {
1542 /* vce clocks */
1543 u32 evclk;
1544 u32 ecclk;
1545 /* gpu clocks */
1546 u32 sclk;
1547 u32 mclk;
1548 u8 clk_idx;
1549 u8 pstate;
1550};
1551
1552struct radeon_dpm {
1553 struct radeon_ps *ps;
1554 /* number of valid power states */
1555 int num_ps;
1556 /* current power state that is active */
1557 struct radeon_ps *current_ps;
1558 /* requested power state */
1559 struct radeon_ps *requested_ps;
1560 /* boot up power state */
1561 struct radeon_ps *boot_ps;
1562 /* default uvd power state */
1563 struct radeon_ps *uvd_ps;
1564 /* vce requirements */
1565 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS6];
1566 enum radeon_vce_level vce_level;
1567 enum radeon_pm_state_type state;
1568 enum radeon_pm_state_type user_state;
1569 u32 platform_caps;
1570 u32 voltage_response_time;
1571 u32 backbias_response_time;
1572 void *priv;
1573 u32 new_active_crtcs;
1574 int new_active_crtc_count;
1575 int high_pixelclock_count;
1576 u32 current_active_crtcs;
1577 int current_active_crtc_count;
1578 bool_Bool single_display;
1579 struct radeon_dpm_dynamic_state dyn_state;
1580 struct radeon_dpm_fan fan;
1581 u32 tdp_limit;
1582 u32 near_tdp_limit;
1583 u32 near_tdp_limit_adjusted;
1584 u32 sq_ramping_threshold;
1585 u32 cac_leakage;
1586 u16 tdp_od_limit;
1587 u32 tdp_adjustment;
1588 u16 load_line_slope;
1589 bool_Bool power_control;
1590 bool_Bool ac_power;
1591 /* special states active */
1592 bool_Bool thermal_active;
1593 bool_Bool uvd_active;
1594 bool_Bool vce_active;
1595 /* thermal handling */
1596 struct radeon_dpm_thermal thermal;
1597 /* forced levels */
1598 enum radeon_dpm_forced_level forced_level;
1599 /* track UVD streams */
1600 unsigned sd;
1601 unsigned hd;
1602};
1603
1604void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool_Bool enable);
1605void radeon_dpm_enable_vce(struct radeon_device *rdev, bool_Bool enable);
1606
1607struct radeon_pm {
1608 struct rwlock mutex;
1609 /* write locked while reprogramming mclk */
1610 struct rwlock mclk_lock;
1611 u32 active_crtcs;
1612 int active_crtc_count;
1613 int req_vblank;
1614 bool_Bool vblank_sync;
1615 fixed20_12 max_bandwidth;
1616 fixed20_12 igp_sideport_mclk;
1617 fixed20_12 igp_system_mclk;
1618 fixed20_12 igp_ht_link_clk;
1619 fixed20_12 igp_ht_link_width;
1620 fixed20_12 k8_bandwidth;
1621 fixed20_12 sideport_bandwidth;
1622 fixed20_12 ht_bandwidth;
1623 fixed20_12 core_bandwidth;
1624 fixed20_12 sclk;
1625 fixed20_12 mclk;
1626 fixed20_12 needed_bandwidth;
1627 struct radeon_power_state *power_state;
1628 /* number of valid power states */
1629 int num_power_states;
1630 int current_power_state_index;
1631 int current_clock_mode_index;
1632 int requested_power_state_index;
1633 int requested_clock_mode_index;
1634 int default_power_state_index;
1635 u32 current_sclk;
1636 u32 current_mclk;
1637 u16 current_vddc;
1638 u16 current_vddci;
1639 u32 default_sclk;
1640 u32 default_mclk;
1641 u16 default_vddc;
1642 u16 default_vddci;
1643 struct radeon_i2c_chan *i2c_bus;
1644 /* selected pm method */
1645 enum radeon_pm_method pm_method;
1646 /* dynpm power management */
1647 struct delayed_work dynpm_idle_work;
1648 enum radeon_dynpm_state dynpm_state;
1649 enum radeon_dynpm_action dynpm_planned_action;
1650 unsigned long dynpm_action_timeout;
1651 bool_Bool dynpm_can_upclock;
1652 bool_Bool dynpm_can_downclock;
1653 /* profile-based power management */
1654 enum radeon_pm_profile_type profile;
1655 int profile_index;
1656 struct radeon_pm_profile profiles[PM_PROFILE_MAX7];
1657 /* internal thermal controller on rv6xx+ */
1658 enum radeon_int_thermal_type int_thermal_type;
1659 struct device *int_hwmon_dev;
1660 /* fan control parameters */
1661 bool_Bool no_fan;
1662 u8 fan_pulses_per_revolution;
1663 u8 fan_min_rpm;
1664 u8 fan_max_rpm;
1665 /* dpm */
1666 bool_Bool dpm_enabled;
1667 bool_Bool sysfs_initialized;
1668 struct radeon_dpm dpm;
1669};
1670
1671#define RADEON_PCIE_SPEED_251 1
1672#define RADEON_PCIE_SPEED_502 2
1673#define RADEON_PCIE_SPEED_804 4
1674
1675int radeon_pm_get_type_index(struct radeon_device *rdev,
1676 enum radeon_pm_state_type ps_type,
1677 int instance);
1678/*
1679 * UVD
1680 */
1681#define RADEON_DEFAULT_UVD_HANDLES10 10
1682#define RADEON_MAX_UVD_HANDLES30 30
1683#define RADEON_UVD_STACK_SIZE(200*1024) (200*1024)
1684#define RADEON_UVD_HEAP_SIZE(256*1024) (256*1024)
1685#define RADEON_UVD_SESSION_SIZE(50*1024) (50*1024)
1686
1687struct radeon_uvd {
1688 bool_Bool fw_header_present;
1689 struct radeon_bo *vcpu_bo;
1690 void *cpu_addr;
1691 uint64_t gpu_addr;
1692 unsigned max_handles;
1693 atomic_t handles[RADEON_MAX_UVD_HANDLES30];
1694 struct drm_file *filp[RADEON_MAX_UVD_HANDLES30];
1695 unsigned img_size[RADEON_MAX_UVD_HANDLES30];
1696 struct delayed_work idle_work;
1697};
1698
1699int radeon_uvd_init(struct radeon_device *rdev);
1700void radeon_uvd_fini(struct radeon_device *rdev);
1701int radeon_uvd_suspend(struct radeon_device *rdev);
1702int radeon_uvd_resume(struct radeon_device *rdev);
1703int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1704 uint32_t handle, struct radeon_fence **fence);
1705int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1706 uint32_t handle, struct radeon_fence **fence);
1707void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1708 uint32_t allowed_domains);
1709void radeon_uvd_free_handles(struct radeon_device *rdev,
1710 struct drm_file *filp);
1711int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1712void radeon_uvd_note_usage(struct radeon_device *rdev);
1713int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1714 unsigned vclk, unsigned dclk,
1715 unsigned vco_min, unsigned vco_max,
1716 unsigned fb_factor, unsigned fb_mask,
1717 unsigned pd_min, unsigned pd_max,
1718 unsigned pd_even,
1719 unsigned *optimal_fb_div,
1720 unsigned *optimal_vclk_div,
1721 unsigned *optimal_dclk_div);
1722int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1723 unsigned cg_upll_func_cntl);
1724
1725/*
1726 * VCE
1727 */
1728#define RADEON_MAX_VCE_HANDLES16 16
1729
1730struct radeon_vce {
1731 struct radeon_bo *vcpu_bo;
1732 uint64_t gpu_addr;
1733 unsigned fw_version;
1734 unsigned fb_version;
1735 atomic_t handles[RADEON_MAX_VCE_HANDLES16];
1736 struct drm_file *filp[RADEON_MAX_VCE_HANDLES16];
1737 unsigned img_size[RADEON_MAX_VCE_HANDLES16];
1738 struct delayed_work idle_work;
1739 uint32_t keyselect;
1740};
1741
1742int radeon_vce_init(struct radeon_device *rdev);
1743void radeon_vce_fini(struct radeon_device *rdev);
1744int radeon_vce_suspend(struct radeon_device *rdev);
1745int radeon_vce_resume(struct radeon_device *rdev);
1746int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1747 uint32_t handle, struct radeon_fence **fence);
1748int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1749 uint32_t handle, struct radeon_fence **fence);
1750void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1751void radeon_vce_note_usage(struct radeon_device *rdev);
1752int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1753int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1754bool_Bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1755 struct radeon_ring *ring,
1756 struct radeon_semaphore *semaphore,
1757 bool_Bool emit_wait);
1758void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1759void radeon_vce_fence_emit(struct radeon_device *rdev,
1760 struct radeon_fence *fence);
1761int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1762int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1763
1764struct r600_audio_pin {
1765 int channels;
1766 int rate;
1767 int bits_per_sample;
1768 u8 status_bits;
1769 u8 category_code;
1770 u32 offset;
1771 bool_Bool connected;
1772 u32 id;
1773};
1774
1775struct r600_audio {
1776 bool_Bool enabled;
1777 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS7];
1778 int num_pins;
1779 struct radeon_audio_funcs *hdmi_funcs;
1780 struct radeon_audio_funcs *dp_funcs;
1781 struct radeon_audio_basic_funcs *funcs;
1782};
1783
1784/*
1785 * Benchmarking
1786 */
1787void radeon_benchmark(struct radeon_device *rdev, int test_number);
1788
1789
1790/*
1791 * Testing
1792 */
1793void radeon_test_moves(struct radeon_device *rdev);
1794void radeon_test_ring_sync(struct radeon_device *rdev,
1795 struct radeon_ring *cpA,
1796 struct radeon_ring *cpB);
1797void radeon_test_syncing(struct radeon_device *rdev);
1798
1799/*
1800 * MMU Notifier
1801 */
1802#if defined(CONFIG_MMU_NOTIFIER)
1803int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1804void radeon_mn_unregister(struct radeon_bo *bo);
1805#else
1806static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1807{
1808 return -ENODEV19;
1809}
1810static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1811#endif
1812
1813/*
1814 * Debugfs
1815 */
1816struct radeon_debugfs {
1817 struct drm_info_list *files;
1818 unsigned num_files;
1819};
1820
1821int radeon_debugfs_add_files(struct radeon_device *rdev,
1822 struct drm_info_list *files,
1823 unsigned nfiles);
1824int radeon_debugfs_fence_init(struct radeon_device *rdev);
1825
1826/*
1827 * ASIC ring specific functions.
1828 */
1829struct radeon_asic_ring {
1830 /* ring read/write ptr handling */
1831 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1832 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1833 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1834
1835 /* validating and patching of IBs */
1836 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1837 int (*cs_parse)(struct radeon_cs_parser *p);
1838
1839 /* command emmit functions */
1840 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1841 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1842 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1843 bool_Bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1844 struct radeon_semaphore *semaphore, bool_Bool emit_wait);
1845 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1846 unsigned vm_id, uint64_t pd_addr);
1847
1848 /* testing functions */
1849 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1850 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1851 bool_Bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1852
1853 /* deprecated */
1854 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1855};
1856
1857/*
1858 * ASIC specific functions.
1859 */
1860struct radeon_asic {
1861 int (*init)(struct radeon_device *rdev);
1862 void (*fini)(struct radeon_device *rdev);
1863 int (*resume)(struct radeon_device *rdev);
1864 int (*suspend)(struct radeon_device *rdev);
1865 void (*vga_set_state)(struct radeon_device *rdev, bool_Bool state);
1866 int (*asic_reset)(struct radeon_device *rdev, bool_Bool hard);
1867 /* Flush the HDP cache via MMIO */
1868 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1869 /* check if 3D engine is idle */
1870 bool_Bool (*gui_idle)(struct radeon_device *rdev);
1871 /* wait for mc_idle */
1872 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1873 /* get the reference clock */
1874 u32 (*get_xclk)(struct radeon_device *rdev);
1875 /* get the gpu clock counter */
1876 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1877 /* get register for info ioctl */
1878 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1879 /* gart */
1880 struct {
1881 void (*tlb_flush)(struct radeon_device *rdev);
1882 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1883 void (*set_page)(struct radeon_device *rdev, unsigned i,
1884 uint64_t entry);
1885 } gart;
1886 struct {
1887 int (*init)(struct radeon_device *rdev);
1888 void (*fini)(struct radeon_device *rdev);
1889 void (*copy_pages)(struct radeon_device *rdev,
1890 struct radeon_ib *ib,
1891 uint64_t pe, uint64_t src,
1892 unsigned count);
1893 void (*write_pages)(struct radeon_device *rdev,
1894 struct radeon_ib *ib,
1895 uint64_t pe,
1896 uint64_t addr, unsigned count,
1897 uint32_t incr, uint32_t flags);
1898 void (*set_pages)(struct radeon_device *rdev,
1899 struct radeon_ib *ib,
1900 uint64_t pe,
1901 uint64_t addr, unsigned count,
1902 uint32_t incr, uint32_t flags);
1903 void (*pad_ib)(struct radeon_ib *ib);
1904 } vm;
1905 /* ring specific callbacks */
1906 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS8];
1907 /* irqs */
1908 struct {
1909 int (*set)(struct radeon_device *rdev);
1910 int (*process)(struct radeon_device *rdev);
1911 } irq;
1912 /* displays */
1913 struct {
1914 /* display watermarks */
1915 void (*bandwidth_update)(struct radeon_device *rdev);
1916 /* get frame count */
1917 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1918 /* wait for vblank */
1919 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1920 /* set backlight level */
1921 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1922 /* get backlight level */
1923 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1924 /* audio callbacks */
1925 void (*hdmi_enable)(struct drm_encoder *encoder, bool_Bool enable);
1926 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1927 } display;
1928 /* copy functions for bo handling */
1929 struct {
1930 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1931 uint64_t src_offset,
1932 uint64_t dst_offset,
1933 unsigned num_gpu_pages,
1934 struct dma_resv *resv);
1935 u32 blit_ring_index;
1936 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1937 uint64_t src_offset,
1938 uint64_t dst_offset,
1939 unsigned num_gpu_pages,
1940 struct dma_resv *resv);
1941 u32 dma_ring_index;
1942 /* method used for bo copy */
1943 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1944 uint64_t src_offset,
1945 uint64_t dst_offset,
1946 unsigned num_gpu_pages,
1947 struct dma_resv *resv);
1948 /* ring used for bo copies */
1949 u32 copy_ring_index;
1950 } copy;
1951 /* surfaces */
1952 struct {
1953 int (*set_reg)(struct radeon_device *rdev, int reg,
1954 uint32_t tiling_flags, uint32_t pitch,
1955 uint32_t offset, uint32_t obj_size);
1956 void (*clear_reg)(struct radeon_device *rdev, int reg);
1957 } surface;
1958 /* hotplug detect */
1959 struct {
1960 void (*init)(struct radeon_device *rdev);
1961 void (*fini)(struct radeon_device *rdev);
1962 bool_Bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1963 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1964 } hpd;
1965 /* static power management */
1966 struct {
1967 void (*misc)(struct radeon_device *rdev);
1968 void (*prepare)(struct radeon_device *rdev);
1969 void (*finish)(struct radeon_device *rdev);
1970 void (*init_profile)(struct radeon_device *rdev);
1971 void (*get_dynpm_state)(struct radeon_device *rdev);
1972 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1973 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1974 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1975 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1976 int (*get_pcie_lanes)(struct radeon_device *rdev);
1977 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1978 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1979 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1980 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1981 int (*get_temperature)(struct radeon_device *rdev);
1982 } pm;
1983 /* dynamic power management */
1984 struct {
1985 int (*init)(struct radeon_device *rdev);
1986 void (*setup_asic)(struct radeon_device *rdev);
1987 int (*enable)(struct radeon_device *rdev);
1988 int (*late_enable)(struct radeon_device *rdev);
1989 void (*disable)(struct radeon_device *rdev);
1990 int (*pre_set_power_state)(struct radeon_device *rdev);
1991 int (*set_power_state)(struct radeon_device *rdev);
1992 void (*post_set_power_state)(struct radeon_device *rdev);
1993 void (*display_configuration_changed)(struct radeon_device *rdev);
1994 void (*fini)(struct radeon_device *rdev);
1995 u32 (*get_sclk)(struct radeon_device *rdev, bool_Bool low);
1996 u32 (*get_mclk)(struct radeon_device *rdev, bool_Bool low);
1997 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1998 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1999 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
2000 bool_Bool (*vblank_too_short)(struct radeon_device *rdev);
2001 void (*powergate_uvd)(struct radeon_device *rdev, bool_Bool gate);
2002 void (*enable_bapm)(struct radeon_device *rdev, bool_Bool enable);
2003 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2004 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2005 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2006 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2007 u32 (*get_current_sclk)(struct radeon_device *rdev);
2008 u32 (*get_current_mclk)(struct radeon_device *rdev);
2009 } dpm;
2010 /* pageflipping */
2011 struct {
2012 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool_Bool async);
2013 bool_Bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2014 } pflip;
2015};
2016
2017/*
2018 * Asic structures
2019 */
2020struct r100_asic {
2021 const unsigned *reg_safe_bm;
2022 unsigned reg_safe_bm_size;
2023 u32 hdp_cntl;
2024};
2025
2026struct r300_asic {
2027 const unsigned *reg_safe_bm;
2028 unsigned reg_safe_bm_size;
2029 u32 resync_scratch;
2030 u32 hdp_cntl;
2031};
2032
2033struct r600_asic {
2034 unsigned max_pipes;
2035 unsigned max_tile_pipes;
2036 unsigned max_simds;
2037 unsigned max_backends;
2038 unsigned max_gprs;
2039 unsigned max_threads;
2040 unsigned max_stack_entries;
2041 unsigned max_hw_contexts;
2042 unsigned max_gs_threads;
2043 unsigned sx_max_export_size;
2044 unsigned sx_max_export_pos_size;
2045 unsigned sx_max_export_smx_size;
2046 unsigned sq_num_cf_insts;
2047 unsigned tiling_nbanks;
2048 unsigned tiling_npipes;
2049 unsigned tiling_group_size;
2050 unsigned tile_config;
2051 unsigned backend_map;
2052 unsigned active_simds;
2053};
2054
2055struct rv770_asic {
2056 unsigned max_pipes;
2057 unsigned max_tile_pipes;
2058 unsigned max_simds;
2059 unsigned max_backends;
2060 unsigned max_gprs;
2061 unsigned max_threads;
2062 unsigned max_stack_entries;
2063 unsigned max_hw_contexts;
2064 unsigned max_gs_threads;
2065 unsigned sx_max_export_size;
2066 unsigned sx_max_export_pos_size;
2067 unsigned sx_max_export_smx_size;
2068 unsigned sq_num_cf_insts;
2069 unsigned sx_num_of_sets;
2070 unsigned sc_prim_fifo_size;
2071 unsigned sc_hiz_tile_fifo_size;
2072 unsigned sc_earlyz_tile_fifo_fize;
2073 unsigned tiling_nbanks;
2074 unsigned tiling_npipes;
2075 unsigned tiling_group_size;
2076 unsigned tile_config;
2077 unsigned backend_map;
2078 unsigned active_simds;
2079};
2080
2081struct evergreen_asic {
2082 unsigned num_ses;
2083 unsigned max_pipes;
2084 unsigned max_tile_pipes;
2085 unsigned max_simds;
2086 unsigned max_backends;
2087 unsigned max_gprs;
2088 unsigned max_threads;
2089 unsigned max_stack_entries;
2090 unsigned max_hw_contexts;
2091 unsigned max_gs_threads;
2092 unsigned sx_max_export_size;
2093 unsigned sx_max_export_pos_size;
2094 unsigned sx_max_export_smx_size;
2095 unsigned sq_num_cf_insts;
2096 unsigned sx_num_of_sets;
2097 unsigned sc_prim_fifo_size;
2098 unsigned sc_hiz_tile_fifo_size;
2099 unsigned sc_earlyz_tile_fifo_size;
2100 unsigned tiling_nbanks;
2101 unsigned tiling_npipes;
2102 unsigned tiling_group_size;
2103 unsigned tile_config;
2104 unsigned backend_map;
2105 unsigned active_simds;
2106};
2107
2108struct cayman_asic {
2109 unsigned max_shader_engines;
2110 unsigned max_pipes_per_simd;
2111 unsigned max_tile_pipes;
2112 unsigned max_simds_per_se;
2113 unsigned max_backends_per_se;
2114 unsigned max_texture_channel_caches;
2115 unsigned max_gprs;
2116 unsigned max_threads;
2117 unsigned max_gs_threads;
2118 unsigned max_stack_entries;
2119 unsigned sx_num_of_sets;
2120 unsigned sx_max_export_size;
2121 unsigned sx_max_export_pos_size;
2122 unsigned sx_max_export_smx_size;
2123 unsigned max_hw_contexts;
2124 unsigned sq_num_cf_insts;
2125 unsigned sc_prim_fifo_size;
2126 unsigned sc_hiz_tile_fifo_size;
2127 unsigned sc_earlyz_tile_fifo_size;
2128
2129 unsigned num_shader_engines;
2130 unsigned num_shader_pipes_per_simd;
2131 unsigned num_tile_pipes;
2132 unsigned num_simds_per_se;
2133 unsigned num_backends_per_se;
2134 unsigned backend_disable_mask_per_asic;
2135 unsigned backend_map;
2136 unsigned num_texture_channel_caches;
2137 unsigned mem_max_burst_length_bytes;
2138 unsigned mem_row_size_in_kb;
2139 unsigned shader_engine_tile_size;
2140 unsigned num_gpus;
2141 unsigned multi_gpu_tile_size;
2142
2143 unsigned tile_config;
2144 unsigned active_simds;
2145};
2146
2147struct si_asic {
2148 unsigned max_shader_engines;
2149 unsigned max_tile_pipes;
2150 unsigned max_cu_per_sh;
2151 unsigned max_sh_per_se;
2152 unsigned max_backends_per_se;
2153 unsigned max_texture_channel_caches;
2154 unsigned max_gprs;
2155 unsigned max_gs_threads;
2156 unsigned max_hw_contexts;
2157 unsigned sc_prim_fifo_size_frontend;
2158 unsigned sc_prim_fifo_size_backend;
2159 unsigned sc_hiz_tile_fifo_size;
2160 unsigned sc_earlyz_tile_fifo_size;
2161
2162 unsigned num_tile_pipes;
2163 unsigned backend_enable_mask;
2164 unsigned backend_disable_mask_per_asic;
2165 unsigned backend_map;
2166 unsigned num_texture_channel_caches;
2167 unsigned mem_max_burst_length_bytes;
2168 unsigned mem_row_size_in_kb;
2169 unsigned shader_engine_tile_size;
2170 unsigned num_gpus;
2171 unsigned multi_gpu_tile_size;
2172
2173 unsigned tile_config;
2174 uint32_t tile_mode_array[32];
2175 uint32_t active_cus;
2176};
2177
2178struct cik_asic {
2179 unsigned max_shader_engines;
2180 unsigned max_tile_pipes;
2181 unsigned max_cu_per_sh;
2182 unsigned max_sh_per_se;
2183 unsigned max_backends_per_se;
2184 unsigned max_texture_channel_caches;
2185 unsigned max_gprs;
2186 unsigned max_gs_threads;
2187 unsigned max_hw_contexts;
2188 unsigned sc_prim_fifo_size_frontend;
2189 unsigned sc_prim_fifo_size_backend;
2190 unsigned sc_hiz_tile_fifo_size;
2191 unsigned sc_earlyz_tile_fifo_size;
2192
2193 unsigned num_tile_pipes;
2194 unsigned backend_enable_mask;
2195 unsigned backend_disable_mask_per_asic;
2196 unsigned backend_map;
2197 unsigned num_texture_channel_caches;
2198 unsigned mem_max_burst_length_bytes;
2199 unsigned mem_row_size_in_kb;
2200 unsigned shader_engine_tile_size;
2201 unsigned num_gpus;
2202 unsigned multi_gpu_tile_size;
2203
2204 unsigned tile_config;
2205 uint32_t tile_mode_array[32];
2206 uint32_t macrotile_mode_array[16];
2207 uint32_t active_cus;
2208};
2209
2210union radeon_asic_config {
2211 struct r300_asic r300;
2212 struct r100_asic r100;
2213 struct r600_asic r600;
2214 struct rv770_asic rv770;
2215 struct evergreen_asic evergreen;
2216 struct cayman_asic cayman;
2217 struct si_asic si;
2218 struct cik_asic cik;
2219};
2220
2221/*
2222 * asic initizalization from radeon_asic.c
2223 */
2224void radeon_agp_disable(struct radeon_device *rdev);
2225int radeon_asic_init(struct radeon_device *rdev);
2226
2227
2228/*
2229 * IOCTL.
2230 */
2231int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *filp);
2233int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *filp);
2235int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2236 struct drm_file *filp);
2237int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2238 struct drm_file *file_priv);
2239int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2240 struct drm_file *file_priv);
2241int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *file_priv);
2243int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *file_priv);
2245int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *filp);
2247int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
2249int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *filp);
2251int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2252 struct drm_file *filp);
2253int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2254 struct drm_file *filp);
2255int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2256 struct drm_file *filp);
2257int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2258int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2259 struct drm_file *filp);
2260int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2261 struct drm_file *filp);
2262
2263/* VRAM scratch page for HDP bug, default vram page */
2264struct r600_vram_scratch {
2265 struct radeon_bo *robj;
2266 volatile uint32_t *ptr;
2267 u64 gpu_addr;
2268};
2269
2270/*
2271 * ACPI
2272 */
2273struct radeon_atif_notification_cfg {
2274 bool_Bool enabled;
2275 int command_code;
2276};
2277
2278struct radeon_atif_notifications {
2279 bool_Bool display_switch;
2280 bool_Bool expansion_mode_change;
2281 bool_Bool thermal_state;
2282 bool_Bool forced_power_state;
2283 bool_Bool system_power_state;
2284 bool_Bool display_conf_change;
2285 bool_Bool px_gfx_switch;
2286 bool_Bool brightness_change;
2287 bool_Bool dgpu_display_event;
2288};
2289
2290struct radeon_atif_functions {
2291 bool_Bool system_params;
2292 bool_Bool sbios_requests;
2293 bool_Bool select_active_disp;
2294 bool_Bool lid_state;
2295 bool_Bool get_tv_standard;
2296 bool_Bool set_tv_standard;
2297 bool_Bool get_panel_expansion_mode;
2298 bool_Bool set_panel_expansion_mode;
2299 bool_Bool temperature_change;
2300 bool_Bool graphics_device_types;
2301};
2302
2303struct radeon_atif {
2304 struct radeon_atif_notifications notifications;
2305 struct radeon_atif_functions functions;
2306 struct radeon_atif_notification_cfg notification_cfg;
2307 struct radeon_encoder *encoder_for_bl;
2308};
2309
2310struct radeon_atcs_functions {
2311 bool_Bool get_ext_state;
2312 bool_Bool pcie_perf_req;
2313 bool_Bool pcie_dev_rdy;
2314 bool_Bool pcie_bus_width;
2315};
2316
2317struct radeon_atcs {
2318 struct radeon_atcs_functions functions;
2319};
2320
2321/*
2322 * Core structure, functions and helpers.
2323 */
2324typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2325typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2326
2327struct radeon_device {
2328 struct device self;
2329 struct device *dev;
2330 struct drm_device *ddev;
2331 struct pci_dev *pdev;
2332 struct rwlock exclusive_lock;
2333
2334 pci_chipset_tag_t pc;
2335 pcitag_t pa_tag;
2336 pci_intr_handle_t intrh;
2337 bus_space_tag_t iot;
2338 bus_space_tag_t memt;
2339 bus_dma_tag_t dmat;
2340 void *irqh;
2341
2342 void (*switchcb)(void *, int, int);
2343 void *switchcbarg;
2344 void *switchcookie;
2345 struct task switchtask;
2346 struct rasops_info ro;
2347 int console;
2348 int primary;
2349
2350 struct task burner_task;
2351 int burner_fblank;
2352
2353#ifdef __sparc64__
2354 struct sunfb sf;
2355 bus_size_t fb_offset;
2356 bus_space_handle_t memh;
2357#endif
2358
2359 unsigned long fb_aper_offset;
2360 unsigned long fb_aper_size;
2361
2362 /* ASIC */
2363 union radeon_asic_config config;
2364 enum radeon_family family;
2365 unsigned long flags;
2366 int usec_timeout;
2367 enum radeon_pll_errata pll_errata;
2368 int num_gb_pipes;
2369 int num_z_pipes;
2370 int disp_priority;
2371 /* BIOS */
2372 uint8_t *bios;
2373 bool_Bool is_atom_bios;
2374 uint16_t bios_header_start;
2375 struct radeon_bo *stolen_vga_memory;
2376 /* Register mmio */
2377 resource_size_t rmmio_base;
2378 resource_size_t rmmio_size;
2379 /* protects concurrent MM_INDEX/DATA based register access */
2380 spinlock_t mmio_idx_lock;
2381 /* protects concurrent SMC based register access */
2382 spinlock_t smc_idx_lock;
2383 /* protects concurrent PLL register access */
2384 spinlock_t pll_idx_lock;
2385 /* protects concurrent MC register access */
2386 spinlock_t mc_idx_lock;
2387 /* protects concurrent PCIE register access */
2388 spinlock_t pcie_idx_lock;
2389 /* protects concurrent PCIE_PORT register access */
2390 spinlock_t pciep_idx_lock;
2391 /* protects concurrent PIF register access */
2392 spinlock_t pif_idx_lock;
2393 /* protects concurrent CG register access */
2394 spinlock_t cg_idx_lock;
2395 /* protects concurrent UVD register access */
2396 spinlock_t uvd_idx_lock;
2397 /* protects concurrent RCU register access */
2398 spinlock_t rcu_idx_lock;
2399 /* protects concurrent DIDT register access */
2400 spinlock_t didt_idx_lock;
2401 /* protects concurrent ENDPOINT (audio) register access */
2402 spinlock_t end_idx_lock;
2403 bus_space_handle_t rmmio_bsh;
2404 void __iomem *rmmio;
2405 radeon_rreg_t mc_rreg;
2406 radeon_wreg_t mc_wreg;
2407 radeon_rreg_t pll_rreg;
2408 radeon_wreg_t pll_wreg;
2409 uint32_t pcie_reg_mask;
2410 radeon_rreg_t pciep_rreg;
2411 radeon_wreg_t pciep_wreg;
2412 /* io port */
2413 bus_space_handle_t rio_mem;
2414 resource_size_t rio_mem_size;
2415 struct radeon_clock clock;
2416 struct radeon_mc mc;
2417 struct radeon_gart gart;
2418 struct radeon_mode_info mode_info;
2419 struct radeon_scratch scratch;
2420 struct radeon_doorbell doorbell;
2421 struct radeon_mman mman;
2422 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS8];
2423 wait_queue_head_t fence_queue;
2424 u64 fence_context;
2425 struct rwlock ring_lock;
2426 struct radeon_ring ring[RADEON_NUM_RINGS8];
2427 bool_Bool ib_pool_ready;
2428 struct radeon_sa_manager ring_tmp_bo;
2429 struct radeon_irq irq;
2430 struct radeon_asic *asic;
2431 struct radeon_gem gem;
2432 struct radeon_pm pm;
2433 struct radeon_uvd uvd;
2434 struct radeon_vce vce;
2435 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH8];
2436 struct radeon_wb wb;
2437 struct radeon_dummy_page dummy_page;
2438 bool_Bool shutdown;
2439 bool_Bool need_swiotlb;
2440 bool_Bool accel_working;
2441 bool_Bool fastfb_working; /* IGP feature*/
2442 bool_Bool needs_reset, in_reset;
2443 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES8];
2444 const struct firmware *me_fw; /* all family ME firmware */
2445 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2446 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2447 const struct firmware *mc_fw; /* NI MC firmware */
2448 const struct firmware *ce_fw; /* SI CE firmware */
2449 const struct firmware *mec_fw; /* CIK MEC firmware */
2450 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2451 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2452 const struct firmware *smc_fw; /* SMC firmware */
2453 const struct firmware *uvd_fw; /* UVD firmware */
2454 const struct firmware *vce_fw; /* VCE firmware */
2455 bool_Bool new_fw;
2456 struct r600_vram_scratch vram_scratch;
2457 int msi_enabled; /* msi enabled */
2458 struct r600_ih ih; /* r6/700 interrupt ring */
2459 struct radeon_rlc rlc;
2460 struct radeon_mec mec;
2461 struct delayed_work hotplug_work;
2462 struct work_struct dp_work;
2463 struct work_struct audio_work;
2464 int num_crtc; /* number of crtcs */
2465 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2466 bool_Bool has_uvd;
2467 bool_Bool has_vce;
2468 struct r600_audio audio; /* audio stuff */
2469 struct notifier_block acpi_nb;
2470 /* only one userspace can use Hyperz features or CMASK at a time */
2471 struct drm_file *hyperz_filp;
2472 struct drm_file *cmask_filp;
2473 /* i2c buses */
2474 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS16];
2475 /* debugfs */
2476 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS32];
2477 unsigned debugfs_count;
2478 /* virtual memory */
2479 struct radeon_vm_manager vm_manager;
2480 struct rwlock gpu_clock_mutex;
2481 /* memory stats */
2482 atomic64_t vram_usage;
2483 atomic64_t gtt_usage;
2484 atomic64_t num_bytes_moved;
2485 atomic_t gpu_reset_counter;
2486 /* ACPI interface */
2487 struct radeon_atif atif;
2488 struct radeon_atcs atcs;
2489 /* srbm instance registers */
2490 struct rwlock srbm_mutex;
2491 /* clock, powergating flags */
2492 u32 cg_flags;
2493 u32 pg_flags;
2494
2495 struct dev_pm_domain vga_pm_domain;
2496 bool_Bool have_disp_power_ref;
2497 u32 px_quirk_flags;
2498
2499 /* tracking pinned memory */
2500 u64 vram_pin_size;
2501 u64 gart_pin_size;
2502};
2503
2504bool_Bool radeon_is_px(struct drm_device *dev);
2505int radeon_device_init(struct radeon_device *rdev,
2506 struct drm_device *ddev,
2507 struct pci_dev *pdev,
2508 uint32_t flags);
2509void radeon_device_fini(struct radeon_device *rdev);
2510int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2511
2512#define RADEON_MIN_MMIO_SIZE0x10000 0x10000
2513
2514uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2515void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2516static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2517 bool_Bool always_indirect)
2518{
2519 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2520 if ((reg
37.1
'reg' is >= field 'rmmio_size'
37.1
'reg' is >= field 'rmmio_size'
37.1
'reg' is >= field 'rmmio_size'
 < rdev->rmmio_size || reg
20.1
'reg' is < RADEON_MIN_MMIO_SIZE
37.2
'reg' is < RADEON_MIN_MMIO_SIZE
20.1
'reg' is < RADEON_MIN_MMIO_SIZE
37.2
'reg' is < RADEON_MIN_MMIO_SIZE
20.1
'reg' is < RADEON_MIN_MMIO_SIZE
37.2
'reg' is < RADEON_MIN_MMIO_SIZE
 < RADEON_MIN_MMIO_SIZE0x10000) && !always_indirect
20.2
'always_indirect' is false
30.1
'always_indirect' is false
37.3
'always_indirect' is false
20.2
'always_indirect' is false
30.1
'always_indirect' is false
37.3
'always_indirect' is false
20.2
'always_indirect' is false
30.1
'always_indirect' is false
37.3
'always_indirect' is false
)
20
←
Assuming 'reg' is >= field 'rmmio_size'
→
21
←
Taking true branch
→
30
←
Assuming 'reg' is < field 'rmmio_size'
→
31
←
Taking true branch
→
38
←
Taking true branch
→
2521 return readl(((void __iomem *)rdev->rmmio) + reg)ioread32(((void *)rdev->rmmio) + reg);
22
←
Returning without writing to 'rdev->family', which participates in a condition later
→
23
←
Returning without writing to 'rdev->smc_fw'
→
32
←
Returning without writing to 'rdev->family', which participates in a condition later
→
33
←
Returning without writing to 'rdev->smc_fw'
→
39
←
Returning without writing to 'rdev->family', which participates in a condition later
→
40
←
Returning without writing to 'rdev->smc_fw'
→
2522 else
2523 return r100_mm_rreg_slow(rdev, reg);
2524}
2525static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2526 bool_Bool always_indirect)
2527{
2528 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE0x10000) && !always_indirect)
2529 writel(v, ((void __iomem *)rdev->rmmio) + reg)iowrite32(v, ((void *)rdev->rmmio) + reg);
2530 else
2531 r100_mm_wreg_slow(rdev, reg, v);
2532}
2533
2534u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2535void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2536
2537u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2538void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2539
2540/*
2541 * Cast helper
2542 */
2543extern const struct dma_fence_ops radeon_fence_ops;
2544
2545static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2546{
2547 struct radeon_fence *__f = container_of(f, struct radeon_fence, base)({ const __typeof( ((struct radeon_fence *)0)->base ) *__mptr
= (f); (struct radeon_fence *)( (char *)__mptr - __builtin_offsetof
(struct radeon_fence, base) );});
2548
2549 if (__f->base.ops == &radeon_fence_ops)
2550 return __f;
2551
2552 return NULL((void *)0);
2553}
2554
2555/*
2556 * Registers read & write functions.
2557 */
2558#define RREG8(reg)ioread8((rdev->rmmio) + (reg)) readb((rdev->rmmio) + (reg))ioread8((rdev->rmmio) + (reg))
2559#define WREG8(reg, v)iowrite8(v, (rdev->rmmio) + (reg)) writeb(v, (rdev->rmmio) + (reg))iowrite8(v, (rdev->rmmio) + (reg))
2560#define RREG16(reg)ioread16((rdev->rmmio) + (reg)) readw((rdev->rmmio) + (reg))ioread16((rdev->rmmio) + (reg))
2561#define WREG16(reg, v)iowrite16(v, (rdev->rmmio) + (reg)) writew(v, (rdev->rmmio) + (reg))iowrite16(v, (rdev->rmmio) + (reg))
2562#define RREG32(reg)r100_mm_rreg(rdev, (reg), 0) r100_mm_rreg(rdev, (reg), false0)
2563#define RREG32_IDX(reg)r100_mm_rreg(rdev, (reg), 1) r100_mm_rreg(rdev, (reg), true1)
2564#define DREG32(reg)do { } while(0) pr_info("REGISTER: " #reg " : 0x%08X\n", \do { } while(0)
2565 r100_mm_rreg(rdev, (reg), false))do { } while(0)
2566#define WREG32(reg, v)r100_mm_wreg(rdev, (reg), (v), 0) r100_mm_wreg(rdev, (reg), (v), false0)
2567#define WREG32_IDX(reg, v)r100_mm_wreg(rdev, (reg), (v), 1) r100_mm_wreg(rdev, (reg), (v), true1)
2568#define REG_SET(FIELD, v)(((v) << FIELD_SHIFT) & FIELD_MASK) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2569#define REG_GET(FIELD, v)(((v) << FIELD_SHIFT) & FIELD_MASK) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2570#define RREG32_PLL(reg)rdev->pll_rreg(rdev, (reg)) rdev->pll_rreg(rdev, (reg))
2571#define WREG32_PLL(reg, v)rdev->pll_wreg(rdev, (reg), (v)) rdev->pll_wreg(rdev, (reg), (v))
2572#define RREG32_MC(reg)rdev->mc_rreg(rdev, (reg)) rdev->mc_rreg(rdev, (reg))
2573#define WREG32_MC(reg, v)rdev->mc_wreg(rdev, (reg), (v)) rdev->mc_wreg(rdev, (reg), (v))
2574#define RREG32_PCIE(reg)rv370_pcie_rreg(rdev, (reg)) rv370_pcie_rreg(rdev, (reg))
2575#define WREG32_PCIE(reg, v)rv370_pcie_wreg(rdev, (reg), (v)) rv370_pcie_wreg(rdev, (reg), (v))
2576#define RREG32_PCIE_PORT(reg)rdev->pciep_rreg(rdev, (reg)) rdev->pciep_rreg(rdev, (reg))
2577#define WREG32_PCIE_PORT(reg, v)rdev->pciep_wreg(rdev, (reg), (v)) rdev->pciep_wreg(rdev, (reg), (v))
2578#define RREG32_SMC(reg)tn_smc_rreg(rdev, (reg)) tn_smc_rreg(rdev, (reg))
2579#define WREG32_SMC(reg, v)tn_smc_wreg(rdev, (reg), (v)) tn_smc_wreg(rdev, (reg), (v))
2580#define RREG32_RCU(reg)r600_rcu_rreg(rdev, (reg)) r600_rcu_rreg(rdev, (reg))
2581#define WREG32_RCU(reg, v)r600_rcu_wreg(rdev, (reg), (v)) r600_rcu_wreg(rdev, (reg), (v))
2582#define RREG32_CG(reg)eg_cg_rreg(rdev, (reg)) eg_cg_rreg(rdev, (reg))
2583#define WREG32_CG(reg, v)eg_cg_wreg(rdev, (reg), (v)) eg_cg_wreg(rdev, (reg), (v))
2584#define RREG32_PIF_PHY0(reg)eg_pif_phy0_rreg(rdev, (reg)) eg_pif_phy0_rreg(rdev, (reg))
2585#define WREG32_PIF_PHY0(reg, v)eg_pif_phy0_wreg(rdev, (reg), (v)) eg_pif_phy0_wreg(rdev, (reg), (v))
2586#define RREG32_PIF_PHY1(reg)eg_pif_phy1_rreg(rdev, (reg)) eg_pif_phy1_rreg(rdev, (reg))
2587#define WREG32_PIF_PHY1(reg, v)eg_pif_phy1_wreg(rdev, (reg), (v)) eg_pif_phy1_wreg(rdev, (reg), (v))
2588#define RREG32_UVD_CTX(reg)r600_uvd_ctx_rreg(rdev, (reg)) r600_uvd_ctx_rreg(rdev, (reg))
2589#define WREG32_UVD_CTX(reg, v)r600_uvd_ctx_wreg(rdev, (reg), (v)) r600_uvd_ctx_wreg(rdev, (reg), (v))
2590#define RREG32_DIDT(reg)cik_didt_rreg(rdev, (reg)) cik_didt_rreg(rdev, (reg))
2591#define WREG32_DIDT(reg, v)cik_didt_wreg(rdev, (reg), (v)) cik_didt_wreg(rdev, (reg), (v))
2592#define WREG32_P(reg, val, mask)do { uint32_t tmp_ = r100_mm_rreg(rdev, (reg), 0); tmp_ &=
(mask); tmp_ |= ((val) & ~(mask)); r100_mm_wreg(rdev, (reg
), (tmp_), 0); } while (0) \
2593 do { \
2594 uint32_t tmp_ = RREG32(reg)r100_mm_rreg(rdev, (reg), 0); \
2595 tmp_ &= (mask); \
2596 tmp_ |= ((val) & ~(mask)); \
2597 WREG32(reg, tmp_)r100_mm_wreg(rdev, (reg), (tmp_), 0); \
2598 } while (0)
2599#define WREG32_AND(reg, and)do { uint32_t tmp_ = r100_mm_rreg(rdev, (reg), 0); tmp_ &=
(and); tmp_ |= ((0) & ~(and)); r100_mm_wreg(rdev, (reg),
(tmp_), 0); } while (0) WREG32_P(reg, 0, and)do { uint32_t tmp_ = r100_mm_rreg(rdev, (reg), 0); tmp_ &=
(and); tmp_ |= ((0) & ~(and)); r100_mm_wreg(rdev, (reg),
(tmp_), 0); } while (0)
2600#define WREG32_OR(reg, or)do { uint32_t tmp_ = r100_mm_rreg(rdev, (reg), 0); tmp_ &=
(~(or)); tmp_ |= ((or) & ~(~(or))); r100_mm_wreg(rdev, (
reg), (tmp_), 0); } while (0) WREG32_P(reg, or, ~(or))do { uint32_t tmp_ = r100_mm_rreg(rdev, (reg), 0); tmp_ &=
(~(or)); tmp_ |= ((or) & ~(~(or))); r100_mm_wreg(rdev, (
reg), (tmp_), 0); } while (0)
2601#define WREG32_PLL_P(reg, val, mask)do { uint32_t tmp_ = rdev->pll_rreg(rdev, (reg)); tmp_ &=
(mask); tmp_ |= ((val) & ~(mask)); rdev->pll_wreg(rdev
, (reg), (tmp_)); } while (0) \
2602 do { \
2603 uint32_t tmp_ = RREG32_PLL(reg)rdev->pll_rreg(rdev, (reg)); \
2604 tmp_ &= (mask); \
2605 tmp_ |= ((val) & ~(mask)); \
2606 WREG32_PLL(reg, tmp_)rdev->pll_wreg(rdev, (reg), (tmp_)); \
2607 } while (0)
2608#define WREG32_SMC_P(reg, val, mask)do { uint32_t tmp_ = tn_smc_rreg(rdev, (reg)); tmp_ &= (mask
); tmp_ |= ((val) & ~(mask)); tn_smc_wreg(rdev, (reg), (tmp_
)); } while (0) \
2609 do { \
2610 uint32_t tmp_ = RREG32_SMC(reg)tn_smc_rreg(rdev, (reg)); \
2611 tmp_ &= (mask); \
2612 tmp_ |= ((val) & ~(mask)); \
2613 WREG32_SMC(reg, tmp_)tn_smc_wreg(rdev, (reg), (tmp_)); \
2614 } while (0)
2615#define DREG32_SYS(sqf, rdev, reg)seq_printf((sqf), "reg" " : 0x%08X\n", r100_mm_rreg((rdev), (
reg), 0)) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false0))
2616#define RREG32_IO(reg)r100_io_rreg(rdev, (reg)) r100_io_rreg(rdev, (reg))
2617#define WREG32_IO(reg, v)r100_io_wreg(rdev, (reg), (v)) r100_io_wreg(rdev, (reg), (v))
2618
2619#define RDOORBELL32(index)cik_mm_rdoorbell(rdev, (index)) cik_mm_rdoorbell(rdev, (index))
2620#define WDOORBELL32(index, v)cik_mm_wdoorbell(rdev, (index), (v)) cik_mm_wdoorbell(rdev, (index), (v))
2621
2622/*
2623 * Indirect registers accessors.
2624 * They used to be inlined, but this increases code size by ~65 kbytes.
2625 * Since each performs a pair of MMIO ops
2626 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2627 * the cost of call+ret is almost negligible. MMIO and locking
2628 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2629 */
2630uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2631void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2632u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2633void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2634u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2635void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2636u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2637void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2638u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2639void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2640u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2641void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2642u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2643void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2644u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2645void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2646
2647void r100_pll_errata_after_index(struct radeon_device *rdev);
2648
2649
2650/*
2651 * ASICs helpers.
2652 */
2653#define ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device
== 0x5969)) ((rdev->pdev->device == 0x515e) || \
2654 (rdev->pdev->device == 0x5969))
2655#define ASIC_IS_RV100(rdev)((rdev->family == CHIP_RV100) || (rdev->family == CHIP_RV200
) || (rdev->family == CHIP_RS100) || (rdev->family == CHIP_RS200
) || (rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280
) || (rdev->family == CHIP_RS300)) ((rdev->family == CHIP_RV100) || \
2656 (rdev->family == CHIP_RV200) || \
2657 (rdev->family == CHIP_RS100) || \
2658 (rdev->family == CHIP_RS200) || \
2659 (rdev->family == CHIP_RV250) || \
2660 (rdev->family == CHIP_RV280) || \
2661 (rdev->family == CHIP_RS300))
2662#define ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480)) ((rdev->family == CHIP_R300) || \
2663 (rdev->family == CHIP_RV350) || \
2664 (rdev->family == CHIP_R350) || \
2665 (rdev->family == CHIP_RV380) || \
2666 (rdev->family == CHIP_R420) || \
2667 (rdev->family == CHIP_R423) || \
2668 (rdev->family == CHIP_RV410) || \
2669 (rdev->family == CHIP_RS400) || \
2670 (rdev->family == CHIP_RS480))
2671#define ASIC_IS_X2(rdev)((rdev->ddev->pdev->device == 0x9441) || (rdev->ddev
->pdev->device == 0x9443) || (rdev->ddev->pdev->
device == 0x944B) || (rdev->ddev->pdev->device == 0x9506
) || (rdev->ddev->pdev->device == 0x9509) || (rdev->
ddev->pdev->device == 0x950F) || (rdev->ddev->pdev
->device == 0x689C) || (rdev->ddev->pdev->device ==
0x689D)) ((rdev->ddev->pdev->device == 0x9441) || \
2672 (rdev->ddev->pdev->device == 0x9443) || \
2673 (rdev->ddev->pdev->device == 0x944B) || \
2674 (rdev->ddev->pdev->device == 0x9506) || \
2675 (rdev->ddev->pdev->device == 0x9509) || \
2676 (rdev->ddev->pdev->device == 0x950F) || \
2677 (rdev->ddev->pdev->device == 0x689C) || \
2678 (rdev->ddev->pdev->device == 0x689D))
2679#define ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) ((rdev->family >= CHIP_RS600))
2680#define ASIC_IS_DCE2(rdev)((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690
) || (rdev->family == CHIP_RS740) || (rdev->family >=
CHIP_R600)) ((rdev->family == CHIP_RS600) || \
2681 (rdev->family == CHIP_RS690) || \
2682 (rdev->family == CHIP_RS740) || \
2683 (rdev->family >= CHIP_R600))
2684#define ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620)) ((rdev->family >= CHIP_RV620))
2685#define ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730)) ((rdev->family >= CHIP_RV730))
2686#define ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)) ((rdev->family >= CHIP_CEDAR))
2687#define ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
& RADEON_IS_IGP)) ((rdev->family >= CHIP_PALM) && \
2688 (rdev->flags & RADEON_IS_IGP))
2689#define ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)) ((rdev->family >= CHIP_BARTS))
2690#define ASIC_IS_DCE6(rdev)((rdev->family >= CHIP_ARUBA)) ((rdev->family >= CHIP_ARUBA))
2691#define ASIC_IS_DCE61(rdev)((rdev->family >= CHIP_ARUBA) && (rdev->flags
& RADEON_IS_IGP)) ((rdev->family >= CHIP_ARUBA) && \
2692 (rdev->flags & RADEON_IS_IGP))
2693#define ASIC_IS_DCE64(rdev)((rdev->family == CHIP_OLAND)) ((rdev->family == CHIP_OLAND))
2694#define ASIC_IS_NODCE(rdev)((rdev->family == CHIP_HAINAN)) ((rdev->family == CHIP_HAINAN))
2695#define ASIC_IS_DCE8(rdev)((rdev->family >= CHIP_BONAIRE)) ((rdev->family >= CHIP_BONAIRE))
2696#define ASIC_IS_DCE81(rdev)((rdev->family == CHIP_KAVERI)) ((rdev->family == CHIP_KAVERI))
2697#define ASIC_IS_DCE82(rdev)((rdev->family == CHIP_BONAIRE)) ((rdev->family == CHIP_BONAIRE))
2698#define ASIC_IS_DCE83(rdev)((rdev->family == CHIP_KABINI) || (rdev->family == CHIP_MULLINS
)) ((rdev->family == CHIP_KABINI) || \
2699 (rdev->family == CHIP_MULLINS))
2700
2701#define ASIC_IS_LOMBOK(rdev)((rdev->ddev->pdev->device == 0x6849) || (rdev->ddev
->pdev->device == 0x6850) || (rdev->ddev->pdev->
device == 0x6858) || (rdev->ddev->pdev->device == 0x6859
) || (rdev->ddev->pdev->device == 0x6840) || (rdev->
ddev->pdev->device == 0x6841) || (rdev->ddev->pdev
->device == 0x6842) || (rdev->ddev->pdev->device ==
0x6843)) ((rdev->ddev->pdev->device == 0x6849) || \
2702 (rdev->ddev->pdev->device == 0x6850) || \
2703 (rdev->ddev->pdev->device == 0x6858) || \
2704 (rdev->ddev->pdev->device == 0x6859) || \
2705 (rdev->ddev->pdev->device == 0x6840) || \
2706 (rdev->ddev->pdev->device == 0x6841) || \
2707 (rdev->ddev->pdev->device == 0x6842) || \
2708 (rdev->ddev->pdev->device == 0x6843))
2709
2710/*
2711 * BIOS helpers.
2712 */
2713#define RBIOS8(i)(rdev->bios[i]) (rdev->bios[i])
2714#define RBIOS16(i)((rdev->bios[i]) | ((rdev->bios[(i)+1]) << 8)) (RBIOS8(i)(rdev->bios[i]) | (RBIOS8((i)+1)(rdev->bios[(i)+1]) << 8))
2715#define RBIOS32(i)((((rdev->bios[i]) | ((rdev->bios[(i)+1]) << 8)))
| (((rdev->bios[(i)+2]) | ((rdev->bios[((i)+2)+1]) <<
8)) << 16)) ((RBIOS16(i)((rdev->bios[i]) | ((rdev->bios[(i)+1]) << 8))) | (RBIOS16((i)+2)((rdev->bios[(i)+2]) | ((rdev->bios[((i)+2)+1]) <<
8)) << 16))
2716
2717int radeon_combios_init(struct radeon_device *rdev);
2718void radeon_combios_fini(struct radeon_device *rdev);
2719int radeon_atombios_init(struct radeon_device *rdev);
2720void radeon_atombios_fini(struct radeon_device *rdev);
2721
2722
2723/*
2724 * RING helpers.
2725 */
2726
2727/**
2728 * radeon_ring_write - write a value to the ring
2729 *
2730 * @ring: radeon_ring structure holding ring information
2731 * @v: dword (dw) value to write
2732 *
2733 * Write a value to the requested ring buffer (all asics).
2734 */
2735static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2736{
2737 if (ring->count_dw <= 0)
2738 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n")__drm_err("radeon: writing more dwords to the ring than expected!\n"
);
2739
2740 ring->ring[ring->wptr++] = v;
2741 ring->wptr &= ring->ptr_mask;
2742 ring->count_dw--;
2743 ring->ring_free_dw--;
2744}
2745
2746/*
2747 * ASICs macro.
2748 */
2749#define radeon_init(rdev)(rdev)->asic->init((rdev)) (rdev)->asic->init((rdev))
2750#define radeon_fini(rdev)(rdev)->asic->fini((rdev)) (rdev)->asic->fini((rdev))
2751#define radeon_resume(rdev)(rdev)->asic->resume((rdev)) (rdev)->asic->resume((rdev))
2752#define radeon_suspend(rdev)(rdev)->asic->suspend((rdev)) (rdev)->asic->suspend((rdev))
2753#define radeon_cs_parse(rdev, r, p)(rdev)->asic->ring[(r)]->cs_parse((p)) (rdev)->asic->ring[(r)]->cs_parse((p))
2754#define radeon_vga_set_state(rdev, state)(rdev)->asic->vga_set_state((rdev), (state)) (rdev)->asic->vga_set_state((rdev), (state))
2755#define radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0) (rdev)->asic->asic_reset((rdev), false0)
2756#define radeon_gart_tlb_flush(rdev)(rdev)->asic->gart.tlb_flush((rdev)) (rdev)->asic->gart.tlb_flush((rdev))
2757#define radeon_gart_get_page_entry(a, f)(rdev)->asic->gart.get_page_entry((a), (f)) (rdev)->asic->gart.get_page_entry((a), (f))
2758#define radeon_gart_set_page(rdev, i, e)(rdev)->asic->gart.set_page((rdev), (i), (e)) (rdev)->asic->gart.set_page((rdev), (i), (e))
2759#define radeon_asic_vm_init(rdev)(rdev)->asic->vm.init((rdev)) (rdev)->asic->vm.init((rdev))
2760#define radeon_asic_vm_fini(rdev)(rdev)->asic->vm.fini((rdev)) (rdev)->asic->vm.fini((rdev))
2761#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count)((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src),
(count))) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2762#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags)((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr
), (count), (incr), (flags))) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2763#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags)((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr),
(count), (incr), (flags))) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2764#define radeon_asic_vm_pad_ib(rdev, ib)((rdev)->asic->vm.pad_ib((ib))) ((rdev)->asic->vm.pad_ib((ib)))
2765#define radeon_ring_start(rdev, r, cp)(rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2766#define radeon_ring_test(rdev, r, cp)(rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2767#define radeon_ib_test(rdev, r, cp)(rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2768#define radeon_ring_ib_execute(rdev, r, ib)(rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2769#define radeon_ring_ib_parse(rdev, r, ib)(rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2770#define radeon_ring_is_lockup(rdev, r, cp)(rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2771#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr)(rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r
), (vm_id), (pd_addr)) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2772#define radeon_ring_get_rptr(rdev, r)(rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r
)) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2773#define radeon_ring_get_wptr(rdev, r)(rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r
)) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2774#define radeon_ring_set_wptr(rdev, r)(rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r
)) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2775#define radeon_irq_set(rdev)(rdev)->asic->irq.set((rdev)) (rdev)->asic->irq.set((rdev))
2776#define radeon_irq_process(rdev)(rdev)->asic->irq.process((rdev)) (rdev)->asic->irq.process((rdev))
2777#define radeon_get_vblank_counter(rdev, crtc)(rdev)->asic->display.get_vblank_counter((rdev), (crtc)
) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2778#define radeon_set_backlight_level(rdev, e, l)(rdev)->asic->display.set_backlight_level((e), (l)) (rdev)->asic->display.set_backlight_level((e), (l))
2779#define radeon_get_backlight_level(rdev, e)(rdev)->asic->display.get_backlight_level((e)) (rdev)->asic->display.get_backlight_level((e))
2780#define radeon_hdmi_enable(rdev, e, b)(rdev)->asic->display.hdmi_enable((e), (b)) (rdev)->asic->display.hdmi_enable((e), (b))
2781#define radeon_hdmi_setmode(rdev, e, m)(rdev)->asic->display.hdmi_setmode((e), (m)) (rdev)->asic->display.hdmi_setmode((e), (m))
2782#define radeon_fence_ring_emit(rdev, r, fence)(rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2783#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait)(rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp)
, (semaphore), (emit_wait)) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2784#define radeon_copy_blit(rdev, s, d, np, resv)(rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2785#define radeon_copy_dma(rdev, s, d, np, resv)(rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2786#define radeon_copy(rdev, s, d, np, resv)(rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2787#define radeon_copy_blit_ring_index(rdev)(rdev)->asic->copy.blit_ring_index (rdev)->asic->copy.blit_ring_index
2788#define radeon_copy_dma_ring_index(rdev)(rdev)->asic->copy.dma_ring_index (rdev)->asic->copy.dma_ring_index
2789#define radeon_copy_ring_index(rdev)(rdev)->asic->copy.copy_ring_index (rdev)->asic->copy.copy_ring_index
2790#define radeon_get_engine_clock(rdev)(rdev)->asic->pm.get_engine_clock((rdev)) (rdev)->asic->pm.get_engine_clock((rdev))
2791#define radeon_set_engine_clock(rdev, e)(rdev)->asic->pm.set_engine_clock((rdev), (e)) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2792#define radeon_get_memory_clock(rdev)(rdev)->asic->pm.get_memory_clock((rdev)) (rdev)->asic->pm.get_memory_clock((rdev))
2793#define radeon_set_memory_clock(rdev, e)(rdev)->asic->pm.set_memory_clock((rdev), (e)) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2794#define radeon_get_pcie_lanes(rdev)(rdev)->asic->pm.get_pcie_lanes((rdev)) (rdev)->asic->pm.get_pcie_lanes((rdev))
2795#define radeon_set_pcie_lanes(rdev, l)(rdev)->asic->pm.set_pcie_lanes((rdev), (l)) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2796#define radeon_set_clock_gating(rdev, e)(rdev)->asic->pm.set_clock_gating((rdev), (e)) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2797#define radeon_set_uvd_clocks(rdev, v, d)(rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2798#define radeon_set_vce_clocks(rdev, ev, ec)(rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2799#define radeon_get_temperature(rdev)(rdev)->asic->pm.get_temperature((rdev)) (rdev)->asic->pm.get_temperature((rdev))
2800#define radeon_set_surface_reg(rdev, r, f, p, o, s)((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (
o), (s))) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2801#define radeon_clear_surface_reg(rdev, r)((rdev)->asic->surface.clear_reg((rdev), (r))) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2802#define radeon_bandwidth_update(rdev)(rdev)->asic->display.bandwidth_update((rdev)) (rdev)->asic->display.bandwidth_update((rdev))
2803#define radeon_hpd_init(rdev)(rdev)->asic->hpd.init((rdev)) (rdev)->asic->hpd.init((rdev))
2804#define radeon_hpd_fini(rdev)(rdev)->asic->hpd.fini((rdev)) (rdev)->asic->hpd.fini((rdev))
2805#define radeon_hpd_sense(rdev, h)(rdev)->asic->hpd.sense((rdev), (h)) (rdev)->asic->hpd.sense((rdev), (h))
2806#define radeon_hpd_set_polarity(rdev, h)(rdev)->asic->hpd.set_polarity((rdev), (h)) (rdev)->asic->hpd.set_polarity((rdev), (h))
2807#define radeon_gui_idle(rdev)(rdev)->asic->gui_idle((rdev)) (rdev)->asic->gui_idle((rdev))
2808#define radeon_pm_misc(rdev)(rdev)->asic->pm.misc((rdev)) (rdev)->asic->pm.misc((rdev))
2809#define radeon_pm_prepare(rdev)(rdev)->asic->pm.prepare((rdev)) (rdev)->asic->pm.prepare((rdev))
2810#define radeon_pm_finish(rdev)(rdev)->asic->pm.finish((rdev)) (rdev)->asic->pm.finish((rdev))
2811#define radeon_pm_init_profile(rdev)(rdev)->asic->pm.init_profile((rdev)) (rdev)->asic->pm.init_profile((rdev))
2812#define radeon_pm_get_dynpm_state(rdev)(rdev)->asic->pm.get_dynpm_state((rdev)) (rdev)->asic->pm.get_dynpm_state((rdev))
2813#define radeon_page_flip(rdev, crtc, base, async)(rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (
async)) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2814#define radeon_page_flip_pending(rdev, crtc)(rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2815#define radeon_wait_for_vblank(rdev, crtc)(rdev)->asic->display.wait_for_vblank((rdev), (crtc)) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2816#define radeon_mc_wait_for_idle(rdev)(rdev)->asic->mc_wait_for_idle((rdev)) (rdev)->asic->mc_wait_for_idle((rdev))
2817#define radeon_get_xclk(rdev)(rdev)->asic->get_xclk((rdev)) (rdev)->asic->get_xclk((rdev))
2818#define radeon_get_gpu_clock_counter(rdev)(rdev)->asic->get_gpu_clock_counter((rdev)) (rdev)->asic->get_gpu_clock_counter((rdev))
2819#define radeon_get_allowed_info_register(rdev, r, v)(rdev)->asic->get_allowed_info_register((rdev), (r), (v
)) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2820#define radeon_dpm_init(rdev)rdev->asic->dpm.init((rdev)) rdev->asic->dpm.init((rdev))
2821#define radeon_dpm_setup_asic(rdev)rdev->asic->dpm.setup_asic((rdev)) rdev->asic->dpm.setup_asic((rdev))
2822#define radeon_dpm_enable(rdev)rdev->asic->dpm.enable((rdev)) rdev->asic->dpm.enable((rdev))
2823#define radeon_dpm_late_enable(rdev)rdev->asic->dpm.late_enable((rdev)) rdev->asic->dpm.late_enable((rdev))
2824#define radeon_dpm_disable(rdev)rdev->asic->dpm.disable((rdev)) rdev->asic->dpm.disable((rdev))
2825#define radeon_dpm_pre_set_power_state(rdev)rdev->asic->dpm.pre_set_power_state((rdev)) rdev->asic->dpm.pre_set_power_state((rdev))
2826#define radeon_dpm_set_power_state(rdev)rdev->asic->dpm.set_power_state((rdev)) rdev->asic->dpm.set_power_state((rdev))
2827#define radeon_dpm_post_set_power_state(rdev)rdev->asic->dpm.post_set_power_state((rdev)) rdev->asic->dpm.post_set_power_state((rdev))
2828#define radeon_dpm_display_configuration_changed(rdev)rdev->asic->dpm.display_configuration_changed((rdev)) rdev->asic->dpm.display_configuration_changed((rdev))
2829#define radeon_dpm_fini(rdev)rdev->asic->dpm.fini((rdev)) rdev->asic->dpm.fini((rdev))
2830#define radeon_dpm_get_sclk(rdev, l)rdev->asic->dpm.get_sclk((rdev), (l)) rdev->asic->dpm.get_sclk((rdev), (l))
2831#define radeon_dpm_get_mclk(rdev, l)rdev->asic->dpm.get_mclk((rdev), (l)) rdev->asic->dpm.get_mclk((rdev), (l))
2832#define radeon_dpm_print_power_state(rdev, ps)rdev->asic->dpm.print_power_state((rdev), (ps)) rdev->asic->dpm.print_power_state((rdev), (ps))
2833#define radeon_dpm_debugfs_print_current_performance_level(rdev, m)rdev->asic->dpm.debugfs_print_current_performance_level
((rdev), (m)) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2834#define radeon_dpm_force_performance_level(rdev, l)rdev->asic->dpm.force_performance_level((rdev), (l)) rdev->asic->dpm.force_performance_level((rdev), (l))
2835#define radeon_dpm_vblank_too_short(rdev)rdev->asic->dpm.vblank_too_short((rdev)) rdev->asic->dpm.vblank_too_short((rdev))
2836#define radeon_dpm_powergate_uvd(rdev, g)rdev->asic->dpm.powergate_uvd((rdev), (g)) rdev->asic->dpm.powergate_uvd((rdev), (g))
2837#define radeon_dpm_enable_bapm(rdev, e)rdev->asic->dpm.enable_bapm((rdev), (e)) rdev->asic->dpm.enable_bapm((rdev), (e))
2838#define radeon_dpm_get_current_sclk(rdev)rdev->asic->dpm.get_current_sclk((rdev)) rdev->asic->dpm.get_current_sclk((rdev))
2839#define radeon_dpm_get_current_mclk(rdev)rdev->asic->dpm.get_current_mclk((rdev)) rdev->asic->dpm.get_current_mclk((rdev))
2840
2841/* Common functions */
2842/* AGP */
2843extern int radeon_gpu_reset(struct radeon_device *rdev);
2844extern void radeon_pci_config_reset(struct radeon_device *rdev);
2845extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool_Bool hung);
2846extern void radeon_agp_disable(struct radeon_device *rdev);
2847extern int radeon_modeset_init(struct radeon_device *rdev);
2848extern void radeon_modeset_fini(struct radeon_device *rdev);
2849extern bool_Bool radeon_card_posted(struct radeon_device *rdev);
2850extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2851extern void radeon_update_display_priority(struct radeon_device *rdev);
2852extern bool_Bool radeon_boot_test_post_card(struct radeon_device *rdev);
2853extern void radeon_scratch_init(struct radeon_device *rdev);
2854extern void radeon_wb_fini(struct radeon_device *rdev);
2855extern int radeon_wb_init(struct radeon_device *rdev);
2856extern void radeon_wb_disable(struct radeon_device *rdev);
2857extern void radeon_surface_init(struct radeon_device *rdev);
2858extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2859extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2860extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2861extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2862extern bool_Bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2863extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2864 struct ttm_tt *ttm, uint64_t addr,
2865 uint32_t flags);
2866extern bool_Bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2867extern bool_Bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2868bool_Bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev, struct ttm_tt *ttm);
2869extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2870extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2871extern int radeon_resume_kms(struct drm_device *dev, bool_Bool resume, bool_Bool fbcon);
2872extern int radeon_suspend_kms(struct drm_device *dev, bool_Bool suspend,
2873 bool_Bool fbcon, bool_Bool freeze);
2874extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2875extern void radeon_program_register_sequence(struct radeon_device *rdev,
2876 const u32 *registers,
2877 const u32 array_size);
2878struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev);
2879
2880/*
2881 * vm
2882 */
2883int radeon_vm_manager_init(struct radeon_device *rdev);
2884void radeon_vm_manager_fini(struct radeon_device *rdev);
2885int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2886void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2887struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2888 struct radeon_vm *vm,
2889 struct list_head *head);
2890struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2891 struct radeon_vm *vm, int ring);
2892void radeon_vm_flush(struct radeon_device *rdev,
2893 struct radeon_vm *vm,
2894 int ring, struct radeon_fence *fence);
2895void radeon_vm_fence(struct radeon_device *rdev,
2896 struct radeon_vm *vm,
2897 struct radeon_fence *fence);
2898uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2899int radeon_vm_update_page_directory(struct radeon_device *rdev,
2900 struct radeon_vm *vm);
2901int radeon_vm_clear_freed(struct radeon_device *rdev,
2902 struct radeon_vm *vm);
2903int radeon_vm_clear_invalids(struct radeon_device *rdev,
2904 struct radeon_vm *vm);
2905int radeon_vm_bo_update(struct radeon_device *rdev,
2906 struct radeon_bo_va *bo_va,
2907 struct ttm_resource *mem);
2908void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2909 struct radeon_bo *bo);
2910struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2911 struct radeon_bo *bo);
2912struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2913 struct radeon_vm *vm,
2914 struct radeon_bo *bo);
2915int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2916 struct radeon_bo_va *bo_va,
2917 uint64_t offset,
2918 uint32_t flags);
2919void radeon_vm_bo_rmv(struct radeon_device *rdev,
2920 struct radeon_bo_va *bo_va);
2921
2922/* audio */
2923void r600_audio_update_hdmi(struct work_struct *work);
2924struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2925struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2926void r600_audio_enable(struct radeon_device *rdev,
2927 struct r600_audio_pin *pin,
2928 u8 enable_mask);
2929void dce6_audio_enable(struct radeon_device *rdev,
2930 struct r600_audio_pin *pin,
2931 u8 enable_mask);
2932
2933/*
2934 * R600 vram scratch functions
2935 */
2936int r600_vram_scratch_init(struct radeon_device *rdev);
2937void r600_vram_scratch_fini(struct radeon_device *rdev);
2938
2939/*
2940 * r600 cs checking helper
2941 */
2942unsigned r600_mip_minify(unsigned size, unsigned level);
2943bool_Bool r600_fmt_is_valid_color(u32 format);
2944bool_Bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2945int r600_fmt_get_blocksize(u32 format);
2946int r600_fmt_get_nblocksx(u32 format, u32 w);
2947int r600_fmt_get_nblocksy(u32 format, u32 h);
2948
2949/*
2950 * r600 functions used by radeon_encoder.c
2951 */
2952struct radeon_hdmi_acr {
2953 u32 clock;
2954
2955 int n_32khz;
2956 int cts_32khz;
2957
2958 int n_44_1khz;
2959 int cts_44_1khz;
2960
2961 int n_48khz;
2962 int cts_48khz;
2963
2964};
2965
2966extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2967
2968extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2969 u32 tiling_pipe_num,
2970 u32 max_rb_num,
2971 u32 total_max_rb_num,
2972 u32 enabled_rb_mask);
2973
2974/*
2975 * evergreen functions used by radeon_encoder.c
2976 */
2977
2978extern int ni_init_microcode(struct radeon_device *rdev);
2979extern int ni_mc_load_microcode(struct radeon_device *rdev);
2980
2981/* radeon_acpi.c */
2982#if defined(CONFIG_ACPI1)
2983extern int radeon_acpi_init(struct radeon_device *rdev);
2984extern void radeon_acpi_fini(struct radeon_device *rdev);
2985extern bool_Bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2986extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2987 u8 perf_req, bool_Bool advertise);
2988extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2989#else
2990static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2991static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2992#endif
2993
2994int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2995 struct radeon_cs_packet *pkt,
2996 unsigned idx);
2997bool_Bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2998void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2999 struct radeon_cs_packet *pkt);
3000int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3001 struct radeon_bo_list **cs_reloc,
3002 int nomm);
3003int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3004 uint32_t *vline_start_end,
3005 uint32_t *vline_status);
3006
3007/* interrupt control register helpers */
3008void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
3009 u32 reg, u32 mask,
3010 bool_Bool enable, const char *name,
3011 unsigned n);
3012
3013#include "radeon_object.h"
3014
3015#endif
←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var)) ((type)(__uintptr_t)(const void *)(var))
14#endif
15
16struct firmware {
17 size_t size;
18 const u8 *data;
19};
20
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23 struct device *device)
24{
25 int r;
26 struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27 M_WAITOK0x0001 | M_ZERO0x0008);
28 r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29 if (r != 0) {
57
←
Assuming 'r' is equal to 0
→
58
←
Taking false branch
→
65
←
Assuming 'r' is equal to 0
→
66
←
Taking false branch
→
73
←
Assuming 'r' is equal to 0
→
74
←
Taking false branch
→
82
←
Assuming 'r' is not equal to 0
→
83
←
Taking true branch
→
30 free(f, M_DRM145, sizeof(struct firmware));
31 *fw = NULL((void *)0);
84
←
Null pointer value stored to field 'smc_fw'
→
32 return -r;
33 } else {
34 *fw = f;
35 return 0;
59
←
Returning zero, which participates in a condition later
→
67
←
Returning zero, which participates in a condition later
→
75
←
Returning zero, which participates in a condition later
→
36 }
37}
38
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41 struct device *device)
42{
43 return request_firmware(fw, name, device);
44}
45
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47
48static inline void
49release_firmware(const struct firmware *fw)
50{
51 if (fw)
52 free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53 free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55
56#endif