/usr/src/sys/dev/pci/if

Bug Summary

File:	dev/pci/if_bge.c
Warning:	line 3950, column 9 Dereference of null pointer
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_bge.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/if_bge.c
1/*	$OpenBSD: if_bge.c,v 1.397 2022/01/09 05:42:46 jsg Exp $	*/

3/*
* Copyright (c) 2001 Wind River Systems
* Copyright (c) 1997, 1998, 1999, 2001
*	Bill Paul <wpaul@windriver.com>.  All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
*    must display the following acknowledgement:
*	This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
*    may be used to endorse or promote products derived from this software
*    without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: if_bge.c,v 1.25 2002/11/14 23:54:49 sam Exp $
*/

38/*
* Broadcom BCM57xx/BCM590x family ethernet driver for OpenBSD.
*
* Written by Bill Paul <wpaul@windriver.com>
* Senior Engineer, Wind River Systems
*/

45/*
* The Broadcom BCM5700 is based on technology originally developed by
* Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
* MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
* two on-board MIPS R4000 CPUs and can have as much as 16MB of external
* SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
* frames, highly configurable RX filtering, and 16 RX and TX queues
* (which, along with RX filter rules, can be used for QOS applications).
* Other features, such as TCP segmentation, may be available as part
* of value-added firmware updates. Unlike the Tigon I and Tigon II,
* firmware images can be stored in hardware and need not be compiled
* into the driver.
*
* The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
* function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
*
* The BCM5701 is a single-chip solution incorporating both the BCM5700
* MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
* does not support external SSRAM.
*
* Broadcom also produces a variation of the BCM5700 under the "Altima"
* brand name, which is functionally similar but lacks PCI-X support.
*
* Without external SSRAM, you can only have at most 4 TX rings,
* and the use of the mini RX ring is disabled. This seems to imply
* that these features are simply not available on the BCM5701. As a
* result, this driver does not implement any support for the mini RX
* ring.
*/

75#include "bpfilter.h"
76#include "vlan.h"

78#include <sys/param.h>
79#include <sys/systm.h>
80#include <sys/sockio.h>
81#include <sys/mbuf.h>
82#include <sys/malloc.h>
83#include <sys/kernel.h>
84#include <sys/device.h>
85#include <sys/timeout.h>
86#include <sys/socket.h>
87#include <sys/atomic.h>

89#include <net/if.h>
90#include <net/if_media.h>

92#include <netinet/in.h>
93#include <netinet/if_ether.h>

95#if NBPFILTER1 > 0
96#include <net/bpf.h>
97#endif

99#if defined(__sparc64__) || defined(__HAVE_FDT)
100#include <dev/ofw/openfirm.h>
101#endif

103#include <dev/pci/pcireg.h>
104#include <dev/pci/pcivar.h>
105#include <dev/pci/pcidevs.h>

107#include <dev/mii/mii.h>
108#include <dev/mii/miivar.h>
109#include <dev/mii/miidevs.h>
110#include <dev/mii/brgphyreg.h>

112#include <dev/pci/if_bgereg.h>

114#define ETHER_MIN_NOPAD(64 - 4)		(ETHER_MIN_LEN64 - ETHER_CRC_LEN4) /* i.e., 60 */

116const struct bge_revision * bge_lookup_rev(u_int32_t);
117int bge_can_use_msi(struct bge_softc *);
118int bge_probe(struct device *, void *, void *);
119void bge_attach(struct device *, struct device *, void *);
120int bge_detach(struct device *, int);
121int bge_activate(struct device *, int);

123struct cfattach bge_ca = {
sizeof(struct bge_softc), bge_probe, bge_attach, bge_detach,
bge_activate
126};

128struct cfdriver bge_cd = {
NULL((void *)0), "bge", DV_IFNET
130};

132void bge_txeof(struct bge_softc *);
133void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
134void bge_rxeof(struct bge_softc *);

136void bge_tick(void *);
137void bge_stats_update(struct bge_softc *);
138void bge_stats_update_regs(struct bge_softc *);
139int bge_cksum_pad(struct mbuf *);
140int bge_encap(struct bge_softc *, struct mbuf *, int *);
141int bge_compact_dma_runt(struct mbuf *);

143int bge_intr(void *);
144void bge_start(struct ifqueue *);
145int bge_ioctl(struct ifnet *, u_long, caddr_t);
146int bge_rxrinfo(struct bge_softc *, struct if_rxrinfo *);
147void bge_init(void *);
148void bge_stop_block(struct bge_softc *, bus_size_t, u_int32_t);
149void bge_stop(struct bge_softc *, int);
150void bge_watchdog(struct ifnet *);
151int bge_ifmedia_upd(struct ifnet *);
152void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);

154u_int8_t bge_nvram_getbyte(struct bge_softc *, int, u_int8_t *);
155int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
156u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *);
157int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);

159void bge_iff(struct bge_softc *);

161int bge_newbuf_jumbo(struct bge_softc *, int);
162int bge_init_rx_ring_jumbo(struct bge_softc *);
163void bge_fill_rx_ring_jumbo(struct bge_softc *);
164void bge_free_rx_ring_jumbo(struct bge_softc *);

166int bge_newbuf(struct bge_softc *, int);
167int bge_init_rx_ring_std(struct bge_softc *);
168void bge_rxtick(void *);
169void bge_fill_rx_ring_std(struct bge_softc *);
170void bge_free_rx_ring_std(struct bge_softc *);

172void bge_free_tx_ring(struct bge_softc *);
173int bge_init_tx_ring(struct bge_softc *);

175void bge_chipinit(struct bge_softc *);
176int bge_blockinit(struct bge_softc *);
177u_int32_t bge_dma_swap_options(struct bge_softc *);
178int bge_phy_addr(struct bge_softc *);

180u_int32_t bge_readmem_ind(struct bge_softc *, int);
181void bge_writemem_ind(struct bge_softc *, int, int);
182void bge_writereg_ind(struct bge_softc *, int, int);
183void bge_writembx(struct bge_softc *, int, int);

185int bge_miibus_readreg(struct device *, int, int);
186void bge_miibus_writereg(struct device *, int, int, int);
187void bge_miibus_statchg(struct device *);

189#define BGE_RESET_SHUTDOWN0	0
190#define BGE_RESET_START1		1
191#define BGE_RESET_SUSPEND2	2
192void bge_sig_post_reset(struct bge_softc *, int);
193void bge_sig_legacy(struct bge_softc *, int);
194void bge_sig_pre_reset(struct bge_softc *, int);
195void bge_stop_fw(struct bge_softc *, int);
196void bge_reset(struct bge_softc *);
197void bge_link_upd(struct bge_softc *);

199void bge_ape_lock_init(struct bge_softc *);
200void bge_ape_read_fw_ver(struct bge_softc *);
201int bge_ape_lock(struct bge_softc *, int);
202void bge_ape_unlock(struct bge_softc *, int);
203void bge_ape_send_event(struct bge_softc *, uint32_t);
204void bge_ape_driver_state_change(struct bge_softc *, int);

206#ifdef BGE_DEBUG
207#define DPRINTF(x)	do { if (bgedebug) printf x; } while (0)
208#define DPRINTFN(n,x)	do { if (bgedebug >= (n)) printf x; } while (0)
209int	bgedebug = 0;
210#else
211#define DPRINTF(x)
212#define DPRINTFN(n,x)
213#endif

215/*
* Various supported device vendors/types and their names. Note: the
* spec seems to indicate that the hardware still has Alteon's vendor
* ID burned into it, though it will always be overridden by the vendor
* ID in the EEPROM. Just to be safe, we cover all possibilities.
*/
221const struct pci_matchid bge_devices[] = {
{ PCI_VENDOR_ALTEON0x12ae, PCI_PRODUCT_ALTEON_BCM57000x0003 },
{ PCI_VENDOR_ALTEON0x12ae, PCI_PRODUCT_ALTEON_BCM57010x0004 },

{ PCI_VENDOR_ALTIMA0x173b, PCI_PRODUCT_ALTIMA_AC10000x03e8 },
{ PCI_VENDOR_ALTIMA0x173b, PCI_PRODUCT_ALTIMA_AC10010x03e9 },
{ PCI_VENDOR_ALTIMA0x173b, PCI_PRODUCT_ALTIMA_AC10030x03eb },
{ PCI_VENDOR_ALTIMA0x173b, PCI_PRODUCT_ALTIMA_AC91000x03ea },

{ PCI_VENDOR_APPLE0x106b, PCI_PRODUCT_APPLE_BCM57010x1645 },

{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57000x1644 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57010x1645 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57020x1646 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5702_ALT0x16c6 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5702X0x16a6 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57030x1647 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5703_ALT0x16c7 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5703X0x16a7 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5704C0x1648 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5704S0x16a8 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5704S_ALT0x1649 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57050x1653 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5705F0x166e },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5705K0x1654 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5705M0x165d },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5705M_ALT0x165e },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57140x1668 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5714S0x1669 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57150x1678 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5715S0x1679 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57170x1655 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5717C0x1665 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57180x1656 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57190x1657 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57200x165f },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57210x1659 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57220x165a },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57230x165b },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57250x1643 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57270x16f3 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57510x1677 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5751F0x167e },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5751M0x167d },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57520x1600 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5752M0x1601 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57530x16f7 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5753F0x16fe },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5753M0x16fd },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57540x167a },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5754M0x1672 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57550x167b },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5755M0x1673 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57560x1674 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57610x1681 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5761E0x1680 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5761S0x1688 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5761SE0x1689 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57620x1687 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57640x1684 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57800x166a },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5780S0x166b },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57810x16dd },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57820x1696 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57840x1698 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5785F0x16a0 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5785G0x1699 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57860x169a },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57870x169b },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5787F0x167f },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5787M0x1693 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57880x169c },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM57890x169d },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM59010x170d },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5901A20x170e },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5903M0x16ff },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM59060x1712 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM5906M0x1713 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577600x1690 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577610x16b0 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577620x1682 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577640x1642 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577650x16b4 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577660x1686 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577670x1683 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577800x1692 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577810x16b1 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577820x16b7 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577850x16b5 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577860x16b3 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577870x1641 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577880x1691 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577900x1694 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577910x16b2 },
{ PCI_VENDOR_BROADCOM0x14e4, PCI_PRODUCT_BROADCOM_BCM577950x16b6 },

{ PCI_VENDOR_FUJITSU0x10cf, PCI_PRODUCT_FUJITSU_PW008GE40x11a2 },
{ PCI_VENDOR_FUJITSU0x10cf, PCI_PRODUCT_FUJITSU_PW008GE50x11a1 },
{ PCI_VENDOR_FUJITSU0x10cf, PCI_PRODUCT_FUJITSU_PP250_450_LAN0x11cc },

{ PCI_VENDOR_SCHNEIDERKOCH0x1148, PCI_PRODUCT_SCHNEIDERKOCH_SK9D210x4400 },

{ PCI_VENDOR_3COM0x10b7, PCI_PRODUCT_3COM_3C9960x0003 }
324};

326#define BGE_IS_JUMBO_CAPABLE(sc)((sc)->bge_flags & 0x00000100)	((sc)->bge_flags & BGE_JUMBO_CAPABLE0x00000100)
327#define BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000)		((sc)->bge_flags & BGE_5700_FAMILY0x00010000)
328#define BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)		((sc)->bge_flags & BGE_5705_PLUS0x00001000)
329#define BGE_IS_5714_FAMILY(sc)((sc)->bge_flags & 0x00008000)		((sc)->bge_flags & BGE_5714_FAMILY0x00008000)
330#define BGE_IS_575X_PLUS(sc)((sc)->bge_flags & 0x00002000)		((sc)->bge_flags & BGE_575X_PLUS0x00002000)
331#define BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000)		((sc)->bge_flags & BGE_5755_PLUS0x00004000)
332#define BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)		((sc)->bge_flags & BGE_5717_PLUS0x00020000)
333#define BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000)		((sc)->bge_flags & BGE_57765_PLUS0x00040000)

335static const struct bge_revision {
u_int32_t		br_chipid;
const char		*br_name;
338} bge_revisions[] = {
{ BGE_CHIPID_BCM5700_A00x7000, "BCM5700 A0" },
{ BGE_CHIPID_BCM5700_A10x7001, "BCM5700 A1" },
{ BGE_CHIPID_BCM5700_B00x7100, "BCM5700 B0" },
{ BGE_CHIPID_BCM5700_B10x7101, "BCM5700 B1" },
{ BGE_CHIPID_BCM5700_B20x7102, "BCM5700 B2" },
{ BGE_CHIPID_BCM5700_B30x7103, "BCM5700 B3" },
{ BGE_CHIPID_BCM5700_ALTIMA0x7104, "BCM5700 Altima" },
{ BGE_CHIPID_BCM5700_C00x7200, "BCM5700 C0" },
{ BGE_CHIPID_BCM5701_A00x0000, "BCM5701 A0" },
{ BGE_CHIPID_BCM5701_B00x0100, "BCM5701 B0" },
{ BGE_CHIPID_BCM5701_B20x0102, "BCM5701 B2" },
{ BGE_CHIPID_BCM5701_B50x0105, "BCM5701 B5" },
/* the 5702 and 5703 share the same ASIC ID */
{ BGE_CHIPID_BCM5703_A00x1000, "BCM5702/5703 A0" },
{ BGE_CHIPID_BCM5703_A10x1001, "BCM5702/5703 A1" },
{ BGE_CHIPID_BCM5703_A20x1002, "BCM5702/5703 A2" },
{ BGE_CHIPID_BCM5703_A30x1003, "BCM5702/5703 A3" },
{ BGE_CHIPID_BCM5703_B00x1100, "BCM5702/5703 B0" },
{ BGE_CHIPID_BCM5704_A00x2000, "BCM5704 A0" },
{ BGE_CHIPID_BCM5704_A10x2001, "BCM5704 A1" },
{ BGE_CHIPID_BCM5704_A20x2002, "BCM5704 A2" },
{ BGE_CHIPID_BCM5704_A30x2003, "BCM5704 A3" },
{ BGE_CHIPID_BCM5704_B00x2100, "BCM5704 B0" },
{ BGE_CHIPID_BCM5705_A00x3000, "BCM5705 A0" },
{ BGE_CHIPID_BCM5705_A10x3001, "BCM5705 A1" },
{ BGE_CHIPID_BCM5705_A20x3002, "BCM5705 A2" },
{ BGE_CHIPID_BCM5705_A30x3003, "BCM5705 A3" },
{ BGE_CHIPID_BCM5750_A00x4000, "BCM5750 A0" },
{ BGE_CHIPID_BCM5750_A10x4001, "BCM5750 A1" },
{ BGE_CHIPID_BCM5750_A30x4003, "BCM5750 A3" },
{ BGE_CHIPID_BCM5750_B00x4010, "BCM5750 B0" },
{ BGE_CHIPID_BCM5750_B10x4101, "BCM5750 B1" },
{ BGE_CHIPID_BCM5750_C00x4200, "BCM5750 C0" },
{ BGE_CHIPID_BCM5750_C10x4201, "BCM5750 C1" },
{ BGE_CHIPID_BCM5750_C20x4202, "BCM5750 C2" },
{ BGE_CHIPID_BCM5714_A00x5000, "BCM5714 A0" },
{ BGE_CHIPID_BCM5752_A00x6000, "BCM5752 A0" },
{ BGE_CHIPID_BCM5752_A10x6001, "BCM5752 A1" },
{ BGE_CHIPID_BCM5752_A20x6002, "BCM5752 A2" },
{ BGE_CHIPID_BCM5714_B00x8000, "BCM5714 B0" },
{ BGE_CHIPID_BCM5714_B30x8003, "BCM5714 B3" },
{ BGE_CHIPID_BCM5715_A00x9000, "BCM5715 A0" },
{ BGE_CHIPID_BCM5715_A10x9001, "BCM5715 A1" },
{ BGE_CHIPID_BCM5715_A30x9003, "BCM5715 A3" },
{ BGE_CHIPID_BCM5717_A00x05717000, "BCM5717 A0" },
{ BGE_CHIPID_BCM5717_B00x05717100, "BCM5717 B0" },
{ BGE_CHIPID_BCM5719_A00x05719000, "BCM5719 A0" },
{ BGE_CHIPID_BCM5719_A10x05719001, "BCM5719 A1" },
{ BGE_CHIPID_BCM5720_A00x05720000, "BCM5720 A0" },
{ BGE_CHIPID_BCM5755_A00xa000, "BCM5755 A0" },
{ BGE_CHIPID_BCM5755_A10xa001, "BCM5755 A1" },
{ BGE_CHIPID_BCM5755_A20xa002, "BCM5755 A2" },
{ BGE_CHIPID_BCM5755_C00xa200, "BCM5755 C0" },
{ BGE_CHIPID_BCM5761_A00x5761000, "BCM5761 A0" },
{ BGE_CHIPID_BCM5761_A10x5761100, "BCM5761 A1" },
{ BGE_CHIPID_BCM5762_A00x05762000, "BCM5762 A0" },
{ BGE_CHIPID_BCM5762_B00x05762100, "BCM5762 B0" },
{ BGE_CHIPID_BCM5784_A00x5784000, "BCM5784 A0" },
{ BGE_CHIPID_BCM5784_A10x5784100, "BCM5784 A1" },
/* the 5754 and 5787 share the same ASIC ID */
{ BGE_CHIPID_BCM5787_A00xb000, "BCM5754/5787 A0" },
{ BGE_CHIPID_BCM5787_A10xb001, "BCM5754/5787 A1" },
{ BGE_CHIPID_BCM5787_A20xb002, "BCM5754/5787 A2" },
{ BGE_CHIPID_BCM5906_A10xc001, "BCM5906 A1" },
{ BGE_CHIPID_BCM5906_A20xc002, "BCM5906 A2" },
{ BGE_CHIPID_BCM57765_A00x57785000, "BCM57765 A0" },
{ BGE_CHIPID_BCM57765_B00x57785100, "BCM57765 B0" },
{ BGE_CHIPID_BCM57766_A00x57766000, "BCM57766 A0" },
{ BGE_CHIPID_BCM57766_A10x57766001, "BCM57766 A1" },
{ BGE_CHIPID_BCM57780_A00x57780000, "BCM57780 A0" },
{ BGE_CHIPID_BCM57780_A10x57780001, "BCM57780 A1" },

{ 0, NULL((void *)0) }
412};

414/*
* Some defaults for major revisions, so that newer steppings
* that we don't know about have a shot at working.
*/
418static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM57000x07, "unknown BCM5700" },
{ BGE_ASICREV_BCM57010x00, "unknown BCM5701" },
/* 5702 and 5703 share the same ASIC ID */
{ BGE_ASICREV_BCM57030x01, "unknown BCM5703" },
{ BGE_ASICREV_BCM57040x02, "unknown BCM5704" },
{ BGE_ASICREV_BCM57050x03, "unknown BCM5705" },
{ BGE_ASICREV_BCM57500x04, "unknown BCM5750" },
{ BGE_ASICREV_BCM57140x09, "unknown BCM5714" },
{ BGE_ASICREV_BCM5714_A00x05, "unknown BCM5714" },
{ BGE_ASICREV_BCM57520x06, "unknown BCM5752" },
{ BGE_ASICREV_BCM57800x08, "unknown BCM5780" },
{ BGE_ASICREV_BCM57550x0a, "unknown BCM5755" },
{ BGE_ASICREV_BCM57610x5761, "unknown BCM5761" },
{ BGE_ASICREV_BCM57840x5784, "unknown BCM5784" },
{ BGE_ASICREV_BCM57850x5785, "unknown BCM5785" },
/* 5754 and 5787 share the same ASIC ID */
{ BGE_ASICREV_BCM57870x0b, "unknown BCM5754/5787" },
{ BGE_ASICREV_BCM59060x0c, "unknown BCM5906" },
{ BGE_ASICREV_BCM577650x57785, "unknown BCM57765" },
{ BGE_ASICREV_BCM577660x57766, "unknown BCM57766" },
{ BGE_ASICREV_BCM577800x57780, "unknown BCM57780" },
{ BGE_ASICREV_BCM57170x5717, "unknown BCM5717" },
{ BGE_ASICREV_BCM57190x5719, "unknown BCM5719" },
{ BGE_ASICREV_BCM57200x5720, "unknown BCM5720" },
{ BGE_ASICREV_BCM57620x5762, "unknown BCM5762" },

{ 0, NULL((void *)0) }
446};

448u_int32_t
449bge_readmem_ind(struct bge_softc *sc, int off)
450{
struct pci_attach_args	*pa = &(sc->bge_pa);
u_int32_t val;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c &&
   off >= BGE_STATS_BLOCK0x00000300 && off < BGE_SEND_RING_1_TO_40x00004000)
return (0);

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR0x7C, off);
val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA0x84);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR0x7C, 0);
return (val);
462}

464void
465bge_writemem_ind(struct bge_softc *sc, int off, int val)
466{
struct pci_attach_args	*pa = &(sc->bge_pa);

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c &&
   off >= BGE_STATS_BLOCK0x00000300 && off < BGE_SEND_RING_1_TO_40x00004000)
return;

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR0x7C, off);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA0x84, val);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR0x7C, 0);
476}

478void
479bge_writereg_ind(struct bge_softc *sc, int off, int val)
480{
struct pci_attach_args	*pa = &(sc->bge_pa);

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR0x78, off);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA0x80, val);
485}

487void
488bge_writembx(struct bge_softc *sc, int off, int val)
489{
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c)
off += BGE_LPMBX_IRQ0_HI0x5800 - BGE_MBX_IRQ0_HI0x0200;

CSR_WRITE_4(sc, off, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (off), (
val)));
494}

496/*
* Clear all stale locks and select the lock for this driver instance.
*/
499void
500bge_ape_lock_init(struct bge_softc *sc)
501{
struct pci_attach_args *pa = &(sc->bge_pa);
uint32_t bit, regbase;
int i;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761)
regbase = BGE_APE_LOCK_GRANT0x004C;
else
regbase = BGE_APE_PER_LOCK_GRANT0x8420;

/* Clear any stale locks. */
for (i = BGE_APE_LOCK_PHY00; i <= BGE_APE_LOCK_GPIO7; i++) {
switch (i) {
case BGE_APE_LOCK_PHY00:
case BGE_APE_LOCK_PHY12:
case BGE_APE_LOCK_PHY23:
case BGE_APE_LOCK_PHY35:
	bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
	break;
default:
	if (pa->pa_function == 0)
		bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
	else
		bit = (1 << pa->pa_function);
}
APE_WRITE_4(sc, regbase + 4 * i, bit)((sc->bge_apetag)->write_4((sc->bge_apehandle), (regbase
 + 4 * i), (bit)));
}

/* Select the PHY lock based on the device's function number. */
switch (pa->pa_function) {
case 0:
sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY00;
break;
case 1:
sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY12;
break;
case 2:
sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY23;
break;
case 3:
sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY35;
break;
default:
printf("%s: PHY lock not supported on function %d\n",
    sc->bge_dev.dv_xname, pa->pa_function);
break;
}
548}

550/*
* Check for APE firmware, set flags, and print version info.
*/
553void
554bge_ape_read_fw_ver(struct bge_softc *sc)
555{
const char *fwtype;
uint32_t apedata, features;

/* Check for a valid APE signature in shared memory. */
apedata = APE_READ_4(sc, BGE_APE_SEG_SIG)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4000
)));
if (apedata != BGE_APE_SEG_SIG_MAGIC0x41504521) {
sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE0x00000002;
return;
}

/* Check if APE firmware is running. */
apedata = APE_READ_4(sc, BGE_APE_FW_STATUS)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x400C
)));
if ((apedata & BGE_APE_FW_STATUS_READY0x00000100) == 0) {
printf("%s: APE signature found but FW status not ready! "
    "0x%08x\n", sc->bge_dev.dv_xname, apedata);
return;
}

sc->bge_mfw_flags |= BGE_MFW_ON_APE0x00000002;

/* Fetch the APE firmware type and version. */
apedata = APE_READ_4(sc, BGE_APE_FW_VERSION)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4018
)));
features = APE_READ_4(sc, BGE_APE_FW_FEATURES)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4010
)));
if ((features & BGE_APE_FW_FEATURE_NCSI0x00000002) != 0) {
sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI0x00000004;
fwtype = "NCSI";
} else if ((features & BGE_APE_FW_FEATURE_DASH0x00000001) != 0) {
sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH0x00000008;
fwtype = "DASH";
} else
fwtype = "UNKN";

/* Print the APE firmware version. */
printf(", APE firmware %s %d.%d.%d.%d", fwtype,
   (apedata & BGE_APE_FW_VERSION_MAJMSK0xFF000000) >> BGE_APE_FW_VERSION_MAJSFT24,
   (apedata & BGE_APE_FW_VERSION_MINMSK0x00FF0000) >> BGE_APE_FW_VERSION_MINSFT16,
   (apedata & BGE_APE_FW_VERSION_REVMSK0x0000FF00) >> BGE_APE_FW_VERSION_REVSFT8,
   (apedata & BGE_APE_FW_VERSION_BLDMSK0x000000FF));
594}

596int
597bge_ape_lock(struct bge_softc *sc, int locknum)
598{
struct pci_attach_args *pa = &(sc->bge_pa);
uint32_t bit, gnt, req, status;
int i, off;

if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) == 0)
return (0);

/* Lock request/grant registers have different bases. */
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761) {
req = BGE_APE_LOCK_REQ0x002C;
gnt = BGE_APE_LOCK_GRANT0x004C;
} else {
req = BGE_APE_PER_LOCK_REQ0x8400;
gnt = BGE_APE_PER_LOCK_GRANT0x8420;
}

off = 4 * locknum;

switch (locknum) {
case BGE_APE_LOCK_GPIO7:
/* Lock required when using GPIO. */
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761)
	return (0);
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_REQ_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_GRC1:
/* Lock required to reset the device. */
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_REQ_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_MEM4:
/* Lock required when accessing certain APE memory. */
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_REQ_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_PHY00:
case BGE_APE_LOCK_PHY12:
case BGE_APE_LOCK_PHY23:
case BGE_APE_LOCK_PHY35:
/* Lock required when accessing PHYs. */
bit = BGE_APE_LOCK_REQ_DRIVER00x00001000;
break;
default:
return (EINVAL22);
}

/* Request a lock. */
APE_WRITE_4(sc, req + off, bit)((sc->bge_apetag)->write_4((sc->bge_apehandle), (req
 + off), (bit)));

/* Wait up to 1 second to acquire lock. */
for (i = 0; i < 20000; i++) {
status = APE_READ_4(sc, gnt + off)((sc->bge_apetag)->read_4((sc->bge_apehandle), (gnt +
 off)));
if (status == bit)
	break;
DELAY(50)(*delay_func)(50);
}

/* Handle any errors. */
if (status != bit) {
printf("%s: APE lock %d request failed! "
    "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
    sc->bge_dev.dv_xname,
    locknum, req + off, bit & 0xFFFF, gnt + off,
    status & 0xFFFF);
/* Revoke the lock request. */
APE_WRITE_4(sc, gnt + off, bit)((sc->bge_apetag)->write_4((sc->bge_apehandle), (gnt
 + off), (bit)));
return (EBUSY16);
}

return (0);
676}

678void
679bge_ape_unlock(struct bge_softc *sc, int locknum)
680{
struct pci_attach_args *pa = &(sc->bge_pa);
uint32_t bit, gnt;
int off;

if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) == 0)
return;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761)
gnt = BGE_APE_LOCK_GRANT0x004C;
else
gnt = BGE_APE_PER_LOCK_GRANT0x8420;

off = 4 * locknum;

switch (locknum) {
case BGE_APE_LOCK_GPIO7:
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761)
	return;
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_GRC1:
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_MEM4:
if (pa->pa_function == 0)
	bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
else
	bit = (1 << pa->pa_function);
break;
case BGE_APE_LOCK_PHY00:
case BGE_APE_LOCK_PHY12:
case BGE_APE_LOCK_PHY23:
case BGE_APE_LOCK_PHY35:
bit = BGE_APE_LOCK_GRANT_DRIVER00x00001000;
break;
default:
return;
}

APE_WRITE_4(sc, gnt + off, bit)((sc->bge_apetag)->write_4((sc->bge_apehandle), (gnt
 + off), (bit)));
727}

729/*
* Send an event to the APE firmware.
*/
732void
733bge_ape_send_event(struct bge_softc *sc, uint32_t event)
734{
uint32_t apedata;
int i;

/* NCSI does not support APE events. */
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) == 0)
return;

/* Wait up to 1ms for APE to service previous event. */
for (i = 10; i > 0; i--) {
if (bge_ape_lock(sc, BGE_APE_LOCK_MEM4) != 0)
	break;
apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4300
)));
if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING0x80000000) == 0) {
	APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4300
), (event | 0x80000000)))
	    BGE_APE_EVENT_STATUS_EVENT_PENDING)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4300
), (event | 0x80000000)));
	bge_ape_unlock(sc, BGE_APE_LOCK_MEM4);
	APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x000C
), (0x00000001)));
	break;
}
bge_ape_unlock(sc, BGE_APE_LOCK_MEM4);
DELAY(100)(*delay_func)(100);
}
if (i == 0) {
printf("%s: APE event 0x%08x send timed out\n",
    sc->bge_dev.dv_xname, event);
}
761}

763void
764bge_ape_driver_state_change(struct bge_softc *sc, int kind)
765{
uint32_t apedata, event;

if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) == 0)
return;

switch (kind) {
case BGE_RESET_START1:
/* If this is the first load, clear the load counter. */
apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4200
)));
if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC0x484F5354)
	APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4208
), (0)));
else {
	apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT)((sc->bge_apetag)->read_4((sc->bge_apehandle), (0x4208
)));
	APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4208
), (++apedata)));
}
APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4200
), (0x484F5354)))
    BGE_APE_HOST_SEG_SIG_MAGIC)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4200
), (0x484F5354)));
APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4204
), (0x00000020)))
    BGE_APE_HOST_SEG_LEN_MAGIC)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4204
), (0x00000020)));

/* Add some version info if bge(4) supports it. */
APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x420C
), ((0xF6000000 | ((1) & 0xffd) << 16 | ((0) & 0xff
) << 8))))
    BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0))((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x420C
), ((0xF6000000 | ((1) & 0xffd) << 16 | ((0) & 0xff
) << 8))));
APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4210
), (0x00000001)))
    BGE_APE_HOST_BEHAV_NO_PHYLOCK)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4210
), (0x00000001)));
APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4214
), (0)))
    BGE_APE_HOST_HEARTBEAT_INT_DISABLE)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x4214
), (0)));
APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x421C
), (0x00000001)))
    BGE_APE_HOST_DRVR_STATE_START)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x421C
), (0x00000001)));
event = BGE_APE_EVENT_STATUS_STATE_START0x00010000;
break;
case BGE_RESET_SHUTDOWN0:
APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x421C
), (0x00000002)))
    BGE_APE_HOST_DRVR_STATE_UNLOAD)((sc->bge_apetag)->write_4((sc->bge_apehandle), (0x421C
), (0x00000002)));
event = BGE_APE_EVENT_STATUS_STATE_UNLOAD0x00020000;
break;
case BGE_RESET_SUSPEND2:
event = BGE_APE_EVENT_STATUS_STATE_SUSPEND0x00040000;
break;
default:
return;
}

bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT0x00000010 |
   BGE_APE_EVENT_STATUS_STATE_CHNGE0x00000500);
811}


814u_int8_t
815bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest)
816{
u_int32_t access, byte = 0;
int i;

/* Lock. */
CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7020)
, (0x00000002)));
for (i = 0; i < 8000; i++) {
if (CSR_READ_4(sc, BGE_NVRAM_SWARB)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7020))
) & BGE_NVRAMSWARB_GNT10x00000200)
	break;
DELAY(20)(*delay_func)(20);
}
if (i == 8000)
return (1);

/* Enable access. */
access = CSR_READ_4(sc, BGE_NVRAM_ACCESS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7024))
);
CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7024)
, (access | 0x00000001)));

CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x700c)
, (addr & 0xfffffffc)));
CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7000)
, ((0x00000080|0x00000100| 0x00000010|0x00000008))));
for (i = 0; i < BGE_TIMEOUT100000 * 10; i++) {
DELAY(10)(*delay_func)(10);
if (CSR_READ_4(sc, BGE_NVRAM_CMD)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7000))
) & BGE_NVRAMCMD_DONE0x00000008) {
	DELAY(10)(*delay_func)(10);
	break;
}
}

if (i == BGE_TIMEOUT100000 * 10) {
printf("%s: nvram read timed out\n", sc->bge_dev.dv_xname);
return (1);
}

/* Get result. */
byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7010))
);

*dest = (swap32(byte)(__uint32_t)(__builtin_constant_p(byte) ? (__uint32_t)(((__uint32_t
)(byte) & 0xff) << 24 | ((__uint32_t)(byte) & 0xff00
) << 8 | ((__uint32_t)(byte) & 0xff0000) >> 8
 | ((__uint32_t)(byte) & 0xff000000) >> 24) : __swap32md
(byte)) >> ((addr % 4) * 8)) & 0xFF;

/* Disable access. */
CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7024)
, (access)));

/* Unlock. */
CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7020)
, (0x00000020)));
CSR_READ_4(sc, BGE_NVRAM_SWARB)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7020))
);

return (0);
862}

864/*
* Read a sequence of bytes from NVRAM.
*/

868int
869bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
870{
int err = 0, i;
u_int8_t byte = 0;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM59060x0c)
return (1);

for (i = 0; i < cnt; i++) {
err = bge_nvram_getbyte(sc, off + i, &byte);
if (err)
	break;
*(dest + i) = byte;
}

return (err ? 1 : 0);
885}

887/*
* Read a byte of data stored in the EEPROM at address 'addr.' The
* BCM570x supports both the traditional bitbang interface and an
* auto access interface for reading the EEPROM. We use the auto
* access method.
*/
893u_int8_t
894bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest)
895{
int i;
u_int32_t byte = 0;

/*
* Enable use of auto EEPROM access so we can avoid
* having to use the bitbang method.
*/
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x01000000)))));

/* Reset the EEPROM, load the clock period. */
CSR_WRITE_4(sc, BGE_EE_ADDR,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6838)
, (0x20000000|((0x60 & 0x1FF) << 16))))
   BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6838)
, (0x20000000|((0x60 & 0x1FF) << 16))));
DELAY(20)(*delay_func)(20);

/* Issue the read EEPROM command. */
CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6838)
, ((((0x60 & 0x1FF) << 16)|((0 & 7) << 26
)| 0x02000000|0x80000000|0x40000000) | addr)));

/* Wait for completion */
for(i = 0; i < BGE_TIMEOUT100000 * 10; i++) {
DELAY(10)(*delay_func)(10);
if (CSR_READ_4(sc, BGE_EE_ADDR)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6838))
) & BGE_EEADDR_DONE0x40000000)
	break;
}

if (i == BGE_TIMEOUT100000 * 10) {
printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
return (1);
}

/* Get result. */
byte = CSR_READ_4(sc, BGE_EE_DATA)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x683C))
);

*dest = (byte >> ((addr % 4) * 8)) & 0xFF;

return (0);
931}

933/*
* Read a sequence of bytes from the EEPROM.
*/
936int
937bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
938{
int i, error = 0;
u_int8_t byte = 0;

for (i = 0; i < cnt; i++) {
error = bge_eeprom_getbyte(sc, off + i, &byte);
if (error)
	break;
*(dest + i) = byte;
}

return (error ? 1 : 0);
950}

952int
953bge_miibus_readreg(struct device *dev, int phy, int reg)
954{
struct bge_softc *sc = (struct bge_softc *)dev;
u_int32_t val, autopoll;
int i;

if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
return (0);

/* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454))
);
if (autopoll & BGE_MIMODE_AUTOPOLL0x00000010) {
BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts &= ~(0x00000004));
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0454)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454
))) & ~(0x00000010)))));
DELAY(80)(*delay_func)(80);
}

CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x044C)
, (0x08000000|0x20000000| ((phy & 0x1F) << 21)|((reg
 & 0x1F) << 16))))
   BGE_MIPHY(phy)|BGE_MIREG(reg))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x044C)
, (0x08000000|0x20000000| ((phy & 0x1F) << 21)|((reg
 & 0x1F) << 16))));
CSR_READ_4(sc, BGE_MI_COMM)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x044C))
); /* force write */

for (i = 0; i < 200; i++) {
delay(1)(*delay_func)(1);
val = CSR_READ_4(sc, BGE_MI_COMM)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x044C))
);
if (!(val & BGE_MICOMM_BUSY0x20000000))
	break;
delay(10)(*delay_func)(10);
}

if (i == 200) {
printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
val = 0;
goto done;
}

val = CSR_READ_4(sc, BGE_MI_COMM)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x044C))
);

990done:
if (autopoll & BGE_MIMODE_AUTOPOLL0x00000010) {
BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts |= (0x00000004));
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0454)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454
))) | (0x00000010)))));
DELAY(80)(*delay_func)(80);
}

bge_ape_unlock(sc, sc->bge_phy_ape_lock);

if (val & BGE_MICOMM_READFAIL0x10000000)
return (0);

return (val & 0xFFFF);
1003}

1005void
1006bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
1007{
struct bge_softc *sc = (struct bge_softc *)dev;
u_int32_t autopoll;
int i;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c &&
   (reg == MII_100T2CR0x09 || reg == BRGPHY_MII_AUXCTL0x18))
return;

if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
return;

/* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454))
);
if (autopoll & BGE_MIMODE_AUTOPOLL0x00000010) {
DELAY(40)(*delay_func)(40);
BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts &= ~(0x00000004));
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0454)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454
))) & ~(0x00000010)))));
DELAY(40)(*delay_func)(40); /* 40 usec is supposed to be adequate */
}

CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x044C)
, (0x04000000|0x20000000| ((phy & 0x1F) << 21)|((reg
 & 0x1F) << 16)|val)))
   BGE_MIPHY(phy)|BGE_MIREG(reg)|val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x044C)
, (0x04000000|0x20000000| ((phy & 0x1F) << 21)|((reg
 & 0x1F) << 16)|val)));
CSR_READ_4(sc, BGE_MI_COMM)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x044C))
); /* force write */

for (i = 0; i < 200; i++) {
delay(1)(*delay_func)(1);
if (!(CSR_READ_4(sc, BGE_MI_COMM)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x044C))
) & BGE_MICOMM_BUSY0x20000000))
	break;
delay(10)(*delay_func)(10);
}

if (autopoll & BGE_MIMODE_AUTOPOLL0x00000010) {
BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts |= (0x00000004));
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0454)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0454
))) | (0x00000010)))));
DELAY(40)(*delay_func)(40);
}

bge_ape_unlock(sc, sc->bge_phy_ape_lock);

if (i == 200) {
printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
}
1050}

1052void
1053bge_miibus_statchg(struct device *dev)
1054{
struct bge_softc *sc = (struct bge_softc *)dev;
struct mii_data *mii = &sc->bge_mii;
u_int32_t mac_mode, rx_mode, tx_mode;

/*
* Get flow control negotiation result.
*/
if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media)((mii->mii_media.ifm_cur->ifm_media) & 0x00000000000000ffULL
) == IFM_AUTO0ULL &&
   (mii->mii_media_active & IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
)) != sc->bge_flowflags)
sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
);

if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
   mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL &&
   IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) != IFM_NONE2ULL)
BGE_STS_SETBIT(sc, BGE_STS_LINK)((sc)->bge_sts |= (0x00000001));
else if (BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
   (!(mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL) ||
   IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_NONE2ULL))
BGE_STS_CLRBIT(sc, BGE_STS_LINK)((sc)->bge_sts &= ~(0x00000001));

if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)))
return;

/* Set the port mode (MII/GMII) to match the link speed. */
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400))
) &
   ~(BGE_MACMODE_PORTMODE0x0000000C | BGE_MACMODE_HALF_DUPLEX0x00000002);
tx_mode = CSR_READ_4(sc, BGE_TX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x045C))
);
rx_mode = CSR_READ_4(sc, BGE_RX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0468))
);

if (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_1000_T16 ||
   IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_1000_SX11)
mac_mode |= BGE_PORTMODE_GMII0x00000008;
else
mac_mode |= BGE_PORTMODE_MII0x00000004;

/* Set MAC flow control behavior to match link flow control settings. */
tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE0x00000010;
rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE0x00000004;
if (mii->mii_media_active & IFM_FDX0x0000010000000000ULL) {
if (sc->bge_flowflags & IFM_ETH_TXPAUSE0x0000000000040000ULL)
	tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE0x00000010;
if (sc->bge_flowflags & IFM_ETH_RXPAUSE0x0000000000020000ULL)
	rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE0x00000004;
} else
mac_mode |= BGE_MACMODE_HALF_DUPLEX0x00000002;

CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, (mac_mode)));
DELAY(40)(*delay_func)(40);
CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x045C)
, (tx_mode)));
CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0468)
, (rx_mode)));
1105}

1107/*
* Initialize a standard receive ring descriptor.
*/
1110int
1111bge_newbuf(struct bge_softc *sc, int i)
1112{
bus_dmamap_t		dmap = sc->bge_cdata.bge_rx_std_map[i];
struct bge_rx_bd	*r = &sc->bge_rdata->bge_rx_std_ring[i];
struct mbuf		*m;
int			error;

m = MCLGETL(NULL, M_DONTWAIT, sc->bge_rx_std_len)m_clget((((void *)0)), (0x0002), (sc->bge_rx_std_len));
if (!m)
return (ENOBUFS55);
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = sc->bge_rx_std_len;
if (!(sc->bge_flags & BGE_RX_ALIGNBUG0x00000008))
   m_adj(m, ETHER_ALIGN2);

error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m,(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmap), (m), (0x0200|0x0001))
   BUS_DMA_READ|BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmap), (m), (0x0200|0x0001));
if (error) {
m_freem(m);
return (ENOBUFS55);
}

bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x01));
sc->bge_cdata.bge_rx_std_chain[i] = m;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x08))
   offsetof(struct bge_ring_data, bge_rx_std_ring) +(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x08))
i * sizeof (struct bge_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x08))
   sizeof (struct bge_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x08))
   BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x08));

BGE_HOSTADDR(r->bge_addr, dmap->dm_segs[0].ds_addr)do { (r->bge_addr).bge_addr_lo = ((u_int64_t) (dmap->dm_segs
[0].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t) == 8) (
r->bge_addr).bge_addr_hi = ((u_int64_t) (dmap->dm_segs[
0].ds_addr) >> 32); else (r->bge_addr).bge_addr_hi =
 0; } while(0);
r->bge_flags = BGE_RXBDFLAG_END0x0004;
r->bge_len = m->m_lenm_hdr.mh_len;
r->bge_idx = i;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x04))
   offsetof(struct bge_ring_data, bge_rx_std_ring) +(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x04))
i * sizeof (struct bge_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x04))
   sizeof (struct bge_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_std_ring) + i * sizeof (struct bge_rx_bd)), (sizeof (
struct bge_rx_bd)), (0x04));

return (0);
1154}

1156/*
* Initialize a Jumbo receive ring descriptor.
*/
1159int
1160bge_newbuf_jumbo(struct bge_softc *sc, int i)
1161{
bus_dmamap_t		dmap = sc->bge_cdata.bge_rx_jumbo_map[i];
struct bge_ext_rx_bd	*r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
struct mbuf		*m;
int			error;

m = MCLGETL(NULL, M_DONTWAIT, BGE_JLEN)m_clget((((void *)0)), (0x0002), (((9022 + 2) + (sizeof(u_int64_t
) - ((9022 + 2) % sizeof(u_int64_t))))));
if (!m)
return (ENOBUFS55);
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = BGE_JUMBO_FRAMELEN9022;
if (!(sc->bge_flags & BGE_RX_ALIGNBUG0x00000008))
   m_adj(m, ETHER_ALIGN2);

error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m,(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmap), (m), (0x0200|0x0001))
   BUS_DMA_READ|BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmap), (m), (0x0200|0x0001));
if (error) {
m_freem(m);
return (ENOBUFS55);
}

bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x01));
sc->bge_cdata.bge_rx_jumbo_chain[i] = m;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x08))
   offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x08))
i * sizeof (struct bge_ext_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x08))
   sizeof (struct bge_ext_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x08))
   BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x08));

/*
* Fill in the extended RX buffer descriptor.
*/
r->bge_bd.bge_flags = BGE_RXBDFLAG_JUMBO_RING0x0020 | BGE_RXBDFLAG_END0x0004;
r->bge_bd.bge_idx = i;
r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
switch (dmap->dm_nsegs) {
case 4:
BGE_HOSTADDR(r->bge_addr3, dmap->dm_segs[3].ds_addr)do { (r->bge_addr3).bge_addr_lo = ((u_int64_t) (dmap->dm_segs
[3].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t) == 8) (
r->bge_addr3).bge_addr_hi = ((u_int64_t) (dmap->dm_segs
[3].ds_addr) >> 32); else (r->bge_addr3).bge_addr_hi
 = 0; } while(0);
r->bge_len3 = dmap->dm_segs[3].ds_len;
/* FALLTHROUGH */
case 3:
BGE_HOSTADDR(r->bge_addr2, dmap->dm_segs[2].ds_addr)do { (r->bge_addr2).bge_addr_lo = ((u_int64_t) (dmap->dm_segs
[2].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t) == 8) (
r->bge_addr2).bge_addr_hi = ((u_int64_t) (dmap->dm_segs
[2].ds_addr) >> 32); else (r->bge_addr2).bge_addr_hi
 = 0; } while(0);
r->bge_len2 = dmap->dm_segs[2].ds_len;
/* FALLTHROUGH */
case 2:
BGE_HOSTADDR(r->bge_addr1, dmap->dm_segs[1].ds_addr)do { (r->bge_addr1).bge_addr_lo = ((u_int64_t) (dmap->dm_segs
[1].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t) == 8) (
r->bge_addr1).bge_addr_hi = ((u_int64_t) (dmap->dm_segs
[1].ds_addr) >> 32); else (r->bge_addr1).bge_addr_hi
 = 0; } while(0);
r->bge_len1 = dmap->dm_segs[1].ds_len;
/* FALLTHROUGH */
case 1:
BGE_HOSTADDR(r->bge_bd.bge_addr, dmap->dm_segs[0].ds_addr)do { (r->bge_bd.bge_addr).bge_addr_lo = ((u_int64_t) (dmap
->dm_segs[0].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t
) == 8) (r->bge_bd.bge_addr).bge_addr_hi = ((u_int64_t) (dmap
->dm_segs[0].ds_addr) >> 32); else (r->bge_bd.bge_addr
).bge_addr_hi = 0; } while(0);
r->bge_bd.bge_len = dmap->dm_segs[0].ds_len;
break;
default:
panic("%s: %d segments", __func__, dmap->dm_nsegs);
}

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x04))
   offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x04))
i * sizeof (struct bge_ext_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x04))
   sizeof (struct bge_ext_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_rx_jumbo_ring) + i * sizeof (struct bge_ext_rx_bd)), (sizeof
 (struct bge_ext_rx_bd)), (0x04));

return (0);
1225}

1227int
1228bge_init_rx_ring_std(struct bge_softc *sc)
1229{
int i;

if (ISSET(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) & (0x00000002)))
return (0);

for (i = 0; i < BGE_STD_RX_RING_CNT512; i++) {
if (bus_dmamap_create(sc->bge_dmatag, sc->bge_rx_std_len, 1,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sc->bge_rx_std_len), (1), (sc->bge_rx_std_len), (0),
 (0x0001 | 0x0002), (&sc->bge_cdata.bge_rx_std_map[i])
)
    sc->bge_rx_std_len, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sc->bge_rx_std_len), (1), (sc->bge_rx_std_len), (0),
 (0x0001 | 0x0002), (&sc->bge_cdata.bge_rx_std_map[i])
)
    &sc->bge_cdata.bge_rx_std_map[i])(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sc->bge_rx_std_len), (1), (sc->bge_rx_std_len), (0),
 (0x0001 | 0x0002), (&sc->bge_cdata.bge_rx_std_map[i])
) != 0) {
	printf("%s: unable to create dmamap for slot %d\n",
	    sc->bge_dev.dv_xname, i);
	goto uncreate;
}
bzero(&sc->bge_rdata->bge_rx_std_ring[i],__builtin_bzero((&sc->bge_rdata->bge_rx_std_ring[i]
), (sizeof(struct bge_rx_bd)))
    sizeof(struct bge_rx_bd))__builtin_bzero((&sc->bge_rdata->bge_rx_std_ring[i]
), (sizeof(struct bge_rx_bd)));
}

sc->bge_std = BGE_STD_RX_RING_CNT512 - 1;

/* lwm must be greater than the replenish threshold */
if_rxr_init(&sc->bge_std_ring, 17, BGE_STD_RX_RING_CNT512);
bge_fill_rx_ring_std(sc);

SET(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) |= (0x00000002));

return (0);

1257uncreate:
while (--i) {
bus_dmamap_destroy(sc->bge_dmatag,(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_cdata.bge_rx_std_map[i]))
    sc->bge_cdata.bge_rx_std_map[i])(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_cdata.bge_rx_std_map[i]));
}
return (1);
1263}

1265/*
* When the refill timeout for a ring is active, that ring is so empty
* that no more packets can be received on it, so the interrupt handler
* will not attempt to refill it, meaning we don't need to protect against
* interrupts here.
*/

1272void
1273bge_rxtick(void *arg)
1274{
struct bge_softc *sc = arg;

if (ISSET(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) & (0x00000002)) &&
   if_rxr_inuse(&sc->bge_std_ring)((&sc->bge_std_ring)->rxr_alive) <= 8)
bge_fill_rx_ring_std(sc);
1280}

1282void
1283bge_rxtick_jumbo(void *arg)
1284{
struct bge_softc *sc = arg;

if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) & (0x00000004)) &&
   if_rxr_inuse(&sc->bge_jumbo_ring)((&sc->bge_jumbo_ring)->rxr_alive) <= 8)
bge_fill_rx_ring_jumbo(sc);
1290}

1292void
1293bge_fill_rx_ring_std(struct bge_softc *sc)
1294{
int i;
int post = 0;
u_int slots;

i = sc->bge_std;
for (slots = if_rxr_get(&sc->bge_std_ring, BGE_STD_RX_RING_CNT512);
   slots > 0; slots--) {
BGE_INC(i, BGE_STD_RX_RING_CNT)(i) = (i + 1) % 512;

if (bge_newbuf(sc, i) != 0)
	break;

sc->bge_std = i;
post = 1;
}
if_rxr_put(&sc->bge_std_ring, slots)do { (&sc->bge_std_ring)->rxr_alive -= (slots); } while
 (0);

if (post)
bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO0x026C, sc->bge_std);

/*
* bge always needs more than 8 packets on the ring. if we cant do
* that now, then try again later.
*/
if (if_rxr_inuse(&sc->bge_std_ring)((&sc->bge_std_ring)->rxr_alive) <= 8)
timeout_add(&sc->bge_rxtimeout, 1);
1321}

1323void
1324bge_free_rx_ring_std(struct bge_softc *sc)
1325{
bus_dmamap_t dmap;
struct mbuf *m;
int i;

if (!ISSET(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) & (0x00000002)))
return;

for (i = 0; i < BGE_STD_RX_RING_CNT512; i++) {
dmap = sc->bge_cdata.bge_rx_std_map[i];
m = sc->bge_cdata.bge_rx_std_chain[i];
if (m != NULL((void *)0)) {
	bus_dmamap_sync(sc->bge_dmatag, dmap, 0,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x02))
	    dmap->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->bge_dmatag, dmap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmap));
	m_freem(m);
	sc->bge_cdata.bge_rx_std_chain[i] = NULL((void *)0);
}
bus_dmamap_destroy(sc->bge_dmatag, dmap)(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (dmap));
sc->bge_cdata.bge_rx_std_map[i] = NULL((void *)0);
bzero(&sc->bge_rdata->bge_rx_std_ring[i],__builtin_bzero((&sc->bge_rdata->bge_rx_std_ring[i]
), (sizeof(struct bge_rx_bd)))
    sizeof(struct bge_rx_bd))__builtin_bzero((&sc->bge_rdata->bge_rx_std_ring[i]
), (sizeof(struct bge_rx_bd)));
}

CLR(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) &= ~(0x00000002));
1350}

1352int
1353bge_init_rx_ring_jumbo(struct bge_softc *sc)
1354{
volatile struct bge_rcb *rcb;
int i;

if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) & (0x00000004)))
return (0);

for (i = 0; i < BGE_JUMBO_RX_RING_CNT256; i++) {
if (bus_dmamap_create(sc->bge_dmatag, BGE_JLEN, 4, BGE_JLEN, 0,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))))), (4), (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) %
 sizeof(u_int64_t))))), (0), (0x0001 | 0x0002), (&sc->
bge_cdata.bge_rx_jumbo_map[i]))
    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))))), (4), (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) %
 sizeof(u_int64_t))))), (0), (0x0001 | 0x0002), (&sc->
bge_cdata.bge_rx_jumbo_map[i]))
    &sc->bge_cdata.bge_rx_jumbo_map[i])(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))))), (4), (((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) %
 sizeof(u_int64_t))))), (0), (0x0001 | 0x0002), (&sc->
bge_cdata.bge_rx_jumbo_map[i])) != 0) {
	printf("%s: unable to create dmamap for slot %d\n",
	    sc->bge_dev.dv_xname, i);
	goto uncreate;
}
bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],__builtin_bzero((&sc->bge_rdata->bge_rx_jumbo_ring[
i]), (sizeof(struct bge_ext_rx_bd)))
    sizeof(struct bge_ext_rx_bd))__builtin_bzero((&sc->bge_rdata->bge_rx_jumbo_ring[
i]), (sizeof(struct bge_ext_rx_bd)));
}

sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT256 - 1;

/* lwm must be greater than the replenish threshold */
if_rxr_init(&sc->bge_jumbo_ring, 17, BGE_JUMBO_RX_RING_CNT256);
bge_fill_rx_ring_jumbo(sc);

SET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) |= (0x00000004));

rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
rcb->bge_maxlen_flags =
   BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD)((0) << 16 | (0x0001));
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2448)
, (rcb->bge_maxlen_flags)));

return (0);

1388uncreate:
while (--i) {
bus_dmamap_destroy(sc->bge_dmatag,(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_cdata.bge_rx_jumbo_map[i]))
    sc->bge_cdata.bge_rx_jumbo_map[i])(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_cdata.bge_rx_jumbo_map[i]));
}
return (1);
1394}

1396void
1397bge_fill_rx_ring_jumbo(struct bge_softc *sc)
1398{
int i;
int post = 0;
u_int slots;

i = sc->bge_jumbo;
for (slots = if_rxr_get(&sc->bge_jumbo_ring, BGE_JUMBO_RX_RING_CNT256);
   slots > 0; slots--) {
BGE_INC(i, BGE_JUMBO_RX_RING_CNT)(i) = (i + 1) % 256;

if (bge_newbuf_jumbo(sc, i) != 0)
	break;

sc->bge_jumbo = i;
post = 1;
}
if_rxr_put(&sc->bge_jumbo_ring, slots)do { (&sc->bge_jumbo_ring)->rxr_alive -= (slots); }
 while (0);

if (post)
bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO0x0274, sc->bge_jumbo);

/*
* bge always needs more than 8 packets on the ring. if we cant do
* that now, then try again later.
*/
if (if_rxr_inuse(&sc->bge_jumbo_ring)((&sc->bge_jumbo_ring)->rxr_alive) <= 8)
timeout_add(&sc->bge_rxtimeout_jumbo, 1);
1425}

1427void
1428bge_free_rx_ring_jumbo(struct bge_softc *sc)
1429{
bus_dmamap_t dmap;
struct mbuf *m;
int i;

if (!ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) & (0x00000004)))
return;

for (i = 0; i < BGE_JUMBO_RX_RING_CNT256; i++) {
dmap = sc->bge_cdata.bge_rx_jumbo_map[i];
m = sc->bge_cdata.bge_rx_jumbo_chain[i];
if (m != NULL((void *)0)) {
	bus_dmamap_sync(sc->bge_dmatag, dmap, 0,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x02))
	    dmap->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmap), (0), (dmap->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->bge_dmatag, dmap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmap));
	m_freem(m);
	sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL((void *)0);
}
bus_dmamap_destroy(sc->bge_dmatag, dmap)(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (dmap));
sc->bge_cdata.bge_rx_jumbo_map[i] = NULL((void *)0);
bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],__builtin_bzero((&sc->bge_rdata->bge_rx_jumbo_ring[
i]), (sizeof(struct bge_ext_rx_bd)))
    sizeof(struct bge_ext_rx_bd))__builtin_bzero((&sc->bge_rdata->bge_rx_jumbo_ring[
i]), (sizeof(struct bge_ext_rx_bd)));
}

CLR(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) &= ~(0x00000004));
1454}

1456void
1457bge_free_tx_ring(struct bge_softc *sc)
1458{
int i;

if (!(sc->bge_flags & BGE_TXRING_VALID0x00000001))
return;

for (i = 0; i < BGE_TX_RING_CNT512; i++) {
if (sc->bge_cdata.bge_tx_chain[i] != NULL((void *)0)) {
	m_freem(sc->bge_cdata.bge_tx_chain[i]);
	sc->bge_cdata.bge_tx_chain[i] = NULL((void *)0);
	sc->bge_cdata.bge_tx_map[i] = NULL((void *)0);
}
bzero(&sc->bge_rdata->bge_tx_ring[i],__builtin_bzero((&sc->bge_rdata->bge_tx_ring[i]), (
sizeof(struct bge_tx_bd)))
    sizeof(struct bge_tx_bd))__builtin_bzero((&sc->bge_rdata->bge_tx_ring[i]), (
sizeof(struct bge_tx_bd)));

bus_dmamap_destroy(sc->bge_dmatag, sc->bge_txdma[i])(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_txdma[i]));
}

sc->bge_flags &= ~BGE_TXRING_VALID0x00000001;
1477}

1479int
1480bge_init_tx_ring(struct bge_softc *sc)
1481{
int i;
bus_size_t txsegsz, txmaxsegsz;

if (sc->bge_flags & BGE_TXRING_VALID0x00000001)
return (0);

sc->bge_txcnt = 0;
sc->bge_tx_saved_considx = 0;

/* Initialize transmit producer index for host-memory send ring. */
sc->bge_tx_prodidx = 0;
bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO0x0304, sc->bge_tx_prodidx);
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5700_BX0x71)
bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO0x0304, sc->bge_tx_prodidx);

/* NIC-memory send ring not used; initialize to zero. */
bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO0x0384, 0);
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5700_BX0x71)
bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO0x0384, 0);

if (BGE_IS_JUMBO_CAPABLE(sc)((sc)->bge_flags & 0x00000100)) {
txsegsz = 4096;
txmaxsegsz = BGE_JLEN((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))));
} else {
txsegsz = MCLBYTES(1 << 11);
txmaxsegsz = MCLBYTES(1 << 11);
}

for (i = 0; i < BGE_TX_RING_CNT512; i++) {
if (bus_dmamap_create(sc->bge_dmatag, txmaxsegsz,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (txmaxsegsz), (30), (txsegsz), (0), (0x0001), (&sc->
bge_txdma[i]))
    BGE_NTXSEG, txsegsz, 0, BUS_DMA_NOWAIT, &sc->bge_txdma[i])(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (txmaxsegsz), (30), (txsegsz), (0), (0x0001), (&sc->
bge_txdma[i])))
	return (ENOBUFS55);
}

sc->bge_flags |= BGE_TXRING_VALID0x00000001;

return (0);
1519}

1521void
1522bge_iff(struct bge_softc *sc)
1523{
struct arpcom		*ac = &sc->arpcom;
struct ifnet		*ifp = &ac->ac_if;
struct ether_multi	*enm;
struct ether_multistep  step;
u_int8_t		hashes[16];
u_int32_t		h, rxmode;

/* First, zot all the existing filters. */
rxmode = CSR_READ_4(sc, BGE_RX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0468))
) & ~BGE_RXMODE_RX_PROMISC0x00000100;
ifp->if_flags &= ~IFF_ALLMULTI0x200;
memset(hashes, 0x00, sizeof(hashes))__builtin_memset((hashes), (0x00), (sizeof(hashes)));

if (ifp->if_flags & IFF_PROMISC0x100) {
ifp->if_flags |= IFF_ALLMULTI0x200;
rxmode |= BGE_RXMODE_RX_PROMISC0x00000100;
} else if (ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
memset(hashes, 0xff, sizeof(hashes))__builtin_memset((hashes), (0xff), (sizeof(hashes)));
} else {
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN6);

	setbit(hashes, h & 0x7F)((hashes)[(h & 0x7F)>>3] |= 1<<((h & 0x7F
)&(8 -1)));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

bus_space_write_raw_region_4(sc->bge_btag, sc->bge_bhandle, BGE_MAR0,((sc->bge_btag)->write_region_4((sc->bge_bhandle), (
0x0470), (const u_int32_t *)(hashes), (sizeof(hashes)) >>
 2))
   hashes, sizeof(hashes))((sc->bge_btag)->write_region_4((sc->bge_bhandle), (
0x0470), (const u_int32_t *)(hashes), (sizeof(hashes)) >>
 2));
CSR_WRITE_4(sc, BGE_RX_MODE, rxmode)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0468)
, (rxmode)));
1556}

1558void
1559bge_sig_pre_reset(struct bge_softc *sc, int type)
1560{
/* no bge_asf_mode. */

if (type == BGE_RESET_START1 || type == BGE_RESET_SUSPEND2)
bge_ape_driver_state_change(sc, type);
1565}

1567void
1568bge_sig_post_reset(struct bge_softc *sc, int type)
1569{
/* no bge_asf_mode. */

if (type == BGE_RESET_SHUTDOWN0)
bge_ape_driver_state_change(sc, type);
1574}

1576void
1577bge_sig_legacy(struct bge_softc *sc, int type)
1578{
/* no bge_asf_mode. */
1580}

1582void
1583bge_stop_fw(struct bge_softc *sc, int type)
1584{
/* no bge_asf_mode. */
1586}

1588u_int32_t
1589bge_dma_swap_options(struct bge_softc *sc)
1590{
u_int32_t dma_options = BGE_DMA_SWAP_OPTIONS0x00000004| 0x00000010|0x00000020;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720) {
dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA0x00000040 |
    BGE_MODECTL_WORDSWAP_B2HRX_DATA0x00000080 | BGE_MODECTL_B2HRX_ENABLE0x00008000 |
    BGE_MODECTL_HTX2B_ENABLE0x00040000;
}

return (dma_options);
1600}

1602int
1603bge_phy_addr(struct bge_softc *sc)
1604{
struct pci_attach_args *pa = &(sc->bge_pa);
int phy_addr = 1;

switch (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12)) {
case BGE_ASICREV_BCM57170x5717:
case BGE_ASICREV_BCM57190x5719:
case BGE_ASICREV_BCM57200x5720:
phy_addr = pa->pa_function;
if (sc->bge_chipid != BGE_CHIPID_BCM5717_A00x05717000) {
	phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x05B4))
) &
	    BGE_SGDIGSTS_IS_SERDES0x00000100) ? 8 : 1;
} else {
	phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3664))
) &
	    BGE_CPMU_PHY_STRAP_IS_SERDES0x00000020) ? 8 : 1;
}
}

return (phy_addr);
1623}

1625/*
* Do endian, PCI and DMA initialization.
*/
1628void
1629bge_chipinit(struct bge_softc *sc)
1630{
struct pci_attach_args	*pa = &(sc->bge_pa);
u_int32_t dma_rw_ctl, misc_ctl, mode_ctl;
int i;

/* Set endianness before we access any non-PCI registers. */
misc_ctl = BGE_INIT(0x00000008|0x00000001| 0x00000002|0x00000080);
if (sc->bge_flags & BGE_TAGGED_STATUS0x00200000)
misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS0x00000200;
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL0x68,
   misc_ctl);

/*
* Clear the MAC statistics block in the NIC's
* internal memory.
*/
for (i = BGE_STATS_BLOCK0x00000300;
   i < BGE_STATS_BLOCK_END0x00000AFF + 1; i += sizeof(u_int32_t))
BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0)do { pci_conf_write(pa->pa_pc, pa->pa_tag, 0x7C, (0xFFFF8000
 & i)); ((sc->bge_btag)->write_4((sc->bge_bhandle
), (0x00008000 + (i & 0x7FFF)), (0))); } while(0);

for (i = BGE_STATUS_BLOCK0x00000B00;
   i < BGE_STATUS_BLOCK_END0x00000B4F + 1; i += sizeof(u_int32_t))
BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0)do { pci_conf_write(pa->pa_pc, pa->pa_tag, 0x7C, (0xFFFF8000
 & i)); ((sc->bge_btag)->write_4((sc->bge_bhandle
), (0x00008000 + (i & 0x7FFF)), (0))); } while(0);

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM577650x57785 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM577660x57766) {
/*
 * For the 57766 and non Ax versions of 57765, bootcode
 * needs to setup the PCIE Fast Training Sequence (FTS)
 * value to prevent transmit hangs.
 */
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) != BGE_CHIPREV_57765_AX0x577850) {
    CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3668)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3668
))) | 0x00040000)))
	CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3668)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3668
))) | 0x00040000)))
	BGE_CPMU_PADRNG_CTL_RDIV2)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3668)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3668
))) | 0x00040000)));
}
}

/*
* Set up the PCI DMA control register.
*/
dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6)((6) << 24) |
   BGE_PCIDMARWCTL_WR_CMD_SHIFT(7)((7) << 28);

if (sc->bge_flags & BGE_PCIE0x00000020) {
if (sc->bge_mps >= 256)
	dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7)((7) << 19);
else
	dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3)((3) << 19);
} else if (sc->bge_flags & BGE_PCIX0x00000010) {
/* PCI-X bus */
if (BGE_IS_5714_FAMILY(sc)((sc)->bge_flags & 0x00008000)) {
	/* 256 bytes for read and write. */
	dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2)((2) << 16) |
	    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2)((2) << 19);

	if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57800x08)
		dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL0x00004000;
	else
		dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL0x00008000;
} else if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02) {
	/* 1536 bytes for read, 384 bytes for write. */
	dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7)((7) << 16) |
	    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3)((3) << 19);
} else {
	/* 384 bytes for read and write. */
	dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3)((3) << 16) |
	    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3)((3) << 19) |
	    (0x0F);
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57030x01 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02) {
	u_int32_t tmp;

	/* Set ONEDMA_ATONCE for hardware workaround. */
	tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x74))) & 0x1f;
	if (tmp == 6 || tmp == 7)
		dma_rw_ctl |=
		    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL0x00004000;

	/* Set PCI-X DMA write workaround. */
	dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE0x00800000;
}
} else {
/* Conventional PCI bus: 256 bytes for read and write. */
dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7)((7) << 16) |
    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7)((7) << 19);

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57050x03 &&
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57500x04)
	dma_rw_ctl |= 0x0F;
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57010x00)
dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM0x00400000 |
    BGE_PCIDMARWCTL_ASRT_ALL_BE0x00800000;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57030x01 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA0x000000FF;

if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT0x00000001;
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A00x57785000)
	dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK0x00000380;

/*
 * Enable HW workaround for controllers that misinterpret
 * a status tag update and leave interrupts permanently
 * disabled.
 */
if (!BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000) &&
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57170x5717 &&
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57620x5762)
	dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA0x00000080;
}

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL0x6C, dma_rw_ctl);

/*
* Set up general mode register.
*/
mode_ctl = bge_dma_swap_options(sc);
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762) {
/* Retain Host-2-BMC settings written by APE firmware. */
mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6800))
) &
    (BGE_MODECTL_BYTESWAP_B2HRX_DATA0x00000040 |
    BGE_MODECTL_WORDSWAP_B2HRX_DATA0x00000080 |
    BGE_MODECTL_B2HRX_ENABLE0x00008000 | BGE_MODECTL_HTX2B_ENABLE0x00040000);
}
mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR0x04000000 | BGE_MODECTL_HOST_SEND_BDS0x00020000 |
   BGE_MODECTL_TX_NO_PHDR_CSUM0x00100000;

/*
* BCM5701 B5 have a bug causing data corruption when using
* 64-bit DMA reads, which can be terminated early and then
* completed later as 32-bit accesses, in combination with
* certain bridges.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57010x00 &&
   sc->bge_chipid == BGE_CHIPID_BCM5701_B50x0105)
mode_ctl |= BGE_MODECTL_FORCE_PCI320x00008000;

CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6800)
, (mode_ctl)));

/*
* Disable memory write invalidate.  Apparently it is not supported
* properly by these devices.
*/
PCI_CLRBIT(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,pci_conf_write(pa->pa_pc, pa->pa_tag, 0x04, (pci_conf_read
(pa->pa_pc, pa->pa_tag, 0x04) & ~(0x00000010)))
   PCI_COMMAND_INVALIDATE_ENABLE)pci_conf_write(pa->pa_pc, pa->pa_tag, 0x04, (pci_conf_read
(pa->pa_pc, pa->pa_tag, 0x04) & ~(0x00000010)));

1785#ifdef __brokenalpha__
/*
* Must ensure that we do not cross an 8K (bytes) boundary
* for DMA reads.  Our highest limit is 1K bytes.  This is a
* restriction on some ALPHA platforms with early revision
* 21174 PCI chipsets, such as the AlphaPC 164lx
*/
PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,pci_conf_write(pa->pa_pc, pa->pa_tag, 0x6C, (pci_conf_read
(pa->pa_pc, pa->pa_tag, 0x6C) | (BGE_PCI_READ_BNDRY_1024
)))
   BGE_PCI_READ_BNDRY_1024)pci_conf_write(pa->pa_pc, pa->pa_tag, 0x6C, (pci_conf_read
(pa->pa_pc, pa->pa_tag, 0x6C) | (BGE_PCI_READ_BNDRY_1024
)));
1794#endif

/* Set the timer prescaler (always 66MHz) */
CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6804)
, ((0x41 << 1))));

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c) {
DELAY(40)(*delay_func)(40);	/* XXX */

/* Put PHY into ready state */
BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6804)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6804
))) & ~(0x00200000)))));
CSR_READ_4(sc, BGE_MISC_CFG)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6804))
); /* Flush */
DELAY(40)(*delay_func)(40);
}
1807}

1809int
1810bge_blockinit(struct bge_softc *sc)
1811{
volatile struct bge_rcb		*rcb;
vaddr_t			rcb_addr;
bge_hostaddr		taddr;
u_int32_t		dmactl, rdmareg, mimode, val;
int			i, limit;

/*
* Initialize the memory window pointer register so that
* we can access the first 32K of internal NIC RAM. This will
* allow us to set up the TX send ring RCBs and the RX return
* ring RCBs, plus other things which live in NIC memory.
*/
CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7C), (
0)));

/* Configure mbuf memory pool */
if (!BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4408)
, (0x00008000)))
    BGE_BUFFPOOL_1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4408)
, (0x00008000)));

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02)
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x440C)
, (0x10000)));
else
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x440C)
, (0x18000)));

/* Configure DMA resource pool */
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x442C)
, (0x00002000)))
    BGE_DMA_DESCRIPTORS)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x442C)
, (0x00002000)));
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4430)
, (0x2000)));
}

/* Configure mbuf pool watermarks */
/* new Broadcom docs strongly recommend these: */
if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4410)
, (0x0)));
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4414)
, (0x2a)));
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4418)
, (0xa0)));
} else if (BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4410)
, (0x0)));

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c) {
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4414)
, (0x04)));
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4418)
, (0x10)));
} else {
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4414)
, (0x10)));
	CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4418)
, (0x60)));
}
} else {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4410)
, (0x50)));
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4414)
, (0x20)));
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4418)
, (0x60)));
}

/* Configure DMA resource watermarks */
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4434)
, (5)));
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4438)
, (10)));

/* Enable buffer manager */
val = BGE_BMANMODE_ENABLE0x00000002 | BGE_BMANMODE_LOMBUF_ATTN0x00000010;
/*
* Change the arbitration algorithm of TXMBUF read request to
* round-robin instead of priority based for BCM5719.  When
* TXFIFO is almost empty, RDMA will hold its request until
* TXFIFO is not almost empty.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719)
val |= BGE_BMANMODE_NO_TX_UNDERRUN0x80000000;
CSR_WRITE_4(sc, BGE_BMAN_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4400)
, (val)));

/* Poll for buffer manager start indication */
for (i = 0; i < 2000; i++) {
if (CSR_READ_4(sc, BGE_BMAN_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4400))
) & BGE_BMANMODE_ENABLE0x00000002)
	break;
DELAY(10)(*delay_func)(10);
}

if (i == 2000) {
printf("%s: buffer manager failed to start\n",
    sc->bge_dev.dv_xname);
return (ENXIO6);
}

/* Enable flow-through queues */
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5C00)
, (0xFFFFFFFF)));
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5C00)
, (0)));

/* Wait until queue initialization is complete */
for (i = 0; i < 2000; i++) {
if (CSR_READ_4(sc, BGE_FTQ_RESET)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x5C00))
) == 0)
	break;
DELAY(10)(*delay_func)(10);
}

if (i == 2000) {
printf("%s: flow-through queue init failed\n",
    sc->bge_dev.dv_xname);
return (ENXIO6);
}

/*
* Summary of rings supported by the controller:
*
* Standard Receive Producer Ring
* - This ring is used to feed receive buffers for "standard"
*   sized frames (typically 1536 bytes) to the controller.
*
* Jumbo Receive Producer Ring
* - This ring is used to feed receive buffers for jumbo sized
*   frames (i.e. anything bigger than the "standard" frames)
*   to the controller.
*
* Mini Receive Producer Ring
* - This ring is used to feed receive buffers for "mini"
*   sized frames to the controller.
* - This feature required external memory for the controller
*   but was never used in a production system.  Should always
*   be disabled.
*
* Receive Return Ring
* - After the controller has placed an incoming frame into a
*   receive buffer that buffer is moved into a receive return
*   ring.  The driver is then responsible to passing the
*   buffer up to the stack.  Many versions of the controller
*   support multiple RR rings.
*
* Send Ring
* - This ring is used for outgoing frames.  Many versions of
*   the controller support multiple send rings.
*/

/* Initialize the standard RX ring control block */
rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring))do { (rcb->bge_hostaddr).bge_addr_lo = ((u_int64_t) (((sc)
->bge_ring_map->dm_segs[0].ds_addr + __builtin_offsetof
(struct bge_ring_data, bge_rx_std_ring))) & 0xffffffff); if
 (sizeof(bus_addr_t) == 8) (rcb->bge_hostaddr).bge_addr_hi
 = ((u_int64_t) (((sc)->bge_ring_map->dm_segs[0].ds_addr
 + __builtin_offsetof(struct bge_ring_data, bge_rx_std_ring))
) >> 32); else (rcb->bge_hostaddr).bge_addr_hi = 0; }
 while(0);
if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
/*
 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
 * Bits 15-2 : Maximum RX frame size
 * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
 * Bit 0     : Reserved
 */
rcb->bge_maxlen_flags =
    BGE_RCB_MAXLEN_FLAGS(512, ETHER_MAX_DIX_LEN << 2)((512) << 16 | (1536 << 2));
} else if (BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)) {
/*
 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
 * Bits 15-2 : Reserved (should be 0)
 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 * Bit 0     : Reserved
 */
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0)((512) << 16 | (0));
} else {
/*
 * Ring size is always XXX entries
 * Bits 31-16: Maximum RX frame size
 * Bits 15-2 : Reserved (should be 0)
 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 * Bit 0     : Reserved
 */
rcb->bge_maxlen_flags =
    BGE_RCB_MAXLEN_FLAGS(ETHER_MAX_DIX_LEN, 0)((1536) << 16 | (0));
}
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57170x5717 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720)
rcb->bge_nicaddr = BGE_STD_RX_RINGS_57170x00040000;
else
rcb->bge_nicaddr = BGE_STD_RX_RINGS0x00006000;
/* Write the standard receive producer ring control block. */
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2450)
, (rcb->bge_hostaddr.bge_addr_hi)));
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2454)
, (rcb->bge_hostaddr.bge_addr_lo)));
CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2458)
, (rcb->bge_maxlen_flags)));
CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x245C)
, (rcb->bge_nicaddr)));

/* Reset the standard receive producer ring producer index. */
bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO0x026C, 0);

/*
* Initialize the Jumbo RX ring control block
* We set the 'ring disabled' bit in the flags
* field until we're actually ready to start
* using this ring (i.e. once we set the MTU
* high enough to require it).
*/
if (sc->bge_flags & BGE_JUMBO_RING0x01000000) {
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
BGE_HOSTADDR(rcb->bge_hostaddr,do { (rcb->bge_hostaddr).bge_addr_lo = ((u_int64_t) (((sc)
->bge_ring_map->dm_segs[0].ds_addr + __builtin_offsetof
(struct bge_ring_data, bge_rx_jumbo_ring))) & 0xffffffff)
; if (sizeof(bus_addr_t) == 8) (rcb->bge_hostaddr).bge_addr_hi
 = ((u_int64_t) (((sc)->bge_ring_map->dm_segs[0].ds_addr
 + __builtin_offsetof(struct bge_ring_data, bge_rx_jumbo_ring
))) >> 32); else (rcb->bge_hostaddr).bge_addr_hi = 0
; } while(0)
    BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring))do { (rcb->bge_hostaddr).bge_addr_lo = ((u_int64_t) (((sc)
->bge_ring_map->dm_segs[0].ds_addr + __builtin_offsetof
(struct bge_ring_data, bge_rx_jumbo_ring))) & 0xffffffff)
; if (sizeof(bus_addr_t) == 8) (rcb->bge_hostaddr).bge_addr_hi
 = ((u_int64_t) (((sc)->bge_ring_map->dm_segs[0].ds_addr
 + __builtin_offsetof(struct bge_ring_data, bge_rx_jumbo_ring
))) >> 32); else (rcb->bge_hostaddr).bge_addr_hi = 0
; } while(0);
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,((0) << 16 | (0x0001 | 0x0002))
    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED)((0) << 16 | (0x0001 | 0x0002));
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57170x5717 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720)
	rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_57170x00044400;
else
	rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS0x00007000;
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2440)
, (rcb->bge_hostaddr.bge_addr_hi)))
    rcb->bge_hostaddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2440)
, (rcb->bge_hostaddr.bge_addr_hi)));
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2444)
, (rcb->bge_hostaddr.bge_addr_lo)))
    rcb->bge_hostaddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2444)
, (rcb->bge_hostaddr.bge_addr_lo)));
/* Program the jumbo receive producer ring RCB parameters. */
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2448)
, (rcb->bge_maxlen_flags)))
    rcb->bge_maxlen_flags)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2448)
, (rcb->bge_maxlen_flags)));
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x244C)
, (rcb->bge_nicaddr)));
/* Reset the jumbo receive producer ring producer index. */
bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO0x0274, 0);
}

/* Disable the mini receive producer ring RCB. */
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000)) {
/* Set up dummy disabled mini ring RCB */
rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
rcb->bge_maxlen_flags =
    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)((0) << 16 | (0x0002));
CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2468)
, (rcb->bge_maxlen_flags)))
    rcb->bge_maxlen_flags)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2468)
, (rcb->bge_maxlen_flags)));
/* Reset the mini receive producer ring producer index. */
bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO0x027C, 0);

/* XXX why? */
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_info)), (sizeof (struct bge_gib)), (0x01|0x04))
    offsetof(struct bge_ring_data, bge_info),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_info)), (sizeof (struct bge_gib)), (0x01|0x04))
    sizeof (struct bge_gib),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_info)), (sizeof (struct bge_gib)), (0x01|0x04))
    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_info)), (sizeof (struct bge_gib)), (0x01|0x04));
}

/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c) {
if (sc->bge_chipid == BGE_CHIPID_BCM5906_A00xc000 ||
    sc->bge_chipid == BGE_CHIPID_BCM5906_A10xc001 ||
    sc->bge_chipid == BGE_CHIPID_BCM5906_A20xc002)
	CSR_WRITE_4(sc, BGE_ISO_PKT_TX,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C20)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0C20
))) & ~3) | 2)))
	    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C20)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0C20
))) & ~3) | 2)));
}
/*
* The BD ring replenish thresholds control how often the
* hardware fetches new BD's from the producer rings in host
* memory.  Setting the value too low on a busy system can
* starve the hardware and recue the throughput.
*
* Set the BD ring replenish thresholds. The recommended
* values are 1/8th the number of descriptors allocated to
* each ring, but since we try to avoid filling the entire
* ring we set these to the minimal value of 8.  This needs to
* be done on several of the supported chip revisions anyway,
* to work around HW bugs.
*/
CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2C18)
, (8)));
if (sc->bge_flags & BGE_JUMBO_RING0x01000000)
CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2C1C)
, (8)));

if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2D00)
, (4)));
CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2D04)
, (4)));
}

/*
* Disable all send rings by setting the 'ring disabled' bit
* in the flags field of all the TX send ring control blocks,
* located in NIC memory.
*/
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000)) {
/* 5700 to 5704 had 16 send rings. */
limit = BGE_TX_RINGS_EXTSSRAM_MAX16;
} else if (BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000) ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762)
limit = 2;
else if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000))
limit = 4;
else
limit = 1;
rcb_addr = BGE_MEMWIN_START0x00008000 + BGE_SEND_RING_RCB0x00000100;
for (i = 0; i < limit; i++) {
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
0) << 16 | (0x0002)))))
    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED))((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
0) << 16 | (0x0002)))));
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0)));
rcb_addr += sizeof(struct bge_rcb);
}

/* Configure send ring RCB 0 (we use only the first ring) */
rcb_addr = BGE_MEMWIN_START0x00008000 + BGE_SEND_RING_RCB0x00000100;
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring))do { (taddr).bge_addr_lo = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_tx_ring))) & 0xffffffff); if (sizeof(bus_addr_t) ==
 8) (taddr).bge_addr_hi = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_tx_ring))) >> 32); else (taddr).bge_addr_hi = 0; }
 while(0);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_hi
)), (taddr.bge_addr_hi)));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_lo
)), (taddr.bge_addr_lo)));
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57170x5717 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720)
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0x00004000
)));
else
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0x00004000
 + ((0 * sizeof(struct bge_tx_bd) * 512) / 4))))
    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT))((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0x00004000
 + ((0 * sizeof(struct bge_tx_bd) * 512) / 4))));
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
512) << 16 | (0)))))
   BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0))((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
512) << 16 | (0)))));

/*
* Disable all receive return rings by setting the
* 'ring disabled' bit in the flags field of all the receive
* return ring control blocks, located in NIC memory.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57170x5717 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720) {
/* Should be 17, use 16 until we get an SRAM map. */
limit = 16;
} else if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000))
limit = BGE_RX_RINGS_MAX16;
else if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57550x0a ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762 ||
   BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000))
limit = 4;
else
limit = 1;
/* Disable all receive return rings */
rcb_addr = BGE_MEMWIN_START0x00008000 + BGE_RX_RETURN_RING_RCB0x00000200;
for (i = 0; i < limit; i++) {
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_hi
)), (0)));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_lo
)), (0)));
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
sc->bge_return_ring_cnt) << 16 | (0x0002)))))
    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
sc->bge_return_ring_cnt) << 16 | (0x0002)))))
	BGE_RCB_FLAG_RING_DISABLED))((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
sc->bge_return_ring_cnt) << 16 | (0x0002)))));
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0)));
bge_writembx(sc, BGE_MBX_RX_CONS0_LO0x0284 +
    (i * (sizeof(u_int64_t))), 0);
rcb_addr += sizeof(struct bge_rcb);
}

/*
* Set up receive return ring 0.  Note that the NIC address
* for RX return rings is 0x0.  The return rings live entirely
* within the host, so the nicaddr field in the RCB isn't used.
*/
rcb_addr = BGE_MEMWIN_START0x00008000 + BGE_RX_RETURN_RING_RCB0x00000200;
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring))do { (taddr).bge_addr_lo = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_rx_return_ring))) & 0xffffffff); if (sizeof(bus_addr_t
) == 8) (taddr).bge_addr_hi = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_rx_return_ring))) >> 32); else (taddr).bge_addr_hi
 = 0; } while(0);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_hi
)), (taddr.bge_addr_hi)));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_hostaddr.bge_addr_lo
)), (taddr.bge_addr_lo)));
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000)((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_nicaddr)), (0x00000000
)));
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
sc->bge_return_ring_cnt) << 16 | (0)))))
   BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0))((sc->bge_btag)->write_4((sc->bge_bhandle), (rcb_addr
 + __builtin_offsetof(struct bge_rcb, bge_maxlen_flags)), (((
sc->bge_return_ring_cnt) << 16 | (0)))));

/* Set random backoff seed for TX */
CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0438)
, ((sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + sc
->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 0x3FF
)))
   (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0438)
, ((sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + sc
->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 0x3FF
)))
    sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0438)
, ((sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + sc
->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 0x3FF
)))
    sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) &((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0438)
, ((sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + sc
->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 0x3FF
)))
   BGE_TX_BACKOFF_SEED_MASK)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0438)
, ((sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + sc
->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 0x3FF
)));

/* Set inter-packet gap */
val = 0x2620;
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762)
val |= CSR_READ_4(sc, BGE_TX_LENGTHS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0464))
) &
    (BGE_TXLEN_JMB_FRM_LEN_MSK0x00FF0000 | BGE_TXLEN_CNT_DN_VAL_MSK0xFF000000);
CSR_WRITE_4(sc, BGE_TX_LENGTHS, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0464)
, (val)));

/*
* Specify which ring to use for packets that don't match
* any RX rules.
*/
CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0500)
, (0x08)));

/*
* Configure number of RX lists. One interrupt distribution
* list, sixteen active lists, one bad frames class.
*/
CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2010)
, (0x181)));

/* Initialize RX list placement stats mask. */
CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007BFFFF)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2018)
, (0x007BFFFF)));
CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2014)
, (0x1)));

/* Disable host coalescing until we get it set up */
CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C00)
, (0x00000000)));

/* Poll to make sure it's shut down. */
for (i = 0; i < 2000; i++) {
if (!(CSR_READ_4(sc, BGE_HCC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3C00))
) & BGE_HCCMODE_ENABLE0x00000002))
	break;
DELAY(10)(*delay_func)(10);
}

if (i == 2000) {
printf("%s: host coalescing engine failed to idle\n",
    sc->bge_dev.dv_xname);
return (ENXIO6);
}

/* Set up host coalescing defaults */
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C08)
, (sc->bge_rx_coal_ticks)));
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C0C)
, (sc->bge_tx_coal_ticks)));
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C10)
, (sc->bge_rx_max_coal_bds)));
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C14)
, (sc->bge_tx_max_coal_bds)));
if (!(BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000))) {
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C18)
, (0)));
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C1C)
, (0)));
}
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C20)
, (0)));
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C24)
, (0)));

/* Set up address of statistics block */
if (!(BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000))) {
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats))do { (taddr).bge_addr_lo = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_info.bge_stats))) & 0xffffffff); if (sizeof(bus_addr_t
) == 8) (taddr).bge_addr_hi = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_info.bge_stats))) >> 32); else (taddr).bge_addr_hi
 = 0; } while(0);
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C30)
, (taddr.bge_addr_hi)));
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C34)
, (taddr.bge_addr_lo)));

CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C40)
, (0x00000300)));
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C44)
, (0x00000B00)));
CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C28)
, (sc->bge_stat_ticks)));
}

/* Set up address of status block */
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block))do { (taddr).bge_addr_lo = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_status_block))) & 0xffffffff); if (sizeof(bus_addr_t
) == 8) (taddr).bge_addr_hi = ((u_int64_t) (((sc)->bge_ring_map
->dm_segs[0].ds_addr + __builtin_offsetof(struct bge_ring_data
, bge_status_block))) >> 32); else (taddr).bge_addr_hi =
 0; } while(0);
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C38)
, (taddr.bge_addr_hi)));
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C3C)
, (taddr.bge_addr_lo)));

sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;

/* Set up status block size. */
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 &&
   sc->bge_chipid != BGE_CHIPID_BCM5700_C00x7200) {
val = BGE_STATBLKSZ_FULL0x00000000;
bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ)__builtin_bzero((&sc->bge_rdata->bge_status_block),
 (sizeof (struct bge_status_block)));
} else {
val = BGE_STATBLKSZ_32BYTE0x00000100;
bzero(&sc->bge_rdata->bge_status_block, 32)__builtin_bzero((&sc->bge_rdata->bge_status_block),
 (32));
}

/* Turn on host coalescing state machine */
CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C00)
, (val | 0x00000002)));

/* Turn on RX BD completion state machine and enable attentions */
CSR_WRITE_4(sc, BGE_RBDC_MODE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3000)
, (0x00000002|0x00000004)))
   BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3000)
, (0x00000002|0x00000004)));

/* Turn on RX list placement state machine */
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2000)
, (0x00000002)));

/* Turn on RX list selector state machine. */
if (!(BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)))
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3400)
, (0x00000002)));

val = BGE_MACMODE_TXDMA_ENB0x00200000 | BGE_MACMODE_RXDMA_ENB0x00400000 |
   BGE_MACMODE_RX_STATS_CLEAR0x00001000 | BGE_MACMODE_TX_STATS_CLEAR0x00008000 |
   BGE_MACMODE_RX_STATS_ENB0x00000800 | BGE_MACMODE_TX_STATS_ENB0x00004000 |
   BGE_MACMODE_FRMHDR_DMA_ENB0x00800000;

if (sc->bge_flags & BGE_FIBER_TBI0x00000200)
   val |= BGE_PORTMODE_TBI0x0000000C;
else if (sc->bge_flags & BGE_FIBER_MII0x00000400)
   val |= BGE_PORTMODE_GMII0x00000008;
else
   val |= BGE_PORTMODE_MII0x00000004;

/* Allow APE to send/receive frames. */
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) != 0)
val |= BGE_MACMODE_APE_RX_EN0x08000000 | BGE_MACMODE_APE_TX_EN0x10000000;

/* Turn on DMA, clear stats */
CSR_WRITE_4(sc, BGE_MAC_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, (val)));
DELAY(40)(*delay_func)(40);

/* Set misc. local control, enable interrupts on attentions */
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00000008)))));

2274#ifdef notdef
/* Assert GPIO pins for PHY reset */
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00004000| 0x00008000|0x00010000)))))
   BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00004000| 0x00008000|0x00010000)))));
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00000800| 0x00001000|0x00002000)))))
   BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00000800| 0x00001000|0x00002000)))));
2280#endif

/* Turn on DMA completion state machine */
if (!(BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)))
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6400)
, (0x00000002)));

val = BGE_WDMAMODE_ENABLE0x00000002|BGE_WDMAMODE_ALL_ATTNS0x000003FC;

/* Enable host coalescing bug fix. */
if (BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000))
val |= BGE_WDMAMODE_STATUS_TAG_FIX0x20000000;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57850x5785)
val |= BGE_WDMAMODE_BURST_ALL_DATA0xC0000000;

/* Turn on write DMA state machine */
CSR_WRITE_4(sc, BGE_WDMA_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4C00)
, (val)));
DELAY(40)(*delay_func)(40);

val = BGE_RDMAMODE_ENABLE0x00000002|BGE_RDMAMODE_ALL_ATTNS0x000003FC;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57170x5717)
val |= BGE_RDMAMODE_MULT_DMA_RD_DIS0x01000000;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57840x5784 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57850x5785 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM577800x57780)
val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN0x00000800 |
       BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN0x00001000 |
       BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN0x00002000;

if (sc->bge_flags & BGE_PCIE0x00000020)
val |= BGE_RDMAMODE_FIFO_LONG_BURST0x00030000;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762) {
val |= CSR_READ_4(sc, BGE_RDMA_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4800))
) &
    BGE_RDMAMODE_H2BNC_VLAN_DET0x20000000;
/*
 * Allow multiple outstanding read requests from
 * non-LSO read DMA engine.
 */
val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS0x01000000;
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57840x5784 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57850x5785 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM577800x57780 ||
   BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000) || BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000)) {
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762)
	rdmareg = BGE_RDMA_RSRVCTRL_REG20x4890;
else
	rdmareg = BGE_RDMA_RSRVCTRL0x4900;
dmactl = CSR_READ_4(sc, rdmareg)((sc->bge_btag)->read_4((sc->bge_bhandle), (rdmareg)
));
/*
 * Adjust tx margin to prevent TX data corruption and
 * fix internal FIFO overflow.
 */
if (sc->bge_chipid == BGE_CHIPID_BCM5719_A00x05719000 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762) {
	dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK0x00000FF0 |
	    BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK0x000FF000 |
	    BGE_RDMA_RSRVCTRL_TXMRGN_MASK0xFFE00000);
	dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K0x00000C00 |
	    BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K0x000C0000 |
	    BGE_RDMA_RSRVCTRL_TXMRGN_320B0x28000000;
}
/*
 * Enable fix for read DMA FIFO overruns.
 * The fix is to limit the number of RX BDs
 * the hardware would fetch at a time.
 */
CSR_WRITE_4(sc, rdmareg, dmactl |((sc->bge_btag)->write_4((sc->bge_bhandle), (rdmareg
), (dmactl | 0x00000004)))
    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX)((sc->bge_btag)->write_4((sc->bge_bhandle), (rdmareg
), (dmactl | 0x00000004)));
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719) {
CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00030000 | 0x000C0000)))
    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00030000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00030000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00030000 | 0x000C0000)));
} else if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720) {
/*
 * Allow 4KB burst length reads for non-LSO frames.
 * Enable 512B burst length reads for buffer descriptors.
 */
CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00020000 | 0x000C0000)))
    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00020000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00020000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910
))) | 0x00020000 | 0x000C0000)));
} else if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762) {
CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x48A0)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x48A0
))) | 0x00030000 | 0x000C0000)))
    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x48A0)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x48A0
))) | 0x00030000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x48A0)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x48A0
))) | 0x00030000 | 0x000C0000)))
    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x48A0)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x48A0
))) | 0x00030000 | 0x000C0000)));
}

CSR_WRITE_4(sc, BGE_RDMA_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4800)
, (val)));
DELAY(40)(*delay_func)(40);

if (sc->bge_flags & BGE_RDMA_BUG0x00800000) {
for (i = 0; i < BGE_NUM_RDMA_CHANNELS4 / 2; i++) {
	val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4BE0 +
 i * 4)));
	if ((val & 0xFFFF) > ETHER_MAX_LEN1518)
		break;
	if (((val >> 16) & 0xFFFF) > ETHER_MAX_LEN1518)
		break;
}
if (i != BGE_NUM_RDMA_CHANNELS4 / 2) {
	val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910))
);
	if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719)
		val |= BGE_RDMA_TX_LENGTH_WA_57190x02000000;
	else
		val |= BGE_RDMA_TX_LENGTH_WA_57200x00200000;
	CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (val)));
}
}

/* Turn on RX data completion state machine */
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2800)
, (0x00000002)));

/* Turn on RX BD initiator state machine */
CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2C00)
, (0x00000002)));

/* Turn on RX data and RX BD initiator state machine */
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x2400)
, (0x00000002)));

/* Turn on Mbuf cluster free state machine */
if (!BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000))
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3800)
, (0x00000002)));

/* Turn on send BD completion state machine */
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x1C00)
, (0x00000002)));

/* Turn on send data completion state machine */
val = BGE_SDCMODE_ENABLE0x00000002;
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761)
val |= BGE_SDCMODE_CDELAY0x00000010;
CSR_WRITE_4(sc, BGE_SDC_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x1000)
, (val)));

/* Turn on send data initiator state machine */
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C00)
, (0x00000002)));

/* Turn on send BD initiator state machine */
CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x1800)
, (0x00000002)));

/* Turn on send BD selector state machine */
CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x1400)
, (0x00000002)));

CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007BFFFF)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C0C)
, (0x007BFFFF)));
CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C08)
, (0x00000001|0x00000002)))
   BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0C08)
, (0x00000001|0x00000002)));

/* ack/clear link change events */
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010 | 0x00000008 | 0x00400000 | 0x00001000)))
   BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010 | 0x00000008 | 0x00400000 | 0x00001000)))
   BGE_MACSTAT_LINK_CHANGED)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010 | 0x00000008 | 0x00400000 | 0x00001000)));

/* Enable PHY auto polling (for MII/GMII only) */
if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0450)
, (0x00000001)));
} else {
if ((sc->bge_flags & BGE_CPMU_PRESENT0x00100000) != 0)
	mimode = BGE_MIMODE_500KHZ_CONST0x00008000;
else
	mimode = BGE_MIMODE_BASE0x000C0000;
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000) ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57050x03) {
	mimode |= BGE_MIMODE_AUTOPOLL0x00000010;
	BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts |= (0x00000004));
}
mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr)((sc->bge_phy_addr & 0x1F) << 5);
CSR_WRITE_4(sc, BGE_MI_MODE, mimode)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0454)
, (mimode)));
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07)
	CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0408)
, (0x00800000)))
	    BGE_EVTENB_MI_INTERRUPT)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0408)
, (0x00800000)));
}

/*
* Clear any pending link state attention.
* Otherwise some link state change events may be lost until attention
* is cleared by bge_intr() -> bge_link_upd() sequence.
* It's not necessary on newer BCM chips - perhaps enabling link
* state change attentions implies clearing pending attention.
*/
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)))
   BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)))
   BGE_MACSTAT_LINK_CHANGED)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)));

/* Enable link state change attentions. */
BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0408)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0408
))) | (0x00001000)))));

return (0);
2474}

2476const struct bge_revision *
2477bge_lookup_rev(u_int32_t chipid)
2478{
const struct bge_revision *br;

for (br = bge_revisions; br->br_name != NULL((void *)0); br++) {
if (br->br_chipid == chipid)
	return (br);
}

for (br = bge_majorrevs; br->br_name != NULL((void *)0); br++) {
if (br->br_chipid == BGE_ASICREV(chipid)((chipid) >> 12))
	return (br);
}

return (NULL((void *)0));
2492}

2494int
2495bge_can_use_msi(struct bge_softc *sc)
2496{
int can_use_msi = 0;

switch (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12)) {
case BGE_ASICREV_BCM5714_A00x05:
case BGE_ASICREV_BCM57140x09:
/*
 * Apparently, MSI doesn't work when these chips are
 * configured in single-port mode.
 */
break;
case BGE_ASICREV_BCM57500x04:
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) != BGE_CHIPREV_5750_AX0x40 &&
    BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) != BGE_CHIPREV_5750_BX0x41)
	can_use_msi = 1;
break;
default:
if (BGE_IS_575X_PLUS(sc)((sc)->bge_flags & 0x00002000))
	can_use_msi = 1;
}

return (can_use_msi);
2518}

2520/*
* Probe for a Broadcom chip. Check the PCI vendor and device IDs
* against our list and return its name if we find a match. Note
* that since the Broadcom controller contains VPD support, we
* can get the device name string from the controller itself instead
* of the compiled-in string. This is a little slow, but it guarantees
* we'll always announce the right product name.
*/
2528int
2529bge_probe(struct device *parent, void *match, void *aux)
2530{
return (pci_matchbyid(aux, bge_devices, nitems(bge_devices)(sizeof((bge_devices)) / sizeof((bge_devices)[0]))));
2532}

2534void
2535bge_attach(struct device *parent, struct device *self, void *aux)
2536{
struct bge_softc	*sc = (struct bge_softc *)self;
struct pci_attach_args	*pa = aux;
pci_chipset_tag_t	pc = pa->pa_pc;
const struct bge_revision *br;
pcireg_t		pm_ctl, memtype, subid, reg;
pci_intr_handle_t	ih;
const char		*intrstr = NULL((void *)0);
int			gotenaddr = 0;
u_int32_t		hwcfg = 0;
u_int32_t		mac_addr = 0;
u_int32_t		misccfg;
struct ifnet		*ifp;
caddr_t			kva;
2550#ifdef __sparc64__
char			name[32];
2552#endif

sc->bge_pa = *pa;

subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG0x2c);

/*
* Map control/status registers.
*/
DPRINTFN(5, ("Map control/status regs\n"));

DPRINTFN(5, ("pci_mapreg_map\n"));
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR00x10);
if (pci_mapreg_map(pa, BGE_PCI_BAR00x10, memtype, 0, &sc->bge_btag,
   &sc->bge_bhandle, NULL((void *)0), &sc->bge_bsize, 0)) {
printf(": can't find mem space\n");
return;
}

/*
* Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
* can clobber the chip's PCI config-space power control registers,
* leaving the card in D3 powersave state.
* We do not have memory-mapped registers in this state,
* so force device into D0 state before starting initialization.
*/
pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD0x4C);
pm_ctl &= ~(PCI_PWR_D00|PCI_PWR_D11|PCI_PWR_D22|PCI_PWR_D33);
pm_ctl |= (1 << 8) | PCI_PWR_D00 ; /* D0 state */
pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD0x4C, pm_ctl);
DELAY(1000)(*delay_func)(1000);	/* 27 usec is allegedly sufficient */

/*
* Save ASIC rev.
*/
sc->bge_chipid =
    (pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL0x68)
     >> BGE_PCIMISCCTL_ASICREV_SHIFT16);

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_USE_PRODID_REG0x0f) {
switch (PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff)) {
case PCI_PRODUCT_BROADCOM_BCM57170x1655:
case PCI_PRODUCT_BROADCOM_BCM57180x1656:
case PCI_PRODUCT_BROADCOM_BCM57190x1657:
case PCI_PRODUCT_BROADCOM_BCM57200x165f:
case PCI_PRODUCT_BROADCOM_BCM57250x1643:
case PCI_PRODUCT_BROADCOM_BCM57270x16f3:
case PCI_PRODUCT_BROADCOM_BCM57620x1687:
case PCI_PRODUCT_BROADCOM_BCM577640x1642:
case PCI_PRODUCT_BROADCOM_BCM577670x1683:
case PCI_PRODUCT_BROADCOM_BCM577870x1641:
	sc->bge_chipid = pci_conf_read(pc, pa->pa_tag,
	    BGE_PCI_GEN2_PRODID_ASICREV0xF4);
	break;
case PCI_PRODUCT_BROADCOM_BCM577610x16b0:
case PCI_PRODUCT_BROADCOM_BCM577620x1682:
case PCI_PRODUCT_BROADCOM_BCM577650x16b4:
case PCI_PRODUCT_BROADCOM_BCM577660x1686:
case PCI_PRODUCT_BROADCOM_BCM577810x16b1:
case PCI_PRODUCT_BROADCOM_BCM577820x16b7:
case PCI_PRODUCT_BROADCOM_BCM577850x16b5:
case PCI_PRODUCT_BROADCOM_BCM577860x16b3:
case PCI_PRODUCT_BROADCOM_BCM577910x16b2:
case PCI_PRODUCT_BROADCOM_BCM577950x16b6:
	sc->bge_chipid = pci_conf_read(pc, pa->pa_tag,
	    BGE_PCI_GEN15_PRODID_ASICREV0xFC);
	break;
default:
	sc->bge_chipid = pci_conf_read(pc, pa->pa_tag,
	    BGE_PCI_PRODID_ASICREV0xBC);
	break;
}
}

sc->bge_phy_addr = bge_phy_addr(sc);

printf(", ");
br = bge_lookup_rev(sc->bge_chipid);
if (br == NULL((void *)0))
printf("unknown ASIC (0x%x)", sc->bge_chipid);
else
printf("%s (0x%x)", br->br_name, sc->bge_chipid);

/*
* PCI Express or PCI-X controller check.
*/
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS0x10,
   &sc->bge_expcap, NULL((void *)0)) != 0) {
/* Extract supported maximum payload size. */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, sc->bge_expcap +
    PCI_PCIE_DCAP0x04);
sc->bge_mps = 128 << (reg & 0x7);
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720)
	sc->bge_expmrq = (fls(2048) - 8) << 12;
else
	sc->bge_expmrq = (fls(4096) - 8) << 12;
/* Disable PCIe Active State Power Management (ASPM). */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
    sc->bge_expcap + PCI_PCIE_LCSR0x10);
reg &= ~(PCI_PCIE_LCSR_ASPM_L0S0x00000001 | PCI_PCIE_LCSR_ASPM_L10x00000002);
pci_conf_write(pa->pa_pc, pa->pa_tag,
    sc->bge_expcap + PCI_PCIE_LCSR0x10, reg);
sc->bge_flags |= BGE_PCIE0x00000020;
} else {
if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE0x70) &
    BGE_PCISTATE_PCI_BUSMODE0x00000004) == 0)
	sc->bge_flags |= BGE_PCIX0x00000010;
}

/*
* SEEPROM check.
*/
2665#ifdef __sparc64__
/*
* Onboard interfaces on UltraSPARC systems generally don't
* have a SEEPROM fitted.  These interfaces, and cards that
* have FCode, are named "network" by the PROM, whereas cards
* without FCode show up as "ethernet".  Since we don't really
* need the information from the SEEPROM on cards that have
* FCode it's fine to pretend they don't have one.
*/
if (OF_getprop(PCITAG_NODE(pa->pa_tag), "name", name,
   sizeof(name)) > 0 && strcmp(name, "network") == 0)
sc->bge_flags |= BGE_NO_EEPROM0x00000080;
2677#endif

/* Save chipset family. */
switch (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12)) {
case BGE_ASICREV_BCM57620x5762:
case BGE_ASICREV_BCM577650x57785:
case BGE_ASICREV_BCM577660x57766:
sc->bge_flags |= BGE_57765_PLUS0x00040000;
/* FALLTHROUGH */
case BGE_ASICREV_BCM57170x5717:
case BGE_ASICREV_BCM57190x5719:
case BGE_ASICREV_BCM57200x5720:
sc->bge_flags |= BGE_5717_PLUS0x00020000 | BGE_5755_PLUS0x00004000 | BGE_575X_PLUS0x00002000 |
    BGE_5705_PLUS0x00001000 | BGE_JUMBO_CAPABLE0x00000100 | BGE_JUMBO_RING0x01000000 |
    BGE_JUMBO_FRAME0x04000000;
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720) {
	/*
	 * Enable work around for DMA engine miscalculation
	 * of TXMBUF available space.
	 */
	sc->bge_flags |= BGE_RDMA_BUG0x00800000;

	if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719 &&
	    sc->bge_chipid == BGE_CHIPID_BCM5719_A00x05719000) {
		/* Jumbo frame on BCM5719 A0 does not work. */
		sc->bge_flags &= ~(BGE_JUMBO_CAPABLE0x00000100 |
		    BGE_JUMBO_RING0x01000000 | BGE_JUMBO_FRAME0x04000000);
	}
}
break;
case BGE_ASICREV_BCM57550x0a:
case BGE_ASICREV_BCM57610x5761:
case BGE_ASICREV_BCM57840x5784:
case BGE_ASICREV_BCM57850x5785:
case BGE_ASICREV_BCM57870x0b:
case BGE_ASICREV_BCM577800x57780:
sc->bge_flags |= BGE_5755_PLUS0x00004000 | BGE_575X_PLUS0x00002000 | BGE_5705_PLUS0x00001000;
break;
case BGE_ASICREV_BCM57000x07:
case BGE_ASICREV_BCM57010x00:
case BGE_ASICREV_BCM57030x01:
case BGE_ASICREV_BCM57040x02:
sc->bge_flags |= BGE_5700_FAMILY0x00010000 | BGE_JUMBO_CAPABLE0x00000100 | BGE_JUMBO_RING0x01000000;
break;
case BGE_ASICREV_BCM5714_A00x05:
case BGE_ASICREV_BCM57800x08:
case BGE_ASICREV_BCM57140x09:
sc->bge_flags |= BGE_5714_FAMILY0x00008000 | BGE_JUMBO_CAPABLE0x00000100 | BGE_JUMBO_STD0x02000000;
/* FALLTHROUGH */
case BGE_ASICREV_BCM57500x04:
case BGE_ASICREV_BCM57520x06:
case BGE_ASICREV_BCM59060x0c:
sc->bge_flags |= BGE_575X_PLUS0x00002000;
/* FALLTHROUGH */
case BGE_ASICREV_BCM57050x03:
sc->bge_flags |= BGE_5705_PLUS0x00001000;
break;
}

if (sc->bge_flags & BGE_JUMBO_STD0x02000000)
sc->bge_rx_std_len = BGE_JLEN((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))));
else
sc->bge_rx_std_len = MCLBYTES(1 << 11);

/*
* When using the BCM5701 in PCI-X mode, data corruption has
* been observed in the first few bytes of some received packets.
* Aligning the packet buffer in memory eliminates the corruption.
* Unfortunately, this misaligns the packet payloads.  On platforms
* which do not support unaligned accesses, we will realign the
* payloads by copying the received packets.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57010x00 &&
   sc->bge_flags & BGE_PCIX0x00000010)
sc->bge_flags |= BGE_RX_ALIGNBUG0x00000008;

if ((BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57010x00) &&
   PCI_VENDOR(subid)(((subid) >> 0) & 0xffff) == DELL_VENDORID0x1028)
sc->bge_phy_flags |= BGE_PHY_NO_3LED0x00000001;

misccfg = CSR_READ_4(sc, BGE_MISC_CFG)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6804))
);
misccfg &= BGE_MISCCFG_BOARD_ID_MASK0x0001E000;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57050x03 &&
   (misccfg == BGE_MISCCFG_BOARD_ID_57880x00010000 ||
    misccfg == BGE_MISCCFG_BOARD_ID_5788M0x00018000))
sc->bge_flags |= BGE_IS_57880x00000800;

if ((BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57030x01 &&
    (misccfg == 0x4000 || misccfg == 0x8000)) ||
   (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57050x03 &&
    PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff) == PCI_VENDOR_BROADCOM0x14e4 &&
    (PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM59010x170d ||
     PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5901A20x170e ||
     PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5705F0x166e)) ||
   (PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff) == PCI_VENDOR_BROADCOM0x14e4 &&
    (PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5751F0x167e ||
     PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5753F0x16fe ||
     PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5787F0x167f)) ||
   PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM577900x1694 ||
   PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM577910x16b2 ||
   PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM577950x16b6 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c)
sc->bge_phy_flags |= BGE_PHY_10_100_ONLY0x00000002;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 ||
   (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57050x03 &&
    (sc->bge_chipid != BGE_CHIPID_BCM5705_A00x3000 &&
     sc->bge_chipid != BGE_CHIPID_BCM5705_A10x3001)) ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c)
sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED0x00000100;

if (sc->bge_chipid == BGE_CHIPID_BCM5701_A00x0000 ||
   sc->bge_chipid == BGE_CHIPID_BCM5701_B00x0100)
sc->bge_phy_flags |= BGE_PHY_CRC_BUG0x00000004;
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5703_AX0x10 ||
   BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5704_AX0x20)
sc->bge_phy_flags |= BGE_PHY_ADC_BUG0x00000008;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A00x2000)
sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG0x00008010;

if ((BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)) &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM59060x0c &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57850x5785 &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM577800x57780 &&
   !BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57550x0a ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57840x5784 ||
    BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57870x0b) {
	if (PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) != PCI_PRODUCT_BROADCOM_BCM57220x165a &&
	    PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) != PCI_PRODUCT_BROADCOM_BCM57560x1674)
		sc->bge_phy_flags |= BGE_PHY_JITTER_BUG0x00000020;
	if (PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == PCI_PRODUCT_BROADCOM_BCM5755M0x1673)
		sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM0x00000080;
} else
	sc->bge_phy_flags |= BGE_PHY_BER_BUG0x00000040;
}

/* Identify chips with APE processor. */
switch (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12)) {
case BGE_ASICREV_BCM57170x5717:
case BGE_ASICREV_BCM57190x5719:
case BGE_ASICREV_BCM57200x5720:
case BGE_ASICREV_BCM57610x5761:
case BGE_ASICREV_BCM57620x5762:
sc->bge_flags |= BGE_APE0x00080000;
break;
}

/* Chips with APE need BAR2 access for APE registers/memory. */
if ((sc->bge_flags & BGE_APE0x00080000) != 0) {
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR20x18);
if (pci_mapreg_map(pa, BGE_PCI_BAR20x18, memtype, 0,
    &sc->bge_apetag, &sc->bge_apehandle, NULL((void *)0),
    &sc->bge_apesize, 0)) {
	printf(": couldn't map BAR2 memory\n");
	goto fail_1;
}

/* Enable APE register/memory access by host driver. */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE0x70);
reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR0x00010000 |
    BGE_PCISTATE_ALLOW_APE_SHMEM_WR0x00020000 |
    BGE_PCISTATE_ALLOW_APE_PSPACE_WR0x00040000;
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE0x70, reg);

bge_ape_lock_init(sc);
bge_ape_read_fw_ver(sc);
}

/* Identify the chips that use an CPMU. */
if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000) ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57840x5784 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57610x5761 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57850x5785 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM577800x57780)
sc->bge_flags |= BGE_CPMU_PRESENT0x00100000;

if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI0x05,
   &sc->bge_msicap, NULL((void *)0))) {
if (bge_can_use_msi(sc) == 0)
	pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED0x20;
}

DPRINTFN(5, ("pci_intr_map\n"));
if (pci_intr_map_msi(pa, &ih) == 0)
sc->bge_flags |= BGE_MSI0x00400000;
else if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
goto fail_1;
}

/*
* All controllers except BCM5700 supports tagged status but
* we use tagged status only for MSI case on BCM5717. Otherwise
* MSI on BCM5717 does not work.
*/
if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000) && sc->bge_flags & BGE_MSI0x00400000)
sc->bge_flags |= BGE_TAGGED_STATUS0x00200000;

DPRINTFN(5, ("pci_intr_string\n"));
intrstr = pci_intr_string(pc, ih);

/* Try to reset the chip. */
DPRINTFN(5, ("bge_reset\n"));
bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN0);
bge_reset(sc);

bge_sig_legacy(sc, BGE_RESET_SHUTDOWN0);
bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN0);

bge_chipinit(sc);

2893#if defined(__sparc64__) || defined(__HAVE_FDT)
if (!gotenaddr && PCITAG_NODE(pa->pa_tag)) {
if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address",
    sc->arpcom.ac_enaddr, ETHER_ADDR_LEN6) == ETHER_ADDR_LEN6)
	gotenaddr = 1;
}
2899#endif

/*
* Get station address from the EEPROM.
*/
if (!gotenaddr) {
mac_addr = bge_readmem_ind(sc, 0x0c14);
if ((mac_addr >> 16) == 0x484b) {
	sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8);
	sc->arpcom.ac_enaddr[1] = (u_char)mac_addr;
	mac_addr = bge_readmem_ind(sc, 0x0c18);
	sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24);
	sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16);
	sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8);
	sc->arpcom.ac_enaddr[5] = (u_char)mac_addr;
	gotenaddr = 1;
}
}
if (!gotenaddr) {
int mac_offset = BGE_EE_MAC_OFFSET0x7C;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c)
	mac_offset = BGE_EE_MAC_OFFSET_59060x10;

if (bge_read_nvram(sc, (caddr_t)&sc->arpcom.ac_enaddr,
    mac_offset + 2, ETHER_ADDR_LEN6) == 0)
	gotenaddr = 1;
}
if (!gotenaddr && (!(sc->bge_flags & BGE_NO_EEPROM0x00000080))) {
if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
    BGE_EE_MAC_OFFSET0x7C + 2, ETHER_ADDR_LEN6) == 0)
	gotenaddr = 1;
}

2933#ifdef __sparc64__
if (!gotenaddr) {
extern void myetheraddr(u_char *);

myetheraddr(sc->arpcom.ac_enaddr);
gotenaddr = 1;
}
2940#endif

if (!gotenaddr) {
printf(": failed to read station address\n");
goto fail_2;
}

/* Allocate the general information block and ring buffers. */
sc->bge_dmatag = pa->pa_dmat;
DPRINTFN(5, ("bus_dmamem_alloc\n"));
if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),(*(sc->bge_dmatag)->_dmamem_alloc)((sc->bge_dmatag),
 (sizeof(struct bge_ring_data)), ((1 << 12)), (0), (&
sc->bge_ring_seg), (1), (&sc->bge_ring_nseg), (0x0001
))
   PAGE_SIZE, 0, &sc->bge_ring_seg, 1, &sc->bge_ring_nseg,(*(sc->bge_dmatag)->_dmamem_alloc)((sc->bge_dmatag),
 (sizeof(struct bge_ring_data)), ((1 << 12)), (0), (&
sc->bge_ring_seg), (1), (&sc->bge_ring_nseg), (0x0001
))
   BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamem_alloc)((sc->bge_dmatag),
 (sizeof(struct bge_ring_data)), ((1 << 12)), (0), (&
sc->bge_ring_seg), (1), (&sc->bge_ring_nseg), (0x0001
))) {
printf(": can't alloc rx buffers\n");
goto fail_2;
}
DPRINTFN(5, ("bus_dmamem_map\n"));
if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg,(*(sc->bge_dmatag)->_dmamem_map)((sc->bge_dmatag), (
&sc->bge_ring_seg), (sc->bge_ring_nseg), (sizeof(struct
 bge_ring_data)), (&kva), (0x0001))
   sc->bge_ring_nseg, sizeof(struct bge_ring_data), &kva,(*(sc->bge_dmatag)->_dmamem_map)((sc->bge_dmatag), (
&sc->bge_ring_seg), (sc->bge_ring_nseg), (sizeof(struct
 bge_ring_data)), (&kva), (0x0001))
   BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamem_map)((sc->bge_dmatag), (
&sc->bge_ring_seg), (sc->bge_ring_nseg), (sizeof(struct
 bge_ring_data)), (&kva), (0x0001))) {
printf(": can't map dma buffers (%lu bytes)\n",
    sizeof(struct bge_ring_data));
goto fail_3;
}
DPRINTFN(5, ("bus_dmamem_create\n"));
if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sizeof(struct bge_ring_data)), (1), (sizeof(struct bge_ring_data
)), (0), (0x0001), (&sc->bge_ring_map))
   sizeof(struct bge_ring_data), 0,(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sizeof(struct bge_ring_data)), (1), (sizeof(struct bge_ring_data
)), (0), (0x0001), (&sc->bge_ring_map))
   BUS_DMA_NOWAIT, &sc->bge_ring_map)(*(sc->bge_dmatag)->_dmamap_create)((sc->bge_dmatag)
, (sizeof(struct bge_ring_data)), (1), (sizeof(struct bge_ring_data
)), (0), (0x0001), (&sc->bge_ring_map))) {
printf(": can't create dma map\n");
goto fail_4;
}
DPRINTFN(5, ("bus_dmamem_load\n"));
if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,(*(sc->bge_dmatag)->_dmamap_load)((sc->bge_dmatag), (
sc->bge_ring_map), (kva), (sizeof(struct bge_ring_data)), (
((void *)0)), (0x0001))
	    sizeof(struct bge_ring_data), NULL,(*(sc->bge_dmatag)->_dmamap_load)((sc->bge_dmatag), (
sc->bge_ring_map), (kva), (sizeof(struct bge_ring_data)), (
((void *)0)), (0x0001))
	    BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamap_load)((sc->bge_dmatag), (
sc->bge_ring_map), (kva), (sizeof(struct bge_ring_data)), (
((void *)0)), (0x0001))) {
goto fail_5;
}

DPRINTFN(5, ("bzero\n"));
sc->bge_rdata = (struct bge_ring_data *)kva;

bzero(sc->bge_rdata, sizeof(struct bge_ring_data))__builtin_bzero((sc->bge_rdata), (sizeof(struct bge_ring_data
)));

/* Set default tuneable values. */
sc->bge_stat_ticks = BGE_TICKS_PER_SEC1000000;
sc->bge_rx_coal_ticks = 150;
sc->bge_rx_max_coal_bds = 64;
sc->bge_tx_coal_ticks = 300;
sc->bge_tx_max_coal_bds = 400;

/* 5705 limits RX return ring to 512 entries. */
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000) || BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000))
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT1024;
else
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705512;

/* Set up ifnet structure */
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_xflags = IFXF_MPSAFE0x1;
ifp->if_ioctl = bge_ioctl;
ifp->if_qstart = bge_start;
ifp->if_watchdog = bge_watchdog;
ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1)((&ifp->if_snd)->ifq_maxlen = (512 - 1));

DPRINTFN(5, ("bcopy\n"));
bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ16);

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010;

3011#if NVLAN1 > 0
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
3013#endif

/*
* 5700 B0 chips do not support checksumming correctly due
* to hardware bugs.
*
* It seems all controllers have a bug that can generate UDP
* datagrams with a checksum value 0 when TX UDP checksum     
* offloading is enabled. Generating UDP checksum value 0 is
* a violation of RFC 768.
*/
if (sc->bge_chipid != BGE_CHIPID_BCM5700_B00x7100)
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_CSUM_IPv40x00000001 | IFCAP_CSUM_TCPv40x00000002;

if (BGE_IS_JUMBO_CAPABLE(sc)((sc)->bge_flags & 0x00000100))
ifp->if_hardmtu = BGE_JUMBO_MTU(9022 - ((6 * 2) + 2) - 4 - 4);

/*
* Do MII setup.
*/
DPRINTFN(5, ("mii setup\n"));
sc->bge_mii.mii_ifp = ifp;
sc->bge_mii.mii_readreg = bge_miibus_readreg;
sc->bge_mii.mii_writereg = bge_miibus_writereg;
sc->bge_mii.mii_statchg = bge_miibus_statchg;

/*
* Figure out what sort of media we have by checking the hardware
* config word in the first 32K of internal NIC memory, or fall back to
* examining the EEPROM if necessary.  Note: on some BCM5700 cards,
* this value seems to be unset. If that's the case, we have to rely on
* identifying the NIC by its PCI subsystem ID, as we do below for the
* SysKonnect SK-9D41.
*/
if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG0x00000B54) == BGE_MAGIC_NUMBER0x4B657654)
hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG0x00000B58);
else if (!(sc->bge_flags & BGE_NO_EEPROM0x00000080)) {
if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET0xC8,
    sizeof(hwcfg))) {
	printf(": failed to read media type\n");
	goto fail_6;
}
hwcfg = ntohl(hwcfg)(__uint32_t)(__builtin_constant_p(hwcfg) ? (__uint32_t)(((__uint32_t
)(hwcfg) & 0xff) << 24 | ((__uint32_t)(hwcfg) &
 0xff00) << 8 | ((__uint32_t)(hwcfg) & 0xff0000) >>
| ((__uint32_t)(hwcfg) & 0xff000000) >> 24) : __swap32md
(hwcfg));
}

/* The SysKonnect SK-9D41 is a 1000baseSX card. */
if (PCI_PRODUCT(subid)(((subid) >> 16) & 0xffff) == SK_SUBSYSID_9D410x4441 ||
   (hwcfg & BGE_HWCFG_MEDIA0x00000030) == BGE_MEDIA_FIBER0x00000020) {
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000))
    sc->bge_flags |= BGE_FIBER_TBI0x00000200;
else
    sc->bge_flags |= BGE_FIBER_MII0x00000400;
}

/* Take advantage of single-shot MSI. */
if (BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000) && sc->bge_flags & BGE_MSI0x00400000)
CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6000)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6000
))) & ~0x00000020)))
    ~BGE_MSIMODE_ONE_SHOT_DISABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6000)
, (((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6000
))) & ~0x00000020)));

/* Hookup IRQ last. */
DPRINTFN(5, ("pci_intr_establish\n"));
sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100,
   bge_intr, sc, sc->bge_dev.dv_xname);
if (sc->bge_intrhand == NULL((void *)0)) {
printf(": couldn't establish interrupt");
if (intrstr != NULL((void *)0))
	printf(" at %s", intrstr);
printf("\n");
goto fail_6;
}

/*
* A Broadcom chip was detected. Inform the world.
*/
printf(": %s, address %s\n", intrstr,
   ether_sprintf(sc->arpcom.ac_enaddr));

if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK0xff00000000000000ULL, bge_ifmedia_upd,
    bge_ifmedia_sts);
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER0x0000000000000100ULL|IFM_1000_SX11, 0, NULL((void *)0));
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER0x0000000000000100ULL|IFM_1000_SX11|IFM_FDX0x0000010000000000ULL,
	    0, NULL((void *)0));
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL, 0, NULL((void *)0));
ifmedia_set(&sc->bge_ifmedia, IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);
sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
} else {
int mii_flags;

/*
 * Do transceiver setup.
 */
ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
	     bge_ifmedia_sts);
mii_flags = MIIF_DOPAUSE0x0100;
if (sc->bge_flags & BGE_FIBER_MII0x00000400)
	mii_flags |= MIIF_HAVEFIBER0x0020;
mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
    sc->bge_phy_addr, MII_OFFSET_ANY-1, mii_flags);

if (LIST_FIRST(&sc->bge_mii.mii_phys)((&sc->bge_mii.mii_phys)->lh_first) == NULL((void *)0)) {
	printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
	ifmedia_add(&sc->bge_mii.mii_media,
		    IFM_ETHER0x0000000000000100ULL|IFM_MANUAL1ULL, 0, NULL((void *)0));
	ifmedia_set(&sc->bge_mii.mii_media,
		    IFM_ETHER0x0000000000000100ULL|IFM_MANUAL1ULL);
} else
	ifmedia_set(&sc->bge_mii.mii_media,
		    IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);
}

/*
* Call MI attach routine.
*/
if_attach(ifp);
ether_ifattach(ifp);

timeout_set(&sc->bge_timeout, bge_tick, sc);
timeout_set(&sc->bge_rxtimeout, bge_rxtick, sc);
timeout_set(&sc->bge_rxtimeout_jumbo, bge_rxtick_jumbo, sc);
return;

3135fail_6:
bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (sc->bge_ring_map));

3138fail_5:
bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map)(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_ring_map));

3141fail_4:
bus_dmamem_unmap(sc->bge_dmatag, (caddr_t)sc->bge_rdata,(*(sc->bge_dmatag)->_dmamem_unmap)((sc->bge_dmatag),
 ((caddr_t)sc->bge_rdata), (sizeof(struct bge_ring_data)))
   sizeof(struct bge_ring_data))(*(sc->bge_dmatag)->_dmamem_unmap)((sc->bge_dmatag),
 ((caddr_t)sc->bge_rdata), (sizeof(struct bge_ring_data)));

3145fail_3:
bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_nseg)(*(sc->bge_dmatag)->_dmamem_free)((sc->bge_dmatag), (
&sc->bge_ring_seg), (sc->bge_ring_nseg));

3148fail_2:
if ((sc->bge_flags & BGE_APE0x00080000) != 0)
bus_space_unmap(sc->bge_apetag, sc->bge_apehandle,
    sc->bge_apesize);

3153fail_1:
bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize);
3155}

3157int
3158bge_detach(struct device *self, int flags)
3159{
struct bge_softc *sc = (struct bge_softc *)self;
struct ifnet *ifp = &sc->arpcom.ac_if;

if (sc->bge_intrhand)
pci_intr_disestablish(sc->bge_pa.pa_pc, sc->bge_intrhand);

bge_stop(sc, 1);

/* Detach any PHYs we might have. */
if (LIST_FIRST(&sc->bge_mii.mii_phys)((&sc->bge_mii.mii_phys)->lh_first) != NULL((void *)0))
mii_detach(&sc->bge_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);

/* Delete any remaining media. */
ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY((uint64_t) -1));

ether_ifdetach(ifp);
if_detach(ifp);

bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (sc->bge_ring_map));
bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map)(*(sc->bge_dmatag)->_dmamap_destroy)((sc->bge_dmatag
), (sc->bge_ring_map));
bus_dmamem_unmap(sc->bge_dmatag, (caddr_t)sc->bge_rdata,(*(sc->bge_dmatag)->_dmamem_unmap)((sc->bge_dmatag),
 ((caddr_t)sc->bge_rdata), (sizeof(struct bge_ring_data)))
   sizeof(struct bge_ring_data))(*(sc->bge_dmatag)->_dmamem_unmap)((sc->bge_dmatag),
 ((caddr_t)sc->bge_rdata), (sizeof(struct bge_ring_data)));
bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_nseg)(*(sc->bge_dmatag)->_dmamem_free)((sc->bge_dmatag), (
&sc->bge_ring_seg), (sc->bge_ring_nseg));

if ((sc->bge_flags & BGE_APE0x00080000) != 0)
bus_space_unmap(sc->bge_apetag, sc->bge_apehandle,
    sc->bge_apesize);

bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize);
return (0);
3190}

3192int
3193bge_activate(struct device *self, int act)
3194{
struct bge_softc *sc = (struct bge_softc *)self;
struct ifnet *ifp = &sc->arpcom.ac_if;
int rv = 0;

switch (act) {
case DVACT_SUSPEND3:
rv = config_activate_children(self, act);
if (ifp->if_flags & IFF_RUNNING0x40)
	bge_stop(sc, 0);
break;
case DVACT_RESUME4:
if (ifp->if_flags & IFF_UP0x1)
	bge_init(sc);
break;
default:
rv = config_activate_children(self, act);
break;
}
return (rv);
3214}

3216void
3217bge_reset(struct bge_softc *sc)
3218{
struct pci_attach_args *pa = &sc->bge_pa;
pcireg_t cachesize, command, devctl;
u_int32_t reset, mac_mode, mac_mode_mask, val;
void (*write_op)(struct bge_softc *, int, int);
int i;

mac_mode_mask = BGE_MACMODE_HALF_DUPLEX0x00000002 | BGE_MACMODE_PORTMODE0x0000000C;
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) != 0)
mac_mode_mask |= BGE_MACMODE_APE_RX_EN0x08000000 | BGE_MACMODE_APE_TX_EN0x10000000;
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400))
) & mac_mode_mask;

if (BGE_IS_575X_PLUS(sc)((sc)->bge_flags & 0x00002000) && !BGE_IS_5714_FAMILY(sc)((sc)->bge_flags & 0x00008000) &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM59060x0c) {
if (sc->bge_flags & BGE_PCIE0x00000020)
	write_op = bge_writembx;
else
	write_op = bge_writemem_ind;
} else
write_op = bge_writereg_ind;

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57000x07 &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57010x00 &&
   !(sc->bge_flags & BGE_NO_EEPROM0x00000080)) {
CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7020)
, (0x00000002)));
for (i = 0; i < 8000; i++) {
	if (CSR_READ_4(sc, BGE_NVRAM_SWARB)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7020))
) &
	    BGE_NVRAMSWARB_GNT10x00000200)
		break;
	DELAY(20)(*delay_func)(20);
}
if (i == 8000)
	printf("%s: nvram lock timed out\n",
	    sc->bge_dev.dv_xname);
}
/* Take APE lock when performing reset. */
bge_ape_lock(sc, BGE_APE_LOCK_GRC1);

/* Save some important PCI state. */
cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ0x0C);
command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD0x04);

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL0x68,
   BGE_PCIMISCCTL_INDIRECT_ACCESS0x00000080 | BGE_PCIMISCCTL_MASK_PCI_INTR0x00000002 |
   BGE_PCIMISCCTL_ENDIAN_WORDSWAP0x00000008 | BGE_PCIMISCCTL_PCISTATE_RW0x00000010);

/* Disable fastboot on controllers that support it. */
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57520x06 ||
   BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000))
CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6894)
, (0)));

/*
* Write the magic number to SRAM at offset 0xB50.
* When firmware finishes its initialization it will
* write ~BGE_SRAM_FW_MB_MAGIC to the same location.
*/
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM0x00000B50, BGE_MAGIC_NUMBER0x4B657654);

reset = BGE_MISCCFG_RESET_CORE_CLOCKS0x00000001 | BGE_32BITTIME_66MHZ(0x41 << 1);

if (sc->bge_flags & BGE_PCIE0x00000020) {
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57850x5785 &&
    !BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
	if (CSR_READ_4(sc, 0x7e2c)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7e2c))
) == 0x60) {
		/* PCI Express 1.0 system */
		CSR_WRITE_4(sc, 0x7e2c, 0x20)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7e2c)
, (0x20)));
	}
}
if (sc->bge_chipid != BGE_CHIPID_BCM5750_A00x4000) {
	/*
	 * Prevent PCI Express link training
	 * during global reset.
	 */
	CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6804)
, ((1<<29))));
	reset |= (1<<29);
}
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c) {
val = CSR_READ_4(sc, BGE_VCPU_STATUS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x5100))
);
CSR_WRITE_4(sc, BGE_VCPU_STATUS,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5100)
, (val | 0x08000000)))
    val | BGE_VCPU_STATUS_DRV_RESET)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5100)
, (val | 0x08000000)));
              val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6890))
);
              CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6890)
, (val & ~0x00400000)))
                  val & ~BGE_VCPU_EXT_CTRL_HALT_CPU)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6890)
, (val & ~0x00400000)));

              sc->bge_flags |= BGE_NO_EEPROM0x00000080;
      }

/*
* Set GPHY Power Down Override to leave GPHY
* powered up in D0 uninitialized.
*/
if (BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000) &&
   (sc->bge_flags & BGE_CPMU_PRESENT0x00100000) == 0)
reset |= BGE_MISCCFG_KEEP_GPHY_POWER0x04000000;

/* Issue global reset */
write_op(sc, BGE_MISC_CFG0x6804, reset);

if (sc->bge_flags & BGE_PCIE0x00000020)
DELAY(100 * 1000)(*delay_func)(100 * 1000);
else
DELAY(1000)(*delay_func)(1000);

if (sc->bge_flags & BGE_PCIE0x00000020) {
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A00x4000) {
	pcireg_t v;

	DELAY(500000)(*delay_func)(500000); /* wait for link training to complete */
	v = pci_conf_read(pa->pa_pc, pa->pa_tag, 0xc4);
	pci_conf_write(pa->pa_pc, pa->pa_tag, 0xc4, v | (1<<15));
}

devctl = pci_conf_read(pa->pa_pc, pa->pa_tag, sc->bge_expcap +
    PCI_PCIE_DCSR0x08);
/* Clear enable no snoop and disable relaxed ordering. */
devctl &= ~(PCI_PCIE_DCSR_ERO0x00000010 | PCI_PCIE_DCSR_ENS0x00000800);
/* Set PCI Express max payload size. */
devctl = (devctl & ~PCI_PCIE_DCSR_MPS0x00007000) | sc->bge_expmrq;
/* Clear error status. */
devctl |= PCI_PCIE_DCSR_CEE0x00010000 | PCI_PCIE_DCSR_NFE0x00020000 |
    PCI_PCIE_DCSR_FEE0x00040000 | PCI_PCIE_DCSR_URE0x00080000;
pci_conf_write(pa->pa_pc, pa->pa_tag, sc->bge_expcap +
    PCI_PCIE_DCSR0x08, devctl);
}

/* Reset some of the PCI state that got zapped by reset */
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL0x68,
   BGE_PCIMISCCTL_INDIRECT_ACCESS0x00000080 | BGE_PCIMISCCTL_MASK_PCI_INTR0x00000002 |
   BGE_PCIMISCCTL_ENDIAN_WORDSWAP0x00000008 | BGE_PCIMISCCTL_PCISTATE_RW0x00000010);
val = BGE_PCISTATE_ROM_ENABLE0x00000020 | BGE_PCISTATE_ROM_RETRY_ENABLE0x00000040;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A00x2000 &&
   (sc->bge_flags & BGE_PCIX0x00000010) != 0)
val |= BGE_PCISTATE_RETRY_SAME_DMA0x00002000;
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE0x00000002) != 0)
val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR0x00010000 |
    BGE_PCISTATE_ALLOW_APE_SHMEM_WR0x00020000 |
    BGE_PCISTATE_ALLOW_APE_PSPACE_WR0x00040000;
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE0x70, val);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ0x0C, cachesize);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD0x04, command);

/* Re-enable MSI, if necessary, and enable memory arbiter. */
if (BGE_IS_5714_FAMILY(sc)((sc)->bge_flags & 0x00008000)) {
/* This chip disables MSI on reset. */
if (sc->bge_flags & BGE_MSI0x00400000) {
	val = pci_conf_read(pa->pa_pc, pa->pa_tag,
	    sc->bge_msicap + PCI_MSI_MC0x00);
	pci_conf_write(pa->pa_pc, pa->pa_tag,
	    sc->bge_msicap + PCI_MSI_MC0x00,
	    val | PCI_MSI_MC_MSIE0x00010000);
	val = CSR_READ_4(sc, BGE_MSI_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6000))
);
	CSR_WRITE_4(sc, BGE_MSI_MODE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6000)
, (val | 0x00000002)))
	    val | BGE_MSIMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6000)
, (val | 0x00000002)));
}
val = CSR_READ_4(sc, BGE_MARB_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4000))
);
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4000)
, (0x00000002 | val)));
} else
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4000)
, (0x00000002)));

/* Fix up byte swapping */
CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6800)
, (bge_dma_swap_options(sc))));

val = CSR_READ_4(sc, BGE_MAC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400))
);
val = (val & ~mac_mode_mask) | mac_mode;
CSR_WRITE_4(sc, BGE_MAC_MODE, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, (val)));
DELAY(40)(*delay_func)(40);

bge_ape_unlock(sc, BGE_APE_LOCK_GRC1);

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c) {
for (i = 0; i < BGE_TIMEOUT100000; i++) {
	val = CSR_READ_4(sc, BGE_VCPU_STATUS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x5100))
);
	if (val & BGE_VCPU_STATUS_INIT_DONE0x04000000)
		break;
	DELAY(100)(*delay_func)(100);
}

if (i >= BGE_TIMEOUT100000)
	printf("%s: reset timed out\n", sc->bge_dev.dv_xname);
} else {
/*
 * Poll until we see 1's complement of the magic number.
 * This indicates that the firmware initialization
 * is complete.  We expect this to fail if no SEEPROM
 * is fitted.
 */
for (i = 0; i < BGE_TIMEOUT100000 * 10; i++) {
	val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM0x00000B50);
	if (val == ~BGE_MAGIC_NUMBER0x4B657654)
		break;
	DELAY(10)(*delay_func)(10);
}

if ((i >= BGE_TIMEOUT100000 * 10) &&
    (!(sc->bge_flags & BGE_NO_EEPROM0x00000080)))
	printf("%s: firmware handshake timed out\n",
	   sc->bge_dev.dv_xname);
/* BCM57765 A0 needs additional time before accessing. */
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A00x57785000)
	DELAY(10 * 1000)(*delay_func)(10 * 1000);       /* XXX */
}

/*
* The 5704 in TBI mode apparently needs some special
* adjustment to ensure the SERDES drive level is set
* to 1.2V.
*/
if (sc->bge_flags & BGE_FIBER_TBI0x00000200 &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02) {
val = CSR_READ_4(sc, BGE_SERDES_CFG)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0590))
);
val = (val & ~0xFFF) | 0x880;
CSR_WRITE_4(sc, BGE_SERDES_CFG, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0590)
, (val)));
}

if (sc->bge_flags & BGE_PCIE0x00000020 &&
   !BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000) &&
   sc->bge_chipid != BGE_CHIPID_BCM5750_A00x4000 &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57850x5785) {
/* Enable Data FIFO protection. */
val = CSR_READ_4(sc, 0x7c00)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x7c00))
);
CSR_WRITE_4(sc, 0x7c00, val | (1<<25))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x7c00)
, (val | (1<<25))));
}

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720)
BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3624)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3624
))) & ~(0x80000000)))))
    CPMU_CLCK_ORIDE_MAC_ORIDE_EN)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3624)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3624
))) & ~(0x80000000)))));
3446}

3448/*
* Frame reception handling. This is called if there's a frame
* on the receive return list.
*
* Note: we have to be able to handle two possibilities here:
* 1) the frame is from the jumbo receive ring
* 2) the frame is from the standard receive ring
*/

3457void
3458bge_rxeof(struct bge_softc *sc)
3459{
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct ifnet *ifp;
uint16_t rx_prod, rx_cons;
int stdcnt = 0, jumbocnt = 0;
bus_dmamap_t dmamap;
bus_addr_t offset, toff;
bus_size_t tlen;
int tosync;
int livelocked;

rx_cons = sc->bge_rx_saved_considx;
rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx;

/* Nothing to do */
if (rx_cons == rx_prod)
return;

ifp = &sc->arpcom.ac_if;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   offsetof(struct bge_ring_data, bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   sizeof (struct bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
));

offset = offsetof(struct bge_ring_data, bge_rx_return_ring)__builtin_offsetof(struct bge_ring_data, bge_rx_return_ring);
tosync = rx_prod - rx_cons;

toff = offset + (rx_cons * sizeof (struct bge_rx_bd));

if (tosync < 0) {
tlen = (sc->bge_return_ring_cnt - rx_cons) *
    sizeof (struct bge_rx_bd);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (toff), (tlen), (0x02))
    toff, tlen, BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (toff), (tlen), (0x02));
tosync = -tosync;
}

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_rx_bd
)), (0x02))
   offset, tosync * sizeof (struct bge_rx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_rx_bd
)), (0x02))
   BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_rx_bd
)), (0x02));

while (rx_cons != rx_prod) {
struct bge_rx_bd	*cur_rx;
u_int32_t		rxidx;
struct mbuf		*m = NULL((void *)0);

cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons];

rxidx = cur_rx->bge_idx;
BGE_INC(rx_cons, sc->bge_return_ring_cnt)(rx_cons) = (rx_cons + 1) % sc->bge_return_ring_cnt;

if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING0x0020) {
	m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
	sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL((void *)0);

	jumbocnt++;

	dmamap = sc->bge_cdata.bge_rx_jumbo_map[rxidx];
	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x02))
	    dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->bge_dmatag, dmamap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmamap));

	if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR0x0400) {
		m_freem(m);
		continue;
	}
} else {
	m = sc->bge_cdata.bge_rx_std_chain[rxidx];
	sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL((void *)0);

	stdcnt++;

	dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x02))
	    dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->bge_dmatag, dmamap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmamap));

	if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR0x0400) {
		m_freem(m);
		continue;
	}
}

3543#ifdef __STRICT_ALIGNMENT
/*
 * The i386 allows unaligned accesses, but for other
 * platforms we must make sure the payload is aligned.
 */
if (sc->bge_flags & BGE_RX_ALIGNBUG0x00000008) {
	bcopy(m->m_datam_hdr.mh_data, m->m_datam_hdr.mh_data + ETHER_ALIGN2,
	    cur_rx->bge_len);
	m->m_datam_hdr.mh_data += ETHER_ALIGN2;
}
3553#endif
m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = cur_rx->bge_len - ETHER_CRC_LEN4;

bge_rxcsum(sc, cur_rx, m);

3558#if NVLAN1 > 0
if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020 &&
    cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG0x0040) {
	m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = cur_rx->bge_vlan_tag;
	m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
}
3564#endif

ml_enqueue(&ml, m);
}

sc->bge_rx_saved_considx = rx_cons;
bge_writembx(sc, BGE_MBX_RX_CONS0_LO0x0284, sc->bge_rx_saved_considx);

livelocked = ifiq_input(&ifp->if_rcv, &ml);
if (stdcnt) {
if_rxr_put(&sc->bge_std_ring, stdcnt)do { (&sc->bge_std_ring)->rxr_alive -= (stdcnt); } while
 (0);
if (livelocked)
	if_rxr_livelocked(&sc->bge_std_ring);
bge_fill_rx_ring_std(sc);
}
if (jumbocnt) {
if_rxr_put(&sc->bge_jumbo_ring, jumbocnt)do { (&sc->bge_jumbo_ring)->rxr_alive -= (jumbocnt)
; } while (0);
if (livelocked)
	if_rxr_livelocked(&sc->bge_jumbo_ring);
bge_fill_rx_ring_jumbo(sc);
}
3585}

3587void
3588bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3589{
if (sc->bge_chipid == BGE_CHIPID_BCM5700_B00x7100) {
/*
 * 5700 B0 chips do not support checksumming correctly due
 * to hardware bugs.
 */
return;
} else if (BGE_IS_5717_PLUS(sc)((sc)->bge_flags & 0x00020000)) {
if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV60x8000) == 0) {
	if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM0x1000 &&
	    (cur_rx->bge_error_flag &
	    BGE_RXERRFLAG_IP_CSUM_NOK0x1000) == 0)
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;

	if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM0x2000) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |=
		    M_TCP_CSUM_IN_OK0x0020|M_UDP_CSUM_IN_OK0x0080;
                      }
              }
      } else {
if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM0x1000 &&
    cur_rx->bge_ip_csum == 0xFFFF)
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;

if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM0x2000 &&
    m->m_pkthdrM_dat.MH.MH_pkthdr.len >= ETHER_MIN_NOPAD(64 - 4) &&
    cur_rx->bge_tcp_udp_csum == 0xFFFF) {
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |=
	    M_TCP_CSUM_IN_OK0x0020|M_UDP_CSUM_IN_OK0x0080;
}
}
3620}

3622void
3623bge_txeof(struct bge_softc *sc)
3624{
struct bge_tx_bd *cur_tx = NULL((void *)0);
struct ifnet *ifp;
bus_dmamap_t dmamap;
bus_addr_t offset, toff;
bus_size_t tlen;
int tosync, freed, txcnt;
u_int32_t cons, newcons;
struct mbuf *m;

/* Nothing to do */
cons = sc->bge_tx_saved_considx; 
newcons = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx;
if (cons == newcons)
return;

ifp = &sc->arpcom.ac_if;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   offsetof(struct bge_ring_data, bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   sizeof (struct bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
))
   BUS_DMASYNC_POSTREAD)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
));

offset = offsetof(struct bge_ring_data, bge_tx_ring)__builtin_offsetof(struct bge_ring_data, bge_tx_ring);
tosync = newcons - cons;

toff = offset + (cons * sizeof (struct bge_tx_bd));

if (tosync < 0) {
tlen = (BGE_TX_RING_CNT512 - cons) * sizeof (struct bge_tx_bd);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (toff), (tlen), (0x02|0x08))
    toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (toff), (tlen), (0x02|0x08));
tosync = -tosync;
}

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_tx_bd
)), (0x02|0x08))
   offset, tosync * sizeof (struct bge_tx_bd),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_tx_bd
)), (0x02|0x08))
   BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (offset), (tosync * sizeof (struct bge_tx_bd
)), (0x02|0x08));

/*
* Go through our tx ring and free mbufs for those
* frames that have been sent.
*/
freed = 0;
while (cons != newcons) {
cur_tx = &sc->bge_rdata->bge_tx_ring[cons];
m = sc->bge_cdata.bge_tx_chain[cons];
if (m != NULL((void *)0)) {
	dmamap = sc->bge_cdata.bge_tx_map[cons];

	sc->bge_cdata.bge_tx_chain[cons] = NULL((void *)0);
	sc->bge_cdata.bge_tx_map[cons] = NULL((void *)0);
	bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x08))
	    dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x08));
	bus_dmamap_unload(sc->bge_dmatag, dmamap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmamap));

	m_freem(m);
}
freed++;
BGE_INC(cons, BGE_TX_RING_CNT)(cons) = (cons + 1) % 512;
}

txcnt = atomic_sub_int_nv(&sc->bge_txcnt, freed)_atomic_sub_int_nv(&sc->bge_txcnt, freed);

sc->bge_tx_saved_considx = cons;

if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
else if (txcnt == 0)
ifp->if_timer = 0;
3694}

3696int
3697bge_intr(void *xsc)
3698{
struct bge_softc *sc;
struct ifnet *ifp;
u_int32_t statusword, statustag;

sc = xsc;
ifp = &sc->arpcom.ac_if;

/* read status word from status block */
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
 | 0x08))
   offsetof(struct bge_ring_data, bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
 | 0x08))
   sizeof (struct bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
 | 0x08))
   BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x02
 | 0x08));

statusword = sc->bge_rdata->bge_status_block.bge_status;
statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24;

if (sc->bge_flags & BGE_TAGGED_STATUS0x00200000) {
if (sc->bge_lasttag == statustag &&
    (CSR_READ_4(sc, BGE_PCI_PCISTATE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x70))) &
     BGE_PCISTATE_INTR_NOT_ACTIVE0x00000002))
	return (0);
sc->bge_lasttag = statustag;
} else {
if (!(statusword & BGE_STATFLAG_UPDATED0x00000001) &&
    (CSR_READ_4(sc, BGE_PCI_PCISTATE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x70))) &
     BGE_PCISTATE_INTR_NOT_ACTIVE0x00000002))
	return (0);
/* Ack interrupt and stop others from occurring. */
bge_writembx(sc, BGE_MBX_IRQ0_LO0x0204, 1);
statustag = 0;
}

/* clear status word */
sc->bge_rdata->bge_status_block.bge_status = 0;

bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x01
 | 0x04))
   offsetof(struct bge_ring_data, bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x01
 | 0x04))
   sizeof (struct bge_status_block),(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x01
 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
sc->bge_ring_map), (__builtin_offsetof(struct bge_ring_data
, bge_status_block)), (sizeof (struct bge_status_block)), (0x01
 | 0x04));

if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 ||
   statusword & BGE_STATFLAG_LINKSTATE_CHANGED0x00000002 ||
   BGE_STS_BIT(sc, BGE_STS_LINK_EVT)((sc)->bge_sts & (0x00000002))) {
KERNEL_LOCK()_kernel_lock();
bge_link_upd(sc);
KERNEL_UNLOCK()_kernel_unlock();
}

/* Re-enable interrupts. */
bge_writembx(sc, BGE_MBX_IRQ0_LO0x0204, statustag);

if (ifp->if_flags & IFF_RUNNING0x40) {
/* Check RX return ring producer/consumer */
bge_rxeof(sc);

/* Check TX ring producer/consumer */
bge_txeof(sc);
}

return (1);
3759}

3761void
3762bge_tick(void *xsc)
3763{
struct bge_softc *sc = xsc;
struct mii_data *mii = &sc->bge_mii;
int s;

s = splnet()splraise(0x7);

if (BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000))
bge_stats_update_regs(sc);
else
bge_stats_update(sc);

if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
/*
 * Since in TBI mode auto-polling can't be used we should poll
 * link status manually. Here we register pending link event
 * and trigger interrupt.
 */
BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT)((sc)->bge_sts |= (0x00000002));
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00000004)))));
} else {
/*
 * Do not touch PHY if we have link up. This could break
 * IPMI/ASF mode or produce extra input errors.
 * (extra input errors was reported for bcm5701 & bcm5704).
 */
if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)))
	mii_tick(mii);
}

timeout_add_sec(&sc->bge_timeout, 1);

splx(s)spllower(s);
3796}

3798void
3799bge_stats_update_regs(struct bge_softc *sc)
3800{
struct ifnet *ifp = &sc->arpcom.ac_if;

sc->bge_tx_collisions += CSR_READ_4(sc, BGE_MAC_STATS +((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, etherStatsCollisions
))))
   offsetof(struct bge_mac_stats_regs, etherStatsCollisions))((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, etherStatsCollisions
))));

sc->bge_rx_overruns += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x224C))
);

/*
* XXX
* Unlike other controllers, the BGE_RXLP_LOCSTAT_IFIN_DROPS counter
* of the BCM5717, BCM5718, BCM5762, BCM5719 A0 and BCM5720 A0
* controllers includes the number of unwanted multicast frames.
* This comes from a silicon bug and known workaround to get rough
* (not exact) counter is to enable interrupt on MBUF low watermark
* attention. This can be accomplished by setting BGE_HCCMODE_ATTN
* bit of BGE_HDD_MODE, BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE
* and BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. However
* that change would generate more interrupts and there are still
* possibilities of losing multiple frames during 
* BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. Given that
* the workaround still would not get correct counter I don't think
* it's worth to implement it. So ignore reading the counter on
* controllers that have the silicon bug.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57170x5717 &&
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) != BGE_ASICREV_BCM57620x5762 &&
   sc->bge_chipid != BGE_CHIPID_BCM5719_A00x05719000 &&
   sc->bge_chipid != BGE_CHIPID_BCM5720_A00x05720000)
sc->bge_rx_discards += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x2250))
);

sc->bge_rx_inerrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x2254))
);

ifp->if_collisionsif_data.ifi_collisions = sc->bge_tx_collisions;
ifp->if_ierrorsif_data.ifi_ierrors = sc->bge_rx_discards + sc->bge_rx_inerrors;

if (sc->bge_flags & BGE_RDMA_BUG0x00800000) {
u_int32_t val, ucast, mcast, bcast;

ucast = CSR_READ_4(sc, BGE_MAC_STATS +((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts
))))
    offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts))((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts
))));
mcast = CSR_READ_4(sc, BGE_MAC_STATS +((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts
))))
    offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts))((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts
))));
bcast = CSR_READ_4(sc, BGE_MAC_STATS +((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts
))))
    offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts))((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0800 +
 __builtin_offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts
))));

/*
 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
 * frames, it's safe to disable workaround for DMA engine's
 * miscalculation of TXMBUF space.
 */
if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS4) {
	val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x4910))
);
	if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57190x5719)
		val &= ~BGE_RDMA_TX_LENGTH_WA_57190x02000000;
	else
		val &= ~BGE_RDMA_TX_LENGTH_WA_57200x00200000;
	CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x4910)
, (val)));
	sc->bge_flags &= ~BGE_RDMA_BUG0x00800000;
}
}
3861}

3863void
3864bge_stats_update(struct bge_softc *sc)
3865{
struct ifnet *ifp = &sc->arpcom.ac_if;
bus_size_t stats = BGE_MEMWIN_START0x00008000 + BGE_STATS_BLOCK0x00000300;
u_int32_t cnt;

3870#define READ_STAT(sc, stats, stat) \
 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))((sc->bge_btag)->read_4((sc->bge_bhandle), (stats + __builtin_offsetof
(struct bge_stats, stat))))

cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
ifp->if_collisionsif_data.ifi_collisions += (u_int32_t)(cnt - sc->bge_tx_collisions);
sc->bge_tx_collisions = cnt;

cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
sc->bge_rx_overruns = cnt;
cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
ifp->if_ierrorsif_data.ifi_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrors);
sc->bge_rx_inerrors = cnt;
cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
ifp->if_ierrorsif_data.ifi_ierrors += (u_int32_t)(cnt - sc->bge_rx_discards);
sc->bge_rx_discards = cnt;

cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
ifp->if_oerrorsif_data.ifi_oerrors += (u_int32_t)(cnt - sc->bge_tx_discards);
sc->bge_tx_discards = cnt;

3890#undef READ_STAT
3891}

3893/*
* Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
*/
3896int
3897bge_compact_dma_runt(struct mbuf *pkt)
3898{
struct mbuf	*m, *prev, *n = NULL((void *)0);
int 		totlen, newprevlen;

prev = NULL((void *)0);
15
←
Null pointer value stored to 'prev'→
totlen = 0;

for (m = pkt; m15.1
'm' is not equal to NULL
 != NULL((void *)0); prev = m,m = m->m_nextm_hdr.mh_next) {
16
←
Loop condition is true.  Entering loop body→
int mlen = m->m_lenm_hdr.mh_len;
int shortfall = 8 - mlen ;

totlen += mlen;
if (mlen == 0)
17
←
Assuming 'mlen' is not equal to 0→
18
←
Taking false branch→
	continue;
if (mlen >= 8)
19
←
Assuming 'mlen' is < 8→
20
←
Taking false branch→
	continue;

/* If we get here, mbuf data is too small for DMA engine.
 * Try to fix by shuffling data to prev or next in chain.
 * If that fails, do a compacting deep-copy of the whole chain.
 */

/* Internal frag. If fits in prev, copy it there. */
if (prev20.1
'prev' is null
 && m_trailingspace(prev) >= m->m_lenm_hdr.mh_len) {
	bcopy(m->m_datam_hdr.mh_data, prev->m_datam_hdr.mh_data+prev->m_lenm_hdr.mh_len, mlen);
	prev->m_lenm_hdr.mh_len += mlen;
	m->m_lenm_hdr.mh_len = 0;
	/* XXX stitch chain */
	prev->m_nextm_hdr.mh_next = m_free(m);
	m = prev;
	continue;
} else if (m->m_nextm_hdr.mh_next != NULL((void *)0) &&
21
←
Assuming field 'mh_next' is equal to NULL→
	   m_trailingspace(m) >= shortfall &&
	   m->m_nextm_hdr.mh_next->m_lenm_hdr.mh_len >= (8 + shortfall)) {
	/* m is writable and have enough data in next, pull up. */

	bcopy(m->m_nextm_hdr.mh_next->m_datam_hdr.mh_data, m->m_datam_hdr.mh_data+m->m_lenm_hdr.mh_len, shortfall);
	m->m_lenm_hdr.mh_len += shortfall;
	m->m_nextm_hdr.mh_next->m_lenm_hdr.mh_len -= shortfall;
	m->m_nextm_hdr.mh_next->m_datam_hdr.mh_data += shortfall;
} else if (m->m_nextm_hdr.mh_next == NULL((void *)0) || 1) {
	/* Got a runt at the very end of the packet.
	 * borrow data from the tail of the preceding mbuf and
	 * update its length in-place. (The original data is still
	 * valid, so we can do this even if prev is not writable.)
	 */

	/* if we'd make prev a runt, just move all of its data. */
3946#ifdef DEBUG
	KASSERT(prev != NULL /*, ("runt but null PREV")*/)((prev != ((void *)0)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_bge.c"
, 3947, "prev != NULL"));
	KASSERT(prev->m_len >= 8 /*, ("runt prev")*/)((prev->m_hdr.mh_len >= 8) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_bge.c", 3948, "prev->m_len >= 8"
));
3949#endif
	if ((prev->m_lenm_hdr.mh_len - shortfall) < 8)
22
←
Dereference of null pointer
		shortfall = prev->m_lenm_hdr.mh_len;

	newprevlen = prev->m_lenm_hdr.mh_len - shortfall;

	MGET(n, M_NOWAIT, MT_DATA)n = m_get((0x0002), (1));
	if (n == NULL((void *)0))
		return (ENOBUFS55);
	KASSERT(m->m_len + shortfall < MLEN((m->m_hdr.mh_len + shortfall < (256 - sizeof(struct m_hdr
))) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_bge.c"
, 3960, "m->m_len + shortfall < MLEN"))
		/*,((m->m_hdr.mh_len + shortfall < (256 - sizeof(struct m_hdr
))) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_bge.c"
, 3960, "m->m_len + shortfall < MLEN"))
		  ("runt %d +prev %d too big\n", m->m_len, shortfall)*/)((m->m_hdr.mh_len + shortfall < (256 - sizeof(struct m_hdr
))) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_bge.c"
, 3960, "m->m_len + shortfall < MLEN"));

	/* first copy the data we're stealing from prev */
	bcopy(prev->m_datam_hdr.mh_data + newprevlen, n->m_datam_hdr.mh_data, shortfall);

	/* update prev->m_len accordingly */
	prev->m_lenm_hdr.mh_len -= shortfall;

	/* copy data from runt m */
	bcopy(m->m_datam_hdr.mh_data, n->m_datam_hdr.mh_data + shortfall, m->m_lenm_hdr.mh_len);

	/* n holds what we stole from prev, plus m */
	n->m_lenm_hdr.mh_len = shortfall + m->m_lenm_hdr.mh_len;

	/* stitch n into chain and free m */
	n->m_nextm_hdr.mh_next = m->m_nextm_hdr.mh_next;
	prev->m_nextm_hdr.mh_next = n;
	/* KASSERT(m->m_next == NULL); */
	m->m_nextm_hdr.mh_next = NULL((void *)0);
	m_free(m);
	m = n;	/* for continuing loop */
}
}
return (0);
3984}

3986/*
* Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
* The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
* but when such padded frames employ the bge IP/TCP checksum offload,
* the hardware checksum assist gives incorrect results (possibly
* from incorporating its own padding into the UDP/TCP checksum; who knows).
* If we pad such runts with zeros, the onboard checksum comes out correct.
*/
3994int
3995bge_cksum_pad(struct mbuf *m)
3996{
int padlen = ETHER_MIN_NOPAD(64 - 4) - m->m_pkthdrM_dat.MH.MH_pkthdr.len;
struct mbuf *last;

/* If there's only the packet-header and we can pad there, use it. */
if (m->m_pkthdrM_dat.MH.MH_pkthdr.len == m->m_lenm_hdr.mh_len && m_trailingspace(m) >= padlen) {
last = m;
} else {
/*
 * Walk packet chain to find last mbuf. We will either
 * pad there, or append a new mbuf and pad it.
 */
for (last = m; last->m_nextm_hdr.mh_next != NULL((void *)0); last = last->m_nextm_hdr.mh_next);
if (m_trailingspace(last) < padlen) {
	/* Allocate new empty mbuf, pad it. Compact later. */
	struct mbuf *n;

	MGET(n, M_DONTWAIT, MT_DATA)n = m_get((0x0002), (1));
	if (n == NULL((void *)0))
		return (ENOBUFS55);
	n->m_lenm_hdr.mh_len = 0;
	last->m_nextm_hdr.mh_next = n;
	last = n;
}
}

/* Now zero the pad area, to avoid the bge cksum-assist bug. */
memset(mtod(last, caddr_t) + last->m_len, 0, padlen)__builtin_memset((((caddr_t)((last)->m_hdr.mh_data)) + last
->m_hdr.mh_len), (0), (padlen));
last->m_lenm_hdr.mh_len += padlen;
m->m_pkthdrM_dat.MH.MH_pkthdr.len += padlen;

return (0);
4028}

4030/*
* Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
* pointers to descriptors.
*/
4034int
4035bge_encap(struct bge_softc *sc, struct mbuf *m, int *txinc)
4036{
struct bge_tx_bd	*f = NULL((void *)0);
u_int32_t		frag, cur;
u_int16_t		csum_flags = 0;
bus_dmamap_t		dmamap;
int			i = 0;

cur = frag = (sc->bge_tx_prodidx + *txinc) % BGE_TX_RING_CNT512;

if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags) {
9
←
Assuming field 'csum_flags' is 0→
10
←
Taking false branch→
if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_IPV4_CSUM_OUT0x0001)
	csum_flags |= BGE_TXBDFLAG_IP_CSUM0x0002;
if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &
    (M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004)) {
	csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM0x0001;
	if (m->m_pkthdrM_dat.MH.MH_pkthdr.len < ETHER_MIN_NOPAD(64 - 4) &&
	    bge_cksum_pad(m) != 0)
		return (ENOBUFS55);
}
}

if (sc->bge_flags & BGE_JUMBO_FRAME0x04000000 && 
11
←
Assuming the condition is false→
   m->m_pkthdrM_dat.MH.MH_pkthdr.len > ETHER_MAX_LEN1518)
csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME0x0008;

if (!(BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5700_BX0x71))
12
←
Assuming the condition is true→
13
←
Taking false branch→
goto doit;

/*
* bcm5700 Revision B silicon cannot handle DMA descriptors with
* less than eight bytes.  If we encounter a teeny mbuf
* at the end of a chain, we can pad.  Otherwise, copy.
*/
if (bge_compact_dma_runt(m) != 0)
14
←
Calling 'bge_compact_dma_runt'→
return (ENOBUFS55);

4072doit:
dmamap = sc->bge_txdma[cur];

/*
* Start packing the mbufs in this chain into
* the fragment pointers. Stop when we run out
* of fragments or hit the end of the mbuf chain.
*/
switch (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m,(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmamap), (m), (0x0001))
   BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmamap), (m), (0x0001))) {
case 0:
break;
case EFBIG27:
if (m_defrag(m, M_DONTWAIT0x0002) == 0 &&
    bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m,(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmamap), (m), (0x0001))
     BUS_DMA_NOWAIT)(*(sc->bge_dmatag)->_dmamap_load_mbuf)((sc->bge_dmatag
), (dmamap), (m), (0x0001)) == 0)
	break;

/* FALLTHROUGH */
default:
return (ENOBUFS55);
}

for (i = 0; i < dmamap->dm_nsegs; i++) {
f = &sc->bge_rdata->bge_tx_ring[frag];
if (sc->bge_cdata.bge_tx_chain[frag] != NULL((void *)0))
	break;
BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr)do { (f->bge_addr).bge_addr_lo = ((u_int64_t) (dmamap->
dm_segs[i].ds_addr) & 0xffffffff); if (sizeof(bus_addr_t)
 == 8) (f->bge_addr).bge_addr_hi = ((u_int64_t) (dmamap->
dm_segs[i].ds_addr) >> 32); else (f->bge_addr).bge_addr_hi
 = 0; } while(0);
f->bge_len = dmamap->dm_segs[i].ds_len;
f->bge_flags = csum_flags;
f->bge_vlan_tag = 0;
4103#if NVLAN1 > 0
if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020) {
	f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG0x0040;
	f->bge_vlan_tag = m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag;
}
4108#endif
cur = frag;
BGE_INC(frag, BGE_TX_RING_CNT)(frag) = (frag + 1) % 512;
}

if (i < dmamap->dm_nsegs)
goto fail_unload;

if (frag == sc->bge_tx_saved_considx)
goto fail_unload;

bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->bge_dmatag)->_dmamap_sync)((sc->bge_dmatag), (
dmamap), (0), (dmamap->dm_mapsize), (0x04));

sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END0x0004;
sc->bge_cdata.bge_tx_chain[cur] = m;
sc->bge_cdata.bge_tx_map[cur] = dmamap;

*txinc += dmamap->dm_nsegs;

return (0);

4130fail_unload:
bus_dmamap_unload(sc->bge_dmatag, dmamap)(*(sc->bge_dmatag)->_dmamap_unload)((sc->bge_dmatag)
, (dmamap));

return (ENOBUFS55);
4134}

4136/*
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
* to the mbuf data regions directly in the transmit descriptors.
*/
4140void
4141bge_start(struct ifqueue *ifq)
4142{
struct ifnet *ifp = ifq->ifq_if;
struct bge_softc *sc = ifp->if_softc;
struct mbuf *m;
int txinc;

if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001))) {
1
Assuming the condition is false→
2
←
Taking false branch→
ifq_purge(ifq);
return;
}

txinc = 0;
while (1) {
3
←
Loop condition is true.  Entering loop body→
/* Check if we have enough free send BDs. */
if (sc->bge_txcnt + txinc + BGE_NTXSEG30 + 16 >=
4
←
Assuming the condition is false→
5
←
Taking false branch→
    BGE_TX_RING_CNT512) {
	ifq_set_oactive(ifq);
	break;
}

m = ifq_dequeue(ifq);
if (m == NULL((void *)0))
6
←
Assuming 'm' is not equal to NULL→
7
←
Taking false branch→
	break;

if (bge_encap(sc, m, &txinc) != 0) {
8
←
Calling 'bge_encap'→
	m_freem(m);
	continue;
}

4171#if NBPFILTER1 > 0
if (ifp->if_bpf)
	bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
4174#endif
}

if (txinc != 0) {
/* Transmit */
sc->bge_tx_prodidx = (sc->bge_tx_prodidx + txinc) %
    BGE_TX_RING_CNT512;
bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO0x0304, sc->bge_tx_prodidx);
if (BGE_CHIPREV(sc->bge_chipid)((sc->bge_chipid) >> 8) == BGE_CHIPREV_5700_BX0x71)
	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO0x0304,
	    sc->bge_tx_prodidx);

atomic_add_int(&sc->bge_txcnt, txinc)_atomic_add_int(&sc->bge_txcnt, txinc);

/*
 * Set a timeout in case the chip goes out to lunch.
 */
ifp->if_timer = 5;
}
4193}

4195void
4196bge_init(void *xsc)
4197{
struct bge_softc *sc = xsc;
struct ifnet *ifp;
u_int16_t *m;
u_int32_t mode;
int s;

s = splnet()splraise(0x7);

ifp = &sc->arpcom.ac_if;

/* Cancel pending I/O and flush buffers. */
bge_stop(sc, 0);
bge_sig_pre_reset(sc, BGE_RESET_START1);
bge_reset(sc);
bge_sig_legacy(sc, BGE_RESET_START1);
bge_sig_post_reset(sc, BGE_RESET_START1);

bge_chipinit(sc);

/*
* Init the various state machines, ring
* control blocks and firmware.
*/
if (bge_blockinit(sc)) {
printf("%s: initialization failure\n", sc->bge_dev.dv_xname);
splx(s)spllower(s);
return;
}

/* Specify MRU. */
if (BGE_IS_JUMBO_CAPABLE(sc)((sc)->bge_flags & 0x00000100))
CSR_WRITE_4(sc, BGE_RX_MTU,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x043C)
, (9022 + 4)))
	BGE_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x043C)
, (9022 + 4)));
else
CSR_WRITE_4(sc, BGE_RX_MTU,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x043C)
, (1518 + 4)))
	ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x043C)
, (1518 + 4)));

/* Load our MAC address. */
m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0410)
, ((__uint16_t)(__builtin_constant_p(m[0]) ? (__uint16_t)(((__uint16_t
)(m[0]) & 0xffU) << 8 | ((__uint16_t)(m[0]) & 0xff00U
) >> 8) : __swap16md(m[0])))));
CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]))((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0414)
, (((__uint16_t)(__builtin_constant_p(m[1]) ? (__uint16_t)(((
__uint16_t)(m[1]) & 0xffU) << 8 | ((__uint16_t)(m[1
]) & 0xff00U) >> 8) : __swap16md(m[1])) << 16
) | (__uint16_t)(__builtin_constant_p(m[2]) ? (__uint16_t)(((
__uint16_t)(m[2]) & 0xffU) << 8 | ((__uint16_t)(m[2
]) & 0xff00U) >> 8) : __swap16md(m[2])))));

if (!(ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)) {
/* Disable hardware decapsulation of VLAN frames. */
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0468)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0468
))) | (0x00000400)))));
}

/* Program promiscuous mode and multicast filters. */
bge_iff(sc);

/* Init RX ring. */
bge_init_rx_ring_std(sc);

/*
* Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
* memory to ensure that the chip has in fact read the first
* entry of the ring.
*/
if (sc->bge_chipid == BGE_CHIPID_BCM5705_A00x3000) {
u_int32_t		v, i;
for (i = 0; i < 10; i++) {
	DELAY(20)(*delay_func)(20);
	v = bge_readmem_ind(sc, BGE_STD_RX_RINGS0x00006000 + 8);
	if (v == (MCLBYTES(1 << 11) - ETHER_ALIGN2))
		break;
}
if (i == 10)
	printf("%s: 5705 A0 chip failed to load RX ring\n",
	    sc->bge_dev.dv_xname);
}

/* Init Jumbo RX ring. */
if (sc->bge_flags & BGE_JUMBO_RING0x01000000)
bge_init_rx_ring_jumbo(sc);

/* Init our RX return ring index */
sc->bge_rx_saved_considx = 0;

/* Init our RX/TX stat counters. */
sc->bge_tx_collisions = 0;
sc->bge_rx_discards = 0;
sc->bge_rx_inerrors = 0;
sc->bge_rx_overruns = 0;
sc->bge_tx_discards = 0;

/* Init TX ring. */
bge_init_tx_ring(sc);

/* Enable TX MAC state machine lockup fix. */
mode = CSR_READ_4(sc, BGE_TX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x045C))
);
if (BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000) ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM59060x0c)
mode |= BGE_TXMODE_MBUF_LOCKUP_FIX0x00000100;
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57200x5720 ||
   BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762) {
mode &= ~(BGE_TXMODE_JMB_FRM_LEN0x00400000 | BGE_TXMODE_CNT_DN_MODE0x00800000);
mode |= CSR_READ_4(sc, BGE_TX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x045C))
) &
    (BGE_TXMODE_JMB_FRM_LEN0x00400000 | BGE_TXMODE_CNT_DN_MODE0x00800000);
}

/* Turn on transmitter */
CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x045C)
, (mode | 0x00000002)));
DELAY(100)(*delay_func)(100);

mode = CSR_READ_4(sc, BGE_RX_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0468))
);
if (BGE_IS_5755_PLUS(sc)((sc)->bge_flags & 0x00004000))
mode |= BGE_RXMODE_IPV6_ENABLE0x01000000;
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57620x5762)
mode |= BGE_RXMODE_IPV4_FRAG_FIX0x02000000;

/* Turn on receiver */
CSR_WRITE_4(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0468)
, (mode | 0x00000002)));
DELAY(10)(*delay_func)(10);

/*
* Set the number of good frames to receive after RX MBUF
* Low Watermark has been reached. After the RX MAC receives
* this number of frames, it will drop subsequent incoming
* frames until the MBUF High Watermark is reached.
*/
if (BGE_IS_57765_PLUS(sc)((sc)->bge_flags & 0x00040000))
CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0504)
, (1)));
else
CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0504)
, (2)));

/* Tell firmware we're alive. */
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6800)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6800
))) | (0x00010000)))));

/* Enable host interrupts. */
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x68), (
(((sc->bge_btag)->read_4((sc->bge_bhandle), (0x68)))
 | (0x00000001)))));
BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x68), (
(((sc->bge_btag)->read_4((sc->bge_bhandle), (0x68)))
 & ~(0x00000002)))));
bge_writembx(sc, BGE_MBX_IRQ0_LO0x0204, 0);

bge_ifmedia_upd(ifp);

ifp->if_flags |= IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

splx(s)spllower(s);

timeout_add_sec(&sc->bge_timeout, 1);
4339}

4341/*
* Set media options.
*/
4344int
4345bge_ifmedia_upd(struct ifnet *ifp)
4346{
struct bge_softc *sc = ifp->if_softc;
struct mii_data *mii = &sc->bge_mii;
struct ifmedia *ifm = &sc->bge_ifmedia;

/* If this is a 1000baseX NIC, enable the TBI port. */
if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
	return (EINVAL22);
switch(IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
case IFM_AUTO0ULL:
	/*
	 * The BCM5704 ASIC appears to have a special
	 * mechanism for programming the autoneg
	 * advertisement registers in TBI mode.
	 */
	if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02) {
		u_int32_t sgdig;
		sgdig = CSR_READ_4(sc, BGE_SGDIG_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x05B4))
);
		if (sgdig & BGE_SGDIGSTS_DONE0x00000002) {
			CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0444)
, (0)));
			sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x05B0))
);
			sgdig |= BGE_SGDIGCFG_AUTO0x80000000 |
			    BGE_SGDIGCFG_PAUSE_CAP0x00000800 |
			    BGE_SGDIGCFG_ASYM_PAUSE0x00001000;
			CSR_WRITE_4(sc, BGE_SGDIG_CFG,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x05B0)
, (sgdig | 0x40000000)))
			    sgdig | BGE_SGDIGCFG_SEND)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x05B0)
, (sgdig | 0x40000000)));
			DELAY(5)(*delay_func)(5);
			CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x05B0)
, (sgdig)));
		}
	}
	break;
case IFM_1000_SX11:
	if ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL) {
		BGE_CLRBIT(sc, BGE_MAC_MODE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) & ~(0x00000002)))))
		    BGE_MACMODE_HALF_DUPLEX)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) & ~(0x00000002)))));
	} else {
		BGE_SETBIT(sc, BGE_MAC_MODE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) | (0x00000002)))))
		    BGE_MACMODE_HALF_DUPLEX)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) | (0x00000002)))));
	}
	DELAY(40)(*delay_func)(40);
	break;
default:
	return (EINVAL22);
}
/* XXX 802.3x flow control for 1000BASE-SX */
return (0);
}

BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT)((sc)->bge_sts |= (0x00000002));
if (mii->mii_instance) {
struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)for((miisc) = ((&mii->mii_phys)->lh_first); (miisc)
!= ((void *)0); (miisc) = ((miisc)->mii_list.le_next))
	mii_phy_reset(miisc);
}
mii_mediachg(mii);

/*
* Force an interrupt so that we will call bge_link_upd
* if needed and clear any pending link state attention.
* Without this we are not getting any further interrupts
* for link state changes and thus will not UP the link and
* not be able to send in bge_start. The only way to get
* things working was to receive a packet and get a RX intr.
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07 ||
   sc->bge_flags & BGE_IS_57880x00000800)
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6808)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6808
))) | (0x00000004)))));
else
BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x3C00)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x3C00
))) | (0x00000008)))));

return (0);
4418}

4420/*
* Report current media status.
*/
4423void
4424bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4425{
struct bge_softc *sc = ifp->if_softc;
struct mii_data *mii = &sc->bge_mii;

if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL;
if (CSR_READ_4(sc, BGE_MAC_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0404))
) &
    BGE_MACSTAT_TBI_PCS_SYNCHED0x00000001) {
	ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;
} else {
	ifmr->ifm_active |= IFM_NONE2ULL;
	return;
}
ifmr->ifm_active |= IFM_1000_SX11;
if (CSR_READ_4(sc, BGE_MAC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400))
) & BGE_MACMODE_HALF_DUPLEX0x00000002)
	ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL;
else
	ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL;
return;
}

mii_pollstat(mii);
ifmr->ifm_status = mii->mii_media_status;
ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
)) |
   sc->bge_flowflags;
4451}

4453int
4454bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4455{
struct bge_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
int s, error = 0;
struct mii_data *mii;

s = splnet()splraise(0x7);

switch(command) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	bge_init(sc);
break;

case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		bge_init(sc);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		bge_stop(sc, 0);
}
break;

case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
/* XXX Flow control is not supported for 1000BASE-SX */
if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
	ifr->ifr_mediaifr_ifru.ifru_media &= ~IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
);
	sc->bge_flowflags = 0;
}

/* Flow control requires full-duplex mode. */
if (IFM_SUBTYPE(ifr->ifr_media)((ifr->ifr_ifru.ifru_media) & 0x00000000000000ffULL) == IFM_AUTO0ULL ||
    (ifr->ifr_mediaifr_ifru.ifru_media & IFM_FDX0x0000010000000000ULL) == 0) {
    	ifr->ifr_mediaifr_ifru.ifru_media &= ~IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
);
}
if (IFM_SUBTYPE(ifr->ifr_media)((ifr->ifr_ifru.ifru_media) & 0x00000000000000ffULL) != IFM_AUTO0ULL) {
	if ((ifr->ifr_mediaifr_ifru.ifru_media & IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
)) == IFM_FLOW0x0000040000000000ULL) {
		/* We can do both TXPAUSE and RXPAUSE. */
		ifr->ifr_mediaifr_ifru.ifru_media |=
		    IFM_ETH_TXPAUSE0x0000000000040000ULL | IFM_ETH_RXPAUSE0x0000000000020000ULL;
	}
	sc->bge_flowflags = ifr->ifr_mediaifr_ifru.ifru_media & IFM_ETH_FMASK(0x0000040000000000ULL|0x0000000000020000ULL|0x0000000000040000ULL
);
}
/* FALLTHROUGH */
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
	error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
	    command);
} else {
	mii = &sc->bge_mii;
	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
	    command);
}
break;

case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
error = bge_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data);
break;

default:
error = ether_ioctl(ifp, &sc->arpcom, command, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40)
	bge_iff(sc);
error = 0;
}

splx(s)spllower(s);
return (error);
4530}

4532int
4533bge_rxrinfo(struct bge_softc *sc, struct if_rxrinfo *ifri)
4534{
struct if_rxring_info ifr[2];
u_int n = 0;

memset(ifr, 0, sizeof(ifr))__builtin_memset((ifr), (0), (sizeof(ifr)));

if (ISSET(sc->bge_flags, BGE_RXRING_VALID)((sc->bge_flags) & (0x00000002))) {
ifr[n].ifr_size = sc->bge_rx_std_len;
strlcpy(ifr[n].ifr_name, "std", sizeof(ifr[n].ifr_name));
ifr[n].ifr_info = sc->bge_std_ring;

n++;
}

if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)((sc->bge_flags) & (0x00000004))) {
ifr[n].ifr_size = BGE_JLEN((9022 + 2) + (sizeof(u_int64_t) - ((9022 + 2) % sizeof(u_int64_t
))));
strlcpy(ifr[n].ifr_name, "jumbo", sizeof(ifr[n].ifr_name));
ifr[n].ifr_info = sc->bge_jumbo_ring;

n++;
}

return (if_rxr_info_ioctl(ifri, n, ifr));
4557}

4559void
4560bge_watchdog(struct ifnet *ifp)
4561{
struct bge_softc *sc;

sc = ifp->if_softc;

printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);

bge_init(sc);

ifp->if_oerrorsif_data.ifi_oerrors++;
4571}

4573void
4574bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit)
4575{
int i;

BGE_CLRBIT(sc, reg, bit)((sc->bge_btag)->write_4((sc->bge_bhandle), (reg), (
(((sc->bge_btag)->read_4((sc->bge_bhandle), (reg))) &
 ~(bit)))));

for (i = 0; i < BGE_TIMEOUT100000; i++) {
if ((CSR_READ_4(sc, reg)((sc->bge_btag)->read_4((sc->bge_bhandle), (reg))) & bit) == 0)
	return;
delay(100)(*delay_func)(100);
}

DPRINTFN(5, ("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
   sc->bge_dev.dv_xname, (u_long) reg, bit));
4588}

4590/*
* Stop the adapter and free any mbufs allocated to the
* RX and TX lists.
*/
4594void
4595bge_stop(struct bge_softc *sc, int softonly)
4596{
struct ifnet *ifp = &sc->arpcom.ac_if;
struct ifmedia_entry *ifm;
struct mii_data *mii;
int mtmp, itmp;

timeout_del(&sc->bge_timeout);
timeout_del(&sc->bge_rxtimeout);
timeout_del(&sc->bge_rxtimeout_jumbo);

ifp->if_flags &= ~IFF_RUNNING0x40;
ifp->if_timer = 0;

if (!softonly) {
/*
 * Tell firmware we're shutting down.
 */
/* bge_stop_fw(sc); */
bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN0);

/*
 * Disable all of the receiver blocks
 */
bge_stop_block(sc, BGE_RX_MODE0x0468, BGE_RXMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RBDI_MODE0x2C00, BGE_RBDIMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RXLP_MODE0x2000, BGE_RXLPMODE_ENABLE0x00000002);
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000))
	bge_stop_block(sc, BGE_RXLS_MODE0x3400, BGE_RXLSMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RDBDI_MODE0x2400, BGE_RBDIMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RDC_MODE0x2800, BGE_RDCMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RBDC_MODE0x3000, BGE_RBDCMODE_ENABLE0x00000002);

/*
 * Disable all of the transmit blocks
 */
bge_stop_block(sc, BGE_SRS_MODE0x1400, BGE_SRSMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_SBDI_MODE0x1800, BGE_SBDIMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_SDI_MODE0x0C00, BGE_SDIMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_RDMA_MODE0x4800, BGE_RDMAMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_SDC_MODE0x1000, BGE_SDCMODE_ENABLE0x00000002);
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000))
	bge_stop_block(sc, BGE_DMAC_MODE0x6400, BGE_DMACMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_SBDC_MODE0x1C00, BGE_SBDCMODE_ENABLE0x00000002);

/*
 * Shut down all of the memory managers and related
 * state machines.
 */
bge_stop_block(sc, BGE_HCC_MODE0x3C00, BGE_HCCMODE_ENABLE0x00000002);
bge_stop_block(sc, BGE_WDMA_MODE0x4C00, BGE_WDMAMODE_ENABLE0x00000002);
if (BGE_IS_5700_FAMILY(sc)((sc)->bge_flags & 0x00010000))
	bge_stop_block(sc, BGE_MBCF_MODE0x3800, BGE_MBCFMODE_ENABLE0x00000002);

CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5C00)
, (0xFFFFFFFF)));
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x5C00)
, (0)));

if (!BGE_IS_5705_PLUS(sc)((sc)->bge_flags & 0x00001000)) {
	bge_stop_block(sc, BGE_BMAN_MODE0x4400, BGE_BMANMODE_ENABLE0x00000002);
	bge_stop_block(sc, BGE_MARB_MODE0x4000, BGE_MARBMODE_ENABLE0x00000002);
}

bge_reset(sc);
bge_sig_legacy(sc, BGE_RESET_SHUTDOWN0);
bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN0);

/*
 * Tell firmware we're shutting down.
 */
BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x6800)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x6800
))) & ~(0x00010000)))));
}

intr_barrier(sc->bge_intrhand);
ifq_barrier(&ifp->if_snd);

ifq_clr_oactive(&ifp->if_snd);

/* Free the RX lists. */
bge_free_rx_ring_std(sc);

/* Free jumbo RX list. */
if (sc->bge_flags & BGE_JUMBO_RING0x01000000)
bge_free_rx_ring_jumbo(sc);

/* Free TX buffers. */
bge_free_tx_ring(sc);

/*
* Isolate/power down the PHY, but leave the media selection
* unchanged so that things will be put back to normal when
* we bring the interface back up.
*/
if (!(sc->bge_flags & BGE_FIBER_TBI0x00000200)) {
mii = &sc->bge_mii;
itmp = ifp->if_flags;
ifp->if_flags |= IFF_UP0x1;
ifm = mii->mii_media.ifm_cur;
mtmp = ifm->ifm_media;
ifm->ifm_media = IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL;
mii_mediachg(mii);
ifm->ifm_media = mtmp;
ifp->if_flags = itmp;
}

sc->bge_tx_saved_considx = BGE_TXCONS_UNSET0xFFFF;

if (!softonly) {
/* Clear MAC's link state (PHY may still have link UP). */
BGE_STS_CLRBIT(sc, BGE_STS_LINK)((sc)->bge_sts &= ~(0x00000001));
}
4705}

4707void
4708bge_link_upd(struct bge_softc *sc)
4709{
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mii_data *mii = &sc->bge_mii;
u_int32_t status;
int link;

/* Clear 'pending link event' flag */
BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT)((sc)->bge_sts &= ~(0x00000002));

/*
* Process link state changes.
* Grrr. The link status word in the status block does
* not work correctly on the BCM5700 rev AX and BX chips,
* according to all available information. Hence, we have
* to enable MII interrupts in order to properly obtain
* async link changes. Unfortunately, this also means that
* we have to read the MAC status register to detect link
* changes, thereby adding an additional register access to
* the interrupt handler.
*
*/
if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57000x07) {
status = CSR_READ_4(sc, BGE_MAC_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0404))
);
if (status & BGE_MACSTAT_MI_INTERRUPT0x00800000) {
	mii_pollstat(mii);

	if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
	    mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL &&
	    IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) != IFM_NONE2ULL)
		BGE_STS_SETBIT(sc, BGE_STS_LINK)((sc)->bge_sts |= (0x00000001));
	else if (BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
	    (!(mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL) ||
	    IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_NONE2ULL))
		BGE_STS_CLRBIT(sc, BGE_STS_LINK)((sc)->bge_sts &= ~(0x00000001));

	/* Clear the interrupt */
	CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0408)
, (0x00800000)))
	    BGE_EVTENB_MI_INTERRUPT)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0408)
, (0x00800000)));
	bge_miibus_readreg(&sc->bge_dev, sc->bge_phy_addr,
	    BRGPHY_MII_ISR0x1A);
	bge_miibus_writereg(&sc->bge_dev, sc->bge_phy_addr,
	    BRGPHY_MII_IMR0x1B, BRGPHY_INTRS~(0x0002|0x0004|0x0008));
}
return;
}

if (sc->bge_flags & BGE_FIBER_TBI0x00000200) {
status = CSR_READ_4(sc, BGE_MAC_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0404))
);
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED0x00000001) {
	if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001))) {
		BGE_STS_SETBIT(sc, BGE_STS_LINK)((sc)->bge_sts |= (0x00000001));
		if (BGE_ASICREV(sc->bge_chipid)((sc->bge_chipid) >> 12) == BGE_ASICREV_BCM57040x02)
			BGE_CLRBIT(sc, BGE_MAC_MODE,((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) & ~(0x00020000)))))
			    BGE_MACMODE_TBI_SEND_CFGS)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0400)
, ((((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400
))) & ~(0x00020000)))));
		CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0xFFFFFFFF)));
		status = CSR_READ_4(sc, BGE_MAC_MODE)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0400))
);
		link = (status & BGE_MACMODE_HALF_DUPLEX0x00000002) ?
		    LINK_STATE_HALF_DUPLEX5 :
		    LINK_STATE_FULL_DUPLEX6;
		ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL)));
		if (ifp->if_link_stateif_data.ifi_link_state != link) {
			ifp->if_link_stateif_data.ifi_link_state = link;
			if_link_state_change(ifp);
		}
	}
} else if (BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001))) {
	BGE_STS_CLRBIT(sc, BGE_STS_LINK)((sc)->bge_sts &= ~(0x00000001));
	link = LINK_STATE_DOWN2;
	ifp->if_baudrateif_data.ifi_baudrate = 0;
	if (ifp->if_link_stateif_data.ifi_link_state != link) {
		ifp->if_link_stateif_data.ifi_link_state = link;
		if_link_state_change(ifp);
	}
}
} else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)((sc)->bge_sts & (0x00000004))) {
/*
 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
 * in status word always set. Workaround this bug by reading
 * PHY link status directly.
 */
link = (CSR_READ_4(sc, BGE_MI_STS)((sc->bge_btag)->read_4((sc->bge_bhandle), (0x0450))
) & BGE_MISTS_LINK0x00000001)?
    BGE_STS_LINK0x00000001 : 0;

if (BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) != link) {
	mii_pollstat(mii);

	if (!BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
	    mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL &&
	    IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) != IFM_NONE2ULL)
		BGE_STS_SETBIT(sc, BGE_STS_LINK)((sc)->bge_sts |= (0x00000001));
	else if (BGE_STS_BIT(sc, BGE_STS_LINK)((sc)->bge_sts & (0x00000001)) &&
	    (!(mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL) ||
	    IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_NONE2ULL))
		BGE_STS_CLRBIT(sc, BGE_STS_LINK)((sc)->bge_sts &= ~(0x00000001));
}
} else {
/*
 * For controllers that call mii_tick, we have to poll
 * link status.
 */
mii_pollstat(mii);
}

/* Clear the attention */
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)))
   BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)))
   BGE_MACSTAT_LINK_CHANGED)((sc->bge_btag)->write_4((sc->bge_bhandle), (0x0404)
, (0x00000010| 0x00000008|0x00400000| 0x00001000)));
4816}