Bug Summary

File:dev/ic/rt2860.c
Warning:line 3209, column 2
Value stored to 'val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name rt2860.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/ic/rt2860.c
1/* $OpenBSD: rt2860.c,v 1.101 2020/12/12 11:48:52 jan Exp $ */
2
3/*-
4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*-
20 * Ralink Technology RT2860/RT3090/RT3290/RT3390/RT3562/RT5390/
21 * RT5392 chipset driver
22 * http://www.ralinktech.com/
23 */
24
25#include "bpfilter.h"
26
27#include <sys/param.h>
28#include <sys/sockio.h>
29#include <sys/mbuf.h>
30#include <sys/kernel.h>
31#include <sys/socket.h>
32#include <sys/systm.h>
33#include <sys/malloc.h>
34#include <sys/queue.h>
35#include <sys/timeout.h>
36#include <sys/conf.h>
37#include <sys/device.h>
38#include <sys/endian.h>
39
40#include <machine/bus.h>
41#include <machine/intr.h>
42
43#if NBPFILTER1 > 0
44#include <net/bpf.h>
45#endif
46#include <net/if.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
49
50#include <netinet/in.h>
51#include <netinet/if_ether.h>
52
53#include <net80211/ieee80211_var.h>
54#include <net80211/ieee80211_amrr.h>
55#include <net80211/ieee80211_radiotap.h>
56
57#include <dev/ic/rt2860var.h>
58#include <dev/ic/rt2860reg.h>
59
60#include <dev/pci/pcidevs.h>
61
62#ifdef RAL_DEBUG
63#define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0)
64#define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0)
65int rt2860_debug = 0;
66#else
67#define DPRINTF(x)
68#define DPRINTFN(n, x)
69#endif
70
71void rt2860_attachhook(struct device *);
72int rt2860_alloc_tx_ring(struct rt2860_softc *,
73 struct rt2860_tx_ring *);
74void rt2860_reset_tx_ring(struct rt2860_softc *,
75 struct rt2860_tx_ring *);
76void rt2860_free_tx_ring(struct rt2860_softc *,
77 struct rt2860_tx_ring *);
78int rt2860_alloc_tx_pool(struct rt2860_softc *);
79void rt2860_free_tx_pool(struct rt2860_softc *);
80int rt2860_alloc_rx_ring(struct rt2860_softc *,
81 struct rt2860_rx_ring *);
82void rt2860_reset_rx_ring(struct rt2860_softc *,
83 struct rt2860_rx_ring *);
84void rt2860_free_rx_ring(struct rt2860_softc *,
85 struct rt2860_rx_ring *);
86struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *);
87int rt2860_media_change(struct ifnet *);
88void rt2860_iter_func(void *, struct ieee80211_node *);
89void rt2860_updatestats(struct rt2860_softc *);
90void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
91 int);
92void rt2860_node_leave(struct ieee80211com *,
93 struct ieee80211_node *);
94int rt2860_ampdu_rx_start(struct ieee80211com *,
95 struct ieee80211_node *, uint8_t);
96void rt2860_ampdu_rx_stop(struct ieee80211com *,
97 struct ieee80211_node *, uint8_t);
98int rt2860_newstate(struct ieee80211com *, enum ieee80211_state,
99 int);
100uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
101uint16_t rt3290_efuse_read_2(struct rt2860_softc *, uint16_t);
102uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
103void rt2860_intr_coherent(struct rt2860_softc *);
104void rt2860_drain_stats_fifo(struct rt2860_softc *);
105void rt2860_tx_intr(struct rt2860_softc *, int);
106void rt2860_rx_intr(struct rt2860_softc *);
107void rt2860_tbtt_intr(struct rt2860_softc *);
108void rt2860_gp_intr(struct rt2860_softc *);
109int rt2860_tx(struct rt2860_softc *, struct mbuf *,
110 struct ieee80211_node *);
111void rt2860_start(struct ifnet *);
112void rt2860_watchdog(struct ifnet *);
113int rt2860_ioctl(struct ifnet *, u_long, caddr_t);
114void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
115uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
116void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
117uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
118void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
119int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
120void rt2860_enable_mrr(struct rt2860_softc *);
121void rt2860_set_txpreamble(struct rt2860_softc *);
122void rt2860_set_basicrates(struct rt2860_softc *);
123void rt2860_select_chan_group(struct rt2860_softc *, int);
124void rt2860_set_chan(struct rt2860_softc *, u_int);
125void rt3090_set_chan(struct rt2860_softc *, u_int);
126void rt5390_set_chan(struct rt2860_softc *, u_int);
127int rt3090_rf_init(struct rt2860_softc *);
128void rt5390_rf_init(struct rt2860_softc *);
129void rt3090_rf_wakeup(struct rt2860_softc *);
130void rt5390_rf_wakeup(struct rt2860_softc *);
131int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
132 uint8_t *);
133void rt3090_rf_setup(struct rt2860_softc *);
134void rt2860_set_leds(struct rt2860_softc *, uint16_t);
135void rt2860_set_gp_timer(struct rt2860_softc *, int);
136void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
137void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
138void rt2860_updateslot(struct ieee80211com *);
139void rt2860_updateprot(struct ieee80211com *);
140void rt2860_updateedca(struct ieee80211com *);
141int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
142 struct ieee80211_key *);
143void rt2860_delete_key(struct ieee80211com *,
144 struct ieee80211_node *, struct ieee80211_key *);
145#if NBPFILTER1 > 0
146int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
147#endif
148const char * rt2860_get_rf(uint16_t);
149int rt2860_read_eeprom(struct rt2860_softc *);
150int rt2860_bbp_init(struct rt2860_softc *);
151void rt5390_bbp_init(struct rt2860_softc *);
152int rt3290_wlan_enable(struct rt2860_softc *);
153int rt2860_txrx_enable(struct rt2860_softc *);
154int rt2860_init(struct ifnet *);
155void rt2860_stop(struct ifnet *, int);
156int rt2860_load_microcode(struct rt2860_softc *);
157void rt2860_calib(struct rt2860_softc *);
158void rt3090_set_rx_antenna(struct rt2860_softc *, int);
159void rt2860_switch_chan(struct rt2860_softc *,
160 struct ieee80211_channel *);
161#ifndef IEEE80211_STA_ONLY
162int rt2860_setup_beacon(struct rt2860_softc *);
163#endif
164void rt2860_enable_tsf_sync(struct rt2860_softc *);
165
166static const struct {
167 uint32_t reg;
168 uint32_t val;
169} rt2860_def_mac[] = {
170 RT2860_DEF_MAC{ 0x042c, 0xf8f0e8e0 }, { 0x0430, 0x6f77d0c8 }, { 0x1408, 0x0000013f
}, { 0x140c, 0x00008003 }, { 0x1004, 0x00000000 }, { 0x1400,
0x00017f97 }, { 0x1104, 0x00000209 }, { 0x1330, 0x00000000 }
, { 0x1334, 0x00080606 }, { 0x1350, 0x00001020 }, { 0x1348, 0x000a2090
}, { 0x1018, 0x00001f00 }, { 0x102c, 0x7f031e46 }, { 0x0214,
0x00002273 }, { 0x0218, 0x00002344 }, { 0x021c, 0x000034aa }
, { 0x040c, 0x1f3fbf9f }, { 0x134c, 0x47d01f0f }, { 0x1404, 0x00000013
}, { 0x1364, 0x05740003 }, { 0x1368, 0x05740003 }, { 0x1374,
0x01744004 }, { 0x1378, 0x03f44084 }, { 0x136c, 0x01744004 }
, { 0x1370, 0x03f54084 }, { 0x1340, 0x0000583f }, { 0x1608, 0x00000002
}, { 0x1344, 0x00092b20 }, { 0x1380, 0x002400ca }, { 0x1100,
0x33a41010 }, { 0x1204, 0x00000003 }
171};
172
173static const struct {
174 uint8_t reg;
175 uint8_t val;
176} rt2860_def_bbp[] = {
177 RT2860_DEF_BBP{ 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69, 0x12 }, { 70,
0x0a }, { 73, 0x10 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x6a
}, { 84, 0x99 }, { 86, 0x00 }, { 91, 0x04 }, { 92, 0x00 }, {
103, 0x00 }, { 105, 0x05 }, { 106, 0x35 }
178},rt3290_def_bbp[] = {
179 RT3290_DEF_BBP{ 31, 0x08 }, { 68, 0x0b }, { 73, 0x13 }, { 75, 0x46 }, { 76,
0x28 }, { 77, 0x59 }, { 82, 0x62 }, { 83, 0x7a }, { 84, 0x9a
}, { 86, 0x38 }, { 91, 0x04 }, { 103, 0xc0 }, { 104, 0x92 },
{ 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 }
180},rt5390_def_bbp[] = {
181 RT5390_DEF_BBP{ 31, 0x08 }, { 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69,
0x0d }, { 70, 0x06 }, { 73, 0x13 }, { 75, 0x46 }, { 76, 0x28
}, { 77, 0x59 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x7a }, {
84, 0x9a }, { 86, 0x38 }, { 91, 0x04 }, { 92, 0x02 }, { 103,
0xc0 }, { 104, 0x92 }, { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12
}
182};
183
184static const struct rfprog {
185 uint8_t chan;
186 uint32_t r1, r2, r3, r4;
187} rt2860_rf2850[] = {
188 RT2860_RF2850{ 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, { 2, 0x100bb3,
0x1301e1, 0x05a014, 0x001407 }, { 3, 0x100bb3, 0x1301e2, 0x05a014
, 0x001402 }, { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, {
5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, { 6, 0x100bb3, 0x1301e3
, 0x05a014, 0x001407 }, { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402
}, { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, { 9, 0x100bb3
, 0x1301e5, 0x05a014, 0x001402 }, { 10, 0x100bb3, 0x1301e5, 0x05a014
, 0x001407 }, { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },
{ 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, { 13, 0x100bb3
, 0x1301e7, 0x05a014, 0x001402 }, { 14, 0x100bb3, 0x1301e8, 0x05a014
, 0x001404 }, { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 },
{ 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, { 40, 0x100bb2
, 0x1301a0, 0x056014, 0x001400 }, { 44, 0x100bb2, 0x1301a0, 0x056014
, 0x001408 }, { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },
{ 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, { 52, 0x100bb2
, 0x1301a2, 0x056014, 0x001404 }, { 54, 0x100bb2, 0x1301a2, 0x056014
, 0x001408 }, { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },
{ 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, { 62, 0x100bb2
, 0x1301a4, 0x056014, 0x001404 }, { 64, 0x100bb2, 0x1301a4, 0x056014
, 0x001408 }, { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }
, { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, { 104, 0x100bb2
, 0x1701ac, 0x15e014, 0x001408 }, { 108, 0x100bb3, 0x17028c, 0x15e014
, 0x001404 }, { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }
, { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, { 116, 0x100bb3
, 0x13028e, 0x05e014, 0x001408 }, { 118, 0x100bb3, 0x13028f, 0x05e014
, 0x001404 }, { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }
, { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, { 126, 0x100bb1
, 0x1300e0, 0x05e014, 0x001406 }, { 128, 0x100bb1, 0x1300e0, 0x05e014
, 0x001408 }, { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }
, { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, { 136, 0x100bb1
, 0x1300e1, 0x05e014, 0x001406 }, { 140, 0x100bb1, 0x1300e2, 0x05e014
, 0x001400 }, { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }
, { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, { 153, 0x100bb1
, 0x1300e3, 0x05e014, 0x001403 }, { 157, 0x100bb1, 0x1300e3, 0x05e014
, 0x001407 }, { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }
, { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, { 165, 0x100bb1
, 0x1300e4, 0x05e014, 0x001405 }, { 167, 0x100bb1, 0x1300f4, 0x05e014
, 0x001407 }, { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }
, { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, { 173, 0x100bb1
, 0x1300f5, 0x05e014, 0x001403 }
189};
190
191struct {
192 uint8_t n, r, k;
193} rt3090_freqs[] = {
194 RT3070_RF3052{ 0xf1, 2, 2 }, { 0xf1, 2, 7 }, { 0xf2, 2, 2 }, { 0xf2, 2, 7 }
, { 0xf3, 2, 2 }, { 0xf3, 2, 7 }, { 0xf4, 2, 2 }, { 0xf4, 2, 7
}, { 0xf5, 2, 2 }, { 0xf5, 2, 7 }, { 0xf6, 2, 2 }, { 0xf6, 2
, 7 }, { 0xf7, 2, 2 }, { 0xf8, 2, 4 }, { 0x56, 0, 4 }, { 0x56
, 0, 6 }, { 0x56, 0, 8 }, { 0x57, 0, 0 }, { 0x57, 0, 2 }, { 0x57
, 0, 4 }, { 0x57, 0, 8 }, { 0x57, 0, 10 }, { 0x58, 0, 0 }, { 0x58
, 0, 4 }, { 0x58, 0, 6 }, { 0x58, 0, 8 }, { 0x5b, 0, 8 }, { 0x5b
, 0, 10 }, { 0x5c, 0, 0 }, { 0x5c, 0, 4 }, { 0x5c, 0, 6 }, { 0x5c
, 0, 8 }, { 0x5d, 0, 0 }, { 0x5d, 0, 2 }, { 0x5d, 0, 4 }, { 0x5d
, 0, 8 }, { 0x5d, 0, 10 }, { 0x5e, 0, 0 }, { 0x5e, 0, 4 }, { 0x5e
, 0, 6 }, { 0x5e, 0, 8 }, { 0x5f, 0, 0 }, { 0x5f, 0, 9 }, { 0x5f
, 0, 11 }, { 0x60, 0, 1 }, { 0x60, 0, 5 }, { 0x60, 0, 7 }, { 0x60
, 0, 9 }, { 0x61, 0, 1 }, { 0x61, 0, 3 }, { 0x61, 0, 5 }, { 0x61
, 0, 7 }, { 0x61, 0, 9 }
195};
196
197static const struct {
198 uint8_t reg;
199 uint8_t val;
200} rt3090_def_rf[] = {
201 RT3070_DEF_RF{ 4, 0x40 }, { 5, 0x03 }, { 6, 0x02 }, { 7, 0x60 }, { 9, 0x0f
}, { 10, 0x41 }, { 11, 0x21 }, { 12, 0x7b }, { 14, 0x90 }, {
15, 0x58 }, { 16, 0xb3 }, { 17, 0x92 }, { 18, 0x2c }, { 19, 0x02
}, { 20, 0xba }, { 21, 0xdb }, { 24, 0x16 }, { 25, 0x01 }, {
29, 0x1f }
202}, rt3290_def_rf[] = {
203 RT3290_DEF_RF{ 1, 0x0f }, { 2, 0x80 }, { 3, 0x08 }, { 4, 0x00 }, { 6, 0xa0
}, { 8, 0xf3 }, { 9, 0x02 }, { 10, 0x53 }, { 11, 0x4a }, { 12
, 0x46 }, { 13, 0x9f }, { 18, 0x03 }, { 22, 0x20 }, { 25, 0x80
}, { 27, 0x09 }, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, {
32, 0x80 }, { 33, 0x00 }, { 34, 0x05 }, { 35, 0x12 }, { 36, 0x00
}, { 38, 0x85 }, { 39, 0x1b }, { 40, 0x0b }, { 41, 0xbb }, {
42, 0xd5 }, { 43, 0x7b }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x73
}, { 47, 0x00 }, { 48, 0x10 }, { 49, 0x98 }, { 52, 0x38 }, {
53, 0x00 }, { 54, 0x78 }, { 55, 0x43 }, { 56, 0x02 }, { 57, 0x80
}, { 58, 0x7f }, { 59, 0x09 }, { 60, 0x45 }, { 61, 0xc1 }
204}, rt3572_def_rf[] = {
205 RT3572_DEF_RF{ 0, 0x70 }, { 1, 0x81 }, { 2, 0xf1 }, { 3, 0x02 }, { 4, 0x4c
}, { 5, 0x05 }, { 6, 0x4a }, { 7, 0xd8 }, { 9, 0xc3 }, { 10,
0xf1 }, { 11, 0xb9 }, { 12, 0x70 }, { 13, 0x65 }, { 14, 0xa0
}, { 15, 0x53 }, { 16, 0x4c }, { 17, 0x23 }, { 18, 0xac }, {
19, 0x93 }, { 20, 0xb3 }, { 21, 0xd0 }, { 22, 0x00 }, { 23, 0x3c
}, { 24, 0x16 }, { 25, 0x15 }, { 26, 0x85 }, { 27, 0x00 }, {
28, 0x00 }, { 29, 0x9b }, { 30, 0x09 }, { 31, 0x10 }
206}, rt5390_def_rf[] = {
207 RT5390_DEF_RF{ 1, 0x0f }, { 2, 0x80 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xa0
}, { 7, 0x00 }, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13
, 0x9f }, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03
}, { 19, 0x00 }, { 20, 0x00 }, { 21, 0x00 }, { 22, 0x20 }, {
23, 0x00 }, { 24, 0x00 }, { 25, 0xc0 }, { 26, 0x00 }, { 27, 0x09
}, { 28, 0x00 }, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, {
32, 0x80 }, { 33, 0x00 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00
}, { 37, 0x08 }, { 38, 0x85 }, { 39, 0x1b }, { 40, 0x0b }, {
41, 0xbb }, { 42, 0xd2 }, { 43, 0x9a }, { 44, 0x0e }, { 45, 0xa2
}, { 46, 0x7b }, { 47, 0x00 }, { 48, 0x10 }, { 49, 0x94 }, {
52, 0x38 }, { 53, 0x84 }, { 54, 0x78 }, { 55, 0x44 }, { 56, 0x22
}, { 57, 0x80 }, { 58, 0x7f }, { 59, 0x8f }, { 60, 0x45 }, {
61, 0xdd }, { 62, 0x00 }, { 63, 0x00 }
208}, rt5392_def_rf[] = {
209 RT5392_DEF_RF{ 1, 0x17 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xe0 }, { 7, 0x00
}, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13, 0x9f }, {
14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, { 19, 0x4d
}, { 20, 0x00 }, { 21, 0x8d }, { 22, 0x20 }, { 23, 0x0b }, {
24, 0x44 }, { 25, 0x80 }, { 26, 0x82 }, { 27, 0x09 }, { 28, 0x00
}, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, { 32, 0x20 }, {
33, 0xc0 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00 }, { 37, 0x08
}, { 38, 0x89 }, { 39, 0x1b }, { 40, 0x0f }, { 41, 0xbb }, {
42, 0xd5 }, { 43, 0x9b }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x73
}, { 47, 0x0c }, { 48, 0x10 }, { 49, 0x94 }, { 50, 0x94 }, {
51, 0x3a }, { 52, 0x48 }, { 53, 0x44 }, { 54, 0x38 }, { 55, 0x43
}, { 56, 0xa1 }, { 57, 0x00 }, { 58, 0x39 }, { 59, 0x07 }, {
60, 0x45 }, { 61, 0x91 }, { 62, 0x39 }, { 63, 0x07 }
210};
211
212int
213rt2860_attach(void *xsc, int id)
214{
215 struct rt2860_softc *sc = xsc;
216 struct ieee80211com *ic = &sc->sc_ic;
217 int qid, ntries, error;
218 uint32_t tmp, reg;
219
220 sc->amrr.amrr_min_success_threshold = 1;
221 sc->amrr.amrr_max_success_threshold = 15;
222
223 if (id == PCI_PRODUCT_RALINK_RT32900x3290)
224 reg = RT2860_PCI_CFG0x0000;
225 else
226 reg = RT2860_ASIC_VER_ID0x1000;
227
228 /* wait for NIC to initialize */
229 for (ntries = 0; ntries < 100; ntries++) {
230 tmp = RAL_READ(sc, reg)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((reg))));
231 if (tmp != 0 && tmp != 0xffffffff)
232 break;
233 DELAY(10)(*delay_func)(10);
234 }
235 if (ntries == 100) {
236 printf("%s: timeout waiting for NIC to initialize\n",
237 sc->sc_dev.dv_xname);
238 return ETIMEDOUT60;
239 }
240 sc->mac_ver = tmp >> 16;
241 sc->mac_rev = tmp & 0xffff;
242
243 if (sc->mac_ver != 0x2860 &&
244 (id == PCI_PRODUCT_RALINK_RT28900x0681 ||
245 id == PCI_PRODUCT_RALINK_RT27900x0781 ||
246 id == PCI_PRODUCT_AWT_RT28900x1059))
247 sc->sc_flags |= RT2860_ADVANCED_PS(1 << 1);
248
249 /* retrieve RF rev. no and various other things from EEPROM */
250 rt2860_read_eeprom(sc);
251 printf(", address %s\n", ether_sprintf(ic->ic_myaddr));
252 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n",
253 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev,
254 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
255
256 /*
257 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
258 */
259 for (qid = 0; qid < 6; qid++) {
260 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
261 printf("%s: could not allocate Tx ring %d\n",
262 sc->sc_dev.dv_xname, qid);
263 goto fail1;
264 }
265 }
266
267 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
268 printf("%s: could not allocate Rx ring\n",
269 sc->sc_dev.dv_xname);
270 goto fail1;
271 }
272
273 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
274 printf("%s: could not allocate Tx pool\n",
275 sc->sc_dev.dv_xname);
276 goto fail2;
277 }
278
279 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
280 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
281 EDCA_AC_VO : 5;
282
283 config_mountroot(xsc, rt2860_attachhook);
284
285 return 0;
286
287fail2: rt2860_free_rx_ring(sc, &sc->rxq);
288fail1: while (--qid >= 0)
289 rt2860_free_tx_ring(sc, &sc->txq[qid]);
290 return error;
291}
292
293void
294rt2860_attachhook(struct device *self)
295{
296 struct rt2860_softc *sc = (struct rt2860_softc *)self;
297 struct ieee80211com *ic = &sc->sc_ic;
298 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
299 int i, error;
300
301 if (sc->mac_ver == 0x3290) {
302 error = loadfirmware("ral-rt3290", &sc->ucode, &sc->ucsize);
303 } else {
304 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize);
305 }
306 if (error != 0) {
307 printf("%s: error %d, could not read firmware file %s\n",
308 sc->sc_dev.dv_xname, error, "ral-rt2860");
309 return;
310 }
311
312 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
313 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
314 ic->ic_state = IEEE80211_S_INIT;
315
316 /* set device capabilities */
317 ic->ic_caps =
318 IEEE80211_C_MONITOR0x00000200 | /* monitor mode supported */
319#ifndef IEEE80211_STA_ONLY
320 IEEE80211_C_IBSS0x00000002 | /* IBSS mode supported */
321 IEEE80211_C_HOSTAP0x00000008 | /* HostAP mode supported */
322 IEEE80211_C_APPMGT0x00000020 | /* HostAP power management */
323#endif
324 IEEE80211_C_SHPREAMBLE0x00000100 | /* short preamble supported */
325 IEEE80211_C_SHSLOT0x00000080 | /* short slot time supported */
326 IEEE80211_C_WEP0x00000001 | /* s/w WEP */
327 IEEE80211_C_RSN0x00001000; /* WPA/RSN */
328
329 if (sc->rf_rev == RT2860_RF_27500x0004 || sc->rf_rev == RT2860_RF_28500x0002) {
330 /* set supported .11a rates */
331 ic->ic_sup_rates[IEEE80211_MODE_11A] =
332 ieee80211_std_rateset_11a;
333
334 /* set supported .11a channels */
335 for (i = 14; i < nitems(rt2860_rf2850)(sizeof((rt2860_rf2850)) / sizeof((rt2860_rf2850)[0])); i++) {
336 uint8_t chan = rt2860_rf2850[i].chan;
337 ic->ic_channels[chan].ic_freq =
338 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ0x0100);
339 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A(0x0100 | 0x0040);
340 }
341 }
342
343 /* set supported .11b and .11g rates */
344 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
345 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
346
347 /* set supported .11b and .11g channels (1 through 14) */
348 for (i = 1; i <= 14; i++) {
349 ic->ic_channels[i].ic_freq =
350 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ0x0080);
351 ic->ic_channels[i].ic_flags =
352 IEEE80211_CHAN_CCK0x0020 | IEEE80211_CHAN_OFDM0x0040 |
353 IEEE80211_CHAN_DYN0x0400 | IEEE80211_CHAN_2GHZ0x0080;
354 }
355
356 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
357 ic->ic_max_aid = min(IEEE80211_AID_MAX2007, RT2860_WCID_MAX254);
358
359 ifp->if_softc = sc;
360 ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
361 ifp->if_ioctl = rt2860_ioctl;
362 ifp->if_start = rt2860_start;
363 ifp->if_watchdog = rt2860_watchdog;
364 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ)__builtin_memcpy((ifp->if_xname), (sc->sc_dev.dv_xname)
, (16))
;
365
366 if_attach(ifp);
367 ieee80211_ifattach(ifp);
368 ic->ic_node_alloc = rt2860_node_alloc;
369 ic->ic_newassoc = rt2860_newassoc;
370#ifndef IEEE80211_STA_ONLY
371 ic->ic_node_leave = rt2860_node_leave;
372#endif
373 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start;
374 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop;
375 ic->ic_updateslot = rt2860_updateslot;
376 ic->ic_updateedca = rt2860_updateedca;
377 ic->ic_set_key = rt2860_set_key;
378 ic->ic_delete_key = rt2860_delete_key;
379 /* override state transition machine */
380 sc->sc_newstate = ic->ic_newstate;
381 ic->ic_newstate = rt2860_newstate;
382 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status);
383
384#if NBPFILTER1 > 0
385 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO127,
386 sizeof (struct ieee80211_frame) + 64);
387
388 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
389 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len));
390 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
| 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | 1 << IEEE80211_RADIOTAP_ANTENNA
| 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)))
;
391
392 sc->sc_txtap_len = sizeof sc->sc_txtapu;
393 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len));
394 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
)))
;
395#endif
396}
397
398int
399rt2860_detach(void *xsc)
400{
401 struct rt2860_softc *sc = xsc;
402 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
403 int qid;
404
405 ieee80211_ifdetach(ifp); /* free all nodes */
406 if_detach(ifp);
407
408 for (qid = 0; qid < 6; qid++)
409 rt2860_free_tx_ring(sc, &sc->txq[qid]);
410 rt2860_free_rx_ring(sc, &sc->rxq);
411 rt2860_free_tx_pool(sc);
412
413 if (sc->ucode != NULL((void *)0))
414 free(sc->ucode, M_DEVBUF2, sc->ucsize);
415
416 return 0;
417}
418
419void
420rt2860_suspend(void *xsc)
421{
422 struct rt2860_softc *sc = xsc;
423 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
424
425 if (ifp->if_flags & IFF_RUNNING0x40)
426 rt2860_stop(ifp, 1);
427}
428
429void
430rt2860_wakeup(void *xsc)
431{
432 struct rt2860_softc *sc = xsc;
433 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
434
435 if (ifp->if_flags & IFF_UP0x1)
436 rt2860_init(ifp);
437}
438
439int
440rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
441{
442 int nsegs, size, error;
443
444 size = RT2860_TX_RING_COUNT64 * sizeof (struct rt2860_txd);
445
446 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&ring->map))
447 BUS_DMA_NOWAIT, &ring->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&ring->map))
;
448 if (error != 0) {
449 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
450 goto fail;
451 }
452
453 /* Tx rings must be 4-DWORD aligned */
454 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), (16), (0), (&ring->seg), (1), (&nsegs), (0x0001
| 0x1000))
455 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), (16), (0), (&ring->seg), (1), (&nsegs), (0x0001
| 0x1000))
;
456 if (error != 0) {
457 printf("%s: could not allocate DMA memory\n",
458 sc->sc_dev.dv_xname);
459 goto fail;
460 }
461
462 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&ring
->seg), (nsegs), (size), ((caddr_t *)&ring->txd), (
0x0001))
463 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&ring
->seg), (nsegs), (size), ((caddr_t *)&ring->txd), (
0x0001))
;
464 if (error != 0) {
465 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
466 goto fail;
467 }
468
469 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (ring->
map), (ring->txd), (size), (((void *)0)), (0x0001))
470 BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (ring->
map), (ring->txd), (size), (((void *)0)), (0x0001))
;
471 if (error != 0) {
472 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
473 goto fail;
474 }
475
476 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (size), (0x04))
;
477
478 ring->paddr = ring->map->dm_segs[0].ds_addr;
479
480 return 0;
481
482fail: rt2860_free_tx_ring(sc, ring);
483 return error;
484}
485
486void
487rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
488{
489 struct rt2860_tx_data *data;
490 int i;
491
492 for (i = 0; i < RT2860_TX_RING_COUNT64; i++) {
493 if ((data = ring->data[i]) == NULL((void *)0))
494 continue; /* nothing mapped in this slot */
495
496 bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
;
498 bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map))
;
499 m_freem(data->m);
500 data->m= NULL((void *)0);
501 data->ni = NULL((void *)0); /* node already freed */
502
503 SLIST_INSERT_HEAD(&sc->data_pool, data, next)do { (data)->next.sle_next = (&sc->data_pool)->slh_first
; (&sc->data_pool)->slh_first = (data); } while (0)
;
504 ring->data[i] = NULL((void *)0);
505 }
506
507 ring->queued = 0;
508 ring->cur = ring->next = 0;
509}
510
511void
512rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
513{
514 struct rt2860_tx_data *data;
515 int i;
516
517 if (ring->txd != NULL((void *)0)) {
518 bus_dmamap_sync(sc->sc_dmat, ring->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x08))
519 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x08))
;
520 bus_dmamap_unload(sc->sc_dmat, ring->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (ring
->map))
;
521 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)ring->txd), (64 * sizeof (struct rt2860_txd)))
522 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd))(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)ring->txd), (64 * sizeof (struct rt2860_txd)))
;
523 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
ring->seg), (1))
;
524 }
525 if (ring->map != NULL((void *)0))
526 bus_dmamap_destroy(sc->sc_dmat, ring->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (ring
->map))
;
527
528 for (i = 0; i < RT2860_TX_RING_COUNT64; i++) {
529 if ((data = ring->data[i]) == NULL((void *)0))
530 continue; /* nothing mapped in this slot */
531
532 bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
533 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
;
534 bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map))
;
535 m_freem(data->m);
536
537 SLIST_INSERT_HEAD(&sc->data_pool, data, next)do { (data)->next.sle_next = (&sc->data_pool)->slh_first
; (&sc->data_pool)->slh_first = (data); } while (0)
;
538 }
539}
540
541/*
542 * Allocate a pool of TX Wireless Information blocks.
543 */
544int
545rt2860_alloc_tx_pool(struct rt2860_softc *sc)
546{
547 caddr_t vaddr;
548 bus_addr_t paddr;
549 int i, nsegs, size, error;
550
551 size = RT2860_TX_POOL_COUNT(64 * 2) * RT2860_TXWI_DMASZ(sizeof (struct rt2860_txwi) + sizeof (struct ieee80211_htframe
) + sizeof (uint16_t))
;
552
553 /* init data_pool early in case of failure.. */
554 SLIST_INIT(&sc->data_pool){ ((&sc->data_pool)->slh_first) = ((void *)0); };
555
556 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&sc->txwi_map))
557 BUS_DMA_NOWAIT, &sc->txwi_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&sc->txwi_map))
;
558 if (error != 0) {
559 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
560 goto fail;
561 }
562
563 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), ((1 << 12)), (0), (&sc->txwi_seg), (1), (&
nsegs), (0x0001 | 0x1000))
564 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), ((1 << 12)), (0), (&sc->txwi_seg), (1), (&
nsegs), (0x0001 | 0x1000))
;
565 if (error != 0) {
566 printf("%s: could not allocate DMA memory\n",
567 sc->sc_dev.dv_xname);
568 goto fail;
569 }
570
571 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->txwi_seg), (nsegs), (size), (&sc->txwi_vaddr), (0x0001
))
572 &sc->txwi_vaddr, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->txwi_seg), (nsegs), (size), (&sc->txwi_vaddr), (0x0001
))
;
573 if (error != 0) {
574 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
575 goto fail;
576 }
577
578 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
txwi_map), (sc->txwi_vaddr), (size), (((void *)0)), (0x0001
))
579 size, NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
txwi_map), (sc->txwi_vaddr), (size), (((void *)0)), (0x0001
))
;
580 if (error != 0) {
581 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
582 goto fail;
583 }
584
585 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), (0), (size), (0x04))
586 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), (0), (size), (0x04))
;
587
588 vaddr = sc->txwi_vaddr;
589 paddr = sc->txwi_map->dm_segs[0].ds_addr;
590 for (i = 0; i < RT2860_TX_POOL_COUNT(64 * 2); i++) {
591 struct rt2860_tx_data *data = &sc->data[i];
592
593 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (15), ((1 << 11)), (0), (0x0001), (&data->
map))
594 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (15), ((1 << 11)), (0), (0x0001), (&data->
map))
595 &data->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (15), ((1 << 11)), (0), (0x0001), (&data->
map))
; /* <0> */
596 if (error != 0) {
597 printf("%s: could not create DMA map\n",
598 sc->sc_dev.dv_xname);
599 goto fail;
600 }
601 data->txwi = (struct rt2860_txwi *)vaddr;
602 data->paddr = paddr;
603 vaddr += RT2860_TXWI_DMASZ(sizeof (struct rt2860_txwi) + sizeof (struct ieee80211_htframe
) + sizeof (uint16_t))
;
604 paddr += RT2860_TXWI_DMASZ(sizeof (struct rt2860_txwi) + sizeof (struct ieee80211_htframe
) + sizeof (uint16_t))
;
605
606 SLIST_INSERT_HEAD(&sc->data_pool, data, next)do { (data)->next.sle_next = (&sc->data_pool)->slh_first
; (&sc->data_pool)->slh_first = (data); } while (0)
;
607 }
608
609 return 0;
610
611fail: rt2860_free_tx_pool(sc);
612 return error;
613}
614
615void
616rt2860_free_tx_pool(struct rt2860_softc *sc)
617{
618 if (sc->txwi_vaddr != NULL((void *)0)) {
619 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), (0), (sc->txwi_map->dm_mapsize), (0x08))
620 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), (0), (sc->txwi_map->dm_mapsize), (0x08))
;
621 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
txwi_map))
;
622 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (sc->
txwi_vaddr), ((64 * 2) * (sizeof (struct rt2860_txwi) + sizeof
(struct ieee80211_htframe) + sizeof (uint16_t))))
623 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (sc->
txwi_vaddr), ((64 * 2) * (sizeof (struct rt2860_txwi) + sizeof
(struct ieee80211_htframe) + sizeof (uint16_t))))
;
624 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
sc->txwi_seg), (1))
;
625 }
626 if (sc->txwi_map != NULL((void *)0))
627 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->txwi_map))
;
628
629 while (!SLIST_EMPTY(&sc->data_pool)(((&sc->data_pool)->slh_first) == ((void *)0))) {
630 struct rt2860_tx_data *data;
631 data = SLIST_FIRST(&sc->data_pool)((&sc->data_pool)->slh_first);
632 bus_dmamap_destroy(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (data
->map))
;
633 SLIST_REMOVE_HEAD(&sc->data_pool, next)do { (&sc->data_pool)->slh_first = (&sc->data_pool
)->slh_first->next.sle_next; } while (0)
;
634 }
635}
636
637int
638rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
639{
640 int i, nsegs, size, error;
641
642 size = RT2860_RX_RING_COUNT128 * sizeof (struct rt2860_rxd);
643
644 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&ring->map))
645 BUS_DMA_NOWAIT, &ring->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0001), (&ring->map))
;
646 if (error != 0) {
647 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
648 goto fail;
649 }
650
651 /* Rx ring must be 4-DWORD aligned */
652 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), (16), (0), (&ring->seg), (1), (&nsegs), (0x0001
| 0x1000))
653 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), (16), (0), (&ring->seg), (1), (&nsegs), (0x0001
| 0x1000))
;
654 if (error != 0) {
655 printf("%s: could not allocate DMA memory\n",
656 sc->sc_dev.dv_xname);
657 goto fail;
658 }
659
660 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&ring
->seg), (nsegs), (size), ((caddr_t *)&ring->rxd), (
0x0001))
661 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&ring
->seg), (nsegs), (size), ((caddr_t *)&ring->rxd), (
0x0001))
;
662 if (error != 0) {
663 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
664 goto fail;
665 }
666
667 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (ring->
map), (ring->rxd), (size), (((void *)0)), (0x0001))
668 BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (ring->
map), (ring->rxd), (size), (((void *)0)), (0x0001))
;
669 if (error != 0) {
670 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
671 goto fail;
672 }
673
674 ring->paddr = ring->map->dm_segs[0].ds_addr;
675
676 for (i = 0; i < RT2860_RX_RING_COUNT128; i++) {
677 struct rt2860_rx_data *data = &ring->data[i];
678 struct rt2860_rxd *rxd = &ring->rxd[i];
679
680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (1), ((1 << 11)), (0), (0x0001), (&data->
map))
681 0, BUS_DMA_NOWAIT, &data->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (1), ((1 << 11)), (0), (0x0001), (&data->
map))
;
682 if (error != 0) {
683 printf("%s: could not create DMA map\n",
684 sc->sc_dev.dv_xname);
685 goto fail;
686 }
687
688 data->m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
689 if (data->m == NULL((void *)0)) {
690 printf("%s: could not allocate Rx mbuf\n",
691 sc->sc_dev.dv_xname);
692 error = ENOBUFS55;
693 goto fail;
694 }
695
696 error = bus_dmamap_load(sc->sc_dmat, data->map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
697 mtod(data->m, void *), MCLBYTES, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
698 BUS_DMA_READ | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
;
699 if (error != 0) {
700 printf("%s: could not load DMA map\n",
701 sc->sc_dev.dv_xname);
702 goto fail;
703 }
704
705 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr)((__uint32_t)(data->map->dm_segs[0].ds_addr));
706 rxd->sdl0 = htole16(MCLBYTES)((__uint16_t)((1 << 11)));
707 }
708
709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (size), (0x04))
;
710
711 return 0;
712
713fail: rt2860_free_rx_ring(sc, ring);
714 return error;
715}
716
717void
718rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
719{
720 int i;
721
722 for (i = 0; i < RT2860_RX_RING_COUNT128; i++)
723 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE)((__uint16_t)((1 << 15)));
724
725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x04))
726 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x04))
;
727
728 ring->cur = 0;
729}
730
731void
732rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
733{
734 int i;
735
736 if (ring->rxd != NULL((void *)0)) {
737 bus_dmamap_sync(sc->sc_dmat, ring->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x08))
738 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x08))
;
739 bus_dmamap_unload(sc->sc_dmat, ring->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (ring
->map))
;
740 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)ring->rxd), (128 * sizeof (struct rt2860_rxd)))
741 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd))(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)ring->rxd), (128 * sizeof (struct rt2860_rxd)))
;
742 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
ring->seg), (1))
;
743 }
744 if (ring->map != NULL((void *)0))
745 bus_dmamap_destroy(sc->sc_dmat, ring->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (ring
->map))
;
746
747 for (i = 0; i < RT2860_RX_RING_COUNT128; i++) {
748 struct rt2860_rx_data *data = &ring->data[i];
749
750 if (data->m != NULL((void *)0)) {
751 bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02))
752 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02))
;
753 bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map))
;
754 m_freem(data->m);
755 }
756 if (data->map != NULL((void *)0))
757 bus_dmamap_destroy(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (data
->map))
;
758 }
759}
760
761struct ieee80211_node *
762rt2860_node_alloc(struct ieee80211com *ic)
763{
764 return malloc(sizeof (struct rt2860_node), M_DEVBUF2,
765 M_NOWAIT0x0002 | M_ZERO0x0008);
766}
767
768int
769rt2860_media_change(struct ifnet *ifp)
770{
771 struct rt2860_softc *sc = ifp->if_softc;
772 struct ieee80211com *ic = &sc->sc_ic;
773 uint8_t rate, ridx;
774 int error;
775
776 error = ieee80211_media_change(ifp);
777 if (error != ENETRESET52)
778 return error;
779
780 if (ic->ic_fixed_rate != -1) {
781 rate = ic->ic_sup_rates[ic->ic_curmode].
782 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL0x7f;
783 for (ridx = 0; ridx <= RT2860_RIDX_MAX11; ridx++)
784 if (rt2860_rates[ridx].rate == rate)
785 break;
786 sc->fixed_ridx = ridx;
787 }
788
789 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
790 (IFF_UP0x1 | IFF_RUNNING0x40)) {
791 rt2860_stop(ifp, 0);
792 rt2860_init(ifp);
793 }
794 return 0;
795}
796
797void
798rt2860_iter_func(void *arg, struct ieee80211_node *ni)
799{
800 struct rt2860_softc *sc = arg;
801 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
802
803 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
804}
805
806void
807rt2860_updatestats(struct rt2860_softc *sc)
808{
809 struct ieee80211com *ic = &sc->sc_ic;
810
811#ifndef IEEE80211_STA_ONLY
812 /*
813 * In IBSS or HostAP modes (when the hardware sends beacons), the
814 * MAC can run into a livelock and start sending CTS-to-self frames
815 * like crazy if protection is enabled. Fortunately, we can detect
816 * when such a situation occurs and reset the MAC.
817 */
818 if (ic->ic_curmode != IEEE80211_M_STA) {
819 /* check if we're in a livelock situation.. */
820 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x10f4))));
821 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
822 /* ..and reset MAC/BBP for a while.. */
823 DPRINTF(("CTS-to-self livelock detected\n"));
824 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 0)))))
;
825 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
826 DELAY(1)(*delay_func)(1);
827 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 3) | (1 << 2)))))
828 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 3) | (1 << 2)))))
;
829 }
830 }
831#endif
832 if (ic->ic_opmode == IEEE80211_M_STA)
833 rt2860_iter_func(sc, ic->ic_bss);
834#ifndef IEEE80211_STA_ONLY
835 else
836 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc);
837#endif
838}
839
840void
841rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
842{
843 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
844 struct rt2860_node *rn = (void *)ni;
845 struct ieee80211_rateset *rs = &ni->ni_rates;
846 uint8_t rate, wcid = 0;
847 int ridx, i, j;
848
849 if (isnew && ni->ni_associd != 0) {
850 /* only interested in true associations */
851 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd)((ni->ni_associd) &~ 0xc000);
852
853 /* init WCID table entry */
854 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x1800
+ (wcid) * 8))), ((ni->ni_macaddr)), ((6))))
855 ni->ni_macaddr, IEEE80211_ADDR_LEN)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x1800
+ (wcid) * 8))), ((ni->ni_macaddr)), ((6))))
;
856 }
857 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
858 isnew, ether_sprintf(ni->ni_macaddr), wcid));
859
860 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
861 /* start at lowest available bit-rate, AMRR will raise */
862 ni->ni_txrate = 0;
863
864 for (i = 0; i < rs->rs_nrates; i++) {
865 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL0x7f;
866 /* convert 802.11 rate to hardware rate index */
867 for (ridx = 0; ridx < RT2860_RIDX_MAX11; ridx++)
868 if (rt2860_rates[ridx].rate == rate)
869 break;
870 rn->ridx[i] = ridx;
871 /* determine rate of control response frames */
872 for (j = i; j >= 0; j--) {
873 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC0x80) &&
874 rt2860_rates[rn->ridx[i]].phy ==
875 rt2860_rates[rn->ridx[j]].phy)
876 break;
877 }
878 if (j >= 0) {
879 rn->ctl_ridx[i] = rn->ridx[j];
880 } else {
881 /* no basic rate found, use mandatory one */
882 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx;
883 }
884 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n",
885 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i]));
886 }
887}
888
889#ifndef IEEE80211_STA_ONLY
890void
891rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni)
892{
893 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
894 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
895
896 /* clear Rx WCID search table entry */
897 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x1800
+ (wcid) * 8))), ((0)), ((2))))
;
898}
899#endif
900
901int
902rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
903 uint8_t tid)
904{
905 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
906 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
907 uint32_t tmp;
908
909 /* update BA session mask */
910 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4)(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x1800 + (wcid
) * 8) + 4))))
;
911 tmp |= (1 << tid) << 16;
912 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1800 + (
wcid) * 8) + 4)), ((tmp))))
;
913 return 0;
914}
915
916void
917rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
918 uint8_t tid)
919{
920 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
921 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
922 uint32_t tmp;
923
924 /* update BA session mask */
925 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4)(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x1800 + (wcid
) * 8) + 4))))
;
926 tmp &= ~((1 << tid) << 16);
927 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1800 + (
wcid) * 8) + 4)), ((tmp))))
;
928}
929
930int
931rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
932{
933 struct rt2860_softc *sc = ic->ic_ific_ac.ac_if.if_softc;
934 enum ieee80211_state ostate;
935 uint32_t tmp;
936
937 ostate = ic->ic_state;
938
939 if (ostate == IEEE80211_S_RUN) {
940 /* turn link LED off */
941 rt2860_set_leds(sc, RT2860_LED_RADIO(1 << 13));
942 }
943
944 switch (nstate) {
945 case IEEE80211_S_INIT:
946 if (ostate == IEEE80211_S_RUN) {
947 /* abort TSF synchronization */
948 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1114))));
949 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1114)), (
(tmp & ~((1 << 20) | (1 << 16) | (1 << 19
))))))
950 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1114)), (
(tmp & ~((1 << 20) | (1 << 16) | (1 << 19
))))))
951 RT2860_TBTT_TIMER_EN))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1114)), (
(tmp & ~((1 << 20) | (1 << 16) | (1 << 19
))))))
;
952 }
953 rt2860_set_gp_timer(sc, 0);
954 break;
955
956 case IEEE80211_S_SCAN:
957 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
958 if (ostate != IEEE80211_S_SCAN)
959 rt2860_set_gp_timer(sc, 150);
960 break;
961
962 case IEEE80211_S_AUTH:
963 case IEEE80211_S_ASSOC:
964 rt2860_set_gp_timer(sc, 0);
965 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
966 break;
967
968 case IEEE80211_S_RUN:
969 rt2860_set_gp_timer(sc, 0);
970 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
971
972 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
973 rt2860_updateslot(ic);
974 rt2860_enable_mrr(sc);
975 rt2860_set_txpreamble(sc);
976 rt2860_set_basicrates(sc);
977 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid);
978 }
979
980#ifndef IEEE80211_STA_ONLY
981 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
982 ic->ic_opmode == IEEE80211_M_IBSS)
983 (void)rt2860_setup_beacon(sc);
984#endif
985
986 if (ic->ic_opmode == IEEE80211_M_STA) {
987 /* fake a join to init the tx rate */
988 rt2860_newassoc(ic, ic->ic_bss, 1);
989 }
990
991 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
992 rt2860_enable_tsf_sync(sc);
993 rt2860_set_gp_timer(sc, 500);
994 }
995
996 /* turn link LED on */
997 rt2860_set_leds(sc, RT2860_LED_RADIO(1 << 13) |
998 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0
)
?
999 RT2860_LED_LINK_2GHZ(1 << 14) : RT2860_LED_LINK_5GHZ(1 << 15)));
1000 break;
1001 }
1002
1003 return sc->sc_newstate(ic, nstate, arg);
1004}
1005
1006/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
1007uint16_t
1008rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
1009{
1010 uint32_t tmp;
1011 uint16_t reg;
1012 int ntries;
1013
1014 addr *= 2;
1015 /*-
1016 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1017 * DATA0: F E D C
1018 * DATA1: B A 9 8
1019 * DATA2: 7 6 5 4
1020 * DATA3: 3 2 1 0
1021 */
1022 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0580))));
1023 tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000);
1024 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30);
1025 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0580)), (
(tmp))))
;
1026 for (ntries = 0; ntries < 500; ntries++) {
1027 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0580))));
1028 if (!(tmp & RT3070_EFSROM_KICK(1U << 30)))
1029 break;
1030 DELAY(2)(*delay_func)(2);
1031 }
1032 if (ntries == 500)
1033 return 0xffff;
1034
1035 if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f)
1036 return 0xffff; /* address not found */
1037
1038 /* determine to which 32-bit register our 16-bit word belongs */
1039 reg = RT3070_EFUSE_DATA30x059c - (addr & 0xc);
1040 tmp = RAL_READ(sc, reg)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((reg))));
1041
1042 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1043}
1044
1045/* Read 16 bits from eFUSE ROM (RT3290 only) */
1046uint16_t
1047rt3290_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
1048{
1049 uint32_t tmp;
1050 uint16_t reg;
1051 int ntries;
1052
1053 addr *= 2;
1054 /*-
1055 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1056 * DATA3: 3 2 1 0
1057 * DATA2: 7 6 5 4
1058 * DATA1: B A 9 8
1059 * DATA0: F E D C
1060 */
1061 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0024))));
1062 tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000);
1063 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30);
1064 RAL_WRITE(sc, RT3290_EFUSE_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0024)), (
(tmp))))
;
1065 for (ntries = 0; ntries < 500; ntries++) {
1066 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0024))));
1067 if (!(tmp & RT3070_EFSROM_KICK(1U << 30)))
1068 break;
1069 DELAY(2)(*delay_func)(2);
1070 }
1071 if (ntries == 500)
1072 return 0xffff;
1073
1074 if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f)
1075 return 0xffff; /* address not found */
1076
1077 /* determine to which 32-bit register our 16-bit word belongs */
1078 reg = RT3290_EFUSE_DATA30x0028 + (addr & 0xc);
1079 tmp = RAL_READ(sc, reg)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((reg))));
1080
1081 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1082}
1083
1084/*
1085 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1086 * 93C66 or 93C86).
1087 */
1088uint16_t
1089rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1090{
1091 uint32_t tmp;
1092 uint16_t val;
1093 int n;
1094
1095 /* clock C once before the first command */
1096 RT2860_EEPROM_CTL(sc, 0)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), (((0))))); bus_space_barrier(((sc))->sc_st, ((sc))->
sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1); } while ( 0
)
;
1097
1098 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1099 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 0)))))); bus_space_barrier
(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02);
(*delay_func)(1); } while ( 0)
;
1100 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1101
1102 /* write start bit (1) */
1103 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 2)))))); bus_space_barrier
(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02);
(*delay_func)(1); } while ( 0)
;
1104 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 2) | (1 << 0))))));
bus_space_barrier(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800
, 0x01 | 0x02); (*delay_func)(1); } while ( 0)
;
1105
1106 /* write READ opcode (10) */
1107 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 2)))))); bus_space_barrier
(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02);
(*delay_func)(1); } while ( 0)
;
1108 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 2) | (1 << 0))))));
bus_space_barrier(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800
, 0x01 | 0x02); (*delay_func)(1); } while ( 0)
;
1109 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1110 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 0)))))); bus_space_barrier
(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02);
(*delay_func)(1); } while ( 0)
;
1111
1112 /* write address (A5-A0 or A7-A0) */
1113 n = ((RAL_READ(sc, RT2860_PCI_EECTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0004)))) & 0x30) == 0) ? 5 : 7;
1114 for (; n >= 0; n--) {
1115 RT2860_EEPROM_CTL(sc, RT2860_S |do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (((addr >> n) & 1) <<
2)))))); bus_space_barrier(((sc))->sc_st, ((sc))->sc_sh
, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1); } while ( 0)
1116 (((addr >> n) & 1) << RT2860_SHIFT_D))do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (((addr >> n) & 1) <<
2)))))); bus_space_barrier(((sc))->sc_st, ((sc))->sc_sh
, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1); } while ( 0)
;
1117 RT2860_EEPROM_CTL(sc, RT2860_S |do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (((addr >> n) & 1) <<
2) | (1 << 0)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
1118 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (((addr >> n) & 1) <<
2) | (1 << 0)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1119 }
1120
1121 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1122
1123 /* read data Q15-Q0 */
1124 val = 0;
1125 for (n = 15; n >= 0; n--) {
1126 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1) | (1 << 0)))))); bus_space_barrier
(((sc))->sc_st, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02);
(*delay_func)(1); } while ( 0)
;
1127 tmp = RAL_READ(sc, RT2860_PCI_EECTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0004))));
1128 val |= ((tmp & RT2860_Q(1 << 3)) >> RT2860_SHIFT_Q3) << n;
1129 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1130 }
1131
1132 RT2860_EEPROM_CTL(sc, 0)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), (((0))))); bus_space_barrier(((sc))->sc_st, ((sc))->
sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1); } while ( 0
)
;
1133
1134 /* clear Chip Select and clock C */
1135 RT2860_EEPROM_CTL(sc, RT2860_S)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 1)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1136 RT2860_EEPROM_CTL(sc, 0)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), (((0))))); bus_space_barrier(((sc))->sc_st, ((sc))->
sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1); } while ( 0
)
;
1137 RT2860_EEPROM_CTL(sc, RT2860_C)do { ((((sc))->sc_st)->write_4((((sc))->sc_sh), ((0x0004
)), ((((1 << 0)))))); bus_space_barrier(((sc))->sc_st
, ((sc))->sc_sh, 0, 0x1800, 0x01 | 0x02); (*delay_func)(1)
; } while ( 0)
;
1138
1139 return val;
1140}
1141
1142static __inline uint16_t
1143rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1144{
1145 /* either eFUSE ROM or EEPROM */
1146 return sc->sc_srom_read(sc, addr);
1147}
1148
1149void
1150rt2860_intr_coherent(struct rt2860_softc *sc)
1151{
1152 uint32_t tmp;
1153
1154 /* DMA finds data coherent event when checking the DDONE bit */
1155
1156 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1157
1158 /* restart DMA engine */
1159 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0208))));
1160 tmp &= ~(RT2860_TX_WB_DDONE(1 << 6) | RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0));
1161 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0208)), (
(tmp))))
;
1162
1163 (void)rt2860_txrx_enable(sc);
1164}
1165
1166void
1167rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1168{
1169 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
1170 struct ieee80211_amrr_node *amn;
1171 uint32_t stat;
1172 uint8_t wcid, mcs, pid;
1173
1174 /* drain Tx status FIFO (maxsize = 16) */
1175 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1718))))) & RT2860_TXQ_VLD(1 << 0)) {
1176 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1177
1178 wcid = (stat >> RT2860_TXQ_WCID_SHIFT8) & 0xff;
1179
1180 /* if no ACK was requested, no feedback is available */
1181 if (!(stat & RT2860_TXQ_ACKREQ(1 << 7)) || wcid == 0xff)
1182 continue;
1183
1184 /* update per-STA AMRR stats */
1185 amn = &sc->amn[wcid];
1186 amn->amn_txcnt++;
1187 if (stat & RT2860_TXQ_OK(1 << 5)) {
1188 /*
1189 * Check if there were retries, ie if the Tx success
1190 * rate is different from the requested rate. Note
1191 * that it works only because we do not allow rate
1192 * fallback from OFDM to CCK.
1193 */
1194 mcs = (stat >> RT2860_TXQ_MCS_SHIFT16) & 0x7f;
1195 pid = (stat >> RT2860_TXQ_PID_SHIFT1) & 0xf;
1196 if (mcs + 1 != pid)
1197 amn->amn_retrycnt++;
1198 } else {
1199 amn->amn_retrycnt++;
1200 ifp->if_oerrorsif_data.ifi_oerrors++;
1201 }
1202 }
1203}
1204
1205void
1206rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1207{
1208 struct ieee80211com *ic = &sc->sc_ic;
1209 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
1210 struct rt2860_tx_ring *ring = &sc->txq[qid];
1211 uint32_t hw;
1212
1213 rt2860_drain_stats_fifo(sc);
1214
1215 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid))(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x023c + (qid
) * 16)))))
;
1216 while (ring->next != hw) {
1217 struct rt2860_tx_data *data = ring->data[ring->next];
1218
1219 if (data != NULL((void *)0)) {
1220 bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
1221 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
;
1222 bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map))
;
1223 m_freem(data->m);
1224 data->m= NULL((void *)0);
1225 ieee80211_release_node(ic, data->ni);
1226 data->ni = NULL((void *)0);
1227
1228 SLIST_INSERT_HEAD(&sc->data_pool, data, next)do { (data)->next.sle_next = (&sc->data_pool)->slh_first
; (&sc->data_pool)->slh_first = (data); } while (0)
;
1229 ring->data[ring->next] = NULL((void *)0);
1230 }
1231 ring->queued--;
1232 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT64;
1233 }
1234
1235 sc->sc_tx_timer = 0;
1236 if (ring->queued <= RT2860_TX_RING_ONEMORE((64 - 1) - (1 + (15 / 2))))
1237 sc->qfullmsk &= ~(1 << qid);
1238 ifq_clr_oactive(&ifp->if_snd);
1239 rt2860_start(ifp);
1240}
1241
1242/*
1243 * Return the Rx chain with the highest RSSI for a given frame.
1244 */
1245static __inline uint8_t
1246rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1247{
1248 uint8_t rxchain = 0;
1249
1250 if (sc->nrxchains > 1) {
1251 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1252 rxchain = 1;
1253 if (sc->nrxchains > 2)
1254 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1255 rxchain = 2;
1256 }
1257 return rxchain;
1258}
1259
1260void
1261rt2860_rx_intr(struct rt2860_softc *sc)
1262{
1263 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
1264 struct ieee80211com *ic = &sc->sc_ic;
1265 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
1266 struct ieee80211_frame *wh;
1267 struct ieee80211_rxinfo rxi;
1268 struct ieee80211_node *ni;
1269 struct mbuf *m, *m1;
1270 uint32_t hw;
1271 uint8_t ant, rssi;
1272 int error;
1273#if NBPFILTER1 > 0
1274 struct rt2860_rx_radiotap_header *tap;
1275 uint16_t phy;
1276#endif
1277
1278 hw = RAL_READ(sc, RT2860_FS_DRX_IDX)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x029c)))) & 0xfff;
1279 while (sc->rxq.cur != hw) {
1280 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1281 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1282 struct rt2860_rxwi *rxwi;
1283
1284 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x02))
1285 sc->rxq.cur * sizeof (struct rt2860_rxd),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x02))
1286 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x02))
;
1287
1288 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))__builtin_expect(((!(rxd->sdl0 & ((__uint16_t)((1 <<
15))))) != 0), 0)
) {
1289 DPRINTF(("RXD DDONE bit not set!\n"));
1290 break; /* should not happen */
1291 }
1292
1293 if (__predict_false(rxd->flags &__builtin_expect(((rxd->flags & ((__uint32_t)((1 <<
8) | (1 << 9)))) != 0), 0)
1294 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))__builtin_expect(((rxd->flags & ((__uint32_t)((1 <<
8) | (1 << 9)))) != 0), 0)
) {
1295 ifp->if_ierrorsif_data.ifi_ierrors++;
1296 goto skip;
1297 }
1298
1299 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))__builtin_expect(((rxd->flags & ((__uint32_t)((1 <<
10)))) != 0), 0)
) {
1300 /* report MIC failures to net80211 for TKIP */
1301 ic->ic_stats.is_rx_locmicfail++;
1302 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1303 ifp->if_ierrorsif_data.ifi_ierrors++;
1304 goto skip;
1305 }
1306
1307 m1 = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
1308 if (__predict_false(m1 == NULL)__builtin_expect(((m1 == ((void *)0)) != 0), 0)) {
1309 ifp->if_ierrorsif_data.ifi_ierrors++;
1310 goto skip;
1311 }
1312
1313 bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02))
1314 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02))
;
1315 bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map))
;
1316
1317 error = bus_dmamap_load(sc->sc_dmat, data->map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((m1)->m_hdr.mh_data))), ((1 << 11))
, (((void *)0)), (0x0200 | 0x0001))
1318 mtod(m1, void *), MCLBYTES, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((m1)->m_hdr.mh_data))), ((1 << 11))
, (((void *)0)), (0x0200 | 0x0001))
1319 BUS_DMA_READ | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((m1)->m_hdr.mh_data))), ((1 << 11))
, (((void *)0)), (0x0200 | 0x0001))
;
1320 if (__predict_false(error != 0)__builtin_expect(((error != 0) != 0), 0)) {
1321 m_freem(m1);
1322
1323 /* try to reload the old mbuf */
1324 error = bus_dmamap_load(sc->sc_dmat, data->map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
1325 mtod(data->m, void *), MCLBYTES, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
1326 BUS_DMA_READ | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (data->
map), (((void *)((data->m)->m_hdr.mh_data))), ((1 <<
11)), (((void *)0)), (0x0200 | 0x0001))
;
1327 if (__predict_false(error != 0)__builtin_expect(((error != 0) != 0), 0)) {
1328 panic("%s: could not load old rx mbuf",
1329 sc->sc_dev.dv_xname);
1330 }
1331 /* physical address may have changed */
1332 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr)((__uint32_t)(data->map->dm_segs[0].ds_addr));
1333 ifp->if_ierrorsif_data.ifi_ierrors++;
1334 goto skip;
1335 }
1336
1337 /*
1338 * New mbuf successfully loaded, update Rx ring and continue
1339 * processing.
1340 */
1341 m = data->m;
1342 data->m = m1;
1343 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr)((__uint32_t)(data->map->dm_segs[0].ds_addr));
1344
1345 rxwi = mtod(m, struct rt2860_rxwi *)((struct rt2860_rxwi *)((m)->m_hdr.mh_data));
1346
1347 /* finalize mbuf */
1348 m->m_datam_hdr.mh_data = (caddr_t)(rxwi + 1);
1349 m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = letoh16(rxwi->len)((__uint16_t)(rxwi->len)) & 0xfff;
1350
1351 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1352 rxi.rxi_flags = 0;
1353 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) {
1354 /* frame is decrypted by hardware */
1355 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED0x40;
1356 rxi.rxi_flags |= IEEE80211_RXI_HWDEC0x00000001;
1357 }
1358
1359 /* HW may insert 2 padding bytes after 802.11 header */
1360 if (rxd->flags & htole32(RT2860_RX_L2PAD)((__uint32_t)((1 << 14)))) {
1361 u_int hdrlen = ieee80211_get_hdrlen(wh);
1362 memmove((caddr_t)wh + 2, wh, hdrlen)__builtin_memmove(((caddr_t)wh + 2), (wh), (hdrlen));
1363 m->m_datam_hdr.mh_data += 2;
1364 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1365 }
1366
1367 ant = rt2860_maxrssi_chain(sc, rxwi);
1368 rssi = rxwi->rssi[ant];
1369
1370#if NBPFILTER1 > 0
1371 if (__predict_true(sc->sc_drvbpf == NULL)__builtin_expect(((sc->sc_drvbpf == ((void *)0)) != 0), 1))
1372 goto skipbpf;
1373
1374 tap = &sc->sc_rxtapsc_rxtapu.th;
1375 tap->wr_flags = 0;
1376 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq)((__uint16_t)(ic->ic_ibss_chan->ic_freq));
1377 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags)((__uint16_t)(ic->ic_ibss_chan->ic_flags));
1378 tap->wr_antsignal = rssi;
1379 tap->wr_antenna = ant;
1380 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant);
1381 tap->wr_rate = 2; /* in case it can't be found below */
1382 phy = letoh16(rxwi->phy)((__uint16_t)(rxwi->phy));
1383 switch (phy & RT2860_PHY_MODE0xc000) {
1384 case RT2860_PHY_CCK(0 << 14):
1385 switch ((phy & RT2860_PHY_MCS0x7f) & ~RT2860_PHY_SHPRE(1 << 3)) {
1386 case 0: tap->wr_rate = 2; break;
1387 case 1: tap->wr_rate = 4; break;
1388 case 2: tap->wr_rate = 11; break;
1389 case 3: tap->wr_rate = 22; break;
1390 }
1391 if (phy & RT2860_PHY_SHPRE(1 << 3))
1392 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
1393 break;
1394 case RT2860_PHY_OFDM(1 << 14):
1395 switch (phy & RT2860_PHY_MCS0x7f) {
1396 case 0: tap->wr_rate = 12; break;
1397 case 1: tap->wr_rate = 18; break;
1398 case 2: tap->wr_rate = 24; break;
1399 case 3: tap->wr_rate = 36; break;
1400 case 4: tap->wr_rate = 48; break;
1401 case 5: tap->wr_rate = 72; break;
1402 case 6: tap->wr_rate = 96; break;
1403 case 7: tap->wr_rate = 108; break;
1404 }
1405 break;
1406 }
1407 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m,
1408 BPF_DIRECTION_IN(1 << 0));
1409skipbpf:
1410#endif
1411 /* grab a reference to the source node */
1412 ni = ieee80211_find_rxnode(ic, wh);
1413
1414 /* send the frame to the 802.11 layer */
1415 rxi.rxi_rssi = rssi;
1416 rxi.rxi_tstamp = 0; /* unused */
1417 ieee80211_inputm(ifp, m, ni, &rxi, &ml);
1418
1419 /* node is no longer needed */
1420 ieee80211_release_node(ic, ni);
1421
1422skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE)((__uint16_t)((1 << 15)));
1423
1424 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x04))
1425 sc->rxq.cur * sizeof (struct rt2860_rxd),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x04))
1426 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rxq.map), (sc->rxq.cur * sizeof (struct rt2860_rxd)), (sizeof
(struct rt2860_rxd)), (0x04))
;
1427
1428 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT128;
1429 }
1430 if_input(ifp, &ml);
1431
1432 /* tell HW what we have processed */
1433 RAL_WRITE(sc, RT2860_RX_CALC_IDX,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0298)), (
((sc->rxq.cur - 1) % 128))))
1434 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0298)), (
((sc->rxq.cur - 1) % 128))))
;
1435}
1436
1437void
1438rt2860_tbtt_intr(struct rt2860_softc *sc)
1439{
1440 struct ieee80211com *ic = &sc->sc_ic;
1441
1442#ifndef IEEE80211_STA_ONLY
1443 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1444 /* one less beacon until next DTIM */
1445 if (ic->ic_dtim_count == 0)
1446 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1447 else
1448 ic->ic_dtim_count--;
1449
1450 /* update dynamic parts of beacon */
1451 rt2860_setup_beacon(sc);
1452
1453 /* flush buffered multicast frames */
1454 if (ic->ic_dtim_count == 0)
1455 ieee80211_notify_dtim(ic);
1456 }
1457#endif
1458 /* check if protection mode has changed */
1459 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT0x00100000) {
1460 rt2860_updateprot(ic);
1461 sc->sc_ic_flags = ic->ic_flags;
1462 }
1463}
1464
1465void
1466rt2860_gp_intr(struct rt2860_softc *sc)
1467{
1468 struct ieee80211com *ic = &sc->sc_ic;
1469
1470 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state));
1471
1472 if (ic->ic_state == IEEE80211_S_SCAN)
1473 ieee80211_next_scan(&ic->ic_ific_ac.ac_if);
1474 else if (ic->ic_state == IEEE80211_S_RUN)
1475 rt2860_updatestats(sc);
1476}
1477
1478int
1479rt2860_intr(void *arg)
1480{
1481 struct rt2860_softc *sc = arg;
1482 uint32_t r;
1483
1484 r = RAL_READ(sc, RT2860_INT_STATUS)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0200))));
1485 if (__predict_false(r == 0xffffffff)__builtin_expect(((r == 0xffffffff) != 0), 0))
1486 return 0; /* device likely went away */
1487 if (r == 0)
1488 return 0; /* not for us */
1489
1490 /* acknowledge interrupts */
1491 RAL_WRITE(sc, RT2860_INT_STATUS, r)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0200)), (
(r))))
;
1492
1493 if (r & RT2860_TX_RX_COHERENT(1 << 10))
1494 rt2860_intr_coherent(sc);
1495
1496 if (r & RT2860_MAC_INT_2(1 << 13)) /* TX status */
1497 rt2860_drain_stats_fifo(sc);
1498
1499 if (r & RT2860_TX_DONE_INT5(1 << 8))
1500 rt2860_tx_intr(sc, 5);
1501
1502 if (r & RT2860_RX_DONE_INT(1 << 2))
1503 rt2860_rx_intr(sc);
1504
1505 if (r & RT2860_TX_DONE_INT4(1 << 7))
1506 rt2860_tx_intr(sc, 4);
1507
1508 if (r & RT2860_TX_DONE_INT3(1 << 6))
1509 rt2860_tx_intr(sc, 3);
1510
1511 if (r & RT2860_TX_DONE_INT2(1 << 5))
1512 rt2860_tx_intr(sc, 2);
1513
1514 if (r & RT2860_TX_DONE_INT1(1 << 4))
1515 rt2860_tx_intr(sc, 1);
1516
1517 if (r & RT2860_TX_DONE_INT0(1 << 3))
1518 rt2860_tx_intr(sc, 0);
1519
1520 if (r & RT2860_MAC_INT_0(1 << 11)) /* TBTT */
1521 rt2860_tbtt_intr(sc);
1522
1523 if (r & RT2860_MAC_INT_3(1 << 14)) /* Auto wakeup */
1524 /* TBD wakeup */;
1525
1526 if (r & RT2860_MAC_INT_4(1 << 15)) /* GP timer */
1527 rt2860_gp_intr(sc);
1528
1529 return 1;
1530}
1531
1532int
1533rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1534{
1535 struct ieee80211com *ic = &sc->sc_ic;
1536 struct rt2860_node *rn = (void *)ni;
1537 struct rt2860_tx_ring *ring;
1538 struct rt2860_tx_data *data;
1539 struct rt2860_txd *txd;
1540 struct rt2860_txwi *txwi;
1541 struct ieee80211_frame *wh;
1542 bus_dma_segment_t *seg;
1543 u_int hdrlen;
1544 uint16_t qos, dur;
1545 uint8_t type, qsel, mcs, pid, tid, qid;
1546 int nsegs, hasqos, ridx, ctl_ridx;
1547
1548 /* the data pool contains at least one element, pick the first */
1549 data = SLIST_FIRST(&sc->data_pool)((&sc->data_pool)->slh_first);
1550
1551 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1552 hdrlen = ieee80211_get_hdrlen(wh);
1553 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
1554
1555 if ((hasqos = ieee80211_has_qos(wh))) {
1556 qos = ieee80211_get_qos(wh);
1557 tid = qos & IEEE80211_QOS_TID0x000f;
1558 qid = ieee80211_up_to_ac(ic, tid);
1559 } else {
1560 qos = 0;
1561 tid = 0;
1562 qid = (type == IEEE80211_FC0_TYPE_MGT0x00) ?
1563 sc->mgtqid : EDCA_AC_BE;
1564 }
1565 ring = &sc->txq[qid];
1566
1567 /* pickup a rate index */
1568 if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) ||
1569 type != IEEE80211_FC0_TYPE_DATA0x08) {
1570 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
1571 RT2860_RIDX_OFDM64 : RT2860_RIDX_CCK10;
1572 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
1573 } else if (ic->ic_fixed_rate != -1) {
1574 ridx = sc->fixed_ridx;
1575 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
1576 } else {
1577 ridx = rn->ridx[ni->ni_txrate];
1578 ctl_ridx = rn->ctl_ridx[ni->ni_txrate];
1579 }
1580
1581 /* get MCS code from rate index */
1582 mcs = rt2860_rates[ridx].mcs;
1583
1584 /* setup TX Wireless Information */
1585 txwi = data->txwi;
1586 txwi->flags = 0;
1587 /* let HW generate seq numbers for non-QoS frames */
1588 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ(1 << 1);
1589 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA0x08) ? rn->wcid : 0xff;
1590 txwi->len = htole16(m->m_pkthdr.len)((__uint16_t)(m->M_dat.MH.MH_pkthdr.len));
1591 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1592 txwi->phy = htole16(RT2860_PHY_CCK)((__uint16_t)((0 << 14)));
1593 if (ridx != RT2860_RIDX_CCK10 &&
1594 (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000))
1595 mcs |= RT2860_PHY_SHPRE(1 << 3);
1596 } else
1597 txwi->phy = htole16(RT2860_PHY_OFDM)((__uint16_t)((1 << 14)));
1598 txwi->phy |= htole16(mcs)((__uint16_t)(mcs));
1599
1600 /*
1601 * We store the MCS code into the driver-private PacketID field.
1602 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1603 * that we know at which initial rate the frame was transmitted.
1604 * We add 1 to the MCS code because setting the PacketID field to
1605 * 0 means that we don't want feedback in TX_STAT_FIFO.
1606 */
1607 pid = (mcs + 1) & 0xf;
1608 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT)((__uint16_t)(pid << 12));
1609
1610 /* check if RTS/CTS or CTS-to-self protection is required */
1611 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1612 (m->m_pkthdrM_dat.MH.MH_pkthdr.len + IEEE80211_CRC_LEN4 > ic->ic_rtsthreshold ||
1613 ((ic->ic_flags & IEEE80211_F_USEPROT0x00100000) &&
1614 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1615 txwi->txop = RT2860_TX_TXOP_HT0;
1616 else
1617 txwi->txop = RT2860_TX_TXOP_BACKOFF3;
1618
1619 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1620 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK0x0060) !=
1621 IEEE80211_QOS_ACK_POLICY_NOACK0x0020)) {
1622 txwi->xflags |= RT2860_TX_ACK(1 << 0);
1623
1624 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000)
1625 dur = rt2860_rates[ctl_ridx].sp_ack_dur;
1626 else
1627 dur = rt2860_rates[ctl_ridx].lp_ack_dur;
1628 *(uint16_t *)wh->i_dur = htole16(dur)((__uint16_t)(dur));
1629 }
1630#ifndef IEEE80211_STA_ONLY
1631 /* ask MAC to insert timestamp into probe responses */
1632 if ((wh->i_fc[0] &
1633 (IEEE80211_FC0_TYPE_MASK0x0c | IEEE80211_FC0_SUBTYPE_MASK0xf0)) ==
1634 (IEEE80211_FC0_TYPE_MGT0x00 | IEEE80211_FC0_SUBTYPE_PROBE_RESP0x50))
1635 /* NOTE: beacons do not pass through tx_data() */
1636 txwi->flags |= RT2860_TX_TS(1 << 3);
1637#endif
1638
1639#if NBPFILTER1 > 0
1640 if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) {
1641 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtapsc_txtapu.th;
1642
1643 tap->wt_flags = 0;
1644 tap->wt_rate = rt2860_rates[ridx].rate;
1645 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq)((__uint16_t)(ic->ic_ibss_chan->ic_freq));
1646 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags)((__uint16_t)(ic->ic_ibss_chan->ic_flags));
1647 if (mcs & RT2860_PHY_SHPRE(1 << 3))
1648 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
1649
1650 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, m,
1651 BPF_DIRECTION_OUT(1 << 1));
1652 }
1653#endif
1654
1655 /* copy and trim 802.11 header */
1656 memcpy(txwi + 1, wh, hdrlen)__builtin_memcpy((txwi + 1), (wh), (hdrlen));
1657 m_adj(m, hdrlen);
1658
1659 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE)((ring->queued <= ((64 - 1) - (1 + (15 / 2)))) ? (void)
0 : __assert("diagnostic ", "/usr/src/sys/dev/ic/rt2860.c", 1659
, "ring->queued <= RT2860_TX_RING_ONEMORE"))
; /* <1> */
1660
1661 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
data->map), (m), (0x0001))
) {
1662 if (m_defrag(m, M_DONTWAIT0x0002))
1663 return (ENOBUFS55);
1664 if (bus_dmamap_load_mbuf(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
data->map), (m), (0x0001))
1665 data->map, m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
data->map), (m), (0x0001))
)
1666 return (EFBIG27);
1667 }
1668
1669 /* The map will fit into the tx ring: (a "full" ring may have a few
1670 * unused descriptors, at most (txds(MAX_SCATTER) - 1))
1671 *
1672 * ring->queued + txds(data->map->nsegs)
1673 * <= { <0> data->map->nsegs <= MAX_SCATTER }
1674 * ring->queued + txds(MAX_SCATTER)
1675 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) }
1676 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER)
1677 * <= { arithmetic }
1678 * TX_RING_MAX
1679 */
1680
1681 qsel = (qid < EDCA_NUM_AC4) ? RT2860_TX_QSEL_EDCA(2 << 1) : RT2860_TX_QSEL_MGMT(0 << 1);
1682
1683 /* first segment is TXWI + 802.11 header */
1684 txd = &ring->txd[ring->cur];
1685 txd->sdp0 = htole32(data->paddr)((__uint32_t)(data->paddr));
1686 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen)((__uint16_t)(sizeof (struct rt2860_txwi) + hdrlen));
1687 txd->flags = qsel;
1688
1689 /* setup payload segments */
1690 seg = data->map->dm_segs;
1691 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) {
1692 txd->sdp1 = htole32(seg->ds_addr)((__uint32_t)(seg->ds_addr));
1693 txd->sdl1 = htole16(seg->ds_len)((__uint16_t)(seg->ds_len));
1694 seg++;
1695 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT64;
1696 /* grab a new Tx descriptor */
1697 txd = &ring->txd[ring->cur];
1698 txd->sdp0 = htole32(seg->ds_addr)((__uint32_t)(seg->ds_addr));
1699 txd->sdl0 = htole16(seg->ds_len)((__uint16_t)(seg->ds_len));
1700 txd->flags = qsel;
1701 seg++;
1702 }
1703 /* finalize last segment */
1704 if (nsegs > 0) {
1705 txd->sdp1 = htole32(seg->ds_addr)((__uint32_t)(seg->ds_addr));
1706 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1)((__uint16_t)(seg->ds_len | (1 << 14)));
1707 } else {
1708 txd->sdl0 |= htole16(RT2860_TX_LS0)((__uint16_t)((1 << 14)));
1709 txd->sdl1 = 0;
1710 }
1711
1712 /* remove from the free pool and link it into the SW Tx slot */
1713 SLIST_REMOVE_HEAD(&sc->data_pool, next)do { (&sc->data_pool)->slh_first = (&sc->data_pool
)->slh_first->next.sle_next; } while (0)
;
1714 data->m = m;
1715 data->ni = ni;
1716 ring->data[ring->cur] = data;
1717
1718 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), ((caddr_t)txwi - sc->txwi_vaddr), ((sizeof (struct
rt2860_txwi) + sizeof (struct ieee80211_htframe) + sizeof (uint16_t
))), (0x04))
1719 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), ((caddr_t)txwi - sc->txwi_vaddr), ((sizeof (struct
rt2860_txwi) + sizeof (struct ieee80211_htframe) + sizeof (uint16_t
))), (0x04))
1720 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
txwi_map), ((caddr_t)txwi - sc->txwi_vaddr), ((sizeof (struct
rt2860_txwi) + sizeof (struct ieee80211_htframe) + sizeof (uint16_t
))), (0x04))
;
1721 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x04))
1722 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x04))
;
1723 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x04))
1724 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
map), (0), (ring->map->dm_mapsize), (0x04))
;
1725
1726 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1727 qid, txwi->wcid, data->map->dm_nsegs, ridx));
1728
1729 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT64;
1730 ring->queued += 1 + (data->map->dm_nsegs / 2);
1731 if (ring->queued > RT2860_TX_RING_ONEMORE((64 - 1) - (1 + (15 / 2))))
1732 sc->qfullmsk |= 1 << qid;
1733
1734 /* kick Tx */
1735 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0238 + (
qid) * 16))), ((ring->cur))))
;
1736
1737 return 0;
1738}
1739
1740void
1741rt2860_start(struct ifnet *ifp)
1742{
1743 struct rt2860_softc *sc = ifp->if_softc;
1744 struct ieee80211com *ic = &sc->sc_ic;
1745 struct ieee80211_node *ni;
1746 struct mbuf *m;
1747
1748 if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd))
1749 return;
1750
1751 for (;;) {
1752 if (SLIST_EMPTY(&sc->data_pool)(((&sc->data_pool)->slh_first) == ((void *)0)) || sc->qfullmsk != 0) {
1753 ifq_set_oactive(&ifp->if_snd);
1754 break;
1755 }
1756 /* send pending management frames first */
1757 m = mq_dequeue(&ic->ic_mgtq);
1758 if (m != NULL((void *)0)) {
1759 ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie;
1760 goto sendit;
1761 }
1762 if (ic->ic_state != IEEE80211_S_RUN)
1763 break;
1764
1765 /* send buffered frames for power-save mode */
1766 m = mq_dequeue(&ic->ic_pwrsaveq);
1767 if (m != NULL((void *)0)) {
1768 ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie;
1769 goto sendit;
1770 }
1771
1772 /* encapsulate and send data frames */
1773 m = ifq_dequeue(&ifp->if_snd);
1774 if (m == NULL((void *)0))
1775 break;
1776#if NBPFILTER1 > 0
1777 if (ifp->if_bpf != NULL((void *)0))
1778 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
1779#endif
1780 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL((void *)0))
1781 continue;
1782sendit:
1783#if NBPFILTER1 > 0
1784 if (ic->ic_rawbpf != NULL((void *)0))
1785 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT(1 << 1));
1786#endif
1787 if (rt2860_tx(sc, m, ni) != 0) {
1788 m_freem(m);
1789 ieee80211_release_node(ic, ni);
1790 ifp->if_oerrorsif_data.ifi_oerrors++;
1791 continue;
1792 }
1793
1794 sc->sc_tx_timer = 5;
1795 ifp->if_timer = 1;
1796 }
1797}
1798
1799void
1800rt2860_watchdog(struct ifnet *ifp)
1801{
1802 struct rt2860_softc *sc = ifp->if_softc;
1803
1804 ifp->if_timer = 0;
1805
1806 if (sc->sc_tx_timer > 0) {
1807 if (--sc->sc_tx_timer == 0) {
1808 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
1809 rt2860_stop(ifp, 0);
1810 rt2860_init(ifp);
1811 ifp->if_oerrorsif_data.ifi_oerrors++;
1812 return;
1813 }
1814 ifp->if_timer = 1;
1815 }
1816
1817 ieee80211_watchdog(ifp);
1818}
1819
1820int
1821rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1822{
1823 struct rt2860_softc *sc = ifp->if_softc;
1824 struct ieee80211com *ic = &sc->sc_ic;
1825 int s, error = 0;
1826
1827 s = splnet()splraise(0x7);
1828
1829 switch (cmd) {
1830 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12)))
:
1831 ifp->if_flags |= IFF_UP0x1;
1832 /* FALLTHROUGH */
1833 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16)))
:
1834 if (ifp->if_flags & IFF_UP0x1) {
1835 if (!(ifp->if_flags & IFF_RUNNING0x40))
1836 rt2860_init(ifp);
1837 } else {
1838 if (ifp->if_flags & IFF_RUNNING0x40)
1839 rt2860_stop(ifp, 1);
1840 }
1841 break;
1842
1843 case SIOCS80211CHANNEL((unsigned long)0x80000000 | ((sizeof(struct ieee80211chanreq
) & 0x1fff) << 16) | ((('i')) << 8) | ((238))
)
:
1844 /*
1845 * This allows for fast channel switching in monitor mode
1846 * (used by kismet). In IBSS mode, we must explicitly reset
1847 * the interface to generate a new beacon frame.
1848 */
1849 error = ieee80211_ioctl(ifp, cmd, data);
1850 if (error == ENETRESET52 &&
1851 ic->ic_opmode == IEEE80211_M_MONITOR) {
1852 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
1853 (IFF_UP0x1 | IFF_RUNNING0x40))
1854 rt2860_switch_chan(sc, ic->ic_ibss_chan);
1855 error = 0;
1856 }
1857 break;
1858
1859 default:
1860 error = ieee80211_ioctl(ifp, cmd, data);
1861 }
1862
1863 if (error == ENETRESET52) {
1864 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
1865 (IFF_UP0x1 | IFF_RUNNING0x40)) {
1866 rt2860_stop(ifp, 0);
1867 rt2860_init(ifp);
1868 }
1869 error = 0;
1870 }
1871
1872 splx(s)spllower(s);
1873
1874 return error;
1875}
1876
1877/*
1878 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
1879 * We access the BBP through the 8051 microcontroller unit which means that
1880 * the microcode must be loaded first.
1881 */
1882void
1883rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
1884{
1885 int ntries;
1886
1887 for (ntries = 0; ntries < 100; ntries++) {
1888 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7028)))) & RT2860_BBP_CSR_KICK(1 << 17)))
1889 break;
1890 DELAY(1)(*delay_func)(1);
1891 }
1892 if (ntries == 100) {
1893 printf("%s: could not write to BBP through MCU\n",
1894 sc->sc_dev.dv_xname);
1895 return;
1896 }
1897
1898 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
((1 << 19) | (1 << 17) | reg << 8 | val))))
1899 RT2860_BBP_CSR_KICK | reg << 8 | val)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
((1 << 19) | (1 << 17) | reg << 8 | val))))
;
1900 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
1901
1902 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP0x80, 0, 0);
1903 DELAY(1000)(*delay_func)(1000);
1904}
1905
1906uint8_t
1907rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
1908{
1909 uint32_t val;
1910 int ntries;
1911
1912 for (ntries = 0; ntries < 100; ntries++) {
1913 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7028)))) & RT2860_BBP_CSR_KICK(1 << 17)))
1914 break;
1915 DELAY(1)(*delay_func)(1);
1916 }
1917 if (ntries == 100) {
1918 printf("%s: could not read from BBP through MCU\n",
1919 sc->sc_dev.dv_xname);
1920 return 0;
1921 }
1922
1923 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
((1 << 19) | (1 << 17) | (1 << 16) | reg <<
8))))
1924 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
((1 << 19) | (1 << 17) | (1 << 16) | reg <<
8))))
;
1925 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
1926
1927 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP0x80, 0, 0);
1928 DELAY(1000)(*delay_func)(1000);
1929
1930 for (ntries = 0; ntries < 100; ntries++) {
1931 val = RAL_READ(sc, RT2860_H2M_BBPAGENT)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7028))));
1932 if (!(val & RT2860_BBP_CSR_KICK(1 << 17)))
1933 return val & 0xff;
1934 DELAY(1)(*delay_func)(1);
1935 }
1936 printf("%s: could not read from BBP through MCU\n",
1937 sc->sc_dev.dv_xname);
1938
1939 return 0;
1940}
1941
1942/*
1943 * Write to one of the 4 programmable 24-bit RF registers.
1944 */
1945void
1946rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
1947{
1948 uint32_t tmp;
1949 int ntries;
1950
1951 for (ntries = 0; ntries < 100; ntries++) {
1952 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1020)))) & RT2860_RF_REG_CTRL(1U << 31)))
1953 break;
1954 DELAY(1)(*delay_func)(1);
1955 }
1956 if (ntries == 100) {
1957 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname);
1958 return;
1959 }
1960
1961 /* RF registers are 24-bit on the RT2860 */
1962 tmp = RT2860_RF_REG_CTRL(1U << 31) | 24 << RT2860_RF_REG_WIDTH_SHIFT24 |
1963 (val & 0x3fffff) << 2 | (reg & 3);
1964 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1020)), (
(tmp))))
;
1965}
1966
1967uint8_t
1968rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
1969{
1970 uint32_t tmp;
1971 int ntries;
1972
1973 for (ntries = 0; ntries < 100; ntries++) {
1974 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0500)))) & RT3070_RF_KICK(1 << 17)))
1975 break;
1976 DELAY(1)(*delay_func)(1);
1977 }
1978 if (ntries == 100) {
1979 printf("%s: could not read RF register\n",
1980 sc->sc_dev.dv_xname);
1981 return 0xff;
1982 }
1983 tmp = RT3070_RF_KICK(1 << 17) | reg << 8;
1984 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0500)), (
(tmp))))
;
1985
1986 for (ntries = 0; ntries < 100; ntries++) {
1987 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0500))));
1988 if (!(tmp & RT3070_RF_KICK(1 << 17)))
1989 break;
1990 DELAY(1)(*delay_func)(1);
1991 }
1992 if (ntries == 100) {
1993 printf("%s: could not read RF register\n",
1994 sc->sc_dev.dv_xname);
1995 return 0xff;
1996 }
1997 return tmp & 0xff;
1998}
1999
2000void
2001rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2002{
2003 uint32_t tmp;
2004 int ntries;
2005
2006 for (ntries = 0; ntries < 10; ntries++) {
2007 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0500)))) & RT3070_RF_KICK(1 << 17)))
2008 break;
2009 DELAY(10)(*delay_func)(10);
2010 }
2011 if (ntries == 10) {
2012 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname);
2013 return;
2014 }
2015
2016 tmp = RT3070_RF_WRITE(1 << 16) | RT3070_RF_KICK(1 << 17) | reg << 8 | val;
2017 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0500)), (
(tmp))))
;
2018}
2019
2020/*
2021 * Send a command to the 8051 microcontroller unit.
2022 */
2023int
2024rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2025{
2026 int slot, ntries;
2027 uint32_t tmp;
2028 uint8_t cid;
2029
2030 for (ntries = 0; ntries < 100; ntries++) {
2031 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7010)))) & RT2860_H2M_BUSY(1 << 24)))
2032 break;
2033 DELAY(2)(*delay_func)(2);
2034 }
2035 if (ntries == 100)
2036 return EIO5;
2037
2038 cid = wait ? cmd : RT2860_TOKEN_NO_INTR0xff;
2039 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7010)), (
((1 << 24) | cid << 16 | arg))))
;
2040 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
2041 RAL_WRITE(sc, RT2860_HOST_CMD, cmd)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0404)), (
(cmd))))
;
2042
2043 if (!wait)
2044 return 0;
2045 /* wait for the command to complete */
2046 for (ntries = 0; ntries < 200; ntries++) {
2047 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7014))));
2048 /* find the command slot */
2049 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2050 if ((tmp & 0xff) == cid)
2051 break;
2052 if (slot < 4)
2053 break;
2054 DELAY(100)(*delay_func)(100);
2055 }
2056 if (ntries == 200) {
2057 /* clear command and status */
2058 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x701c)), (
(0xffffffff))))
;
2059 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7014)), (
(0xffffffff))))
;
2060 return ETIMEDOUT60;
2061 }
2062 /* get command status (1 means success) */
2063 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x701c))));
2064 tmp = (tmp >> (slot * 8)) & 0xff;
2065 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2066 cmd, slot, tmp));
2067 /* clear command and status */
2068 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x701c)), (
(0xffffffff))))
;
2069 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7014)), (
(0xffffffff))))
;
2070 return (tmp == 1) ? 0 : EIO5;
2071}
2072
2073void
2074rt2860_enable_mrr(struct rt2860_softc *sc)
2075{
2076#define CCK(mcs) (mcs)
2077#define OFDM(mcs) (1 << 3 | (mcs))
2078 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2079 OFDM(6) << 28 | /* 54->48 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2080 OFDM(5) << 24 | /* 48->36 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2081 OFDM(4) << 20 | /* 36->24 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2082 OFDM(3) << 16 | /* 24->18 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2083 OFDM(2) << 12 | /* 18->12 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2084 OFDM(1) << 8 | /* 12-> 9 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2085 OFDM(0) << 4 | /* 9-> 6 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
2086 OFDM(0))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x135c)), (
(OFDM(6) << 28 | OFDM(5) << 24 | OFDM(4) <<
20 | OFDM(3) << 16 | OFDM(2) << 12 | OFDM(1) <<
8 | OFDM(0) << 4 | OFDM(0)))))
; /* 6-> 6 */
2087
2088 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1360)), (
(CCK(2) << 12 | CCK(1) << 8 | CCK(0) << 4 |
CCK(0)))))
2089 CCK(2) << 12 | /* 11->5.5 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1360)), (
(CCK(2) << 12 | CCK(1) << 8 | CCK(0) << 4 |
CCK(0)))))
2090 CCK(1) << 8 | /* 5.5-> 2 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1360)), (
(CCK(2) << 12 | CCK(1) << 8 | CCK(0) << 4 |
CCK(0)))))
2091 CCK(0) << 4 | /* 2-> 1 */(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1360)), (
(CCK(2) << 12 | CCK(1) << 8 | CCK(0) << 4 |
CCK(0)))))
2092 CCK(0))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1360)), (
(CCK(2) << 12 | CCK(1) << 8 | CCK(0) << 4 |
CCK(0)))))
; /* 1-> 1 */
2093#undef OFDM
2094#undef CCK
2095}
2096
2097void
2098rt2860_set_txpreamble(struct rt2860_softc *sc)
2099{
2100 uint32_t tmp;
2101
2102 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1404))));
2103 tmp &= ~RT2860_CCK_SHORT_EN(1 << 4);
2104 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE0x00040000)
2105 tmp |= RT2860_CCK_SHORT_EN(1 << 4);
2106 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1404)), (
(tmp))))
;
2107}
2108
2109void
2110rt2860_set_basicrates(struct rt2860_softc *sc)
2111{
2112 struct ieee80211com *ic = &sc->sc_ic;
2113
2114 /* set basic rates mask */
2115 if (ic->ic_curmode == IEEE80211_MODE_11B)
2116 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1408)), (
(0x003))))
;
2117 else if (ic->ic_curmode == IEEE80211_MODE_11A)
2118 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1408)), (
(0x150))))
;
2119 else /* 11g */
2120 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1408)), (
(0x15f))))
;
2121}
2122
2123void
2124rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2125{
2126 uint32_t tmp;
2127 uint8_t agc;
2128
2129 /* Wait for BBP to settle */
2130 DELAY(1000)(*delay_func)(1000);
2131
2132 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2133 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2134 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2135 rt2860_mcu_bbp_write(sc, 86, 0x00);
2136
2137 if (group == 0) {
2138 if (sc->ext_2ghz_lna) {
2139 rt2860_mcu_bbp_write(sc, 82, 0x62);
2140 rt2860_mcu_bbp_write(sc, 75, 0x46);
2141 } else {
2142 rt2860_mcu_bbp_write(sc, 82, 0x84);
2143 rt2860_mcu_bbp_write(sc, 75, 0x50);
2144 }
2145 } else {
2146 if (sc->mac_ver == 0x3572)
2147 rt2860_mcu_bbp_write(sc, 82, 0x94);
2148 else
2149 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2150
2151 if (sc->ext_5ghz_lna)
2152 rt2860_mcu_bbp_write(sc, 75, 0x46);
2153 else
2154 rt2860_mcu_bbp_write(sc, 75, 0x50);
2155 }
2156
2157 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x132c))));
2158 tmp &= ~(RT2860_5G_BAND_SEL_N(1 << 2) | RT2860_5G_BAND_SEL_P(1 << 1));
2159 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N(1 << 2) : RT2860_5G_BAND_SEL_P(1 << 1);
2160 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x132c)), (
(tmp))))
;
2161
2162 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2163 tmp = RT2860_RFTR_EN(1U << 16) | RT2860_TRSW_EN(1U << 18) | RT2860_LNA_PE0_EN((1U << 8) | (1U << 9));
2164 if (sc->nrxchains > 1)
2165 tmp |= RT2860_LNA_PE1_EN((1U << 10) | (1U << 11));
2166 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2167 tmp |= RT3593_LNA_PE2_EN((1U << 28) | (1U << 29));
2168 if (group == 0) { /* 2GHz */
2169 tmp |= RT2860_PA_PE_G0_EN(1U << 1);
2170 if (sc->ntxchains > 1)
2171 tmp |= RT2860_PA_PE_G1_EN(1U << 3);
2172 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2173 tmp |= RT3593_PA_PE_G2_EN(1U << 25);
2174 } else { /* 5GHz */
2175 tmp |= RT2860_PA_PE_A0_EN(1U << 0);
2176 if (sc->ntxchains > 1)
2177 tmp |= RT2860_PA_PE_A1_EN(1U << 2);
2178 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2179 tmp |= RT3593_PA_PE_A2_EN(1U << 24);
2180 }
2181 if (sc->mac_ver == 0x3572) {
2182 rt3090_rf_write(sc, 8, 0x00);
2183 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1328)), (
(tmp))))
;
2184 rt3090_rf_write(sc, 8, 0x80);
2185 } else
2186 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1328)), (
(tmp))))
;
2187
2188 if (sc->mac_ver == 0x3593) {
2189 tmp = RAL_READ(sc, RT2860_GPIO_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0228))));
2190 if (sc->sc_flags & RT2860_PCIE(1 << 2)) {
2191 tmp &= ~0x01010000;
2192 if (group == 0)
2193 tmp |= 0x00010000;
2194 } else {
2195 tmp &= ~0x00008080;
2196 if (group == 0)
2197 tmp |= 0x00000080;
2198 }
2199 tmp = (tmp & ~0x00001000) | 0x00000010;
2200 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0228)), (
(tmp))))
;
2201 }
2202
2203 /* set initial AGC value */
2204 if (group == 0) { /* 2GHz band */
2205 if (sc->mac_ver >= 0x3071)
2206 agc = 0x1c + sc->lna[0] * 2;
2207 else
2208 agc = 0x2e + sc->lna[0];
2209 } else { /* 5GHz band */
2210 if (sc->mac_ver == 0x3572)
2211 agc = 0x22 + (sc->lna[group] * 5) / 3;
2212 else
2213 agc = 0x32 + (sc->lna[group] * 5) / 3;
2214 }
2215 rt2860_mcu_bbp_write(sc, 66, agc);
2216
2217 DELAY(1000)(*delay_func)(1000);
2218}
2219
2220void
2221rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2222{
2223 const struct rfprog *rfprog = rt2860_rf2850;
2224 uint32_t r2, r3, r4;
2225 int8_t txpow1, txpow2;
2226 u_int i;
2227
2228 /* find the settings for this channel (we know it exists) */
2229 for (i = 0; rfprog[i].chan != chan; i++);
2230
2231 r2 = rfprog[i].r2;
2232 if (sc->ntxchains == 1)
2233 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2234 if (sc->nrxchains == 1)
2235 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2236 else if (sc->nrxchains == 2)
2237 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2238
2239 /* use Tx power values from EEPROM */
2240 txpow1 = sc->txpow1[i];
2241 txpow2 = sc->txpow2[i];
2242 if (chan > 14) {
2243 if (txpow1 >= 0)
2244 txpow1 = txpow1 << 1 | 1;
2245 else
2246 txpow1 = (7 + txpow1) << 1;
2247 if (txpow2 >= 0)
2248 txpow2 = txpow2 << 1 | 1;
2249 else
2250 txpow2 = (7 + txpow2) << 1;
2251 }
2252 r3 = rfprog[i].r3 | txpow1 << 7;
2253 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2254
2255 rt2860_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2256 rt2860_rf_write(sc, RT2860_RF22, r2);
2257 rt2860_rf_write(sc, RT2860_RF31, r3);
2258 rt2860_rf_write(sc, RT2860_RF43, r4);
2259
2260 DELAY(200)(*delay_func)(200);
2261
2262 rt2860_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2263 rt2860_rf_write(sc, RT2860_RF22, r2);
2264 rt2860_rf_write(sc, RT2860_RF31, r3 | 1);
2265 rt2860_rf_write(sc, RT2860_RF43, r4);
2266
2267 DELAY(200)(*delay_func)(200);
2268
2269 rt2860_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2270 rt2860_rf_write(sc, RT2860_RF22, r2);
2271 rt2860_rf_write(sc, RT2860_RF31, r3);
2272 rt2860_rf_write(sc, RT2860_RF43, r4);
2273}
2274
2275void
2276rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2277{
2278 int8_t txpow1, txpow2;
2279 uint8_t rf;
2280 int i;
2281
2282 KASSERT(chan >= 1 && chan <= 14)((chan >= 1 && chan <= 14) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/ic/rt2860.c", 2282, "chan >= 1 && chan <= 14"
))
; /* RT3090 is 2GHz only */
2283
2284 /* find the settings for this channel (we know it exists) */
2285 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2286
2287 /* use Tx power values from EEPROM */
2288 txpow1 = sc->txpow1[i];
2289 txpow2 = sc->txpow2[i];
2290
2291 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2292 rf = rt3090_rf_read(sc, 3);
2293 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2294 rt3090_rf_write(sc, 3, rf);
2295 rf = rt3090_rf_read(sc, 6);
2296 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2297 rt3090_rf_write(sc, 6, rf);
2298
2299 /* set Tx0 power */
2300 rf = rt3090_rf_read(sc, 12);
2301 rf = (rf & ~0x1f) | txpow1;
2302 rt3090_rf_write(sc, 12, rf);
2303
2304 /* set Tx1 power */
2305 rf = rt3090_rf_read(sc, 13);
2306 rf = (rf & ~0x1f) | txpow2;
2307 rt3090_rf_write(sc, 13, rf);
2308
2309 rf = rt3090_rf_read(sc, 1);
2310 rf &= ~0xfc;
2311 if (sc->ntxchains == 1)
2312 rf |= RT3070_TX1_PD(1 << 5) | RT3070_TX2_PD(1 << 7);
2313 else if (sc->ntxchains == 2)
2314 rf |= RT3070_TX2_PD(1 << 7);
2315 if (sc->nrxchains == 1)
2316 rf |= RT3070_RX1_PD(1 << 4) | RT3070_RX2_PD(1 << 6);
2317 else if (sc->nrxchains == 2)
2318 rf |= RT3070_RX2_PD(1 << 6);
2319 rt3090_rf_write(sc, 1, rf);
2320
2321 /* set RF offset */
2322 rf = rt3090_rf_read(sc, 23);
2323 rf = (rf & ~0x7f) | sc->freq;
2324 rt3090_rf_write(sc, 23, rf);
2325
2326 /* program RF filter */
2327 rf = rt3090_rf_read(sc, 24); /* Tx */
2328 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2329 rt3090_rf_write(sc, 24, rf);
2330 rf = rt3090_rf_read(sc, 31); /* Rx */
2331 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2332 rt3090_rf_write(sc, 31, rf);
2333
2334 /* enable RF tuning */
2335 rf = rt3090_rf_read(sc, 7);
2336 rt3090_rf_write(sc, 7, rf | RT3070_TUNE(1 << 0));
2337}
2338
2339void
2340rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2341{
2342 uint8_t h20mhz, rf, tmp;
2343 int8_t txpow1, txpow2;
2344 int i;
2345
2346 /* RT5390 is 2GHz only */
2347 KASSERT(chan >= 1 && chan <= 14)((chan >= 1 && chan <= 14) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/ic/rt2860.c", 2347, "chan >= 1 && chan <= 14"
))
;
2348
2349 /* find the settings for this channel (we know it exists) */
2350 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2351
2352 /* use Tx power values from EEPROM */
2353 txpow1 = sc->txpow1[i];
2354 txpow2 = sc->txpow2[i];
2355
2356 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2357 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2358 rf = rt3090_rf_read(sc, 11);
2359 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2360 rt3090_rf_write(sc, 11, rf);
2361
2362 rf = rt3090_rf_read(sc, 49);
2363 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2364 /* the valid range of the RF R49 is 0x00~0x27 */
2365 if ((rf & 0x3f) > 0x27)
2366 rf = (rf & ~0x3f) | 0x27;
2367 rt3090_rf_write(sc, 49, rf);
2368 if (sc->mac_ver == 0x5392) {
2369 rf = rt3090_rf_read(sc, 50);
2370 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2371 /* the valid range of the RF R50 is 0x00~0x27 */
2372 if ((rf & 0x3f) > 0x27)
2373 rf = (rf & ~0x3f) | 0x27;
2374 rt3090_rf_write(sc, 50, rf);
2375 }
2376
2377 rf = rt3090_rf_read(sc, 1);
2378 rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3);
2379 if (sc->mac_ver == 0x5392)
2380 rf |= RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5);
2381 rt3090_rf_write(sc, 1, rf);
2382
2383 rf = rt3090_rf_read(sc, 2);
2384 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL(1 << 7));
2385 DELAY(1000)(*delay_func)(1000);
2386 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL(1 << 7));
2387
2388 rf = rt3090_rf_read(sc, 17);
2389 tmp = rf;
2390 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2391 rf = MIN(rf, 0x5f)(((rf)<(0x5f))?(rf):(0x5f));
2392 if (tmp != rf)
2393 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2394
2395 if (sc->mac_ver == 0x5390) {
2396 if (chan <= 4)
2397 rf = 0x73;
2398 else if (chan >= 5 && chan <= 6)
2399 rf = 0x63;
2400 else if (chan >= 7 && chan <= 10)
2401 rf = 0x53;
2402 else
2403 rf = 43;
2404 rt3090_rf_write(sc, 55, rf);
2405
2406 if (chan == 1)
2407 rf = 0x0c;
2408 else if (chan == 2)
2409 rf = 0x0b;
2410 else if (chan == 3)
2411 rf = 0x0a;
2412 else if (chan >= 4 && chan <= 6)
2413 rf = 0x09;
2414 else if (chan >= 7 && chan <= 12)
2415 rf = 0x08;
2416 else if (chan == 13)
2417 rf = 0x07;
2418 else
2419 rf = 0x06;
2420 rt3090_rf_write(sc, 59, rf);
2421 } else if (sc->mac_ver == 0x3290) {
2422 if (chan == 6)
2423 rt2860_mcu_bbp_write(sc, 68, 0x0c);
2424 else
2425 rt2860_mcu_bbp_write(sc, 68, 0x0b);
2426
2427 if (chan >= 1 && chan < 6)
2428 rf = 0x0f;
2429 else if (chan >= 7 && chan <= 11)
2430 rf = 0x0e;
2431 else if (chan >= 12 && chan <= 14)
2432 rf = 0x0d;
2433 rt3090_rf_write(sc, 59, rf);
2434 }
2435
2436 /* Tx/Rx h20M */
2437 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2438 rf = rt3090_rf_read(sc, 30);
2439 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2440 rt3090_rf_write(sc, 30, rf);
2441
2442 /* Rx BB filter VCM */
2443 rf = rt3090_rf_read(sc, 30);
2444 rf = (rf & ~0x18) | 0x10;
2445 rt3090_rf_write(sc, 30, rf);
2446
2447 /* Initiate VCO calibration. */
2448 rf = rt3090_rf_read(sc, 3);
2449 rf |= RT3593_VCOCAL(1 << 7);
2450 rt3090_rf_write(sc, 3, rf);
2451}
2452
2453int
2454rt3090_rf_init(struct rt2860_softc *sc)
2455{
2456 uint32_t tmp;
2457 uint8_t rf, bbp;
2458 int i;
2459
2460 rf = rt3090_rf_read(sc, 30);
2461 /* toggle RF R30 bit 7 */
2462 rt3090_rf_write(sc, 30, rf | 0x80);
2463 DELAY(1000)(*delay_func)(1000);
2464 rt3090_rf_write(sc, 30, rf & ~0x80);
2465
2466 tmp = RAL_READ(sc, RT3070_LDO_CFG0)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x05d4))));
2467 tmp &= ~0x1f000000;
2468 if (sc->patch_dac && sc->mac_rev < 0x0211)
2469 tmp |= 0x0d000000; /* 1.35V */
2470 else
2471 tmp |= 0x01000000; /* 1.2V */
2472 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x05d4)), (
(tmp))))
;
2473
2474 /* patch LNA_PE_G1 */
2475 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x05dc))));
2476 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x05dc)), (
(tmp & ~0x20))))
;
2477
2478 /* initialize RF registers to default value */
2479 if (sc->mac_ver == 0x3572) {
2480 for (i = 0; i < nitems(rt3572_def_rf)(sizeof((rt3572_def_rf)) / sizeof((rt3572_def_rf)[0])); i++) {
2481 rt3090_rf_write(sc, rt3572_def_rf[i].reg,
2482 rt3572_def_rf[i].val);
2483 }
2484 } else {
2485 for (i = 0; i < nitems(rt3090_def_rf)(sizeof((rt3090_def_rf)) / sizeof((rt3090_def_rf)[0])); i++) {
2486 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2487 rt3090_def_rf[i].val);
2488 }
2489 }
2490
2491 /* select 20MHz bandwidth */
2492 rt3090_rf_write(sc, 31, 0x14);
2493
2494 rf = rt3090_rf_read(sc, 6);
2495 rt3090_rf_write(sc, 6, rf | 0x40);
2496
2497 if (sc->mac_ver != 0x3593) {
2498 /* calibrate filter for 20MHz bandwidth */
2499 sc->rf24_20mhz = 0x1f; /* default value */
2500 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2501
2502 /* select 40MHz bandwidth */
2503 bbp = rt2860_mcu_bbp_read(sc, 4);
2504 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2505 rf = rt3090_rf_read(sc, 31);
2506 rt3090_rf_write(sc, 31, rf | 0x20);
2507
2508 /* calibrate filter for 40MHz bandwidth */
2509 sc->rf24_40mhz = 0x2f; /* default value */
2510 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2511
2512 /* go back to 20MHz bandwidth */
2513 bbp = rt2860_mcu_bbp_read(sc, 4);
2514 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2515 }
2516 if (sc->mac_rev < 0x0211)
2517 rt3090_rf_write(sc, 27, 0x03);
2518
2519 tmp = RAL_READ(sc, RT3070_OPT_14)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0114))));
2520 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0114)), (
(tmp | 1))))
;
2521
2522 if (sc->rf_rev == RT3070_RF_30200x0005)
2523 rt3090_set_rx_antenna(sc, 0);
2524
2525 bbp = rt2860_mcu_bbp_read(sc, 138);
2526 if (sc->mac_ver == 0x3593) {
2527 if (sc->ntxchains == 1)
2528 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2529 else if (sc->ntxchains == 2)
2530 bbp |= 0x40; /* turn off DAC2 */
2531 if (sc->nrxchains == 1)
2532 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2533 else if (sc->nrxchains == 2)
2534 bbp &= ~0x04; /* turn off ADC2 */
2535 } else {
2536 if (sc->ntxchains == 1)
2537 bbp |= 0x20; /* turn off DAC1 */
2538 if (sc->nrxchains == 1)
2539 bbp &= ~0x02; /* turn off ADC1 */
2540 }
2541 rt2860_mcu_bbp_write(sc, 138, bbp);
2542
2543 rf = rt3090_rf_read(sc, 1);
2544 rf &= ~(RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3));
2545 rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5);
2546 rt3090_rf_write(sc, 1, rf);
2547
2548 rf = rt3090_rf_read(sc, 15);
2549 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2(1 << 3));
2550
2551 rf = rt3090_rf_read(sc, 17);
2552 rf &= ~RT3070_TX_LO1(1 << 3);
2553 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2554 rf |= 0x20; /* fix for long range Rx issue */
2555 if (sc->txmixgain_2ghz >= 2)
2556 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2557 rt3090_rf_write(sc, 17, rf);
2558
2559 rf = rt3090_rf_read(sc, 20);
2560 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1(1 << 3));
2561
2562 rf = rt3090_rf_read(sc, 21);
2563 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2(1 << 3));
2564
2565 return 0;
2566}
2567
2568void
2569rt5390_rf_init(struct rt2860_softc *sc)
2570{
2571 uint8_t rf, bbp;
2572 int i;
2573
2574 rf = rt3090_rf_read(sc, 2);
2575 /* Toggle RF R2 bit 7. */
2576 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL(1 << 7));
2577 DELAY(1000)(*delay_func)(1000);
2578 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL(1 << 7));
2579
2580 /* Initialize RF registers to default value. */
2581 if (sc->mac_ver == 0x5392) {
2582 for (i = 0; i < nitems(rt5392_def_rf)(sizeof((rt5392_def_rf)) / sizeof((rt5392_def_rf)[0])); i++) {
2583 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2584 rt5392_def_rf[i].val);
2585 }
2586 } else if (sc->mac_ver == 0x3290) {
2587 for (i = 0; i < nitems(rt3290_def_rf)(sizeof((rt3290_def_rf)) / sizeof((rt3290_def_rf)[0])); i++) {
2588 rt3090_rf_write(sc, rt3290_def_rf[i].reg,
2589 rt3290_def_rf[i].val);
2590 }
2591 } else {
2592 for (i = 0; i < nitems(rt5390_def_rf)(sizeof((rt5390_def_rf)) / sizeof((rt5390_def_rf)[0])); i++) {
2593 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2594 rt5390_def_rf[i].val);
2595 }
2596 }
2597
2598 sc->rf24_20mhz = 0x1f;
2599 sc->rf24_40mhz = 0x2f;
2600
2601 if (sc->mac_rev < 0x0211)
2602 rt3090_rf_write(sc, 27, 0x03);
2603
2604 /* Set led open drain enable. */
2605 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0114)), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0114)))) |
1))))
;
2606
2607 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1334)), (
(0))))
;
2608 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1338)), (
(0))))
;
2609
2610 if (sc->mac_ver == 0x3290 ||
2611 sc->mac_ver == 0x5390)
2612 rt3090_set_rx_antenna(sc, 0);
2613
2614 /* Patch RSSI inaccurate issue. */
2615 rt2860_mcu_bbp_write(sc, 79, 0x13);
2616 rt2860_mcu_bbp_write(sc, 80, 0x05);
2617 rt2860_mcu_bbp_write(sc, 81, 0x33);
2618
2619 /* Enable DC filter. */
2620 if (sc->mac_rev >= 0x0211 ||
2621 sc->mac_ver == 0x3290)
2622 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2623
2624 bbp = rt2860_mcu_bbp_read(sc, 138);
2625 if (sc->ntxchains == 1)
2626 bbp |= 0x20; /* Turn off DAC1. */
2627 if (sc->nrxchains == 1)
2628 bbp &= ~0x02; /* Turn off ADC1. */
2629 rt2860_mcu_bbp_write(sc, 138, bbp);
2630
2631 /* Enable RX LO1 and LO2. */
2632 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1(1 << 5));
2633 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2(1 << 7));
2634
2635 /* Avoid data lost and CRC error. */
2636 rt2860_mcu_bbp_write(sc, 4,
2637 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL(1 << 6));
2638
2639 rf = rt3090_rf_read(sc, 30);
2640 rf = (rf & ~0x18) | 0x10;
2641 rt3090_rf_write(sc, 30, rf);
2642
2643 /* Disable hardware antenna diversity. */
2644 if (sc->mac_ver == 0x5390)
2645 rt2860_mcu_bbp_write(sc, 154, 0);
2646}
2647
2648void
2649rt3090_rf_wakeup(struct rt2860_softc *sc)
2650{
2651 uint32_t tmp;
2652 uint8_t rf;
2653
2654 if (sc->mac_ver == 0x3593) {
2655 /* enable VCO */
2656 rf = rt3090_rf_read(sc, 1);
2657 rt3090_rf_write(sc, 1, rf | RT3593_VCO(1 << 0));
2658
2659 /* initiate VCO calibration */
2660 rf = rt3090_rf_read(sc, 3);
2661 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL(1 << 7));
2662
2663 /* enable VCO bias current control */
2664 rf = rt3090_rf_read(sc, 6);
2665 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC(1 << 6));
2666
2667 /* initiate res calibration */
2668 rf = rt3090_rf_read(sc, 2);
2669 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL(1 << 7));
2670
2671 /* set reference current control to 0.33 mA */
2672 rf = rt3090_rf_read(sc, 22);
2673 rf &= ~RT3593_CP_IC_MASK0xe0;
2674 rf |= 1 << RT3593_CP_IC_SHIFT5;
2675 rt3090_rf_write(sc, 22, rf);
2676
2677 /* enable RX CTB */
2678 rf = rt3090_rf_read(sc, 46);
2679 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB(1 << 5));
2680
2681 rf = rt3090_rf_read(sc, 20);
2682 rf &= ~(RT3593_LDO_RF_VC_MASK0xe0 | RT3593_LDO_PLL_VC_MASK0x0e);
2683 rt3090_rf_write(sc, 20, rf);
2684 } else {
2685 /* enable RF block */
2686 rf = rt3090_rf_read(sc, 1);
2687 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK(1 << 0));
2688
2689 /* enable VCO bias current control */
2690 rf = rt3090_rf_read(sc, 7);
2691 rt3090_rf_write(sc, 7, rf | 0x30);
2692
2693 rf = rt3090_rf_read(sc, 9);
2694 rt3090_rf_write(sc, 9, rf | 0x0e);
2695
2696 /* enable RX CTB */
2697 rf = rt3090_rf_read(sc, 21);
2698 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB(1 << 7));
2699
2700 /* fix Tx to Rx IQ glitch by raising RF voltage */
2701 rf = rt3090_rf_read(sc, 27);
2702 rf &= ~0x77;
2703 if (sc->mac_rev < 0x0211)
2704 rf |= 0x03;
2705 rt3090_rf_write(sc, 27, rf);
2706 }
2707 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2708 tmp = RAL_READ(sc, RT3070_LDO_CFG0)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x05d4))));
2709 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2710 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x05d4)), (
(tmp))))
;
2711 }
2712}
2713
2714void
2715rt5390_rf_wakeup(struct rt2860_softc *sc)
2716{
2717 uint32_t tmp;
2718 uint8_t rf;
2719
2720 rf = rt3090_rf_read(sc, 1);
2721 rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) |
2722 RT3070_TX0_PD(1 << 3);
2723 if (sc->mac_ver == 0x5392)
2724 rf |= RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5);
2725 rt3090_rf_write(sc, 1, rf);
2726
2727 rf = rt3090_rf_read(sc, 6);
2728 rf |= RT3593_VCO_IC(1 << 6) | RT3593_VCOCAL(1 << 7);
2729 if (sc->mac_ver == 0x5390)
2730 rf &= ~RT3593_VCO_IC(1 << 6);
2731 rt3090_rf_write(sc, 6, rf);
2732
2733 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL(1 << 7));
2734
2735 rf = rt3090_rf_read(sc, 22);
2736 rf = (rf & ~0xe0) | 0x20;
2737 rt3090_rf_write(sc, 22, rf);
2738
2739 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB(1 << 6));
2740 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2741 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL(1 << 7));
2742
2743 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2744 tmp = RAL_READ(sc, RT3070_LDO_CFG0)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x05d4))));
2745 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2746 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x05d4)), (
(tmp))))
;
2747 }
2748}
2749
2750int
2751rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2752 uint8_t *val)
2753{
2754 uint8_t rf22, rf24;
2755 uint8_t bbp55_pb, bbp55_sb, delta;
2756 int ntries;
2757
2758 /* program filter */
2759 rf24 = rt3090_rf_read(sc, 24);
2760 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2761 rt3090_rf_write(sc, 24, rf24);
2762
2763 /* enable baseband loopback mode */
2764 rf22 = rt3090_rf_read(sc, 22);
2765 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK(1 << 0));
2766
2767 /* set power and frequency of passband test tone */
2768 rt2860_mcu_bbp_write(sc, 24, 0x00);
2769 for (ntries = 0; ntries < 100; ntries++) {
2770 /* transmit test tone */
2771 rt2860_mcu_bbp_write(sc, 25, 0x90);
2772 DELAY(1000)(*delay_func)(1000);
2773 /* read received power */
2774 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
2775 if (bbp55_pb != 0)
2776 break;
2777 }
2778 if (ntries == 100)
2779 return ETIMEDOUT60;
2780
2781 /* set power and frequency of stopband test tone */
2782 rt2860_mcu_bbp_write(sc, 24, 0x06);
2783 for (ntries = 0; ntries < 100; ntries++) {
2784 /* transmit test tone */
2785 rt2860_mcu_bbp_write(sc, 25, 0x90);
2786 DELAY(1000)(*delay_func)(1000);
2787 /* read received power */
2788 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
2789
2790 delta = bbp55_pb - bbp55_sb;
2791 if (delta > target)
2792 break;
2793
2794 /* reprogram filter */
2795 rf24++;
2796 rt3090_rf_write(sc, 24, rf24);
2797 }
2798 if (ntries < 100) {
2799 if (rf24 != init)
2800 rf24--; /* backtrack */
2801 *val = rf24;
2802 rt3090_rf_write(sc, 24, rf24);
2803 }
2804
2805 /* restore initial state */
2806 rt2860_mcu_bbp_write(sc, 24, 0x00);
2807
2808 /* disable baseband loopback mode */
2809 rf22 = rt3090_rf_read(sc, 22);
2810 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK(1 << 0));
2811
2812 return 0;
2813}
2814
2815void
2816rt3090_rf_setup(struct rt2860_softc *sc)
2817{
2818 uint8_t bbp;
2819 int i;
2820
2821 if (sc->mac_rev >= 0x0211) {
2822 /* enable DC filter */
2823 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2824
2825 /* improve power consumption */
2826 bbp = rt2860_mcu_bbp_read(sc, 31);
2827 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
2828 }
2829
2830 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1334)), (
(0))))
;
2831 if (sc->mac_rev < 0x0211) {
2832 RAL_WRITE(sc, RT2860_TX_SW_CFG2,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1338)), (
(sc->patch_dac ? 0x2c : 0x0f))))
2833 sc->patch_dac ? 0x2c : 0x0f)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1338)), (
(sc->patch_dac ? 0x2c : 0x0f))))
;
2834 } else
2835 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1338)), (
(0))))
;
2836
2837 /* initialize RF registers from ROM */
2838 if (sc->mac_ver < 0x5390) {
2839 for (i = 0; i < 10; i++) {
2840 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
2841 continue;
2842 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
2843 }
2844 }
2845}
2846
2847void
2848rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2849{
2850 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS0x50,
2851 which | (sc->leds & 0x7f), 0);
2852}
2853
2854/*
2855 * Hardware has a general-purpose programmable timer interrupt that can
2856 * periodically raise MAC_INT_4.
2857 */
2858void
2859rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
2860{
2861 uint32_t tmp;
2862
2863 /* disable GP timer before reprogramming it */
2864 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x112c))));
2865 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x112c)), (
(tmp & ~(1 << 1)))))
;
2866
2867 if (ms == 0)
2868 return;
2869
2870 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1128))));
2871 ms *= 16; /* Unit: 64us */
2872 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT16;
2873 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1128)), (
(tmp))))
;
2874
2875 /* enable GP timer */
2876 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x112c))));
2877 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x112c)), (
(tmp | (1 << 1)))))
;
2878}
2879
2880void
2881rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
2882{
2883 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1010)), (
(bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid
[3] << 24))))
2884 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1010)), (
(bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid
[3] << 24))))
;
2885 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1014)), (
(bssid[4] | bssid[5] << 8))))
2886 bssid[4] | bssid[5] << 8)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1014)), (
(bssid[4] | bssid[5] << 8))))
;
2887}
2888
2889void
2890rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
2891{
2892 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1008)), (
(addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3]
<< 24))))
2893 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1008)), (
(addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3]
<< 24))))
;
2894 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x100c)), (
(addr[4] | addr[5] << 8 | 0xff << 16))))
2895 addr[4] | addr[5] << 8 | 0xff << 16)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x100c)), (
(addr[4] | addr[5] << 8 | 0xff << 16))))
;
2896}
2897
2898void
2899rt2860_updateslot(struct ieee80211com *ic)
2900{
2901 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2902 uint32_t tmp;
2903
2904 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1104))));
2905 tmp &= ~0xff;
2906 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT0x00020000) ?
2907 IEEE80211_DUR_DS_SHSLOT9 : IEEE80211_DUR_DS_SLOT20;
2908 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1104)), (
(tmp))))
;
2909}
2910
2911void
2912rt2860_updateprot(struct ieee80211com *ic)
2913{
2914 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2915 uint32_t tmp;
2916
2917 tmp = RT2860_RTSTH_EN(1 << 26) | RT2860_PROT_NAV_SHORT(1 << 18) | RT2860_TXOP_ALLOW_ALL(0x3f << 20);
2918 /* setup protection frame rate (MCS code) */
2919 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
2920 rt2860_rates[RT2860_RIDX_OFDM64].mcs :
2921 rt2860_rates[RT2860_RIDX_CCK113].mcs;
2922
2923 /* CCK frames don't require protection */
2924 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1364)), (
(tmp))))
;
2925
2926 if (ic->ic_flags & IEEE80211_F_USEPROT0x00100000) {
2927 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2928 tmp |= RT2860_PROT_CTRL_RTS_CTS(1 << 16);
2929 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2930 tmp |= RT2860_PROT_CTRL_CTS(2 << 16);
2931 }
2932 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1368)), (
(tmp))))
;
2933}
2934
2935void
2936rt2860_updateedca(struct ieee80211com *ic)
2937{
2938 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2939 int aci;
2940
2941 /* update MAC TX configuration registers */
2942 for (aci = 0; aci < EDCA_NUM_AC4; aci++) {
2943 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1300 + (
aci) * 4))), ((ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 | ic->ic_edca_ac
[aci].ac_aifsn << 8 | ic->ic_edca_ac[aci].ac_txoplimit
))))
2944 ic->ic_edca_ac[aci].ac_ecwmax << 16 |(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1300 + (
aci) * 4))), ((ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 | ic->ic_edca_ac
[aci].ac_aifsn << 8 | ic->ic_edca_ac[aci].ac_txoplimit
))))
2945 ic->ic_edca_ac[aci].ac_ecwmin << 12 |(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1300 + (
aci) * 4))), ((ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 | ic->ic_edca_ac
[aci].ac_aifsn << 8 | ic->ic_edca_ac[aci].ac_txoplimit
))))
2946 ic->ic_edca_ac[aci].ac_aifsn << 8 |(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1300 + (
aci) * 4))), ((ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 | ic->ic_edca_ac
[aci].ac_aifsn << 8 | ic->ic_edca_ac[aci].ac_txoplimit
))))
2947 ic->ic_edca_ac[aci].ac_txoplimit)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1300 + (
aci) * 4))), ((ic->ic_edca_ac[aci].ac_ecwmax << 16 |
ic->ic_edca_ac[aci].ac_ecwmin << 12 | ic->ic_edca_ac
[aci].ac_aifsn << 8 | ic->ic_edca_ac[aci].ac_txoplimit
))))
;
2948 }
2949
2950 /* update SCH/DMA registers too */
2951 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0214)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_aifsn << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_aifsn))))
2952 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0214)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_aifsn << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_aifsn))))
2953 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0214)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_aifsn << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_aifsn))))
2954 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0214)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_aifsn << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_aifsn))))
2955 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0214)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_aifsn << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_aifsn))))
;
2956 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0218)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmin << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmin))))
2957 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0218)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmin << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmin))))
2958 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0218)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmin << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmin))))
2959 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0218)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmin << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmin))))
2960 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0218)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmin << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmin))))
;
2961 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x021c)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmax << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmax))))
2962 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x021c)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmax << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmax))))
2963 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x021c)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmax << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmax))))
2964 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x021c)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmax << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmax))))
2965 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x021c)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | ic->
ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | ic->ic_edca_ac
[EDCA_AC_BK].ac_ecwmax << 4 | ic->ic_edca_ac[EDCA_AC_BE
].ac_ecwmax))))
;
2966 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0220)), (
(ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_BE].ac_txoplimit))))
2967 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0220)), (
(ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_BE].ac_txoplimit))))
2968 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0220)), (
(ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_BE].ac_txoplimit))))
;
2969 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0224)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_VI].ac_txoplimit))))
2970 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0224)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_VI].ac_txoplimit))))
2971 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0224)), (
(ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | ic->
ic_edca_ac[EDCA_AC_VI].ac_txoplimit))))
;
2972}
2973
2974int
2975rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
2976 struct ieee80211_key *k)
2977{
2978 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2979 bus_size_t base;
2980 uint32_t attr;
2981 uint8_t mode, wcid, iv[8];
2982
2983 /* defer setting of WEP keys until interface is brought up */
2984 if ((ic->ic_ific_ac.ac_if.if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) !=
2985 (IFF_UP0x1 | IFF_RUNNING0x40))
2986 return 0;
2987
2988 /* map net80211 cipher to RT2860 security mode */
2989 switch (k->k_cipher) {
2990 case IEEE80211_CIPHER_WEP40:
2991 mode = RT2860_MODE_WEP401;
2992 break;
2993 case IEEE80211_CIPHER_WEP104:
2994 mode = RT2860_MODE_WEP1042;
2995 break;
2996 case IEEE80211_CIPHER_TKIP:
2997 mode = RT2860_MODE_TKIP3;
2998 break;
2999 case IEEE80211_CIPHER_CCMP:
3000 mode = RT2860_MODE_AES_CCMP4;
3001 break;
3002 default:
3003 return EINVAL22;
3004 }
3005
3006 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
3007 wcid = 0; /* NB: update WCID0 for group keys */
3008 base = RT2860_SKEY(0, k->k_id)(0x6c00 + (0) * 128 + (k->k_id) * 32);
3009 } else {
3010 wcid = ((struct rt2860_node *)ni)->wcid;
3011 base = RT2860_PKEY(wcid)(0x4000 + (wcid) * 32);
3012 }
3013
3014 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3015 RAL_WRITE_REGION_1(sc, base, k->k_key, 16)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
)), ((k->k_key)), ((16))))
;
3016#ifndef IEEE80211_STA_ONLY
3017 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3018 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
+ 16)), ((&k->k_key[16])), ((8))))
;
3019 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
+ 24)), ((&k->k_key[24])), ((8))))
;
3020 } else
3021#endif
3022 {
3023 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
+ 16)), ((&k->k_key[24])), ((8))))
;
3024 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
+ 24)), ((&k->k_key[16])), ((8))))
;
3025 }
3026 } else
3027 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((base
)), ((k->k_key)), ((k->k_len))))
;
3028
3029 if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001) ||
3030 (k->k_flags & IEEE80211_KEY_TX0x00000002)) {
3031 /* set initial packet number in IV+EIV */
3032 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3033 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3034 uint32_t val = arc4random();
3035 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3036 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3037 val += 0x000100;
3038 iv[0] = val;
3039 iv[1] = val >> 8;
3040 iv[2] = val >> 16;
3041 iv[3] = k->k_id << 6;
3042 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3043 } else {
3044 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3045 iv[0] = k->k_tsc >> 8;
3046 iv[1] = (iv[0] | 0x20) & 0x7f;
3047 iv[2] = k->k_tsc;
3048 } else /* CCMP */ {
3049 iv[0] = k->k_tsc;
3050 iv[1] = k->k_tsc >> 8;
3051 iv[2] = 0;
3052 }
3053 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV0x20;
3054 iv[4] = k->k_tsc >> 16;
3055 iv[5] = k->k_tsc >> 24;
3056 iv[6] = k->k_tsc >> 32;
3057 iv[7] = k->k_tsc >> 40;
3058 }
3059 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x6000
+ (wcid) * 8))), ((iv)), ((8))))
;
3060 }
3061
3062 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
3063 /* install group key */
3064 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7000))));
3065 attr &= ~(0xf << (k->k_id * 4));
3066 attr |= mode << (k->k_id * 4);
3067 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7000)), (
(attr))))
;
3068 } else {
3069 /* install pairwise key */
3070 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid))(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x6800 + (wcid
) * 4)))))
;
3071 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN(1 << 0);
3072 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x6800 + (
wcid) * 4))), ((attr))))
;
3073 }
3074 return 0;
3075}
3076
3077void
3078rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3079 struct ieee80211_key *k)
3080{
3081 struct rt2860_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
3082 uint32_t attr;
3083 uint8_t wcid;
3084
3085 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
3086 /* remove group key */
3087 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x7000))));
3088 attr &= ~(0xf << (k->k_id * 4));
3089 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7000)), (
(attr))))
;
3090
3091 } else {
3092 /* remove pairwise key */
3093 wcid = ((struct rt2860_node *)ni)->wcid;
3094 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid))(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x6800 + (wcid
) * 4)))))
;
3095 attr &= ~0xf;
3096 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x6800 + (
wcid) * 4))), ((attr))))
;
3097 }
3098}
3099
3100#if NBPFILTER1 > 0
3101int8_t
3102rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3103{
3104 struct ieee80211com *ic = &sc->sc_ic;
3105 struct ieee80211_channel *c = ic->ic_ibss_chan;
3106 int delta;
3107
3108 if (IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) {
3109 u_int chan = ieee80211_chan2ieee(ic, c);
3110 delta = sc->rssi_5ghz[rxchain];
3111
3112 /* determine channel group */
3113 if (chan <= 64)
3114 delta -= sc->lna[1];
3115 else if (chan <= 128)
3116 delta -= sc->lna[2];
3117 else
3118 delta -= sc->lna[3];
3119 } else
3120 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3121
3122 return -12 - delta - rssi;
3123}
3124#endif
3125
3126/*
3127 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3128 * Used to adjust per-rate Tx power registers.
3129 */
3130static __inline uint32_t
3131b4inc(uint32_t b32, int8_t delta)
3132{
3133 int8_t i, b4;
3134
3135 for (i = 0; i < 8; i++) {
3136 b4 = b32 & 0xf;
3137 b4 += delta;
3138 if (b4 < 0)
3139 b4 = 0;
3140 else if (b4 > 0xf)
3141 b4 = 0xf;
3142 b32 = b32 >> 4 | b4 << 28;
3143 }
3144 return b32;
3145}
3146
3147const char *
3148rt2860_get_rf(uint16_t rev)
3149{
3150 switch (rev) {
3151 case RT2860_RF_28200x0001: return "RT2820";
3152 case RT2860_RF_28500x0002: return "RT2850";
3153 case RT2860_RF_27200x0003: return "RT2720";
3154 case RT2860_RF_27500x0004: return "RT2750";
3155 case RT3070_RF_30200x0005: return "RT3020";
3156 case RT3070_RF_20200x0006: return "RT2020";
3157 case RT3070_RF_30210x0007: return "RT3021";
3158 case RT3070_RF_30220x0008: return "RT3022";
3159 case RT3070_RF_30520x0009: return "RT3052";
3160 case RT3070_RF_33200x000b: return "RT3320";
3161 case RT3070_RF_30530x000d: return "RT3053";
3162 case RT3290_RF_32900x3290: return "RT3290";
3163 case RT5390_RF_53600x5360: return "RT5360";
3164 case RT5390_RF_53900x5390: return "RT5390";
3165 case RT5390_RF_53920x5392: return "RT5392";
3166 default: return "unknown";
3167 }
3168}
3169
3170int
3171rt2860_read_eeprom(struct rt2860_softc *sc)
3172{
3173 struct ieee80211com *ic = &sc->sc_ic;
3174 int8_t delta_2ghz, delta_5ghz;
3175 uint32_t tmp;
3176 uint16_t val;
3177 int ridx, ant, i;
3178
3179 /* check whether the ROM is eFUSE ROM or EEPROM */
3180 sc->sc_srom_read = rt2860_eeprom_read_2;
3181 if (sc->mac_ver == 0x3290) {
3182 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0024))));
3183 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3184 if (tmp & RT3070_SEL_EFUSE(1U << 31))
3185 sc->sc_srom_read = rt3290_efuse_read_2;
3186 } else if (sc->mac_ver >= 0x3071) {
3187 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0580))));
3188 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3189 if (tmp & RT3070_SEL_EFUSE(1U << 31))
3190 sc->sc_srom_read = rt3090_efuse_read_2;
3191 }
3192
3193 /* read EEPROM version */
3194 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION0x01);
3195 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
3196
3197 /* read MAC address */
3198 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC010x02);
3199 ic->ic_myaddr[0] = val & 0xff;
3200 ic->ic_myaddr[1] = val >> 8;
3201 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC230x03);
3202 ic->ic_myaddr[2] = val & 0xff;
3203 ic->ic_myaddr[3] = val >> 8;
3204 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC450x04);
3205 ic->ic_myaddr[4] = val & 0xff;
3206 ic->ic_myaddr[5] = val >> 8;
3207
3208 /* read country code */
3209 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY0x1c);
Value stored to 'val' is never read
3210 DPRINTF(("EEPROM region code=0x%04x\n", val));
3211
3212 /* read vendor BBP settings */
3213 for (i = 0; i < 8; i++) {
3214 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE0x78 + i);
3215 sc->bbp[i].val = val & 0xff;
3216 sc->bbp[i].reg = val >> 8;
3217 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3218 }
3219 if (sc->mac_ver >= 0x3071) {
3220 /* read vendor RF settings */
3221 for (i = 0; i < 10; i++) {
3222 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE0x82 + i);
3223 sc->rf[i].val = val & 0xff;
3224 sc->rf[i].reg = val >> 8;
3225 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3226 sc->rf[i].val));
3227 }
3228 }
3229
3230 /* read RF frequency offset from EEPROM */
3231 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS0x1d);
3232 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3233 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3234 if ((val >> 8) != 0xff) {
3235 /* read LEDs operating mode */
3236 sc->leds = val >> 8;
3237 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED10x1e);
3238 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED20x1f);
3239 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED30x20);
3240 } else {
3241 /* broken EEPROM, use default settings */
3242 sc->leds = 0x01;
3243 sc->led[0] = 0x5555;
3244 sc->led[1] = 0x2221;
3245 sc->led[2] = 0xa9f8;
3246 }
3247 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3248 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3249
3250 /* read RF information */
3251 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA0x1a);
3252 DPRINTF(("EEPROM ANT 0x%04x\n", val));
3253 if (sc->mac_ver >= 0x5390 || sc->mac_ver == 0x3290)
3254 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID0x00);
3255 else
3256 sc->rf_rev = (val >> 8) & 0xf;
3257 sc->ntxchains = (val >> 4) & 0xf;
3258 sc->nrxchains = val & 0xf;
3259 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3260 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3261
3262 /* check if RF supports automatic Tx access gain control */
3263 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG0x1b);
3264 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3265 /* check if driver should patch the DAC issue */
3266 if ((val >> 8) != 0xff)
3267 sc->patch_dac = (val >> 15) & 1;
3268 if ((val & 0xff) != 0xff) {
3269 sc->ext_5ghz_lna = (val >> 3) & 1;
3270 sc->ext_2ghz_lna = (val >> 2) & 1;
3271 /* check if RF supports automatic Tx access gain control */
3272 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
3273 /* check if we have a hardware radio switch */
3274 sc->rfswitch = val & 1;
3275 }
3276 if (sc->sc_flags & RT2860_ADVANCED_PS(1 << 1)) {
3277 /* read PCIe power save level */
3278 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL0x11);
3279 if ((val & 0xff) != 0xff) {
3280 sc->pslevel = val & 0x3;
3281 val = rt2860_srom_read(sc, RT2860_EEPROM_REV0x12);
3282 if ((val & 0xff80) != 0x9280)
3283 sc->pslevel = MIN(sc->pslevel, 1)(((sc->pslevel)<(1))?(sc->pslevel):(1));
3284 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3285 }
3286 }
3287
3288 /* read power settings for 2GHz channels */
3289 for (i = 0; i < 14; i += 2) {
3290 val = rt2860_srom_read(sc,
3291 RT2860_EEPROM_PWR2GHZ_BASE10x29 + i / 2);
3292 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3293 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3294
3295 if (sc->mac_ver != 0x5390) {
3296 val = rt2860_srom_read(sc,
3297 RT2860_EEPROM_PWR2GHZ_BASE20x30 + i / 2);
3298 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3299 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3300 }
3301 }
3302 /* fix broken Tx power entries */
3303 for (i = 0; i < 14; i++) {
3304 if (sc->txpow1[i] < 0 ||
3305 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3306 sc->txpow1[i] = 5;
3307 if (sc->mac_ver != 0x5390) {
3308 if (sc->txpow2[i] < 0 ||
3309 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3310 sc->txpow2[i] = 5;
3311 }
3312 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3313 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3314 }
3315 /* read power settings for 5GHz channels */
3316 for (i = 0; i < 40; i += 2) {
3317 val = rt2860_srom_read(sc,
3318 RT2860_EEPROM_PWR5GHZ_BASE10x3c + i / 2);
3319 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3320 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3321
3322 val = rt2860_srom_read(sc,
3323 RT2860_EEPROM_PWR5GHZ_BASE20x53 + i / 2);
3324 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3325 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3326 }
3327 /* fix broken Tx power entries */
3328 for (i = 0; i < 40; i++) {
3329 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3330 sc->txpow1[14 + i] = 5;
3331 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3332 sc->txpow2[14 + i] = 5;
3333 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3334 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3335 sc->txpow2[14 + i]));
3336 }
3337
3338 /* read Tx power compensation for each Tx rate */
3339 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR0x28);
3340 delta_2ghz = delta_5ghz = 0;
3341 if ((val & 0xff) != 0xff && (val & 0x80)) {
3342 delta_2ghz = val & 0xf;
3343 if (!(val & 0x40)) /* negative number */
3344 delta_2ghz = -delta_2ghz;
3345 }
3346 val >>= 8;
3347 if ((val & 0xff) != 0xff && (val & 0x80)) {
3348 delta_5ghz = val & 0xf;
3349 if (!(val & 0x40)) /* negative number */
3350 delta_5ghz = -delta_5ghz;
3351 }
3352 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3353 delta_2ghz, delta_5ghz));
3354
3355 for (ridx = 0; ridx < 5; ridx++) {
3356 uint32_t reg;
3357
3358 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2);
3359 reg = val;
3360 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2 + 1);
3361 reg |= (uint32_t)val << 16;
3362
3363 sc->txpow20mhz[ridx] = reg;
3364 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3365 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3366
3367 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3368 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3369 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3370 }
3371
3372 /* read factory-calibrated samples for temperature compensation */
3373 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ0x37);
3374 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3375 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3376 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ0x38);
3377 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3378 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3379 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ0x39);
3380 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3381 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3382 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ0x3a);
3383 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3384 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3385 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ0x3b);
3386 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3387 sc->step_2ghz = val >> 8;
3388 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3389 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3390 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3391 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3392 sc->tssi_2ghz[8], sc->step_2ghz));
3393 /* check that ref value is correct, otherwise disable calibration */
3394 if (sc->tssi_2ghz[4] == 0xff)
3395 sc->calib_2ghz = 0;
3396
3397 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ0x6a);
3398 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3399 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3400 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ0x6b);
3401 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3402 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3403 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ0x6c);
3404 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3405 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3406 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ0x6d);
3407 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3408 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3409 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ0x6e);
3410 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3411 sc->step_5ghz = val >> 8;
3412 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3413 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3414 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3415 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3416 sc->tssi_5ghz[8], sc->step_5ghz));
3417 /* check that ref value is correct, otherwise disable calibration */
3418 if (sc->tssi_5ghz[4] == 0xff)
3419 sc->calib_5ghz = 0;
3420
3421 /* read RSSI offsets and LNA gains from EEPROM */
3422 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ0x23);
3423 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3424 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3425 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ0x24);
3426 if (sc->mac_ver >= 0x3071) {
3427 /*
3428 * On RT3090 chips (limited to 2 Rx chains), this ROM
3429 * field contains the Tx mixer gain for the 2GHz band.
3430 */
3431 if ((val & 0xff) != 0xff)
3432 sc->txmixgain_2ghz = val & 0x7;
3433 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3434 } else
3435 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3436 sc->lna[2] = val >> 8; /* channel group 2 */
3437
3438 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ0x25);
3439 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3440 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3441 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ0x26);
3442 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3443 sc->lna[3] = val >> 8; /* channel group 3 */
3444
3445 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA0x22);
3446 if (sc->mac_ver >= 0x3071)
3447 sc->lna[0] = RT3090_DEF_LNA10;
3448 else /* channel group 0 */
3449 sc->lna[0] = val & 0xff;
3450 sc->lna[1] = val >> 8; /* channel group 1 */
3451
3452 /* fix broken 5GHz LNA entries */
3453 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3454 DPRINTF(("invalid LNA for channel group %d\n", 2));
3455 sc->lna[2] = sc->lna[1];
3456 }
3457 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3458 DPRINTF(("invalid LNA for channel group %d\n", 3));
3459 sc->lna[3] = sc->lna[1];
3460 }
3461
3462 /* fix broken RSSI offset entries */
3463 for (ant = 0; ant < 3; ant++) {
3464 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3465 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3466 ant + 1, sc->rssi_2ghz[ant]));
3467 sc->rssi_2ghz[ant] = 0;
3468 }
3469 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3470 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3471 ant + 1, sc->rssi_5ghz[ant]));
3472 sc->rssi_5ghz[ant] = 0;
3473 }
3474 }
3475
3476 return 0;
3477}
3478
3479int
3480rt2860_bbp_init(struct rt2860_softc *sc)
3481{
3482 int i, ntries;
3483
3484 /* wait for BBP to wake up */
3485 for (ntries = 0; ntries < 20; ntries++) {
3486 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3487 if (bbp0 != 0 && bbp0 != 0xff)
3488 break;
3489 }
3490 if (ntries == 20) {
3491 printf("%s: timeout waiting for BBP to wake up\n",
3492 sc->sc_dev.dv_xname);
3493 return ETIMEDOUT60;
3494 }
3495
3496 /* initialize BBP registers to default values */
3497 if (sc->mac_ver >= 0x5390 ||
3498 sc->mac_ver == 0x3290)
3499 rt5390_bbp_init(sc);
3500 else {
3501 for (i = 0; i < nitems(rt2860_def_bbp)(sizeof((rt2860_def_bbp)) / sizeof((rt2860_def_bbp)[0])); i++) {
3502 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3503 rt2860_def_bbp[i].val);
3504 }
3505 }
3506
3507 /* fix BBP84 for RT2860E */
3508 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3509 rt2860_mcu_bbp_write(sc, 84, 0x19);
3510
3511 if (sc->mac_ver >= 0x3071) {
3512 rt2860_mcu_bbp_write(sc, 79, 0x13);
3513 rt2860_mcu_bbp_write(sc, 80, 0x05);
3514 rt2860_mcu_bbp_write(sc, 81, 0x33);
3515 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3516 rt2860_mcu_bbp_write(sc, 69, 0x16);
3517 rt2860_mcu_bbp_write(sc, 73, 0x12);
3518 }
3519
3520 return 0;
3521}
3522
3523void
3524rt5390_bbp_init(struct rt2860_softc *sc)
3525{
3526 uint8_t bbp;
3527 int i;
3528
3529 /* Apply maximum likelihood detection for 2 stream case. */
3530 if (sc->nrxchains > 1) {
3531 bbp = rt2860_mcu_bbp_read(sc, 105);
3532 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD(1 << 2));
3533 }
3534
3535 /* Avoid data lost and CRC error. */
3536 bbp = rt2860_mcu_bbp_read(sc, 4);
3537 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6));
3538 if (sc->mac_ver == 0x3290) {
3539 for (i = 0; i < nitems(rt3290_def_bbp)(sizeof((rt3290_def_bbp)) / sizeof((rt3290_def_bbp)[0])); i++) {
3540 rt2860_mcu_bbp_write(sc, rt3290_def_bbp[i].reg,
3541 rt3290_def_bbp[i].val);
3542 }
3543 } else {
3544 for (i = 0; i < nitems(rt5390_def_bbp)(sizeof((rt5390_def_bbp)) / sizeof((rt5390_def_bbp)[0])); i++) {
3545 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3546 rt5390_def_bbp[i].val);
3547 }
3548 }
3549
3550 if (sc->mac_ver == 0x5392) {
3551 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3552 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3553 rt2860_mcu_bbp_write(sc, 98, 0x12);
3554 rt2860_mcu_bbp_write(sc, 106, 0x05);
3555 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3556 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3557 }
3558
3559 bbp = rt2860_mcu_bbp_read(sc, 152);
3560 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3561
3562 /* Disable hardware antenna diversity. */
3563 if (sc->mac_ver == 0x5390)
3564 rt2860_mcu_bbp_write(sc, 154, 0);
3565}
3566
3567int
3568rt3290_wlan_enable(struct rt2860_softc *sc)
3569{
3570 uint32_t tmp;
3571 int ntries;
3572
3573 /* enable chip and check readiness */
3574 tmp = RAL_READ(sc, RT3290_WLAN_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0080))));
3575 tmp |= RT3290_WLAN_EN(1U << 0) | RT3290_FRC_WL_ANT_SET(1U << 5) |
3576 RT3290_GPIO_OUT_OE_ALL(0xff << 24);
3577 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0080)), (
(tmp))))
;
3578
3579 for (ntries = 0; ntries < 200; ntries++) {
3580 tmp = RAL_READ(sc, RT3290_CMB_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0020))));
3581 if ((tmp & RT3290_PLL_LD(1U << 23)) &&
3582 (tmp & RT3290_XTAL_RDY(1U << 22)))
3583 break;
3584 DELAY(20)(*delay_func)(20);
3585 }
3586 if (ntries == 200)
3587 return EIO5;
3588
3589 /* toggle reset */
3590 tmp = RAL_READ(sc, RT3290_WLAN_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0080))));
3591 tmp |= RT3290_WLAN_RESET(1U << 3) | RT3290_WLAN_CLK_EN(1U << 1);
3592 tmp &= ~RT3290_PCIE_APP0_CLK_REQ(1U << 4);
3593 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0080)), (
(tmp))))
;
3594 DELAY(20)(*delay_func)(20);
3595 tmp &= ~RT3290_WLAN_RESET(1U << 3);
3596 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0080)), (
(tmp))))
;
3597 DELAY(1000)(*delay_func)(1000);
3598
3599 /* clear garbage interrupts */
3600 RAL_WRITE(sc, RT2860_INT_STATUS, 0x7fffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0200)), (
(0x7fffffff))))
;
3601
3602 return 0;
3603}
3604
3605int
3606rt2860_txrx_enable(struct rt2860_softc *sc)
3607{
3608 uint32_t tmp;
3609 int ntries;
3610
3611 /* enable Tx/Rx DMA engine */
3612 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 2)))))
;
3613 RAL_BARRIER_READ_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x01
| 0x02)
;
3614 for (ntries = 0; ntries < 200; ntries++) {
3615 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0208))));
3616 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
3617 break;
3618 DELAY(1000)(*delay_func)(1000);
3619 }
3620 if (ntries == 200) {
3621 printf("%s: timeout waiting for DMA engine\n",
3622 sc->sc_dev.dv_xname);
3623 return ETIMEDOUT60;
3624 }
3625
3626 DELAY(50)(*delay_func)(50);
3627
3628 tmp |= RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0) |
3629 RT2860_WPDMA_BT_SIZE642 << RT2860_WPDMA_BT_SIZE_SHIFT4;
3630 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0208)), (
(tmp))))
;
3631
3632 /* set Rx filter */
3633 tmp = RT2860_DROP_CRC_ERR(1 << 0) | RT2860_DROP_PHY_ERR(1 << 1);
3634 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) {
3635 tmp |= RT2860_DROP_UC_NOME(1 << 2) | RT2860_DROP_DUPL(1 << 7) |
3636 RT2860_DROP_CTS(1 << 11) | RT2860_DROP_BA(1 << 14) | RT2860_DROP_ACK(1 << 10) |
3637 RT2860_DROP_VER_ERR(1 << 4) | RT2860_DROP_CTRL_RSV(1 << 16) |
3638 RT2860_DROP_CFACK(1 << 8) | RT2860_DROP_CFEND(1 << 9);
3639 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA)
3640 tmp |= RT2860_DROP_RTS(1 << 12) | RT2860_DROP_PSPOLL(1 << 13);
3641 }
3642 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1400)), (
(tmp))))
;
3643
3644 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 3) | (1 << 2)))))
3645 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 3) | (1 << 2)))))
;
3646
3647 return 0;
3648}
3649
3650int
3651rt2860_init(struct ifnet *ifp)
3652{
3653 struct rt2860_softc *sc = ifp->if_softc;
3654 struct ieee80211com *ic = &sc->sc_ic;
3655 uint32_t tmp;
3656 uint8_t bbp1, bbp3;
3657 int i, qid, ridx, ntries, error;
3658
3659 /* for CardBus, power on the socket */
3660 if (!(sc->sc_flags & RT2860_ENABLED(1 << 0))) {
3661 if (sc->sc_enable != NULL((void *)0) && (*sc->sc_enable)(sc) != 0) {
3662 printf("%s: could not enable device\n",
3663 sc->sc_dev.dv_xname);
3664 return EIO5;
3665 }
3666 sc->sc_flags |= RT2860_ENABLED(1 << 0);
3667 }
3668
3669 if (sc->mac_ver == 0x3290) {
3670 if ((error = rt3290_wlan_enable(sc)) != 0) {
3671 printf("%s: could not enable wlan\n",
3672 sc->sc_dev.dv_xname);
3673 rt2860_stop(ifp, 1);
3674 return error;
3675 }
3676 }
3677
3678 if (sc->mac_ver == 0x3290 && sc->rfswitch){
3679 /* hardware has a radio switch on GPIO pin 0 */
3680 if (!(RAL_READ(sc, RT3290_WLAN_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0080)))) & RT3290_RADIO_EN(1U << 8))) {
3681 printf("%s: radio is disabled by hardware switch\n",
3682 sc->sc_dev.dv_xname);
3683 }
3684 } else if (sc->rfswitch) {
3685 /* hardware has a radio switch on GPIO pin 2 */
3686 if (!(RAL_READ(sc, RT2860_GPIO_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0228)))) & (1 << 2))) {
3687 printf("%s: radio is disabled by hardware switch\n",
3688 sc->sc_dev.dv_xname);
3689#ifdef notyet
3690 rt2860_stop(ifp, 1);
3691 return EPERM1;
3692#endif
3693 }
3694 }
3695 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1204)), (
((1 << 1)))))
;
3696
3697 /* disable DMA */
3698 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0208))));
3699 tmp &= 0xff0;
3700 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0208)), (
(tmp))))
;
3701
3702 /* PBF hardware reset */
3703 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
(0xe1f))))
;
3704 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
3705 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
(0xe00))))
;
3706
3707 if ((error = rt2860_load_microcode(sc)) != 0) {
3708 printf("%s: could not load 8051 microcode\n",
3709 sc->sc_dev.dv_xname);
3710 rt2860_stop(ifp, 1);
3711 return error;
3712 }
3713
3714 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl))__builtin_memcpy((ic->ic_myaddr), (((caddr_t)((ifp->if_sadl
)->sdl_data + (ifp->if_sadl)->sdl_nlen))), (6))
;
3715 rt2860_set_macaddr(sc, ic->ic_myaddr);
3716
3717 /* init Tx power for all Tx rates (from EEPROM) */
3718 for (ridx = 0; ridx < 5; ridx++) {
3719 if (sc->txpow20mhz[ridx] == 0xffffffff)
3720 continue;
3721 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx])(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1314 + (
ridx) * 4))), ((sc->txpow20mhz[ridx]))))
;
3722 }
3723
3724 for (ntries = 0; ntries < 100; ntries++) {
3725 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0208))));
3726 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
3727 break;
3728 DELAY(1000)(*delay_func)(1000);
3729 }
3730 if (ntries == 100) {
3731 printf("%s: timeout waiting for DMA engine\n",
3732 sc->sc_dev.dv_xname);
3733 rt2860_stop(ifp, 1);
3734 return ETIMEDOUT60;
3735 }
3736 tmp &= 0xff0;
3737 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0208)), (
(tmp))))
;
3738
3739 /* reset Rx ring and all 6 Tx rings */
3740 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x020c)), (
(0x1003f))))
;
3741
3742 /* PBF hardware reset */
3743 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
(0xe1f))))
;
3744 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
3745 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
(0xe00))))
;
3746
3747 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1204)), (
((1 << 1) | (1 << 0)))))
;
3748
3749 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 1) | (1 << 0)))))
;
3750 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
3751 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
(0))))
;
3752
3753 for (i = 0; i < nitems(rt2860_def_mac)(sizeof((rt2860_def_mac)) / sizeof((rt2860_def_mac)[0])); i++)
3754 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((rt2860_def_mac
[i].reg)), ((rt2860_def_mac[i].val))))
;
3755 if (sc->mac_ver == 0x3290 ||
3756 sc->mac_ver >= 0x5390)
3757 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1330)), (
(0x00000404))))
;
3758 else if (sc->mac_ver >= 0x3071) {
3759 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3760 RAL_WRITE(sc, RT2860_TX_SW_CFG0,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1330)), (
(4 << 8))))
3761 4 << RT2860_DLY_PAPE_EN_SHIFT)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1330)), (
(4 << 8))))
;
3762 }
3763
3764 if (!(RAL_READ(sc, RT2860_PCI_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0000)))) & RT2860_PCI_CFG_PCI(1 << 16))) {
3765 sc->sc_flags |= RT2860_PCIE(1 << 2);
3766 /* PCIe has different clock cycle count than PCI */
3767 tmp = RAL_READ(sc, RT2860_US_CYC_CNT)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x02a4))));
3768 tmp = (tmp & ~0xff) | 0x7d;
3769 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x02a4)), (
(tmp))))
;
3770 }
3771
3772 /* wait while MAC is busy */
3773 for (ntries = 0; ntries < 100; ntries++) {
3774 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1200)))) &
3775 (RT2860_RX_STATUS_BUSY(1 << 1) | RT2860_TX_STATUS_BUSY(1 << 0))))
3776 break;
3777 DELAY(1000)(*delay_func)(1000);
3778 }
3779 if (ntries == 100) {
3780 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname);
3781 rt2860_stop(ifp, 1);
3782 return ETIMEDOUT60;
3783 }
3784
3785 /* clear Host to MCU mailbox */
3786 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
(0))))
;
3787 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7010)), (
(0))))
;
3788
3789 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET0x72, 0, 0);
3790 DELAY(1000)(*delay_func)(1000);
3791
3792 if ((error = rt2860_bbp_init(sc)) != 0) {
3793 rt2860_stop(ifp, 1);
3794 return error;
3795 }
3796
3797 /* clear RX WCID search table */
3798 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x1800
+ (0) * 8))), ((0)), ((512))))
;
3799 /* clear pairwise key table */
3800 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x4000
+ (0) * 32))), ((0)), ((2048))))
;
3801 /* clear IV/EIV table */
3802 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x6000
+ (0) * 8))), ((0)), ((512))))
;
3803 /* clear WCID attribute table */
3804 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x6800
+ (0) * 4))), ((0)), ((256))))
;
3805 /* clear shared key table */
3806 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), (((0x6c00
+ (0) * 128 + (0) * 32))), ((0)), ((8 * 32))))
;
3807 /* clear shared key mode */
3808 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4)(((sc)->sc_st)->set_region_4(((sc)->sc_sh), ((0x7000
)), ((0)), ((4))))
;
3809
3810 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
3811 for (qid = 0; qid < 6; qid++) {
3812 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0230 + (
qid) * 16))), ((sc->txq[qid].paddr))))
;
3813 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0234 + (
qid) * 16))), ((64))))
;
3814 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0238 + (
qid) * 16))), ((0))))
;
3815 }
3816
3817 /* init Rx ring */
3818 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0290)), (
(sc->rxq.paddr))))
;
3819 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0294)), (
(128))))
;
3820 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0298)), (
(128 - 1))))
;
3821
3822 /* setup maximum buffer sizes */
3823 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1018)), (
(1 << 12 | ((1 << 11) - sizeof (struct rt2860_rxwi
) - 2)))))
3824 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1018)), (
(1 << 12 | ((1 << 11) - sizeof (struct rt2860_rxwi
) - 2)))))
;
3825
3826 for (ntries = 0; ntries < 100; ntries++) {
3827 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0208))));
3828 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
3829 break;
3830 DELAY(1000)(*delay_func)(1000);
3831 }
3832 if (ntries == 100) {
3833 printf("%s: timeout waiting for DMA engine\n",
3834 sc->sc_dev.dv_xname);
3835 rt2860_stop(ifp, 1);
3836 return ETIMEDOUT60;
3837 }
3838 tmp &= 0xff0;
3839 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0208)), (
(tmp))))
;
3840
3841 /* disable interrupts mitigation */
3842 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0210)), (
(0))))
;
3843
3844 /* write vendor-specific BBP values (from EEPROM) */
3845 for (i = 0; i < 8; i++) {
3846 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
3847 continue;
3848 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
3849 }
3850
3851 /* select Main antenna for 1T1R devices */
3852 if (sc->rf_rev == RT3070_RF_20200x0006 ||
3853 sc->rf_rev == RT3070_RF_30200x0005 ||
3854 sc->rf_rev == RT3290_RF_32900x3290 ||
3855 sc->rf_rev == RT3070_RF_33200x000b ||
3856 sc->rf_rev == RT5390_RF_53900x5390)
3857 rt3090_set_rx_antenna(sc, 0);
3858
3859 /* send LEDs operating mode to microcontroller */
3860 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED10x52, sc->led[0], 0);
3861 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED20x53, sc->led[1], 0);
3862 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED30x54, sc->led[2], 0);
3863
3864 if (sc->mac_ver == 0x3290 ||
3865 sc->mac_ver >= 0x5390)
3866 rt5390_rf_init(sc);
3867 else if (sc->mac_ver >= 0x3071)
3868 rt3090_rf_init(sc);
3869
3870 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP0x30, 0x02ff, 1);
3871 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP0x31, 0, 1);
3872
3873 if (sc->mac_ver == 0x3290 ||
3874 sc->mac_ver >= 0x5390)
3875 rt5390_rf_wakeup(sc);
3876 else if (sc->mac_ver >= 0x3071)
3877 rt3090_rf_wakeup(sc);
3878
3879 /* disable non-existing Rx chains */
3880 bbp3 = rt2860_mcu_bbp_read(sc, 3);
3881 bbp3 &= ~(1 << 3 | 1 << 4);
3882 if (sc->nrxchains == 2)
3883 bbp3 |= 1 << 3;
3884 else if (sc->nrxchains == 3)
3885 bbp3 |= 1 << 4;
3886 rt2860_mcu_bbp_write(sc, 3, bbp3);
3887
3888 /* disable non-existing Tx chains */
3889 bbp1 = rt2860_mcu_bbp_read(sc, 1);
3890 if (sc->ntxchains == 1)
3891 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
3892 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
3893 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
3894 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
3895 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
3896 rt2860_mcu_bbp_write(sc, 1, bbp1);
3897
3898 if (sc->mac_ver >= 0x3071)
3899 rt3090_rf_setup(sc);
3900
3901 /* select default channel */
3902 ic->ic_bss->ni_chan = ic->ic_ibss_chan;
3903 rt2860_switch_chan(sc, ic->ic_ibss_chan);
3904
3905 /* reset RF from MCU */
3906 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET0x72, 0, 0);
3907
3908 /* set RTS threshold */
3909 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1344))));
3910 tmp &= ~0xffff00;
3911 tmp |= ic->ic_rtsthreshold << 8;
3912 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1344)), (
(tmp))))
;
3913
3914 /* setup initial protection mode */
3915 sc->sc_ic_flags = ic->ic_flags;
3916 rt2860_updateprot(ic);
3917
3918 /* turn radio LED on */
3919 rt2860_set_leds(sc, RT2860_LED_RADIO(1 << 13));
3920
3921 /* enable Tx/Rx DMA engine */
3922 if ((error = rt2860_txrx_enable(sc)) != 0) {
3923 rt2860_stop(ifp, 1);
3924 return error;
3925 }
3926
3927 /* clear pending interrupts */
3928 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0200)), (
(0xffffffff))))
;
3929 /* enable interrupts */
3930 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0204)), (
(0x3fffc))))
;
3931
3932 if (sc->sc_flags & RT2860_ADVANCED_PS(1 << 1))
3933 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL0x83, sc->pslevel, 0);
3934
3935 ifp->if_flags |= IFF_RUNNING0x40;
3936 ifq_clr_oactive(&ifp->if_snd);
3937
3938 if (ic->ic_flags & IEEE80211_F_WEPON0x00000100) {
3939 /* install WEP keys */
3940 for (i = 0; i < IEEE80211_WEP_NKID4; i++)
3941 (void)rt2860_set_key(ic, NULL((void *)0), &ic->ic_nw_keys[i]);
3942 }
3943
3944 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3945 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1)));
3946 else
3947 ieee80211_new_state(ic, IEEE80211_S_RUN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_RUN), (-1)));
3948
3949 return 0;
3950}
3951
3952void
3953rt2860_stop(struct ifnet *ifp, int disable)
3954{
3955 struct rt2860_softc *sc = ifp->if_softc;
3956 struct ieee80211com *ic = &sc->sc_ic;
3957 uint32_t tmp;
3958 int qid;
3959
3960 if (ifp->if_flags & IFF_RUNNING0x40)
3961 rt2860_set_leds(sc, 0); /* turn all LEDs off */
3962
3963 sc->sc_tx_timer = 0;
3964 ifp->if_timer = 0;
3965 ifp->if_flags &= ~IFF_RUNNING0x40;
3966 ifq_clr_oactive(&ifp->if_snd);
3967
3968 ieee80211_new_state(ic, IEEE80211_S_INIT, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_INIT), (-1))); /* free all nodes */
3969
3970 /* disable interrupts */
3971 RAL_WRITE(sc, RT2860_INT_MASK, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0204)), (
(0))))
;
3972
3973 /* disable GP timer */
3974 rt2860_set_gp_timer(sc, 0);
3975
3976 /* disable Rx */
3977 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1004))));
3978 tmp &= ~(RT2860_MAC_RX_EN(1 << 3) | RT2860_MAC_TX_EN(1 << 2));
3979 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
(tmp))))
;
3980
3981 /* reset adapter */
3982 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
((1 << 1) | (1 << 0)))))
;
3983 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
3984 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1004)), (
(0))))
;
3985
3986 /* reset Tx and Rx rings (and reclaim TXWIs) */
3987 sc->qfullmsk = 0;
3988 for (qid = 0; qid < 6; qid++)
3989 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
3990 rt2860_reset_rx_ring(sc, &sc->rxq);
3991
3992 /* for CardBus, power down the socket */
3993 if (disable && sc->sc_disable != NULL((void *)0)) {
3994 if (sc->sc_flags & RT2860_ENABLED(1 << 0)) {
3995 (*sc->sc_disable)(sc);
3996 sc->sc_flags &= ~RT2860_ENABLED(1 << 0);
3997 }
3998 }
3999}
4000
4001int
4002rt2860_load_microcode(struct rt2860_softc *sc)
4003{
4004 int ntries;
4005
4006 /* set "host program ram write selection" bit */
4007 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
((1 << 16)))))
;
4008 /* write microcode image */
4009 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), ((0x2000
)), ((sc->ucode)), ((sc->ucsize))))
;
4010 /* kick microcontroller unit */
4011 RAL_WRITE(sc, RT2860_SYS_CTRL, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
(0))))
;
4012 RAL_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x02
)
;
4013 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0400)), (
((1 << 0)))))
;
4014
4015 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7028)), (
(0))))
;
4016 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x7010)), (
(0))))
;
4017
4018 /* wait until microcontroller is ready */
4019 RAL_BARRIER_READ_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, 0x01
| 0x02)
;
4020 for (ntries = 0; ntries < 1000; ntries++) {
4021 if (RAL_READ(sc, RT2860_SYS_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0400)))) & RT2860_MCU_READY(1 << 7))
4022 break;
4023 DELAY(1000)(*delay_func)(1000);
4024 }
4025 if (ntries == 1000) {
4026 printf("%s: timeout waiting for MCU to initialize\n",
4027 sc->sc_dev.dv_xname);
4028 return ETIMEDOUT60;
4029 }
4030 return 0;
4031}
4032
4033/*
4034 * This function is called periodically to adjust Tx power based on
4035 * temperature variation.
4036 */
4037void
4038rt2860_calib(struct rt2860_softc *sc)
4039{
4040 struct ieee80211com *ic = &sc->sc_ic;
4041 const uint8_t *tssi;
4042 uint8_t step, bbp49;
4043 int8_t ridx, d;
4044
4045 /* read current temperature */
4046 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4047
4048 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0
)
) {
4049 tssi = &sc->tssi_2ghz[4];
4050 step = sc->step_2ghz;
4051 } else {
4052 tssi = &sc->tssi_5ghz[4];
4053 step = sc->step_5ghz;
4054 }
4055
4056 if (bbp49 < tssi[0]) { /* lower than reference */
4057 /* use higher Tx power than default */
4058 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4059 } else if (bbp49 > tssi[0]) { /* greater than reference */
4060 /* use lower Tx power than default */
4061 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++);
4062 } else {
4063 /* use default Tx power */
4064 d = 0;
4065 }
4066 d *= step;
4067
4068 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4069
4070 /* write adjusted Tx power values for each Tx rate */
4071 for (ridx = 0; ridx < 5; ridx++) {
4072 if (sc->txpow20mhz[ridx] == 0xffffffff)
4073 continue;
4074 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1314 + (
ridx) * 4))), ((b4inc(sc->txpow20mhz[ridx], d)))))
4075 b4inc(sc->txpow20mhz[ridx], d))(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x1314 + (
ridx) * 4))), ((b4inc(sc->txpow20mhz[ridx], d)))))
;
4076 }
4077}
4078
4079void
4080rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4081{
4082 uint32_t tmp;
4083 if (aux) {
4084 if (sc->mac_ver == 0x5390) {
4085 rt2860_mcu_bbp_write(sc, 152,
4086 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4087 } else {
4088 tmp = RAL_READ(sc, RT2860_PCI_EECTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0004))));
4089 RAL_WRITE(sc, RT2860_PCI_EECTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0004)), (
(tmp & ~(1 << 0)))))
4090 tmp & ~RT2860_C)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0004)), (
(tmp & ~(1 << 0)))))
;
4091 tmp = RAL_READ(sc, RT2860_GPIO_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0228))));
4092 RAL_WRITE(sc, RT2860_GPIO_CTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0228)), (
((tmp & ~0x0808) | 0x08))))
4093 (tmp & ~0x0808) | 0x08)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0228)), (
((tmp & ~0x0808) | 0x08))))
;
4094 }
4095 } else {
4096 if (sc->mac_ver == 0x5390) {
4097 rt2860_mcu_bbp_write(sc, 152,
4098 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4099 } else {
4100 tmp = RAL_READ(sc, RT2860_PCI_EECTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0004))));
4101 RAL_WRITE(sc, RT2860_PCI_EECTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0004)), (
(tmp | (1 << 0)))))
4102 tmp | RT2860_C)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0004)), (
(tmp | (1 << 0)))))
;
4103 tmp = RAL_READ(sc, RT2860_GPIO_CTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0228))));
4104 RAL_WRITE(sc, RT2860_GPIO_CTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0228)), (
(tmp & ~0x0808))))
4105 tmp & ~0x0808)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0228)), (
(tmp & ~0x0808))))
;
4106 }
4107 }
4108}
4109
4110void
4111rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4112{
4113 struct ieee80211com *ic = &sc->sc_ic;
4114 u_int chan, group;
4115
4116 chan = ieee80211_chan2ieee(ic, c);
4117 if (chan == 0 || chan == IEEE80211_CHAN_ANY0xffff)
4118 return;
4119
4120 if (sc->mac_ver == 0x3290 ||
4121 sc->mac_ver >= 0x5390)
4122 rt5390_set_chan(sc, chan);
4123 else if (sc->mac_ver >= 0x3071)
4124 rt3090_set_chan(sc, chan);
4125 else
4126 rt2860_set_chan(sc, chan);
4127
4128 /* determine channel group */
4129 if (chan <= 14)
4130 group = 0;
4131 else if (chan <= 64)
4132 group = 1;
4133 else if (chan <= 128)
4134 group = 2;
4135 else
4136 group = 3;
4137
4138 /* XXX necessary only when group has changed! */
4139 if (sc->mac_ver <= 0x5390)
4140 rt2860_select_chan_group(sc, group);
4141
4142 DELAY(1000)(*delay_func)(1000);
4143}
4144
4145#ifndef IEEE80211_STA_ONLY
4146int
4147rt2860_setup_beacon(struct rt2860_softc *sc)
4148{
4149 struct ieee80211com *ic = &sc->sc_ic;
4150 struct rt2860_txwi txwi;
4151 struct mbuf *m;
4152 int ridx;
4153
4154 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL((void *)0))
4155 return ENOBUFS55;
4156
4157 memset(&txwi, 0, sizeof txwi)__builtin_memset((&txwi), (0), (sizeof txwi));
4158 txwi.wcid = 0xff;
4159 txwi.len = htole16(m->m_pkthdr.len)((__uint16_t)(m->M_dat.MH.MH_pkthdr.len));
4160 /* send beacons at the lowest available rate */
4161 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
4162 RT2860_RIDX_OFDM64 : RT2860_RIDX_CCK10;
4163 txwi.phy = htole16(rt2860_rates[ridx].mcs)((__uint16_t)(rt2860_rates[ridx].mcs));
4164 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4165 txwi.phy |= htole16(RT2860_PHY_OFDM)((__uint16_t)((1 << 14)));
4166 txwi.txop = RT2860_TX_TXOP_HT0;
4167 txwi.flags = RT2860_TX_TS(1 << 3);
4168 txwi.xflags = RT2860_TX_NSEQ(1 << 1);
4169
4170 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x7800
+ (0) * 512))), (((uint8_t *)&txwi)), ((sizeof txwi))))
4171 (uint8_t *)&txwi, sizeof txwi)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x7800
+ (0) * 512))), (((uint8_t *)&txwi)), ((sizeof txwi))))
;
4172 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x7800
+ (0) * 512) + sizeof txwi)), ((((uint8_t *)((m)->m_hdr.mh_data
)))), ((m->M_dat.MH.MH_pkthdr.len))))
4173 mtod(m, uint8_t *), m->m_pkthdr.len)(((sc)->sc_st)->write_region_1(((sc)->sc_sh), (((0x7800
+ (0) * 512) + sizeof txwi)), ((((uint8_t *)((m)->m_hdr.mh_data
)))), ((m->M_dat.MH.MH_pkthdr.len))))
;
4174
4175 m_freem(m);
4176
4177 return 0;
4178}
4179#endif
4180
4181void
4182rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4183{
4184 struct ieee80211com *ic = &sc->sc_ic;
4185 uint32_t tmp;
4186
4187 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((0x1114))));
4188
4189 tmp &= ~0x1fffff;
4190 tmp |= ic->ic_bss->ni_intval * 16;
4191 tmp |= RT2860_TSF_TIMER_EN(1 << 16) | RT2860_TBTT_TIMER_EN(1 << 19);
4192 if (ic->ic_opmode == IEEE80211_M_STA) {
4193 /*
4194 * Local TSF is always updated with remote TSF on beacon
4195 * reception.
4196 */
4197 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT17;
4198 }
4199#ifndef IEEE80211_STA_ONLY
4200 else if (ic->ic_opmode == IEEE80211_M_IBSS) {
4201 tmp |= RT2860_BCN_TX_EN(1 << 20);
4202 /*
4203 * Local TSF is updated with remote TSF on beacon reception
4204 * only if the remote TSF is greater than local TSF.
4205 */
4206 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT17;
4207 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
4208 tmp |= RT2860_BCN_TX_EN(1 << 20);
4209 /* SYNC with nobody */
4210 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT17;
4211 }
4212#endif
4213
4214 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x1114)), (
(tmp))))
;
4215}