File: | dev/pci/if_rge.c |
Warning: | line 481, column 16 Access to field 'rge_cmdsts' results in a dereference of a null pointer (loaded from variable 'd') |
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1 | /* $OpenBSD: if_rge.c,v 1.16 2021/11/23 01:44:44 kevlo Exp $ */ | |||
2 | ||||
3 | /* | |||
4 | * Copyright (c) 2019, 2020 Kevin Lo <kevlo@openbsd.org> | |||
5 | * | |||
6 | * Permission to use, copy, modify, and distribute this software for any | |||
7 | * purpose with or without fee is hereby granted, provided that the above | |||
8 | * copyright notice and this permission notice appear in all copies. | |||
9 | * | |||
10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |||
11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |||
12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |||
13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |||
14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |||
15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |||
16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |||
17 | */ | |||
18 | ||||
19 | #include "bpfilter.h" | |||
20 | #include "vlan.h" | |||
21 | ||||
22 | #include <sys/param.h> | |||
23 | #include <sys/systm.h> | |||
24 | #include <sys/sockio.h> | |||
25 | #include <sys/mbuf.h> | |||
26 | #include <sys/malloc.h> | |||
27 | #include <sys/kernel.h> | |||
28 | #include <sys/socket.h> | |||
29 | #include <sys/device.h> | |||
30 | #include <sys/endian.h> | |||
31 | ||||
32 | #include <net/if.h> | |||
33 | #include <net/if_media.h> | |||
34 | ||||
35 | #include <netinet/in.h> | |||
36 | #include <netinet/if_ether.h> | |||
37 | ||||
38 | #if NBPFILTER1 > 0 | |||
39 | #include <net/bpf.h> | |||
40 | #endif | |||
41 | ||||
42 | #include <machine/bus.h> | |||
43 | #include <machine/intr.h> | |||
44 | ||||
45 | #include <dev/mii/mii.h> | |||
46 | ||||
47 | #include <dev/pci/pcivar.h> | |||
48 | #include <dev/pci/pcireg.h> | |||
49 | #include <dev/pci/pcidevs.h> | |||
50 | ||||
51 | #include <dev/pci/if_rgereg.h> | |||
52 | ||||
53 | #ifdef RGE_DEBUG | |||
54 | #define DPRINTF(x) do { if (rge_debug > 0) printf x; } while (0) | |||
55 | int rge_debug = 0; | |||
56 | #else | |||
57 | #define DPRINTF(x) | |||
58 | #endif | |||
59 | ||||
60 | int rge_match(struct device *, void *, void *); | |||
61 | void rge_attach(struct device *, struct device *, void *); | |||
62 | int rge_activate(struct device *, int); | |||
63 | int rge_intr(void *); | |||
64 | int rge_encap(struct rge_queues *, struct mbuf *, int); | |||
65 | int rge_ioctl(struct ifnet *, u_long, caddr_t); | |||
66 | void rge_start(struct ifqueue *); | |||
67 | void rge_watchdog(struct ifnet *); | |||
68 | int rge_init(struct ifnet *); | |||
69 | void rge_stop(struct ifnet *); | |||
70 | int rge_ifmedia_upd(struct ifnet *); | |||
71 | void rge_ifmedia_sts(struct ifnet *, struct ifmediareq *); | |||
72 | int rge_allocmem(struct rge_softc *); | |||
73 | int rge_newbuf(struct rge_queues *); | |||
74 | void rge_discard_rxbuf(struct rge_queues *, int); | |||
75 | void rge_rx_list_init(struct rge_queues *); | |||
76 | void rge_tx_list_init(struct rge_queues *); | |||
77 | void rge_fill_rx_ring(struct rge_queues *); | |||
78 | int rge_rxeof(struct rge_queues *); | |||
79 | int rge_txeof(struct rge_queues *); | |||
80 | void rge_reset(struct rge_softc *); | |||
81 | void rge_iff(struct rge_softc *); | |||
82 | void rge_set_phy_power(struct rge_softc *, int); | |||
83 | void rge_phy_config(struct rge_softc *); | |||
84 | void rge_phy_config_mac_cfg2(struct rge_softc *); | |||
85 | void rge_phy_config_mac_cfg3(struct rge_softc *); | |||
86 | void rge_phy_config_mac_cfg4(struct rge_softc *); | |||
87 | void rge_phy_config_mac_cfg5(struct rge_softc *); | |||
88 | void rge_phy_config_mcu(struct rge_softc *, uint16_t); | |||
89 | void rge_set_macaddr(struct rge_softc *, const uint8_t *); | |||
90 | void rge_get_macaddr(struct rge_softc *, uint8_t *); | |||
91 | void rge_hw_init(struct rge_softc *); | |||
92 | void rge_disable_phy_ocp_pwrsave(struct rge_softc *); | |||
93 | void rge_patch_phy_mcu(struct rge_softc *, int); | |||
94 | void rge_add_media_types(struct rge_softc *); | |||
95 | void rge_config_imtype(struct rge_softc *, int); | |||
96 | void rge_disable_hw_im(struct rge_softc *); | |||
97 | void rge_disable_sim_im(struct rge_softc *); | |||
98 | void rge_setup_sim_im(struct rge_softc *); | |||
99 | void rge_setup_intr(struct rge_softc *, int); | |||
100 | void rge_exit_oob(struct rge_softc *); | |||
101 | void rge_write_csi(struct rge_softc *, uint32_t, uint32_t); | |||
102 | uint32_t rge_read_csi(struct rge_softc *, uint32_t); | |||
103 | void rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t); | |||
104 | uint16_t rge_read_mac_ocp(struct rge_softc *, uint16_t); | |||
105 | void rge_write_ephy(struct rge_softc *, uint16_t, uint16_t); | |||
106 | uint16_t rge_read_ephy(struct rge_softc *, uint16_t); | |||
107 | void rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t); | |||
108 | uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t); | |||
109 | void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t); | |||
110 | uint16_t rge_read_phy_ocp(struct rge_softc *, uint16_t); | |||
111 | int rge_get_link_status(struct rge_softc *); | |||
112 | void rge_txstart(void *); | |||
113 | void rge_tick(void *); | |||
114 | void rge_link_state(struct rge_softc *); | |||
115 | #ifndef SMALL_KERNEL | |||
116 | int rge_wol(struct ifnet *, int); | |||
117 | void rge_wol_power(struct rge_softc *); | |||
118 | #endif | |||
119 | ||||
120 | static const struct { | |||
121 | uint16_t reg; | |||
122 | uint16_t val; | |||
123 | } rtl8125_mac_cfg2_mcu[] = { | |||
124 | RTL8125_MAC_CFG2_MCU{ 0xa436, 0xa016 }, { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438 , 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x8013 }, { 0xa438, 0x1800 }, { 0xa438, 0x8021 }, { 0xa438, 0x1800 }, { 0xa438, 0x802f }, { 0xa438, 0x1800 }, { 0xa438, 0x803d }, { 0xa438, 0x1800 } , { 0xa438, 0x8042 }, { 0xa438, 0x1800 }, { 0xa438, 0x8051 }, { 0xa438, 0x1800 }, { 0xa438, 0x8051 }, { 0xa438, 0xa088 }, { 0xa438, 0x1800 }, { 0xa438, 0x0a50 }, { 0xa438, 0x8008 }, { 0xa438 , 0xd014 }, { 0xa438, 0xd1a3 }, { 0xa438, 0xd700 }, { 0xa438, 0x401a }, { 0xa438, 0xd707 }, { 0xa438, 0x40c2 }, { 0xa438, 0x60a6 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f8b }, { 0xa438, 0x1800 } , { 0xa438, 0x0a86 }, { 0xa438, 0x1800 }, { 0xa438, 0x0a6c }, { 0xa438, 0x8080 }, { 0xa438, 0xd019 }, { 0xa438, 0xd1a2 }, { 0xa438, 0xd700 }, { 0xa438, 0x401a }, { 0xa438, 0xd707 }, { 0xa438 , 0x40c4 }, { 0xa438, 0x60a6 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f8b }, { 0xa438, 0x1800 }, { 0xa438, 0x0a86 }, { 0xa438, 0x1800 }, { 0xa438, 0x0a84 }, { 0xa438, 0xd503 }, { 0xa438, 0x8970 } , { 0xa438, 0x0c07 }, { 0xa438, 0x0901 }, { 0xa438, 0xd500 }, { 0xa438, 0xce01 }, { 0xa438, 0xcf09 }, { 0xa438, 0xd705 }, { 0xa438, 0x4000 }, { 0xa438, 0xceff }, { 0xa438, 0xaf0a }, { 0xa438 , 0xd504 }, { 0xa438, 0x1800 }, { 0xa438, 0x1213 }, { 0xa438, 0x8401 }, { 0xa438, 0xd500 }, { 0xa438, 0x8580 }, { 0xa438, 0x1800 }, { 0xa438, 0x1253 }, { 0xa438, 0xd064 }, { 0xa438, 0xd181 } , { 0xa438, 0xd704 }, { 0xa438, 0x4018 }, { 0xa438, 0xd504 }, { 0xa438, 0xc50f }, { 0xa438, 0xd706 }, { 0xa438, 0x2c59 }, { 0xa438, 0x804d }, { 0xa438, 0xc60f }, { 0xa438, 0xf002 }, { 0xa438 , 0xc605 }, { 0xa438, 0xae02 }, { 0xa438, 0x1800 }, { 0xa438, 0x10fd }, { 0xa436, 0xa026 }, { 0xa438, 0xffff }, { 0xa436, 0xa024 }, { 0xa438, 0xffff }, { 0xa436, 0xa022 }, { 0xa438, 0x10f4 } , { 0xa436, 0xa020 }, { 0xa438, 0x1252 }, { 0xa436, 0xa006 }, { 0xa438, 0x1206 }, { 0xa436, 0xa004 }, { 0xa438, 0x0a78 }, { 0xa436, 0xa002 }, { 0xa438, 0x0a60 }, { 0xa436, 0xa000 }, { 0xa438 , 0x0a4f }, { 0xa436, 0xa008 }, { 0xa438, 0x3f00 }, { 0xa436, 0xa016 }, { 0xa438, 0x0010 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 } , { 0xa438, 0x1800 }, { 0xa438, 0x8066 }, { 0xa438, 0x1800 }, { 0xa438, 0x807c }, { 0xa438, 0x1800 }, { 0xa438, 0x8089 }, { 0xa438, 0x1800 }, { 0xa438, 0x808e }, { 0xa438, 0x1800 }, { 0xa438 , 0x80a0 }, { 0xa438, 0x1800 }, { 0xa438, 0x80b2 }, { 0xa438, 0x1800 }, { 0xa438, 0x80c2 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xd700 }, { 0xa438, 0x62db }, { 0xa438, 0x655c } , { 0xa438, 0xd73e }, { 0xa438, 0x60e9 }, { 0xa438, 0x614a }, { 0xa438, 0x61ab }, { 0xa438, 0x0c0f }, { 0xa438, 0x0501 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438 , 0x0503 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0505 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0509 }, { 0xa438, 0x1800 } , { 0xa438, 0x0304 }, { 0xa438, 0x653c }, { 0xa438, 0xd73e }, { 0xa438, 0x60e9 }, { 0xa438, 0x614a }, { 0xa438, 0x61ab }, { 0xa438, 0x0c0f }, { 0xa438, 0x0503 }, { 0xa438, 0x1800 }, { 0xa438 , 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0502 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0506 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f } , { 0xa438, 0x050a }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0xd73e }, { 0xa438, 0x60e9 }, { 0xa438, 0x614a }, { 0xa438, 0x61ab }, { 0xa438, 0x0c0f }, { 0xa438, 0x0505 }, { 0xa438 , 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0506 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0504 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 } , { 0xa438, 0x0c0f }, { 0xa438, 0x050c }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0xd73e }, { 0xa438, 0x60e9 }, { 0xa438, 0x614a }, { 0xa438, 0x61ab }, { 0xa438, 0x0c0f }, { 0xa438 , 0x0509 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x050a }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x050c }, { 0xa438, 0x1800 } , { 0xa438, 0x0304 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0508 }, { 0xa438, 0x1800 }, { 0xa438, 0x0304 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xd73e }, { 0xa438, 0x60e9 }, { 0xa438 , 0x614a }, { 0xa438, 0x61ab }, { 0xa438, 0x0c0f }, { 0xa438, 0x0501 }, { 0xa438, 0x1800 }, { 0xa438, 0x0321 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0502 }, { 0xa438, 0x1800 }, { 0xa438, 0x0321 } , { 0xa438, 0x0c0f }, { 0xa438, 0x0504 }, { 0xa438, 0x1800 }, { 0xa438, 0x0321 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0508 }, { 0xa438, 0x1800 }, { 0xa438, 0x0321 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0346 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0x8208 }, { 0xa438, 0x609d }, { 0xa438, 0xa50f }, { 0xa438, 0x1800 }, { 0xa438, 0x001a }, { 0xa438, 0x0c0f }, { 0xa438, 0x0503 } , { 0xa438, 0x1800 }, { 0xa438, 0x001a }, { 0xa438, 0x607d }, { 0xa438, 0x1800 }, { 0xa438, 0x00ab }, { 0xa438, 0x1800 }, { 0xa438, 0x00ab }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438 , 0xd700 }, { 0xa438, 0x60fd }, { 0xa438, 0xa50f }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0xaa0f }, { 0xa438, 0x1800 }, { 0xa438, 0x017b }, { 0xa438, 0x0c0f }, { 0xa438, 0x0503 } , { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0a05 }, { 0xa438, 0x1800 }, { 0xa438, 0x017b }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xd700 }, { 0xa438 , 0x60fd }, { 0xa438, 0xa50f }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0xaa0f }, { 0xa438, 0x1800 }, { 0xa438, 0x01e0 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0503 }, { 0xa438, 0xce00 } , { 0xa438, 0xd500 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0a05 }, { 0xa438, 0x1800 }, { 0xa438, 0x01e0 }, { 0xa438, 0xd700 }, { 0xa438, 0x60fd }, { 0xa438, 0xa50f }, { 0xa438, 0xce00 }, { 0xa438 , 0xd500 }, { 0xa438, 0xaa0f }, { 0xa438, 0x1800 }, { 0xa438, 0x0231 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0503 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0a05 } , { 0xa438, 0x1800 }, { 0xa438, 0x0231 }, { 0xa436, 0xa08e }, { 0xa438, 0xffff }, { 0xa436, 0xa08c }, { 0xa438, 0x0221 }, { 0xa436, 0xa08a }, { 0xa438, 0x01ce }, { 0xa436, 0xa088 }, { 0xa438 , 0x0169 }, { 0xa436, 0xa086 }, { 0xa438, 0x00a6 }, { 0xa436, 0xa084 }, { 0xa438, 0x000d }, { 0xa436, 0xa082 }, { 0xa438, 0x0308 }, { 0xa436, 0xa080 }, { 0xa438, 0x029f }, { 0xa436, 0xa090 } , { 0xa438, 0x007f }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438 , 0x8017 }, { 0xa438, 0x1800 }, { 0xa438, 0x801b }, { 0xa438, 0x1800 }, { 0xa438, 0x8029 }, { 0xa438, 0x1800 }, { 0xa438, 0x8054 }, { 0xa438, 0x1800 }, { 0xa438, 0x805a }, { 0xa438, 0x1800 } , { 0xa438, 0x8064 }, { 0xa438, 0x1800 }, { 0xa438, 0x80a7 }, { 0xa438, 0x9430 }, { 0xa438, 0x9480 }, { 0xa438, 0xb408 }, { 0xa438, 0xd120 }, { 0xa438, 0xd057 }, { 0xa438, 0x1800 }, { 0xa438 , 0x064b }, { 0xa438, 0xcb80 }, { 0xa438, 0x9906 }, { 0xa438, 0x1800 }, { 0xa438, 0x0567 }, { 0xa438, 0xcb94 }, { 0xa438, 0x8190 }, { 0xa438, 0x82a0 }, { 0xa438, 0x800a }, { 0xa438, 0x8406 } , { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0x8dff }, { 0xa438, 0x1000 }, { 0xa438, 0x07e4 }, { 0xa438, 0xa840 }, { 0xa438, 0x0000 }, { 0xa438, 0x1800 }, { 0xa438, 0x0773 }, { 0xa438 , 0xcb91 }, { 0xa438, 0x0000 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, { 0xa438, 0xd139 }, { 0xa438, 0xf002 }, { 0xa438, 0xd140 }, { 0xa438, 0xd040 }, { 0xa438, 0xb404 }, { 0xa438, 0x0c0f } , { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x07dc }, { 0xa438, 0xa610 }, { 0xa438, 0xa110 }, { 0xa438, 0xa2a0 }, { 0xa438, 0xa404 }, { 0xa438, 0xd704 }, { 0xa438, 0x4045 }, { 0xa438 , 0xa180 }, { 0xa438, 0xd704 }, { 0xa438, 0x405d }, { 0xa438, 0xa720 }, { 0xa438, 0x1000 }, { 0xa438, 0x0742 }, { 0xa438, 0x1000 }, { 0xa438, 0x07ec }, { 0xa438, 0xd700 }, { 0xa438, 0x5f74 } , { 0xa438, 0x1000 }, { 0xa438, 0x0742 }, { 0xa438, 0xd702 }, { 0xa438, 0x7fb6 }, { 0xa438, 0x8190 }, { 0xa438, 0x82a0 }, { 0xa438, 0x8404 }, { 0xa438, 0x8610 }, { 0xa438, 0x0c0f }, { 0xa438 , 0x0d01 }, { 0xa438, 0x1000 }, { 0xa438, 0x07dc }, { 0xa438, 0x1800 }, { 0xa438, 0x064b }, { 0xa438, 0x1000 }, { 0xa438, 0x07c0 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa7 }, { 0xa438, 0x1800 } , { 0xa438, 0x0481 }, { 0xa438, 0x0000 }, { 0xa438, 0x94bc }, { 0xa438, 0x870c }, { 0xa438, 0xa190 }, { 0xa438, 0xa00a }, { 0xa438, 0xa280 }, { 0xa438, 0xa404 }, { 0xa438, 0x8220 }, { 0xa438 , 0x1800 }, { 0xa438, 0x078e }, { 0xa438, 0xcb92 }, { 0xa438, 0xa840 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, { 0xa438, 0xd140 }, { 0xa438, 0xf002 }, { 0xa438, 0xd150 }, { 0xa438, 0xd040 } , { 0xa438, 0xd703 }, { 0xa438, 0x60a0 }, { 0xa438, 0x6121 }, { 0xa438, 0x61a2 }, { 0xa438, 0x6223 }, { 0xa438, 0xf02f }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d10 }, { 0xa438, 0x8010 }, { 0xa438 , 0xa740 }, { 0xa438, 0xf00f }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d20 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xf00a }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d30 }, { 0xa438, 0x8010 } , { 0xa438, 0xa740 }, { 0xa438, 0xf005 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d40 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e4 }, { 0xa438, 0xa610 }, { 0xa438 , 0xa008 }, { 0xa438, 0xd704 }, { 0xa438, 0x4046 }, { 0xa438, 0xa002 }, { 0xa438, 0xd704 }, { 0xa438, 0x405d }, { 0xa438, 0xa720 }, { 0xa438, 0x1000 }, { 0xa438, 0x0742 }, { 0xa438, 0x1000 } , { 0xa438, 0x07f7 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f74 }, { 0xa438, 0x1000 }, { 0xa438, 0x0742 }, { 0xa438, 0xd702 }, { 0xa438, 0x7fb5 }, { 0xa438, 0x800a }, { 0xa438, 0x0cf0 }, { 0xa438 , 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e4 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xd701 }, { 0xa438, 0x3ad4 }, { 0xa438, 0x0537 }, { 0xa438, 0x8610 }, { 0xa438, 0x8840 } , { 0xa438, 0x1800 }, { 0xa438, 0x064b }, { 0xa438, 0x8301 }, { 0xa438, 0x800a }, { 0xa438, 0x8190 }, { 0xa438, 0x82a0 }, { 0xa438, 0x8404 }, { 0xa438, 0xa70c }, { 0xa438, 0x9402 }, { 0xa438 , 0x890c }, { 0xa438, 0x8840 }, { 0xa438, 0x1800 }, { 0xa438, 0x064b }, { 0xa436, 0xa10e }, { 0xa438, 0x0642 }, { 0xa436, 0xa10c }, { 0xa438, 0x0686 }, { 0xa436, 0xa10a }, { 0xa438, 0x0788 } , { 0xa436, 0xa108 }, { 0xa438, 0x047b }, { 0xa436, 0xa106 }, { 0xa438, 0x065c }, { 0xa436, 0xa104 }, { 0xa438, 0x0769 }, { 0xa436, 0xa102 }, { 0xa438, 0x0565 }, { 0xa436, 0xa100 }, { 0xa438 , 0x06f9 }, { 0xa436, 0xa110 }, { 0xa438, 0x00ff }, { 0xa436, 0xb87c }, { 0xa438, 0x8530 }, { 0xa436, 0xb87e }, { 0xa438, 0xaf85 }, { 0xa438, 0x3caf }, { 0xa438, 0x8593 }, { 0xa438, 0xaf85 } , { 0xa438, 0x9caf }, { 0xa438, 0x85a5 }, { 0xa438, 0xbf86 }, { 0xa438, 0xd702 }, { 0xa438, 0x5afb }, { 0xa438, 0xe083 }, { 0xa438, 0xfb0c }, { 0xa438, 0x020d }, { 0xa438, 0x021b }, { 0xa438 , 0x10bf }, { 0xa438, 0x86d7 }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x86da }, { 0xa438, 0x025a }, { 0xa438, 0xfbe0 }, { 0xa438, 0x83fc }, { 0xa438, 0x0c02 }, { 0xa438, 0x0d02 } , { 0xa438, 0x1b10 }, { 0xa438, 0xbf86 }, { 0xa438, 0xda02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf86 }, { 0xa438, 0xdd02 }, { 0xa438, 0x5afb }, { 0xa438, 0xe083 }, { 0xa438, 0xfd0c }, { 0xa438 , 0x020d }, { 0xa438, 0x021b }, { 0xa438, 0x10bf }, { 0xa438, 0x86dd }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x86e0 }, { 0xa438, 0x025a }, { 0xa438, 0xfbe0 }, { 0xa438, 0x83fe } , { 0xa438, 0x0c02 }, { 0xa438, 0x0d02 }, { 0xa438, 0x1b10 }, { 0xa438, 0xbf86 }, { 0xa438, 0xe002 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xaf2f }, { 0xa438, 0xbd02 }, { 0xa438, 0x2cac }, { 0xa438 , 0x0286 }, { 0xa438, 0x65af }, { 0xa438, 0x212b }, { 0xa438, 0x022c }, { 0xa438, 0x6002 }, { 0xa438, 0x86b6 }, { 0xa438, 0xaf21 }, { 0xa438, 0x0cd1 }, { 0xa438, 0x03bf }, { 0xa438, 0x8710 } , { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x870d }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x8719 }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x8716 }, { 0xa438 , 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x871f }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x871c }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x8728 }, { 0xa438, 0x025a } , { 0xa438, 0xb7bf }, { 0xa438, 0x8725 }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x8707 }, { 0xa438, 0x025a }, { 0xa438, 0xfbad }, { 0xa438, 0x281c }, { 0xa438, 0xd100 }, { 0xa438 , 0xbf87 }, { 0xa438, 0x0a02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x1302 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x2202 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 } , { 0xa438, 0x2b02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xae1a }, { 0xa438, 0xd101 }, { 0xa438, 0xbf87 }, { 0xa438, 0x0a02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x1302 }, { 0xa438 , 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x2202 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x2b02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xd101 }, { 0xa438, 0xbf87 }, { 0xa438, 0x3402 } , { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x3102 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x3d02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x3a02 }, { 0xa438 , 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x4302 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x4002 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x4c02 }, { 0xa438, 0x5ab7 } , { 0xa438, 0xbf87 }, { 0xa438, 0x4902 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xd100 }, { 0xa438, 0xbf87 }, { 0xa438, 0x2e02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x3702 }, { 0xa438 , 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x4602 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xbf87 }, { 0xa438, 0x4f02 }, { 0xa438, 0x5ab7 }, { 0xa438, 0xaf35 }, { 0xa438, 0x7ff8 }, { 0xa438, 0xfaef } , { 0xa438, 0x69bf }, { 0xa438, 0x86e3 }, { 0xa438, 0x025a }, { 0xa438, 0xfbbf }, { 0xa438, 0x86fb }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x86e6 }, { 0xa438, 0x025a }, { 0xa438 , 0xfbbf }, { 0xa438, 0x86fe }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x86e9 }, { 0xa438, 0x025a }, { 0xa438, 0xfbbf }, { 0xa438, 0x8701 }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf } , { 0xa438, 0x86ec }, { 0xa438, 0x025a }, { 0xa438, 0xfbbf }, { 0xa438, 0x8704 }, { 0xa438, 0x025a }, { 0xa438, 0xb7bf }, { 0xa438, 0x86ef }, { 0xa438, 0x0262 }, { 0xa438, 0x7cbf }, { 0xa438 , 0x86f2 }, { 0xa438, 0x0262 }, { 0xa438, 0x7cbf }, { 0xa438, 0x86f5 }, { 0xa438, 0x0262 }, { 0xa438, 0x7cbf }, { 0xa438, 0x86f8 }, { 0xa438, 0x0262 }, { 0xa438, 0x7cef }, { 0xa438, 0x96fe } , { 0xa438, 0xfc04 }, { 0xa438, 0xf8fa }, { 0xa438, 0xef69 }, { 0xa438, 0xbf86 }, { 0xa438, 0xef02 }, { 0xa438, 0x6273 }, { 0xa438, 0xbf86 }, { 0xa438, 0xf202 }, { 0xa438, 0x6273 }, { 0xa438 , 0xbf86 }, { 0xa438, 0xf502 }, { 0xa438, 0x6273 }, { 0xa438, 0xbf86 }, { 0xa438, 0xf802 }, { 0xa438, 0x6273 }, { 0xa438, 0xef96 }, { 0xa438, 0xfefc }, { 0xa438, 0x0420 }, { 0xa438, 0xb540 } , { 0xa438, 0x53b5 }, { 0xa438, 0x4086 }, { 0xa438, 0xb540 }, { 0xa438, 0xb9b5 }, { 0xa438, 0x40c8 }, { 0xa438, 0xb03a }, { 0xa438, 0xc8b0 }, { 0xa438, 0xbac8 }, { 0xa438, 0xb13a }, { 0xa438 , 0xc8b1 }, { 0xa438, 0xba77 }, { 0xa438, 0xbd26 }, { 0xa438, 0xffbd }, { 0xa438, 0x2677 }, { 0xa438, 0xbd28 }, { 0xa438, 0xffbd }, { 0xa438, 0x2840 }, { 0xa438, 0xbd26 }, { 0xa438, 0xc8bd } , { 0xa438, 0x2640 }, { 0xa438, 0xbd28 }, { 0xa438, 0xc8bd }, { 0xa438, 0x28bb }, { 0xa438, 0xa430 }, { 0xa438, 0x98b0 }, { 0xa438, 0x1eba }, { 0xa438, 0xb01e }, { 0xa438, 0xdcb0 }, { 0xa438 , 0x1e98 }, { 0xa438, 0xb09e }, { 0xa438, 0xbab0 }, { 0xa438, 0x9edc }, { 0xa438, 0xb09e }, { 0xa438, 0x98b1 }, { 0xa438, 0x1eba }, { 0xa438, 0xb11e }, { 0xa438, 0xdcb1 }, { 0xa438, 0x1e98 } , { 0xa438, 0xb19e }, { 0xa438, 0xbab1 }, { 0xa438, 0x9edc }, { 0xa438, 0xb19e }, { 0xa438, 0x11b0 }, { 0xa438, 0x1e22 }, { 0xa438, 0xb01e }, { 0xa438, 0x33b0 }, { 0xa438, 0x1e11 }, { 0xa438 , 0xb09e }, { 0xa438, 0x22b0 }, { 0xa438, 0x9e33 }, { 0xa438, 0xb09e }, { 0xa438, 0x11b1 }, { 0xa438, 0x1e22 }, { 0xa438, 0xb11e }, { 0xa438, 0x33b1 }, { 0xa438, 0x1e11 }, { 0xa438, 0xb19e } , { 0xa438, 0x22b1 }, { 0xa438, 0x9e33 }, { 0xa438, 0xb19e }, { 0xa436, 0xb85e }, { 0xa438, 0x2f71 }, { 0xa436, 0xb860 }, { 0xa438, 0x20d9 }, { 0xa436, 0xb862 }, { 0xa438, 0x2109 }, { 0xa436 , 0xb864 }, { 0xa438, 0x34e7 }, { 0xa436, 0xb878 }, { 0xa438, 0x000f } | |||
125 | }, rtl8125_mac_cfg3_mcu[] = { | |||
126 | RTL8125_MAC_CFG3_MCU{ 0xa436, 0xa016 }, { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438 , 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x808b }, { 0xa438, 0x1800 }, { 0xa438, 0x808f }, { 0xa438, 0x1800 }, { 0xa438, 0x8093 }, { 0xa438, 0x1800 }, { 0xa438, 0x8097 }, { 0xa438, 0x1800 } , { 0xa438, 0x809d }, { 0xa438, 0x1800 }, { 0xa438, 0x80a1 }, { 0xa438, 0x1800 }, { 0xa438, 0x80aa }, { 0xa438, 0xd718 }, { 0xa438, 0x607b }, { 0xa438, 0x40da }, { 0xa438, 0xf00e }, { 0xa438 , 0x42da }, { 0xa438, 0xf01e }, { 0xa438, 0xd718 }, { 0xa438, 0x615b }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, { 0xa438, 0x1000 }, { 0xa438, 0x14bc } , { 0xa438, 0xd718 }, { 0xa438, 0x5f2e }, { 0xa438, 0xf01c }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438 , 0xd718 }, { 0xa438, 0x5f2e }, { 0xa438, 0xf024 }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 } , { 0xa438, 0x5f2e }, { 0xa438, 0xf02c }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 }, { 0xa438 , 0x5f2e }, { 0xa438, 0xf034 }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac11 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa410 }, { 0xa438, 0xce00 } , { 0xa438, 0xd500 }, { 0xa438, 0x4779 }, { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, { 0xa438, 0xf034 }, { 0xa438 , 0xd719 }, { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac22 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa420 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x4559 } , { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, { 0xa438, 0xf023 }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, { 0xa438 , 0xd504 }, { 0xa438, 0xac44 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa440 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x4339 }, { 0xa438, 0xd504 }, { 0xa438, 0xac0f } , { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, { 0xa438, 0xf012 }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac88 }, { 0xa438 , 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa480 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x4119 }, { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, { 0xa438, 0xd500 } , { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, { 0xa438, 0xf001 }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fac }, { 0xa438, 0xc48f }, { 0xa438, 0x1000 }, { 0xa438 , 0x141b }, { 0xa438, 0xd504 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x121a }, { 0xa438, 0xd0b4 }, { 0xa438, 0xd1bb }, { 0xa438, 0x1800 }, { 0xa438, 0x0898 }, { 0xa438, 0xd0b4 } , { 0xa438, 0xd1bb }, { 0xa438, 0x1800 }, { 0xa438, 0x0a0e }, { 0xa438, 0xd064 }, { 0xa438, 0xd18a }, { 0xa438, 0x1800 }, { 0xa438, 0x0b7e }, { 0xa438, 0x401c }, { 0xa438, 0xd501 }, { 0xa438 , 0xa804 }, { 0xa438, 0x8804 }, { 0xa438, 0x1800 }, { 0xa438, 0x053b }, { 0xa438, 0xd500 }, { 0xa438, 0xa301 }, { 0xa438, 0x1800 }, { 0xa438, 0x0648 }, { 0xa438, 0xc520 }, { 0xa438, 0xa201 } , { 0xa438, 0xd701 }, { 0xa438, 0x252d }, { 0xa438, 0x1646 }, { 0xa438, 0xd708 }, { 0xa438, 0x4006 }, { 0xa438, 0x1800 }, { 0xa438, 0x1646 }, { 0xa438, 0x1800 }, { 0xa438, 0x0308 }, { 0xa436 , 0xa026 }, { 0xa438, 0x0307 }, { 0xa436, 0xa024 }, { 0xa438, 0x1645 }, { 0xa436, 0xa022 }, { 0xa438, 0x0647 }, { 0xa436, 0xa020 }, { 0xa438, 0x053a }, { 0xa436, 0xa006 }, { 0xa438, 0x0b7c } , { 0xa436, 0xa004 }, { 0xa438, 0x0a0c }, { 0xa436, 0xa002 }, { 0xa438, 0x0896 }, { 0xa436, 0xa000 }, { 0xa438, 0x11a1 }, { 0xa436, 0xa008 }, { 0xa438, 0xff00 }, { 0xa436, 0xa016 }, { 0xa438 , 0x0010 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x8015 }, { 0xa438, 0x1800 }, { 0xa438, 0x801a } , { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438 , 0x801a }, { 0xa438, 0xad02 }, { 0xa438, 0x1000 }, { 0xa438, 0x02d7 }, { 0xa438, 0x1800 }, { 0xa438, 0x00ed }, { 0xa438, 0x0c0f }, { 0xa438, 0x0509 }, { 0xa438, 0xc100 }, { 0xa438, 0x1800 } , { 0xa438, 0x008f }, { 0xa436, 0xa08e }, { 0xa438, 0xffff }, { 0xa436, 0xa08c }, { 0xa438, 0xffff }, { 0xa436, 0xa08a }, { 0xa438, 0xffff }, { 0xa436, 0xa088 }, { 0xa438, 0xffff }, { 0xa436 , 0xa086 }, { 0xa438, 0xffff }, { 0xa436, 0xa084 }, { 0xa438, 0xffff }, { 0xa436, 0xa082 }, { 0xa438, 0x008d }, { 0xa436, 0xa080 }, { 0xa438, 0x00eb }, { 0xa436, 0xa090 }, { 0xa438, 0x0103 } , { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x8014 }, { 0xa438 , 0x1800 }, { 0xa438, 0x8018 }, { 0xa438, 0x1800 }, { 0xa438, 0x8024 }, { 0xa438, 0x1800 }, { 0xa438, 0x8051 }, { 0xa438, 0x1800 }, { 0xa438, 0x8055 }, { 0xa438, 0x1800 }, { 0xa438, 0x8072 } , { 0xa438, 0x1800 }, { 0xa438, 0x80dc }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0xfffd }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438 , 0xfffd }, { 0xa438, 0x8301 }, { 0xa438, 0x800a }, { 0xa438, 0x8190 }, { 0xa438, 0x82a0 }, { 0xa438, 0x8404 }, { 0xa438, 0xa70c }, { 0xa438, 0x9402 }, { 0xa438, 0x890c }, { 0xa438, 0x8840 } , { 0xa438, 0xa380 }, { 0xa438, 0x1800 }, { 0xa438, 0x066e }, { 0xa438, 0xcb91 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, { 0xa438, 0xd139 }, { 0xa438, 0xf002 }, { 0xa438, 0xd140 }, { 0xa438 , 0xd040 }, { 0xa438, 0xb404 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e0 }, { 0xa438, 0xa610 }, { 0xa438, 0xa110 }, { 0xa438, 0xa2a0 }, { 0xa438, 0xa404 } , { 0xa438, 0xd704 }, { 0xa438, 0x4085 }, { 0xa438, 0xa180 }, { 0xa438, 0xa404 }, { 0xa438, 0x8280 }, { 0xa438, 0xd704 }, { 0xa438, 0x405d }, { 0xa438, 0xa720 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0743 }, { 0xa438, 0x1000 }, { 0xa438, 0x07f0 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f74 }, { 0xa438, 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0xd702 }, { 0xa438, 0x7fb6 }, { 0xa438, 0x8190 } , { 0xa438, 0x82a0 }, { 0xa438, 0x8404 }, { 0xa438, 0x8610 }, { 0xa438, 0x0000 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0d01 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e0 }, { 0xa438, 0x1800 }, { 0xa438 , 0x066e }, { 0xa438, 0xd158 }, { 0xa438, 0xd04d }, { 0xa438, 0x1800 }, { 0xa438, 0x03d4 }, { 0xa438, 0x94bc }, { 0xa438, 0x870c }, { 0xa438, 0x8380 }, { 0xa438, 0xd10d }, { 0xa438, 0xd040 } , { 0xa438, 0x1000 }, { 0xa438, 0x07c4 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xa190 }, { 0xa438, 0xa00a }, { 0xa438, 0xa280 }, { 0xa438, 0xa404 }, { 0xa438, 0xa220 }, { 0xa438 , 0xd130 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x07c4 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xbb80 }, { 0xa438, 0xd1c4 }, { 0xa438, 0xd074 }, { 0xa438, 0xa301 } , { 0xa438, 0xd704 }, { 0xa438, 0x604b }, { 0xa438, 0xa90c }, { 0xa438, 0x1800 }, { 0xa438, 0x0556 }, { 0xa438, 0xcb92 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, { 0xa438, 0xd116 }, { 0xa438 , 0xf002 }, { 0xa438, 0xd119 }, { 0xa438, 0xd040 }, { 0xa438, 0xd703 }, { 0xa438, 0x60a0 }, { 0xa438, 0x6241 }, { 0xa438, 0x63e2 }, { 0xa438, 0x6583 }, { 0xa438, 0xf054 }, { 0xa438, 0xd701 } , { 0xa438, 0x611e }, { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d10 }, { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, { 0xa438, 0xf02f }, { 0xa438, 0x0cf0 }, { 0xa438 , 0x0d50 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xf02a }, { 0xa438, 0xd701 }, { 0xa438, 0x611e }, { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d20 } , { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, { 0xa438, 0xf021 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d60 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xf01c }, { 0xa438, 0xd701 }, { 0xa438 , 0x611e }, { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d30 }, { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, { 0xa438, 0xf013 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d70 } , { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xf00e }, { 0xa438, 0xd701 }, { 0xa438, 0x611e }, { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d40 }, { 0xa438 , 0xa010 }, { 0xa438, 0x8740 }, { 0xa438, 0xf005 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d80 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e8 }, { 0xa438, 0xa610 } , { 0xa438, 0xd704 }, { 0xa438, 0x405d }, { 0xa438, 0xa720 }, { 0xa438, 0xd700 }, { 0xa438, 0x5ff4 }, { 0xa438, 0xa008 }, { 0xa438, 0xd704 }, { 0xa438, 0x4046 }, { 0xa438, 0xa002 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0x1000 }, { 0xa438, 0x07fb }, { 0xa438, 0xd703 }, { 0xa438, 0x7f6f }, { 0xa438, 0x7f4e }, { 0xa438, 0x7f2d }, { 0xa438, 0x7f0c }, { 0xa438, 0x800a } , { 0xa438, 0x0cf0 }, { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e8 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0xd702 }, { 0xa438 , 0x7fb5 }, { 0xa438, 0xd701 }, { 0xa438, 0x3ad4 }, { 0xa438, 0x0556 }, { 0xa438, 0x8610 }, { 0xa438, 0x1800 }, { 0xa438, 0x066e }, { 0xa438, 0xd1f5 }, { 0xa438, 0xd049 }, { 0xa438, 0x1800 } , { 0xa438, 0x01ec }, { 0xa436, 0xa10e }, { 0xa438, 0x01ea }, { 0xa436, 0xa10c }, { 0xa438, 0x06a9 }, { 0xa436, 0xa10a }, { 0xa438, 0x078a }, { 0xa436, 0xa108 }, { 0xa438, 0x03d2 }, { 0xa436 , 0xa106 }, { 0xa438, 0x067f }, { 0xa436, 0xa104 }, { 0xa438, 0x0665 }, { 0xa436, 0xa102 }, { 0xa438, 0x0000 }, { 0xa436, 0xa100 }, { 0xa438, 0x0000 }, { 0xa436, 0xa110 }, { 0xa438, 0x00fc } , { 0xa436, 0xb87c }, { 0xa438, 0x8530 }, { 0xa436, 0xb87e }, { 0xa438, 0xaf85 }, { 0xa438, 0x3caf }, { 0xa438, 0x8545 }, { 0xa438, 0xaf85 }, { 0xa438, 0x45af }, { 0xa438, 0x8545 }, { 0xa438 , 0xee82 }, { 0xa438, 0xf900 }, { 0xa438, 0x0103 }, { 0xa438, 0xaf03 }, { 0xa438, 0xb7f8 }, { 0xa438, 0xe0a6 }, { 0xa438, 0x00e1 }, { 0xa438, 0xa601 }, { 0xa438, 0xef01 }, { 0xa438, 0x58f0 } , { 0xa438, 0xa080 }, { 0xa438, 0x37a1 }, { 0xa438, 0x8402 }, { 0xa438, 0xae16 }, { 0xa438, 0xa185 }, { 0xa438, 0x02ae }, { 0xa438, 0x11a1 }, { 0xa438, 0x8702 }, { 0xa438, 0xae0c }, { 0xa438 , 0xa188 }, { 0xa438, 0x02ae }, { 0xa438, 0x07a1 }, { 0xa438, 0x8902 }, { 0xa438, 0xae02 }, { 0xa438, 0xae1c }, { 0xa438, 0xe0b4 }, { 0xa438, 0x62e1 }, { 0xa438, 0xb463 }, { 0xa438, 0x6901 } , { 0xa438, 0xe4b4 }, { 0xa438, 0x62e5 }, { 0xa438, 0xb463 }, { 0xa438, 0xe0b4 }, { 0xa438, 0x62e1 }, { 0xa438, 0xb463 }, { 0xa438, 0x6901 }, { 0xa438, 0xe4b4 }, { 0xa438, 0x62e5 }, { 0xa438 , 0xb463 }, { 0xa438, 0xfc04 }, { 0xa436, 0xb85e }, { 0xa438, 0x03b3 }, { 0xa436, 0xb860 }, { 0xa438, 0xffff }, { 0xa436, 0xb862 }, { 0xa438, 0xffff }, { 0xa436, 0xb864 }, { 0xa438, 0xffff } , { 0xa436, 0xb878 }, { 0xa438, 0x0001 } | |||
127 | }, rtl8125_mac_cfg4_mcu[] = { | |||
128 | RTL8125_MAC_CFG4_MCU{ 0xa436, 0x8024 }, { 0xa438, 0x3700 }, { 0xa436, 0xb82e }, { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, { 0xa438 , 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x8025 }, { 0xa438, 0x1800 }, { 0xa438, 0x803a } , { 0xa438, 0x1800 }, { 0xa438, 0x8044 }, { 0xa438, 0x1800 }, { 0xa438, 0x8083 }, { 0xa438, 0x1800 }, { 0xa438, 0x808d }, { 0xa438, 0x1800 }, { 0xa438, 0x808d }, { 0xa438, 0x1800 }, { 0xa438 , 0x808d }, { 0xa438, 0xd712 }, { 0xa438, 0x4077 }, { 0xa438, 0xd71e }, { 0xa438, 0x4159 }, { 0xa438, 0xd71e }, { 0xa438, 0x6099 }, { 0xa438, 0x7f44 }, { 0xa438, 0x1800 }, { 0xa438, 0x1a14 } , { 0xa438, 0x9040 }, { 0xa438, 0x9201 }, { 0xa438, 0x1800 }, { 0xa438, 0x1b1a }, { 0xa438, 0xd71e }, { 0xa438, 0x2425 }, { 0xa438, 0x1a14 }, { 0xa438, 0xd71f }, { 0xa438, 0x3ce5 }, { 0xa438 , 0x1afb }, { 0xa438, 0x1800 }, { 0xa438, 0x1b00 }, { 0xa438, 0xd712 }, { 0xa438, 0x4077 }, { 0xa438, 0xd71e }, { 0xa438, 0x4159 }, { 0xa438, 0xd71e }, { 0xa438, 0x60b9 }, { 0xa438, 0x2421 } , { 0xa438, 0x1c17 }, { 0xa438, 0x1800 }, { 0xa438, 0x1a14 }, { 0xa438, 0x9040 }, { 0xa438, 0x1800 }, { 0xa438, 0x1c2c }, { 0xa438, 0xd71e }, { 0xa438, 0x2425 }, { 0xa438, 0x1a14 }, { 0xa438 , 0xd71f }, { 0xa438, 0x3ce5 }, { 0xa438, 0x1c0f }, { 0xa438, 0x1800 }, { 0xa438, 0x1c13 }, { 0xa438, 0xd702 }, { 0xa438, 0xd501 }, { 0xa438, 0x6072 }, { 0xa438, 0x8401 }, { 0xa438, 0xf002 } , { 0xa438, 0xa401 }, { 0xa438, 0x1000 }, { 0xa438, 0x146e }, { 0xa438, 0x1800 }, { 0xa438, 0x0b77 }, { 0xa438, 0xd703 }, { 0xa438, 0x665d }, { 0xa438, 0x653e }, { 0xa438, 0x641f }, { 0xa438 , 0xd700 }, { 0xa438, 0x62c4 }, { 0xa438, 0x6185 }, { 0xa438, 0x6066 }, { 0xa438, 0x1800 }, { 0xa438, 0x165a }, { 0xa438, 0xc101 }, { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 } , { 0xa438, 0xd700 }, { 0xa438, 0x7fa6 }, { 0xa438, 0x1800 }, { 0xa438, 0x807d }, { 0xa438, 0xc102 }, { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 }, { 0xa438, 0xd700 }, { 0xa438 , 0x2569 }, { 0xa438, 0x8058 }, { 0xa438, 0x1800 }, { 0xa438, 0x807d }, { 0xa438, 0xc104 }, { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 }, { 0xa438, 0xd700 }, { 0xa438, 0x7fa4 } , { 0xa438, 0x1800 }, { 0xa438, 0x807d }, { 0xa438, 0xc120 }, { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 }, { 0xa438, 0xd703 }, { 0xa438, 0x7fbf }, { 0xa438, 0x1800 }, { 0xa438 , 0x807d }, { 0xa438, 0xc140 }, { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 }, { 0xa438, 0xd703 }, { 0xa438, 0x7fbe }, { 0xa438, 0x1800 }, { 0xa438, 0x807d }, { 0xa438, 0xc180 } , { 0xa438, 0xcb00 }, { 0xa438, 0x1000 }, { 0xa438, 0x1945 }, { 0xa438, 0xd703 }, { 0xa438, 0x7fbd }, { 0xa438, 0xc100 }, { 0xa438, 0xcb00 }, { 0xa438, 0xd708 }, { 0xa438, 0x6018 }, { 0xa438 , 0x1800 }, { 0xa438, 0x165a }, { 0xa438, 0x1000 }, { 0xa438, 0x14f6 }, { 0xa438, 0xd014 }, { 0xa438, 0xd1e3 }, { 0xa438, 0x1000 }, { 0xa438, 0x1356 }, { 0xa438, 0xd705 }, { 0xa438, 0x5fbe } , { 0xa438, 0x1800 }, { 0xa438, 0x1559 }, { 0xa436, 0xa026 }, { 0xa438, 0xffff }, { 0xa436, 0xa024 }, { 0xa438, 0xffff }, { 0xa436, 0xa022 }, { 0xa438, 0xffff }, { 0xa436, 0xa020 }, { 0xa438 , 0x1557 }, { 0xa436, 0xa006 }, { 0xa438, 0x1677 }, { 0xa436, 0xa004 }, { 0xa438, 0x0b75 }, { 0xa436, 0xa002 }, { 0xa438, 0x1c17 }, { 0xa436, 0xa000 }, { 0xa438, 0x1b04 }, { 0xa436, 0xa008 } , { 0xa438, 0x1f00 }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438 , 0x817f }, { 0xa438, 0x1800 }, { 0xa438, 0x82ab }, { 0xa438, 0x1800 }, { 0xa438, 0x83f8 }, { 0xa438, 0x1800 }, { 0xa438, 0x8444 }, { 0xa438, 0x1800 }, { 0xa438, 0x8454 }, { 0xa438, 0x1800 } , { 0xa438, 0x8459 }, { 0xa438, 0x1800 }, { 0xa438, 0x8465 }, { 0xa438, 0xcb11 }, { 0xa438, 0xa50c }, { 0xa438, 0x8310 }, { 0xa438, 0xd701 }, { 0xa438, 0x4076 }, { 0xa438, 0x0c03 }, { 0xa438 , 0x0903 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d00 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d } , { 0xa438, 0x1000 }, { 0xa438, 0x0a4d }, { 0xa438, 0xcb12 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f84 }, { 0xa438, 0xd102 }, { 0xa438, 0xd040 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xd701 }, { 0xa438, 0x60f3 }, { 0xa438, 0xd413 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xd410 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xcb13 }, { 0xa438, 0xa108 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8108 }, { 0xa438, 0xa00a }, { 0xa438, 0xa910 }, { 0xa438 , 0xa780 }, { 0xa438, 0xd14a }, { 0xa438, 0xd048 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd701 }, { 0xa438, 0x6255 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f74 }, { 0xa438, 0x6326 } , { 0xa438, 0xd702 }, { 0xa438, 0x5f07 }, { 0xa438, 0x800a }, { 0xa438, 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0902 }, { 0xa438, 0xffe2 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fab }, { 0xa438, 0xba08 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8b }, { 0xa438, 0x9a08 }, { 0xa438, 0x800a }, { 0xa438, 0xd702 }, { 0xa438, 0x6535 }, { 0xa438, 0xd40d }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xcb14 }, { 0xa438, 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 } , { 0xa438, 0x8001 }, { 0xa438, 0xa00a }, { 0xa438, 0xa780 }, { 0xa438, 0xd14a }, { 0xa438, 0xd048 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438 , 0x6206 }, { 0xa438, 0xd702 }, { 0xa438, 0x5f47 }, { 0xa438, 0x800a }, { 0xa438, 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0902 }, { 0xa438, 0x1800 }, { 0xa438, 0x8064 }, { 0xa438, 0x800a }, { 0xa438, 0xd40e }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a37 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f } , { 0xa438, 0x7f8c }, { 0xa438, 0xd701 }, { 0xa438, 0x6073 }, { 0xa438, 0xd701 }, { 0xa438, 0x4216 }, { 0xa438, 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438 , 0xa001 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0xd120 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 } , { 0xa438, 0x8504 }, { 0xa438, 0xcb21 }, { 0xa438, 0xa301 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5f9f }, { 0xa438, 0x8301 }, { 0xa438, 0xd704 }, { 0xa438 , 0x40e0 }, { 0xa438, 0xd196 }, { 0xa438, 0xd04d }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xcb22 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a6d } , { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0xa640 }, { 0xa438, 0x9503 }, { 0xa438, 0x8910 }, { 0xa438, 0x8720 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438 , 0x0d01 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d01 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0x0c1f }, { 0xa438, 0x0f14 }, { 0xa438, 0xcb23 }, { 0xa438, 0x8fc0 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0xaf40 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0x0cc0 }, { 0xa438, 0x0f80 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438 , 0xafc0 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd701 }, { 0xa438, 0x5dee }, { 0xa438, 0xcb24 }, { 0xa438, 0x8f1f }, { 0xa438, 0x1000 } , { 0xa438, 0x0a5e }, { 0xa438, 0xd701 }, { 0xa438, 0x7f6e }, { 0xa438, 0xa111 }, { 0xa438, 0xa215 }, { 0xa438, 0xa401 }, { 0xa438, 0x8404 }, { 0xa438, 0xa720 }, { 0xa438, 0xcb25 }, { 0xa438 , 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8640 }, { 0xa438, 0x9503 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b43 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b86 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e } , { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438 , 0x7f8c }, { 0xa438, 0xcb26 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f82 }, { 0xa438, 0x8111 }, { 0xa438, 0x8205 }, { 0xa438, 0x8404 }, { 0xa438, 0xcb27 } , { 0xa438, 0xd404 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438 , 0x0d02 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0xa710 }, { 0xa438, 0xa104 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8104 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0xa120 }, { 0xa438, 0xaa0f }, { 0xa438, 0x8110 }, { 0xa438, 0xa284 }, { 0xa438, 0xa404 }, { 0xa438, 0xa00a }, { 0xa438, 0xd193 }, { 0xa438 , 0xd046 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xcb28 }, { 0xa438, 0xa110 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 } , { 0xa438, 0x5fa8 }, { 0xa438, 0x8110 }, { 0xa438, 0x8284 }, { 0xa438, 0xa404 }, { 0xa438, 0x800a }, { 0xa438, 0x8710 }, { 0xa438, 0xb804 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438 , 0xd71f }, { 0xa438, 0x7f82 }, { 0xa438, 0x9804 }, { 0xa438, 0xcb29 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f85 }, { 0xa438, 0xa710 }, { 0xa438, 0xb820 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f65 }, { 0xa438, 0x9820 }, { 0xa438, 0xcb2a }, { 0xa438, 0xa190 }, { 0xa438, 0xa284 }, { 0xa438, 0xa404 }, { 0xa438 , 0xa00a }, { 0xa438, 0xd13d }, { 0xa438, 0xd04a }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x3444 }, { 0xa438, 0x8149 }, { 0xa438, 0xa220 }, { 0xa438, 0xd1a0 } , { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x3444 }, { 0xa438, 0x8151 }, { 0xa438, 0xd702 }, { 0xa438, 0x5f51 }, { 0xa438, 0xcb2f }, { 0xa438 , 0xa302 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd708 }, { 0xa438, 0x5f63 }, { 0xa438, 0xd411 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0x8302 }, { 0xa438, 0xd409 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fa3 }, { 0xa438, 0x8190 }, { 0xa438, 0x82a4 }, { 0xa438, 0x8404 } , { 0xa438, 0x800a }, { 0xa438, 0xb808 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7fa3 }, { 0xa438, 0x9808 }, { 0xa438, 0x1800 }, { 0xa438, 0x0433 }, { 0xa438 , 0xcb15 }, { 0xa438, 0xa508 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d01 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d01 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a7d }, { 0xa438, 0x1000 }, { 0xa438, 0x0a4d }, { 0xa438, 0xa301 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5f9f }, { 0xa438, 0x8301 }, { 0xa438 , 0xd704 }, { 0xa438, 0x40e0 }, { 0xa438, 0xd115 }, { 0xa438, 0xd04f }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xd413 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a37 }, { 0xa438, 0xcb16 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a6d }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0xa640 }, { 0xa438, 0x9503 }, { 0xa438, 0x8720 }, { 0xa438 , 0xd17a }, { 0xa438, 0xd04c }, { 0xa438, 0x0c1f }, { 0xa438, 0x0f14 }, { 0xa438, 0xcb17 }, { 0xa438, 0x8fc0 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0xaf40 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a25 }, { 0xa438, 0x0cc0 }, { 0xa438, 0x0f80 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0xafc0 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a25 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd701 }, { 0xa438, 0x61ce }, { 0xa438, 0xd700 }, { 0xa438, 0x5db4 }, { 0xa438, 0xcb18 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8640 }, { 0xa438, 0x9503 } , { 0xa438, 0xa720 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b43 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xffd6 }, { 0xa438, 0x8f1f }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438 , 0xd701 }, { 0xa438, 0x7f8e }, { 0xa438, 0xa131 }, { 0xa438, 0xaa0f }, { 0xa438, 0xa2d5 }, { 0xa438, 0xa407 }, { 0xa438, 0xa720 }, { 0xa438, 0x8310 }, { 0xa438, 0xa308 }, { 0xa438, 0x8308 } , { 0xa438, 0xcb19 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8640 }, { 0xa438, 0x9503 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b43 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b86 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e } , { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0xcb1a }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f82 }, { 0xa438, 0x8111 }, { 0xa438, 0x82c5 }, { 0xa438 , 0xa404 }, { 0xa438, 0x8402 }, { 0xa438, 0xb804 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f82 }, { 0xa438, 0x9804 }, { 0xa438, 0xcb1b }, { 0xa438, 0x1000 } , { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f85 }, { 0xa438, 0xa710 }, { 0xa438, 0xb820 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f65 }, { 0xa438 , 0x9820 }, { 0xa438, 0xcb1c }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a7d }, { 0xa438, 0xa110 }, { 0xa438, 0xa284 }, { 0xa438, 0xa404 }, { 0xa438, 0x8402 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa8 }, { 0xa438 , 0xcb1d }, { 0xa438, 0xa180 }, { 0xa438, 0xa402 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa8 }, { 0xa438, 0xa220 }, { 0xa438, 0xd1f5 }, { 0xa438, 0xd049 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x3444 }, { 0xa438, 0x8221 }, { 0xa438, 0xd702 }, { 0xa438, 0x5f51 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e } , { 0xa438, 0xd71f }, { 0xa438, 0x5fa3 }, { 0xa438, 0xa504 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d00 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438 , 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0xa00a }, { 0xa438, 0x8190 }, { 0xa438, 0x82a4 }, { 0xa438, 0x8402 }, { 0xa438, 0xa404 }, { 0xa438, 0xb808 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7fa3 }, { 0xa438, 0x9808 }, { 0xa438, 0xcb2b }, { 0xa438, 0xcb2c }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438 , 0x5f84 }, { 0xa438, 0xd14a }, { 0xa438, 0xd048 }, { 0xa438, 0xa780 }, { 0xa438, 0xcb2d }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5f94 }, { 0xa438, 0x6208 } , { 0xa438, 0xd702 }, { 0xa438, 0x5f27 }, { 0xa438, 0x800a }, { 0xa438, 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0902 }, { 0xa438, 0xa00a }, { 0xa438, 0xffe9 }, { 0xa438, 0xcb2e }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438, 0x0c1f } , { 0xa438, 0x0d02 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0xa190 }, { 0xa438, 0xa284 }, { 0xa438, 0xa406 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa8 }, { 0xa438, 0xa220 }, { 0xa438, 0xd1a0 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 } , { 0xa438, 0x3444 }, { 0xa438, 0x827d }, { 0xa438, 0xd702 }, { 0xa438, 0x5f51 }, { 0xa438, 0xcb2f }, { 0xa438, 0xa302 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd708 }, { 0xa438 , 0x5f63 }, { 0xa438, 0xd411 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0x8302 }, { 0xa438, 0xd409 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fa3 }, { 0xa438, 0x8190 }, { 0xa438, 0x82a4 }, { 0xa438, 0x8406 }, { 0xa438, 0x800a }, { 0xa438, 0xb808 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e } , { 0xa438, 0xd71f }, { 0xa438, 0x7fa3 }, { 0xa438, 0x9808 }, { 0xa438, 0x1800 }, { 0xa438, 0x0433 }, { 0xa438, 0xcb30 }, { 0xa438, 0x8380 }, { 0xa438, 0xcb31 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f86 }, { 0xa438, 0x9308 }, { 0xa438, 0xb204 }, { 0xa438, 0xb301 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd701 }, { 0xa438, 0x5fa2 } , { 0xa438, 0xb302 }, { 0xa438, 0x9204 }, { 0xa438, 0xcb32 }, { 0xa438, 0xd408 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xd141 }, { 0xa438, 0xd043 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xd704 }, { 0xa438, 0x4ccc }, { 0xa438, 0xd700 }, { 0xa438, 0x4c81 }, { 0xa438, 0xd702 }, { 0xa438, 0x609e }, { 0xa438, 0xd1e5 } , { 0xa438, 0xd04d }, { 0xa438, 0xf003 }, { 0xa438, 0xd1e5 }, { 0xa438, 0xd04d }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xd700 }, { 0xa438 , 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d01 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d01 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0x8710 }, { 0xa438, 0xa108 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8108 }, { 0xa438, 0xa203 }, { 0xa438, 0x8120 }, { 0xa438, 0x8a0f }, { 0xa438, 0xa111 }, { 0xa438, 0x8204 }, { 0xa438, 0xa140 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8140 }, { 0xa438, 0xd17a }, { 0xa438, 0xd04b }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xa204 } , { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa7 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438 , 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0xd404 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 } , { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0xa710 }, { 0xa438, 0x8101 }, { 0xa438 , 0x8201 }, { 0xa438, 0xa104 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8104 }, { 0xa438, 0xa120 }, { 0xa438, 0xaa0f }, { 0xa438, 0x8110 }, { 0xa438, 0xa284 }, { 0xa438, 0xa404 } , { 0xa438, 0xa00a }, { 0xa438, 0xd193 }, { 0xa438, 0xd047 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xa110 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa8 }, { 0xa438, 0xa180 }, { 0xa438, 0xd13d }, { 0xa438, 0xd04a }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 } , { 0xa438, 0xf024 }, { 0xa438, 0xa710 }, { 0xa438, 0xa00a }, { 0xa438, 0x8190 }, { 0xa438, 0x8204 }, { 0xa438, 0xa280 }, { 0xa438, 0xa404 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438 , 0xd700 }, { 0xa438, 0x5fa7 }, { 0xa438, 0x8710 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0x800a }, { 0xa438, 0x8190 }, { 0xa438, 0x8284 }, { 0xa438, 0x8406 }, { 0xa438, 0xd700 }, { 0xa438, 0x4121 }, { 0xa438 , 0xd701 }, { 0xa438, 0x60f3 }, { 0xa438, 0xd1e5 }, { 0xa438, 0xd04d }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x8710 }, { 0xa438, 0xa00a } , { 0xa438, 0x8190 }, { 0xa438, 0x8204 }, { 0xa438, 0xa280 }, { 0xa438, 0xa404 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5fac }, { 0xa438 , 0x9920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f8c }, { 0xa438, 0xcb33 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x5f85 } , { 0xa438, 0xa710 }, { 0xa438, 0xb820 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd71f }, { 0xa438, 0x7f65 }, { 0xa438, 0x9820 }, { 0xa438, 0xcb34 }, { 0xa438, 0xa00a }, { 0xa438 , 0xa190 }, { 0xa438, 0xa284 }, { 0xa438, 0xa404 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa9 }, { 0xa438, 0xd701 }, { 0xa438, 0x6853 }, { 0xa438, 0xd700 } , { 0xa438, 0x6083 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d00 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0x8190 }, { 0xa438 , 0x8284 }, { 0xa438, 0xcb35 }, { 0xa438, 0xd407 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0x8110 }, { 0xa438, 0x8204 }, { 0xa438, 0xa280 }, { 0xa438, 0xa00a }, { 0xa438, 0xd704 } , { 0xa438, 0x4215 }, { 0xa438, 0xa304 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb8 }, { 0xa438, 0xd1c3 }, { 0xa438, 0xd043 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x8304 }, { 0xa438, 0xd700 }, { 0xa438, 0x4109 }, { 0xa438, 0xf01e }, { 0xa438, 0xcb36 }, { 0xa438, 0xd412 }, { 0xa438, 0x1000 } , { 0xa438, 0x0a37 }, { 0xa438, 0xd700 }, { 0xa438, 0x6309 }, { 0xa438, 0xd702 }, { 0xa438, 0x42c7 }, { 0xa438, 0x800a }, { 0xa438, 0x8180 }, { 0xa438, 0x8280 }, { 0xa438, 0x8404 }, { 0xa438 , 0xa004 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a42 }, { 0xa438, 0x8001 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0902 } , { 0xa438, 0xa00a }, { 0xa438, 0xd14a }, { 0xa438, 0xd048 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xd700 }, { 0xa438, 0x6083 }, { 0xa438 , 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0xf003 }, { 0xa438, 0x0c1f }, { 0xa438, 0x0d02 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a7d }, { 0xa438, 0xcc55 }, { 0xa438, 0xcb37 }, { 0xa438, 0xa00a } , { 0xa438, 0xa190 }, { 0xa438, 0xa2a4 }, { 0xa438, 0xa404 }, { 0xa438, 0xd700 }, { 0xa438, 0x6041 }, { 0xa438, 0xa402 }, { 0xa438, 0xd13d }, { 0xa438, 0xd04a }, { 0xa438, 0x1000 }, { 0xa438 , 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fa9 }, { 0xa438, 0xd702 }, { 0xa438, 0x5f71 }, { 0xa438, 0xcb38 } , { 0xa438, 0x8224 }, { 0xa438, 0xa288 }, { 0xa438, 0x8180 }, { 0xa438, 0xa110 }, { 0xa438, 0xa404 }, { 0xa438, 0x800a }, { 0xa438, 0xd700 }, { 0xa438, 0x6041 }, { 0xa438, 0x8402 }, { 0xa438 , 0xd415 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a37 }, { 0xa438, 0xd13d }, { 0xa438, 0xd04a }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0xcb39 } , { 0xa438, 0xa00a }, { 0xa438, 0xa190 }, { 0xa438, 0xa2a0 }, { 0xa438, 0xa404 }, { 0xa438, 0xd700 }, { 0xa438, 0x6041 }, { 0xa438, 0xa402 }, { 0xa438, 0xd17a }, { 0xa438, 0xd047 }, { 0xa438 , 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x1800 }, { 0xa438, 0x0560 }, { 0xa438, 0xa111 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 } , { 0xa438, 0x0000 }, { 0xa438, 0xd3f5 }, { 0xa438, 0xd219 }, { 0xa438, 0x1000 }, { 0xa438, 0x0c31 }, { 0xa438, 0xd708 }, { 0xa438, 0x5fa5 }, { 0xa438, 0xa215 }, { 0xa438, 0xd30e }, { 0xa438 , 0xd21a }, { 0xa438, 0x1000 }, { 0xa438, 0x0c31 }, { 0xa438, 0xd708 }, { 0xa438, 0x63e9 }, { 0xa438, 0xd708 }, { 0xa438, 0x5f65 }, { 0xa438, 0xd708 }, { 0xa438, 0x7f36 }, { 0xa438, 0xa004 } , { 0xa438, 0x1000 }, { 0xa438, 0x0c35 }, { 0xa438, 0x8004 }, { 0xa438, 0xa001 }, { 0xa438, 0x1000 }, { 0xa438, 0x0c35 }, { 0xa438, 0x8001 }, { 0xa438, 0xd708 }, { 0xa438, 0x4098 }, { 0xa438 , 0xd102 }, { 0xa438, 0x9401 }, { 0xa438, 0xf003 }, { 0xa438, 0xd103 }, { 0xa438, 0xb401 }, { 0xa438, 0x1000 }, { 0xa438, 0x0c27 }, { 0xa438, 0xa108 }, { 0xa438, 0x1000 }, { 0xa438, 0x0c35 } , { 0xa438, 0x8108 }, { 0xa438, 0x8110 }, { 0xa438, 0x8294 }, { 0xa438, 0xa202 }, { 0xa438, 0x1800 }, { 0xa438, 0x0bdb }, { 0xa438, 0xd39c }, { 0xa438, 0xd210 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0c31 }, { 0xa438, 0xd708 }, { 0xa438, 0x5fa5 }, { 0xa438, 0xd39c }, { 0xa438, 0xd210 }, { 0xa438, 0x1000 }, { 0xa438, 0x0c31 }, { 0xa438, 0xd708 }, { 0xa438, 0x5fa5 }, { 0xa438, 0x1000 } , { 0xa438, 0x0c31 }, { 0xa438, 0xd708 }, { 0xa438, 0x29b5 }, { 0xa438, 0x840e }, { 0xa438, 0xd708 }, { 0xa438, 0x5f4a }, { 0xa438, 0x0c1f }, { 0xa438, 0x1014 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0c31 }, { 0xa438, 0xd709 }, { 0xa438, 0x7fa4 }, { 0xa438, 0x901f }, { 0xa438, 0x1800 }, { 0xa438, 0x0c23 }, { 0xa438, 0xcb43 }, { 0xa438, 0xa508 }, { 0xa438, 0xd701 }, { 0xa438, 0x3699 } , { 0xa438, 0x844a }, { 0xa438, 0xa504 }, { 0xa438, 0xa190 }, { 0xa438, 0xa2a0 }, { 0xa438, 0xa404 }, { 0xa438, 0xa00a }, { 0xa438, 0xd700 }, { 0xa438, 0x2109 }, { 0xa438, 0x05ea }, { 0xa438 , 0xa402 }, { 0xa438, 0x1800 }, { 0xa438, 0x05ea }, { 0xa438, 0xcb90 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0ca0 }, { 0xa438, 0x1800 }, { 0xa438, 0x06db }, { 0xa438, 0xd1ff }, { 0xa438, 0xd052 } , { 0xa438, 0xa508 }, { 0xa438, 0x8718 }, { 0xa438, 0xa00a }, { 0xa438, 0xa190 }, { 0xa438, 0xa2a0 }, { 0xa438, 0xa404 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0c50 }, { 0xa438, 0x1800 }, { 0xa438 , 0x09ef }, { 0xa438, 0x1000 }, { 0xa438, 0x0a5e }, { 0xa438, 0xd704 }, { 0xa438, 0x2e70 }, { 0xa438, 0x06da }, { 0xa438, 0xd700 }, { 0xa438, 0x5f55 }, { 0xa438, 0xa90c }, { 0xa438, 0x1800 } , { 0xa438, 0x0645 }, { 0xa436, 0xa10e }, { 0xa438, 0x0644 }, { 0xa436, 0xa10c }, { 0xa438, 0x09e9 }, { 0xa436, 0xa10a }, { 0xa438, 0x06da }, { 0xa436, 0xa108 }, { 0xa438, 0x05e1 }, { 0xa436 , 0xa106 }, { 0xa438, 0x0be4 }, { 0xa436, 0xa104 }, { 0xa438, 0x0435 }, { 0xa436, 0xa102 }, { 0xa438, 0x0141 }, { 0xa436, 0xa100 }, { 0xa438, 0x026d }, { 0xa436, 0xa110 }, { 0xa438, 0x00ff } , { 0xa436, 0xb87c }, { 0xa438, 0x85fe }, { 0xa436, 0xb87e }, { 0xa438, 0xaf86 }, { 0xa438, 0x16af }, { 0xa438, 0x8699 }, { 0xa438, 0xaf86 }, { 0xa438, 0xe5af }, { 0xa438, 0x86f9 }, { 0xa438 , 0xaf87 }, { 0xa438, 0x7aaf }, { 0xa438, 0x883a }, { 0xa438, 0xaf88 }, { 0xa438, 0x58af }, { 0xa438, 0x8b6c }, { 0xa438, 0xd48b }, { 0xa438, 0x7c02 }, { 0xa438, 0x8644 }, { 0xa438, 0x2c00 } , { 0xa438, 0x503c }, { 0xa438, 0xffd6 }, { 0xa438, 0xac27 }, { 0xa438, 0x18e1 }, { 0xa438, 0x82fe }, { 0xa438, 0xad28 }, { 0xa438, 0x0cd4 }, { 0xa438, 0x8b84 }, { 0xa438, 0x0286 }, { 0xa438 , 0x442c }, { 0xa438, 0x003c }, { 0xa438, 0xac27 }, { 0xa438, 0x06ee }, { 0xa438, 0x8299 }, { 0xa438, 0x01ae }, { 0xa438, 0x04ee }, { 0xa438, 0x8299 }, { 0xa438, 0x00af }, { 0xa438, 0x23dc } , { 0xa438, 0xf9fa }, { 0xa438, 0xcefa }, { 0xa438, 0xfbef }, { 0xa438, 0x79fb }, { 0xa438, 0xc4bf }, { 0xa438, 0x8b76 }, { 0xa438, 0x026c }, { 0xa438, 0x6dac }, { 0xa438, 0x2804 }, { 0xa438 , 0xd203 }, { 0xa438, 0xae02 }, { 0xa438, 0xd201 }, { 0xa438, 0xbdd8 }, { 0xa438, 0x19d9 }, { 0xa438, 0xef94 }, { 0xa438, 0x026c }, { 0xa438, 0x6d78 }, { 0xa438, 0x03ef }, { 0xa438, 0x648a } , { 0xa438, 0x0002 }, { 0xa438, 0xbdd8 }, { 0xa438, 0x19d9 }, { 0xa438, 0xef94 }, { 0xa438, 0x026c }, { 0xa438, 0x6d78 }, { 0xa438, 0x03ef }, { 0xa438, 0x7402 }, { 0xa438, 0x72cd }, { 0xa438 , 0xac50 }, { 0xa438, 0x02ef }, { 0xa438, 0x643a }, { 0xa438, 0x019f }, { 0xa438, 0xe4ef }, { 0xa438, 0x4678 }, { 0xa438, 0x03ac }, { 0xa438, 0x2002 }, { 0xa438, 0xae02 }, { 0xa438, 0xd0ff } , { 0xa438, 0xffef }, { 0xa438, 0x97ff }, { 0xa438, 0xfec6 }, { 0xa438, 0xfefd }, { 0xa438, 0x041f }, { 0xa438, 0x771f }, { 0xa438, 0x221c }, { 0xa438, 0x450d }, { 0xa438, 0x481f }, { 0xa438 , 0x00ac }, { 0xa438, 0x7f04 }, { 0xa438, 0x1a94 }, { 0xa438, 0xae08 }, { 0xa438, 0x1a94 }, { 0xa438, 0xac7f }, { 0xa438, 0x03d7 }, { 0xa438, 0x0100 }, { 0xa438, 0xef46 }, { 0xa438, 0x0d48 } , { 0xa438, 0x1f00 }, { 0xa438, 0x1c45 }, { 0xa438, 0xef69 }, { 0xa438, 0xef57 }, { 0xa438, 0xef74 }, { 0xa438, 0x0272 }, { 0xa438, 0xe8a7 }, { 0xa438, 0xffff }, { 0xa438, 0x0d1a }, { 0xa438 , 0x941b }, { 0xa438, 0x979e }, { 0xa438, 0x072d }, { 0xa438, 0x0100 }, { 0xa438, 0x1a64 }, { 0xa438, 0xef76 }, { 0xa438, 0xef97 }, { 0xa438, 0x0d98 }, { 0xa438, 0xd400 }, { 0xa438, 0xff1d } , { 0xa438, 0x941a }, { 0xa438, 0x89cf }, { 0xa438, 0x1a75 }, { 0xa438, 0xaf74 }, { 0xa438, 0xf9bf }, { 0xa438, 0x8b79 }, { 0xa438, 0x026c }, { 0xa438, 0x6da1 }, { 0xa438, 0x0005 }, { 0xa438 , 0xe180 }, { 0xa438, 0xa0ae }, { 0xa438, 0x03e1 }, { 0xa438, 0x80a1 }, { 0xa438, 0xaf26 }, { 0xa438, 0x9aac }, { 0xa438, 0x284d }, { 0xa438, 0xe08f }, { 0xa438, 0xffef }, { 0xa438, 0x10c0 } , { 0xa438, 0xe08f }, { 0xa438, 0xfe10 }, { 0xa438, 0x1b08 }, { 0xa438, 0xa000 }, { 0xa438, 0x04c8 }, { 0xa438, 0xaf40 }, { 0xa438, 0x67c8 }, { 0xa438, 0xbf8b }, { 0xa438, 0x8c02 }, { 0xa438 , 0x6c4e }, { 0xa438, 0xc4bf }, { 0xa438, 0x8b8f }, { 0xa438, 0x026c }, { 0xa438, 0x6def }, { 0xa438, 0x74e0 }, { 0xa438, 0x830c }, { 0xa438, 0xad20 }, { 0xa438, 0x0302 }, { 0xa438, 0x74ac } , { 0xa438, 0xccef }, { 0xa438, 0x971b }, { 0xa438, 0x76ad }, { 0xa438, 0x5f02 }, { 0xa438, 0xae13 }, { 0xa438, 0xef69 }, { 0xa438, 0xef30 }, { 0xa438, 0x1b32 }, { 0xa438, 0xc4ef }, { 0xa438 , 0x46e4 }, { 0xa438, 0x8ffb }, { 0xa438, 0xe58f }, { 0xa438, 0xfce7 }, { 0xa438, 0x8ffd }, { 0xa438, 0xcc10 }, { 0xa438, 0x11ae }, { 0xa438, 0xb8d1 }, { 0xa438, 0x00a1 }, { 0xa438, 0x1f03 } , { 0xa438, 0xaf40 }, { 0xa438, 0x4fbf }, { 0xa438, 0x8b8c }, { 0xa438, 0x026c }, { 0xa438, 0x4ec4 }, { 0xa438, 0xbf8b }, { 0xa438, 0x8f02 }, { 0xa438, 0x6c6d }, { 0xa438, 0xef74 }, { 0xa438 , 0xe083 }, { 0xa438, 0x0cad }, { 0xa438, 0x2003 }, { 0xa438, 0x0274 }, { 0xa438, 0xaccc }, { 0xa438, 0xef97 }, { 0xa438, 0x1b76 }, { 0xa438, 0xad5f }, { 0xa438, 0x02ae }, { 0xa438, 0x04ef } , { 0xa438, 0x69ef }, { 0xa438, 0x3111 }, { 0xa438, 0xaed1 }, { 0xa438, 0x0287 }, { 0xa438, 0x80af }, { 0xa438, 0x2293 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xfafb }, { 0xa438, 0xef59 }, { 0xa438 , 0xe080 }, { 0xa438, 0x13ad }, { 0xa438, 0x252f }, { 0xa438, 0xbf88 }, { 0xa438, 0x2802 }, { 0xa438, 0x6c6d }, { 0xa438, 0xef64 }, { 0xa438, 0x1f44 }, { 0xa438, 0xe18f }, { 0xa438, 0xb91b } , { 0xa438, 0x64ad }, { 0xa438, 0x4f1d }, { 0xa438, 0xd688 }, { 0xa438, 0x2bd7 }, { 0xa438, 0x882e }, { 0xa438, 0x0274 }, { 0xa438, 0x73ad }, { 0xa438, 0x5008 }, { 0xa438, 0xbf88 }, { 0xa438 , 0x3102 }, { 0xa438, 0x737c }, { 0xa438, 0xae03 }, { 0xa438, 0x0287 }, { 0xa438, 0xd0bf }, { 0xa438, 0x882b }, { 0xa438, 0x0273 }, { 0xa438, 0x73e0 }, { 0xa438, 0x824c }, { 0xa438, 0xf621 } , { 0xa438, 0xe482 }, { 0xa438, 0x4cbf }, { 0xa438, 0x8834 }, { 0xa438, 0x0273 }, { 0xa438, 0x7cef }, { 0xa438, 0x95ff }, { 0xa438, 0xfefd }, { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, { 0xa438 , 0xfafb }, { 0xa438, 0xef79 }, { 0xa438, 0xbf88 }, { 0xa438, 0x1f02 }, { 0xa438, 0x737c }, { 0xa438, 0x1f22 }, { 0xa438, 0xac32 }, { 0xa438, 0x31ef }, { 0xa438, 0x12bf }, { 0xa438, 0x8822 } , { 0xa438, 0x026c }, { 0xa438, 0x4ed6 }, { 0xa438, 0x8fba }, { 0xa438, 0x1f33 }, { 0xa438, 0xac3c }, { 0xa438, 0x1eef }, { 0xa438, 0x13bf }, { 0xa438, 0x8837 }, { 0xa438, 0x026c }, { 0xa438 , 0x4eef }, { 0xa438, 0x96d8 }, { 0xa438, 0x19d9 }, { 0xa438, 0xbf88 }, { 0xa438, 0x2502 }, { 0xa438, 0x6c4e }, { 0xa438, 0xbf88 }, { 0xa438, 0x2502 }, { 0xa438, 0x6c4e }, { 0xa438, 0x1616 } , { 0xa438, 0x13ae }, { 0xa438, 0xdf12 }, { 0xa438, 0xaecc }, { 0xa438, 0xbf88 }, { 0xa438, 0x1f02 }, { 0xa438, 0x7373 }, { 0xa438, 0xef97 }, { 0xa438, 0xfffe }, { 0xa438, 0xfdfc }, { 0xa438 , 0x0466 }, { 0xa438, 0xac88 }, { 0xa438, 0x54ac }, { 0xa438, 0x88f0 }, { 0xa438, 0xac8a }, { 0xa438, 0x92ac }, { 0xa438, 0xbadd }, { 0xa438, 0xac6c }, { 0xa438, 0xeeac }, { 0xa438, 0x6cff } , { 0xa438, 0xad02 }, { 0xa438, 0x99ac }, { 0xa438, 0x0030 }, { 0xa438, 0xac88 }, { 0xa438, 0xd4c3 }, { 0xa438, 0x5000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438 , 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x00b4 }, { 0xa438, 0xecee }, { 0xa438, 0x8298 }, { 0xa438, 0x00af }, { 0xa438, 0x1412 } , { 0xa438, 0xf8bf }, { 0xa438, 0x8b5d }, { 0xa438, 0x026c }, { 0xa438, 0x6d58 }, { 0xa438, 0x03e1 }, { 0xa438, 0x8fb8 }, { 0xa438, 0x2901 }, { 0xa438, 0xe58f }, { 0xa438, 0xb8a0 }, { 0xa438 , 0x0049 }, { 0xa438, 0xef47 }, { 0xa438, 0xe483 }, { 0xa438, 0x02e5 }, { 0xa438, 0x8303 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x5f1a }, { 0xa438, 0x95f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 } , { 0xa438, 0x00d8 }, { 0xa438, 0xf605 }, { 0xa438, 0x1f11 }, { 0xa438, 0xef60 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3002 }, { 0xa438, 0x6c4e }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438 , 0x6c6d }, { 0xa438, 0xf728 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0xf628 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0c64 } , { 0xa438, 0xef46 }, { 0xa438, 0xbf8b }, { 0xa438, 0x6002 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0289 }, { 0xa438, 0x9902 }, { 0xa438, 0x3920 }, { 0xa438, 0xaf89 }, { 0xa438, 0x96a0 }, { 0xa438 , 0x0149 }, { 0xa438, 0xef47 }, { 0xa438, 0xe483 }, { 0xa438, 0x04e5 }, { 0xa438, 0x8305 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x5f1a }, { 0xa438, 0x95f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 } , { 0xa438, 0x00d8 }, { 0xa438, 0xf605 }, { 0xa438, 0x1f11 }, { 0xa438, 0xef60 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3002 }, { 0xa438, 0x6c4e }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438 , 0x6c6d }, { 0xa438, 0xf729 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0xf629 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0c64 } , { 0xa438, 0xef46 }, { 0xa438, 0xbf8b }, { 0xa438, 0x6302 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0289 }, { 0xa438, 0x9902 }, { 0xa438, 0x3920 }, { 0xa438, 0xaf89 }, { 0xa438, 0x96a0 }, { 0xa438 , 0x0249 }, { 0xa438, 0xef47 }, { 0xa438, 0xe483 }, { 0xa438, 0x06e5 }, { 0xa438, 0x8307 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x5f1a }, { 0xa438, 0x95f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 } , { 0xa438, 0x00d8 }, { 0xa438, 0xf605 }, { 0xa438, 0x1f11 }, { 0xa438, 0xef60 }, { 0xa438, 0xbf8b }, { 0xa438, 0x3002 }, { 0xa438, 0x6c4e }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438 , 0x6c6d }, { 0xa438, 0xf72a }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0xf62a }, { 0xa438, 0xbf8b }, { 0xa438, 0x3302 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0c64 } , { 0xa438, 0xef46 }, { 0xa438, 0xbf8b }, { 0xa438, 0x6602 }, { 0xa438, 0x6c4e }, { 0xa438, 0x0289 }, { 0xa438, 0x9902 }, { 0xa438, 0x3920 }, { 0xa438, 0xaf89 }, { 0xa438, 0x96ef }, { 0xa438 , 0x47e4 }, { 0xa438, 0x8308 }, { 0xa438, 0xe583 }, { 0xa438, 0x09bf }, { 0xa438, 0xc25f }, { 0xa438, 0x1a95 }, { 0xa438, 0xf705 }, { 0xa438, 0xeeff }, { 0xa438, 0xd200 }, { 0xa438, 0xd8f6 } , { 0xa438, 0x051f }, { 0xa438, 0x11ef }, { 0xa438, 0x60bf }, { 0xa438, 0x8b30 }, { 0xa438, 0x026c }, { 0xa438, 0x4ebf }, { 0xa438, 0x8b33 }, { 0xa438, 0x026c }, { 0xa438, 0x6df7 }, { 0xa438 , 0x2bbf }, { 0xa438, 0x8b33 }, { 0xa438, 0x026c }, { 0xa438, 0x4ef6 }, { 0xa438, 0x2bbf }, { 0xa438, 0x8b33 }, { 0xa438, 0x026c }, { 0xa438, 0x4e0c }, { 0xa438, 0x64ef }, { 0xa438, 0x46bf } , { 0xa438, 0x8b69 }, { 0xa438, 0x026c }, { 0xa438, 0x4e02 }, { 0xa438, 0x8999 }, { 0xa438, 0x0239 }, { 0xa438, 0x20af }, { 0xa438, 0x8996 }, { 0xa438, 0xaf39 }, { 0xa438, 0x1ef8 }, { 0xa438 , 0xf9fa }, { 0xa438, 0xe08f }, { 0xa438, 0xb838 }, { 0xa438, 0x02ad }, { 0xa438, 0x2702 }, { 0xa438, 0xae03 }, { 0xa438, 0xaf8b }, { 0xa438, 0x201f }, { 0xa438, 0x66ef }, { 0xa438, 0x65bf } , { 0xa438, 0xc21f }, { 0xa438, 0x1a96 }, { 0xa438, 0xf705 }, { 0xa438, 0xeeff }, { 0xa438, 0xd200 }, { 0xa438, 0xdaf6 }, { 0xa438, 0x05bf }, { 0xa438, 0xc22f }, { 0xa438, 0x1a96 }, { 0xa438 , 0xf705 }, { 0xa438, 0xeeff }, { 0xa438, 0xd200 }, { 0xa438, 0xdbf6 }, { 0xa438, 0x05ef }, { 0xa438, 0x021f }, { 0xa438, 0x110d }, { 0xa438, 0x42bf }, { 0xa438, 0x8b3c }, { 0xa438, 0x026c } , { 0xa438, 0x4eef }, { 0xa438, 0x021b }, { 0xa438, 0x031f }, { 0xa438, 0x110d }, { 0xa438, 0x42bf }, { 0xa438, 0x8b36 }, { 0xa438, 0x026c }, { 0xa438, 0x4eef }, { 0xa438, 0x021a }, { 0xa438 , 0x031f }, { 0xa438, 0x110d }, { 0xa438, 0x42bf }, { 0xa438, 0x8b39 }, { 0xa438, 0x026c }, { 0xa438, 0x4ebf }, { 0xa438, 0xc23f }, { 0xa438, 0x1a96 }, { 0xa438, 0xf705 }, { 0xa438, 0xeeff } , { 0xa438, 0xd200 }, { 0xa438, 0xdaf6 }, { 0xa438, 0x05bf }, { 0xa438, 0xc24f }, { 0xa438, 0x1a96 }, { 0xa438, 0xf705 }, { 0xa438, 0xeeff }, { 0xa438, 0xd200 }, { 0xa438, 0xdbf6 }, { 0xa438 , 0x05ef }, { 0xa438, 0x021f }, { 0xa438, 0x110d }, { 0xa438, 0x42bf }, { 0xa438, 0x8b45 }, { 0xa438, 0x026c }, { 0xa438, 0x4eef }, { 0xa438, 0x021b }, { 0xa438, 0x031f }, { 0xa438, 0x110d } , { 0xa438, 0x42bf }, { 0xa438, 0x8b3f }, { 0xa438, 0x026c }, { 0xa438, 0x4eef }, { 0xa438, 0x021a }, { 0xa438, 0x031f }, { 0xa438, 0x110d }, { 0xa438, 0x42bf }, { 0xa438, 0x8b42 }, { 0xa438 , 0x026c }, { 0xa438, 0x4eef }, { 0xa438, 0x56d0 }, { 0xa438, 0x201f }, { 0xa438, 0x11bf }, { 0xa438, 0x8b4e }, { 0xa438, 0x026c }, { 0xa438, 0x4ebf }, { 0xa438, 0x8b48 }, { 0xa438, 0x026c } , { 0xa438, 0x4ebf }, { 0xa438, 0x8b4b }, { 0xa438, 0x026c }, { 0xa438, 0x4ee1 }, { 0xa438, 0x8578 }, { 0xa438, 0xef03 }, { 0xa438, 0x480a }, { 0xa438, 0x2805 }, { 0xa438, 0xef20 }, { 0xa438 , 0x1b01 }, { 0xa438, 0xad27 }, { 0xa438, 0x3f1f }, { 0xa438, 0x44e0 }, { 0xa438, 0x8560 }, { 0xa438, 0xe185 }, { 0xa438, 0x61bf }, { 0xa438, 0x8b51 }, { 0xa438, 0x026c }, { 0xa438, 0x4ee0 } , { 0xa438, 0x8566 }, { 0xa438, 0xe185 }, { 0xa438, 0x67bf }, { 0xa438, 0x8b54 }, { 0xa438, 0x026c }, { 0xa438, 0x4ee0 }, { 0xa438, 0x856c }, { 0xa438, 0xe185 }, { 0xa438, 0x6dbf }, { 0xa438 , 0x8b57 }, { 0xa438, 0x026c }, { 0xa438, 0x4ee0 }, { 0xa438, 0x8572 }, { 0xa438, 0xe185 }, { 0xa438, 0x73bf }, { 0xa438, 0x8b5a }, { 0xa438, 0x026c }, { 0xa438, 0x4ee1 }, { 0xa438, 0x8fb8 } , { 0xa438, 0x5900 }, { 0xa438, 0xf728 }, { 0xa438, 0xe58f }, { 0xa438, 0xb8af }, { 0xa438, 0x8b2c }, { 0xa438, 0xe185 }, { 0xa438, 0x791b }, { 0xa438, 0x21ad }, { 0xa438, 0x373e }, { 0xa438 , 0x1f44 }, { 0xa438, 0xe085 }, { 0xa438, 0x62e1 }, { 0xa438, 0x8563 }, { 0xa438, 0xbf8b }, { 0xa438, 0x5102 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe085 }, { 0xa438, 0x68e1 }, { 0xa438, 0x8569 } , { 0xa438, 0xbf8b }, { 0xa438, 0x5402 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe085 }, { 0xa438, 0x6ee1 }, { 0xa438, 0x856f }, { 0xa438, 0xbf8b }, { 0xa438, 0x5702 }, { 0xa438, 0x6c4e }, { 0xa438 , 0xe085 }, { 0xa438, 0x74e1 }, { 0xa438, 0x8575 }, { 0xa438, 0xbf8b }, { 0xa438, 0x5a02 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe18f }, { 0xa438, 0xb859 }, { 0xa438, 0x00f7 }, { 0xa438, 0x28e5 } , { 0xa438, 0x8fb8 }, { 0xa438, 0xae4a }, { 0xa438, 0x1f44 }, { 0xa438, 0xe085 }, { 0xa438, 0x64e1 }, { 0xa438, 0x8565 }, { 0xa438, 0xbf8b }, { 0xa438, 0x5102 }, { 0xa438, 0x6c4e }, { 0xa438 , 0xe085 }, { 0xa438, 0x6ae1 }, { 0xa438, 0x856b }, { 0xa438, 0xbf8b }, { 0xa438, 0x5402 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe085 }, { 0xa438, 0x70e1 }, { 0xa438, 0x8571 }, { 0xa438, 0xbf8b } , { 0xa438, 0x5702 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe085 }, { 0xa438, 0x76e1 }, { 0xa438, 0x8577 }, { 0xa438, 0xbf8b }, { 0xa438, 0x5a02 }, { 0xa438, 0x6c4e }, { 0xa438, 0xe18f }, { 0xa438 , 0xb859 }, { 0xa438, 0x00f7 }, { 0xa438, 0x28e5 }, { 0xa438, 0x8fb8 }, { 0xa438, 0xae0c }, { 0xa438, 0xe18f }, { 0xa438, 0xb839 }, { 0xa438, 0x04ac }, { 0xa438, 0x2f04 }, { 0xa438, 0xee8f } , { 0xa438, 0xb800 }, { 0xa438, 0xfefd }, { 0xa438, 0xfc04 }, { 0xa438, 0xf0ac }, { 0xa438, 0x8efc }, { 0xa438, 0xac8c }, { 0xa438, 0xf0ac }, { 0xa438, 0xfaf0 }, { 0xa438, 0xacf8 }, { 0xa438 , 0xf0ac }, { 0xa438, 0xf6f0 }, { 0xa438, 0xad00 }, { 0xa438, 0xf0ac }, { 0xa438, 0xfef0 }, { 0xa438, 0xacfc }, { 0xa438, 0xf0ac }, { 0xa438, 0xf4f0 }, { 0xa438, 0xacf2 }, { 0xa438, 0xf0ac } , { 0xa438, 0xf0f0 }, { 0xa438, 0xacb0 }, { 0xa438, 0xf0ac }, { 0xa438, 0xaef0 }, { 0xa438, 0xacac }, { 0xa438, 0xf0ac }, { 0xa438, 0xaaf0 }, { 0xa438, 0xacee }, { 0xa438, 0xf0b0 }, { 0xa438 , 0x24f0 }, { 0xa438, 0xb0a4 }, { 0xa438, 0xf0b1 }, { 0xa438, 0x24f0 }, { 0xa438, 0xb1a4 }, { 0xa438, 0xee8f }, { 0xa438, 0xb800 }, { 0xa438, 0xd400 }, { 0xa438, 0x00af }, { 0xa438, 0x3976 } , { 0xa438, 0x66ac }, { 0xa438, 0xeabb }, { 0xa438, 0xa430 }, { 0xa438, 0x6e50 }, { 0xa438, 0x6e53 }, { 0xa438, 0x6e56 }, { 0xa438, 0x6e59 }, { 0xa438, 0x6e5c }, { 0xa438, 0x6e5f }, { 0xa438 , 0x6e62 }, { 0xa438, 0x6e65 }, { 0xa438, 0xd9ac }, { 0xa438, 0x70f0 }, { 0xa438, 0xac6a }, { 0xa436, 0xb85e }, { 0xa438, 0x23b7 }, { 0xa436, 0xb860 }, { 0xa438, 0x74db }, { 0xa436, 0xb862 } , { 0xa438, 0x268c }, { 0xa436, 0xb864 }, { 0xa438, 0x3fe5 }, { 0xa436, 0xb886 }, { 0xa438, 0x2250 }, { 0xa436, 0xb888 }, { 0xa438, 0x140e }, { 0xa436, 0xb88a }, { 0xa438, 0x3696 }, { 0xa436 , 0xb88c }, { 0xa438, 0x3973 }, { 0xa436, 0xb838 }, { 0xa438, 0x00ff }, { 0xb820, 0x0010 }, { 0xa436, 0x8464 }, { 0xa438, 0xaf84 }, { 0xa438, 0x7caf }, { 0xa438, 0x8485 }, { 0xa438, 0xaf85 } , { 0xa438, 0x13af }, { 0xa438, 0x851e }, { 0xa438, 0xaf85 }, { 0xa438, 0xb9af }, { 0xa438, 0x8684 }, { 0xa438, 0xaf87 }, { 0xa438, 0x01af }, { 0xa438, 0x8701 }, { 0xa438, 0xac38 }, { 0xa438 , 0x03af }, { 0xa438, 0x38bb }, { 0xa438, 0xaf38 }, { 0xa438, 0xc302 }, { 0xa438, 0x4618 }, { 0xa438, 0xbf85 }, { 0xa438, 0x0a02 }, { 0xa438, 0x54b7 }, { 0xa438, 0xbf85 }, { 0xa438, 0x1002 } , { 0xa438, 0x54c0 }, { 0xa438, 0xd400 }, { 0xa438, 0x0fbf }, { 0xa438, 0x8507 }, { 0xa438, 0x024f }, { 0xa438, 0x48bf }, { 0xa438, 0x8504 }, { 0xa438, 0x024f }, { 0xa438, 0x6759 }, { 0xa438 , 0xf0a1 }, { 0xa438, 0x3008 }, { 0xa438, 0xbf85 }, { 0xa438, 0x0d02 }, { 0xa438, 0x54c0 }, { 0xa438, 0xae06 }, { 0xa438, 0xbf85 }, { 0xa438, 0x0d02 }, { 0xa438, 0x54b7 }, { 0xa438, 0xbf85 } , { 0xa438, 0x0402 }, { 0xa438, 0x4f67 }, { 0xa438, 0xa183 }, { 0xa438, 0x02ae }, { 0xa438, 0x15a1 }, { 0xa438, 0x8502 }, { 0xa438, 0xae10 }, { 0xa438, 0x59f0 }, { 0xa438, 0xa180 }, { 0xa438 , 0x16bf }, { 0xa438, 0x8501 }, { 0xa438, 0x024f }, { 0xa438, 0x67a1 }, { 0xa438, 0x381b }, { 0xa438, 0xae0b }, { 0xa438, 0xe18f }, { 0xa438, 0xffbf }, { 0xa438, 0x84fe }, { 0xa438, 0x024f } , { 0xa438, 0x48ae }, { 0xa438, 0x17bf }, { 0xa438, 0x84fe }, { 0xa438, 0x0254 }, { 0xa438, 0xb7bf }, { 0xa438, 0x84fb }, { 0xa438, 0x0254 }, { 0xa438, 0xb7ae }, { 0xa438, 0x09a1 }, { 0xa438 , 0x5006 }, { 0xa438, 0xbf84 }, { 0xa438, 0xfb02 }, { 0xa438, 0x54c0 }, { 0xa438, 0xaf04 }, { 0xa438, 0x4700 }, { 0xa438, 0xad34 }, { 0xa438, 0xfdad }, { 0xa438, 0x0670 }, { 0xa438, 0xae14 } , { 0xa438, 0xf0a6 }, { 0xa438, 0x00b8 }, { 0xa438, 0xbd32 }, { 0xa438, 0x30bd }, { 0xa438, 0x30aa }, { 0xa438, 0xbd2c }, { 0xa438, 0xccbd }, { 0xa438, 0x2ca1 }, { 0xa438, 0x0705 }, { 0xa438 , 0xec80 }, { 0xa438, 0xaf40 }, { 0xa438, 0xf7af }, { 0xa438, 0x40f5 }, { 0xa438, 0xd101 }, { 0xa438, 0xbf85 }, { 0xa438, 0xa402 }, { 0xa438, 0x4f48 }, { 0xa438, 0xbf85 }, { 0xa438, 0xa702 } , { 0xa438, 0x54c0 }, { 0xa438, 0xd10f }, { 0xa438, 0xbf85 }, { 0xa438, 0xaa02 }, { 0xa438, 0x4f48 }, { 0xa438, 0x024d }, { 0xa438, 0x6abf }, { 0xa438, 0x85ad }, { 0xa438, 0x024f }, { 0xa438 , 0x67bf }, { 0xa438, 0x8ff7 }, { 0xa438, 0xddbf }, { 0xa438, 0x85b0 }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438, 0x8ff8 }, { 0xa438, 0xddbf }, { 0xa438, 0x85b3 }, { 0xa438, 0x024f } , { 0xa438, 0x67bf }, { 0xa438, 0x8ff9 }, { 0xa438, 0xddbf }, { 0xa438, 0x85b6 }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438, 0x8ffa }, { 0xa438, 0xddd1 }, { 0xa438, 0x00bf }, { 0xa438 , 0x85aa }, { 0xa438, 0x024f }, { 0xa438, 0x4802 }, { 0xa438, 0x4d6a }, { 0xa438, 0xbf85 }, { 0xa438, 0xad02 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfbdd }, { 0xa438, 0xbf85 } , { 0xa438, 0xb002 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfcdd }, { 0xa438, 0xbf85 }, { 0xa438, 0xb302 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfddd }, { 0xa438 , 0xbf85 }, { 0xa438, 0xb602 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfedd }, { 0xa438, 0xbf85 }, { 0xa438, 0xa702 }, { 0xa438, 0x54b7 }, { 0xa438, 0xbf85 }, { 0xa438, 0xa102 } , { 0xa438, 0x54b7 }, { 0xa438, 0xaf3c }, { 0xa438, 0x2066 }, { 0xa438, 0xb800 }, { 0xa438, 0xb8bd }, { 0xa438, 0x30ee }, { 0xa438, 0xbd2c }, { 0xa438, 0xb8bd }, { 0xa438, 0x7040 }, { 0xa438 , 0xbd86 }, { 0xa438, 0xc8bd }, { 0xa438, 0x8640 }, { 0xa438, 0xbd88 }, { 0xa438, 0xc8bd }, { 0xa438, 0x8802 }, { 0xa438, 0x1929 }, { 0xa438, 0xa202 }, { 0xa438, 0x02ae }, { 0xa438, 0x03a2 } , { 0xa438, 0x032e }, { 0xa438, 0xd10f }, { 0xa438, 0xbf85 }, { 0xa438, 0xaa02 }, { 0xa438, 0x4f48 }, { 0xa438, 0xe18f }, { 0xa438, 0xf7bf }, { 0xa438, 0x85ad }, { 0xa438, 0x024f }, { 0xa438 , 0x48e1 }, { 0xa438, 0x8ff8 }, { 0xa438, 0xbf85 }, { 0xa438, 0xb002 }, { 0xa438, 0x4f48 }, { 0xa438, 0xe18f }, { 0xa438, 0xf9bf }, { 0xa438, 0x85b3 }, { 0xa438, 0x024f }, { 0xa438, 0x48e1 } , { 0xa438, 0x8ffa }, { 0xa438, 0xbf85 }, { 0xa438, 0xb602 }, { 0xa438, 0x4f48 }, { 0xa438, 0xae2c }, { 0xa438, 0xd100 }, { 0xa438, 0xbf85 }, { 0xa438, 0xaa02 }, { 0xa438, 0x4f48 }, { 0xa438 , 0xe18f }, { 0xa438, 0xfbbf }, { 0xa438, 0x85ad }, { 0xa438, 0x024f }, { 0xa438, 0x48e1 }, { 0xa438, 0x8ffc }, { 0xa438, 0xbf85 }, { 0xa438, 0xb002 }, { 0xa438, 0x4f48 }, { 0xa438, 0xe18f } , { 0xa438, 0xfdbf }, { 0xa438, 0x85b3 }, { 0xa438, 0x024f }, { 0xa438, 0x48e1 }, { 0xa438, 0x8ffe }, { 0xa438, 0xbf85 }, { 0xa438, 0xb602 }, { 0xa438, 0x4f48 }, { 0xa438, 0xbf86 }, { 0xa438 , 0x7e02 }, { 0xa438, 0x4f67 }, { 0xa438, 0xa100 }, { 0xa438, 0x02ae }, { 0xa438, 0x25a1 }, { 0xa438, 0x041d }, { 0xa438, 0xe18f }, { 0xa438, 0xf1bf }, { 0xa438, 0x8675 }, { 0xa438, 0x024f } , { 0xa438, 0x48e1 }, { 0xa438, 0x8ff2 }, { 0xa438, 0xbf86 }, { 0xa438, 0x7802 }, { 0xa438, 0x4f48 }, { 0xa438, 0xe18f }, { 0xa438, 0xf3bf }, { 0xa438, 0x867b }, { 0xa438, 0x024f }, { 0xa438 , 0x48ae }, { 0xa438, 0x29a1 }, { 0xa438, 0x070b }, { 0xa438, 0xae24 }, { 0xa438, 0xbf86 }, { 0xa438, 0x8102 }, { 0xa438, 0x4f67 }, { 0xa438, 0xad28 }, { 0xa438, 0x1be1 }, { 0xa438, 0x8ff4 } , { 0xa438, 0xbf86 }, { 0xa438, 0x7502 }, { 0xa438, 0x4f48 }, { 0xa438, 0xe18f }, { 0xa438, 0xf5bf }, { 0xa438, 0x8678 }, { 0xa438, 0x024f }, { 0xa438, 0x48e1 }, { 0xa438, 0x8ff6 }, { 0xa438 , 0xbf86 }, { 0xa438, 0x7b02 }, { 0xa438, 0x4f48 }, { 0xa438, 0xaf09 }, { 0xa438, 0x8420 }, { 0xa438, 0xbc32 }, { 0xa438, 0x20bc }, { 0xa438, 0x3e76 }, { 0xa438, 0xbc08 }, { 0xa438, 0xfda6 } , { 0xa438, 0x1a00 }, { 0xa438, 0xb64e }, { 0xa438, 0xd101 }, { 0xa438, 0xbf85 }, { 0xa438, 0xa402 }, { 0xa438, 0x4f48 }, { 0xa438, 0xbf85 }, { 0xa438, 0xa702 }, { 0xa438, 0x54c0 }, { 0xa438 , 0xd10f }, { 0xa438, 0xbf85 }, { 0xa438, 0xaa02 }, { 0xa438, 0x4f48 }, { 0xa438, 0x024d }, { 0xa438, 0x6abf }, { 0xa438, 0x85ad }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438, 0x8ff7 } , { 0xa438, 0xddbf }, { 0xa438, 0x85b0 }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438, 0x8ff8 }, { 0xa438, 0xddbf }, { 0xa438, 0x85b3 }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438 , 0x8ff9 }, { 0xa438, 0xddbf }, { 0xa438, 0x85b6 }, { 0xa438, 0x024f }, { 0xa438, 0x67bf }, { 0xa438, 0x8ffa }, { 0xa438, 0xddd1 }, { 0xa438, 0x00bf }, { 0xa438, 0x85aa }, { 0xa438, 0x024f } , { 0xa438, 0x4802 }, { 0xa438, 0x4d6a }, { 0xa438, 0xbf85 }, { 0xa438, 0xad02 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfbdd }, { 0xa438, 0xbf85 }, { 0xa438, 0xb002 }, { 0xa438 , 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfcdd }, { 0xa438, 0xbf85 }, { 0xa438, 0xb302 }, { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfddd }, { 0xa438, 0xbf85 }, { 0xa438, 0xb602 } , { 0xa438, 0x4f67 }, { 0xa438, 0xbf8f }, { 0xa438, 0xfedd }, { 0xa438, 0xbf85 }, { 0xa438, 0xa702 }, { 0xa438, 0x54b7 }, { 0xa438, 0xaf00 }, { 0xa438, 0x8800 }, { 0xa436, 0xb818 }, { 0xa438 , 0x38b8 }, { 0xa436, 0xb81a }, { 0xa438, 0x0444 }, { 0xa436, 0xb81c }, { 0xa438, 0x40ee }, { 0xa436, 0xb81e }, { 0xa438, 0x3c1a }, { 0xa436, 0xb850 }, { 0xa438, 0x0981 }, { 0xa436, 0xb852 } , { 0xa438, 0x0085 }, { 0xa436, 0xb878 }, { 0xa438, 0xffff }, { 0xa436, 0xb884 }, { 0xa438, 0xffff }, { 0xa436, 0xb832 }, { 0xa438, 0x003f }, { 0xa436, 0x0000 }, { 0xa438, 0x0000 }, { 0xa436 , 0xb82e }, { 0xa438, 0x0000 }, { 0xa436, 0x8024 }, { 0xa438, 0x0000 }, { 0xb820, 0x0000 }, { 0xa436, 0x801e }, { 0xa438, 0x0021 } | |||
129 | }, rtl8125_mac_cfg5_mcu[] = { | |||
130 | RTL8125_MAC_CFG5_MCU{ 0xa436, 0x8024 }, { 0xa438, 0x3701 }, { 0xa436, 0xb82e }, { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, { 0xa438 , 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x8024 } , { 0xa438, 0x1800 }, { 0xa438, 0x802f }, { 0xa438, 0x1800 }, { 0xa438, 0x8051 }, { 0xa438, 0x1800 }, { 0xa438, 0x8057 }, { 0xa438, 0x1800 }, { 0xa438, 0x8063 }, { 0xa438, 0x1800 }, { 0xa438 , 0x8068 }, { 0xa438, 0xd093 }, { 0xa438, 0xd1c4 }, { 0xa438, 0x1000 }, { 0xa438, 0x135c }, { 0xa438, 0xd704 }, { 0xa438, 0x5fbc }, { 0xa438, 0xd504 }, { 0xa438, 0xc9f1 }, { 0xa438, 0x1800 } , { 0xa438, 0x0fc9 }, { 0xa438, 0xbb50 }, { 0xa438, 0xd505 }, { 0xa438, 0xa202 }, { 0xa438, 0xd504 }, { 0xa438, 0x8c0f }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1519 }, { 0xa438 , 0x1800 }, { 0xa438, 0x1548 }, { 0xa438, 0x2f70 }, { 0xa438, 0x802a }, { 0xa438, 0x2f73 }, { 0xa438, 0x156a }, { 0xa438, 0x1800 }, { 0xa438, 0x155c }, { 0xa438, 0xd505 }, { 0xa438, 0xa202 } , { 0xa438, 0xd500 }, { 0xa438, 0x1800 }, { 0xa438, 0x1551 }, { 0xa438, 0xc0c1 }, { 0xa438, 0xc0c0 }, { 0xa438, 0xd05a }, { 0xa438, 0xd1ba }, { 0xa438, 0xd701 }, { 0xa438, 0x2529 }, { 0xa438 , 0x022a }, { 0xa438, 0xd0a7 }, { 0xa438, 0xd1b9 }, { 0xa438, 0xa208 }, { 0xa438, 0x1000 }, { 0xa438, 0x080e }, { 0xa438, 0xd701 }, { 0xa438, 0x408b }, { 0xa438, 0x1000 }, { 0xa438, 0x0a65 } , { 0xa438, 0xf003 }, { 0xa438, 0x1000 }, { 0xa438, 0x0a6b }, { 0xa438, 0xd701 }, { 0xa438, 0x1000 }, { 0xa438, 0x0920 }, { 0xa438, 0x1000 }, { 0xa438, 0x0915 }, { 0xa438, 0x1000 }, { 0xa438 , 0x0909 }, { 0xa438, 0x228f }, { 0xa438, 0x8038 }, { 0xa438, 0x9801 }, { 0xa438, 0xd71e }, { 0xa438, 0x5d61 }, { 0xa438, 0xd701 }, { 0xa438, 0x1800 }, { 0xa438, 0x022a }, { 0xa438, 0x2005 } , { 0xa438, 0x091a }, { 0xa438, 0x3bd9 }, { 0xa438, 0x0919 }, { 0xa438, 0x1800 }, { 0xa438, 0x0916 }, { 0xa438, 0x1000 }, { 0xa438, 0x14c5 }, { 0xa438, 0xd703 }, { 0xa438, 0x3181 }, { 0xa438 , 0x8061 }, { 0xa438, 0x60ad }, { 0xa438, 0x1000 }, { 0xa438, 0x135c }, { 0xa438, 0xd703 }, { 0xa438, 0x5fba }, { 0xa438, 0x1800 }, { 0xa438, 0x0cc7 }, { 0xa438, 0xd096 }, { 0xa438, 0xd1a9 } , { 0xa438, 0xd503 }, { 0xa438, 0x1800 }, { 0xa438, 0x0c94 }, { 0xa438, 0xa802 }, { 0xa438, 0xa301 }, { 0xa438, 0xa801 }, { 0xa438, 0xc004 }, { 0xa438, 0xd710 }, { 0xa438, 0x4000 }, { 0xa438 , 0x1800 }, { 0xa438, 0x1e79 }, { 0xa436, 0xa026 }, { 0xa438, 0x1e78 }, { 0xa436, 0xa024 }, { 0xa438, 0x0c93 }, { 0xa436, 0xa022 }, { 0xa438, 0x0cc5 }, { 0xa436, 0xa020 }, { 0xa438, 0x0915 } , { 0xa436, 0xa006 }, { 0xa438, 0x020a }, { 0xa436, 0xa004 }, { 0xa438, 0x155b }, { 0xa436, 0xa002 }, { 0xa438, 0x1542 }, { 0xa436, 0xa000 }, { 0xa438, 0x0fc7 }, { 0xa436, 0xa008 }, { 0xa438 , 0xff00 }, { 0xa436, 0xa016 }, { 0xa438, 0x0010 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x801d } , { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438 , 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0xd700 }, { 0xa438, 0x6090 }, { 0xa438, 0x60d1 }, { 0xa438, 0xc95c }, { 0xa438, 0xf007 }, { 0xa438, 0x60b1 }, { 0xa438, 0xc95a } , { 0xa438, 0xf004 }, { 0xa438, 0xc956 }, { 0xa438, 0xf002 }, { 0xa438, 0xc94e }, { 0xa438, 0x1800 }, { 0xa438, 0x00cd }, { 0xa438, 0xd700 }, { 0xa438, 0x6090 }, { 0xa438, 0x60d1 }, { 0xa438 , 0xc95c }, { 0xa438, 0xf007 }, { 0xa438, 0x60b1 }, { 0xa438, 0xc95a }, { 0xa438, 0xf004 }, { 0xa438, 0xc956 }, { 0xa438, 0xf002 }, { 0xa438, 0xc94e }, { 0xa438, 0x1000 }, { 0xa438, 0x022a } , { 0xa438, 0x1800 }, { 0xa438, 0x0132 }, { 0xa436, 0xa08e }, { 0xa438, 0xffff }, { 0xa436, 0xa08c }, { 0xa438, 0xffff }, { 0xa436, 0xa08a }, { 0xa438, 0xffff }, { 0xa436, 0xa088 }, { 0xa438 , 0xffff }, { 0xa436, 0xa086 }, { 0xa438, 0xffff }, { 0xa436, 0xa084 }, { 0xa438, 0xffff }, { 0xa436, 0xa082 }, { 0xa438, 0x012f }, { 0xa436, 0xa080 }, { 0xa438, 0x00cc }, { 0xa436, 0xa090 } , { 0xa438, 0x0103 }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438 , 0x8020 }, { 0xa438, 0x1800 }, { 0xa438, 0x802a }, { 0xa438, 0x1800 }, { 0xa438, 0x8035 }, { 0xa438, 0x1800 }, { 0xa438, 0x803c }, { 0xa438, 0x1800 }, { 0xa438, 0x803c }, { 0xa438, 0x1800 } , { 0xa438, 0x803c }, { 0xa438, 0x1800 }, { 0xa438, 0x803c }, { 0xa438, 0xd107 }, { 0xa438, 0xd042 }, { 0xa438, 0xa404 }, { 0xa438, 0x1000 }, { 0xa438, 0x09df }, { 0xa438, 0xd700 }, { 0xa438 , 0x5fb4 }, { 0xa438, 0x8280 }, { 0xa438, 0xd700 }, { 0xa438, 0x6065 }, { 0xa438, 0xd125 }, { 0xa438, 0xf002 }, { 0xa438, 0xd12b }, { 0xa438, 0xd040 }, { 0xa438, 0x1800 }, { 0xa438, 0x077f } , { 0xa438, 0x0cf0 }, { 0xa438, 0x0c50 }, { 0xa438, 0xd104 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x0aa8 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x1800 }, { 0xa438 , 0x0a2e }, { 0xa438, 0xcb9b }, { 0xa438, 0xd110 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x0b7b }, { 0xa438, 0x1000 }, { 0xa438, 0x09df }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 } , { 0xa438, 0x1800 }, { 0xa438, 0x081b }, { 0xa438, 0x1000 }, { 0xa438, 0x09df }, { 0xa438, 0xd704 }, { 0xa438, 0x7fb8 }, { 0xa438, 0xa718 }, { 0xa438, 0x1800 }, { 0xa438, 0x074e }, { 0xa436 , 0xa10e }, { 0xa438, 0xffff }, { 0xa436, 0xa10c }, { 0xa438, 0xffff }, { 0xa436, 0xa10a }, { 0xa438, 0xffff }, { 0xa436, 0xa108 }, { 0xa438, 0xffff }, { 0xa436, 0xa106 }, { 0xa438, 0x074d } , { 0xa436, 0xa104 }, { 0xa438, 0x0818 }, { 0xa436, 0xa102 }, { 0xa438, 0x0a2c }, { 0xa436, 0xa100 }, { 0xa438, 0x077e }, { 0xa436, 0xa110 }, { 0xa438, 0x000f }, { 0xa436, 0xb87c }, { 0xa438 , 0x8625 }, { 0xa436, 0xb87e }, { 0xa438, 0xaf86 }, { 0xa438, 0x3daf }, { 0xa438, 0x8689 }, { 0xa438, 0xaf88 }, { 0xa438, 0x69af }, { 0xa438, 0x8887 }, { 0xa438, 0xaf88 }, { 0xa438, 0x9caf } , { 0xa438, 0x889c }, { 0xa438, 0xaf88 }, { 0xa438, 0x9caf }, { 0xa438, 0x889c }, { 0xa438, 0xbf86 }, { 0xa438, 0x49d7 }, { 0xa438, 0x0040 }, { 0xa438, 0x0277 }, { 0xa438, 0x7daf }, { 0xa438 , 0x2727 }, { 0xa438, 0x0000 }, { 0xa438, 0x7205 }, { 0xa438, 0x0000 }, { 0xa438, 0x7208 }, { 0xa438, 0x0000 }, { 0xa438, 0x71f3 }, { 0xa438, 0x0000 }, { 0xa438, 0x71f6 }, { 0xa438, 0x0000 } , { 0xa438, 0x7229 }, { 0xa438, 0x0000 }, { 0xa438, 0x722c }, { 0xa438, 0x0000 }, { 0xa438, 0x7217 }, { 0xa438, 0x0000 }, { 0xa438, 0x721a }, { 0xa438, 0x0000 }, { 0xa438, 0x721d }, { 0xa438 , 0x0000 }, { 0xa438, 0x7211 }, { 0xa438, 0x0000 }, { 0xa438, 0x7220 }, { 0xa438, 0x0000 }, { 0xa438, 0x7214 }, { 0xa438, 0x0000 }, { 0xa438, 0x722f }, { 0xa438, 0x0000 }, { 0xa438, 0x7223 } , { 0xa438, 0x0000 }, { 0xa438, 0x7232 }, { 0xa438, 0x0000 }, { 0xa438, 0x7226 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xfae0 }, { 0xa438, 0x85b3 }, { 0xa438, 0x3802 }, { 0xa438, 0xad27 }, { 0xa438 , 0x02ae }, { 0xa438, 0x03af }, { 0xa438, 0x8830 }, { 0xa438, 0x1f66 }, { 0xa438, 0xef65 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x1f1a }, { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 } , { 0xa438, 0x00da }, { 0xa438, 0xf605 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x2f1a }, { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, { 0xa438, 0x00db }, { 0xa438, 0xf605 }, { 0xa438 , 0xef02 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x4202 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef02 }, { 0xa438, 0x1b03 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 } , { 0xa438, 0xbf88 }, { 0xa438, 0x4502 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef02 }, { 0xa438, 0x1a03 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x4802 }, { 0xa438 , 0x6e7d }, { 0xa438, 0xbfc2 }, { 0xa438, 0x3f1a }, { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, { 0xa438, 0x00da }, { 0xa438, 0xf605 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x4f1a } , { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, { 0xa438, 0x00db }, { 0xa438, 0xf605 }, { 0xa438, 0xef02 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438 , 0x4b02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef02 }, { 0xa438, 0x1b03 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x4e02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef02 } , { 0xa438, 0x1a03 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x5102 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef56 }, { 0xa438, 0xd020 }, { 0xa438, 0x1f11 }, { 0xa438 , 0xbf88 }, { 0xa438, 0x5402 }, { 0xa438, 0x6e7d }, { 0xa438, 0xbf88 }, { 0xa438, 0x5702 }, { 0xa438, 0x6e7d }, { 0xa438, 0xbf88 }, { 0xa438, 0x5a02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe185 } , { 0xa438, 0xa0ef }, { 0xa438, 0x0348 }, { 0xa438, 0x0a28 }, { 0xa438, 0x05ef }, { 0xa438, 0x201b }, { 0xa438, 0x01ad }, { 0xa438, 0x2735 }, { 0xa438, 0x1f44 }, { 0xa438, 0xe085 }, { 0xa438 , 0x88e1 }, { 0xa438, 0x8589 }, { 0xa438, 0xbf88 }, { 0xa438, 0x5d02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, { 0xa438, 0x8ee1 }, { 0xa438, 0x858f }, { 0xa438, 0xbf88 }, { 0xa438, 0x6002 } , { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, { 0xa438, 0x94e1 }, { 0xa438, 0x8595 }, { 0xa438, 0xbf88 }, { 0xa438, 0x6302 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, { 0xa438, 0x9ae1 }, { 0xa438 , 0x859b }, { 0xa438, 0xbf88 }, { 0xa438, 0x6602 }, { 0xa438, 0x6e7d }, { 0xa438, 0xaf88 }, { 0xa438, 0x3cbf }, { 0xa438, 0x883f }, { 0xa438, 0x026e }, { 0xa438, 0x9cad }, { 0xa438, 0x2835 } , { 0xa438, 0x1f44 }, { 0xa438, 0xe08f }, { 0xa438, 0xf8e1 }, { 0xa438, 0x8ff9 }, { 0xa438, 0xbf88 }, { 0xa438, 0x5d02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe08f }, { 0xa438, 0xfae1 }, { 0xa438 , 0x8ffb }, { 0xa438, 0xbf88 }, { 0xa438, 0x6002 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe08f }, { 0xa438, 0xfce1 }, { 0xa438, 0x8ffd }, { 0xa438, 0xbf88 }, { 0xa438, 0x6302 }, { 0xa438, 0x6e7d } , { 0xa438, 0xe08f }, { 0xa438, 0xfee1 }, { 0xa438, 0x8fff }, { 0xa438, 0xbf88 }, { 0xa438, 0x6602 }, { 0xa438, 0x6e7d }, { 0xa438, 0xaf88 }, { 0xa438, 0x3ce1 }, { 0xa438, 0x85a1 }, { 0xa438 , 0x1b21 }, { 0xa438, 0xad37 }, { 0xa438, 0x341f }, { 0xa438, 0x44e0 }, { 0xa438, 0x858a }, { 0xa438, 0xe185 }, { 0xa438, 0x8bbf }, { 0xa438, 0x885d }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 } , { 0xa438, 0x8590 }, { 0xa438, 0xe185 }, { 0xa438, 0x91bf }, { 0xa438, 0x8860 }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 }, { 0xa438, 0x8596 }, { 0xa438, 0xe185 }, { 0xa438, 0x97bf }, { 0xa438 , 0x8863 }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 }, { 0xa438, 0x859c }, { 0xa438, 0xe185 }, { 0xa438, 0x9dbf }, { 0xa438, 0x8866 }, { 0xa438, 0x026e }, { 0xa438, 0x7dae }, { 0xa438, 0x401f } , { 0xa438, 0x44e0 }, { 0xa438, 0x858c }, { 0xa438, 0xe185 }, { 0xa438, 0x8dbf }, { 0xa438, 0x885d }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 }, { 0xa438, 0x8592 }, { 0xa438, 0xe185 }, { 0xa438 , 0x93bf }, { 0xa438, 0x8860 }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 }, { 0xa438, 0x8598 }, { 0xa438, 0xe185 }, { 0xa438, 0x99bf }, { 0xa438, 0x8863 }, { 0xa438, 0x026e }, { 0xa438, 0x7de0 } , { 0xa438, 0x859e }, { 0xa438, 0xe185 }, { 0xa438, 0x9fbf }, { 0xa438, 0x8866 }, { 0xa438, 0x026e }, { 0xa438, 0x7dae }, { 0xa438, 0x0ce1 }, { 0xa438, 0x85b3 }, { 0xa438, 0x3904 }, { 0xa438 , 0xac2f }, { 0xa438, 0x04ee }, { 0xa438, 0x85b3 }, { 0xa438, 0x00af }, { 0xa438, 0x39d9 }, { 0xa438, 0x22ac }, { 0xa438, 0xeaf0 }, { 0xa438, 0xacf6 }, { 0xa438, 0xf0ac }, { 0xa438, 0xfaf0 } , { 0xa438, 0xacf8 }, { 0xa438, 0xf0ac }, { 0xa438, 0xfcf0 }, { 0xa438, 0xad00 }, { 0xa438, 0xf0ac }, { 0xa438, 0xfef0 }, { 0xa438, 0xacf0 }, { 0xa438, 0xf0ac }, { 0xa438, 0xf4f0 }, { 0xa438 , 0xacf2 }, { 0xa438, 0xf0ac }, { 0xa438, 0xb0f0 }, { 0xa438, 0xacae }, { 0xa438, 0xf0ac }, { 0xa438, 0xacf0 }, { 0xa438, 0xacaa }, { 0xa438, 0xa100 }, { 0xa438, 0x0ce1 }, { 0xa438, 0x8ff7 } , { 0xa438, 0xbf88 }, { 0xa438, 0x8402 }, { 0xa438, 0x6e7d }, { 0xa438, 0xaf26 }, { 0xa438, 0xe9e1 }, { 0xa438, 0x8ff6 }, { 0xa438, 0xbf88 }, { 0xa438, 0x8402 }, { 0xa438, 0x6e7d }, { 0xa438 , 0xaf26 }, { 0xa438, 0xf520 }, { 0xa438, 0xac86 }, { 0xa438, 0xbf88 }, { 0xa438, 0x3f02 }, { 0xa438, 0x6e9c }, { 0xa438, 0xad28 }, { 0xa438, 0x03af }, { 0xa438, 0x3324 }, { 0xa438, 0xad38 } , { 0xa438, 0x03af }, { 0xa438, 0x32e6 }, { 0xa438, 0xaf32 }, { 0xa438, 0xfb00 }, { 0xa436, 0xb87c }, { 0xa438, 0x8ff6 }, { 0xa436, 0xb87e }, { 0xa438, 0x0705 }, { 0xa436, 0xb87c }, { 0xa438 , 0x8ff8 }, { 0xa436, 0xb87e }, { 0xa438, 0x19cc }, { 0xa436, 0xb87c }, { 0xa438, 0x8ffa }, { 0xa436, 0xb87e }, { 0xa438, 0x28e3 }, { 0xa436, 0xb87c }, { 0xa438, 0x8ffc }, { 0xa436, 0xb87e } , { 0xa438, 0x1047 }, { 0xa436, 0xb87c }, { 0xa438, 0x8ffe }, { 0xa436, 0xb87e }, { 0xa438, 0x0a45 }, { 0xa436, 0xb85e }, { 0xa438, 0x271e }, { 0xa436, 0xb860 }, { 0xa438, 0x3846 }, { 0xa436 , 0xb862 }, { 0xa438, 0x26e6 }, { 0xa436, 0xb864 }, { 0xa438, 0x32e3 }, { 0xa436, 0xb886 }, { 0xa438, 0xffff }, { 0xa436, 0xb888 }, { 0xa438, 0xffff }, { 0xa436, 0xb88a }, { 0xa438, 0xffff } , { 0xa436, 0xb88c }, { 0xa438, 0xffff }, { 0xa436, 0xb838 }, { 0xa438, 0x000f }, { 0xb820, 0x0010 }, { 0xa436, 0x846e }, { 0xa438, 0xaf84 }, { 0xa438, 0x86af }, { 0xa438, 0x8690 }, { 0xa438 , 0xaf86 }, { 0xa438, 0xa4af }, { 0xa438, 0x86a4 }, { 0xa438, 0xaf86 }, { 0xa438, 0xa4af }, { 0xa438, 0x86a4 }, { 0xa438, 0xaf86 }, { 0xa438, 0xa4af }, { 0xa438, 0x86a4 }, { 0xa438, 0xee82 } , { 0xa438, 0x5f00 }, { 0xa438, 0x0284 }, { 0xa438, 0x90af }, { 0xa438, 0x0441 }, { 0xa438, 0xf8e0 }, { 0xa438, 0x8ff3 }, { 0xa438, 0xa000 }, { 0xa438, 0x0502 }, { 0xa438, 0x84a4 }, { 0xa438 , 0xae06 }, { 0xa438, 0xa001 }, { 0xa438, 0x0302 }, { 0xa438, 0x84c8 }, { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xef59 }, { 0xa438, 0xe080 }, { 0xa438, 0x15ad }, { 0xa438, 0x2702 } , { 0xa438, 0xae03 }, { 0xa438, 0xaf84 }, { 0xa438, 0xc3bf }, { 0xa438, 0x53ca }, { 0xa438, 0x0252 }, { 0xa438, 0xc8ad }, { 0xa438, 0x2807 }, { 0xa438, 0x0285 }, { 0xa438, 0x2cee }, { 0xa438 , 0x8ff3 }, { 0xa438, 0x01ef }, { 0xa438, 0x95fd }, { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xfaef }, { 0xa438, 0x69bf }, { 0xa438, 0x53ca }, { 0xa438, 0x0252 }, { 0xa438, 0xc8ac } , { 0xa438, 0x2822 }, { 0xa438, 0xd480 }, { 0xa438, 0x00bf }, { 0xa438, 0x8684 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438, 0x8687 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438 , 0x868a }, { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438, 0x868d }, { 0xa438, 0x0252 }, { 0xa438, 0xa9ee }, { 0xa438, 0x8ff3 }, { 0xa438, 0x00af }, { 0xa438, 0x8526 }, { 0xa438, 0xe08f } , { 0xa438, 0xf4e1 }, { 0xa438, 0x8ff5 }, { 0xa438, 0xe28f }, { 0xa438, 0xf6e3 }, { 0xa438, 0x8ff7 }, { 0xa438, 0x1b45 }, { 0xa438, 0xac27 }, { 0xa438, 0x0eee }, { 0xa438, 0x8ff4 }, { 0xa438 , 0x00ee }, { 0xa438, 0x8ff5 }, { 0xa438, 0x0002 }, { 0xa438, 0x852c }, { 0xa438, 0xaf85 }, { 0xa438, 0x26e0 }, { 0xa438, 0x8ff4 }, { 0xa438, 0xe18f }, { 0xa438, 0xf52c }, { 0xa438, 0x0001 } , { 0xa438, 0xe48f }, { 0xa438, 0xf4e5 }, { 0xa438, 0x8ff5 }, { 0xa438, 0xef96 }, { 0xa438, 0xfefd }, { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xef59 }, { 0xa438, 0xbf53 }, { 0xa438 , 0x2202 }, { 0xa438, 0x52c8 }, { 0xa438, 0xa18b }, { 0xa438, 0x02ae }, { 0xa438, 0x03af }, { 0xa438, 0x85da }, { 0xa438, 0xbf57 }, { 0xa438, 0x7202 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f } , { 0xa438, 0xf8e5 }, { 0xa438, 0x8ff9 }, { 0xa438, 0xbf57 }, { 0xa438, 0x7502 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xfae5 }, { 0xa438, 0x8ffb }, { 0xa438, 0xbf57 }, { 0xa438 , 0x7802 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xfce5 }, { 0xa438, 0x8ffd }, { 0xa438, 0xbf57 }, { 0xa438, 0x7b02 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xfee5 } , { 0xa438, 0x8fff }, { 0xa438, 0xbf57 }, { 0xa438, 0x6c02 }, { 0xa438, 0x52c8 }, { 0xa438, 0xa102 }, { 0xa438, 0x13ee }, { 0xa438, 0x8ffc }, { 0xa438, 0x80ee }, { 0xa438, 0x8ffd }, { 0xa438 , 0x00ee }, { 0xa438, 0x8ffe }, { 0xa438, 0x80ee }, { 0xa438, 0x8fff }, { 0xa438, 0x00af }, { 0xa438, 0x8599 }, { 0xa438, 0xa101 }, { 0xa438, 0x0cbf }, { 0xa438, 0x534c }, { 0xa438, 0x0252 } , { 0xa438, 0xc8a1 }, { 0xa438, 0x0303 }, { 0xa438, 0xaf85 }, { 0xa438, 0x77bf }, { 0xa438, 0x5322 }, { 0xa438, 0x0252 }, { 0xa438, 0xc8a1 }, { 0xa438, 0x8b02 }, { 0xa438, 0xae03 }, { 0xa438 , 0xaf86 }, { 0xa438, 0x64e0 }, { 0xa438, 0x8ff8 }, { 0xa438, 0xe18f }, { 0xa438, 0xf9bf }, { 0xa438, 0x8684 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9e0 }, { 0xa438, 0x8ffa }, { 0xa438, 0xe18f } , { 0xa438, 0xfbbf }, { 0xa438, 0x8687 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9e0 }, { 0xa438, 0x8ffc }, { 0xa438, 0xe18f }, { 0xa438, 0xfdbf }, { 0xa438, 0x868a }, { 0xa438, 0x0252 }, { 0xa438 , 0xa9e0 }, { 0xa438, 0x8ffe }, { 0xa438, 0xe18f }, { 0xa438, 0xffbf }, { 0xa438, 0x868d }, { 0xa438, 0x0252 }, { 0xa438, 0xa9af }, { 0xa438, 0x867f }, { 0xa438, 0xbf53 }, { 0xa438, 0x2202 } , { 0xa438, 0x52c8 }, { 0xa438, 0xa144 }, { 0xa438, 0x3cbf }, { 0xa438, 0x547b }, { 0xa438, 0x0252 }, { 0xa438, 0xc8e4 }, { 0xa438, 0x8ff8 }, { 0xa438, 0xe58f }, { 0xa438, 0xf9bf }, { 0xa438 , 0x547e }, { 0xa438, 0x0252 }, { 0xa438, 0xc8e4 }, { 0xa438, 0x8ffa }, { 0xa438, 0xe58f }, { 0xa438, 0xfbbf }, { 0xa438, 0x5481 }, { 0xa438, 0x0252 }, { 0xa438, 0xc8e4 }, { 0xa438, 0x8ffc } , { 0xa438, 0xe58f }, { 0xa438, 0xfdbf }, { 0xa438, 0x5484 }, { 0xa438, 0x0252 }, { 0xa438, 0xc8e4 }, { 0xa438, 0x8ffe }, { 0xa438, 0xe58f }, { 0xa438, 0xffbf }, { 0xa438, 0x5322 }, { 0xa438 , 0x0252 }, { 0xa438, 0xc8a1 }, { 0xa438, 0x4448 }, { 0xa438, 0xaf85 }, { 0xa438, 0xa7bf }, { 0xa438, 0x5322 }, { 0xa438, 0x0252 }, { 0xa438, 0xc8a1 }, { 0xa438, 0x313c }, { 0xa438, 0xbf54 } , { 0xa438, 0x7b02 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xf8e5 }, { 0xa438, 0x8ff9 }, { 0xa438, 0xbf54 }, { 0xa438, 0x7e02 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438 , 0xfae5 }, { 0xa438, 0x8ffb }, { 0xa438, 0xbf54 }, { 0xa438, 0x8102 }, { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xfce5 }, { 0xa438, 0x8ffd }, { 0xa438, 0xbf54 }, { 0xa438, 0x8402 } , { 0xa438, 0x52c8 }, { 0xa438, 0xe48f }, { 0xa438, 0xfee5 }, { 0xa438, 0x8fff }, { 0xa438, 0xbf53 }, { 0xa438, 0x2202 }, { 0xa438, 0x52c8 }, { 0xa438, 0xa131 }, { 0xa438, 0x03af }, { 0xa438 , 0x85a7 }, { 0xa438, 0xd480 }, { 0xa438, 0x00bf }, { 0xa438, 0x8684 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438, 0x8687 }, { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438, 0x868a } , { 0xa438, 0x0252 }, { 0xa438, 0xa9bf }, { 0xa438, 0x868d }, { 0xa438, 0x0252 }, { 0xa438, 0xa9ef }, { 0xa438, 0x95fd }, { 0xa438, 0xfc04 }, { 0xa438, 0xf0d1 }, { 0xa438, 0x2af0 }, { 0xa438 , 0xd12c }, { 0xa438, 0xf0d1 }, { 0xa438, 0x44f0 }, { 0xa438, 0xd146 }, { 0xa438, 0xbf86 }, { 0xa438, 0xa102 }, { 0xa438, 0x52c8 }, { 0xa438, 0xbf86 }, { 0xa438, 0xa102 }, { 0xa438, 0x52c8 } , { 0xa438, 0xd101 }, { 0xa438, 0xaf06 }, { 0xa438, 0xa570 }, { 0xa438, 0xce42 }, { 0xa436, 0xb818 }, { 0xa438, 0x043d }, { 0xa436, 0xb81a }, { 0xa438, 0x06a3 }, { 0xa436, 0xb81c }, { 0xa438 , 0xffff }, { 0xa436, 0xb81e }, { 0xa438, 0xffff }, { 0xa436, 0xb850 }, { 0xa438, 0xffff }, { 0xa436, 0xb852 }, { 0xa438, 0xffff }, { 0xa436, 0xb878 }, { 0xa438, 0xffff }, { 0xa436, 0xb884 } , { 0xa438, 0xffff }, { 0xa436, 0xb832 }, { 0xa438, 0x0003 }, { 0xa436, 0x0000 }, { 0xa438, 0x0000 }, { 0xa436, 0xb82e }, { 0xa438, 0x0000 }, { 0xa436, 0x8024 }, { 0xa438, 0x0000 }, { 0xb820 , 0x0000 }, { 0xa436, 0x801e }, { 0xa438, 0x0019 } | |||
131 | }; | |||
132 | ||||
133 | struct cfattach rge_ca = { | |||
134 | sizeof(struct rge_softc), rge_match, rge_attach, NULL((void *)0), rge_activate | |||
135 | }; | |||
136 | ||||
137 | struct cfdriver rge_cd = { | |||
138 | NULL((void *)0), "rge", DV_IFNET | |||
139 | }; | |||
140 | ||||
141 | const struct pci_matchid rge_devices[] = { | |||
142 | { PCI_VENDOR_REALTEK0x10ec, PCI_PRODUCT_REALTEK_E30000x3000 }, | |||
143 | { PCI_VENDOR_REALTEK0x10ec, PCI_PRODUCT_REALTEK_RTL81250x8125 } | |||
144 | }; | |||
145 | ||||
146 | int | |||
147 | rge_match(struct device *parent, void *match, void *aux) | |||
148 | { | |||
149 | return (pci_matchbyid((struct pci_attach_args *)aux, rge_devices, | |||
150 | nitems(rge_devices)(sizeof((rge_devices)) / sizeof((rge_devices)[0])))); | |||
151 | } | |||
152 | ||||
153 | void | |||
154 | rge_attach(struct device *parent, struct device *self, void *aux) | |||
155 | { | |||
156 | struct rge_softc *sc = (struct rge_softc *)self; | |||
157 | struct pci_attach_args *pa = aux; | |||
158 | pci_chipset_tag_t pc = pa->pa_pc; | |||
159 | pci_intr_handle_t ih; | |||
160 | const char *intrstr = NULL((void *)0); | |||
161 | struct ifnet *ifp; | |||
162 | struct rge_queues *q; | |||
163 | pcireg_t reg; | |||
164 | uint32_t hwrev; | |||
165 | uint8_t eaddr[ETHER_ADDR_LEN6]; | |||
166 | int offset; | |||
167 | ||||
168 | pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D00x0000); | |||
169 | ||||
170 | /* | |||
171 | * Map control/status registers. | |||
172 | */ | |||
173 | if (pci_mapreg_map(pa, RGE_PCI_BAR2(0x10 + 8), PCI_MAPREG_TYPE_MEM0x00000000 | | |||
174 | PCI_MAPREG_MEM_TYPE_64BIT0x00000004, 0, &sc->rge_btag, &sc->rge_bhandle, | |||
175 | NULL((void *)0), &sc->rge_bsize, 0)) { | |||
176 | if (pci_mapreg_map(pa, RGE_PCI_BAR1(0x10 + 4), PCI_MAPREG_TYPE_MEM0x00000000 | | |||
177 | PCI_MAPREG_MEM_TYPE_32BIT0x00000000, 0, &sc->rge_btag, | |||
178 | &sc->rge_bhandle, NULL((void *)0), &sc->rge_bsize, 0)) { | |||
179 | if (pci_mapreg_map(pa, RGE_PCI_BAR00x10, PCI_MAPREG_TYPE_IO0x00000001, | |||
180 | 0, &sc->rge_btag, &sc->rge_bhandle, NULL((void *)0), | |||
181 | &sc->rge_bsize, 0)) { | |||
182 | printf(": can't map mem or i/o space\n"); | |||
183 | return; | |||
184 | } | |||
185 | } | |||
186 | } | |||
187 | ||||
188 | q = malloc(sizeof(struct rge_queues), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008); | |||
189 | if (q == NULL((void *)0)) { | |||
190 | printf(": unable to allocate queue memory\n"); | |||
191 | return; | |||
192 | } | |||
193 | q->q_sc = sc; | |||
194 | q->q_index = 0; | |||
195 | ||||
196 | sc->sc_queues = q; | |||
197 | sc->sc_nqueues = 1; | |||
198 | ||||
199 | /* | |||
200 | * Allocate interrupt. | |||
201 | */ | |||
202 | if (pci_intr_map_msi(pa, &ih) == 0) | |||
203 | sc->rge_flags |= RGE_FLAG_MSI0x00000001; | |||
204 | else if (pci_intr_map(pa, &ih) != 0) { | |||
205 | printf(": couldn't map interrupt\n"); | |||
206 | return; | |||
207 | } | |||
208 | intrstr = pci_intr_string(pc, ih); | |||
209 | sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100, rge_intr, | |||
210 | sc, sc->sc_dev.dv_xname); | |||
211 | if (sc->sc_ih == NULL((void *)0)) { | |||
212 | printf(": couldn't establish interrupt"); | |||
213 | if (intrstr != NULL((void *)0)) | |||
214 | printf(" at %s", intrstr); | |||
215 | printf("\n"); | |||
216 | return; | |||
217 | } | |||
218 | printf(": %s", intrstr); | |||
219 | ||||
220 | sc->sc_dmat = pa->pa_dmat; | |||
221 | sc->sc_pc = pa->pa_pc; | |||
222 | sc->sc_tag = pa->pa_tag; | |||
223 | ||||
224 | /* Determine hardware revision */ | |||
225 | hwrev = RGE_READ_4(sc, RGE_TXCFG)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0040)) ) & RGE_TXCFG_HWREV0x7cf00000; | |||
226 | switch (hwrev) { | |||
227 | case 0x60800000: | |||
228 | sc->rge_type = MAC_CFG2; | |||
229 | break; | |||
230 | case 0x60900000: | |||
231 | sc->rge_type = MAC_CFG3; | |||
232 | break; | |||
233 | case 0x64000000: | |||
234 | sc->rge_type = MAC_CFG4; | |||
235 | break; | |||
236 | case 0x64100000: | |||
237 | sc->rge_type = MAC_CFG5; | |||
238 | break; | |||
239 | default: | |||
240 | printf(": unknown version 0x%08x\n", hwrev); | |||
241 | return; | |||
242 | } | |||
243 | ||||
244 | rge_config_imtype(sc, RGE_IMTYPE_SIM1); | |||
245 | ||||
246 | /* | |||
247 | * PCI Express check. | |||
248 | */ | |||
249 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS0x10, | |||
250 | &offset, NULL((void *)0))) { | |||
251 | /* Disable PCIe ASPM and ECPM. */ | |||
252 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, | |||
253 | offset + PCI_PCIE_LCSR0x10); | |||
254 | reg &= ~(PCI_PCIE_LCSR_ASPM_L0S0x00000001 | PCI_PCIE_LCSR_ASPM_L10x00000002 | | |||
255 | PCI_PCIE_LCSR_ECPM0x00000100); | |||
256 | pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCI_PCIE_LCSR0x10, | |||
257 | reg); | |||
258 | } | |||
259 | ||||
260 | rge_exit_oob(sc); | |||
261 | rge_hw_init(sc); | |||
262 | ||||
263 | rge_get_macaddr(sc, eaddr); | |||
264 | printf(", address %s\n", ether_sprintf(eaddr)); | |||
265 | ||||
266 | memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN)__builtin_memcpy((sc->sc_arpcom.ac_enaddr), (eaddr), (6)); | |||
267 | ||||
268 | rge_set_phy_power(sc, 1); | |||
269 | rge_phy_config(sc); | |||
270 | ||||
271 | if (rge_allocmem(sc)) | |||
272 | return; | |||
273 | ||||
274 | ifp = &sc->sc_arpcom.ac_if; | |||
275 | ifp->if_softc = sc; | |||
276 | strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ16); | |||
277 | ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000; | |||
278 | ifp->if_xflags = IFXF_MPSAFE0x1; | |||
279 | ifp->if_ioctl = rge_ioctl; | |||
280 | ifp->if_qstart = rge_start; | |||
281 | ifp->if_watchdog = rge_watchdog; | |||
282 | ifq_set_maxlen(&ifp->if_snd, RGE_TX_LIST_CNT - 1)((&ifp->if_snd)->ifq_maxlen = (1024 - 1)); | |||
283 | ifp->if_hardmtu = RGE_JUMBO_MTU(9216 - ((6 * 2) + 2) - 4 - 4); | |||
284 | ||||
285 | ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_IPv40x00000001 | | |||
286 | IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004; | |||
287 | ||||
288 | #if NVLAN1 > 0 | |||
289 | ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020; | |||
290 | #endif | |||
291 | ||||
292 | #ifndef SMALL_KERNEL | |||
293 | ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_WOL0x00008000; | |||
294 | ifp->if_wol = rge_wol; | |||
295 | rge_wol(ifp, 0); | |||
296 | #endif | |||
297 | timeout_set(&sc->sc_timeout, rge_tick, sc); | |||
298 | task_set(&sc->sc_task, rge_txstart, sc); | |||
299 | ||||
300 | /* Initialize ifmedia structures. */ | |||
301 | ifmedia_init(&sc->sc_media, IFM_IMASK0xff00000000000000ULL, rge_ifmedia_upd, | |||
302 | rge_ifmedia_sts); | |||
303 | rge_add_media_types(sc); | |||
304 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0)); | |||
305 | ifmedia_set(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL); | |||
306 | sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media; | |||
307 | ||||
308 | if_attach(ifp); | |||
309 | ether_ifattach(ifp); | |||
310 | } | |||
311 | ||||
312 | int | |||
313 | rge_activate(struct device *self, int act) | |||
314 | { | |||
315 | #ifndef SMALL_KERNEL | |||
316 | struct rge_softc *sc = (struct rge_softc *)self; | |||
317 | #endif | |||
318 | int rv = 0; | |||
319 | ||||
320 | switch (act) { | |||
321 | case DVACT_POWERDOWN6: | |||
322 | rv = config_activate_children(self, act); | |||
323 | #ifndef SMALL_KERNEL | |||
324 | rge_wol_power(sc); | |||
325 | #endif | |||
326 | break; | |||
327 | default: | |||
328 | rv = config_activate_children(self, act); | |||
329 | break; | |||
330 | } | |||
331 | return (rv); | |||
332 | } | |||
333 | ||||
334 | int | |||
335 | rge_intr(void *arg) | |||
336 | { | |||
337 | struct rge_softc *sc = arg; | |||
338 | struct rge_queues *q = sc->sc_queues; | |||
339 | struct ifnet *ifp = &sc->sc_arpcom.ac_if; | |||
340 | uint32_t status; | |||
341 | int claimed = 0, rv; | |||
342 | ||||
343 | if (!(ifp->if_flags & IFF_RUNNING0x40)) | |||
344 | return (0); | |||
345 | ||||
346 | /* Disable interrupts. */ | |||
347 | RGE_WRITE_4(sc, RGE_IMR, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0038) , (0))); | |||
348 | ||||
349 | if (!(sc->rge_flags & RGE_FLAG_MSI0x00000001)) { | |||
350 | if ((RGE_READ_4(sc, RGE_ISR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x003c)) ) & sc->rge_intrs) == 0) | |||
351 | return (0); | |||
352 | } | |||
353 | ||||
354 | status = RGE_READ_4(sc, RGE_ISR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x003c)) ); | |||
355 | if (status) | |||
356 | RGE_WRITE_4(sc, RGE_ISR, status)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x003c) , (status))); | |||
357 | ||||
358 | if (status & RGE_ISR_PCS_TIMEOUT0x00004000) | |||
359 | claimed = 1; | |||
360 | ||||
361 | rv = 0; | |||
362 | if (status & sc->rge_intrs) { | |||
363 | rv |= rge_rxeof(q); | |||
364 | rv |= rge_txeof(q); | |||
365 | ||||
366 | if (status & RGE_ISR_SYSTEM_ERR0x00008000) { | |||
367 | KERNEL_LOCK()_kernel_lock(); | |||
368 | rge_init(ifp); | |||
369 | KERNEL_UNLOCK()_kernel_unlock(); | |||
370 | } | |||
371 | claimed = 1; | |||
372 | } | |||
373 | ||||
374 | if (sc->rge_timerintr) { | |||
375 | if (!rv) { | |||
376 | /* | |||
377 | * Nothing needs to be processed, fallback | |||
378 | * to use TX/RX interrupts. | |||
379 | */ | |||
380 | rge_setup_intr(sc, RGE_IMTYPE_NONE0); | |||
381 | ||||
382 | /* | |||
383 | * Recollect, mainly to avoid the possible | |||
384 | * race introduced by changing interrupt | |||
385 | * masks. | |||
386 | */ | |||
387 | rge_rxeof(q); | |||
388 | rge_txeof(q); | |||
389 | } else | |||
390 | RGE_WRITE_4(sc, RGE_TIMERCNT, 1)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0048) , (1))); | |||
391 | } else if (rv) { | |||
392 | /* | |||
393 | * Assume that using simulated interrupt moderation | |||
394 | * (hardware timer based) could reduce the interrupt | |||
395 | * rate. | |||
396 | */ | |||
397 | rge_setup_intr(sc, RGE_IMTYPE_SIM1); | |||
398 | } | |||
399 | ||||
400 | RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0038) , (sc->rge_intrs))); | |||
401 | ||||
402 | return (claimed); | |||
403 | } | |||
404 | ||||
405 | int | |||
406 | rge_encap(struct rge_queues *q, struct mbuf *m, int idx) | |||
407 | { | |||
408 | struct rge_softc *sc = q->q_sc; | |||
409 | struct rge_tx_desc *d = NULL((void *)0); | |||
410 | struct rge_txq *txq; | |||
411 | bus_dmamap_t txmap; | |||
412 | uint32_t cmdsts, cflags = 0; | |||
413 | int cur, error, i, last, nsegs; | |||
414 | ||||
415 | /* | |||
416 | * Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested. | |||
417 | * Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not | |||
418 | * take affect. | |||
419 | */ | |||
420 | if ((m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & | |||
421 | (M_IPV4_CSUM_OUT0x0001 | M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004)) != 0) { | |||
422 | cflags |= RGE_TDEXTSTS_IPCSUM0x20000000; | |||
423 | if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002) | |||
424 | cflags |= RGE_TDEXTSTS_TCPCSUM0x40000000; | |||
425 | if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004) | |||
426 | cflags |= RGE_TDEXTSTS_UDPCSUM0x80000000; | |||
427 | } | |||
428 | ||||
429 | txq = &q->q_tx.rge_txq[idx]; | |||
430 | txmap = txq->txq_dmamap; | |||
431 | ||||
432 | error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), ( txmap), (m), (0x0001)); | |||
433 | switch (error) { | |||
434 | case 0: | |||
435 | break; | |||
436 | case EFBIG27: /* mbuf chain is too fragmented */ | |||
437 | if (m_defrag(m, M_DONTWAIT0x0002) == 0 && | |||
438 | bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), ( txmap), (m), (0x0001)) | |||
439 | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), ( txmap), (m), (0x0001)) == 0) | |||
440 | break; | |||
441 | ||||
442 | /* FALLTHROUGH */ | |||
443 | default: | |||
444 | return (0); | |||
445 | } | |||
446 | ||||
447 | bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txmap ), (0), (txmap->dm_mapsize), (0x04)) | |||
448 | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txmap ), (0), (txmap->dm_mapsize), (0x04)); | |||
449 | ||||
450 | nsegs = txmap->dm_nsegs; | |||
451 | ||||
452 | /* Set up hardware VLAN tagging. */ | |||
453 | #if NVLAN1 > 0 | |||
454 | if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020) | |||
455 | cflags |= swap16(m->m_pkthdr.ether_vtag | RGE_TDEXTSTS_VTAG)(__uint16_t)(__builtin_constant_p(m->M_dat.MH.MH_pkthdr.ether_vtag | 0x00020000) ? (__uint16_t)(((__uint16_t)(m->M_dat.MH.MH_pkthdr .ether_vtag | 0x00020000) & 0xffU) << 8 | ((__uint16_t )(m->M_dat.MH.MH_pkthdr.ether_vtag | 0x00020000) & 0xff00U ) >> 8) : __swap16md(m->M_dat.MH.MH_pkthdr.ether_vtag | 0x00020000)); | |||
456 | #endif | |||
457 | ||||
458 | cur = idx; | |||
459 | cmdsts = RGE_TDCMDSTS_SOF0x20000000; | |||
460 | ||||
461 | for (i = 0; i < txmap->dm_nsegs; i++) { | |||
462 | d = &q->q_tx.rge_tx_list[cur]; | |||
463 | ||||
464 | d->rge_extsts = htole32(cflags)((__uint32_t)(cflags)); | |||
465 | d->rge_addrlo = htole32(RGE_ADDR_LO(txmap->dm_segs[i].ds_addr))((__uint32_t)(((uint64_t) (txmap->dm_segs[i].ds_addr) & 0xffffffff))); | |||
466 | d->rge_addrhi = htole32(RGE_ADDR_HI(txmap->dm_segs[i].ds_addr))((__uint32_t)(((uint64_t) (txmap->dm_segs[i].ds_addr) >> 32))); | |||
467 | ||||
468 | cmdsts |= txmap->dm_segs[i].ds_len; | |||
469 | ||||
470 | if (cur == RGE_TX_LIST_CNT1024 - 1) | |||
471 | cmdsts |= RGE_TDCMDSTS_EOR0x40000000; | |||
472 | ||||
473 | d->rge_cmdsts = htole32(cmdsts)((__uint32_t)(cmdsts)); | |||
474 | ||||
475 | last = cur; | |||
476 | cmdsts = RGE_TDCMDSTS_OWN0x80000000; | |||
477 | cur = RGE_NEXT_TX_DESC(cur)(((cur) + 1) % 1024); | |||
478 | } | |||
479 | ||||
480 | /* Set EOF on the last descriptor. */ | |||
481 | d->rge_cmdsts |= htole32(RGE_TDCMDSTS_EOF)((__uint32_t)(0x10000000)); | |||
| ||||
482 | ||||
483 | /* Transfer ownership of packet to the chip. */ | |||
484 | d = &q->q_tx.rge_tx_list[idx]; | |||
485 | ||||
486 | d->rge_cmdsts |= htole32(RGE_TDCMDSTS_OWN)((__uint32_t)(0x80000000)); | |||
487 | ||||
488 | bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (cur * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)) | |||
489 | cur * sizeof(struct rge_tx_desc), sizeof(struct rge_tx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (cur * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)) | |||
490 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (cur * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)); | |||
491 | ||||
492 | /* Update info of TX queue and descriptors. */ | |||
493 | txq->txq_mbuf = m; | |||
494 | txq->txq_descidx = last; | |||
495 | ||||
496 | return (nsegs); | |||
497 | } | |||
498 | ||||
499 | int | |||
500 | rge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) | |||
501 | { | |||
502 | struct rge_softc *sc = ifp->if_softc; | |||
503 | struct ifreq *ifr = (struct ifreq *)data; | |||
504 | int s, error = 0; | |||
505 | ||||
506 | s = splnet()splraise(0x7); | |||
507 | ||||
508 | switch (cmd) { | |||
509 | case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((12))): | |||
510 | ifp->if_flags |= IFF_UP0x1; | |||
511 | if (!(ifp->if_flags & IFF_RUNNING0x40)) | |||
512 | rge_init(ifp); | |||
513 | break; | |||
514 | case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((16))): | |||
515 | if (ifp->if_flags & IFF_UP0x1) { | |||
516 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
517 | error = ENETRESET52; | |||
518 | else | |||
519 | rge_init(ifp); | |||
520 | } else { | |||
521 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
522 | rge_stop(ifp); | |||
523 | } | |||
524 | break; | |||
525 | case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct ifmediareq) & 0x1fff) << 16) | ((('i')) << 8) | ((56))): | |||
526 | case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct ifreq) & 0x1fff) << 16) | ((('i')) << 8) | ((55))): | |||
527 | error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); | |||
528 | break; | |||
529 | case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((170))): | |||
530 | error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data, | |||
531 | NULL((void *)0), RGE_JUMBO_FRAMELEN9216, &sc->sc_queues->q_rx.rge_rx_ring); | |||
532 | break; | |||
533 | default: | |||
534 | error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); | |||
535 | } | |||
536 | ||||
537 | if (error == ENETRESET52) { | |||
538 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
539 | rge_iff(sc); | |||
540 | error = 0; | |||
541 | } | |||
542 | ||||
543 | splx(s)spllower(s); | |||
544 | return (error); | |||
545 | } | |||
546 | ||||
547 | void | |||
548 | rge_start(struct ifqueue *ifq) | |||
549 | { | |||
550 | struct ifnet *ifp = ifq->ifq_if; | |||
551 | struct rge_softc *sc = ifp->if_softc; | |||
552 | struct rge_queues *q = sc->sc_queues; | |||
553 | struct mbuf *m; | |||
554 | int free, idx, used; | |||
555 | int queued = 0; | |||
556 | ||||
557 | if (!LINK_STATE_IS_UP(ifp->if_link_state)((ifp->if_data.ifi_link_state) >= 4 || (ifp->if_data .ifi_link_state) == 0)) { | |||
| ||||
558 | ifq_purge(ifq); | |||
559 | return; | |||
560 | } | |||
561 | ||||
562 | /* Calculate free space. */ | |||
563 | idx = q->q_tx.rge_txq_prodidx; | |||
564 | free = q->q_tx.rge_txq_considx; | |||
565 | if (free <= idx) | |||
566 | free += RGE_TX_LIST_CNT1024; | |||
567 | free -= idx; | |||
568 | ||||
569 | for (;;) { | |||
570 | if (RGE_TX_NSEGS32 >= free + 2) { | |||
571 | ifq_set_oactive(&ifp->if_snd); | |||
572 | break; | |||
573 | } | |||
574 | ||||
575 | m = ifq_dequeue(ifq); | |||
576 | if (m == NULL((void *)0)) | |||
577 | break; | |||
578 | ||||
579 | used = rge_encap(q, m, idx); | |||
580 | if (used == 0) { | |||
581 | m_freem(m); | |||
582 | continue; | |||
583 | } | |||
584 | ||||
585 | KASSERT(used <= free)((used <= free) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_rge.c" , 585, "used <= free")); | |||
586 | free -= used; | |||
587 | ||||
588 | #if NBPFILTER1 > 0 | |||
589 | if (ifp->if_bpf) | |||
590 | bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1)); | |||
591 | #endif | |||
592 | ||||
593 | idx += used; | |||
594 | if (idx >= RGE_TX_LIST_CNT1024) | |||
595 | idx -= RGE_TX_LIST_CNT1024; | |||
596 | ||||
597 | queued++; | |||
598 | } | |||
599 | ||||
600 | if (queued == 0) | |||
601 | return; | |||
602 | ||||
603 | /* Set a timeout in case the chip goes out to lunch. */ | |||
604 | ifp->if_timer = 5; | |||
605 | ||||
606 | q->q_tx.rge_txq_prodidx = idx; | |||
607 | ifq_serialize(ifq, &sc->sc_task); | |||
608 | } | |||
609 | ||||
610 | void | |||
611 | rge_watchdog(struct ifnet *ifp) | |||
612 | { | |||
613 | struct rge_softc *sc = ifp->if_softc; | |||
614 | ||||
615 | printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); | |||
616 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
617 | ||||
618 | rge_init(ifp); | |||
619 | } | |||
620 | ||||
621 | int | |||
622 | rge_init(struct ifnet *ifp) | |||
623 | { | |||
624 | struct rge_softc *sc = ifp->if_softc; | |||
625 | struct rge_queues *q = sc->sc_queues; | |||
626 | uint32_t val; | |||
627 | int i; | |||
628 | ||||
629 | rge_stop(ifp); | |||
630 | ||||
631 | /* Set MAC address. */ | |||
632 | rge_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); | |||
633 | ||||
634 | /* Set Maximum frame size. */ | |||
635 | RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x00da) , (9216))); | |||
636 | ||||
637 | /* Initialize RX and TX descriptors lists. */ | |||
638 | rge_rx_list_init(q); | |||
639 | rge_tx_list_init(q); | |||
640 | ||||
641 | /* Load the addresses of the RX and TX lists into the chip. */ | |||
642 | RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00e4) , (((uint64_t) (q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr ) & 0xffffffff)))) | |||
643 | RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00e4) , (((uint64_t) (q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr ) & 0xffffffff)))); | |||
644 | RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00e8) , (((uint64_t) (q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr ) >> 32)))) | |||
645 | RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00e8) , (((uint64_t) (q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr ) >> 32)))); | |||
646 | RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0020) , (((uint64_t) (q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr ) & 0xffffffff)))) | |||
647 | RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0020) , (((uint64_t) (q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr ) & 0xffffffff)))); | |||
648 | RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0024) , (((uint64_t) (q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr ) >> 32)))) | |||
649 | RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0024) , (((uint64_t) (q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr ) >> 32)))); | |||
650 | ||||
651 | RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) | (0xc0)))); | |||
652 | ||||
653 | RGE_CLRBIT_1(sc, 0xf1, 0x80)((sc->rge_btag)->write_1((sc->rge_bhandle), (0xf1), ( ((sc->rge_btag)->read_1((sc->rge_bhandle), (0xf1))) & ~(0x80)))); | |||
654 | RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0053) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0053 ))) & ~(0x80)))); | |||
655 | RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) & ~(0x01)))); | |||
656 | RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_RDY_TO_L23)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0054) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0054 ))) & ~(0x02)))); | |||
657 | ||||
658 | /* Clear interrupt moderation timer. */ | |||
659 | for (i = 0; i < 64; i++) | |||
660 | RGE_WRITE_4(sc, RGE_INTMITI(i), 0)((sc->rge_btag)->write_4((sc->rge_bhandle), ((0x0a00 + (i) * 4)), (0))); | |||
661 | ||||
662 | /* Set the initial RX and TX configurations. */ | |||
663 | RGE_WRITE_4(sc, RGE_RXCFG, RGE_RXCFG_CONFIG)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (0x40c00700))); | |||
664 | RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0040) , (0x03000700))); | |||
665 | ||||
666 | val = rge_read_csi(sc, 0x70c) & ~0xff000000; | |||
667 | rge_write_csi(sc, 0x70c, val | 0x27000000); | |||
668 | ||||
669 | /* Enable hardware optimization function. */ | |||
670 | val = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x78) & ~0x00007000; | |||
671 | pci_conf_write(sc->sc_pc, sc->sc_tag, 0x78, val | 0x00005000); | |||
672 | ||||
673 | RGE_WRITE_2(sc, 0x0382, 0x221b)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x0382) , (0x221b))); | |||
674 | ||||
675 | RGE_WRITE_1(sc, RGE_RSS_CTRL, 0)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x4500) , (0))); | |||
676 | ||||
677 | val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x4800)) ) & ~0x001c; | |||
678 | RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x4800) , (val | (fls(sc->sc_nqueues) - 1) << 2))); | |||
679 | ||||
680 | RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0052) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0052 ))) & ~(0x10)))); | |||
681 | ||||
682 | rge_write_mac_ocp(sc, 0xc140, 0xffff); | |||
683 | rge_write_mac_ocp(sc, 0xc142, 0xffff); | |||
684 | ||||
685 | RGE_MAC_SETBIT(sc, 0xeb58, 0x0001)rge_write_mac_ocp(sc, 0xeb58, rge_read_mac_ocp(sc, 0xeb58) | ( 0x0001)); | |||
686 | ||||
687 | val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700; | |||
688 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) | |||
689 | rge_write_mac_ocp(sc, 0xe614, val | 0x0400); | |||
690 | else | |||
691 | rge_write_mac_ocp(sc, 0xe614, val | 0x0200); | |||
692 | ||||
693 | val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00; | |||
694 | rge_write_mac_ocp(sc, 0xe63e, val | | |||
695 | ((fls(sc->sc_nqueues) - 1) & 0x03) << 10); | |||
696 | ||||
697 | RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030)rge_write_mac_ocp(sc, 0xe63e, rge_read_mac_ocp(sc, 0xe63e) & ~(0x0030)); | |||
698 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) | |||
699 | RGE_MAC_SETBIT(sc, 0xe63e, 0x0020)rge_write_mac_ocp(sc, 0xe63e, rge_read_mac_ocp(sc, 0xe63e) | ( 0x0020)); | |||
700 | ||||
701 | RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001)rge_write_mac_ocp(sc, 0xc0b4, rge_read_mac_ocp(sc, 0xc0b4) & ~(0x0001)); | |||
702 | RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001)rge_write_mac_ocp(sc, 0xc0b4, rge_read_mac_ocp(sc, 0xc0b4) | ( 0x0001)); | |||
703 | RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c)rge_write_mac_ocp(sc, 0xc0b4, rge_read_mac_ocp(sc, 0xc0b4) | ( 0x000c)); | |||
704 | ||||
705 | val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff; | |||
706 | rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033); | |||
707 | ||||
708 | val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0; | |||
709 | rge_write_mac_ocp(sc, 0xeb50, val | 0x0040); | |||
710 | ||||
711 | val = rge_read_mac_ocp(sc, 0xe056) & ~0x00f0; | |||
712 | rge_write_mac_ocp(sc, 0xe056, val | 0x0030); | |||
713 | ||||
714 | RGE_WRITE_1(sc, RGE_TDFNR, 0x10)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0057) , (0x10))); | |||
715 | ||||
716 | RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_TX_10M_PS_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00d0) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00d0 ))) | (0x80)))); | |||
717 | ||||
718 | RGE_MAC_CLRBIT(sc, 0xe040, 0x1000)rge_write_mac_ocp(sc, 0xe040, rge_read_mac_ocp(sc, 0xe040) & ~(0x1000)); | |||
719 | ||||
720 | val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003; | |||
721 | rge_write_mac_ocp(sc, 0xea1c, val | 0x0001); | |||
722 | ||||
723 | val = rge_read_mac_ocp(sc, 0xe0c0) & ~0x4f0f; | |||
724 | rge_write_mac_ocp(sc, 0xe0c0, val | 0x4403); | |||
725 | ||||
726 | RGE_MAC_SETBIT(sc, 0xe052, 0x0068)rge_write_mac_ocp(sc, 0xe052, rge_read_mac_ocp(sc, 0xe052) | ( 0x0068)); | |||
727 | RGE_MAC_CLRBIT(sc, 0xe052, 0x0080)rge_write_mac_ocp(sc, 0xe052, rge_read_mac_ocp(sc, 0xe052) & ~(0x0080)); | |||
728 | ||||
729 | val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff; | |||
730 | rge_write_mac_ocp(sc, 0xd430, val | 0x047f); | |||
731 | ||||
732 | RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00d0) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00d0 ))) | (0x40 | 0x80)))); | |||
733 | ||||
734 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) | |||
735 | RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00d3) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00d3 ))) | (0x01)))); | |||
736 | ||||
737 | /* Disable EEE plus. */ | |||
738 | RGE_MAC_CLRBIT(sc, 0xe080, 0x0002)rge_write_mac_ocp(sc, 0xe080, rge_read_mac_ocp(sc, 0xe080) & ~(0x0002)); | |||
739 | ||||
740 | RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004)rge_write_mac_ocp(sc, 0xea1c, rge_read_mac_ocp(sc, 0xea1c) & ~(0x0004)); | |||
741 | ||||
742 | RGE_MAC_SETBIT(sc, 0xeb54, 0x0001)rge_write_mac_ocp(sc, 0xeb54, rge_read_mac_ocp(sc, 0xeb54) | ( 0x0001)); | |||
743 | DELAY(1)(*delay_func)(1); | |||
744 | RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001)rge_write_mac_ocp(sc, 0xeb54, rge_read_mac_ocp(sc, 0xeb54) & ~(0x0001)); | |||
745 | ||||
746 | RGE_CLRBIT_4(sc, 0x1880, 0x0030)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x1880) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x1880 ))) & ~(0x0030)))); | |||
747 | ||||
748 | rge_write_mac_ocp(sc, 0xe098, 0xc302); | |||
749 | ||||
750 | if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020) | |||
751 | RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) | (0x00c00000)))); | |||
752 | ||||
753 | RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x00e0) , (((sc->rge_btag)->read_2((sc->rge_bhandle), (0x00e0 ))) | (0x0020)))); | |||
754 | ||||
755 | for (i = 0; i < 10; i++) { | |||
756 | if (!(rge_read_mac_ocp(sc, 0xe00e) & 0x2000)) | |||
757 | break; | |||
758 | DELAY(1000)(*delay_func)(1000); | |||
759 | } | |||
760 | ||||
761 | /* Disable RXDV gate. */ | |||
762 | RGE_CLRBIT_1(sc, RGE_PPSW, 0x08)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00f2) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00f2 ))) & ~(0x08)))); | |||
763 | DELAY(2000)(*delay_func)(2000); | |||
764 | ||||
765 | rge_ifmedia_upd(ifp); | |||
766 | ||||
767 | /* Enable transmit and receive. */ | |||
768 | RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0037) , (0x04 | 0x08))); | |||
769 | ||||
770 | /* Program promiscuous mode and multicast filters. */ | |||
771 | rge_iff(sc); | |||
772 | ||||
773 | RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0053) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0053 ))) & ~(0x80)))); | |||
774 | RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) & ~(0x01)))); | |||
775 | ||||
776 | RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) & ~(0xc0)))); | |||
777 | ||||
778 | /* Enable interrupts. */ | |||
779 | rge_setup_intr(sc, RGE_IMTYPE_SIM1); | |||
780 | ||||
781 | ifp->if_flags |= IFF_RUNNING0x40; | |||
782 | ifq_clr_oactive(&ifp->if_snd); | |||
783 | ||||
784 | timeout_add_sec(&sc->sc_timeout, 1); | |||
785 | ||||
786 | return (0); | |||
787 | } | |||
788 | ||||
789 | /* | |||
790 | * Stop the adapter and free any mbufs allocated to the RX and TX lists. | |||
791 | */ | |||
792 | void | |||
793 | rge_stop(struct ifnet *ifp) | |||
794 | { | |||
795 | struct rge_softc *sc = ifp->if_softc; | |||
796 | struct rge_queues *q = sc->sc_queues; | |||
797 | int i; | |||
798 | ||||
799 | timeout_del(&sc->sc_timeout); | |||
800 | ||||
801 | ifp->if_timer = 0; | |||
802 | ifp->if_flags &= ~IFF_RUNNING0x40; | |||
803 | sc->rge_timerintr = 0; | |||
804 | ||||
805 | RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))) | |||
806 | RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))) | |||
807 | RGE_RXCFG_ERRPKT)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))); | |||
808 | ||||
809 | RGE_WRITE_4(sc, RGE_IMR, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0038) , (0))); | |||
810 | RGE_WRITE_4(sc, RGE_ISR, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x003c) , (0))); | |||
811 | ||||
812 | /* Clear timer interrupts. */ | |||
813 | RGE_WRITE_4(sc, RGE_TIMERINT0, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0058) , (0))); | |||
814 | RGE_WRITE_4(sc, RGE_TIMERINT1, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x005c) , (0))); | |||
815 | RGE_WRITE_4(sc, RGE_TIMERINT2, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x008c) , (0))); | |||
816 | RGE_WRITE_4(sc, RGE_TIMERINT3, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00f4) , (0))); | |||
817 | ||||
818 | rge_reset(sc); | |||
819 | ||||
820 | intr_barrier(sc->sc_ih); | |||
821 | ifq_barrier(&ifp->if_snd); | |||
822 | ifq_clr_oactive(&ifp->if_snd); | |||
823 | ||||
824 | if (q->q_rx.rge_head != NULL((void *)0)) { | |||
825 | m_freem(q->q_rx.rge_head); | |||
826 | q->q_rx.rge_head = q->q_rx.rge_tail = NULL((void *)0); | |||
827 | } | |||
828 | ||||
829 | /* Free the TX list buffers. */ | |||
830 | for (i = 0; i < RGE_TX_LIST_CNT1024; i++) { | |||
831 | if (q->q_tx.rge_txq[i].txq_mbuf != NULL((void *)0)) { | |||
832 | bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (q-> q_tx.rge_txq[i].txq_dmamap)) | |||
833 | q->q_tx.rge_txq[i].txq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (q-> q_tx.rge_txq[i].txq_dmamap)); | |||
834 | m_freem(q->q_tx.rge_txq[i].txq_mbuf); | |||
835 | q->q_tx.rge_txq[i].txq_mbuf = NULL((void *)0); | |||
836 | } | |||
837 | } | |||
838 | ||||
839 | /* Free the RX list buffers. */ | |||
840 | for (i = 0; i < RGE_RX_LIST_CNT1024; i++) { | |||
841 | if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL((void *)0)) { | |||
842 | bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (q-> q_rx.rge_rxq[i].rxq_dmamap)) | |||
843 | q->q_rx.rge_rxq[i].rxq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (q-> q_rx.rge_rxq[i].rxq_dmamap)); | |||
844 | m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); | |||
845 | q->q_rx.rge_rxq[i].rxq_mbuf = NULL((void *)0); | |||
846 | } | |||
847 | } | |||
848 | } | |||
849 | ||||
850 | /* | |||
851 | * Set media options. | |||
852 | */ | |||
853 | int | |||
854 | rge_ifmedia_upd(struct ifnet *ifp) | |||
855 | { | |||
856 | struct rge_softc *sc = ifp->if_softc; | |||
857 | struct ifmedia *ifm = &sc->sc_media; | |||
858 | int anar, gig, val; | |||
859 | ||||
860 | if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL) | |||
861 | return (EINVAL22); | |||
862 | ||||
863 | /* Disable Gigabit Lite. */ | |||
864 | RGE_PHY_CLRBIT(sc, 0xa428, 0x0200)rge_write_phy_ocp(sc, 0xa428, rge_read_phy_ocp(sc, 0xa428) & ~(0x0200)); | |||
865 | RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001)rge_write_phy_ocp(sc, 0xa5ea, rge_read_phy_ocp(sc, 0xa5ea) & ~(0x0001)); | |||
866 | ||||
867 | val = rge_read_phy_ocp(sc, 0xa5d4); | |||
868 | val &= ~RGE_ADV_2500TFDX0x0080; | |||
869 | ||||
870 | anar = gig = 0; | |||
871 | switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) { | |||
872 | case IFM_AUTO0ULL: | |||
873 | anar = ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
874 | gig = GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
875 | val |= RGE_ADV_2500TFDX0x0080; | |||
876 | break; | |||
877 | case IFM_2500_T34: | |||
878 | anar = ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
879 | gig = GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
880 | val |= RGE_ADV_2500TFDX0x0080; | |||
881 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(2500)((((2500) * 1000ULL) * 1000ULL)); | |||
882 | break; | |||
883 | case IFM_1000_T16: | |||
884 | anar = ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
885 | gig = GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
886 | ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL))); | |||
887 | break; | |||
888 | case IFM_100_TX6: | |||
889 | gig = rge_read_phy(sc, 0, MII_100T2CR0x09) & | |||
890 | ~(GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100); | |||
891 | anar = ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL) ? | |||
892 | ANAR_TX0x0080 | ANAR_TX_FD0x0100 | ANAR_10_FD0x0040 | ANAR_100x0020 : | |||
893 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
894 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(100)((((100) * 1000ULL) * 1000ULL)); | |||
895 | break; | |||
896 | case IFM_10_T3: | |||
897 | gig = rge_read_phy(sc, 0, MII_100T2CR0x09) & | |||
898 | ~(GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100); | |||
899 | anar = ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL) ? | |||
900 | ANAR_10_FD0x0040 | ANAR_100x0020 : ANAR_100x0020; | |||
901 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(10)((((10) * 1000ULL) * 1000ULL)); | |||
902 | break; | |||
903 | default: | |||
904 | printf("%s: unsupported media type\n", sc->sc_dev.dv_xname); | |||
905 | return (EINVAL22); | |||
906 | } | |||
907 | ||||
908 | rge_write_phy(sc, 0, MII_ANAR0x04, anar | ANAR_PAUSE_ASYM(2 << 10) | ANAR_FC0x0400); | |||
909 | rge_write_phy(sc, 0, MII_100T2CR0x09, gig); | |||
910 | rge_write_phy_ocp(sc, 0xa5d4, val); | |||
911 | rge_write_phy(sc, 0, MII_BMCR0x00, BMCR_RESET0x8000 | BMCR_AUTOEN0x1000 | | |||
912 | BMCR_STARTNEG0x0200); | |||
913 | ||||
914 | return (0); | |||
915 | } | |||
916 | ||||
917 | /* | |||
918 | * Report current media status. | |||
919 | */ | |||
920 | void | |||
921 | rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) | |||
922 | { | |||
923 | struct rge_softc *sc = ifp->if_softc; | |||
924 | uint16_t status = 0; | |||
925 | ||||
926 | ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL; | |||
927 | ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL; | |||
928 | ||||
929 | if (rge_get_link_status(sc)) { | |||
930 | ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
931 | ||||
932 | status = RGE_READ_2(sc, RGE_PHYSTAT)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x006c)) ); | |||
933 | if ((status & RGE_PHYSTAT_FDX0x0001) || | |||
934 | (status & RGE_PHYSTAT_2500MBPS0x0400)) | |||
935 | ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL; | |||
936 | else | |||
937 | ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL; | |||
938 | ||||
939 | if (status & RGE_PHYSTAT_10MBPS0x0004) | |||
940 | ifmr->ifm_active |= IFM_10_T3; | |||
941 | else if (status & RGE_PHYSTAT_100MBPS0x0008) | |||
942 | ifmr->ifm_active |= IFM_100_TX6; | |||
943 | else if (status & RGE_PHYSTAT_1000MBPS0x0010) | |||
944 | ifmr->ifm_active |= IFM_1000_T16; | |||
945 | else if (status & RGE_PHYSTAT_2500MBPS0x0400) | |||
946 | ifmr->ifm_active |= IFM_2500_T34; | |||
947 | } | |||
948 | } | |||
949 | ||||
950 | /* | |||
951 | * Allocate memory for RX/TX rings. | |||
952 | */ | |||
953 | int | |||
954 | rge_allocmem(struct rge_softc *sc) | |||
955 | { | |||
956 | struct rge_queues *q = sc->sc_queues; | |||
957 | int error, i; | |||
958 | ||||
959 | /* Allocate DMA'able memory for the TX ring. */ | |||
960 | error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sizeof (struct rge_tx_desc) * 1024)), (1), ((sizeof(struct rge_tx_desc ) * 1024)), (0), (0x0001), (&q->q_tx.rge_tx_list_map)) | |||
961 | RGE_TX_LIST_SZ, 0, BUS_DMA_NOWAIT, &q->q_tx.rge_tx_list_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sizeof (struct rge_tx_desc) * 1024)), (1), ((sizeof(struct rge_tx_desc ) * 1024)), (0), (0x0001), (&q->q_tx.rge_tx_list_map)); | |||
962 | if (error) { | |||
963 | printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname); | |||
964 | return (error); | |||
965 | } | |||
966 | error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_tx_desc) * 1024)), (256), (0), (&q->q_tx.rge_tx_listseg ), (1), (&q->q_tx.rge_tx_listnseg), (0x0001| 0x1000)) | |||
967 | &q->q_tx.rge_tx_listseg, 1, &q->q_tx.rge_tx_listnseg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_tx_desc) * 1024)), (256), (0), (&q->q_tx.rge_tx_listseg ), (1), (&q->q_tx.rge_tx_listnseg), (0x0001| 0x1000)) | |||
968 | BUS_DMA_NOWAIT| BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_tx_desc) * 1024)), (256), (0), (&q->q_tx.rge_tx_listseg ), (1), (&q->q_tx.rge_tx_listnseg), (0x0001| 0x1000)); | |||
969 | if (error) { | |||
970 | printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname); | |||
971 | return (error); | |||
972 | } | |||
973 | ||||
974 | /* Load the map for the TX ring. */ | |||
975 | error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg), ((sizeof (struct rge_tx_desc) * 1024)), ((caddr_t *)&q->q_tx.rge_tx_list ), (0x0001 | 0x0004)) | |||
976 | q->q_tx.rge_tx_listnseg, RGE_TX_LIST_SZ,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg), ((sizeof (struct rge_tx_desc) * 1024)), ((caddr_t *)&q->q_tx.rge_tx_list ), (0x0001 | 0x0004)) | |||
977 | (caddr_t *)&q->q_tx.rge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg), ((sizeof (struct rge_tx_desc) * 1024)), ((caddr_t *)&q->q_tx.rge_tx_list ), (0x0001 | 0x0004)); | |||
978 | if (error) { | |||
979 | printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname); | |||
980 | bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg)) | |||
981 | q->q_tx.rge_tx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg)); | |||
982 | return (error); | |||
983 | } | |||
984 | error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (q->q_tx.rge_tx_list), ((sizeof(struct rge_tx_desc) * 1024)), (((void *)0)), (0x0001)) | |||
985 | q->q_tx.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (q->q_tx.rge_tx_list), ((sizeof(struct rge_tx_desc) * 1024)), (((void *)0)), (0x0001)); | |||
986 | if (error) { | |||
987 | printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname); | |||
988 | bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map)); | |||
989 | bus_dmamem_unmap(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t )q->q_tx.rge_tx_list), ((sizeof(struct rge_tx_desc) * 1024 ))) | |||
990 | (caddr_t)q->q_tx.rge_tx_list, RGE_TX_LIST_SZ)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t )q->q_tx.rge_tx_list), ((sizeof(struct rge_tx_desc) * 1024 ))); | |||
991 | bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg)) | |||
992 | q->q_tx.rge_tx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_tx.rge_tx_listseg), (q->q_tx.rge_tx_listnseg)); | |||
993 | return (error); | |||
994 | } | |||
995 | ||||
996 | /* Create DMA maps for TX buffers. */ | |||
997 | for (i = 0; i < RGE_TX_LIST_CNT1024; i++) { | |||
998 | error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (32), (9216), (0), (0x0001), (&q->q_tx.rge_txq[i].txq_dmamap )) | |||
999 | RGE_TX_NSEGS, RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (32), (9216), (0), (0x0001), (&q->q_tx.rge_txq[i].txq_dmamap )) | |||
1000 | &q->q_tx.rge_txq[i].txq_dmamap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (32), (9216), (0), (0x0001), (&q->q_tx.rge_txq[i].txq_dmamap )); | |||
1001 | if (error) { | |||
1002 | printf("%s: can't create DMA map for TX\n", | |||
1003 | sc->sc_dev.dv_xname); | |||
1004 | return (error); | |||
1005 | } | |||
1006 | } | |||
1007 | ||||
1008 | /* Allocate DMA'able memory for the RX ring. */ | |||
1009 | error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sizeof (struct rge_rx_desc) * 1024)), (1), ((sizeof(struct rge_rx_desc ) * 1024)), (0), (0x0001), (&q->q_rx.rge_rx_list_map)) | |||
1010 | RGE_RX_LIST_SZ, 0, BUS_DMA_NOWAIT, &q->q_rx.rge_rx_list_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sizeof (struct rge_rx_desc) * 1024)), (1), ((sizeof(struct rge_rx_desc ) * 1024)), (0), (0x0001), (&q->q_rx.rge_rx_list_map)); | |||
1011 | if (error) { | |||
1012 | printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname); | |||
1013 | return (error); | |||
1014 | } | |||
1015 | error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_rx_desc) * 1024)), (256), (0), (&q->q_rx.rge_rx_listseg ), (1), (&q->q_rx.rge_rx_listnseg), (0x0001| 0x1000)) | |||
1016 | &q->q_rx.rge_rx_listseg, 1, &q->q_rx.rge_rx_listnseg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_rx_desc) * 1024)), (256), (0), (&q->q_rx.rge_rx_listseg ), (1), (&q->q_rx.rge_rx_listnseg), (0x0001| 0x1000)) | |||
1017 | BUS_DMA_NOWAIT| BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((sizeof (struct rge_rx_desc) * 1024)), (256), (0), (&q->q_rx.rge_rx_listseg ), (1), (&q->q_rx.rge_rx_listnseg), (0x0001| 0x1000)); | |||
1018 | if (error) { | |||
1019 | printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname); | |||
1020 | return (error); | |||
1021 | } | |||
1022 | ||||
1023 | /* Load the map for the RX ring. */ | |||
1024 | error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg), ((sizeof (struct rge_rx_desc) * 1024)), ((caddr_t *)&q->q_rx.rge_rx_list ), (0x0001 | 0x0004)) | |||
1025 | q->q_rx.rge_rx_listnseg, RGE_RX_LIST_SZ,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg), ((sizeof (struct rge_rx_desc) * 1024)), ((caddr_t *)&q->q_rx.rge_rx_list ), (0x0001 | 0x0004)) | |||
1026 | (caddr_t *)&q->q_rx.rge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&q ->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg), ((sizeof (struct rge_rx_desc) * 1024)), ((caddr_t *)&q->q_rx.rge_rx_list ), (0x0001 | 0x0004)); | |||
1027 | if (error) { | |||
1028 | printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname); | |||
1029 | bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg)) | |||
1030 | q->q_rx.rge_rx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg)); | |||
1031 | return (error); | |||
1032 | } | |||
1033 | error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (q->q_rx.rge_rx_list), ((sizeof(struct rge_rx_desc) * 1024)), (((void *)0)), (0x0001)) | |||
1034 | q->q_rx.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (q->q_rx.rge_rx_list), ((sizeof(struct rge_rx_desc) * 1024)), (((void *)0)), (0x0001)); | |||
1035 | if (error) { | |||
1036 | printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname); | |||
1037 | bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map)); | |||
1038 | bus_dmamem_unmap(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t )q->q_rx.rge_rx_list), ((sizeof(struct rge_rx_desc) * 1024 ))) | |||
1039 | (caddr_t)q->q_rx.rge_rx_list, RGE_RX_LIST_SZ)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t )q->q_rx.rge_rx_list), ((sizeof(struct rge_rx_desc) * 1024 ))); | |||
1040 | bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg)) | |||
1041 | q->q_rx.rge_rx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (& q->q_rx.rge_rx_listseg), (q->q_rx.rge_rx_listnseg)); | |||
1042 | return (error); | |||
1043 | } | |||
1044 | ||||
1045 | /* Create DMA maps for RX buffers. */ | |||
1046 | for (i = 0; i < RGE_RX_LIST_CNT1024; i++) { | |||
1047 | error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (1), (9216), (0), (0x0001), (&q->q_rx.rge_rxq[i].rxq_dmamap )) | |||
1048 | RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (1), (9216), (0), (0x0001), (&q->q_rx.rge_rxq[i].rxq_dmamap )) | |||
1049 | &q->q_rx.rge_rxq[i].rxq_dmamap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (9216 ), (1), (9216), (0), (0x0001), (&q->q_rx.rge_rxq[i].rxq_dmamap )); | |||
1050 | if (error) { | |||
1051 | printf("%s: can't create DMA map for RX\n", | |||
1052 | sc->sc_dev.dv_xname); | |||
1053 | return (error); | |||
1054 | } | |||
1055 | } | |||
1056 | ||||
1057 | return (error); | |||
1058 | } | |||
1059 | ||||
1060 | /* | |||
1061 | * Initialize the RX descriptor and attach an mbuf cluster. | |||
1062 | */ | |||
1063 | int | |||
1064 | rge_newbuf(struct rge_queues *q) | |||
1065 | { | |||
1066 | struct rge_softc *sc = q->q_sc; | |||
1067 | struct mbuf *m; | |||
1068 | struct rge_rx_desc *r; | |||
1069 | struct rge_rxq *rxq; | |||
1070 | bus_dmamap_t rxmap; | |||
1071 | int idx; | |||
1072 | ||||
1073 | m = MCLGETL(NULL, M_DONTWAIT, RGE_JUMBO_FRAMELEN)m_clget((((void *)0)), (0x0002), (9216)); | |||
1074 | if (m == NULL((void *)0)) | |||
1075 | return (ENOBUFS55); | |||
1076 | ||||
1077 | m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = RGE_JUMBO_FRAMELEN9216; | |||
1078 | ||||
1079 | idx = q->q_rx.rge_rxq_prodidx; | |||
1080 | rxq = &q->q_rx.rge_rxq[idx]; | |||
1081 | rxmap = rxq->rxq_dmamap; | |||
1082 | ||||
1083 | if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), ( rxmap), (m), (0x0001))) { | |||
1084 | m_freem(m); | |||
1085 | return (ENOBUFS55); | |||
1086 | } | |||
1087 | ||||
1088 | bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxmap ), (0), (rxmap->dm_mapsize), (0x01)) | |||
1089 | BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxmap ), (0), (rxmap->dm_mapsize), (0x01)); | |||
1090 | ||||
1091 | /* Map the segments into RX descriptors. */ | |||
1092 | r = &q->q_rx.rge_rx_list[idx]; | |||
1093 | ||||
1094 | if (RGE_OWN(r)(((__uint32_t)((r)->rge_cmdsts)) & 0x80000000)) { | |||
1095 | printf("%s: tried to map busy RX descriptor\n", | |||
1096 | sc->sc_dev.dv_xname); | |||
1097 | m_freem(m); | |||
1098 | return (ENOBUFS55); | |||
1099 | } | |||
1100 | ||||
1101 | rxq->rxq_mbuf = m; | |||
1102 | ||||
1103 | r->rge_extsts = 0; | |||
1104 | r->rge_addrlo = htole32(RGE_ADDR_LO(rxmap->dm_segs[0].ds_addr))((__uint32_t)(((uint64_t) (rxmap->dm_segs[0].ds_addr) & 0xffffffff))); | |||
1105 | r->rge_addrhi = htole32(RGE_ADDR_HI(rxmap->dm_segs[0].ds_addr))((__uint32_t)(((uint64_t) (rxmap->dm_segs[0].ds_addr) >> 32))); | |||
1106 | ||||
1107 | r->rge_cmdsts = htole32(rxmap->dm_segs[0].ds_len)((__uint32_t)(rxmap->dm_segs[0].ds_len)); | |||
1108 | if (idx == RGE_RX_LIST_CNT1024 - 1) | |||
1109 | r->rge_cmdsts |= htole32(RGE_RDCMDSTS_EOR)((__uint32_t)(0x40000000)); | |||
1110 | ||||
1111 | r->rge_cmdsts |= htole32(RGE_RDCMDSTS_OWN)((__uint32_t)(0x80000000)); | |||
1112 | ||||
1113 | bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)) | |||
1114 | idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)) | |||
1115 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)); | |||
1116 | ||||
1117 | q->q_rx.rge_rxq_prodidx = RGE_NEXT_RX_DESC(idx)(((idx) + 1) % 1024); | |||
1118 | ||||
1119 | return (0); | |||
1120 | } | |||
1121 | ||||
1122 | void | |||
1123 | rge_discard_rxbuf(struct rge_queues *q, int idx) | |||
1124 | { | |||
1125 | struct rge_softc *sc = q->q_sc; | |||
1126 | struct rge_rx_desc *r; | |||
1127 | ||||
1128 | r = &q->q_rx.rge_rx_list[idx]; | |||
1129 | ||||
1130 | r->rge_cmdsts = htole32(RGE_JUMBO_FRAMELEN)((__uint32_t)(9216)); | |||
1131 | r->rge_extsts = 0; | |||
1132 | if (idx == RGE_RX_LIST_CNT1024 - 1) | |||
1133 | r->rge_cmdsts |= htole32(RGE_RDCMDSTS_EOR)((__uint32_t)(0x40000000)); | |||
1134 | r->rge_cmdsts |= htole32(RGE_RDCMDSTS_OWN)((__uint32_t)(0x80000000)); | |||
1135 | ||||
1136 | bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)) | |||
1137 | idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)) | |||
1138 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (idx * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x01 | 0x04)); | |||
1139 | } | |||
1140 | ||||
1141 | void | |||
1142 | rge_rx_list_init(struct rge_queues *q) | |||
1143 | { | |||
1144 | memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ)__builtin_memset((q->q_rx.rge_rx_list), (0), ((sizeof(struct rge_rx_desc) * 1024))); | |||
1145 | ||||
1146 | q->q_rx.rge_rxq_prodidx = q->q_rx.rge_rxq_considx = 0; | |||
1147 | q->q_rx.rge_head = q->q_rx.rge_tail = NULL((void *)0); | |||
1148 | ||||
1149 | if_rxr_init(&q->q_rx.rge_rx_ring, 2, RGE_RX_LIST_CNT1024 - 1); | |||
1150 | rge_fill_rx_ring(q); | |||
1151 | } | |||
1152 | ||||
1153 | void | |||
1154 | rge_fill_rx_ring(struct rge_queues *q) | |||
1155 | { | |||
1156 | struct if_rxring *rxr = &q->q_rx.rge_rx_ring; | |||
1157 | int slots; | |||
1158 | ||||
1159 | for (slots = if_rxr_get(rxr, RGE_RX_LIST_CNT1024); slots > 0; slots--) { | |||
1160 | if (rge_newbuf(q) == ENOBUFS55) | |||
1161 | break; | |||
1162 | } | |||
1163 | if_rxr_put(rxr, slots)do { (rxr)->rxr_alive -= (slots); } while (0); | |||
1164 | } | |||
1165 | ||||
1166 | void | |||
1167 | rge_tx_list_init(struct rge_queues *q) | |||
1168 | { | |||
1169 | struct rge_softc *sc = q->q_sc; | |||
1170 | int i; | |||
1171 | ||||
1172 | memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ)__builtin_memset((q->q_tx.rge_tx_list), (0), ((sizeof(struct rge_tx_desc) * 1024))); | |||
1173 | ||||
1174 | for (i = 0; i < RGE_TX_LIST_CNT1024; i++) | |||
1175 | q->q_tx.rge_txq[i].txq_mbuf = NULL((void *)0); | |||
1176 | ||||
1177 | bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (0), (q->q_tx.rge_tx_list_map->dm_mapsize ), (0x01 | 0x04)) | |||
1178 | q->q_tx.rge_tx_list_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (0), (q->q_tx.rge_tx_list_map->dm_mapsize ), (0x01 | 0x04)) | |||
1179 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (0), (q->q_tx.rge_tx_list_map->dm_mapsize ), (0x01 | 0x04)); | |||
1180 | ||||
1181 | q->q_tx.rge_txq_prodidx = q->q_tx.rge_txq_considx = 0; | |||
1182 | } | |||
1183 | ||||
1184 | int | |||
1185 | rge_rxeof(struct rge_queues *q) | |||
1186 | { | |||
1187 | struct rge_softc *sc = q->q_sc; | |||
1188 | struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 }; | |||
1189 | struct mbuf *m; | |||
1190 | struct ifnet *ifp = &sc->sc_arpcom.ac_if; | |||
1191 | struct if_rxring *rxr = &q->q_rx.rge_rx_ring; | |||
1192 | struct rge_rx_desc *cur_rx; | |||
1193 | struct rge_rxq *rxq; | |||
1194 | uint32_t rxstat, extsts; | |||
1195 | int i, total_len, rx = 0; | |||
1196 | ||||
1197 | for (i = q->q_rx.rge_rxq_considx; if_rxr_inuse(rxr)((rxr)->rxr_alive) > 0; | |||
1198 | i = RGE_NEXT_RX_DESC(i)(((i) + 1) % 1024)) { | |||
1199 | /* Invalidate the descriptor memory. */ | |||
1200 | bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (i * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x02 | 0x08)) | |||
1201 | i * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (i * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x02 | 0x08)) | |||
1202 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_rx.rge_rx_list_map), (i * sizeof(struct rge_rx_desc)), (sizeof (struct rge_rx_desc)), (0x02 | 0x08)); | |||
1203 | ||||
1204 | cur_rx = &q->q_rx.rge_rx_list[i]; | |||
1205 | ||||
1206 | if (RGE_OWN(cur_rx)(((__uint32_t)((cur_rx)->rge_cmdsts)) & 0x80000000)) | |||
1207 | break; | |||
1208 | ||||
1209 | rxstat = letoh32(cur_rx->rge_cmdsts)((__uint32_t)(cur_rx->rge_cmdsts)); | |||
1210 | extsts = letoh32(cur_rx->rge_extsts)((__uint32_t)(cur_rx->rge_extsts)); | |||
1211 | ||||
1212 | total_len = RGE_RXBYTES(cur_rx)(((__uint32_t)((cur_rx)->rge_cmdsts)) & 0x00003fff); | |||
1213 | rxq = &q->q_rx.rge_rxq[i]; | |||
1214 | m = rxq->rxq_mbuf; | |||
1215 | rxq->rxq_mbuf = NULL((void *)0); | |||
1216 | if_rxr_put(rxr, 1)do { (rxr)->rxr_alive -= (1); } while (0); | |||
1217 | rx = 1; | |||
1218 | ||||
1219 | /* Invalidate the RX mbuf and unload its map. */ | |||
1220 | bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxq-> rxq_dmamap), (0), (rxq->rxq_dmamap->dm_mapsize), (0x02) ) | |||
1221 | rxq->rxq_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxq-> rxq_dmamap), (0), (rxq->rxq_dmamap->dm_mapsize), (0x02) ); | |||
1222 | bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (rxq ->rxq_dmamap)); | |||
1223 | ||||
1224 | if ((rxstat & (RGE_RDCMDSTS_SOF0x20000000 | RGE_RDCMDSTS_EOF0x10000000)) != | |||
1225 | (RGE_RDCMDSTS_SOF0x20000000 | RGE_RDCMDSTS_EOF0x10000000)) { | |||
1226 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
1227 | m_freem(m); | |||
1228 | rge_discard_rxbuf(q, i); | |||
1229 | continue; | |||
1230 | } | |||
1231 | ||||
1232 | if (rxstat & RGE_RDCMDSTS_RXERRSUM0x00200000) { | |||
1233 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
1234 | /* | |||
1235 | * If this is part of a multi-fragment packet, | |||
1236 | * discard all the pieces. | |||
1237 | */ | |||
1238 | if (q->q_rx.rge_head != NULL((void *)0)) { | |||
1239 | m_freem(q->q_rx.rge_head); | |||
1240 | q->q_rx.rge_head = q->q_rx.rge_tail = NULL((void *)0); | |||
1241 | } | |||
1242 | m_freem(m); | |||
1243 | rge_discard_rxbuf(q, i); | |||
1244 | continue; | |||
1245 | } | |||
1246 | ||||
1247 | if (q->q_rx.rge_head != NULL((void *)0)) { | |||
1248 | m->m_lenm_hdr.mh_len = total_len; | |||
1249 | /* | |||
1250 | * Special case: if there's 4 bytes or less | |||
1251 | * in this buffer, the mbuf can be discarded: | |||
1252 | * the last 4 bytes is the CRC, which we don't | |||
1253 | * care about anyway. | |||
1254 | */ | |||
1255 | if (m->m_lenm_hdr.mh_len <= ETHER_CRC_LEN4) { | |||
1256 | q->q_rx.rge_tail->m_lenm_hdr.mh_len -= | |||
1257 | (ETHER_CRC_LEN4 - m->m_lenm_hdr.mh_len); | |||
1258 | m_freem(m); | |||
1259 | } else { | |||
1260 | m->m_lenm_hdr.mh_len -= ETHER_CRC_LEN4; | |||
1261 | m->m_flagsm_hdr.mh_flags &= ~M_PKTHDR0x0002; | |||
1262 | q->q_rx.rge_tail->m_nextm_hdr.mh_next = m; | |||
1263 | } | |||
1264 | m = q->q_rx.rge_head; | |||
1265 | q->q_rx.rge_head = q->q_rx.rge_tail = NULL((void *)0); | |||
1266 | m->m_pkthdrM_dat.MH.MH_pkthdr.len = total_len - ETHER_CRC_LEN4; | |||
1267 | } else | |||
1268 | m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = | |||
1269 | (total_len - ETHER_CRC_LEN4); | |||
1270 | ||||
1271 | /* Check IP header checksum. */ | |||
1272 | if (!(rxstat & RGE_RDCMDSTS_IPCSUMERR0x00010000) && | |||
1273 | (extsts & RGE_RDEXTSTS_IPV40x40000000)) | |||
1274 | m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008; | |||
1275 | ||||
1276 | /* Check TCP/UDP checksum. */ | |||
1277 | if ((extsts & (RGE_RDEXTSTS_IPV40x40000000 | RGE_RDEXTSTS_IPV60x80000000)) && | |||
1278 | (((rxstat & RGE_RDCMDSTS_TCPPKT0x00020000) && | |||
1279 | !(rxstat & RGE_RDCMDSTS_TCPCSUMERR0x00004000)) || | |||
1280 | ((rxstat & RGE_RDCMDSTS_UDPPKT0x00040000) && | |||
1281 | !(rxstat & RGE_RDCMDSTS_UDPCSUMERR0x00008000)))) | |||
1282 | m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 | | |||
1283 | M_UDP_CSUM_IN_OK0x0080; | |||
1284 | ||||
1285 | #if NVLAN1 > 0 | |||
1286 | if (extsts & RGE_RDEXTSTS_VTAG0x00010000) { | |||
1287 | m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = | |||
1288 | ntohs(extsts & RGE_RDEXTSTS_VLAN_MASK)(__uint16_t)(__builtin_constant_p(extsts & 0x0000ffff) ? ( __uint16_t)(((__uint16_t)(extsts & 0x0000ffff) & 0xffU ) << 8 | ((__uint16_t)(extsts & 0x0000ffff) & 0xff00U ) >> 8) : __swap16md(extsts & 0x0000ffff)); | |||
1289 | m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020; | |||
1290 | } | |||
1291 | #endif | |||
1292 | ||||
1293 | ml_enqueue(&ml, m); | |||
1294 | } | |||
1295 | ||||
1296 | if (ifiq_input(&ifp->if_rcv, &ml)) | |||
1297 | if_rxr_livelocked(rxr); | |||
1298 | ||||
1299 | q->q_rx.rge_rxq_considx = i; | |||
1300 | rge_fill_rx_ring(q); | |||
1301 | ||||
1302 | return (rx); | |||
1303 | } | |||
1304 | ||||
1305 | int | |||
1306 | rge_txeof(struct rge_queues *q) | |||
1307 | { | |||
1308 | struct rge_softc *sc = q->q_sc; | |||
1309 | struct ifnet *ifp = &sc->sc_arpcom.ac_if; | |||
1310 | struct rge_txq *txq; | |||
1311 | uint32_t txstat; | |||
1312 | int cons, idx, prod; | |||
1313 | int free = 0; | |||
1314 | ||||
1315 | prod = q->q_tx.rge_txq_prodidx; | |||
1316 | cons = q->q_tx.rge_txq_considx; | |||
1317 | ||||
1318 | while (prod != cons) { | |||
1319 | txq = &q->q_tx.rge_txq[cons]; | |||
1320 | idx = txq->txq_descidx; | |||
1321 | ||||
1322 | bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x02 | 0x08)) | |||
1323 | idx * sizeof(struct rge_tx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x02 | 0x08)) | |||
1324 | sizeof(struct rge_tx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x02 | 0x08)) | |||
1325 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x02 | 0x08)); | |||
1326 | ||||
1327 | txstat = letoh32(q->q_tx.rge_tx_list[idx].rge_cmdsts)((__uint32_t)(q->q_tx.rge_tx_list[idx].rge_cmdsts)); | |||
1328 | ||||
1329 | if (txstat & RGE_TDCMDSTS_OWN0x80000000) { | |||
1330 | free = 2; | |||
1331 | break; | |||
1332 | } | |||
1333 | ||||
1334 | bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txq-> txq_dmamap), (0), (txq->txq_dmamap->dm_mapsize), (0x08) ) | |||
1335 | txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txq-> txq_dmamap), (0), (txq->txq_dmamap->dm_mapsize), (0x08) ); | |||
1336 | bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (txq ->txq_dmamap)); | |||
1337 | m_freem(txq->txq_mbuf); | |||
1338 | txq->txq_mbuf = NULL((void *)0); | |||
1339 | ||||
1340 | if (txstat & (RGE_TDCMDSTS_EXCESSCOLL0x00100000 | RGE_TDCMDSTS_COLL0x000f0000)) | |||
1341 | ifp->if_collisionsif_data.ifi_collisions++; | |||
1342 | if (txstat & RGE_TDCMDSTS_TXERR0x00800000) | |||
1343 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
1344 | ||||
1345 | bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)) | |||
1346 | idx * sizeof(struct rge_tx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)) | |||
1347 | sizeof(struct rge_tx_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)) | |||
1348 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (q-> q_tx.rge_tx_list_map), (idx * sizeof(struct rge_tx_desc)), (sizeof (struct rge_tx_desc)), (0x01 | 0x04)); | |||
1349 | ||||
1350 | cons = RGE_NEXT_TX_DESC(idx)(((idx) + 1) % 1024); | |||
1351 | free = 1; | |||
1352 | } | |||
1353 | ||||
1354 | if (free == 0) | |||
1355 | return (0); | |||
1356 | ||||
1357 | q->q_tx.rge_txq_considx = cons; | |||
1358 | ||||
1359 | if (ifq_is_oactive(&ifp->if_snd)) | |||
1360 | ifq_restart(&ifp->if_snd); | |||
1361 | else if (free == 2) | |||
1362 | ifq_serialize(&ifp->if_snd, &sc->sc_task); | |||
1363 | else | |||
1364 | ifp->if_timer = 0; | |||
1365 | ||||
1366 | return (1); | |||
1367 | } | |||
1368 | ||||
1369 | void | |||
1370 | rge_reset(struct rge_softc *sc) | |||
1371 | { | |||
1372 | int i; | |||
1373 | ||||
1374 | /* Enable RXDV gate. */ | |||
1375 | RGE_SETBIT_1(sc, RGE_PPSW, 0x08)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00f2) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00f2 ))) | (0x08)))); | |||
1376 | DELAY(2000)(*delay_func)(2000); | |||
1377 | ||||
1378 | for (i = 0; i < 3000; i++) { | |||
1379 | DELAY(50)(*delay_func)(50); | |||
1380 | if ((RGE_READ_1(sc, RGE_MCUCMD)((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00d3)) ) & (RGE_MCUCMD_RXFIFO_EMPTY0x10 | | |||
1381 | RGE_MCUCMD_TXFIFO_EMPTY0x20)) == (RGE_MCUCMD_RXFIFO_EMPTY0x10 | | |||
1382 | RGE_MCUCMD_TXFIFO_EMPTY0x20)) | |||
1383 | break; | |||
1384 | } | |||
1385 | if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) { | |||
1386 | for (i = 0; i < 3000; i++) { | |||
1387 | DELAY(50)(*delay_func)(50); | |||
1388 | if ((RGE_READ_2(sc, RGE_IM)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x00e2)) ) & 0x0103) == 0x0103) | |||
1389 | break; | |||
1390 | } | |||
1391 | } | |||
1392 | ||||
1393 | DELAY(2000)(*delay_func)(2000); | |||
1394 | ||||
1395 | /* Soft reset. */ | |||
1396 | RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0037) , (0x10))); | |||
1397 | ||||
1398 | for (i = 0; i < RGE_TIMEOUT100; i++) { | |||
1399 | DELAY(100)(*delay_func)(100); | |||
1400 | if (!(RGE_READ_1(sc, RGE_CMD)((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0037)) ) & RGE_CMD_RESET0x10)) | |||
1401 | break; | |||
1402 | } | |||
1403 | if (i == RGE_TIMEOUT100) | |||
1404 | printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); | |||
1405 | } | |||
1406 | ||||
1407 | void | |||
1408 | rge_iff(struct rge_softc *sc) | |||
1409 | { | |||
1410 | struct ifnet *ifp = &sc->sc_arpcom.ac_if; | |||
1411 | struct arpcom *ac = &sc->sc_arpcom; | |||
1412 | struct ether_multi *enm; | |||
1413 | struct ether_multistep step; | |||
1414 | uint32_t hashes[2]; | |||
1415 | uint32_t rxfilt; | |||
1416 | int h = 0; | |||
1417 | ||||
1418 | rxfilt = RGE_READ_4(sc, RGE_RXCFG)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044)) ); | |||
1419 | rxfilt &= ~(RGE_RXCFG_ALLPHYS0x00000001 | RGE_RXCFG_MULTI0x00000004); | |||
1420 | ifp->if_flags &= ~IFF_ALLMULTI0x200; | |||
1421 | ||||
1422 | /* | |||
1423 | * Always accept frames destined to our station address. | |||
1424 | * Always accept broadcast frames. | |||
1425 | */ | |||
1426 | rxfilt |= RGE_RXCFG_INDIV0x00000002 | RGE_RXCFG_BROAD0x00000008; | |||
1427 | ||||
1428 | if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) { | |||
1429 | ifp->if_flags |= IFF_ALLMULTI0x200; | |||
1430 | rxfilt |= RGE_RXCFG_MULTI0x00000004; | |||
1431 | if (ifp->if_flags & IFF_PROMISC0x100) | |||
1432 | rxfilt |= RGE_RXCFG_ALLPHYS0x00000001; | |||
1433 | hashes[0] = hashes[1] = 0xffffffff; | |||
1434 | } else { | |||
1435 | rxfilt |= RGE_RXCFG_MULTI0x00000004; | |||
1436 | /* Program new filter. */ | |||
1437 | memset(hashes, 0, sizeof(hashes))__builtin_memset((hashes), (0), (sizeof(hashes))); | |||
1438 | ||||
1439 | ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first ); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step )).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while ( 0); | |||
1440 | while (enm != NULL((void *)0)) { | |||
1441 | h = ether_crc32_be(enm->enm_addrlo, | |||
1442 | ETHER_ADDR_LEN6) >> 26; | |||
1443 | ||||
1444 | if (h < 32) | |||
1445 | hashes[0] |= (1 << h); | |||
1446 | else | |||
1447 | hashes[1] |= (1 << (h - 32)); | |||
1448 | ||||
1449 | ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm = (((enm))->enm_list.le_next); } while ( 0); | |||
1450 | } | |||
1451 | } | |||
1452 | ||||
1453 | RGE_WRITE_4(sc, RGE_RXCFG, rxfilt)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (rxfilt))); | |||
1454 | RGE_WRITE_4(sc, RGE_MAR0, swap32(hashes[1]))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0008) , ((__uint32_t)(__builtin_constant_p(hashes[1]) ? (__uint32_t )(((__uint32_t)(hashes[1]) & 0xff) << 24 | ((__uint32_t )(hashes[1]) & 0xff00) << 8 | ((__uint32_t)(hashes[ 1]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[1]) & 0xff000000) >> 24) : __swap32md(hashes[1]))))); | |||
1455 | RGE_WRITE_4(sc, RGE_MAR4, swap32(hashes[0]))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x000c) , ((__uint32_t)(__builtin_constant_p(hashes[0]) ? (__uint32_t )(((__uint32_t)(hashes[0]) & 0xff) << 24 | ((__uint32_t )(hashes[0]) & 0xff00) << 8 | ((__uint32_t)(hashes[ 0]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[0]) & 0xff000000) >> 24) : __swap32md(hashes[0]))))); | |||
1456 | } | |||
1457 | ||||
1458 | void | |||
1459 | rge_set_phy_power(struct rge_softc *sc, int on) | |||
1460 | { | |||
1461 | int i; | |||
1462 | ||||
1463 | if (on) { | |||
1464 | RGE_SETBIT_1(sc, RGE_PMCH, 0xc0)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x006f) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x006f ))) | (0xc0)))); | |||
1465 | ||||
1466 | rge_write_phy(sc, 0, MII_BMCR0x00, BMCR_AUTOEN0x1000); | |||
1467 | ||||
1468 | for (i = 0; i < RGE_TIMEOUT100; i++) { | |||
1469 | if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) | |||
1470 | break; | |||
1471 | DELAY(1000)(*delay_func)(1000); | |||
1472 | } | |||
1473 | } else { | |||
1474 | rge_write_phy(sc, 0, MII_BMCR0x00, BMCR_AUTOEN0x1000 | BMCR_PDOWN0x0800); | |||
1475 | RGE_CLRBIT_1(sc, RGE_PMCH, 0x80)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x006f) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x006f ))) & ~(0x80)))); | |||
1476 | RGE_CLRBIT_1(sc, RGE_PPSW, 0x40)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00f2) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00f2 ))) & ~(0x40)))); | |||
1477 | } | |||
1478 | } | |||
1479 | ||||
1480 | void | |||
1481 | rge_phy_config(struct rge_softc *sc) | |||
1482 | { | |||
1483 | /* Read microcode version. */ | |||
1484 | rge_write_phy_ocp(sc, 0xa436, 0x801e); | |||
1485 | sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438); | |||
1486 | ||||
1487 | switch (sc->rge_type) { | |||
1488 | case MAC_CFG2: | |||
1489 | rge_phy_config_mac_cfg2(sc); | |||
1490 | break; | |||
1491 | case MAC_CFG3: | |||
1492 | rge_phy_config_mac_cfg3(sc); | |||
1493 | break; | |||
1494 | case MAC_CFG4: | |||
1495 | rge_phy_config_mac_cfg4(sc); | |||
1496 | break; | |||
1497 | case MAC_CFG5: | |||
1498 | rge_phy_config_mac_cfg5(sc); | |||
1499 | break; | |||
1500 | default: | |||
1501 | break; /* Can't happen. */ | |||
1502 | } | |||
1503 | ||||
1504 | rge_write_phy(sc, 0x0a5b, 0x12, | |||
1505 | rge_read_phy(sc, 0x0a5b, 0x12) & ~0x8000); | |||
1506 | ||||
1507 | /* Disable EEE. */ | |||
1508 | RGE_MAC_CLRBIT(sc, 0xe040, 0x0003)rge_write_mac_ocp(sc, 0xe040, rge_read_mac_ocp(sc, 0xe040) & ~(0x0003)); | |||
1509 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { | |||
1510 | RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006)rge_write_mac_ocp(sc, 0xeb62, rge_read_mac_ocp(sc, 0xeb62) & ~(0x0006)); | |||
1511 | RGE_PHY_CLRBIT(sc, 0xa432, 0x0010)rge_write_phy_ocp(sc, 0xa432, rge_read_phy_ocp(sc, 0xa432) & ~(0x0010)); | |||
1512 | } | |||
1513 | RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006)rge_write_phy_ocp(sc, 0xa5d0, rge_read_phy_ocp(sc, 0xa5d0) & ~(0x0006)); | |||
1514 | RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001)rge_write_phy_ocp(sc, 0xa6d4, rge_read_phy_ocp(sc, 0xa6d4) & ~(0x0001)); | |||
1515 | RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010)rge_write_phy_ocp(sc, 0xa6d8, rge_read_phy_ocp(sc, 0xa6d8) & ~(0x0010)); | |||
1516 | RGE_PHY_CLRBIT(sc, 0xa428, 0x0080)rge_write_phy_ocp(sc, 0xa428, rge_read_phy_ocp(sc, 0xa428) & ~(0x0080)); | |||
1517 | RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200)rge_write_phy_ocp(sc, 0xa4a2, rge_read_phy_ocp(sc, 0xa4a2) & ~(0x0200)); | |||
1518 | ||||
1519 | rge_patch_phy_mcu(sc, 1); | |||
1520 | RGE_MAC_CLRBIT(sc, 0xe052, 0x0001)rge_write_mac_ocp(sc, 0xe052, rge_read_mac_ocp(sc, 0xe052) & ~(0x0001)); | |||
1521 | RGE_PHY_CLRBIT(sc, 0xa442, 0x3000)rge_write_phy_ocp(sc, 0xa442, rge_read_phy_ocp(sc, 0xa442) & ~(0x3000)); | |||
1522 | RGE_PHY_CLRBIT(sc, 0xa430, 0x8000)rge_write_phy_ocp(sc, 0xa430, rge_read_phy_ocp(sc, 0xa430) & ~(0x8000)); | |||
1523 | rge_patch_phy_mcu(sc, 0); | |||
1524 | } | |||
1525 | ||||
1526 | void | |||
1527 | rge_phy_config_mac_cfg2(struct rge_softc *sc) | |||
1528 | { | |||
1529 | uint16_t val; | |||
1530 | int i; | |||
1531 | ||||
1532 | for (i = 0; i < nitems(rtl8125_mac_cfg2_ephy)(sizeof((rtl8125_mac_cfg2_ephy)) / sizeof((rtl8125_mac_cfg2_ephy )[0])); i++) | |||
1533 | rge_write_ephy(sc, rtl8125_mac_cfg2_ephy[i].reg, | |||
1534 | rtl8125_mac_cfg2_ephy[i].val); | |||
1535 | ||||
1536 | rge_phy_config_mcu(sc, RGE_MAC_CFG2_MCODE_VER0x0b11); | |||
1537 | ||||
1538 | val = rge_read_phy_ocp(sc, 0xad40) & ~0x03ff; | |||
1539 | rge_write_phy_ocp(sc, 0xad40, val | 0x0084); | |||
1540 | RGE_PHY_SETBIT(sc, 0xad4e, 0x0010)rge_write_phy_ocp(sc, 0xad4e, rge_read_phy_ocp(sc, 0xad4e) | ( 0x0010)); | |||
1541 | val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; | |||
1542 | rge_write_phy_ocp(sc, 0xad16, val | 0x0006); | |||
1543 | val = rge_read_phy_ocp(sc, 0xad32) & ~0x03ff; | |||
1544 | rge_write_phy_ocp(sc, 0xad32, val | 0x0006); | |||
1545 | RGE_PHY_CLRBIT(sc, 0xac08, 0x1100)rge_write_phy_ocp(sc, 0xac08, rge_read_phy_ocp(sc, 0xac08) & ~(0x1100)); | |||
1546 | val = rge_read_phy_ocp(sc, 0xac8a) & ~0xf000; | |||
1547 | rge_write_phy_ocp(sc, 0xac8a, val | 0x7000); | |||
1548 | RGE_PHY_SETBIT(sc, 0xad18, 0x0400)rge_write_phy_ocp(sc, 0xad18, rge_read_phy_ocp(sc, 0xad18) | ( 0x0400)); | |||
1549 | RGE_PHY_SETBIT(sc, 0xad1a, 0x03ff)rge_write_phy_ocp(sc, 0xad1a, rge_read_phy_ocp(sc, 0xad1a) | ( 0x03ff)); | |||
1550 | RGE_PHY_SETBIT(sc, 0xad1c, 0x03ff)rge_write_phy_ocp(sc, 0xad1c, rge_read_phy_ocp(sc, 0xad1c) | ( 0x03ff)); | |||
1551 | ||||
1552 | rge_write_phy_ocp(sc, 0xa436, 0x80ea); | |||
1553 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1554 | rge_write_phy_ocp(sc, 0xa438, val | 0xc400); | |||
1555 | rge_write_phy_ocp(sc, 0xa436, 0x80eb); | |||
1556 | val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; | |||
1557 | rge_write_phy_ocp(sc, 0xa438, val | 0x0300); | |||
1558 | rge_write_phy_ocp(sc, 0xa436, 0x80f8); | |||
1559 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1560 | rge_write_phy_ocp(sc, 0xa438, val | 0x1c00); | |||
1561 | rge_write_phy_ocp(sc, 0xa436, 0x80f1); | |||
1562 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1563 | rge_write_phy_ocp(sc, 0xa438, val | 0x3000); | |||
1564 | rge_write_phy_ocp(sc, 0xa436, 0x80fe); | |||
1565 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1566 | rge_write_phy_ocp(sc, 0xa438, val | 0xa500); | |||
1567 | rge_write_phy_ocp(sc, 0xa436, 0x8102); | |||
1568 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1569 | rge_write_phy_ocp(sc, 0xa438, val | 0x5000); | |||
1570 | rge_write_phy_ocp(sc, 0xa436, 0x8105); | |||
1571 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1572 | rge_write_phy_ocp(sc, 0xa438, val | 0x3300); | |||
1573 | rge_write_phy_ocp(sc, 0xa436, 0x8100); | |||
1574 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1575 | rge_write_phy_ocp(sc, 0xa438, val | 0x7000); | |||
1576 | rge_write_phy_ocp(sc, 0xa436, 0x8104); | |||
1577 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1578 | rge_write_phy_ocp(sc, 0xa438, val | 0xf000); | |||
1579 | rge_write_phy_ocp(sc, 0xa436, 0x8106); | |||
1580 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1581 | rge_write_phy_ocp(sc, 0xa438, val | 0x6500); | |||
1582 | rge_write_phy_ocp(sc, 0xa436, 0x80dc); | |||
1583 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1584 | rge_write_phy_ocp(sc, 0xa438, val | 0xed00); | |||
1585 | rge_write_phy_ocp(sc, 0xa436, 0x80df); | |||
1586 | RGE_PHY_SETBIT(sc, 0xa438, 0x0100)rge_write_phy_ocp(sc, 0xa438, rge_read_phy_ocp(sc, 0xa438) | ( 0x0100)); | |||
1587 | rge_write_phy_ocp(sc, 0xa436, 0x80e1); | |||
1588 | RGE_PHY_CLRBIT(sc, 0xa438, 0x0100)rge_write_phy_ocp(sc, 0xa438, rge_read_phy_ocp(sc, 0xa438) & ~(0x0100)); | |||
1589 | val = rge_read_phy_ocp(sc, 0xbf06) & ~0x003f; | |||
1590 | rge_write_phy_ocp(sc, 0xbf06, val | 0x0038); | |||
1591 | rge_write_phy_ocp(sc, 0xa436, 0x819f); | |||
1592 | rge_write_phy_ocp(sc, 0xa438, 0xd0b6); | |||
1593 | rge_write_phy_ocp(sc, 0xbc34, 0x5555); | |||
1594 | val = rge_read_phy_ocp(sc, 0xbf0a) & ~0x0e00; | |||
1595 | rge_write_phy_ocp(sc, 0xbf0a, val | 0x0a00); | |||
1596 | RGE_PHY_CLRBIT(sc, 0xa5c0, 0x0400)rge_write_phy_ocp(sc, 0xa5c0, rge_read_phy_ocp(sc, 0xa5c0) & ~(0x0400)); | |||
1597 | RGE_PHY_SETBIT(sc, 0xa442, 0x0800)rge_write_phy_ocp(sc, 0xa442, rge_read_phy_ocp(sc, 0xa442) | ( 0x0800)); | |||
1598 | } | |||
1599 | ||||
1600 | void | |||
1601 | rge_phy_config_mac_cfg3(struct rge_softc *sc) | |||
1602 | { | |||
1603 | uint16_t val; | |||
1604 | int i; | |||
1605 | static const uint16_t mac_cfg3_a438_value[] = | |||
1606 | { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff, | |||
1607 | 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; | |||
1608 | ||||
1609 | static const uint16_t mac_cfg3_b88e_value[] = | |||
1610 | { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, | |||
1611 | 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, | |||
1612 | 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, | |||
1613 | 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, | |||
1614 | 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050, | |||
1615 | 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 }; | |||
1616 | ||||
1617 | for (i = 0; i < nitems(rtl8125_mac_cfg3_ephy)(sizeof((rtl8125_mac_cfg3_ephy)) / sizeof((rtl8125_mac_cfg3_ephy )[0])); i++) | |||
1618 | rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg, | |||
1619 | rtl8125_mac_cfg3_ephy[i].val); | |||
1620 | ||||
1621 | val = rge_read_ephy(sc, 0x002a) & ~0x7000; | |||
1622 | rge_write_ephy(sc, 0x002a, val | 0x3000); | |||
1623 | RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040)rge_write_ephy(sc, 0x0019, rge_read_ephy(sc, 0x0019) & ~( 0x0040)); | |||
1624 | RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00)rge_write_ephy(sc, 0x001b, rge_read_ephy(sc, 0x001b) | (0x0e00 )); | |||
1625 | RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000)rge_write_ephy(sc, 0x001b, rge_read_ephy(sc, 0x001b) & ~( 0x7000)); | |||
1626 | rge_write_ephy(sc, 0x0002, 0x6042); | |||
1627 | rge_write_ephy(sc, 0x0006, 0x0014); | |||
1628 | val = rge_read_ephy(sc, 0x006a) & ~0x7000; | |||
1629 | rge_write_ephy(sc, 0x006a, val | 0x3000); | |||
1630 | RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040)rge_write_ephy(sc, 0x0059, rge_read_ephy(sc, 0x0059) & ~( 0x0040)); | |||
1631 | RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00)rge_write_ephy(sc, 0x005b, rge_read_ephy(sc, 0x005b) | (0x0e00 )); | |||
1632 | RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000)rge_write_ephy(sc, 0x005b, rge_read_ephy(sc, 0x005b) & ~( 0x7000)); | |||
1633 | rge_write_ephy(sc, 0x0042, 0x6042); | |||
1634 | rge_write_ephy(sc, 0x0046, 0x0014); | |||
1635 | ||||
1636 | rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER0x0b33); | |||
1637 | ||||
1638 | RGE_PHY_SETBIT(sc, 0xad4e, 0x0010)rge_write_phy_ocp(sc, 0xad4e, rge_read_phy_ocp(sc, 0xad4e) | ( 0x0010)); | |||
1639 | val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; | |||
1640 | rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); | |||
1641 | val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; | |||
1642 | rge_write_phy_ocp(sc, 0xad32, val | 0x0006); | |||
1643 | RGE_PHY_CLRBIT(sc, 0xac08, 0x1000)rge_write_phy_ocp(sc, 0xac08, rge_read_phy_ocp(sc, 0xac08) & ~(0x1000)); | |||
1644 | RGE_PHY_CLRBIT(sc, 0xac08, 0x0100)rge_write_phy_ocp(sc, 0xac08, rge_read_phy_ocp(sc, 0xac08) & ~(0x0100)); | |||
1645 | val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; | |||
1646 | rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); | |||
1647 | val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; | |||
1648 | rge_write_phy_ocp(sc, 0xad40, val | 0x0040); | |||
1649 | val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; | |||
1650 | rge_write_phy_ocp(sc, 0xad40, val | 0x0004); | |||
1651 | RGE_PHY_CLRBIT(sc, 0xac14, 0x0080)rge_write_phy_ocp(sc, 0xac14, rge_read_phy_ocp(sc, 0xac14) & ~(0x0080)); | |||
1652 | RGE_PHY_CLRBIT(sc, 0xac80, 0x0300)rge_write_phy_ocp(sc, 0xac80, rge_read_phy_ocp(sc, 0xac80) & ~(0x0300)); | |||
1653 | val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; | |||
1654 | rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); | |||
1655 | rge_write_phy_ocp(sc, 0xad4c, 0x00a8); | |||
1656 | rge_write_phy_ocp(sc, 0xac5c, 0x01ff); | |||
1657 | val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; | |||
1658 | rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); | |||
1659 | rge_write_phy_ocp(sc, 0xb87c, 0x8157); | |||
1660 | val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; | |||
1661 | rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); | |||
1662 | rge_write_phy_ocp(sc, 0xb87c, 0x8159); | |||
1663 | val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; | |||
1664 | rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); | |||
1665 | RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN +((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))) | |||
1666 | 32)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))); | |||
1667 | rge_write_phy_ocp(sc, 0xb87c, 0x80a2); | |||
1668 | rge_write_phy_ocp(sc, 0xb87e, 0x0153); | |||
1669 | rge_write_phy_ocp(sc, 0xb87c, 0x809c); | |||
1670 | rge_write_phy_ocp(sc, 0xb87e, 0x0153); | |||
1671 | ||||
1672 | rge_write_phy_ocp(sc, 0xa436, 0x81b3); | |||
1673 | for (i = 0; i < nitems(mac_cfg3_a438_value)(sizeof((mac_cfg3_a438_value)) / sizeof((mac_cfg3_a438_value) [0])); i++) | |||
1674 | rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); | |||
1675 | for (i = 0; i < 26; i++) | |||
1676 | rge_write_phy_ocp(sc, 0xa438, 0); | |||
1677 | rge_write_phy_ocp(sc, 0xa436, 0x8257); | |||
1678 | rge_write_phy_ocp(sc, 0xa438, 0x020f); | |||
1679 | rge_write_phy_ocp(sc, 0xa436, 0x80ea); | |||
1680 | rge_write_phy_ocp(sc, 0xa438, 0x7843); | |||
1681 | ||||
1682 | rge_patch_phy_mcu(sc, 1); | |||
1683 | RGE_PHY_CLRBIT(sc, 0xb896, 0x0001)rge_write_phy_ocp(sc, 0xb896, rge_read_phy_ocp(sc, 0xb896) & ~(0x0001)); | |||
1684 | RGE_PHY_CLRBIT(sc, 0xb892, 0xff00)rge_write_phy_ocp(sc, 0xb892, rge_read_phy_ocp(sc, 0xb892) & ~(0xff00)); | |||
1685 | for (i = 0; i < nitems(mac_cfg3_b88e_value)(sizeof((mac_cfg3_b88e_value)) / sizeof((mac_cfg3_b88e_value) [0])); i += 2) { | |||
1686 | rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); | |||
1687 | rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); | |||
1688 | } | |||
1689 | RGE_PHY_SETBIT(sc, 0xb896, 0x0001)rge_write_phy_ocp(sc, 0xb896, rge_read_phy_ocp(sc, 0xb896) | ( 0x0001)); | |||
1690 | rge_patch_phy_mcu(sc, 0); | |||
1691 | ||||
1692 | RGE_PHY_SETBIT(sc, 0xd068, 0x2000)rge_write_phy_ocp(sc, 0xd068, rge_read_phy_ocp(sc, 0xd068) | ( 0x2000)); | |||
1693 | rge_write_phy_ocp(sc, 0xa436, 0x81a2); | |||
1694 | RGE_PHY_SETBIT(sc, 0xa438, 0x0100)rge_write_phy_ocp(sc, 0xa438, rge_read_phy_ocp(sc, 0xa438) | ( 0x0100)); | |||
1695 | val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; | |||
1696 | rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); | |||
1697 | RGE_PHY_CLRBIT(sc, 0xa454, 0x0001)rge_write_phy_ocp(sc, 0xa454, rge_read_phy_ocp(sc, 0xa454) & ~(0x0001)); | |||
1698 | RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020)rge_write_phy_ocp(sc, 0xa5d4, rge_read_phy_ocp(sc, 0xa5d4) | ( 0x0020)); | |||
1699 | RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010)rge_write_phy_ocp(sc, 0xad4e, rge_read_phy_ocp(sc, 0xad4e) & ~(0x0010)); | |||
1700 | RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001)rge_write_phy_ocp(sc, 0xa86a, rge_read_phy_ocp(sc, 0xa86a) & ~(0x0001)); | |||
1701 | RGE_PHY_SETBIT(sc, 0xa442, 0x0800)rge_write_phy_ocp(sc, 0xa442, rge_read_phy_ocp(sc, 0xa442) | ( 0x0800)); | |||
1702 | } | |||
1703 | ||||
1704 | void | |||
1705 | rge_phy_config_mac_cfg4(struct rge_softc *sc) | |||
1706 | { | |||
1707 | uint16_t val; | |||
1708 | int i; | |||
1709 | static const uint16_t mac_cfg4_b87c_value[] = | |||
1710 | { 0x8013, 0x0700, 0x8fb9, 0x2801, 0x8fba, 0x0100, 0x8fbc, 0x1900, | |||
1711 | 0x8fbe, 0xe100, 0x8fc0, 0x0800, 0x8fc2, 0xe500, 0x8fc4, 0x0f00, | |||
1712 | 0x8fc6, 0xf100, 0x8fc8, 0x0400, 0x8fca, 0xf300, 0x8fcc, 0xfd00, | |||
1713 | 0x8fce, 0xff00, 0x8fd0, 0xfb00, 0x8fd2, 0x0100, 0x8fd4, 0xf400, | |||
1714 | 0x8fd6, 0xff00, 0x8fd8, 0xf600, 0x813d, 0x390e, 0x814f, 0x790e, | |||
1715 | 0x80b0, 0x0f31 }; | |||
1716 | ||||
1717 | for (i = 0; i < nitems(rtl8125_mac_cfg4_ephy)(sizeof((rtl8125_mac_cfg4_ephy)) / sizeof((rtl8125_mac_cfg4_ephy )[0])); i++) | |||
1718 | rge_write_ephy(sc, rtl8125_mac_cfg4_ephy[i].reg, | |||
1719 | rtl8125_mac_cfg4_ephy[i].val); | |||
1720 | ||||
1721 | rge_write_phy_ocp(sc, 0xbf86, 0x9000); | |||
1722 | RGE_PHY_SETBIT(sc, 0xc402, 0x0400)rge_write_phy_ocp(sc, 0xc402, rge_read_phy_ocp(sc, 0xc402) | ( 0x0400)); | |||
1723 | RGE_PHY_CLRBIT(sc, 0xc402, 0x0400)rge_write_phy_ocp(sc, 0xc402, rge_read_phy_ocp(sc, 0xc402) & ~(0x0400)); | |||
1724 | rge_write_phy_ocp(sc, 0xbd86, 0x1010); | |||
1725 | rge_write_phy_ocp(sc, 0xbd88, 0x1010); | |||
1726 | val = rge_read_phy_ocp(sc, 0xbd4e) & ~0x0c00; | |||
1727 | rge_write_phy_ocp(sc, 0xbd4e, val | 0x0800); | |||
1728 | val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; | |||
1729 | rge_write_phy_ocp(sc, 0xbf46, val | 0x0700); | |||
1730 | ||||
1731 | rge_phy_config_mcu(sc, RGE_MAC_CFG4_MCODE_VER0x0b17); | |||
1732 | ||||
1733 | RGE_PHY_SETBIT(sc, 0xa442, 0x0800)rge_write_phy_ocp(sc, 0xa442, rge_read_phy_ocp(sc, 0xa442) | ( 0x0800)); | |||
1734 | RGE_PHY_SETBIT(sc, 0xbc08, 0x000c)rge_write_phy_ocp(sc, 0xbc08, rge_read_phy_ocp(sc, 0xbc08) | ( 0x000c)); | |||
1735 | rge_write_phy_ocp(sc, 0xa436, 0x8fff); | |||
1736 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1737 | rge_write_phy_ocp(sc, 0xa438, val | 0x0400); | |||
1738 | for (i = 0; i < 6; i++) { | |||
1739 | rge_write_phy_ocp(sc, 0xb87c, 0x8560 + i * 2); | |||
1740 | if (i < 3) | |||
1741 | rge_write_phy_ocp(sc, 0xb87e, 0x19cc); | |||
1742 | else | |||
1743 | rge_write_phy_ocp(sc, 0xb87e, 0x147d); | |||
1744 | } | |||
1745 | rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); | |||
1746 | rge_write_phy_ocp(sc, 0xb87e, 0x0907); | |||
1747 | val = rge_read_phy_ocp(sc, 0xacda) & ~0xff00; | |||
1748 | rge_write_phy_ocp(sc, 0xacda, val | 0xff00); | |||
1749 | val = rge_read_phy_ocp(sc, 0xacde) & ~0xf000; | |||
1750 | rge_write_phy_ocp(sc, 0xacde, val | 0xf000); | |||
1751 | rge_write_phy_ocp(sc, 0xb87c, 0x80d6); | |||
1752 | rge_write_phy_ocp(sc, 0xb87e, 0x2801); | |||
1753 | rge_write_phy_ocp(sc, 0xb87c, 0x80F2); | |||
1754 | rge_write_phy_ocp(sc, 0xb87e, 0x2801); | |||
1755 | rge_write_phy_ocp(sc, 0xb87c, 0x80f4); | |||
1756 | rge_write_phy_ocp(sc, 0xb87e, 0x6077); | |||
1757 | rge_write_phy_ocp(sc, 0xb506, 0x01e7); | |||
1758 | rge_write_phy_ocp(sc, 0xac8c, 0x0ffc); | |||
1759 | rge_write_phy_ocp(sc, 0xac46, 0xb7b4); | |||
1760 | rge_write_phy_ocp(sc, 0xac50, 0x0fbc); | |||
1761 | rge_write_phy_ocp(sc, 0xac3c, 0x9240); | |||
1762 | rge_write_phy_ocp(sc, 0xac4E, 0x0db4); | |||
1763 | rge_write_phy_ocp(sc, 0xacc6, 0x0707); | |||
1764 | rge_write_phy_ocp(sc, 0xacc8, 0xa0d3); | |||
1765 | rge_write_phy_ocp(sc, 0xad08, 0x0007); | |||
1766 | for (i = 0; i < nitems(mac_cfg4_b87c_value)(sizeof((mac_cfg4_b87c_value)) / sizeof((mac_cfg4_b87c_value) [0])); i += 2) { | |||
1767 | rge_write_phy_ocp(sc, 0xb87c, mac_cfg4_b87c_value[i]); | |||
1768 | rge_write_phy_ocp(sc, 0xb87e, mac_cfg4_b87c_value[i + 1]); | |||
1769 | } | |||
1770 | RGE_PHY_SETBIT(sc, 0xbf4c, 0x0002)rge_write_phy_ocp(sc, 0xbf4c, rge_read_phy_ocp(sc, 0xbf4c) | ( 0x0002)); | |||
1771 | RGE_PHY_SETBIT(sc, 0xbcca, 0x0300)rge_write_phy_ocp(sc, 0xbcca, rge_read_phy_ocp(sc, 0xbcca) | ( 0x0300)); | |||
1772 | rge_write_phy_ocp(sc, 0xb87c, 0x8141); | |||
1773 | rge_write_phy_ocp(sc, 0xb87e, 0x320e); | |||
1774 | rge_write_phy_ocp(sc, 0xb87c, 0x8153); | |||
1775 | rge_write_phy_ocp(sc, 0xb87e, 0x720e); | |||
1776 | RGE_PHY_CLRBIT(sc, 0xa432, 0x0040)rge_write_phy_ocp(sc, 0xa432, rge_read_phy_ocp(sc, 0xa432) & ~(0x0040)); | |||
1777 | rge_write_phy_ocp(sc, 0xb87c, 0x8529); | |||
1778 | rge_write_phy_ocp(sc, 0xb87e, 0x050e); | |||
1779 | RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN +((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))) | |||
1780 | 32)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))); | |||
1781 | rge_write_phy_ocp(sc, 0xa436, 0x816c); | |||
1782 | rge_write_phy_ocp(sc, 0xa438, 0xc4a0); | |||
1783 | rge_write_phy_ocp(sc, 0xa436, 0x8170); | |||
1784 | rge_write_phy_ocp(sc, 0xa438, 0xc4a0); | |||
1785 | rge_write_phy_ocp(sc, 0xa436, 0x8174); | |||
1786 | rge_write_phy_ocp(sc, 0xa438, 0x04a0); | |||
1787 | rge_write_phy_ocp(sc, 0xa436, 0x8178); | |||
1788 | rge_write_phy_ocp(sc, 0xa438, 0x04a0); | |||
1789 | rge_write_phy_ocp(sc, 0xa436, 0x817c); | |||
1790 | rge_write_phy_ocp(sc, 0xa438, 0x0719); | |||
1791 | rge_write_phy_ocp(sc, 0xa436, 0x8ff4); | |||
1792 | rge_write_phy_ocp(sc, 0xa438, 0x0400); | |||
1793 | rge_write_phy_ocp(sc, 0xa436, 0x8ff1); | |||
1794 | rge_write_phy_ocp(sc, 0xa438, 0x0404); | |||
1795 | rge_write_phy_ocp(sc, 0xbf4a, 0x001b); | |||
1796 | for (i = 0; i < 6; i++) { | |||
1797 | rge_write_phy_ocp(sc, 0xb87c, 0x8033 + i * 4); | |||
1798 | if (i == 2) | |||
1799 | rge_write_phy_ocp(sc, 0xb87e, 0xfc32); | |||
1800 | else | |||
1801 | rge_write_phy_ocp(sc, 0xb87e, 0x7c13); | |||
1802 | } | |||
1803 | rge_write_phy_ocp(sc, 0xb87c, 0x8145); | |||
1804 | rge_write_phy_ocp(sc, 0xb87e, 0x370e); | |||
1805 | rge_write_phy_ocp(sc, 0xb87c, 0x8157); | |||
1806 | rge_write_phy_ocp(sc, 0xb87e, 0x770e); | |||
1807 | rge_write_phy_ocp(sc, 0xb87c, 0x8169); | |||
1808 | rge_write_phy_ocp(sc, 0xb87e, 0x0d0a); | |||
1809 | rge_write_phy_ocp(sc, 0xb87c, 0x817b); | |||
1810 | rge_write_phy_ocp(sc, 0xb87e, 0x1d0a); | |||
1811 | rge_write_phy_ocp(sc, 0xa436, 0x8217); | |||
1812 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1813 | rge_write_phy_ocp(sc, 0xa438, val | 0x5000); | |||
1814 | rge_write_phy_ocp(sc, 0xa436, 0x821a); | |||
1815 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1816 | rge_write_phy_ocp(sc, 0xa438, val | 0x5000); | |||
1817 | rge_write_phy_ocp(sc, 0xa436, 0x80da); | |||
1818 | rge_write_phy_ocp(sc, 0xa438, 0x0403); | |||
1819 | rge_write_phy_ocp(sc, 0xa436, 0x80dc); | |||
1820 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1821 | rge_write_phy_ocp(sc, 0xa438, val | 0x1000); | |||
1822 | rge_write_phy_ocp(sc, 0xa436, 0x80b3); | |||
1823 | rge_write_phy_ocp(sc, 0xa438, 0x0384); | |||
1824 | rge_write_phy_ocp(sc, 0xa436, 0x80b7); | |||
1825 | rge_write_phy_ocp(sc, 0xa438, 0x2007); | |||
1826 | rge_write_phy_ocp(sc, 0xa436, 0x80ba); | |||
1827 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1828 | rge_write_phy_ocp(sc, 0xa438, val | 0x6c00); | |||
1829 | rge_write_phy_ocp(sc, 0xa436, 0x80b5); | |||
1830 | rge_write_phy_ocp(sc, 0xa438, 0xf009); | |||
1831 | rge_write_phy_ocp(sc, 0xa436, 0x80bd); | |||
1832 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1833 | rge_write_phy_ocp(sc, 0xa438, val | 0x9f00); | |||
1834 | rge_write_phy_ocp(sc, 0xa436, 0x80c7); | |||
1835 | rge_write_phy_ocp(sc, 0xa438, 0xf083); | |||
1836 | rge_write_phy_ocp(sc, 0xa436, 0x80dd); | |||
1837 | rge_write_phy_ocp(sc, 0xa438, 0x03f0); | |||
1838 | rge_write_phy_ocp(sc, 0xa436, 0x80df); | |||
1839 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1840 | rge_write_phy_ocp(sc, 0xa438, val | 0x1000); | |||
1841 | rge_write_phy_ocp(sc, 0xa436, 0x80cb); | |||
1842 | rge_write_phy_ocp(sc, 0xa438, 0x2007); | |||
1843 | rge_write_phy_ocp(sc, 0xa436, 0x80ce); | |||
1844 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1845 | rge_write_phy_ocp(sc, 0xa438, val | 0x6c00); | |||
1846 | rge_write_phy_ocp(sc, 0xa436, 0x80c9); | |||
1847 | rge_write_phy_ocp(sc, 0xa438, 0x8009); | |||
1848 | rge_write_phy_ocp(sc, 0xa436, 0x80d1); | |||
1849 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1850 | rge_write_phy_ocp(sc, 0xa438, val | 0x8000); | |||
1851 | rge_write_phy_ocp(sc, 0xa436, 0x80a3); | |||
1852 | rge_write_phy_ocp(sc, 0xa438, 0x200a); | |||
1853 | rge_write_phy_ocp(sc, 0xa436, 0x80a5); | |||
1854 | rge_write_phy_ocp(sc, 0xa438, 0xf0ad); | |||
1855 | rge_write_phy_ocp(sc, 0xa436, 0x809f); | |||
1856 | rge_write_phy_ocp(sc, 0xa438, 0x6073); | |||
1857 | rge_write_phy_ocp(sc, 0xa436, 0x80a1); | |||
1858 | rge_write_phy_ocp(sc, 0xa438, 0x000b); | |||
1859 | rge_write_phy_ocp(sc, 0xa436, 0x80a9); | |||
1860 | val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; | |||
1861 | rge_write_phy_ocp(sc, 0xa438, val | 0xc000); | |||
1862 | rge_patch_phy_mcu(sc, 1); | |||
1863 | RGE_PHY_CLRBIT(sc, 0xb896, 0x0001)rge_write_phy_ocp(sc, 0xb896, rge_read_phy_ocp(sc, 0xb896) & ~(0x0001)); | |||
1864 | RGE_PHY_CLRBIT(sc, 0xb892, 0xff00)rge_write_phy_ocp(sc, 0xb892, rge_read_phy_ocp(sc, 0xb892) & ~(0xff00)); | |||
1865 | rge_write_phy_ocp(sc, 0xb88e, 0xc23e); | |||
1866 | rge_write_phy_ocp(sc, 0xb890, 0x0000); | |||
1867 | rge_write_phy_ocp(sc, 0xb88e, 0xc240); | |||
1868 | rge_write_phy_ocp(sc, 0xb890, 0x0103); | |||
1869 | rge_write_phy_ocp(sc, 0xb88e, 0xc242); | |||
1870 | rge_write_phy_ocp(sc, 0xb890, 0x0507); | |||
1871 | rge_write_phy_ocp(sc, 0xb88e, 0xc244); | |||
1872 | rge_write_phy_ocp(sc, 0xb890, 0x090b); | |||
1873 | rge_write_phy_ocp(sc, 0xb88e, 0xc246); | |||
1874 | rge_write_phy_ocp(sc, 0xb890, 0x0c0e); | |||
1875 | rge_write_phy_ocp(sc, 0xb88e, 0xc248); | |||
1876 | rge_write_phy_ocp(sc, 0xb890, 0x1012); | |||
1877 | rge_write_phy_ocp(sc, 0xb88e, 0xc24a); | |||
1878 | rge_write_phy_ocp(sc, 0xb890, 0x1416); | |||
1879 | RGE_PHY_SETBIT(sc, 0xb896, 0x0001)rge_write_phy_ocp(sc, 0xb896, rge_read_phy_ocp(sc, 0xb896) | ( 0x0001)); | |||
1880 | rge_patch_phy_mcu(sc, 0); | |||
1881 | RGE_PHY_SETBIT(sc, 0xa86a, 0x0001)rge_write_phy_ocp(sc, 0xa86a, rge_read_phy_ocp(sc, 0xa86a) | ( 0x0001)); | |||
1882 | RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001)rge_write_phy_ocp(sc, 0xa6f0, rge_read_phy_ocp(sc, 0xa6f0) | ( 0x0001)); | |||
1883 | rge_write_phy_ocp(sc, 0xbfa0, 0xd70d); | |||
1884 | rge_write_phy_ocp(sc, 0xbfa2, 0x4100); | |||
1885 | rge_write_phy_ocp(sc, 0xbfa4, 0xe868); | |||
1886 | rge_write_phy_ocp(sc, 0xbfa6, 0xdc59); | |||
1887 | rge_write_phy_ocp(sc, 0xb54c, 0x3c18); | |||
1888 | RGE_PHY_CLRBIT(sc, 0xbfa4, 0x0020)rge_write_phy_ocp(sc, 0xbfa4, rge_read_phy_ocp(sc, 0xbfa4) & ~(0x0020)); | |||
1889 | rge_write_phy_ocp(sc, 0xa436, 0x817d); | |||
1890 | RGE_PHY_SETBIT(sc, 0xa438, 0x1000)rge_write_phy_ocp(sc, 0xa438, rge_read_phy_ocp(sc, 0xa438) | ( 0x1000)); | |||
1891 | } | |||
1892 | ||||
1893 | void | |||
1894 | rge_phy_config_mac_cfg5(struct rge_softc *sc) | |||
1895 | { | |||
1896 | uint16_t val; | |||
1897 | int i; | |||
1898 | ||||
1899 | for (i = 0; i < nitems(rtl8125_mac_cfg5_ephy)(sizeof((rtl8125_mac_cfg5_ephy)) / sizeof((rtl8125_mac_cfg5_ephy )[0])); i++) | |||
1900 | rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg, | |||
1901 | rtl8125_mac_cfg5_ephy[i].val); | |||
1902 | ||||
1903 | rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER0x0b55); | |||
1904 | ||||
1905 | RGE_PHY_SETBIT(sc, 0xa442, 0x0800)rge_write_phy_ocp(sc, 0xa442, rge_read_phy_ocp(sc, 0xa442) | ( 0x0800)); | |||
1906 | val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; | |||
1907 | rge_write_phy_ocp(sc, 0xac46, val | 0x0090); | |||
1908 | val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; | |||
1909 | rge_write_phy_ocp(sc, 0xad30, val | 0x0001); | |||
1910 | RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, RGE_JUMBO_MTU + ETHER_HDR_LEN +((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))) | |||
1911 | 32)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x6048) , ((9216 - ((6 * 2) + 2) - 4 - 4) + ((6 * 2) + 2) + 32))); | |||
1912 | rge_write_phy_ocp(sc, 0xb87c, 0x80f5); | |||
1913 | rge_write_phy_ocp(sc, 0xb87e, 0x760e); | |||
1914 | rge_write_phy_ocp(sc, 0xb87c, 0x8107); | |||
1915 | rge_write_phy_ocp(sc, 0xb87e, 0x360e); | |||
1916 | rge_write_phy_ocp(sc, 0xb87c, 0x8551); | |||
1917 | val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; | |||
1918 | rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); | |||
1919 | val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; | |||
1920 | rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); | |||
1921 | val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; | |||
1922 | rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); | |||
1923 | for (i = 0; i < 10; i++) { | |||
1924 | rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); | |||
1925 | rge_write_phy_ocp(sc, 0xa438, 0x2417); | |||
1926 | } | |||
1927 | RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040)rge_write_phy_ocp(sc, 0xa4ca, rge_read_phy_ocp(sc, 0xa4ca) | ( 0x0040)); | |||
1928 | val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; | |||
1929 | rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); | |||
1930 | rge_write_phy_ocp(sc, 0xa436, 0x8170); | |||
1931 | val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; | |||
1932 | rge_write_phy_ocp(sc, 0xa438, val | 0xd800); | |||
1933 | } | |||
1934 | ||||
1935 | void | |||
1936 | rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version) | |||
1937 | { | |||
1938 | if (sc->rge_mcodever != mcode_version) { | |||
1939 | int i; | |||
1940 | ||||
1941 | rge_patch_phy_mcu(sc, 1); | |||
1942 | ||||
1943 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { | |||
1944 | rge_write_phy_ocp(sc, 0xa436, 0x8024); | |||
1945 | if (sc->rge_type == MAC_CFG2) | |||
1946 | rge_write_phy_ocp(sc, 0xa438, 0x8600); | |||
1947 | else | |||
1948 | rge_write_phy_ocp(sc, 0xa438, 0x8601); | |||
1949 | rge_write_phy_ocp(sc, 0xa436, 0xb82e); | |||
1950 | rge_write_phy_ocp(sc, 0xa438, 0x0001); | |||
1951 | ||||
1952 | RGE_PHY_SETBIT(sc, 0xb820, 0x0080)rge_write_phy_ocp(sc, 0xb820, rge_read_phy_ocp(sc, 0xb820) | ( 0x0080)); | |||
1953 | } | |||
1954 | ||||
1955 | if (sc->rge_type == MAC_CFG2) { | |||
1956 | for (i = 0; i < nitems(rtl8125_mac_cfg2_mcu)(sizeof((rtl8125_mac_cfg2_mcu)) / sizeof((rtl8125_mac_cfg2_mcu )[0])); i++) { | |||
1957 | rge_write_phy_ocp(sc, | |||
1958 | rtl8125_mac_cfg2_mcu[i].reg, | |||
1959 | rtl8125_mac_cfg2_mcu[i].val); | |||
1960 | } | |||
1961 | } else if (sc->rge_type == MAC_CFG3) { | |||
1962 | for (i = 0; i < nitems(rtl8125_mac_cfg3_mcu)(sizeof((rtl8125_mac_cfg3_mcu)) / sizeof((rtl8125_mac_cfg3_mcu )[0])); i++) { | |||
1963 | rge_write_phy_ocp(sc, | |||
1964 | rtl8125_mac_cfg3_mcu[i].reg, | |||
1965 | rtl8125_mac_cfg3_mcu[i].val); | |||
1966 | } | |||
1967 | } else if (sc->rge_type == MAC_CFG4) { | |||
1968 | for (i = 0; i < nitems(rtl8125_mac_cfg4_mcu)(sizeof((rtl8125_mac_cfg4_mcu)) / sizeof((rtl8125_mac_cfg4_mcu )[0])); i++) { | |||
1969 | rge_write_phy_ocp(sc, | |||
1970 | rtl8125_mac_cfg4_mcu[i].reg, | |||
1971 | rtl8125_mac_cfg4_mcu[i].val); | |||
1972 | } | |||
1973 | } else if (sc->rge_type == MAC_CFG5) { | |||
1974 | for (i = 0; i < nitems(rtl8125_mac_cfg5_mcu)(sizeof((rtl8125_mac_cfg5_mcu)) / sizeof((rtl8125_mac_cfg5_mcu )[0])); i++) { | |||
1975 | rge_write_phy_ocp(sc, | |||
1976 | rtl8125_mac_cfg5_mcu[i].reg, | |||
1977 | rtl8125_mac_cfg5_mcu[i].val); | |||
1978 | } | |||
1979 | } | |||
1980 | ||||
1981 | if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) { | |||
1982 | RGE_PHY_CLRBIT(sc, 0xb820, 0x0080)rge_write_phy_ocp(sc, 0xb820, rge_read_phy_ocp(sc, 0xb820) & ~(0x0080)); | |||
1983 | ||||
1984 | rge_write_phy_ocp(sc, 0xa436, 0); | |||
1985 | rge_write_phy_ocp(sc, 0xa438, 0); | |||
1986 | RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001)rge_write_phy_ocp(sc, 0xb82e, rge_read_phy_ocp(sc, 0xb82e) & ~(0x0001)); | |||
1987 | rge_write_phy_ocp(sc, 0xa436, 0x8024); | |||
1988 | rge_write_phy_ocp(sc, 0xa438, 0); | |||
1989 | } | |||
1990 | ||||
1991 | rge_patch_phy_mcu(sc, 0); | |||
1992 | ||||
1993 | /* Write microcode version. */ | |||
1994 | rge_write_phy_ocp(sc, 0xa436, 0x801e); | |||
1995 | rge_write_phy_ocp(sc, 0xa438, mcode_version); | |||
1996 | } | |||
1997 | } | |||
1998 | ||||
1999 | void | |||
2000 | rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) | |||
2001 | { | |||
2002 | RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) | (0xc0)))); | |||
2003 | RGE_WRITE_4(sc, RGE_MAC0,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0000) , (addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]))) | |||
2004 | addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0])((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0000) , (addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]))); | |||
2005 | RGE_WRITE_4(sc, RGE_MAC4,((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0004) , (addr[5] << 8 | addr[4]))) | |||
2006 | addr[5] << 8 | addr[4])((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0004) , (addr[5] << 8 | addr[4]))); | |||
2007 | RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) & ~(0xc0)))); | |||
2008 | } | |||
2009 | ||||
2010 | void | |||
2011 | rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) | |||
2012 | { | |||
2013 | *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x19e0)) ); | |||
2014 | *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x19e4)) ); | |||
2015 | } | |||
2016 | ||||
2017 | void | |||
2018 | rge_hw_init(struct rge_softc *sc) | |||
2019 | { | |||
2020 | int i; | |||
2021 | ||||
2022 | RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) | (0xc0)))); | |||
2023 | RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) & ~(0x01)))); | |||
2024 | RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0053) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0053 ))) & ~(0x80)))); | |||
2025 | RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) & ~(0xc0)))); | |||
2026 | RGE_CLRBIT_1(sc, 0xf1, 0x80)((sc->rge_btag)->write_1((sc->rge_bhandle), (0xf1), ( ((sc->rge_btag)->read_1((sc->rge_bhandle), (0xf1))) & ~(0x80)))); | |||
2027 | ||||
2028 | /* Disable UPS. */ | |||
2029 | RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010)rge_write_mac_ocp(sc, 0xd40a, rge_read_mac_ocp(sc, 0xd40a) & ~(0x0010)); | |||
2030 | ||||
2031 | /* Configure MAC MCU. */ | |||
2032 | rge_write_mac_ocp(sc, 0xfc38, 0); | |||
2033 | ||||
2034 | for (i = 0xfc28; i < 0xfc38; i += 2) | |||
2035 | rge_write_mac_ocp(sc, i, 0); | |||
2036 | ||||
2037 | DELAY(3000)(*delay_func)(3000); | |||
2038 | rge_write_mac_ocp(sc, 0xfc26, 0); | |||
2039 | ||||
2040 | if (sc->rge_type == MAC_CFG3) { | |||
2041 | for (i = 0; i < nitems(rtl8125_mac_bps)(sizeof((rtl8125_mac_bps)) / sizeof((rtl8125_mac_bps)[0])); i++) { | |||
2042 | rge_write_mac_ocp(sc, rtl8125_mac_bps[i].reg, | |||
2043 | rtl8125_mac_bps[i].val); | |||
2044 | } | |||
2045 | } else if (sc->rge_type == MAC_CFG5) { | |||
2046 | for (i = 0; i < nitems(rtl8125b_mac_bps)(sizeof((rtl8125b_mac_bps)) / sizeof((rtl8125b_mac_bps)[0])); i++) { | |||
2047 | rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, | |||
2048 | rtl8125b_mac_bps[i].val); | |||
2049 | } | |||
2050 | } | |||
2051 | ||||
2052 | /* Disable PHY power saving. */ | |||
2053 | rge_disable_phy_ocp_pwrsave(sc); | |||
2054 | ||||
2055 | /* Set PCIe uncorrectable error status. */ | |||
2056 | rge_write_csi(sc, 0x108, | |||
2057 | rge_read_csi(sc, 0x108) | 0x00100000); | |||
2058 | ||||
2059 | } | |||
2060 | ||||
2061 | void | |||
2062 | rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) | |||
2063 | { | |||
2064 | if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { | |||
2065 | rge_patch_phy_mcu(sc, 1); | |||
2066 | rge_write_phy_ocp(sc, 0xc416, 0); | |||
2067 | rge_write_phy_ocp(sc, 0xc416, 0x0500); | |||
2068 | rge_patch_phy_mcu(sc, 0); | |||
2069 | } | |||
2070 | } | |||
2071 | ||||
2072 | void | |||
2073 | rge_patch_phy_mcu(struct rge_softc *sc, int set) | |||
2074 | { | |||
2075 | int i; | |||
2076 | ||||
2077 | if (set) | |||
2078 | RGE_PHY_SETBIT(sc, 0xb820, 0x0010)rge_write_phy_ocp(sc, 0xb820, rge_read_phy_ocp(sc, 0xb820) | ( 0x0010)); | |||
2079 | else | |||
2080 | RGE_PHY_CLRBIT(sc, 0xb820, 0x0010)rge_write_phy_ocp(sc, 0xb820, rge_read_phy_ocp(sc, 0xb820) & ~(0x0010)); | |||
2081 | ||||
2082 | for (i = 0; i < 1000; i++) { | |||
2083 | if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) == 0x0040) | |||
2084 | break; | |||
2085 | DELAY(100)(*delay_func)(100); | |||
2086 | } | |||
2087 | if (i == 1000) { | |||
2088 | DPRINTF(("timeout waiting to patch phy mcu\n")); | |||
2089 | return; | |||
2090 | } | |||
2091 | } | |||
2092 | ||||
2093 | void | |||
2094 | rge_add_media_types(struct rge_softc *sc) | |||
2095 | { | |||
2096 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0)); | |||
2097 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0)); | |||
2098 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 0, NULL((void *)0)); | |||
2099 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0)); | |||
2100 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0)); | |||
2101 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0)); | |||
2102 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0)); | |||
2103 | ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0)); | |||
2104 | } | |||
2105 | ||||
2106 | void | |||
2107 | rge_config_imtype(struct rge_softc *sc, int imtype) | |||
2108 | { | |||
2109 | switch (imtype) { | |||
2110 | case RGE_IMTYPE_NONE0: | |||
2111 | sc->rge_intrs = RGE_INTRS(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000020 | 0x00000080 | 0x00004000 | 0x00008000); | |||
2112 | break; | |||
2113 | case RGE_IMTYPE_SIM1: | |||
2114 | sc->rge_intrs = RGE_INTRS_TIMER(0x00000002 | 0x00000008 | 0x00004000 | 0x00008000); | |||
2115 | break; | |||
2116 | default: | |||
2117 | panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); | |||
2118 | } | |||
2119 | } | |||
2120 | ||||
2121 | void | |||
2122 | rge_disable_hw_im(struct rge_softc *sc) | |||
2123 | { | |||
2124 | RGE_WRITE_2(sc, RGE_IM, 0)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x00e2) , (0))); | |||
2125 | } | |||
2126 | ||||
2127 | void | |||
2128 | rge_disable_sim_im(struct rge_softc *sc) | |||
2129 | { | |||
2130 | RGE_WRITE_4(sc, RGE_TIMERINT0, 0)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0058) , (0))); | |||
2131 | sc->rge_timerintr = 0; | |||
2132 | } | |||
2133 | ||||
2134 | void | |||
2135 | rge_setup_sim_im(struct rge_softc *sc) | |||
2136 | { | |||
2137 | RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0058) , (0x2600))); | |||
2138 | RGE_WRITE_4(sc, RGE_TIMERCNT, 1)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0048) , (1))); | |||
2139 | sc->rge_timerintr = 1; | |||
2140 | } | |||
2141 | ||||
2142 | void | |||
2143 | rge_setup_intr(struct rge_softc *sc, int imtype) | |||
2144 | { | |||
2145 | rge_config_imtype(sc, imtype); | |||
2146 | ||||
2147 | /* Enable interrupts. */ | |||
2148 | RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0038) , (sc->rge_intrs))); | |||
2149 | ||||
2150 | switch (imtype) { | |||
2151 | case RGE_IMTYPE_NONE0: | |||
2152 | rge_disable_sim_im(sc); | |||
2153 | rge_disable_hw_im(sc); | |||
2154 | break; | |||
2155 | case RGE_IMTYPE_SIM1: | |||
2156 | rge_disable_hw_im(sc); | |||
2157 | rge_setup_sim_im(sc); | |||
2158 | break; | |||
2159 | default: | |||
2160 | panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); | |||
2161 | } | |||
2162 | } | |||
2163 | ||||
2164 | void | |||
2165 | rge_exit_oob(struct rge_softc *sc) | |||
2166 | { | |||
2167 | int i; | |||
2168 | ||||
2169 | RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))) | |||
2170 | RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))) | |||
2171 | RGE_RXCFG_ERRPKT)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0044) , (((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0044 ))) & ~(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)))); | |||
2172 | ||||
2173 | /* Disable RealWoW. */ | |||
2174 | rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); | |||
2175 | ||||
2176 | rge_reset(sc); | |||
2177 | ||||
2178 | /* Disable OOB. */ | |||
2179 | RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00d3) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00d3 ))) & ~(0x80)))); | |||
2180 | ||||
2181 | RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000)rge_write_mac_ocp(sc, 0xe8de, rge_read_mac_ocp(sc, 0xe8de) & ~(0x4000)); | |||
2182 | ||||
2183 | for (i = 0; i < 10; i++) { | |||
2184 | DELAY(100)(*delay_func)(100); | |||
2185 | if (RGE_READ_2(sc, RGE_TWICMD)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x00d2)) ) & 0x0200) | |||
2186 | break; | |||
2187 | } | |||
2188 | ||||
2189 | rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); | |||
2190 | rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); | |||
2191 | rge_write_mac_ocp(sc, 0xc01e, 0x5555); | |||
2192 | ||||
2193 | for (i = 0; i < 10; i++) { | |||
2194 | DELAY(100)(*delay_func)(100); | |||
2195 | if (RGE_READ_2(sc, RGE_TWICMD)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x00d2)) ) & 0x0200) | |||
2196 | break; | |||
2197 | } | |||
2198 | ||||
2199 | if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { | |||
2200 | printf("%s: rge_exit_oob(): rtl8125_is_ups_resume!!\n", | |||
2201 | sc->sc_dev.dv_xname); | |||
2202 | for (i = 0; i < RGE_TIMEOUT100; i++) { | |||
2203 | if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) | |||
2204 | break; | |||
2205 | DELAY(1000)(*delay_func)(1000); | |||
2206 | } | |||
2207 | RGE_MAC_CLRBIT(sc, 0xd408, 0x0100)rge_write_mac_ocp(sc, 0xd408, rge_read_mac_ocp(sc, 0xd408) & ~(0x0100)); | |||
2208 | if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) | |||
2209 | RGE_PHY_CLRBIT(sc, 0xa466, 0x0001)rge_write_phy_ocp(sc, 0xa466, rge_read_phy_ocp(sc, 0xa466) & ~(0x0001)); | |||
2210 | RGE_PHY_CLRBIT(sc, 0xa468, 0x000a)rge_write_phy_ocp(sc, 0xa468, rge_read_phy_ocp(sc, 0xa468) & ~(0x000a)); | |||
2211 | } | |||
2212 | } | |||
2213 | ||||
2214 | void | |||
2215 | rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) | |||
2216 | { | |||
2217 | int i; | |||
2218 | ||||
2219 | RGE_WRITE_4(sc, RGE_CSIDR, val)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0064) , (val))); | |||
2220 | RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0068) , ((reg & 0x00000fff) | (0x0000000f << 12) | 0x80000000 ))) | |||
2221 | (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0068) , ((reg & 0x00000fff) | (0x0000000f << 12) | 0x80000000 ))); | |||
2222 | ||||
2223 | for (i = 0; i < 10; i++) { | |||
2224 | DELAY(100)(*delay_func)(100); | |||
2225 | if (!(RGE_READ_4(sc, RGE_CSIAR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0068)) ) & RGE_CSIAR_BUSY0x80000000)) | |||
2226 | break; | |||
2227 | } | |||
2228 | ||||
2229 | DELAY(20)(*delay_func)(20); | |||
2230 | } | |||
2231 | ||||
2232 | uint32_t | |||
2233 | rge_read_csi(struct rge_softc *sc, uint32_t reg) | |||
2234 | { | |||
2235 | int i; | |||
2236 | ||||
2237 | RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0068) , ((reg & 0x00000fff) | (0x0000000f << 12)))) | |||
2238 | (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT))((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0068) , ((reg & 0x00000fff) | (0x0000000f << 12)))); | |||
2239 | ||||
2240 | for (i = 0; i < 10; i++) { | |||
2241 | DELAY(100)(*delay_func)(100); | |||
2242 | if (RGE_READ_4(sc, RGE_CSIAR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0068)) ) & RGE_CSIAR_BUSY0x80000000) | |||
2243 | break; | |||
2244 | } | |||
2245 | ||||
2246 | DELAY(20)(*delay_func)(20); | |||
2247 | ||||
2248 | return (RGE_READ_4(sc, RGE_CSIDR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0064)) )); | |||
2249 | } | |||
2250 | ||||
2251 | void | |||
2252 | rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) | |||
2253 | { | |||
2254 | uint32_t tmp; | |||
2255 | ||||
2256 | tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT16; | |||
2257 | tmp += val; | |||
2258 | tmp |= RGE_MACOCP_BUSY0x80000000; | |||
2259 | RGE_WRITE_4(sc, RGE_MACOCP, tmp)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00b0) , (tmp))); | |||
2260 | } | |||
2261 | ||||
2262 | uint16_t | |||
2263 | rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) | |||
2264 | { | |||
2265 | uint32_t val; | |||
2266 | ||||
2267 | val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT16; | |||
2268 | RGE_WRITE_4(sc, RGE_MACOCP, val)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00b0) , (val))); | |||
2269 | ||||
2270 | return (RGE_READ_4(sc, RGE_MACOCP)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x00b0)) ) & RGE_MACOCP_DATA_MASK0x0000ffff); | |||
2271 | } | |||
2272 | ||||
2273 | void | |||
2274 | rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) | |||
2275 | { | |||
2276 | uint32_t tmp; | |||
2277 | int i; | |||
2278 | ||||
2279 | tmp = (reg & RGE_EPHYAR_ADDR_MASK0x0000007f) << RGE_EPHYAR_ADDR_SHIFT16; | |||
2280 | tmp |= RGE_EPHYAR_BUSY0x80000000 | (val & RGE_EPHYAR_DATA_MASK0x0000ffff); | |||
2281 | RGE_WRITE_4(sc, RGE_EPHYAR, tmp)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0080) , (tmp))); | |||
2282 | ||||
2283 | for (i = 0; i < 10; i++) { | |||
2284 | DELAY(100)(*delay_func)(100); | |||
2285 | if (!(RGE_READ_4(sc, RGE_EPHYAR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0080)) ) & RGE_EPHYAR_BUSY0x80000000)) | |||
2286 | break; | |||
2287 | } | |||
2288 | ||||
2289 | DELAY(20)(*delay_func)(20); | |||
2290 | } | |||
2291 | ||||
2292 | uint16_t | |||
2293 | rge_read_ephy(struct rge_softc *sc, uint16_t reg) | |||
2294 | { | |||
2295 | uint32_t val; | |||
2296 | int i; | |||
2297 | ||||
2298 | val = (reg & RGE_EPHYAR_ADDR_MASK0x0000007f) << RGE_EPHYAR_ADDR_SHIFT16; | |||
2299 | RGE_WRITE_4(sc, RGE_EPHYAR, val)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x0080) , (val))); | |||
2300 | ||||
2301 | for (i = 0; i < 10; i++) { | |||
2302 | DELAY(100)(*delay_func)(100); | |||
2303 | val = RGE_READ_4(sc, RGE_EPHYAR)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x0080)) ); | |||
2304 | if (val & RGE_EPHYAR_BUSY0x80000000) | |||
2305 | break; | |||
2306 | } | |||
2307 | ||||
2308 | DELAY(20)(*delay_func)(20); | |||
2309 | ||||
2310 | return (val & RGE_EPHYAR_DATA_MASK0x0000ffff); | |||
2311 | } | |||
2312 | ||||
2313 | void | |||
2314 | rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) | |||
2315 | { | |||
2316 | uint16_t off, phyaddr; | |||
2317 | ||||
2318 | phyaddr = addr ? addr : RGE_PHYBASE0x0a40 + (reg / 8); | |||
2319 | phyaddr <<= 4; | |||
2320 | ||||
2321 | off = addr ? reg : 0x10 + (reg % 8); | |||
2322 | ||||
2323 | phyaddr += (off - 16) << 1; | |||
2324 | ||||
2325 | rge_write_phy_ocp(sc, phyaddr, val); | |||
2326 | } | |||
2327 | ||||
2328 | uint16_t | |||
2329 | rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) | |||
2330 | { | |||
2331 | uint16_t off, phyaddr; | |||
2332 | ||||
2333 | phyaddr = addr ? addr : RGE_PHYBASE0x0a40 + (reg / 8); | |||
2334 | phyaddr <<= 4; | |||
2335 | ||||
2336 | off = addr ? reg : 0x10 + (reg % 8); | |||
2337 | ||||
2338 | phyaddr += (off - 16) << 1; | |||
2339 | ||||
2340 | return (rge_read_phy_ocp(sc, phyaddr)); | |||
2341 | } | |||
2342 | ||||
2343 | void | |||
2344 | rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) | |||
2345 | { | |||
2346 | uint32_t tmp; | |||
2347 | int i; | |||
2348 | ||||
2349 | tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT16; | |||
2350 | tmp |= RGE_PHYOCP_BUSY0x80000000 | val; | |||
2351 | RGE_WRITE_4(sc, RGE_PHYOCP, tmp)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00b8) , (tmp))); | |||
2352 | ||||
2353 | for (i = 0; i < RGE_TIMEOUT100; i++) { | |||
2354 | DELAY(1)(*delay_func)(1); | |||
2355 | if (!(RGE_READ_4(sc, RGE_PHYOCP)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x00b8)) ) & RGE_PHYOCP_BUSY0x80000000)) | |||
2356 | break; | |||
2357 | } | |||
2358 | } | |||
2359 | ||||
2360 | uint16_t | |||
2361 | rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) | |||
2362 | { | |||
2363 | uint32_t val; | |||
2364 | int i; | |||
2365 | ||||
2366 | val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT16; | |||
2367 | RGE_WRITE_4(sc, RGE_PHYOCP, val)((sc->rge_btag)->write_4((sc->rge_bhandle), (0x00b8) , (val))); | |||
2368 | ||||
2369 | for (i = 0; i < RGE_TIMEOUT100; i++) { | |||
2370 | DELAY(1)(*delay_func)(1); | |||
2371 | val = RGE_READ_4(sc, RGE_PHYOCP)((sc->rge_btag)->read_4((sc->rge_bhandle), (0x00b8)) ); | |||
2372 | if (val & RGE_PHYOCP_BUSY0x80000000) | |||
2373 | break; | |||
2374 | } | |||
2375 | ||||
2376 | return (val & RGE_PHYOCP_DATA_MASK0x0000ffff); | |||
2377 | } | |||
2378 | ||||
2379 | int | |||
2380 | rge_get_link_status(struct rge_softc *sc) | |||
2381 | { | |||
2382 | return ((RGE_READ_2(sc, RGE_PHYSTAT)((sc->rge_btag)->read_2((sc->rge_bhandle), (0x006c)) ) & RGE_PHYSTAT_LINK0x0002) ? 1 : 0); | |||
2383 | } | |||
2384 | ||||
2385 | void | |||
2386 | rge_txstart(void *arg) | |||
2387 | { | |||
2388 | struct rge_softc *sc = arg; | |||
2389 | ||||
2390 | RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START)((sc->rge_btag)->write_2((sc->rge_bhandle), (0x0090) , (0x0001))); | |||
2391 | } | |||
2392 | ||||
2393 | void | |||
2394 | rge_tick(void *arg) | |||
2395 | { | |||
2396 | struct rge_softc *sc = arg; | |||
2397 | int s; | |||
2398 | ||||
2399 | s = splnet()splraise(0x7); | |||
2400 | rge_link_state(sc); | |||
2401 | splx(s)spllower(s); | |||
2402 | ||||
2403 | timeout_add_sec(&sc->sc_timeout, 1); | |||
2404 | } | |||
2405 | ||||
2406 | void | |||
2407 | rge_link_state(struct rge_softc *sc) | |||
2408 | { | |||
2409 | struct ifnet *ifp = &sc->sc_arpcom.ac_if; | |||
2410 | int link = LINK_STATE_DOWN2; | |||
2411 | ||||
2412 | if (rge_get_link_status(sc)) | |||
2413 | link = LINK_STATE_UP4; | |||
2414 | ||||
2415 | if (ifp->if_link_stateif_data.ifi_link_state != link) { | |||
2416 | ifp->if_link_stateif_data.ifi_link_state = link; | |||
2417 | if_link_state_change(ifp); | |||
2418 | } | |||
2419 | } | |||
2420 | ||||
2421 | #ifndef SMALL_KERNEL | |||
2422 | int | |||
2423 | rge_wol(struct ifnet *ifp, int enable) | |||
2424 | { | |||
2425 | struct rge_softc *sc = ifp->if_softc; | |||
2426 | ||||
2427 | if (enable) { | |||
2428 | if (!(RGE_READ_1(sc, RGE_CFG1)((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0052)) ) & RGE_CFG1_PM_EN0x01)) { | |||
2429 | printf("%s: power management is disabled, " | |||
2430 | "cannot do WOL\n", sc->sc_dev.dv_xname); | |||
2431 | return (ENOTSUP91); | |||
2432 | } | |||
2433 | ||||
2434 | } | |||
2435 | ||||
2436 | rge_iff(sc); | |||
2437 | ||||
2438 | if (enable) | |||
2439 | RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001)rge_write_mac_ocp(sc, 0xc0b6, rge_read_mac_ocp(sc, 0xc0b6) | ( 0x0001)); | |||
2440 | else | |||
2441 | RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001)rge_write_mac_ocp(sc, 0xc0b6, rge_read_mac_ocp(sc, 0xc0b6) & ~(0x0001)); | |||
2442 | ||||
2443 | RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) | (0xc0)))); | |||
2444 | RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST |((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) & ~(0x02 | 0x10 | 0x20 | 0x40)))) | |||
2445 | RGE_CFG5_WOL_MCAST | RGE_CFG5_WOL_BCAST)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) & ~(0x02 | 0x10 | 0x20 | 0x40)))); | |||
2446 | RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0054) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0054 ))) & ~(0x10 | 0x20)))); | |||
2447 | if (enable) | |||
2448 | RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0056) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0056 ))) | (0x02)))); | |||
2449 | RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0050) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0050 ))) & ~(0xc0)))); | |||
2450 | ||||
2451 | return (0); | |||
2452 | } | |||
2453 | ||||
2454 | void | |||
2455 | rge_wol_power(struct rge_softc *sc) | |||
2456 | { | |||
2457 | /* Disable RXDV gate. */ | |||
2458 | RGE_CLRBIT_1(sc, RGE_PPSW, 0x08)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x00f2) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x00f2 ))) & ~(0x08)))); | |||
2459 | DELAY(2000)(*delay_func)(2000); | |||
2460 | ||||
2461 | RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0052) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0052 ))) | (0x01)))); | |||
2462 | RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN)((sc->rge_btag)->write_1((sc->rge_bhandle), (0x0053) , (((sc->rge_btag)->read_1((sc->rge_bhandle), (0x0053 ))) | (0x20)))); | |||
2463 | } | |||
2464 | #endif |