Bug Summary

File:dev/pci/ixgbe_x540.c
Warning:line 92, column 2
Value stored to 'ret_val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ixgbe_x540.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/ixgbe_x540.c
1/* $OpenBSD: ixgbe_x540.c,v 1.13 2022/01/09 05:42:56 jsg Exp $ */
2
3/******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2017, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
11
12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 POSSIBILITY OF SUCH DAMAGE.
34
35******************************************************************************/
36/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 331224 2018-03-19 20:55:05Z erj $*/
37
38#include <dev/pci/ixgbe.h>
39#include <dev/pci/ixgbe_type.h>
40
41#define IXGBE_X540_MAX_TX_QUEUES128 128
42#define IXGBE_X540_MAX_RX_QUEUES128 128
43#define IXGBE_X540_RAR_ENTRIES128 128
44#define IXGBE_X540_MC_TBL_SIZE128 128
45#define IXGBE_X540_VFT_TBL_SIZE128 128
46#define IXGBE_X540_RX_PB_SIZE384 384
47
48int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw);
49int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
50int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
51void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52
53int32_t ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
54 ixgbe_link_speed *speed, bool_Bool *autoneg);
55enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
56int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
57 bool_Bool link_up_wait_to_complete);
58int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
59int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw);
60uint64_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
61
62int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
63int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data);
64int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data);
65int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
66int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, uint16_t *checksum_val);
67int32_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
68
69int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);
70void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);
71void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw);
72
73int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index);
74int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index);
75
76/**
77 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
78 * @hw: pointer to hardware structure
79 *
80 * Initialize the function pointers and assign the MAC type for X540.
81 * Does not touch the hardware.
82 **/
83int32_t ixgbe_init_ops_X540(struct ixgbe_hw *hw)
84{
85 struct ixgbe_mac_info *mac = &hw->mac;
86 struct ixgbe_phy_info *phy = &hw->phy;
87 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
88 int32_t ret_val;
89
90 DEBUGFUNC("ixgbe_init_ops_X540");;
91
92 ret_val = ixgbe_init_phy_ops_generic(hw);
Value stored to 'ret_val' is never read
93 ret_val = ixgbe_init_ops_generic(hw);
94
95 /* EEPROM */
96 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
97 eeprom->ops.read = ixgbe_read_eerd_X540;
98 eeprom->ops.write = ixgbe_write_eewr_X540;
99 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
100 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
101 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
102
103 /* PHY */
104 phy->ops.init = ixgbe_init_phy_ops_generic;
105 phy->ops.reset = NULL((void *)0);
106 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
107
108 /* MAC */
109 mac->ops.reset_hw = ixgbe_reset_hw_X540;
110 mac->ops.get_media_type = ixgbe_get_media_type_X540;
111 mac->ops.get_supported_physical_layer =
112 ixgbe_get_supported_physical_layer_X540;
113 mac->ops.read_analog_reg8 = NULL((void *)0);
114 mac->ops.write_analog_reg8 = NULL((void *)0);
115 mac->ops.start_hw = ixgbe_start_hw_X540;
116 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
117 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
118 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
119 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
120 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
121 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
122
123 /* RAR, Multicast, VLAN */
124 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
125 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
126 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
127 mac->rar_highwater = 1;
128 mac->ops.set_vfta = ixgbe_set_vfta_generic;
129 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
130 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
131 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
132
133 /* Link */
134 mac->ops.get_link_capabilities =
135 ixgbe_get_copper_link_capabilities_generic;
136 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
137 mac->ops.check_link = ixgbe_check_mac_link_generic;
138
139 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE128;
140 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE128;
141 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES128;
142 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE384;
143 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES128;
144 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES128;
145 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/;
146
147 /*
148 * FWSM register
149 * ARC supported; valid only if manageability features are
150 * enabled.
151 */
152 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_FWSM_IDX]))))
153 & IXGBE_FWSM_MODE_MASK0xE);
154
155 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
156
157 /* LEDs */
158 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
159 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
160
161 return ret_val;
162}
163
164/**
165 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
166 * @hw: pointer to hardware structure
167 * @speed: pointer to link speed
168 * @autoneg: TRUE when autoneg or autotry is enabled
169 *
170 * Determines the link capabilities by reading the AUTOC register.
171 **/
172int32_t ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
173 ixgbe_link_speed *speed,
174 bool_Bool *autoneg)
175{
176 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
177
178 return IXGBE_SUCCESS0;
179}
180
181/**
182 * ixgbe_get_media_type_X540 - Get media type
183 * @hw: pointer to hardware structure
184 *
185 * Returns the media type (fiber, copper, backplane)
186 **/
187enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
188{
189 return ixgbe_media_type_copper;
190}
191
192/**
193 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
194 * @hw: pointer to hardware structure
195 * @speed: new link speed
196 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
197 **/
198int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
199 ixgbe_link_speed speed,
200 bool_Bool autoneg_wait_to_complete)
201{
202 DEBUGFUNC("ixgbe_setup_mac_link_X540");;
203 return hw->phy.ops.setup_link_speed(hw, speed,
204 autoneg_wait_to_complete);
205}
206
207/**
208 * ixgbe_reset_hw_X540 - Perform hardware reset
209 * @hw: pointer to hardware structure
210 *
211 * Resets the hardware by resetting the transmit and receive units, masks
212 * and clears all interrupts, and perform a reset.
213 **/
214int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
215{
216 int32_t status;
217 uint32_t ctrl, i;
218 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
219
220 DEBUGFUNC("ixgbe_reset_hw_X540");;
221
222 /* Call adapter stop to disable tx/rx and clear interrupts */
223 status = hw->mac.ops.stop_adapter(hw);
224 if (status != IXGBE_SUCCESS0)
225 goto reset_hw_out;
226
227 /* flush pending Tx transactions */
228 ixgbe_clear_tx_pending(hw);
229
230mac_reset_top:
231 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
232 if (status != IXGBE_SUCCESS0) {
233 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
234 "semaphore failed with %d", status);
235 return IXGBE_ERR_SWFW_SYNC-16;
236 }
237 ctrl = IXGBE_CTRL_RST0x04000000;
238 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
)));
239 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
), (ctrl)));
240 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
241 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
242
243 /* Poll for reset bit to self-clear indicating reset is complete */
244 for (i = 0; i < 10; i++) {
245 usec_delay(1)(*delay_func)(1);
246 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
)));
247 if (!(ctrl & IXGBE_CTRL_RST_MASK(0x00000008 | 0x04000000)))
248 break;
249 }
250
251 if (ctrl & IXGBE_CTRL_RST_MASK(0x00000008 | 0x04000000)) {
252 status = IXGBE_ERR_RESET_FAILED-15;
253 ERROR_REPORT1(IXGBE_ERROR_POLLING,
254 "Reset polling failed to complete.\n");
255 }
256 msec_delay(100)(*delay_func)(1000 * (100));
257
258 /*
259 * Double resets are required for recovery from certain error
260 * conditions. Between resets, it is necessary to stall to allow time
261 * for any pending HW events to complete.
262 */
263 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED0x01) {
264 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED0x01;
265 goto mac_reset_top;
266 }
267
268 /* Set the Rx packet buffer size. */
269 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03C00
+ ((0) * 4))), (384 << 10)));
270
271 /* Store the permanent mac address */
272 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
273
274 /*
275 * Store MAC address from RAR0, clear receive address registers, and
276 * clear the multicast table. Also reset num_rar_entries to 128,
277 * since we modify this value when programming the SAN MAC address.
278 */
279 hw->mac.num_rar_entries = 128;
280 hw->mac.ops.init_rx_addrs(hw);
281
282reset_hw_out:
283 return status;
284}
285
286/**
287 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
288 * @hw: pointer to hardware structure
289 *
290 * Starts the hardware using the generic start_hw function
291 * and the generation start_hw function.
292 * Then performs revision-specific operations, if any.
293 **/
294int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw)
295{
296 int32_t ret_val = IXGBE_SUCCESS0;
297
298 DEBUGFUNC("ixgbe_start_hw_X540");;
299
300 ret_val = ixgbe_start_hw_generic(hw);
301 if (ret_val != IXGBE_SUCCESS0)
302 goto out;
303
304 ret_val = ixgbe_start_hw_gen2(hw);
305
306out:
307 return ret_val;
308}
309
310/**
311 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
312 * @hw: pointer to hardware structure
313 *
314 * Determines physical layer capabilities of the current configuration.
315 **/
316uint64_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
317{
318 uint64_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN0;
319 uint16_t ext_ability = 0;
320
321 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");;
322
323 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY0xB,
324 IXGBE_MDIO_PMA_PMD_DEV_TYPE0x1, &ext_ability);
325 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY0x0004)
326 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T0x00001;
327 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY0x0020)
328 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T0x00002;
329 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY0x0080)
330 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX0x00004;
331
332 return physical_layer;
333}
334
335/**
336 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
337 * @hw: pointer to hardware structure
338 *
339 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
340 * ixgbe_hw struct in order to set up EEPROM access.
341 **/
342int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
343{
344 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
345 uint32_t eec;
346 uint16_t eeprom_size;
347
348 DEBUGFUNC("ixgbe_init_eeprom_params_X540");;
349
350 if (eeprom->type == ixgbe_eeprom_uninitialized) {
351 eeprom->semaphore_delay = 10;
352 eeprom->type = ixgbe_flash;
353
354 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX]))));
355 eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE0x00007800) >>
356 IXGBE_EEC_SIZE_SHIFT11);
357 eeprom->word_size = 1 << (eeprom_size +
358 IXGBE_EEPROM_WORD_SIZE_SHIFT6);
359
360 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
361 eeprom->type, eeprom->word_size);
362 }
363
364 return IXGBE_SUCCESS0;
365}
366
367/**
368 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
369 * @hw: pointer to hardware structure
370 * @offset: offset of word in the EEPROM to read
371 * @data: word read from the EEPROM
372 *
373 * Reads a 16 bit word from the EEPROM using the EERD register.
374 **/
375int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data)
376{
377 int32_t status = IXGBE_SUCCESS0;
378
379 DEBUGFUNC("ixgbe_read_eerd_X540");;
380 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001) ==
381 IXGBE_SUCCESS0) {
382 status = ixgbe_read_eerd_generic(hw, offset, data);
383 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001);
384 } else {
385 status = IXGBE_ERR_SWFW_SYNC-16;
386 }
387
388 return status;
389}
390
391/**
392 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
393 * @hw: pointer to hardware structure
394 * @offset: offset of word in the EEPROM to write
395 * @data: word write to the EEPROM
396 *
397 * Write a 16 bit word to the EEPROM using the EEWR register.
398 **/
399int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data)
400{
401 int32_t status = IXGBE_SUCCESS0;
402
403 DEBUGFUNC("ixgbe_write_eewr_X540");;
404 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001) ==
405 IXGBE_SUCCESS0) {
406 status = ixgbe_write_eewr_generic(hw, offset, data);
407 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001);
408 } else {
409 status = IXGBE_ERR_SWFW_SYNC-16;
410 }
411
412 return status;
413}
414
415/**
416 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
417 *
418 * This function does not use synchronization for EERD and EEWR. It can
419 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
420 *
421 * @hw: pointer to hardware structure
422 *
423 * Returns a negative error code on error, or the 16-bit checksum
424 **/
425int32_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
426{
427 uint16_t i, j;
428 uint16_t checksum = 0;
429 uint16_t length = 0;
430 uint16_t pointer = 0;
431 uint16_t word = 0;
432 uint16_t ptr_start = IXGBE_PCIE_ANALOG_PTR0x03;
433
434 /* Do not use hw->eeprom.ops.read because we do not want to take
435 * the synchronization semaphores here. Instead use
436 * ixgbe_read_eerd_generic
437 */
438
439 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");;
440
441 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
442 * checksum itself
443 */
444 for (i = 0; i < IXGBE_EEPROM_CHECKSUM0x3F; i++) {
445 if (ixgbe_read_eerd_generic(hw, i, &word)) {
446 DEBUGOUT("EEPROM read failed\n");
447 return IXGBE_ERR_EEPROM-1;
448 }
449 checksum += word;
450 }
451
452 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
453 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
454 */
455 for (i = ptr_start; i < IXGBE_FW_PTR0x0F; i++) {
456 if (i == IXGBE_PHY_PTR0x04 || i == IXGBE_OPTION_ROM_PTR0x05)
457 continue;
458
459 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
460 DEBUGOUT("EEPROM read failed\n");
461 return IXGBE_ERR_EEPROM-1;
462 }
463
464 /* Skip pointer section if the pointer is invalid. */
465 if (pointer == 0xFFFF || pointer == 0 ||
466 pointer >= hw->eeprom.word_size)
467 continue;
468
469 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
470 DEBUGOUT("EEPROM read failed\n");
471 return IXGBE_ERR_EEPROM-1;
472 }
473
474 /* Skip pointer section if length is invalid. */
475 if (length == 0xFFFF || length == 0 ||
476 (pointer + length) >= hw->eeprom.word_size)
477 continue;
478
479 for (j = pointer + 1; j <= pointer + length; j++) {
480 if (ixgbe_read_eerd_generic(hw, j, &word)) {
481 DEBUGOUT("EEPROM read failed\n");
482 return IXGBE_ERR_EEPROM-1;
483 }
484 checksum += word;
485 }
486 }
487
488 checksum = (uint16_t)IXGBE_EEPROM_SUM0xBABA - checksum;
489
490 return (int32_t)checksum;
491}
492
493/**
494 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
495 * @hw: pointer to hardware structure
496 * @checksum_val: calculated checksum
497 *
498 * Performs checksum calculation and validates the EEPROM checksum. If the
499 * caller does not need checksum_val, the value can be NULL.
500 **/
501int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
502 uint16_t *checksum_val)
503{
504 int32_t status;
505 uint16_t checksum;
506 uint16_t read_checksum = 0;
507
508 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");;
509
510 /* Read the first word from the EEPROM. If this times out or fails, do
511 * not continue or we could be in for a very long wait while every
512 * EEPROM read fails
513 */
514 status = hw->eeprom.ops.read(hw, 0, &checksum);
515 if (status) {
516 DEBUGOUT("EEPROM read failed\n");
517 return status;
518 }
519
520 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001))
521 return IXGBE_ERR_SWFW_SYNC-16;
522
523 status = hw->eeprom.ops.calc_checksum(hw);
524 if (status < 0)
525 goto out;
526
527 checksum = (uint16_t)(status & 0xffff);
528
529 /* Do not use hw->eeprom.ops.read because we do not want to take
530 * the synchronization semaphores twice here.
531 */
532 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM0x3F,
533 &read_checksum);
534 if (status)
535 goto out;
536
537 /* Verify read checksum from EEPROM is the same as
538 * calculated checksum
539 */
540 if (read_checksum != checksum) {
541 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
542 "Invalid EEPROM checksum");
543 status = IXGBE_ERR_EEPROM_CHECKSUM-2;
544 }
545
546 /* If the user cares, return the calculated checksum */
547 if (checksum_val)
548 *checksum_val = checksum;
549
550out:
551 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001);
552
553 return status;
554}
555
556/**
557 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
558 * @hw: pointer to hardware structure
559 *
560 * After writing EEPROM to shadow RAM using EEWR register, software calculates
561 * checksum and updates the EEPROM and instructs the hardware to update
562 * the flash.
563 **/
564int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
565{
566 int32_t status;
567 uint16_t checksum;
568
569 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");;
570
571 /* Read the first word from the EEPROM. If this times out or fails, do
572 * not continue or we could be in for a very long wait while every
573 * EEPROM read fails
574 */
575 status = hw->eeprom.ops.read(hw, 0, &checksum);
576 if (status) {
577 DEBUGOUT("EEPROM read failed\n");
578 return status;
579 }
580
581 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001))
582 return IXGBE_ERR_SWFW_SYNC-16;
583
584 status = hw->eeprom.ops.calc_checksum(hw);
585 if (status < 0)
586 goto out;
587
588 checksum = (uint16_t)(status & 0xffff);
589
590 /* Do not use hw->eeprom.ops.write because we do not want to
591 * take the synchronization semaphores twice here.
592 */
593 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM0x3F, checksum);
594 if (status)
595 goto out;
596
597 status = ixgbe_update_flash_X540(hw);
598
599out:
600 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM0x0001);
601
602 return status;
603}
604
605/**
606 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
607 * @hw: pointer to hardware structure
608 *
609 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
610 * EEPROM from shadow RAM to the flash device.
611 **/
612int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw)
613{
614 uint32_t flup;
615 int32_t status;
616
617 DEBUGFUNC("ixgbe_update_flash_X540");;
618
619 status = ixgbe_poll_flash_update_done_X540(hw);
620 if (status == IXGBE_ERR_EEPROM-1) {
621 DEBUGOUT("Flash update time out\n");
622 goto out;
623 }
624
625 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX])))) | IXGBE_EEC_FLUP0x00800000;
626 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX])), (flup)));
627
628 status = ixgbe_poll_flash_update_done_X540(hw);
629 if (status == IXGBE_SUCCESS0)
630 DEBUGOUT("Flash update complete\n");
631 else
632 DEBUGOUT("Flash update time out\n");
633
634 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
635 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX]))));
636
637 if (flup & IXGBE_EEC_SEC1VAL0x02000000) {
638 flup |= IXGBE_EEC_FLUP0x00800000;
639 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX])), (flup)));
640 }
641
642 status = ixgbe_poll_flash_update_done_X540(hw);
643 if (status == IXGBE_SUCCESS0)
644 DEBUGOUT("Flash update complete\n");
645 else
646 DEBUGOUT("Flash update time out\n");
647 }
648out:
649 return status;
650}
651
652/**
653 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
654 * @hw: pointer to hardware structure
655 *
656 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
657 * flash update is done.
658 **/
659int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
660{
661 uint32_t i;
662 uint32_t reg;
663 int32_t status = IXGBE_ERR_EEPROM-1;
664
665 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");;
666
667 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS20000; i++) {
668 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_EEC_IDX]))));
669 if (reg & IXGBE_EEC_FLUDONE0x04000000) {
670 status = IXGBE_SUCCESS0;
671 break;
672 }
673 msec_delay(5)(*delay_func)(1000 * (5));
674 }
675
676 if (i == IXGBE_FLUDONE_ATTEMPTS20000)
677 ERROR_REPORT1(IXGBE_ERROR_POLLING,
678 "Flash update status polling timed out");
679
680 return status;
681}
682
683/**
684 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
685 * @hw: pointer to hardware structure
686 * @mask: Mask to specify which semaphore to acquire
687 *
688 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
689 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
690 **/
691int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)
692{
693 uint32_t swmask = mask & IXGBE_GSSR_NVM_PHY_MASK0xF;
694 uint32_t fwmask = swmask << 5;
695 uint32_t swi2c_mask = mask & IXGBE_GSSR_I2C_MASK0x1800;
696 uint32_t timeout = 200;
697 uint32_t hwmask = 0;
698 uint32_t swfw_sync;
699 uint32_t i;
700
701 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");;
702
703 if (swmask & IXGBE_GSSR_EEP_SM0x0001)
704 hwmask |= IXGBE_GSSR_FLASH_SM0x0010;
705
706 /* SW only mask doesn't have FW bit pair */
707 if (mask & IXGBE_GSSR_SW_MNG_SM0x0400)
708 swmask |= IXGBE_GSSR_SW_MNG_SM0x0400;
709
710 swmask |= swi2c_mask;
711 fwmask |= swi2c_mask << 2;
712 if (hw->mac.type >= ixgbe_mac_X550)
713 timeout = 1000;
714
715 for (i = 0; i < timeout; i++) {
716 /* SW NVM semaphore bit is used for access to all
717 * SW_FW_SYNC bits (not just NVM)
718 */
719 if (ixgbe_get_swfw_sync_semaphore(hw)) {
720 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
721 return IXGBE_ERR_SWFW_SYNC-16;
722 }
723
724 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX]))));
725 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
726 swfw_sync |= swmask;
727 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX])), (swfw_sync)))
728 swfw_sync)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX])), (swfw_sync)));
729 ixgbe_release_swfw_sync_semaphore(hw);
730 return IXGBE_SUCCESS0;
731 }
732 /* Firmware currently using resource (fwmask), hardware
733 * currently using resource (hwmask), or other software
734 * thread currently using resource (swmask)
735 */
736 ixgbe_release_swfw_sync_semaphore(hw);
737 msec_delay(5)(*delay_func)(1000 * (5));
738 }
739
740 /* If the resource is not released by the FW/HW the SW can assume that
741 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
742 * of the requested resource(s) while ignoring the corresponding FW/HW
743 * bits in the SW_FW_SYNC register.
744 */
745 if (ixgbe_get_swfw_sync_semaphore(hw)) {
746 DEBUGOUT("Failed to get NVM semaphore and register semaphore while forcefully ignoring FW semaphore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
747 return IXGBE_ERR_SWFW_SYNC-16;
748 }
749 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX]))));
750 if (swfw_sync & (fwmask | hwmask)) {
751 swfw_sync |= swmask;
752 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX])), (swfw_sync)));
753 ixgbe_release_swfw_sync_semaphore(hw);
754 msec_delay(5)(*delay_func)(1000 * (5));
755 return IXGBE_SUCCESS0;
756 }
757 /* If the resource is not released by other SW the SW can assume that
758 * the other SW malfunctions. In that case the SW should clear all SW
759 * flags that it does not own and then repeat the whole process once
760 * again.
761 */
762 if (swfw_sync & swmask) {
763 uint32_t rmask = IXGBE_GSSR_EEP_SM0x0001 | IXGBE_GSSR_PHY0_SM0x0002 |
764 IXGBE_GSSR_PHY1_SM0x0004 | IXGBE_GSSR_MAC_CSR_SM0x0008 |
765 IXGBE_GSSR_SW_MNG_SM0x0400;
766
767 if (swi2c_mask)
768 rmask |= IXGBE_GSSR_I2C_MASK0x1800;
769 ixgbe_release_swfw_sync_X540(hw, rmask);
770 ixgbe_release_swfw_sync_semaphore(hw);
771 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
772 return IXGBE_ERR_SWFW_SYNC-16;
773 }
774 ixgbe_release_swfw_sync_semaphore(hw);
775 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
776
777 return IXGBE_ERR_SWFW_SYNC-16;
778}
779
780/**
781 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
782 * @hw: pointer to hardware structure
783 * @mask: Mask to specify which semaphore to release
784 *
785 * Releases the SWFW semaphore through the SW_FW_SYNC register
786 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
787 **/
788void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)
789{
790 uint32_t swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK0xF | IXGBE_GSSR_SW_MNG_SM0x0400);
791 uint32_t swfw_sync;
792
793 DEBUGFUNC("ixgbe_release_swfw_sync_X540");;
794
795 if (mask & IXGBE_GSSR_I2C_MASK0x1800)
796 swmask |= mask & IXGBE_GSSR_I2C_MASK0x1800;
797 ixgbe_get_swfw_sync_semaphore(hw);
798
799 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX]))));
800 swfw_sync &= ~swmask;
801 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX])), (swfw_sync)));
802
803 ixgbe_release_swfw_sync_semaphore(hw);
804 msec_delay(2)(*delay_func)(1000 * (2));
805}
806
807/**
808 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
809 * @hw: pointer to hardware structure
810 *
811 * Sets the hardware semaphores so SW/FW can gain control of shared resources
812 **/
813int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
814{
815 int32_t status = IXGBE_ERR_EEPROM-1;
816 uint32_t timeout = 2000;
817 uint32_t i;
818 uint32_t swsm;
819
820 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");;
821
822 /* Get SMBI software semaphore between device drivers first */
823 for (i = 0; i < timeout; i++) {
824 /*
825 * If the SMBI bit is 0 when we read it, then the bit will be
826 * set and we have the semaphore
827 */
828 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWSM_IDX]))));
829 if (!(swsm & IXGBE_SWSM_SMBI0x00000001)) {
830 status = IXGBE_SUCCESS0;
831 break;
832 }
833 usec_delay(50)(*delay_func)(50);
834 }
835
836 /* Now get the semaphore between SW/FW through the REGSMP bit */
837 if (status == IXGBE_SUCCESS0) {
838 for (i = 0; i < timeout; i++) {
839 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX]))));
840 if (!(swsm & IXGBE_SWFW_REGSMP0x80000000))
841 break;
842
843 usec_delay(50)(*delay_func)(50);
844 }
845
846 /*
847 * Release semaphores and return error if SW NVM semaphore
848 * was not granted because we don't have access to the EEPROM
849 */
850 if (i >= timeout) {
851 ERROR_REPORT1(IXGBE_ERROR_POLLING,
852 "REGSMP Software NVM semaphore not granted.\n");
853 ixgbe_release_swfw_sync_semaphore(hw);
854 status = IXGBE_ERR_EEPROM-1;
855 }
856 } else {
857 ERROR_REPORT1(IXGBE_ERROR_POLLING,
858 "Software semaphore SMBI between device drivers "
859 "not granted.\n");
860 }
861
862 return status;
863}
864
865/**
866 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
867 * @hw: pointer to hardware structure
868 *
869 * This function clears hardware semaphore bits.
870 **/
871void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
872{
873 uint32_t swsm;
874
875 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");;
876
877 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
878
879 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX]))));
880 swsm &= ~IXGBE_SWFW_REGSMP0x80000000;
881 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWFW_SYNC_IDX])), (swsm)));
882
883 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWSM_IDX]))));
884 swsm &= ~IXGBE_SWSM_SMBI0x00000001;
885 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((hw)
)->mvals[IXGBE_SWSM_IDX])), (swsm)));
886
887 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
888}
889
890/**
891 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
892 * @hw: pointer to hardware structure
893 *
894 * This function reset hardware semaphore bits for a semaphore that may
895 * have be left locked due to a catastrophic failure.
896 **/
897void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
898{
899 uint32_t rmask;
900
901 /* First try to grab the semaphore but we don't need to bother
902 * looking to see whether we got the lock or not since we do
903 * the same thing regardless of whether we got the lock or not.
904 * We got the lock - we release it.
905 * We timeout trying to get the lock - we force its release.
906 */
907 ixgbe_get_swfw_sync_semaphore(hw);
908 ixgbe_release_swfw_sync_semaphore(hw);
909
910 /* Acquire and release all software resources. */
911 rmask = IXGBE_GSSR_EEP_SM0x0001 | IXGBE_GSSR_PHY0_SM0x0002 |
912 IXGBE_GSSR_PHY1_SM0x0004 | IXGBE_GSSR_MAC_CSR_SM0x0008 |
913 IXGBE_GSSR_SW_MNG_SM0x0400;
914
915 rmask |= IXGBE_GSSR_I2C_MASK0x1800;
916 ixgbe_acquire_swfw_sync_X540(hw, rmask);
917 ixgbe_release_swfw_sync_X540(hw, rmask);
918}
919
920/**
921 * ixgbe_blink_led_start_X540 - Blink LED based on index.
922 * @hw: pointer to hardware structure
923 * @index: led number to blink
924 *
925 * Devices that implement the version 2 interface:
926 * X540
927 **/
928int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index)
929{
930 uint32_t macc_reg;
931 uint32_t ledctl_reg;
932 ixgbe_link_speed speed;
933 bool_Bool link_up;
934
935 DEBUGFUNC("ixgbe_blink_led_start_X540");;
936
937 if (index > 3)
938 return IXGBE_ERR_PARAM-5;
939
940 /*
941 * Link should be up in order for the blink bit in the LED control
942 * register to work. Force link and speed in the MAC if link is down.
943 * This will be reversed when we stop the blinking.
944 */
945 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE0);
946 if (link_up == FALSE0) {
947 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04330
)));
948 macc_reg |= IXGBE_MACC_FLU0x00000001 | IXGBE_MACC_FSV_10G0x00030000 | IXGBE_MACC_FS0x00040000;
949 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04330
), (macc_reg)));
950 }
951 /* Set the LED to LINK_UP + BLINK. */
952 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00200
)));
953 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index)(0x0000000F << (8 * (index)));
954 ledctl_reg |= IXGBE_LED_BLINK(index)(0x00000080 << (8 * (index)));
955 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00200
), (ledctl_reg)));
956 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
957
958 return IXGBE_SUCCESS0;
959}
960
961/**
962 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
963 * @hw: pointer to hardware structure
964 * @index: led number to stop blinking
965 *
966 * Devices that implement the version 2 interface:
967 * X540
968 **/
969int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index)
970{
971 uint32_t macc_reg;
972 uint32_t ledctl_reg;
973
974 if (index > 3)
975 return IXGBE_ERR_PARAM-5;
976
977 DEBUGFUNC("ixgbe_blink_led_stop_X540");;
978
979 /* Restore the LED to its default value. */
980 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00200
)));
981 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index)(0x0000000F << (8 * (index)));
982 ledctl_reg |= IXGBE_LED_LINK_ACTIVE0x4 << IXGBE_LED_MODE_SHIFT(index)(8*(index));
983 ledctl_reg &= ~IXGBE_LED_BLINK(index)(0x00000080 << (8 * (index)));
984 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00200
), (ledctl_reg)));
985
986 /* Unforce link and speed in the MAC. */
987 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04330
)));
988 macc_reg &= ~(IXGBE_MACC_FLU0x00000001 | IXGBE_MACC_FSV_10G0x00030000 | IXGBE_MACC_FS0x00040000);
989 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04330
), (macc_reg)));
990 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
991
992 return IXGBE_SUCCESS0;
993}