/usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1

Bug Summary

File:	dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
Warning:	line 522, column 16 Access to field 'count' results in a dereference of a null pointer (loaded from field 'vdd_dep_on_sclk')
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name process_pptables_v1_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
1/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
23#include "pp_debug.h"
24#include <linux/module.h>
25#include <linux/slab.h>

27#include "process_pptables_v1_0.h"
28#include "ppatomctrl.h"
29#include "atombios.h"
30#include "hwmgr.h"
31#include "cgs_common.h"
32#include "pptable_v1_0.h"

34/**
* Private Function used during initialization.
* @param hwmgr Pointer to the hardware manager.
* @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE).
* @param cap Which capability to set/reset.
*/
40static void set_hw_cap(struct pp_hwmgr *hwmgr, bool_Bool setIt, enum phm_platform_caps cap)
41{
if (setIt)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
else
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
46}


49/**
* Private Function used during initialization.
* @param hwmgr Pointer to the hardware manager.
* @param powerplay_caps the bit array (from BIOS) of capability bits.
* @exception the current implementation always returns 1.
*/
55static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
56{
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),do { if (!((~powerplay_caps & 0x10))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!"); continue
; } } while (0)
"ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!", continue)do { if (!((~powerplay_caps & 0x10))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!"); continue
; } } while (0);
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),do { if (!((~powerplay_caps & 0x40))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!"
); continue; } } while (0)
"ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!", continue)do { if (!((~powerplay_caps & 0x40))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!"
); continue; } } while (0);
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),do { if (!((~powerplay_caps & 0x200))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!"
); continue; } } while (0)
"ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!", continue)do { if (!((~powerplay_caps & 0x200))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!"
); continue; } } while (0);
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),do { if (!((~powerplay_caps & 0x400))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!"
); continue; } } while (0)
"ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!", continue)do { if (!((~powerplay_caps & 0x400))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!"
); continue; } } while (0);
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),do { if (!((~powerplay_caps & 0x800))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!"
); continue; } } while (0)
"ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!", continue)do { if (!((~powerplay_caps & 0x800))) { printk("\0014" "amdgpu: "
 "%s\n", "ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!"
); continue; } } while (0);

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY0x2),
	PHM_PlatformCaps_PowerPlaySupport
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE0x4),
	PHM_PlatformCaps_BiosPowerSourceControl
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC0x20),
	PHM_PlatformCaps_AutomaticDCTransition
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL0x1000),
	PHM_PlatformCaps_EnableMVDDControl
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL0x8000),
	PHM_PlatformCaps_ControlVDDCI
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL0x1),
	PHM_PlatformCaps_ControlVDDGFX
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_BACO0x20000),
	PHM_PlatformCaps_BACO
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND0x8),
	PHM_PlatformCaps_DisableVoltageIsland
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL0x1000000),
	PHM_PlatformCaps_CombinePCCWithThermalSignal
  );

set_hw_cap(
	hwmgr,
	0 != (powerplay_caps & ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE0x2000000),
	PHM_PlatformCaps_LoadPostProductionFirmware
  );

return 0;
129}

131/**
* Private Function to get the PowerPlay Table Address.
*/
134static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
135{
int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo)(((char*)(&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->PowerPlayInfo
)-(char*)0)/sizeof(USHORT));

u16 size;
u8 frev, crev;
void *table_address = (void *)hwmgr->soft_pp_table;

if (!table_address) {
table_address = (ATOM_Tonga_POWERPLAYTABLE *)
		smu_atom_get_data_table(hwmgr->adev,
				index, &size, &frev, &crev);
hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
hwmgr->soft_pp_table_size = size;
}

return table_address;
151}

153static int get_vddc_lookup_table(
struct pp_hwmgr	*hwmgr,
phm_ppt_v1_voltage_lookup_table	**lookup_table,
const ATOM_Tonga_Voltage_Lookup_Table *vddc_lookup_pp_tables,
uint32_t max_levels
)
159{
uint32_t table_size, i;
phm_ppt_v1_voltage_lookup_table *table;
phm_ppt_v1_voltage_lookup_record *record;
ATOM_Tonga_Voltage_Lookup_Record *atom_record;

PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),do { if (!((0 != vddc_lookup_pp_tables->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid CAC Leakage PowerPlay Table!"
); return 1; } } while (0)
"Invalid CAC Leakage PowerPlay Table!", return 1)do { if (!((0 != vddc_lookup_pp_tables->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid CAC Leakage PowerPlay Table!"
); return 1; } } while (0);

table_size = sizeof(uint32_t) +
sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;

table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == table)
return -ENOMEM12;

table->count = vddc_lookup_pp_tables->ucNumEntries;

for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_voltage_lookup_record *)((char *)&(table)->
entries + (sizeof(phm_ppt_v1_voltage_lookup_record) * (i)))
			phm_ppt_v1_voltage_lookup_record,(phm_ppt_v1_voltage_lookup_record *)((char *)&(table)->
entries + (sizeof(phm_ppt_v1_voltage_lookup_record) * (i)))
			entries, table, i)(phm_ppt_v1_voltage_lookup_record *)((char *)&(table)->
entries + (sizeof(phm_ppt_v1_voltage_lookup_record) * (i)));
atom_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_Voltage_Lookup_Record *)((char *)&(vddc_lookup_pp_tables
)->entries + (sizeof(ATOM_Tonga_Voltage_Lookup_Record) * (
i)))
			ATOM_Tonga_Voltage_Lookup_Record,(ATOM_Tonga_Voltage_Lookup_Record *)((char *)&(vddc_lookup_pp_tables
)->entries + (sizeof(ATOM_Tonga_Voltage_Lookup_Record) * (
i)))
			entries, vddc_lookup_pp_tables, i)(ATOM_Tonga_Voltage_Lookup_Record *)((char *)&(vddc_lookup_pp_tables
)->entries + (sizeof(ATOM_Tonga_Voltage_Lookup_Record) * (
i)));
record->us_calculated = 0;
record->us_vdd = le16_to_cpu(atom_record->usVdd)((__uint16_t)(atom_record->usVdd));
record->us_cac_low = le16_to_cpu(atom_record->usCACLow)((__uint16_t)(atom_record->usCACLow));
record->us_cac_mid = le16_to_cpu(atom_record->usCACMid)((__uint16_t)(atom_record->usCACMid));
record->us_cac_high = le16_to_cpu(atom_record->usCACHigh)((__uint16_t)(atom_record->usCACHigh));
}

*lookup_table = table;

return 0;
195}

197/**
* Private Function used during initialization.
* Initialize Platform Power Management Parameter table
* @param hwmgr Pointer to the hardware manager.
* @param atom_ppm_table Pointer to PPM table in VBIOS
*/
203static int get_platform_power_management_table(
struct pp_hwmgr *hwmgr,
ATOM_Tonga_PPM_Table *atom_ppm_table)
206{
struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL(0x0001 | 0x0004));
struct phm_ppt_v1_information *pp_table_information =
(struct phm_ppt_v1_information *)(hwmgr->pptable);

if (NULL((void *)0) == ptr)
return -ENOMEM12;

ptr->ppm_design
= atom_ppm_table->ucPpmDesign;
ptr->cpu_core_number
= le16_to_cpu(atom_ppm_table->usCpuCoreNumber)((__uint16_t)(atom_ppm_table->usCpuCoreNumber));
ptr->platform_tdp
= le32_to_cpu(atom_ppm_table->ulPlatformTDP)((__uint32_t)(atom_ppm_table->ulPlatformTDP));
ptr->small_ac_platform_tdp
= le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP)((__uint32_t)(atom_ppm_table->ulSmallACPlatformTDP));
ptr->platform_tdc
= le32_to_cpu(atom_ppm_table->ulPlatformTDC)((__uint32_t)(atom_ppm_table->ulPlatformTDC));
ptr->small_ac_platform_tdc
= le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC)((__uint32_t)(atom_ppm_table->ulSmallACPlatformTDC));
ptr->apu_tdp
= le32_to_cpu(atom_ppm_table->ulApuTDP)((__uint32_t)(atom_ppm_table->ulApuTDP));
ptr->dgpu_tdp
= le32_to_cpu(atom_ppm_table->ulDGpuTDP)((__uint32_t)(atom_ppm_table->ulDGpuTDP));
ptr->dgpu_ulv_power
= le32_to_cpu(atom_ppm_table->ulDGpuUlvPower)((__uint32_t)(atom_ppm_table->ulDGpuUlvPower));
ptr->tj_max
= le32_to_cpu(atom_ppm_table->ulTjmax)((__uint32_t)(atom_ppm_table->ulTjmax));

pp_table_information->ppm_parameter_table = ptr;

return 0;
238}

240/**
* Private Function used during initialization.
* Initialize TDP limits for DPM2
* @param hwmgr Pointer to the hardware manager.
* @param powerplay_table Pointer to the PowerPlay Table.
*/
246static int init_dpm_2_parameters(
struct pp_hwmgr *hwmgr,
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
)
250{
int result = 0;
struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
ATOM_Tonga_PPM_Table *atom_ppm_table;
uint32_t disable_ppm = 0;
uint32_t disable_power_control = 0;

pp_table_information->us_ulv_voltage_offset =
le16_to_cpu(powerplay_table->usUlvVoltageOffset)((__uint16_t)(powerplay_table->usUlvVoltageOffset));

pp_table_information->ppm_parameter_table = NULL((void *)0);
pp_table_information->vddc_lookup_table = NULL((void *)0);
pp_table_information->vddgfx_lookup_table = NULL((void *)0);
/* TDP limits */
hwmgr->platform_descriptor.TDPODLimit =
le16_to_cpu(powerplay_table->usPowerControlLimit)((__uint16_t)(powerplay_table->usPowerControlLimit));
hwmgr->platform_descriptor.TDPAdjustment = 0;
hwmgr->platform_descriptor.VidAdjustment = 0;
hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
hwmgr->platform_descriptor.VidMinLimit = 0;
hwmgr->platform_descriptor.VidMaxLimit = 1500000;
hwmgr->platform_descriptor.VidStep = 6250;

disable_power_control = 0;
if (0 == disable_power_control) {
/* enable TDP overdrive (PowerControl) feature as well if supported */
if (hwmgr->platform_descriptor.TDPODLimit != 0)
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	PHM_PlatformCaps_PowerControl);
}

if (0 != powerplay_table->usVddcLookupTableOffset) {
const ATOM_Tonga_Voltage_Lookup_Table *pVddcCACTable =
	(ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
	le16_to_cpu(powerplay_table->usVddcLookupTableOffset)((__uint16_t)(powerplay_table->usVddcLookupTableOffset)));

result = get_vddc_lookup_table(hwmgr,
	&pp_table_information->vddc_lookup_table, pVddcCACTable, 16);
}

if (0 != powerplay_table->usVddgfxLookupTableOffset) {
const ATOM_Tonga_Voltage_Lookup_Table *pVddgfxCACTable =
	(ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
	le16_to_cpu(powerplay_table->usVddgfxLookupTableOffset)((__uint16_t)(powerplay_table->usVddgfxLookupTableOffset)));

result = get_vddc_lookup_table(hwmgr,
	&pp_table_information->vddgfx_lookup_table, pVddgfxCACTable, 16);
}

disable_ppm = 0;
if (0 == disable_ppm) {
atom_ppm_table = (ATOM_Tonga_PPM_Table *)
	(((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset)((__uint16_t)(powerplay_table->usPPMTableOffset)));

if (0 != powerplay_table->usPPMTableOffset) {
	if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) {
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_EnablePlatformPowerManagement);
	}
}
}

return result;
313}

315static int get_valid_clk(
struct pp_hwmgr *hwmgr,
struct phm_clock_array **clk_table,
phm_ppt_v1_clock_voltage_dependency_table const *clk_volt_pp_table
)
320{
uint32_t table_size, i;
struct phm_clock_array *table;
phm_ppt_v1_clock_voltage_dependency_record *dep_record;

PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),do { if (!((0 != clk_volt_pp_table->count))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0)
"Invalid PowerPlay Table!", return -1)do { if (!((0 != clk_volt_pp_table->count))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0);

table_size = sizeof(uint32_t) +
sizeof(uint32_t) * clk_volt_pp_table->count;

table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == table)
return -ENOMEM12;

table->count = (uint32_t)clk_volt_pp_table->count;

for (i = 0; i < table->count; i++) {
dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
clk_volt_pp_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
		phm_ppt_v1_clock_voltage_dependency_record,(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
clk_volt_pp_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
		entries, clk_volt_pp_table, i)(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
clk_volt_pp_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)));
table->values[i] = (uint32_t)dep_record->clk;
}
*clk_table = table;

return 0;
347}

349static int get_hard_limits(
struct pp_hwmgr *hwmgr,
struct phm_clock_and_voltage_limits *limits,
ATOM_Tonga_Hard_Limit_Table const *limitable
)
354{
PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1)do { if (!((0 != limitable->ucNumEntries))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0);

/* currently we always take entries[0] parameters */
limits->sclk = le32_to_cpu(limitable->entries[0].ulSCLKLimit)((__uint32_t)(limitable->entries[0].ulSCLKLimit));
limits->mclk = le32_to_cpu(limitable->entries[0].ulMCLKLimit)((__uint32_t)(limitable->entries[0].ulMCLKLimit));
limits->vddc = le16_to_cpu(limitable->entries[0].usVddcLimit)((__uint16_t)(limitable->entries[0].usVddcLimit));
limits->vddci = le16_to_cpu(limitable->entries[0].usVddciLimit)((__uint16_t)(limitable->entries[0].usVddciLimit));
limits->vddgfx = le16_to_cpu(limitable->entries[0].usVddgfxLimit)((__uint16_t)(limitable->entries[0].usVddgfxLimit));

return 0;
365}

367static int get_mclk_voltage_dependency_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table,
ATOM_Tonga_MCLK_Dependency_Table const *mclk_dep_table
)
372{
uint32_t table_size, i;
phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record;
ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record;

PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),do { if (!((0 != mclk_dep_table->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0)
"Invalid PowerPlay Table!", return -1)do { if (!((0 != mclk_dep_table->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0);

table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
* mclk_dep_table->ucNumEntries;

mclk_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == mclk_table)
return -ENOMEM12;

mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;

for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
mclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
mclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
			phm_ppt_v1_clock_voltage_dependency_record,(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
mclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
				entries, mclk_table, i)(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
mclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)));
mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
i)))
			ATOM_Tonga_MCLK_Dependency_Record,(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
i)))
				entries, mclk_dep_table, i)(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
i)));
mclk_table_record->vddInd = mclk_dep_record->ucVddcInd;
mclk_table_record->vdd_offset = le16_to_cpu(mclk_dep_record->usVddgfxOffset)((__uint16_t)(mclk_dep_record->usVddgfxOffset));
mclk_table_record->vddci = le16_to_cpu(mclk_dep_record->usVddci)((__uint16_t)(mclk_dep_record->usVddci));
mclk_table_record->mvdd = le16_to_cpu(mclk_dep_record->usMvdd)((__uint16_t)(mclk_dep_record->usMvdd));
mclk_table_record->clk = le32_to_cpu(mclk_dep_record->ulMclk)((__uint32_t)(mclk_dep_record->ulMclk));
}

*pp_tonga_mclk_dep_table = mclk_table;

return 0;
408}

410static int get_sclk_voltage_dependency_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
PPTable_Generic_SubTable_Header const  *sclk_dep_table
)
415{
uint32_t table_size, i;
phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record;

if (sclk_dep_table->ucRevId < 1) {
const ATOM_Tonga_SCLK_Dependency_Table *tonga_table =
	    (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table;
ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;

PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),do { if (!((0 != tonga_table->ucNumEntries))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0)
	"Invalid PowerPlay Table!", return -1)do { if (!((0 != tonga_table->ucNumEntries))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0);

table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
	* tonga_table->ucNumEntries;

sclk_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == sclk_table)
	return -ENOMEM12;

sclk_table->count = (uint32_t)tonga_table->ucNumEntries;

for (i = 0; i < tonga_table->ucNumEntries; i++) {
	sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(tonga_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
i)))
				ATOM_Tonga_SCLK_Dependency_Record,(ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(tonga_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
i)))
				entries, tonga_table, i)(ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(tonga_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
i)));
	sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
				phm_ppt_v1_clock_voltage_dependency_record,(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
				entries, sclk_table, i)(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)));
	sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
	sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset)((__uint16_t)(sclk_dep_record->usVddcOffset));
	sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk)((__uint32_t)(sclk_dep_record->ulSclk));
	sclk_table_record->cks_enable =
		(((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
	sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
}
} else {
const ATOM_Polaris_SCLK_Dependency_Table *polaris_table =
	    (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table;
ATOM_Polaris_SCLK_Dependency_Record *sclk_dep_record;

PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),do { if (!((0 != polaris_table->ucNumEntries))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0)
	"Invalid PowerPlay Table!", return -1)do { if (!((0 != polaris_table->ucNumEntries))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return -1; }
 } while (0);

table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
	* polaris_table->ucNumEntries;

sclk_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == sclk_table)
	return -ENOMEM12;

sclk_table->count = (uint32_t)polaris_table->ucNumEntries;

for (i = 0; i < polaris_table->ucNumEntries; i++) {
	sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Polaris_SCLK_Dependency_Record *)((char *)&(polaris_table
)->entries + (sizeof(ATOM_Polaris_SCLK_Dependency_Record) *
 (i)))
				ATOM_Polaris_SCLK_Dependency_Record,(ATOM_Polaris_SCLK_Dependency_Record *)((char *)&(polaris_table
)->entries + (sizeof(ATOM_Polaris_SCLK_Dependency_Record) *
 (i)))
				entries, polaris_table, i)(ATOM_Polaris_SCLK_Dependency_Record *)((char *)&(polaris_table
)->entries + (sizeof(ATOM_Polaris_SCLK_Dependency_Record) *
 (i)));
	sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
				phm_ppt_v1_clock_voltage_dependency_record,(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)))
				entries, sclk_table, i)(phm_ppt_v1_clock_voltage_dependency_record *)((char *)&(
sclk_table)->entries + (sizeof(phm_ppt_v1_clock_voltage_dependency_record
) * (i)));
	sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
	sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset)((__uint16_t)(sclk_dep_record->usVddcOffset));
	sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk)((__uint32_t)(sclk_dep_record->ulSclk));
	sclk_table_record->cks_enable =
		(((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
	sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
	sclk_table_record->sclk_offset = le32_to_cpu(sclk_dep_record->ulSclkOffset)((__uint32_t)(sclk_dep_record->ulSclkOffset));
}
}
*pp_tonga_sclk_dep_table = sclk_table;

return 0;
489}

491static int get_pcie_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_pcie_table **pp_tonga_pcie_table,
PPTable_Generic_SubTable_Header const *ptable
)
496{
uint32_t table_size, i, pcie_count;
phm_ppt_v1_pcie_table *pcie_table;
struct phm_ppt_v1_information *pp_table_information =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_pcie_record *pcie_record;

if (ptable->ucRevId < 1) {
27
←
Assuming field 'ucRevId' is < 1→
28
←
Taking true branch→
const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)ptable;
ATOM_Tonga_PCIE_Record *atom_pcie_record;

PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),do { if (!((atom_pcie_table->ucNumEntries != 0))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0)
29
←
Assuming field 'ucNumEntries' is not equal to 0→
30
←
Taking false branch→
31
←
Loop condition is false.  Exiting loop→
	"Invalid PowerPlay Table!", return -1)do { if (!((atom_pcie_table->ucNumEntries != 0))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0);

table_size = sizeof(uint32_t) +
	sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;

pcie_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (pcie_table == NULL((void *)0))
32
←
Assuming 'pcie_table' is not equal to NULL→
33
←
Taking false branch→
	return -ENOMEM12;

/*
* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
*/
pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
34
←
Access to field 'count' results in a dereference of a null pointer (loaded from field 'vdd_dep_on_sclk')
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
	pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
	pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n")printk("\0013" "amdgpu: " "Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"
);

pcie_table->count = pcie_count;
for (i = 0; i < pcie_count; i++) {
	pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)))
				phm_ppt_v1_pcie_record,(phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)))
				entries, pcie_table, i)(phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)));
	atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_PCIE_Record *)((char *)&(atom_pcie_table)->
entries + (sizeof(ATOM_Tonga_PCIE_Record) * (i)))
				ATOM_Tonga_PCIE_Record,(ATOM_Tonga_PCIE_Record *)((char *)&(atom_pcie_table)->
entries + (sizeof(ATOM_Tonga_PCIE_Record) * (i)))
				entries, atom_pcie_table, i)(ATOM_Tonga_PCIE_Record *)((char *)&(atom_pcie_table)->
entries + (sizeof(ATOM_Tonga_PCIE_Record) * (i)));
	pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed;
	pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth)((__uint16_t)(atom_pcie_record->usPCIELaneWidth));
}

*pp_tonga_pcie_table = pcie_table;
} else {
/* Polaris10/Polaris11 and newer. */
const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)ptable;
ATOM_Polaris10_PCIE_Record *atom_pcie_record;

PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),do { if (!((atom_pcie_table->ucNumEntries != 0))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0)
	"Invalid PowerPlay Table!", return -1)do { if (!((atom_pcie_table->ucNumEntries != 0))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0);

table_size = sizeof(uint32_t) +
	sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;

pcie_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (pcie_table == NULL((void *)0))
	return -ENOMEM12;

/*
* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
*/
pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
	pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
	pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n")printk("\0013" "amdgpu: " "Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"
);

pcie_table->count = pcie_count;

for (i = 0; i < pcie_count; i++) {
	pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)))
				phm_ppt_v1_pcie_record,(phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)))
				entries, pcie_table, i)(phm_ppt_v1_pcie_record *)((char *)&(pcie_table)->entries
 + (sizeof(phm_ppt_v1_pcie_record) * (i)));
	atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Polaris10_PCIE_Record *)((char *)&(atom_pcie_table)
->entries + (sizeof(ATOM_Polaris10_PCIE_Record) * (i)))
				ATOM_Polaris10_PCIE_Record,(ATOM_Polaris10_PCIE_Record *)((char *)&(atom_pcie_table)
->entries + (sizeof(ATOM_Polaris10_PCIE_Record) * (i)))
				entries, atom_pcie_table, i)(ATOM_Polaris10_PCIE_Record *)((char *)&(atom_pcie_table)
->entries + (sizeof(ATOM_Polaris10_PCIE_Record) * (i)));
	pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed;
	pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth)((__uint16_t)(atom_pcie_record->usPCIELaneWidth));
	pcie_record->pcie_sclk = le32_to_cpu(atom_pcie_record->ulPCIE_Sclk)((__uint32_t)(atom_pcie_record->ulPCIE_Sclk));
}

*pp_tonga_pcie_table = pcie_table;
}

return 0;
585}

587static int get_cac_tdp_table(
struct pp_hwmgr *hwmgr,
struct phm_cac_tdp_table **cac_tdp_table,
const PPTable_Generic_SubTable_Header * table
)
592{
uint32_t table_size;
struct phm_cac_tdp_table *tdp_table;

table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);
tdp_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == tdp_table)
return -ENOMEM12;

hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == hwmgr->dyn_state.cac_dtp_table) {
kfree(tdp_table);
return -ENOMEM12;
}

if (table->ucRevId < 3) {
const ATOM_Tonga_PowerTune_Table *tonga_table =
	(ATOM_Tonga_PowerTune_Table *)table;
tdp_table->usTDP = le16_to_cpu(tonga_table->usTDP)((__uint16_t)(tonga_table->usTDP));
tdp_table->usConfigurableTDP =
	le16_to_cpu(tonga_table->usConfigurableTDP)((__uint16_t)(tonga_table->usConfigurableTDP));
tdp_table->usTDC = le16_to_cpu(tonga_table->usTDC)((__uint16_t)(tonga_table->usTDC));
tdp_table->usBatteryPowerLimit =
	le16_to_cpu(tonga_table->usBatteryPowerLimit)((__uint16_t)(tonga_table->usBatteryPowerLimit));
tdp_table->usSmallPowerLimit =
	le16_to_cpu(tonga_table->usSmallPowerLimit)((__uint16_t)(tonga_table->usSmallPowerLimit));
tdp_table->usLowCACLeakage =
	le16_to_cpu(tonga_table->usLowCACLeakage)((__uint16_t)(tonga_table->usLowCACLeakage));
tdp_table->usHighCACLeakage =
	le16_to_cpu(tonga_table->usHighCACLeakage)((__uint16_t)(tonga_table->usHighCACLeakage));
tdp_table->usMaximumPowerDeliveryLimit =
	le16_to_cpu(tonga_table->usMaximumPowerDeliveryLimit)((__uint16_t)(tonga_table->usMaximumPowerDeliveryLimit));
tdp_table->usDefaultTargetOperatingTemp =
	le16_to_cpu(tonga_table->usTjMax)((__uint16_t)(tonga_table->usTjMax));
tdp_table->usTargetOperatingTemp =
	le16_to_cpu(tonga_table->usTjMax)((__uint16_t)(tonga_table->usTjMax)); /*Set the initial temp to the same as default */
tdp_table->usPowerTuneDataSetID =
	le16_to_cpu(tonga_table->usPowerTuneDataSetID)((__uint16_t)(tonga_table->usPowerTuneDataSetID));
tdp_table->usSoftwareShutdownTemp =
	le16_to_cpu(tonga_table->usSoftwareShutdownTemp)((__uint16_t)(tonga_table->usSoftwareShutdownTemp));
tdp_table->usClockStretchAmount =
	le16_to_cpu(tonga_table->usClockStretchAmount)((__uint16_t)(tonga_table->usClockStretchAmount));
} else {   /* Fiji and newer */
const ATOM_Fiji_PowerTune_Table *fijitable =
	(ATOM_Fiji_PowerTune_Table *)table;
tdp_table->usTDP = le16_to_cpu(fijitable->usTDP)((__uint16_t)(fijitable->usTDP));
tdp_table->usConfigurableTDP = le16_to_cpu(fijitable->usConfigurableTDP)((__uint16_t)(fijitable->usConfigurableTDP));
tdp_table->usTDC = le16_to_cpu(fijitable->usTDC)((__uint16_t)(fijitable->usTDC));
tdp_table->usBatteryPowerLimit = le16_to_cpu(fijitable->usBatteryPowerLimit)((__uint16_t)(fijitable->usBatteryPowerLimit));
tdp_table->usSmallPowerLimit = le16_to_cpu(fijitable->usSmallPowerLimit)((__uint16_t)(fijitable->usSmallPowerLimit));
tdp_table->usLowCACLeakage = le16_to_cpu(fijitable->usLowCACLeakage)((__uint16_t)(fijitable->usLowCACLeakage));
tdp_table->usHighCACLeakage = le16_to_cpu(fijitable->usHighCACLeakage)((__uint16_t)(fijitable->usHighCACLeakage));
tdp_table->usMaximumPowerDeliveryLimit =
	le16_to_cpu(fijitable->usMaximumPowerDeliveryLimit)((__uint16_t)(fijitable->usMaximumPowerDeliveryLimit));
tdp_table->usDefaultTargetOperatingTemp =
	le16_to_cpu(fijitable->usTjMax)((__uint16_t)(fijitable->usTjMax));
tdp_table->usTargetOperatingTemp =
	le16_to_cpu(fijitable->usTjMax)((__uint16_t)(fijitable->usTjMax)); /*Set the initial temp to the same as default */
tdp_table->usPowerTuneDataSetID =
	le16_to_cpu(fijitable->usPowerTuneDataSetID)((__uint16_t)(fijitable->usPowerTuneDataSetID));
tdp_table->usSoftwareShutdownTemp =
	le16_to_cpu(fijitable->usSoftwareShutdownTemp)((__uint16_t)(fijitable->usSoftwareShutdownTemp));
tdp_table->usClockStretchAmount =
	le16_to_cpu(fijitable->usClockStretchAmount)((__uint16_t)(fijitable->usClockStretchAmount));
tdp_table->usTemperatureLimitHotspot =
	le16_to_cpu(fijitable->usTemperatureLimitHotspot)((__uint16_t)(fijitable->usTemperatureLimitHotspot));
tdp_table->usTemperatureLimitLiquid1 =
	le16_to_cpu(fijitable->usTemperatureLimitLiquid1)((__uint16_t)(fijitable->usTemperatureLimitLiquid1));
tdp_table->usTemperatureLimitLiquid2 =
	le16_to_cpu(fijitable->usTemperatureLimitLiquid2)((__uint16_t)(fijitable->usTemperatureLimitLiquid2));
tdp_table->usTemperatureLimitVrVddc =
	le16_to_cpu(fijitable->usTemperatureLimitVrVddc)((__uint16_t)(fijitable->usTemperatureLimitVrVddc));
tdp_table->usTemperatureLimitVrMvdd =
	le16_to_cpu(fijitable->usTemperatureLimitVrMvdd)((__uint16_t)(fijitable->usTemperatureLimitVrMvdd));
tdp_table->usTemperatureLimitPlx =
	le16_to_cpu(fijitable->usTemperatureLimitPlx)((__uint16_t)(fijitable->usTemperatureLimitPlx));
tdp_table->ucLiquid1_I2C_address =
	fijitable->ucLiquid1_I2C_address;
tdp_table->ucLiquid2_I2C_address =
	fijitable->ucLiquid2_I2C_address;
tdp_table->ucLiquid_I2C_Line =
	fijitable->ucLiquid_I2C_Line;
tdp_table->ucVr_I2C_address = fijitable->ucVr_I2C_address;
tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
}

*cac_tdp_table = tdp_table;

return 0;
685}

687static int get_mm_clock_voltage_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_mm_clock_voltage_dependency_table **tonga_mm_table,
const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table
)
692{
uint32_t table_size, i;
const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record;
phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
phm_ppt_v1_mm_clock_voltage_dependency_record *mm_table_record;

PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),do { if (!((0 != mm_dependency_table->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0)
"Invalid PowerPlay Table!", return -1)do { if (!((0 != mm_dependency_table->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0);
table_size = sizeof(uint32_t) +
sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record)
* mm_dependency_table->ucNumEntries;
mm_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == mm_table)
return -ENOMEM12;

mm_table->count = mm_dependency_table->ucNumEntries;

for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
mm_dependency_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dependency_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (i
)))
				ATOM_Tonga_MM_Dependency_Record,(ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dependency_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (i
)))
				entries, mm_dependency_table, i)(ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dependency_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (i
)));
mm_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((phm_ppt_v1_mm_clock_voltage_dependency_record *)((char *)&
(mm_table)->entries + (sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record
) * (i)))
			phm_ppt_v1_mm_clock_voltage_dependency_record,(phm_ppt_v1_mm_clock_voltage_dependency_record *)((char *)&
(mm_table)->entries + (sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record
) * (i)))
			entries, mm_table, i)(phm_ppt_v1_mm_clock_voltage_dependency_record *)((char *)&
(mm_table)->entries + (sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record
) * (i)));
mm_table_record->vddcInd = mm_dependency_record->ucVddcInd;
mm_table_record->vddgfx_offset = le16_to_cpu(mm_dependency_record->usVddgfxOffset)((__uint16_t)(mm_dependency_record->usVddgfxOffset));
mm_table_record->aclk = le32_to_cpu(mm_dependency_record->ulAClk)((__uint32_t)(mm_dependency_record->ulAClk));
mm_table_record->samclock = le32_to_cpu(mm_dependency_record->ulSAMUClk)((__uint32_t)(mm_dependency_record->ulSAMUClk));
mm_table_record->eclk = le32_to_cpu(mm_dependency_record->ulEClk)((__uint32_t)(mm_dependency_record->ulEClk));
mm_table_record->vclk = le32_to_cpu(mm_dependency_record->ulVClk)((__uint32_t)(mm_dependency_record->ulVClk));
mm_table_record->dclk = le32_to_cpu(mm_dependency_record->ulDClk)((__uint32_t)(mm_dependency_record->ulDClk));
}

*tonga_mm_table = mm_table;

return 0;
729}

731static int get_gpio_table(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_gpio_table **pp_tonga_gpio_table,
const ATOM_Tonga_GPIO_Table *atom_gpio_table)
734{
uint32_t table_size;
struct phm_ppt_v1_gpio_table *pp_gpio_table;
struct phm_ppt_v1_information *pp_table_information =
	(struct phm_ppt_v1_information *)(hwmgr->pptable);

table_size = sizeof(struct phm_ppt_v1_gpio_table);
pp_gpio_table = kzalloc(table_size, GFP_KERNEL(0x0001 | 0x0004));
if (!pp_gpio_table)
return -ENOMEM12;

if (pp_table_information->vdd_dep_on_sclk->count <
	atom_gpio_table->ucVRHotTriggeredSclkDpmIndex)
PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "SCLK DPM index for VRHot cannot exceed the total sclk level count!"
); ; } } while (0)
		"SCLK DPM index for VRHot cannot exceed the total sclk level count!",)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "SCLK DPM index for VRHot cannot exceed the total sclk level count!"
); ; } } while (0);
else
pp_gpio_table->vrhot_triggered_sclk_dpm_index =
		atom_gpio_table->ucVRHotTriggeredSclkDpmIndex;

*pp_tonga_gpio_table = pp_gpio_table;

return 0;
756}
757/**
* Private Function used during initialization.
* Initialize clock voltage dependency
* @param hwmgr Pointer to the hardware manager.
* @param powerplay_table Pointer to the PowerPlay Table.
*/
763static int init_clock_voltage_dependency(
struct pp_hwmgr *hwmgr,
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
)
767{
int result = 0;
struct phm_ppt_v1_information *pp_table_information =
(struct phm_ppt_v1_information *)(hwmgr->pptable);

const ATOM_Tonga_MM_Dependency_Table *mm_dependency_table =
(const ATOM_Tonga_MM_Dependency_Table *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usMMDependencyTableOffset)((__uint16_t)(powerplay_table->usMMDependencyTableOffset)));
const PPTable_Generic_SubTable_Header *pPowerTuneTable =
(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usPowerTuneTableOffset)((__uint16_t)(powerplay_table->usPowerTuneTableOffset)));
const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
(const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)((__uint16_t)(powerplay_table->usMclkDependencyTableOffset
)));
const PPTable_Generic_SubTable_Header *sclk_dep_table =
(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)((__uint16_t)(powerplay_table->usSclkDependencyTableOffset
)));
const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
(const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usHardLimitTableOffset)((__uint16_t)(powerplay_table->usHardLimitTableOffset)));
const PPTable_Generic_SubTable_Header *pcie_table =
(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usPCIETableOffset)((__uint16_t)(powerplay_table->usPCIETableOffset)));
const ATOM_Tonga_GPIO_Table *gpio_table =
(const ATOM_Tonga_GPIO_Table *)(((unsigned long) powerplay_table) +
le16_to_cpu(powerplay_table->usGPIOTableOffset)((__uint16_t)(powerplay_table->usGPIOTableOffset)));

pp_table_information->vdd_dep_on_sclk = NULL((void *)0);
15
←
Null pointer value stored to field 'vdd_dep_on_sclk'→
pp_table_information->vdd_dep_on_mclk = NULL((void *)0);
pp_table_information->mm_dep_table = NULL((void *)0);
pp_table_information->pcie_table = NULL((void *)0);
pp_table_information->gpio_table = NULL((void *)0);

if (powerplay_table->usMMDependencyTableOffset != 0)
16
←
Assuming field 'usMMDependencyTableOffset' is equal to 0→
17
←
Taking false branch→
result = get_mm_clock_voltage_table(hwmgr,
&pp_table_information->mm_dep_table, mm_dependency_table);

if (result17.1
'result' is equal to 0
 == 0 && powerplay_table->usPowerTuneTableOffset != 0)
18
←
Assuming field 'usPowerTuneTableOffset' is equal to 0→
19
←
Taking false branch→
result = get_cac_tdp_table(hwmgr,
&pp_table_information->cac_dtp_table, pPowerTuneTable);

if (result19.1
'result' is equal to 0
 == 0 && powerplay_table->usSclkDependencyTableOffset != 0)
20
←
Assuming field 'usSclkDependencyTableOffset' is equal to 0→
21
←
Taking false branch→
result = get_sclk_voltage_dependency_table(hwmgr,
&pp_table_information->vdd_dep_on_sclk, sclk_dep_table);

if (result21.1
'result' is equal to 0
 == 0 && powerplay_table->usMclkDependencyTableOffset != 0)
22
←
Assuming field 'usMclkDependencyTableOffset' is equal to 0→
23
←
Taking false branch→
result = get_mclk_voltage_dependency_table(hwmgr,
&pp_table_information->vdd_dep_on_mclk, mclk_dep_table);

if (result23.1
'result' is equal to 0
 == 0 && powerplay_table->usPCIETableOffset != 0)
24
←
Assuming field 'usPCIETableOffset' is not equal to 0→
25
←
Taking true branch→
result = get_pcie_table(hwmgr,
26
←
Calling 'get_pcie_table'→
&pp_table_information->pcie_table, pcie_table);

if (result == 0 && powerplay_table->usHardLimitTableOffset != 0)
result = get_hard_limits(hwmgr,
&pp_table_information->max_clock_voltage_on_dc, pHardLimits);

hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
pp_table_information->max_clock_voltage_on_dc.sclk;
hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
pp_table_information->max_clock_voltage_on_dc.mclk;
hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
pp_table_information->max_clock_voltage_on_dc.vddc;
hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
pp_table_information->max_clock_voltage_on_dc.vddci;

if (result == 0 && (NULL((void *)0) != pp_table_information->vdd_dep_on_mclk)
&& (0 != pp_table_information->vdd_dep_on_mclk->count))
result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values,
pp_table_information->vdd_dep_on_mclk);

if (result == 0 && (NULL((void *)0) != pp_table_information->vdd_dep_on_sclk)
&& (0 != pp_table_information->vdd_dep_on_sclk->count))
result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
pp_table_information->vdd_dep_on_sclk);

if (!result && gpio_table)
result = get_gpio_table(hwmgr, &pp_table_information->gpio_table,
		gpio_table);

return result;
848}

850/** Retrieves the (signed) Overdrive limits from VBIOS.
* The max engine clock, memory clock and max temperature come from the firmware info table.
*
* The information is placed into the platform descriptor.
*
* @param hwmgr source of the VBIOS table and owner of the platform descriptor to be updated.
* @param powerplay_table the address of the PowerPlay table.
*
* @return 1 as long as the firmware info table was present and of a supported version.
*/
860static int init_over_drive_limits(
struct pp_hwmgr *hwmgr,
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
863{
hwmgr->platform_descriptor.overdriveLimit.engineClock =
le32_to_cpu(powerplay_table->ulMaxODEngineClock)((__uint32_t)(powerplay_table->ulMaxODEngineClock));
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
le32_to_cpu(powerplay_table->ulMaxODMemoryClock)((__uint32_t)(powerplay_table->ulMaxODMemoryClock));

hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr->platform_descriptor.overdriveVDDCStep = 0;

return 0;
874}

876/**
* Private Function used during initialization.
* Inspect the PowerPlay table for obvious signs of corruption.
* @param hwmgr Pointer to the hardware manager.
* @param powerplay_table Pointer to the PowerPlay Table.
* @exception This implementation always returns 1.
*/
883static int init_thermal_controller(
struct pp_hwmgr *hwmgr,
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
)
887{
const PPTable_Generic_SubTable_Header *fan_table;
ATOM_Tonga_Thermal_Controller *thermal_controller;

thermal_controller = (ATOM_Tonga_Thermal_Controller *)
(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table->usThermalControllerOffset)((__uint16_t)(powerplay_table->usThermalControllerOffset)));
PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),do { if (!((0 != powerplay_table->usThermalControllerOffset
))) { printk("\0014" "amdgpu: " "%s\n", "Thermal controller table not set!"
); return -1; } } while (0)
"Thermal controller table not set!", return -1)do { if (!((0 != powerplay_table->usThermalControllerOffset
))) { printk("\0014" "amdgpu: " "%s\n", "Thermal controller table not set!"
); return -1; } } while (0);

hwmgr->thermal_controller.ucType = thermal_controller->ucType;
hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;

hwmgr->thermal_controller.fanInfo.bNoFan =
(0 != (thermal_controller->ucFanParameters & ATOM_TONGA_PP_FANPARAMETERS_NOFAN0x80));

hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
thermal_controller->ucFanParameters &
ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK0x0f;

hwmgr->thermal_controller.fanInfo.ulMinRPM
= thermal_controller->ucFanMinRPM * 100UL;
hwmgr->thermal_controller.fanInfo.ulMaxRPM
= thermal_controller->ucFanMaxRPM * 100UL;

set_hw_cap(
	hwmgr,
	ATOM_TONGA_PP_THERMALCONTROLLER_NONE0 != hwmgr->thermal_controller.ucType,
	PHM_PlatformCaps_ThermalController
  );

if (0 == powerplay_table->usFanTableOffset) {
hwmgr->thermal_controller.use_hw_fan_control = 1;
return 0;
}

fan_table = (const PPTable_Generic_SubTable_Header *)
(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table->usFanTableOffset)((__uint16_t)(powerplay_table->usFanTableOffset)));

PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),do { if (!((0 != powerplay_table->usFanTableOffset))) { printk
("\0014" "amdgpu: " "%s\n", "Fan table not set!"); return -1;
 } } while (0)
"Fan table not set!", return -1)do { if (!((0 != powerplay_table->usFanTableOffset))) { printk
("\0014" "amdgpu: " "%s\n", "Fan table not set!"); return -1;
 } } while (0);
PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),do { if (!((0 < fan_table->ucRevId))) { printk("\0014" "amdgpu: "
 "%s\n", "Unsupported fan table format!"); return -1; } } while
 (0)
"Unsupported fan table format!", return -1)do { if (!((0 < fan_table->ucRevId))) { printk("\0014" "amdgpu: "
 "%s\n", "Unsupported fan table format!"); return -1; } } while
 (0);

hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
= 100000;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);

if (fan_table->ucRevId < 8) {
const ATOM_Tonga_Fan_Table *tonga_fan_table =
	(ATOM_Tonga_Fan_Table *)fan_table;
hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
	= tonga_fan_table->ucTHyst;
hwmgr->thermal_controller.advanceFanControlParameters.usTMin
	= le16_to_cpu(tonga_fan_table->usTMin)((__uint16_t)(tonga_fan_table->usTMin));
hwmgr->thermal_controller.advanceFanControlParameters.usTMed
	= le16_to_cpu(tonga_fan_table->usTMed)((__uint16_t)(tonga_fan_table->usTMed));
hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
	= le16_to_cpu(tonga_fan_table->usTHigh)((__uint16_t)(tonga_fan_table->usTHigh));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
	= le16_to_cpu(tonga_fan_table->usPWMMin)((__uint16_t)(tonga_fan_table->usPWMMin));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
	= le16_to_cpu(tonga_fan_table->usPWMMed)((__uint16_t)(tonga_fan_table->usPWMMed));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
	= le16_to_cpu(tonga_fan_table->usPWMHigh)((__uint16_t)(tonga_fan_table->usPWMHigh));
hwmgr->thermal_controller.advanceFanControlParameters.usTMax
	= 10900;                  /* hard coded */
hwmgr->thermal_controller.advanceFanControlParameters.usTMax
	= le16_to_cpu(tonga_fan_table->usTMax)((__uint16_t)(tonga_fan_table->usTMax));
hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
	= tonga_fan_table->ucFanControlMode;
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
	= le16_to_cpu(tonga_fan_table->usFanPWMMax)((__uint16_t)(tonga_fan_table->usFanPWMMax));
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
	= 4836;
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
	= le16_to_cpu(tonga_fan_table->usFanOutputSensitivity)((__uint16_t)(tonga_fan_table->usFanOutputSensitivity));
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
	= le16_to_cpu(tonga_fan_table->usFanRPMMax)((__uint16_t)(tonga_fan_table->usFanRPMMax));
hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
	= (le32_to_cpu(tonga_fan_table->ulMinFanSCLKAcousticLimit)((__uint32_t)(tonga_fan_table->ulMinFanSCLKAcousticLimit)) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
	= tonga_fan_table->ucTargetTemperature;
hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
	= tonga_fan_table->ucMinimumPWMLimit;
} else {
const ATOM_Fiji_Fan_Table *fiji_fan_table =
	(ATOM_Fiji_Fan_Table *)fan_table;
hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
	= fiji_fan_table->ucTHyst;
hwmgr->thermal_controller.advanceFanControlParameters.usTMin
	= le16_to_cpu(fiji_fan_table->usTMin)((__uint16_t)(fiji_fan_table->usTMin));
hwmgr->thermal_controller.advanceFanControlParameters.usTMed
	= le16_to_cpu(fiji_fan_table->usTMed)((__uint16_t)(fiji_fan_table->usTMed));
hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
	= le16_to_cpu(fiji_fan_table->usTHigh)((__uint16_t)(fiji_fan_table->usTHigh));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
	= le16_to_cpu(fiji_fan_table->usPWMMin)((__uint16_t)(fiji_fan_table->usPWMMin));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
	= le16_to_cpu(fiji_fan_table->usPWMMed)((__uint16_t)(fiji_fan_table->usPWMMed));
hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
	= le16_to_cpu(fiji_fan_table->usPWMHigh)((__uint16_t)(fiji_fan_table->usPWMHigh));
hwmgr->thermal_controller.advanceFanControlParameters.usTMax
	= le16_to_cpu(fiji_fan_table->usTMax)((__uint16_t)(fiji_fan_table->usTMax));
hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
	= fiji_fan_table->ucFanControlMode;
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
	= le16_to_cpu(fiji_fan_table->usFanPWMMax)((__uint16_t)(fiji_fan_table->usFanPWMMax));
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
	= 4836;
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
	= le16_to_cpu(fiji_fan_table->usFanOutputSensitivity)((__uint16_t)(fiji_fan_table->usFanOutputSensitivity));
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
	= le16_to_cpu(fiji_fan_table->usFanRPMMax)((__uint16_t)(fiji_fan_table->usFanRPMMax));
hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
	= (le32_to_cpu(fiji_fan_table->ulMinFanSCLKAcousticLimit)((__uint32_t)(fiji_fan_table->ulMinFanSCLKAcousticLimit)) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
	= fiji_fan_table->ucTargetTemperature;
hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
	= fiji_fan_table->ucMinimumPWMLimit;

hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
	= le16_to_cpu(fiji_fan_table->usFanGainEdge)((__uint16_t)(fiji_fan_table->usFanGainEdge));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
	= le16_to_cpu(fiji_fan_table->usFanGainHotspot)((__uint16_t)(fiji_fan_table->usFanGainHotspot));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
	= le16_to_cpu(fiji_fan_table->usFanGainLiquid)((__uint16_t)(fiji_fan_table->usFanGainLiquid));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
	= le16_to_cpu(fiji_fan_table->usFanGainVrVddc)((__uint16_t)(fiji_fan_table->usFanGainVrVddc));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
	= le16_to_cpu(fiji_fan_table->usFanGainVrMvdd)((__uint16_t)(fiji_fan_table->usFanGainVrMvdd));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
	= le16_to_cpu(fiji_fan_table->usFanGainPlx)((__uint16_t)(fiji_fan_table->usFanGainPlx));
hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
	= le16_to_cpu(fiji_fan_table->usFanGainHbm)((__uint16_t)(fiji_fan_table->usFanGainHbm));
}

return 0;
1028}

1030/**
* Private Function used during initialization.
* Inspect the PowerPlay table for obvious signs of corruption.
* @param hwmgr Pointer to the hardware manager.
* @param powerplay_table Pointer to the PowerPlay Table.
* @exception 2 if the powerplay table is incorrect.
*/
1037static int check_powerplay_tables(
struct pp_hwmgr *hwmgr,
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
)
1041{
const ATOM_Tonga_State_Array *state_arrays;

state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table->usStateArrayOffset)((__uint16_t)(powerplay_table->usStateArrayOffset)));

PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=do { if (!((7 <= powerplay_table->sHeader.ucTableFormatRevision
))) { printk("\0014" "amdgpu: " "%s\n", "Unsupported PPTable format!"
); return -1; } } while (0)
powerplay_table->sHeader.ucTableFormatRevision),do { if (!((7 <= powerplay_table->sHeader.ucTableFormatRevision
))) { printk("\0014" "amdgpu: " "%s\n", "Unsupported PPTable format!"
); return -1; } } while (0)
"Unsupported PPTable format!", return -1)do { if (!((7 <= powerplay_table->sHeader.ucTableFormatRevision
))) { printk("\0014" "amdgpu: " "%s\n", "Unsupported PPTable format!"
); return -1; } } while (0);
PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),do { if (!((0 != powerplay_table->usStateArrayOffset))) { printk
("\0014" "amdgpu: " "%s\n", "State table is not set!"); return
 -1; } } while (0)
"State table is not set!", return -1)do { if (!((0 != powerplay_table->usStateArrayOffset))) { printk
("\0014" "amdgpu: " "%s\n", "State table is not set!"); return
 -1; } } while (0);
PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),do { if (!((0 < powerplay_table->sHeader.usStructureSize
))) { printk("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"
); return -1; } } while (0)
"Invalid PowerPlay Table!", return -1)do { if (!((0 < powerplay_table->sHeader.usStructureSize
))) { printk("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"
); return -1; } } while (0);
PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),do { if (!((0 < state_arrays->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0)
"Invalid PowerPlay Table!", return -1)do { if (!((0 < state_arrays->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table!"); return
 -1; } } while (0);

return 0;
1058}

1060static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
1061{
int result = 0;
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;

hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL(0x0001 | 0x0004));

PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),do { if (!((((void *)0) != hwmgr->pptable))) { printk("\0014"
 "amdgpu: " "%s\n", "Failed to allocate hwmgr->pptable!");
 return -12; } } while (0)
1
Assuming null is not equal to field 'pptable'→
2
←
Taking false branch→
3
←
Loop condition is false.  Exiting loop→
	    "Failed to allocate hwmgr->pptable!", return -ENOMEM)do { if (!((((void *)0) != hwmgr->pptable))) { printk("\0014"
 "amdgpu: " "%s\n", "Failed to allocate hwmgr->pptable!");
 return -12; } } while (0);

powerplay_table = get_powerplay_table(hwmgr);

PP_ASSERT_WITH_CODE((NULL != powerplay_table),do { if (!((((void *)0) != powerplay_table))) { printk("\0014"
 "amdgpu: " "%s\n", "Missing PowerPlay Table!"); return -1; }
 } while (0)
4
←
Taking false branch→
5
←
Loop condition is false.  Exiting loop→
"Missing PowerPlay Table!", return -1)do { if (!((((void *)0) != powerplay_table))) { printk("\0014"
 "amdgpu: " "%s\n", "Missing PowerPlay Table!"); return -1; }
 } while (0);

result = check_powerplay_tables(hwmgr, powerplay_table);

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "check_powerplay_tables failed"); return result; } } while (
0)
6
←
Taking false branch→
7
←
Loop condition is false.  Exiting loop→
	    "check_powerplay_tables failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "check_powerplay_tables failed"); return result; } } while (
0);

result = set_platform_caps(hwmgr,
		   le32_to_cpu(powerplay_table->ulPlatformCaps)((__uint32_t)(powerplay_table->ulPlatformCaps)));

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "set_platform_caps failed"); return result; } } while (0)
8
←
Taking false branch→
9
←
Loop condition is false.  Exiting loop→
	    "set_platform_caps failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "set_platform_caps failed"); return result; } } while (0);

result = init_thermal_controller(hwmgr, powerplay_table);

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_thermal_controller failed"); return result; } } while
 (0)
10
←
Taking false branch→
11
←
Loop condition is false.  Exiting loop→
	    "init_thermal_controller failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_thermal_controller failed"); return result; } } while
 (0);

result = init_over_drive_limits(hwmgr, powerplay_table);

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_over_drive_limits failed"); return result; } } while (
0)
12
←
Taking false branch→
13
←
Loop condition is false.  Exiting loop→
	    "init_over_drive_limits failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_over_drive_limits failed"); return result; } } while (
0);

result = init_clock_voltage_dependency(hwmgr, powerplay_table);
14
←
Calling 'init_clock_voltage_dependency'→

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_clock_voltage_dependency failed"); return result; } }
 while (0)
	    "init_clock_voltage_dependency failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_clock_voltage_dependency failed"); return result; } }
 while (0);

result = init_dpm_2_parameters(hwmgr, powerplay_table);

PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_dpm_2_parameters failed"); return result; } } while (
0)
	    "init_dpm_2_parameters failed", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "init_dpm_2_parameters failed"); return result; } } while (
0);

return result;
1107}

1109static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
1110{
struct phm_ppt_v1_information *pp_table_information =
(struct phm_ppt_v1_information *)(hwmgr->pptable);

kfree(pp_table_information->vdd_dep_on_sclk);
pp_table_information->vdd_dep_on_sclk = NULL((void *)0);

kfree(pp_table_information->vdd_dep_on_mclk);
pp_table_information->vdd_dep_on_mclk = NULL((void *)0);

kfree(pp_table_information->valid_mclk_values);
pp_table_information->valid_mclk_values = NULL((void *)0);

kfree(pp_table_information->valid_sclk_values);
pp_table_information->valid_sclk_values = NULL((void *)0);

kfree(pp_table_information->vddc_lookup_table);
pp_table_information->vddc_lookup_table = NULL((void *)0);

kfree(pp_table_information->vddgfx_lookup_table);
pp_table_information->vddgfx_lookup_table = NULL((void *)0);

kfree(pp_table_information->mm_dep_table);
pp_table_information->mm_dep_table = NULL((void *)0);

kfree(pp_table_information->cac_dtp_table);
pp_table_information->cac_dtp_table = NULL((void *)0);

kfree(hwmgr->dyn_state.cac_dtp_table);
hwmgr->dyn_state.cac_dtp_table = NULL((void *)0);

kfree(pp_table_information->ppm_parameter_table);
pp_table_information->ppm_parameter_table = NULL((void *)0);

kfree(pp_table_information->pcie_table);
pp_table_information->pcie_table = NULL((void *)0);

kfree(pp_table_information->gpio_table);
pp_table_information->gpio_table = NULL((void *)0);

kfree(hwmgr->pptable);
hwmgr->pptable = NULL((void *)0);

return 0;
1154}

1156const struct pp_table_func pptable_v1_0_funcs = {
.pptable_init = pp_tables_v1_0_initialize,
.pptable_fini = pp_tables_v1_0_uninitialize,
1159};

1161int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr)
1162{
ATOM_Tonga_State_Array const *state_arrays;
const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);

PP_ASSERT_WITH_CODE((NULL != pp_table),do { if (!((((void *)0) != pp_table))) { printk("\0014" "amdgpu: "
 "%s\n", "Missing PowerPlay Table!"); return -1; } } while (0
)
	"Missing PowerPlay Table!", return -1)do { if (!((((void *)0) != pp_table))) { printk("\0014" "amdgpu: "
 "%s\n", "Missing PowerPlay Table!"); return -1; } } while (0
);
PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=do { if (!((pp_table->sHeader.ucTableFormatRevision >= 7
))) { printk("\0014" "amdgpu: " "%s\n", "Incorrect PowerPlay table revision!"
); return -1; } } while (0)
	ATOM_Tonga_TABLE_REVISION_TONGA),do { if (!((pp_table->sHeader.ucTableFormatRevision >= 7
))) { printk("\0014" "amdgpu: " "%s\n", "Incorrect PowerPlay table revision!"
); return -1; } } while (0)
	"Incorrect PowerPlay table revision!", return -1)do { if (!((pp_table->sHeader.ucTableFormatRevision >= 7
))) { printk("\0014" "amdgpu: " "%s\n", "Incorrect PowerPlay table revision!"
); return -1; } } while (0);

state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
	le16_to_cpu(pp_table->usStateArrayOffset)((__uint16_t)(pp_table->usStateArrayOffset)));

return (uint32_t)(state_arrays->ucNumEntries);
1176}

1178/**
1179* Private function to convert flags stored in the BIOS to software flags in PowerPlay.
1180*/
1181static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
uint16_t classification, uint16_t classification2)
1183{
uint32_t result = 0;

if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT0x0008)
result |= PP_StateClassificationFlag_Boot;

if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL0x0010)
result |= PP_StateClassificationFlag_Thermal;

if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE0x0020)
result |= PP_StateClassificationFlag_LimitedPowerSource;

if (classification & ATOM_PPLIB_CLASSIFICATION_REST0x0040)
result |= PP_StateClassificationFlag_Rest;

if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED0x0080)
result |= PP_StateClassificationFlag_Forced;

if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI0x1000)
result |= PP_StateClassificationFlag_ACPI;

if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_20x0001)
result |= PP_StateClassificationFlag_LimitedPowerSource_2;

return result;
1208}

1210static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
1211{
const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
const ATOM_Tonga_VCE_State_Table *vce_state_table;


if (pp_table == NULL((void *)0))
return 0;

vce_state_table = (void *)pp_table +
	le16_to_cpu(pp_table->usVCEStateTableOffset)((__uint16_t)(pp_table->usVCEStateTableOffset));

return vce_state_table->ucNumEntries;
1223}

1225static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,
struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag)
1227{
const ATOM_Tonga_VCE_State_Record *vce_state_record;
ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;
ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record;
ATOM_Tonga_MM_Dependency_Record *mm_dep_record;
const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr);
const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable)
					  + le16_to_cpu(pptable->usVCEStateTableOffset)((__uint16_t)(pptable->usVCEStateTableOffset)));
const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = (ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long)pptable)
					  + le16_to_cpu(pptable->usSclkDependencyTableOffset)((__uint16_t)(pptable->usSclkDependencyTableOffset)));
const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = (ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long)pptable)
					  + le16_to_cpu(pptable->usMclkDependencyTableOffset)((__uint16_t)(pptable->usMclkDependencyTableOffset)));
const ATOM_Tonga_MM_Dependency_Table *mm_dep_table = (ATOM_Tonga_MM_Dependency_Table *)(((unsigned long)pptable)
					  + le16_to_cpu(pptable->usMMDependencyTableOffset)((__uint16_t)(pptable->usMMDependencyTableOffset)));

PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries),do { if (!((i < vce_state_table->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Requested state entry ID is out of range!"
); return -22; } } while (0)
	 "Requested state entry ID is out of range!",do { if (!((i < vce_state_table->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Requested state entry ID is out of range!"
); return -22; } } while (0)
	 return -EINVAL)do { if (!((i < vce_state_table->ucNumEntries))) { printk
("\0014" "amdgpu: " "%s\n", "Requested state entry ID is out of range!"
); return -22; } } while (0);

vce_state_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_VCE_State_Record *)((char *)&(vce_state_table
)->entries + (sizeof(ATOM_Tonga_VCE_State_Record) * (i)))
			ATOM_Tonga_VCE_State_Record,(ATOM_Tonga_VCE_State_Record *)((char *)&(vce_state_table
)->entries + (sizeof(ATOM_Tonga_VCE_State_Record) * (i)))
			entries, vce_state_table, i)(ATOM_Tonga_VCE_State_Record *)((char *)&(vce_state_table
)->entries + (sizeof(ATOM_Tonga_VCE_State_Record) * (i)));
sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(sclk_dep_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
vce_state_record->ucSCLKIndex)))
			ATOM_Tonga_SCLK_Dependency_Record,(ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(sclk_dep_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
vce_state_record->ucSCLKIndex)))
			entries, sclk_dep_table,(ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(sclk_dep_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
vce_state_record->ucSCLKIndex)))
			vce_state_record->ucSCLKIndex)(ATOM_Tonga_SCLK_Dependency_Record *)((char *)&(sclk_dep_table
)->entries + (sizeof(ATOM_Tonga_SCLK_Dependency_Record) * (
vce_state_record->ucSCLKIndex)));
mm_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dep_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (vce_state_record
->ucVCEClockIndex)))
			ATOM_Tonga_MM_Dependency_Record,(ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dep_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (vce_state_record
->ucVCEClockIndex)))
			entries, mm_dep_table,(ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dep_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (vce_state_record
->ucVCEClockIndex)))
			vce_state_record->ucVCEClockIndex)(ATOM_Tonga_MM_Dependency_Record *)((char *)&(mm_dep_table
)->entries + (sizeof(ATOM_Tonga_MM_Dependency_Record) * (vce_state_record
->ucVCEClockIndex)));
*flag = vce_state_record->ucFlag;

vce_state->evclk = le32_to_cpu(mm_dep_record->ulEClk)((__uint32_t)(mm_dep_record->ulEClk));
vce_state->ecclk = le32_to_cpu(mm_dep_record->ulEClk)((__uint32_t)(mm_dep_record->ulEClk));
vce_state->sclk = le32_to_cpu(sclk_dep_record->ulSclk)((__uint32_t)(sclk_dep_record->ulSclk));

if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries)
mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
mclk_dep_table->ucNumEntries - 1)))
			ATOM_Tonga_MCLK_Dependency_Record,(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
mclk_dep_table->ucNumEntries - 1)))
			entries, mclk_dep_table,(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
mclk_dep_table->ucNumEntries - 1)))
			mclk_dep_table->ucNumEntries - 1)(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
mclk_dep_table->ucNumEntries - 1)));
else
mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
vce_state_record->ucMCLKIndex)))
			ATOM_Tonga_MCLK_Dependency_Record,(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
vce_state_record->ucMCLKIndex)))
			entries, mclk_dep_table,(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
vce_state_record->ucMCLKIndex)))
			vce_state_record->ucMCLKIndex)(ATOM_Tonga_MCLK_Dependency_Record *)((char *)&(mclk_dep_table
)->entries + (sizeof(ATOM_Tonga_MCLK_Dependency_Record) * (
vce_state_record->ucMCLKIndex)));

vce_state->mclk = le32_to_cpu(mclk_dep_record->ulMclk)((__uint32_t)(mclk_dep_record->ulMclk));
return 0;
1276}

1278/**
1279* Create a Power State out of an entry in the PowerPlay table.
1280* This function is called by the hardware back-end.
1281* @param hwmgr Pointer to the hardware manager.
1282* @param entry_index The index of the entry to be extracted from the table.
1283* @param power_state The address of the PowerState instance being created.
1284* @return -1 if the entry cannot be retrieved.
1285*/
1286int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr,
uint32_t entry_index, struct pp_power_state *power_state,
int (*call_back_func)(struct pp_hwmgr *, void *,
		struct pp_power_state *, void *, uint32_t))
1290{
int result = 0;
const ATOM_Tonga_State_Array *state_arrays;
const ATOM_Tonga_State *state_entry;
const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
int i, j;
uint32_t flags = 0;

PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;)do { if (!((((void *)0) != pp_table))) { printk("\0014" "amdgpu: "
 "%s\n", "Missing PowerPlay Table!"); return -1;; } } while (
0);
power_state->classification.bios_index = entry_index;

if (pp_table->sHeader.ucTableFormatRevision >=
	ATOM_Tonga_TABLE_REVISION_TONGA7) {
state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
		le16_to_cpu(pp_table->usStateArrayOffset)((__uint16_t)(pp_table->usStateArrayOffset)));

PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),do { if (!((0 < pp_table->usStateArrayOffset))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array Offset."
); return -1; } } while (0)
		"Invalid PowerPlay Table State Array Offset.", return -1)do { if (!((0 < pp_table->usStateArrayOffset))) { printk
("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array Offset."
); return -1; } } while (0);
PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),do { if (!((0 < state_arrays->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array."
); return -1; } } while (0)
		"Invalid PowerPlay Table State Array.", return -1)do { if (!((0 < state_arrays->ucNumEntries))) { printk(
"\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array."
); return -1; } } while (0);
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),do { if (!((entry_index <= state_arrays->ucNumEntries))
) { printk("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array Entry."
); return -1; } } while (0)
		"Invalid PowerPlay Table State Array Entry.", return -1)do { if (!((entry_index <= state_arrays->ucNumEntries))
) { printk("\0014" "amdgpu: " "%s\n", "Invalid PowerPlay Table State Array Entry."
); return -1; } } while (0);

state_entry = GET_FLEXIBLE_ARRAY_MEMBER_ADDR((ATOM_Tonga_State *)((char *)&(state_arrays)->entries +
 (sizeof(ATOM_Tonga_State) * (entry_index)))
				ATOM_Tonga_State, entries,(ATOM_Tonga_State *)((char *)&(state_arrays)->entries +
 (sizeof(ATOM_Tonga_State) * (entry_index)))
				state_arrays, entry_index)(ATOM_Tonga_State *)((char *)&(state_arrays)->entries +
 (sizeof(ATOM_Tonga_State) * (entry_index)));

result = call_back_func(hwmgr, (void *)state_entry, power_state,
		(void *)pp_table,
		make_classification_flags(hwmgr,
			le16_to_cpu(state_entry->usClassification)((__uint16_t)(state_entry->usClassification)),
			le16_to_cpu(state_entry->usClassification2)((__uint16_t)(state_entry->usClassification2))));
}

if (!result && (power_state->classification.flags &
	PP_StateClassificationFlag_Boot))
result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));

hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);

if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS6)) {
for (j = 0; j < i; j++)
	ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL((void *)0), &flags);
}

return result;
1336}
