Bug Summary

File:dev/pci/drm/amd/amdgpu/psp_v12_0.c
Warning:line 86, column 6
Access to field 'data' results in a dereference of a null pointer (loaded from field 'ta_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name psp_v12_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

/usr/src/sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

→
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
43MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
44
45/* address block */
46#define smnMP1_FIRMWARE_FLAGS0x3010024 0x3010024
47
48static int psp_v12_0_init_microcode(struct psp_context *psp)
49{
50 struct amdgpu_device *adev = psp->adev;
51 const char *chip_name;
52 char fw_name[30];
53 int err = 0;
54 const struct ta_firmware_header_v1_0 *ta_hdr;
55 DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");
56
57 switch (adev->asic_type) {
1
Control jumps to 'case CHIP_RENOIR:' at line 58
→
58 case CHIP_RENOIR:
59 if (adev->apu_flags & AMD_APU_IS_RENOIR)
2
←
Assuming the condition is false
→
3
←
Taking false branch
→
60 chip_name = "renoir";
61 else
62 chip_name = "green_sardine";
63 break;
4
←
 Execution continues on line 68
→
64 default:
65 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c"
, 65); } while (0);
66 }
67
68 err = psp_init_asd_microcode(psp, chip_name);
69 if (err)
5
←
Assuming 'err' is 0
→
6
←
Taking false branch
→
70 return err;
71
72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
7
←
Calling 'request_firmware'
→
11
←
Returning from 'request_firmware'
→
74 if (err) {
12
←
Assuming 'err' is 0
→
13
←
Taking false branch
→
75 release_firmware(adev->psp.ta_fw);
76 adev->psp.ta_fw = NULL((void *)0);
77 dev_info(adev->dev,do { } while(0)
78 "psp v12.0: Failed to load firmware \"%s\"\n",do { } while(0)
79 fw_name)do { } while(0);
80 } else {
81 err = amdgpu_ucode_validate(adev->psp.ta_fw);
82 if (err)
14
←
Assuming 'err' is 0
→
15
←
Taking false branch
→
83 goto out;
84
85 ta_hdr = (const struct ta_firmware_header_v1_0 *)
86 adev->psp.ta_fw->data;
16
←
Access to field 'data' results in a dereference of a null pointer (loaded from field 'ta_fw')
87 adev->psp.ta_hdcp_ucode_version =
88 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version)((__uint32_t)(ta_hdr->ta_hdcp_ucode_version));
89 adev->psp.ta_hdcp_ucode_size =
90 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes)((__uint32_t)(ta_hdr->ta_hdcp_size_bytes));
91 adev->psp.ta_hdcp_start_addr =
92 (uint8_t *)ta_hdr +
93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ta_hdr->header.ucode_array_offset_bytes));
94
95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version)((__uint32_t)(ta_hdr->header.ucode_version));
96
97 adev->psp.ta_dtm_ucode_version =
98 le32_to_cpu(ta_hdr->ta_dtm_ucode_version)((__uint32_t)(ta_hdr->ta_dtm_ucode_version));
99 adev->psp.ta_dtm_ucode_size =
100 le32_to_cpu(ta_hdr->ta_dtm_size_bytes)((__uint32_t)(ta_hdr->ta_dtm_size_bytes));
101 adev->psp.ta_dtm_start_addr =
102 (uint8_t *)adev->psp.ta_hdcp_start_addr +
103 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes)((__uint32_t)(ta_hdr->ta_dtm_offset_bytes));
104 }
105
106 return 0;
107
108out:
109 release_firmware(adev->psp.ta_fw);
110 adev->psp.ta_fw = NULL((void *)0);
111 if (err) {
112 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "psp v12.0: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
113 "psp v12.0: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "psp v12.0: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
114 fw_name)printf("drm:pid%d:%s *ERROR* " "psp v12.0: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
115 }
116
117 return err;
118}
119
120static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
121{
122 int ret;
123 uint32_t psp_gfxdrv_command_reg = 0;
124 struct amdgpu_device *adev = psp->adev;
125 uint32_t sol_reg;
126
127 /* Check sOS sign of life register to confirm sys driver and sOS
128 * are already been loaded.
129 */
130 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x0091), 0);
131 if (sol_reg)
132 return 0;
133
134 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
135 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35)(adev->reg_offset[MP0_HWIP][0][0] + 0x0063),
136 0x80000000, 0x80000000, false0);
137 if (ret)
138 return ret;
139
140 memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
141
142 /* Copy PSP System Driver binary to memory */
143 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size)__builtin_memcpy((psp->fw_pri_buf), (psp->sys_start_addr
), (psp->sys_bin_size));
144
145 /* Provide the sys driver to bootloader */
146 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0064)), ((uint32_t)(psp->fw_pri_mc_addr >> 20)
), 0)
147 (uint32_t)(psp->fw_pri_mc_addr >> 20))amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0064)), ((uint32_t)(psp->fw_pri_mc_addr >> 20)
), 0);
148 psp_gfxdrv_command_reg = 1 << 16;
149 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0063)), (psp_gfxdrv_command_reg), 0)
150 psp_gfxdrv_command_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0063)), (psp_gfxdrv_command_reg), 0);
151
152 /* there might be handshake issue with hardware which needs delay */
153 mdelay(20);
154
155 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35)(adev->reg_offset[MP0_HWIP][0][0] + 0x0063),
156 0x80000000, 0x80000000, false0);
157
158 return ret;
159}
160
161static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
162{
163 int ret;
164 unsigned int psp_gfxdrv_command_reg = 0;
165 struct amdgpu_device *adev = psp->adev;
166 uint32_t sol_reg;
167
168 /* Check sOS sign of life register to confirm sys driver and sOS
169 * are already been loaded.
170 */
171 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x0091), 0);
172 if (sol_reg)
173 return 0;
174
175 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
176 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35)(adev->reg_offset[MP0_HWIP][0][0] + 0x0063),
177 0x80000000, 0x80000000, false0);
178 if (ret)
179 return ret;
180
181 memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
182
183 /* Copy Secure OS binary to PSP memory */
184 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size)__builtin_memcpy((psp->fw_pri_buf), (psp->sos_start_addr
), (psp->sos_bin_size));
185
186 /* Provide the PSP secure OS to bootloader */
187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0064)), ((uint32_t)(psp->fw_pri_mc_addr >> 20)
), 0)
188 (uint32_t)(psp->fw_pri_mc_addr >> 20))amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0064)), ((uint32_t)(psp->fw_pri_mc_addr >> 20)
), 0);
189 psp_gfxdrv_command_reg = 2 << 16;
190 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0063)), (psp_gfxdrv_command_reg), 0)
191 psp_gfxdrv_command_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0063)), (psp_gfxdrv_command_reg), 0);
192
193 /* there might be handshake issue with hardware which needs delay */
194 mdelay(20);
195 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)(adev->reg_offset[MP0_HWIP][0][0] + 0x0091),
196 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x0091), 0),
197 0, true1);
198
199 return ret;
200}
201
202static void psp_v12_0_reroute_ih(struct psp_context *psp)
203{
204 struct amdgpu_device *adev = psp->adev;
205 uint32_t tmp;
206
207 /* Change IH ring for VMC */
208 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b)(((0) & ~0x0001FFFFL) | (0x0001FFFFL & ((0x1244b) <<
0x0)));
209 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1)(((tmp) & ~0x000C0000L) | (0x000C0000L & ((1) <<
0x12)));
210 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1)(((tmp) & ~0x00300000L) | (0x00300000L & ((1) <<
0x14)));
211
212 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0085)), (3), 0);
213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0086)), (tmp), 0);
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0080)), (GFX_CTRL_CMD_ID_GBR_IH_SET), 0);
215
216 mdelay(20);
217 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)(adev->reg_offset[MP0_HWIP][0][0] + 0x0080),
218 0x80000000, 0x8000FFFF, false0);
219
220 /* Change IH ring for UMC */
221 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b)(((0) & ~0x0001FFFFL) | (0x0001FFFFL & ((0x1216b) <<
0x0)));
222 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1)(((tmp) & ~0x00300000L) | (0x00300000L & ((1) <<
0x14)));
223
224 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0085)), (4), 0);
225 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0086)), (tmp), 0);
226 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0080)), (GFX_CTRL_CMD_ID_GBR_IH_SET), 0);
227
228 mdelay(20);
229 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)(adev->reg_offset[MP0_HWIP][0][0] + 0x0080),
230 0x80000000, 0x8000FFFF, false0);
231}
232
233static int psp_v12_0_ring_init(struct psp_context *psp,
234 enum psp_ring_type ring_type)
235{
236 int ret = 0;
237 struct psp_ring *ring;
238 struct amdgpu_device *adev = psp->adev;
239
240 psp_v12_0_reroute_ih(psp);
241
242 ring = &psp->km_ring;
243
244 ring->ring_type = ring_type;
245
246 /* allocate 4k Page of Local Frame Buffer memory for ring */
247 ring->ring_size = 0x1000;
248 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE(1 << 12),
249 AMDGPU_GEM_DOMAIN_VRAM0x4,
250 &adev->firmware.rbuf,
251 &ring->ring_mem_mc_addr,
252 (void **)&ring->ring_mem);
253 if (ret) {
254 ring->ring_size = 0;
255 return ret;
256 }
257
258 return 0;
259}
260
261static int psp_v12_0_ring_create(struct psp_context *psp,
262 enum psp_ring_type ring_type)
263{
264 int ret = 0;
265 unsigned int psp_ring_reg = 0;
266 struct psp_ring *ring = &psp->km_ring;
267 struct amdgpu_device *adev = psp->adev;
268
269 if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2))) {
270 /* Write low address of the ring to C2PMSG_102 */
271 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr)((u32)(ring->ring_mem_mc_addr));
272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a6)), (psp_ring_reg), 0);
273 /* Write high address of the ring to C2PMSG_103 */
274 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr)((u32)(((ring->ring_mem_mc_addr) >> 16) >> 16)
);
275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a7)), (psp_ring_reg), 0);
276
277 /* Write the ring initialization command to C2PMSG_101 */
278 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a5)), (GFX_CTRL_CMD_ID_INIT_GPCOM_RING), 0)
279 GFX_CTRL_CMD_ID_INIT_GPCOM_RING)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a5)), (GFX_CTRL_CMD_ID_INIT_GPCOM_RING), 0);
280
281 /* there might be handshake issue with hardware which needs delay */
282 mdelay(20);
283
284 /* Wait for response flag (bit 31) in C2PMSG_101 */
285 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101)(adev->reg_offset[MP0_HWIP][0][0] + 0x00a5),
286 0x80000000, 0x8000FFFF, false0);
287
288 } else {
289 /* Write low address of the ring to C2PMSG_69 */
290 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr)((u32)(ring->ring_mem_mc_addr));
291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0085)), (psp_ring_reg), 0);
292 /* Write high address of the ring to C2PMSG_70 */
293 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr)((u32)(((ring->ring_mem_mc_addr) >> 16) >> 16)
);
294 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0086)), (psp_ring_reg), 0);
295 /* Write size of ring to C2PMSG_71 */
296 psp_ring_reg = ring->ring_size;
297 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0087)), (psp_ring_reg), 0);
298 /* Write the ring initialization command to C2PMSG_64 */
299 psp_ring_reg = ring_type;
300 psp_ring_reg = psp_ring_reg << 16;
301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0080)), (psp_ring_reg), 0);
302
303 /* there might be handshake issue with hardware which needs delay */
304 mdelay(20);
305
306 /* Wait for response flag (bit 31) in C2PMSG_64 */
307 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)(adev->reg_offset[MP0_HWIP][0][0] + 0x0080),
308 0x80000000, 0x8000FFFF, false0);
309 }
310
311 return ret;
312}
313
314static int psp_v12_0_ring_stop(struct psp_context *psp,
315 enum psp_ring_type ring_type)
316{
317 int ret = 0;
318 struct amdgpu_device *adev = psp->adev;
319
320 /* Write the ring destroy command*/
321 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
322 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a5)), (GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING), 0)
323 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a5)), (GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING), 0);
324 else
325 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0080)), (GFX_CTRL_CMD_ID_DESTROY_RINGS), 0)
326 GFX_CTRL_CMD_ID_DESTROY_RINGS)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0080)), (GFX_CTRL_CMD_ID_DESTROY_RINGS), 0);
327
328 /* there might be handshake issue with hardware which needs delay */
329 mdelay(20);
330
331 /* Wait for response flag (bit 31) */
332 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
333 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101)(adev->reg_offset[MP0_HWIP][0][0] + 0x00a5),
334 0x80000000, 0x80000000, false0);
335 else
336 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)(adev->reg_offset[MP0_HWIP][0][0] + 0x0080),
337 0x80000000, 0x80000000, false0);
338
339 return ret;
340}
341
342static int psp_v12_0_ring_destroy(struct psp_context *psp,
343 enum psp_ring_type ring_type)
344{
345 int ret = 0;
346 struct psp_ring *ring = &psp->km_ring;
347 struct amdgpu_device *adev = psp->adev;
348
349 ret = psp_v12_0_ring_stop(psp, ring_type);
350 if (ret)
351 DRM_ERROR("Fail to stop psp ring\n")__drm_err("Fail to stop psp ring\n");
352
353 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
354 &ring->ring_mem_mc_addr,
355 (void **)&ring->ring_mem);
356
357 return ret;
358}
359
360static int psp_v12_0_mode1_reset(struct psp_context *psp)
361{
362 int ret;
363 uint32_t offset;
364 struct amdgpu_device *adev = psp->adev;
365
366 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)(adev->reg_offset[MP0_HWIP][0][0] + 0x0080);
367
368 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false0);
369
370 if (ret) {
371 DRM_INFO("psp is not working correctly before mode1 reset!\n")printk("\0016" "[" "drm" "] " "psp is not working correctly before mode1 reset!\n"
);
372 return -EINVAL22;
373 }
374
375 /*send the mode 1 reset command*/
376 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST)amdgpu_device_wreg(adev, (offset), (GFX_CTRL_CMD_ID_MODE1_RST
), 0);
377
378 drm_msleep(500)mdelay(500);
379
380 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33)(adev->reg_offset[MP0_HWIP][0][0] + 0x0061);
381
382 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false0);
383
384 if (ret) {
385 DRM_INFO("psp mode 1 reset failed!\n")printk("\0016" "[" "drm" "] " "psp mode 1 reset failed!\n");
386 return -EINVAL22;
387 }
388
389 DRM_INFO("psp mode1 reset succeed \n")printk("\0016" "[" "drm" "] " "psp mode1 reset succeed \n");
390
391 return 0;
392}
393
394static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
395{
396 uint32_t data;
397 struct amdgpu_device *adev = psp->adev;
398
399 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
400 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x00a6), 0);
401 else
402 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x0083), 0);
403
404 return data;
405}
406
407static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
408{
409 struct amdgpu_device *adev = psp->adev;
410
411 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a6)), (value), 0);
413 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x00a5)), (GFX_CTRL_CMD_ID_CONSUME_CMD), 0);
414 } else
415 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value)amdgpu_device_wreg(adev, ((adev->reg_offset[MP0_HWIP][0][0
] + 0x0083)), (value), 0);
416}
417
418static const struct psp_funcs psp_v12_0_funcs = {
419 .init_microcode = psp_v12_0_init_microcode,
420 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
421 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
422 .ring_init = psp_v12_0_ring_init,
423 .ring_create = psp_v12_0_ring_create,
424 .ring_stop = psp_v12_0_ring_stop,
425 .ring_destroy = psp_v12_0_ring_destroy,
426 .mode1_reset = psp_v12_0_mode1_reset,
427 .ring_get_wptr = psp_v12_0_ring_get_wptr,
428 .ring_set_wptr = psp_v12_0_ring_set_wptr,
429};
430
431void psp_v12_0_set_psp_funcs(struct psp_context *psp)
432{
433 psp->funcs = &psp_v12_0_funcs;
434}
←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var)) ((type)(__uintptr_t)(const void *)(var))
14#endif
15
16struct firmware {
17 size_t size;
18 const u8 *data;
19};
20
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23 struct device *device)
24{
25 int r;
26 struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27 M_WAITOK0x0001 | M_ZERO0x0008);
28 r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29 if (r != 0) {
8
←
Assuming 'r' is not equal to 0
→
9
←
Taking true branch
→
30 free(f, M_DRM145, sizeof(struct firmware));
31 *fw = NULL((void *)0);
10
←
Null pointer value stored to field 'ta_fw'
→
32 return -r;
33 } else {
34 *fw = f;
35 return 0;
36 }
37}
38
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41 struct device *device)
42{
43 return request_firmware(fw, name, device);
44}
45
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47
48static inline void
49release_firmware(const struct firmware *fw)
50{
51 if (fw)
52 free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53 free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55
56#endif