Bug Summary

File:dev/pci/igc_phy.c
Warning:line 564, column 6
Branch condition evaluates to a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name igc_phy.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/igc_phy.c
1/* $OpenBSD: igc_phy.c,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
2/*-
3 * Copyright 2021 Intel Corp
4 * Copyright 2021 Rubicon Communications, LLC (Netgate)
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <dev/pci/igc_api.h>
9
10/**
11 * igc_init_phy_ops_generic - Initialize PHY function pointers
12 * @hw: pointer to the HW structure
13 *
14 * Setups up the function pointers to no-op functions
15 **/
16void
17igc_init_phy_ops_generic(struct igc_hw *hw)
18{
19 struct igc_phy_info *phy = &hw->phy;
20 DEBUGFUNC("igc_init_phy_ops_generic")do { if (0) printf("igc_init_phy_ops_generic" "\n"); } while (
0);
21
22 /* Initialize function pointers */
23 phy->ops.init_params = igc_null_ops_generic;
24 phy->ops.acquire = igc_null_ops_generic;
25 phy->ops.check_reset_block = igc_null_ops_generic;
26 phy->ops.commit = igc_null_ops_generic;
27 phy->ops.force_speed_duplex = igc_null_ops_generic;
28 phy->ops.get_info = igc_null_ops_generic;
29 phy->ops.set_page = igc_null_set_page;
30 phy->ops.read_reg = igc_null_read_reg;
31 phy->ops.read_reg_locked = igc_null_read_reg;
32 phy->ops.read_reg_page = igc_null_read_reg;
33 phy->ops.release = igc_null_phy_generic;
34 phy->ops.reset = igc_null_ops_generic;
35 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
36 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
37 phy->ops.write_reg = igc_null_write_reg;
38 phy->ops.write_reg_locked = igc_null_write_reg;
39 phy->ops.write_reg_page = igc_null_write_reg;
40 phy->ops.power_up = igc_null_phy_generic;
41 phy->ops.power_down = igc_null_phy_generic;
42}
43
44/**
45 * igc_null_set_page - No-op function, return 0
46 * @hw: pointer to the HW structure
47 * @data: dummy variable
48 **/
49int
50igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, uint16_t IGC_UNUSEDARG data)
51{
52 DEBUGFUNC("igc_null_set_page")do { if (0) printf("igc_null_set_page" "\n"); } while (0);
53 return IGC_SUCCESS0;
54}
55
56/**
57 * igc_null_read_reg - No-op function, return 0
58 * @hw: pointer to the HW structure
59 * @offset: dummy variable
60 * @data: dummy variable
61 **/
62int
63igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
64 uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG *data)
65{
66 DEBUGFUNC("igc_null_read_reg")do { if (0) printf("igc_null_read_reg" "\n"); } while (0);
67 return IGC_SUCCESS0;
68}
69
70/**
71 * igc_null_phy_generic - No-op function, return void
72 * @hw: pointer to the HW structure
73 **/
74void
75igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
76{
77 DEBUGFUNC("igc_null_phy_generic")do { if (0) printf("igc_null_phy_generic" "\n"); } while (0);
78 return;
79}
80
81/**
82 * igc_null_lplu_state - No-op function, return 0
83 * @hw: pointer to the HW structure
84 * @active: dummy variable
85 **/
86int
87igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, bool_Bool IGC_UNUSEDARG active)
88{
89 DEBUGFUNC("igc_null_lplu_state")do { if (0) printf("igc_null_lplu_state" "\n"); } while (0);
90 return IGC_SUCCESS0;
91}
92
93/**
94 * igc_null_write_reg - No-op function, return 0
95 * @hw: pointer to the HW structure
96 * @offset: dummy variable
97 * @data: dummy variable
98 **/
99int
100igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
101 uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG data)
102{
103 DEBUGFUNC("igc_null_write_reg")do { if (0) printf("igc_null_write_reg" "\n"); } while (0);
104 return IGC_SUCCESS0;
105}
106
107/**
108 * igc_check_reset_block_generic - Check if PHY reset is blocked
109 * @hw: pointer to the HW structure
110 *
111 * Read the PHY management control register and check whether a PHY reset
112 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
113 * return IGC_BLK_PHY_RESET (12).
114 **/
115int
116igc_check_reset_block_generic(struct igc_hw *hw)
117{
118 uint32_t manc;
119
120 DEBUGFUNC("igc_check_reset_block")do { if (0) printf("igc_check_reset_block" "\n"); } while (0);
121
122 manc = IGC_READ_REG(hw, IGC_MANC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05820)
));
123
124 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE0x00040000) ?
125 IGC_BLK_PHY_RESET12 : IGC_SUCCESS0;
126}
127
128/**
129 * igc_get_phy_id - Retrieve the PHY ID and revision
130 * @hw: pointer to the HW structure
131 *
132 * Reads the PHY registers and stores the PHY ID and possibly the PHY
133 * revision in the hardware structure.
134 **/
135int
136igc_get_phy_id(struct igc_hw *hw)
137{
138 struct igc_phy_info *phy = &hw->phy;
139 uint16_t phy_id;
140 int ret_val = IGC_SUCCESS0;
141
142 DEBUGFUNC("igc_get_phy_id")do { if (0) printf("igc_get_phy_id" "\n"); } while (0);
143
144 if (!phy->ops.read_reg)
145 return IGC_SUCCESS0;
146
147 ret_val = phy->ops.read_reg(hw, PHY_ID10x02, &phy_id);
148 if (ret_val)
149 return ret_val;
150
151 phy->id = (uint32_t)(phy_id << 16);
152 DELAY(20)(*delay_func)(20);
153 ret_val = phy->ops.read_reg(hw, PHY_ID20x03, &phy_id);
154 if (ret_val)
155 return ret_val;
156
157 phy->id |= (uint32_t)(phy_id & PHY_REVISION_MASK0xFFFFFFF0);
158 phy->revision = (uint32_t)(phy_id & ~PHY_REVISION_MASK0xFFFFFFF0);
159
160
161 return IGC_SUCCESS0;
162}
163
164/**
165 * igc_read_phy_reg_mdic - Read MDI control register
166 * @hw: pointer to the HW structure
167 * @offset: register offset to be read
168 * @data: pointer to the read data
169 *
170 * Reads the MDI control register in the PHY at offset and stores the
171 * information read to data.
172 **/
173int
174igc_read_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t *data)
175{
176 struct igc_phy_info *phy = &hw->phy;
177 uint32_t i, mdic = 0;
178
179 DEBUGFUNC("igc_read_phy_reg_mdic")do { if (0) printf("igc_read_phy_reg_mdic" "\n"); } while (0);
180
181 if (offset > MAX_PHY_REG_ADDRESS0x1F) {
182 DEBUGOUT1("PHY Address %d is out of range\n", offset)do { if (0) printf("PHY Address %d is out of range\n", offset
); } while (0);
183 return -IGC_ERR_PARAM4;
184 }
185
186 /* Set up Op-code, Phy Address, and register offset in the MDI
187 * Control register. The MAC will take care of interfacing with the
188 * PHY to retrieve the desired data.
189 */
190 mdic = ((offset << IGC_MDIC_REG_SHIFT16) |
191 (phy->addr << IGC_MDIC_PHY_SHIFT21) | (IGC_MDIC_OP_READ0x08000000));
192
193 IGC_WRITE_REG(hw, IGC_MDIC, mdic)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00020)
, (mdic)));
194
195 /* Poll the ready bit to see if the MDI read completed
196 * Increasing the time out as testing showed failures with
197 * the lower time out
198 */
199 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT640 * 3); i++) {
200 DELAY(50)(*delay_func)(50);
201 mdic = IGC_READ_REG(hw, IGC_MDIC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00020)
));
202 if (mdic & IGC_MDIC_READY0x10000000)
203 break;
204 }
205 if (!(mdic & IGC_MDIC_READY0x10000000)) {
206 DEBUGOUT("MDI Read did not complete\n")do { if (0) printf("MDI Read did not complete\n"); } while (0
);
207 return -IGC_ERR_PHY2;
208 }
209 if (mdic & IGC_MDIC_ERROR0x40000000) {
210 DEBUGOUT("MDI Error\n")do { if (0) printf("MDI Error\n"); } while (0);
211 return -IGC_ERR_PHY2;
212 }
213 if (((mdic & IGC_MDIC_REG_MASK0x001F0000) >> IGC_MDIC_REG_SHIFT16) != offset) {
214 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",do { if (0) printf("MDI Read offset error - requested %d, returned %d\n"
, offset, (mdic & 0x001F0000) >> 16); } while (0)
215 offset, (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT)do { if (0) printf("MDI Read offset error - requested %d, returned %d\n"
, offset, (mdic & 0x001F0000) >> 16); } while (0);
216 return -IGC_ERR_PHY2;
217 }
218 *data = (uint16_t)mdic;
219
220 return IGC_SUCCESS0;
221}
222
223/**
224 * igc_write_phy_reg_mdic - Write MDI control register
225 * @hw: pointer to the HW structure
226 * @offset: register offset to write to
227 * @data: data to write to register at offset
228 *
229 * Writes data to MDI control register in the PHY at offset.
230 **/
231int
232igc_write_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t data)
233{
234 struct igc_phy_info *phy = &hw->phy;
235 uint32_t i, mdic = 0;
236
237 DEBUGFUNC("igc_write_phy_reg_mdic")do { if (0) printf("igc_write_phy_reg_mdic" "\n"); } while (0
);
238
239 if (offset > MAX_PHY_REG_ADDRESS0x1F) {
240 DEBUGOUT1("PHY Address %d is out of range\n", offset)do { if (0) printf("PHY Address %d is out of range\n", offset
); } while (0);
241 return -IGC_ERR_PARAM4;
242 }
243
244 /* Set up Op-code, Phy Address, and register offset in the MDI
245 * Control register. The MAC will take care of interfacing with the
246 * PHY to retrieve the desired data.
247 */
248 mdic = (((uint32_t)data) | (offset << IGC_MDIC_REG_SHIFT16) |
249 (phy->addr << IGC_MDIC_PHY_SHIFT21) | (IGC_MDIC_OP_WRITE0x04000000));
250
251 IGC_WRITE_REG(hw, IGC_MDIC, mdic)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00020)
, (mdic)));
252
253 /* Poll the ready bit to see if the MDI read completed
254 * Increasing the time out as testing showed failures with
255 * the lower time out
256 */
257 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT640 * 3); i++) {
258 DELAY(50)(*delay_func)(50);
259 mdic = IGC_READ_REG(hw, IGC_MDIC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00020)
));
260 if (mdic & IGC_MDIC_READY0x10000000)
261 break;
262 }
263 if (!(mdic & IGC_MDIC_READY0x10000000)) {
264 DEBUGOUT("MDI Write did not complete\n")do { if (0) printf("MDI Write did not complete\n"); } while (
0);
265 return -IGC_ERR_PHY2;
266 }
267 if (mdic & IGC_MDIC_ERROR0x40000000) {
268 DEBUGOUT("MDI Error\n")do { if (0) printf("MDI Error\n"); } while (0);
269 return -IGC_ERR_PHY2;
270 }
271 if (((mdic & IGC_MDIC_REG_MASK0x001F0000) >> IGC_MDIC_REG_SHIFT16) != offset)
272 return -IGC_ERR_PHY2;
273
274 return IGC_SUCCESS0;
275}
276
277/**
278 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
279 * @hw: pointer to the HW structure
280 *
281 * Reads the MII auto-neg advertisement register and/or the 1000T control
282 * register and if the PHY is already setup for auto-negotiation, then
283 * return successful. Otherwise, setup advertisement and flow control to
284 * the appropriate values for the wanted auto-negotiation.
285 **/
286int
287igc_phy_setup_autoneg(struct igc_hw *hw)
288{
289 struct igc_phy_info *phy = &hw->phy;
290 uint16_t mii_autoneg_adv_reg;
291 uint16_t mii_1000t_ctrl_reg = 0;
292 uint16_t aneg_multigbt_an_ctrl = 0;
293 int ret_val;
294
295 DEBUGFUNC("igc_phy_setup_autoneg")do { if (0) printf("igc_phy_setup_autoneg" "\n"); } while (0);
296
297 phy->autoneg_advertised &= phy->autoneg_mask;
298
299 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
300 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV0x04, &mii_autoneg_adv_reg);
301 if (ret_val)
302 return ret_val;
303
304 if (phy->autoneg_mask & ADVERTISE_1000_FULL0x0020) {
305 /* Read the MII 1000Base-T Control Register (Address 9). */
306 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL0x09,
307 &mii_1000t_ctrl_reg);
308 if (ret_val)
309 return ret_val;
310 }
311
312 if ((phy->autoneg_mask & ADVERTISE_2500_FULL0x0080) &&
313 hw->phy.id == I225_I_PHY_ID0x67C9DC00) {
314 /* Read the MULTI GBT AN Control Register - reg 7.32 */
315 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK0x0007 <<
316 MMD_DEVADDR_SHIFT16) | ANEG_MULTIGBT_AN_CTRL0x0020,
317 &aneg_multigbt_an_ctrl);
318 if (ret_val)
319 return ret_val;
320 }
321
322 /* Need to parse both autoneg_advertised and fc and set up
323 * the appropriate PHY registers. First we will parse for
324 * autoneg_advertised software override. Since we can advertise
325 * a plethora of combinations, we need to check each bit
326 * individually.
327 */
328
329 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
330 * Advertisement Register (Address 4) and the 1000 mb speed bits in
331 * the 1000Base-T Control Register (Address 9).
332 */
333 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS0x0100 | NWAY_AR_100TX_HD_CAPS0x0080 |
334 NWAY_AR_10T_FD_CAPS0x0040 | NWAY_AR_10T_HD_CAPS0x0020);
335 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS0x0100 | CR_1000T_FD_CAPS0x0200);
336
337 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised)do { if (0) printf("autoneg_advertised %x\n", phy->autoneg_advertised
); } while (0);
338
339 /* Do we want to advertise 10 Mb Half Duplex? */
340 if (phy->autoneg_advertised & ADVERTISE_10_HALF0x0001) {
341 DEBUGOUT("Advertise 10mb Half duplex\n")do { if (0) printf("Advertise 10mb Half duplex\n"); } while (
0);
342 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS0x0020;
343 }
344
345 /* Do we want to advertise 10 Mb Full Duplex? */
346 if (phy->autoneg_advertised & ADVERTISE_10_FULL0x0002) {
347 DEBUGOUT("Advertise 10mb Full duplex\n")do { if (0) printf("Advertise 10mb Full duplex\n"); } while (
0);
348 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS0x0040;
349 }
350
351 /* Do we want to advertise 100 Mb Half Duplex? */
352 if (phy->autoneg_advertised & ADVERTISE_100_HALF0x0004) {
353 DEBUGOUT("Advertise 100mb Half duplex\n")do { if (0) printf("Advertise 100mb Half duplex\n"); } while (
0);
354 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS0x0080;
355 }
356
357 /* Do we want to advertise 100 Mb Full Duplex? */
358 if (phy->autoneg_advertised & ADVERTISE_100_FULL0x0008) {
359 DEBUGOUT("Advertise 100mb Full duplex\n")do { if (0) printf("Advertise 100mb Full duplex\n"); } while (
0);
360 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS0x0100;
361 }
362
363 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
364 if (phy->autoneg_advertised & ADVERTISE_1000_HALF0x0010)
365 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n")do { if (0) printf("Advertise 1000mb Half duplex request denied!\n"
); } while (0);
366
367 /* Do we want to advertise 1000 Mb Full Duplex? */
368 if (phy->autoneg_advertised & ADVERTISE_1000_FULL0x0020) {
369 DEBUGOUT("Advertise 1000mb Full duplex\n")do { if (0) printf("Advertise 1000mb Full duplex\n"); } while
(0);
370 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS0x0200;
371 }
372
373 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
374 if (phy->autoneg_advertised & ADVERTISE_2500_HALF0x0040)
375 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n")do { if (0) printf("Advertise 2500mb Half duplex request denied!\n"
); } while (0);
376
377 /* Do we want to advertise 2500 Mb Full Duplex? */
378 if (phy->autoneg_advertised & ADVERTISE_2500_FULL0x0080) {
379 DEBUGOUT("Advertise 2500mb Full duplex\n")do { if (0) printf("Advertise 2500mb Full duplex\n"); } while
(0);
380 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS0x0080;
381 } else
382 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS0x0080;
383
384 /* Check for a software override of the flow control settings, and
385 * setup the PHY advertisement registers accordingly. If
386 * auto-negotiation is enabled, then software will have to set the
387 * "PAUSE" bits to the correct value in the Auto-Negotiation
388 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
389 * negotiation.
390 *
391 * The possible values of the "fc" parameter are:
392 * 0: Flow control is completely disabled
393 * 1: Rx flow control is enabled (we can receive pause frames
394 * but not send pause frames).
395 * 2: Tx flow control is enabled (we can send pause frames
396 * but we do not support receiving pause frames).
397 * 3: Both Rx and Tx flow control (symmetric) are enabled.
398 * other: No software override. The flow control configuration
399 * in the EEPROM is used.
400 */
401 switch (hw->fc.current_mode) {
402 case igc_fc_none:
403 /* Flow control (Rx & Tx) is completely disabled by a
404 * software over-ride.
405 */
406 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
407 break;
408 case igc_fc_rx_pause:
409 /* Rx Flow control is enabled, and Tx Flow control is
410 * disabled, by a software over-ride.
411 *
412 * Since there really isn't a way to advertise that we are
413 * capable of Rx Pause ONLY, we will advertise that we
414 * support both symmetric and asymmetric Rx PAUSE. Later
415 * (in igc_config_fc_after_link_up) we will disable the
416 * hw's ability to send PAUSE frames.
417 */
418 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
419 break;
420 case igc_fc_tx_pause:
421 /* Tx Flow control is enabled, and Rx Flow control is
422 * disabled, by a software over-ride.
423 */
424 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR0x0800;
425 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE0x0400;
426 break;
427 case igc_fc_full:
428 /* Flow control (both Rx and Tx) is enabled by a software
429 * over-ride.
430 */
431 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
432 break;
433 default:
434 DEBUGOUT("Flow control param set incorrectly\n")do { if (0) printf("Flow control param set incorrectly\n"); }
while (0);
435 return -IGC_ERR_CONFIG3;
436 }
437
438 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV0x04, mii_autoneg_adv_reg);
439 if (ret_val)
440 return ret_val;
441
442 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg)do { if (0) printf("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
); } while (0);
443
444 if (phy->autoneg_mask & ADVERTISE_1000_FULL0x0020)
445 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL0x09,
446 mii_1000t_ctrl_reg);
447
448 if ((phy->autoneg_mask & ADVERTISE_2500_FULL0x0080) &&
449 hw->phy.id == I225_I_PHY_ID0x67C9DC00)
450 ret_val = phy->ops.write_reg(hw,
451 (STANDARD_AN_REG_MASK0x0007 << MMD_DEVADDR_SHIFT16) |
452 ANEG_MULTIGBT_AN_CTRL0x0020, aneg_multigbt_an_ctrl);
453
454 return ret_val;
455}
456
457/**
458 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
459 * @hw: pointer to the HW structure
460 *
461 * Performs initial bounds checking on autoneg advertisement parameter, then
462 * configure to advertise the full capability. Setup the PHY to autoneg
463 * and restart the negotiation process between the link partner. If
464 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
465 **/
466int
467igc_copper_link_autoneg(struct igc_hw *hw)
468{
469 struct igc_phy_info *phy = &hw->phy;
470 uint16_t phy_ctrl;
471 int ret_val;
472
473 DEBUGFUNC("igc_copper_link_autoneg")do { if (0) printf("igc_copper_link_autoneg" "\n"); } while (
0);
474
475 /* Perform some bounds checking on the autoneg advertisement
476 * parameter.
477 */
478 phy->autoneg_advertised &= phy->autoneg_mask;
479
480 /* If autoneg_advertised is zero, we assume it was not defaulted
481 * by the calling code so we set to advertise full capability.
482 */
483 if (!phy->autoneg_advertised)
484 phy->autoneg_advertised = phy->autoneg_mask;
485
486 DEBUGOUT("Reconfiguring auto-neg advertisement params\n")do { if (0) printf("Reconfiguring auto-neg advertisement params\n"
); } while (0);
487 ret_val = igc_phy_setup_autoneg(hw);
488 if (ret_val) {
489 DEBUGOUT("Error Setting up Auto-Negotiation\n")do { if (0) printf("Error Setting up Auto-Negotiation\n"); } while
(0);
490 return ret_val;
491 }
492 DEBUGOUT("Restarting Auto-Neg\n")do { if (0) printf("Restarting Auto-Neg\n"); } while (0);
493
494 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
495 * the Auto Neg Restart bit in the PHY control register.
496 */
497 ret_val = phy->ops.read_reg(hw, PHY_CONTROL0x00, &phy_ctrl);
498 if (ret_val)
499 return ret_val;
500
501 phy_ctrl |= (MII_CR_AUTO_NEG_EN0x1000 | MII_CR_RESTART_AUTO_NEG0x0200);
502 ret_val = phy->ops.write_reg(hw, PHY_CONTROL0x00, phy_ctrl);
503 if (ret_val)
504 return ret_val;
505
506 /* Does the user want to wait for Auto-Neg to complete here, or
507 * check at a later time (for example, callback routine).
508 */
509 if (phy->autoneg_wait_to_complete) {
510 ret_val = igc_wait_autoneg(hw);
511 if (ret_val)
512 return ret_val;
513 }
514
515 hw->mac.get_link_status = true1;
516
517 return ret_val;
518}
519
520/**
521 * igc_setup_copper_link_generic - Configure copper link settings
522 * @hw: pointer to the HW structure
523 *
524 * Calls the appropriate function to configure the link for auto-neg or forced
525 * speed and duplex. Then we check for link, once link is established calls
526 * to configure collision distance and flow control are called. If link is
527 * not established, we return -IGC_ERR_PHY (-2).
528 **/
529int
530igc_setup_copper_link_generic(struct igc_hw *hw)
531{
532 int ret_val;
533 bool_Bool link;
1
'link' declared without an initial value
→
534
535 DEBUGFUNC("igc_setup_copper_link_generic")do { if (0) printf("igc_setup_copper_link_generic" "\n"); } while
(0);
2
←
Taking false branch
→
3
←
Loop condition is false. Exiting loop
→
536
537 if (hw->mac.autoneg) {
4
←
Assuming field 'autoneg' is false
→
5
←
Taking false branch
→
538 /* Setup autoneg and flow control advertisement and perform
539 * autonegotiation.
540 */
541 ret_val = igc_copper_link_autoneg(hw);
542 if (ret_val)
543 return ret_val;
544 } else {
545 /* PHY will be set to 10H, 10F, 100H or 100F
546 * depending on user settings.
547 */
548 DEBUGOUT("Forcing Speed and Duplex\n")do { if (0) printf("Forcing Speed and Duplex\n"); } while (0);
6
←
Taking false branch
→
7
←
Loop condition is false. Exiting loop
→
549 ret_val = hw->phy.ops.force_speed_duplex(hw);
550 if (ret_val) {
8
←
Assuming 'ret_val' is 0
→
9
←
Taking false branch
→
551 DEBUGOUT("Error Forcing Speed and Duplex\n")do { if (0) printf("Error Forcing Speed and Duplex\n"); } while
(0);
552 return ret_val;
553 }
554 }
555
556 /* Check link status. Wait up to 100 microseconds for link to become
557 * valid.
558 */
559 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT10, 10,
10
←
Calling 'igc_phy_has_link_generic'
→
17
←
Returning from 'igc_phy_has_link_generic'
→
560 &link);
561 if (ret_val
17.1
'ret_val' is 0
)
18
←
Taking false branch
→
562 return ret_val;
563
564 if (link) {
19
←
Branch condition evaluates to a garbage value
565 DEBUGOUT("Valid link established!!!\n")do { if (0) printf("Valid link established!!!\n"); } while (0
);
566 hw->mac.ops.config_collision_dist(hw);
567 ret_val = igc_config_fc_after_link_up_generic(hw);
568 } else
569 DEBUGOUT("Unable to establish link!!!\n")do { if (0) printf("Unable to establish link!!!\n"); } while (
0);
570
571 return ret_val;
572}
573
574/**
575 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
576 * @hw: pointer to the HW structure
577 *
578 * Success returns 0, Failure returns 1
579 *
580 * A downshift is detected by querying the PHY link health.
581 **/
582int
583igc_check_downshift_generic(struct igc_hw *hw)
584{
585 struct igc_phy_info *phy = &hw->phy;
586 int ret_val;
587
588 DEBUGFUNC("igc_check_downshift_generic")do { if (0) printf("igc_check_downshift_generic" "\n"); } while
(0);
589
590 switch (phy->type) {
591 case igc_phy_i225:
592 default:
593 /* speed downshift not supported */
594 phy->speed_downgraded = false0;
595 return IGC_SUCCESS0;
596 }
597
598 return ret_val;
599}
600
601/**
602 * igc_wait_autoneg - Wait for auto-neg completion
603 * @hw: pointer to the HW structure
604 *
605 * Waits for auto-negotiation to complete or for the auto-negotiation time
606 * limit to expire, which ever happens first.
607 **/
608int
609igc_wait_autoneg(struct igc_hw *hw)
610{
611 uint16_t i, phy_status;
612 int ret_val = IGC_SUCCESS0;
613
614 DEBUGFUNC("igc_wait_autoneg")do { if (0) printf("igc_wait_autoneg" "\n"); } while (0);
615
616 if (!hw->phy.ops.read_reg)
617 return IGC_SUCCESS0;
618
619 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
620 for (i = PHY_AUTO_NEG_LIMIT45; i > 0; i--) {
621 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS0x01, &phy_status);
622 if (ret_val)
623 break;
624 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS0x01, &phy_status);
625 if (ret_val)
626 break;
627 if (phy_status & MII_SR_AUTONEG_COMPLETE0x0020)
628 break;
629 msec_delay(100)(*delay_func)(1000 * (100));
630 }
631
632 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
633 * has completed.
634 */
635 return ret_val;
636}
637
638/**
639 * igc_phy_has_link_generic - Polls PHY for link
640 * @hw: pointer to the HW structure
641 * @iterations: number of times to poll for link
642 * @usec_interval: delay between polling attempts
643 * @success: pointer to whether polling was successful or not
644 *
645 * Polls the PHY status register for link, 'iterations' number of times.
646 **/
647int
648igc_phy_has_link_generic(struct igc_hw *hw, uint32_t iterations,
649 uint32_t usec_interval, bool_Bool *success)
650{
651 uint16_t i, phy_status;
652 int ret_val = IGC_SUCCESS0;
653
654 DEBUGFUNC("igc_phy_has_link_generic")do { if (0) printf("igc_phy_has_link_generic" "\n"); } while (
0);
11
←
Taking false branch
→
12
←
Loop condition is false. Exiting loop
→
655
656 if (!hw->phy.ops.read_reg)
13
←
Assuming field 'read_reg' is null, which participates in a condition later
→
14
←
Taking true branch
→
657 return IGC_SUCCESS0;
15
←
Returning without writing to '*success'
→
16
←
Returning zero, which participates in a condition later
→
658
659 for (i = 0; i < iterations; i++) {
660 /* Some PHYs require the PHY_STATUS register to be read
661 * twice due to the link bit being sticky. No harm doing
662 * it across the board.
663 */
664 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS0x01, &phy_status);
665 if (ret_val) {
666 /* If the first read fails, another entity may have
667 * ownership of the resources, wait and try again to
668 * see if they have relinquished the resources yet.
669 */
670 if (usec_interval >= 1000)
671 msec_delay(usec_interval/1000)(*delay_func)(1000 * (usec_interval/1000));
672 else
673 DELAY(usec_interval)(*delay_func)(usec_interval);
674 }
675 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS0x01, &phy_status);
676 if (ret_val)
677 break;
678 if (phy_status & MII_SR_LINK_STATUS0x0004)
679 break;
680 if (usec_interval >= 1000)
681 msec_delay(usec_interval/1000)(*delay_func)(1000 * (usec_interval/1000));
682 else
683 DELAY(usec_interval)(*delay_func)(usec_interval);
684 }
685
686 *success = (i < iterations);
687
688 return ret_val;
689}
690
691/**
692 * igc_phy_sw_reset_generic - PHY software reset
693 * @hw: pointer to the HW structure
694 *
695 * Does a software reset of the PHY by reading the PHY control register and
696 * setting/write the control register reset bit to the PHY.
697 **/
698int
699igc_phy_sw_reset_generic(struct igc_hw *hw)
700{
701 uint16_t phy_ctrl;
702 int ret_val;
703
704 DEBUGFUNC("igc_phy_sw_reset_generic")do { if (0) printf("igc_phy_sw_reset_generic" "\n"); } while (
0);
705
706 if (!hw->phy.ops.read_reg)
707 return IGC_SUCCESS0;
708
709 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL0x00, &phy_ctrl);
710 if (ret_val)
711 return ret_val;
712
713 phy_ctrl |= MII_CR_RESET0x8000;
714 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL0x00, phy_ctrl);
715 if (ret_val)
716 return ret_val;
717
718 DELAY(1)(*delay_func)(1);
719
720 return ret_val;
721}
722
723/**
724 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
725 * @hw: pointer to the HW structure
726 *
727 * In the case of a PHY power down to save power, or to turn off link during a
728 * driver unload, or wake on lan is not enabled, restore the link to previous
729 * settings.
730 **/
731void
732igc_power_up_phy_copper(struct igc_hw *hw)
733{
734 uint16_t mii_reg = 0;
735
736 /* The PHY will retain its settings across a power down/up cycle */
737 hw->phy.ops.read_reg(hw, PHY_CONTROL0x00, &mii_reg);
738 mii_reg &= ~MII_CR_POWER_DOWN0x0800;
739 hw->phy.ops.write_reg(hw, PHY_CONTROL0x00, mii_reg);
740 DELAY(300)(*delay_func)(300);
741}
742
743/**
744 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
745 * @hw: pointer to the HW structure
746 *
747 * In the case of a PHY power down to save power, or to turn off link during a
748 * driver unload, or wake on lan is not enabled, restore the link to previous
749 * settings.
750 **/
751void
752igc_power_down_phy_copper(struct igc_hw *hw)
753{
754 uint16_t mii_reg = 0;
755
756 /* The PHY will retain its settings across a power down/up cycle */
757 hw->phy.ops.read_reg(hw, PHY_CONTROL0x00, &mii_reg);
758 mii_reg |= MII_CR_POWER_DOWN0x0800;
759 hw->phy.ops.write_reg(hw, PHY_CONTROL0x00, mii_reg);
760 msec_delay(1)(*delay_func)(1000 * (1));
761}
762
763/**
764 * igc_write_phy_reg_gpy - Write GPY PHY register
765 * @hw: pointer to the HW structure
766 * @offset: register offset to write to
767 * @data: data to write at register offset
768 *
769 * Acquires semaphore, if necessary, then writes the data to PHY register
770 * at the offset. Release any acquired semaphores before exiting.
771 **/
772int
773igc_write_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t data)
774{
775 uint8_t dev_addr = (offset & GPY_MMD_MASK0xFFFF0000) >> GPY_MMD_SHIFT16;
776 int ret_val;
777
778 DEBUGFUNC("igc_write_phy_reg_gpy")do { if (0) printf("igc_write_phy_reg_gpy" "\n"); } while (0);
779
780 offset = offset & GPY_REG_MASK0x0000FFFF;
781
782 if (!dev_addr) {
783 ret_val = hw->phy.ops.acquire(hw);
784 if (ret_val)
785 return ret_val;
786 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
787 if (ret_val)
788 return ret_val;
789 hw->phy.ops.release(hw);
790 } else {
791 ret_val = igc_write_xmdio_reg(hw, (uint16_t)offset, dev_addr,
792 data);
793 }
794
795 return ret_val;
796}
797
798/**
799 * igc_read_phy_reg_gpy - Read GPY PHY register
800 * @hw: pointer to the HW structure
801 * @offset: lower half is register offset to read to
802 * upper half is MMD to use.
803 * @data: data to read at register offset
804 *
805 * Acquires semaphore, if necessary, then reads the data in the PHY register
806 * at the offset. Release any acquired semaphores before exiting.
807 **/
808int
809igc_read_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t *data)
810{
811 uint8_t dev_addr = (offset & GPY_MMD_MASK0xFFFF0000) >> GPY_MMD_SHIFT16;
812 int ret_val;
813
814 DEBUGFUNC("igc_read_phy_reg_gpy")do { if (0) printf("igc_read_phy_reg_gpy" "\n"); } while (0);
815
816 offset = offset & GPY_REG_MASK0x0000FFFF;
817
818 if (!dev_addr) {
819 ret_val = hw->phy.ops.acquire(hw);
820 if (ret_val)
821 return ret_val;
822 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
823 if (ret_val)
824 return ret_val;
825 hw->phy.ops.release(hw);
826 } else {
827 ret_val = igc_read_xmdio_reg(hw, (uint16_t)offset, dev_addr,
828 data);
829 }
830
831 return ret_val;
832}
833
834/**
835 * __igc_access_xmdio_reg - Read/write XMDIO register
836 * @hw: pointer to the HW structure
837 * @address: XMDIO address to program
838 * @dev_addr: device address to program
839 * @data: pointer to value to read/write from/to the XMDIO address
840 * @read: boolean flag to indicate read or write
841 **/
842int
843__igc_access_xmdio_reg(struct igc_hw *hw, uint16_t address, uint8_t dev_addr,
844 uint16_t *data, bool_Bool read)
845{
846 int ret_val;
847
848 DEBUGFUNC("__igc_access_xmdio_reg")do { if (0) printf("__igc_access_xmdio_reg" "\n"); } while (0
);
849
850 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC13, dev_addr);
851 if (ret_val)
852 return ret_val;
853
854 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD14, address);
855 if (ret_val)
856 return ret_val;
857
858 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC13, IGC_MMDAC_FUNC_DATA0x4000 |
859 dev_addr);
860 if (ret_val)
861 return ret_val;
862
863 if (read)
864 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD14, data);
865 else
866 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD14, *data);
867 if (ret_val)
868 return ret_val;
869
870 /* Recalibrate the device back to 0 */
871 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC13, 0);
872 if (ret_val)
873 return ret_val;
874
875 return ret_val;
876}
877
878/**
879 * igc_read_xmdio_reg - Read XMDIO register
880 * @hw: pointer to the HW structure
881 * @addr: XMDIO address to program
882 * @dev_addr: device address to program
883 * @data: value to be read from the EMI address
884 **/
885int
886igc_read_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr,
887 uint16_t *data)
888{
889 DEBUGFUNC("igc_read_xmdio_reg")do { if (0) printf("igc_read_xmdio_reg" "\n"); } while (0);
890
891 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true1);
892}
893
894/**
895 * igc_write_xmdio_reg - Write XMDIO register
896 * @hw: pointer to the HW structure
897 * @addr: XMDIO address to program
898 * @dev_addr: device address to program
899 * @data: value to be written to the XMDIO address
900 **/
901int
902igc_write_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr,
903 uint16_t data)
904{
905 DEBUGFUNC("igc_write_xmdio_reg")do { if (0) printf("igc_write_xmdio_reg" "\n"); } while (0);
906
907 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false0);
908}