Bug Summary

File:dev/usb/if_urtwn.c
Warning:line 596, column 11
2nd function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_urtwn.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/usb/if_urtwn.c
1/* $OpenBSD: if_urtwn.c,v 1.98 2021/10/04 01:33:42 kevlo Exp $ */
2
3/*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/*
22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/
23 * RTL8192EU.
24 */
25
26#include "bpfilter.h"
27
28#include <sys/param.h>
29#include <sys/sockio.h>
30#include <sys/mbuf.h>
31#include <sys/kernel.h>
32#include <sys/socket.h>
33#include <sys/systm.h>
34#include <sys/timeout.h>
35#include <sys/conf.h>
36#include <sys/device.h>
37#include <sys/endian.h>
38
39#include <machine/bus.h>
40#include <machine/intr.h>
41
42#if NBPFILTER1 > 0
43#include <net/bpf.h>
44#endif
45#include <net/if.h>
46#include <net/if_dl.h>
47#include <net/if_media.h>
48
49#include <netinet/in.h>
50#include <netinet/if_ether.h>
51
52#include <net80211/ieee80211_var.h>
53#include <net80211/ieee80211_amrr.h>
54#include <net80211/ieee80211_radiotap.h>
55
56#include <dev/usb/usb.h>
57#include <dev/usb/usbdi.h>
58#include <dev/usb/usbdivar.h>
59#include <dev/usb/usbdi_util.h>
60#include <dev/usb/usbdevs.h>
61
62#include <dev/ic/r92creg.h>
63#include <dev/ic/rtwnvar.h>
64
65/* Maximum number of output pipes is 3. */
66#define R92C_MAX_EPOUT3 3
67
68#define R92C_HQ_NPAGES12 12
69#define R92C_LQ_NPAGES2 2
70#define R92C_NQ_NPAGES2 2
71#define R92C_TXPKTBUF_COUNT256 256
72#define R92C_TX_PAGE_COUNT248 248
73#define R92C_TX_PAGE_BOUNDARY(248 + 1) (R92C_TX_PAGE_COUNT248 + 1)
74#define R92C_MAX_RX_DMA_SIZE0x2800 0x2800
75
76#define R88E_HQ_NPAGES0 0
77#define R88E_LQ_NPAGES9 9
78#define R88E_NQ_NPAGES0 0
79#define R88E_TXPKTBUF_COUNT177 177
80#define R88E_TX_PAGE_COUNT168 168
81#define R88E_TX_PAGE_BOUNDARY(168 + 1) (R88E_TX_PAGE_COUNT168 + 1)
82#define R88E_MAX_RX_DMA_SIZE0x2400 0x2400
83
84#define R92E_HQ_NPAGES16 16
85#define R92E_LQ_NPAGES16 16
86#define R92E_NQ_NPAGES16 16
87#define R92E_TX_PAGE_COUNT248 248
88#define R92E_TX_PAGE_BOUNDARY(248 + 1) (R92E_TX_PAGE_COUNT248 + 1)
89#define R92E_MAX_RX_DMA_SIZE0x3fc0 0x3fc0
90
91#define R92C_TXDESC_SUMSIZE32 32
92#define R92C_TXDESC_SUMOFFSET14 14
93
94/* USB Requests. */
95#define R92C_REQ_REGS0x05 0x05
96
97/*
98 * Driver definitions.
99 */
100#define URTWN_RX_LIST_COUNT1 1
101#define URTWN_TX_LIST_COUNT8 8
102#define URTWN_HOST_CMD_RING_COUNT32 32
103
104#define URTWN_RXBUFSZ(16 * 1024) (16 * 1024)
105#define URTWN_TXBUFSZ(sizeof(struct r92e_tx_desc_usb) + (2300 + 4 + (3 + 1 + 4))) (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN(2300 + 4 + (3 + 1 + 4)))
106
107#define URTWN_RIDX_COUNT28 28
108
109#define URTWN_TX_TIMEOUT5000 5000 /* ms */
110
111#define URTWN_LED_LINK0 0
112#define URTWN_LED_DATA1 1
113
114struct urtwn_rx_radiotap_header {
115 struct ieee80211_radiotap_header wr_ihdr;
116 uint8_t wr_flags;
117 uint8_t wr_rate;
118 uint16_t wr_chan_freq;
119 uint16_t wr_chan_flags;
120 uint8_t wr_dbm_antsignal;
121} __packed__attribute__((__packed__));
122
123#define URTWN_RX_RADIOTAP_PRESENT(1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE
| 1 << IEEE80211_RADIOTAP_CHANNEL | 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL
)
\
124 (1 << IEEE80211_RADIOTAP_FLAGS | \
125 1 << IEEE80211_RADIOTAP_RATE | \
126 1 << IEEE80211_RADIOTAP_CHANNEL | \
127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
128
129struct urtwn_tx_radiotap_header {
130 struct ieee80211_radiotap_header wt_ihdr;
131 uint8_t wt_flags;
132 uint16_t wt_chan_freq;
133 uint16_t wt_chan_flags;
134} __packed__attribute__((__packed__));
135
136#define URTWN_TX_RADIOTAP_PRESENT(1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_CHANNEL
)
\
137 (1 << IEEE80211_RADIOTAP_FLAGS | \
138 1 << IEEE80211_RADIOTAP_CHANNEL)
139
140struct urtwn_softc;
141
142struct urtwn_rx_data {
143 struct urtwn_softc *sc;
144 struct usbd_xfer *xfer;
145 uint8_t *buf;
146};
147
148struct urtwn_tx_data {
149 struct urtwn_softc *sc;
150 struct usbd_pipe *pipe;
151 struct usbd_xfer *xfer;
152 uint8_t *buf;
153 TAILQ_ENTRY(urtwn_tx_data)struct { struct urtwn_tx_data *tqe_next; struct urtwn_tx_data
**tqe_prev; }
next;
154};
155
156struct urtwn_host_cmd {
157 void (*cb)(struct urtwn_softc *, void *);
158 uint8_t data[256];
159};
160
161struct urtwn_cmd_newstate {
162 enum ieee80211_state state;
163 int arg;
164};
165
166struct urtwn_cmd_key {
167 struct ieee80211_key key;
168 struct ieee80211_node *ni;
169};
170
171struct urtwn_host_cmd_ring {
172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT32];
173 int cur;
174 int next;
175 int queued;
176};
177
178struct urtwn_softc {
179 struct device sc_dev;
180 struct rtwn_softc sc_sc;
181
182 struct usbd_device *sc_udev;
183 struct usbd_interface *sc_iface;
184 struct usb_task sc_task;
185
186 struct timeout scan_to;
187 struct timeout calib_to;
188
189 int ntx;
190 struct usbd_pipe *rx_pipe;
191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT3];
192 int ac2idx[EDCA_NUM_AC4];
193
194 struct urtwn_host_cmd_ring cmdq;
195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT1];
196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT8];
197 TAILQ_HEAD(, urtwn_tx_data)struct { struct urtwn_tx_data *tqh_first; struct urtwn_tx_data
**tqh_last; }
tx_free_list;
198
199 struct ieee80211_amrr amrr;
200 struct ieee80211_amrr_node amn;
201
202#if NBPFILTER1 > 0
203 caddr_t sc_drvbpf;
204
205 union {
206 struct urtwn_rx_radiotap_header th;
207 uint8_t pad[64];
208 } sc_rxtapu;
209#define sc_rxtapsc_rxtapu.th sc_rxtapu.th
210 int sc_rxtap_len;
211
212 union {
213 struct urtwn_tx_radiotap_header th;
214 uint8_t pad[64];
215 } sc_txtapu;
216#define sc_txtapsc_txtapu.th sc_txtapu.th
217 int sc_txtap_len;
218#endif
219 int sc_key_tasks;
220};
221
222#ifdef URTWN_DEBUG
223#define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0)
224#define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0)
225int urtwn_debug = 4;
226#else
227#define DPRINTF(x)
228#define DPRINTFN(n, x)
229#endif
230
231/*
232 * Various supported device vendors/products.
233 */
234#define URTWN_DEV(v, p, f){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (f) | 0x80000000 } \
235 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB0x80000000 }
236#define URTWN_DEV_8192CU(v, p){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000001 | 0x00000010
) | 0x80000000 }
URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000001 | 0x00000010
) | 0x80000000 }
237#define URTWN_DEV_8188EU(v, p){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000020) | 0x80000000
}
URTWN_DEV(v, p, RTWN_CHIP_88E){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000020) | 0x80000000
}
238#define URTWN_DEV_8192EU(v, p){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000040) | 0x80000000
}
URTWN_DEV(v, p, RTWN_CHIP_92E){ { USB_VENDOR_v, USB_PRODUCT_v_p }, (0x00000040) | 0x80000000
}
239static const struct urtwn_type {
240 struct usb_devno dev;
241 uint32_t chip;
242} urtwn_devs[] = {
243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1){ { 0x07b8, 0x8188 }, (0x00000001 | 0x00000010) | 0x80000000 },
244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1){ { 0x07b8, 0x8188 }, (0x00000001 | 0x00000010) | 0x80000000 },
245 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2){ { 0x07b8, 0x8189 }, (0x00000001 | 0x00000010) | 0x80000000 },
246 URTWN_DEV_8192CU(ABOCOM, RTL8192CU){ { 0x07b8, 0x8178 }, (0x00000001 | 0x00000010) | 0x80000000 },
247 URTWN_DEV_8192CU(ASUS, RTL8192CU){ { 0x0b05, 0x17ab }, (0x00000001 | 0x00000010) | 0x80000000 },
248 URTWN_DEV_8192CU(ASUS, RTL8192CU_2){ { 0x0b05, 0x17ba }, (0x00000001 | 0x00000010) | 0x80000000 },
249 URTWN_DEV_8192CU(ASUS, RTL8192CU_3){ { 0x0b05, 0x17c0 }, (0x00000001 | 0x00000010) | 0x80000000 },
250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1){ { 0x13d3, 0x3358 }, (0x00000001 | 0x00000010) | 0x80000000 },
251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2){ { 0x13d3, 0x3359 }, (0x00000001 | 0x00000010) | 0x80000000 },
252 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU){ { 0x13d3, 0x3357 }, (0x00000001 | 0x00000010) | 0x80000000 },
253 URTWN_DEV_8192CU(BELKIN, F7D2102){ { 0x050d, 0x2103 }, (0x00000001 | 0x00000010) | 0x80000000 },
254 URTWN_DEV_8192CU(BELKIN, F9L1004V1){ { 0x050d, 0x1004 }, (0x00000001 | 0x00000010) | 0x80000000 },
255 URTWN_DEV_8192CU(BELKIN, RTL8188CU){ { 0x050d, 0x1102 }, (0x00000001 | 0x00000010) | 0x80000000 },
256 URTWN_DEV_8192CU(BELKIN, RTL8188CUS){ { 0x050d, 0x11f2 }, (0x00000001 | 0x00000010) | 0x80000000 },
257 URTWN_DEV_8192CU(BELKIN, RTL8192CU){ { 0x050d, 0x2102 }, (0x00000001 | 0x00000010) | 0x80000000 },
258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1){ { 0x050d, 0x21f2 }, (0x00000001 | 0x00000010) | 0x80000000 },
259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1){ { 0x04f2, 0xaff7 }, (0x00000001 | 0x00000010) | 0x80000000 },
260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2){ { 0x04f2, 0xaff8 }, (0x00000001 | 0x00000010) | 0x80000000 },
261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3){ { 0x04f2, 0xaff9 }, (0x00000001 | 0x00000010) | 0x80000000 },
262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4){ { 0x04f2, 0xaffa }, (0x00000001 | 0x00000010) | 0x80000000 },
263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5){ { 0x04f2, 0xaffb }, (0x00000001 | 0x00000010) | 0x80000000 },
264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6){ { 0x04f2, 0xaffc }, (0x00000001 | 0x00000010) | 0x80000000 },
265 URTWN_DEV_8192CU(COMPARE, RTL8192CU){ { 0xcdab, 0x8010 }, (0x00000001 | 0x00000010) | 0x80000000 },
266 URTWN_DEV_8192CU(COREGA, RTL8192CU){ { 0x07aa, 0x0056 }, (0x00000001 | 0x00000010) | 0x80000000 },
267 URTWN_DEV_8192CU(DLINK, DWA131B){ { 0x2001, 0x330d }, (0x00000001 | 0x00000010) | 0x80000000 },
268 URTWN_DEV_8192CU(DLINK, RTL8188CU){ { 0x2001, 0x3308 }, (0x00000001 | 0x00000010) | 0x80000000 },
269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1){ { 0x2001, 0x3307 }, (0x00000001 | 0x00000010) | 0x80000000 },
270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2){ { 0x2001, 0x3309 }, (0x00000001 | 0x00000010) | 0x80000000 },
271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3){ { 0x2001, 0x330a }, (0x00000001 | 0x00000010) | 0x80000000 },
272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4){ { 0x2001, 0x330b }, (0x00000001 | 0x00000010) | 0x80000000 },
273 URTWN_DEV_8192CU(EDIMAX, EW7811UN){ { 0x7392, 0x7811 }, (0x00000001 | 0x00000010) | 0x80000000 },
274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU){ { 0x7392, 0x7822 }, (0x00000001 | 0x00000010) | 0x80000000 },
275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU){ { 0x4855, 0x0090 }, (0x00000001 | 0x00000010) | 0x80000000 },
276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU){ { 0x4855, 0x0091 }, (0x00000001 | 0x00000010) | 0x80000000 },
277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150){ { 0x06f8, 0xe033 }, (0x00000001 | 0x00000010) | 0x80000000 },
278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU){ { 0x06f8, 0xe035 }, (0x00000001 | 0x00000010) | 0x80000000 },
279 URTWN_DEV_8192CU(HAWKING, RTL8192CU){ { 0x0e66, 0x0019 }, (0x00000001 | 0x00000010) | 0x80000000 },
280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2){ { 0x0e66, 0x0020 }, (0x00000001 | 0x00000010) | 0x80000000 },
281 URTWN_DEV_8192CU(HP3, RTL8188CU){ { 0x103c, 0x1629 }, (0x00000001 | 0x00000010) | 0x80000000 },
282 URTWN_DEV_8192CU(IODATA, WNG150UM){ { 0x04bb, 0x094c }, (0x00000001 | 0x00000010) | 0x80000000 },
283 URTWN_DEV_8192CU(IODATA, RTL8192CU){ { 0x04bb, 0x0950 }, (0x00000001 | 0x00000010) | 0x80000000 },
284 URTWN_DEV_8192CU(NETGEAR, N300MA){ { 0x0846, 0xf001 }, (0x00000001 | 0x00000010) | 0x80000000 },
285 URTWN_DEV_8192CU(NETGEAR, WNA1000M){ { 0x0846, 0x9041 }, (0x00000001 | 0x00000010) | 0x80000000 },
286 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2){ { 0x0846, 0x9043 }, (0x00000001 | 0x00000010) | 0x80000000 },
287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU){ { 0x0846, 0x9021 }, (0x00000001 | 0x00000010) | 0x80000000 },
288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU){ { 0x9846, 0x9041 }, (0x00000001 | 0x00000010) | 0x80000000 },
289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU){ { 0x4856, 0x0091 }, (0x00000001 | 0x00000010) | 0x80000000 },
290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU){ { 0x0eb0, 0x9071 }, (0x00000001 | 0x00000010) | 0x80000000 },
291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1){ { 0x2019, 0xab2a }, (0x00000001 | 0x00000010) | 0x80000000 },
292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2){ { 0x2019, 0xed17 }, (0x00000001 | 0x00000010) | 0x80000000 },
293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3){ { 0x2019, 0x4902 }, (0x00000001 | 0x00000010) | 0x80000000 },
294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4){ { 0x2019, 0xab2e }, (0x00000001 | 0x00000010) | 0x80000000 },
295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS){ { 0x2019, 0x1201 }, (0x00000001 | 0x00000010) | 0x80000000 },
296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU){ { 0x2019, 0xab2b }, (0x00000001 | 0x00000010) | 0x80000000 },
297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0){ { 0x0bda, 0x8170 }, (0x00000001 | 0x00000010) | 0x80000000 },
298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1){ { 0x0bda, 0x817e }, (0x00000001 | 0x00000010) | 0x80000000 },
299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV){ { 0x0bda, 0x018a }, (0x00000001 | 0x00000010) | 0x80000000 },
300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0){ { 0x0bda, 0x8176 }, (0x00000001 | 0x00000010) | 0x80000000 },
301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1){ { 0x0bda, 0x817a }, (0x00000001 | 0x00000010) | 0x80000000 },
302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2){ { 0x0bda, 0x817b }, (0x00000001 | 0x00000010) | 0x80000000 },
303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3){ { 0x0bda, 0x8191 }, (0x00000001 | 0x00000010) | 0x80000000 },
304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4){ { 0x0bda, 0x5088 }, (0x00000001 | 0x00000010) | 0x80000000 },
305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5){ { 0x0bda, 0x819a }, (0x00000001 | 0x00000010) | 0x80000000 },
306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO){ { 0x0bda, 0x8754 }, (0x00000001 | 0x00000010) | 0x80000000 },
307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS){ { 0x0bda, 0x818a }, (0x00000001 | 0x00000010) | 0x80000000 },
308 URTWN_DEV_8192CU(REALTEK, RTL8188RU){ { 0x0bda, 0x817d }, (0x00000001 | 0x00000010) | 0x80000000 },
309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2){ { 0x0bda, 0x317f }, (0x00000001 | 0x00000010) | 0x80000000 },
310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3){ { 0x0bda, 0x817f }, (0x00000001 | 0x00000010) | 0x80000000 },
311 URTWN_DEV_8192CU(REALTEK, RTL8191CU){ { 0x0bda, 0x8177 }, (0x00000001 | 0x00000010) | 0x80000000 },
312 URTWN_DEV_8192CU(REALTEK, RTL8192CE){ { 0x0bda, 0x817c }, (0x00000001 | 0x00000010) | 0x80000000 },
313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU){ { 0x0bda, 0x8186 }, (0x00000001 | 0x00000010) | 0x80000000 },
314 URTWN_DEV_8192CU(REALTEK, RTL8192CU){ { 0x0bda, 0x8178 }, (0x00000001 | 0x00000010) | 0x80000000 },
315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU){ { 0x0df6, 0x0052 }, (0x00000001 | 0x00000010) | 0x80000000 },
316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2){ { 0x0df6, 0x005c }, (0x00000001 | 0x00000010) | 0x80000000 },
317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU){ { 0x0df6, 0x0061 }, (0x00000001 | 0x00000010) | 0x80000000 },
318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2){ { 0x0df6, 0x0070 }, (0x00000001 | 0x00000010) | 0x80000000 },
319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2){ { 0x0df6, 0x0077 }, (0x00000001 | 0x00000010) | 0x80000000 },
320 URTWN_DEV_8192CU(TPLINK, RTL8192CU){ { 0x2357, 0x0100 }, (0x00000001 | 0x00000010) | 0x80000000 },
321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU){ { 0x20f4, 0x648b }, (0x00000001 | 0x00000010) | 0x80000000 },
322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU){ { 0x20f4, 0x624d }, (0x00000001 | 0x00000010) | 0x80000000 },
323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU){ { 0x0586, 0x341f }, (0x00000001 | 0x00000010) | 0x80000000 },
324 /* URTWN_RTL8188E */
325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU){ { 0x07b8, 0x8179 }, (0x00000020) | 0x80000000 },
326 URTWN_DEV_8188EU(DLINK, DWA121B1){ { 0x2001, 0x331b }, (0x00000020) | 0x80000000 },
327 URTWN_DEV_8188EU(DLINK, DWA123D1){ { 0x2001, 0x3310 }, (0x00000020) | 0x80000000 },
328 URTWN_DEV_8188EU(DLINK, DWA125D1){ { 0x2001, 0x330f }, (0x00000020) | 0x80000000 },
329 URTWN_DEV_8188EU(EDIMAX, EW7811UNV2){ { 0x7392, 0xb811 }, (0x00000020) | 0x80000000 },
330 URTWN_DEV_8188EU(ELECOM, WDC150SU2M){ { 0x056e, 0x4008 }, (0x00000020) | 0x80000000 },
331 URTWN_DEV_8188EU(REALTEK, RTL8188ETV){ { 0x0bda, 0x0179 }, (0x00000020) | 0x80000000 },
332 URTWN_DEV_8188EU(REALTEK, RTL8188EU){ { 0x0bda, 0x8179 }, (0x00000020) | 0x80000000 },
333 URTWN_DEV_8188EU(TPLINK, RTL8188EUS){ { 0x2357, 0x010c }, (0x00000020) | 0x80000000 },
334 URTWN_DEV_8188EU(ASUS, RTL8188EUS){ { 0x0b05, 0x18f0 }, (0x00000020) | 0x80000000 },
335
336 /* URTWN_RTL8192EU */
337 URTWN_DEV_8192EU(DLINK, DWA131E1){ { 0x2001, 0x3319 }, (0x00000040) | 0x80000000 },
338 URTWN_DEV_8192EU(REALTEK, RTL8192EU){ { 0x0bda, 0x818b }, (0x00000040) | 0x80000000 },
339 URTWN_DEV_8192EU(TPLINK, RTL8192EU){ { 0x2357, 0x0107 }, (0x00000040) | 0x80000000 },
340 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2){ { 0x2357, 0x0108 }, (0x00000040) | 0x80000000 },
341 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3){ { 0x2357, 0x0109 }, (0x00000040) | 0x80000000 }
342};
343
344#define urtwn_lookup(v, p)((const struct urtwn_type *)usbd_match_device((const struct usb_devno
*)(urtwn_devs), sizeof (urtwn_devs) / sizeof ((urtwn_devs)[0
]), sizeof ((urtwn_devs)[0]), (v), (p)))
\
345 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)usbd_match_device((const struct usb_devno *)(urtwn_devs), sizeof
(urtwn_devs) / sizeof ((urtwn_devs)[0]), sizeof ((urtwn_devs
)[0]), (v), (p))
)
346
347int urtwn_match(struct device *, void *, void *);
348void urtwn_attach(struct device *, struct device *, void *);
349int urtwn_detach(struct device *, int);
350int urtwn_open_pipes(struct urtwn_softc *);
351void urtwn_close_pipes(struct urtwn_softc *);
352int urtwn_alloc_rx_list(struct urtwn_softc *);
353void urtwn_free_rx_list(struct urtwn_softc *);
354int urtwn_alloc_tx_list(struct urtwn_softc *);
355void urtwn_free_tx_list(struct urtwn_softc *);
356void urtwn_task(void *);
357void urtwn_do_async(struct urtwn_softc *,
358 void (*)(struct urtwn_softc *, void *), void *, int);
359void urtwn_wait_async(void *);
360int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
361 int);
362void urtwn_write_1(void *, uint16_t, uint8_t);
363void urtwn_write_2(void *, uint16_t, uint16_t);
364void urtwn_write_4(void *, uint16_t, uint32_t);
365int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
366 int);
367uint8_t urtwn_read_1(void *, uint16_t);
368uint16_t urtwn_read_2(void *, uint16_t);
369uint32_t urtwn_read_4(void *, uint16_t);
370int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t);
371void urtwn_calib_to(void *);
372void urtwn_calib_cb(struct urtwn_softc *, void *);
373void urtwn_scan_to(void *);
374void urtwn_next_scan(void *);
375void urtwn_cancel_scan(void *);
376int urtwn_newstate(struct ieee80211com *, enum ieee80211_state,
377 int);
378void urtwn_newstate_cb(struct urtwn_softc *, void *);
379void urtwn_updateslot(struct ieee80211com *);
380void urtwn_updateslot_cb(struct urtwn_softc *, void *);
381void urtwn_updateedca(struct ieee80211com *);
382void urtwn_updateedca_cb(struct urtwn_softc *, void *);
383int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *,
384 struct ieee80211_key *);
385void urtwn_set_key_cb(struct urtwn_softc *, void *);
386void urtwn_delete_key(struct ieee80211com *,
387 struct ieee80211_node *, struct ieee80211_key *);
388void urtwn_delete_key_cb(struct urtwn_softc *, void *);
389void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
390 struct mbuf_list *);
391void urtwn_rxeof(struct usbd_xfer *, void *,
392 usbd_status);
393void urtwn_txeof(struct usbd_xfer *, void *,
394 usbd_status);
395int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *);
396int urtwn_ioctl(struct ifnet *, u_long, caddr_t);
397int urtwn_power_on(void *);
398int urtwn_alloc_buffers(void *);
399int urtwn_r92c_power_on(struct urtwn_softc *);
400int urtwn_r92e_power_on(struct urtwn_softc *);
401int urtwn_r88e_power_on(struct urtwn_softc *);
402int urtwn_llt_init(struct urtwn_softc *, int);
403int urtwn_fw_loadpage(void *, int, uint8_t *, int);
404int urtwn_load_firmware(void *, u_char **, size_t *);
405int urtwn_dma_init(void *);
406void urtwn_aggr_init(void *);
407void urtwn_mac_init(void *);
408void urtwn_bb_init(void *);
409void urtwn_burstlen_init(struct urtwn_softc *);
410int urtwn_init(void *);
411void urtwn_stop(void *);
412int urtwn_is_oactive(void *);
413void urtwn_next_calib(void *);
414void urtwn_cancel_calib(void *);
415
416/* Aliases. */
417#define urtwn_bb_writeurtwn_write_4 urtwn_write_4
418#define urtwn_bb_readurtwn_read_4 urtwn_read_4
419
420struct cfdriver urtwn_cd = {
421 NULL((void *)0), "urtwn", DV_IFNET
422};
423
424const struct cfattach urtwn_ca = {
425 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach
426};
427
428int
429urtwn_match(struct device *parent, void *match, void *aux)
430{
431 struct usb_attach_arg *uaa = aux;
432
433 if (uaa->iface == NULL((void *)0) || uaa->configno != 1)
434 return (UMATCH_NONE0);
435
436 return ((urtwn_lookup(uaa->vendor, uaa->product)((const struct urtwn_type *)usbd_match_device((const struct usb_devno
*)(urtwn_devs), sizeof (urtwn_devs) / sizeof ((urtwn_devs)[0
]), sizeof ((urtwn_devs)[0]), (uaa->vendor), (uaa->product
)))
!= NULL((void *)0)) ?
437 UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0);
438}
439
440void
441urtwn_attach(struct device *parent, struct device *self, void *aux)
442{
443 struct urtwn_softc *sc = (struct urtwn_softc *)self;
444 struct usb_attach_arg *uaa = aux;
445 struct ifnet *ifp;
446 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
447
448 sc->sc_udev = uaa->device;
449 sc->sc_iface = uaa->iface;
450
451 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)((const struct urtwn_type *)usbd_match_device((const struct usb_devno
*)(urtwn_devs), sizeof (urtwn_devs) / sizeof ((urtwn_devs)[0
]), sizeof ((urtwn_devs)[0]), (uaa->vendor), (uaa->product
)))
->chip;
452
453 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC)((&sc->sc_task)->fun = (urtwn_task), (&sc->sc_task
)->arg = (sc), (&sc->sc_task)->type = (0), (&
sc->sc_task)->state = 0x0)
;
454 timeout_set(&sc->scan_to, urtwn_scan_to, sc);
455 timeout_set(&sc->calib_to, urtwn_calib_to, sc);
456 if (urtwn_open_pipes(sc) != 0)
1
Calling 'urtwn_open_pipes'
457 return;
458
459 sc->amrr.amrr_min_success_threshold = 1;
460 sc->amrr.amrr_max_success_threshold = 10;
461
462 /* Attach the bus-agnostic driver. */
463 sc->sc_sc.sc_ops.cookie = sc;
464 sc->sc_sc.sc_ops.write_1 = urtwn_write_1;
465 sc->sc_sc.sc_ops.write_2 = urtwn_write_2;
466 sc->sc_sc.sc_ops.write_4 = urtwn_write_4;
467 sc->sc_sc.sc_ops.read_1 = urtwn_read_1;
468 sc->sc_sc.sc_ops.read_2 = urtwn_read_2;
469 sc->sc_sc.sc_ops.read_4 = urtwn_read_4;
470 sc->sc_sc.sc_ops.tx = urtwn_tx;
471 sc->sc_sc.sc_ops.power_on = urtwn_power_on;
472 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init;
473 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage;
474 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware;
475 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init;
476 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init;
477 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init;
478 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers;
479 sc->sc_sc.sc_ops.init = urtwn_init;
480 sc->sc_sc.sc_ops.stop = urtwn_stop;
481 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive;
482 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib;
483 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib;
484 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan;
485 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan;
486 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async;
487 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) {
488 urtwn_close_pipes(sc);
489 return;
490 }
491
492 /* ifp is now valid */
493 ifp = &sc->sc_sc.sc_ic.ic_ific_ac.ac_if;
494 ifp->if_ioctl = urtwn_ioctl;
495
496 ic->ic_updateslot = urtwn_updateslot;
497 ic->ic_updateedca = urtwn_updateedca;
498 ic->ic_set_key = urtwn_set_key;
499 ic->ic_delete_key = urtwn_delete_key;
500 /* Override state transition machine. */
501 ic->ic_newstate = urtwn_newstate;
502
503#if NBPFILTER1 > 0
504 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO127,
505 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN64);
506
507 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
508 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len));
509 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
| 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)))
;
510
511 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
512 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len));
513 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_CHANNEL)))
;
514#endif
515}
516
517int
518urtwn_detach(struct device *self, int flags)
519{
520 struct urtwn_softc *sc = (struct urtwn_softc *)self;
521 int s;
522
523 s = splusb()splraise(0x5);
524
525 if (timeout_initialized(&sc->scan_to)((&sc->scan_to)->to_flags & 0x04))
526 timeout_del(&sc->scan_to);
527 if (timeout_initialized(&sc->calib_to)((&sc->calib_to)->to_flags & 0x04))
528 timeout_del(&sc->calib_to);
529
530 /* Wait for all async commands to complete. */
531 usb_rem_wait_task(sc->sc_udev, &sc->sc_task);
532
533 usbd_ref_wait(sc->sc_udev);
534
535 rtwn_detach(&sc->sc_sc, flags);
536
537 /* Abort and close Tx/Rx pipes. */
538 urtwn_close_pipes(sc);
539
540 /* Free Tx/Rx buffers. */
541 urtwn_free_tx_list(sc);
542 urtwn_free_rx_list(sc);
543 splx(s)spllower(s);
544
545 return (0);
546}
547
548int
549urtwn_open_pipes(struct urtwn_softc *sc)
550{
551 /* Bulk-out endpoints addresses (from highest to lowest prio). */
552 uint8_t epaddr[R92C_MAX_EPOUT3] = { 0, 0, 0 };
553 uint8_t rx_no;
554 usb_interface_descriptor_t *id;
555 usb_endpoint_descriptor_t *ed;
556 int i, error, nrx = 0;
557
558 /* Find all bulk endpoints. */
559 id = usbd_get_interface_descriptor(sc->sc_iface);
560 for (i = 0; i < id->bNumEndpoints; i++) {
2
Assuming 'i' is < field 'bNumEndpoints'
3
Loop condition is true. Entering loop body
9
Assuming 'i' is >= field 'bNumEndpoints'
10
Loop condition is false. Execution continues on line 574
561 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i);
562 if (ed == NULL((void *)0) || UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) != UE_BULK0x02)
4
Assuming 'ed' is not equal to NULL
5
Assuming the condition is false
6
Taking false branch
563 continue;
564
565 if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80) {
7
Assuming the condition is true
8
Taking true branch
566 rx_no = ed->bEndpointAddress;
567 nrx++;
568 } else {
569 if (sc->ntx < R92C_MAX_EPOUT3)
570 epaddr[sc->ntx] = ed->bEndpointAddress;
571 sc->ntx++;
572 }
573 }
574 if (nrx
10.1
'nrx' is not equal to 0
== 0) {
11
Taking false branch
575 printf("%s: %d: invalid number of Rx bulk pipes\n",
576 sc->sc_dev.dv_xname, nrx);
577 return (EIO5);
578 }
579 DPRINTF(("found %d bulk-out pipes\n", sc->ntx));
580 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT3) {
12
Assuming field 'ntx' is not equal to 0
13
Assuming field 'ntx' is <= R92C_MAX_EPOUT
14
Taking false branch
581 printf("%s: %d: invalid number of Tx bulk pipes\n",
582 sc->sc_dev.dv_xname, sc->ntx);
583 return (EIO5);
584 }
585
586 /* Open bulk-in pipe. */
587 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe);
588 if (error != 0) {
15
Assuming 'error' is equal to 0
16
Taking false branch
589 printf("%s: could not open Rx bulk pipe\n",
590 sc->sc_dev.dv_xname);
591 goto fail;
592 }
593
594 /* Open bulk-out pipes (up to 3). */
595 for (i = 0; i < sc->ntx; i++) {
17
Assuming 'i' is < field 'ntx'
18
Loop condition is true. Entering loop body
21
Assuming 'i' is < field 'ntx'
22
Loop condition is true. Entering loop body
25
Assuming 'i' is < field 'ntx'
26
Loop condition is true. Entering loop body
29
The value 3 is assigned to 'i'
30
Assuming 'i' is < field 'ntx'
31
Loop condition is true. Entering loop body
596 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0,
32
2nd function call argument is an uninitialized value
597 &sc->tx_pipe[i]);
598 if (error != 0) {
19
Assuming 'error' is equal to 0
20
Taking false branch
23
Assuming 'error' is equal to 0
24
Taking false branch
27
Assuming 'error' is equal to 0
28
Taking false branch
599 printf("%s: could not open Tx bulk pipe 0x%02x\n",
600 sc->sc_dev.dv_xname, epaddr[i]);
601 goto fail;
602 }
603 }
604
605 /* Map 802.11 access categories to USB pipes. */
606 sc->ac2idx[EDCA_AC_BK] =
607 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0);
608 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0;
609 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */
610
611 if (error != 0)
612 fail: urtwn_close_pipes(sc);
613 return (error);
614}
615
616void
617urtwn_close_pipes(struct urtwn_softc *sc)
618{
619 int i;
620
621 /* Close Rx pipe. */
622 if (sc->rx_pipe != NULL((void *)0))
623 usbd_close_pipe(sc->rx_pipe);
624 /* Close Tx pipes. */
625 for (i = 0; i < R92C_MAX_EPOUT3; i++) {
626 if (sc->tx_pipe[i] == NULL((void *)0))
627 continue;
628 usbd_close_pipe(sc->tx_pipe[i]);
629 }
630}
631
632int
633urtwn_alloc_rx_list(struct urtwn_softc *sc)
634{
635 struct urtwn_rx_data *data;
636 int i, error = 0;
637
638 for (i = 0; i < URTWN_RX_LIST_COUNT1; i++) {
639 data = &sc->rx_data[i];
640
641 data->sc = sc; /* Backpointer for callbacks. */
642
643 data->xfer = usbd_alloc_xfer(sc->sc_udev);
644 if (data->xfer == NULL((void *)0)) {
645 printf("%s: could not allocate xfer\n",
646 sc->sc_dev.dv_xname);
647 error = ENOMEM12;
648 break;
649 }
650 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ(16 * 1024));
651 if (data->buf == NULL((void *)0)) {
652 printf("%s: could not allocate xfer buffer\n",
653 sc->sc_dev.dv_xname);
654 error = ENOMEM12;
655 break;
656 }
657 }
658 if (error != 0)
659 urtwn_free_rx_list(sc);
660 return (error);
661}
662
663void
664urtwn_free_rx_list(struct urtwn_softc *sc)
665{
666 int i;
667
668 /* NB: Caller must abort pipe first. */
669 for (i = 0; i < URTWN_RX_LIST_COUNT1; i++) {
670 if (sc->rx_data[i].xfer != NULL((void *)0))
671 usbd_free_xfer(sc->rx_data[i].xfer);
672 sc->rx_data[i].xfer = NULL((void *)0);
673 }
674}
675
676int
677urtwn_alloc_tx_list(struct urtwn_softc *sc)
678{
679 struct urtwn_tx_data *data;
680 int i, error = 0;
681
682 TAILQ_INIT(&sc->tx_free_list)do { (&sc->tx_free_list)->tqh_first = ((void *)0); (
&sc->tx_free_list)->tqh_last = &(&sc->tx_free_list
)->tqh_first; } while (0)
;
683 for (i = 0; i < URTWN_TX_LIST_COUNT8; i++) {
684 data = &sc->tx_data[i];
685
686 data->sc = sc; /* Backpointer for callbacks. */
687
688 data->xfer = usbd_alloc_xfer(sc->sc_udev);
689 if (data->xfer == NULL((void *)0)) {
690 printf("%s: could not allocate xfer\n",
691 sc->sc_dev.dv_xname);
692 error = ENOMEM12;
693 break;
694 }
695 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ(sizeof(struct r92e_tx_desc_usb) + (2300 + 4 + (3 + 1 + 4))));
696 if (data->buf == NULL((void *)0)) {
697 printf("%s: could not allocate xfer buffer\n",
698 sc->sc_dev.dv_xname);
699 error = ENOMEM12;
700 break;
701 }
702 /* Append this Tx buffer to our free list. */
703 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next)do { (data)->next.tqe_next = ((void *)0); (data)->next.
tqe_prev = (&sc->tx_free_list)->tqh_last; *(&sc
->tx_free_list)->tqh_last = (data); (&sc->tx_free_list
)->tqh_last = &(data)->next.tqe_next; } while (0)
;
704 }
705 if (error != 0)
706 urtwn_free_tx_list(sc);
707 return (error);
708}
709
710void
711urtwn_free_tx_list(struct urtwn_softc *sc)
712{
713 int i;
714
715 /* NB: Caller must abort pipe first. */
716 for (i = 0; i < URTWN_TX_LIST_COUNT8; i++) {
717 if (sc->tx_data[i].xfer != NULL((void *)0))
718 usbd_free_xfer(sc->tx_data[i].xfer);
719 sc->tx_data[i].xfer = NULL((void *)0);
720 }
721}
722
723void
724urtwn_task(void *arg)
725{
726 struct urtwn_softc *sc = arg;
727 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
728 struct urtwn_host_cmd *cmd;
729 int s;
730
731 /* Process host commands. */
732 s = splusb()splraise(0x5);
733 while (ring->next != ring->cur) {
734 cmd = &ring->cmd[ring->next];
735 splx(s)spllower(s);
736 /* Invoke callback. */
737 cmd->cb(sc, cmd->data);
738 s = splusb()splraise(0x5);
739 ring->queued--;
740 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT32;
741 }
742 splx(s)spllower(s);
743}
744
745void
746urtwn_do_async(struct urtwn_softc *sc,
747 void (*cb)(struct urtwn_softc *, void *), void *arg, int len)
748{
749 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
750 struct urtwn_host_cmd *cmd;
751 int s;
752
753 s = splusb()splraise(0x5);
754 cmd = &ring->cmd[ring->cur];
755 cmd->cb = cb;
756 KASSERT(len <= sizeof(cmd->data))((len <= sizeof(cmd->data)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/usb/if_urtwn.c", 756, "len <= sizeof(cmd->data)"
))
;
757 memcpy(cmd->data, arg, len)__builtin_memcpy((cmd->data), (arg), (len));
758 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT32;
759
760 /* If there is no pending command already, schedule a task. */
761 if (++ring->queued == 1)
762 usb_add_task(sc->sc_udev, &sc->sc_task);
763 splx(s)spllower(s);
764}
765
766void
767urtwn_wait_async(void *cookie)
768{
769 struct urtwn_softc *sc = cookie;
770 int s;
771
772 s = splusb()splraise(0x5);
773 /* Wait for all queued asynchronous commands to complete. */
774 usb_wait_task(sc->sc_udev, &sc->sc_task);
775 splx(s)spllower(s);
776}
777
778int
779urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
780 int len)
781{
782 usb_device_request_t req;
783
784 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
785 req.bRequest = R92C_REQ_REGS0x05;
786 USETW(req.wValue, addr)(*(u_int16_t *)(req.wValue) = (addr));
787 USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0));
788 USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));
789 return (usbd_do_request(sc->sc_udev, &req, buf));
790}
791
792void
793urtwn_write_1(void *cookie, uint16_t addr, uint8_t val)
794{
795 struct urtwn_softc *sc = cookie;
796
797 urtwn_write_region_1(sc, addr, &val, 1);
798}
799
800void
801urtwn_write_2(void *cookie, uint16_t addr, uint16_t val)
802{
803 struct urtwn_softc *sc = cookie;
804
805 val = htole16(val)((__uint16_t)(val));
806 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
807}
808
809void
810urtwn_write_4(void *cookie, uint16_t addr, uint32_t val)
811{
812 struct urtwn_softc *sc = cookie;
813
814 val = htole32(val)((__uint32_t)(val));
815 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
816}
817
818int
819urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
820 int len)
821{
822 usb_device_request_t req;
823
824 req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00);
825 req.bRequest = R92C_REQ_REGS0x05;
826 USETW(req.wValue, addr)(*(u_int16_t *)(req.wValue) = (addr));
827 USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0));
828 USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));
829 return (usbd_do_request(sc->sc_udev, &req, buf));
830}
831
832uint8_t
833urtwn_read_1(void *cookie, uint16_t addr)
834{
835 struct urtwn_softc *sc = cookie;
836 uint8_t val;
837
838 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
839 return (0xff);
840 return (val);
841}
842
843uint16_t
844urtwn_read_2(void *cookie, uint16_t addr)
845{
846 struct urtwn_softc *sc = cookie;
847 uint16_t val;
848
849 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
850 return (0xffff);
851 return (letoh16(val)((__uint16_t)(val)));
852}
853
854uint32_t
855urtwn_read_4(void *cookie, uint16_t addr)
856{
857 struct urtwn_softc *sc = cookie;
858 uint32_t val;
859
860 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
861 return (0xffffffff);
862 return (letoh32(val)((__uint32_t)(val)));
863}
864
865int
866urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
867{
868 int ntries;
869
870 urtwn_write_4(sc, R92C_LLT_INIT0x1e0,
871 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE)(((1) << 30) & 0xc0000000) |
872 SM(R92C_LLT_INIT_ADDR, addr)(((addr) << 8) & 0x0000ff00) |
873 SM(R92C_LLT_INIT_DATA, data)(((data) << 0) & 0x000000ff));
874 /* Wait for write operation to complete. */
875 for (ntries = 0; ntries < 20; ntries++) {
876 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP)(((urtwn_read_4(sc, 0x1e0)) & 0xc0000000) >> 30) ==
877 R92C_LLT_INIT_OP_NO_ACTIVE0)
878 return (0);
879 DELAY(5)(*delay_func)(5);
880 }
881 return (ETIMEDOUT60);
882}
883
884void
885urtwn_calib_to(void *arg)
886{
887 struct urtwn_softc *sc = arg;
888
889 if (usbd_is_dying(sc->sc_udev))
890 return;
891
892 usbd_ref_incr(sc->sc_udev);
893
894 /* Do it in a process context. */
895 urtwn_do_async(sc, urtwn_calib_cb, NULL((void *)0), 0);
896
897 usbd_ref_decr(sc->sc_udev);
898}
899
900/* ARGSUSED */
901void
902urtwn_calib_cb(struct urtwn_softc *sc, void *arg)
903{
904 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
905 int s;
906
907 s = splnet()splraise(0x7);
908 if (ic->ic_opmode == IEEE80211_M_STA) {
909 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn);
910 }
911 splx(s)spllower(s);
912
913 rtwn_calib(&sc->sc_sc);
914}
915
916void
917urtwn_next_calib(void *cookie)
918{
919 struct urtwn_softc *sc = cookie;
920
921 if (!usbd_is_dying(sc->sc_udev))
922 timeout_add_sec(&sc->calib_to, 2);
923}
924
925void
926urtwn_cancel_calib(void *cookie)
927{
928 struct urtwn_softc *sc = cookie;
929
930 if (timeout_initialized(&sc->calib_to)((&sc->calib_to)->to_flags & 0x04))
931 timeout_del(&sc->calib_to);
932}
933
934void
935urtwn_scan_to(void *arg)
936{
937 struct urtwn_softc *sc = arg;
938
939 if (usbd_is_dying(sc->sc_udev))
940 return;
941
942 usbd_ref_incr(sc->sc_udev);
943 rtwn_next_scan(&sc->sc_sc);
944 usbd_ref_decr(sc->sc_udev);
945}
946
947void
948urtwn_next_scan(void *arg)
949{
950 struct urtwn_softc *sc = arg;
951
952 if (!usbd_is_dying(sc->sc_udev))
953 timeout_add_msec(&sc->scan_to, 200);
954}
955
956void
957urtwn_cancel_scan(void *cookie)
958{
959 struct urtwn_softc *sc = cookie;
960
961 if (timeout_initialized(&sc->scan_to)((&sc->scan_to)->to_flags & 0x04))
962 timeout_del(&sc->scan_to);
963}
964
965int
966urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
967{
968 struct rtwn_softc *sc_sc = ic->ic_softcic_ac.ac_if.if_softc;
969 struct device *self = sc_sc->sc_pdev;
970 struct urtwn_softc *sc = (struct urtwn_softc *)self;
971 struct urtwn_cmd_newstate cmd;
972
973 /* Do it in a process context. */
974 cmd.state = nstate;
975 cmd.arg = arg;
976 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd));
977 return (0);
978}
979
980void
981urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
982{
983 struct urtwn_cmd_newstate *cmd = arg;
984 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
985
986 rtwn_newstate(ic, cmd->state, cmd->arg);
987}
988
989void
990urtwn_updateslot(struct ieee80211com *ic)
991{
992 struct rtwn_softc *sc_sc = ic->ic_softcic_ac.ac_if.if_softc;
993 struct device *self = sc_sc->sc_pdev;
994 struct urtwn_softc *sc = (struct urtwn_softc *)self;
995
996 /* Do it in a process context. */
997 urtwn_do_async(sc, urtwn_updateslot_cb, NULL((void *)0), 0);
998}
999
1000/* ARGSUSED */
1001void
1002urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg)
1003{
1004 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1005
1006 rtwn_updateslot(ic);
1007}
1008
1009void
1010urtwn_updateedca(struct ieee80211com *ic)
1011{
1012 struct rtwn_softc *sc_sc = ic->ic_softcic_ac.ac_if.if_softc;
1013 struct device *self = sc_sc->sc_pdev;
1014 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1015
1016 /* Do it in a process context. */
1017 urtwn_do_async(sc, urtwn_updateedca_cb, NULL((void *)0), 0);
1018}
1019
1020/* ARGSUSED */
1021void
1022urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg)
1023{
1024 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1025
1026 rtwn_updateedca(ic);
1027}
1028
1029int
1030urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1031 struct ieee80211_key *k)
1032{
1033 struct rtwn_softc *sc_sc = ic->ic_softcic_ac.ac_if.if_softc;
1034 struct device *self = sc_sc->sc_pdev;
1035 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1036 struct urtwn_cmd_key cmd;
1037
1038 /* Only handle keys for CCMP */
1039 if (k->k_cipher != IEEE80211_CIPHER_CCMP)
1040 return ieee80211_set_key(ic, ni, k);
1041
1042 /* Defer setting of WEP keys until interface is brought up. */
1043 if ((ic->ic_ific_ac.ac_if.if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) !=
1044 (IFF_UP0x1 | IFF_RUNNING0x40))
1045 return (0);
1046
1047 /* Do it in a process context. */
1048 cmd.key = *k;
1049 cmd.ni = ni;
1050 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd));
1051 sc->sc_key_tasks++;
1052
1053 return (EBUSY16);
1054}
1055
1056void
1057urtwn_set_key_cb(struct urtwn_softc *sc, void *arg)
1058{
1059 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1060 struct urtwn_cmd_key *cmd = arg;
1061
1062 sc->sc_key_tasks--;
1063
1064 if (rtwn_set_key(ic, cmd->ni, &cmd->key) == 0) {
1065 if (sc->sc_key_tasks == 0) {
1066 DPRINTF(("marking port %s valid\n",
1067 ether_sprintf(cmd->ni->ni_macaddr)));
1068 cmd->ni->ni_port_valid = 1;
1069 ieee80211_set_link_state(ic, LINK_STATE_UP4);
1070 }
1071 } else {
1072 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH,((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE
, 0))
1073 IEEE80211_REASON_AUTH_LEAVE)((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE
, 0))
;
1074 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1)));
1075 }
1076}
1077
1078void
1079urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1080 struct ieee80211_key *k)
1081{
1082 struct rtwn_softc *sc_sc = ic->ic_softcic_ac.ac_if.if_softc;
1083 struct device *self = sc_sc->sc_pdev;
1084 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1085 struct urtwn_cmd_key cmd;
1086
1087 /* Only handle keys for CCMP */
1088 if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
1089 ieee80211_delete_key(ic, ni, k);
1090 return;
1091 }
1092
1093 if (!(ic->ic_ific_ac.ac_if.if_flags & IFF_RUNNING0x40) ||
1094 ic->ic_state != IEEE80211_S_RUN)
1095 return; /* Nothing to do. */
1096
1097 /* Do it in a process context. */
1098 cmd.key = *k;
1099 cmd.ni = ni;
1100 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd));
1101}
1102
1103void
1104urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg)
1105{
1106 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1107 struct urtwn_cmd_key *cmd = arg;
1108
1109 rtwn_delete_key(ic, cmd->ni, &cmd->key);
1110}
1111
1112int
1113urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m,
1114 struct ieee80211_node *ni)
1115{
1116 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1117 struct ieee80211_key *k;
1118 struct ieee80211_frame *wh;
1119 uint64_t pn, *prsc;
1120 uint8_t *ivp;
1121 uint8_t tid;
1122 int hdrlen, hasqos;
1123
1124 k = ieee80211_get_rxkey(ic, m, ni);
1125 if (k == NULL((void *)0))
1126 return 1;
1127
1128 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1129 hdrlen = ieee80211_get_hdrlen(wh);
1130 ivp = (uint8_t *)wh + hdrlen;
1131
1132 /* Check that ExtIV bit is set. */
1133 if (!(ivp[3] & IEEE80211_WEP_EXTIV0x20))
1134 return 1;
1135
1136 hasqos = ieee80211_has_qos(wh);
1137 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID0x000f : 0;
1138 prsc = &k->k_rsc[tid];
1139
1140 /* Extract the 48-bit PN from the CCMP header. */
1141 pn = (uint64_t)ivp[0] |
1142 (uint64_t)ivp[1] << 8 |
1143 (uint64_t)ivp[4] << 16 |
1144 (uint64_t)ivp[5] << 24 |
1145 (uint64_t)ivp[6] << 32 |
1146 (uint64_t)ivp[7] << 40;
1147 if (pn <= *prsc) {
1148 ic->ic_stats.is_ccmp_replays++;
1149 return 1;
1150 }
1151 /* Last seen packet number is updated in ieee80211_inputm(). */
1152
1153 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */
1154 m_adj(m, -IEEE80211_CCMP_MICLEN8);
1155 return 0;
1156}
1157
1158void
1159urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen,
1160 struct mbuf_list *ml)
1161{
1162 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1163 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
1164 struct ieee80211_rxinfo rxi;
1165 struct ieee80211_frame *wh;
1166 struct ieee80211_node *ni;
1167 struct r92c_rx_desc_usb *rxd;
1168 uint32_t rxdw0, rxdw3;
1169 struct mbuf *m;
1170 uint8_t rate;
1171 int8_t rssi = 0;
1172 int s, infosz;
1173
1174 rxd = (struct r92c_rx_desc_usb *)buf;
1175 rxdw0 = letoh32(rxd->rxdw0)((__uint32_t)(rxd->rxdw0));
1176 rxdw3 = letoh32(rxd->rxdw3)((__uint32_t)(rxd->rxdw3));
1177
1178 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))__builtin_expect(((rxdw0 & (0x00004000 | 0x00008000)) != 0
), 0)
) {
1179 /*
1180 * This should not happen since we setup our Rx filter
1181 * to not receive these frames.
1182 */
1183 ifp->if_ierrorsif_data.ifi_ierrors++;
1184 return;
1185 }
1186 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)__builtin_expect(((pktlen < sizeof(*wh) || pktlen > (1 <<
11)) != 0), 0)
) {
1187 ifp->if_ierrorsif_data.ifi_ierrors++;
1188 return;
1189 }
1190
1191 rate = MS(rxdw3, R92C_RXDW3_RATE)(((rxdw3) & 0x0000003f) >> 0);
1192 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ)(((rxdw0) & 0x000f0000) >> 16) * 8;
1193
1194 /* Get RSSI from PHY status descriptor if present. */
1195 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST0x04000000)) {
1196 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]);
1197 /* Update our average RSSI. */
1198 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi);
1199 }
1200
1201 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n",
1202 pktlen, rate, infosz, rssi));
1203
1204 MGETHDR(m, M_DONTWAIT, MT_DATA)m = m_gethdr((0x0002), (1));
1205 if (__predict_false(m == NULL)__builtin_expect(((m == ((void *)0)) != 0), 0)) {
1206 ifp->if_ierrorsif_data.ifi_ierrors++;
1207 return;
1208 }
1209 if (pktlen > MHLEN((256 - sizeof(struct m_hdr)) - sizeof(struct pkthdr))) {
1210 MCLGET(m, M_DONTWAIT)(void) m_clget((m), (0x0002), (1 << 11));
1211 if (__predict_false(!(m->m_flags & M_EXT))__builtin_expect(((!(m->m_hdr.mh_flags & 0x0001)) != 0
), 0)
) {
1212 ifp->if_ierrorsif_data.ifi_ierrors++;
1213 m_freem(m);
1214 return;
1215 }
1216 }
1217 /* Finalize mbuf. */
1218 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz);
1219 memcpy(mtod(m, uint8_t *), wh, pktlen)__builtin_memcpy((((uint8_t *)((m)->m_hdr.mh_data))), (wh)
, (pktlen))
;
1220 m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = pktlen;
1221
1222 s = splnet()splraise(0x7);
1223#if NBPFILTER1 > 0
1224 if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) {
1225 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtapsc_rxtapu.th;
1226 struct mbuf mb;
1227
1228 tap->wr_flags = 0;
1229 /* Map HW rate index to 802.11 rate. */
1230 if (!(rxdw3 & R92C_RXDW3_HT0x00000040)) {
1231 switch (rate) {
1232 /* CCK. */
1233 case 0: tap->wr_rate = 2; break;
1234 case 1: tap->wr_rate = 4; break;
1235 case 2: tap->wr_rate = 11; break;
1236 case 3: tap->wr_rate = 22; break;
1237 /* OFDM. */
1238 case 4: tap->wr_rate = 12; break;
1239 case 5: tap->wr_rate = 18; break;
1240 case 6: tap->wr_rate = 24; break;
1241 case 7: tap->wr_rate = 36; break;
1242 case 8: tap->wr_rate = 48; break;
1243 case 9: tap->wr_rate = 72; break;
1244 case 10: tap->wr_rate = 96; break;
1245 case 11: tap->wr_rate = 108; break;
1246 }
1247 if (rate <= 3)
1248 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
1249 } else if (rate >= 12) { /* MCS0~15. */
1250 /* Bit 7 set means HT MCS instead of rate. */
1251 tap->wr_rate = 0x80 | (rate - 12);
1252 }
1253 tap->wr_dbm_antsignal = rssi;
1254 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq)((__uint16_t)(ic->ic_ibss_chan->ic_freq));
1255 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags)((__uint16_t)(ic->ic_ibss_chan->ic_flags));
1256
1257 mb.m_datam_hdr.mh_data = (caddr_t)tap;
1258 mb.m_lenm_hdr.mh_len = sc->sc_rxtap_len;
1259 mb.m_nextm_hdr.mh_next = m;
1260 mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0);
1261 mb.m_typem_hdr.mh_type = 0;
1262 mb.m_flagsm_hdr.mh_flags = 0;
1263 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN(1 << 0));
1264 }
1265#endif
1266
1267 ni = ieee80211_find_rxnode(ic, wh);
1268 rxi.rxi_flags = 0;
1269 rxi.rxi_rssi = rssi;
1270 rxi.rxi_tstamp = 0; /* Unused. */
1271
1272 /* Handle hardware decryption. */
1273 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c) != IEEE80211_FC0_TYPE_CTL0x04)
1274 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) &&
1275 (ni->ni_flags & IEEE80211_NODE_RXPROT0x0008) &&
1276 ((!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1277 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) ||
1278 (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1279 ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) {
1280 if (urtwn_ccmp_decap(sc, m, ni) != 0) {
1281 ifp->if_ierrorsif_data.ifi_ierrors++;
1282 m_freem(m);
1283 ieee80211_release_node(ic, ni);
1284 return;
1285 }
1286 rxi.rxi_flags |= IEEE80211_RXI_HWDEC0x00000001;
1287 }
1288
1289 ieee80211_inputm(ifp, m, ni, &rxi, ml);
1290 /* Node is no longer needed. */
1291 ieee80211_release_node(ic, ni);
1292 splx(s)spllower(s);
1293}
1294
1295void
1296urtwn_rxeof(struct usbd_xfer *xfer, void *priv,
1297 usbd_status status)
1298{
1299 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
1300 struct urtwn_rx_data *data = priv;
1301 struct urtwn_softc *sc = data->sc;
1302 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1303 struct r92c_rx_desc_usb *rxd;
1304 uint32_t rxdw0;
1305 uint8_t *buf;
1306 int len, totlen, pktlen, infosz, npkts, error, align;
1307
1308 if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0
)
) {
1309 DPRINTF(("RX status=%d\n", status));
1310 if (status == USBD_STALLED)
1311 usbd_clear_endpoint_stall_async(sc->rx_pipe);
1312 if (status != USBD_CANCELLED)
1313 goto resubmit;
1314 return;
1315 }
1316 usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &len, NULL((void *)0));
1317
1318 if (__predict_false(len < sizeof(*rxd))__builtin_expect(((len < sizeof(*rxd)) != 0), 0)) {
1319 DPRINTF(("xfer too short %d\n", len));
1320 goto resubmit;
1321 }
1322 buf = data->buf;
1323
1324 /* Get the number of encapsulated frames. */
1325 rxd = (struct r92c_rx_desc_usb *)buf;
1326 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT)(((((__uint32_t)(rxd->rxdw2))) & 0x00ff0000) >> 16
)
;
1327 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts));
1328
1329 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
1330 int ntries, type;
1331 struct r88e_tx_rpt_ccx *rxstat;
1332
1333 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT)(((((__uint32_t)(rxd->rxdw3))) & 0x0000c000) >> 14
)
;
1334
1335 if (type == R88E_RXDW3_RPT_TX11) {
1336 buf += sizeof(struct r92c_rx_desc_usb);
1337 rxstat = (struct r88e_tx_rpt_ccx *)buf;
1338 ntries = MS(letoh32(rxstat->rptb2),(((((__uint32_t)(rxstat->rptb2))) & 0x3f) >> 0)
1339 R88E_RPTB2_RETRY_CNT)(((((__uint32_t)(rxstat->rptb2))) & 0x3f) >> 0);
1340
1341 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK0x40)
1342 sc->amn.amn_txcnt++;
1343 if (ntries > 0)
1344 sc->amn.amn_retrycnt++;
1345
1346 goto resubmit;
1347 }
1348 } else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
1349 int type;
1350 struct r92e_c2h_tx_rpt *txrpt;
1351
1352 if (letoh32(rxd->rxdw2)((__uint32_t)(rxd->rxdw2)) & R92E_RXDW2_RPT_C2H0x10000000) {
1353 if (len < sizeof(struct r92c_rx_desc_usb) + 2)
1354 goto resubmit;
1355
1356 type = buf[sizeof(struct r92c_rx_desc_usb)];
1357 switch (type) {
1358 case R92C_C2HEVT_TX_REPORT3:
1359 buf += sizeof(struct r92c_rx_desc_usb) + 2;
1360 txrpt = (struct r92e_c2h_tx_rpt *)buf;
1361 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT)(((txrpt->rptb2) & 0x3f) >> 0) > 0)
1362 sc->amn.amn_retrycnt++;
1363 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER0x80 |
1364 R92E_RPTB0_LIFE_EXPIRE0x40)) == 0)
1365 sc->amn.amn_txcnt++;
1366 break;
1367 default:
1368 break;
1369 }
1370 goto resubmit;
1371 }
1372 }
1373
1374 align = (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040 ? 7 : 127);
1375
1376 /* Process all of them. */
1377 while (npkts-- > 0) {
1378 if (__predict_false(len < sizeof(*rxd))__builtin_expect(((len < sizeof(*rxd)) != 0), 0))
1379 break;
1380 rxd = (struct r92c_rx_desc_usb *)buf;
1381 rxdw0 = letoh32(rxd->rxdw0)((__uint32_t)(rxd->rxdw0));
1382
1383 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN)(((rxdw0) & 0x00003fff) >> 0);
1384 if (__predict_false(pktlen == 0)__builtin_expect(((pktlen == 0) != 0), 0))
1385 break;
1386
1387 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ)(((rxdw0) & 0x000f0000) >> 16) * 8;
1388
1389 /* Make sure everything fits in xfer. */
1390 totlen = sizeof(*rxd) + infosz + pktlen;
1391 if (__predict_false(totlen > len)__builtin_expect(((totlen > len) != 0), 0))
1392 break;
1393
1394 /* Process 802.11 frame. */
1395 urtwn_rx_frame(sc, buf, pktlen, &ml);
1396
1397 /* Handle chunk alignment. */
1398 totlen = (totlen + align) & ~align;
1399 buf += totlen;
1400 len -= totlen;
1401 }
1402 if_input(&ic->ic_ific_ac.ac_if, &ml);
1403
1404 resubmit:
1405 /* Setup a new transfer. */
1406 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ(16 * 1024),
1407 USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, USBD_NO_TIMEOUT0, urtwn_rxeof);
1408 error = usbd_transfer(data->xfer);
1409 if (error != 0 && error != USBD_IN_PROGRESS)
1410 DPRINTF(("could not set up new transfer: %d\n", error));
1411}
1412
1413void
1414urtwn_txeof(struct usbd_xfer *xfer, void *priv,
1415 usbd_status status)
1416{
1417 struct urtwn_tx_data *data = priv;
1418 struct urtwn_softc *sc = data->sc;
1419 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_ific_ac.ac_if;
1420 int s;
1421
1422 s = splnet()splraise(0x7);
1423 /* Put this Tx buffer back to our free list. */
1424 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next)do { (data)->next.tqe_next = ((void *)0); (data)->next.
tqe_prev = (&sc->tx_free_list)->tqh_last; *(&sc
->tx_free_list)->tqh_last = (data); (&sc->tx_free_list
)->tqh_last = &(data)->next.tqe_next; } while (0)
;
1425
1426 if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0
)
) {
1427 DPRINTF(("TX status=%d\n", status));
1428 if (status == USBD_STALLED)
1429 usbd_clear_endpoint_stall_async(data->pipe);
1430 ifp->if_oerrorsif_data.ifi_oerrors++;
1431 splx(s)spllower(s);
1432 return;
1433 }
1434 sc->sc_sc.sc_tx_timer = 0;
1435
1436 /* We just released a Tx buffer, notify Tx. */
1437 if (ifq_is_oactive(&ifp->if_snd)) {
1438 ifq_clr_oactive(&ifp->if_snd);
1439 rtwn_start(ifp);
1440 }
1441 splx(s)spllower(s);
1442}
1443
1444void
1445urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m,
1446 struct ieee80211_frame *wh, struct ieee80211_key *k,
1447 struct ieee80211_node *ni)
1448{
1449 struct r92c_tx_desc_usb *txd;
1450 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1451 uint8_t raid, type;
1452 uint32_t pktlen;
1453
1454 txd = (struct r92c_tx_desc_usb *)*txdp;
1455 (*txdp) += sizeof(*txd);
1456 memset(txd, 0, sizeof(*txd))__builtin_memset((txd), (0), (sizeof(*txd)));
1457
1458 pktlen = m->m_pkthdrM_dat.MH.MH_pkthdr.len;
1459 if (k != NULL((void *)0) && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1460 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,((__uint32_t)((((3) << 22) & 0x00c00000)))
1461 R92C_TXDW1_CIPHER_AES))((__uint32_t)((((3) << 22) & 0x00c00000)));
1462 pktlen += IEEE80211_CCMP_HDRLEN8;
1463 }
1464
1465 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
1466
1467 txd->txdw0 |= htole32(((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1468 SM(R92C_TXDW0_PKTLEN, pktlen) |((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1469 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1470 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG)((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
;
1471 if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01))
1472 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST)((__uint32_t)(0x01000000));
1473
1474 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1475 type == IEEE80211_FC0_TYPE_DATA0x08) {
1476 if (ic->ic_curmode == IEEE80211_MODE_11B ||
1477 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B0x04))
1478 raid = R92C_RAID_11B6;
1479 else
1480 raid = R92C_RAID_11BG4;
1481 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
1482 txd->txdw1 |= htole32(((__uint32_t)((((0) << 0) & 0x0000003f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1483 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) |((__uint32_t)((((0) << 0) & 0x0000003f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1484 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |((__uint32_t)((((0) << 0) & 0x0000003f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1485 SM(R92C_TXDW1_RAID, raid))((__uint32_t)((((0) << 0) & 0x0000003f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
;
1486 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK)((__uint32_t)(0x00010000));
1487 /* Request TX status report for AMRR */
1488 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT)((__uint32_t)(0x00080000));
1489 } else {
1490 txd->txdw1 |= htole32(((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
) | 0x00000040))
1491 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) |((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
) | 0x00000040))
1492 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
) | 0x00000040))
1493 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK)((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
) | 0x00000040))
;
1494 }
1495
1496 if (pktlen + IEEE80211_CRC_LEN4 > ic->ic_rtsthreshold) {
1497 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |((__uint32_t)(0x00001000 | 0x00002000))
1498 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00001000 | 0x00002000));
1499 } else if (ic->ic_flags & IEEE80211_F_USEPROT0x00100000) {
1500 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1501 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |((__uint32_t)(0x00000800 | 0x00002000))
1502 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00000800 | 0x00002000));
1503 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1504 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |((__uint32_t)(0x00001000 | 0x00002000))
1505 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00001000 | 0x00002000));
1506 }
1507 }
1508 txd->txdw5 |= htole32(0x0001ff00)((__uint32_t)(0x0001ff00));
1509
1510 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
1511 /* Use AMRR */
1512 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE)((__uint32_t)(0x00000100));
1513 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,((__uint32_t)((((ni->ni_txrate) << 0) & 0x0000001f
)))
1514 ni->ni_txrate))((__uint32_t)((((ni->ni_txrate) << 0) & 0x0000001f
)))
;
1515 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,((__uint32_t)((((ni->ni_txrate) << 0) & 0x0000003f
)))
1516 ni->ni_txrate))((__uint32_t)((((ni->ni_txrate) << 0) & 0x0000003f
)))
;
1517 } else {
1518 /* Send RTS at OFDM24 and data at OFDM54. */
1519 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8))((__uint32_t)((((8) << 0) & 0x0000001f)));
1520 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11))((__uint32_t)((((11) << 0) & 0x0000003f)));
1521 }
1522 } else {
1523 txd->txdw1 |= htole32(((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x12) <<
8) & 0x00001f00) | (((6) << 16) & 0x000f0000))
)
1524 SM(R92C_TXDW1_MACID, 0) |((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x12) <<
8) & 0x00001f00) | (((6) << 16) & 0x000f0000))
)
1525 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x12) <<
8) & 0x00001f00) | (((6) << 16) & 0x000f0000))
)
1526 SM(R92C_TXDW1_RAID, R92C_RAID_11B))((__uint32_t)((((0) << 0) & 0x0000001f) | (((0x12) <<
8) & 0x00001f00) | (((6) << 16) & 0x000f0000))
)
;
1527
1528 /* Force CCK1. */
1529 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE)((__uint32_t)(0x00000100));
1530 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0))((__uint32_t)((((0) << 0) & 0x0000003f)));
1531 }
1532 /* Set sequence number (already little endian). */
1533 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT4;
1534
1535 if (!ieee80211_has_qos(wh)) {
1536 /* Use HW sequence numbering for non-QoS frames. */
1537 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ)((__uint32_t)(0x00000080));
1538 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN)((__uint16_t)(0x8000));
1539 } else
1540 txd->txdw4 |= htole32(R92C_TXDW4_QOS)((__uint32_t)(0x00000040));
1541}
1542
1543void
1544urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m,
1545 struct ieee80211_frame *wh, struct ieee80211_key *k,
1546 struct ieee80211_node *ni)
1547{
1548 struct r92e_tx_desc_usb *txd;
1549 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1550 uint8_t raid, type;
1551 uint32_t pktlen;
1552
1553 txd = (struct r92e_tx_desc_usb *)*txdp;
1554 (*txdp) += sizeof(*txd);
1555 memset(txd, 0, sizeof(*txd))__builtin_memset((txd), (0), (sizeof(*txd)));
1556
1557 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
1558
1559 pktlen = m->m_pkthdrM_dat.MH.MH_pkthdr.len;
1560 if (k != NULL((void *)0) && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1561 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,((__uint32_t)((((3) << 22) & 0x00c00000)))
1562 R92C_TXDW1_CIPHER_AES))((__uint32_t)((((3) << 22) & 0x00c00000)));
1563 pktlen += IEEE80211_CCMP_HDRLEN8;
1564 }
1565
1566 txd->txdw0 |= htole32(((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1567 SM(R92C_TXDW0_PKTLEN, pktlen) |((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1568 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
1569 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG)((__uint32_t)((((pktlen) << 0) & 0x0000ffff) | (((sizeof
(*txd)) << 16) & 0x00ff0000) | 0x80000000 | 0x08000000
| 0x04000000))
;
1570 if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01))
1571 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST)((__uint32_t)(0x01000000));
1572
1573 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
1574 type == IEEE80211_FC0_TYPE_DATA0x08) {
1575 if (ic->ic_curmode == IEEE80211_MODE_11B ||
1576 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B0x04))
1577 raid = R92E_RAID_11B8;
1578 else
1579 raid = R92E_RAID_11BG6;
1580 txd->txdw1 |= htole32(((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1581 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) |((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1582 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
1583 SM(R92C_TXDW1_RAID, raid))((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x00) <<
8) & 0x00001f00) | (((raid) << 16) & 0x000f0000
)))
;
1584 /* Request TX status report for AMRR */
1585 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK)((__uint32_t)(0x00080000 | 0x00010000));
1586
1587 if (pktlen + IEEE80211_CRC_LEN4 > ic->ic_rtsthreshold) {
1588 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |((__uint32_t)(0x00001000 | 0x00002000))
1589 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00001000 | 0x00002000));
1590 } else if (ic->ic_flags & IEEE80211_F_USEPROT0x00100000) {
1591 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1592 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |((__uint32_t)(0x00000800 | 0x00002000))
1593 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00000800 | 0x00002000));
1594 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1595 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |((__uint32_t)(0x00001000 | 0x00002000))
1596 R92C_TXDW4_HWRTSEN)((__uint32_t)(0x00001000 | 0x00002000));
1597 }
1598 }
1599 txd->txdw5 |= htole32(0x0001ff00)((__uint32_t)(0x0001ff00));
1600
1601 /* Use AMRR */
1602 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE)((__uint32_t)(0x1000));
1603 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate))((__uint32_t)((((ni->ni_txrate) << 24) & 0x1f000000
)))
;
1604 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate))((__uint32_t)((((ni->ni_txrate) << 0) & 0x0000007f
)))
;
1605 } else {
1606 txd->txdw1 |= htole32(((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x12) <<
8) & 0x00001f00) | (((8) << 16) & 0x000f0000))
)
1607 SM(R92E_TXDW1_MACID, 0) |((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x12) <<
8) & 0x00001f00) | (((8) << 16) & 0x000f0000))
)
1608 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x12) <<
8) & 0x00001f00) | (((8) << 16) & 0x000f0000))
)
1609 SM(R92C_TXDW1_RAID, R92E_RAID_11B))((__uint32_t)((((0) << 0) & 0x0000007f) | (((0x12) <<
8) & 0x00001f00) | (((8) << 16) & 0x000f0000))
)
;
1610
1611 /* Force CCK1. */
1612 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE)((__uint32_t)(0x1000));
1613 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0))((__uint32_t)((((0) << 0) & 0x0000007f)));
1614 }
1615 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f))((__uint32_t)((((0x1f) << 8) & 0x00001f00)));
1616
1617 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq))((__uint16_t)((((*(uint16_t *)wh->i_seq) << 11) &
0x0000ffff)))
;
1618
1619 if (!ieee80211_has_qos(wh)) {
1620 /* Use HW sequence numbering for non-QoS frames. */
1621 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN)((__uint16_t)(0x8000));
1622 }
1623}
1624
1625int
1626urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni)
1627{
1628 struct urtwn_softc *sc = cookie;
1629 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1630 struct ieee80211_frame *wh;
1631 struct ieee80211_key *k = NULL((void *)0);
1632 struct urtwn_tx_data *data;
1633 struct usbd_pipe *pipe;
1634 uint16_t qos, sum;
1635 uint8_t tid, qid;
1636 int i, xferlen, error, headerlen;
1637 uint8_t *txdp;
1638
1639 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1640
1641 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) {
1642 k = ieee80211_get_txkey(ic, wh, ni);
1643 if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
1644 if ((m = ieee80211_encrypt(ic, m, k)) == NULL((void *)0))
1645 return (ENOBUFS55);
1646 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
1647 }
1648 }
1649
1650 if (ieee80211_has_qos(wh)) {
1651 qos = ieee80211_get_qos(wh);
1652 tid = qos & IEEE80211_QOS_TID0x000f;
1653 qid = ieee80211_up_to_ac(ic, tid);
1654 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK0x0c)
1655 != IEEE80211_FC0_TYPE_DATA0x08) {
1656 /* Use AC VO for management frames. */
1657 qid = EDCA_AC_VO;
1658 } else
1659 qid = EDCA_AC_BE;
1660
1661 /* Get the USB pipe to use for this AC. */
1662 pipe = sc->tx_pipe[sc->ac2idx[qid]];
1663
1664 /* Grab a Tx buffer from our free list. */
1665 data = TAILQ_FIRST(&sc->tx_free_list)((&sc->tx_free_list)->tqh_first);
1666 TAILQ_REMOVE(&sc->tx_free_list, data, next)do { if (((data)->next.tqe_next) != ((void *)0)) (data)->
next.tqe_next->next.tqe_prev = (data)->next.tqe_prev; else
(&sc->tx_free_list)->tqh_last = (data)->next.tqe_prev
; *(data)->next.tqe_prev = (data)->next.tqe_next; ((data
)->next.tqe_prev) = ((void *)-1); ((data)->next.tqe_next
) = ((void *)-1); } while (0)
;
1667
1668 /* Fill Tx descriptor. */
1669 txdp = data->buf;
1670 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
1671 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni);
1672 else
1673 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni);
1674
1675 /* Compute Tx descriptor checksum. */
1676 sum = 0;
1677 for (i = 0; i < R92C_TXDESC_SUMSIZE32 / 2; i++)
1678 sum ^= ((uint16_t *)data->buf)[i];
1679 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET14] = sum;
1680
1681#if NBPFILTER1 > 0
1682 if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) {
1683 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtapsc_txtapu.th;
1684 struct mbuf mb;
1685
1686 tap->wt_flags = 0;
1687 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq)((__uint16_t)(ic->ic_bss->ni_chan->ic_freq));
1688 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags)((__uint16_t)(ic->ic_bss->ni_chan->ic_flags));
1689
1690 mb.m_datam_hdr.mh_data = (caddr_t)tap;
1691 mb.m_lenm_hdr.mh_len = sc->sc_txtap_len;
1692 mb.m_nextm_hdr.mh_next = m;
1693 mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0);
1694 mb.m_typem_hdr.mh_type = 0;
1695 mb.m_flagsm_hdr.mh_flags = 0;
1696 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT(1 << 1));
1697 }
1698#endif
1699
1700 if (k != NULL((void *)0) && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1701 xferlen = (txdp - data->buf) + m->m_pkthdrM_dat.MH.MH_pkthdr.len +
1702 IEEE80211_CCMP_HDRLEN8;
1703 headerlen = ieee80211_get_hdrlen(wh);
1704
1705 m_copydata(m, 0, headerlen, txdp);
1706 txdp += headerlen;
1707
1708 k->k_tsc++;
1709 txdp[0] = k->k_tsc;
1710 txdp[1] = k->k_tsc >> 8;
1711 txdp[2] = 0;
1712 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV0x20;
1713 txdp[4] = k->k_tsc >> 16;
1714 txdp[5] = k->k_tsc >> 24;
1715 txdp[6] = k->k_tsc >> 32;
1716 txdp[7] = k->k_tsc >> 40;
1717 txdp += IEEE80211_CCMP_HDRLEN8;
1718
1719 m_copydata(m, headerlen, m->m_pkthdrM_dat.MH.MH_pkthdr.len - headerlen, txdp);
1720 m_freem(m);
1721 } else {
1722 xferlen = (txdp - data->buf) + m->m_pkthdrM_dat.MH.MH_pkthdr.len;
1723 m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, txdp);
1724 m_freem(m);
1725 }
1726
1727 data->pipe = pipe;
1728 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen,
1729 USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, URTWN_TX_TIMEOUT5000,
1730 urtwn_txeof);
1731 error = usbd_transfer(data->xfer);
1732 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)__builtin_expect(((error != USBD_IN_PROGRESS && error
!= 0) != 0), 0)
) {
1733 /* Put this Tx buffer back to our free list. */
1734 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next)do { (data)->next.tqe_next = ((void *)0); (data)->next.
tqe_prev = (&sc->tx_free_list)->tqh_last; *(&sc
->tx_free_list)->tqh_last = (data); (&sc->tx_free_list
)->tqh_last = &(data)->next.tqe_next; } while (0)
;
1735 return (error);
1736 }
1737 ieee80211_release_node(ic, ni);
1738 return (0);
1739}
1740
1741int
1742urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1743{
1744 struct rtwn_softc *sc_sc = ifp->if_softc;
1745 struct device *self = sc_sc->sc_pdev;
1746 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1747 int error;
1748
1749 if (usbd_is_dying(sc->sc_udev))
1750 return ENXIO6;
1751
1752 usbd_ref_incr(sc->sc_udev);
1753 error = rtwn_ioctl(ifp, cmd, data);
1754 usbd_ref_decr(sc->sc_udev);
1755
1756 return (error);
1757}
1758
1759int
1760urtwn_r92c_power_on(struct urtwn_softc *sc)
1761{
1762 uint32_t reg;
1763 int ntries;
1764
1765 /* Wait for autoload done bit. */
1766 for (ntries = 0; ntries < 1000; ntries++) {
1767 if (urtwn_read_1(sc, R92C_APS_FSMCO0x004) & R92C_APS_FSMCO_PFM_ALDN0x00000002)
1768 break;
1769 DELAY(5)(*delay_func)(5);
1770 }
1771 if (ntries == 1000) {
1772 printf("%s: timeout waiting for chip autoload\n",
1773 sc->sc_dev.dv_xname);
1774 return (ETIMEDOUT60);
1775 }
1776
1777 /* Unlock ISO/CLK/Power control register. */
1778 urtwn_write_1(sc, R92C_RSV_CTRL0x01c, 0);
1779 /* Move SPS into PWM mode. */
1780 urtwn_write_1(sc, R92C_SPS0_CTRL0x011, 0x2b);
1781 DELAY(100)(*delay_func)(100);
1782
1783 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL0x021);
1784 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN0x01)) {
1785 urtwn_write_1(sc, R92C_LDOV12D_CTRL0x021,
1786 reg | R92C_LDOV12D_CTRL_LDV12_EN0x01);
1787 DELAY(100)(*delay_func)(100);
1788 urtwn_write_1(sc, R92C_SYS_ISO_CTRL0x000,
1789 urtwn_read_1(sc, R92C_SYS_ISO_CTRL0x000) &
1790 ~R92C_SYS_ISO_CTRL_MD2PP0x0001);
1791 }
1792
1793 /* Auto enable WLAN. */
1794 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1795 urtwn_read_2(sc, R92C_APS_FSMCO0x004) | R92C_APS_FSMCO_APFM_ONMAC0x00000100);
1796 for (ntries = 0; ntries < 1000; ntries++) {
1797 if (!(urtwn_read_2(sc, R92C_APS_FSMCO0x004) &
1798 R92C_APS_FSMCO_APFM_ONMAC0x00000100))
1799 break;
1800 DELAY(5)(*delay_func)(5);
1801 }
1802 if (ntries == 1000) {
1803 printf("%s: timeout waiting for MAC auto ON\n",
1804 sc->sc_dev.dv_xname);
1805 return (ETIMEDOUT60);
1806 }
1807
1808 /* Enable radio, GPIO and LED functions. */
1809 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1810 R92C_APS_FSMCO_AFSM_HSUS0x00000800 |
1811 R92C_APS_FSMCO_PDN_EN0x00000010 |
1812 R92C_APS_FSMCO_PFM_ALDN0x00000002);
1813 /* Release RF digital isolation. */
1814 urtwn_write_2(sc, R92C_SYS_ISO_CTRL0x000,
1815 urtwn_read_2(sc, R92C_SYS_ISO_CTRL0x000) & ~R92C_SYS_ISO_CTRL_DIOR0x0200);
1816
1817 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1818 reg = urtwn_read_2(sc, R92C_CR0x100);
1819 reg |= R92C_CR_HCI_TXDMA_EN0x00000001 | R92C_CR_HCI_RXDMA_EN0x00000002 |
1820 R92C_CR_TXDMA_EN0x00000004 | R92C_CR_RXDMA_EN0x00000008 | R92C_CR_PROTOCOL_EN0x00000010 |
1821 R92C_CR_SCHEDULE_EN0x00000020 | R92C_CR_MACTXEN0x00000040 | R92C_CR_MACRXEN0x00000080 |
1822 R92C_CR_ENSEC0x00000200;
1823 urtwn_write_2(sc, R92C_CR0x100, reg);
1824
1825 urtwn_write_1(sc, 0xfe10, 0x19);
1826 return (0);
1827}
1828
1829int
1830urtwn_r92e_power_on(struct urtwn_softc *sc)
1831{
1832 uint32_t reg;
1833 int ntries;
1834
1835 if (urtwn_read_4(sc, R92C_SYS_CFG0x0f0) & R92E_SYS_CFG_SPSLDO_SEL0x01000000) {
1836 /* LDO. */
1837 urtwn_write_1(sc, R92E_LDO_SWR_CTRL0x07c, 0xc3);
1838 } else {
1839 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL20x014);
1840 reg &= 0xff0fffff;
1841 reg |= 0x00500000;
1842 urtwn_write_4(sc, R92C_SYS_SWR_CTRL20x014, reg);
1843 urtwn_write_1(sc, R92E_LDO_SWR_CTRL0x07c, 0x83);
1844 }
1845
1846 /* 40MHz crystal source */
1847 urtwn_write_1(sc, R92C_AFE_PLL_CTRL0x028,
1848 urtwn_read_1(sc, R92C_AFE_PLL_CTRL0x028) & 0xfb);
1849 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT0x078,
1850 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT0x078) & 0xfffffc7f);
1851
1852 urtwn_write_1(sc, R92C_AFE_PLL_CTRL0x028,
1853 urtwn_read_1(sc, R92C_AFE_PLL_CTRL0x028) & 0xbf);
1854 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT0x078,
1855 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT0x078) & 0xffdfffff);
1856
1857 /* Disable HWPDN. */
1858 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1859 urtwn_read_2(sc, R92C_APS_FSMCO0x004) & ~R92C_APS_FSMCO_APDM_HPDN0x00008000);
1860 for (ntries = 0; ntries < 5000; ntries++) {
1861 if (urtwn_read_4(sc, R92C_APS_FSMCO0x004) & R92C_APS_FSMCO_SUS_HOST0x00020000)
1862 break;
1863 DELAY(10)(*delay_func)(10);
1864 }
1865 if (ntries == 5000) {
1866 printf("%s: timeout waiting for chip power up\n",
1867 sc->sc_dev.dv_xname);
1868 return (ETIMEDOUT60);
1869 }
1870
1871 /* Disable WL suspend. */
1872 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1873 urtwn_read_2(sc, R92C_APS_FSMCO0x004) &
1874 ~(R92C_APS_FSMCO_AFSM_HSUS0x00000800 | R92C_APS_FSMCO_AFSM_PCIE0x00001000));
1875
1876 /* Auto enable WLAN. */
1877 urtwn_write_4(sc, R92C_APS_FSMCO0x004,
1878 urtwn_read_4(sc, R92C_APS_FSMCO0x004) | R92C_APS_FSMCO_RDY_MACON0x00010000);
1879 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1880 urtwn_read_2(sc, R92C_APS_FSMCO0x004) | R92C_APS_FSMCO_APFM_ONMAC0x00000100);
1881 for (ntries = 0; ntries < 5000; ntries++) {
1882 if (!(urtwn_read_2(sc, R92C_APS_FSMCO0x004) &
1883 R92C_APS_FSMCO_APFM_ONMAC0x00000100))
1884 break;
1885 DELAY(10)(*delay_func)(10);
1886 }
1887 if (ntries == 5000) {
1888 printf("%s: timeout waiting for MAC auto ON\n",
1889 sc->sc_dev.dv_xname);
1890 return (ETIMEDOUT60);
1891 }
1892
1893 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1894 urtwn_write_2(sc, R92C_CR0x100, 0);
1895 reg = urtwn_read_2(sc, R92C_CR0x100);
1896 reg |= R92C_CR_HCI_TXDMA_EN0x00000001 | R92C_CR_HCI_RXDMA_EN0x00000002 |
1897 R92C_CR_TXDMA_EN0x00000004 | R92C_CR_RXDMA_EN0x00000008 | R92C_CR_PROTOCOL_EN0x00000010 |
1898 R92C_CR_SCHEDULE_EN0x00000020 | R92C_CR_ENSEC0x00000200 | R92C_CR_CALTMR_EN0x00000400;
1899 urtwn_write_2(sc, R92C_CR0x100, reg);
1900 return (0);
1901}
1902
1903int
1904urtwn_r88e_power_on(struct urtwn_softc *sc)
1905{
1906 uint32_t reg;
1907 int ntries;
1908
1909 /* Wait for power ready bit. */
1910 for (ntries = 0; ntries < 5000; ntries++) {
1911 if (urtwn_read_4(sc, R92C_APS_FSMCO0x004) & R92C_APS_FSMCO_SUS_HOST0x00020000)
1912 break;
1913 DELAY(10)(*delay_func)(10);
1914 }
1915 if (ntries == 5000) {
1916 printf("%s: timeout waiting for chip power up\n",
1917 sc->sc_dev.dv_xname);
1918 return (ETIMEDOUT60);
1919 }
1920
1921 /* Reset BB. */
1922 urtwn_write_1(sc, R92C_SYS_FUNC_EN0x002,
1923 urtwn_read_1(sc, R92C_SYS_FUNC_EN0x002) & ~(R92C_SYS_FUNC_EN_BBRSTB0x0001 |
1924 R92C_SYS_FUNC_EN_BB_GLB_RST0x0002));
1925
1926 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL0x024 + 2,
1927 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL0x024 + 2) | 0x80);
1928
1929 /* Disable HWPDN. */
1930 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1931 urtwn_read_2(sc, R92C_APS_FSMCO0x004) & ~R92C_APS_FSMCO_APDM_HPDN0x00008000);
1932 /* Disable WL suspend. */
1933 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1934 urtwn_read_2(sc, R92C_APS_FSMCO0x004) &
1935 ~(R92C_APS_FSMCO_AFSM_HSUS0x00000800 | R92C_APS_FSMCO_AFSM_PCIE0x00001000));
1936
1937 /* Auto enable WLAN. */
1938 urtwn_write_2(sc, R92C_APS_FSMCO0x004,
1939 urtwn_read_2(sc, R92C_APS_FSMCO0x004) | R92C_APS_FSMCO_APFM_ONMAC0x00000100);
1940 for (ntries = 0; ntries < 5000; ntries++) {
1941 if (!(urtwn_read_2(sc, R92C_APS_FSMCO0x004) &
1942 R92C_APS_FSMCO_APFM_ONMAC0x00000100))
1943 break;
1944 DELAY(10)(*delay_func)(10);
1945 }
1946 if (ntries == 5000) {
1947 printf("%s: timeout waiting for MAC auto ON\n",
1948 sc->sc_dev.dv_xname);
1949 return (ETIMEDOUT60);
1950 }
1951
1952 /* Enable LDO normal mode. */
1953 urtwn_write_1(sc, R92C_LPLDO_CTRL0x023,
1954 urtwn_read_1(sc, R92C_LPLDO_CTRL0x023) & ~0x10);
1955
1956 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1957 urtwn_write_2(sc, R92C_CR0x100, 0);
1958 reg = urtwn_read_2(sc, R92C_CR0x100);
1959 reg |= R92C_CR_HCI_TXDMA_EN0x00000001 | R92C_CR_HCI_RXDMA_EN0x00000002 |
1960 R92C_CR_TXDMA_EN0x00000004 | R92C_CR_RXDMA_EN0x00000008 | R92C_CR_PROTOCOL_EN0x00000010 |
1961 R92C_CR_SCHEDULE_EN0x00000020 | R92C_CR_ENSEC0x00000200 | R92C_CR_CALTMR_EN0x00000400;
1962 urtwn_write_2(sc, R92C_CR0x100, reg);
1963 return (0);
1964}
1965
1966int
1967urtwn_llt_init(struct urtwn_softc *sc, int page_count)
1968{
1969 int i, error, pktbuf_count;
1970
1971 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) ?
1972 R88E_TXPKTBUF_COUNT177 : R92C_TXPKTBUF_COUNT256;
1973
1974 /* Reserve pages [0; page_count]. */
1975 for (i = 0; i < page_count; i++) {
1976 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1977 return (error);
1978 }
1979 /* NB: 0xff indicates end-of-list. */
1980 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
1981 return (error);
1982 /*
1983 * Use pages [page_count + 1; pktbuf_count - 1]
1984 * as ring buffer.
1985 */
1986 for (++i; i < pktbuf_count - 1; i++) {
1987 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1988 return (error);
1989 }
1990 /* Make the last page point to the beginning of the ring buffer. */
1991 error = urtwn_llt_write(sc, i, page_count + 1);
1992 return (error);
1993}
1994
1995int
1996urtwn_auto_llt_init(struct urtwn_softc *sc)
1997{
1998 int ntries;
1999
2000 urtwn_write_4(sc, R92E_AUTO_LLT0x224, urtwn_read_4(sc,
2001 R92E_AUTO_LLT0x224) | R92E_AUTO_LLT_EN0x00010000);
2002 for (ntries = 0; ntries < 1000; ntries++) {
2003 if (!(urtwn_read_4(sc, R92E_AUTO_LLT0x224) & R92E_AUTO_LLT_EN0x00010000))
2004 return (0);
2005 DELAY(2)(*delay_func)(2);
2006 }
2007
2008 return (ETIMEDOUT60);
2009}
2010
2011int
2012urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len)
2013{
2014 struct urtwn_softc *sc = cookie;
2015 uint32_t reg;
2016 int off, mlen, error = 0;
2017
2018 reg = urtwn_read_4(sc, R92C_MCUFWDL0x080);
2019 reg = RW(reg, R92C_MCUFWDL_PAGE, page)(((reg) & ~0x00070000) | (((page) << 16) & 0x00070000
))
;
2020 urtwn_write_4(sc, R92C_MCUFWDL0x080, reg);
2021
2022 off = R92C_FW_START_ADDR0x1000;
2023 while (len > 0) {
2024 if (len > 196)
2025 mlen = 196;
2026 else if (len > 4)
2027 mlen = 4;
2028 else
2029 mlen = 1;
2030 error = urtwn_write_region_1(sc, off, buf, mlen);
2031 if (error != 0)
2032 break;
2033 off += mlen;
2034 buf += mlen;
2035 len -= mlen;
2036 }
2037 return (error);
2038}
2039
2040int
2041urtwn_load_firmware(void *cookie, u_char **fw, size_t *len)
2042{
2043 struct urtwn_softc *sc = cookie;
2044 const char *name;
2045 int error;
2046
2047 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
2048 name = "urtwn-rtl8192eu";
2049 else if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020)
2050 name = "urtwn-rtl8188eu";
2051 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT0x00000008 | RTWN_CHIP_92C0x00000001)) ==
2052 RTWN_CHIP_UMC_A_CUT0x00000008)
2053 name = "urtwn-rtl8192cU";
2054 else
2055 name = "urtwn-rtl8192cT";
2056
2057 error = loadfirmware(name, fw, len);
2058 if (error)
2059 printf("%s: could not read firmware %s (error %d)\n",
2060 sc->sc_dev.dv_xname, name, error);
2061 return (error);
2062}
2063
2064int
2065urtwn_dma_init(void *cookie)
2066{
2067 struct urtwn_softc *sc = cookie;
2068 uint32_t reg;
2069 uint16_t dmasize;
2070 int hqpages, lqpages, nqpages, pagecnt, boundary;
2071 int error, hashq, haslq, hasnq;
2072
2073 /* Default initialization of chipset values. */
2074 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
2075 hqpages = R88E_HQ_NPAGES0;
2076 lqpages = R88E_LQ_NPAGES9;
2077 nqpages = R88E_NQ_NPAGES0;
2078 pagecnt = R88E_TX_PAGE_COUNT168;
2079 boundary = R88E_TX_PAGE_BOUNDARY(168 + 1);
2080 dmasize = R88E_MAX_RX_DMA_SIZE0x2400;
2081 } else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2082 hqpages = R92E_HQ_NPAGES16;
2083 lqpages = R92E_LQ_NPAGES16;
2084 nqpages = R92E_NQ_NPAGES16;
2085 pagecnt = R92E_TX_PAGE_COUNT248;
2086 boundary = R92E_TX_PAGE_BOUNDARY(248 + 1);
2087 dmasize = R92E_MAX_RX_DMA_SIZE0x3fc0;
2088 } else {
2089 hqpages = R92C_HQ_NPAGES12;
2090 lqpages = R92C_LQ_NPAGES2;
2091 nqpages = R92C_NQ_NPAGES2;
2092 pagecnt = R92C_TX_PAGE_COUNT248;
2093 boundary = R92C_TX_PAGE_BOUNDARY(248 + 1);
2094 dmasize = R92C_MAX_RX_DMA_SIZE0x2800;
2095 }
2096
2097 /* Initialize LLT table. */
2098 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2099 error = urtwn_auto_llt_init(sc);
2100 } else {
2101 error = urtwn_llt_init(sc, pagecnt);
2102 }
2103 if (error != 0)
2104 return (error);
2105
2106 /* Get Tx queues to USB endpoints mapping. */
2107 hashq = hasnq = haslq = 0;
2108 switch (sc->ntx) {
2109 case 3:
2110 haslq = 1;
2111 pagecnt -= lqpages;
2112 /* FALLTHROUGH */
2113 case 2:
2114 hasnq = 1;
2115 pagecnt -= nqpages;
2116 /* FALLTHROUGH */
2117 case 1:
2118 hashq = 1;
2119 pagecnt -= hqpages;
2120 break;
2121 }
2122
2123 /* Set number of pages for normal priority queue. */
2124 urtwn_write_1(sc, R92C_RQPN_NPQ0x214, hasnq ? nqpages : 0);
2125 urtwn_write_4(sc, R92C_RQPN0x200,
2126 /* Set number of pages for public queue. */
2127 SM(R92C_RQPN_PUBQ, pagecnt)(((pagecnt) << 16) & 0x00ff0000) |
2128 /* Set number of pages for high priority queue. */
2129 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0)(((hashq ? hqpages : 0) << 0) & 0x000000ff) |
2130 /* Set number of pages for low priority queue. */
2131 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0)(((haslq ? lqpages : 0) << 8) & 0x0000ff00) |
2132 /* Load values. */
2133 R92C_RQPN_LD0x80000000);
2134
2135 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY0x424, boundary);
2136 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY0x425, boundary);
2137 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD0x45d, boundary);
2138 urtwn_write_1(sc, R92C_TRXFF_BNDY0x114, boundary);
2139 urtwn_write_1(sc, R92C_TDECTRL0x208 + 1, boundary);
2140
2141 /* Set queue to USB pipe mapping. */
2142 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL0x10c);
2143 reg &= ~R92C_TRXDMA_CTRL_QMAP_M0xfff0;
2144 if (haslq)
2145 reg |= R92C_TRXDMA_CTRL_QMAP_3EP0xf5b0;
2146 else if (hashq) {
2147 if (!hasnq)
2148 reg |= R92C_TRXDMA_CTRL_QMAP_HQ0xfff0;
2149 else
2150 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ0xfaf0;
2151 }
2152 urtwn_write_2(sc, R92C_TRXDMA_CTRL0x10c, reg);
2153
2154 /* Set Tx/Rx transfer page boundary. */
2155 urtwn_write_2(sc, R92C_TRXFF_BNDY0x114 + 2, dmasize - 1);
2156
2157 if (!(sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)) {
2158 /* Set Tx/Rx transfer page size. */
2159 urtwn_write_1(sc, R92C_PBP0x104,
2160 SM(R92C_PBP_PSRX, R92C_PBP_128)(((1) << 0) & 0x0f) |
2161 SM(R92C_PBP_PSTX, R92C_PBP_128)(((1) << 4) & 0xf0));
2162 }
2163 return (error);
2164}
2165
2166void
2167urtwn_aggr_init(void *cookie)
2168{
2169 struct urtwn_softc *sc = cookie;
2170 uint32_t reg = 0;
2171 int dmasize, dmatiming, ndesc;
2172
2173 /* Set burst packet length. */
2174 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
2175 urtwn_burstlen_init(sc);
2176
2177 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2178 dmasize = 6;
2179 dmatiming = 32;
2180 ndesc = 3;
2181 } else {
2182 dmasize = 48;
2183 dmatiming = 4;
2184 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) ? 1 : 6;
2185 }
2186
2187 /* Tx aggregation setting. */
2188 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2189 urtwn_write_1(sc, R92E_DWBCN1_CTRL0x228, ndesc << 1);
2190 } else {
2191 reg = urtwn_read_4(sc, R92C_TDECTRL0x208);
2192 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc)(((reg) & ~0x000000f0) | (((ndesc) << 4) & 0x000000f0
))
;
2193 urtwn_write_4(sc, R92C_TDECTRL0x208, reg);
2194 }
2195
2196 /* Rx aggregation setting. */
2197 if (!(sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)) {
2198 urtwn_write_1(sc, R92C_TRXDMA_CTRL0x10c,
2199 urtwn_read_1(sc, R92C_TRXDMA_CTRL0x10c) |
2200 R92C_TRXDMA_CTRL_RXDMA_AGG_EN0x0004);
2201 }
2202
2203 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH0x280, dmasize);
2204 if (sc->sc_sc.chip & (RTWN_CHIP_92C0x00000001 | RTWN_CHIP_88C0x00000010))
2205 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO0xfe5b, dmatiming);
2206 else
2207 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH0x280 + 1, dmatiming);
2208
2209 /* Drop incorrect bulk out. */
2210 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK0x20c,
2211 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK0x20c) |
2212 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN0x00000200);
2213}
2214
2215void
2216urtwn_mac_init(void *cookie)
2217{
2218 struct urtwn_softc *sc = cookie;
2219 int i;
2220
2221 /* Write MAC initialization values. */
2222 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
2223 for (i = 0; i < nitems(rtl8188eu_mac)(sizeof((rtl8188eu_mac)) / sizeof((rtl8188eu_mac)[0])); i++) {
2224 urtwn_write_1(sc, rtl8188eu_mac[i].reg,
2225 rtl8188eu_mac[i].val);
2226 }
2227 urtwn_write_1(sc, R92C_MAX_AGGR_NUM0x4ca, 0x07);
2228 } else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2229 for (i = 0; i < nitems(rtl8192eu_mac)(sizeof((rtl8192eu_mac)) / sizeof((rtl8192eu_mac)[0])); i++) {
2230 urtwn_write_1(sc, rtl8192eu_mac[i].reg,
2231 rtl8192eu_mac[i].val);
2232 }
2233 } else {
2234 for (i = 0; i < nitems(rtl8192cu_mac)(sizeof((rtl8192cu_mac)) / sizeof((rtl8192cu_mac)[0])); i++)
2235 urtwn_write_1(sc, rtl8192cu_mac[i].reg,
2236 rtl8192cu_mac[i].val);
2237 }
2238}
2239
2240void
2241urtwn_bb_init(void *cookie)
2242{
2243 struct urtwn_softc *sc = cookie;
2244 const struct r92c_bb_prog *prog;
2245 uint32_t reg;
2246 uint8_t xtal;
2247 int i;
2248
2249 /* Enable BB and RF. */
2250 urtwn_write_2(sc, R92C_SYS_FUNC_EN0x002,
2251 urtwn_read_2(sc, R92C_SYS_FUNC_EN0x002) |
2252 R92C_SYS_FUNC_EN_BBRSTB0x0001 | R92C_SYS_FUNC_EN_BB_GLB_RST0x0002 |
2253 R92C_SYS_FUNC_EN_DIO_RF0x2000);
2254
2255 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E0x00000020 | RTWN_CHIP_92E0x00000040)))
2256 urtwn_write_2(sc, R92C_AFE_PLL_CTRL0x028, 0xdb83);
2257
2258 urtwn_write_1(sc, R92C_RF_CTRL0x01f,
2259 R92C_RF_CTRL_EN0x01 | R92C_RF_CTRL_RSTB0x02 | R92C_RF_CTRL_SDMRSTB0x04);
2260 urtwn_write_1(sc, R92C_SYS_FUNC_EN0x002,
2261 R92C_SYS_FUNC_EN_USBA0x0004 | R92C_SYS_FUNC_EN_USBD0x0010 |
2262 R92C_SYS_FUNC_EN_BB_GLB_RST0x0002 | R92C_SYS_FUNC_EN_BBRSTB0x0001);
2263
2264 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E0x00000020 | RTWN_CHIP_92E0x00000040))) {
2265 urtwn_write_1(sc, R92C_LDOHCI12_CTRL0x022, 0x0f);
2266 urtwn_write_1(sc, 0x15, 0xe9);
2267 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL0x024 + 1, 0x80);
2268 }
2269
2270 /* Select BB programming based on board type. */
2271 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020)
2272 prog = &rtl8188eu_bb_prog;
2273 else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
2274 prog = &rtl8192eu_bb_prog;
2275 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C0x00000001)) {
2276 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD2)
2277 prog = &rtl8188ce_bb_prog;
2278 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA1)
2279 prog = &rtl8188ru_bb_prog;
2280 else
2281 prog = &rtl8188cu_bb_prog;
2282 } else {
2283 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD2)
2284 prog = &rtl8192ce_bb_prog;
2285 else
2286 prog = &rtl8192cu_bb_prog;
2287 }
2288 /* Write BB initialization values. */
2289 for (i = 0; i < prog->count; i++) {
2290 urtwn_bb_writeurtwn_write_4(sc, prog->regs[i], prog->vals[i]);
2291 DELAY(1)(*delay_func)(1);
2292 }
2293
2294 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R0x00000002) {
2295 /* 8192C 1T only configuration. */
2296 reg = urtwn_bb_readurtwn_read_4(sc, R92C_FPGA0_TXINFO0x804);
2297 reg = (reg & ~0x00000003) | 0x2;
2298 urtwn_bb_writeurtwn_write_4(sc, R92C_FPGA0_TXINFO0x804, reg);
2299
2300 reg = urtwn_bb_readurtwn_read_4(sc, R92C_FPGA1_TXINFO0x90c);
2301 reg = (reg & ~0x00300033) | 0x00200022;
2302 urtwn_bb_writeurtwn_write_4(sc, R92C_FPGA1_TXINFO0x90c, reg);
2303
2304 reg = urtwn_bb_readurtwn_read_4(sc, R92C_CCK0_AFESETTING0xa04);
2305 reg = (reg & ~0xff000000) | 0x45 << 24;
2306 urtwn_bb_writeurtwn_write_4(sc, R92C_CCK0_AFESETTING0xa04, reg);
2307
2308 reg = urtwn_bb_readurtwn_read_4(sc, R92C_OFDM0_TRXPATHENA0xc04);
2309 reg = (reg & ~0x000000ff) | 0x23;
2310 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_TRXPATHENA0xc04, reg);
2311
2312 reg = urtwn_bb_readurtwn_read_4(sc, R92C_OFDM0_AGCPARAM10xc70);
2313 reg = (reg & ~0x00000030) | 1 << 4;
2314 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCPARAM10xc70, reg);
2315
2316 reg = urtwn_bb_readurtwn_read_4(sc, 0xe74);
2317 reg = (reg & ~0x0c000000) | 2 << 26;
2318 urtwn_bb_writeurtwn_write_4(sc, 0xe74, reg);
2319 reg = urtwn_bb_readurtwn_read_4(sc, 0xe78);
2320 reg = (reg & ~0x0c000000) | 2 << 26;
2321 urtwn_bb_writeurtwn_write_4(sc, 0xe78, reg);
2322 reg = urtwn_bb_readurtwn_read_4(sc, 0xe7c);
2323 reg = (reg & ~0x0c000000) | 2 << 26;
2324 urtwn_bb_writeurtwn_write_4(sc, 0xe7c, reg);
2325 reg = urtwn_bb_readurtwn_read_4(sc, 0xe80);
2326 reg = (reg & ~0x0c000000) | 2 << 26;
2327 urtwn_bb_writeurtwn_write_4(sc, 0xe80, reg);
2328 reg = urtwn_bb_readurtwn_read_4(sc, 0xe88);
2329 reg = (reg & ~0x0c000000) | 2 << 26;
2330 urtwn_bb_writeurtwn_write_4(sc, 0xe88, reg);
2331 }
2332
2333 /* Write AGC values. */
2334 for (i = 0; i < prog->agccount; i++) {
2335 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCRSSITABLE0xc78,
2336 prog->agcvals[i]);
2337 DELAY(1)(*delay_func)(1);
2338 }
2339
2340 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
2341 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCCORE1(0)(0xc50 + (0) * 8), 0x69553422);
2342 DELAY(1)(*delay_func)(1);
2343 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCCORE1(0)(0xc50 + (0) * 8), 0x69553420);
2344 DELAY(1)(*delay_func)(1);
2345 } else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2346 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCCORE1(0)(0xc50 + (0) * 8), 0x00040022);
2347 DELAY(1)(*delay_func)(1);
2348 urtwn_bb_writeurtwn_write_4(sc, R92C_OFDM0_AGCCORE1(0)(0xc50 + (0) * 8), 0x00040020);
2349 DELAY(1)(*delay_func)(1);
2350 }
2351
2352 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020) {
2353 xtal = sc->sc_sc.crystal_cap & 0x3f;
2354 reg = urtwn_bb_readurtwn_read_4(sc, R92C_AFE_XTAL_CTRL0x024);
2355 urtwn_bb_writeurtwn_write_4(sc, R92C_AFE_XTAL_CTRL0x024,
2356 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)(((reg) & ~0x007ff800) | (((xtal | xtal << 6) <<
11) & 0x007ff800))
);
2357 } else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040) {
2358 xtal = sc->sc_sc.crystal_cap & 0x3f;
2359 reg = urtwn_read_4(sc, R92C_AFE_CTRL30x02c);
2360 reg &= 0xff000fff;
2361 reg |= (xtal | (xtal << 6)) << 12;
2362 urtwn_write_4(sc, R92C_AFE_CTRL30x02c, reg);
2363
2364 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL0x024, 0x000f81fb);
2365 }
2366
2367 if (urtwn_bb_readurtwn_read_4(sc, R92C_HSSI_PARAM2(0)(0x824 + (0) * 8)) & R92C_HSSI_PARAM2_CCK_HIPWR0x00000200)
2368 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR0x01;
2369}
2370
2371void
2372urtwn_burstlen_init(struct urtwn_softc *sc)
2373{
2374 uint8_t reg;
2375
2376 reg = urtwn_read_1(sc, R92E_RXDMA_PRO0x290);
2377 reg &= ~0x30;
2378 switch (sc->sc_udev->speed) {
2379 case USB_SPEED_HIGH3:
2380 urtwn_write_1(sc, R92E_RXDMA_PRO0x290, reg | 0x1e);
2381 break;
2382 default:
2383 urtwn_write_1(sc, R92E_RXDMA_PRO0x290, reg | 0x2e);
2384 break;
2385 }
2386}
2387
2388int
2389urtwn_power_on(void *cookie)
2390{
2391 struct urtwn_softc *sc = cookie;
2392
2393 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020)
2394 return (urtwn_r88e_power_on(sc));
2395 else if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
2396 return (urtwn_r92e_power_on(sc));
2397
2398 return (urtwn_r92c_power_on(sc));
2399}
2400
2401int
2402urtwn_alloc_buffers(void *cookie)
2403{
2404 struct urtwn_softc *sc = cookie;
2405 int error;
2406
2407 /* Init host async commands ring. */
2408 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0;
2409
2410 /* Allocate Tx/Rx buffers. */
2411 error = urtwn_alloc_rx_list(sc);
2412 if (error != 0) {
2413 printf("%s: could not allocate Rx buffers\n",
2414 sc->sc_dev.dv_xname);
2415 return (error);
2416 }
2417 error = urtwn_alloc_tx_list(sc);
2418 if (error != 0) {
2419 printf("%s: could not allocate Tx buffers\n",
2420 sc->sc_dev.dv_xname);
2421 return (error);
2422 }
2423
2424 return (0);
2425}
2426
2427int
2428urtwn_init(void *cookie)
2429{
2430 struct urtwn_softc *sc = cookie;
2431 int i, error;
2432
2433 if (sc->sc_sc.chip & RTWN_CHIP_92E0x00000040)
2434 urtwn_write_1(sc, R92C_ACLK_MON0x03e, 0);
2435
2436 /* Queue Rx xfers. */
2437 for (i = 0; i < URTWN_RX_LIST_COUNT1; i++) {
2438 struct urtwn_rx_data *data = &sc->rx_data[i];
2439
2440 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf,
2441 URTWN_RXBUFSZ(16 * 1024), USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
2442 USBD_NO_TIMEOUT0, urtwn_rxeof);
2443 error = usbd_transfer(data->xfer);
2444 if (error != 0 && error != USBD_IN_PROGRESS)
2445 return (error);
2446 }
2447
2448 ieee80211_amrr_node_init(&sc->amrr, &sc->amn);
2449
2450 /*
2451 * Enable TX reports for AMRR.
2452 * In order to get reports we need to explicitly reset the register.
2453 */
2454 if (sc->sc_sc.chip & RTWN_CHIP_88E0x00000020)
2455 urtwn_write_1(sc, R88E_TX_RPT_CTRL0x4ec, (urtwn_read_1(sc,
2456 R88E_TX_RPT_CTRL0x4ec) & ~0) | R88E_TX_RPT_CTRL_EN0x01);
2457
2458 return (0);
2459}
2460
2461void
2462urtwn_stop(void *cookie)
2463{
2464 struct urtwn_softc *sc = cookie;
2465 int i;
2466
2467 /* Abort Tx. */
2468 for (i = 0; i < R92C_MAX_EPOUT3; i++) {
2469 if (sc->tx_pipe[i] != NULL((void *)0))
2470 usbd_abort_pipe(sc->tx_pipe[i]);
2471 }
2472 /* Stop Rx pipe. */
2473 usbd_abort_pipe(sc->rx_pipe);
2474 /* Free Tx/Rx buffers. */
2475 urtwn_free_tx_list(sc);
2476 urtwn_free_rx_list(sc);
2477}
2478
2479int
2480urtwn_is_oactive(void *cookie)
2481{
2482 struct urtwn_softc *sc = cookie;
2483
2484 return (TAILQ_EMPTY(&sc->tx_free_list)(((&sc->tx_free_list)->tqh_first) == ((void *)0)));
2485}