Bug Summary

File:dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
Warning:line 1164, column 10
Potential leak of memory pointed to by 'enc1'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dcn30_resource.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +sse -target-feature +sse2 -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c

/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c

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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn30_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn20/dcn20_resource.h"
35
36#include "dcn30_resource.h"
37
38#include "dcn10/dcn10_ipp.h"
39#include "dcn30/dcn30_hubbub.h"
40#include "dcn30/dcn30_mpc.h"
41#include "dcn30/dcn30_hubp.h"
42#include "irq/dcn30/irq_service_dcn30.h"
43#include "dcn30/dcn30_dpp.h"
44#include "dcn30/dcn30_optc.h"
45#include "dcn20/dcn20_hwseq.h"
46#include "dcn30/dcn30_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
48#include "dcn30/dcn30_opp.h"
49#include "dcn20/dcn20_dsc.h"
50#include "dcn30/dcn30_vpg.h"
51#include "dcn30/dcn30_afmt.h"
52#include "dcn30/dcn30_dio_stream_encoder.h"
53#include "dcn30/dcn30_dio_link_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "clk_mgr.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn30/dcn30_dccg.h"
62#include "dcn10/dcn10_resource.h"
63#include "dce/dce_panel_cntl.h"
64
65#include "dcn30/dcn30_dwb.h"
66#include "dcn30/dcn30_mmhubbub.h"
67
68#include "sienna_cichlid_ip_offset.h"
69#include "dcn/dcn_3_0_0_offset.h"
70#include "dcn/dcn_3_0_0_sh_mask.h"
71
72#include "nbio/nbio_7_4_offset.h"
73
74#include "dcn/dpcs_3_0_0_offset.h"
75#include "dcn/dpcs_3_0_0_sh_mask.h"
76
77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dmub_abm.h"
82#include "dce/dmub_psr.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85
86#include "dml/dcn30/display_mode_vba_30.h"
87#include "vm_helper.h"
88#include "dcn20/dcn20_vmid.h"
89#include "amdgpu_socbb.h"
90
91#define DC_LOGGER_INIT(logger)
92
93struct _vcs_dpi_ip_params_st dcn3_0_ip = {
94 .use_min_dcfclk = 1,
95 .clamp_min_dcfclk = 0,
96 .odm_capable = 1,
97 .gpuvm_enable = 0,
98 .hostvm_enable = 0,
99 .gpuvm_max_page_table_levels = 4,
100 .hostvm_max_page_table_levels = 4,
101 .hostvm_cached_page_table_levels = 0,
102 .pte_group_size_bytes = 2048,
103 .num_dsc = 6,
104 .rob_buffer_size_kbytes = 184,
105 .det_buffer_size_kbytes = 184,
106 .dpte_buffer_size_in_pte_reqs_luma = 84,
107 .pde_proc_buffer_size_64k_reqs = 48,
108 .dpp_output_buffer_pixels = 2560,
109 .opp_output_buffer_lines = 1,
110 .pixel_chunk_size_kbytes = 8,
111 .pte_enable = 1,
112 .max_page_table_levels = 2,
113 .pte_chunk_size_kbytes = 2, // ?
114 .meta_chunk_size_kbytes = 2,
115 .writeback_chunk_size_kbytes = 8,
116 .line_buffer_size_bits = 789504,
117 .is_line_buffer_bpp_fixed = 0, // ?
118 .line_buffer_fixed_bpp = 0, // ?
119 .dcc_supported = true1,
120 .writeback_interface_buffer_size_kbytes = 90,
121 .writeback_line_buffer_buffer_size = 0,
122 .max_line_buffer_lines = 12,
123 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640
124 .writeback_chroma_buffer_size_kbytes = 8,
125 .writeback_chroma_line_buffer_width_pixels = 4,
126 .writeback_max_hscl_ratio = 1,
127 .writeback_max_vscl_ratio = 1,
128 .writeback_min_hscl_ratio = 1,
129 .writeback_min_vscl_ratio = 1,
130 .writeback_max_hscl_taps = 1,
131 .writeback_max_vscl_taps = 1,
132 .writeback_line_buffer_luma_buffer_size = 0,
133 .writeback_line_buffer_chroma_buffer_size = 14643,
134 .cursor_buffer_size = 8,
135 .cursor_chunk_size = 2,
136 .max_num_otg = 6,
137 .max_num_dpp = 6,
138 .max_num_wb = 1,
139 .max_dchub_pscl_bw_pix_per_clk = 4,
140 .max_pscl_lb_bw_pix_per_clk = 2,
141 .max_lb_vscl_bw_pix_per_clk = 4,
142 .max_vscl_hscl_bw_pix_per_clk = 4,
143 .max_hscl_ratio = 6,
144 .max_vscl_ratio = 6,
145 .hscl_mults = 4,
146 .vscl_mults = 4,
147 .max_hscl_taps = 8,
148 .max_vscl_taps = 8,
149 .dispclk_ramp_margin_percent = 1,
150 .underscan_factor = 1.11,
151 .min_vblank_lines = 32,
152 .dppclk_delay_subtotal = 46,
153 .dynamic_metadata_vm_enabled = true1,
154 .dppclk_delay_scl_lb_only = 16,
155 .dppclk_delay_scl = 50,
156 .dppclk_delay_cnvc_formatter = 27,
157 .dppclk_delay_cnvc_cursor = 6,
158 .dispclk_delay_subtotal = 119,
159 .dcfclk_cstate_latency = 5.2, // SRExitTime
160 .max_inter_dcn_tile_repeaters = 8,
161 .odm_combine_4to1_supported = true1,
162
163 .xfc_supported = false0,
164 .xfc_fill_bw_overhead_percent = 10.0,
165 .xfc_fill_constant_bytes = 0,
166 .gfx7_compat_tiling_supported = 0,
167 .number_of_cursors = 1,
168};
169
170struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
171 .clock_limits = {
172 {
173 .state = 0,
174 .dispclk_mhz = 562.0,
175 .dppclk_mhz = 300.0,
176 .phyclk_mhz = 300.0,
177 .phyclk_d18_mhz = 667.0,
178 .dscclk_mhz = 405.6,
179 },
180 },
181 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
182 .num_states = 1,
183 .sr_exit_time_us = 15.5,
184 .sr_enter_plus_exit_time_us = 20,
185 .urgent_latency_us = 4.0,
186 .urgent_latency_pixel_data_only_us = 4.0,
187 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
188 .urgent_latency_vm_data_only_us = 4.0,
189 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
190 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
191 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
192 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
193 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
194 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
195 .max_avg_sdp_bw_use_normal_percent = 60.0,
196 .max_avg_dram_bw_use_normal_percent = 40.0,
197 .writeback_latency_us = 12.0,
198 .max_request_size_bytes = 256,
199 .fabric_datapath_to_dcn_data_return_bytes = 64,
200 .dcn_downspread_percent = 0.5,
201 .downspread_percent = 0.38,
202 .dram_page_open_time_ns = 50.0,
203 .dram_rw_turnaround_time_ns = 17.5,
204 .dram_return_buffer_per_channel_bytes = 8192,
205 .round_trip_ping_latency_dcfclk_cycles = 191,
206 .urgent_out_of_order_return_per_channel_bytes = 4096,
207 .channel_interleave_bytes = 256,
208 .num_banks = 8,
209 .gpuvm_min_page_size_bytes = 4096,
210 .hostvm_min_page_size_bytes = 4096,
211 .dram_clock_change_latency_us = 404,
212 .dummy_pstate_latency_us = 5,
213 .writeback_dram_clock_change_latency_us = 23.0,
214 .return_bus_width_bytes = 64,
215 .dispclk_dppclk_vco_speed_mhz = 3650,
216 .xfc_bus_transport_time_us = 20, // ?
217 .xfc_xbuf_latency_tolerance_us = 4, // ?
218 .use_urgent_burst_bw = 1, // ?
219 .do_urgent_latency_adjustment = true1,
220 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
221 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
222};
223
224enum dcn30_clk_src_array_id {
225 DCN30_CLK_SRC_PLL0,
226 DCN30_CLK_SRC_PLL1,
227 DCN30_CLK_SRC_PLL2,
228 DCN30_CLK_SRC_PLL3,
229 DCN30_CLK_SRC_PLL4,
230 DCN30_CLK_SRC_PLL5,
231 DCN30_CLK_SRC_TOTAL
232};
233
234/* begin *********************
235 * macros to expend register list macro defined in HW object header file
236 */
237
238/* DCN */
239/* TODO awful hack. fixup dcn20_dwb.h */
240#undef BASE_INNER
241#define BASE_INNER(seg)DCN_BASE__INST0_SEGseg DCN_BASE__INST0_SEG ## seg
242
243#define BASE(seg)DCN_BASE__INST0_SEGseg BASE_INNER(seg)DCN_BASE__INST0_SEGseg
244
245#define SR(reg_name).reg_name = DCN_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\
246 .reg_name = BASE(mm ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \
247 mm ## reg_name
248
249#define SRI(reg_name, block, id).reg_name = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\
250 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
251 mm ## block ## id ## _ ## reg_name
252
253#define SRI2(reg_name, block, id).reg_name = DCN_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\
254 .reg_name = BASE(mm ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \
255 mm ## reg_name
256
257#define SRIR(var_name, reg_name, block, id).var_name = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\
258 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
259 mm ## block ## id ## _ ## reg_name
260
261#define SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX
+ mmblockid_reg_name\
262 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
263 mm ## block ## id ## _ ## reg_name
264
265#define SRII_MPC_RMU(reg_name, block, id).RMU_reg_name[id] = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX
+ mmblockid_reg_name\
266 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
267 mm ## block ## id ## _ ## reg_name
268
269#define SRII_DWB(reg_name, temp_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGmmblockid_temp_name_BASE_IDX
+ mmblockid_temp_name\
270 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## temp_name ## _BASE_IDX + \
271 mm ## block ## id ## _ ## temp_name
272
273#define DCCG_SRII(reg_name, block, id).block_reg_name[id] = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX
+ mmblockid_reg_name\
274 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
275 mm ## block ## id ## _ ## reg_name
276
277#define VUPDATE_SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGmmreg_name_blockid_BASE_IDX
+ mmreg_name_blockid\
278 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## reg_name ## _ ## block ## id ## _BASE_IDX + \
279 mm ## reg_name ## _ ## block ## id
280
281/* NBIO */
282#define NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg \
283 NBIO_BASE__INST0_SEG ## seg
284
285#define NBIO_BASE(seg)NBIO_BASE__INST0_SEGseg \
286 NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg
287
288#define NBIO_SR(reg_name).reg_name = NBIO_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\
289 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX)NBIO_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \
290 mm ## reg_name
291
292/* MMHUB */
293#define MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg \
294 MMHUB_BASE__INST0_SEG ## seg
295
296#define MMHUB_BASE(seg)MMHUB_BASE__INST0_SEGseg \
297 MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg
298
299#define MMHUB_SR(reg_name).reg_name = MMHUB_BASE__INST0_SEGmmMMreg_name_BASE_IDX + mmMMreg_name\
300 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX)MMHUB_BASE__INST0_SEGmmMM ## reg_name ## _BASE_IDX + \
301 mmMM ## reg_name
302
303/* CLOCK */
304#define CLK_BASE_INNER(seg)CLK_BASE__INST0_SEGseg \
305 CLK_BASE__INST0_SEG ## seg
306
307#define CLK_BASE(seg)CLK_BASE__INST0_SEGseg \
308 CLK_BASE_INNER(seg)CLK_BASE__INST0_SEGseg
309
310#define CLK_SRI(reg_name, block, inst).reg_name = CLK_BASE__INST0_SEGmmblock_inst_reg_name_BASE_IDX
+ mmblock_inst_reg_name\
311 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX)CLK_BASE__INST0_SEGmm ## block ## _ ## inst ## _ ## reg_name ##
_BASE_IDX + \
312 mm ## block ## _ ## inst ## _ ## reg_name
313
314
315static const struct bios_registers bios_regs = {
316 NBIO_SR(BIOS_SCRATCH_3).BIOS_SCRATCH_3 = 0x00000014 + 0x003b,
317 NBIO_SR(BIOS_SCRATCH_6).BIOS_SCRATCH_6 = 0x00000014 + 0x003e
318};
319
320#define clk_src_regs(index, pllid)[index] = { .PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX
+ mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 +
0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0
+ 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .PHASE[4] = 0x000000C0
+ 0x0091, .PHASE[5] = 0x000000C0 + 0x0095, .MODULO[0] = 0x000000C0
+ 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0
+ 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0
+ 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL
[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 +
0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL
[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL[4] = 0x000000C0 +
0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}\
321[index] = {\
322 CS_COMMON_REG_LIST_DCN2_0(index, pllid).PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX
+ mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 +
0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0
+ 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .PHASE[4] = 0x000000C0
+ 0x0091, .PHASE[5] = 0x000000C0 + 0x0095, .MODULO[0] = 0x000000C0
+ 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0
+ 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0
+ 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL
[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 +
0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL
[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL[4] = 0x000000C0 +
0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,\
323}
324
325static const struct dce110_clk_src_regs clk_src_regs[] = {
326 clk_src_regs(0, A)[0] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0040, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,},
327 clk_src_regs(1, B)[1] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0041, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,},
328 clk_src_regs(2, C)[2] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0042, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,},
329 clk_src_regs(3, D)[3] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0043, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,},
330 clk_src_regs(4, E)[4] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x004c, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,},
331 clk_src_regs(5, F)[5] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x007e, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE
[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .
PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095
, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 +
0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0
+ 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0
+ 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 +
0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 +
0x0094,}
332};
333
334static const struct dce110_clk_src_shift cs_shift = {
335 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).DP_DTO0_PHASE = 0x0, .DP_DTO0_MODULO = 0x0, .PHYPLLA_DCCG_DEEP_COLOR_CNTL
= 0x4, .DP_DTO0_ENABLE = 0x4
336};
337
338static const struct dce110_clk_src_mask cs_mask = {
339 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK).DP_DTO0_PHASE = 0xFFFFFFFFL, .DP_DTO0_MODULO = 0xFFFFFFFFL, .
PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x00000030L, .DP_DTO0_ENABLE =
0x00000010L
340};
341
342#define abm_regs(id)[id] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX
+ mmABMid_DC_ABM1_HG_SAMPLE_RATE, .DC_ABM1_LS_SAMPLE_RATE = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX
+ mmABMid_DC_ABM1_LS_SAMPLE_RATE, .BL1_PWM_BL_UPDATE_SAMPLE_RATE
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX
+ mmABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE, .DC_ABM1_HG_MISC_CTRL
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX +
mmABMid_DC_ABM1_HG_MISC_CTRL, .DC_ABM1_IPCSC_COEFF_SEL = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX
+ mmABMid_DC_ABM1_IPCSC_COEFF_SEL, .BL1_PWM_CURRENT_ABM_LEVEL
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_CURRENT_ABM_LEVEL, .BL1_PWM_TARGET_ABM_LEVEL
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_TARGET_ABM_LEVEL, .BL1_PWM_USER_LEVEL = DCN_BASE__INST0_SEGmmABMid_BL1_PWM_USER_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_USER_LEVEL, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX
+ mmABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, .DC_ABM1_HGLS_REG_READ_PROGRESS
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX
+ mmABMid_DC_ABM1_HGLS_REG_READ_PROGRESS, .DC_ABM1_ACE_OFFSET_SLOPE_0
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX
+ mmABMid_DC_ABM1_ACE_OFFSET_SLOPE_0, .DC_ABM1_ACE_THRES_12 =
DCN_BASE__INST0_SEGmmABMid_DC_ABM1_ACE_THRES_12_BASE_IDX + mmABMid_DC_ABM1_ACE_THRES_12
, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}\
343[id] = {\
344 ABM_DCN30_REG_LIST(id).MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX
+ mmABMid_DC_ABM1_HG_SAMPLE_RATE, .DC_ABM1_LS_SAMPLE_RATE = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX
+ mmABMid_DC_ABM1_LS_SAMPLE_RATE, .BL1_PWM_BL_UPDATE_SAMPLE_RATE
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX
+ mmABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE, .DC_ABM1_HG_MISC_CTRL
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX +
mmABMid_DC_ABM1_HG_MISC_CTRL, .DC_ABM1_IPCSC_COEFF_SEL = DCN_BASE__INST0_SEGmmABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX
+ mmABMid_DC_ABM1_IPCSC_COEFF_SEL, .BL1_PWM_CURRENT_ABM_LEVEL
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_CURRENT_ABM_LEVEL, .BL1_PWM_TARGET_ABM_LEVEL
= DCN_BASE__INST0_SEGmmABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_TARGET_ABM_LEVEL, .BL1_PWM_USER_LEVEL = DCN_BASE__INST0_SEGmmABMid_BL1_PWM_USER_LEVEL_BASE_IDX
+ mmABMid_BL1_PWM_USER_LEVEL, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX
+ mmABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, .DC_ABM1_HGLS_REG_READ_PROGRESS
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX
+ mmABMid_DC_ABM1_HGLS_REG_READ_PROGRESS, .DC_ABM1_ACE_OFFSET_SLOPE_0
= DCN_BASE__INST0_SEGmmABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX
+ mmABMid_DC_ABM1_ACE_OFFSET_SLOPE_0, .DC_ABM1_ACE_THRES_12 =
DCN_BASE__INST0_SEGmmABMid_DC_ABM1_ACE_THRES_12_BASE_IDX + mmABMid_DC_ABM1_ACE_THRES_12
, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a\
345}
346
347static const struct dce_abm_registers abm_regs[] = {
348 abm_regs(0)[0] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0e97, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0e98, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0e81, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0e8f, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0e84, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0e7d, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0e7c, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0e7b, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0e94, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0e8e, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0e85,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0e8a, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
349 abm_regs(1)[1] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0ed8, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0ed9, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0ec2, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0ed0, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0ec5, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0ebe, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0ebd, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0ebc, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0ed5, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0ecf, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0ec6,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0ecb, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
350 abm_regs(2)[2] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0f19, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0f1a, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0f03, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0f11, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0f06, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0eff, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0efe, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0efd, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0f16, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0f10, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0f07,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0f0c, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
351 abm_regs(3)[3] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0f5a, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0f5b, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0f44, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0f52, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0f47, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0f40, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0f3f, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0f3e, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0f57, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0f51, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0f48,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0f4d, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
352 abm_regs(4)[4] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0f9b, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0f9c, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0f85, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0f93, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0f88, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0f81, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0f80, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0f7f, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0f98, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0f92, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0f89,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0f8e, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
353 abm_regs(5)[5] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG
= 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 +
0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0fdc, .DC_ABM1_LS_SAMPLE_RATE
= 0x00009000 + 0x0fdd, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000
+ 0x0fc6, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0fd4, .DC_ABM1_IPCSC_COEFF_SEL
= 0x00009000 + 0x0fc9, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000
+ 0x0fc2, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0fc1, .
BL1_PWM_USER_LEVEL = 0x00009000 + 0x0fc0, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
= 0x00009000 + 0x0fd9, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000
+ 0x0fd3, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0fca,
.DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0fcf, .BIOS_SCRATCH_2
= 0x00000014 + 0x003a},
354};
355
356static const struct dce_abm_shift abm_shift = {
357 ABM_MASK_SH_LIST_DCN301(__SHIFT).MASTER_COMM_INTERRUPT = 0x0, .MASTER_COMM_CMD_REG_BYTE0 = 0x0
, .MASTER_COMM_CMD_REG_BYTE1 = 0x8, .MASTER_COMM_CMD_REG_BYTE2
= 0x10, .ABM1_HG_NUM_OF_BINS_SEL = 0x0, .ABM1_HG_VMAX_SEL = 0x8
, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x10, .ABM1_IPCSC_COEFF_SEL_R
= 0x10, .ABM1_IPCSC_COEFF_SEL_G = 0x8, .ABM1_IPCSC_COEFF_SEL_B
= 0x0, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0, .BL1_PWM_TARGET_ABM_LEVEL
= 0x0, .BL1_PWM_USER_LEVEL = 0x0, .ABM1_LS_MIN_PIXEL_VALUE_THRES
= 0x0, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x10, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR
= 0x10, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x18, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR
= 0x1f
358};
359
360static const struct dce_abm_mask abm_mask = {
361 ABM_MASK_SH_LIST_DCN301(_MASK).MASTER_COMM_INTERRUPT = 0x00000001L, .MASTER_COMM_CMD_REG_BYTE0
= 0x000000FFL, .MASTER_COMM_CMD_REG_BYTE1 = 0x0000FF00L, .MASTER_COMM_CMD_REG_BYTE2
= 0x00FF0000L, .ABM1_HG_NUM_OF_BINS_SEL = 0x00000003L, .ABM1_HG_VMAX_SEL
= 0x00000100L, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x00030000L,
.ABM1_IPCSC_COEFF_SEL_R = 0x000F0000L, .ABM1_IPCSC_COEFF_SEL_G
= 0x00000F00L, .ABM1_IPCSC_COEFF_SEL_B = 0x0000000FL, .BL1_PWM_CURRENT_ABM_LEVEL
= 0x0001FFFFL, .BL1_PWM_TARGET_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_USER_LEVEL
= 0x0001FFFFL, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x000003FFL,
.ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x03FF0000L, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR
= 0x00010000L, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x01000000L
, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x80000000L
362};
363
364
365
366#define audio_regs(id)[id] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA
= DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}\
367[id] = {\
368 AUD_COMMON_REG_LIST(id).AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA
= DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae\
369}
370
371static const struct dce_audio_registers audio_regs[] = {
372 audio_regs(0)[0] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0386
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0387, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
373 audio_regs(1)[1] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x038c
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x038d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
374 audio_regs(2)[2] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0392
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0393, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
375 audio_regs(3)[3] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0398
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0399, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
376 audio_regs(4)[4] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x039e
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x039f, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
377 audio_regs(5)[5] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03a4
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03a5, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
378 audio_regs(6)[6] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03aa
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03ab, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}
379};
380
381#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh
, .AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh
, .DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh
, .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh
, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh
, .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh
, .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh
, .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh
, .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh
, .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh
, .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh\
382 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh,\
383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh).AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh,\
384 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh).DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh
, .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh
, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh
, .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh
, .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh
, .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh
, .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh
, .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh
, .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh
385
386static const struct dce_audio_shift audio_shift = {
387 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT).AZALIA_ENDPOINT_REG_INDEX = 0x0, .AZALIA_ENDPOINT_REG_DATA =
0x0, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL =
0x4, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO
= 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE
= 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE
= 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES
= 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f
388};
389
390static const struct dce_audio_mask audio_mask = {
391 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK).AZALIA_ENDPOINT_REG_INDEX = 0x00003FFFL, .AZALIA_ENDPOINT_REG_DATA
= 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DCCG_AUDIO_DTO_SEL
= 0x00000030L, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x00100000L
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x01000000L, .DCCG_AUDIO_DTO1_USE_512FBR_DTO
= 0x10000000L, .DCCG_AUDIO_DTO0_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_PHASE
= 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_PHASE
= 0xFFFFFFFFL, .AUDIO_RATE_CAPABILITIES = 0x00000FFFL, .CLKSTOP
= 0x40000000L, .EPSS = 0x80000000L
392};
393
394#define vpg_regs(id)[id] = { .VPG_GENERIC_STATUS = DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_STATUS_BASE_IDX
+ mmVPGid_VPG_GENERIC_STATUS, .VPG_GENERIC_PACKET_ACCESS_CTRL
= DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX
+ mmVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL, .VPG_GENERIC_PACKET_DATA
= DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX
+ mmVPGid_VPG_GENERIC_PACKET_DATA, .VPG_GSP_FRAME_UPDATE_CTRL
= DCN_BASE__INST0_SEGmmVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX
+ mmVPGid_VPG_GSP_FRAME_UPDATE_CTRL}\
395[id] = {\
396 VPG_DCN3_REG_LIST(id).VPG_GENERIC_STATUS = DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_STATUS_BASE_IDX
+ mmVPGid_VPG_GENERIC_STATUS, .VPG_GENERIC_PACKET_ACCESS_CTRL
= DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX
+ mmVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL, .VPG_GENERIC_PACKET_DATA
= DCN_BASE__INST0_SEGmmVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX
+ mmVPGid_VPG_GENERIC_PACKET_DATA, .VPG_GSP_FRAME_UPDATE_CTRL
= DCN_BASE__INST0_SEGmmVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX
+ mmVPGid_VPG_GSP_FRAME_UPDATE_CTRL\
397}
398
399static const struct dcn30_vpg_registers vpg_regs[] = {
400 vpg_regs(0)[0] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x206c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2068, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2069, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x206a},
401 vpg_regs(1)[1] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x216c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2168, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2169, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x216a},
402 vpg_regs(2)[2] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x226c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2268, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2269, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x226a},
403 vpg_regs(3)[3] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x236c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2368, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2369, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x236a},
404 vpg_regs(4)[4] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x246c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2468, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2469, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x246a},
405 vpg_regs(5)[5] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x256c, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x000034C0 + 0x2568, .VPG_GENERIC_PACKET_DATA = 0x000034C0
+ 0x2569, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x256a},
406 vpg_regs(6)[6] = { .VPG_GENERIC_STATUS = 0x00009000 + 0x0935, .VPG_GENERIC_PACKET_ACCESS_CTRL
= 0x00009000 + 0x0931, .VPG_GENERIC_PACKET_DATA = 0x00009000
+ 0x0932, .VPG_GSP_FRAME_UPDATE_CTRL = 0x00009000 + 0x0933},
407};
408
409static const struct dcn30_vpg_shift vpg_shift = {
410 DCN3_VPG_MASK_SH_LIST(__SHIFT).VPG_GENERIC_CONFLICT_OCCURED = 0x1, .VPG_GENERIC_CONFLICT_CLR
= 0x4, .VPG_GENERIC_DATA_INDEX = 0x0, .VPG_GENERIC_DATA_BYTE0
= 0x0, .VPG_GENERIC_DATA_BYTE1 = 0x8, .VPG_GENERIC_DATA_BYTE2
= 0x10, .VPG_GENERIC_DATA_BYTE3 = 0x18, .VPG_GENERIC0_FRAME_UPDATE
= 0x0, .VPG_GENERIC1_FRAME_UPDATE = 0x1, .VPG_GENERIC2_FRAME_UPDATE
= 0x2, .VPG_GENERIC3_FRAME_UPDATE = 0x3, .VPG_GENERIC4_FRAME_UPDATE
= 0x4, .VPG_GENERIC5_FRAME_UPDATE = 0x5, .VPG_GENERIC6_FRAME_UPDATE
= 0x6, .VPG_GENERIC7_FRAME_UPDATE = 0x7, .VPG_GENERIC8_FRAME_UPDATE
= 0x8, .VPG_GENERIC9_FRAME_UPDATE = 0x9, .VPG_GENERIC10_FRAME_UPDATE
= 0xa, .VPG_GENERIC11_FRAME_UPDATE = 0xb, .VPG_GENERIC12_FRAME_UPDATE
= 0xc, .VPG_GENERIC13_FRAME_UPDATE = 0xd, .VPG_GENERIC14_FRAME_UPDATE
= 0xe
411};
412
413static const struct dcn30_vpg_mask vpg_mask = {
414 DCN3_VPG_MASK_SH_LIST(_MASK).VPG_GENERIC_CONFLICT_OCCURED = 0x00000002L, .VPG_GENERIC_CONFLICT_CLR
= 0x00000010L, .VPG_GENERIC_DATA_INDEX = 0x000000FFL, .VPG_GENERIC_DATA_BYTE0
= 0x000000FFL, .VPG_GENERIC_DATA_BYTE1 = 0x0000FF00L, .VPG_GENERIC_DATA_BYTE2
= 0x00FF0000L, .VPG_GENERIC_DATA_BYTE3 = 0xFF000000L, .VPG_GENERIC0_FRAME_UPDATE
= 0x00000001L, .VPG_GENERIC1_FRAME_UPDATE = 0x00000002L, .VPG_GENERIC2_FRAME_UPDATE
= 0x00000004L, .VPG_GENERIC3_FRAME_UPDATE = 0x00000008L, .VPG_GENERIC4_FRAME_UPDATE
= 0x00000010L, .VPG_GENERIC5_FRAME_UPDATE = 0x00000020L, .VPG_GENERIC6_FRAME_UPDATE
= 0x00000040L, .VPG_GENERIC7_FRAME_UPDATE = 0x00000080L, .VPG_GENERIC8_FRAME_UPDATE
= 0x00000100L, .VPG_GENERIC9_FRAME_UPDATE = 0x00000200L, .VPG_GENERIC10_FRAME_UPDATE
= 0x00000400L, .VPG_GENERIC11_FRAME_UPDATE = 0x00000800L, .VPG_GENERIC12_FRAME_UPDATE
= 0x00001000L, .VPG_GENERIC13_FRAME_UPDATE = 0x00002000L, .VPG_GENERIC14_FRAME_UPDATE
= 0x00004000L
415};
416
417#define afmt_regs(id)[id] = { .AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX
+ mmAFMTid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_VBI_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_0_BASE_IDX
+ mmAFMTid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_1_BASE_IDX
+ mmAFMTid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_2_BASE_IDX
+ mmAFMTid_AFMT_60958_2, .AFMT_MEM_PWR = DCN_BASE__INST0_SEGmmAFMTid_AFMT_MEM_PWR_BASE_IDX
+ mmAFMTid_AFMT_MEM_PWR}\
418[id] = {\
419 AFMT_DCN3_REG_LIST(id).AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX
+ mmAFMTid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_VBI_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL
= DCN_BASE__INST0_SEGmmAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
+ mmAFMTid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_0_BASE_IDX
+ mmAFMTid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_1_BASE_IDX
+ mmAFMTid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGmmAFMTid_AFMT_60958_2_BASE_IDX
+ mmAFMTid_AFMT_60958_2, .AFMT_MEM_PWR = DCN_BASE__INST0_SEGmmAFMTid_AFMT_MEM_PWR_BASE_IDX
+ mmAFMTid_AFMT_MEM_PWR\
420}
421
422static const struct dcn30_afmt_registers afmt_regs[] = {
423 afmt_regs(0)[0] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2083, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2074, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2082, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2075,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2085, .AFMT_60958_0
= 0x000034C0 + 0x2078, .AFMT_60958_1 = 0x000034C0 + 0x2079, .
AFMT_60958_2 = 0x000034C0 + 0x207f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2087},
424 afmt_regs(1)[1] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2183, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2174, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2182, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2175,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2185, .AFMT_60958_0
= 0x000034C0 + 0x2178, .AFMT_60958_1 = 0x000034C0 + 0x2179, .
AFMT_60958_2 = 0x000034C0 + 0x217f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2187},
425 afmt_regs(2)[2] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2283, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2274, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2282, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2275,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2285, .AFMT_60958_0
= 0x000034C0 + 0x2278, .AFMT_60958_1 = 0x000034C0 + 0x2279, .
AFMT_60958_2 = 0x000034C0 + 0x227f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2287},
426 afmt_regs(3)[3] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2383, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2374, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2382, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2375,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2385, .AFMT_60958_0
= 0x000034C0 + 0x2378, .AFMT_60958_1 = 0x000034C0 + 0x2379, .
AFMT_60958_2 = 0x000034C0 + 0x237f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2387},
427 afmt_regs(4)[4] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2483, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2474, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2482, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2475,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2485, .AFMT_60958_0
= 0x000034C0 + 0x2478, .AFMT_60958_1 = 0x000034C0 + 0x2479, .
AFMT_60958_2 = 0x000034C0 + 0x247f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2487},
428 afmt_regs(5)[5] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2583, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x2574, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0
+ 0x2582, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2575,
.AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2585, .AFMT_60958_0
= 0x000034C0 + 0x2578, .AFMT_60958_1 = 0x000034C0 + 0x2579, .
AFMT_60958_2 = 0x000034C0 + 0x257f, .AFMT_MEM_PWR = 0x000034C0
+ 0x2587},
429 afmt_regs(6)[6] = { .AFMT_INFOFRAME_CONTROL0 = 0x00009000 + 0x092b, .AFMT_VBI_PACKET_CONTROL
= 0x00009000 + 0x091c, .AFMT_AUDIO_PACKET_CONTROL = 0x00009000
+ 0x092a, .AFMT_AUDIO_PACKET_CONTROL2 = 0x00009000 + 0x091d,
.AFMT_AUDIO_SRC_CONTROL = 0x00009000 + 0x092d, .AFMT_60958_0
= 0x00009000 + 0x0920, .AFMT_60958_1 = 0x00009000 + 0x0921, .
AFMT_60958_2 = 0x00009000 + 0x0927, .AFMT_MEM_PWR = 0x00009000
+ 0x092f},
430};
431
432static const struct dcn30_afmt_shift afmt_shift = {
433 DCN3_AFMT_MASK_SH_LIST(__SHIFT).AFMT_AUDIO_INFO_UPDATE = 0x7, .AFMT_AUDIO_SRC_SELECT = 0x0, .
AFMT_AUDIO_CHANNEL_ENABLE = 0x8, .AFMT_60958_CS_UPDATE = 0x1a
, .AFMT_AUDIO_LAYOUT_OVRD = 0x0, .AFMT_60958_OSF_OVRD = 0x1c,
.AFMT_60958_CS_CHANNEL_NUMBER_L = 0x14, .AFMT_60958_CS_CLOCK_ACCURACY
= 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2
= 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4
= 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6
= 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x14, .AFMT_AUDIO_SAMPLE_SEND
= 0x0, .AFMT_MEM_PWR_FORCE = 0x4
434};
435
436static const struct dcn30_afmt_mask afmt_mask = {
437 DCN3_AFMT_MASK_SH_LIST(_MASK).AFMT_AUDIO_INFO_UPDATE = 0x00000080L, .AFMT_AUDIO_SRC_SELECT
= 0x00000007L, .AFMT_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .AFMT_60958_CS_UPDATE
= 0x04000000L, .AFMT_AUDIO_LAYOUT_OVRD = 0x00000001L, .AFMT_60958_OSF_OVRD
= 0x10000000L, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x00F00000L
, .AFMT_60958_CS_CLOCK_ACCURACY = 0x30000000L, .AFMT_60958_CS_CHANNEL_NUMBER_R
= 0x00F00000L, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0000000FL
, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x000000F0L, .AFMT_60958_CS_CHANNEL_NUMBER_4
= 0x00000F00L, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0x0000F000L
, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x000F0000L, .AFMT_60958_CS_CHANNEL_NUMBER_7
= 0x00F00000L, .AFMT_AUDIO_SAMPLE_SEND = 0x00000001L, .AFMT_MEM_PWR_FORCE
= 0x00000030L
438};
439
440#define stream_enc_regs(id)[id] = { .AFMT_CNTL = DCN_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX
+ mmDIGid_AFMT_CNTL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX
+ mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX
+ mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX
+ mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_GENERIC_PACKET_CONTROL4
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .HDMI_GENERIC_PACKET_CONTROL6
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL6, .HDMI_GENERIC_PACKET_CONTROL7
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL7, .HDMI_GENERIC_PACKET_CONTROL8
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL8, .HDMI_GENERIC_PACKET_CONTROL9
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL9, .HDMI_GENERIC_PACKET_CONTROL10
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL10, .HDMI_INFOFRAME_CONTROL0
= DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 =
DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX +
mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX
+ mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX
+ mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX
+ mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX
+ mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX
+ mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX
+ mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX
+ mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX
+ mmDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_VBID_MISC_BASE_IDX
+ mmDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX
+ mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX
+ mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX
+ mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX
+ mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX
+ mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX
+ mmDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX
+ mmDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX
+ mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX
+ mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX
+ mmDPid_DP_SEC_AUD_N, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX
+ mmDPid_DP_SEC_TIMESTAMP, .DP_DSC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX
+ mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
+ mmDPid_DP_DSC_BYTES_PER_PIXEL, .DP_SEC_METADATA_TRANSMISSION
= DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX
+ mmDPid_DP_SEC_FRAMING4, .DP_GSP11_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_GSP11_CNTL_BASE_IDX
+ mmDPid_DP_GSP11_CNTL, .DME_CONTROL = DCN_BASE__INST0_SEGmmDMEid_DME_CONTROL_BASE_IDX
+ mmDMEid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN}\
441[id] = {\
442 SE_DCN3_REG_LIST(id).AFMT_CNTL = DCN_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX + mmDIGid_AFMT_CNTL
, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX
+ mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX
+ mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX
+ mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_GENERIC_PACKET_CONTROL4
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .HDMI_GENERIC_PACKET_CONTROL6
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL6, .HDMI_GENERIC_PACKET_CONTROL7
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL7, .HDMI_GENERIC_PACKET_CONTROL8
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL8, .HDMI_GENERIC_PACKET_CONTROL9
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL9, .HDMI_GENERIC_PACKET_CONTROL10
= DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL10, .HDMI_INFOFRAME_CONTROL0
= DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 =
DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX +
mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX
+ mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX
+ mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX
+ mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX
+ mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX
+ mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX
+ mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX
+ mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX
+ mmDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_VBID_MISC_BASE_IDX
+ mmDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX
+ mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX
+ mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX
+ mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX
+ mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX
+ mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX
+ mmDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX
+ mmDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX
+ mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX
+ mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX
+ mmDPid_DP_SEC_AUD_N, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX
+ mmDPid_DP_SEC_TIMESTAMP, .DP_DSC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX
+ mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
+ mmDPid_DP_DSC_BYTES_PER_PIXEL, .DP_SEC_METADATA_TRANSMISSION
= DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX
+ mmDPid_DP_SEC_FRAMING4, .DP_GSP11_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_GSP11_CNTL_BASE_IDX
+ mmDPid_DP_GSP11_CNTL, .DME_CONTROL = DCN_BASE__INST0_SEGmmDMEid_DME_CONTROL_BASE_IDX
+ mmDMEid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN\
443}
444
445static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
446 stream_enc_regs(0)[0] = { .AFMT_CNTL = 0x000034C0 + 0x20af, .DIG_FE_CNTL = 0x000034C0
+ 0x208b, .HDMI_CONTROL = 0x000034C0 + 0x2093, .HDMI_DB_CONTROL
= 0x000034C0 + 0x20a6, .HDMI_GC = 0x000034C0 + 0x209d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x209a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x209e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x209f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x20a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x20a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x209c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x209b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x20a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x20a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x20a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x20a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2098, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2099, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2097, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2095, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2096, .HDMI_ACR_32_0
= 0x000034C0 + 0x20a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x20a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x20a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x20aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x20ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x20ac, .DP_DB_CNTL = 0x000034C0 + 0x2159, .DP_MSA_MISC
= 0x000034C0 + 0x210e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x215a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x210a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x214c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x214d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x214e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x214f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2137
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2139, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2109, .DP_SEC_CNTL = 0x000034C0 + 0x212b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2153, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2157, .DP_STEER_FIFO = 0x000034C0 + 0x210d, .DP_VID_M = 0x000034C0
+ 0x2112, .DP_VID_N = 0x000034C0 + 0x2111, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x210c, .DP_VID_TIMING = 0x000034C0 + 0x2110,
.DP_SEC_AUD_N = 0x000034C0 + 0x2131, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2135, .DP_DSC_CNTL = 0x000034C0 + 0x2152, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x215c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x215b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2092
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2130, .DP_GSP11_CNTL = 0x000034C0
+ 0x2161, .DME_CONTROL = 0x000034C0 + 0x2089, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x215b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2092, .DIG_FE_CNTL = 0x000034C0 + 0x208b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x208e},
447 stream_enc_regs(1)[1] = { .AFMT_CNTL = 0x000034C0 + 0x21af, .DIG_FE_CNTL = 0x000034C0
+ 0x218b, .HDMI_CONTROL = 0x000034C0 + 0x2193, .HDMI_DB_CONTROL
= 0x000034C0 + 0x21a6, .HDMI_GC = 0x000034C0 + 0x219d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x219a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x219e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x219f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x21a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x21a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x219c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x219b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x21a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x21a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x21a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x21a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2198, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2199, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2197, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2195, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2196, .HDMI_ACR_32_0
= 0x000034C0 + 0x21a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x21a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x21a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x21aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x21ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x21ac, .DP_DB_CNTL = 0x000034C0 + 0x2259, .DP_MSA_MISC
= 0x000034C0 + 0x220e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x225a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x220a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x224c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x224d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x224e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x224f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2237
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2239, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2209, .DP_SEC_CNTL = 0x000034C0 + 0x222b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2253, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2257, .DP_STEER_FIFO = 0x000034C0 + 0x220d, .DP_VID_M = 0x000034C0
+ 0x2212, .DP_VID_N = 0x000034C0 + 0x2211, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x220c, .DP_VID_TIMING = 0x000034C0 + 0x2210,
.DP_SEC_AUD_N = 0x000034C0 + 0x2231, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2235, .DP_DSC_CNTL = 0x000034C0 + 0x2252, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x225c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x225b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2192
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2230, .DP_GSP11_CNTL = 0x000034C0
+ 0x2261, .DME_CONTROL = 0x000034C0 + 0x2189, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x225b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2192, .DIG_FE_CNTL = 0x000034C0 + 0x218b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x218e},
448 stream_enc_regs(2)[2] = { .AFMT_CNTL = 0x000034C0 + 0x22af, .DIG_FE_CNTL = 0x000034C0
+ 0x228b, .HDMI_CONTROL = 0x000034C0 + 0x2293, .HDMI_DB_CONTROL
= 0x000034C0 + 0x22a6, .HDMI_GC = 0x000034C0 + 0x229d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x229a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x229e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x229f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x22a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x22a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x229c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x229b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x22a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x22a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x22a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x22a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2298, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2299, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2297, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2295, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2296, .HDMI_ACR_32_0
= 0x000034C0 + 0x22a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x22a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x22a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x22aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x22ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x22ac, .DP_DB_CNTL = 0x000034C0 + 0x2359, .DP_MSA_MISC
= 0x000034C0 + 0x230e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x235a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x230a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x234c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x234d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x234e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x234f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2337
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2339, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2309, .DP_SEC_CNTL = 0x000034C0 + 0x232b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2353, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2357, .DP_STEER_FIFO = 0x000034C0 + 0x230d, .DP_VID_M = 0x000034C0
+ 0x2312, .DP_VID_N = 0x000034C0 + 0x2311, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x230c, .DP_VID_TIMING = 0x000034C0 + 0x2310,
.DP_SEC_AUD_N = 0x000034C0 + 0x2331, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2335, .DP_DSC_CNTL = 0x000034C0 + 0x2352, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x235c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x235b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2292
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2330, .DP_GSP11_CNTL = 0x000034C0
+ 0x2361, .DME_CONTROL = 0x000034C0 + 0x2289, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x235b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2292, .DIG_FE_CNTL = 0x000034C0 + 0x228b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x228e},
449 stream_enc_regs(3)[3] = { .AFMT_CNTL = 0x000034C0 + 0x23af, .DIG_FE_CNTL = 0x000034C0
+ 0x238b, .HDMI_CONTROL = 0x000034C0 + 0x2393, .HDMI_DB_CONTROL
= 0x000034C0 + 0x23a6, .HDMI_GC = 0x000034C0 + 0x239d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x239a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x239e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x239f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x23a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x23a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x239c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x239b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x23a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x23a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x23a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x23a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2398, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2399, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2397, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2395, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2396, .HDMI_ACR_32_0
= 0x000034C0 + 0x23a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x23a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x23a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x23aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x23ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x23ac, .DP_DB_CNTL = 0x000034C0 + 0x2459, .DP_MSA_MISC
= 0x000034C0 + 0x240e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x245a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x240a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x244c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x244d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x244e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x244f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2437
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2439, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2409, .DP_SEC_CNTL = 0x000034C0 + 0x242b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2453, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2457, .DP_STEER_FIFO = 0x000034C0 + 0x240d, .DP_VID_M = 0x000034C0
+ 0x2412, .DP_VID_N = 0x000034C0 + 0x2411, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x240c, .DP_VID_TIMING = 0x000034C0 + 0x2410,
.DP_SEC_AUD_N = 0x000034C0 + 0x2431, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2435, .DP_DSC_CNTL = 0x000034C0 + 0x2452, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x245c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x245b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2392
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2430, .DP_GSP11_CNTL = 0x000034C0
+ 0x2461, .DME_CONTROL = 0x000034C0 + 0x2389, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x245b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2392, .DIG_FE_CNTL = 0x000034C0 + 0x238b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x238e},
450 stream_enc_regs(4)[4] = { .AFMT_CNTL = 0x000034C0 + 0x24af, .DIG_FE_CNTL = 0x000034C0
+ 0x248b, .HDMI_CONTROL = 0x000034C0 + 0x2493, .HDMI_DB_CONTROL
= 0x000034C0 + 0x24a6, .HDMI_GC = 0x000034C0 + 0x249d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x249a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x249e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x249f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x24a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x24a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x249c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x249b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x24a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x24a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x24a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x24a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2498, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2499, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2497, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2495, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2496, .HDMI_ACR_32_0
= 0x000034C0 + 0x24a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x24a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x24a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x24aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x24ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x24ac, .DP_DB_CNTL = 0x000034C0 + 0x2559, .DP_MSA_MISC
= 0x000034C0 + 0x250e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x255a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x250a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x254c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x254d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x254e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x254f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2537
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2539, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2509, .DP_SEC_CNTL = 0x000034C0 + 0x252b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2553, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2557, .DP_STEER_FIFO = 0x000034C0 + 0x250d, .DP_VID_M = 0x000034C0
+ 0x2512, .DP_VID_N = 0x000034C0 + 0x2511, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x250c, .DP_VID_TIMING = 0x000034C0 + 0x2510,
.DP_SEC_AUD_N = 0x000034C0 + 0x2531, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2535, .DP_DSC_CNTL = 0x000034C0 + 0x2552, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x255c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x255b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2492
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2530, .DP_GSP11_CNTL = 0x000034C0
+ 0x2561, .DME_CONTROL = 0x000034C0 + 0x2489, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x255b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2492, .DIG_FE_CNTL = 0x000034C0 + 0x248b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x248e},
451 stream_enc_regs(5)[5] = { .AFMT_CNTL = 0x000034C0 + 0x25af, .DIG_FE_CNTL = 0x000034C0
+ 0x258b, .HDMI_CONTROL = 0x000034C0 + 0x2593, .HDMI_DB_CONTROL
= 0x000034C0 + 0x25a6, .HDMI_GC = 0x000034C0 + 0x259d, .HDMI_GENERIC_PACKET_CONTROL0
= 0x000034C0 + 0x259a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0
+ 0x259e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x259f
, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x25a0, .HDMI_GENERIC_PACKET_CONTROL4
= 0x000034C0 + 0x25a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0
+ 0x259c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x259b
, .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x25a2, .HDMI_GENERIC_PACKET_CONTROL8
= 0x000034C0 + 0x25a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0
+ 0x25a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x25a5
, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2598, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2599, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2597, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2595, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2596, .HDMI_ACR_32_0
= 0x000034C0 + 0x25a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x25a8,
.HDMI_ACR_44_0 = 0x000034C0 + 0x25a9, .HDMI_ACR_44_1 = 0x000034C0
+ 0x25aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x25ab, .HDMI_ACR_48_1
= 0x000034C0 + 0x25ac, .DP_DB_CNTL = 0x000034C0 + 0x2659, .DP_MSA_MISC
= 0x000034C0 + 0x260e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x265a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x260a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x264c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x264d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x264e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x264f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2637
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2639, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2609, .DP_SEC_CNTL = 0x000034C0 + 0x262b, .
DP_SEC_CNTL2 = 0x000034C0 + 0x2653, .DP_SEC_CNTL6 = 0x000034C0
+ 0x2657, .DP_STEER_FIFO = 0x000034C0 + 0x260d, .DP_VID_M = 0x000034C0
+ 0x2612, .DP_VID_N = 0x000034C0 + 0x2611, .DP_VID_STREAM_CNTL
= 0x000034C0 + 0x260c, .DP_VID_TIMING = 0x000034C0 + 0x2610,
.DP_SEC_AUD_N = 0x000034C0 + 0x2631, .DP_SEC_TIMESTAMP = 0x000034C0
+ 0x2635, .DP_DSC_CNTL = 0x000034C0 + 0x2652, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x265c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0
+ 0x265b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2592
, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2630, .DP_GSP11_CNTL = 0x000034C0
+ 0x2661, .DME_CONTROL = 0x000034C0 + 0x2589, .DP_SEC_METADATA_TRANSMISSION
= 0x000034C0 + 0x265b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0
+ 0x2592, .DIG_FE_CNTL = 0x000034C0 + 0x258b, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x258e}
452};
453
454static const struct dcn10_stream_encoder_shift se_shift = {
455 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .HDMI_PACKET_GEN_VERSION
= 0x4, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18
, .HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_DATA_SCRAMBLE_EN = 0x1
, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x3, .HDMI_GC_CONT = 0x5
, .HDMI_GC_SEND = 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_AUDIO_INFO_SEND
= 0x4, .HDMI_AUDIO_INFO_LINE = 0x8, .HDMI_GC_AVMUTE = 0x0, .
DP_MSE_RATE_X = 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING
= 0x0, .DP_SEC_GSP0_ENABLE = 0x14, .DP_SEC_STREAM_ENABLE = 0x0
, .DP_SEC_GSP1_ENABLE = 0x15, .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE
= 0x17, .DP_SEC_MPG_ENABLE = 0x1c, .DP_SEC_GSP4_SEND = 0xc, .
DP_SEC_GSP4_SEND_PENDING = 0xd, .DP_SEC_GSP4_LINE_NUM = 0x10,
.DP_SEC_GSP4_SEND_ANY_LINE = 0xf, .DP_VID_STREAM_DIS_DEFER =
0x8, .DP_VID_STREAM_ENABLE = 0x0, .DP_VID_STREAM_STATUS = 0x10
, .DP_STEER_FIFO_RESET = 0x0, .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N
= 0x0, .DP_VID_M = 0x0, .DIG_START = 0xa, .HDMI_AUDIO_DELAY_EN
= 0x4, .HDMI_ACR_AUTO_SEND = 0xc, .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY
= 0x1f, .HDMI_ACR_CTS_32 = 0xc, .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44
= 0xc, .HDMI_ACR_N_44 = 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48
= 0x0, .DP_SEC_AUD_N = 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, .DP_SEC_ASP_ENABLE
= 0x4, .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .
DP_SEC_ACM_ENABLE = 0x10, .AFMT_AUDIO_CLOCK_EN = 0x0, .HDMI_CLOCK_CHANNEL_RATE
= 0x2, .TMDS_PIXEL_ENCODING = 0x1c, .TMDS_COLOR_FORMAT = 0x1e
, .DIG_STEREOSYNC_SELECT = 0x4, .DIG_STEREOSYNC_GATE_EN = 0x8
, .DP_SEC_GSP4_ENABLE = 0x18, .DP_SEC_GSP5_ENABLE = 0x19, .DP_SEC_GSP6_ENABLE
= 0x1a, .DP_SEC_GSP7_ENABLE = 0x1b, .DP_SEC_GSP7_SEND = 0x18
, .DP_SEC_GSP7_LINE_NUM = 0x0, .DP_SEC_GSP11_PPS = 0x1c, .DP_SEC_GSP11_ENABLE
= 0x4, .DP_SEC_GSP11_LINE_NUM = 0x10, .DP_DB_DISABLE = 0xc, .
DP_MSA_MISC0 = 0x18, .DP_MSA_HTOTAL = 0x10, .DP_MSA_VTOTAL = 0x0
, .DP_MSA_HSTART = 0x10, .DP_MSA_VSTART = 0x0, .DP_MSA_HSYNCWIDTH
= 0x10, .DP_MSA_HSYNCPOLARITY = 0x1f, .DP_MSA_VSYNCWIDTH = 0x0
, .DP_MSA_VSYNCPOLARITY = 0xf, .DP_MSA_HWIDTH = 0x10, .DP_MSA_VHEIGHT
= 0x0, .HDMI_DB_DISABLE = 0xc, .DP_VID_N_MUL = 0xa, .DIG_SOURCE_SELECT
= 0x0, .HDMI_GENERIC0_CONT = 0x1, .HDMI_GENERIC0_SEND = 0x0,
.HDMI_GENERIC1_CONT = 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC2_CONT
= 0x9, .HDMI_GENERIC2_SEND = 0x8, .HDMI_GENERIC3_CONT = 0xd,
.HDMI_GENERIC3_SEND = 0xc, .HDMI_GENERIC4_CONT = 0x11, .HDMI_GENERIC4_SEND
= 0x10, .HDMI_GENERIC5_CONT = 0x15, .HDMI_GENERIC5_SEND = 0x14
, .HDMI_GENERIC6_CONT = 0x19, .HDMI_GENERIC6_SEND = 0x18, .HDMI_GENERIC7_CONT
= 0x1d, .HDMI_GENERIC7_SEND = 0x1c, .HDMI_GENERIC8_CONT = 0x1
, .HDMI_GENERIC8_SEND = 0x0, .HDMI_GENERIC9_CONT = 0x5, .HDMI_GENERIC9_SEND
= 0x4, .HDMI_GENERIC10_CONT = 0x9, .HDMI_GENERIC10_SEND = 0x8
, .HDMI_GENERIC11_CONT = 0xd, .HDMI_GENERIC11_SEND = 0xc, .HDMI_GENERIC12_CONT
= 0x11, .HDMI_GENERIC12_SEND = 0x10, .HDMI_GENERIC13_CONT = 0x15
, .HDMI_GENERIC13_SEND = 0x14, .HDMI_GENERIC14_CONT = 0x19, .
HDMI_GENERIC14_SEND = 0x18, .HDMI_GENERIC0_LINE = 0x0, .HDMI_GENERIC1_LINE
= 0x10, .HDMI_GENERIC2_LINE = 0x0, .HDMI_GENERIC3_LINE = 0x10
, .HDMI_GENERIC4_LINE = 0x0, .HDMI_GENERIC5_LINE = 0x10, .HDMI_GENERIC6_LINE
= 0x0, .HDMI_GENERIC7_LINE = 0x10, .HDMI_GENERIC8_LINE = 0x0
, .HDMI_GENERIC9_LINE = 0x10, .HDMI_GENERIC10_LINE = 0x0, .HDMI_GENERIC11_LINE
= 0x10, .HDMI_GENERIC12_LINE = 0x0, .HDMI_GENERIC13_LINE = 0x10
, .HDMI_GENERIC14_LINE = 0x0, .DP_DSC_MODE = 0x0, .DP_DSC_SLICE_WIDTH
= 0x10, .DP_DSC_BYTES_PER_PIXEL = 0x0, .DP_VBID6_LINE_REFERENCE
= 0xf, .DP_VBID6_LINE_NUM = 0x10, .METADATA_ENGINE_EN = 0x4,
.METADATA_HUBP_REQUESTOR_ID = 0x0, .METADATA_STREAM_TYPE = 0x8
, .DP_SEC_METADATA_PACKET_ENABLE = 0x0, .DP_SEC_METADATA_PACKET_LINE_REFERENCE
= 0x1, .DP_SEC_METADATA_PACKET_LINE = 0x10, .HDMI_METADATA_PACKET_ENABLE
= 0x0, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x4, .HDMI_METADATA_PACKET_LINE
= 0x10, .DOLBY_VISION_EN = 0x12, .DP_PIXEL_COMBINE = 0x1c, .
DP_SST_SDP_SPLITTING = 0x0, .DIG_CLOCK_PATTERN = 0x0
456};
457
458static const struct dcn10_stream_encoder_mask se_mask = {
459 SE_COMMON_MASK_SH_LIST_DCN30(_MASK).DP_PIXEL_ENCODING = 0x00000007L, .DP_COMPONENT_DEPTH = 0x07000000L
, .HDMI_PACKET_GEN_VERSION = 0x00000010L, .HDMI_KEEPOUT_MODE =
0x00000001L, .HDMI_DEEP_COLOR_ENABLE = 0x01000000L, .HDMI_DEEP_COLOR_DEPTH
= 0x30000000L, .HDMI_DATA_SCRAMBLE_EN = 0x00000002L, .HDMI_NO_EXTRA_NULL_PACKET_FILLED
= 0x00000008L, .HDMI_GC_CONT = 0x00000020L, .HDMI_GC_SEND = 0x00000010L
, .HDMI_NULL_SEND = 0x00000001L, .HDMI_AUDIO_INFO_SEND = 0x00000010L
, .HDMI_AUDIO_INFO_LINE = 0x00003F00L, .HDMI_GC_AVMUTE = 0x00000001L
, .DP_MSE_RATE_X = 0xFC000000L, .DP_MSE_RATE_Y = 0x03FFFFFFL,
.DP_MSE_RATE_UPDATE_PENDING = 0x00000001L, .DP_SEC_GSP0_ENABLE
= 0x00100000L, .DP_SEC_STREAM_ENABLE = 0x00000001L, .DP_SEC_GSP1_ENABLE
= 0x00200000L, .DP_SEC_GSP2_ENABLE = 0x00400000L, .DP_SEC_GSP3_ENABLE
= 0x00800000L, .DP_SEC_MPG_ENABLE = 0x10000000L, .DP_SEC_GSP4_SEND
= 0x00001000L, .DP_SEC_GSP4_SEND_PENDING = 0x00002000L, .DP_SEC_GSP4_LINE_NUM
= 0xFFFF0000L, .DP_SEC_GSP4_SEND_ANY_LINE = 0x00008000L, .DP_VID_STREAM_DIS_DEFER
= 0x00000300L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_VID_STREAM_STATUS
= 0x00010000L, .DP_STEER_FIFO_RESET = 0x00000001L, .DP_VID_M_N_GEN_EN
= 0x00000100L, .DP_VID_N = 0x00FFFFFFL, .DP_VID_M = 0x00FFFFFFL
, .DIG_START = 0x00000400L, .HDMI_AUDIO_DELAY_EN = 0x00000030L
, .HDMI_ACR_AUTO_SEND = 0x00001000L, .HDMI_ACR_SOURCE = 0x00000100L
, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000L, .HDMI_ACR_CTS_32 = 0xFFFFF000L
, .HDMI_ACR_N_32 = 0x000FFFFFL, .HDMI_ACR_CTS_44 = 0xFFFFF000L
, .HDMI_ACR_N_44 = 0x000FFFFFL, .HDMI_ACR_CTS_48 = 0xFFFFF000L
, .HDMI_ACR_N_48 = 0x000FFFFFL, .DP_SEC_AUD_N = 0x00FFFFFFL, .
DP_SEC_TIMESTAMP_MODE = 0x00000001L, .DP_SEC_ASP_ENABLE = 0x00000010L
, .DP_SEC_ATP_ENABLE = 0x00000100L, .DP_SEC_AIP_ENABLE = 0x00001000L
, .DP_SEC_ACM_ENABLE = 0x00010000L, .AFMT_AUDIO_CLOCK_EN = 0x00000001L
, .HDMI_CLOCK_CHANNEL_RATE = 0x00000004L, .TMDS_PIXEL_ENCODING
= 0x10000000L, .TMDS_COLOR_FORMAT = 0xC0000000L, .DIG_STEREOSYNC_SELECT
= 0x00000070L, .DIG_STEREOSYNC_GATE_EN = 0x00000100L, .DP_SEC_GSP4_ENABLE
= 0x01000000L, .DP_SEC_GSP5_ENABLE = 0x02000000L, .DP_SEC_GSP6_ENABLE
= 0x04000000L, .DP_SEC_GSP7_ENABLE = 0x08000000L, .DP_SEC_GSP7_SEND
= 0x01000000L, .DP_SEC_GSP7_LINE_NUM = 0x0000FFFFL, .DP_SEC_GSP11_PPS
= 0x10000000L, .DP_SEC_GSP11_ENABLE = 0x00000010L, .DP_SEC_GSP11_LINE_NUM
= 0xFFFF0000L, .DP_DB_DISABLE = 0x00001000L, .DP_MSA_MISC0 =
0xFF000000L, .DP_MSA_HTOTAL = 0xFFFF0000L, .DP_MSA_VTOTAL = 0x0000FFFFL
, .DP_MSA_HSTART = 0xFFFF0000L, .DP_MSA_VSTART = 0x0000FFFFL,
.DP_MSA_HSYNCWIDTH = 0x7FFF0000L, .DP_MSA_HSYNCPOLARITY = 0x80000000L
, .DP_MSA_VSYNCWIDTH = 0x00007FFFL, .DP_MSA_VSYNCPOLARITY = 0x00008000L
, .DP_MSA_HWIDTH = 0xFFFF0000L, .DP_MSA_VHEIGHT = 0x0000FFFFL
, .HDMI_DB_DISABLE = 0x00001000L, .DP_VID_N_MUL = 0x00000C00L
, .DIG_SOURCE_SELECT = 0x00000007L, .HDMI_GENERIC0_CONT = 0x00000002L
, .HDMI_GENERIC0_SEND = 0x00000001L, .HDMI_GENERIC1_CONT = 0x00000020L
, .HDMI_GENERIC1_SEND = 0x00000010L, .HDMI_GENERIC2_CONT = 0x00000200L
, .HDMI_GENERIC2_SEND = 0x00000100L, .HDMI_GENERIC3_CONT = 0x00002000L
, .HDMI_GENERIC3_SEND = 0x00001000L, .HDMI_GENERIC4_CONT = 0x00020000L
, .HDMI_GENERIC4_SEND = 0x00010000L, .HDMI_GENERIC5_CONT = 0x00200000L
, .HDMI_GENERIC5_SEND = 0x00100000L, .HDMI_GENERIC6_CONT = 0x02000000L
, .HDMI_GENERIC6_SEND = 0x01000000L, .HDMI_GENERIC7_CONT = 0x20000000L
, .HDMI_GENERIC7_SEND = 0x10000000L, .HDMI_GENERIC8_CONT = 0x00000002L
, .HDMI_GENERIC8_SEND = 0x00000001L, .HDMI_GENERIC9_CONT = 0x00000020L
, .HDMI_GENERIC9_SEND = 0x00000010L, .HDMI_GENERIC10_CONT = 0x00000200L
, .HDMI_GENERIC10_SEND = 0x00000100L, .HDMI_GENERIC11_CONT = 0x00002000L
, .HDMI_GENERIC11_SEND = 0x00001000L, .HDMI_GENERIC12_CONT = 0x00020000L
, .HDMI_GENERIC12_SEND = 0x00010000L, .HDMI_GENERIC13_CONT = 0x00200000L
, .HDMI_GENERIC13_SEND = 0x00100000L, .HDMI_GENERIC14_CONT = 0x02000000L
, .HDMI_GENERIC14_SEND = 0x01000000L, .HDMI_GENERIC0_LINE = 0x0000FFFFL
, .HDMI_GENERIC1_LINE = 0xFFFF0000L, .HDMI_GENERIC2_LINE = 0x0000FFFFL
, .HDMI_GENERIC3_LINE = 0xFFFF0000L, .HDMI_GENERIC4_LINE = 0x0000FFFFL
, .HDMI_GENERIC5_LINE = 0xFFFF0000L, .HDMI_GENERIC6_LINE = 0x0000FFFFL
, .HDMI_GENERIC7_LINE = 0xFFFF0000L, .HDMI_GENERIC8_LINE = 0x0000FFFFL
, .HDMI_GENERIC9_LINE = 0xFFFF0000L, .HDMI_GENERIC10_LINE = 0x0000FFFFL
, .HDMI_GENERIC11_LINE = 0xFFFF0000L, .HDMI_GENERIC12_LINE = 0x0000FFFFL
, .HDMI_GENERIC13_LINE = 0xFFFF0000L, .HDMI_GENERIC14_LINE = 0x0000FFFFL
, .DP_DSC_MODE = 0x00000003L, .DP_DSC_SLICE_WIDTH = 0x1FFF0000L
, .DP_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .DP_VBID6_LINE_REFERENCE
= 0x00008000L, .DP_VBID6_LINE_NUM = 0xFFFF0000L, .METADATA_ENGINE_EN
= 0x00000010L, .METADATA_HUBP_REQUESTOR_ID = 0x00000007L, .METADATA_STREAM_TYPE
= 0x00000100L, .DP_SEC_METADATA_PACKET_ENABLE = 0x00000001L,
.DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x00000002L, .DP_SEC_METADATA_PACKET_LINE
= 0xFFFF0000L, .HDMI_METADATA_PACKET_ENABLE = 0x00000001L, .
HDMI_METADATA_PACKET_LINE_REFERENCE = 0x00000010L, .HDMI_METADATA_PACKET_LINE
= 0xFFFF0000L, .DOLBY_VISION_EN = 0x00040000L, .DP_PIXEL_COMBINE
= 0x30000000L, .DP_SST_SDP_SPLITTING = 0x00000001L, .DIG_CLOCK_PATTERN
= 0x000003FFL
460};
461
462
463#define aux_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_TX_CONTROL}\
464[id] = {\
465 DCN2_AUX_REG_LIST(id).AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_TX_CONTROL\
466}
467
468static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
469 aux_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1f5a, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f59},
470 aux_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1f76, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f75},
471 aux_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1f92, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f91},
472 aux_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1fae, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fad},
473 aux_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1fca, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fc9},
474 aux_regs(5)[5] = { .AUX_CONTROL = 0x000034C0 + 0x1fdc, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1fe6, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fe7
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fe5}
475};
476
477#define hpd_regs(id)[id] = { .DC_HPD_CONTROL = DCN_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX
+ mmHPDid_DC_HPD_CONTROL}\
478[id] = {\
479 HPD_REG_LIST(id).DC_HPD_CONTROL = DCN_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX
+ mmHPDid_DC_HPD_CONTROL\
480}
481
482static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
483 hpd_regs(0)[0] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f16},
484 hpd_regs(1)[1] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f1e},
485 hpd_regs(2)[2] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f26},
486 hpd_regs(3)[3] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f2e},
487 hpd_regs(4)[4] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f36},
488 hpd_regs(5)[5] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f3e}
489};
490
491#define link_regs(id, phyid)[id] = { .DIG_BE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .TMDS_DCBALANCER_CONTROL = DCN_BASE__INST0_SEGmmDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX
+ mmDIGid_TMDS_DCBALANCER_CONTROL, .DP_CONFIG = DCN_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX
+ mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX
+ mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX
+ mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX
+ mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
+ mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX
+ mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX
+ mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX
+ mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX
+ mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX
+ mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX
+ mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL
= DCN_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
+ mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .CLOCK_ENABLE = DCN_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX
+ mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX
+ mmUNIPHYphyid_CHANNEL_XBAR_CNTL, .DIG_LANE_ENABLE = DCN_BASE__INST0_SEGmmDIGid_DIG_LANE_ENABLE_BASE_IDX
+ mmDIGid_DIG_LANE_ENABLE, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CNTL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL
= DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 =
DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL0
, .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCSTX_PLL_UPDATE_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX
+ mmRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX
+ mmRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE3, .DPCSTX_TX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CLOCK_CNTL_BASE_IDX
+ mmDPCSTXid_DPCSTX_TX_CLOCK_CNTL, .DPCSTX_TX_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CNTL_BASE_IDX
+ mmDPCSTXid_DPCSTX_TX_CNTL, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0
+ 0x2937, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
= DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, .DP_DPHY_INTERNAL_CTRL
= DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX +
mmDPid_DP_DPHY_INTERNAL_CTRL }\
492[id] = {\
493 LE_DCN3_REG_LIST(id).DIG_BE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .TMDS_DCBALANCER_CONTROL = DCN_BASE__INST0_SEGmmDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX
+ mmDIGid_TMDS_DCBALANCER_CONTROL, .DP_CONFIG = DCN_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX
+ mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX
+ mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX
+ mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX
+ mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
+ mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX
+ mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX
+ mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX
+ mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX
+ mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX
+ mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX
+ mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL
= DCN_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
+ mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, \
494 UNIPHY_DCN2_REG_LIST(phyid).CLOCK_ENABLE = DCN_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX
+ mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX
+ mmUNIPHYphyid_CHANNEL_XBAR_CNTL, \
495 DPCS_DCN2_REG_LIST(id).DIG_LANE_ENABLE = DCN_BASE__INST0_SEGmmDIGid_DIG_LANE_ENABLE_BASE_IDX
+ mmDIGid_DIG_LANE_ENABLE, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CNTL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL
= DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 =
DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL0
, .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCSTX_PLL_UPDATE_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX
+ mmRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX
+ mmRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_FUSE3, .DPCSTX_TX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CLOCK_CNTL_BASE_IDX
+ mmDPCSTXid_DPCSTX_TX_CLOCK_CNTL, .DPCSTX_TX_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CNTL_BASE_IDX
+ mmDPCSTXid_DPCSTX_TX_CNTL, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0
+ 0x2937, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
= DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX
+ mmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, \
496 SRI(DP_DPHY_INTERNAL_CTRL, DP, id).DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX
+ mmDPid_DP_DPHY_INTERNAL_CTRL \
497}
498
499static const struct dce110_aux_registers_shift aux_shift = {
500 DCN_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS
= 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG
= 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, .
AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW
= 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX =
0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, .
AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUX_RX_TIMEOUT_LEN
= 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf
501};
502
503static const struct dce110_aux_registers_mask aux_mask = {
504 DCN_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x00000001L, .AUX_RESET = 0x00000010L, .AUX_RESET_DONE
= 0x00000020L, .AUX_REG_RW_CNTL_STATUS = 0x0000000CL, .AUX_SW_USE_AUX_REG_REQ
= 0x00010000L, .AUX_SW_DONE_USING_AUX_REG = 0x00020000L, .AUX_SW_START_DELAY
= 0x000000F0L, .AUX_SW_WR_BYTES = 0x001F0000L, .AUX_SW_GO = 0x00000001L
, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .AUX_SW_DATA_RW
= 0x00000001L, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .
AUX_SW_INDEX = 0x001F0000L, .AUX_SW_DATA = 0x0000FF00L, .AUX_SW_REPLY_BYTE_COUNT
= 0x1F000000L, .AUX_SW_DONE = 0x00000001L, .AUX_SW_DONE_ACK =
0x00000002L, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL
= 0x00018000L
505};
506
507static const struct dcn10_link_enc_registers link_enc_regs[] = {
508 link_regs(0, A)[0] = { .DIG_BE_CNTL = 0x000034C0 + 0x20b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x20b1, .TMDS_CTL_BITS = 0x000034C0 + 0x20de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x20df, .DP_CONFIG = 0x000034C0
+ 0x210b, .DP_DPHY_CNTL = 0x000034C0 + 0x2117, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x211d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x211e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2119, .DP_DPHY_SYM1 = 0x000034C0
+ 0x211a, .DP_DPHY_SYM2 = 0x000034C0 + 0x211b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2118, .DP_LINK_CNTL = 0x000034C0 + 0x2108, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2113, .DP_MSE_SAT0 = 0x000034C0
+ 0x213a, .DP_MSE_SAT1 = 0x000034C0 + 0x213b, .DP_MSE_SAT2 =
0x000034C0 + 0x213c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x213d
, .DP_SEC_CNTL = 0x000034C0 + 0x212b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x210c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2124, .DP_SEC_CNTL1
= 0x000034C0 + 0x212c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2144, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2145
, .CLOCK_ENABLE = 0x000000C0 + 0x00a0, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x286e, .DIG_LANE_ENABLE = 0x000034C0 + 0x20e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x20de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2943
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2944, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2945, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2946
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2947, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2948, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2949
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x294a, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x294b, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x294c
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x294d, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x294e, .RDPCSTX_CNTL = 0x000034C0 + 0x2930, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2931, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2932, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2940
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2942, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2933, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2934
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2935, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x294f, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2950
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2951, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2952, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2928
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2929, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2953, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x293c
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x210f },
509 link_regs(1, B)[1] = { .DIG_BE_CNTL = 0x000034C0 + 0x21b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x21b1, .TMDS_CTL_BITS = 0x000034C0 + 0x21de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x21df, .DP_CONFIG = 0x000034C0
+ 0x220b, .DP_DPHY_CNTL = 0x000034C0 + 0x2217, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x221d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x221e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2219, .DP_DPHY_SYM1 = 0x000034C0
+ 0x221a, .DP_DPHY_SYM2 = 0x000034C0 + 0x221b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2218, .DP_LINK_CNTL = 0x000034C0 + 0x2208, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2213, .DP_MSE_SAT0 = 0x000034C0
+ 0x223a, .DP_MSE_SAT1 = 0x000034C0 + 0x223b, .DP_MSE_SAT2 =
0x000034C0 + 0x223c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x223d
, .DP_SEC_CNTL = 0x000034C0 + 0x222b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x220c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2224, .DP_SEC_CNTL1
= 0x000034C0 + 0x222c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2244, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2245
, .CLOCK_ENABLE = 0x000000C0 + 0x00a1, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2870, .DIG_LANE_ENABLE = 0x000034C0 + 0x21e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x21de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2a1b
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2a1c, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2a1d, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2a1e
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2a1f, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2a20, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2a21
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2a22, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x2a23, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2a24
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2a25, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x2a26, .RDPCSTX_CNTL = 0x000034C0 + 0x2a08, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2a09, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2a0a, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2a18
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2a1a, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2a0b, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2a0c
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2a0d, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x2a27, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2a28
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2a29, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2a2a, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2a00
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2a01, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2a2b, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2a14
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x220f },
510 link_regs(2, C)[2] = { .DIG_BE_CNTL = 0x000034C0 + 0x22b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x22b1, .TMDS_CTL_BITS = 0x000034C0 + 0x22de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x22df, .DP_CONFIG = 0x000034C0
+ 0x230b, .DP_DPHY_CNTL = 0x000034C0 + 0x2317, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x231d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x231e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2319, .DP_DPHY_SYM1 = 0x000034C0
+ 0x231a, .DP_DPHY_SYM2 = 0x000034C0 + 0x231b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2318, .DP_LINK_CNTL = 0x000034C0 + 0x2308, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2313, .DP_MSE_SAT0 = 0x000034C0
+ 0x233a, .DP_MSE_SAT1 = 0x000034C0 + 0x233b, .DP_MSE_SAT2 =
0x000034C0 + 0x233c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x233d
, .DP_SEC_CNTL = 0x000034C0 + 0x232b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x230c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2324, .DP_SEC_CNTL1
= 0x000034C0 + 0x232c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2344, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2345
, .CLOCK_ENABLE = 0x000000C0 + 0x00a2, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2872, .DIG_LANE_ENABLE = 0x000034C0 + 0x22e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x22de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2af3
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2af4, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2af5, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2af6
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2af7, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2af8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2af9
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2afa, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x2afb, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2afc
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2afd, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x2afe, .RDPCSTX_CNTL = 0x000034C0 + 0x2ae0, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2ae1, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2ae2, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2af0
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2af2, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2ae3, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2ae4
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2ae5, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x2aff, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2b00
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2b01, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2b02, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2ad8
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2ad9, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2b03, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2aec
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x230f },
511 link_regs(3, D)[3] = { .DIG_BE_CNTL = 0x000034C0 + 0x23b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x23b1, .TMDS_CTL_BITS = 0x000034C0 + 0x23de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x23df, .DP_CONFIG = 0x000034C0
+ 0x240b, .DP_DPHY_CNTL = 0x000034C0 + 0x2417, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x241d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x241e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2419, .DP_DPHY_SYM1 = 0x000034C0
+ 0x241a, .DP_DPHY_SYM2 = 0x000034C0 + 0x241b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2418, .DP_LINK_CNTL = 0x000034C0 + 0x2408, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2413, .DP_MSE_SAT0 = 0x000034C0
+ 0x243a, .DP_MSE_SAT1 = 0x000034C0 + 0x243b, .DP_MSE_SAT2 =
0x000034C0 + 0x243c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x243d
, .DP_SEC_CNTL = 0x000034C0 + 0x242b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x240c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2424, .DP_SEC_CNTL1
= 0x000034C0 + 0x242c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2444, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2445
, .CLOCK_ENABLE = 0x000000C0 + 0x00a3, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2874, .DIG_LANE_ENABLE = 0x000034C0 + 0x23e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x23de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2bcb
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2bcc, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2bcd, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2bce
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2bcf, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2bd0, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2bd1
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2bd2, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x2bd3, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2bd4
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2bd5, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x2bd6, .RDPCSTX_CNTL = 0x000034C0 + 0x2bb8, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2bb9, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2bba, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2bc8
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2bca, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2bbb, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2bbc
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2bbd, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x2bd7, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2bd8
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2bd9, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2bda, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2bb0
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2bb1, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2bdb, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2bc4
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x240f },
512 link_regs(4, E)[4] = { .DIG_BE_CNTL = 0x000034C0 + 0x24b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x24b1, .TMDS_CTL_BITS = 0x000034C0 + 0x24de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x24df, .DP_CONFIG = 0x000034C0
+ 0x250b, .DP_DPHY_CNTL = 0x000034C0 + 0x2517, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x251d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x251e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2519, .DP_DPHY_SYM1 = 0x000034C0
+ 0x251a, .DP_DPHY_SYM2 = 0x000034C0 + 0x251b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2518, .DP_LINK_CNTL = 0x000034C0 + 0x2508, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2513, .DP_MSE_SAT0 = 0x000034C0
+ 0x253a, .DP_MSE_SAT1 = 0x000034C0 + 0x253b, .DP_MSE_SAT2 =
0x000034C0 + 0x253c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x253d
, .DP_SEC_CNTL = 0x000034C0 + 0x252b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x250c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2524, .DP_SEC_CNTL1
= 0x000034C0 + 0x252c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2544, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2545
, .CLOCK_ENABLE = 0x000000C0 + 0x00a4, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2876, .DIG_LANE_ENABLE = 0x000034C0 + 0x24e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x24de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2ca3
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2ca4, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2ca5, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2ca6
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2ca7, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2ca8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2ca9
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2caa, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x2cab, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2cac
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2cad, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x2cae, .RDPCSTX_CNTL = 0x000034C0 + 0x2c90, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2c91, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2c92, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2ca0
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2ca2, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2c93, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2c94
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2c95, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x2caf, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2cb0
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2cb1, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2cb2, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2c88
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2c89, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2cb3, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2c9c
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x250f },
513 link_regs(5, F)[5] = { .DIG_BE_CNTL = 0x000034C0 + 0x25b0, .DIG_BE_EN_CNTL =
0x000034C0 + 0x25b1, .TMDS_CTL_BITS = 0x000034C0 + 0x25de, .
TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x25df, .DP_CONFIG = 0x000034C0
+ 0x260b, .DP_DPHY_CNTL = 0x000034C0 + 0x2617, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x261d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x261e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2619, .DP_DPHY_SYM1 = 0x000034C0
+ 0x261a, .DP_DPHY_SYM2 = 0x000034C0 + 0x261b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2618, .DP_LINK_CNTL = 0x000034C0 + 0x2608, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2613, .DP_MSE_SAT0 = 0x000034C0
+ 0x263a, .DP_MSE_SAT1 = 0x000034C0 + 0x263b, .DP_MSE_SAT2 =
0x000034C0 + 0x263c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x263d
, .DP_SEC_CNTL = 0x000034C0 + 0x262b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x260c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2624, .DP_SEC_CNTL1
= 0x000034C0 + 0x262c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2644, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2645
, .CLOCK_ENABLE = 0x000000C0 + 0x00a5, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2878, .DIG_LANE_ENABLE = 0x000034C0 + 0x25e5, .TMDS_CTL_BITS
= 0x000034C0 + 0x25de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2d7b
, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2d7c, .RDPCSTX_PHY_CNTL5
= 0x000034C0 + 0x2d7d, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2d7e
, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2d7f, .RDPCSTX_PHY_CNTL8
= 0x000034C0 + 0x2d80, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2d81
, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2d82, .RDPCSTX_PHY_CNTL11
= 0x000034C0 + 0x2d83, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2d84
, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2d85, .RDPCSTX_PHY_CNTL14
= 0x000034C0 + 0x2d86, .RDPCSTX_CNTL = 0x000034C0 + 0x2d68, .
RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2d69, .RDPCSTX_INTERRUPT_CONTROL
= 0x000034C0 + 0x2d6a, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2d78
, .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2d7a, .RDPCSTX_PLL_UPDATE_DATA
= 0x000034C0 + 0x2d6b, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2d6c
, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2d6d, .RDPCSTX_PHY_FUSE0
= 0x000034C0 + 0x2d87, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2d88
, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2d89, .RDPCSTX_PHY_FUSE3
= 0x000034C0 + 0x2d8a, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2d60
, .DPCSTX_TX_CNTL = 0x000034C0 + 0x2d61, .RDPCSTX0_RDPCSTX_SCRATCH
= 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 +
0x2d8b, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2d74
, .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x260f }
514};
515
516static const struct dcn10_link_enc_shift le_shift = {
517 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT).DIG_ENABLE = 0x0, .DIG_HPD_SELECT = 0x1c, .DIG_MODE = 0x10, .
DIG_FE_SOURCE_SELECT = 0x8, .TMDS_CTL0 = 0x0, .DPHY_BYPASS = 0x10
, .DPHY_ATEST_SEL_LANE0 = 0x0, .DPHY_ATEST_SEL_LANE1 = 0x1, .
DPHY_ATEST_SEL_LANE2 = 0x2, .DPHY_ATEST_SEL_LANE3 = 0x3, .DPHY_PRBS_EN
= 0x0, .DPHY_PRBS_SEL = 0x4, .DPHY_SYM1 = 0x0, .DPHY_SYM2 = 0xa
, .DPHY_SYM3 = 0x14, .DPHY_SYM4 = 0x0, .DPHY_SYM5 = 0xa, .DPHY_SYM6
= 0x14, .DPHY_SYM7 = 0x0, .DPHY_SYM8 = 0xa, .DPHY_SCRAMBLER_BS_COUNT
= 0x8, .DPHY_SCRAMBLER_ADVANCE = 0x4, .DPHY_RX_FAST_TRAINING_CAPABLE
= 0x0, .DPHY_LOAD_BS_COUNT = 0x0, .DPHY_TRAINING_PATTERN_SEL
= 0x0, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x0, .DP_LINK_TRAINING_COMPLETE
= 0x4, .DP_IDLE_BS_INTERVAL = 0x0, .DP_VBID_DISABLE = 0x18, .
DP_VID_ENHANCED_FRAME_MODE = 0x1c, .DP_VID_STREAM_ENABLE = 0x0
, .DP_UDI_LANES = 0x0, .DP_SEC_GSP0_LINE_NUM = 0x10, .DP_SEC_GSP0_PRIORITY
= 0x4, .DP_MSE_SAT_SRC0 = 0x0, .DP_MSE_SAT_SRC1 = 0x10, .DP_MSE_SAT_SLOT_COUNT0
= 0x8, .DP_MSE_SAT_SLOT_COUNT1 = 0x18, .DP_MSE_SAT_SRC2 = 0x0
, .DP_MSE_SAT_SRC3 = 0x10, .DP_MSE_SAT_SLOT_COUNT2 = 0x8, .DP_MSE_SAT_SLOT_COUNT3
= 0x18, .DP_MSE_SAT_UPDATE = 0x0, .DP_MSE_16_MTP_KEEPOUT = 0x8
, .AUX_HPD_SEL = 0x14, .AUX_LS_READ_EN = 0x8, .AUX_RX_RECEIVE_WINDOW
= 0x8, .DC_HPD_EN = 0x1c, .DPHY_FEC_EN = 0x4, .DPHY_FEC_READY_SHADOW
= 0x5, .DPHY_FEC_ACTIVE_STATUS = 0x6, .DIG_LANE0EN = 0x0, .DIG_LANE1EN
= 0x1, .DIG_LANE2EN = 0x2, .DIG_LANE3EN = 0x3, .DIG_CLK_EN =
0x8, .TMDS_CTL0 = 0x0, .SYMCLKA_CLOCK_ENABLE = 0x0, .UNIPHY_LINK_ENABLE
= 0x1c, .UNIPHY_CHANNEL0_XBAR_SOURCE = 0x0, .UNIPHY_CHANNEL1_XBAR_SOURCE
= 0x8, .UNIPHY_CHANNEL2_XBAR_SOURCE = 0x10, .UNIPHY_CHANNEL3_XBAR_SOURCE
= 0x18, .AUX_RX_START_WINDOW = 0x4, .AUX_RX_HALF_SYM_DETECT_LEN
= 0xc, .AUX_RX_TRANSITION_FILTER_EN = 0x10, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT
= 0x11, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x12, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP
= 0x13, .AUX_RX_PHASE_DETECT_LEN = 0x14, .AUX_RX_DETECTION_THRESHOLD
= 0x1c, .AUX_TX_PRECHARGE_LEN = 0x0, .AUX_TX_PRECHARGE_SYMBOLS
= 0x8, .AUX_MODE_DET_CHECK_DELAY = 0x10, .AUX_RX_PRECHARGE_SKIP
= 0x0, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf,\
518 DPCS_DCN2_MASK_SH_LIST(__SHIFT).RDPCS_PHY_DP_TX0_CLK_RDY = 0x2, .RDPCS_PHY_DP_TX0_DATA_EN = 0x3
, .RDPCS_PHY_DP_TX1_CLK_RDY = 0xa, .RDPCS_PHY_DP_TX1_DATA_EN =
0xb, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x12, .RDPCS_PHY_DP_TX2_DATA_EN
= 0x13, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x1a, .RDPCS_PHY_DP_TX3_DATA_EN
= 0x1b, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x0, .RDPCS_PHY_DP_TX1_TERM_CTRL
= 0x8, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x10, .RDPCS_PHY_DP_TX3_TERM_CTRL
= 0x18, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x4, .RDPCS_PHY_DP_TX0_WIDTH
= 0x4, .RDPCS_PHY_DP_TX0_RATE = 0x1, .RDPCS_PHY_DP_TX1_WIDTH
= 0xc, .RDPCS_PHY_DP_TX1_RATE = 0x9, .RDPCS_PHY_DP_TX2_PSTATE
= 0x8, .RDPCS_PHY_DP_TX3_PSTATE = 0xc, .RDPCS_PHY_DP_TX2_MPLL_EN
= 0xa, .RDPCS_PHY_DP_TX3_MPLL_EN = 0xe, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT
= 0x10, .RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0, .RDPCS_PHY_DP_MPLLB_SSC_PEAK
= 0x0, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x18, .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE
= 0x0, .RDPCS_PHY_DP_MPLLB_FRACN_REM = 0x0, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV
= 0x14, .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x10, .RDPCS_PHY_DP_MPLLB_SSC_EN
= 0x8, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x0, .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
= 0x4, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN = 0x2, .RDPCS_PHY_DP_MPLLB_STATE
= 0x7, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN = 0x1c, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER
= 0x14, .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x18, .RDPCS_PHY_DP_MPLLB_PMIX_EN
= 0x1c, .RDPCS_TX_FIFO_LANE0_EN = 0xc, .RDPCS_TX_FIFO_LANE1_EN
= 0xd, .RDPCS_TX_FIFO_LANE2_EN = 0xe, .RDPCS_TX_FIFO_LANE3_EN
= 0xf, .RDPCS_TX_FIFO_EN = 0x10, .RDPCS_TX_FIFO_RD_START_DELAY
= 0x14, .RDPCS_EXT_REFCLK_EN = 0x0, .RDPCS_SRAMCLK_BYPASS = 0x10
, .RDPCS_SRAMCLK_EN = 0xd, .RDPCS_SRAMCLK_CLOCK_ON = 0xe, .RDPCS_SYMCLK_DIV2_CLOCK_ON
= 0xa, .RDPCS_SYMCLK_DIV2_GATE_DIS = 0x8, .RDPCS_SYMCLK_DIV2_EN
= 0x9, .RDPCS_PHY_DP_TX0_DISABLE = 0x1, .RDPCS_PHY_DP_TX1_DISABLE
= 0x9, .RDPCS_PHY_DP_TX2_DISABLE = 0x11, .RDPCS_PHY_DP_TX3_DISABLE
= 0x19, .RDPCS_PHY_DP_TX0_REQ = 0x4, .RDPCS_PHY_DP_TX1_REQ =
0xc, .RDPCS_PHY_DP_TX2_REQ = 0x14, .RDPCS_PHY_DP_TX3_REQ = 0x1c
, .RDPCS_PHY_DP_TX0_ACK = 0x5, .RDPCS_PHY_DP_TX1_ACK = 0xd, .
RDPCS_PHY_DP_TX2_ACK = 0x15, .RDPCS_PHY_DP_TX3_ACK = 0x1d, .RDPCS_PHY_DP_TX0_RESET
= 0x0, .RDPCS_PHY_DP_TX1_RESET = 0x8, .RDPCS_PHY_DP_TX2_RESET
= 0x10, .RDPCS_PHY_DP_TX3_RESET = 0x18, .RDPCS_PHY_RESET = 0x0
, .RDPCS_PHY_CR_MUX_SEL = 0x15, .RDPCS_PHY_REF_RANGE = 0x9, .
RDPCS_SRAM_BYPASS = 0x1f, .RDPCS_SRAM_EXT_LD_DONE = 0x1d, .RDPCS_PHY_HDMIMODE_ENABLE
= 0x8, .RDPCS_SRAM_INIT_DONE = 0x1c, .RDPCS_PHY_DP4_POR = 0x3
, .RDPCS_PLL_UPDATE_DATA = 0x0, .RDPCS_REG_FIFO_ERROR_MASK = 0x10
, .RDPCS_TX_FIFO_ERROR_MASK = 0x14, .RDPCS_DPALT_DISABLE_TOGGLE_MASK
= 0x11, .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x12, .RDPCS_TX_CR_ADDR
= 0x0, .RDPCS_TX_CR_DATA = 0x0, .RDPCS_PHY_DP_MPLLB_V2I = 0x12
, .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX0_EQ_PRE =
0x6, .RDPCS_PHY_DP_TX0_EQ_POST = 0xc, .RDPCS_PHY_DP_MPLLB_FREQ_VCO
= 0x14, .RDPCS_PHY_DP_MPLLB_CP_INT = 0x12, .RDPCS_PHY_DP_MPLLB_CP_PROP
= 0x19, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX1_EQ_PRE
= 0x6, .RDPCS_PHY_DP_TX1_EQ_POST = 0xc, .RDPCS_PHY_DP_TX2_EQ_MAIN
= 0x0, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX2_EQ_POST
= 0xc, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0, .RDPCS_PHY_DCO_FINETUNE
= 0x12, .RDPCS_PHY_DCO_RANGE = 0x18, .RDPCS_PHY_DP_TX3_EQ_PRE
= 0x6, .RDPCS_PHY_DP_TX3_EQ_POST = 0xc, .DPCS_SYMCLK_CLOCK_ON
= 0x2, .DPCS_SYMCLK_GATE_DIS = 0x0, .DPCS_SYMCLK_EN = 0x1, .
DPCS_TX_DATA_SWAP = 0xe, .DPCS_TX_DATA_ORDER_INVERT = 0xf, .DPCS_TX_FIFO_EN
= 0x10, .DPCS_TX_FIFO_RD_START_DELAY = 0x14, .RDPCS_PHY_RX_REF_LD_VAL
= 0x0, .RDPCS_PHY_RX_VCO_LD_VAL = 0x8, .RDPCS_PHY_DPALT_DISABLE_ACK
= 0x12, .RDPCS_PHY_DP_TX0_PSTATE = 0x0, .RDPCS_PHY_DP_TX1_PSTATE
= 0x4, .RDPCS_PHY_DP_TX0_MPLL_EN = 0x2, .RDPCS_PHY_DP_TX1_MPLL_EN
= 0x6, .RDPCS_PHY_DP_REF_CLK_EN = 0x13, .RDPCS_PHY_DP_TX2_WIDTH
= 0x14, .RDPCS_PHY_DP_TX2_RATE = 0x11, .RDPCS_PHY_DP_TX3_WIDTH
= 0x1c, .RDPCS_PHY_DP_TX3_RATE = 0x19, .UNIPHYA_SOFT_RESET =
0x0, .UNIPHYB_SOFT_RESET = 0x2, .UNIPHYC_SOFT_RESET = 0x4, .
UNIPHYD_SOFT_RESET = 0x6, .UNIPHYE_SOFT_RESET = 0x8, .RDPCS_PHY_DPALT_DP4
= 0x10, .RDPCS_PHY_DPALT_DISABLE = 0x11
519};
520
521static const struct dcn10_link_enc_mask le_mask = {
522 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK).DIG_ENABLE = 0x00000001L, .DIG_HPD_SELECT = 0x70000000L, .DIG_MODE
= 0x00070000L, .DIG_FE_SOURCE_SELECT = 0x00007F00L, .TMDS_CTL0
= 0x00000001L, .DPHY_BYPASS = 0x00010000L, .DPHY_ATEST_SEL_LANE0
= 0x00000001L, .DPHY_ATEST_SEL_LANE1 = 0x00000002L, .DPHY_ATEST_SEL_LANE2
= 0x00000004L, .DPHY_ATEST_SEL_LANE3 = 0x00000008L, .DPHY_PRBS_EN
= 0x00000001L, .DPHY_PRBS_SEL = 0x00000030L, .DPHY_SYM1 = 0x000003FFL
, .DPHY_SYM2 = 0x000FFC00L, .DPHY_SYM3 = 0x3FF00000L, .DPHY_SYM4
= 0x000003FFL, .DPHY_SYM5 = 0x000FFC00L, .DPHY_SYM6 = 0x3FF00000L
, .DPHY_SYM7 = 0x000003FFL, .DPHY_SYM8 = 0x000FFC00L, .DPHY_SCRAMBLER_BS_COUNT
= 0x0003FF00L, .DPHY_SCRAMBLER_ADVANCE = 0x00000010L, .DPHY_RX_FAST_TRAINING_CAPABLE
= 0x00000001L, .DPHY_LOAD_BS_COUNT = 0x000003FFL, .DPHY_TRAINING_PATTERN_SEL
= 0x00000003L, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x00000007L, .
DP_LINK_TRAINING_COMPLETE = 0x00000010L, .DP_IDLE_BS_INTERVAL
= 0x0003FFFFL, .DP_VBID_DISABLE = 0x01000000L, .DP_VID_ENHANCED_FRAME_MODE
= 0x10000000L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_UDI_LANES
= 0x00000003L, .DP_SEC_GSP0_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP0_PRIORITY
= 0x00000010L, .DP_MSE_SAT_SRC0 = 0x00000007L, .DP_MSE_SAT_SRC1
= 0x00070000L, .DP_MSE_SAT_SLOT_COUNT0 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT1
= 0x3F000000L, .DP_MSE_SAT_SRC2 = 0x00000007L, .DP_MSE_SAT_SRC3
= 0x00070000L, .DP_MSE_SAT_SLOT_COUNT2 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT3
= 0x3F000000L, .DP_MSE_SAT_UPDATE = 0x00000003L, .DP_MSE_16_MTP_KEEPOUT
= 0x00000100L, .AUX_HPD_SEL = 0x00700000L, .AUX_LS_READ_EN =
0x00000100L, .AUX_RX_RECEIVE_WINDOW = 0x00000700L, .DC_HPD_EN
= 0x10000000L, .DPHY_FEC_EN = 0x00000010L, .DPHY_FEC_READY_SHADOW
= 0x00000020L, .DPHY_FEC_ACTIVE_STATUS = 0x00000040L, .DIG_LANE0EN
= 0x00000001L, .DIG_LANE1EN = 0x00000002L, .DIG_LANE2EN = 0x00000004L
, .DIG_LANE3EN = 0x00000008L, .DIG_CLK_EN = 0x00000100L, .TMDS_CTL0
= 0x00000001L, .SYMCLKA_CLOCK_ENABLE = 0x00000001L, .UNIPHY_LINK_ENABLE
= 0x10000000L, .UNIPHY_CHANNEL0_XBAR_SOURCE = 0x00000003L, .
UNIPHY_CHANNEL1_XBAR_SOURCE = 0x00000300L, .UNIPHY_CHANNEL2_XBAR_SOURCE
= 0x00030000L, .UNIPHY_CHANNEL3_XBAR_SOURCE = 0x03000000L, .
AUX_RX_START_WINDOW = 0x00000070L, .AUX_RX_HALF_SYM_DETECT_LEN
= 0x00003000L, .AUX_RX_TRANSITION_FILTER_EN = 0x00010000L, .
AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00020000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_START
= 0x00040000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x00080000L
, .AUX_RX_PHASE_DETECT_LEN = 0x00300000L, .AUX_RX_DETECTION_THRESHOLD
= 0x70000000L, .AUX_TX_PRECHARGE_LEN = 0x0000000FL, .AUX_TX_PRECHARGE_SYMBOLS
= 0x00003F00L, .AUX_MODE_DET_CHECK_DELAY = 0x00070000L, .AUX_RX_PRECHARGE_SKIP
= 0x000000FFL, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL
= 0x00018000L,\
523 DPCS_DCN2_MASK_SH_LIST(_MASK).RDPCS_PHY_DP_TX0_CLK_RDY = 0x00000004L, .RDPCS_PHY_DP_TX0_DATA_EN
= 0x00000008L, .RDPCS_PHY_DP_TX1_CLK_RDY = 0x00000400L, .RDPCS_PHY_DP_TX1_DATA_EN
= 0x00000800L, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x00040000L, .RDPCS_PHY_DP_TX2_DATA_EN
= 0x00080000L, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x04000000L, .RDPCS_PHY_DP_TX3_DATA_EN
= 0x08000000L, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x00000007L, .RDPCS_PHY_DP_TX1_TERM_CTRL
= 0x00000700L, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x00070000L, .RDPCS_PHY_DP_TX3_TERM_CTRL
= 0x07000000L, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x0000FFF0L,
.RDPCS_PHY_DP_TX0_WIDTH = 0x00000030L, .RDPCS_PHY_DP_TX0_RATE
= 0x0000000EL, .RDPCS_PHY_DP_TX1_WIDTH = 0x00003000L, .RDPCS_PHY_DP_TX1_RATE
= 0x00000E00L, .RDPCS_PHY_DP_TX2_PSTATE = 0x00000300L, .RDPCS_PHY_DP_TX3_PSTATE
= 0x00003000L, .RDPCS_PHY_DP_TX2_MPLL_EN = 0x00000400L, .RDPCS_PHY_DP_TX3_MPLL_EN
= 0x00004000L, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT = 0xFFFF0000L,
.RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0000FFFFL, .RDPCS_PHY_DP_MPLLB_SSC_PEAK
= 0x000FFFFFL, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x01000000L
, .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE = 0x001FFFFFL, .RDPCS_PHY_DP_MPLLB_FRACN_REM
= 0x0000FFFFL, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = 0x00700000L
, .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x00070000L, .RDPCS_PHY_DP_MPLLB_SSC_EN
= 0x00000100L, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x00000001L
, .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000070L, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN
= 0x00000004L, .RDPCS_PHY_DP_MPLLB_STATE = 0x00000080L, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN
= 0x10000000L, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER = 0x0FF00000L
, .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x01000000L, .RDPCS_PHY_DP_MPLLB_PMIX_EN
= 0x10000000L, .RDPCS_TX_FIFO_LANE0_EN = 0x00001000L, .RDPCS_TX_FIFO_LANE1_EN
= 0x00002000L, .RDPCS_TX_FIFO_LANE2_EN = 0x00004000L, .RDPCS_TX_FIFO_LANE3_EN
= 0x00008000L, .RDPCS_TX_FIFO_EN = 0x00010000L, .RDPCS_TX_FIFO_RD_START_DELAY
= 0x01F00000L, .RDPCS_EXT_REFCLK_EN = 0x00000001L, .RDPCS_SRAMCLK_BYPASS
= 0x00010000L, .RDPCS_SRAMCLK_EN = 0x00002000L, .RDPCS_SRAMCLK_CLOCK_ON
= 0x00004000L, .RDPCS_SYMCLK_DIV2_CLOCK_ON = 0x00000400L, .RDPCS_SYMCLK_DIV2_GATE_DIS
= 0x00000100L, .RDPCS_SYMCLK_DIV2_EN = 0x00000200L, .RDPCS_PHY_DP_TX0_DISABLE
= 0x00000002L, .RDPCS_PHY_DP_TX1_DISABLE = 0x00000200L, .RDPCS_PHY_DP_TX2_DISABLE
= 0x00020000L, .RDPCS_PHY_DP_TX3_DISABLE = 0x02000000L, .RDPCS_PHY_DP_TX0_REQ
= 0x00000010L, .RDPCS_PHY_DP_TX1_REQ = 0x00001000L, .RDPCS_PHY_DP_TX2_REQ
= 0x00100000L, .RDPCS_PHY_DP_TX3_REQ = 0x10000000L, .RDPCS_PHY_DP_TX0_ACK
= 0x00000020L, .RDPCS_PHY_DP_TX1_ACK = 0x00002000L, .RDPCS_PHY_DP_TX2_ACK
= 0x00200000L, .RDPCS_PHY_DP_TX3_ACK = 0x20000000L, .RDPCS_PHY_DP_TX0_RESET
= 0x00000001L, .RDPCS_PHY_DP_TX1_RESET = 0x00000100L, .RDPCS_PHY_DP_TX2_RESET
= 0x00010000L, .RDPCS_PHY_DP_TX3_RESET = 0x01000000L, .RDPCS_PHY_RESET
= 0x00000001L, .RDPCS_PHY_CR_MUX_SEL = 0x00200000L, .RDPCS_PHY_REF_RANGE
= 0x00003E00L, .RDPCS_SRAM_BYPASS = 0x80000000L, .RDPCS_SRAM_EXT_LD_DONE
= 0x20000000L, .RDPCS_PHY_HDMIMODE_ENABLE = 0x00000100L, .RDPCS_SRAM_INIT_DONE
= 0x10000000L, .RDPCS_PHY_DP4_POR = 0x00000008L, .RDPCS_PLL_UPDATE_DATA
= 0x00000001L, .RDPCS_REG_FIFO_ERROR_MASK = 0x00010000L, .RDPCS_TX_FIFO_ERROR_MASK
= 0x00100000L, .RDPCS_DPALT_DISABLE_TOGGLE_MASK = 0x00020000L
, .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x00040000L, .RDPCS_TX_CR_ADDR
= 0x0000FFFFL, .RDPCS_TX_CR_DATA = 0x0000FFFFL, .RDPCS_PHY_DP_MPLLB_V2I
= 0x000C0000L, .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX0_EQ_PRE
= 0x00000FC0L, .RDPCS_PHY_DP_TX0_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_MPLLB_FREQ_VCO
= 0x00300000L, .RDPCS_PHY_DP_MPLLB_CP_INT = 0x01FC0000L, .RDPCS_PHY_DP_MPLLB_CP_PROP
= 0xFE000000L, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX1_EQ_PRE
= 0x00000FC0L, .RDPCS_PHY_DP_TX1_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_TX2_EQ_MAIN
= 0x0000003FL, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX2_EQ_POST
= 0x0003F000L, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DCO_FINETUNE
= 0x00FC0000L, .RDPCS_PHY_DCO_RANGE = 0x03000000L, .RDPCS_PHY_DP_TX3_EQ_PRE
= 0x00000FC0L, .RDPCS_PHY_DP_TX3_EQ_POST = 0x0003F000L, .DPCS_SYMCLK_CLOCK_ON
= 0x00000004L, .DPCS_SYMCLK_GATE_DIS = 0x00000001L, .DPCS_SYMCLK_EN
= 0x00000002L, .DPCS_TX_DATA_SWAP = 0x00004000L, .DPCS_TX_DATA_ORDER_INVERT
= 0x00008000L, .DPCS_TX_FIFO_EN = 0x00010000L, .DPCS_TX_FIFO_RD_START_DELAY
= 0x00F00000L, .RDPCS_PHY_RX_REF_LD_VAL = 0x0000007FL, .RDPCS_PHY_RX_VCO_LD_VAL
= 0x001FFF00L, .RDPCS_PHY_DPALT_DISABLE_ACK = 0x00040000L, .
RDPCS_PHY_DP_TX0_PSTATE = 0x00000003L, .RDPCS_PHY_DP_TX1_PSTATE
= 0x00000030L, .RDPCS_PHY_DP_TX0_MPLL_EN = 0x00000004L, .RDPCS_PHY_DP_TX1_MPLL_EN
= 0x00000040L, .RDPCS_PHY_DP_REF_CLK_EN = 0x00080000L, .RDPCS_PHY_DP_TX2_WIDTH
= 0x00300000L, .RDPCS_PHY_DP_TX2_RATE = 0x000E0000L, .RDPCS_PHY_DP_TX3_WIDTH
= 0x30000000L, .RDPCS_PHY_DP_TX3_RATE = 0x0E000000L, .UNIPHYA_SOFT_RESET
= 0x00000001L, .UNIPHYB_SOFT_RESET = 0x00000004L, .UNIPHYC_SOFT_RESET
= 0x00000010L, .UNIPHYD_SOFT_RESET = 0x00000040L, .UNIPHYE_SOFT_RESET
= 0x00000100L, .RDPCS_PHY_DPALT_DP4 = 0x00010000L, .RDPCS_PHY_DPALT_DISABLE
= 0x00020000L
524};
525
526
527static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
528 { DCN_PANEL_CNTL_REG_LIST().PWRSEQ_CNTL = 0x000034C0 + 0x2883, .PWRSEQ_STATE = 0x000034C0
+ 0x2884, .PWRSEQ_REF_DIV = 0x000034C0 + 0x2885, .BL_PWM_CNTL
= 0x000034C0 + 0x2888, .BL_PWM_CNTL2 = 0x000034C0 + 0x2889, .
BL_PWM_PERIOD_CNTL = 0x000034C0 + 0x288a, .BL_PWM_GRP1_REG_LOCK
= 0x000034C0 + 0x288b, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a }
529};
530
531static const struct dce_panel_cntl_shift panel_cntl_shift = {
532 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT).LVTMA_BLON = 0x18, .LVTMA_BLON_OVRD = 0x19, .LVTMA_DIGON = 0x10
, .LVTMA_DIGON_OVRD = 0x11, .LVTMA_PWRSEQ_TARGET_STATE = 0x4,
.LVTMA_PWRSEQ_TARGET_STATE_R = 0x0, .BL_PWM_REF_DIV = 0x10, .
BL_PWM_PERIOD = 0x0, .BL_PWM_PERIOD_BITCNT = 0x10, .BL_ACTIVE_INT_FRAC_CNT
= 0x0, .BL_PWM_FRACTIONAL_EN = 0x1e, .BL_PWM_EN = 0x1f, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN
= 0x1f, .BL_PWM_GRP1_REG_LOCK = 0x0, .BL_PWM_GRP1_REG_UPDATE_PENDING
= 0x8
533};
534
535static const struct dce_panel_cntl_mask panel_cntl_mask = {
536 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK).LVTMA_BLON = 0x01000000L, .LVTMA_BLON_OVRD = 0x02000000L, .LVTMA_DIGON
= 0x00010000L, .LVTMA_DIGON_OVRD = 0x00020000L, .LVTMA_PWRSEQ_TARGET_STATE
= 0x00000010L, .LVTMA_PWRSEQ_TARGET_STATE_R = 0x00000001L, .
BL_PWM_REF_DIV = 0xFFFF0000L, .BL_PWM_PERIOD = 0x0000FFFFL, .
BL_PWM_PERIOD_BITCNT = 0x000F0000L, .BL_ACTIVE_INT_FRAC_CNT =
0x0000FFFFL, .BL_PWM_FRACTIONAL_EN = 0x40000000L, .BL_PWM_EN
= 0x80000000L, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = 0x80000000L
, .BL_PWM_GRP1_REG_LOCK = 0x00000001L, .BL_PWM_GRP1_REG_UPDATE_PENDING
= 0x00000100L
537};
538
539#define dpp_regs(id)[id] = { .CM_DEALPHA = DCN_BASE__INST0_SEGmmCMid_CM_DEALPHA_BASE_IDX
+ mmCMid_CM_DEALPHA, .CM_MEM_PWR_STATUS = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_STATUS_BASE_IDX
+ mmCMid_CM_MEM_PWR_STATUS, .CM_BIAS_CR_R = DCN_BASE__INST0_SEGmmCMid_CM_BIAS_CR_R_BASE_IDX
+ mmCMid_CM_BIAS_CR_R, .CM_BIAS_Y_G_CB_B = DCN_BASE__INST0_SEGmmCMid_CM_BIAS_Y_G_CB_B_BASE_IDX
+ mmCMid_CM_BIAS_Y_G_CB_B, .PRE_DEGAM = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_DEGAM_BASE_IDX
+ mmCNVC_CFGid_PRE_DEGAM, .CM_GAMCOR_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_CONTROL_BASE_IDX
+ mmCMid_CM_GAMCOR_CONTROL, .CM_GAMCOR_LUT_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_CONTROL, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_DATA_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_DATA, .CM_GAMCOR_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_B, .CM_GAMCOR_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_G, .CM_GAMCOR_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_R, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMB_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_B, .CM_GAMCOR_RAMB_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_B, .CM_GAMCOR_RAMB_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_G, .CM_GAMCOR_RAMB_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_G, .CM_GAMCOR_RAMB_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_R, .CM_GAMCOR_RAMB_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_R, .CM_GAMCOR_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_REGION_0_1, .CM_GAMCOR_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_REGION_32_33, .CM_GAMCOR_RAMB_OFFSET_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_OFFSET_B, .CM_GAMCOR_RAMB_OFFSET_G =
DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX +
mmCMid_CM_GAMCOR_RAMB_OFFSET_G, .CM_GAMCOR_RAMB_OFFSET_R = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_OFFSET_R, .CM_GAMCOR_RAMB_START_BASE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, .CM_GAMCOR_RAMB_START_BASE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, .CM_GAMCOR_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_B, .CM_GAMCOR_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_G, .CM_GAMCOR_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_R, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMA_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_B, .CM_GAMCOR_RAMA_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_B, .CM_GAMCOR_RAMA_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_G, .CM_GAMCOR_RAMA_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_G, .CM_GAMCOR_RAMA_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_R, .CM_GAMCOR_RAMA_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_R, .CM_GAMCOR_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_REGION_0_1, .CM_GAMCOR_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_REGION_32_33, .CM_GAMCOR_RAMA_OFFSET_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_OFFSET_B, .CM_GAMCOR_RAMA_OFFSET_G =
DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX +
mmCMid_CM_GAMCOR_RAMA_OFFSET_G, .CM_GAMCOR_RAMA_OFFSET_R = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_OFFSET_R, .CM_GAMCOR_RAMA_START_BASE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, .CM_GAMCOR_RAMA_START_BASE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, .CM_GAMUT_REMAP_CONTROL
= DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C33_C34, .CM_GAMUT_REMAP_B_C11_C12 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM
= DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX
+ mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX
+ mmDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX
+ mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX
+ mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX
+ mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX
+ mmDSCLid_DSCL_AUTOCAL, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX
+ mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
+ mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA =
DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX +
mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX
+ mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX
+ mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C
= DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C
= DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT
= DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX +
mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_C, .RECOUT_START = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX
+ mmDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX
+ mmDSCLid_RECOUT_SIZE, .PRE_DEALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_DEALPHA_BASE_IDX
+ mmCNVC_CFGid_PRE_DEALPHA, .PRE_REALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_REALPHA_BASE_IDX
+ mmCNVC_CFGid_PRE_REALPHA, .PRE_CSC_MODE = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_MODE_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_MODE, .PRE_CSC_C11_C12 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_C11_C12, .PRE_CSC_C33_C34 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_C33_C34, .PRE_CSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_B_C11_C12, .PRE_CSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_B_C33_C34, .CM_POST_CSC_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_CONTROL_BASE_IDX
+ mmCMid_CM_POST_CSC_CONTROL, .CM_POST_CSC_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_C11_C12_BASE_IDX
+ mmCMid_CM_POST_CSC_C11_C12, .CM_POST_CSC_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_C33_C34_BASE_IDX
+ mmCMid_CM_POST_CSC_C33_C34, .CM_POST_CSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_B_C11_C12_BASE_IDX
+ mmCMid_CM_POST_CSC_B_C11_C12, .CM_POST_CSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_B_C33_C34_BASE_IDX
+ mmCMid_CM_POST_CSC_B_C33_C34, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX
+ mmCMid_CM_MEM_PWR_CTRL, .CM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX
+ mmCMid_CM_CONTROL, .FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX
+ mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX
+ mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX
+ mmCMid_CM_HDR_MULT_COEF, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX
+ mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_BLUE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B =
DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX
, .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX
+ mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX
+ mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX
+ mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX
+ mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL =
DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
+ mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX
+ mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX =
DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX
, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_DATA, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, .CM_BLNDGAM_LUT_CONTROL
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_CONTROL_BASE_IDX +
mmCMid_CM_BLNDGAM_LUT_CONTROL,}\
540[id] = {\
541 DPP_REG_LIST_DCN30(id).CM_DEALPHA = DCN_BASE__INST0_SEGmmCMid_CM_DEALPHA_BASE_IDX +
mmCMid_CM_DEALPHA, .CM_MEM_PWR_STATUS = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_STATUS_BASE_IDX
+ mmCMid_CM_MEM_PWR_STATUS, .CM_BIAS_CR_R = DCN_BASE__INST0_SEGmmCMid_CM_BIAS_CR_R_BASE_IDX
+ mmCMid_CM_BIAS_CR_R, .CM_BIAS_Y_G_CB_B = DCN_BASE__INST0_SEGmmCMid_CM_BIAS_Y_G_CB_B_BASE_IDX
+ mmCMid_CM_BIAS_Y_G_CB_B, .PRE_DEGAM = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_DEGAM_BASE_IDX
+ mmCNVC_CFGid_PRE_DEGAM, .CM_GAMCOR_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_CONTROL_BASE_IDX
+ mmCMid_CM_GAMCOR_CONTROL, .CM_GAMCOR_LUT_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_CONTROL, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_LUT_DATA_BASE_IDX
+ mmCMid_CM_GAMCOR_LUT_DATA, .CM_GAMCOR_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_B, .CM_GAMCOR_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_G, .CM_GAMCOR_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_CNTL_R, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMB_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_B, .CM_GAMCOR_RAMB_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_B, .CM_GAMCOR_RAMB_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_G, .CM_GAMCOR_RAMB_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_G, .CM_GAMCOR_RAMB_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL1_R, .CM_GAMCOR_RAMB_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_END_CNTL2_R, .CM_GAMCOR_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_REGION_0_1, .CM_GAMCOR_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_REGION_32_33, .CM_GAMCOR_RAMB_OFFSET_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_OFFSET_B, .CM_GAMCOR_RAMB_OFFSET_G =
DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX +
mmCMid_CM_GAMCOR_RAMB_OFFSET_G, .CM_GAMCOR_RAMB_OFFSET_R = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_OFFSET_R, .CM_GAMCOR_RAMB_START_BASE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, .CM_GAMCOR_RAMB_START_BASE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, .CM_GAMCOR_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_B, .CM_GAMCOR_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_G, .CM_GAMCOR_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_CNTL_R, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMA_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_B, .CM_GAMCOR_RAMA_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_B, .CM_GAMCOR_RAMA_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_G, .CM_GAMCOR_RAMA_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_G, .CM_GAMCOR_RAMA_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL1_R, .CM_GAMCOR_RAMA_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_END_CNTL2_R, .CM_GAMCOR_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_REGION_0_1, .CM_GAMCOR_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_REGION_32_33, .CM_GAMCOR_RAMA_OFFSET_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_OFFSET_B, .CM_GAMCOR_RAMA_OFFSET_G =
DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX +
mmCMid_CM_GAMCOR_RAMA_OFFSET_G, .CM_GAMCOR_RAMA_OFFSET_R = DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_OFFSET_R, .CM_GAMCOR_RAMA_START_BASE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, .CM_GAMCOR_RAMA_START_BASE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX
+ mmCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, .CM_GAMUT_REMAP_CONTROL
= DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C33_C34, .CM_GAMUT_REMAP_B_C11_C12 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 =
DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX +
mmCMid_CM_GAMUT_REMAP_B_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM
= DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX
+ mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX
+ mmDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX
+ mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX
+ mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX
+ mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX
+ mmDSCLid_DSCL_AUTOCAL, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX
+ mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
+ mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA =
DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX +
mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX
+ mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX
+ mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C
= DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C
= DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT
= DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX +
mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_C, .RECOUT_START = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX
+ mmDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX
+ mmDSCLid_RECOUT_SIZE, .PRE_DEALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_DEALPHA_BASE_IDX
+ mmCNVC_CFGid_PRE_DEALPHA, .PRE_REALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_REALPHA_BASE_IDX
+ mmCNVC_CFGid_PRE_REALPHA, .PRE_CSC_MODE = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_MODE_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_MODE, .PRE_CSC_C11_C12 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_C11_C12, .PRE_CSC_C33_C34 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_C33_C34, .PRE_CSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_B_C11_C12, .PRE_CSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX
+ mmCNVC_CFGid_PRE_CSC_B_C33_C34, .CM_POST_CSC_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_CONTROL_BASE_IDX
+ mmCMid_CM_POST_CSC_CONTROL, .CM_POST_CSC_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_C11_C12_BASE_IDX
+ mmCMid_CM_POST_CSC_C11_C12, .CM_POST_CSC_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_C33_C34_BASE_IDX
+ mmCMid_CM_POST_CSC_C33_C34, .CM_POST_CSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_B_C11_C12_BASE_IDX
+ mmCMid_CM_POST_CSC_B_C11_C12, .CM_POST_CSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_POST_CSC_B_C33_C34_BASE_IDX
+ mmCMid_CM_POST_CSC_B_C33_C34, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX
+ mmCMid_CM_MEM_PWR_CTRL, .CM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX
+ mmCMid_CM_CONTROL, .FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX
+ mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX
+ mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX
+ mmCMid_CM_HDR_MULT_COEF, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX
+ mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_BLUE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B =
DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX
, .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX
+ mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX
+ mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX
+ mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX
+ mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL =
DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
+ mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX
+ mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33
= DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX =
DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX
, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_DATA, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, .CM_BLNDGAM_LUT_CONTROL
= DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_CONTROL_BASE_IDX +
mmCMid_CM_BLNDGAM_LUT_CONTROL,\
542}
543
544static const struct dcn3_dpp_registers dpp_regs[] = {
545 dpp_regs(0)[0] = { .CM_DEALPHA = 0x000034C0 + 0x0dd5, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x0dd3, .CM_BIAS_CR_R = 0x000034C0 + 0x0d3b, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x0d3c, .PRE_DEGAM = 0x000034C0
+ 0x0ced, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x0d3d, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x0d40, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0d3e
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0d3e, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x0d3f, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x0d64, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x0d65
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x0d66, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x0d67, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0d68, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0d69
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x0d6d, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x0d6e, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x0d6f, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x0d70,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x0d71, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x0d72, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x0d76, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x0d86
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x0d73, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x0d74, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x0d75, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x0d6a
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x0d6b, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x0d6c, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x0d41, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x0d42
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x0d43, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x0d44, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0d45, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0d46
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d4a, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x0d4b, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x0d4c, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d4d,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d4e, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x0d4f, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x0d53, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x0d63
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x0d50, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x0d51, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x0d52, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x0d47
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x0d48, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x0d49, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x0d2e, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0d2f, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x0d30, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x0d31, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0d32, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x0d33, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x0d34, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0d35, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x0d36, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x0d37, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0d38, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0d39, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x0d3a, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x0d0d, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0d0e
, .OTG_H_BLANK = 0x000034C0 + 0x0d0f, .OTG_V_BLANK = 0x000034C0
+ 0x0d10, .SCL_MODE = 0x000034C0 + 0x0cfb, .LB_DATA_FORMAT =
0x000034C0 + 0x0d14, .LB_MEMORY_CTRL = 0x000034C0 + 0x0d15, .
DSCL_AUTOCAL = 0x000034C0 + 0x0d0c, .SCL_TAP_CONTROL = 0x000034C0
+ 0x0cfc, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0cf9, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0cfa, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0cfe
, .MPC_SIZE = 0x000034C0 + 0x0d13, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0d00, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0d04, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0d02
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0d07, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0d01, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0d03, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0d05, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x0d08, .RECOUT_START = 0x000034C0 + 0x0d11, .
RECOUT_SIZE = 0x000034C0 + 0x0d12, .PRE_DEALPHA = 0x000034C0 +
0x0cde, .PRE_REALPHA = 0x000034C0 + 0x0cee, .PRE_CSC_MODE = 0x000034C0
+ 0x0cdf, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0ce0, .PRE_CSC_C33_C34
= 0x000034C0 + 0x0ce5, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0ce6
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0ceb, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x0d21, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0d22
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0d27, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x0d28, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x0d2d, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0dd2, .CM_CONTROL =
0x000034C0 + 0x0d20, .FORMAT_CONTROL = 0x000034C0 + 0x0cd0, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL
= 0x000034C0 + 0x0cf1, .CURSOR0_COLOR0 = 0x000034C0 + 0x0cf2
, .CURSOR0_COLOR1 = 0x000034C0 + 0x0cf3, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x0cf4, .DPP_CONTROL = 0x000034C0 + 0x0cc5, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x0dd1, .CURSOR_CONTROL = 0x000034C0
+ 0x0678, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0cdd, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x0cd1, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0cd2
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0cd3, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x0cd4, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0cd5, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x0cd6, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0cd7
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0cd8, .COLOR_KEYER_RED =
0x000034C0 + 0x0cd9, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0cda
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0cdb, .CURSOR_CONTROL = 0x000034C0
+ 0x0678, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0d1a, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0d17, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0d87
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0dae, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x0daf, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x0db0, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0db7
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0db8, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x0db9, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x0dba, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0dbb
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0dbc, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x0dc0, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x0dc1, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0dc2,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0dc3, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x0dc4, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x0dc5, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0dc6
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0dc7, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x0dc8, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x0dc9, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0dca
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0dcb, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x0dcc, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x0dcd, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0dce
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0dcf, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x0dd0, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x0d8b, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d8c
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0d8d, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x0d94, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x0d95, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d96
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d97, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x0d98, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x0d99, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0d9d,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0d9e, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x0d9f, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x0da0, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0da1,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0da2, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x0da3, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x0da4, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0da5
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0da6, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x0da7, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x0da8, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0da9
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0daa, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x0dab, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x0dac, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0dad
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0d88, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x0d89, .CM_3DLUT_MODE = 0x000034C0 + 0x0e10,
.CM_3DLUT_INDEX = 0x000034C0 + 0x0e11, .CM_3DLUT_DATA = 0x000034C0
+ 0x0e12, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0e13, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x0e14, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x0ddf, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0dd7, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x0df7, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x0df8, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0df9
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0dfa, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x0dfb, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x0dfc, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0dfd, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0dfe, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x0dff, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x0e00, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0e01, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0e02, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x0e03, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x0e04, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0e05
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0e06, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x0e07, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x0e08, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0e09
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0e0a, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x0e0b, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x0e0c, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0e0d
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0de0, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x0de1, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x0de2, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0de3, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0de4, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x0de5, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x0de6, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0de7, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0de8, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x0de9, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x0dea, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0deb
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0dec, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x0ded, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x0dee, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0def
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0df0, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x0df1, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x0df2, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0df3
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0df4, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x0df5, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x0df6, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0ddd, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x0d87, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0dde
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0d8e, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0d8f, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x0d90, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x0db1, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0db2, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x0db3, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x0d8a,},
546 dpp_regs(1)[1] = { .CM_DEALPHA = 0x000034C0 + 0x0f40, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x0f3e, .CM_BIAS_CR_R = 0x000034C0 + 0x0ea6, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x0ea7, .PRE_DEGAM = 0x000034C0
+ 0x0e58, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x0ea8, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x0eab, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0ea9
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0ea9, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x0eaa, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x0ecf, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x0ed0
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x0ed1, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x0ed2, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0ed3, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0ed4
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x0ed8, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x0ed9, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x0eda, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x0edb,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x0edc, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x0edd, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x0ee1, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x0ef1
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x0ede, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x0edf, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x0ee0, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x0ed5
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x0ed6, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x0ed7, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x0eac, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x0ead
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x0eae, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x0eaf, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0eb0, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0eb1
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x0eb5, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x0eb6, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x0eb7, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x0eb8,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x0eb9, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x0eba, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x0ebe, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x0ece
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x0ebb, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x0ebc, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x0ebd, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x0eb2
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x0eb3, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x0eb4, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x0e99, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0e9a, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x0e9b, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x0e9c, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0e9d, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x0e9e, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x0e9f, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0ea0, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x0ea1, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x0ea2, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0ea3, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0ea4, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x0ea5, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x0e78, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0e79
, .OTG_H_BLANK = 0x000034C0 + 0x0e7a, .OTG_V_BLANK = 0x000034C0
+ 0x0e7b, .SCL_MODE = 0x000034C0 + 0x0e66, .LB_DATA_FORMAT =
0x000034C0 + 0x0e7f, .LB_MEMORY_CTRL = 0x000034C0 + 0x0e80, .
DSCL_AUTOCAL = 0x000034C0 + 0x0e77, .SCL_TAP_CONTROL = 0x000034C0
+ 0x0e67, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0e64, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0e65, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0e69
, .MPC_SIZE = 0x000034C0 + 0x0e7e, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0e6b, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0e6f, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e6d
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e72, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0e6c, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0e6e, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0e70, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x0e73, .RECOUT_START = 0x000034C0 + 0x0e7c, .
RECOUT_SIZE = 0x000034C0 + 0x0e7d, .PRE_DEALPHA = 0x000034C0 +
0x0e49, .PRE_REALPHA = 0x000034C0 + 0x0e59, .PRE_CSC_MODE = 0x000034C0
+ 0x0e4a, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0e4b, .PRE_CSC_C33_C34
= 0x000034C0 + 0x0e50, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0e51
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0e56, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x0e8c, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0e8d
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0e92, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x0e93, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x0e98, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0f3d, .CM_CONTROL =
0x000034C0 + 0x0e8b, .FORMAT_CONTROL = 0x000034C0 + 0x0e3b, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL
= 0x000034C0 + 0x0e5c, .CURSOR0_COLOR0 = 0x000034C0 + 0x0e5d
, .CURSOR0_COLOR1 = 0x000034C0 + 0x0e5e, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x0e5f, .DPP_CONTROL = 0x000034C0 + 0x0e30, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x0f3c, .CURSOR_CONTROL = 0x000034C0
+ 0x0754, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0e48, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x0e3c, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0e3d
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0e3e, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x0e3f, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0e40, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x0e41, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0e42
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0e43, .COLOR_KEYER_RED =
0x000034C0 + 0x0e44, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0e45
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0e46, .CURSOR_CONTROL = 0x000034C0
+ 0x0754, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0e85, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0e82, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0ef2
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0f19, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x0f1a, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x0f1b, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0f22
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0f23, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x0f24, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x0f25, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0f26
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0f27, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x0f2b, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x0f2c, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0f2d,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0f2e, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x0f2f, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x0f30, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0f31
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0f32, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x0f33, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x0f34, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0f35
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0f36, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x0f37, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x0f38, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0f39
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0f3a, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x0f3b, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x0ef6, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ef7
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0ef8, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x0eff, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x0f00, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0f01
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0f02, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x0f03, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x0f04, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0f08,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0f09, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x0f0a, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x0f0b, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0f0c,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0f0d, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x0f0e, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x0f0f, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0f10
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0f11, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x0f12, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x0f13, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0f14
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0f15, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x0f16, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x0f17, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0f18
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0ef3, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x0ef4, .CM_3DLUT_MODE = 0x000034C0 + 0x0f7b,
.CM_3DLUT_INDEX = 0x000034C0 + 0x0f7c, .CM_3DLUT_DATA = 0x000034C0
+ 0x0f7d, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0f7e, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x0f7f, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x0f4a, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0f42, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x0f62, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x0f63, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0f64
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0f65, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x0f66, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x0f67, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0f68, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0f69, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x0f6a, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x0f6b, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0f6c, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0f6d, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x0f6e, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x0f6f, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0f70
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0f71, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x0f72, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x0f73, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0f74
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0f75, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x0f76, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x0f77, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0f78
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0f4b, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x0f4c, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x0f4d, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0f4e, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0f4f, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x0f50, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x0f51, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0f52, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0f53, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x0f54, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x0f55, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0f56
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0f57, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x0f58, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x0f59, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0f5a
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0f5b, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x0f5c, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x0f5d, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0f5e
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0f5f, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x0f60, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x0f61, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0f48, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x0ef2, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0f49
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0ef9, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0efa, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x0efb, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x0f1c, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x0f1d, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x0f1e, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x0ef5,},
547 dpp_regs(2)[2] = { .CM_DEALPHA = 0x000034C0 + 0x10ab, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x10a9, .CM_BIAS_CR_R = 0x000034C0 + 0x1011, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x1012, .PRE_DEGAM = 0x000034C0
+ 0x0fc3, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x1013, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x1016, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1014
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1014, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x1015, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x103a, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x103b
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x103c, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x103d, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x103e, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x103f
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x1043, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x1044, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x1045, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x1046,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x1047, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x1048, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x104c, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x105c
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x1049, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x104a, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x104b, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x1040
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x1041, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x1042, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x1017, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x1018
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x1019, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x101a, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x101b, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x101c
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x1020, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x1021, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x1022, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x1023,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x1024, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x1025, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x1029, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x1039
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x1026, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x1027, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x1028, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x101d
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x101e, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x101f, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x1004, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x1005, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x1006, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x1007, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1008, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x1009, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x100a, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x100b, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x100c, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x100d, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x100e, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x100f, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x1010, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x0fe3, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0fe4
, .OTG_H_BLANK = 0x000034C0 + 0x0fe5, .OTG_V_BLANK = 0x000034C0
+ 0x0fe6, .SCL_MODE = 0x000034C0 + 0x0fd1, .LB_DATA_FORMAT =
0x000034C0 + 0x0fea, .LB_MEMORY_CTRL = 0x000034C0 + 0x0feb, .
DSCL_AUTOCAL = 0x000034C0 + 0x0fe2, .SCL_TAP_CONTROL = 0x000034C0
+ 0x0fd2, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0fcf, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0fd0, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0fd4
, .MPC_SIZE = 0x000034C0 + 0x0fe9, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0fd6, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0fda, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fd8
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fdd, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0fd7, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0fd9, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0fdb, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x0fde, .RECOUT_START = 0x000034C0 + 0x0fe7, .
RECOUT_SIZE = 0x000034C0 + 0x0fe8, .PRE_DEALPHA = 0x000034C0 +
0x0fb4, .PRE_REALPHA = 0x000034C0 + 0x0fc4, .PRE_CSC_MODE = 0x000034C0
+ 0x0fb5, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0fb6, .PRE_CSC_C33_C34
= 0x000034C0 + 0x0fbb, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0fbc
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0fc1, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x0ff7, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0ff8
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0ffd, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x0ffe, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x1003, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x10a8, .CM_CONTROL =
0x000034C0 + 0x0ff6, .FORMAT_CONTROL = 0x000034C0 + 0x0fa6, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL
= 0x000034C0 + 0x0fc7, .CURSOR0_COLOR0 = 0x000034C0 + 0x0fc8
, .CURSOR0_COLOR1 = 0x000034C0 + 0x0fc9, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x0fca, .DPP_CONTROL = 0x000034C0 + 0x0f9b, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x10a7, .CURSOR_CONTROL = 0x000034C0
+ 0x0830, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0fb3, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x0fa7, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0fa8
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0fa9, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x0faa, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0fab, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x0fac, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0fad
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0fae, .COLOR_KEYER_RED =
0x000034C0 + 0x0faf, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0fb0
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0fb1, .CURSOR_CONTROL = 0x000034C0
+ 0x0830, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0ff0, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0fed, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x105d
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1084, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x1085, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x1086, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x108d
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x108e, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x108f, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x1090, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x1091
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1092, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x1096, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x1097, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1098,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x1099, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x109a, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x109b, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x109c
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x109d, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x109e, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x109f, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x10a0
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x10a1, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x10a2, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x10a3, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x10a4
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x10a5, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x10a6, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x1061, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x1062
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x1063, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x106a, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x106b, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x106c
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x106d, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x106e, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x106f, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1073,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x1074, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x1075, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x1076, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x1077,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x1078, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x1079, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x107a, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x107b
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x107c, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x107d, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x107e, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x107f
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x1080, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x1081, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x1082, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x1083
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x105e, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x105f, .CM_3DLUT_MODE = 0x000034C0 + 0x10e6,
.CM_3DLUT_INDEX = 0x000034C0 + 0x10e7, .CM_3DLUT_DATA = 0x000034C0
+ 0x10e8, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x10e9, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x10ea, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x10b5, .CM_SHAPER_CONTROL = 0x000034C0 + 0x10ad, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x10cd, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x10ce, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x10cf
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x10d0, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x10d1, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x10d2, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x10d3, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x10d4, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x10d5, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x10d6, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x10d7, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x10d8, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x10d9, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x10da, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x10db
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x10dc, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x10dd, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x10de, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x10df
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x10e0, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x10e1, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x10e2, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x10e3
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x10b6, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x10b7, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x10b8, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x10b9, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x10ba, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x10bb, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x10bc, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x10bd, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x10be, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x10bf, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x10c0, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x10c1
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x10c2, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x10c3, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x10c4, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x10c5
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x10c6, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x10c7, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x10c8, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x10c9
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x10ca, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x10cb, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x10cc, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x10b3, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x105d, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x10b4
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x1064, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x1065, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x1066, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x1087, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x1088, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x1089, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x1060,},
548 dpp_regs(3)[3] = { .CM_DEALPHA = 0x000034C0 + 0x1216, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x1214, .CM_BIAS_CR_R = 0x000034C0 + 0x117c, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x117d, .PRE_DEGAM = 0x000034C0
+ 0x112e, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x117e, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x1181, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x117f
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x117f, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x1180, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x11a5, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x11a6
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x11a7, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x11a8, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x11a9, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x11aa
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x11ae, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x11af, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x11b0, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x11b1,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x11b2, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x11b3, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x11b7, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x11c7
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x11b4, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x11b5, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x11b6, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x11ab
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x11ac, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x11ad, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x1182, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x1183
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x1184, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x1185, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x1186, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x1187
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x118b, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x118c, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x118d, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x118e,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x118f, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x1190, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x1194, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x11a4
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x1191, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x1192, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x1193, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x1188
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x1189, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x118a, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x116f, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x1170, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x1171, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x1172, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1173, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x1174, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x1175, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x1176, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x1177, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x1178, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x1179, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x117a, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x117b, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x114e, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x114f
, .OTG_H_BLANK = 0x000034C0 + 0x1150, .OTG_V_BLANK = 0x000034C0
+ 0x1151, .SCL_MODE = 0x000034C0 + 0x113c, .LB_DATA_FORMAT =
0x000034C0 + 0x1155, .LB_MEMORY_CTRL = 0x000034C0 + 0x1156, .
DSCL_AUTOCAL = 0x000034C0 + 0x114d, .SCL_TAP_CONTROL = 0x000034C0
+ 0x113d, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x113a, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x113b, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x113f
, .MPC_SIZE = 0x000034C0 + 0x1154, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x1141, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x1145, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1143
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1148, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x1142, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x1144, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x1146, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x1149, .RECOUT_START = 0x000034C0 + 0x1152, .
RECOUT_SIZE = 0x000034C0 + 0x1153, .PRE_DEALPHA = 0x000034C0 +
0x111f, .PRE_REALPHA = 0x000034C0 + 0x112f, .PRE_CSC_MODE = 0x000034C0
+ 0x1120, .PRE_CSC_C11_C12 = 0x000034C0 + 0x1121, .PRE_CSC_C33_C34
= 0x000034C0 + 0x1126, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x1127
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x112c, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x1162, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x1163
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x1168, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x1169, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x116e, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x1213, .CM_CONTROL =
0x000034C0 + 0x1161, .FORMAT_CONTROL = 0x000034C0 + 0x1111, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x1110, .CURSOR0_CONTROL
= 0x000034C0 + 0x1132, .CURSOR0_COLOR0 = 0x000034C0 + 0x1133
, .CURSOR0_COLOR1 = 0x000034C0 + 0x1134, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x1135, .DPP_CONTROL = 0x000034C0 + 0x1106, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x1212, .CURSOR_CONTROL = 0x000034C0
+ 0x090c, .ALPHA_2BIT_LUT = 0x000034C0 + 0x111e, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x1112, .FCNV_FP_BIAS_G = 0x000034C0 + 0x1113
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x1114, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x1115, .FCNV_FP_SCALE_G = 0x000034C0 + 0x1116, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x1117, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x1118
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x1119, .COLOR_KEYER_RED =
0x000034C0 + 0x111a, .COLOR_KEYER_GREEN = 0x000034C0 + 0x111b
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x111c, .CURSOR_CONTROL = 0x000034C0
+ 0x090c, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x115b, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x1158, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x11c8
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x11ef, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x11f0, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x11f1, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x11f8
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x11f9, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x11fa, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x11fb, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x11fc
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x11fd, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x1201, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x1202, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1203,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x1204, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x1205, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x1206, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x1207
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x1208, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x1209, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x120a, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x120b
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x120c, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x120d, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x120e, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x120f
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x1210, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x1211, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x11cc, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x11cd
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x11ce, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x11d5, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x11d6, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x11d7
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x11d8, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x11d9, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x11da, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x11de,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x11df, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x11e0, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x11e1, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x11e2,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x11e3, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x11e4, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x11e5, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x11e6
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x11e7, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x11e8, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x11e9, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x11ea
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x11eb, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x11ec, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x11ed, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x11ee
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x11c9, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x11ca, .CM_3DLUT_MODE = 0x000034C0 + 0x1251,
.CM_3DLUT_INDEX = 0x000034C0 + 0x1252, .CM_3DLUT_DATA = 0x000034C0
+ 0x1253, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x1254, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x1255, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x1220, .CM_SHAPER_CONTROL = 0x000034C0 + 0x1218, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x1238, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x1239, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x123a
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x123b, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x123c, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x123d, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x123e, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x123f, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x1240, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x1241, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x1242, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x1243, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x1244, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x1245, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x1246
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x1247, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x1248, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x1249, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x124a
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x124b, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x124c, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x124d, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x124e
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x1221, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x1222, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x1223, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x1224, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x1225, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x1226, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x1227, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x1228, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x1229, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x122a, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x122b, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x122c
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x122d, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x122e, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x122f, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1230
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1231, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x1232, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x1233, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1234
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x1235, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x1236, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x1237, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x121e, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x11c8, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x121f
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x11cf, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x11d0, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x11d1, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x11f2, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x11f3, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x11f4, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x11cb,},
549 dpp_regs(4)[4] = { .CM_DEALPHA = 0x000034C0 + 0x1381, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x137f, .CM_BIAS_CR_R = 0x000034C0 + 0x12e7, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x12e8, .PRE_DEGAM = 0x000034C0
+ 0x1299, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x12e9, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x12ec, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x12ea
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x12ea, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x12eb, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x1310, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x1311
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x1312, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x1313, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x1314, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x1315
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x1319, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x131a, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x131b, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x131c,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x131d, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x131e, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x1322, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x1332
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x131f, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x1320, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x1321, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x1316
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x1317, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x1318, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x12ed, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x12ee
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x12ef, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x12f0, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x12f1, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x12f2
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x12f6, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x12f7, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x12f8, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x12f9,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x12fa, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x12fb, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x12ff, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x130f
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x12fc, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x12fd, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x12fe, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x12f3
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x12f4, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x12f5, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x12da, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x12db, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x12dc, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x12dd, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x12de, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x12df, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x12e0, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x12e1, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x12e2, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x12e3, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x12e4, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x12e5, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x12e6, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x12b9, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x12ba
, .OTG_H_BLANK = 0x000034C0 + 0x12bb, .OTG_V_BLANK = 0x000034C0
+ 0x12bc, .SCL_MODE = 0x000034C0 + 0x12a7, .LB_DATA_FORMAT =
0x000034C0 + 0x12c0, .LB_MEMORY_CTRL = 0x000034C0 + 0x12c1, .
DSCL_AUTOCAL = 0x000034C0 + 0x12b8, .SCL_TAP_CONTROL = 0x000034C0
+ 0x12a8, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x12a5, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x12a6, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x12aa
, .MPC_SIZE = 0x000034C0 + 0x12bf, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x12ac, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x12b0, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x12ae
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x12b3, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x12ad, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x12af, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x12b1, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x12b4, .RECOUT_START = 0x000034C0 + 0x12bd, .
RECOUT_SIZE = 0x000034C0 + 0x12be, .PRE_DEALPHA = 0x000034C0 +
0x128a, .PRE_REALPHA = 0x000034C0 + 0x129a, .PRE_CSC_MODE = 0x000034C0
+ 0x128b, .PRE_CSC_C11_C12 = 0x000034C0 + 0x128c, .PRE_CSC_C33_C34
= 0x000034C0 + 0x1291, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x1292
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x1297, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x12cd, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x12ce
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x12d3, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x12d4, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x12d9, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x137e, .CM_CONTROL =
0x000034C0 + 0x12cc, .FORMAT_CONTROL = 0x000034C0 + 0x127c, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x127b, .CURSOR0_CONTROL
= 0x000034C0 + 0x129d, .CURSOR0_COLOR0 = 0x000034C0 + 0x129e
, .CURSOR0_COLOR1 = 0x000034C0 + 0x129f, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x12a0, .DPP_CONTROL = 0x000034C0 + 0x1271, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x137d, .CURSOR_CONTROL = 0x000034C0
+ 0x09e8, .ALPHA_2BIT_LUT = 0x000034C0 + 0x1289, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x127d, .FCNV_FP_BIAS_G = 0x000034C0 + 0x127e
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x127f, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x1280, .FCNV_FP_SCALE_G = 0x000034C0 + 0x1281, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x1282, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x1283
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x1284, .COLOR_KEYER_RED =
0x000034C0 + 0x1285, .COLOR_KEYER_GREEN = 0x000034C0 + 0x1286
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x1287, .CURSOR_CONTROL = 0x000034C0
+ 0x09e8, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x12c6, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x12c3, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x1333
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x135a, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x135b, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x135c, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x1363
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x1364, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x1365, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x1366, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x1367
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1368, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x136c, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x136d, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x136e,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x136f, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x1370, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x1371, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x1372
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x1373, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x1374, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x1375, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x1376
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x1377, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x1378, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x1379, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x137a
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x137b, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x137c, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x1337, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x1338
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x1339, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x1340, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x1341, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x1342
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x1343, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x1344, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x1345, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1349,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x134a, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x134b, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x134c, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x134d,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x134e, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x134f, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x1350, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x1351
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x1352, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x1353, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x1354, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x1355
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x1356, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x1357, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x1358, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x1359
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x1334, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x1335, .CM_3DLUT_MODE = 0x000034C0 + 0x13bc,
.CM_3DLUT_INDEX = 0x000034C0 + 0x13bd, .CM_3DLUT_DATA = 0x000034C0
+ 0x13be, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x13bf, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x13c0, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x138b, .CM_SHAPER_CONTROL = 0x000034C0 + 0x1383, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x13a3, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x13a4, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x13a5
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x13a6, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x13a7, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x13a8, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x13a9, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x13aa, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x13ab, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x13ac, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x13ad, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x13ae, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x13af, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x13b0, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x13b1
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x13b2, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x13b3, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x13b4, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x13b5
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x13b6, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x13b7, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x13b8, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x13b9
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x138c, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x138d, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x138e, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x138f, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x1390, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x1391, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x1392, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x1393, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x1394, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x1395, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x1396, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x1397
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x1398, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x1399, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x139a, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x139b
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x139c, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x139d, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x139e, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x139f
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x13a0, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x13a1, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x13a2, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x1389, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x1333, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x138a
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x133a, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x133b, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x133c, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x135d, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x135e, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x135f, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x1336,},
550 dpp_regs(5)[5] = { .CM_DEALPHA = 0x000034C0 + 0x14ec, .CM_MEM_PWR_STATUS
= 0x000034C0 + 0x14ea, .CM_BIAS_CR_R = 0x000034C0 + 0x1452, .
CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x1453, .PRE_DEGAM = 0x000034C0
+ 0x1404, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x1454, .CM_GAMCOR_LUT_CONTROL
= 0x000034C0 + 0x1457, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1455
, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1455, .CM_GAMCOR_LUT_DATA
= 0x000034C0 + 0x1456, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0
+ 0x147b, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x147c
, .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x147d, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x147e, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x147f, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x1480
, .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x1484, .CM_GAMCOR_RAMB_END_CNTL2_B
= 0x000034C0 + 0x1485, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0
+ 0x1486, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x1487,
.CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x1488, .CM_GAMCOR_RAMB_END_CNTL2_R
= 0x000034C0 + 0x1489, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0
+ 0x148d, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x149d
, .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x148a, .CM_GAMCOR_RAMB_OFFSET_G
= 0x000034C0 + 0x148b, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0
+ 0x148c, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x1481
, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x1482, .CM_GAMCOR_RAMB_START_BASE_CNTL_R
= 0x000034C0 + 0x1483, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0
+ 0x1458, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x1459
, .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x145a, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
= 0x000034C0 + 0x145b, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x145c, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x145d
, .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x1461, .CM_GAMCOR_RAMA_END_CNTL2_B
= 0x000034C0 + 0x1462, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0
+ 0x1463, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x1464,
.CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x1465, .CM_GAMCOR_RAMA_END_CNTL2_R
= 0x000034C0 + 0x1466, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0
+ 0x146a, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x147a
, .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x1467, .CM_GAMCOR_RAMA_OFFSET_G
= 0x000034C0 + 0x1468, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0
+ 0x1469, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x145e
, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x145f, .CM_GAMCOR_RAMA_START_BASE_CNTL_R
= 0x000034C0 + 0x1460, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 +
0x1445, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x1446, .CM_GAMUT_REMAP_C13_C14
= 0x000034C0 + 0x1447, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 +
0x1448, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1449, .CM_GAMUT_REMAP_C31_C32
= 0x000034C0 + 0x144a, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 +
0x144b, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x144c, .CM_GAMUT_REMAP_B_C13_C14
= 0x000034C0 + 0x144d, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0
+ 0x144e, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x144f, .
CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x1450, .CM_GAMUT_REMAP_B_C33_C34
= 0x000034C0 + 0x1451, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0
+ 0x1424, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x1425
, .OTG_H_BLANK = 0x000034C0 + 0x1426, .OTG_V_BLANK = 0x000034C0
+ 0x1427, .SCL_MODE = 0x000034C0 + 0x1412, .LB_DATA_FORMAT =
0x000034C0 + 0x142b, .LB_MEMORY_CTRL = 0x000034C0 + 0x142c, .
DSCL_AUTOCAL = 0x000034C0 + 0x1423, .SCL_TAP_CONTROL = 0x000034C0
+ 0x1413, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x1410, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x1411, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x1415
, .MPC_SIZE = 0x000034C0 + 0x142a, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x1417, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x141b, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1419
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x141e, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x1418, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x141a, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x141c, .SCL_VERT_FILTER_INIT_C
= 0x000034C0 + 0x141f, .RECOUT_START = 0x000034C0 + 0x1428, .
RECOUT_SIZE = 0x000034C0 + 0x1429, .PRE_DEALPHA = 0x000034C0 +
0x13f5, .PRE_REALPHA = 0x000034C0 + 0x1405, .PRE_CSC_MODE = 0x000034C0
+ 0x13f6, .PRE_CSC_C11_C12 = 0x000034C0 + 0x13f7, .PRE_CSC_C33_C34
= 0x000034C0 + 0x13fc, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x13fd
, .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x1402, .CM_POST_CSC_CONTROL
= 0x000034C0 + 0x1438, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x1439
, .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x143e, .CM_POST_CSC_B_C11_C12
= 0x000034C0 + 0x143f, .CM_POST_CSC_B_C33_C34 = 0x000034C0 +
0x1444, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x14e9, .CM_CONTROL =
0x000034C0 + 0x1437, .FORMAT_CONTROL = 0x000034C0 + 0x13e7, .
CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x13e6, .CURSOR0_CONTROL
= 0x000034C0 + 0x1408, .CURSOR0_COLOR0 = 0x000034C0 + 0x1409
, .CURSOR0_COLOR1 = 0x000034C0 + 0x140a, .CURSOR0_FP_SCALE_BIAS
= 0x000034C0 + 0x140b, .DPP_CONTROL = 0x000034C0 + 0x13dc, .
CM_HDR_MULT_COEF = 0x000034C0 + 0x14e8, .CURSOR_CONTROL = 0x000034C0
+ 0x0ac4, .ALPHA_2BIT_LUT = 0x000034C0 + 0x13f4, .FCNV_FP_BIAS_R
= 0x000034C0 + 0x13e8, .FCNV_FP_BIAS_G = 0x000034C0 + 0x13e9
, .FCNV_FP_BIAS_B = 0x000034C0 + 0x13ea, .FCNV_FP_SCALE_R = 0x000034C0
+ 0x13eb, .FCNV_FP_SCALE_G = 0x000034C0 + 0x13ec, .FCNV_FP_SCALE_B
= 0x000034C0 + 0x13ed, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x13ee
, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x13ef, .COLOR_KEYER_RED =
0x000034C0 + 0x13f0, .COLOR_KEYER_GREEN = 0x000034C0 + 0x13f1
, .COLOR_KEYER_BLUE = 0x000034C0 + 0x13f2, .CURSOR_CONTROL = 0x000034C0
+ 0x0ac4, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x1431, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x142e, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x149e
, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x14c5, .CM_BLNDGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x14c6, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x14c7, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x14ce
, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x14cf, .CM_BLNDGAM_RAMB_END_CNTL1_G
= 0x000034C0 + 0x14d0, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0
+ 0x14d1, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x14d2
, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x14d3, .CM_BLNDGAM_RAMB_REGION_0_1
= 0x000034C0 + 0x14d7, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0
+ 0x14d8, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x14d9,
.CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x14da, .CM_BLNDGAM_RAMB_REGION_8_9
= 0x000034C0 + 0x14db, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0
+ 0x14dc, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x14dd
, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x14de, .CM_BLNDGAM_RAMB_REGION_16_17
= 0x000034C0 + 0x14df, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0
+ 0x14e0, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x14e1
, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x14e2, .CM_BLNDGAM_RAMB_REGION_24_25
= 0x000034C0 + 0x14e3, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0
+ 0x14e4, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x14e5
, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x14e6, .CM_BLNDGAM_RAMB_REGION_32_33
= 0x000034C0 + 0x14e7, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x14a2, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x14a3
, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x14a4, .CM_BLNDGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x14ab, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x14ac, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x14ad
, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x14ae, .CM_BLNDGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x14af, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x14b0, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x14b4,
.CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x14b5, .CM_BLNDGAM_RAMA_REGION_4_5
= 0x000034C0 + 0x14b6, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0
+ 0x14b7, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x14b8,
.CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x14b9, .CM_BLNDGAM_RAMA_REGION_12_13
= 0x000034C0 + 0x14ba, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0
+ 0x14bb, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x14bc
, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x14bd, .CM_BLNDGAM_RAMA_REGION_20_21
= 0x000034C0 + 0x14be, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0
+ 0x14bf, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x14c0
, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x14c1, .CM_BLNDGAM_RAMA_REGION_28_29
= 0x000034C0 + 0x14c2, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0
+ 0x14c3, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x14c4
, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x149f, .CM_BLNDGAM_LUT_DATA
= 0x000034C0 + 0x14a0, .CM_3DLUT_MODE = 0x000034C0 + 0x1527,
.CM_3DLUT_INDEX = 0x000034C0 + 0x1528, .CM_3DLUT_DATA = 0x000034C0
+ 0x1529, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x152a, .CM_3DLUT_READ_WRITE_CONTROL
= 0x000034C0 + 0x152b, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0
+ 0x14f6, .CM_SHAPER_CONTROL = 0x000034C0 + 0x14ee, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x150e, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x150f, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x1510
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x1511, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x1512, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x1513, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x1514, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x1515, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x1516, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x1517, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x1518, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x1519, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x151a, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x151b, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x151c
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x151d, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x151e, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x151f, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x1520
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x1521, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x1522, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x1523, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x1524
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x14f7, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x14f8, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x14f9, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x14fa, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x14fb, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x14fc, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x14fd, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x14fe, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x14ff, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x1500, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x1501, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x1502
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x1503, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x1504, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x1505, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1506
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1507, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x1508, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x1509, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x150a
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x150b, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x150c, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x150d, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x14f4, .CM_BLNDGAM_CONTROL
= 0x000034C0 + 0x149e, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x14f5
, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x14a5, .
CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x14a6, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
= 0x000034C0 + 0x14a7, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B =
0x000034C0 + 0x14c8, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0
+ 0x14c9, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 +
0x14ca, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x14a1,},
551};
552
553static const struct dcn3_dpp_shift tf_shift = {
554 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT).GAMCOR_MEM_PWR_STATE = 0x0, .CM_DEALPHA_EN = 0x0, .CM_DEALPHA_ABLND
= 0x1, .CM_BIAS_CR_R = 0x0, .CM_BIAS_Y_G = 0x0, .CM_BIAS_CB_B
= 0x10, .GAMCOR_MEM_PWR_DIS = 0x2, .GAMCOR_MEM_PWR_FORCE = 0x0
, .PRE_DEGAM_MODE = 0x0, .PRE_DEGAM_SELECT = 0x4, .CM_GAMCOR_MODE
= 0x0, .CM_GAMCOR_SELECT = 0x2, .CM_GAMCOR_PWL_DISABLE = 0x3
, .CM_GAMCOR_MODE_CURRENT = 0x4, .CM_GAMCOR_SELECT_CURRENT = 0x6
, .CM_GAMCOR_LUT_INDEX = 0x0, .CM_GAMCOR_LUT_DATA = 0x0, .CM_GAMCOR_LUT_WRITE_COLOR_MASK
= 0x0, .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x3, .CM_GAMCOR_LUT_READ_DBG
= 0x5, .CM_GAMCOR_LUT_HOST_SEL = 0x6, .CM_GAMCOR_LUT_CONFIG_MODE
= 0x7, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B
= 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_B
= 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .CM_GAMCOR_RAMA_OFFSET_B
= 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0xc, .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .CM_GAMUT_REMAP_MODE = 0x0, .CM_GAMUT_REMAP_MODE_CURRENT
= 0x2, .CM_GAMUT_REMAP_C11 = 0x0, .CM_GAMUT_REMAP_C12 = 0x10
, .CM_GAMUT_REMAP_C13 = 0x0, .CM_GAMUT_REMAP_C14 = 0x10, .CM_GAMUT_REMAP_C21
= 0x0, .CM_GAMUT_REMAP_C22 = 0x10, .CM_GAMUT_REMAP_C23 = 0x0
, .CM_GAMUT_REMAP_C24 = 0x10, .CM_GAMUT_REMAP_C31 = 0x0, .CM_GAMUT_REMAP_C32
= 0x10, .CM_GAMUT_REMAP_C33 = 0x0, .CM_GAMUT_REMAP_C34 = 0x10
, .EXT_OVERSCAN_LEFT = 0x10, .EXT_OVERSCAN_RIGHT = 0x0, .EXT_OVERSCAN_BOTTOM
= 0x0, .EXT_OVERSCAN_TOP = 0x10, .OTG_H_BLANK_START = 0x0, .
OTG_H_BLANK_END = 0x10, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END
= 0x10, .INTERLEAVE_EN = 0x0, .LB_DATA_FORMAT__ALPHA_EN = 0x4
, .MEMORY_CONFIG = 0x0, .LB_MAX_PARTITIONS = 0x8, .AUTOCAL_MODE
= 0x0, .AUTOCAL_NUM_PIPE = 0x8, .AUTOCAL_PIPE_ID = 0xc, .SCL_V_NUM_TAPS
= 0x0, .SCL_H_NUM_TAPS = 0x4, .SCL_V_NUM_TAPS_C = 0x8, .SCL_H_NUM_TAPS_C
= 0xc, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .SCL_COEF_RAM_PHASE
= 0x8, .SCL_COEF_RAM_FILTER_TYPE = 0x10, .SCL_COEF_RAM_EVEN_TAP_COEF
= 0x0, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .SCL_COEF_RAM_ODD_TAP_COEF
= 0x10, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .SCL_H_2TAP_HARDCODE_COEF_EN
= 0x0, .SCL_H_2TAP_SHARP_EN = 0x4, .SCL_H_2TAP_SHARP_FACTOR =
0x8, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x10, .SCL_V_2TAP_SHARP_EN
= 0x14, .SCL_V_2TAP_SHARP_FACTOR = 0x18, .SCL_COEF_RAM_SELECT
= 0x8, .DSCL_MODE = 0x0, .RECOUT_START_X = 0x0, .RECOUT_START_Y
= 0x10, .RECOUT_WIDTH = 0x0, .RECOUT_HEIGHT = 0x10, .MPC_WIDTH
= 0x0, .MPC_HEIGHT = 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO
= 0x0, .SCL_H_SCALE_RATIO_C = 0x0, .SCL_V_SCALE_RATIO_C = 0x0
, .SCL_H_INIT_FRAC = 0x0, .SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC_C
= 0x0, .SCL_H_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC = 0x0, .SCL_V_INIT_INT
= 0x18, .SCL_V_INIT_FRAC_C = 0x0, .SCL_V_INIT_INT_C = 0x18, .
SCL_CHROMA_COEF_MODE = 0x10, .SCL_COEF_RAM_SELECT_CURRENT = 0xc
, .PRE_DEALPHA_EN = 0x0, .PRE_DEALPHA_ABLND_EN = 0x4, .PRE_REALPHA_EN
= 0x0, .PRE_REALPHA_ABLND_EN = 0x4, .PRE_CSC_MODE = 0x0, .PRE_CSC_MODE_CURRENT
= 0x2, .PRE_CSC_C11 = 0x0, .PRE_CSC_C12 = 0x10, .PRE_CSC_C33
= 0x0, .PRE_CSC_C34 = 0x10, .CM_POST_CSC_MODE = 0x0, .CM_POST_CSC_MODE_CURRENT
= 0x2, .CM_POST_CSC_C11 = 0x0, .CM_POST_CSC_C12 = 0x10, .CM_POST_CSC_C33
= 0x0, .CM_POST_CSC_C34 = 0x10, .CNVC_BYPASS = 0xc, .FORMAT_CONTROL__ALPHA_EN
= 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CNVC_SURFACE_PIXEL_FORMAT
= 0x0, .CNVC_ALPHA_PLANE_ENABLE = 0x8, .CUR0_MODE = 0x4, .CUR0_EXPANSION_MODE
= 0x1, .CUR0_ENABLE = 0x0, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 =
0x0, .CUR0_FP_BIAS = 0x10, .CUR0_FP_SCALE = 0x0, .DPP_CLOCK_ENABLE
= 0x4, .CM_HDR_MULT_COEF = 0x0, .CM_BYPASS = 0x0, .CURSOR_MODE
= 0x8, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18,
.CURSOR_ENABLE = 0x0, .FORMAT_CNV16 = 0x4, .CNVC_BYPASS_MSB_ALIGN
= 0xd, .CLAMP_POSITIVE = 0x10, .CLAMP_POSITIVE_C = 0x11, .FORMAT_CROSSBAR_R
= 0x18, .FORMAT_CROSSBAR_G = 0x1a, .FORMAT_CROSSBAR_B = 0x1c
, .ALPHA_2BIT_LUT0 = 0x0, .ALPHA_2BIT_LUT1 = 0x8, .ALPHA_2BIT_LUT2
= 0x10, .ALPHA_2BIT_LUT3 = 0x18, .FCNV_FP_BIAS_R = 0x0, .FCNV_FP_BIAS_G
= 0x0, .FCNV_FP_BIAS_B = 0x0, .FCNV_FP_SCALE_R = 0x0, .FCNV_FP_SCALE_G
= 0x0, .FCNV_FP_SCALE_B = 0x0, .COLOR_KEYER_EN = 0x0, .COLOR_KEYER_MODE
= 0x4, .COLOR_KEYER_ALPHA_LOW = 0x0, .COLOR_KEYER_ALPHA_HIGH
= 0x10, .COLOR_KEYER_RED_LOW = 0x0, .COLOR_KEYER_RED_HIGH = 0x10
, .COLOR_KEYER_GREEN_LOW = 0x0, .COLOR_KEYER_GREEN_HIGH = 0x10
, .COLOR_KEYER_BLUE_LOW = 0x0, .COLOR_KEYER_BLUE_HIGH = 0x10,
.CUR0_PIX_INV_MODE = 0x2, .CUR0_PIXEL_ALPHA_MOD_EN = 0x7, .CUR0_ROM_EN
= 0x3, .OBUF_MEM_PWR_FORCE = 0x0, .LUT_MEM_PWR_FORCE = 0x0, .
CM_3DLUT_MODE = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0
, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_START_G
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .
CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .
CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .
CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_LUT_INDEX = 0x0, .CM_BLNDGAM_LUT_DATA = 0x0
, .BLNDGAM_MEM_PWR_FORCE = 0x4, .CM_3DLUT_MODE = 0x0, .CM_3DLUT_SIZE
= 0x4, .CM_3DLUT_INDEX = 0x0, .CM_3DLUT_DATA0 = 0x0, .CM_3DLUT_DATA1
= 0x10, .CM_3DLUT_DATA_30BIT = 0x2, .CM_3DLUT_WRITE_EN_MASK =
0x0, .CM_3DLUT_RAM_SEL = 0x4, .CM_3DLUT_30BIT_EN = 0x8, .CM_3DLUT_READ_SEL
= 0x10, .CM_SHAPER_LUT_MODE = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_B
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_G
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_R
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMB_EXP_REGION_END_B
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_G
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_R
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION_START_B
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_G
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_R
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMA_EXP_REGION_END_B
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_G
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_R
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_LUT_WRITE_EN_MASK
= 0x0, .CM_SHAPER_LUT_WRITE_SEL = 0x4, .CM_SHAPER_LUT_INDEX =
0x0, .CM_SHAPER_LUT_DATA = 0x0, .CM_BLNDGAM_MODE = 0x0, .CM_BLNDGAM_MODE_CURRENT
= 0x4, .CM_BLNDGAM_SELECT_CURRENT = 0x6, .CM_BLNDGAM_SELECT =
0x2, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_G
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_LUT_WRITE_COLOR_MASK
= 0x0, .CM_BLNDGAM_LUT_HOST_SEL = 0x6, .CM_BLNDGAM_LUT_CONFIG_MODE
= 0x7, .CM_3DLUT_MODE_CURRENT = 0x8, .CM_SHAPER_MODE_CURRENT
= 0x2
555};
556
557static const struct dcn3_dpp_mask tf_mask = {
558 DPP_REG_LIST_SH_MASK_DCN30(_MASK).GAMCOR_MEM_PWR_STATE = 0x00000003L, .CM_DEALPHA_EN = 0x00000001L
, .CM_DEALPHA_ABLND = 0x00000002L, .CM_BIAS_CR_R = 0x0000FFFFL
, .CM_BIAS_Y_G = 0x0000FFFFL, .CM_BIAS_CB_B = 0xFFFF0000L, .GAMCOR_MEM_PWR_DIS
= 0x00000004L, .GAMCOR_MEM_PWR_FORCE = 0x00000003L, .PRE_DEGAM_MODE
= 0x00000003L, .PRE_DEGAM_SELECT = 0x00000070L, .CM_GAMCOR_MODE
= 0x00000003L, .CM_GAMCOR_SELECT = 0x00000004L, .CM_GAMCOR_PWL_DISABLE
= 0x00000008L, .CM_GAMCOR_MODE_CURRENT = 0x00000030L, .CM_GAMCOR_SELECT_CURRENT
= 0x00000040L, .CM_GAMCOR_LUT_INDEX = 0x000001FFL, .CM_GAMCOR_LUT_DATA
= 0x0003FFFFL, .CM_GAMCOR_LUT_WRITE_COLOR_MASK = 0x00000007L
, .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x00000018L, .CM_GAMCOR_LUT_READ_DBG
= 0x00000020L, .CM_GAMCOR_LUT_HOST_SEL = 0x00000040L, .CM_GAMCOR_LUT_CONFIG_MODE
= 0x00000080L, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B
= 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL
, .CM_GAMCOR_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B
= 0xFFFF0000L, .CM_GAMCOR_RAMA_OFFSET_B = 0x0007FFFFL, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET
= 0x000001FFL, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L
, .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x70000000L, .CM_GAMUT_REMAP_MODE = 0x00000003L, .CM_GAMUT_REMAP_MODE_CURRENT
= 0x0000000CL, .CM_GAMUT_REMAP_C11 = 0x0000FFFFL, .CM_GAMUT_REMAP_C12
= 0xFFFF0000L, .CM_GAMUT_REMAP_C13 = 0x0000FFFFL, .CM_GAMUT_REMAP_C14
= 0xFFFF0000L, .CM_GAMUT_REMAP_C21 = 0x0000FFFFL, .CM_GAMUT_REMAP_C22
= 0xFFFF0000L, .CM_GAMUT_REMAP_C23 = 0x0000FFFFL, .CM_GAMUT_REMAP_C24
= 0xFFFF0000L, .CM_GAMUT_REMAP_C31 = 0x0000FFFFL, .CM_GAMUT_REMAP_C32
= 0xFFFF0000L, .CM_GAMUT_REMAP_C33 = 0x0000FFFFL, .CM_GAMUT_REMAP_C34
= 0xFFFF0000L, .EXT_OVERSCAN_LEFT = 0x1FFF0000L, .EXT_OVERSCAN_RIGHT
= 0x00001FFFL, .EXT_OVERSCAN_BOTTOM = 0x00001FFFL, .EXT_OVERSCAN_TOP
= 0x1FFF0000L, .OTG_H_BLANK_START = 0x00003FFFL, .OTG_H_BLANK_END
= 0x3FFF0000L, .OTG_V_BLANK_START = 0x00003FFFL, .OTG_V_BLANK_END
= 0x3FFF0000L, .INTERLEAVE_EN = 0x00000001L, .LB_DATA_FORMAT__ALPHA_EN
= 0x00000010L, .MEMORY_CONFIG = 0x00000003L, .LB_MAX_PARTITIONS
= 0x00003F00L, .AUTOCAL_MODE = 0x00000003L, .AUTOCAL_NUM_PIPE
= 0x00000300L, .AUTOCAL_PIPE_ID = 0x00003000L, .SCL_V_NUM_TAPS
= 0x00000007L, .SCL_H_NUM_TAPS = 0x00000070L, .SCL_V_NUM_TAPS_C
= 0x00000700L, .SCL_H_NUM_TAPS_C = 0x00007000L, .SCL_COEF_RAM_TAP_PAIR_IDX
= 0x00000003L, .SCL_COEF_RAM_PHASE = 0x00003F00L, .SCL_COEF_RAM_FILTER_TYPE
= 0x00070000L, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x00003FFFL, .SCL_COEF_RAM_EVEN_TAP_COEF_EN
= 0x00008000L, .SCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .SCL_COEF_RAM_ODD_TAP_COEF_EN
= 0x80000000L, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x00000001L, .
SCL_H_2TAP_SHARP_EN = 0x00000010L, .SCL_H_2TAP_SHARP_FACTOR =
0x00000700L, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x00010000L, .SCL_V_2TAP_SHARP_EN
= 0x00100000L, .SCL_V_2TAP_SHARP_FACTOR = 0x07000000L, .SCL_COEF_RAM_SELECT
= 0x00000100L, .DSCL_MODE = 0x00000007L, .RECOUT_START_X = 0x00001FFFL
, .RECOUT_START_Y = 0x1FFF0000L, .RECOUT_WIDTH = 0x00003FFFL,
.RECOUT_HEIGHT = 0x3FFF0000L, .MPC_WIDTH = 0x00003FFFL, .MPC_HEIGHT
= 0x3FFF0000L, .SCL_H_SCALE_RATIO = 0x07FFFFFFL, .SCL_V_SCALE_RATIO
= 0x07FFFFFFL, .SCL_H_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_V_SCALE_RATIO_C
= 0x07FFFFFFL, .SCL_H_INIT_FRAC = 0x00FFFFFFL, .SCL_H_INIT_INT
= 0x0F000000L, .SCL_H_INIT_FRAC_C = 0x00FFFFFFL, .SCL_H_INIT_INT_C
= 0x0F000000L, .SCL_V_INIT_FRAC = 0x00FFFFFFL, .SCL_V_INIT_INT
= 0x0F000000L, .SCL_V_INIT_FRAC_C = 0x00FFFFFFL, .SCL_V_INIT_INT_C
= 0x0F000000L, .SCL_CHROMA_COEF_MODE = 0x00010000L, .SCL_COEF_RAM_SELECT_CURRENT
= 0x00001000L, .PRE_DEALPHA_EN = 0x00000001L, .PRE_DEALPHA_ABLND_EN
= 0x00000010L, .PRE_REALPHA_EN = 0x00000001L, .PRE_REALPHA_ABLND_EN
= 0x00000010L, .PRE_CSC_MODE = 0x00000003L, .PRE_CSC_MODE_CURRENT
= 0x0000000CL, .PRE_CSC_C11 = 0x0000FFFFL, .PRE_CSC_C12 = 0xFFFF0000L
, .PRE_CSC_C33 = 0x0000FFFFL, .PRE_CSC_C34 = 0xFFFF0000L, .CM_POST_CSC_MODE
= 0x00000003L, .CM_POST_CSC_MODE_CURRENT = 0x0000000CL, .CM_POST_CSC_C11
= 0x0000FFFFL, .CM_POST_CSC_C12 = 0xFFFF0000L, .CM_POST_CSC_C33
= 0x0000FFFFL, .CM_POST_CSC_C34 = 0xFFFF0000L, .CNVC_BYPASS =
0x00001000L, .FORMAT_CONTROL__ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE
= 0x00000001L, .CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CNVC_ALPHA_PLANE_ENABLE
= 0x00000100L, .CUR0_MODE = 0x00000070L, .CUR0_EXPANSION_MODE
= 0x00000002L, .CUR0_ENABLE = 0x00000001L, .CUR0_COLOR0 = 0x00FFFFFFL
, .CUR0_COLOR1 = 0x00FFFFFFL, .CUR0_FP_BIAS = 0xFFFF0000L, .CUR0_FP_SCALE
= 0x0000FFFFL, .DPP_CLOCK_ENABLE = 0x00000010L, .CM_HDR_MULT_COEF
= 0x0007FFFFL, .CM_BYPASS = 0x00000001L, .CURSOR_MODE = 0x00000700L
, .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L
, .CURSOR_ENABLE = 0x00000001L, .FORMAT_CNV16 = 0x00000010L, .
CNVC_BYPASS_MSB_ALIGN = 0x00002000L, .CLAMP_POSITIVE = 0x00010000L
, .CLAMP_POSITIVE_C = 0x00020000L, .FORMAT_CROSSBAR_R = 0x03000000L
, .FORMAT_CROSSBAR_G = 0x0C000000L, .FORMAT_CROSSBAR_B = 0x30000000L
, .ALPHA_2BIT_LUT0 = 0x000000FFL, .ALPHA_2BIT_LUT1 = 0x0000FF00L
, .ALPHA_2BIT_LUT2 = 0x00FF0000L, .ALPHA_2BIT_LUT3 = 0xFF000000L
, .FCNV_FP_BIAS_R = 0x0007FFFFL, .FCNV_FP_BIAS_G = 0x0007FFFFL
, .FCNV_FP_BIAS_B = 0x0007FFFFL, .FCNV_FP_SCALE_R = 0x0007FFFFL
, .FCNV_FP_SCALE_G = 0x0007FFFFL, .FCNV_FP_SCALE_B = 0x0007FFFFL
, .COLOR_KEYER_EN = 0x00000001L, .COLOR_KEYER_MODE = 0x00000030L
, .COLOR_KEYER_ALPHA_LOW = 0x0000FFFFL, .COLOR_KEYER_ALPHA_HIGH
= 0xFFFF0000L, .COLOR_KEYER_RED_LOW = 0x0000FFFFL, .COLOR_KEYER_RED_HIGH
= 0xFFFF0000L, .COLOR_KEYER_GREEN_LOW = 0x0000FFFFL, .COLOR_KEYER_GREEN_HIGH
= 0xFFFF0000L, .COLOR_KEYER_BLUE_LOW = 0x0000FFFFL, .COLOR_KEYER_BLUE_HIGH
= 0xFFFF0000L, .CUR0_PIX_INV_MODE = 0x00000004L, .CUR0_PIXEL_ALPHA_MOD_EN
= 0x00000080L, .CUR0_ROM_EN = 0x00000008L, .OBUF_MEM_PWR_FORCE
= 0x00000003L, .LUT_MEM_PWR_FORCE = 0x00000003L, .CM_3DLUT_MODE
= 0x00000003L, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G
= 0xFFFF0000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0xFFFF0000L
, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0xFFFF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_LUT_INDEX = 0x000001FFL, .CM_BLNDGAM_LUT_DATA
= 0x0003FFFFL, .BLNDGAM_MEM_PWR_FORCE = 0x00000030L, .CM_3DLUT_MODE
= 0x00000003L, .CM_3DLUT_SIZE = 0x00000010L, .CM_3DLUT_INDEX
= 0x000007FFL, .CM_3DLUT_DATA0 = 0x0000FFFFL, .CM_3DLUT_DATA1
= 0xFFFF0000L, .CM_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .CM_3DLUT_WRITE_EN_MASK
= 0x0000000FL, .CM_3DLUT_RAM_SEL = 0x00000010L, .CM_3DLUT_30BIT_EN
= 0x00000100L, .CM_3DLUT_READ_SEL = 0x00030000L, .CM_SHAPER_LUT_MODE
= 0x00000003L, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0003FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0003FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B
= 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0000FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_R
= 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x3FFF0000L
, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0003FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B
= 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0000FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_R
= 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x3FFF0000L
, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L, .
CM_SHAPER_LUT_WRITE_SEL = 0x00000010L, .CM_SHAPER_LUT_INDEX =
0x000000FFL, .CM_SHAPER_LUT_DATA = 0x00FFFFFFL, .CM_BLNDGAM_MODE
= 0x00000003L, .CM_BLNDGAM_MODE_CURRENT = 0x00000030L, .CM_BLNDGAM_SELECT_CURRENT
= 0x00000040L, .CM_BLNDGAM_SELECT = 0x00000004L, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_B
= 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_BLNDGAM_LUT_WRITE_COLOR_MASK
= 0x00000007L, .CM_BLNDGAM_LUT_HOST_SEL = 0x00000040L, .CM_BLNDGAM_LUT_CONFIG_MODE
= 0x00000080L, .CM_3DLUT_MODE_CURRENT = 0x00000300L, .CM_SHAPER_MODE_CURRENT
= 0x0000000CL
559};
560
561#define opp_regs(id)[id] = { .FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX
+ mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX
+ mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX
+ mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
+ mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL =
DCN_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
+ mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX
+ mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1
= DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX
+ mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX
+ mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX
+ mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX
+ mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX
+ mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX
+ mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX
+ mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX
+ mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX
+ mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX
+ mmFMTid_FMT_422_CONTROL,}\
562[id] = {\
563 OPP_REG_LIST_DCN30(id).FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX
+ mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX
+ mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX
+ mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
+ mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL =
DCN_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
+ mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX
+ mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1
= DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX
+ mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX
+ mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX
+ mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX
+ mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX
+ mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX
+ mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX
+ mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX
+ mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX
+ mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX
+ mmFMTid_FMT_422_CONTROL,\
564}
565
566static const struct dcn20_opp_registers opp_regs[] = {
567 opp_regs(0)[0] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1841, .FMT_CONTROL
= 0x000034C0 + 0x1840, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x1842, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1843, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x1844, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1845
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x183f, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x1847, .OPPBUF_CONTROL = 0x000034C0 + 0x1884
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1885, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x1886, .OPP_PIPE_CONTROL = 0x000034C0 + 0x188c
, .DPG_CONTROL = 0x000034C0 + 0x1854, .DPG_DIMENSIONS = 0x000034C0
+ 0x1856, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x185a, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x1859, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1858
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x1857, .DPG_RAMP_CONTROL =
0x000034C0 + 0x1855, .DPG_STATUS = 0x000034C0 + 0x185b, .FMT_422_CONTROL
= 0x000034C0 + 0x1849,},
568 opp_regs(1)[1] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x189b, .FMT_CONTROL
= 0x000034C0 + 0x189a, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x189c, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x189d, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x189e, .FMT_CLAMP_CNTL = 0x000034C0 + 0x189f
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1899, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x18a1, .OPPBUF_CONTROL = 0x000034C0 + 0x18de
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x18df, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x18e0, .OPP_PIPE_CONTROL = 0x000034C0 + 0x18e6
, .DPG_CONTROL = 0x000034C0 + 0x18ae, .DPG_DIMENSIONS = 0x000034C0
+ 0x18b0, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x18b4, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x18b3, .DPG_COLOUR_G_Y = 0x000034C0 + 0x18b2
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x18b1, .DPG_RAMP_CONTROL =
0x000034C0 + 0x18af, .DPG_STATUS = 0x000034C0 + 0x18b5, .FMT_422_CONTROL
= 0x000034C0 + 0x18a3,},
569 opp_regs(2)[2] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x18f5, .FMT_CONTROL
= 0x000034C0 + 0x18f4, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x18f6, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x18f7, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x18f8, .FMT_CLAMP_CNTL = 0x000034C0 + 0x18f9
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x18f3, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x18fb, .OPPBUF_CONTROL = 0x000034C0 + 0x1938
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1939, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x193a, .OPP_PIPE_CONTROL = 0x000034C0 + 0x1940
, .DPG_CONTROL = 0x000034C0 + 0x1908, .DPG_DIMENSIONS = 0x000034C0
+ 0x190a, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x190e, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x190d, .DPG_COLOUR_G_Y = 0x000034C0 + 0x190c
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x190b, .DPG_RAMP_CONTROL =
0x000034C0 + 0x1909, .DPG_STATUS = 0x000034C0 + 0x190f, .FMT_422_CONTROL
= 0x000034C0 + 0x18fd,},
570 opp_regs(3)[3] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x194f, .FMT_CONTROL
= 0x000034C0 + 0x194e, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x1950, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1951, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x1952, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1953
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x194d, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x1955, .OPPBUF_CONTROL = 0x000034C0 + 0x1992
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1993, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x1994, .OPP_PIPE_CONTROL = 0x000034C0 + 0x199a
, .DPG_CONTROL = 0x000034C0 + 0x1962, .DPG_DIMENSIONS = 0x000034C0
+ 0x1964, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x1968, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x1967, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1966
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x1965, .DPG_RAMP_CONTROL =
0x000034C0 + 0x1963, .DPG_STATUS = 0x000034C0 + 0x1969, .FMT_422_CONTROL
= 0x000034C0 + 0x1957,},
571 opp_regs(4)[4] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x19a9, .FMT_CONTROL
= 0x000034C0 + 0x19a8, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x19aa, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x19ab, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x19ac, .FMT_CLAMP_CNTL = 0x000034C0 + 0x19ad
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x19a7, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x19af, .OPPBUF_CONTROL = 0x000034C0 + 0x19ec
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x19ed, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x19ee, .OPP_PIPE_CONTROL = 0x000034C0 + 0x19f4
, .DPG_CONTROL = 0x000034C0 + 0x19bc, .DPG_DIMENSIONS = 0x000034C0
+ 0x19be, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x19c2, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x19c1, .DPG_COLOUR_G_Y = 0x000034C0 + 0x19c0
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x19bf, .DPG_RAMP_CONTROL =
0x000034C0 + 0x19bd, .DPG_STATUS = 0x000034C0 + 0x19c3, .FMT_422_CONTROL
= 0x000034C0 + 0x19b1,},
572 opp_regs(5)[5] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1a03, .FMT_CONTROL
= 0x000034C0 + 0x1a02, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x1a04, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1a05, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x1a06, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1a07
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1a01, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x1a09, .OPPBUF_CONTROL = 0x000034C0 + 0x1a46
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1a47, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x1a48, .OPP_PIPE_CONTROL = 0x000034C0 + 0x1a4e
, .DPG_CONTROL = 0x000034C0 + 0x1a16, .DPG_DIMENSIONS = 0x000034C0
+ 0x1a18, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x1a1c, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x1a1b, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1a1a
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x1a19, .DPG_RAMP_CONTROL =
0x000034C0 + 0x1a17, .DPG_STATUS = 0x000034C0 + 0x1a1d, .FMT_422_CONTROL
= 0x000034C0 + 0x1a0b,}
573};
574
575static const struct dcn20_opp_shift opp_shift = {
576 OPP_MASK_SH_LIST_DCN20(__SHIFT).FMT_TRUNCATE_EN = 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE
= 0x1, .FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_MODE
= 0x9, .FMT_SPATIAL_DITHER_DEPTH = 0xb, .FMT_TEMPORAL_DITHER_EN
= 0x10, .FMT_HIGHPASS_RANDOM_ENABLE = 0xf, .FMT_FRAME_RANDOM_ENABLE
= 0xd, .FMT_RGB_RANDOM_ENABLE = 0xe, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX
= 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_PIXEL_ENCODING
= 0x10, .FMT_STEREOSYNC_OVERRIDE = 0x0, .FMT_RAND_R_SEED = 0x0
, .FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_CLAMP_DATA_EN
= 0x0, .FMT_CLAMP_COLOR_FORMAT = 0x10, .FMT_DYNAMIC_EXP_EN =
0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_MAP420MEM_PWR_FORCE =
0x0, .OPPBUF_ACTIVE_WIDTH = 0x0, .OPPBUF_PIXEL_REPETITION = 0x18
, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x0, .OPPBUF_3D_VACT_SPACE2_SIZE
= 0xa, .OPP_PIPE_CLOCK_EN = 0x0, .DPG_EN = 0x0, .DPG_MODE = 0x4
, .DPG_DYNAMIC_RANGE = 0x8, .DPG_BIT_DEPTH = 0xc, .DPG_VRES =
0x10, .DPG_HRES = 0x14, .DPG_ACTIVE_WIDTH = 0x10, .DPG_ACTIVE_HEIGHT
= 0x0, .DPG_X_OFFSET = 0x0, .DPG_SEGMENT_WIDTH = 0x10, .DPG_COLOUR0_R_CR
= 0x0, .DPG_COLOUR1_R_CR = 0x10, .DPG_COLOUR0_B_CB = 0x0, .DPG_COLOUR1_B_CB
= 0x10, .DPG_COLOUR0_G_Y = 0x0, .DPG_COLOUR1_G_Y = 0x10, .DPG_RAMP0_OFFSET
= 0x0, .DPG_INC0 = 0x18, .DPG_INC1 = 0x1c, .DPG_DOUBLE_BUFFER_PENDING
= 0x0, .OPPBUF_DISPLAY_SEGMENTATION = 0x10, .OPPBUF_OVERLAP_PIXEL_NUM
= 0x14, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x0
577};
578
579static const struct dcn20_opp_mask opp_mask = {
580 OPP_MASK_SH_LIST_DCN20(_MASK).FMT_TRUNCATE_EN = 0x00000001L, .FMT_TRUNCATE_DEPTH = 0x00000030L
, .FMT_TRUNCATE_MODE = 0x00000002L, .FMT_SPATIAL_DITHER_EN = 0x00000100L
, .FMT_SPATIAL_DITHER_MODE = 0x00000600L, .FMT_SPATIAL_DITHER_DEPTH
= 0x00001800L, .FMT_TEMPORAL_DITHER_EN = 0x00010000L, .FMT_HIGHPASS_RANDOM_ENABLE
= 0x00008000L, .FMT_FRAME_RANDOM_ENABLE = 0x00002000L, .FMT_RGB_RANDOM_ENABLE
= 0x00004000L, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x00000F00L
, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x00003000L, .
FMT_PIXEL_ENCODING = 0x00030000L, .FMT_STEREOSYNC_OVERRIDE = 0x00000001L
, .FMT_RAND_R_SEED = 0x000000FFL, .FMT_RAND_G_SEED = 0x000000FFL
, .FMT_RAND_B_SEED = 0x000000FFL, .FMT_CLAMP_DATA_EN = 0x00000001L
, .FMT_CLAMP_COLOR_FORMAT = 0x00070000L, .FMT_DYNAMIC_EXP_EN =
0x00000001L, .FMT_DYNAMIC_EXP_MODE = 0x00000010L, .FMT_MAP420MEM_PWR_FORCE
= 0x00000003L, .OPPBUF_ACTIVE_WIDTH = 0x00003FFFL, .OPPBUF_PIXEL_REPETITION
= 0x0F000000L, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x000003FFL, .OPPBUF_3D_VACT_SPACE2_SIZE
= 0x000FFC00L, .OPP_PIPE_CLOCK_EN = 0x00000001L, .DPG_EN = 0x00000001L
, .DPG_MODE = 0x00000070L, .DPG_DYNAMIC_RANGE = 0x00000100L, .
DPG_BIT_DEPTH = 0x00003000L, .DPG_VRES = 0x000F0000L, .DPG_HRES
= 0x00F00000L, .DPG_ACTIVE_WIDTH = 0x3FFF0000L, .DPG_ACTIVE_HEIGHT
= 0x00003FFFL, .DPG_X_OFFSET = 0x00003FFFL, .DPG_SEGMENT_WIDTH
= 0x3FFF0000L, .DPG_COLOUR0_R_CR = 0x0000FFFFL, .DPG_COLOUR1_R_CR
= 0xFFFF0000L, .DPG_COLOUR0_B_CB = 0x0000FFFFL, .DPG_COLOUR1_B_CB
= 0xFFFF0000L, .DPG_COLOUR0_G_Y = 0x0000FFFFL, .DPG_COLOUR1_G_Y
= 0xFFFF0000L, .DPG_RAMP0_OFFSET = 0x0000FFFFL, .DPG_INC0 = 0x0F000000L
, .DPG_INC1 = 0xF0000000L, .DPG_DOUBLE_BUFFER_PENDING = 0x00000001L
, .OPPBUF_DISPLAY_SEGMENTATION = 0x00070000L, .OPPBUF_OVERLAP_PIXEL_NUM
= 0x00F00000L, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x00000001L
581};
582
583#define aux_engine_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX
+ mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX
+ mmDP_AUXid_AUX_SW_STATUS, .AUXN_IMPCAL = 0, .AUXP_IMPCAL =
0, .AUX_RESET_MASK = 0x00000010L, }\
584[id] = {\
585 AUX_COMMON_REG_LIST0(id).AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX
+ mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX
+ mmDP_AUXid_AUX_SW_STATUS, \
586 .AUXN_IMPCAL = 0, \
587 .AUXP_IMPCAL = 0, \
588 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK0x00000010L, \
589}
590
591static const struct dce110_aux_registers aux_engine_regs[] = {
592 aux_engine_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_ARB_CONTROL =
0x000034C0 + 0x1f52, .AUX_SW_DATA = 0x000034C0 + 0x1f56, .AUX_SW_CONTROL
= 0x000034C0 + 0x1f51, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1f53, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b, .AUX_SW_STATUS
= 0x000034C0 + 0x1f54, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, },
593 aux_engine_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_ARB_CONTROL =
0x000034C0 + 0x1f6e, .AUX_SW_DATA = 0x000034C0 + 0x1f72, .AUX_SW_CONTROL
= 0x000034C0 + 0x1f6d, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1f6f, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77, .AUX_SW_STATUS
= 0x000034C0 + 0x1f70, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, },
594 aux_engine_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_ARB_CONTROL =
0x000034C0 + 0x1f8a, .AUX_SW_DATA = 0x000034C0 + 0x1f8e, .AUX_SW_CONTROL
= 0x000034C0 + 0x1f89, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1f8b, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93, .AUX_SW_STATUS
= 0x000034C0 + 0x1f8c, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, },
595 aux_engine_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_ARB_CONTROL =
0x000034C0 + 0x1fa6, .AUX_SW_DATA = 0x000034C0 + 0x1faa, .AUX_SW_CONTROL
= 0x000034C0 + 0x1fa5, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1fa7, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf, .AUX_SW_STATUS
= 0x000034C0 + 0x1fa8, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, },
596 aux_engine_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_ARB_CONTROL =
0x000034C0 + 0x1fc2, .AUX_SW_DATA = 0x000034C0 + 0x1fc6, .AUX_SW_CONTROL
= 0x000034C0 + 0x1fc1, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1fc3, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb, .AUX_SW_STATUS
= 0x000034C0 + 0x1fc4, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, },
597 aux_engine_regs(5)[5] = { .AUX_CONTROL = 0x000034C0 + 0x1fdc, .AUX_ARB_CONTROL =
0x000034C0 + 0x1fde, .AUX_SW_DATA = 0x000034C0 + 0x1fe2, .AUX_SW_CONTROL
= 0x000034C0 + 0x1fdd, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1fdf, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fe7, .AUX_SW_STATUS
= 0x000034C0 + 0x1fe0, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .
AUX_RESET_MASK = 0x00000010L, }
598};
599
600#define dwbc_regs_dcn3(id)[id] = { .DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL
= 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, .
FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0
+ 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE
= 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f
, .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0
+ 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G
= 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234
, .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
= 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0
+ 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET
= 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294
, .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT
= 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0
+ 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, .
DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24
= 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0
+ 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, .
DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14
= 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0
+ 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, .
DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34
= 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3
, .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA
= 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6
, .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G
= 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0
+ 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G
= 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, .
DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G
= 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 +
0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, .
DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0,
.DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4,
.DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8,
.DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc,
.DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0
+ 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0
, .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R
= 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, .
DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, .
DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G
= 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 +
0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3
= 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0
+ 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, .
DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11
= 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0
+ 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3,
.DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19
= 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0
+ 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7,
.DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27
= 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0
+ 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb,
.DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,}\
601[id] = {\
602 DWBC_COMMON_REG_LIST_DCN30(id).DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL
= 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, .
FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0
+ 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE
= 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f
, .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0
+ 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G
= 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234
, .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
= 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0
+ 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET
= 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294
, .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT
= 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0
+ 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, .
DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24
= 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0
+ 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, .
DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14
= 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0
+ 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, .
DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34
= 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3
, .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA
= 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6
, .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G
= 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0
+ 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G
= 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, .
DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G
= 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 +
0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, .
DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0,
.DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4,
.DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8,
.DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc,
.DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0
+ 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0
, .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R
= 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, .
DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, .
DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G
= 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 +
0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3
= 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0
+ 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, .
DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11
= 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0
+ 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3,
.DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19
= 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0
+ 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7,
.DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27
= 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0
+ 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb,
.DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,\
603}
604
605static const struct dcn30_dwbc_registers dwbc30_regs[] = {
606 dwbc_regs_dcn3(0)[0] = { .DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL
= 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, .
FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0
+ 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE
= 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f
, .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0
+ 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G
= 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234
, .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
= 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0
+ 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET
= 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294
, .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT
= 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0
+ 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, .
DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24
= 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0
+ 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, .
DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14
= 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0
+ 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, .
DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34
= 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3
, .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA
= 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6
, .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G
= 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0
+ 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G
= 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0
+ 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae
, .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B
= 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0
+ 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, .
DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R
= 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0
+ 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G
= 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 +
0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, .
DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0,
.DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4,
.DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8,
.DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc,
.DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B
= 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0
+ 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0
, .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R
= 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, .
DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, .
DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G
= 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 +
0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3
= 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0
+ 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, .
DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11
= 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0
+ 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3,
.DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19
= 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0
+ 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7,
.DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27
= 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0
+ 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb,
.DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,},
607};
608
609static const struct dcn30_dwbc_shift dwbc30_shift = {
610 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DWB_ENABLE = 0x0, .DISPCLK_R_DWB_GATE_DIS = 0x4, .DISPCLK_G_DWB_GATE_DIS
= 0x8, .DWB_TEST_CLK_SEL = 0xc, .DWB_OGAM_LUT_MEM_PWR_FORCE =
0x10, .DWB_OGAM_LUT_MEM_PWR_DIS = 0x12, .DWB_OGAM_LUT_MEM_PWR_STATE
= 0x14, .FC_FRAME_CAPTURE_EN = 0x0, .FC_FRAME_CAPTURE_RATE =
0x4, .FC_WINDOW_CROP_EN = 0x8, .FC_EYE_SELECTION = 0xc, .FC_STEREO_EYE_POLARITY
= 0x10, .FC_NEW_CONTENT = 0x14, .FC_FRAME_CAPTURE_EN_CURRENT
= 0x1f, .FC_FIRST_PIXEL_DELAY_COUNT = 0x0, .FC_WINDOW_START_X
= 0x0, .FC_WINDOW_START_Y = 0x10, .FC_WINDOW_WIDTH = 0x0, .FC_WINDOW_HEIGHT
= 0x10, .FC_SOURCE_WIDTH = 0x0, .FC_SOURCE_HEIGHT = 0x10, .DWB_UPDATE_LOCK
= 0x0, .DWB_UPDATE_PENDING = 0x4, .DWB_CRC_EN = 0x0, .DWB_CRC_CONT_EN
= 0x4, .DWB_CRC_SRC_SEL = 0x8, .DWB_CRC_RED_MASK = 0x0, .DWB_CRC_GREEN_MASK
= 0x10, .DWB_CRC_BLUE_MASK = 0x0, .DWB_CRC_A_MASK = 0x10, .DWB_CRC_SIG_RED
= 0x0, .DWB_CRC_SIG_GREEN = 0x10, .DWB_CRC_SIG_BLUE = 0x0, .
DWB_CRC_SIG_A = 0x10, .OUT_FORMAT = 0x0, .OUT_DENORM = 0x4, .
OUT_MAX = 0x8, .OUT_MIN = 0x14, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
= 0x0, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0, .DWB_HOST_READ_RATE_CONTROL
= 0x0, .DWB_SOFT_RESET = 0x0, .DWB_HDR_MULT_COEF = 0x0, .DWB_GAMUT_REMAP_MODE
= 0x0, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x18, .DWB_GAMUT_REMAP_COEF_FORMAT
= 0x0, .DWB_GAMUT_REMAPA_C11 = 0x0, .DWB_GAMUT_REMAPA_C12 = 0x10
, .DWB_GAMUT_REMAPA_C13 = 0x0, .DWB_GAMUT_REMAPA_C14 = 0x10, .
DWB_GAMUT_REMAPA_C21 = 0x0, .DWB_GAMUT_REMAPA_C22 = 0x10, .DWB_GAMUT_REMAPA_C23
= 0x0, .DWB_GAMUT_REMAPA_C24 = 0x10, .DWB_GAMUT_REMAPA_C31 =
0x0, .DWB_GAMUT_REMAPA_C32 = 0x10, .DWB_GAMUT_REMAPA_C33 = 0x0
, .DWB_GAMUT_REMAPA_C34 = 0x10, .DWB_GAMUT_REMAPB_C11 = 0x0, .
DWB_GAMUT_REMAPB_C12 = 0x10, .DWB_GAMUT_REMAPB_C13 = 0x0, .DWB_GAMUT_REMAPB_C14
= 0x10, .DWB_GAMUT_REMAPB_C21 = 0x0, .DWB_GAMUT_REMAPB_C22 =
0x10, .DWB_GAMUT_REMAPB_C23 = 0x0, .DWB_GAMUT_REMAPB_C24 = 0x10
, .DWB_GAMUT_REMAPB_C31 = 0x0, .DWB_GAMUT_REMAPB_C32 = 0x10, .
DWB_GAMUT_REMAPB_C33 = 0x0, .DWB_GAMUT_REMAPB_C34 = 0x10, .DWB_OGAM_MODE
= 0x0, .DWB_OGAM_SELECT = 0x4, .DWB_OGAM_PWL_DISABLE = 0x8, .
DWB_OGAM_MODE_CURRENT = 0x18, .DWB_OGAM_SELECT_CURRENT = 0x1c
, .DWB_OGAM_LUT_INDEX = 0x0, .DWB_OGAM_LUT_DATA = 0x0, .DWB_OGAM_LUT_WRITE_COLOR_MASK
= 0x0, .DWB_OGAM_LUT_READ_COLOR_SEL = 0x4, .DWB_OGAM_LUT_READ_DBG
= 0x8, .DWB_OGAM_LUT_HOST_SEL = 0xc, .DWB_OGAM_LUT_CONFIG_MODE
= 0x10, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R
= 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_B
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_R
= 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMA_OFFSET_B
= 0x0, .DWB_OGAM_RAMA_OFFSET_G = 0x0, .DWB_OGAM_RAMA_OFFSET_R
= 0x0, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B
= 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G
= 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_B
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G
= 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_R
= 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMB_OFFSET_B
= 0x0, .DWB_OGAM_RAMB_OFFSET_G = 0x0, .DWB_OGAM_RAMB_OFFSET_R
= 0x0, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS
= 0xc, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x1c
611};
612
613static const struct dcn30_dwbc_mask dwbc30_mask = {
614 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK).DWB_ENABLE = 0x00000001L, .DISPCLK_R_DWB_GATE_DIS = 0x00000010L
, .DISPCLK_G_DWB_GATE_DIS = 0x00000100L, .DWB_TEST_CLK_SEL = 0x00003000L
, .DWB_OGAM_LUT_MEM_PWR_FORCE = 0x00030000L, .DWB_OGAM_LUT_MEM_PWR_DIS
= 0x00040000L, .DWB_OGAM_LUT_MEM_PWR_STATE = 0x00300000L, .FC_FRAME_CAPTURE_EN
= 0x00000001L, .FC_FRAME_CAPTURE_RATE = 0x00000030L, .FC_WINDOW_CROP_EN
= 0x00000100L, .FC_EYE_SELECTION = 0x00003000L, .FC_STEREO_EYE_POLARITY
= 0x00010000L, .FC_NEW_CONTENT = 0x00100000L, .FC_FRAME_CAPTURE_EN_CURRENT
= 0x80000000L, .FC_FIRST_PIXEL_DELAY_COUNT = 0x00000FFFL, .FC_WINDOW_START_X
= 0x00001FFFL, .FC_WINDOW_START_Y = 0x1FFF0000L, .FC_WINDOW_WIDTH
= 0x00000FFFL, .FC_WINDOW_HEIGHT = 0x0FFF0000L, .FC_SOURCE_WIDTH
= 0x00007FFFL, .FC_SOURCE_HEIGHT = 0x7FFF0000L, .DWB_UPDATE_LOCK
= 0x00000001L, .DWB_UPDATE_PENDING = 0x00000010L, .DWB_CRC_EN
= 0x00000001L, .DWB_CRC_CONT_EN = 0x00000010L, .DWB_CRC_SRC_SEL
= 0x00000300L, .DWB_CRC_RED_MASK = 0x0000FFFFL, .DWB_CRC_GREEN_MASK
= 0xFFFF0000L, .DWB_CRC_BLUE_MASK = 0x0000FFFFL, .DWB_CRC_A_MASK
= 0xFFFF0000L, .DWB_CRC_SIG_RED = 0x0000FFFFL, .DWB_CRC_SIG_GREEN
= 0xFFFF0000L, .DWB_CRC_SIG_BLUE = 0x0000FFFFL, .DWB_CRC_SIG_A
= 0xFFFF0000L, .OUT_FORMAT = 0x00000003L, .OUT_DENORM = 0x00000030L
, .OUT_MAX = 0x0003FF00L, .OUT_MIN = 0x3FF00000L, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
= 0x00000001L, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0000FFFFL,
.DWB_HOST_READ_RATE_CONTROL = 0x000000FFL, .DWB_SOFT_RESET =
0x00000001L, .DWB_HDR_MULT_COEF = 0x0007FFFFL, .DWB_GAMUT_REMAP_MODE
= 0x00000003L, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x03000000L, .
DWB_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, .DWB_GAMUT_REMAPA_C11
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C13
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C21
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C23
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C31
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C33
= 0x0000FFFFL, .DWB_GAMUT_REMAPA_C34 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C11
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C13
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C21
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C23
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C31
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C33
= 0x0000FFFFL, .DWB_GAMUT_REMAPB_C34 = 0xFFFF0000L, .DWB_OGAM_MODE
= 0x00000003L, .DWB_OGAM_SELECT = 0x00000010L, .DWB_OGAM_PWL_DISABLE
= 0x00000100L, .DWB_OGAM_MODE_CURRENT = 0x03000000L, .DWB_OGAM_SELECT_CURRENT
= 0x10000000L, .DWB_OGAM_LUT_INDEX = 0x000001FFL, .DWB_OGAM_LUT_DATA
= 0x0003FFFFL, .DWB_OGAM_LUT_WRITE_COLOR_MASK = 0x00000007L,
.DWB_OGAM_LUT_READ_COLOR_SEL = 0x00000030L, .DWB_OGAM_LUT_READ_DBG
= 0x00000100L, .DWB_OGAM_LUT_HOST_SEL = 0x00001000L, .DWB_OGAM_LUT_CONFIG_MODE
= 0x00010000L, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_G
= 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L
, .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R
= 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G
= 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R
= 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B
= 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0003FFFFL
, .DWB_OGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R
= 0xFFFF0000L, .DWB_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_G
= 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B
= 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL
, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_R
= 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L
, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B
= 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0003FFFFL
, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R
= 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0003FFFFL
, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_B
= 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0xFFFF0000L
, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_G
= 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G = 0xFFFF0000L
, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_R
= 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0xFFFF0000L
, .DWB_OGAM_RAMB_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_G
= 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L
, .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS
= 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L
, .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET
= 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L
, .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET
= 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L
615};
616
617#define mcif_wb_regs_dcn3(id)[id] = { .MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS
= 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275
, .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2
= 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278
, .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS
= 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 +
0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2
= 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0
+ 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y
= 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284
, .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C
= 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a
, .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y
= 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290
, .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
= 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0
+ 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL
= 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0
+ 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE
= 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0
+ 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, .
MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH
= 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0
+ 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, .
MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH
= 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0
+ 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, .
MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION
= 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0
+ 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x033f, .MMHUBBUB_WARMUP_ADDR_REGION
= 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0
+ 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae
, .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
= 0x000034C0 + 0x02a7,}\
618[id] = {\
619 MCIF_WB_COMMON_REG_LIST_DCN30(id).MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS
= 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275
, .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2
= 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278
, .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS
= 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 +
0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2
= 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0
+ 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y
= 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284
, .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C
= 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a
, .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y
= 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290
, .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
= 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0
+ 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL
= 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0
+ 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE
= 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0
+ 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, .
MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH
= 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0
+ 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, .
MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH
= 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0
+ 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, .
MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION
= 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0
+ 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x033f, .MMHUBBUB_WARMUP_ADDR_REGION
= 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0
+ 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae
, .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
= 0x000034C0 + 0x02a7,\
620}
621
622static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
623 mcif_wb_regs_dcn3(0)[0] = { .MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS
= 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275
, .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2
= 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278
, .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS
= 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 +
0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2
= 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0
+ 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y
= 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284
, .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C
= 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a
, .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y
= 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290
, .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
= 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0
+ 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL
= 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0
+ 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE
= 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0
+ 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, .
MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH
= 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0
+ 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, .
MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH
= 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0
+ 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, .
MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION
= 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0
+ 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x033f, .MMHUBBUB_WARMUP_ADDR_REGION
= 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0
+ 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae
, .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
= 0x000034C0 + 0x02a7,}
624};
625
626static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
627 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT).MCIF_WB_BUFMGR_ENABLE = 0x0, .MCIF_WB_BUFMGR_SW_INT_EN = 0x4
, .MCIF_WB_BUFMGR_SW_INT_ACK = 0x5, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN
= 0x6, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x7, .MCIF_WB_BUFMGR_SW_LOCK
= 0x8, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x18, .MCIF_WB_BUFMGR_VCE_INT_STATUS
= 0x0, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x1, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS
= 0x2, .MCIF_WB_BUFMGR_CUR_BUF = 0x4, .MCIF_WB_BUFMGR_BUFTAG
= 0x8, .MCIF_WB_BUFMGR_CUR_LINE_L = 0xc, .MCIF_WB_BUFMGR_NEXT_BUF
= 0x1c, .MCIF_WB_BUF_LUMA_PITCH = 0x8, .MCIF_WB_BUF_CHROMA_PITCH
= 0x18, .MCIF_WB_BUF_1_ACTIVE = 0x0, .MCIF_WB_BUF_1_SW_LOCKED
= 0x1, .MCIF_WB_BUF_1_VCE_LOCKED = 0x2, .MCIF_WB_BUF_1_OVERFLOW
= 0x3, .MCIF_WB_BUF_1_DISABLE = 0x4, .MCIF_WB_BUF_1_MODE = 0x5
, .MCIF_WB_BUF_1_BUFTAG = 0x8, .MCIF_WB_BUF_1_NXT_BUF = 0xc, .
MCIF_WB_BUF_1_CUR_LINE_L = 0x10, .MCIF_WB_BUF_1_NEW_CONTENT =
0xd, .MCIF_WB_BUF_1_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL
= 0xf, .MCIF_WB_BUF_1_TMZ = 0x10, .MCIF_WB_BUF_1_Y_OVERRUN =
0x11, .MCIF_WB_BUF_1_C_OVERRUN = 0x12, .MCIF_WB_BUF_2_ACTIVE
= 0x0, .MCIF_WB_BUF_2_SW_LOCKED = 0x1, .MCIF_WB_BUF_2_VCE_LOCKED
= 0x2, .MCIF_WB_BUF_2_OVERFLOW = 0x3, .MCIF_WB_BUF_2_DISABLE
= 0x4, .MCIF_WB_BUF_2_MODE = 0x5, .MCIF_WB_BUF_2_BUFTAG = 0x8
, .MCIF_WB_BUF_2_NXT_BUF = 0xc, .MCIF_WB_BUF_2_CUR_LINE_L = 0x10
, .MCIF_WB_BUF_2_NEW_CONTENT = 0xd, .MCIF_WB_BUF_2_COLOR_DEPTH
= 0xe, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_2_TMZ
= 0x10, .MCIF_WB_BUF_2_Y_OVERRUN = 0x11, .MCIF_WB_BUF_2_C_OVERRUN
= 0x12, .MCIF_WB_BUF_3_ACTIVE = 0x0, .MCIF_WB_BUF_3_SW_LOCKED
= 0x1, .MCIF_WB_BUF_3_VCE_LOCKED = 0x2, .MCIF_WB_BUF_3_OVERFLOW
= 0x3, .MCIF_WB_BUF_3_DISABLE = 0x4, .MCIF_WB_BUF_3_MODE = 0x5
, .MCIF_WB_BUF_3_BUFTAG = 0x8, .MCIF_WB_BUF_3_NXT_BUF = 0xc, .
MCIF_WB_BUF_3_CUR_LINE_L = 0x10, .MCIF_WB_BUF_3_NEW_CONTENT =
0xd, .MCIF_WB_BUF_3_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL
= 0xf, .MCIF_WB_BUF_3_TMZ = 0x10, .MCIF_WB_BUF_3_Y_OVERRUN =
0x11, .MCIF_WB_BUF_3_C_OVERRUN = 0x12, .MCIF_WB_BUF_4_ACTIVE
= 0x0, .MCIF_WB_BUF_4_SW_LOCKED = 0x1, .MCIF_WB_BUF_4_VCE_LOCKED
= 0x2, .MCIF_WB_BUF_4_OVERFLOW = 0x3, .MCIF_WB_BUF_4_DISABLE
= 0x4, .MCIF_WB_BUF_4_MODE = 0x5, .MCIF_WB_BUF_4_BUFTAG = 0x8
, .MCIF_WB_BUF_4_NXT_BUF = 0xc, .MCIF_WB_BUF_4_CUR_LINE_L = 0x10
, .MCIF_WB_BUF_4_NEW_CONTENT = 0xd, .MCIF_WB_BUF_4_COLOR_DEPTH
= 0xe, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_4_TMZ
= 0x10, .MCIF_WB_BUF_4_Y_OVERRUN = 0x11, .MCIF_WB_BUF_4_C_OVERRUN
= 0x12, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x0, .MCIF_WB_TIME_PER_PIXEL
= 0x14, .WM_CHANGE_ACK_FORCE_ON = 0x0, .MCIF_WB_BUF_1_ADDR_Y
= 0x0, .MCIF_WB_BUF_1_ADDR_C = 0x0, .MCIF_WB_BUF_2_ADDR_Y = 0x0
, .MCIF_WB_BUF_2_ADDR_C = 0x0, .MCIF_WB_BUF_3_ADDR_Y = 0x0, .
MCIF_WB_BUF_3_ADDR_C = 0x0, .MCIF_WB_BUF_4_ADDR_Y = 0x0, .MCIF_WB_BUF_4_ADDR_C
= 0x0, .MCIF_WB_BUFMGR_VCE_LOCK_IGNORE = 0x0, .MCIF_WB_BUFMGR_VCE_INT_EN
= 0x4, .MCIF_WB_BUFMGR_VCE_INT_ACK = 0x5, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN
= 0x6, .MCIF_WB_BUFMGR_VCE_LOCK = 0x8, .MCIF_WB_BUFMGR_SLICE_SIZE
= 0x10, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x0, .NB_PSTATE_CHANGE_WATERMARK_MASK
= 0x18, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x0, .NB_PSTATE_CHANGE_FORCE_ON
= 0x1, .NB_PSTATE_ALLOW_FOR_URGENT = 0x2, .MCIF_WB_CLI_WATERMARK
= 0x0, .MCIF_WB_CLI_WATERMARK_MASK = 0x18, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE
= 0x0, .DIS_REFRESH_UNDER_NBPREQ = 0x0, .PERFRAME_SELF_REFRESH
= 0x1, .MAX_SCALED_TIME_TO_URGENT = 0x0, .MCIF_WB_BUF_LUMA_SIZE
= 0x0, .MCIF_WB_BUF_CHROMA_SIZE = 0x0, .MCIF_WB_BUF_1_ADDR_Y_HIGH
= 0x0, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_Y_HIGH
= 0x0, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_Y_HIGH
= 0x0, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_Y_HIGH
= 0x0, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_WIDTH
= 0x0, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_2_RESOLUTION_WIDTH
= 0x0, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_3_RESOLUTION_WIDTH
= 0x0, .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_4_RESOLUTION_WIDTH
= 0x0, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x10, .MMHUBBUB_WARMUP_ADDR_REGION
= 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_LOW
= 0x0, .MMHUBBUB_WARMUP_EN = 0x0, .MMHUBBUB_WARMUP_SW_INT_EN
= 0x4, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x5, .MMHUBBUB_WARMUP_SW_INT_ACK
= 0x6, .MMHUBBUB_WARMUP_INC_ADDR = 0x8, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
= 0x0
628};
629
630static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
631 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK).MCIF_WB_BUFMGR_ENABLE = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_EN
= 0x00000010L, .MCIF_WB_BUFMGR_SW_INT_ACK = 0x00000020L, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN
= 0x00000040L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x00000080L
, .MCIF_WB_BUFMGR_SW_LOCK = 0x00000F00L, .MCIF_WB_BUF_ADDR_FENCE_EN
= 0x01000000L, .MCIF_WB_BUFMGR_VCE_INT_STATUS = 0x00000001L,
.MCIF_WB_BUFMGR_SW_INT_STATUS = 0x00000002L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS
= 0x00000004L, .MCIF_WB_BUFMGR_CUR_BUF = 0x00000070L, .MCIF_WB_BUFMGR_BUFTAG
= 0x00000F00L, .MCIF_WB_BUFMGR_CUR_LINE_L = 0x01FFF000L, .MCIF_WB_BUFMGR_NEXT_BUF
= 0x70000000L, .MCIF_WB_BUF_LUMA_PITCH = 0x0000FF00L, .MCIF_WB_BUF_CHROMA_PITCH
= 0xFF000000L, .MCIF_WB_BUF_1_ACTIVE = 0x00000001L, .MCIF_WB_BUF_1_SW_LOCKED
= 0x00000002L, .MCIF_WB_BUF_1_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_1_OVERFLOW
= 0x00000008L, .MCIF_WB_BUF_1_DISABLE = 0x00000010L, .MCIF_WB_BUF_1_MODE
= 0x000000E0L, .MCIF_WB_BUF_1_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_1_NXT_BUF
= 0x00007000L, .MCIF_WB_BUF_1_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_1_NEW_CONTENT
= 0x00002000L, .MCIF_WB_BUF_1_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL
= 0x00008000L, .MCIF_WB_BUF_1_TMZ = 0x00010000L, .MCIF_WB_BUF_1_Y_OVERRUN
= 0x00020000L, .MCIF_WB_BUF_1_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_2_ACTIVE
= 0x00000001L, .MCIF_WB_BUF_2_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_2_VCE_LOCKED
= 0x00000004L, .MCIF_WB_BUF_2_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_2_DISABLE
= 0x00000010L, .MCIF_WB_BUF_2_MODE = 0x000000E0L, .MCIF_WB_BUF_2_BUFTAG
= 0x00000F00L, .MCIF_WB_BUF_2_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_2_CUR_LINE_L
= 0x1FFF0000L, .MCIF_WB_BUF_2_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_2_COLOR_DEPTH
= 0x00004000L, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0x00008000L,
.MCIF_WB_BUF_2_TMZ = 0x00010000L, .MCIF_WB_BUF_2_Y_OVERRUN =
0x00020000L, .MCIF_WB_BUF_2_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_3_ACTIVE
= 0x00000001L, .MCIF_WB_BUF_3_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_3_VCE_LOCKED
= 0x00000004L, .MCIF_WB_BUF_3_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_3_DISABLE
= 0x00000010L, .MCIF_WB_BUF_3_MODE = 0x000000E0L, .MCIF_WB_BUF_3_BUFTAG
= 0x00000F00L, .MCIF_WB_BUF_3_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_3_CUR_LINE_L
= 0x1FFF0000L, .MCIF_WB_BUF_3_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_3_COLOR_DEPTH
= 0x00004000L, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0x00008000L,
.MCIF_WB_BUF_3_TMZ = 0x00010000L, .MCIF_WB_BUF_3_Y_OVERRUN =
0x00020000L, .MCIF_WB_BUF_3_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_4_ACTIVE
= 0x00000001L, .MCIF_WB_BUF_4_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_4_VCE_LOCKED
= 0x00000004L, .MCIF_WB_BUF_4_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_4_DISABLE
= 0x00000010L, .MCIF_WB_BUF_4_MODE = 0x000000E0L, .MCIF_WB_BUF_4_BUFTAG
= 0x00000F00L, .MCIF_WB_BUF_4_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_4_CUR_LINE_L
= 0x1FFF0000L, .MCIF_WB_BUF_4_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_4_COLOR_DEPTH
= 0x00004000L, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0x00008000L,
.MCIF_WB_BUF_4_TMZ = 0x00010000L, .MCIF_WB_BUF_4_Y_OVERRUN =
0x00020000L, .MCIF_WB_BUF_4_C_OVERRUN = 0x00040000L, .MCIF_WB_CLIENT_ARBITRATION_SLICE
= 0x00000003L, .MCIF_WB_TIME_PER_PIXEL = 0xFFF00000L, .WM_CHANGE_ACK_FORCE_ON
= 0x00000001L, .MCIF_WB_BUF_1_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_C
= 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_C
= 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_C
= 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_C
= 0xFFFFFFFFL, .MCIF_WB_BUFMGR_VCE_LOCK_IGNORE = 0x00000001L
, .MCIF_WB_BUFMGR_VCE_INT_EN = 0x00000010L, .MCIF_WB_BUFMGR_VCE_INT_ACK
= 0x00000020L, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN = 0x00000040L
, .MCIF_WB_BUFMGR_VCE_LOCK = 0x00000F00L, .MCIF_WB_BUFMGR_SLICE_SIZE
= 0x1FFF0000L, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x001FFFFFL
, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x07000000L, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST
= 0x00000001L, .NB_PSTATE_CHANGE_FORCE_ON = 0x00000002L, .NB_PSTATE_ALLOW_FOR_URGENT
= 0x00000004L, .MCIF_WB_CLI_WATERMARK = 0x001FFFFFL, .MCIF_WB_CLI_WATERMARK_MASK
= 0x07000000L, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x00000001L
, .DIS_REFRESH_UNDER_NBPREQ = 0x00000001L, .PERFRAME_SELF_REFRESH
= 0x00000002L, .MAX_SCALED_TIME_TO_URGENT = 0x003FFFFFL, .MCIF_WB_BUF_LUMA_SIZE
= 0x000FFFFFL, .MCIF_WB_BUF_CHROMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_1_ADDR_Y_HIGH
= 0x000000FFL, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_Y_HIGH
= 0x000000FFL, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_Y_HIGH
= 0x000000FFL, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_Y_HIGH
= 0x000000FFL, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_RESOLUTION_WIDTH
= 0x00001FFFL, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x1FFF0000L
, .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT
= 0x1FFF0000L, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x00001FFFL
, .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_4_RESOLUTION_WIDTH
= 0x00001FFFL, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x1FFF0000L
, .MMHUBBUB_WARMUP_ADDR_REGION = 0x07FFFFFFL, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH
= 0x000007FFL, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0xFFFFFFFFL,
.MMHUBBUB_WARMUP_EN = 0x00000001L, .MMHUBBUB_WARMUP_SW_INT_EN
= 0x00000010L, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x00000020L,
.MMHUBBUB_WARMUP_SW_INT_ACK = 0x00000040L, .MMHUBBUB_WARMUP_INC_ADDR
= 0x03FFFF00L, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x0000FFFFL
632};
633
634#define dsc_regsDCN20(id)[id] = { .DSC_TOP_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX
+ mmDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX
+ mmDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG0_BASE_IDX
+ mmDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG1_BASE_IDX
+ mmDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_STATUS_BASE_IDX
+ mmDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX
+ mmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 =
DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG0
, .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG1_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG2_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG3_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG4_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG5_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG6_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG7_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG8_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG9_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG10_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG11_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG12_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG13_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG14_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG15_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG16_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG17_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG18_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG19_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG20_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG21_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG22_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX
+ mmDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX +
mmDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX
+ mmDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0
= DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG0
, .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG1_BASE_IDX
+ mmDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGmmDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX
+ mmDSCRMid_DSCRM_DSC_FORWARD_CONFIG}\
635[id] = {\
636 DSC_REG_LIST_DCN20(id).DSC_TOP_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX
+ mmDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX
+ mmDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG0_BASE_IDX
+ mmDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG1_BASE_IDX
+ mmDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_STATUS_BASE_IDX
+ mmDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX
+ mmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 =
DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG0
, .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG1_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG2_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG3_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG4_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG5_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG6_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG7_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG8_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG9_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG10_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG11_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG12_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG13_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG14_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG15_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG16_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG17_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG18_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG19_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG20_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG21_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG22_BASE_IDX
+ mmDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX
+ mmDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX
+ mmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX
+ mmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX +
mmDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX
+ mmDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
= DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
+ mmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0
= DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG0
, .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG1_BASE_IDX
+ mmDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGmmDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX
+ mmDSCRMid_DSCRM_DSC_FORWARD_CONFIG\
637}
638
639static const struct dcn20_dsc_registers dsc_regs[] = {
640 dsc_regsDCN20(0)[0] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3000, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x3001, .DSCC_CONFIG0 = 0x000034C0 + 0x300a, .
DSCC_CONFIG1 = 0x000034C0 + 0x300b, .DSCC_STATUS = 0x000034C0
+ 0x300c, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x300d
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x300e, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x300f, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3010
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3011, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x3012, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3013
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3014, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x3015, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3016
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3017, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x3018, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3019
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x301a, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x301b, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x301c
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x301d, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x301e, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x301f
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3020, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x3021, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3022
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3023, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x3024, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x3025, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3026,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3027, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x3028, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x3029, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x302a
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x302b, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x302c, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x302d
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302e
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302f
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3030
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3031
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x3032, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3033, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3034, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3035, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3005, .DSCCIF_CONFIG1
= 0x000034C0 + 0x3006, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a64},
641 dsc_regsDCN20(1)[1] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x305c, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x305d, .DSCC_CONFIG0 = 0x000034C0 + 0x3066, .
DSCC_CONFIG1 = 0x000034C0 + 0x3067, .DSCC_STATUS = 0x000034C0
+ 0x3068, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x3069
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x306a, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x306b, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x306c
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x306d, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x306e, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x306f
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3070, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x3071, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3072
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3073, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x3074, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3075
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x3076, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x3077, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x3078
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x3079, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x307a, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x307b
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x307c, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x307d, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x307e
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x307f, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x3080, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x3081, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3082,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3083, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x3084, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x3085, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3086
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3087, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x3088, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x3089
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308a
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308b
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308c
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308d
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x308e, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x308f, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3090, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3091, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3061, .DSCCIF_CONFIG1
= 0x000034C0 + 0x3062, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a65},
642 dsc_regsDCN20(2)[2] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x30b8, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x30b9, .DSCC_CONFIG0 = 0x000034C0 + 0x30c2, .
DSCC_CONFIG1 = 0x000034C0 + 0x30c3, .DSCC_STATUS = 0x000034C0
+ 0x30c4, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x30c5
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x30c6, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x30c7, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x30c8
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x30c9, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x30ca, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x30cb
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x30cc, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x30cd, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x30ce
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x30cf, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x30d0, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x30d1
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x30d2, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x30d3, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x30d4
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x30d5, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x30d6, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x30d7
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x30d8, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x30d9, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x30da
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x30db, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x30dc, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x30dd, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30de,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30df, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x30e0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x30e1, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30e2
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30e3, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x30e4, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x30e5
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e6
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e7
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e8
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e9
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x30ea, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x30eb, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x30ec, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x30ed, .DSCCIF_CONFIG0 = 0x000034C0 + 0x30bd, .DSCCIF_CONFIG1
= 0x000034C0 + 0x30be, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a66},
643 dsc_regsDCN20(3)[3] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3114, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x3115, .DSCC_CONFIG0 = 0x000034C0 + 0x311e, .
DSCC_CONFIG1 = 0x000034C0 + 0x311f, .DSCC_STATUS = 0x000034C0
+ 0x3120, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x3121
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x3122, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x3123, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3124
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3125, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x3126, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3127
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3128, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x3129, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x312a
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x312b, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x312c, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x312d
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x312e, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x312f, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x3130
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x3131, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x3132, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x3133
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3134, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x3135, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3136
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3137, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x3138, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x3139, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x313a,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x313b, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x313c, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x313d, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x313e
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x313f, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x3140, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x3141
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3142
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3143
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3144
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3145
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x3146, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3147, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3148, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3149, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3119, .DSCCIF_CONFIG1
= 0x000034C0 + 0x311a, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a67},
644 dsc_regsDCN20(4)[4] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3170, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x3171, .DSCC_CONFIG0 = 0x000034C0 + 0x317a, .
DSCC_CONFIG1 = 0x000034C0 + 0x317b, .DSCC_STATUS = 0x000034C0
+ 0x317c, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x317d
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x317e, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x317f, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3180
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3181, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x3182, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3183
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3184, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x3185, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3186
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3187, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x3188, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3189
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x318a, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x318b, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x318c
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x318d, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x318e, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x318f
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3190, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x3191, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3192
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3193, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x3194, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x3195, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3196,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3197, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x3198, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x3199, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x319a
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x319b, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x319c, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x319d
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x319e
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x319f
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a0
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a1
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x31a2, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x31a3, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x31a4, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x31a5, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3175, .DSCCIF_CONFIG1
= 0x000034C0 + 0x3176, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a68},
645 dsc_regsDCN20(5)[5] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x31cc, .DSC_DEBUG_CONTROL
= 0x000034C0 + 0x31cd, .DSCC_CONFIG0 = 0x000034C0 + 0x31d6, .
DSCC_CONFIG1 = 0x000034C0 + 0x31d7, .DSCC_STATUS = 0x000034C0
+ 0x31d8, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x31d9
, .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x31da, .DSCC_PPS_CONFIG1 =
0x000034C0 + 0x31db, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x31dc
, .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x31dd, .DSCC_PPS_CONFIG4 =
0x000034C0 + 0x31de, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x31df
, .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x31e0, .DSCC_PPS_CONFIG7 =
0x000034C0 + 0x31e1, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x31e2
, .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x31e3, .DSCC_PPS_CONFIG10
= 0x000034C0 + 0x31e4, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x31e5
, .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x31e6, .DSCC_PPS_CONFIG13
= 0x000034C0 + 0x31e7, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x31e8
, .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x31e9, .DSCC_PPS_CONFIG16
= 0x000034C0 + 0x31ea, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x31eb
, .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x31ec, .DSCC_PPS_CONFIG19
= 0x000034C0 + 0x31ed, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x31ee
, .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x31ef, .DSCC_PPS_CONFIG22
= 0x000034C0 + 0x31f0, .DSCC_MEM_POWER_CONTROL = 0x000034C0 +
0x31f1, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x31f2,
.DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x31f3, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x000034C0 + 0x31f4, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0
+ 0x31f5, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x31f6
, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x31f7, .DSCC_MAX_ABS_ERROR0
= 0x000034C0 + 0x31f8, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x31f9
, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fa
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fb
, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fc
, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fd
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 +
0x31fe, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x31ff, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3200, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0
+ 0x3201, .DSCCIF_CONFIG0 = 0x000034C0 + 0x31d1, .DSCCIF_CONFIG1
= 0x000034C0 + 0x31d2, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0
+ 0x1a69}
646};
647
648static const struct dcn20_dsc_shift dsc_shift = {
649 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT).DSC_CLOCK_EN = 0x0, .DSC_DISPCLK_R_GATE_DIS = 0x4, .DSC_DSCCLK_R_GATE_DIS
= 0x8, .DSC_DBG_EN = 0x0, .ICH_RESET_AT_END_OF_LINE = 0x0, .
NUMBER_OF_SLICES_PER_LINE = 0x4, .ALTERNATE_ICH_ENCODING_EN =
0x8, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0x10, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE
= 0x0, .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x0, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED
= 0x0, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x1, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED
= 0x2, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x3, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED
= 0x4, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x5, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED
= 0x6, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x7, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED
= 0x8, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x9
, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0xa, .
DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0xb, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN
= 0x10, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x11, .
DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x12, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN
= 0x13, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x14,
.DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x15, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN
= 0x16, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x17,
.DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x18
, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN =
0x19, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN
= 0x1a, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN
= 0x1b, .DSC_VERSION_MINOR = 0x0, .DSC_VERSION_MAJOR = 0x4, .
PPS_IDENTIFIER = 0x8, .LINEBUF_DEPTH = 0x18, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT
= 0x1c, .BITS_PER_PIXEL = 0x0, .VBR_ENABLE = 0xa, .SIMPLE_422
= 0xb, .CONVERT_RGB = 0xc, .BLOCK_PRED_ENABLE = 0xd, .NATIVE_422
= 0xe, .NATIVE_420 = 0xf, .CHUNK_SIZE = 0x10, .PIC_WIDTH = 0x0
, .PIC_HEIGHT = 0x10, .SLICE_WIDTH = 0x0, .SLICE_HEIGHT = 0x10
, .INITIAL_XMIT_DELAY = 0x0, .INITIAL_DEC_DELAY = 0x10, .INITIAL_SCALE_VALUE
= 0x0, .SCALE_INCREMENT_INTERVAL = 0x10, .SCALE_DECREMENT_INTERVAL
= 0x0, .FIRST_LINE_BPG_OFFSET = 0x10, .SECOND_LINE_BPG_OFFSET
= 0x18, .NFL_BPG_OFFSET = 0x0, .SLICE_BPG_OFFSET = 0x10, .NSL_BPG_OFFSET
= 0x0, .SECOND_LINE_OFFSET_ADJ = 0x10, .INITIAL_OFFSET = 0x0
, .FINAL_OFFSET = 0x10, .FLATNESS_MIN_QP = 0x0, .FLATNESS_MAX_QP
= 0x8, .RC_MODEL_SIZE = 0x10, .RC_EDGE_FACTOR = 0x0, .RC_QUANT_INCR_LIMIT0
= 0x8, .RC_QUANT_INCR_LIMIT1 = 0x10, .RC_TGT_OFFSET_LO = 0x18
, .RC_TGT_OFFSET_HI = 0x1c, .RC_BUF_THRESH0 = 0x0, .RC_BUF_THRESH1
= 0x8, .RC_BUF_THRESH2 = 0x10, .RC_BUF_THRESH3 = 0x18, .RC_BUF_THRESH4
= 0x0, .RC_BUF_THRESH5 = 0x8, .RC_BUF_THRESH6 = 0x10, .RC_BUF_THRESH7
= 0x18, .RC_BUF_THRESH8 = 0x0, .RC_BUF_THRESH9 = 0x8, .RC_BUF_THRESH10
= 0x10, .RC_BUF_THRESH11 = 0x18, .RC_BUF_THRESH12 = 0x0, .RC_BUF_THRESH13
= 0x8, .RANGE_MIN_QP0 = 0x10, .RANGE_MAX_QP0 = 0x15, .RANGE_BPG_OFFSET0
= 0x1a, .RANGE_MIN_QP1 = 0x0, .RANGE_MAX_QP1 = 0x5, .RANGE_BPG_OFFSET1
= 0xa, .RANGE_MIN_QP2 = 0x10, .RANGE_MAX_QP2 = 0x15, .RANGE_BPG_OFFSET2
= 0x1a, .RANGE_MIN_QP3 = 0x0, .RANGE_MAX_QP3 = 0x5, .RANGE_BPG_OFFSET3
= 0xa, .RANGE_MIN_QP4 = 0x10, .RANGE_MAX_QP4 = 0x15, .RANGE_BPG_OFFSET4
= 0x1a, .RANGE_MIN_QP5 = 0x0, .RANGE_MAX_QP5 = 0x5, .RANGE_BPG_OFFSET5
= 0xa, .RANGE_MIN_QP6 = 0x10, .RANGE_MAX_QP6 = 0x15, .RANGE_BPG_OFFSET6
= 0x1a, .RANGE_MIN_QP7 = 0x0, .RANGE_MAX_QP7 = 0x5, .RANGE_BPG_OFFSET7
= 0xa, .RANGE_MIN_QP8 = 0x10, .RANGE_MAX_QP8 = 0x15, .RANGE_BPG_OFFSET8
= 0x1a, .RANGE_MIN_QP9 = 0x0, .RANGE_MAX_QP9 = 0x5, .RANGE_BPG_OFFSET9
= 0xa, .RANGE_MIN_QP10 = 0x10, .RANGE_MAX_QP10 = 0x15, .RANGE_BPG_OFFSET10
= 0x1a, .RANGE_MIN_QP11 = 0x0, .RANGE_MAX_QP11 = 0x5, .RANGE_BPG_OFFSET11
= 0xa, .RANGE_MIN_QP12 = 0x10, .RANGE_MAX_QP12 = 0x15, .RANGE_BPG_OFFSET12
= 0x1a, .RANGE_MIN_QP13 = 0x0, .RANGE_MAX_QP13 = 0x5, .RANGE_BPG_OFFSET13
= 0xa, .RANGE_MIN_QP14 = 0x10, .RANGE_MAX_QP14 = 0x15, .RANGE_BPG_OFFSET14
= 0x1a, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x0, .DSCC_MEM_PWR_FORCE
= 0x4, .DSCC_MEM_PWR_DIS = 0x8, .DSCC_MEM_PWR_STATE = 0x10, .
DSCC_NATIVE_422_MEM_PWR_FORCE = 0x14, .DSCC_NATIVE_422_MEM_PWR_DIS
= 0x18, .DSCC_NATIVE_422_MEM_PWR_STATE = 0x1c, .DSCC_R_Y_SQUARED_ERROR_LOWER
= 0x0, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x0, .DSCC_G_CB_SQUARED_ERROR_LOWER
= 0x0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x0, .DSCC_B_CR_SQUARED_ERROR_LOWER
= 0x0, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x0, .DSCC_R_Y_MAX_ABS_ERROR
= 0x0, .DSCC_G_CB_MAX_ABS_ERROR = 0x10, .DSCC_B_CR_MAX_ABS_ERROR
= 0x0, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
= 0x0, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
= 0x0, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, .
DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
= 0x0, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, .
INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x0, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN
= 0x4, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x8, .INPUT_PIXEL_FORMAT
= 0xc, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x10, .DOUBLE_BUFFER_REG_UPDATE_PENDING
= 0x18, .PIC_WIDTH = 0x0, .PIC_HEIGHT = 0x10, .DSCRM_DSC_FORWARD_EN
= 0x0, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x4
650};
651
652static const struct dcn20_dsc_mask dsc_mask = {
653 DSC_REG_LIST_SH_MASK_DCN20(_MASK).DSC_CLOCK_EN = 0x00000001L, .DSC_DISPCLK_R_GATE_DIS = 0x00000010L
, .DSC_DSCCLK_R_GATE_DIS = 0x00000100L, .DSC_DBG_EN = 0x00000001L
, .ICH_RESET_AT_END_OF_LINE = 0x0000000FL, .NUMBER_OF_SLICES_PER_LINE
= 0x00000030L, .ALTERNATE_ICH_ENCODING_EN = 0x00000100L, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION
= 0xFFFF0000L, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0003FFFFL
, .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x00000001L, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED
= 0x00000001L, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x00000002L
, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x00000004L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED
= 0x00000008L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x00000010L
, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x00000020L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED
= 0x00000040L, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x00000080L
, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x00000100L
, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x00000200L
, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0x00000400L
, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0x00000800L
, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x00010000L, .
DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x00020000L, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN
= 0x00040000L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN =
0x00080000L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x00100000L
, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x00200000L,
.DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x00400000L, .
DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x00800000L, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN
= 0x01000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN
= 0x02000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN
= 0x04000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN
= 0x08000000L, .DSC_VERSION_MINOR = 0x0000000FL, .DSC_VERSION_MAJOR
= 0x000000F0L, .PPS_IDENTIFIER = 0x0000FF00L, .LINEBUF_DEPTH
= 0x0F000000L, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0xF0000000L
, .BITS_PER_PIXEL = 0x000003FFL, .VBR_ENABLE = 0x00000400L, .
SIMPLE_422 = 0x00000800L, .CONVERT_RGB = 0x00001000L, .BLOCK_PRED_ENABLE
= 0x00002000L, .NATIVE_422 = 0x00004000L, .NATIVE_420 = 0x00008000L
, .CHUNK_SIZE = 0xFFFF0000L, .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT
= 0xFFFF0000L, .SLICE_WIDTH = 0x0000FFFFL, .SLICE_HEIGHT = 0xFFFF0000L
, .INITIAL_XMIT_DELAY = 0x000003FFL, .INITIAL_DEC_DELAY = 0xFFFF0000L
, .INITIAL_SCALE_VALUE = 0x0000003FL, .SCALE_INCREMENT_INTERVAL
= 0xFFFF0000L, .SCALE_DECREMENT_INTERVAL = 0x00000FFFL, .FIRST_LINE_BPG_OFFSET
= 0x001F0000L, .SECOND_LINE_BPG_OFFSET = 0x1F000000L, .NFL_BPG_OFFSET
= 0x0000FFFFL, .SLICE_BPG_OFFSET = 0xFFFF0000L, .NSL_BPG_OFFSET
= 0x0000FFFFL, .SECOND_LINE_OFFSET_ADJ = 0xFFFF0000L, .INITIAL_OFFSET
= 0x0000FFFFL, .FINAL_OFFSET = 0xFFFF0000L, .FLATNESS_MIN_QP
= 0x0000001FL, .FLATNESS_MAX_QP = 0x00001F00L, .RC_MODEL_SIZE
= 0xFFFF0000L, .RC_EDGE_FACTOR = 0x0000000FL, .RC_QUANT_INCR_LIMIT0
= 0x00001F00L, .RC_QUANT_INCR_LIMIT1 = 0x001F0000L, .RC_TGT_OFFSET_LO
= 0x0F000000L, .RC_TGT_OFFSET_HI = 0xF0000000L, .RC_BUF_THRESH0
= 0x000000FFL, .RC_BUF_THRESH1 = 0x0000FF00L, .RC_BUF_THRESH2
= 0x00FF0000L, .RC_BUF_THRESH3 = 0xFF000000L, .RC_BUF_THRESH4
= 0x000000FFL, .RC_BUF_THRESH5 = 0x0000FF00L, .RC_BUF_THRESH6
= 0x00FF0000L, .RC_BUF_THRESH7 = 0xFF000000L, .RC_BUF_THRESH8
= 0x000000FFL, .RC_BUF_THRESH9 = 0x0000FF00L, .RC_BUF_THRESH10
= 0x00FF0000L, .RC_BUF_THRESH11 = 0xFF000000L, .RC_BUF_THRESH12
= 0x000000FFL, .RC_BUF_THRESH13 = 0x0000FF00L, .RANGE_MIN_QP0
= 0x001F0000L, .RANGE_MAX_QP0 = 0x03E00000L, .RANGE_BPG_OFFSET0
= 0xFC000000L, .RANGE_MIN_QP1 = 0x0000001FL, .RANGE_MAX_QP1 =
0x000003E0L, .RANGE_BPG_OFFSET1 = 0x0000FC00L, .RANGE_MIN_QP2
= 0x001F0000L, .RANGE_MAX_QP2 = 0x03E00000L, .RANGE_BPG_OFFSET2
= 0xFC000000L, .RANGE_MIN_QP3 = 0x0000001FL, .RANGE_MAX_QP3 =
0x000003E0L, .RANGE_BPG_OFFSET3 = 0x0000FC00L, .RANGE_MIN_QP4
= 0x001F0000L, .RANGE_MAX_QP4 = 0x03E00000L, .RANGE_BPG_OFFSET4
= 0xFC000000L, .RANGE_MIN_QP5 = 0x0000001FL, .RANGE_MAX_QP5 =
0x000003E0L, .RANGE_BPG_OFFSET5 = 0x0000FC00L, .RANGE_MIN_QP6
= 0x001F0000L, .RANGE_MAX_QP6 = 0x03E00000L, .RANGE_BPG_OFFSET6
= 0xFC000000L, .RANGE_MIN_QP7 = 0x0000001FL, .RANGE_MAX_QP7 =
0x000003E0L, .RANGE_BPG_OFFSET7 = 0x0000FC00L, .RANGE_MIN_QP8
= 0x001F0000L, .RANGE_MAX_QP8 = 0x03E00000L, .RANGE_BPG_OFFSET8
= 0xFC000000L, .RANGE_MIN_QP9 = 0x0000001FL, .RANGE_MAX_QP9 =
0x000003E0L, .RANGE_BPG_OFFSET9 = 0x0000FC00L, .RANGE_MIN_QP10
= 0x001F0000L, .RANGE_MAX_QP10 = 0x03E00000L, .RANGE_BPG_OFFSET10
= 0xFC000000L, .RANGE_MIN_QP11 = 0x0000001FL, .RANGE_MAX_QP11
= 0x000003E0L, .RANGE_BPG_OFFSET11 = 0x0000FC00L, .RANGE_MIN_QP12
= 0x001F0000L, .RANGE_MAX_QP12 = 0x03E00000L, .RANGE_BPG_OFFSET12
= 0xFC000000L, .RANGE_MIN_QP13 = 0x0000001FL, .RANGE_MAX_QP13
= 0x000003E0L, .RANGE_BPG_OFFSET13 = 0x0000FC00L, .RANGE_MIN_QP14
= 0x001F0000L, .RANGE_MAX_QP14 = 0x03E00000L, .RANGE_BPG_OFFSET14
= 0xFC000000L, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x00000003L
, .DSCC_MEM_PWR_FORCE = 0x00000030L, .DSCC_MEM_PWR_DIS = 0x00000100L
, .DSCC_MEM_PWR_STATE = 0x00030000L, .DSCC_NATIVE_422_MEM_PWR_FORCE
= 0x00300000L, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x01000000L, .
DSCC_NATIVE_422_MEM_PWR_STATE = 0x30000000L, .DSCC_R_Y_SQUARED_ERROR_LOWER
= 0xFFFFFFFFL, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .
DSCC_G_CB_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_G_CB_SQUARED_ERROR_UPPER
= 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0xFFFFFFFFL,
.DSCC_B_CR_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_R_Y_MAX_ABS_ERROR
= 0x0000FFFFL, .DSCC_G_CB_MAX_ABS_ERROR = 0xFFFF0000L, .DSCC_B_CR_MAX_ABS_ERROR
= 0x0000FFFFL, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
= 0x0003FFFFL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL
, .INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x00000001L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN
= 0x00000010L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x00000100L
, .INPUT_PIXEL_FORMAT = 0x00007000L, .DSCCIF_CONFIG0__BITS_PER_COMPONENT
= 0x000F0000L, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x01000000L
, .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .DSCRM_DSC_FORWARD_EN
= 0x00000001L, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x00000070L
654};
655
656static const struct dcn30_mpc_registers mpc_regs = {
657 MPC_REG_LIST_DCN3_0(0).MPCC_TOP_SEL[0] = 0x00009000 + 0x0000, .MPCC_BOT_SEL[0] = 0x00009000
+ 0x0001, .MPCC_CONTROL[0] = 0x00009000 + 0x0003, .MPCC_STATUS
[0] = 0x00009000 + 0x000d, .MPCC_OPP_ID[0] = 0x00009000 + 0x0002
, .MPCC_BG_G_Y[0] = 0x00009000 + 0x000a, .MPCC_BG_R_CR[0] = 0x00009000
+ 0x0009, .MPCC_BG_B_CB[0] = 0x00009000 + 0x000b, .MPCC_SM_CONTROL
[0] = 0x00009000 + 0x0004, .MPCC_UPDATE_LOCK_SEL[0] = 0x00009000
+ 0x0005, .MPCC_TOP_GAIN[0] = 0x00009000 + 0x0006, .MPCC_BOT_GAIN_INSIDE
[0] = 0x00009000 + 0x0007, .MPCC_BOT_GAIN_OUTSIDE[0] = 0x00009000
+ 0x0008, .MPCC_MEM_PWR_CTRL[0] = 0x00009000 + 0x000c, .MPCC_OGAM_LUT_INDEX
[0] = 0x00009000 + 0x0101, .MPCC_OGAM_LUT_DATA[0] = 0x00009000
+ 0x0102, .MPCC_GAMUT_REMAP_COEF_FORMAT[0] = 0x00009000 + 0x014a
, .MPCC_GAMUT_REMAP_MODE[0] = 0x00009000 + 0x014b, .MPC_GAMUT_REMAP_C11_C12_A
[0] = 0x00009000 + 0x014c, .MPC_GAMUT_REMAP_C33_C34_A[0] = 0x00009000
+ 0x0151, .MPC_GAMUT_REMAP_C11_C12_B[0] = 0x00009000 + 0x0152
, .MPC_GAMUT_REMAP_C33_C34_B[0] = 0x00009000 + 0x0157, .MPCC_OGAM_RAMA_START_CNTL_B
[0] = 0x00009000 + 0x0104, .MPCC_OGAM_RAMA_START_CNTL_G[0] = 0x00009000
+ 0x0105, .MPCC_OGAM_RAMA_START_CNTL_R[0] = 0x00009000 + 0x0106
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[0] = 0x00009000 + 0x0107
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[0] = 0x00009000 + 0x0108
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[0] = 0x00009000 + 0x0109
, .MPCC_OGAM_RAMA_END_CNTL1_B[0] = 0x00009000 + 0x010d, .MPCC_OGAM_RAMA_END_CNTL2_B
[0] = 0x00009000 + 0x010e, .MPCC_OGAM_RAMA_END_CNTL1_G[0] = 0x00009000
+ 0x010f, .MPCC_OGAM_RAMA_END_CNTL2_G[0] = 0x00009000 + 0x0110
, .MPCC_OGAM_RAMA_END_CNTL1_R[0] = 0x00009000 + 0x0111, .MPCC_OGAM_RAMA_END_CNTL2_R
[0] = 0x00009000 + 0x0112, .MPCC_OGAM_RAMA_REGION_0_1[0] = 0x00009000
+ 0x0116, .MPCC_OGAM_RAMA_REGION_32_33[0] = 0x00009000 + 0x0126
, .MPCC_OGAM_RAMA_OFFSET_B[0] = 0x00009000 + 0x0113, .MPCC_OGAM_RAMA_OFFSET_G
[0] = 0x00009000 + 0x0114, .MPCC_OGAM_RAMA_OFFSET_R[0] = 0x00009000
+ 0x0115, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[0] = 0x00009000 +
0x010a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[0] = 0x00009000 + 0x010b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[0] = 0x00009000 + 0x010c,
.MPCC_OGAM_RAMB_START_CNTL_B[0] = 0x00009000 + 0x0127, .MPCC_OGAM_RAMB_START_CNTL_G
[0] = 0x00009000 + 0x0128, .MPCC_OGAM_RAMB_START_CNTL_R[0] = 0x00009000
+ 0x0129, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[0] = 0x00009000
+ 0x012a, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[0] = 0x00009000
+ 0x012b, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[0] = 0x00009000
+ 0x012c, .MPCC_OGAM_RAMB_END_CNTL1_B[0] = 0x00009000 + 0x0130
, .MPCC_OGAM_RAMB_END_CNTL2_B[0] = 0x00009000 + 0x0131, .MPCC_OGAM_RAMB_END_CNTL1_G
[0] = 0x00009000 + 0x0132, .MPCC_OGAM_RAMB_END_CNTL2_G[0] = 0x00009000
+ 0x0133, .MPCC_OGAM_RAMB_END_CNTL1_R[0] = 0x00009000 + 0x0134
, .MPCC_OGAM_RAMB_END_CNTL2_R[0] = 0x00009000 + 0x0135, .MPCC_OGAM_RAMB_REGION_0_1
[0] = 0x00009000 + 0x0139, .MPCC_OGAM_RAMB_REGION_32_33[0] = 0x00009000
+ 0x0149, .MPCC_OGAM_RAMB_OFFSET_B[0] = 0x00009000 + 0x0136,
.MPCC_OGAM_RAMB_OFFSET_G[0] = 0x00009000 + 0x0137, .MPCC_OGAM_RAMB_OFFSET_R
[0] = 0x00009000 + 0x0138, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
0] = 0x00009000 + 0x012d, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[0
] = 0x00009000 + 0x012e, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[0]
= 0x00009000 + 0x012f, .MPCC_OGAM_CONTROL[0] = 0x00009000 + 0x0100
, .MPCC_OGAM_LUT_CONTROL[0] = 0x00009000 + 0x0103,
658 MPC_REG_LIST_DCN3_0(1).MPCC_TOP_SEL[1] = 0x00009000 + 0x0020, .MPCC_BOT_SEL[1] = 0x00009000
+ 0x0021, .MPCC_CONTROL[1] = 0x00009000 + 0x0023, .MPCC_STATUS
[1] = 0x00009000 + 0x002d, .MPCC_OPP_ID[1] = 0x00009000 + 0x0022
, .MPCC_BG_G_Y[1] = 0x00009000 + 0x002a, .MPCC_BG_R_CR[1] = 0x00009000
+ 0x0029, .MPCC_BG_B_CB[1] = 0x00009000 + 0x002b, .MPCC_SM_CONTROL
[1] = 0x00009000 + 0x0024, .MPCC_UPDATE_LOCK_SEL[1] = 0x00009000
+ 0x0025, .MPCC_TOP_GAIN[1] = 0x00009000 + 0x0026, .MPCC_BOT_GAIN_INSIDE
[1] = 0x00009000 + 0x0027, .MPCC_BOT_GAIN_OUTSIDE[1] = 0x00009000
+ 0x0028, .MPCC_MEM_PWR_CTRL[1] = 0x00009000 + 0x002c, .MPCC_OGAM_LUT_INDEX
[1] = 0x00009000 + 0x0181, .MPCC_OGAM_LUT_DATA[1] = 0x00009000
+ 0x0182, .MPCC_GAMUT_REMAP_COEF_FORMAT[1] = 0x00009000 + 0x01ca
, .MPCC_GAMUT_REMAP_MODE[1] = 0x00009000 + 0x01cb, .MPC_GAMUT_REMAP_C11_C12_A
[1] = 0x00009000 + 0x01cc, .MPC_GAMUT_REMAP_C33_C34_A[1] = 0x00009000
+ 0x01d1, .MPC_GAMUT_REMAP_C11_C12_B[1] = 0x00009000 + 0x01d2
, .MPC_GAMUT_REMAP_C33_C34_B[1] = 0x00009000 + 0x01d7, .MPCC_OGAM_RAMA_START_CNTL_B
[1] = 0x00009000 + 0x0184, .MPCC_OGAM_RAMA_START_CNTL_G[1] = 0x00009000
+ 0x0185, .MPCC_OGAM_RAMA_START_CNTL_R[1] = 0x00009000 + 0x0186
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[1] = 0x00009000 + 0x0187
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[1] = 0x00009000 + 0x0188
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[1] = 0x00009000 + 0x0189
, .MPCC_OGAM_RAMA_END_CNTL1_B[1] = 0x00009000 + 0x018d, .MPCC_OGAM_RAMA_END_CNTL2_B
[1] = 0x00009000 + 0x018e, .MPCC_OGAM_RAMA_END_CNTL1_G[1] = 0x00009000
+ 0x018f, .MPCC_OGAM_RAMA_END_CNTL2_G[1] = 0x00009000 + 0x0190
, .MPCC_OGAM_RAMA_END_CNTL1_R[1] = 0x00009000 + 0x0191, .MPCC_OGAM_RAMA_END_CNTL2_R
[1] = 0x00009000 + 0x0192, .MPCC_OGAM_RAMA_REGION_0_1[1] = 0x00009000
+ 0x0196, .MPCC_OGAM_RAMA_REGION_32_33[1] = 0x00009000 + 0x01a6
, .MPCC_OGAM_RAMA_OFFSET_B[1] = 0x00009000 + 0x0193, .MPCC_OGAM_RAMA_OFFSET_G
[1] = 0x00009000 + 0x0194, .MPCC_OGAM_RAMA_OFFSET_R[1] = 0x00009000
+ 0x0195, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[1] = 0x00009000 +
0x018a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[1] = 0x00009000 + 0x018b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[1] = 0x00009000 + 0x018c,
.MPCC_OGAM_RAMB_START_CNTL_B[1] = 0x00009000 + 0x01a7, .MPCC_OGAM_RAMB_START_CNTL_G
[1] = 0x00009000 + 0x01a8, .MPCC_OGAM_RAMB_START_CNTL_R[1] = 0x00009000
+ 0x01a9, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[1] = 0x00009000
+ 0x01aa, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[1] = 0x00009000
+ 0x01ab, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[1] = 0x00009000
+ 0x01ac, .MPCC_OGAM_RAMB_END_CNTL1_B[1] = 0x00009000 + 0x01b0
, .MPCC_OGAM_RAMB_END_CNTL2_B[1] = 0x00009000 + 0x01b1, .MPCC_OGAM_RAMB_END_CNTL1_G
[1] = 0x00009000 + 0x01b2, .MPCC_OGAM_RAMB_END_CNTL2_G[1] = 0x00009000
+ 0x01b3, .MPCC_OGAM_RAMB_END_CNTL1_R[1] = 0x00009000 + 0x01b4
, .MPCC_OGAM_RAMB_END_CNTL2_R[1] = 0x00009000 + 0x01b5, .MPCC_OGAM_RAMB_REGION_0_1
[1] = 0x00009000 + 0x01b9, .MPCC_OGAM_RAMB_REGION_32_33[1] = 0x00009000
+ 0x01c9, .MPCC_OGAM_RAMB_OFFSET_B[1] = 0x00009000 + 0x01b6,
.MPCC_OGAM_RAMB_OFFSET_G[1] = 0x00009000 + 0x01b7, .MPCC_OGAM_RAMB_OFFSET_R
[1] = 0x00009000 + 0x01b8, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
1] = 0x00009000 + 0x01ad, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[1
] = 0x00009000 + 0x01ae, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[1]
= 0x00009000 + 0x01af, .MPCC_OGAM_CONTROL[1] = 0x00009000 + 0x0180
, .MPCC_OGAM_LUT_CONTROL[1] = 0x00009000 + 0x0183,
659 MPC_REG_LIST_DCN3_0(2).MPCC_TOP_SEL[2] = 0x00009000 + 0x0040, .MPCC_BOT_SEL[2] = 0x00009000
+ 0x0041, .MPCC_CONTROL[2] = 0x00009000 + 0x0043, .MPCC_STATUS
[2] = 0x00009000 + 0x004d, .MPCC_OPP_ID[2] = 0x00009000 + 0x0042
, .MPCC_BG_G_Y[2] = 0x00009000 + 0x004a, .MPCC_BG_R_CR[2] = 0x00009000
+ 0x0049, .MPCC_BG_B_CB[2] = 0x00009000 + 0x004b, .MPCC_SM_CONTROL
[2] = 0x00009000 + 0x0044, .MPCC_UPDATE_LOCK_SEL[2] = 0x00009000
+ 0x0045, .MPCC_TOP_GAIN[2] = 0x00009000 + 0x0046, .MPCC_BOT_GAIN_INSIDE
[2] = 0x00009000 + 0x0047, .MPCC_BOT_GAIN_OUTSIDE[2] = 0x00009000
+ 0x0048, .MPCC_MEM_PWR_CTRL[2] = 0x00009000 + 0x004c, .MPCC_OGAM_LUT_INDEX
[2] = 0x00009000 + 0x0201, .MPCC_OGAM_LUT_DATA[2] = 0x00009000
+ 0x0202, .MPCC_GAMUT_REMAP_COEF_FORMAT[2] = 0x00009000 + 0x024a
, .MPCC_GAMUT_REMAP_MODE[2] = 0x00009000 + 0x024b, .MPC_GAMUT_REMAP_C11_C12_A
[2] = 0x00009000 + 0x024c, .MPC_GAMUT_REMAP_C33_C34_A[2] = 0x00009000
+ 0x0251, .MPC_GAMUT_REMAP_C11_C12_B[2] = 0x00009000 + 0x0252
, .MPC_GAMUT_REMAP_C33_C34_B[2] = 0x00009000 + 0x0257, .MPCC_OGAM_RAMA_START_CNTL_B
[2] = 0x00009000 + 0x0204, .MPCC_OGAM_RAMA_START_CNTL_G[2] = 0x00009000
+ 0x0205, .MPCC_OGAM_RAMA_START_CNTL_R[2] = 0x00009000 + 0x0206
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[2] = 0x00009000 + 0x0207
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[2] = 0x00009000 + 0x0208
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[2] = 0x00009000 + 0x0209
, .MPCC_OGAM_RAMA_END_CNTL1_B[2] = 0x00009000 + 0x020d, .MPCC_OGAM_RAMA_END_CNTL2_B
[2] = 0x00009000 + 0x020e, .MPCC_OGAM_RAMA_END_CNTL1_G[2] = 0x00009000
+ 0x020f, .MPCC_OGAM_RAMA_END_CNTL2_G[2] = 0x00009000 + 0x0210
, .MPCC_OGAM_RAMA_END_CNTL1_R[2] = 0x00009000 + 0x0211, .MPCC_OGAM_RAMA_END_CNTL2_R
[2] = 0x00009000 + 0x0212, .MPCC_OGAM_RAMA_REGION_0_1[2] = 0x00009000
+ 0x0216, .MPCC_OGAM_RAMA_REGION_32_33[2] = 0x00009000 + 0x0226
, .MPCC_OGAM_RAMA_OFFSET_B[2] = 0x00009000 + 0x0213, .MPCC_OGAM_RAMA_OFFSET_G
[2] = 0x00009000 + 0x0214, .MPCC_OGAM_RAMA_OFFSET_R[2] = 0x00009000
+ 0x0215, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[2] = 0x00009000 +
0x020a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[2] = 0x00009000 + 0x020b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[2] = 0x00009000 + 0x020c,
.MPCC_OGAM_RAMB_START_CNTL_B[2] = 0x00009000 + 0x0227, .MPCC_OGAM_RAMB_START_CNTL_G
[2] = 0x00009000 + 0x0228, .MPCC_OGAM_RAMB_START_CNTL_R[2] = 0x00009000
+ 0x0229, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[2] = 0x00009000
+ 0x022a, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[2] = 0x00009000
+ 0x022b, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[2] = 0x00009000
+ 0x022c, .MPCC_OGAM_RAMB_END_CNTL1_B[2] = 0x00009000 + 0x0230
, .MPCC_OGAM_RAMB_END_CNTL2_B[2] = 0x00009000 + 0x0231, .MPCC_OGAM_RAMB_END_CNTL1_G
[2] = 0x00009000 + 0x0232, .MPCC_OGAM_RAMB_END_CNTL2_G[2] = 0x00009000
+ 0x0233, .MPCC_OGAM_RAMB_END_CNTL1_R[2] = 0x00009000 + 0x0234
, .MPCC_OGAM_RAMB_END_CNTL2_R[2] = 0x00009000 + 0x0235, .MPCC_OGAM_RAMB_REGION_0_1
[2] = 0x00009000 + 0x0239, .MPCC_OGAM_RAMB_REGION_32_33[2] = 0x00009000
+ 0x0249, .MPCC_OGAM_RAMB_OFFSET_B[2] = 0x00009000 + 0x0236,
.MPCC_OGAM_RAMB_OFFSET_G[2] = 0x00009000 + 0x0237, .MPCC_OGAM_RAMB_OFFSET_R
[2] = 0x00009000 + 0x0238, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
2] = 0x00009000 + 0x022d, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[2
] = 0x00009000 + 0x022e, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[2]
= 0x00009000 + 0x022f, .MPCC_OGAM_CONTROL[2] = 0x00009000 + 0x0200
, .MPCC_OGAM_LUT_CONTROL[2] = 0x00009000 + 0x0203,
660 MPC_REG_LIST_DCN3_0(3).MPCC_TOP_SEL[3] = 0x00009000 + 0x0060, .MPCC_BOT_SEL[3] = 0x00009000
+ 0x0061, .MPCC_CONTROL[3] = 0x00009000 + 0x0063, .MPCC_STATUS
[3] = 0x00009000 + 0x006d, .MPCC_OPP_ID[3] = 0x00009000 + 0x0062
, .MPCC_BG_G_Y[3] = 0x00009000 + 0x006a, .MPCC_BG_R_CR[3] = 0x00009000
+ 0x0069, .MPCC_BG_B_CB[3] = 0x00009000 + 0x006b, .MPCC_SM_CONTROL
[3] = 0x00009000 + 0x0064, .MPCC_UPDATE_LOCK_SEL[3] = 0x00009000
+ 0x0065, .MPCC_TOP_GAIN[3] = 0x00009000 + 0x0066, .MPCC_BOT_GAIN_INSIDE
[3] = 0x00009000 + 0x0067, .MPCC_BOT_GAIN_OUTSIDE[3] = 0x00009000
+ 0x0068, .MPCC_MEM_PWR_CTRL[3] = 0x00009000 + 0x006c, .MPCC_OGAM_LUT_INDEX
[3] = 0x00009000 + 0x0281, .MPCC_OGAM_LUT_DATA[3] = 0x00009000
+ 0x0282, .MPCC_GAMUT_REMAP_COEF_FORMAT[3] = 0x00009000 + 0x02ca
, .MPCC_GAMUT_REMAP_MODE[3] = 0x00009000 + 0x02cb, .MPC_GAMUT_REMAP_C11_C12_A
[3] = 0x00009000 + 0x02cc, .MPC_GAMUT_REMAP_C33_C34_A[3] = 0x00009000
+ 0x02d1, .MPC_GAMUT_REMAP_C11_C12_B[3] = 0x00009000 + 0x02d2
, .MPC_GAMUT_REMAP_C33_C34_B[3] = 0x00009000 + 0x02d7, .MPCC_OGAM_RAMA_START_CNTL_B
[3] = 0x00009000 + 0x0284, .MPCC_OGAM_RAMA_START_CNTL_G[3] = 0x00009000
+ 0x0285, .MPCC_OGAM_RAMA_START_CNTL_R[3] = 0x00009000 + 0x0286
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[3] = 0x00009000 + 0x0287
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[3] = 0x00009000 + 0x0288
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[3] = 0x00009000 + 0x0289
, .MPCC_OGAM_RAMA_END_CNTL1_B[3] = 0x00009000 + 0x028d, .MPCC_OGAM_RAMA_END_CNTL2_B
[3] = 0x00009000 + 0x028e, .MPCC_OGAM_RAMA_END_CNTL1_G[3] = 0x00009000
+ 0x028f, .MPCC_OGAM_RAMA_END_CNTL2_G[3] = 0x00009000 + 0x0290
, .MPCC_OGAM_RAMA_END_CNTL1_R[3] = 0x00009000 + 0x0291, .MPCC_OGAM_RAMA_END_CNTL2_R
[3] = 0x00009000 + 0x0292, .MPCC_OGAM_RAMA_REGION_0_1[3] = 0x00009000
+ 0x0296, .MPCC_OGAM_RAMA_REGION_32_33[3] = 0x00009000 + 0x02a6
, .MPCC_OGAM_RAMA_OFFSET_B[3] = 0x00009000 + 0x0293, .MPCC_OGAM_RAMA_OFFSET_G
[3] = 0x00009000 + 0x0294, .MPCC_OGAM_RAMA_OFFSET_R[3] = 0x00009000
+ 0x0295, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[3] = 0x00009000 +
0x028a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[3] = 0x00009000 + 0x028b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[3] = 0x00009000 + 0x028c,
.MPCC_OGAM_RAMB_START_CNTL_B[3] = 0x00009000 + 0x02a7, .MPCC_OGAM_RAMB_START_CNTL_G
[3] = 0x00009000 + 0x02a8, .MPCC_OGAM_RAMB_START_CNTL_R[3] = 0x00009000
+ 0x02a9, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[3] = 0x00009000
+ 0x02aa, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[3] = 0x00009000
+ 0x02ab, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[3] = 0x00009000
+ 0x02ac, .MPCC_OGAM_RAMB_END_CNTL1_B[3] = 0x00009000 + 0x02b0
, .MPCC_OGAM_RAMB_END_CNTL2_B[3] = 0x00009000 + 0x02b1, .MPCC_OGAM_RAMB_END_CNTL1_G
[3] = 0x00009000 + 0x02b2, .MPCC_OGAM_RAMB_END_CNTL2_G[3] = 0x00009000
+ 0x02b3, .MPCC_OGAM_RAMB_END_CNTL1_R[3] = 0x00009000 + 0x02b4
, .MPCC_OGAM_RAMB_END_CNTL2_R[3] = 0x00009000 + 0x02b5, .MPCC_OGAM_RAMB_REGION_0_1
[3] = 0x00009000 + 0x02b9, .MPCC_OGAM_RAMB_REGION_32_33[3] = 0x00009000
+ 0x02c9, .MPCC_OGAM_RAMB_OFFSET_B[3] = 0x00009000 + 0x02b6,
.MPCC_OGAM_RAMB_OFFSET_G[3] = 0x00009000 + 0x02b7, .MPCC_OGAM_RAMB_OFFSET_R
[3] = 0x00009000 + 0x02b8, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
3] = 0x00009000 + 0x02ad, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[3
] = 0x00009000 + 0x02ae, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[3]
= 0x00009000 + 0x02af, .MPCC_OGAM_CONTROL[3] = 0x00009000 + 0x0280
, .MPCC_OGAM_LUT_CONTROL[3] = 0x00009000 + 0x0283,
661 MPC_REG_LIST_DCN3_0(4).MPCC_TOP_SEL[4] = 0x00009000 + 0x0080, .MPCC_BOT_SEL[4] = 0x00009000
+ 0x0081, .MPCC_CONTROL[4] = 0x00009000 + 0x0083, .MPCC_STATUS
[4] = 0x00009000 + 0x008d, .MPCC_OPP_ID[4] = 0x00009000 + 0x0082
, .MPCC_BG_G_Y[4] = 0x00009000 + 0x008a, .MPCC_BG_R_CR[4] = 0x00009000
+ 0x0089, .MPCC_BG_B_CB[4] = 0x00009000 + 0x008b, .MPCC_SM_CONTROL
[4] = 0x00009000 + 0x0084, .MPCC_UPDATE_LOCK_SEL[4] = 0x00009000
+ 0x0085, .MPCC_TOP_GAIN[4] = 0x00009000 + 0x0086, .MPCC_BOT_GAIN_INSIDE
[4] = 0x00009000 + 0x0087, .MPCC_BOT_GAIN_OUTSIDE[4] = 0x00009000
+ 0x0088, .MPCC_MEM_PWR_CTRL[4] = 0x00009000 + 0x008c, .MPCC_OGAM_LUT_INDEX
[4] = 0x00009000 + 0x0301, .MPCC_OGAM_LUT_DATA[4] = 0x00009000
+ 0x0302, .MPCC_GAMUT_REMAP_COEF_FORMAT[4] = 0x00009000 + 0x034a
, .MPCC_GAMUT_REMAP_MODE[4] = 0x00009000 + 0x034b, .MPC_GAMUT_REMAP_C11_C12_A
[4] = 0x00009000 + 0x034c, .MPC_GAMUT_REMAP_C33_C34_A[4] = 0x00009000
+ 0x0351, .MPC_GAMUT_REMAP_C11_C12_B[4] = 0x00009000 + 0x0352
, .MPC_GAMUT_REMAP_C33_C34_B[4] = 0x00009000 + 0x0357, .MPCC_OGAM_RAMA_START_CNTL_B
[4] = 0x00009000 + 0x0304, .MPCC_OGAM_RAMA_START_CNTL_G[4] = 0x00009000
+ 0x0305, .MPCC_OGAM_RAMA_START_CNTL_R[4] = 0x00009000 + 0x0306
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[4] = 0x00009000 + 0x0307
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[4] = 0x00009000 + 0x0308
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[4] = 0x00009000 + 0x0309
, .MPCC_OGAM_RAMA_END_CNTL1_B[4] = 0x00009000 + 0x030d, .MPCC_OGAM_RAMA_END_CNTL2_B
[4] = 0x00009000 + 0x030e, .MPCC_OGAM_RAMA_END_CNTL1_G[4] = 0x00009000
+ 0x030f, .MPCC_OGAM_RAMA_END_CNTL2_G[4] = 0x00009000 + 0x0310
, .MPCC_OGAM_RAMA_END_CNTL1_R[4] = 0x00009000 + 0x0311, .MPCC_OGAM_RAMA_END_CNTL2_R
[4] = 0x00009000 + 0x0312, .MPCC_OGAM_RAMA_REGION_0_1[4] = 0x00009000
+ 0x0316, .MPCC_OGAM_RAMA_REGION_32_33[4] = 0x00009000 + 0x0326
, .MPCC_OGAM_RAMA_OFFSET_B[4] = 0x00009000 + 0x0313, .MPCC_OGAM_RAMA_OFFSET_G
[4] = 0x00009000 + 0x0314, .MPCC_OGAM_RAMA_OFFSET_R[4] = 0x00009000
+ 0x0315, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[4] = 0x00009000 +
0x030a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[4] = 0x00009000 + 0x030b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[4] = 0x00009000 + 0x030c,
.MPCC_OGAM_RAMB_START_CNTL_B[4] = 0x00009000 + 0x0327, .MPCC_OGAM_RAMB_START_CNTL_G
[4] = 0x00009000 + 0x0328, .MPCC_OGAM_RAMB_START_CNTL_R[4] = 0x00009000
+ 0x0329, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[4] = 0x00009000
+ 0x032a, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[4] = 0x00009000
+ 0x032b, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[4] = 0x00009000
+ 0x032c, .MPCC_OGAM_RAMB_END_CNTL1_B[4] = 0x00009000 + 0x0330
, .MPCC_OGAM_RAMB_END_CNTL2_B[4] = 0x00009000 + 0x0331, .MPCC_OGAM_RAMB_END_CNTL1_G
[4] = 0x00009000 + 0x0332, .MPCC_OGAM_RAMB_END_CNTL2_G[4] = 0x00009000
+ 0x0333, .MPCC_OGAM_RAMB_END_CNTL1_R[4] = 0x00009000 + 0x0334
, .MPCC_OGAM_RAMB_END_CNTL2_R[4] = 0x00009000 + 0x0335, .MPCC_OGAM_RAMB_REGION_0_1
[4] = 0x00009000 + 0x0339, .MPCC_OGAM_RAMB_REGION_32_33[4] = 0x00009000
+ 0x0349, .MPCC_OGAM_RAMB_OFFSET_B[4] = 0x00009000 + 0x0336,
.MPCC_OGAM_RAMB_OFFSET_G[4] = 0x00009000 + 0x0337, .MPCC_OGAM_RAMB_OFFSET_R
[4] = 0x00009000 + 0x0338, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
4] = 0x00009000 + 0x032d, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[4
] = 0x00009000 + 0x032e, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[4]
= 0x00009000 + 0x032f, .MPCC_OGAM_CONTROL[4] = 0x00009000 + 0x0300
, .MPCC_OGAM_LUT_CONTROL[4] = 0x00009000 + 0x0303,
662 MPC_REG_LIST_DCN3_0(5).MPCC_TOP_SEL[5] = 0x00009000 + 0x00a0, .MPCC_BOT_SEL[5] = 0x00009000
+ 0x00a1, .MPCC_CONTROL[5] = 0x00009000 + 0x00a3, .MPCC_STATUS
[5] = 0x00009000 + 0x00ad, .MPCC_OPP_ID[5] = 0x00009000 + 0x00a2
, .MPCC_BG_G_Y[5] = 0x00009000 + 0x00aa, .MPCC_BG_R_CR[5] = 0x00009000
+ 0x00a9, .MPCC_BG_B_CB[5] = 0x00009000 + 0x00ab, .MPCC_SM_CONTROL
[5] = 0x00009000 + 0x00a4, .MPCC_UPDATE_LOCK_SEL[5] = 0x00009000
+ 0x00a5, .MPCC_TOP_GAIN[5] = 0x00009000 + 0x00a6, .MPCC_BOT_GAIN_INSIDE
[5] = 0x00009000 + 0x00a7, .MPCC_BOT_GAIN_OUTSIDE[5] = 0x00009000
+ 0x00a8, .MPCC_MEM_PWR_CTRL[5] = 0x00009000 + 0x00ac, .MPCC_OGAM_LUT_INDEX
[5] = 0x00009000 + 0x0381, .MPCC_OGAM_LUT_DATA[5] = 0x00009000
+ 0x0382, .MPCC_GAMUT_REMAP_COEF_FORMAT[5] = 0x00009000 + 0x03ca
, .MPCC_GAMUT_REMAP_MODE[5] = 0x00009000 + 0x03cb, .MPC_GAMUT_REMAP_C11_C12_A
[5] = 0x00009000 + 0x03cc, .MPC_GAMUT_REMAP_C33_C34_A[5] = 0x00009000
+ 0x03d1, .MPC_GAMUT_REMAP_C11_C12_B[5] = 0x00009000 + 0x03d2
, .MPC_GAMUT_REMAP_C33_C34_B[5] = 0x00009000 + 0x03d7, .MPCC_OGAM_RAMA_START_CNTL_B
[5] = 0x00009000 + 0x0384, .MPCC_OGAM_RAMA_START_CNTL_G[5] = 0x00009000
+ 0x0385, .MPCC_OGAM_RAMA_START_CNTL_R[5] = 0x00009000 + 0x0386
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[5] = 0x00009000 + 0x0387
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[5] = 0x00009000 + 0x0388
, .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[5] = 0x00009000 + 0x0389
, .MPCC_OGAM_RAMA_END_CNTL1_B[5] = 0x00009000 + 0x038d, .MPCC_OGAM_RAMA_END_CNTL2_B
[5] = 0x00009000 + 0x038e, .MPCC_OGAM_RAMA_END_CNTL1_G[5] = 0x00009000
+ 0x038f, .MPCC_OGAM_RAMA_END_CNTL2_G[5] = 0x00009000 + 0x0390
, .MPCC_OGAM_RAMA_END_CNTL1_R[5] = 0x00009000 + 0x0391, .MPCC_OGAM_RAMA_END_CNTL2_R
[5] = 0x00009000 + 0x0392, .MPCC_OGAM_RAMA_REGION_0_1[5] = 0x00009000
+ 0x0396, .MPCC_OGAM_RAMA_REGION_32_33[5] = 0x00009000 + 0x03a6
, .MPCC_OGAM_RAMA_OFFSET_B[5] = 0x00009000 + 0x0393, .MPCC_OGAM_RAMA_OFFSET_G
[5] = 0x00009000 + 0x0394, .MPCC_OGAM_RAMA_OFFSET_R[5] = 0x00009000
+ 0x0395, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[5] = 0x00009000 +
0x038a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[5] = 0x00009000 + 0x038b
, .MPCC_OGAM_RAMA_START_BASE_CNTL_R[5] = 0x00009000 + 0x038c,
.MPCC_OGAM_RAMB_START_CNTL_B[5] = 0x00009000 + 0x03a7, .MPCC_OGAM_RAMB_START_CNTL_G
[5] = 0x00009000 + 0x03a8, .MPCC_OGAM_RAMB_START_CNTL_R[5] = 0x00009000
+ 0x03a9, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[5] = 0x00009000
+ 0x03aa, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[5] = 0x00009000
+ 0x03ab, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[5] = 0x00009000
+ 0x03ac, .MPCC_OGAM_RAMB_END_CNTL1_B[5] = 0x00009000 + 0x03b0
, .MPCC_OGAM_RAMB_END_CNTL2_B[5] = 0x00009000 + 0x03b1, .MPCC_OGAM_RAMB_END_CNTL1_G
[5] = 0x00009000 + 0x03b2, .MPCC_OGAM_RAMB_END_CNTL2_G[5] = 0x00009000
+ 0x03b3, .MPCC_OGAM_RAMB_END_CNTL1_R[5] = 0x00009000 + 0x03b4
, .MPCC_OGAM_RAMB_END_CNTL2_R[5] = 0x00009000 + 0x03b5, .MPCC_OGAM_RAMB_REGION_0_1
[5] = 0x00009000 + 0x03b9, .MPCC_OGAM_RAMB_REGION_32_33[5] = 0x00009000
+ 0x03c9, .MPCC_OGAM_RAMB_OFFSET_B[5] = 0x00009000 + 0x03b6,
.MPCC_OGAM_RAMB_OFFSET_G[5] = 0x00009000 + 0x03b7, .MPCC_OGAM_RAMB_OFFSET_R
[5] = 0x00009000 + 0x03b8, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[
5] = 0x00009000 + 0x03ad, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[5
] = 0x00009000 + 0x03ae, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[5]
= 0x00009000 + 0x03af, .MPCC_OGAM_CONTROL[5] = 0x00009000 + 0x0380
, .MPCC_OGAM_LUT_CONTROL[5] = 0x00009000 + 0x0383,
663 MPC_OUT_MUX_REG_LIST_DCN3_0(0).MUX[0] = 0x00009000 + 0x0580, .CUR[0] = 0x00009000 + 0x0513,
.CSC_MODE[0] = 0x00009000 + 0x0599, .CSC_C11_C12_A[0] = 0x00009000
+ 0x059a, .CSC_C33_C34_A[0] = 0x00009000 + 0x059f, .CSC_C11_C12_B
[0] = 0x00009000 + 0x05a0, .CSC_C33_C34_B[0] = 0x00009000 + 0x05a5
, .DENORM_CONTROL[0] = 0x00009000 + 0x0581, .DENORM_CLAMP_G_Y
[0] = 0x00009000 + 0x0582, .DENORM_CLAMP_B_CB[0] = 0x00009000
+ 0x0583, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
664 MPC_OUT_MUX_REG_LIST_DCN3_0(1).MUX[1] = 0x00009000 + 0x0584, .CUR[1] = 0x00009000 + 0x0518,
.CSC_MODE[1] = 0x00009000 + 0x05a6, .CSC_C11_C12_A[1] = 0x00009000
+ 0x05a7, .CSC_C33_C34_A[1] = 0x00009000 + 0x05ac, .CSC_C11_C12_B
[1] = 0x00009000 + 0x05ad, .CSC_C33_C34_B[1] = 0x00009000 + 0x05b2
, .DENORM_CONTROL[1] = 0x00009000 + 0x0585, .DENORM_CLAMP_G_Y
[1] = 0x00009000 + 0x0586, .DENORM_CLAMP_B_CB[1] = 0x00009000
+ 0x0587, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
665 MPC_OUT_MUX_REG_LIST_DCN3_0(2).MUX[2] = 0x00009000 + 0x0588, .CUR[2] = 0x00009000 + 0x051d,
.CSC_MODE[2] = 0x00009000 + 0x05b3, .CSC_C11_C12_A[2] = 0x00009000
+ 0x05b4, .CSC_C33_C34_A[2] = 0x00009000 + 0x05b9, .CSC_C11_C12_B
[2] = 0x00009000 + 0x05ba, .CSC_C33_C34_B[2] = 0x00009000 + 0x05bf
, .DENORM_CONTROL[2] = 0x00009000 + 0x0589, .DENORM_CLAMP_G_Y
[2] = 0x00009000 + 0x058a, .DENORM_CLAMP_B_CB[2] = 0x00009000
+ 0x058b, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
666 MPC_OUT_MUX_REG_LIST_DCN3_0(3).MUX[3] = 0x00009000 + 0x058c, .CUR[3] = 0x00009000 + 0x0522,
.CSC_MODE[3] = 0x00009000 + 0x05c0, .CSC_C11_C12_A[3] = 0x00009000
+ 0x05c1, .CSC_C33_C34_A[3] = 0x00009000 + 0x05c6, .CSC_C11_C12_B
[3] = 0x00009000 + 0x05c7, .CSC_C33_C34_B[3] = 0x00009000 + 0x05cc
, .DENORM_CONTROL[3] = 0x00009000 + 0x058d, .DENORM_CLAMP_G_Y
[3] = 0x00009000 + 0x058e, .DENORM_CLAMP_B_CB[3] = 0x00009000
+ 0x058f, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
667 MPC_OUT_MUX_REG_LIST_DCN3_0(4).MUX[4] = 0x00009000 + 0x0590, .CUR[4] = 0x00009000 + 0x0527,
.CSC_MODE[4] = 0x00009000 + 0x05cd, .CSC_C11_C12_A[4] = 0x00009000
+ 0x05ce, .CSC_C33_C34_A[4] = 0x00009000 + 0x05d3, .CSC_C11_C12_B
[4] = 0x00009000 + 0x05d4, .CSC_C33_C34_B[4] = 0x00009000 + 0x05d9
, .DENORM_CONTROL[4] = 0x00009000 + 0x0591, .DENORM_CLAMP_G_Y
[4] = 0x00009000 + 0x0592, .DENORM_CLAMP_B_CB[4] = 0x00009000
+ 0x0593, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
668 MPC_OUT_MUX_REG_LIST_DCN3_0(5).MUX[5] = 0x00009000 + 0x0594, .CUR[5] = 0x00009000 + 0x052c,
.CSC_MODE[5] = 0x00009000 + 0x05da, .CSC_C11_C12_A[5] = 0x00009000
+ 0x05db, .CSC_C33_C34_A[5] = 0x00009000 + 0x05e0, .CSC_C11_C12_B
[5] = 0x00009000 + 0x05e1, .CSC_C33_C34_B[5] = 0x00009000 + 0x05e6
, .DENORM_CONTROL[5] = 0x00009000 + 0x0595, .DENORM_CLAMP_G_Y
[5] = 0x00009000 + 0x0596, .DENORM_CLAMP_B_CB[5] = 0x00009000
+ 0x0597, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x0598,
669 MPC_RMU_GLOBAL_REG_LIST_DCN3AG.MPC_RMU_CONTROL = 0x00009000 + 0x0680, .MPC_RMU_MEM_PWR_CTRL
= 0x00009000 + 0x0681,
670 MPC_RMU_REG_LIST_DCN3AG(0).SHAPER_CONTROL[0] = 0x00009000 + 0x0682, .SHAPER_OFFSET_R[0]
= 0x00009000 + 0x0683, .SHAPER_OFFSET_G[0] = 0x00009000 + 0x0684
, .SHAPER_OFFSET_B[0] = 0x00009000 + 0x0685, .SHAPER_SCALE_R[
0] = 0x00009000 + 0x0686, .SHAPER_SCALE_G_B[0] = 0x00009000 +
0x0687, .SHAPER_LUT_INDEX[0] = 0x00009000 + 0x0688, .SHAPER_LUT_DATA
[0] = 0x00009000 + 0x0689, .SHAPER_LUT_WRITE_EN_MASK[0] = 0x00009000
+ 0x068a, .SHAPER_RAMA_START_CNTL_B[0] = 0x00009000 + 0x068b
, .SHAPER_RAMA_START_CNTL_G[0] = 0x00009000 + 0x068c, .SHAPER_RAMA_START_CNTL_R
[0] = 0x00009000 + 0x068d, .SHAPER_RAMA_END_CNTL_B[0] = 0x00009000
+ 0x068e, .SHAPER_RAMA_END_CNTL_G[0] = 0x00009000 + 0x068f, .
SHAPER_RAMA_END_CNTL_R[0] = 0x00009000 + 0x0690, .SHAPER_RAMA_REGION_0_1
[0] = 0x00009000 + 0x0691, .SHAPER_RAMA_REGION_2_3[0] = 0x00009000
+ 0x0692, .SHAPER_RAMA_REGION_4_5[0] = 0x00009000 + 0x0693, .
SHAPER_RAMA_REGION_6_7[0] = 0x00009000 + 0x0694, .SHAPER_RAMA_REGION_8_9
[0] = 0x00009000 + 0x0695, .SHAPER_RAMA_REGION_10_11[0] = 0x00009000
+ 0x0696, .SHAPER_RAMA_REGION_12_13[0] = 0x00009000 + 0x0697
, .SHAPER_RAMA_REGION_14_15[0] = 0x00009000 + 0x0698, .SHAPER_RAMA_REGION_16_17
[0] = 0x00009000 + 0x0699, .SHAPER_RAMA_REGION_18_19[0] = 0x00009000
+ 0x069a, .SHAPER_RAMA_REGION_20_21[0] = 0x00009000 + 0x069b
, .SHAPER_RAMA_REGION_22_23[0] = 0x00009000 + 0x069c, .SHAPER_RAMA_REGION_24_25
[0] = 0x00009000 + 0x069d, .SHAPER_RAMA_REGION_26_27[0] = 0x00009000
+ 0x069e, .SHAPER_RAMA_REGION_28_29[0] = 0x00009000 + 0x069f
, .SHAPER_RAMA_REGION_30_31[0] = 0x00009000 + 0x06a0, .SHAPER_RAMA_REGION_32_33
[0] = 0x00009000 + 0x06a1, .SHAPER_RAMB_START_CNTL_B[0] = 0x00009000
+ 0x06a2, .SHAPER_RAMB_START_CNTL_G[0] = 0x00009000 + 0x06a3
, .SHAPER_RAMB_START_CNTL_R[0] = 0x00009000 + 0x06a4, .SHAPER_RAMB_END_CNTL_B
[0] = 0x00009000 + 0x06a5, .SHAPER_RAMB_END_CNTL_G[0] = 0x00009000
+ 0x06a6, .SHAPER_RAMB_END_CNTL_R[0] = 0x00009000 + 0x06a7, .
SHAPER_RAMB_REGION_0_1[0] = 0x00009000 + 0x06a8, .SHAPER_RAMB_REGION_2_3
[0] = 0x00009000 + 0x06a9, .SHAPER_RAMB_REGION_4_5[0] = 0x00009000
+ 0x06aa, .SHAPER_RAMB_REGION_6_7[0] = 0x00009000 + 0x06ab, .
SHAPER_RAMB_REGION_8_9[0] = 0x00009000 + 0x06ac, .SHAPER_RAMB_REGION_10_11
[0] = 0x00009000 + 0x06ad, .SHAPER_RAMB_REGION_12_13[0] = 0x00009000
+ 0x06ae, .SHAPER_RAMB_REGION_14_15[0] = 0x00009000 + 0x06af
, .SHAPER_RAMB_REGION_16_17[0] = 0x00009000 + 0x06b0, .SHAPER_RAMB_REGION_18_19
[0] = 0x00009000 + 0x06b1, .SHAPER_RAMB_REGION_20_21[0] = 0x00009000
+ 0x06b2, .SHAPER_RAMB_REGION_22_23[0] = 0x00009000 + 0x06b3
, .SHAPER_RAMB_REGION_24_25[0] = 0x00009000 + 0x06b4, .SHAPER_RAMB_REGION_26_27
[0] = 0x00009000 + 0x06b5, .SHAPER_RAMB_REGION_28_29[0] = 0x00009000
+ 0x06b6, .SHAPER_RAMB_REGION_30_31[0] = 0x00009000 + 0x06b7
, .SHAPER_RAMB_REGION_32_33[0] = 0x00009000 + 0x06b8, .RMU_3DLUT_MODE
[0] = 0x00009000 + 0x06b9, .RMU_3DLUT_INDEX[0] = 0x00009000 +
0x06ba, .RMU_3DLUT_DATA[0] = 0x00009000 + 0x06bb, .RMU_3DLUT_DATA_30BIT
[0] = 0x00009000 + 0x06bc, .RMU_3DLUT_READ_WRITE_CONTROL[0] =
0x00009000 + 0x06bd, .RMU_3DLUT_OUT_NORM_FACTOR[0] = 0x00009000
+ 0x06be, .RMU_3DLUT_OUT_OFFSET_R[0] = 0x00009000 + 0x06bf, .
RMU_3DLUT_OUT_OFFSET_G[0] = 0x00009000 + 0x06c0, .RMU_3DLUT_OUT_OFFSET_B
[0] = 0x00009000 + 0x06c1,
671 MPC_RMU_REG_LIST_DCN3AG(1).SHAPER_CONTROL[1] = 0x00009000 + 0x06c2, .SHAPER_OFFSET_R[1]
= 0x00009000 + 0x06c3, .SHAPER_OFFSET_G[1] = 0x00009000 + 0x06c4
, .SHAPER_OFFSET_B[1] = 0x00009000 + 0x06c5, .SHAPER_SCALE_R[
1] = 0x00009000 + 0x06c6, .SHAPER_SCALE_G_B[1] = 0x00009000 +
0x06c7, .SHAPER_LUT_INDEX[1] = 0x00009000 + 0x06c8, .SHAPER_LUT_DATA
[1] = 0x00009000 + 0x06c9, .SHAPER_LUT_WRITE_EN_MASK[1] = 0x00009000
+ 0x06ca, .SHAPER_RAMA_START_CNTL_B[1] = 0x00009000 + 0x06cb
, .SHAPER_RAMA_START_CNTL_G[1] = 0x00009000 + 0x06cc, .SHAPER_RAMA_START_CNTL_R
[1] = 0x00009000 + 0x06cd, .SHAPER_RAMA_END_CNTL_B[1] = 0x00009000
+ 0x06ce, .SHAPER_RAMA_END_CNTL_G[1] = 0x00009000 + 0x06cf, .
SHAPER_RAMA_END_CNTL_R[1] = 0x00009000 + 0x06d0, .SHAPER_RAMA_REGION_0_1
[1] = 0x00009000 + 0x06d1, .SHAPER_RAMA_REGION_2_3[1] = 0x00009000
+ 0x06d2, .SHAPER_RAMA_REGION_4_5[1] = 0x00009000 + 0x06d3, .
SHAPER_RAMA_REGION_6_7[1] = 0x00009000 + 0x06d4, .SHAPER_RAMA_REGION_8_9
[1] = 0x00009000 + 0x06d5, .SHAPER_RAMA_REGION_10_11[1] = 0x00009000
+ 0x06d6, .SHAPER_RAMA_REGION_12_13[1] = 0x00009000 + 0x06d7
, .SHAPER_RAMA_REGION_14_15[1] = 0x00009000 + 0x06d8, .SHAPER_RAMA_REGION_16_17
[1] = 0x00009000 + 0x06d9, .SHAPER_RAMA_REGION_18_19[1] = 0x00009000
+ 0x06da, .SHAPER_RAMA_REGION_20_21[1] = 0x00009000 + 0x06db
, .SHAPER_RAMA_REGION_22_23[1] = 0x00009000 + 0x06dc, .SHAPER_RAMA_REGION_24_25
[1] = 0x00009000 + 0x06dd, .SHAPER_RAMA_REGION_26_27[1] = 0x00009000
+ 0x06de, .SHAPER_RAMA_REGION_28_29[1] = 0x00009000 + 0x06df
, .SHAPER_RAMA_REGION_30_31[1] = 0x00009000 + 0x06e0, .SHAPER_RAMA_REGION_32_33
[1] = 0x00009000 + 0x06e1, .SHAPER_RAMB_START_CNTL_B[1] = 0x00009000
+ 0x06e2, .SHAPER_RAMB_START_CNTL_G[1] = 0x00009000 + 0x06e3
, .SHAPER_RAMB_START_CNTL_R[1] = 0x00009000 + 0x06e4, .SHAPER_RAMB_END_CNTL_B
[1] = 0x00009000 + 0x06e5, .SHAPER_RAMB_END_CNTL_G[1] = 0x00009000
+ 0x06e6, .SHAPER_RAMB_END_CNTL_R[1] = 0x00009000 + 0x06e7, .
SHAPER_RAMB_REGION_0_1[1] = 0x00009000 + 0x06e8, .SHAPER_RAMB_REGION_2_3
[1] = 0x00009000 + 0x06e9, .SHAPER_RAMB_REGION_4_5[1] = 0x00009000
+ 0x06ea, .SHAPER_RAMB_REGION_6_7[1] = 0x00009000 + 0x06eb, .
SHAPER_RAMB_REGION_8_9[1] = 0x00009000 + 0x06ec, .SHAPER_RAMB_REGION_10_11
[1] = 0x00009000 + 0x06ed, .SHAPER_RAMB_REGION_12_13[1] = 0x00009000
+ 0x06ee, .SHAPER_RAMB_REGION_14_15[1] = 0x00009000 + 0x06ef
, .SHAPER_RAMB_REGION_16_17[1] = 0x00009000 + 0x06f0, .SHAPER_RAMB_REGION_18_19
[1] = 0x00009000 + 0x06f1, .SHAPER_RAMB_REGION_20_21[1] = 0x00009000
+ 0x06f2, .SHAPER_RAMB_REGION_22_23[1] = 0x00009000 + 0x06f3
, .SHAPER_RAMB_REGION_24_25[1] = 0x00009000 + 0x06f4, .SHAPER_RAMB_REGION_26_27
[1] = 0x00009000 + 0x06f5, .SHAPER_RAMB_REGION_28_29[1] = 0x00009000
+ 0x06f6, .SHAPER_RAMB_REGION_30_31[1] = 0x00009000 + 0x06f7
, .SHAPER_RAMB_REGION_32_33[1] = 0x00009000 + 0x06f8, .RMU_3DLUT_MODE
[1] = 0x00009000 + 0x06f9, .RMU_3DLUT_INDEX[1] = 0x00009000 +
0x06fa, .RMU_3DLUT_DATA[1] = 0x00009000 + 0x06fb, .RMU_3DLUT_DATA_30BIT
[1] = 0x00009000 + 0x06fc, .RMU_3DLUT_READ_WRITE_CONTROL[1] =
0x00009000 + 0x06fd, .RMU_3DLUT_OUT_NORM_FACTOR[1] = 0x00009000
+ 0x06fe, .RMU_3DLUT_OUT_OFFSET_R[1] = 0x00009000 + 0x06ff, .
RMU_3DLUT_OUT_OFFSET_G[1] = 0x00009000 + 0x0700, .RMU_3DLUT_OUT_OFFSET_B
[1] = 0x00009000 + 0x0701,
672 MPC_RMU_REG_LIST_DCN3AG(2).SHAPER_CONTROL[2] = 0x00009000 + 0x0702, .SHAPER_OFFSET_R[2]
= 0x00009000 + 0x0703, .SHAPER_OFFSET_G[2] = 0x00009000 + 0x0704
, .SHAPER_OFFSET_B[2] = 0x00009000 + 0x0705, .SHAPER_SCALE_R[
2] = 0x00009000 + 0x0706, .SHAPER_SCALE_G_B[2] = 0x00009000 +
0x0707, .SHAPER_LUT_INDEX[2] = 0x00009000 + 0x0708, .SHAPER_LUT_DATA
[2] = 0x00009000 + 0x0709, .SHAPER_LUT_WRITE_EN_MASK[2] = 0x00009000
+ 0x070a, .SHAPER_RAMA_START_CNTL_B[2] = 0x00009000 + 0x070b
, .SHAPER_RAMA_START_CNTL_G[2] = 0x00009000 + 0x070c, .SHAPER_RAMA_START_CNTL_R
[2] = 0x00009000 + 0x070d, .SHAPER_RAMA_END_CNTL_B[2] = 0x00009000
+ 0x070e, .SHAPER_RAMA_END_CNTL_G[2] = 0x00009000 + 0x070f, .
SHAPER_RAMA_END_CNTL_R[2] = 0x00009000 + 0x0710, .SHAPER_RAMA_REGION_0_1
[2] = 0x00009000 + 0x0711, .SHAPER_RAMA_REGION_2_3[2] = 0x00009000
+ 0x0712, .SHAPER_RAMA_REGION_4_5[2] = 0x00009000 + 0x0713, .
SHAPER_RAMA_REGION_6_7[2] = 0x00009000 + 0x0714, .SHAPER_RAMA_REGION_8_9
[2] = 0x00009000 + 0x0715, .SHAPER_RAMA_REGION_10_11[2] = 0x00009000
+ 0x0716, .SHAPER_RAMA_REGION_12_13[2] = 0x00009000 + 0x0717
, .SHAPER_RAMA_REGION_14_15[2] = 0x00009000 + 0x0718, .SHAPER_RAMA_REGION_16_17
[2] = 0x00009000 + 0x0719, .SHAPER_RAMA_REGION_18_19[2] = 0x00009000
+ 0x071a, .SHAPER_RAMA_REGION_20_21[2] = 0x00009000 + 0x071b
, .SHAPER_RAMA_REGION_22_23[2] = 0x00009000 + 0x071c, .SHAPER_RAMA_REGION_24_25
[2] = 0x00009000 + 0x071d, .SHAPER_RAMA_REGION_26_27[2] = 0x00009000
+ 0x071e, .SHAPER_RAMA_REGION_28_29[2] = 0x00009000 + 0x071f
, .SHAPER_RAMA_REGION_30_31[2] = 0x00009000 + 0x0720, .SHAPER_RAMA_REGION_32_33
[2] = 0x00009000 + 0x0721, .SHAPER_RAMB_START_CNTL_B[2] = 0x00009000
+ 0x0722, .SHAPER_RAMB_START_CNTL_G[2] = 0x00009000 + 0x0723
, .SHAPER_RAMB_START_CNTL_R[2] = 0x00009000 + 0x0724, .SHAPER_RAMB_END_CNTL_B
[2] = 0x00009000 + 0x0725, .SHAPER_RAMB_END_CNTL_G[2] = 0x00009000
+ 0x0726, .SHAPER_RAMB_END_CNTL_R[2] = 0x00009000 + 0x0727, .
SHAPER_RAMB_REGION_0_1[2] = 0x00009000 + 0x0728, .SHAPER_RAMB_REGION_2_3
[2] = 0x00009000 + 0x0729, .SHAPER_RAMB_REGION_4_5[2] = 0x00009000
+ 0x072a, .SHAPER_RAMB_REGION_6_7[2] = 0x00009000 + 0x072b, .
SHAPER_RAMB_REGION_8_9[2] = 0x00009000 + 0x072c, .SHAPER_RAMB_REGION_10_11
[2] = 0x00009000 + 0x072d, .SHAPER_RAMB_REGION_12_13[2] = 0x00009000
+ 0x072e, .SHAPER_RAMB_REGION_14_15[2] = 0x00009000 + 0x072f
, .SHAPER_RAMB_REGION_16_17[2] = 0x00009000 + 0x0730, .SHAPER_RAMB_REGION_18_19
[2] = 0x00009000 + 0x0731, .SHAPER_RAMB_REGION_20_21[2] = 0x00009000
+ 0x0732, .SHAPER_RAMB_REGION_22_23[2] = 0x00009000 + 0x0733
, .SHAPER_RAMB_REGION_24_25[2] = 0x00009000 + 0x0734, .SHAPER_RAMB_REGION_26_27
[2] = 0x00009000 + 0x0735, .SHAPER_RAMB_REGION_28_29[2] = 0x00009000
+ 0x0736, .SHAPER_RAMB_REGION_30_31[2] = 0x00009000 + 0x0737
, .SHAPER_RAMB_REGION_32_33[2] = 0x00009000 + 0x0738, .RMU_3DLUT_MODE
[2] = 0x00009000 + 0x0739, .RMU_3DLUT_INDEX[2] = 0x00009000 +
0x073a, .RMU_3DLUT_DATA[2] = 0x00009000 + 0x073b, .RMU_3DLUT_DATA_30BIT
[2] = 0x00009000 + 0x073c, .RMU_3DLUT_READ_WRITE_CONTROL[2] =
0x00009000 + 0x073d, .RMU_3DLUT_OUT_NORM_FACTOR[2] = 0x00009000
+ 0x073e, .RMU_3DLUT_OUT_OFFSET_R[2] = 0x00009000 + 0x073f, .
RMU_3DLUT_OUT_OFFSET_G[2] = 0x00009000 + 0x0740, .RMU_3DLUT_OUT_OFFSET_B
[2] = 0x00009000 + 0x0741,
673 MPC_DWB_MUX_REG_LIST_DCN3_0(0).DWB_MUX[0] = 0x00009000 + 0x055c,
674};
675
676static const struct dcn30_mpc_shift mpc_shift = {
677 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).MPCC_TOP_SEL = 0x0, .MPCC_BOT_SEL = 0x0, .MPCC_MODE = 0x0, .
MPCC_ALPHA_BLND_MODE = 0x4, .MPCC_ALPHA_MULTIPLIED_MODE = 0x6
, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x7, .MPCC_GLOBAL_ALPHA = 0x10
, .MPCC_GLOBAL_GAIN = 0x18, .MPCC_IDLE = 0x0, .MPCC_BUSY = 0x1
, .MPCC_OPP_ID = 0x0, .MPCC_BG_G_Y = 0x0, .MPCC_BG_R_CR = 0x0
, .MPCC_BG_B_CB = 0x0, .MPCC_SM_EN = 0x0, .MPCC_SM_MODE = 0x1
, .MPCC_SM_FRAME_ALT = 0x4, .MPCC_SM_FIELD_ALT = 0x5, .MPCC_SM_FORCE_NEXT_FRAME_POL
= 0x8, .MPCC_SM_FORCE_NEXT_TOP_POL = 0x10, .MPC_OUT_MUX = 0x0
, .MPCC_UPDATE_LOCK_SEL = 0x0, .MPCC_BG_BPC = 0x8, .MPCC_BOT_GAIN_MODE
= 0xb, .MPCC_TOP_GAIN = 0x0, .MPCC_BOT_GAIN_INSIDE = 0x0, .MPCC_BOT_GAIN_OUTSIDE
= 0x0, .MPC_OCSC_MODE = 0x0, .MPC_OCSC_C11_A = 0x0, .MPC_OCSC_C12_A
= 0x10, .MPCC_DISABLED = 0x2, .MPCC_OGAM_MEM_PWR_FORCE = 0x0
, .MPCC_OGAM_MEM_PWR_DIS = 0x2, .MPC_OUT_DENORM_MODE = 0x18, .
MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_R_CR
= 0x0, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_G_Y
= 0x0, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_B_CB
= 0x0, .MPCC_GAMUT_REMAP_MODE = 0x0, .MPCC_GAMUT_REMAP_MODE_CURRENT
= 0x7, .MPCC_GAMUT_REMAP_COEF_FORMAT = 0x0, .MPCC_GAMUT_REMAP_C11_A
= 0x0, .MPCC_GAMUT_REMAP_C12_A = 0x10, .MPC_DWB0_MUX = 0x0, .
MPC_DWB0_MUX_STATUS = 0x4, .MPC_OUT_RATE_CONTROL = 0x9, .MPC_OUT_RATE_CONTROL_DISABLE
= 0x8, .MPC_OUT_FLOW_CONTROL_MODE = 0xa, .MPC_OUT_FLOW_CONTROL_COUNT
= 0xb, .MPC_RMU0_MUX = 0x0, .MPC_RMU1_MUX = 0x8, .MPC_RMU0_MUX_STATUS
= 0x4, .MPC_RMU1_MUX_STATUS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x0, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
= 0x10, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B
= 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B
= 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .MPCC_OGAM_RAMA_OFFSET_B = 0x0, .MPCC_OGAM_RAMA_OFFSET_G
= 0x0, .MPCC_OGAM_RAMA_OFFSET_R = 0x0, .MPCC_OGAM_LUT_INDEX =
0x0, .MPCC_OGAM_MODE = 0x0, .MPCC_OGAM_SELECT = 0x2, .MPCC_OGAM_PWL_DISABLE
= 0x3, .MPCC_OGAM_MODE_CURRENT = 0x7, .MPCC_OGAM_SELECT_CURRENT
= 0x9, .MPCC_OGAM_LUT_WRITE_COLOR_MASK = 0x0, .MPCC_OGAM_LUT_READ_COLOR_SEL
= 0x3, .MPCC_OGAM_LUT_READ_DBG = 0x5, .MPCC_OGAM_LUT_HOST_SEL
= 0x6, .MPCC_OGAM_LUT_CONFIG_MODE = 0x7, .MPCC_OGAM_LUT_DATA
= 0x0, .MPC_RMU_3DLUT_MODE = 0x0, .MPC_RMU_3DLUT_SIZE = 0x4,
.MPC_RMU_3DLUT_WRITE_EN_MASK = 0x0, .MPC_RMU_3DLUT_RAM_SEL =
0x4, .MPC_RMU_3DLUT_30BIT_EN = 0x8, .MPC_RMU_3DLUT_READ_SEL =
0x10, .MPC_RMU_3DLUT_INDEX = 0x0, .MPC_RMU_3DLUT_DATA0 = 0x0
, .MPC_RMU_3DLUT_DATA1 = 0x10, .MPC_RMU_3DLUT_DATA_30BIT = 0x2
, .MPC_RMU_SHAPER_LUT_MODE = 0x0, .MPC_RMU_SHAPER_OFFSET_R = 0x0
, .MPC_RMU_SHAPER_OFFSET_G = 0x0, .MPC_RMU_SHAPER_OFFSET_B = 0x0
, .MPC_RMU_SHAPER_SCALE_R = 0x0, .MPC_RMU_SHAPER_SCALE_G = 0x0
, .MPC_RMU_SHAPER_SCALE_B = 0x10, .MPC_RMU_SHAPER_LUT_INDEX =
0x0, .MPC_RMU_SHAPER_LUT_DATA = 0x0, .MPC_RMU_SHAPER_LUT_WRITE_EN_MASK
= 0x0, .MPC_RMU_SHAPER_LUT_WRITE_SEL = 0x4, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B
= 0x0, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14
, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B = 0x0, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B
= 0x10, .MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .
MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c
, .MPC_RMU0_MEM_PWR_FORCE = 0x0, .MPC_RMU0_MEM_PWR_DIS = 0x2,
.MPC_RMU0_SHAPER_MEM_PWR_STATE = 0x4, .MPC_RMU0_3DLUT_MEM_PWR_STATE
= 0x6, .MPC_RMU1_MEM_PWR_FORCE = 0xa, .MPC_RMU1_MEM_PWR_DIS =
0xc, .MPC_RMU1_SHAPER_MEM_PWR_STATE = 0xe, .MPC_RMU1_3DLUT_MEM_PWR_STATE
= 0x10, .MPC_RMU_SHAPER_MODE_CURRENT = 0x8, .CUR_VUPDATE_LOCK_SET
= 0x0
678};
679
680static const struct dcn30_mpc_mask mpc_mask = {
681 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK).MPCC_TOP_SEL = 0x0000000FL, .MPCC_BOT_SEL = 0x0000000FL, .MPCC_MODE
= 0x00000003L, .MPCC_ALPHA_BLND_MODE = 0x00000030L, .MPCC_ALPHA_MULTIPLIED_MODE
= 0x00000040L, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x00000080L,
.MPCC_GLOBAL_ALPHA = 0x00FF0000L, .MPCC_GLOBAL_GAIN = 0xFF000000L
, .MPCC_IDLE = 0x00000001L, .MPCC_BUSY = 0x00000002L, .MPCC_OPP_ID
= 0x0000000FL, .MPCC_BG_G_Y = 0x00000FFFL, .MPCC_BG_R_CR = 0x00000FFFL
, .MPCC_BG_B_CB = 0x00000FFFL, .MPCC_SM_EN = 0x00000001L, .MPCC_SM_MODE
= 0x0000000EL, .MPCC_SM_FRAME_ALT = 0x00000010L, .MPCC_SM_FIELD_ALT
= 0x00000020L, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x00000300L, .
MPCC_SM_FORCE_NEXT_TOP_POL = 0x00030000L, .MPC_OUT_MUX = 0x0000000FL
, .MPCC_UPDATE_LOCK_SEL = 0x0000000FL, .MPCC_BG_BPC = 0x00000700L
, .MPCC_BOT_GAIN_MODE = 0x00000800L, .MPCC_TOP_GAIN = 0x0007FFFFL
, .MPCC_BOT_GAIN_INSIDE = 0x0007FFFFL, .MPCC_BOT_GAIN_OUTSIDE
= 0x0007FFFFL, .MPC_OCSC_MODE = 0x00000003L, .MPC_OCSC_C11_A
= 0x0000FFFFL, .MPC_OCSC_C12_A = 0xFFFF0000L, .MPCC_DISABLED
= 0x00000004L, .MPCC_OGAM_MEM_PWR_FORCE = 0x00000003L, .MPCC_OGAM_MEM_PWR_DIS
= 0x00000004L, .MPC_OUT_DENORM_MODE = 0x07000000L, .MPC_OUT_DENORM_CLAMP_MAX_R_CR
= 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x00000FFFL,
.MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_G_Y
= 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0x00FFF000L,
.MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x00000FFFL, .MPCC_GAMUT_REMAP_MODE
= 0x00000003L, .MPCC_GAMUT_REMAP_MODE_CURRENT = 0x00000180L,
.MPCC_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, .MPCC_GAMUT_REMAP_C11_A
= 0x0000FFFFL, .MPCC_GAMUT_REMAP_C12_A = 0xFFFF0000L, .MPC_DWB0_MUX
= 0x0000000FL, .MPC_DWB0_MUX_STATUS = 0x000000F0L, .MPC_OUT_RATE_CONTROL
= 0x00000200L, .MPC_OUT_RATE_CONTROL_DISABLE = 0x00000100L, .
MPC_OUT_FLOW_CONTROL_MODE = 0x00000400L, .MPC_OUT_FLOW_CONTROL_COUNT
= 0x007FF800L, .MPC_RMU0_MUX = 0x0000000FL, .MPC_RMU1_MUX = 0x00000F00L
, .MPC_RMU0_MUX_STATUS = 0x000000F0L, .MPC_RMU1_MUX_STATUS = 0x0000F000L
, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
= 0xFFFF0000L, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL
, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B
= 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL
, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x07F00000L, .MPCC_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_G
= 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .MPCC_OGAM_LUT_INDEX
= 0x000001FFL, .MPCC_OGAM_MODE = 0x00000003L, .MPCC_OGAM_SELECT
= 0x00000004L, .MPCC_OGAM_PWL_DISABLE = 0x00000008L, .MPCC_OGAM_MODE_CURRENT
= 0x00000180L, .MPCC_OGAM_SELECT_CURRENT = 0x00000200L, .MPCC_OGAM_LUT_WRITE_COLOR_MASK
= 0x00000007L, .MPCC_OGAM_LUT_READ_COLOR_SEL = 0x00000018L, .
MPCC_OGAM_LUT_READ_DBG = 0x00000020L, .MPCC_OGAM_LUT_HOST_SEL
= 0x00000040L, .MPCC_OGAM_LUT_CONFIG_MODE = 0x00000080L, .MPCC_OGAM_LUT_DATA
= 0x0003FFFFL, .MPC_RMU_3DLUT_MODE = 0x00000003L, .MPC_RMU_3DLUT_SIZE
= 0x00000010L, .MPC_RMU_3DLUT_WRITE_EN_MASK = 0x0000000FL, .
MPC_RMU_3DLUT_RAM_SEL = 0x00000010L, .MPC_RMU_3DLUT_30BIT_EN =
0x00000100L, .MPC_RMU_3DLUT_READ_SEL = 0x00030000L, .MPC_RMU_3DLUT_INDEX
= 0x000007FFL, .MPC_RMU_3DLUT_DATA0 = 0x0000FFFFL, .MPC_RMU_3DLUT_DATA1
= 0xFFFF0000L, .MPC_RMU_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .MPC_RMU_SHAPER_LUT_MODE
= 0x00000003L, .MPC_RMU_SHAPER_OFFSET_R = 0x0007FFFFL, .MPC_RMU_SHAPER_OFFSET_G
= 0x0007FFFFL, .MPC_RMU_SHAPER_OFFSET_B = 0x0007FFFFL, .MPC_RMU_SHAPER_SCALE_R
= 0x0000FFFFL, .MPC_RMU_SHAPER_SCALE_G = 0x0000FFFFL, .MPC_RMU_SHAPER_SCALE_B
= 0xFFFF0000L, .MPC_RMU_SHAPER_LUT_INDEX = 0x000000FFL, .MPC_RMU_SHAPER_LUT_DATA
= 0x00FFFFFFL, .MPC_RMU_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L
, .MPC_RMU_SHAPER_LUT_WRITE_SEL = 0x00000010L, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B
= 0x0003FFFFL, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B
= 0x07F00000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL
, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x3FFF0000L, .
MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET =
0x01FF0000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS =
0x70000000L, .MPC_RMU0_MEM_PWR_FORCE = 0x00000003L, .MPC_RMU0_MEM_PWR_DIS
= 0x00000004L, .MPC_RMU0_SHAPER_MEM_PWR_STATE = 0x00000030L,
.MPC_RMU0_3DLUT_MEM_PWR_STATE = 0x000000C0L, .MPC_RMU1_MEM_PWR_FORCE
= 0x00000C00L, .MPC_RMU1_MEM_PWR_DIS = 0x00001000L, .MPC_RMU1_SHAPER_MEM_PWR_STATE
= 0x0000C000L, .MPC_RMU1_3DLUT_MEM_PWR_STATE = 0x00030000L, .
MPC_RMU_SHAPER_MODE_CURRENT = 0x00000300L, .CUR_VUPDATE_LOCK_SET
= 0x00000001L
682};
683
684#define optc_regs(id)[id] = {.OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX
+ mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX
+ mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX
+ mmOTGid_OTG_VREADY_PARAM, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GLOBAL_CONTROL4 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL4, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
+ mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX
+ mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX
+ mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX
+ mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX
+ mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
+ mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX
+ mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX
+ mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
+ mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
+ mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT
= DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX
+ mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX
+ mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX
+ mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX
+ mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLANK_DATA_COLOR = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_DATA_COLOR_BASE_IDX
+ mmOTGid_OTG_BLANK_DATA_COLOR, .OTG_BLANK_DATA_COLOR_EXT = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX
+ mmOTGid_OTG_BLANK_DATA_COLOR_EXT, .OTG_M_CONST_DTO0 = DCN_BASE__INST0_SEGmmOTGid_OTG_M_CONST_DTO0_BASE_IDX
+ mmOTGid_OTG_M_CONST_DTO0, .OTG_M_CONST_DTO1 = DCN_BASE__INST0_SEGmmOTGid_OTG_M_CONST_DTO1_BASE_IDX
+ mmOTGid_OTG_M_CONST_DTO1, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX
+ mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL
= DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT
= DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX
+ mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL
= DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX
+ mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX
+ mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0
+ 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
+ mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX
+ mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX
+ mmOTGid_OTG_DSC_START_POSITION, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL2_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL2, .OTG_DRR_TRIGGER_WINDOW = DCN_BASE__INST0_SEGmmOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX
+ mmOTGid_OTG_DRR_TRIGGER_WINDOW, .OTG_DRR_V_TOTAL_CHANGE = DCN_BASE__INST0_SEGmmOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX
+ mmOTGid_OTG_DRR_V_TOTAL_CHANGE, .OPTC_DATA_FORMAT_CONTROL =
DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
+ mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX
+ mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX
+ mmODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGmmODMid_OPTC_MEMORY_CONFIG_BASE_IDX
+ mmODMid_OPTC_MEMORY_CONFIG, .DWB_SOURCE_SELECT = 0x000034C0
+ 0x1e2a}\
685[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id).OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX
+ mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX
+ mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX
+ mmOTGid_OTG_VREADY_PARAM, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GLOBAL_CONTROL4 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL4, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
+ mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX
+ mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX
+ mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX
+ mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX
+ mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
+ mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX
+ mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX
+ mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
+ mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
+ mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT
= DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX
+ mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX
+ mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX
+ mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX
+ mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLANK_DATA_COLOR = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_DATA_COLOR_BASE_IDX
+ mmOTGid_OTG_BLANK_DATA_COLOR, .OTG_BLANK_DATA_COLOR_EXT = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX
+ mmOTGid_OTG_BLANK_DATA_COLOR_EXT, .OTG_M_CONST_DTO0 = DCN_BASE__INST0_SEGmmOTGid_OTG_M_CONST_DTO0_BASE_IDX
+ mmOTGid_OTG_M_CONST_DTO0, .OTG_M_CONST_DTO1 = DCN_BASE__INST0_SEGmmOTGid_OTG_M_CONST_DTO1_BASE_IDX
+ mmOTGid_OTG_M_CONST_DTO1, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX
+ mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION
= DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL
= DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT
= DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX
+ mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL
= DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX
+ mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX
+ mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL
= DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0
+ 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
+ mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX
+ mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX
+ mmOTGid_OTG_DSC_START_POSITION, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL2_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL2, .OTG_DRR_TRIGGER_WINDOW = DCN_BASE__INST0_SEGmmOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX
+ mmOTGid_OTG_DRR_TRIGGER_WINDOW, .OTG_DRR_V_TOTAL_CHANGE = DCN_BASE__INST0_SEGmmOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX
+ mmOTGid_OTG_DRR_V_TOTAL_CHANGE, .OPTC_DATA_FORMAT_CONTROL =
DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
+ mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX
+ mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX
+ mmODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGmmODMid_OPTC_MEMORY_CONFIG_BASE_IDX
+ mmODMid_OPTC_MEMORY_CONFIG, .DWB_SOURCE_SELECT = 0x000034C0
+ 0x1e2a}
686
687
688static const struct dcn_optc_registers optc_regs[] = {
689 optc_regs(0)[0] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1b87, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1b88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1b89
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1b8b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1b90, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1b91
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1b94, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1b5b, .OTG_H_TOTAL = 0x000034C0 + 0x1b2a, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1b2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1b2c, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1b2d, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1b2e, .OTG_V_TOTAL = 0x000034C0 + 0x1b2f, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1b36, .OTG_V_SYNC_A = 0x000034C0 + 0x1b37, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1b38, .OTG_CONTROL = 0x000034C0
+ 0x1b41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1b54, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1b83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1b53
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1b31, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1b30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1b33, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1b39, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1b3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1b82, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1b4c, .OTG_STATUS = 0x000034C0
+ 0x1b49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1b4a, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1b4b, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1b5e
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1b5f, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1b9c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1b9d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1b86, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1b63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1b62, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1b65
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1b64, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1b67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1b66, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1acf, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1acb, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1aca, .CONTROL = 0x000034C0 + 0x0528, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1b52, .OTG_GSL_CONTROL = 0x000034C0 + 0x1b8c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1b68, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1b6e, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1b6f, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1b6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1b6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1b6c,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1b6d, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1b3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1b91, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1b92, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1b8d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1b8e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1b8f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1b9f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1b69, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1b9a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1b99, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1acc, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1acd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ace
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ad0, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
690 optc_regs(1)[1] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c07, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1c08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c09
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c0b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1c10, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c11
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1c14, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1bdb, .OTG_H_TOTAL = 0x000034C0 + 0x1baa, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1bab, .OTG_H_SYNC_A = 0x000034C0 + 0x1bac, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1bad, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1bae, .OTG_V_TOTAL = 0x000034C0 + 0x1baf, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1bb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1bb7, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1bb8, .OTG_CONTROL = 0x000034C0
+ 0x1bc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1bd4, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1c03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1bd3
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1bb1, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1bb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1bb3, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1bb9, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1bbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c02, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1bcc, .OTG_STATUS = 0x000034C0
+ 0x1bc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1bca, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1bcb, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1bde
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1bdf, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1c1c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1c1d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c06, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1be3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1be2, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1be5
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1be4, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1be7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1be6, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1adf, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1adb, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1ada, .CONTROL = 0x000034C0 + 0x0529, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1bd2, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c0c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1be8, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1bee, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1bef, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1bea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1beb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1bec,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1bed, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1bba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c11, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1c12, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c0d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c0e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1c0f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1c1f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1be9, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1c1a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1c19, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1adc, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1add, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ade
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ae0, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
691 optc_regs(2)[2] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c87, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1c88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c89
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c8b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1c90, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c91
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c92, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1c94, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1c5b, .OTG_H_TOTAL = 0x000034C0 + 0x1c2a, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1c2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1c2c, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1c2d, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1c2e, .OTG_V_TOTAL = 0x000034C0 + 0x1c2f, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1c36, .OTG_V_SYNC_A = 0x000034C0 + 0x1c37, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1c38, .OTG_CONTROL = 0x000034C0
+ 0x1c41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1c54, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1c83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1c53
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1c31, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1c30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1c33, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1c39, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1c3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c82, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1c4c, .OTG_STATUS = 0x000034C0
+ 0x1c49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1c4a, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1c4b, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1c5e
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1c5f, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1c9c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1c9d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c86, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1c63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1c62, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1c65
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1c64, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1c67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1c66, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aef, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1aeb, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1aea, .CONTROL = 0x000034C0 + 0x052a, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1c52, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c8c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1c68, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1c6e, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1c6f, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1c6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1c6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1c6c,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1c6d, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1c3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c91, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1c92, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c8d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c8e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1c8f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1c9f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1c69, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1c9a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1c99, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1aec, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1aed, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1aee
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1af0, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
692 optc_regs(3)[3] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1d07, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1d08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1d09
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1d0b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1d10, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d11
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d12, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1d14, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1cdb, .OTG_H_TOTAL = 0x000034C0 + 0x1caa, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1cab, .OTG_H_SYNC_A = 0x000034C0 + 0x1cac, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1cad, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1cae, .OTG_V_TOTAL = 0x000034C0 + 0x1caf, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1cb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1cb7, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1cb8, .OTG_CONTROL = 0x000034C0
+ 0x1cc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1cd4, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1d03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1cd3
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1cb1, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1cb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1cb3, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1cb9, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1cbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1d02, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1ccc, .OTG_STATUS = 0x000034C0
+ 0x1cc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1cca, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1ccb, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1cde
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1cdf, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1d1c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1d1d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1d06, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1ce3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1ce2, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1ce5
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1ce4, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1ce7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1ce6, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aff, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1afb, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1afa, .CONTROL = 0x000034C0 + 0x052b, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1cd2, .OTG_GSL_CONTROL = 0x000034C0 + 0x1d0c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1ce8, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1cee, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1cef, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1cea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1ceb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1cec,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1ced, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1cba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d11, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1d12, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1d0d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1d0e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1d0f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1d1f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1ce9, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1d1a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1d19, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1afc, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1afd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1afe
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b00, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
693 optc_regs(4)[4] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1d87, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1d88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1d89
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1d8b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1d90, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d91
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d92, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1d94, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1d5b, .OTG_H_TOTAL = 0x000034C0 + 0x1d2a, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1d2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1d2c, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1d2d, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1d2e, .OTG_V_TOTAL = 0x000034C0 + 0x1d2f, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1d36, .OTG_V_SYNC_A = 0x000034C0 + 0x1d37, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1d38, .OTG_CONTROL = 0x000034C0
+ 0x1d41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1d54, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1d83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1d53
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1d31, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1d30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1d33, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1d39, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1d3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1d82, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1d4c, .OTG_STATUS = 0x000034C0
+ 0x1d49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1d4a, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1d4b, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1d5e
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1d5f, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1d9c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1d9d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1d86, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1d63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1d62, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1d65
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1d64, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1d67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1d66, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1b0f, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1b0b, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1b0a, .CONTROL = 0x000034C0 + 0x052c, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1d52, .OTG_GSL_CONTROL = 0x000034C0 + 0x1d8c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1d68, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1d6e, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1d6f, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1d6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1d6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1d6c,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1d6d, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1d3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d91, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1d92, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1d8d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1d8e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1d8f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1d9f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1d69, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1d9a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1d99, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1b0c, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1b0d, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1b0e
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b10, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
694 optc_regs(5)[5] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1e07, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1e08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1e09
, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1e0b, .OTG_GLOBAL_CONTROL0
= 0x000034C0 + 0x1e10, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1e11
, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1e12, .OTG_GLOBAL_CONTROL4
= 0x000034C0 + 0x1e14, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0
+ 0x1ddb, .OTG_H_TOTAL = 0x000034C0 + 0x1daa, .OTG_H_BLANK_START_END
= 0x000034C0 + 0x1dab, .OTG_H_SYNC_A = 0x000034C0 + 0x1dac, .
OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1dad, .OTG_H_TIMING_CNTL =
0x000034C0 + 0x1dae, .OTG_V_TOTAL = 0x000034C0 + 0x1daf, .OTG_V_BLANK_START_END
= 0x000034C0 + 0x1db6, .OTG_V_SYNC_A = 0x000034C0 + 0x1db7, .
OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1db8, .OTG_CONTROL = 0x000034C0
+ 0x1dc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1dd4, .OTG_3D_STRUCTURE_CONTROL
= 0x000034C0 + 0x1e03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1dd3
, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1db1, .OTG_V_TOTAL_MIN = 0x000034C0
+ 0x1db0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1db3, .OTG_TRIGA_CNTL
= 0x000034C0 + 0x1db9, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0
+ 0x1dbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1e02, .
OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1dcc, .OTG_STATUS = 0x000034C0
+ 0x1dc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1dca, .OTG_NOM_VERT_POSITION
= 0x000034C0 + 0x1dcb, .OTG_BLANK_DATA_COLOR = 0x000034C0 + 0x1dde
, .OTG_BLANK_DATA_COLOR_EXT = 0x000034C0 + 0x1ddf, .OTG_M_CONST_DTO0
= 0x000034C0 + 0x1e1c, .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1e1d
, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1e06, .OTG_VERTICAL_INTERRUPT0_CONTROL
= 0x000034C0 + 0x1de3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0
+ 0x1de2, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1de5
, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1de4, .OTG_VERTICAL_INTERRUPT2_CONTROL
= 0x000034C0 + 0x1de7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0
+ 0x1de6, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1b1f, .
OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1b1b, .OPTC_INPUT_GLOBAL_CONTROL
= 0x000034C0 + 0x1b1a, .CONTROL = 0x000034C0 + 0x052d, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1dd2, .OTG_GSL_CONTROL = 0x000034C0 + 0x1e0c
, .OTG_CRC_CNTL = 0x000034C0 + 0x1de8, .OTG_CRC0_DATA_RG = 0x000034C0
+ 0x1dee, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1def, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1dea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1deb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1dec,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1ded, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 +
0x1dba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1e11, .OTG_GLOBAL_CONTROL2
= 0x000034C0 + 0x1e12, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1e0d
, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1e0e, .OTG_VUPDATE_KEEPOUT
= 0x000034C0 + 0x1e0f, .OTG_DSC_START_POSITION = 0x000034C0 +
0x1e1f, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1de9, .OTG_DRR_TRIGGER_WINDOW
= 0x000034C0 + 0x1e1a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 +
0x1e19, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1b1c, .OPTC_BYTES_PER_PIXEL
= 0x000034C0 + 0x1b1d, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1b1e
, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b20, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a}
695};
696
697static const struct dcn_optc_shift optc_shift = {
698 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).VSTARTUP_START = 0x0, .VUPDATE_OFFSET = 0x0, .VUPDATE_WIDTH =
0x10, .VREADY_OFFSET = 0x0, .OTG_MASTER_UPDATE_LOCK = 0x0, .
UPDATE_LOCK_STATUS = 0x8, .MASTER_UPDATE_LOCK_DB_START_X = 0x0
, .MASTER_UPDATE_LOCK_DB_END_X = 0x10, .MASTER_UPDATE_LOCK_DB_EN
= 0x1f, .MASTER_UPDATE_LOCK_DB_START_Y = 0x0, .MASTER_UPDATE_LOCK_DB_END_Y
= 0x10, .OTG_MASTER_UPDATE_LOCK_SEL = 0x19, .DIG_UPDATE_POSITION_X
= 0x0, .DIG_UPDATE_POSITION_Y = 0x10, .OTG_UPDATE_PENDING = 0x0
, .OTG_H_TOTAL = 0x0, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END
= 0x10, .OTG_H_SYNC_A_START = 0x0, .OTG_H_SYNC_A_END = 0x10,
.OTG_H_SYNC_A_POL = 0x0, .OTG_V_TOTAL = 0x0, .OTG_V_BLANK_START
= 0x0, .OTG_V_BLANK_END = 0x10, .OTG_V_SYNC_A_START = 0x0, .
OTG_V_SYNC_A_END = 0x10, .OTG_V_SYNC_A_POL = 0x0, .OTG_V_SYNC_MODE
= 0x8, .OTG_MASTER_EN = 0x0, .OTG_START_POINT_CNTL = 0xc, .OTG_DISABLE_POINT_CNTL
= 0x8, .OTG_FIELD_NUMBER_CNTL = 0xd, .OTG_OUT_MUX = 0x14, .OTG_STEREO_EN
= 0x18, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x0, .OTG_STEREO_SYNC_OUTPUT_POLARITY
= 0xf, .OTG_STEREO_EYE_FLAG_POLARITY = 0x11, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP
= 0x12, .OTG_STEREO_CURRENT_EYE = 0x0, .OTG_3D_STRUCTURE_EN =
0x0, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x8, .OTG_3D_STRUCTURE_STEREO_SEL_OVR
= 0xc, .OTG_V_TOTAL_MAX = 0x0, .OTG_V_TOTAL_MIN = 0x0, .OTG_V_TOTAL_MIN_SEL
= 0x0, .OTG_V_TOTAL_MAX_SEL = 0x1, .OTG_FORCE_LOCK_ON_EVENT =
0x4, .OTG_SET_V_TOTAL_MIN_MASK_EN = 0x7, .OTG_SET_V_TOTAL_MIN_MASK
= 0x10, .OTG_VTOTAL_MID_REPLACING_MIN_EN = 0x3, .OTG_VTOTAL_MID_REPLACING_MAX_EN
= 0x2, .OTG_FORCE_COUNT_NOW_CLEAR = 0x18, .OTG_FORCE_COUNT_NOW_MODE
= 0x0, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x10, .OTG_TRIGA_SOURCE_SELECT
= 0x0, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x5, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL
= 0x10, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x12, .OTG_TRIGA_POLARITY_SELECT
= 0x8, .OTG_TRIGA_FREQUENCY_SELECT = 0x14, .OTG_TRIGA_DELAY =
0x18, .OTG_TRIGA_CLEAR = 0x1f, .OTG_STATIC_SCREEN_EVENT_MASK
= 0x0, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x10, .OTG_FRAME_COUNT
= 0x0, .OTG_V_BLANK = 0x0, .OTG_V_ACTIVE_DISP = 0x1, .OTG_HORZ_COUNT
= 0x10, .OTG_VERT_COUNT = 0x0, .OTG_VERT_COUNT_NOM = 0x0, .OTG_BLANK_DATA_COLOR_BLUE_CB
= 0x0, .OTG_BLANK_DATA_COLOR_GREEN_Y = 0xa, .OTG_BLANK_DATA_COLOR_RED_CR
= 0x14, .OTG_BLANK_DATA_COLOR_BLUE_CB_EXT = 0x0, .OTG_BLANK_DATA_COLOR_GREEN_Y_EXT
= 0x8, .OTG_BLANK_DATA_COLOR_RED_CR_EXT = 0x10, .OTG_M_CONST_DTO_PHASE
= 0x0, .OTG_M_CONST_DTO_MODULO = 0x0, .OTG_BUSY = 0x10, .OTG_CLOCK_EN
= 0x0, .OTG_CLOCK_ON = 0x8, .OTG_CLOCK_GATE_DIS = 0x1, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE
= 0x8, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT0_LINE_END
= 0x10, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT1_LINE_START
= 0x0, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT2_LINE_START
= 0x0, .OPTC_INPUT_CLK_EN = 0x1, .OPTC_INPUT_CLK_ON = 0x2, .
OPTC_INPUT_CLK_GATE_DIS = 0x0, .OPTC_UNDERFLOW_OCCURRED_STATUS
= 0xa, .OPTC_UNDERFLOW_CLEAR = 0xc, .VTG0_ENABLE = 0x1f, .VTG0_FP2
= 0x0, .VTG0_VCOUNT_INIT = 0x10, .OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED
= 0x0, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x8, .OTG_AUTO_FORCE_VSYNC_MODE
= 0x10, .OTG_GSL0_EN = 0x0, .OTG_GSL1_EN = 0x1, .OTG_GSL2_EN
= 0x2, .OTG_GSL_MASTER_EN = 0x3, .OTG_GSL_FORCE_DELAY = 0x10
, .OTG_GSL_CHECK_ALL_FIELDS = 0x1c, .OTG_CRC_CONT_EN = 0x4, .
OTG_CRC0_SELECT = 0x14, .OTG_CRC_EN = 0x0, .CRC0_R_CR = 0x0, .
CRC0_G_Y = 0x10, .CRC0_B_CB = 0x0, .OTG_CRC0_WINDOWA_X_START =
0x0, .OTG_CRC0_WINDOWA_X_END = 0x10, .OTG_CRC0_WINDOWA_Y_START
= 0x0, .OTG_CRC0_WINDOWA_Y_END = 0x10, .OTG_CRC0_WINDOWB_X_START
= 0x0, .OTG_CRC0_WINDOWB_X_END = 0x10, .OTG_CRC0_WINDOWB_Y_START
= 0x0, .OTG_CRC0_WINDOWB_Y_END = 0x10, .OTG_TRIGA_MANUAL_TRIG
= 0x0, .GSL0_READY_SOURCE_SEL = 0x0, .GSL1_READY_SOURCE_SEL =
0x4, .GSL2_READY_SOURCE_SEL = 0x8, .MANUAL_FLOW_CONTROL_SEL =
0x10, .GLOBAL_UPDATE_LOCK_EN = 0xa, .OTG_GSL_WINDOW_START_X =
0x0, .OTG_GSL_WINDOW_END_X = 0x10, .OTG_GSL_WINDOW_START_Y =
0x0, .OTG_GSL_WINDOW_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN
= 0x1f, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_GSL_MASTER_MODE
= 0x4, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x1f, .OTG_DSC_START_POSITION_X
= 0x0, .OTG_DSC_START_POSITION_LINE_NUM = 0x10, .OTG_CRC_DSC_MODE
= 0x0, .OTG_CRC_DATA_STREAM_COMBINE_MODE = 0x1, .OTG_CRC_DATA_STREAM_SPLIT_MODE
= 0x4, .OTG_CRC_DATA_FORMAT = 0x8, .OPTC_SEG0_SRC_SEL = 0x8,
.OPTC_SEG1_SRC_SEL = 0xc, .OPTC_SEG2_SRC_SEL = 0x10, .OPTC_SEG3_SRC_SEL
= 0x14, .OPTC_NUM_OF_INPUT_SEGMENT = 0x0, .OPTC_MEM_SEL = 0x0
, .OPTC_DATA_FORMAT = 0x0, .OPTC_DSC_MODE = 0x4, .OPTC_DSC_BYTES_PER_PIXEL
= 0x0, .OPTC_DSC_SLICE_WIDTH = 0x10, .OPTC_SEGMENT_WIDTH = 0x0
, .OPTC_DWB0_SOURCE_SELECT = 0x0, .OPTC_DWB1_SOURCE_SELECT = 0x3
, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x0, .OTG_DRR_TRIGGER_WINDOW_END_X
= 0x10, .OTG_DRR_V_TOTAL_CHANGE_LIMIT = 0x0, .OTG_H_TIMING_DIV_MODE
= 0x0, .OTG_DRR_TIMING_DBUF_UPDATE_MODE = 0x18
699};
700
701static const struct dcn_optc_mask optc_mask = {
702 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK).VSTARTUP_START = 0x000003FFL, .VUPDATE_OFFSET = 0x0000FFFFL,
.VUPDATE_WIDTH = 0x03FF0000L, .VREADY_OFFSET = 0x0000FFFFL, .
OTG_MASTER_UPDATE_LOCK = 0x00000001L, .UPDATE_LOCK_STATUS = 0x00000100L
, .MASTER_UPDATE_LOCK_DB_START_X = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_X
= 0x7FFF0000L, .MASTER_UPDATE_LOCK_DB_EN = 0x80000000L, .MASTER_UPDATE_LOCK_DB_START_Y
= 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_Y = 0x7FFF0000L, .
OTG_MASTER_UPDATE_LOCK_SEL = 0x0E000000L, .DIG_UPDATE_POSITION_X
= 0x00007FFFL, .DIG_UPDATE_POSITION_Y = 0x7FFF0000L, .OTG_UPDATE_PENDING
= 0x00000001L, .OTG_H_TOTAL = 0x00007FFFL, .OTG_H_BLANK_START
= 0x00007FFFL, .OTG_H_BLANK_END = 0x7FFF0000L, .OTG_H_SYNC_A_START
= 0x00007FFFL, .OTG_H_SYNC_A_END = 0x7FFF0000L, .OTG_H_SYNC_A_POL
= 0x00000001L, .OTG_V_TOTAL = 0x00007FFFL, .OTG_V_BLANK_START
= 0x00007FFFL, .OTG_V_BLANK_END = 0x7FFF0000L, .OTG_V_SYNC_A_START
= 0x00007FFFL, .OTG_V_SYNC_A_END = 0x7FFF0000L, .OTG_V_SYNC_A_POL
= 0x00000001L, .OTG_V_SYNC_MODE = 0x00000100L, .OTG_MASTER_EN
= 0x00000001L, .OTG_START_POINT_CNTL = 0x00001000L, .OTG_DISABLE_POINT_CNTL
= 0x00000300L, .OTG_FIELD_NUMBER_CNTL = 0x00002000L, .OTG_OUT_MUX
= 0x00100000L, .OTG_STEREO_EN = 0x01000000L, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM
= 0x00007FFFL, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0x00008000L
, .OTG_STEREO_EYE_FLAG_POLARITY = 0x00020000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP
= 0x00040000L, .OTG_STEREO_CURRENT_EYE = 0x00000001L, .OTG_3D_STRUCTURE_EN
= 0x00000001L, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x00000300L
, .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0x00001000L, .OTG_V_TOTAL_MAX
= 0x00007FFFL, .OTG_V_TOTAL_MIN = 0x00007FFFL, .OTG_V_TOTAL_MIN_SEL
= 0x00000001L, .OTG_V_TOTAL_MAX_SEL = 0x00000002L, .OTG_FORCE_LOCK_ON_EVENT
= 0x00000010L, .OTG_SET_V_TOTAL_MIN_MASK_EN = 0x00000080L, .
OTG_SET_V_TOTAL_MIN_MASK = 0xFFFF0000L, .OTG_VTOTAL_MID_REPLACING_MIN_EN
= 0x00000008L, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x00000004L
, .OTG_FORCE_COUNT_NOW_CLEAR = 0x01000000L, .OTG_FORCE_COUNT_NOW_MODE
= 0x00000003L, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x00010000L, .
OTG_TRIGA_SOURCE_SELECT = 0x0000001FL, .OTG_TRIGA_SOURCE_PIPE_SELECT
= 0x000000E0L, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x00030000L
, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x000C0000L, .OTG_TRIGA_POLARITY_SELECT
= 0x00000700L, .OTG_TRIGA_FREQUENCY_SELECT = 0x00300000L, .OTG_TRIGA_DELAY
= 0x1F000000L, .OTG_TRIGA_CLEAR = 0x80000000L, .OTG_STATIC_SCREEN_EVENT_MASK
= 0x0000FFFFL, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x00FF0000L,
.OTG_FRAME_COUNT = 0x00FFFFFFL, .OTG_V_BLANK = 0x00000001L, .
OTG_V_ACTIVE_DISP = 0x00000002L, .OTG_HORZ_COUNT = 0x7FFF0000L
, .OTG_VERT_COUNT = 0x00007FFFL, .OTG_VERT_COUNT_NOM = 0x00007FFFL
, .OTG_BLANK_DATA_COLOR_BLUE_CB = 0x000003FFL, .OTG_BLANK_DATA_COLOR_GREEN_Y
= 0x000FFC00L, .OTG_BLANK_DATA_COLOR_RED_CR = 0x3FF00000L, .
OTG_BLANK_DATA_COLOR_BLUE_CB_EXT = 0x0000003FL, .OTG_BLANK_DATA_COLOR_GREEN_Y_EXT
= 0x00003F00L, .OTG_BLANK_DATA_COLOR_RED_CR_EXT = 0x003F0000L
, .OTG_M_CONST_DTO_PHASE = 0xFFFFFFFFL, .OTG_M_CONST_DTO_MODULO
= 0xFFFFFFFFL, .OTG_BUSY = 0x00010000L, .OTG_CLOCK_EN = 0x00000001L
, .OTG_CLOCK_ON = 0x00000100L, .OTG_CLOCK_GATE_DIS = 0x00000002L
, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT0_LINE_START
= 0x00007FFFL, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x7FFF0000L
, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT1_LINE_START
= 0x00007FFFL, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x00000100L
, .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x00007FFFL, .OPTC_INPUT_CLK_EN
= 0x00000002L, .OPTC_INPUT_CLK_ON = 0x00000004L, .OPTC_INPUT_CLK_GATE_DIS
= 0x00000001L, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0x00000400L
, .OPTC_UNDERFLOW_CLEAR = 0x00001000L, .VTG0_ENABLE = 0x80000000L
, .VTG0_FP2 = 0x00007FFFL, .VTG0_VCOUNT_INIT = 0x7FFF0000L, .
OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x00000001L, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR
= 0x00000100L, .OTG_AUTO_FORCE_VSYNC_MODE = 0x00030000L, .OTG_GSL0_EN
= 0x00000001L, .OTG_GSL1_EN = 0x00000002L, .OTG_GSL2_EN = 0x00000004L
, .OTG_GSL_MASTER_EN = 0x00000008L, .OTG_GSL_FORCE_DELAY = 0x001F0000L
, .OTG_GSL_CHECK_ALL_FIELDS = 0x10000000L, .OTG_CRC_CONT_EN =
0x00000010L, .OTG_CRC0_SELECT = 0x00700000L, .OTG_CRC_EN = 0x00000001L
, .CRC0_R_CR = 0x0000FFFFL, .CRC0_G_Y = 0xFFFF0000L, .CRC0_B_CB
= 0x0000FFFFL, .OTG_CRC0_WINDOWA_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_X_END
= 0x7FFF0000L, .OTG_CRC0_WINDOWA_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_Y_END
= 0x7FFF0000L, .OTG_CRC0_WINDOWB_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_X_END
= 0x7FFF0000L, .OTG_CRC0_WINDOWB_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_Y_END
= 0x7FFF0000L, .OTG_TRIGA_MANUAL_TRIG = 0x00000001L, .GSL0_READY_SOURCE_SEL
= 0x00000007L, .GSL1_READY_SOURCE_SEL = 0x00000070L, .GSL2_READY_SOURCE_SEL
= 0x00000700L, .MANUAL_FLOW_CONTROL_SEL = 0x00070000L, .GLOBAL_UPDATE_LOCK_EN
= 0x00000400L, .OTG_GSL_WINDOW_START_X = 0x00007FFFL, .OTG_GSL_WINDOW_END_X
= 0x7FFF0000L, .OTG_GSL_WINDOW_START_Y = 0x00007FFFL, .OTG_GSL_WINDOW_END_Y
= 0x7FFF0000L, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L
, .OTG_GSL_MASTER_MODE = 0x00000030L, .OTG_MASTER_UPDATE_LOCK_GSL_EN
= 0x80000000L, .OTG_DSC_START_POSITION_X = 0x00007FFFL, .OTG_DSC_START_POSITION_LINE_NUM
= 0x03FF0000L, .OTG_CRC_DSC_MODE = 0x00000001L, .OTG_CRC_DATA_STREAM_COMBINE_MODE
= 0x00000002L, .OTG_CRC_DATA_STREAM_SPLIT_MODE = 0x00000030L
, .OTG_CRC_DATA_FORMAT = 0x00000300L, .OPTC_SEG0_SRC_SEL = 0x00000F00L
, .OPTC_SEG1_SRC_SEL = 0x0000F000L, .OPTC_SEG2_SRC_SEL = 0x000F0000L
, .OPTC_SEG3_SRC_SEL = 0x00F00000L, .OPTC_NUM_OF_INPUT_SEGMENT
= 0x00000003L, .OPTC_MEM_SEL = 0x0000FFFFL, .OPTC_DATA_FORMAT
= 0x00000003L, .OPTC_DSC_MODE = 0x00000030L, .OPTC_DSC_BYTES_PER_PIXEL
= 0x7FFFFFFFL, .OPTC_DSC_SLICE_WIDTH = 0x1FFF0000L, .OPTC_SEGMENT_WIDTH
= 0x00001FFFL, .OPTC_DWB0_SOURCE_SELECT = 0x00000007L, .OPTC_DWB1_SOURCE_SELECT
= 0x00000038L, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x00007FFFL
, .OTG_DRR_TRIGGER_WINDOW_END_X = 0x7FFF0000L, .OTG_DRR_V_TOTAL_CHANGE_LIMIT
= 0x00007FFFL, .OTG_H_TIMING_DIV_MODE = 0x00000003L, .OTG_DRR_TIMING_DBUF_UPDATE_MODE
= 0x03000000L
703};
704
705#define hubp_regs(id)[id] = { .DCHUBP_CNTL = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX
+ mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C =
DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .
DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_CONTROL, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX
+ mmHUBPRETid_HUBPRET_CONTROL, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX
+ mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C
= DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX
+ mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX
+ mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX
+ mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX
+ mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX
+ mmHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR
= DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX
+ mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX
+ mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS
= DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS
, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX
+ mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VMID_SETTINGS_0_BASE_IDX
+ mmHUBPREQid_VMID_SETTINGS_0, .FLIP_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_3, .FLIP_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_4, .FLIP_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_5, .FLIP_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_6, .VBLANK_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_5, .VBLANK_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_6, .DCN_DMDATA_VM_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_DMDATA_VM_CNTL}\
706[id] = {\
707 HUBP_REG_LIST_DCN30(id).DCHUBP_CNTL = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX
+ mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C =
DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C
= DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .
DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL
= DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_CONTROL, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX
+ mmHUBPRETid_HUBPRET_CONTROL, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX
+ mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C
= DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX
+ mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX
+ mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX
+ mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX
+ mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX
+ mmHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR
= DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX
+ mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX
+ mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS
= DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS
, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX
+ mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VMID_SETTINGS_0_BASE_IDX
+ mmHUBPREQid_VMID_SETTINGS_0, .FLIP_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_3, .FLIP_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_4, .FLIP_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_5, .FLIP_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_6, .VBLANK_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_5, .VBLANK_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_6, .DCN_DMDATA_VM_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_DMDATA_VM_CNTL\
708}
709
710static const struct dcn_hubp2_registers hubp_regs[] = {
711 hubp_regs(0)[0] = { .DCHUBP_CNTL = 0x000034C0 + 0x05f3, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x05f6, .HUBPREQ_DEBUG = 0x000034C0 + 0x05f7,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x05e6, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x05e7, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0607
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0608, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x05e5, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x061b
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ea, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x05e9, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x05ee, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x05ed, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05ec, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x05eb, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x05f0, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x05ef
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060b,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x060a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x060f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x060e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0613, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x0612, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0617, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x0616, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x060d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x060c
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0611
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0610, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0615
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0614
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x0619, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x0618, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0621, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x0622, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x0623, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0624, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0625, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0626, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0627, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0628, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x061a, .HUBPRET_CONTROL
= 0x000034C0 + 0x066c, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0629
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x05f1, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x05f2, .BLANK_OFFSET_0 = 0x000034C0 + 0x0644
, .BLANK_OFFSET_1 = 0x000034C0 + 0x0645, .DST_DIMENSIONS = 0x000034C0
+ 0x0646, .DST_AFTER_SCALER = 0x000034C0 + 0x0647, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x064a, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x065d
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x064b, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x064d, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0656
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0657, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x065a, .PER_LINE_DELIVERY = 0x000034C0 + 0x065b
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x064c, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x064e, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0658
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0659, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x062a, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x062b, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x062c, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x062d
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x062e, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x062f, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0630
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0631, .HUBP_CLK_CNTL =
0x000034C0 + 0x05f4, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0652
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x0653, .NOM_PARAMETERS_2 =
0x000034C0 + 0x0654, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0655
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0643, .PREFETCH_SETTINGS
= 0x000034C0 + 0x0648, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0649
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0635, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x0636, .CURSOR_SETTINGS = 0x000034C0 + 0x065c
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x067a, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x0679, .CURSOR_SIZE = 0x000034C0 + 0x067b, .
CURSOR_CONTROL = 0x000034C0 + 0x0678, .CURSOR_POSITION = 0x000034C0
+ 0x067c, .CURSOR_HOT_SPOT = 0x000034C0 + 0x067d, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x067f, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0682
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0683, .DMDATA_CNTL = 0x000034C0
+ 0x0684, .DMDATA_SW_CNTL = 0x000034C0 + 0x0687, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0685, .DMDATA_SW_DATA = 0x000034C0 + 0x0688
, .DMDATA_STATUS = 0x000034C0 + 0x0686, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x064f, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0650, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x0651, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0632
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0633, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x061c, .VMID_SETTINGS_0 = 0x000034C0 + 0x0609
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x0665, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x0666, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x0667
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0668, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x0663, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x0664
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x0634},
712 hubp_regs(1)[1] = { .DCHUBP_CNTL = 0x000034C0 + 0x06cf, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x06d2, .HUBPREQ_DEBUG = 0x000034C0 + 0x06d3,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x06c2, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x06c3, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x06e3
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x06e4, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x06c1, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x06f7
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x06c6, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x06c5, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x06ca, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x06c9, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06c8, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x06c7, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x06cc, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x06cb
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06e7,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x06e6, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x06eb, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x06ea, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x06ef, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x06ee, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x06f3, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x06f2, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x06e9, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06e8
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06ed
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06ec, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f1
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f0
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x06f5, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x06f4, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x06fd, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x06fe, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x06ff, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0700, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0701, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0702, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0703, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0704, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x06f6, .HUBPRET_CONTROL
= 0x000034C0 + 0x0748, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0705
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x06cd, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x06ce, .BLANK_OFFSET_0 = 0x000034C0 + 0x0720
, .BLANK_OFFSET_1 = 0x000034C0 + 0x0721, .DST_DIMENSIONS = 0x000034C0
+ 0x0722, .DST_AFTER_SCALER = 0x000034C0 + 0x0723, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x0726, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0739
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0727, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x0729, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0732
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0733, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x0736, .PER_LINE_DELIVERY = 0x000034C0 + 0x0737
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0728, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x072a, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0734
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0735, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x0706, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x0707, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x0708, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0709
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x070a, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x070b, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x070c
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x070d, .HUBP_CLK_CNTL =
0x000034C0 + 0x06d0, .NOM_PARAMETERS_0 = 0x000034C0 + 0x072e
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x072f, .NOM_PARAMETERS_2 =
0x000034C0 + 0x0730, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0731
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x071f, .PREFETCH_SETTINGS
= 0x000034C0 + 0x0724, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0725
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0711, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x0712, .CURSOR_SETTINGS = 0x000034C0 + 0x0738
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0756, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x0755, .CURSOR_SIZE = 0x000034C0 + 0x0757, .
CURSOR_CONTROL = 0x000034C0 + 0x0754, .CURSOR_POSITION = 0x000034C0
+ 0x0758, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0759, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x075b, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x075e
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x075f, .DMDATA_CNTL = 0x000034C0
+ 0x0760, .DMDATA_SW_CNTL = 0x000034C0 + 0x0763, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0761, .DMDATA_SW_DATA = 0x000034C0 + 0x0764
, .DMDATA_STATUS = 0x000034C0 + 0x0762, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x072b, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x072c, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x072d, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x070e
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x070f, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x06f8, .VMID_SETTINGS_0 = 0x000034C0 + 0x06e5
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x0741, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x0742, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x0743
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0744, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x073f, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x0740
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x0710},
713 hubp_regs(2)[2] = { .DCHUBP_CNTL = 0x000034C0 + 0x07ab, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x07ae, .HUBPREQ_DEBUG = 0x000034C0 + 0x07af,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x079e, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x079f, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x07bf
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x07c0, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x079d, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x07d3
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a2, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x07a1, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x07a6, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x07a5, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a4, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x07a3, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x07a8, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x07a7
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c3,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c2, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x07c7, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x07c6, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x07cb, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x07ca, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x07cf, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x07ce, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x07c5, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c4
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c9
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c8, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07cd
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07cc
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x07d1, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x07d0, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x07d9, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x07da, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x07db, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x07dc, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x07dd, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x07de, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x07df, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x07e0, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x07d2, .HUBPRET_CONTROL
= 0x000034C0 + 0x0824, .DCN_EXPANSION_MODE = 0x000034C0 + 0x07e1
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x07a9, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x07aa, .BLANK_OFFSET_0 = 0x000034C0 + 0x07fc
, .BLANK_OFFSET_1 = 0x000034C0 + 0x07fd, .DST_DIMENSIONS = 0x000034C0
+ 0x07fe, .DST_AFTER_SCALER = 0x000034C0 + 0x07ff, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x0802, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0815
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0803, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x0805, .NOM_PARAMETERS_4 = 0x000034C0 + 0x080e
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x080f, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x0812, .PER_LINE_DELIVERY = 0x000034C0 + 0x0813
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0804, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x0806, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0810
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0811, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x07e2, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x07e3, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x07e4, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x07e5
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x07e6, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x07e7, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x07e8
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x07e9, .HUBP_CLK_CNTL =
0x000034C0 + 0x07ac, .NOM_PARAMETERS_0 = 0x000034C0 + 0x080a
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x080b, .NOM_PARAMETERS_2 =
0x000034C0 + 0x080c, .NOM_PARAMETERS_3 = 0x000034C0 + 0x080d
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x07fb, .PREFETCH_SETTINGS
= 0x000034C0 + 0x0800, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0801
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x07ed, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x07ee, .CURSOR_SETTINGS = 0x000034C0 + 0x0814
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0832, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x0831, .CURSOR_SIZE = 0x000034C0 + 0x0833, .
CURSOR_CONTROL = 0x000034C0 + 0x0830, .CURSOR_POSITION = 0x000034C0
+ 0x0834, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0835, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x0837, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x083a
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x083b, .DMDATA_CNTL = 0x000034C0
+ 0x083c, .DMDATA_SW_CNTL = 0x000034C0 + 0x083f, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x083d, .DMDATA_SW_DATA = 0x000034C0 + 0x0840
, .DMDATA_STATUS = 0x000034C0 + 0x083e, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x0807, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0808, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x0809, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x07ea
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x07eb, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x07d4, .VMID_SETTINGS_0 = 0x000034C0 + 0x07c1
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x081d, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x081e, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x081f
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0820, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x081b, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x081c
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x07ec},
714 hubp_regs(3)[3] = { .DCHUBP_CNTL = 0x000034C0 + 0x0887, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x088a, .HUBPREQ_DEBUG = 0x000034C0 + 0x088b,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x087a, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x087b, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x089b
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x089c, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x0879, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x08af
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x087e, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x087d, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x0882, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0881, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0880, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x087f, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x0884, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0883
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x089f,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x089e, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x08a3, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x08a2, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x08a7, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x08a6, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x08ab, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x08aa, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x08a1, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a0
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a5
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a4, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a9
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a8
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x08ad, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x08ac, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x08b5, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x08b6, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x08b7, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x08b8, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x08b9, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x08ba, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x08bb, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x08bc, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x08ae, .HUBPRET_CONTROL
= 0x000034C0 + 0x0900, .DCN_EXPANSION_MODE = 0x000034C0 + 0x08bd
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0885, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x0886, .BLANK_OFFSET_0 = 0x000034C0 + 0x08d8
, .BLANK_OFFSET_1 = 0x000034C0 + 0x08d9, .DST_DIMENSIONS = 0x000034C0
+ 0x08da, .DST_AFTER_SCALER = 0x000034C0 + 0x08db, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x08de, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x08f1
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x08df, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x08e1, .NOM_PARAMETERS_4 = 0x000034C0 + 0x08ea
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x08eb, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x08ee, .PER_LINE_DELIVERY = 0x000034C0 + 0x08ef
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x08e0, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x08e2, .NOM_PARAMETERS_6 = 0x000034C0 + 0x08ec
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x08ed, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x08be, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x08bf, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x08c0, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x08c1
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x08c2, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x08c3, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x08c4
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x08c5, .HUBP_CLK_CNTL =
0x000034C0 + 0x0888, .NOM_PARAMETERS_0 = 0x000034C0 + 0x08e6
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x08e7, .NOM_PARAMETERS_2 =
0x000034C0 + 0x08e8, .NOM_PARAMETERS_3 = 0x000034C0 + 0x08e9
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x08d7, .PREFETCH_SETTINGS
= 0x000034C0 + 0x08dc, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x08dd
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x08c9, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x08ca, .CURSOR_SETTINGS = 0x000034C0 + 0x08f0
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x090e, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x090d, .CURSOR_SIZE = 0x000034C0 + 0x090f, .
CURSOR_CONTROL = 0x000034C0 + 0x090c, .CURSOR_POSITION = 0x000034C0
+ 0x0910, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0911, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x0913, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0916
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0917, .DMDATA_CNTL = 0x000034C0
+ 0x0918, .DMDATA_SW_CNTL = 0x000034C0 + 0x091b, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0919, .DMDATA_SW_DATA = 0x000034C0 + 0x091c
, .DMDATA_STATUS = 0x000034C0 + 0x091a, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x08e3, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x08e4, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x08e5, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x08c6
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x08c7, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x08b0, .VMID_SETTINGS_0 = 0x000034C0 + 0x089d
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x08f9, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x08fa, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x08fb
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x08fc, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x08f7, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x08f8
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x08c8},
715 hubp_regs(4)[4] = { .DCHUBP_CNTL = 0x000034C0 + 0x0963, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x0966, .HUBPREQ_DEBUG = 0x000034C0 + 0x0967,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x0956, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x0957, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0977
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0978, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x0955, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x098b
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x095a, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x0959, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x095e, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x095d, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x095c, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x095b, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x0960, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x095f
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x097b,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x097a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x097f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x097e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0983, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x0982, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0987, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x0986, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x097d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x097c
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0981
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0980, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0985
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0984
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x0989, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x0988, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0991, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x0992, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x0993, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0994, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0995, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0996, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0997, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0998, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x098a, .HUBPRET_CONTROL
= 0x000034C0 + 0x09dc, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0999
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0961, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x0962, .BLANK_OFFSET_0 = 0x000034C0 + 0x09b4
, .BLANK_OFFSET_1 = 0x000034C0 + 0x09b5, .DST_DIMENSIONS = 0x000034C0
+ 0x09b6, .DST_AFTER_SCALER = 0x000034C0 + 0x09b7, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x09ba, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x09cd
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x09bb, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x09bd, .NOM_PARAMETERS_4 = 0x000034C0 + 0x09c6
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x09c7, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x09ca, .PER_LINE_DELIVERY = 0x000034C0 + 0x09cb
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x09bc, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x09be, .NOM_PARAMETERS_6 = 0x000034C0 + 0x09c8
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x09c9, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x099a, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x099b, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x099c, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x099d
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x099e, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x099f, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x09a0
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x09a1, .HUBP_CLK_CNTL =
0x000034C0 + 0x0964, .NOM_PARAMETERS_0 = 0x000034C0 + 0x09c2
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x09c3, .NOM_PARAMETERS_2 =
0x000034C0 + 0x09c4, .NOM_PARAMETERS_3 = 0x000034C0 + 0x09c5
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x09b3, .PREFETCH_SETTINGS
= 0x000034C0 + 0x09b8, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x09b9
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x09a5, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x09a6, .CURSOR_SETTINGS = 0x000034C0 + 0x09cc
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x09ea, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x09e9, .CURSOR_SIZE = 0x000034C0 + 0x09eb, .
CURSOR_CONTROL = 0x000034C0 + 0x09e8, .CURSOR_POSITION = 0x000034C0
+ 0x09ec, .CURSOR_HOT_SPOT = 0x000034C0 + 0x09ed, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x09ef, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x09f2
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x09f3, .DMDATA_CNTL = 0x000034C0
+ 0x09f4, .DMDATA_SW_CNTL = 0x000034C0 + 0x09f7, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x09f5, .DMDATA_SW_DATA = 0x000034C0 + 0x09f8
, .DMDATA_STATUS = 0x000034C0 + 0x09f6, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x09bf, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x09c0, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x09c1, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x09a2
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x09a3, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x098c, .VMID_SETTINGS_0 = 0x000034C0 + 0x0979
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x09d5, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x09d6, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x09d7
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x09d8, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x09d3, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x09d4
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x09a4},
716 hubp_regs(5)[5] = { .DCHUBP_CNTL = 0x000034C0 + 0x0a3f, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x0a42, .HUBPREQ_DEBUG = 0x000034C0 + 0x0a43,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x0a32, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x0a33, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0a53
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0a54, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x0a31, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x0a67
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x0a36, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x0a35, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x0a3a, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0a39, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0a38, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x0a37, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x0a3c, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0a3b
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0a57,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x0a56, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x0a5b, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x0a5a, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0a5f, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x0a5e, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0a63, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x0a62, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x0a59, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a58
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a5d
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a5c, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a61
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a60
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x0a65, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x0a64, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0a6d, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x0a6e, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x0a6f, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0a70, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0a71, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0a72, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0a73, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0a74, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x0a66, .HUBPRET_CONTROL
= 0x000034C0 + 0x0ab8, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0a75
, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0a3d, .DCHUBP_REQ_SIZE_CONFIG_C
= 0x000034C0 + 0x0a3e, .BLANK_OFFSET_0 = 0x000034C0 + 0x0a90
, .BLANK_OFFSET_1 = 0x000034C0 + 0x0a91, .DST_DIMENSIONS = 0x000034C0
+ 0x0a92, .DST_AFTER_SCALER = 0x000034C0 + 0x0a93, .VBLANK_PARAMETERS_0
= 0x000034C0 + 0x0a96, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0aa9
, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0a97, .VBLANK_PARAMETERS_3
= 0x000034C0 + 0x0a99, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0aa2
, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0aa3, .PER_LINE_DELIVERY_PRE
= 0x000034C0 + 0x0aa6, .PER_LINE_DELIVERY = 0x000034C0 + 0x0aa7
, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0a98, .VBLANK_PARAMETERS_4
= 0x000034C0 + 0x0a9a, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0aa4
, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0aa5, .DCN_TTU_QOS_WM = 0x000034C0
+ 0x0a76, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x0a77, .DCN_SURF0_TTU_CNTL0
= 0x000034C0 + 0x0a78, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0a79
, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x0a7a, .DCN_SURF1_TTU_CNTL1
= 0x000034C0 + 0x0a7b, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0a7c
, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0a7d, .HUBP_CLK_CNTL =
0x000034C0 + 0x0a40, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0a9e
, .NOM_PARAMETERS_1 = 0x000034C0 + 0x0a9f, .NOM_PARAMETERS_2 =
0x000034C0 + 0x0aa0, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0aa1
, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0a8f, .PREFETCH_SETTINGS
= 0x000034C0 + 0x0a94, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0a95
, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0a81, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x000034C0 + 0x0a82, .CURSOR_SETTINGS = 0x000034C0 + 0x0aa8
, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0ac6, .CURSOR_SURFACE_ADDRESS
= 0x000034C0 + 0x0ac5, .CURSOR_SIZE = 0x000034C0 + 0x0ac7, .
CURSOR_CONTROL = 0x000034C0 + 0x0ac4, .CURSOR_POSITION = 0x000034C0
+ 0x0ac8, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0ac9, .CURSOR_DST_OFFSET
= 0x000034C0 + 0x0acb, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0ace
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0acf, .DMDATA_CNTL = 0x000034C0
+ 0x0ad0, .DMDATA_SW_CNTL = 0x000034C0 + 0x0ad3, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0ad1, .DMDATA_SW_DATA = 0x000034C0 + 0x0ad4
, .DMDATA_STATUS = 0x000034C0 + 0x0ad2, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x0a9b, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0a9c, .FLIP_PARAMETERS_2
= 0x000034C0 + 0x0a9d, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0a7e
, .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0a7f, .DCSURF_FLIP_CONTROL2
= 0x000034C0 + 0x0a68, .VMID_SETTINGS_0 = 0x000034C0 + 0x0a55
, .FLIP_PARAMETERS_3 = 0x000034C0 + 0x0ab1, .FLIP_PARAMETERS_4
= 0x000034C0 + 0x0ab2, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x0ab3
, .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0ab4, .VBLANK_PARAMETERS_5
= 0x000034C0 + 0x0aaf, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x0ab0
, .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x0a80}
717};
718
719static const struct dcn_hubp2_shift hubp_shift = {
720 HUBP_MASK_SH_LIST_DCN30(__SHIFT).REFCYC_PER_VM_DMDATA = 0x0, .DMDATA_VM_FAULT_STATUS = 0x10, .
DMDATA_VM_FAULT_STATUS_CLEAR = 0x14, .DMDATA_VM_UNDERFLOW_STATUS
= 0x18, .DMDATA_VM_LATE_STATUS = 0x19, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR
= 0x1a, .DMDATA_VM_DONE = 0x1f, .HUBP_BLANK_EN = 0x0, .HUBP_TTU_DISABLE
= 0xc, .HUBP_UNDERFLOW_STATUS = 0x1c, .HUBP_UNDERFLOW_CLEAR =
0x1f, .HUBP_NO_OUTSTANDING_REQ = 0x1, .HUBP_VTG_SEL = 0x4, .
HUBP_DISABLE = 0x2, .NUM_PIPES = 0x0, .PIPE_INTERLEAVE = 0x6,
.MAX_COMPRESSED_FRAGS = 0xc, .NUM_PKRS = 0x10, .SW_MODE = 0x0
, .META_LINEAR = 0x9, .PIPE_ALIGNED = 0xb, .PITCH = 0x0, .META_PITCH
= 0x10, .PITCH_C = 0x0, .META_PITCH_C = 0x10, .SURFACE_PIXEL_FORMAT
= 0x0, .SURFACE_FLIP_TYPE = 0x1, .SURFACE_FLIP_MODE_FOR_STEREOSYNC
= 0xc, .SURFACE_FLIP_IN_STEREOSYNC = 0x10, .SURFACE_FLIP_PENDING
= 0x8, .SURFACE_UPDATE_LOCK = 0x0, .PRI_VIEWPORT_WIDTH = 0x0
, .PRI_VIEWPORT_HEIGHT = 0x10, .PRI_VIEWPORT_X_START = 0x0, .
PRI_VIEWPORT_Y_START = 0x10, .SEC_VIEWPORT_WIDTH = 0x0, .SEC_VIEWPORT_HEIGHT
= 0x10, .SEC_VIEWPORT_X_START = 0x0, .SEC_VIEWPORT_Y_START =
0x10, .PRI_VIEWPORT_WIDTH_C = 0x0, .PRI_VIEWPORT_HEIGHT_C = 0x10
, .PRI_VIEWPORT_X_START_C = 0x0, .PRI_VIEWPORT_Y_START_C = 0x10
, .SEC_VIEWPORT_WIDTH_C = 0x0, .SEC_VIEWPORT_HEIGHT_C = 0x10,
.SEC_VIEWPORT_X_START_C = 0x0, .SEC_VIEWPORT_Y_START_C = 0x10
, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_SURFACE_ADDRESS
= 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_SURFACE_ADDRESS
= 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_META_SURFACE_ADDRESS
= 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_META_SURFACE_ADDRESS
= 0x0, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_ADDRESS_C
= 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_SURFACE_ADDRESS_C
= 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_C
= 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_C
= 0x0, .SURFACE_INUSE_ADDRESS = 0x0, .SURFACE_INUSE_ADDRESS_HIGH
= 0x0, .SURFACE_INUSE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS_HIGH_C
= 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
= 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C
= 0x0, .PRIMARY_SURFACE_TMZ = 0x0, .PRIMARY_SURFACE_TMZ_C = 0x4
, .PRIMARY_META_SURFACE_TMZ = 0x10, .PRIMARY_META_SURFACE_TMZ_C
= 0x11, .PRIMARY_SURFACE_DCC_EN = 0x1, .PRIMARY_SURFACE_DCC_IND_BLK
= 0x2, .PRIMARY_SURFACE_DCC_IND_BLK_C = 0x5, .SECONDARY_SURFACE_TMZ
= 0x8, .SECONDARY_SURFACE_TMZ_C = 0xc, .SECONDARY_META_SURFACE_TMZ
= 0x12, .SECONDARY_META_SURFACE_TMZ_C = 0x13, .SECONDARY_SURFACE_DCC_EN
= 0x9, .SECONDARY_SURFACE_DCC_IND_BLK = 0xa, .SECONDARY_SURFACE_DCC_IND_BLK_C
= 0xd, .DET_BUF_PLANE1_BASE_ADDRESS = 0x0, .CROSSBAR_SRC_CB_B
= 0x14, .CROSSBAR_SRC_CR_R = 0x16, .CROSSBAR_SRC_Y_G = 0x12,
.CROSSBAR_SRC_ALPHA = 0x10, .PACK_3TO2_ELEMENT_DISABLE = 0xc
, .DRQ_EXPANSION_MODE = 0x0, .PRQ_EXPANSION_MODE = 0x6, .MRQ_EXPANSION_MODE
= 0x4, .CRQ_EXPANSION_MODE = 0x2, .CHUNK_SIZE = 0x8, .MIN_CHUNK_SIZE
= 0xb, .META_CHUNK_SIZE = 0x10, .MIN_META_CHUNK_SIZE = 0x12,
.DPTE_GROUP_SIZE = 0x14, .SWATH_HEIGHT = 0x0, .PTE_ROW_HEIGHT_LINEAR
= 0x4, .CHUNK_SIZE_C = 0x8, .MIN_CHUNK_SIZE_C = 0xb, .META_CHUNK_SIZE_C
= 0x10, .MIN_META_CHUNK_SIZE_C = 0x12, .DPTE_GROUP_SIZE_C = 0x14
, .SWATH_HEIGHT_C = 0x0, .PTE_ROW_HEIGHT_LINEAR_C = 0x4, .REFCYC_H_BLANK_END
= 0x0, .DLG_V_BLANK_END = 0x10, .MIN_DST_Y_NEXT_START = 0x0,
.REFCYC_PER_HTOTAL = 0x0, .REFCYC_X_AFTER_SCALER = 0x0, .DST_Y_AFTER_SCALER
= 0x10, .DST_Y_PER_VM_VBLANK = 0x0, .DST_Y_PER_ROW_VBLANK = 0x8
, .REF_FREQ_TO_PIX_FREQ = 0x0, .REFCYC_PER_PTE_GROUP_VBLANK_L
= 0x0, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x0, .DST_Y_PER_META_ROW_NOM_L
= 0x0, .REFCYC_PER_META_CHUNK_NOM_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_L
= 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x10, .REFCYC_PER_LINE_DELIVERY_L
= 0x0, .REFCYC_PER_LINE_DELIVERY_C = 0x10, .REFCYC_PER_PTE_GROUP_VBLANK_C
= 0x0, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x0, .DST_Y_PER_META_ROW_NOM_C
= 0x0, .REFCYC_PER_META_CHUNK_NOM_C = 0x0, .QoS_LEVEL_LOW_WM
= 0x0, .QoS_LEVEL_HIGH_WM = 0x10, .MIN_TTU_VBLANK = 0x0, .QoS_LEVEL_FLIP
= 0x1c, .ROW_TTU_MODE = 0x1b, .REFCYC_PER_REQ_DELIVERY = 0x0
, .QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE
= 0x0, .HUBP_CLOCK_ENABLE = 0x0, .DST_Y_PER_PTE_ROW_NOM_L = 0x0
, .REFCYC_PER_PTE_GROUP_NOM_L = 0x0, .DST_Y_PER_PTE_ROW_NOM_C
= 0x0, .REFCYC_PER_PTE_GROUP_NOM_C = 0x0, .ENABLE_L1_TLB = 0x0
, .SYSTEM_ACCESS_MODE = 0x3, .REFCYC_PER_REQ_DELIVERY = 0x0, .
QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE
= 0x0, .ROTATION_ANGLE = 0x8, .H_MIRROR_EN = 0xa, .ALPHA_PLANE_EN
= 0xb, .DST_Y_PREFETCH = 0x18, .VRATIO_PREFETCH = 0x0, .VRATIO_PREFETCH_C
= 0x0, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0, .MC_VM_SYSTEM_APERTURE_HIGH_ADDR
= 0x0, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST
= 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS
= 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE
= 0x8, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK
= 0x18, .CURSOR_ENABLE = 0x0, .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION
= 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, .
CURSOR_DST_X_OFFSET = 0x0, .DMDATA_ADDRESS_HIGH = 0x0, .DMDATA_MODE
= 0x2, .DMDATA_UPDATED = 0x0, .DMDATA_REPEAT = 0x1, .DMDATA_SIZE
= 0x10, .DMDATA_SW_UPDATED = 0x0, .DMDATA_SW_REPEAT = 0x1, .
DMDATA_SW_SIZE = 0x10, .DMDATA_QOS_MODE = 0x0, .DMDATA_QOS_LEVEL
= 0x4, .DMDATA_DL_DELTA = 0x10, .DMDATA_DONE = 0x0, .DST_Y_PER_VM_FLIP
= 0x0, .DST_Y_PER_ROW_FLIP = 0x8, .REFCYC_PER_PTE_GROUP_FLIP_L
= 0x0, .REFCYC_PER_META_CHUNK_FLIP_L = 0x0, .HUBP_VREADY_AT_OR_AFTER_VSYNC
= 0x8, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x9, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS
= 0x9, .SURFACE_GSL_ENABLE = 0x8, .SURFACE_TRIPLE_BUFFER_ENABLE
= 0xa, .VMID = 0x0, .REFCYC_PER_VM_GROUP_FLIP = 0x0, .REFCYC_PER_VM_REQ_FLIP
= 0x0, .REFCYC_PER_PTE_GROUP_FLIP_C = 0x0, .REFCYC_PER_META_CHUNK_FLIP_C
= 0x0, .REFCYC_PER_VM_GROUP_VBLANK = 0x0, .REFCYC_PER_VM_REQ_VBLANK
= 0x0, .VM_GROUP_SIZE = 0x18
721};
722
723static const struct dcn_hubp2_mask hubp_mask = {
724 HUBP_MASK_SH_LIST_DCN30(_MASK).REFCYC_PER_VM_DMDATA = 0x0000FFFFL, .DMDATA_VM_FAULT_STATUS =
0x000F0000L, .DMDATA_VM_FAULT_STATUS_CLEAR = 0x00100000L, .DMDATA_VM_UNDERFLOW_STATUS
= 0x01000000L, .DMDATA_VM_LATE_STATUS = 0x02000000L, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR
= 0x04000000L, .DMDATA_VM_DONE = 0x80000000L, .HUBP_BLANK_EN
= 0x00000001L, .HUBP_TTU_DISABLE = 0x00001000L, .HUBP_UNDERFLOW_STATUS
= 0x70000000L, .HUBP_UNDERFLOW_CLEAR = 0x80000000L, .HUBP_NO_OUTSTANDING_REQ
= 0x00000002L, .HUBP_VTG_SEL = 0x000000F0L, .HUBP_DISABLE = 0x00000004L
, .NUM_PIPES = 0x00000007L, .PIPE_INTERLEAVE = 0x000000C0L, .
MAX_COMPRESSED_FRAGS = 0x00003000L, .NUM_PKRS = 0x00070000L, .
SW_MODE = 0x0000001FL, .META_LINEAR = 0x00000200L, .PIPE_ALIGNED
= 0x00000800L, .PITCH = 0x00003FFFL, .META_PITCH = 0x3FFF0000L
, .PITCH_C = 0x00003FFFL, .META_PITCH_C = 0x3FFF0000L, .SURFACE_PIXEL_FORMAT
= 0x0000007FL, .SURFACE_FLIP_TYPE = 0x00000002L, .SURFACE_FLIP_MODE_FOR_STEREOSYNC
= 0x00003000L, .SURFACE_FLIP_IN_STEREOSYNC = 0x00010000L, .SURFACE_FLIP_PENDING
= 0x00000100L, .SURFACE_UPDATE_LOCK = 0x00000001L, .PRI_VIEWPORT_WIDTH
= 0x00003FFFL, .PRI_VIEWPORT_HEIGHT = 0x3FFF0000L, .PRI_VIEWPORT_X_START
= 0x00003FFFL, .PRI_VIEWPORT_Y_START = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH
= 0x00003FFFL, .SEC_VIEWPORT_HEIGHT = 0x3FFF0000L, .SEC_VIEWPORT_X_START
= 0x00003FFFL, .SEC_VIEWPORT_Y_START = 0x3FFF0000L, .PRI_VIEWPORT_WIDTH_C
= 0x00003FFFL, .PRI_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .PRI_VIEWPORT_X_START_C
= 0x00003FFFL, .PRI_VIEWPORT_Y_START_C = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH_C
= 0x00003FFFL, .SEC_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .SEC_VIEWPORT_X_START_C
= 0x00003FFFL, .SEC_VIEWPORT_Y_START_C = 0x3FFF0000L, .PRIMARY_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .PRIMARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_META_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, .
SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_META_SURFACE_ADDRESS
= 0xFFFFFFFFL, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL
, .PRIMARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH_C
= 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .
PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS_C
= 0xFFFFFFFFL, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL
, .SECONDARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS
= 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_INUSE_ADDRESS_C
= 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .
SURFACE_EARLIEST_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
= 0x0000FFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0xFFFFFFFFL
, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_SURFACE_TMZ
= 0x00000001L, .PRIMARY_SURFACE_TMZ_C = 0x00000010L, .PRIMARY_META_SURFACE_TMZ
= 0x00010000L, .PRIMARY_META_SURFACE_TMZ_C = 0x00020000L, .PRIMARY_SURFACE_DCC_EN
= 0x00000002L, .PRIMARY_SURFACE_DCC_IND_BLK = 0x0000000CL, .
PRIMARY_SURFACE_DCC_IND_BLK_C = 0x00000060L, .SECONDARY_SURFACE_TMZ
= 0x00000100L, .SECONDARY_SURFACE_TMZ_C = 0x00001000L, .SECONDARY_META_SURFACE_TMZ
= 0x00040000L, .SECONDARY_META_SURFACE_TMZ_C = 0x00080000L, .
SECONDARY_SURFACE_DCC_EN = 0x00000200L, .SECONDARY_SURFACE_DCC_IND_BLK
= 0x00000C00L, .SECONDARY_SURFACE_DCC_IND_BLK_C = 0x00006000L
, .DET_BUF_PLANE1_BASE_ADDRESS = 0x00000FFFL, .CROSSBAR_SRC_CB_B
= 0x00300000L, .CROSSBAR_SRC_CR_R = 0x00C00000L, .CROSSBAR_SRC_Y_G
= 0x000C0000L, .CROSSBAR_SRC_ALPHA = 0x00030000L, .PACK_3TO2_ELEMENT_DISABLE
= 0x00001000L, .DRQ_EXPANSION_MODE = 0x00000003L, .PRQ_EXPANSION_MODE
= 0x000000C0L, .MRQ_EXPANSION_MODE = 0x00000030L, .CRQ_EXPANSION_MODE
= 0x0000000CL, .CHUNK_SIZE = 0x00000700L, .MIN_CHUNK_SIZE = 0x00001800L
, .META_CHUNK_SIZE = 0x00030000L, .MIN_META_CHUNK_SIZE = 0x000C0000L
, .DPTE_GROUP_SIZE = 0x00700000L, .SWATH_HEIGHT = 0x00000007L
, .PTE_ROW_HEIGHT_LINEAR = 0x00000070L, .CHUNK_SIZE_C = 0x00000700L
, .MIN_CHUNK_SIZE_C = 0x00001800L, .META_CHUNK_SIZE_C = 0x00030000L
, .MIN_META_CHUNK_SIZE_C = 0x000C0000L, .DPTE_GROUP_SIZE_C = 0x00700000L
, .SWATH_HEIGHT_C = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR_C = 0x00000070L
, .REFCYC_H_BLANK_END = 0x00001FFFL, .DLG_V_BLANK_END = 0x7FFF0000L
, .MIN_DST_Y_NEXT_START = 0x0003FFFFL, .REFCYC_PER_HTOTAL = 0x001FFFFFL
, .REFCYC_X_AFTER_SCALER = 0x00001FFFL, .DST_Y_AFTER_SCALER =
0x00070000L, .DST_Y_PER_VM_VBLANK = 0x0000007FL, .DST_Y_PER_ROW_VBLANK
= 0x00003F00L, .REF_FREQ_TO_PIX_FREQ = 0x001FFFFFL, .REFCYC_PER_PTE_GROUP_VBLANK_L
= 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x007FFFFFL
, .DST_Y_PER_META_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_L
= 0x007FFFFFL, .REFCYC_PER_LINE_DELIVERY_PRE_L = 0x00001FFFL
, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x1FFF0000L, .REFCYC_PER_LINE_DELIVERY_L
= 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_C = 0x1FFF0000L, .REFCYC_PER_PTE_GROUP_VBLANK_C
= 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x007FFFFFL
, .DST_Y_PER_META_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_C
= 0x007FFFFFL, .QoS_LEVEL_LOW_WM = 0x00003FFFL, .QoS_LEVEL_HIGH_WM
= 0x3FFF0000L, .MIN_TTU_VBLANK = 0x00FFFFFFL, .QoS_LEVEL_FLIP
= 0xF0000000L, .ROW_TTU_MODE = 0x08000000L, .REFCYC_PER_REQ_DELIVERY
= 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE
= 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .
HUBP_CLOCK_ENABLE = 0x00000001L, .DST_Y_PER_PTE_ROW_NOM_L = 0x0001FFFFL
, .REFCYC_PER_PTE_GROUP_NOM_L = 0x007FFFFFL, .DST_Y_PER_PTE_ROW_NOM_C
= 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_C = 0x007FFFFFL, .ENABLE_L1_TLB
= 0x00000001L, .SYSTEM_ACCESS_MODE = 0x00000018L, .REFCYC_PER_REQ_DELIVERY
= 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE
= 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .
ROTATION_ANGLE = 0x00000300L, .H_MIRROR_EN = 0x00000400L, .ALPHA_PLANE_EN
= 0x00000800L, .DST_Y_PREFETCH = 0xFF000000L, .VRATIO_PREFETCH
= 0x003FFFFFL, .VRATIO_PREFETCH_C = 0x003FFFFFL, .MC_VM_SYSTEM_APERTURE_LOW_ADDR
= 0x3FFFFFFFL, .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x3FFFFFFFL
, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST
= 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .
CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L
, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L, .
CURSOR_2X_MAGNIFY = 0x00000010L, .CURSOR_PITCH = 0x00030000L,
.CURSOR_LINES_PER_CHUNK = 0x1F000000L, .CURSOR_ENABLE = 0x00000001L
, .CURSOR_X_POSITION = 0x3FFF0000L, .CURSOR_Y_POSITION = 0x00003FFFL
, .CURSOR_HOT_SPOT_X = 0x00FF0000L, .CURSOR_HOT_SPOT_Y = 0x000000FFL
, .CURSOR_DST_X_OFFSET = 0x00001FFFL, .DMDATA_ADDRESS_HIGH = 0x0000FFFFL
, .DMDATA_MODE = 0x00000004L, .DMDATA_UPDATED = 0x00000001L, .
DMDATA_REPEAT = 0x00000002L, .DMDATA_SIZE = 0x0FFF0000L, .DMDATA_SW_UPDATED
= 0x00000001L, .DMDATA_SW_REPEAT = 0x00000002L, .DMDATA_SW_SIZE
= 0x0FFF0000L, .DMDATA_QOS_MODE = 0x00000001L, .DMDATA_QOS_LEVEL
= 0x000000F0L, .DMDATA_DL_DELTA = 0xFFFF0000L, .DMDATA_DONE =
0x00000001L, .DST_Y_PER_VM_FLIP = 0x0000007FL, .DST_Y_PER_ROW_FLIP
= 0x00003F00L, .REFCYC_PER_PTE_GROUP_FLIP_L = 0x007FFFFFL, .
REFCYC_PER_META_CHUNK_FLIP_L = 0x007FFFFFL, .HUBP_VREADY_AT_OR_AFTER_VSYNC
= 0x00000100L, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x00000200L
, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x00000200L, .SURFACE_GSL_ENABLE
= 0x00000100L, .SURFACE_TRIPLE_BUFFER_ENABLE = 0x00000400L, .
VMID = 0x0000000FL, .REFCYC_PER_VM_GROUP_FLIP = 0x007FFFFFL, .
REFCYC_PER_VM_REQ_FLIP = 0x007FFFFFL, .REFCYC_PER_PTE_GROUP_FLIP_C
= 0x007FFFFFL, .REFCYC_PER_META_CHUNK_FLIP_C = 0x007FFFFFL, .
REFCYC_PER_VM_GROUP_VBLANK = 0x007FFFFFL, .REFCYC_PER_VM_REQ_VBLANK
= 0x007FFFFFL, .VM_GROUP_SIZE = 0x07000000L
725};
726
727static const struct dcn_hubbub_registers hubbub_reg = {
728 HUBBUB_REG_LIST_DCN30(0).DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x000034C0 + 0x0509,
.DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x000034C0
+ 0x050d, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x000034C0
+ 0x050e, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x000034C0
+ 0x0512, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x000034C0
+ 0x0513, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x000034C0
+ 0x0517, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x000034C0
+ 0x0518, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x000034C0
+ 0x051c, .DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = 0x000034C0 +
0x051d, .DCHUBBUB_ARB_DRAM_STATE_CNTL = 0x000034C0 + 0x0508,
.DCHUBBUB_ARB_SAT_LEVEL = 0x000034C0 + 0x0506, .DCHUBBUB_ARB_DF_REQ_OUTSTAND
= 0x000034C0 + 0x0505, .DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0
+ 0x051f, .DCHUBBUB_TEST_DEBUG_INDEX = 0x000034C0 + 0x053d, .
DCHUBBUB_TEST_DEBUG_DATA = 0x000034C0 + 0x053e, .DCHUBBUB_SOFT_RESET
= 0x000034C0 + 0x052e, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1
, .DCN_VM_FB_LOCATION_BASE = 0x000034C0 + 0x0493, .DCN_VM_FB_LOCATION_TOP
= 0x000034C0 + 0x0494, .DCN_VM_FB_OFFSET = 0x000034C0 + 0x0495
, .DCN_VM_AGP_BOT = 0x000034C0 + 0x0496, .DCN_VM_AGP_TOP = 0x000034C0
+ 0x0497, .DCN_VM_AGP_BASE = 0x000034C0 + 0x0498, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
= 0x000034C0 + 0x050b, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
= 0x000034C0 + 0x050c, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
= 0x000034C0 + 0x0510, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
= 0x000034C0 + 0x0511, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
= 0x000034C0 + 0x0515, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
= 0x000034C0 + 0x0516, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
= 0x000034C0 + 0x051a, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
= 0x000034C0 + 0x051b, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x000034C0
+ 0x053f, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x000034C0 + 0x0541
, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x000034C0 + 0x0543, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
= 0x000034C0 + 0x0545, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x000034C0
+ 0x0540, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x000034C0 + 0x0542
, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x000034C0 + 0x0544, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
= 0x000034C0 + 0x0546, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
= 0x000034C0 + 0x050a, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
= 0x000034C0 + 0x050f, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
= 0x000034C0 + 0x0514, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
= 0x000034C0 + 0x0519
729};
730
731static const struct dcn_hubbub_shift hubbub_shift = {
732 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCHUBBUB_GLOBAL_SOFT_RESET
= 0x0, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x8, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE
= 0x4, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x0, .
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x1, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE
= 0x4, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x5,
.DCHUBBUB_ARB_SAT_LEVEL = 0x0, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND
= 0xc, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
= 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
= 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
= 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0
, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
= 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
= 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
= 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
= 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .FB_BASE = 0x0, .
FB_TOP = 0x0, .FB_OFFSET = 0x0, .AGP_BOT = 0x0, .AGP_TOP = 0x0
, .AGP_BASE = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
= 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
= 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
= 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
= 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
= 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
= 0x0, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A = 0x10, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B
= 0x10, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C = 0x10, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A = 0x10
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B = 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D = 0x10
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A = 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C = 0x10
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D = 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
= 0x10, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
= 0x10
733};
734
735static const struct dcn_hubbub_mask hubbub_mask = {
736 HUBBUB_MASK_SH_LIST_DCN30(_MASK).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCHUBBUB_GLOBAL_SOFT_RESET
= 0x00000001L, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x00000100L
, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x00000010L
, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x00000001L,
.DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x00000002L,
.DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x00000010L,
.DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x00000020L
, .DCHUBBUB_ARB_SAT_LEVEL = 0xFFFFFFFFL, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND
= 0x001FF000L, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x00003FFFL
, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
= 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x00003FFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
= 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
= 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0000FFFFL
, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
= 0x0000FFFFL, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, .
FB_BASE = 0x00FFFFFFL, .FB_TOP = 0x00FFFFFFL, .FB_OFFSET = 0x00FFFFFFL
, .AGP_BOT = 0x00FFFFFFL, .AGP_TOP = 0x00FFFFFFL, .AGP_BASE =
0x00FFFFFFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x000003FFL,
.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
= 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x000003FFL
, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
= 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x000003FFL
, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x000003FFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
= 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x00003FFFL
, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
= 0x00003FFFL, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A = 0x3FFF0000L
, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B = 0x3FFF0000L, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C
= 0x3FFF0000L, .DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D = 0x3FFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0xFFFF0000L
, .DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0xFFFF0000L
737};
738
739static const struct dccg_registers dccg_regs = {
740 DCCG_REG_LIST_DCN30().DPPCLK_DTO_CTRL = 0x000000C0 + 0x00b6, .DPPCLK_DTO_PARAM[0] =
0x000000C0 + 0x0099, .DPPCLK_DTO_PARAM[1] = 0x000000C0 + 0x009a
, .DPPCLK_DTO_PARAM[2] = 0x000000C0 + 0x009b, .DPPCLK_DTO_PARAM
[3] = 0x000000C0 + 0x009c, .REFCLK_CNTL = 0x000000C0 + 0x0049
, .DPPCLK_DTO_PARAM[4] = 0x000000C0 + 0x009d, .DPPCLK_DTO_PARAM
[5] = 0x000000C0 + 0x009e, .PHYASYMCLK_CLOCK_CNTL = 0x000034C0
+ 0x0052, .PHYBSYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0053, .PHYCSYMCLK_CLOCK_CNTL
= 0x000034C0 + 0x0054
741};
742
743static const struct dccg_shift dccg_shift = {
744 DCCG_MASK_SH_LIST_DCN3(__SHIFT).DPPCLK_DTO_ENABLE[0] = 0x0, .DPPCLK_DTO_DB_EN[0] = 0x1, .DPPCLK_DTO_ENABLE
[1] = 0x4, .DPPCLK_DTO_DB_EN[1] = 0x5, .DPPCLK_DTO_ENABLE[2] =
0x8, .DPPCLK_DTO_DB_EN[2] = 0x9, .DPPCLK_DTO_ENABLE[3] = 0xc
, .DPPCLK_DTO_DB_EN[3] = 0xd, .DPPCLK0_DTO_PHASE = 0x0, .DPPCLK0_DTO_MODULO
= 0x10, .REFCLK_CLOCK_EN = 0x0, .REFCLK_SRC_SEL = 0x1, .DPPCLK_DTO_ENABLE
[4] = 0x10, .DPPCLK_DTO_DB_EN[4] = 0x11, .DPPCLK_DTO_ENABLE[5
] = 0x14, .DPPCLK_DTO_DB_EN[5] = 0x15, .PHYASYMCLK_FORCE_EN =
0x0, .PHYASYMCLK_FORCE_SRC_SEL = 0x4, .PHYBSYMCLK_FORCE_EN =
0x0, .PHYBSYMCLK_FORCE_SRC_SEL = 0x4, .PHYCSYMCLK_FORCE_EN =
0x0, .PHYCSYMCLK_FORCE_SRC_SEL = 0x4
745};
746
747static const struct dccg_mask dccg_mask = {
748 DCCG_MASK_SH_LIST_DCN3(_MASK).DPPCLK_DTO_ENABLE[0] = 0x00000001L, .DPPCLK_DTO_DB_EN[0] = 0x00000002L
, .DPPCLK_DTO_ENABLE[1] = 0x00000010L, .DPPCLK_DTO_DB_EN[1] =
0x00000020L, .DPPCLK_DTO_ENABLE[2] = 0x00000100L, .DPPCLK_DTO_DB_EN
[2] = 0x00000200L, .DPPCLK_DTO_ENABLE[3] = 0x00001000L, .DPPCLK_DTO_DB_EN
[3] = 0x00002000L, .DPPCLK0_DTO_PHASE = 0x000000FFL, .DPPCLK0_DTO_MODULO
= 0x00FF0000L, .REFCLK_CLOCK_EN = 0x00000001L, .REFCLK_SRC_SEL
= 0x00000002L, .DPPCLK_DTO_ENABLE[4] = 0x00010000L, .DPPCLK_DTO_DB_EN
[4] = 0x00020000L, .DPPCLK_DTO_ENABLE[5] = 0x00100000L, .DPPCLK_DTO_DB_EN
[5] = 0x00200000L, .PHYASYMCLK_FORCE_EN = 0x00000001L, .PHYASYMCLK_FORCE_SRC_SEL
= 0x00000010L, .PHYBSYMCLK_FORCE_EN = 0x00000001L, .PHYBSYMCLK_FORCE_SRC_SEL
= 0x00000010L, .PHYCSYMCLK_FORCE_EN = 0x00000001L, .PHYCSYMCLK_FORCE_SRC_SEL
= 0x00000010L
749};
750
751static const struct dce_hwseq_registers hwseq_reg = {
752 HWSEQ_DCN30_REG_LIST().REFCLK_CNTL = 0x000000C0 + 0x0049, .DCHUBBUB_GLOBAL_TIMER_CNTL
= 0x000034C0 + 0x051f, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede
, .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2
= 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0530, .
DCFCLK_CNTL = 0x000034C0 + 0x0530, .DC_MEM_GLOBAL_PWR_REQ_CNTL
= 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080
, .PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0083, .PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0
+ 0x0087, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PHYPLL_PIXEL_RATE_CNTL
[2] = 0x000000C0 + 0x008b, .PIXEL_RATE_CNTL[3] = 0x000000C0 +
0x008c, .PHYPLL_PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008f, .PIXEL_RATE_CNTL
[4] = 0x000000C0 + 0x0090, .PHYPLL_PIXEL_RATE_CNTL[4] = 0x000000C0
+ 0x0093, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094, .PHYPLL_PIXEL_RATE_CNTL
[5] = 0x000000C0 + 0x0097, .MICROSECOND_TIME_BASE_DIV = 0x000000C0
+ 0x007b, .MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, .
DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0 + 0x0071, .RBBMIF_TIMEOUT_DIS
= 0x000034C0 + 0x0183, .RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0184
, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1, .DPP_TOP0_DPP_CRC_CTRL
= 0x000034C0 + 0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0
+ 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0 + 0x0cc7, .
MPC_CRC_CTRL = 0x00009000 + 0x0502, .MPC_CRC_RESULT_GB = 0x00009000
+ 0x0505, .MPC_CRC_RESULT_C = 0x00009000 + 0x0506, .MPC_CRC_RESULT_AR
= 0x00009000 + 0x0504, .DOMAIN0_PG_CONFIG = 0x000034C0 + 0x0080
, .DOMAIN1_PG_CONFIG = 0x000034C0 + 0x0082, .DOMAIN2_PG_CONFIG
= 0x000034C0 + 0x0084, .DOMAIN3_PG_CONFIG = 0x000034C0 + 0x0086
, .DOMAIN4_PG_CONFIG = 0x000034C0 + 0x0088, .DOMAIN5_PG_CONFIG
= 0x000034C0 + 0x008a, .DOMAIN6_PG_CONFIG = 0x000034C0 + 0x008c
, .DOMAIN7_PG_CONFIG = 0x000034C0 + 0x008e, .DOMAIN8_PG_CONFIG
= 0x000034C0 + 0x0090, .DOMAIN9_PG_CONFIG = 0x000034C0 + 0x0092
, .DOMAIN16_PG_CONFIG = 0x000034C0 + 0x00a1, .DOMAIN17_PG_CONFIG
= 0x000034C0 + 0x00a3, .DOMAIN18_PG_CONFIG = 0x000034C0 + 0x00a5
, .DOMAIN19_PG_CONFIG = 0x000034C0 + 0x00a7, .DOMAIN20_PG_CONFIG
= 0x000034C0 + 0x00a9, .DOMAIN21_PG_CONFIG = 0x000034C0 + 0x00ab
, .DOMAIN0_PG_STATUS = 0x000034C0 + 0x0081, .DOMAIN1_PG_STATUS
= 0x000034C0 + 0x0083, .DOMAIN2_PG_STATUS = 0x000034C0 + 0x0085
, .DOMAIN3_PG_STATUS = 0x000034C0 + 0x0087, .DOMAIN4_PG_STATUS
= 0x000034C0 + 0x0089, .DOMAIN5_PG_STATUS = 0x000034C0 + 0x008b
, .DOMAIN6_PG_STATUS = 0x000034C0 + 0x008d, .DOMAIN7_PG_STATUS
= 0x000034C0 + 0x008f, .DOMAIN8_PG_STATUS = 0x000034C0 + 0x0091
, .DOMAIN9_PG_STATUS = 0x000034C0 + 0x0093, .DOMAIN10_PG_STATUS
= 0x000034C0 + 0x0095, .DOMAIN11_PG_STATUS = 0x000034C0 + 0x0097
, .DOMAIN16_PG_STATUS = 0x000034C0 + 0x00a2, .DOMAIN17_PG_STATUS
= 0x000034C0 + 0x00a4, .DOMAIN18_PG_STATUS = 0x000034C0 + 0x00a6
, .DOMAIN19_PG_STATUS = 0x000034C0 + 0x00a8, .DOMAIN20_PG_STATUS
= 0x000034C0 + 0x00aa, .DOMAIN21_PG_STATUS = 0x000034C0 + 0x00ac
, .D1VGA_CONTROL = 0x000000C0 + 0x000c, .D2VGA_CONTROL = 0x000000C0
+ 0x000e, .D3VGA_CONTROL = 0x000000C0 + 0x0038, .D4VGA_CONTROL
= 0x000000C0 + 0x0039, .D5VGA_CONTROL = 0x000000C0 + 0x003a,
.D6VGA_CONTROL = 0x000000C0 + 0x003b, .DC_IP_REQUEST_CNTL = 0x000034C0
+ 0x00b2, .REFCLK_CNTL = 0x000000C0 + 0x0049, .DCHUBBUB_GLOBAL_TIMER_CNTL
= 0x000034C0 + 0x051f, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede
, .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2
= 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0530, .
DCFCLK_CNTL = 0x000034C0 + 0x0530, .DC_MEM_GLOBAL_PWR_REQ_CNTL
= 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080
, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL
[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 +
0x008c, .PIXEL_RATE_CNTL[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL
[5] = 0x000000C0 + 0x0094, .PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0
+ 0x0083, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0087, .
PHYPLL_PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x008b, .PHYPLL_PIXEL_RATE_CNTL
[3] = 0x000000C0 + 0x008f, .PHYPLL_PIXEL_RATE_CNTL[4] = 0x000000C0
+ 0x0093, .PHYPLL_PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0097, .
MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .MILLISECOND_TIME_BASE_DIV
= 0x000000C0 + 0x0070, .DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0
+ 0x0071, .RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x0183, .RBBMIF_TIMEOUT_DIS_2
= 0x000034C0 + 0x0184, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1
, .DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 + 0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A
= 0x000034C0 + 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0
+ 0x0cc7, .MPC_CRC_CTRL = 0x00009000 + 0x0502, .MPC_CRC_RESULT_GB
= 0x00009000 + 0x0505, .MPC_CRC_RESULT_C = 0x00009000 + 0x0506
, .MPC_CRC_RESULT_AR = 0x00009000 + 0x0504, .AZALIA_AUDIO_DTO
= 0x000034C0 + 0x03c3, .AZALIA_CONTROLLER_CLOCK_GATING = 0x000034C0
+ 0x03c2
753};
754
755static const struct dce_hwseq_shift hwseq_shift = {
756 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT).PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE
= 0x0, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCFCLK_GATE_DIS
= 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV
= 0x0, .DOMAIN0_POWER_FORCEON = 0x0, .DOMAIN0_POWER_GATE = 0x8
, .DOMAIN1_POWER_FORCEON = 0x0, .DOMAIN1_POWER_GATE = 0x8, .DOMAIN2_POWER_FORCEON
= 0x0, .DOMAIN2_POWER_GATE = 0x8, .DOMAIN3_POWER_FORCEON = 0x0
, .DOMAIN3_POWER_GATE = 0x8, .DOMAIN4_POWER_FORCEON = 0x0, .DOMAIN4_POWER_GATE
= 0x8, .DOMAIN5_POWER_FORCEON = 0x0, .DOMAIN5_POWER_GATE = 0x8
, .DOMAIN6_POWER_FORCEON = 0x0, .DOMAIN6_POWER_GATE = 0x8, .DOMAIN7_POWER_FORCEON
= 0x0, .DOMAIN7_POWER_GATE = 0x8, .DOMAIN8_POWER_FORCEON = 0x0
, .DOMAIN8_POWER_GATE = 0x8, .DOMAIN9_POWER_FORCEON = 0x0, .DOMAIN9_POWER_GATE
= 0x8, .DOMAIN10_POWER_FORCEON = 0x0, .DOMAIN10_POWER_GATE =
0x8, .DOMAIN11_POWER_FORCEON = 0x0, .DOMAIN11_POWER_GATE = 0x8
, .DOMAIN16_POWER_FORCEON = 0x0, .DOMAIN16_POWER_GATE = 0x8, .
DOMAIN17_POWER_FORCEON = 0x0, .DOMAIN17_POWER_GATE = 0x8, .DOMAIN18_POWER_FORCEON
= 0x0, .DOMAIN18_POWER_GATE = 0x8, .DOMAIN19_POWER_FORCEON =
0x0, .DOMAIN19_POWER_GATE = 0x8, .DOMAIN20_POWER_FORCEON = 0x0
, .DOMAIN20_POWER_GATE = 0x8, .DOMAIN21_POWER_FORCEON = 0x0, .
DOMAIN21_POWER_GATE = 0x8, .DOMAIN0_PGFSM_PWR_STATUS = 0x1e, .
DOMAIN1_PGFSM_PWR_STATUS = 0x1e, .DOMAIN2_PGFSM_PWR_STATUS = 0x1e
, .DOMAIN3_PGFSM_PWR_STATUS = 0x1e, .DOMAIN4_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN5_PGFSM_PWR_STATUS = 0x1e, .DOMAIN6_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN7_PGFSM_PWR_STATUS = 0x1e, .DOMAIN8_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN9_PGFSM_PWR_STATUS = 0x1e, .DOMAIN10_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN11_PGFSM_PWR_STATUS = 0x1e, .DOMAIN16_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN17_PGFSM_PWR_STATUS = 0x1e, .DOMAIN18_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN19_PGFSM_PWR_STATUS = 0x1e, .DOMAIN20_PGFSM_PWR_STATUS
= 0x1e, .DOMAIN21_PGFSM_PWR_STATUS = 0x1e, .IP_REQUEST_EN = 0x0
, .AZALIA_AUDIO_DTO_MODULE = 0x10
757};
758
759static const struct dce_hwseq_mask hwseq_mask = {
760 HWSEQ_DCN30_MASK_SH_LIST(_MASK).PIXEL_RATE_SOURCE = 0x00000003L, .DP_DTO0_ENABLE = 0x00000010L
, .PHYPLL_PIXEL_RATE_SOURCE = 0x00000007L, .DCHUBBUB_GLOBAL_TIMER_ENABLE
= 0x00001000L, .DCFCLK_GATE_DIS = 0x80000000L, .DC_MEM_GLOBAL_PWR_REQ_DIS
= 0x00000001L, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, .
DOMAIN0_POWER_FORCEON = 0x00000001L, .DOMAIN0_POWER_GATE = 0x00000100L
, .DOMAIN1_POWER_FORCEON = 0x00000001L, .DOMAIN1_POWER_GATE =
0x00000100L, .DOMAIN2_POWER_FORCEON = 0x00000001L, .DOMAIN2_POWER_GATE
= 0x00000100L, .DOMAIN3_POWER_FORCEON = 0x00000001L, .DOMAIN3_POWER_GATE
= 0x00000100L, .DOMAIN4_POWER_FORCEON = 0x00000001L, .DOMAIN4_POWER_GATE
= 0x00000100L, .DOMAIN5_POWER_FORCEON = 0x00000001L, .DOMAIN5_POWER_GATE
= 0x00000100L, .DOMAIN6_POWER_FORCEON = 0x00000001L, .DOMAIN6_POWER_GATE
= 0x00000100L, .DOMAIN7_POWER_FORCEON = 0x00000001L, .DOMAIN7_POWER_GATE
= 0x00000100L, .DOMAIN8_POWER_FORCEON = 0x00000001L, .DOMAIN8_POWER_GATE
= 0x00000100L, .DOMAIN9_POWER_FORCEON = 0x00000001L, .DOMAIN9_POWER_GATE
= 0x00000100L, .DOMAIN10_POWER_FORCEON = 0x00000001L, .DOMAIN10_POWER_GATE
= 0x00000100L, .DOMAIN11_POWER_FORCEON = 0x00000001L, .DOMAIN11_POWER_GATE
= 0x00000100L, .DOMAIN16_POWER_FORCEON = 0x00000001L, .DOMAIN16_POWER_GATE
= 0x00000100L, .DOMAIN17_POWER_FORCEON = 0x00000001L, .DOMAIN17_POWER_GATE
= 0x00000100L, .DOMAIN18_POWER_FORCEON = 0x00000001L, .DOMAIN18_POWER_GATE
= 0x00000100L, .DOMAIN19_POWER_FORCEON = 0x00000001L, .DOMAIN19_POWER_GATE
= 0x00000100L, .DOMAIN20_POWER_FORCEON = 0x00000001L, .DOMAIN20_POWER_GATE
= 0x00000100L, .DOMAIN21_POWER_FORCEON = 0x00000001L, .DOMAIN21_POWER_GATE
= 0x00000100L, .DOMAIN0_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN1_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN2_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN3_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN4_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN5_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN6_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN7_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN8_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN9_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN10_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN11_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN16_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN17_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN18_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN19_PGFSM_PWR_STATUS
= 0xC0000000L, .DOMAIN20_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN21_PGFSM_PWR_STATUS
= 0xC0000000L, .IP_REQUEST_EN = 0x00000001L, .AZALIA_AUDIO_DTO_MODULE
= 0xFFFF0000L
761};
762#define vmid_regs(id)[id] = { .CNTL = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_CNTL_BASE_IDX
+ mmDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32}\
763[id] = {\
764 DCN20_VMID_REG_LIST(id).CNTL = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_CNTL_BASE_IDX +
mmDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32
= DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
+ mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32\
765}
766
767static const struct dcn_vmid_registers vmid_regs[] = {
768 vmid_regs(0)[0] = { .CNTL = 0x000034C0 + 0x0559, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x055a, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x055b, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x055c,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x055d, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x055e, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x055f},
769 vmid_regs(1)[1] = { .CNTL = 0x000034C0 + 0x0560, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0561, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0562, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0563,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0564, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x0565, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0566},
770 vmid_regs(2)[2] = { .CNTL = 0x000034C0 + 0x0567, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0568, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0569, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x056a,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x056b, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x056c, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x056d},
771 vmid_regs(3)[3] = { .CNTL = 0x000034C0 + 0x056e, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x056f, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0570, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0571,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0572, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x0573, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0574},
772 vmid_regs(4)[4] = { .CNTL = 0x000034C0 + 0x0575, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0576, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0577, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0578,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0579, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x057a, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x057b},
773 vmid_regs(5)[5] = { .CNTL = 0x000034C0 + 0x057c, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x057d, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x057e, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x057f,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0580, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x0581, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0582},
774 vmid_regs(6)[6] = { .CNTL = 0x000034C0 + 0x0583, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0584, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0585, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0586,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0587, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x0588, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0589},
775 vmid_regs(7)[7] = { .CNTL = 0x000034C0 + 0x058a, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x058b, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x058c, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x058d,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x058e, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x058f, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0590},
776 vmid_regs(8)[8] = { .CNTL = 0x000034C0 + 0x0591, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0592, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x0593, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0594,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0595, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x0596, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x0597},
777 vmid_regs(9)[9] = { .CNTL = 0x000034C0 + 0x0598, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x0599, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x059a, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x059b,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x059c, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x059d, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x059e},
778 vmid_regs(10)[10] = { .CNTL = 0x000034C0 + 0x059f, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05a0, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05a1, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a2,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05a3, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05a4, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05a5},
779 vmid_regs(11)[11] = { .CNTL = 0x000034C0 + 0x05a6, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05a7, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05a8, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a9,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05aa, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05ab, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05ac},
780 vmid_regs(12)[12] = { .CNTL = 0x000034C0 + 0x05ad, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05ae, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05af, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b0,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b1, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05b2, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05b3},
781 vmid_regs(13)[13] = { .CNTL = 0x000034C0 + 0x05b4, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05b5, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05b6, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b7,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b8, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05b9, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05ba},
782 vmid_regs(14)[14] = { .CNTL = 0x000034C0 + 0x05bb, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05bc, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05bd, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05be,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05bf, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05c0, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05c1},
783 vmid_regs(15)[15] = { .CNTL = 0x000034C0 + 0x05c2, .PAGE_TABLE_BASE_ADDR_HI32
= 0x000034C0 + 0x05c3, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0
+ 0x05c4, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05c5,
.PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05c6, .PAGE_TABLE_END_ADDR_HI32
= 0x000034C0 + 0x05c7, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0
+ 0x05c8}
784};
785
786static const struct dcn20_vmid_shift vmid_shifts = {
787 DCN20_VMID_MASK_SH_LIST(__SHIFT).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x1, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE
= 0x3, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0x0, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32
= 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32
= 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32
= 0x0
788};
789
790static const struct dcn20_vmid_mask vmid_masks = {
791 DCN20_VMID_MASK_SH_LIST(_MASK).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x00000006L, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE
= 0x00000078L, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0xFFFFFFFFL
, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4
= 0x0000000FL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 =
0xFFFFFFFFL, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL
, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL
792};
793
794static const struct resource_caps res_cap_dcn3 = {
795 .num_timing_generator = 6,
796 .num_opp = 6,
797 .num_video_plane = 6,
798 .num_audio = 6,
799 .num_stream_encoder = 6,
800 .num_pll = 6,
801 .num_dwb = 1,
802 .num_ddc = 6,
803 .num_vmid = 16,
804 .num_mpc_3dlut = 3,
805 .num_dsc = 6,
806};
807
808static const struct dc_plane_cap plane_cap = {
809 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
810 .blends_with_above = true1,
811 .blends_with_below = true1,
812 .per_pixel_alpha = true1,
813
814 .pixel_format_support = {
815 .argb8888 = true1,
816 .nv12 = true1,
817 .fp16 = true1,
818 .p010 = false0,
819 .ayuv = false0,
820 },
821
822 .max_upscale_factor = {
823 .argb8888 = 16000,
824 .nv12 = 16000,
825 .fp16 = 16000
826 },
827
828 .max_downscale_factor = {
829 .argb8888 = 600,
830 .nv12 = 600,
831 .fp16 = 600
832 }
833};
834
835static const struct dc_debug_options debug_defaults_drv = {
836 .disable_dmcu = true1, //No DMCU on DCN30
837 .force_abm_enable = false0,
838 .timing_trace = false0,
839 .clock_trace = true1,
840 .disable_pplib_clock_request = true1,
841 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
842 .force_single_disp_pipe_split = false0,
843 .disable_dcc = DCC_ENABLE,
844 .vsr_support = true1,
845 .performance_trace = false0,
846 .max_downscale_src_width = 7680,/*upto 8K*/
847 .disable_pplib_wm_range = false0,
848 .scl_reset_length10 = true1,
849 .sanity_checks = false0,
850 .underflow_assert_delay_us = 0xFFFFFFFF,
851 .dwb_fi_phase = -1, // -1 = disable,
852 .dmub_command_table = true1,
853 .disable_psr = false0,
854};
855
856static const struct dc_debug_options debug_defaults_diags = {
857 .disable_dmcu = true1, //No dmcu on DCN30
858 .force_abm_enable = false0,
859 .timing_trace = true1,
860 .clock_trace = true1,
861 .disable_dpp_power_gate = true1,
862 .disable_hubp_power_gate = true1,
863 .disable_clock_gate = true1,
864 .disable_pplib_clock_request = true1,
865 .disable_pplib_wm_range = true1,
866 .disable_stutter = false0,
867 .scl_reset_length10 = true1,
868 .dwb_fi_phase = -1, // -1 = disable
869 .dmub_command_table = true1,
870 .disable_psr = true1,
871 .enable_tri_buf = true1,
872};
873
874void dcn30_dpp_destroy(struct dpp **dpp)
875{
876 kfree(TO_DCN20_DPP(*dpp)({ const __typeof( ((struct dcn20_dpp *)0)->base ) *__mptr
= (*dpp); (struct dcn20_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn20_dpp, base) );}));
877 *dpp = NULL((void *)0);
878}
879
880static struct dpp *dcn30_dpp_create(
881 struct dc_context *ctx,
882 uint32_t inst)
883{
884 struct dcn3_dpp *dpp =
885 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL(0x0001 | 0x0004));
886
887 if (!dpp)
888 return NULL((void *)0);
889
890 if (dpp3_construct(dpp, ctx, inst,
891 &dpp_regs[inst], &tf_shift, &tf_mask))
892 return &dpp->base;
893
894 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 894); do
{} while (0); } while (0);
895 kfree(dpp);
896 return NULL((void *)0);
897}
898
899static struct output_pixel_processor *dcn30_opp_create(
900 struct dc_context *ctx, uint32_t inst)
901{
902 struct dcn20_opp *opp =
903 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL(0x0001 | 0x0004));
904
905 if (!opp) {
906 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 906); do
{} while (0); } while (0);
907 return NULL((void *)0);
908 }
909
910 dcn20_opp_construct(opp, ctx, inst,
911 &opp_regs[inst], &opp_shift, &opp_mask);
912 return &opp->base;
913}
914
915static struct dce_aux *dcn30_aux_engine_create(
916 struct dc_context *ctx,
917 uint32_t inst)
918{
919 struct aux_engine_dce110 *aux_engine =
920 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL(0x0001 | 0x0004));
921
922 if (!aux_engine)
923 return NULL((void *)0);
924
925 dce110_aux_engine_construct(aux_engine, ctx, inst,
926 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
927 &aux_engine_regs[inst],
928 &aux_mask,
929 &aux_shift,
930 ctx->dc->caps.extended_aux_timeout_support);
931
932 return &aux_engine->base;
933}
934
935#define i2c_inst_regs(id){ .SETUP = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX +
mmDC_I2C_DDCid_SETUP, .SPEED = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX
+ mmDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX
+ mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b } { I2C_HW_ENGINE_COMMON_REG_LIST(id).SETUP = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX + mmDC_I2C_DDCid_SETUP
, .SPEED = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX +
mmDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX
+ mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b }
936
937static const struct dce_i2c_registers i2c_hw_regs[] = {
938 i2c_inst_regs(1){ .SETUP = 0x000034C0 + 0x1ea3, .SPEED = 0x000034C0 + 0x1ea2,
.HW_STATUS = 0x000034C0 + 0x1e9c, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
939 i2c_inst_regs(2){ .SETUP = 0x000034C0 + 0x1ea5, .SPEED = 0x000034C0 + 0x1ea4,
.HW_STATUS = 0x000034C0 + 0x1e9d, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
940 i2c_inst_regs(3){ .SETUP = 0x000034C0 + 0x1ea7, .SPEED = 0x000034C0 + 0x1ea6,
.HW_STATUS = 0x000034C0 + 0x1e9e, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
941 i2c_inst_regs(4){ .SETUP = 0x000034C0 + 0x1ea9, .SPEED = 0x000034C0 + 0x1ea8,
.HW_STATUS = 0x000034C0 + 0x1e9f, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
942 i2c_inst_regs(5){ .SETUP = 0x000034C0 + 0x1eab, .SPEED = 0x000034C0 + 0x1eaa,
.HW_STATUS = 0x000034C0 + 0x1ea0, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
943 i2c_inst_regs(6){ .SETUP = 0x000034C0 + 0x1ead, .SPEED = 0x000034C0 + 0x1eac,
.HW_STATUS = 0x000034C0 + 0x1ea1, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
944};
945
946static const struct dce_i2c_shift i2c_shifts = {
947 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN
= 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL
= 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY
= 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ
= 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO
= 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, .
DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET
= 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT =
0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0
, .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5,
.DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS
= 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0
= 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW
= 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE
= 0x1f, .XTAL_REF_DIV = 0x8, .DC_I2C_REG_RW_CNTL_STATUS = 0x2
, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x8, .DC_I2C_DDC1_SEND_RESET_LENGTH
= 0x2
948};
949
950static const struct dce_i2c_mask i2c_masks = {
951 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK).DC_I2C_DDC1_ENABLE = 0x00000040L, .DC_I2C_DDC1_TIME_LIMIT = 0xFF000000L
, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x00000001L, .DC_I2C_DDC1_CLK_DRIVE_EN
= 0x00000080L, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x00000002L, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY
= 0x00FF0000L, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x0000FF00L, .
DC_I2C_DDC1_HW_STATUS = 0x00000003L, .DC_I2C_SW_USE_I2C_REG_REQ
= 0x00100000L, .DC_I2C_SW_DONE_USING_I2C_REG = 0x00200000L, .
DC_I2C_NO_QUEUED_SW_GO = 0x00000010L, .DC_I2C_SW_PRIORITY = 0x00000003L
, .DC_I2C_SOFT_RESET = 0x00000002L, .DC_I2C_SW_STATUS_RESET =
0x00000008L, .DC_I2C_GO = 0x00000001L, .DC_I2C_SEND_RESET = 0x00000004L
, .DC_I2C_TRANSACTION_COUNT = 0x00300000L, .DC_I2C_DDC_SELECT
= 0x00000700L, .DC_I2C_DDC1_PRESCALE = 0xFFFF0000L, .DC_I2C_DDC1_THRESHOLD
= 0x00000003L, .DC_I2C_SW_STOPPED_ON_NACK = 0x00000100L, .DC_I2C_SW_TIMEOUT
= 0x00000020L, .DC_I2C_SW_ABORTED = 0x00000010L, .DC_I2C_SW_DONE
= 0x00000004L, .DC_I2C_SW_STATUS = 0x00000003L, .DC_I2C_STOP_ON_NACK0
= 0x00000100L, .DC_I2C_START0 = 0x00001000L, .DC_I2C_RW0 = 0x00000001L
, .DC_I2C_STOP0 = 0x00002000L, .DC_I2C_COUNT0 = 0x03FF0000L, .
DC_I2C_DATA_RW = 0x00000001L, .DC_I2C_DATA = 0x0000FF00L, .DC_I2C_INDEX
= 0x03FF0000L, .DC_I2C_INDEX_WRITE = 0x80000000L, .XTAL_REF_DIV
= 0x00007F00L, .DC_I2C_REG_RW_CNTL_STATUS = 0x0000000CL, .DC_I2C_DDC1_START_STOP_TIMING_CNTL
= 0x00000300L, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x00000004L
952};
953
954static struct dce_i2c_hw *dcn30_i2c_hw_create(
955 struct dc_context *ctx,
956 uint32_t inst)
957{
958 struct dce_i2c_hw *dce_i2c_hw =
959 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL(0x0001 | 0x0004));
960
961 if (!dce_i2c_hw)
962 return NULL((void *)0);
963
964 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
965 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
966
967 return dce_i2c_hw;
968}
969
970static struct mpc *dcn30_mpc_create(
971 struct dc_context *ctx,
972 int num_mpcc,
973 int num_rmu)
974{
975 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
976 GFP_KERNEL(0x0001 | 0x0004));
977
978 if (!mpc30)
979 return NULL((void *)0);
980
981 dcn30_mpc_construct(mpc30, ctx,
982 &mpc_regs,
983 &mpc_shift,
984 &mpc_mask,
985 num_mpcc,
986 num_rmu);
987
988 return &mpc30->base;
989}
990
991struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
992{
993 int i;
994
995 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
996 GFP_KERNEL(0x0001 | 0x0004));
997
998 if (!hubbub3)
999 return NULL((void *)0);
1000
1001 hubbub3_construct(hubbub3, ctx,
1002 &hubbub_reg,
1003 &hubbub_shift,
1004 &hubbub_mask);
1005
1006
1007 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1008 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1009
1010 vmid->ctx = ctx;
1011
1012 vmid->regs = &vmid_regs[i];
1013 vmid->shifts = &vmid_shifts;
1014 vmid->masks = &vmid_masks;
1015 }
1016
1017 return &hubbub3->base;
1018}
1019
1020static struct timing_generator *dcn30_timing_generator_create(
1021 struct dc_context *ctx,
1022 uint32_t instance)
1023{
1024 struct optc *tgn10 =
1025 kzalloc(sizeof(struct optc), GFP_KERNEL(0x0001 | 0x0004));
1026
1027 if (!tgn10)
1028 return NULL((void *)0);
1029
1030 tgn10->base.inst = instance;
1031 tgn10->base.ctx = ctx;
1032
1033 tgn10->tg_regs = &optc_regs[instance];
1034 tgn10->tg_shift = &optc_shift;
1035 tgn10->tg_mask = &optc_mask;
1036
1037 dcn30_timing_generator_init(tgn10);
1038
1039 return &tgn10->base;
1040}
1041
1042static const struct encoder_feature_support link_enc_feature = {
1043 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1044 .max_hdmi_pixel_clock = 600000,
1045 .hdmi_ycbcr420_supported = true1,
1046 .dp_ycbcr420_supported = true1,
1047 .fec_supported = true1,
1048 .flags.bits.IS_HBR2_CAPABLE = true1,
1049 .flags.bits.IS_HBR3_CAPABLE = true1,
1050 .flags.bits.IS_TPS3_CAPABLE = true1,
1051 .flags.bits.IS_TPS4_CAPABLE = true1
1052};
1053
1054static struct link_encoder *dcn30_link_encoder_create(
1055 const struct encoder_init_data *enc_init_data)
1056{
1057 struct dcn20_link_encoder *enc20 =
1058 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL(0x0001 | 0x0004));
1059
1060 if (!enc20)
1061 return NULL((void *)0);
1062
1063 dcn30_link_encoder_construct(enc20,
1064 enc_init_data,
1065 &link_enc_feature,
1066 &link_enc_regs[enc_init_data->transmitter],
1067 &link_enc_aux_regs[enc_init_data->channel - 1],
1068 &link_enc_hpd_regs[enc_init_data->hpd_source],
1069 &le_shift,
1070 &le_mask);
1071
1072 return &enc20->enc10.base;
1073}
1074
1075static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1076{
1077 struct dce_panel_cntl *panel_cntl =
1078 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL(0x0001 | 0x0004));
1079
1080 if (!panel_cntl)
1081 return NULL((void *)0);
1082
1083 dce_panel_cntl_construct(panel_cntl,
1084 init_data,
1085 &panel_cntl_regs[init_data->inst],
1086 &panel_cntl_shift,
1087 &panel_cntl_mask);
1088
1089 return &panel_cntl->base;
1090}
1091
1092static void read_dce_straps(
1093 struct dc_context *ctx,
1094 struct resource_straps *straps)
1095{
1096 generic_reg_get(ctx, mmDC_PINSTRAPS0x2880 + BASE(mmDC_PINSTRAPS_BASE_IDX)0x000034C0,
1097 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO)0xe, 0x0000C000L, &straps->dc_pinstraps_audio);
1098
1099}
1100
1101static struct audio *dcn30_create_audio(
1102 struct dc_context *ctx, unsigned int inst)
1103{
1104 return dce_audio_create(ctx, inst,
1105 &audio_regs[inst], &audio_shift, &audio_mask);
1106}
1107
1108static struct vpg *dcn30_vpg_create(
1109 struct dc_context *ctx,
1110 uint32_t inst)
1111{
1112 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL(0x0001 | 0x0004));
1113
1114 if (!vpg3)
1115 return NULL((void *)0);
1116
1117 vpg3_construct(vpg3, ctx, inst,
1118 &vpg_regs[inst],
1119 &vpg_shift,
1120 &vpg_mask);
1121
1122 return &vpg3->base;
1123}
1124
1125static struct afmt *dcn30_afmt_create(
1126 struct dc_context *ctx,
1127 uint32_t inst)
1128{
1129 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL(0x0001 | 0x0004));
1130
1131 if (!afmt3)
1132 return NULL((void *)0);
1133
1134 afmt3_construct(afmt3, ctx, inst,
1135 &afmt_regs[inst],
1136 &afmt_shift,
1137 &afmt_mask);
1138
1139 return &afmt3->base;
1140}
1141
1142struct stream_encoder *dcn30_stream_encoder_create(
1143 enum engine_id eng_id,
1144 struct dc_context *ctx)
1145{
1146 struct dcn10_stream_encoder *enc1;
1147 struct vpg *vpg;
1148 struct afmt *afmt;
1149 int vpg_inst;
1150 int afmt_inst;
1151
1152 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1153 if (eng_id <= ENGINE_ID_DIGF) {
1
Assuming 'eng_id' is <= ENGINE_ID_DIGF
→
2
←
Taking true branch
→
1154 vpg_inst = eng_id;
1155 afmt_inst = eng_id;
1156 } else
1157 return NULL((void *)0);
1158
1159 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL(0x0001 | 0x0004));
3
←
Calling 'kzalloc'
→
5
←
Returned allocated memory
→
1160 vpg = dcn30_vpg_create(ctx, vpg_inst);
1161 afmt = dcn30_afmt_create(ctx, afmt_inst);
1162
1163 if (!enc1 || !vpg
6.1
'vpg' is null
6.1
'vpg' is null
 || !afmt)
6
←
Assuming 'enc1' is non-null
→
1164 return NULL((void *)0);
7
←
Potential leak of memory pointed to by 'enc1'
1165
1166 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1167 eng_id, vpg, afmt,
1168 &stream_enc_regs[eng_id],
1169 &se_shift, &se_mask);
1170
1171 return &enc1->base;
1172}
1173
1174struct dce_hwseq *dcn30_hwseq_create(
1175 struct dc_context *ctx)
1176{
1177 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL(0x0001 | 0x0004));
1178
1179 if (hws) {
1180 hws->ctx = ctx;
1181 hws->regs = &hwseq_reg;
1182 hws->shifts = &hwseq_shift;
1183 hws->masks = &hwseq_mask;
1184 }
1185 return hws;
1186}
1187static const struct resource_create_funcs res_create_funcs = {
1188 .read_dce_straps = read_dce_straps,
1189 .create_audio = dcn30_create_audio,
1190 .create_stream_encoder = dcn30_stream_encoder_create,
1191 .create_hwseq = dcn30_hwseq_create,
1192};
1193
1194static const struct resource_create_funcs res_create_maximus_funcs = {
1195 .read_dce_straps = NULL((void *)0),
1196 .create_audio = NULL((void *)0),
1197 .create_stream_encoder = NULL((void *)0),
1198 .create_hwseq = dcn30_hwseq_create,
1199};
1200
1201static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1202{
1203 unsigned int i;
1204
1205 for (i = 0; i < pool->base.stream_enc_count; i++) {
1206 if (pool->base.stream_enc[i] != NULL((void *)0)) {
1207 if (pool->base.stream_enc[i]->vpg != NULL((void *)0)) {
1208 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)({ const __typeof( ((struct dcn30_vpg *)0)->base ) *__mptr
= (pool->base.stream_enc[i]->vpg); (struct dcn30_vpg *
)( (char *)__mptr - __builtin_offsetof(struct dcn30_vpg, base
) );}));
1209 pool->base.stream_enc[i]->vpg = NULL((void *)0);
1210 }
1211 if (pool->base.stream_enc[i]->afmt != NULL((void *)0)) {
1212 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)({ const __typeof( ((struct dcn30_afmt *)0)->base ) *__mptr
= (pool->base.stream_enc[i]->afmt); (struct dcn30_afmt
*)( (char *)__mptr - __builtin_offsetof(struct dcn30_afmt, base
) );}));
1213 pool->base.stream_enc[i]->afmt = NULL((void *)0);
1214 }
1215 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (pool->base.stream_enc[i]); (struct dcn10_stream_encoder
*)( (char *)__mptr - __builtin_offsetof(struct dcn10_stream_encoder
, base) );}));
1216 pool->base.stream_enc[i] = NULL((void *)0);
1217 }
1218 }
1219
1220 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1221 if (pool->base.dscs[i] != NULL((void *)0))
1222 dcn20_dsc_destroy(&pool->base.dscs[i]);
1223 }
1224
1225 if (pool->base.mpc != NULL((void *)0)) {
1226 kfree(TO_DCN20_MPC(pool->base.mpc)({ const __typeof( ((struct dcn20_mpc *)0)->base ) *__mptr
= (pool->base.mpc); (struct dcn20_mpc *)( (char *)__mptr -
__builtin_offsetof(struct dcn20_mpc, base) );}));
1227 pool->base.mpc = NULL((void *)0);
1228 }
1229 if (pool->base.hubbub != NULL((void *)0)) {
1230 kfree(pool->base.hubbub);
1231 pool->base.hubbub = NULL((void *)0);
1232 }
1233 for (i = 0; i < pool->base.pipe_count; i++) {
1234 if (pool->base.dpps[i] != NULL((void *)0))
1235 dcn30_dpp_destroy(&pool->base.dpps[i]);
1236
1237 if (pool->base.ipps[i] != NULL((void *)0))
1238 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1239
1240 if (pool->base.hubps[i] != NULL((void *)0)) {
1241 kfree(TO_DCN20_HUBP(pool->base.hubps[i])({ const __typeof( ((struct dcn20_hubp *)0)->base ) *__mptr
= (pool->base.hubps[i]); (struct dcn20_hubp *)( (char *)__mptr
- __builtin_offsetof(struct dcn20_hubp, base) );}));
1242 pool->base.hubps[i] = NULL((void *)0);
1243 }
1244
1245 if (pool->base.irqs != NULL((void *)0)) {
1246 dal_irq_service_destroy(&pool->base.irqs);
1247 }
1248 }
1249
1250 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1251 if (pool->base.engines[i] != NULL((void *)0))
1252 dce110_engine_destroy(&pool->base.engines[i]);
1253 if (pool->base.hw_i2cs[i] != NULL((void *)0)) {
1254 kfree(pool->base.hw_i2cs[i]);
1255 pool->base.hw_i2cs[i] = NULL((void *)0);
1256 }
1257 if (pool->base.sw_i2cs[i] != NULL((void *)0)) {
1258 kfree(pool->base.sw_i2cs[i]);
1259 pool->base.sw_i2cs[i] = NULL((void *)0);
1260 }
1261 }
1262
1263 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1264 if (pool->base.opps[i] != NULL((void *)0))
1265 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1266 }
1267
1268 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1269 if (pool->base.timing_generators[i] != NULL((void *)0)) {
1270 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct optc *)0)->base ) *__mptr = (pool
->base.timing_generators[i]); (struct optc *)( (char *)__mptr
- __builtin_offsetof(struct optc, base) );}));
1271 pool->base.timing_generators[i] = NULL((void *)0);
1272 }
1273 }
1274
1275 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1276 if (pool->base.dwbc[i] != NULL((void *)0)) {
1277 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])({ const __typeof( ((struct dcn30_dwbc *)0)->base ) *__mptr
= (pool->base.dwbc[i]); (struct dcn30_dwbc *)( (char *)__mptr
- __builtin_offsetof(struct dcn30_dwbc, base) );}));
1278 pool->base.dwbc[i] = NULL((void *)0);
1279 }
1280 if (pool->base.mcif_wb[i] != NULL((void *)0)) {
1281 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])({ const __typeof( ((struct dcn30_mmhubbub *)0)->base ) *__mptr
= (pool->base.mcif_wb[i]); (struct dcn30_mmhubbub *)( (char
*)__mptr - __builtin_offsetof(struct dcn30_mmhubbub, base) )
;}));
1282 pool->base.mcif_wb[i] = NULL((void *)0);
1283 }
1284 }
1285
1286 for (i = 0; i < pool->base.audio_count; i++) {
1287 if (pool->base.audios[i])
1288 dce_aud_destroy(&pool->base.audios[i]);
1289 }
1290
1291 for (i = 0; i < pool->base.clk_src_count; i++) {
1292 if (pool->base.clock_sources[i] != NULL((void *)0)) {
1293 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1294 pool->base.clock_sources[i] = NULL((void *)0);
1295 }
1296 }
1297
1298 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1299 if (pool->base.mpc_lut[i] != NULL((void *)0)) {
1300 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1301 pool->base.mpc_lut[i] = NULL((void *)0);
1302 }
1303 if (pool->base.mpc_shaper[i] != NULL((void *)0)) {
1304 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1305 pool->base.mpc_shaper[i] = NULL((void *)0);
1306 }
1307 }
1308
1309 if (pool->base.dp_clock_source != NULL((void *)0)) {
1310 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1311 pool->base.dp_clock_source = NULL((void *)0);
1312 }
1313
1314 for (i = 0; i < pool->base.pipe_count; i++) {
1315 if (pool->base.multiple_abms[i] != NULL((void *)0))
1316 dce_abm_destroy(&pool->base.multiple_abms[i]);
1317 }
1318
1319 if (pool->base.psr != NULL((void *)0))
1320 dmub_psr_destroy(&pool->base.psr);
1321
1322 if (pool->base.dccg != NULL((void *)0))
1323 dcn_dccg_destroy(&pool->base.dccg);
1324}
1325
1326static struct hubp *dcn30_hubp_create(
1327 struct dc_context *ctx,
1328 uint32_t inst)
1329{
1330 struct dcn20_hubp *hubp2 =
1331 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL(0x0001 | 0x0004));
1332
1333 if (!hubp2)
1334 return NULL((void *)0);
1335
1336 if (hubp3_construct(hubp2, ctx, inst,
1337 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1338 return &hubp2->base;
1339
1340 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1340); do
{} while (0); } while (0);
1341 kfree(hubp2);
1342 return NULL((void *)0);
1343}
1344
1345static bool_Bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1346{
1347 int i;
1348 uint32_t pipe_count = pool->res_cap->num_dwb;
1349
1350 for (i = 0; i < pipe_count; i++) {
1351 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1352 GFP_KERNEL(0x0001 | 0x0004));
1353
1354 if (!dwbc30) {
1355 dm_error("DC: failed to create dwbc30!\n")__drm_err("DC: failed to create dwbc30!\n");
1356 return false0;
1357 }
1358
1359 dcn30_dwbc_construct(dwbc30, ctx,
1360 &dwbc30_regs[i],
1361 &dwbc30_shift,
1362 &dwbc30_mask,
1363 i);
1364
1365 pool->dwbc[i] = &dwbc30->base;
1366 }
1367 return true1;
1368}
1369
1370static bool_Bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1371{
1372 int i;
1373 uint32_t pipe_count = pool->res_cap->num_dwb;
1374
1375 for (i = 0; i < pipe_count; i++) {
1376 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1377 GFP_KERNEL(0x0001 | 0x0004));
1378
1379 if (!mcif_wb30) {
1380 dm_error("DC: failed to create mcif_wb30!\n")__drm_err("DC: failed to create mcif_wb30!\n");
1381 return false0;
1382 }
1383
1384 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1385 &mcif_wb30_regs[i],
1386 &mcif_wb30_shift,
1387 &mcif_wb30_mask,
1388 i);
1389
1390 pool->mcif_wb[i] = &mcif_wb30->base;
1391 }
1392 return true1;
1393}
1394
1395static struct display_stream_compressor *dcn30_dsc_create(
1396 struct dc_context *ctx, uint32_t inst)
1397{
1398 struct dcn20_dsc *dsc =
1399 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL(0x0001 | 0x0004));
1400
1401 if (!dsc) {
1402 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1402); do
{} while (0); } while (0);
1403 return NULL((void *)0);
1404 }
1405
1406 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1407 return &dsc->base;
1408}
1409
1410enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1411{
1412
1413 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1414}
1415
1416static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1417{
1418 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool)({ const __typeof( ((struct dcn30_resource_pool *)0)->base
) *__mptr = (*pool); (struct dcn30_resource_pool *)( (char *
)__mptr - __builtin_offsetof(struct dcn30_resource_pool, base
) );});
1419
1420 dcn30_resource_destruct(dcn30_pool);
1421 kfree(dcn30_pool);
1422 *pool = NULL((void *)0);
1423}
1424
1425static struct clock_source *dcn30_clock_source_create(
1426 struct dc_context *ctx,
1427 struct dc_bios *bios,
1428 enum clock_source_id id,
1429 const struct dce110_clk_src_regs *regs,
1430 bool_Bool dp_clk_src)
1431{
1432 struct dce110_clk_src *clk_src =
1433 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL(0x0001 | 0x0004));
1434
1435 if (!clk_src)
1436 return NULL((void *)0);
1437
1438 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1439 regs, &cs_shift, &cs_mask)) {
1440 clk_src->base.dp_clk_src = dp_clk_src;
1441 return &clk_src->base;
1442 }
1443
1444 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1444); do
{} while (0); } while (0);
1445 return NULL((void *)0);
1446}
1447
1448int dcn30_populate_dml_pipes_from_context(
1449 struct dc *dc, struct dc_state *context,
1450 display_e2e_pipe_params_st *pipes)
1451{
1452 int i, pipe_cnt;
1453 struct resource_context *res_ctx = &context->res_ctx;
1454
1455 dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1456
1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1458 if (!res_ctx->pipe_ctx[i].stream)
1459 continue;
1460
1461 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1462 dm_lb_16;
1463 }
1464
1465 return pipe_cnt;
1466}
1467
1468void dcn30_populate_dml_writeback_from_context(
1469 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1470{
1471 int pipe_cnt, i, j;
1472 double max_calc_writeback_dispclk;
1473 double writeback_dispclk;
1474 struct writeback_st dout_wb;
1475
1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1477 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1478
1479 if (!stream)
1480 continue;
1481 max_calc_writeback_dispclk = 0;
1482
1483 /* Set writeback information */
1484 pipes[pipe_cnt].dout.wb_enable = 0;
1485 pipes[pipe_cnt].dout.num_active_wb = 0;
1486 for (j = 0; j < stream->num_wb_info; j++) {
1487 struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1488
1489 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1490 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1491 pipes[pipe_cnt].dout.wb_enable = 1;
1492 pipes[pipe_cnt].dout.num_active_wb++;
1493 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1494 wb_info->dwb_params.cnv_params.crop_height :
1495 wb_info->dwb_params.cnv_params.src_height;
1496 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1497 wb_info->dwb_params.cnv_params.crop_width :
1498 wb_info->dwb_params.cnv_params.src_width;
1499 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1500 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1501
1502 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1503 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1504 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1505 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1506 } else {
1507 dout_wb.wb_htaps_luma = 1;
1508 dout_wb.wb_vtaps_luma = 1;
1509 }
1510 dout_wb.wb_htaps_chroma = 0;
1511 dout_wb.wb_vtaps_chroma = 0;
1512 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1513 (double)wb_info->dwb_params.cnv_params.crop_width /
1514 (double)wb_info->dwb_params.dest_width :
1515 (double)wb_info->dwb_params.cnv_params.src_width /
1516 (double)wb_info->dwb_params.dest_width;
1517 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1518 (double)wb_info->dwb_params.cnv_params.crop_height /
1519 (double)wb_info->dwb_params.dest_height :
1520 (double)wb_info->dwb_params.cnv_params.src_height /
1521 (double)wb_info->dwb_params.dest_height;
1522 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1523 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1524 dout_wb.wb_pixel_format = dm_444_64;
1525 else
1526 dout_wb.wb_pixel_format = dm_444_32;
1527
1528 /* Workaround for cases where multiple writebacks are connected to same plane
1529 * In which case, need to compute worst case and set the associated writeback parameters
1530 * This workaround is necessary due to DML computation assuming only 1 set of writeback
1531 * parameters per pipe
1532 */
1533 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1534 dout_wb.wb_pixel_format,
1535 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1536 dout_wb.wb_hratio,
1537 dout_wb.wb_vratio,
1538 dout_wb.wb_htaps_luma,
1539 dout_wb.wb_vtaps_luma,
1540 dout_wb.wb_src_width,
1541 dout_wb.wb_dst_width,
1542 pipes[pipe_cnt].pipe.dest.htotal,
1543 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1544
1545 if (writeback_dispclk > max_calc_writeback_dispclk) {
1546 max_calc_writeback_dispclk = writeback_dispclk;
1547 pipes[pipe_cnt].dout.wb = dout_wb;
1548 }
1549 }
1550 }
1551
1552 pipe_cnt++;
1553 }
1554
1555}
1556
1557unsigned int dcn30_calc_max_scaled_time(
1558 unsigned int time_per_pixel,
1559 enum mmhubbub_wbif_mode mode,
1560 unsigned int urgent_watermark)
1561{
1562 unsigned int time_per_byte = 0;
1563 unsigned int total_free_entry = 0xb40;
1564 unsigned int buf_lh_capability;
1565 unsigned int max_scaled_time;
1566
1567 if (mode == PACKED_444) /* packed mode 32 bpp */
1568 time_per_byte = time_per_pixel/4;
1569 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1570 time_per_byte = time_per_pixel/8;
1571
1572 if (time_per_byte == 0)
1573 time_per_byte = 1;
1574
1575 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1576 max_scaled_time = buf_lh_capability - urgent_watermark;
1577 return max_scaled_time;
1578}
1579
1580void dcn30_set_mcif_arb_params(
1581 struct dc *dc,
1582 struct dc_state *context,
1583 display_e2e_pipe_params_st *pipes,
1584 int pipe_cnt)
1585{
1586 enum mmhubbub_wbif_mode wbif_mode;
1587 struct display_mode_lib *dml = &context->bw_ctx.dml;
1588 struct mcif_arb_params *wb_arb_params;
1589 int i, j, k, dwb_pipe;
1590
1591 /* Writeback MCIF_WB arbitration parameters */
1592 dwb_pipe = 0;
1593 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1594
1595 if (!context->res_ctx.pipe_ctx[i].stream)
1596 continue;
1597
1598 for (j = 0; j < MAX_DWB_PIPES1; j++) {
1599 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1600
1601 if (writeback_info->wb_enabled == false0)
1602 continue;
1603
1604 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1605 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1606
1607 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1608 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1609 wbif_mode = PACKED_444_FP16;
1610 else
1611 wbif_mode = PACKED_444;
1612
1613 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1614 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1615 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1616 }
1617 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1618 wb_arb_params->slice_lines = 32;
1619 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1620 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1621 wbif_mode,
1622 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1623 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1624
1625 dwb_pipe++;
1626
1627 if (dwb_pipe >= MAX_DWB_PIPES1)
1628 return;
1629 }
1630 if (dwb_pipe >= MAX_DWB_PIPES1)
1631 return;
1632 }
1633
1634}
1635
1636static struct dc_cap_funcs cap_funcs = {
1637 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1638};
1639
1640bool_Bool dcn30_acquire_post_bldn_3dlut(
1641 struct resource_context *res_ctx,
1642 const struct resource_pool *pool,
1643 int mpcc_id,
1644 struct dc_3dlut **lut,
1645 struct dc_transfer_func **shaper)
1646{
1647 int i;
1648 bool_Bool ret = false0;
1649 union dc_3dlut_state *state;
1650
1651 ASSERT(*lut == NULL && *shaper == NULL)do { if (({ static int __warned; int __ret = !!(!(*lut == ((void
*)0) && *shaper == ((void *)0))); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(*lut == ((void *)0) && *shaper == ((void *)0))"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1651); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1652 *lut = NULL((void *)0);
1653 *shaper = NULL((void *)0);
1654
1655 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1656 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1657 *lut = pool->mpc_lut[i];
1658 *shaper = pool->mpc_shaper[i];
1659 state = &pool->mpc_lut[i]->state;
1660 res_ctx->is_mpc_3dlut_acquired[i] = true1;
1661 state->bits.rmu_idx_valid = 1;
1662 state->bits.rmu_mux_num = i;
1663 if (state->bits.rmu_mux_num == 0)
1664 state->bits.mpc_rmu0_mux = mpcc_id;
1665 else if (state->bits.rmu_mux_num == 1)
1666 state->bits.mpc_rmu1_mux = mpcc_id;
1667 else if (state->bits.rmu_mux_num == 2)
1668 state->bits.mpc_rmu2_mux = mpcc_id;
1669 ret = true1;
1670 break;
1671 }
1672 }
1673 return ret;
1674}
1675
1676bool_Bool dcn30_release_post_bldn_3dlut(
1677 struct resource_context *res_ctx,
1678 const struct resource_pool *pool,
1679 struct dc_3dlut **lut,
1680 struct dc_transfer_func **shaper)
1681{
1682 int i;
1683 bool_Bool ret = false0;
1684
1685 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1686 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1687 res_ctx->is_mpc_3dlut_acquired[i] = false0;
1688 pool->mpc_lut[i]->state.raw = 0;
1689 *lut = NULL((void *)0);
1690 *shaper = NULL((void *)0);
1691 ret = true1;
1692 break;
1693 }
1694 }
1695 return ret;
1696}
1697
1698#define fixed16_to_double(x)(((double) x) / ((double) (1 << 16))) (((double) x) / ((double) (1 << 16)))
1699#define fixed16_to_double_to_cpu(x)(((double) ((__uint32_t)(x))) / ((double) (1 << 16))) fixed16_to_double(le32_to_cpu(x))(((double) ((__uint32_t)(x))) / ((double) (1 << 16)))
1700
1701static bool_Bool is_soc_bounding_box_valid(struct dc *dc)
1702{
1703 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1704
1705 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev)((hw_internal_rev >= NV_SIENNA_CICHLID_P_A0)))
1706 return true1;
1707
1708 return false0;
1709}
1710
1711static bool_Bool init_soc_bounding_box(struct dc *dc,
1712 struct dcn30_resource_pool *pool)
1713{
1714 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
1715 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1716 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1717
1718 DC_LOGGER_INIT(dc->ctx->logger);
1719
1720 if (!bb && !is_soc_bounding_box_valid(dc)) {
1721 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__)__drm_err("%s: not valid soc bounding box/n", __func__);
1722 return false0;
1723 }
1724
1725 if (bb && !is_soc_bounding_box_valid(dc)) {
1726 int i;
1727
1728 dcn3_0_soc.sr_exit_time_us =
1729 fixed16_to_double_to_cpu(bb->sr_exit_time_us)(((double) ((__uint32_t)(bb->sr_exit_time_us))) / ((double
) (1 << 16)));
1730 dcn3_0_soc.sr_enter_plus_exit_time_us =
1731 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us)(((double) ((__uint32_t)(bb->sr_enter_plus_exit_time_us)))
/ ((double) (1 << 16)));
1732 dcn3_0_soc.urgent_latency_us =
1733 fixed16_to_double_to_cpu(bb->urgent_latency_us)(((double) ((__uint32_t)(bb->urgent_latency_us))) / ((double
) (1 << 16)));
1734 dcn3_0_soc.urgent_latency_pixel_data_only_us =
1735 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us)(((double) ((__uint32_t)(bb->urgent_latency_pixel_data_only_us
))) / ((double) (1 << 16)));
1736 dcn3_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
1737 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us)(((double) ((__uint32_t)(bb->urgent_latency_pixel_mixed_with_vm_data_us
))) / ((double) (1 << 16)));
1738 dcn3_0_soc.urgent_latency_vm_data_only_us =
1739 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us)(((double) ((__uint32_t)(bb->urgent_latency_vm_data_only_us
))) / ((double) (1 << 16)));
1740 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
1741 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes
));
1742 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
1743 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes
));
1744 dcn3_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
1745 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_vm_only_bytes
));
1746 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
1747 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only
))) / ((double) (1 << 16)));
1748 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
1749 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm
))) / ((double) (1 << 16)));
1750 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
1751 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only
))) / ((double) (1 << 16)));
1752 dcn3_0_soc.max_avg_sdp_bw_use_normal_percent =
1753 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent)(((double) ((__uint32_t)(bb->max_avg_sdp_bw_use_normal_percent
))) / ((double) (1 << 16)));
1754 dcn3_0_soc.max_avg_dram_bw_use_normal_percent =
1755 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent)(((double) ((__uint32_t)(bb->max_avg_dram_bw_use_normal_percent
))) / ((double) (1 << 16)));
1756 dcn3_0_soc.writeback_latency_us =
1757 fixed16_to_double_to_cpu(bb->writeback_latency_us)(((double) ((__uint32_t)(bb->writeback_latency_us))) / ((double
) (1 << 16)));
1758 dcn3_0_soc.ideal_dram_bw_after_urgent_percent =
1759 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent)(((double) ((__uint32_t)(bb->ideal_dram_bw_after_urgent_percent
))) / ((double) (1 << 16)));
1760 dcn3_0_soc.max_request_size_bytes =
1761 le32_to_cpu(bb->max_request_size_bytes)((__uint32_t)(bb->max_request_size_bytes));
1762 dcn3_0_soc.dram_channel_width_bytes =
1763 le32_to_cpu(bb->dram_channel_width_bytes)((__uint32_t)(bb->dram_channel_width_bytes));
1764 dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes =
1765 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes)((__uint32_t)(bb->fabric_datapath_to_dcn_data_return_bytes
));
1766 dcn3_0_soc.dcn_downspread_percent =
1767 fixed16_to_double_to_cpu(bb->dcn_downspread_percent)(((double) ((__uint32_t)(bb->dcn_downspread_percent))) / (
(double) (1 << 16)));
1768 dcn3_0_soc.downspread_percent =
1769 fixed16_to_double_to_cpu(bb->downspread_percent)(((double) ((__uint32_t)(bb->downspread_percent))) / ((double
) (1 << 16)));
1770 dcn3_0_soc.dram_page_open_time_ns =
1771 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns)(((double) ((__uint32_t)(bb->dram_page_open_time_ns))) / (
(double) (1 << 16)));
1772 dcn3_0_soc.dram_rw_turnaround_time_ns =
1773 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns)(((double) ((__uint32_t)(bb->dram_rw_turnaround_time_ns)))
/ ((double) (1 << 16)));
1774 dcn3_0_soc.dram_return_buffer_per_channel_bytes =
1775 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes)((__uint32_t)(bb->dram_return_buffer_per_channel_bytes));
1776 dcn3_0_soc.round_trip_ping_latency_dcfclk_cycles =
1777 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles)((__uint32_t)(bb->round_trip_ping_latency_dcfclk_cycles));
1778 dcn3_0_soc.urgent_out_of_order_return_per_channel_bytes =
1779 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_bytes
));
1780 dcn3_0_soc.channel_interleave_bytes =
1781 le32_to_cpu(bb->channel_interleave_bytes)((__uint32_t)(bb->channel_interleave_bytes));
1782 dcn3_0_soc.num_banks =
1783 le32_to_cpu(bb->num_banks)((__uint32_t)(bb->num_banks));
1784 dcn3_0_soc.num_chans =
1785 le32_to_cpu(bb->num_chans)((__uint32_t)(bb->num_chans));
1786 dcn3_0_soc.gpuvm_min_page_size_bytes =
1787 le32_to_cpu(bb->vmm_page_size_bytes)((__uint32_t)(bb->vmm_page_size_bytes));
1788 dcn3_0_soc.dram_clock_change_latency_us =
1789 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us)(((double) ((__uint32_t)(bb->dram_clock_change_latency_us)
)) / ((double) (1 << 16)));
1790 dcn3_0_soc.writeback_dram_clock_change_latency_us =
1791 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us)(((double) ((__uint32_t)(bb->writeback_dram_clock_change_latency_us
))) / ((double) (1 << 16)));
1792 dcn3_0_soc.return_bus_width_bytes =
1793 le32_to_cpu(bb->return_bus_width_bytes)((__uint32_t)(bb->return_bus_width_bytes));
1794 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz =
1795 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz)((__uint32_t)(bb->dispclk_dppclk_vco_speed_mhz));
1796 dcn3_0_soc.xfc_bus_transport_time_us =
1797 le32_to_cpu(bb->xfc_bus_transport_time_us)((__uint32_t)(bb->xfc_bus_transport_time_us));
1798 dcn3_0_soc.xfc_xbuf_latency_tolerance_us =
1799 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us)((__uint32_t)(bb->xfc_xbuf_latency_tolerance_us));
1800 dcn3_0_soc.use_urgent_burst_bw =
1801 le32_to_cpu(bb->use_urgent_burst_bw)((__uint32_t)(bb->use_urgent_burst_bw));
1802 dcn3_0_soc.num_states =
1803 le32_to_cpu(bb->num_states)((__uint32_t)(bb->num_states));
1804
1805 for (i = 0; i < dcn3_0_soc.num_states; i++) {
1806 dcn3_0_soc.clock_limits[i].state =
1807 le32_to_cpu(bb->clock_limits[i].state)((__uint32_t)(bb->clock_limits[i].state));
1808 dcn3_0_soc.clock_limits[i].dcfclk_mhz =
1809 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dcfclk_mhz)))
/ ((double) (1 << 16)));
1810 dcn3_0_soc.clock_limits[i].fabricclk_mhz =
1811 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].fabricclk_mhz
))) / ((double) (1 << 16)));
1812 dcn3_0_soc.clock_limits[i].dispclk_mhz =
1813 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dispclk_mhz))
) / ((double) (1 << 16)));
1814 dcn3_0_soc.clock_limits[i].dppclk_mhz =
1815 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dppclk_mhz)))
/ ((double) (1 << 16)));
1816 dcn3_0_soc.clock_limits[i].phyclk_mhz =
1817 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].phyclk_mhz)))
/ ((double) (1 << 16)));
1818 dcn3_0_soc.clock_limits[i].socclk_mhz =
1819 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].socclk_mhz)))
/ ((double) (1 << 16)));
1820 dcn3_0_soc.clock_limits[i].dscclk_mhz =
1821 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dscclk_mhz)))
/ ((double) (1 << 16)));
1822 dcn3_0_soc.clock_limits[i].dram_speed_mts =
1823 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts)(((double) ((__uint32_t)(bb->clock_limits[i].dram_speed_mts
))) / ((double) (1 << 16)));
1824 }
1825 }
1826
1827 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1828 loaded_ip->max_num_dpp = pool->base.pipe_count;
1829 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1830 dcn20_patch_bounding_box(dc, loaded_bb);
1831
1832 if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1833 struct bp_soc_bb_info bb_info = {0};
1834
1835 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1836 if (bb_info.dram_clock_change_latency_100ns > 0)
1837 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1838
1839 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1840 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1841
1842 if (bb_info.dram_sr_exit_latency_100ns > 0)
1843 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1844 }
1845 }
1846
1847 return true1;
1848}
1849
1850static bool_Bool dcn30_split_stream_for_mpc_or_odm(
1851 const struct dc *dc,
1852 struct resource_context *res_ctx,
1853 struct pipe_ctx *pri_pipe,
1854 struct pipe_ctx *sec_pipe,
1855 bool_Bool odm)
1856{
1857 int pipe_idx = sec_pipe->pipe_idx;
1858 const struct resource_pool *pool = dc->res_pool;
1859
1860 *sec_pipe = *pri_pipe;
1861
1862 sec_pipe->pipe_idx = pipe_idx;
1863 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1864 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1865 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1866 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1867 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1868 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1869 sec_pipe->stream_res.dsc = NULL((void *)0);
1870 if (odm) {
1871 if (pri_pipe->next_odm_pipe) {
1872 ASSERT(pri_pipe->next_odm_pipe != sec_pipe)do { if (({ static int __warned; int __ret = !!(!(pri_pipe->
next_odm_pipe != sec_pipe)); if (__ret && !__warned) {
printf("WARNING %s failed at %s:%d\n", "!(pri_pipe->next_odm_pipe != sec_pipe)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1872); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1873 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1874 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1875 }
1876 pri_pipe->next_odm_pipe = sec_pipe;
1877 sec_pipe->prev_odm_pipe = pri_pipe;
1878
1879 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1880 if (sec_pipe->stream->timing.flags.DSC == 1) {
1881 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1882 ASSERT(sec_pipe->stream_res.dsc)do { if (({ static int __warned; int __ret = !!(!(sec_pipe->
stream_res.dsc)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(sec_pipe->stream_res.dsc)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1882); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1883 if (sec_pipe->stream_res.dsc == NULL((void *)0))
1884 return false0;
1885 }
1886 } else {
1887 if (pri_pipe->bottom_pipe) {
1888 ASSERT(pri_pipe->bottom_pipe != sec_pipe)do { if (({ static int __warned; int __ret = !!(!(pri_pipe->
bottom_pipe != sec_pipe)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(pri_pipe->bottom_pipe != sec_pipe)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1888); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1889 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1890 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1891 }
1892 pri_pipe->bottom_pipe = sec_pipe;
1893 sec_pipe->top_pipe = pri_pipe;
1894
1895 ASSERT(pri_pipe->plane_state)do { if (({ static int __warned; int __ret = !!(!(pri_pipe->
plane_state)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(pri_pipe->plane_state)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1895); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1896 }
1897
1898 return true1;
1899}
1900
1901static struct pipe_ctx *dcn30_find_split_pipe(
1902 struct dc *dc,
1903 struct dc_state *context,
1904 int old_index)
1905{
1906 struct pipe_ctx *pipe = NULL((void *)0);
1907 int i;
1908
1909 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL((void *)0)) {
1910 pipe = &context->res_ctx.pipe_ctx[old_index];
1911 pipe->pipe_idx = old_index;
1912 }
1913
1914 if (!pipe)
1915 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1916 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL((void *)0)
1917 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL((void *)0)) {
1918 if (context->res_ctx.pipe_ctx[i].stream == NULL((void *)0)) {
1919 pipe = &context->res_ctx.pipe_ctx[i];
1920 pipe->pipe_idx = i;
1921 break;
1922 }
1923 }
1924 }
1925
1926 /*
1927 * May need to fix pipes getting tossed from 1 opp to another on flip
1928 * Add for debugging transient underflow during topology updates:
1929 * ASSERT(pipe);
1930 */
1931 if (!pipe)
1932 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1933 if (context->res_ctx.pipe_ctx[i].stream == NULL((void *)0)) {
1934 pipe = &context->res_ctx.pipe_ctx[i];
1935 pipe->pipe_idx = i;
1936 break;
1937 }
1938 }
1939
1940 return pipe;
1941}
1942
1943static bool_Bool dcn30_internal_validate_bw(
1944 struct dc *dc,
1945 struct dc_state *context,
1946 display_e2e_pipe_params_st *pipes,
1947 int *pipe_cnt_out,
1948 int *vlevel_out,
1949 bool_Bool fast_validate)
1950{
1951 bool_Bool out = false0;
1952 bool_Bool repopulate_pipes = false0;
1953 int split[MAX_PIPES6] = { 0 };
1954 bool_Bool merge[MAX_PIPES6] = { false0 };
1955 bool_Bool newly_split[MAX_PIPES6] = { false0 };
1956 int pipe_cnt, i, pipe_idx, vlevel;
1957 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1958
1959 ASSERT(pipes)do { if (({ static int __warned; int __ret = !!(!(pipes)); if
(__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(pipes)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 1959); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1960 if (!pipes)
1961 return false0;
1962
1963 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
1964
1965 if (!pipe_cnt) {
1966 out = true1;
1967 goto validate_out;
1968 }
1969
1970 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1971
1972 if (!fast_validate) {
1973 /*
1974 * DML favors voltage over p-state, but we're more interested in
1975 * supporting p-state over voltage. We can't support p-state in
1976 * prefetch mode > 0 so try capping the prefetch mode to start.
1977 */
1978 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1979 dm_allow_self_refresh_and_mclk_switch;
1980 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1981 /* This may adjust vlevel and maxMpcComb */
1982 if (vlevel < context->bw_ctx.dml.soc.num_states)
1983 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1984 }
1985 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1986 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1987 /*
1988 * If mode is unsupported or there's still no p-state support then
1989 * fall back to favoring voltage.
1990 *
1991 * We don't actually support prefetch mode 2, so require that we
1992 * at least support prefetch mode 1.
1993 */
1994 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1995 dm_allow_self_refresh;
1996
1997 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1998 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1999 memset(split, 0, sizeof(split))__builtin_memset((split), (0), (sizeof(split)));
2000 memset(merge, 0, sizeof(merge))__builtin_memset((merge), (0), (sizeof(merge)));
2001 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2002 }
2003 }
2004
2005 dml_log_mode_support_params(&context->bw_ctx.dml);
2006
2007 /* TODO: Need to check calculated vlevel why that fails validation of below resolutions */
2008 if (context->res_ctx.pipe_ctx[0].stream != NULL((void *)0)) {
2009 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
2010 vlevel = 0;
2011 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
2012 vlevel = 0;
2013 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
2014 vlevel = 0;
2015 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
2016 vlevel = 0;
2017 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
2018 vlevel = 0;
2019 }
2020
2021 if (vlevel == context->bw_ctx.dml.soc.num_states)
2022 goto validate_fail;
2023
2024 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2025 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2026 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
2027
2028 if (!pipe->stream)
2029 continue;
2030
2031 /* We only support full screen mpo with ODM */
2032 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2033 && pipe->plane_state && mpo_pipe
2034 && memcmp(&mpo_pipe->plane_res.scl_data.recout,__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout
), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect
)))
2035 &pipe->plane_res.scl_data.recout,__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout
), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect
)))
2036 sizeof(struct rect))__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout
), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect
))) != 0) {
2037 ASSERT(mpo_pipe->plane_state != pipe->plane_state)do { if (({ static int __warned; int __ret = !!(!(mpo_pipe->
plane_state != pipe->plane_state)); if (__ret && !
__warned) { printf("WARNING %s failed at %s:%d\n", "!(mpo_pipe->plane_state != pipe->plane_state)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 2037); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
2038 goto validate_fail;
2039 }
2040 pipe_idx++;
2041 }
2042
2043 /* merge pipes if necessary */
2044 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2045 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2046
2047 /*skip pipes that don't need merging*/
2048 if (!merge[i])
2049 continue;
2050
2051 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2052 if (pipe->prev_odm_pipe) {
2053 /*split off odm pipe*/
2054 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2055 if (pipe->next_odm_pipe)
2056 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2057
2058 pipe->bottom_pipe = NULL((void *)0);
2059 pipe->next_odm_pipe = NULL((void *)0);
2060 pipe->plane_state = NULL((void *)0);
2061 pipe->stream = NULL((void *)0);
2062 pipe->top_pipe = NULL((void *)0);
2063 pipe->prev_odm_pipe = NULL((void *)0);
2064 if (pipe->stream_res.dsc)
2065 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2066 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res))__builtin_memset((&pipe->plane_res), (0), (sizeof(pipe
->plane_res)));
2067 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res))__builtin_memset((&pipe->stream_res), (0), (sizeof(pipe
->stream_res)));
2068 repopulate_pipes = true1;
2069 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2070 struct pipe_ctx *top_pipe = pipe->top_pipe;
2071 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2072
2073 top_pipe->bottom_pipe = bottom_pipe;
2074 if (bottom_pipe)
2075 bottom_pipe->top_pipe = top_pipe;
2076
2077 pipe->top_pipe = NULL((void *)0);
2078 pipe->bottom_pipe = NULL((void *)0);
2079 pipe->plane_state = NULL((void *)0);
2080 pipe->stream = NULL((void *)0);
2081 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res))__builtin_memset((&pipe->plane_res), (0), (sizeof(pipe
->plane_res)));
2082 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res))__builtin_memset((&pipe->stream_res), (0), (sizeof(pipe
->stream_res)));
2083 repopulate_pipes = true1;
2084 } else
2085 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 2085); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0); /* Should never try to merge master pipe */
2086
2087 }
2088
2089 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2090 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2091 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2092 struct pipe_ctx *hsplit_pipe = NULL((void *)0);
2093 bool_Bool odm;
2094 int old_index = -1;
2095
2096 if (!pipe->stream || newly_split[i])
2097 continue;
2098
2099 pipe_idx++;
2100 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2101
2102 if (!pipe->plane_state && !odm)
2103 continue;
2104
2105 if (split[i]) {
2106 if (odm) {
2107 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2108 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2109 else if (old_pipe->next_odm_pipe)
2110 old_index = old_pipe->next_odm_pipe->pipe_idx;
2111 } else {
2112 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2113 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2114 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2115 else if (old_pipe->bottom_pipe &&
2116 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2117 old_index = old_pipe->bottom_pipe->pipe_idx;
2118 }
2119 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2120 ASSERT(hsplit_pipe)do { if (({ static int __warned; int __ret = !!(!(hsplit_pipe
)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(hsplit_pipe)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 2120); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
2121 if (!hsplit_pipe)
2122 goto validate_fail;
2123
2124 if (!dcn30_split_stream_for_mpc_or_odm(
2125 dc, &context->res_ctx,
2126 pipe, hsplit_pipe, odm))
2127 goto validate_fail;
2128
2129 newly_split[hsplit_pipe->pipe_idx] = true1;
2130 repopulate_pipes = true1;
2131 }
2132 if (split[i] == 4) {
2133 struct pipe_ctx *pipe_4to1;
2134
2135 if (odm && old_pipe->next_odm_pipe)
2136 old_index = old_pipe->next_odm_pipe->pipe_idx;
2137 else if (!odm && old_pipe->bottom_pipe &&
2138 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2139 old_index = old_pipe->bottom_pipe->pipe_idx;
2140 else
2141 old_index = -1;
2142 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2143 ASSERT(pipe_4to1)do { if (({ static int __warned; int __ret = !!(!(pipe_4to1))
; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(pipe_4to1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 2143); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
2144 if (!pipe_4to1)
2145 goto validate_fail;
2146 if (!dcn30_split_stream_for_mpc_or_odm(
2147 dc, &context->res_ctx,
2148 pipe, pipe_4to1, odm))
2149 goto validate_fail;
2150 newly_split[pipe_4to1->pipe_idx] = true1;
2151
2152 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2153 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2154 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2155 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2156 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2157 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2158 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2159 else
2160 old_index = -1;
2161 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2162 ASSERT(pipe_4to1)do { if (({ static int __warned; int __ret = !!(!(pipe_4to1))
; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(pipe_4to1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c"
, 2162); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
2163 if (!pipe_4to1)
2164 goto validate_fail;
2165 if (!dcn30_split_stream_for_mpc_or_odm(
2166 dc, &context->res_ctx,
2167 hsplit_pipe, pipe_4to1, odm))
2168 goto validate_fail;
2169 newly_split[pipe_4to1->pipe_idx] = true1;
2170 }
2171 if (odm)
2172 dcn20_build_mapped_resource(dc, context, pipe->stream);
2173 }
2174
2175 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2176 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2177
2178 if (pipe->plane_state) {
2179 if (!resource_build_scaling_params(pipe))
2180 goto validate_fail;
2181 }
2182 }
2183
2184 /* Actual dsc count per stream dsc validation*/
2185 if (!dcn20_validate_dsc(dc, context)) {
2186 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2187 goto validate_fail;
2188 }
2189
2190 if (repopulate_pipes)
2191 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2192 *vlevel_out = vlevel;
2193 *pipe_cnt_out = pipe_cnt;
2194
2195 out = true1;
2196 goto validate_out;
2197
2198validate_fail:
2199 out = false0;
2200
2201validate_out:
2202 return out;
2203}
2204
2205void dcn30_calculate_wm_and_dlg(
2206 struct dc *dc, struct dc_state *context,
2207 display_e2e_pipe_params_st *pipes,
2208 int pipe_cnt,
2209 int vlevel)
2210{
2211 int i, pipe_idx;
2212 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2213 bool_Bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2214 dm_dram_clock_change_unsupported;
2215
2216 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2217 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2218
2219 pipes[0].clks_cfg.voltage = vlevel;
2220 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2221 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2222
2223 /* Set B:
2224 * DCFCLK: 1GHz or min required above 1GHz
2225 * FCLK/UCLK: Max
2226 */
2227 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].valid) {
2228 if (vlevel == 0) {
2229 pipes[0].clks_cfg.voltage = 1;
2230 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2231 }
2232 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.pstate_latency_us;
2233 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_enter_plus_exit_time_us;
2234 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_exit_time_us;
2235 }
2236 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2238 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2239 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2240 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2241 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2242 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2243 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2244
2245 pipes[0].clks_cfg.voltage = vlevel;
2246 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2247
2248 /* Set D:
2249 * DCFCLK: Min Required
2250 * FCLK(proportional to UCLK): 1GHz or Max
2251 * sr_enter_exit = 4, sr_exit = 2us
2252 */
2253 /*
2254 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2255 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2256 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2257 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2258 }
2259 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2260 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2261 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2262 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2263 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2264 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2265 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2266 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2267 */
2268
2269 /* Set C:
2270 * DCFCLK: Min Required
2271 * FCLK(proportional to UCLK): 1GHz or Max
2272 * pstate latency overridden to 5us
2273 */
2274 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].valid) {
2275 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2276 unsigned int min_dram_speed_mts_margin = 160;
2277
2278 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2279
2280 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2281 min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2282
2283 for (i = 3; i > 0; i--) {
2284 if ((min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts) &&
2285 (min_dram_speed_mts - min_dram_speed_mts_margin < dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts))
2286 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2287 }
2288
2289 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_enter_plus_exit_time_us;
2290 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_exit_time_us;
2291 }
2292 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2293 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2294 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2295 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2296 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2297 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2298 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2299 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2300
2301 if (!pstate_en) {
2302 /* The only difference between A and C is p-state latency, if p-state is not supported we want to
2303 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2304 */
2305 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2306 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0x13FFFF;
2307 } else {
2308 /* Set A:
2309 * DCFCLK: Min Required
2310 * FCLK(proportional to UCLK): 1GHz or Max
2311 *
2312 * Set A calculated last so that following calculations are based on Set A
2313 */
2314 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].valid) {
2315 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.pstate_latency_us;
2316 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.sr_enter_plus_exit_time_us;
2317 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.sr_exit_time_us;
2318 }
2319 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2320 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2321 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2322 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2323 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2324 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2325 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2326 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2327 }
2328
2329 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2330
2331 /* Make set D = set A until set D is enabled */
2332 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2333
2334 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2335 if (!context->res_ctx.pipe_ctx[i].stream)
2336 continue;
2337
2338 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2339 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2340
2341 if (dc->config.forced_clocks) {
2342 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2343 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2344 }
2345 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2346 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2347 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2348 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2349
2350 pipe_idx++;
2351 }
2352
2353 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2354
2355 if (!pstate_en)
2356 /* Restore full p-state latency */
2357 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2358 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.pstate_latency_us;
2359}
2360
2361bool_Bool dcn30_validate_bandwidth(struct dc *dc,
2362 struct dc_state *context,
2363 bool_Bool fast_validate)
2364{
2365 bool_Bool out = false0;
2366
2367 BW_VAL_TRACE_SETUP()unsigned long long end_tick = 0; unsigned long long voltage_level_tick
= 0; unsigned long long watermark_tick = 0; unsigned long long
start_tick = dc->debug.bw_val_profile.enable ? dm_get_timestamp
(dc->ctx) : 0;
2368
2369 int vlevel = 0;
2370 int pipe_cnt = 0;
2371 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL(0x0001 | 0x0004));
2372 DC_LOGGER_INIT(dc->ctx->logger);
2373
2374 BW_VAL_TRACE_COUNT()if (dc->debug.bw_val_profile.enable) dc->debug.bw_val_profile
.total_count++;
2375
2376 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2377
2378 if (pipe_cnt == 0)
2379 goto validate_out;
2380
2381 if (!out)
2382 goto validate_fail;
2383
2384 BW_VAL_TRACE_END_VOLTAGE_LEVEL()if (dc->debug.bw_val_profile.enable) voltage_level_tick = dm_get_timestamp
(dc->ctx);
2385
2386 if (fast_validate) {
2387 BW_VAL_TRACE_SKIP(fast)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick
) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug
.bw_val_profile.skip_fast_count++; };
2388 goto validate_out;
2389 }
2390
2391 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2392
2393 BW_VAL_TRACE_END_WATERMARKS()if (dc->debug.bw_val_profile.enable) watermark_tick = dm_get_timestamp
(dc->ctx);
2394
2395 goto validate_out;
2396
2397validate_fail:
2398 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n"
, dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus
[context->bw_ctx.dml.vba.soc.num_states]))
2399 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]))printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n"
, dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus
[context->bw_ctx.dml.vba.soc.num_states]));
2400
2401 BW_VAL_TRACE_SKIP(fail)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick
) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug
.bw_val_profile.skip_fail_count++; };
2402 out = false0;
2403
2404validate_out:
2405 kfree(pipes);
2406
2407 BW_VAL_TRACE_FINISH()if (dc->debug.bw_val_profile.enable) { end_tick = dm_get_timestamp
(dc->ctx); dc->debug.bw_val_profile.total_ticks += end_tick
- start_tick; dc->debug.bw_val_profile.voltage_level_ticks
+= voltage_level_tick - start_tick; if (watermark_tick) { dc
->debug.bw_val_profile.watermark_ticks += watermark_tick -
voltage_level_tick; dc->debug.bw_val_profile.rq_dlg_ticks
+= end_tick - watermark_tick; } };
2408
2409 return out;
2410}
2411
2412static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2413 unsigned int *optimal_dcfclk,
2414 unsigned int *optimal_fclk)
2415{
2416 double bw_from_dram, bw_from_dram1, bw_from_dram2;
2417
2418 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2419 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2420 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2421 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2422
2423 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2424
2425 if (optimal_fclk)
2426 *optimal_fclk = bw_from_dram /
2427 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2428
2429 if (optimal_dcfclk)
2430 *optimal_dcfclk = bw_from_dram /
2431 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2432}
2433
2434void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2435{
2436 unsigned int i, j;
2437 unsigned int num_states = 0;
2438
2439 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES9] = {0};
2440 unsigned int dram_speed_mts[DC__VOLTAGE_STATES9] = {0};
2441 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES9] = {0};
2442 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES9] = {0};
2443
2444 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES9] = {694, 875, 1000, 1200};
2445 unsigned int num_dcfclk_sta_targets = 4;
2446 unsigned int num_uclk_states;
2447
2448 if (dc->ctx->dc_bios->vram_info.num_chans)
2449 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2450
2451 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2452 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2453
2454 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2455 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2456
2457 if (bw_params->clk_table.entries[0].memclk_mhz) {
2458 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2459
2460 for (i = 0; i < MAX_NUM_DPM_LVL8; i++) {
2461 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2462 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2463 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2464 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2465 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2466 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2467 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2468 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2469 }
2470
2471 if (!max_dcfclk_mhz)
2472 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
2473 if (!max_dispclk_mhz)
2474 max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
2475 if (!max_dppclk_mhz)
2476 max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
2477 if (!max_phyclk_mhz)
2478 max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
2479
2480 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2481 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2482 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2483 num_dcfclk_sta_targets++;
2484 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2485 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2486 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2487 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2488 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2489 break;
2490 }
2491 }
2492 // Update size of array since we "removed" duplicates
2493 num_dcfclk_sta_targets = i + 1;
2494 }
2495
2496 num_uclk_states = bw_params->clk_table.num_entries;
2497
2498 // Calculate optimal dcfclk for each uclk
2499 for (i = 0; i < num_uclk_states; i++) {
2500 get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2501 &optimal_dcfclk_for_uclk[i], NULL((void *)0));
2502 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2503 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2504 }
2505 }
2506
2507 // Calculate optimal uclk for each dcfclk sta target
2508 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2509 for (j = 0; j < num_uclk_states; j++) {
2510 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2511 optimal_uclk_for_dcfclk_sta_targets[i] =
2512 bw_params->clk_table.entries[j].memclk_mhz * 16;
2513 break;
2514 }
2515 }
2516 }
2517
2518 i = 0;
2519 j = 0;
2520 // create the final dcfclk and uclk table
2521 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES9) {
2522 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2523 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2524 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2525 } else {
2526 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2527 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2528 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2529 } else {
2530 j = num_uclk_states;
2531 }
2532 }
2533 }
2534
2535 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES9) {
2536 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2537 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2538 }
2539
2540 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES9 &&
2541 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2542 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2543 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2544 }
2545
2546 dcn3_0_soc.num_states = num_states;
2547 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2548 dcn3_0_soc.clock_limits[i].state = i;
2549 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2550 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2551 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2552
2553 /* Fill all states with max values of all other clocks */
2554 dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2555 dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
2556 dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
2557 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2558 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2559 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2560 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2561 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2562 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2563 }
2564 /* re-init DML with updated bb */
2565 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2566 if (dc->current_state)
2567 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2568 }
2569
2570 /* re-init DML with updated bb */
2571 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2572 if (dc->current_state)
2573 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2574}
2575
2576static const struct resource_funcs dcn30_res_pool_funcs = {
2577 .destroy = dcn30_destroy_resource_pool,
2578 .link_enc_create = dcn30_link_encoder_create,
2579 .panel_cntl_create = dcn30_panel_cntl_create,
2580 .validate_bandwidth = dcn30_validate_bandwidth,
2581 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2582 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2583 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2584 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2585 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2586 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2587 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2588 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2589 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2590 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2591 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2592 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2593 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2594};
2595
2596static bool_Bool dcn30_resource_construct(
2597 uint8_t num_virtual_links,
2598 struct dc *dc,
2599 struct dcn30_resource_pool *pool)
2600{
2601 int i;
2602 struct dc_context *ctx = dc->ctx;
2603 struct irq_service_init_data init_data;
2604
2605 ctx->dc_bios->regs = &bios_regs;
2606
2607 pool->base.res_cap = &res_cap_dcn3;
2608
2609 pool->base.funcs = &dcn30_res_pool_funcs;
2610
2611 /*************************************************
2612 * Resource + asic cap harcoding *
2613 *************************************************/
2614 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1;
2615 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2616 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2617 dc->caps.max_downscale_ratio = 600;
2618 dc->caps.i2c_speed_in_khz = 100;
2619 dc->caps.max_cursor_size = 256;
2620 dc->caps.dmdata_alloc_size = 2048;
2621
2622 dc->caps.max_slave_planes = 1;
2623 dc->caps.post_blend_color_processing = true1;
2624 dc->caps.force_dp_tps4_for_cp2520 = true1;
2625 dc->caps.extended_aux_timeout_support = true1;
2626 dc->caps.dmcub_support = true1;
2627
2628 /* Color pipeline capabilities */
2629 dc->caps.color.dpp.dcn_arch = 1;
2630 dc->caps.color.dpp.input_lut_shared = 0;
2631 dc->caps.color.dpp.icsc = 1;
2632 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2633 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2634 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2635 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2636 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2637 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2638 dc->caps.color.dpp.post_csc = 1;
2639 dc->caps.color.dpp.gamma_corr = 1;
2640
2641 dc->caps.color.dpp.hw_3d_lut = 1;
2642 dc->caps.color.dpp.ogam_ram = 1;
2643 // no OGAM ROM on DCN3
2644 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2645 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2646 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2647 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2648 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2649 dc->caps.color.dpp.ocsc = 0;
2650
2651 dc->caps.color.mpc.gamut_remap = 1;
2652 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2653 dc->caps.color.mpc.ogam_ram = 1;
2654 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2655 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2656 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2657 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2658 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2659 dc->caps.color.mpc.ocsc = 1;
2660
2661 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2662 dc->debug = debug_defaults_drv;
2663 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2664 dc->debug = debug_defaults_diags;
2665 } else
2666 dc->debug = debug_defaults_diags;
2667 // Init the vm_helper
2668 if (dc->vm_helper)
2669 vm_helper_init(dc->vm_helper, 16);
2670
2671 /*************************************************
2672 * Create resources *
2673 *************************************************/
2674
2675 /* Clock Sources for Pixel Clock*/
2676 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2677 dcn30_clock_source_create(ctx, ctx->dc_bios,
2678 CLOCK_SOURCE_COMBO_PHY_PLL0,
2679 &clk_src_regs[0], false0);
2680 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2681 dcn30_clock_source_create(ctx, ctx->dc_bios,
2682 CLOCK_SOURCE_COMBO_PHY_PLL1,
2683 &clk_src_regs[1], false0);
2684 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2685 dcn30_clock_source_create(ctx, ctx->dc_bios,
2686 CLOCK_SOURCE_COMBO_PHY_PLL2,
2687 &clk_src_regs[2], false0);
2688 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2689 dcn30_clock_source_create(ctx, ctx->dc_bios,
2690 CLOCK_SOURCE_COMBO_PHY_PLL3,
2691 &clk_src_regs[3], false0);
2692 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2693 dcn30_clock_source_create(ctx, ctx->dc_bios,
2694 CLOCK_SOURCE_COMBO_PHY_PLL4,
2695 &clk_src_regs[4], false0);
2696 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2697 dcn30_clock_source_create(ctx, ctx->dc_bios,
2698 CLOCK_SOURCE_COMBO_PHY_PLL5,
2699 &clk_src_regs[5], false0);
2700
2701 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2702
2703 /* todo: not reuse phy_pll registers */
2704 pool->base.dp_clock_source =
2705 dcn30_clock_source_create(ctx, ctx->dc_bios,
2706 CLOCK_SOURCE_ID_DP_DTO,
2707 &clk_src_regs[0], true1);
2708
2709 for (i = 0; i < pool->base.clk_src_count; i++) {
2710 if (pool->base.clock_sources[i] == NULL((void *)0)) {
2711 dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n");
2712 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2712); do
{} while (0); } while (0);
2713 goto create_fail;
2714 }
2715 }
2716
2717 /* DCCG */
2718 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2719 if (pool->base.dccg == NULL((void *)0)) {
2720 dm_error("DC: failed to create dccg!\n")__drm_err("DC: failed to create dccg!\n");
2721 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2721); do
{} while (0); } while (0);
2722 goto create_fail;
2723 }
2724
2725 /* PP Lib and SMU interfaces */
2726 init_soc_bounding_box(dc, pool);
2727
2728 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2729
2730 /* IRQ */
2731 init_data.ctx = dc->ctx;
2732 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2733 if (!pool->base.irqs)
2734 goto create_fail;
2735
2736 /* HUBBUB */
2737 pool->base.hubbub = dcn30_hubbub_create(ctx);
2738 if (pool->base.hubbub == NULL((void *)0)) {
2739 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2739); do
{} while (0); } while (0);
2740 dm_error("DC: failed to create hubbub!\n")__drm_err("DC: failed to create hubbub!\n");
2741 goto create_fail;
2742 }
2743
2744 /* HUBPs, DPPs, OPPs and TGs */
2745 for (i = 0; i < pool->base.pipe_count; i++) {
2746 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2747 if (pool->base.hubps[i] == NULL((void *)0)) {
2748 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2748); do
{} while (0); } while (0);
2749 dm_error(__drm_err("DC: failed to create hubps!\n")
2750 "DC: failed to create hubps!\n")__drm_err("DC: failed to create hubps!\n");
2751 goto create_fail;
2752 }
2753
2754 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2755 if (pool->base.dpps[i] == NULL((void *)0)) {
2756 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2756); do
{} while (0); } while (0);
2757 dm_error(__drm_err("DC: failed to create dpps!\n")
2758 "DC: failed to create dpps!\n")__drm_err("DC: failed to create dpps!\n");
2759 goto create_fail;
2760 }
2761 }
2762
2763 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2764 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2765 if (pool->base.opps[i] == NULL((void *)0)) {
2766 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2766); do
{} while (0); } while (0);
2767 dm_error(__drm_err("DC: failed to create output pixel processor!\n")
2768 "DC: failed to create output pixel processor!\n")__drm_err("DC: failed to create output pixel processor!\n");
2769 goto create_fail;
2770 }
2771 }
2772
2773 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2774 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2775 ctx, i);
2776 if (pool->base.timing_generators[i] == NULL((void *)0)) {
2777 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2777); do
{} while (0); } while (0);
2778 dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n");
2779 goto create_fail;
2780 }
2781 }
2782 pool->base.timing_generator_count = i;
2783 /* PSR */
2784 pool->base.psr = dmub_psr_create(ctx);
2785
2786 if (pool->base.psr == NULL((void *)0)) {
2787 dm_error("DC: failed to create PSR obj!\n")__drm_err("DC: failed to create PSR obj!\n");
2788 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2788); do
{} while (0); } while (0);
2789 goto create_fail;
2790 }
2791
2792 /* ABM */
2793 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2794 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2795 &abm_regs[i],
2796 &abm_shift,
2797 &abm_mask);
2798 if (pool->base.multiple_abms[i] == NULL((void *)0)) {
2799 dm_error("DC: failed to create abm for pipe %d!\n", i)__drm_err("DC: failed to create abm for pipe %d!\n", i);
2800 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2800); do
{} while (0); } while (0);
2801 goto create_fail;
2802 }
2803 }
2804 /* MPC and DSC */
2805 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2806 if (pool->base.mpc == NULL((void *)0)) {
2807 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2807); do
{} while (0); } while (0);
2808 dm_error("DC: failed to create mpc!\n")__drm_err("DC: failed to create mpc!\n");
2809 goto create_fail;
2810 }
2811
2812 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2813 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2814 if (pool->base.dscs[i] == NULL((void *)0)) {
2815 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2815); do
{} while (0); } while (0);
2816 dm_error("DC: failed to create display stream compressor %d!\n", i)__drm_err("DC: failed to create display stream compressor %d!\n"
, i);
2817 goto create_fail;
2818 }
2819 }
2820
2821 /* DWB and MMHUBBUB */
2822 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2823 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2823); do
{} while (0); } while (0);
2824 dm_error("DC: failed to create dwbc!\n")__drm_err("DC: failed to create dwbc!\n");
2825 goto create_fail;
2826 }
2827
2828 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2829 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2829); do
{} while (0); } while (0);
2830 dm_error("DC: failed to create mcif_wb!\n")__drm_err("DC: failed to create mcif_wb!\n");
2831 goto create_fail;
2832 }
2833
2834 /* AUX and I2C */
2835 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2836 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2837 if (pool->base.engines[i] == NULL((void *)0)) {
2838 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2838); do
{} while (0); } while (0);
2839 dm_error(__drm_err("DC:failed to create aux engine!!\n")
2840 "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n");
2841 goto create_fail;
2842 }
2843 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2844 if (pool->base.hw_i2cs[i] == NULL((void *)0)) {
2845 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2845); do
{} while (0); } while (0);
2846 dm_error(__drm_err("DC:failed to create hw i2c!!\n")
2847 "DC:failed to create hw i2c!!\n")__drm_err("DC:failed to create hw i2c!!\n");
2848 goto create_fail;
2849 }
2850 pool->base.sw_i2cs[i] = NULL((void *)0);
2851 }
2852
2853 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2854 if (!resource_construct(num_virtual_links, dc, &pool->base,
2855 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) ?
2856 &res_create_funcs : &res_create_maximus_funcs)))
2857 goto create_fail;
2858
2859 /* HW Sequencer and Plane caps */
2860 dcn30_hw_sequencer_construct(dc);
2861
2862 dc->caps.max_planes = pool->base.pipe_count;
2863
2864 for (i = 0; i < dc->caps.max_planes; ++i)
2865 dc->caps.planes[i] = plane_cap;
2866
2867 dc->cap_funcs = cap_funcs;
2868
2869 return true1;
2870
2871create_fail:
2872
2873 dcn30_resource_destruct(pool);
2874
2875 return false0;
2876}
2877
2878struct resource_pool *dcn30_create_resource_pool(
2879 const struct dc_init_data *init_data,
2880 struct dc *dc)
2881{
2882 struct dcn30_resource_pool *pool =
2883 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL(0x0001 | 0x0004));
2884
2885 if (!pool)
2886 return NULL((void *)0);
2887
2888 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2889 return &pool->base;
2890
2891 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 2891); do
{} while (0); } while (0);
2892 kfree(pool);
2893 return NULL((void *)0);
2894}
←

/usr/src/sys/dev/pci/drm/include/linux/slab.h

1/* Public domain. */
2
3#ifndef _LINUX_SLAB_H
4#define _LINUX_SLAB_H
5
6#include <sys/types.h>
7#include <sys/malloc.h>
8
9#include <linux/types.h>
10#include <linux/workqueue.h>
11#include <linux/gfp.h>
12
13#include <linux/processor.h> /* for CACHELINESIZE */
14
15static inline void *
16kmalloc(size_t size, int flags)
17{
18 return malloc(size, M_DRM145, flags);
19}
20
21static inline void *
22kmalloc_array(size_t n, size_t size, int flags)
23{
24 if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
25 return NULL((void *)0);
26 return malloc(n * size, M_DRM145, flags);
27}
28
29static inline void *
30kcalloc(size_t n, size_t size, int flags)
31{
32 if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
33 return NULL((void *)0);
34 return malloc(n * size, M_DRM145, flags | M_ZERO0x0008);
35}
36
37static inline void *
38kzalloc(size_t size, int flags)
39{
40 return malloc(size, M_DRM145, flags | M_ZERO0x0008);
4
←
Memory is allocated
→
41}
42
43static inline void
44kfree(const void *objp)
45{
46 free((void *)objp, M_DRM145, 0);
47}
48
49#endif