File: | dev/pci/drm/amd/display/dc/dce/dce_clock_source.c |
Warning: | line 1129, column 2 Value stored to 'clk_src' is never read |
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1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include <linux/slab.h> |
27 | |
28 | #include "dm_services.h" |
29 | |
30 | |
31 | #include "dc_types.h" |
32 | #include "core_types.h" |
33 | |
34 | #include "include/grph_object_id.h" |
35 | #include "include/logger_interface.h" |
36 | |
37 | #include "dce_clock_source.h" |
38 | #include "clk_mgr.h" |
39 | |
40 | #include "reg_helper.h" |
41 | |
42 | #define REG(reg)(clk_src->regs->reg)\ |
43 | (clk_src->regs->reg) |
44 | |
45 | #define CTXclk_src->base.ctx \ |
46 | clk_src->base.ctx |
47 | |
48 | #define DC_LOGGER_INIT() |
49 | |
50 | #undef FN |
51 | #define FN(reg_name, field_name)clk_src->cs_shift->field_name, clk_src->cs_mask-> field_name \ |
52 | clk_src->cs_shift->field_name, clk_src->cs_mask->field_name |
53 | |
54 | #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM6 6 |
55 | #define CALC_PLL_CLK_SRC_ERR_TOLERANCE1 1 |
56 | #define MAX_PLL_CALC_ERROR0xFFFFFFFF 0xFFFFFFFF |
57 | |
58 | #define NUM_ELEMENTS(a)(sizeof(a) / sizeof((a)[0])) (sizeof(a) / sizeof((a)[0])) |
59 | |
60 | static const struct spread_spectrum_data *get_ss_data_entry( |
61 | struct dce110_clk_src *clk_src, |
62 | enum amd_signal_type signal, |
63 | uint32_t pix_clk_khz) |
64 | { |
65 | |
66 | uint32_t entrys_num; |
67 | uint32_t i; |
68 | struct spread_spectrum_data *ss_parm = NULL((void *)0); |
69 | struct spread_spectrum_data *ret = NULL((void *)0); |
70 | |
71 | switch (signal) { |
72 | case SIGNAL_TYPE_DVI_SINGLE_LINK: |
73 | case SIGNAL_TYPE_DVI_DUAL_LINK: |
74 | ss_parm = clk_src->dvi_ss_params; |
75 | entrys_num = clk_src->dvi_ss_params_cnt; |
76 | break; |
77 | |
78 | case SIGNAL_TYPE_HDMI_TYPE_A: |
79 | ss_parm = clk_src->hdmi_ss_params; |
80 | entrys_num = clk_src->hdmi_ss_params_cnt; |
81 | break; |
82 | |
83 | case SIGNAL_TYPE_LVDS: |
84 | ss_parm = clk_src->lvds_ss_params; |
85 | entrys_num = clk_src->lvds_ss_params_cnt; |
86 | break; |
87 | |
88 | case SIGNAL_TYPE_DISPLAY_PORT: |
89 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
90 | case SIGNAL_TYPE_EDP: |
91 | case SIGNAL_TYPE_VIRTUAL: |
92 | ss_parm = clk_src->dp_ss_params; |
93 | entrys_num = clk_src->dp_ss_params_cnt; |
94 | break; |
95 | |
96 | default: |
97 | ss_parm = NULL((void *)0); |
98 | entrys_num = 0; |
99 | break; |
100 | } |
101 | |
102 | if (ss_parm == NULL((void *)0)) |
103 | return ret; |
104 | |
105 | for (i = 0; i < entrys_num; ++i, ++ss_parm) { |
106 | if (ss_parm->freq_range_khz >= pix_clk_khz) { |
107 | ret = ss_parm; |
108 | break; |
109 | } |
110 | } |
111 | |
112 | return ret; |
113 | } |
114 | |
115 | /** |
116 | * Function: calculate_fb_and_fractional_fb_divider |
117 | * |
118 | * * DESCRIPTION: Calculates feedback and fractional feedback dividers values |
119 | * |
120 | *PARAMETERS: |
121 | * targetPixelClock Desired frequency in 100 Hz |
122 | * ref_divider Reference divider (already known) |
123 | * postDivider Post Divider (already known) |
124 | * feedback_divider_param Pointer where to store |
125 | * calculated feedback divider value |
126 | * fract_feedback_divider_param Pointer where to store |
127 | * calculated fract feedback divider value |
128 | * |
129 | *RETURNS: |
130 | * It fills the locations pointed by feedback_divider_param |
131 | * and fract_feedback_divider_param |
132 | * It returns - true if feedback divider not 0 |
133 | * - false should never happen) |
134 | */ |
135 | static bool_Bool calculate_fb_and_fractional_fb_divider( |
136 | struct calc_pll_clock_source *calc_pll_cs, |
137 | uint32_t target_pix_clk_100hz, |
138 | uint32_t ref_divider, |
139 | uint32_t post_divider, |
140 | uint32_t *feedback_divider_param, |
141 | uint32_t *fract_feedback_divider_param) |
142 | { |
143 | uint64_t feedback_divider; |
144 | |
145 | feedback_divider = |
146 | (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; |
147 | feedback_divider *= 10; |
148 | /* additional factor, since we divide by 10 afterwards */ |
149 | feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); |
150 | feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); |
151 | |
152 | /*Round to the number of precision |
153 | * The following code replace the old code (ullfeedbackDivider + 5)/10 |
154 | * for example if the difference between the number |
155 | * of fractional feedback decimal point and the fractional FB Divider precision |
156 | * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ |
157 | |
158 | feedback_divider += 5ULL * |
159 | calc_pll_cs->fract_fb_divider_precision_factor; |
160 | feedback_divider = |
161 | div_u64(feedback_divider, |
162 | calc_pll_cs->fract_fb_divider_precision_factor * 10); |
163 | feedback_divider *= (uint64_t) |
164 | (calc_pll_cs->fract_fb_divider_precision_factor); |
165 | |
166 | *feedback_divider_param = |
167 | div_u64_rem( |
168 | feedback_divider, |
169 | calc_pll_cs->fract_fb_divider_factor, |
170 | fract_feedback_divider_param); |
171 | |
172 | if (*feedback_divider_param != 0) |
173 | return true1; |
174 | return false0; |
175 | } |
176 | |
177 | /** |
178 | *calc_fb_divider_checking_tolerance |
179 | * |
180 | *DESCRIPTION: Calculates Feedback and Fractional Feedback divider values |
181 | * for passed Reference and Post divider, checking for tolerance. |
182 | *PARAMETERS: |
183 | * pll_settings Pointer to structure |
184 | * ref_divider Reference divider (already known) |
185 | * postDivider Post Divider (already known) |
186 | * tolerance Tolerance for Calculated Pixel Clock to be within |
187 | * |
188 | *RETURNS: |
189 | * It fills the PLLSettings structure with PLL Dividers values |
190 | * if calculated values are within required tolerance |
191 | * It returns - true if error is within tolerance |
192 | * - false if error is not within tolerance |
193 | */ |
194 | static bool_Bool calc_fb_divider_checking_tolerance( |
195 | struct calc_pll_clock_source *calc_pll_cs, |
196 | struct pll_settings *pll_settings, |
197 | uint32_t ref_divider, |
198 | uint32_t post_divider, |
199 | uint32_t tolerance) |
200 | { |
201 | uint32_t feedback_divider; |
202 | uint32_t fract_feedback_divider; |
203 | uint32_t actual_calculated_clock_100hz; |
204 | uint32_t abs_err; |
205 | uint64_t actual_calc_clk_100hz; |
206 | |
207 | calculate_fb_and_fractional_fb_divider( |
208 | calc_pll_cs, |
209 | pll_settings->adjusted_pix_clk_100hz, |
210 | ref_divider, |
211 | post_divider, |
212 | &feedback_divider, |
213 | &fract_feedback_divider); |
214 | |
215 | /*Actual calculated value*/ |
216 | actual_calc_clk_100hz = (uint64_t)feedback_divider * |
217 | calc_pll_cs->fract_fb_divider_factor + |
218 | fract_feedback_divider; |
219 | actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10; |
220 | actual_calc_clk_100hz = |
221 | div_u64(actual_calc_clk_100hz, |
222 | ref_divider * post_divider * |
223 | calc_pll_cs->fract_fb_divider_factor); |
224 | |
225 | actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); |
226 | |
227 | abs_err = (actual_calculated_clock_100hz > |
228 | pll_settings->adjusted_pix_clk_100hz) |
229 | ? actual_calculated_clock_100hz - |
230 | pll_settings->adjusted_pix_clk_100hz |
231 | : pll_settings->adjusted_pix_clk_100hz - |
232 | actual_calculated_clock_100hz; |
233 | |
234 | if (abs_err <= tolerance) { |
235 | /*found good values*/ |
236 | pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; |
237 | pll_settings->reference_divider = ref_divider; |
238 | pll_settings->feedback_divider = feedback_divider; |
239 | pll_settings->fract_feedback_divider = fract_feedback_divider; |
240 | pll_settings->pix_clk_post_divider = post_divider; |
241 | pll_settings->calculated_pix_clk_100hz = |
242 | actual_calculated_clock_100hz; |
243 | pll_settings->vco_freq = |
244 | actual_calculated_clock_100hz * post_divider / 10; |
245 | return true1; |
246 | } |
247 | return false0; |
248 | } |
249 | |
250 | static bool_Bool calc_pll_dividers_in_range( |
251 | struct calc_pll_clock_source *calc_pll_cs, |
252 | struct pll_settings *pll_settings, |
253 | uint32_t min_ref_divider, |
254 | uint32_t max_ref_divider, |
255 | uint32_t min_post_divider, |
256 | uint32_t max_post_divider, |
257 | uint32_t err_tolerance) |
258 | { |
259 | uint32_t ref_divider; |
260 | uint32_t post_divider; |
261 | uint32_t tolerance; |
262 | |
263 | /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% |
264 | * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ |
265 | tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / |
266 | 100000; |
267 | if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE1) |
268 | tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE1; |
269 | |
270 | for ( |
271 | post_divider = max_post_divider; |
272 | post_divider >= min_post_divider; |
273 | --post_divider) { |
274 | for ( |
275 | ref_divider = min_ref_divider; |
276 | ref_divider <= max_ref_divider; |
277 | ++ref_divider) { |
278 | if (calc_fb_divider_checking_tolerance( |
279 | calc_pll_cs, |
280 | pll_settings, |
281 | ref_divider, |
282 | post_divider, |
283 | tolerance)) { |
284 | return true1; |
285 | } |
286 | } |
287 | } |
288 | |
289 | return false0; |
290 | } |
291 | |
292 | static uint32_t calculate_pixel_clock_pll_dividers( |
293 | struct calc_pll_clock_source *calc_pll_cs, |
294 | struct pll_settings *pll_settings) |
295 | { |
296 | uint32_t err_tolerance; |
297 | uint32_t min_post_divider; |
298 | uint32_t max_post_divider; |
299 | uint32_t min_ref_divider; |
300 | uint32_t max_ref_divider; |
301 | |
302 | if (pll_settings->adjusted_pix_clk_100hz == 0) { |
303 | DC_LOG_ERROR(__drm_err("%s Bad requested pixel clock", __func__) |
304 | "%s Bad requested pixel clock", __func__)__drm_err("%s Bad requested pixel clock", __func__); |
305 | return MAX_PLL_CALC_ERROR0xFFFFFFFF; |
306 | } |
307 | |
308 | /* 1) Find Post divider ranges */ |
309 | if (pll_settings->pix_clk_post_divider) { |
310 | min_post_divider = pll_settings->pix_clk_post_divider; |
311 | max_post_divider = pll_settings->pix_clk_post_divider; |
312 | } else { |
313 | min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; |
314 | if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < |
315 | calc_pll_cs->min_vco_khz * 10) { |
316 | min_post_divider = calc_pll_cs->min_vco_khz * 10 / |
317 | pll_settings->adjusted_pix_clk_100hz; |
318 | if ((min_post_divider * |
319 | pll_settings->adjusted_pix_clk_100hz) < |
320 | calc_pll_cs->min_vco_khz * 10) |
321 | min_post_divider++; |
322 | } |
323 | |
324 | max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; |
325 | if (max_post_divider * pll_settings->adjusted_pix_clk_100hz |
326 | > calc_pll_cs->max_vco_khz * 10) |
327 | max_post_divider = calc_pll_cs->max_vco_khz * 10 / |
328 | pll_settings->adjusted_pix_clk_100hz; |
329 | } |
330 | |
331 | /* 2) Find Reference divider ranges |
332 | * When SS is enabled, or for Display Port even without SS, |
333 | * pll_settings->referenceDivider is not zero. |
334 | * So calculate PPLL FB and fractional FB divider |
335 | * using the passed reference divider*/ |
336 | |
337 | if (pll_settings->reference_divider) { |
338 | min_ref_divider = pll_settings->reference_divider; |
339 | max_ref_divider = pll_settings->reference_divider; |
340 | } else { |
341 | min_ref_divider = ((calc_pll_cs->ref_freq_khz |
342 | / calc_pll_cs->max_pll_input_freq_khz) |
343 | > calc_pll_cs->min_pll_ref_divider) |
344 | ? calc_pll_cs->ref_freq_khz |
345 | / calc_pll_cs->max_pll_input_freq_khz |
346 | : calc_pll_cs->min_pll_ref_divider; |
347 | |
348 | max_ref_divider = ((calc_pll_cs->ref_freq_khz |
349 | / calc_pll_cs->min_pll_input_freq_khz) |
350 | < calc_pll_cs->max_pll_ref_divider) |
351 | ? calc_pll_cs->ref_freq_khz / |
352 | calc_pll_cs->min_pll_input_freq_khz |
353 | : calc_pll_cs->max_pll_ref_divider; |
354 | } |
355 | |
356 | /* If some parameters are invalid we could have scenario when "min">"max" |
357 | * which produced endless loop later. |
358 | * We should investigate why we get the wrong parameters. |
359 | * But to follow the similar logic when "adjustedPixelClock" is set to be 0 |
360 | * it is better to return here than cause system hang/watchdog timeout later. |
361 | * ## SVS Wed 15 Jul 2009 */ |
362 | |
363 | if (min_post_divider > max_post_divider) { |
364 | DC_LOG_ERROR(__drm_err("%s Post divider range is invalid", __func__) |
365 | "%s Post divider range is invalid", __func__)__drm_err("%s Post divider range is invalid", __func__); |
366 | return MAX_PLL_CALC_ERROR0xFFFFFFFF; |
367 | } |
368 | |
369 | if (min_ref_divider > max_ref_divider) { |
370 | DC_LOG_ERROR(__drm_err("%s Reference divider range is invalid", __func__) |
371 | "%s Reference divider range is invalid", __func__)__drm_err("%s Reference divider range is invalid", __func__); |
372 | return MAX_PLL_CALC_ERROR0xFFFFFFFF; |
373 | } |
374 | |
375 | /* 3) Try to find PLL dividers given ranges |
376 | * starting with minimal error tolerance. |
377 | * Increase error tolerance until PLL dividers found*/ |
378 | err_tolerance = MAX_PLL_CALC_ERROR0xFFFFFFFF; |
379 | |
380 | while (!calc_pll_dividers_in_range( |
381 | calc_pll_cs, |
382 | pll_settings, |
383 | min_ref_divider, |
384 | max_ref_divider, |
385 | min_post_divider, |
386 | max_post_divider, |
387 | err_tolerance)) |
388 | err_tolerance += (err_tolerance > 10) |
389 | ? (err_tolerance / 10) |
390 | : 1; |
391 | |
392 | return err_tolerance; |
393 | } |
394 | |
395 | static bool_Bool pll_adjust_pix_clk( |
396 | struct dce110_clk_src *clk_src, |
397 | struct pixel_clk_params *pix_clk_params, |
398 | struct pll_settings *pll_settings) |
399 | { |
400 | uint32_t actual_pix_clk_100hz = 0; |
401 | uint32_t requested_clk_100hz = 0; |
402 | struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { |
403 | 0 }; |
404 | enum bp_result bp_result; |
405 | switch (pix_clk_params->signal_type) { |
406 | case SIGNAL_TYPE_HDMI_TYPE_A: { |
407 | requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; |
408 | if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { |
409 | switch (pix_clk_params->color_depth) { |
410 | case COLOR_DEPTH_101010: |
411 | requested_clk_100hz = (requested_clk_100hz * 5) >> 2; |
412 | break; /* x1.25*/ |
413 | case COLOR_DEPTH_121212: |
414 | requested_clk_100hz = (requested_clk_100hz * 6) >> 2; |
415 | break; /* x1.5*/ |
416 | case COLOR_DEPTH_161616: |
417 | requested_clk_100hz = requested_clk_100hz * 2; |
418 | break; /* x2.0*/ |
419 | default: |
420 | break; |
421 | } |
422 | } |
423 | actual_pix_clk_100hz = requested_clk_100hz; |
424 | } |
425 | break; |
426 | |
427 | case SIGNAL_TYPE_DISPLAY_PORT: |
428 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
429 | case SIGNAL_TYPE_EDP: |
430 | requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; |
431 | actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; |
432 | break; |
433 | |
434 | default: |
435 | requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; |
436 | actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; |
437 | break; |
438 | } |
439 | |
440 | bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; |
441 | bp_adjust_pixel_clock_params. |
442 | encoder_object_id = pix_clk_params->encoder_object_id; |
443 | bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; |
444 | bp_adjust_pixel_clock_params. |
445 | ss_enable = pix_clk_params->flags.ENABLE_SS; |
446 | bp_result = clk_src->bios->funcs->adjust_pixel_clock( |
447 | clk_src->bios, &bp_adjust_pixel_clock_params); |
448 | if (bp_result == BP_RESULT_OK) { |
449 | pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; |
450 | pll_settings->adjusted_pix_clk_100hz = |
451 | bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; |
452 | pll_settings->reference_divider = |
453 | bp_adjust_pixel_clock_params.reference_divider; |
454 | pll_settings->pix_clk_post_divider = |
455 | bp_adjust_pixel_clock_params.pixel_clock_post_divider; |
456 | |
457 | return true1; |
458 | } |
459 | |
460 | return false0; |
461 | } |
462 | |
463 | /** |
464 | * Calculate PLL Dividers for given Clock Value. |
465 | * First will call VBIOS Adjust Exec table to check if requested Pixel clock |
466 | * will be Adjusted based on usage. |
467 | * Then it will calculate PLL Dividers for this Adjusted clock using preferred |
468 | * method (Maximum VCO frequency). |
469 | * |
470 | * \return |
471 | * Calculation error in units of 0.01% |
472 | */ |
473 | |
474 | static uint32_t dce110_get_pix_clk_dividers_helper ( |
475 | struct dce110_clk_src *clk_src, |
476 | struct pll_settings *pll_settings, |
477 | struct pixel_clk_params *pix_clk_params) |
478 | { |
479 | uint32_t field = 0; |
480 | uint32_t pll_calc_error = MAX_PLL_CALC_ERROR0xFFFFFFFF; |
481 | DC_LOGGER_INIT(); |
482 | /* Check if reference clock is external (not pcie/xtalin) |
483 | * HW Dce80 spec: |
484 | * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB |
485 | * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ |
486 | REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field)generic_reg_get(clk_src->base.ctx, (clk_src->regs->PLL_CNTL ), clk_src->cs_shift->PLL_REF_DIV_SRC, clk_src->cs_mask ->PLL_REF_DIV_SRC, &field); |
487 | pll_settings->use_external_clk = (field > 1); |
488 | |
489 | /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always |
490 | * (we do not care any more from SI for some older DP Sink which |
491 | * does not report SS support, no known issues) */ |
492 | if ((pix_clk_params->flags.ENABLE_SS) || |
493 | (dc_is_dp_signal(pix_clk_params->signal_type))) { |
494 | |
495 | const struct spread_spectrum_data *ss_data = get_ss_data_entry( |
496 | clk_src, |
497 | pix_clk_params->signal_type, |
498 | pll_settings->adjusted_pix_clk_100hz / 10); |
499 | |
500 | if (NULL((void *)0) != ss_data) |
501 | pll_settings->ss_percentage = ss_data->percentage; |
502 | } |
503 | |
504 | /* Check VBIOS AdjustPixelClock Exec table */ |
505 | if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { |
506 | /* Should never happen, ASSERT and fill up values to be able |
507 | * to continue. */ |
508 | DC_LOG_ERROR(__drm_err("%s: Failed to adjust pixel clock!!", __func__) |
509 | "%s: Failed to adjust pixel clock!!", __func__)__drm_err("%s: Failed to adjust pixel clock!!", __func__); |
510 | pll_settings->actual_pix_clk_100hz = |
511 | pix_clk_params->requested_pix_clk_100hz; |
512 | pll_settings->adjusted_pix_clk_100hz = |
513 | pix_clk_params->requested_pix_clk_100hz; |
514 | |
515 | if (dc_is_dp_signal(pix_clk_params->signal_type)) |
516 | pll_settings->adjusted_pix_clk_100hz = 1000000; |
517 | } |
518 | |
519 | /* Calculate Dividers */ |
520 | if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) |
521 | /*Calculate Dividers by HDMI object, no SS case or SS case */ |
522 | pll_calc_error = |
523 | calculate_pixel_clock_pll_dividers( |
524 | &clk_src->calc_pll_hdmi, |
525 | pll_settings); |
526 | else |
527 | /*Calculate Dividers by default object, no SS case or SS case */ |
528 | pll_calc_error = |
529 | calculate_pixel_clock_pll_dividers( |
530 | &clk_src->calc_pll, |
531 | pll_settings); |
532 | |
533 | return pll_calc_error; |
534 | } |
535 | |
536 | static void dce112_get_pix_clk_dividers_helper ( |
537 | struct dce110_clk_src *clk_src, |
538 | struct pll_settings *pll_settings, |
539 | struct pixel_clk_params *pix_clk_params) |
540 | { |
541 | uint32_t actual_pixel_clock_100hz; |
542 | |
543 | actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; |
544 | /* Calculate Dividers */ |
545 | if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { |
546 | switch (pix_clk_params->color_depth) { |
547 | case COLOR_DEPTH_101010: |
548 | actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; |
549 | break; |
550 | case COLOR_DEPTH_121212: |
551 | actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; |
552 | break; |
553 | case COLOR_DEPTH_161616: |
554 | actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; |
555 | break; |
556 | default: |
557 | break; |
558 | } |
559 | } |
560 | pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; |
561 | pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; |
562 | pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; |
563 | } |
564 | |
565 | static uint32_t dce110_get_pix_clk_dividers( |
566 | struct clock_source *cs, |
567 | struct pixel_clk_params *pix_clk_params, |
568 | struct pll_settings *pll_settings) |
569 | { |
570 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (cs); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof (struct dce110_clk_src, base) );}); |
571 | uint32_t pll_calc_error = MAX_PLL_CALC_ERROR0xFFFFFFFF; |
572 | DC_LOGGER_INIT(); |
573 | |
574 | if (pix_clk_params == NULL((void *)0) || pll_settings == NULL((void *)0) |
575 | || pix_clk_params->requested_pix_clk_100hz == 0) { |
576 | DC_LOG_ERROR(__drm_err("%s: Invalid parameters!!\n", __func__) |
577 | "%s: Invalid parameters!!\n", __func__)__drm_err("%s: Invalid parameters!!\n", __func__); |
578 | return pll_calc_error; |
579 | } |
580 | |
581 | memset(pll_settings, 0, sizeof(*pll_settings))__builtin_memset((pll_settings), (0), (sizeof(*pll_settings)) ); |
582 | |
583 | if (cs->id == CLOCK_SOURCE_ID_DP_DTO || |
584 | cs->id == CLOCK_SOURCE_ID_EXTERNAL) { |
585 | pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; |
586 | pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; |
587 | pll_settings->actual_pix_clk_100hz = |
588 | pix_clk_params->requested_pix_clk_100hz; |
589 | return 0; |
590 | } |
591 | |
592 | pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, |
593 | pll_settings, pix_clk_params); |
594 | |
595 | return pll_calc_error; |
596 | } |
597 | |
598 | static uint32_t dce112_get_pix_clk_dividers( |
599 | struct clock_source *cs, |
600 | struct pixel_clk_params *pix_clk_params, |
601 | struct pll_settings *pll_settings) |
602 | { |
603 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (cs); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof (struct dce110_clk_src, base) );}); |
604 | DC_LOGGER_INIT(); |
605 | |
606 | if (pix_clk_params == NULL((void *)0) || pll_settings == NULL((void *)0) |
607 | || pix_clk_params->requested_pix_clk_100hz == 0) { |
608 | DC_LOG_ERROR(__drm_err("%s: Invalid parameters!!\n", __func__) |
609 | "%s: Invalid parameters!!\n", __func__)__drm_err("%s: Invalid parameters!!\n", __func__); |
610 | return -1; |
611 | } |
612 | |
613 | memset(pll_settings, 0, sizeof(*pll_settings))__builtin_memset((pll_settings), (0), (sizeof(*pll_settings)) ); |
614 | |
615 | if (cs->id == CLOCK_SOURCE_ID_DP_DTO || |
616 | cs->id == CLOCK_SOURCE_ID_EXTERNAL) { |
617 | pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; |
618 | pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; |
619 | pll_settings->actual_pix_clk_100hz = |
620 | pix_clk_params->requested_pix_clk_100hz; |
621 | return -1; |
622 | } |
623 | |
624 | dce112_get_pix_clk_dividers_helper(clk_src, |
625 | pll_settings, pix_clk_params); |
626 | |
627 | return 0; |
628 | } |
629 | |
630 | static bool_Bool disable_spread_spectrum(struct dce110_clk_src *clk_src) |
631 | { |
632 | enum bp_result result; |
633 | struct bp_spread_spectrum_parameters bp_ss_params = {0}; |
634 | |
635 | bp_ss_params.pll_id = clk_src->base.id; |
636 | |
637 | /*Call ASICControl to process ATOMBIOS Exec table*/ |
638 | result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( |
639 | clk_src->bios, |
640 | &bp_ss_params, |
641 | false0); |
642 | |
643 | return result == BP_RESULT_OK; |
644 | } |
645 | |
646 | static bool_Bool calculate_ss( |
647 | const struct pll_settings *pll_settings, |
648 | const struct spread_spectrum_data *ss_data, |
649 | struct delta_sigma_data *ds_data) |
650 | { |
651 | struct fixed31_32 fb_div; |
652 | struct fixed31_32 ss_amount; |
653 | struct fixed31_32 ss_nslip_amount; |
654 | struct fixed31_32 ss_ds_frac_amount; |
655 | struct fixed31_32 ss_step_size; |
656 | struct fixed31_32 modulation_time; |
657 | |
658 | if (ds_data == NULL((void *)0)) |
659 | return false0; |
660 | if (ss_data == NULL((void *)0)) |
661 | return false0; |
662 | if (ss_data->percentage == 0) |
663 | return false0; |
664 | if (pll_settings == NULL((void *)0)) |
665 | return false0; |
666 | |
667 | memset(ds_data, 0, sizeof(struct delta_sigma_data))__builtin_memset((ds_data), (0), (sizeof(struct delta_sigma_data ))); |
668 | |
669 | /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ |
670 | /* 6 decimal point support in fractional feedback divider */ |
671 | fb_div = dc_fixpt_from_fraction( |
672 | pll_settings->fract_feedback_divider, 1000000); |
673 | fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); |
674 | |
675 | ds_data->ds_frac_amount = 0; |
676 | /*spreadSpectrumPercentage is in the unit of .01%, |
677 | * so have to divided by 100 * 100*/ |
678 | ss_amount = dc_fixpt_mul( |
679 | fb_div, dc_fixpt_from_fraction(ss_data->percentage, |
680 | 100 * ss_data->percentage_divider)); |
681 | ds_data->feedback_amount = dc_fixpt_floor(ss_amount); |
682 | |
683 | ss_nslip_amount = dc_fixpt_sub(ss_amount, |
684 | dc_fixpt_from_int(ds_data->feedback_amount)); |
685 | ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); |
686 | ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); |
687 | |
688 | ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, |
689 | dc_fixpt_from_int(ds_data->nfrac_amount)); |
690 | ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); |
691 | ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); |
692 | |
693 | /* compute SS_STEP_SIZE_DSFRAC */ |
694 | modulation_time = dc_fixpt_from_fraction( |
695 | pll_settings->reference_freq * 1000, |
696 | pll_settings->reference_divider * ss_data->modulation_freq_hz); |
697 | |
698 | if (ss_data->flags.CENTER_SPREAD) |
699 | modulation_time = dc_fixpt_div_int(modulation_time, 4); |
700 | else |
701 | modulation_time = dc_fixpt_div_int(modulation_time, 2); |
702 | |
703 | ss_step_size = dc_fixpt_div(ss_amount, modulation_time); |
704 | /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ |
705 | ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); |
706 | ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); |
707 | |
708 | return true1; |
709 | } |
710 | |
711 | static bool_Bool enable_spread_spectrum( |
712 | struct dce110_clk_src *clk_src, |
713 | enum amd_signal_type signal, struct pll_settings *pll_settings) |
714 | { |
715 | struct bp_spread_spectrum_parameters bp_params = {0}; |
716 | struct delta_sigma_data d_s_data; |
717 | const struct spread_spectrum_data *ss_data = NULL((void *)0); |
718 | |
719 | ss_data = get_ss_data_entry( |
720 | clk_src, |
721 | signal, |
722 | pll_settings->calculated_pix_clk_100hz / 10); |
723 | |
724 | /* Pixel clock PLL has been programmed to generate desired pixel clock, |
725 | * now enable SS on pixel clock */ |
726 | /* TODO is it OK to return true not doing anything ??*/ |
727 | if (ss_data != NULL((void *)0) && pll_settings->ss_percentage != 0) { |
728 | if (calculate_ss(pll_settings, ss_data, &d_s_data)) { |
729 | bp_params.ds.feedback_amount = |
730 | d_s_data.feedback_amount; |
731 | bp_params.ds.nfrac_amount = |
732 | d_s_data.nfrac_amount; |
733 | bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; |
734 | bp_params.ds_frac_amount = |
735 | d_s_data.ds_frac_amount; |
736 | bp_params.flags.DS_TYPE = 1; |
737 | bp_params.pll_id = clk_src->base.id; |
738 | bp_params.percentage = ss_data->percentage; |
739 | if (ss_data->flags.CENTER_SPREAD) |
740 | bp_params.flags.CENTER_SPREAD = 1; |
741 | if (ss_data->flags.EXTERNAL_SS) |
742 | bp_params.flags.EXTERNAL_SS = 1; |
743 | |
744 | if (BP_RESULT_OK != |
745 | clk_src->bios->funcs-> |
746 | enable_spread_spectrum_on_ppll( |
747 | clk_src->bios, |
748 | &bp_params, |
749 | true1)) |
750 | return false0; |
751 | } else |
752 | return false0; |
753 | } |
754 | return true1; |
755 | } |
756 | |
757 | static void dce110_program_pixel_clk_resync( |
758 | struct dce110_clk_src *clk_src, |
759 | enum amd_signal_type signal_type, |
760 | enum dc_color_depth colordepth) |
761 | { |
762 | REG_UPDATE(RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 0) |
763 | DCCG_DEEP_COLOR_CNTL1, 0)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 0); |
764 | /* |
765 | 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) |
766 | 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) |
767 | 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) |
768 | 48 bit mode: TMDS clock = 2 x pixel clock (2:1) |
769 | */ |
770 | if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) |
771 | return; |
772 | |
773 | switch (colordepth) { |
774 | case COLOR_DEPTH_888: |
775 | REG_UPDATE(RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 0) |
776 | DCCG_DEEP_COLOR_CNTL1, 0)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 0); |
777 | break; |
778 | case COLOR_DEPTH_101010: |
779 | REG_UPDATE(RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 1) |
780 | DCCG_DEEP_COLOR_CNTL1, 1)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 1); |
781 | break; |
782 | case COLOR_DEPTH_121212: |
783 | REG_UPDATE(RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 2) |
784 | DCCG_DEEP_COLOR_CNTL1, 2)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 2); |
785 | break; |
786 | case COLOR_DEPTH_161616: |
787 | REG_UPDATE(RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 3) |
788 | DCCG_DEEP_COLOR_CNTL1, 3)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->RESYNC_CNTL), 1, clk_src->cs_shift->DCCG_DEEP_COLOR_CNTL1 , clk_src->cs_mask->DCCG_DEEP_COLOR_CNTL1, 3); |
789 | break; |
790 | default: |
791 | break; |
792 | } |
793 | } |
794 | |
795 | static void dce112_program_pixel_clk_resync( |
796 | struct dce110_clk_src *clk_src, |
797 | enum amd_signal_type signal_type, |
798 | enum dc_color_depth colordepth, |
799 | bool_Bool enable_ycbcr420) |
800 | { |
801 | uint32_t deep_color_cntl = 0; |
802 | uint32_t double_rate_enable = 0; |
803 | |
804 | /* |
805 | 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) |
806 | 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) |
807 | 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) |
808 | 48 bit mode: TMDS clock = 2 x pixel clock (2:1) |
809 | */ |
810 | if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { |
811 | double_rate_enable = enable_ycbcr420 ? 1 : 0; |
812 | |
813 | switch (colordepth) { |
814 | case COLOR_DEPTH_888: |
815 | deep_color_cntl = 0; |
816 | break; |
817 | case COLOR_DEPTH_101010: |
818 | deep_color_cntl = 1; |
819 | break; |
820 | case COLOR_DEPTH_121212: |
821 | deep_color_cntl = 2; |
822 | break; |
823 | case COLOR_DEPTH_161616: |
824 | deep_color_cntl = 3; |
825 | break; |
826 | default: |
827 | break; |
828 | } |
829 | } |
830 | |
831 | if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) |
832 | REG_UPDATE_2(PIXCLK_RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXCLK_RESYNC_CNTL), 2, clk_src->cs_shift->PHYPLLA_DCCG_DEEP_COLOR_CNTL , clk_src->cs_mask->PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl , clk_src->cs_shift->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable ) |
833 | PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXCLK_RESYNC_CNTL), 2, clk_src->cs_shift->PHYPLLA_DCCG_DEEP_COLOR_CNTL , clk_src->cs_mask->PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl , clk_src->cs_shift->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable ) |
834 | PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXCLK_RESYNC_CNTL), 2, clk_src->cs_shift->PHYPLLA_DCCG_DEEP_COLOR_CNTL , clk_src->cs_mask->PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl , clk_src->cs_shift->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable ); |
835 | else |
836 | REG_UPDATE(PIXCLK_RESYNC_CNTL,generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXCLK_RESYNC_CNTL), 1, clk_src->cs_shift->PHYPLLA_DCCG_DEEP_COLOR_CNTL , clk_src->cs_mask->PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl ) |
837 | PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXCLK_RESYNC_CNTL), 1, clk_src->cs_shift->PHYPLLA_DCCG_DEEP_COLOR_CNTL , clk_src->cs_mask->PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl ); |
838 | |
839 | } |
840 | |
841 | static bool_Bool dce110_program_pix_clk( |
842 | struct clock_source *clock_source, |
843 | struct pixel_clk_params *pix_clk_params, |
844 | struct pll_settings *pll_settings) |
845 | { |
846 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (clock_source); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof(struct dce110_clk_src, base) );}); |
847 | struct bp_pixel_clock_parameters bp_pc_params = {0}; |
848 | |
849 | /* First disable SS |
850 | * ATOMBIOS will enable by default SS on PLL for DP, |
851 | * do not disable it here |
852 | */ |
853 | if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && |
854 | !dc_is_dp_signal(pix_clk_params->signal_type) && |
855 | clock_source->ctx->dce_version <= DCE_VERSION_11_0) |
856 | disable_spread_spectrum(clk_src); |
857 | |
858 | /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ |
859 | bp_pc_params.controller_id = pix_clk_params->controller_id; |
860 | bp_pc_params.pll_id = clock_source->id; |
861 | bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; |
862 | bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; |
863 | bp_pc_params.signal_type = pix_clk_params->signal_type; |
864 | |
865 | bp_pc_params.reference_divider = pll_settings->reference_divider; |
866 | bp_pc_params.feedback_divider = pll_settings->feedback_divider; |
867 | bp_pc_params.fractional_feedback_divider = |
868 | pll_settings->fract_feedback_divider; |
869 | bp_pc_params.pixel_clock_post_divider = |
870 | pll_settings->pix_clk_post_divider; |
871 | bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = |
872 | pll_settings->use_external_clk; |
873 | |
874 | switch (pix_clk_params->color_depth) { |
875 | case COLOR_DEPTH_101010: |
876 | bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30; |
877 | break; |
878 | case COLOR_DEPTH_121212: |
879 | bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36; |
880 | break; |
881 | case COLOR_DEPTH_161616: |
882 | bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48; |
883 | break; |
884 | default: |
885 | break; |
886 | } |
887 | |
888 | if (clk_src->bios->funcs->set_pixel_clock( |
889 | clk_src->bios, &bp_pc_params) != BP_RESULT_OK) |
890 | return false0; |
891 | /* Enable SS |
892 | * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), |
893 | * based on HW display PLL team, SS control settings should be programmed |
894 | * during PLL Reset, but they do not have effect |
895 | * until SS_EN is asserted.*/ |
896 | if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL |
897 | && !dc_is_dp_signal(pix_clk_params->signal_type)) { |
898 | |
899 | if (pix_clk_params->flags.ENABLE_SS) |
900 | if (!enable_spread_spectrum(clk_src, |
901 | pix_clk_params->signal_type, |
902 | pll_settings)) |
903 | return false0; |
904 | |
905 | /* Resync deep color DTO */ |
906 | dce110_program_pixel_clk_resync(clk_src, |
907 | pix_clk_params->signal_type, |
908 | pix_clk_params->color_depth); |
909 | } |
910 | |
911 | return true1; |
912 | } |
913 | |
914 | static bool_Bool dce112_program_pix_clk( |
915 | struct clock_source *clock_source, |
916 | struct pixel_clk_params *pix_clk_params, |
917 | struct pll_settings *pll_settings) |
918 | { |
919 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (clock_source); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof(struct dce110_clk_src, base) );}); |
920 | struct bp_pixel_clock_parameters bp_pc_params = {0}; |
921 | |
922 | #if defined(CONFIG_DRM_AMD_DC_DCN1) |
923 | if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)(clock_source->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS )) { |
924 | unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; |
925 | unsigned dp_dto_ref_100hz = 7000000; |
926 | unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; |
927 | |
928 | /* Set DTO values: phase = target clock, modulo = reference clock */ |
929 | REG_WRITE(PHASE[inst], clock_100hz)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> PHASE[inst]), clock_100hz, __func__); |
930 | REG_WRITE(MODULO[inst], dp_dto_ref_100hz)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> MODULO[inst]), dp_dto_ref_100hz, __func__); |
931 | |
932 | /* Enable DTO */ |
933 | REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXEL_RATE_CNTL[inst]), 1, clk_src->cs_shift->DP_DTO0_ENABLE , clk_src->cs_mask->DP_DTO0_ENABLE, 1); |
934 | return true1; |
935 | } |
936 | #endif |
937 | /* First disable SS |
938 | * ATOMBIOS will enable by default SS on PLL for DP, |
939 | * do not disable it here |
940 | */ |
941 | if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && |
942 | !dc_is_dp_signal(pix_clk_params->signal_type) && |
943 | clock_source->ctx->dce_version <= DCE_VERSION_11_0) |
944 | disable_spread_spectrum(clk_src); |
945 | |
946 | /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ |
947 | bp_pc_params.controller_id = pix_clk_params->controller_id; |
948 | bp_pc_params.pll_id = clock_source->id; |
949 | bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; |
950 | bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; |
951 | bp_pc_params.signal_type = pix_clk_params->signal_type; |
952 | |
953 | if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { |
954 | bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = |
955 | pll_settings->use_external_clk; |
956 | bp_pc_params.flags.SET_XTALIN_REF_SRC = |
957 | !pll_settings->use_external_clk; |
958 | if (pix_clk_params->flags.SUPPORT_YCBCR420) { |
959 | bp_pc_params.flags.SUPPORT_YUV_420 = 1; |
960 | } |
961 | } |
962 | if (clk_src->bios->funcs->set_pixel_clock( |
963 | clk_src->bios, &bp_pc_params) != BP_RESULT_OK) |
964 | return false0; |
965 | /* Resync deep color DTO */ |
966 | if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) |
967 | dce112_program_pixel_clk_resync(clk_src, |
968 | pix_clk_params->signal_type, |
969 | pix_clk_params->color_depth, |
970 | pix_clk_params->flags.SUPPORT_YCBCR420); |
971 | |
972 | return true1; |
973 | } |
974 | |
975 | |
976 | static bool_Bool dce110_clock_source_power_down( |
977 | struct clock_source *clk_src) |
978 | { |
979 | struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (clk_src); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof (struct dce110_clk_src, base) );}); |
980 | enum bp_result bp_result; |
981 | struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; |
982 | |
983 | if (clk_src->dp_clk_src) |
984 | return true1; |
985 | |
986 | /* If Pixel Clock is 0 it means Power Down Pll*/ |
987 | bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; |
988 | bp_pixel_clock_params.pll_id = clk_src->id; |
989 | bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; |
990 | |
991 | /*Call ASICControl to process ATOMBIOS Exec table*/ |
992 | bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( |
993 | dce110_clk_src->bios, |
994 | &bp_pixel_clock_params); |
995 | |
996 | return bp_result == BP_RESULT_OK; |
997 | } |
998 | |
999 | static bool_Bool get_pixel_clk_frequency_100hz( |
1000 | const struct clock_source *clock_source, |
1001 | unsigned int inst, |
1002 | unsigned int *pixel_clk_khz) |
1003 | { |
1004 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (clock_source); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof(struct dce110_clk_src, base) );}); |
1005 | unsigned int clock_hz = 0; |
1006 | |
1007 | if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { |
1008 | clock_hz = REG_READ(PHASE[inst])dm_read_reg_func(clk_src->base.ctx, (clk_src->regs-> PHASE[inst]), __func__); |
1009 | |
1010 | /* NOTE: There is agreement with VBIOS here that MODULO is |
1011 | * programmed equal to DPREFCLK, in which case PHASE will be |
1012 | * equivalent to pixel clock. |
1013 | */ |
1014 | *pixel_clk_khz = clock_hz / 100; |
1015 | return true1; |
1016 | } |
1017 | |
1018 | return false0; |
1019 | } |
1020 | |
1021 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) |
1022 | /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ |
1023 | const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { |
1024 | // /1.001 rates |
1025 | {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17 |
1026 | {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340 |
1027 | {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758 |
1028 | {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87 |
1029 | {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516 |
1030 | {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83 |
1031 | {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527 |
1032 | {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429 |
1033 | {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033 |
1034 | {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857 |
1035 | {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6 |
1036 | {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091 |
1037 | {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055 |
1038 | {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325 |
1039 | {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231 |
1040 | {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974 |
1041 | {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455 |
1042 | {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066 |
1043 | {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377 |
1044 | {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308 |
1045 | {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987 |
1046 | {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209 |
1047 | {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099 |
1048 | {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131 |
1049 | |
1050 | // *1.001 rates |
1051 | {27020, 27030, 27000, 1001, 1000}, //27Mhz |
1052 | {54050, 54060, 54000, 1001, 1000}, //54Mhz |
1053 | {108100, 108110, 108000, 1001, 1000},//108Mhz |
1054 | }; |
1055 | |
1056 | const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( |
1057 | unsigned int pixel_rate_khz) |
1058 | { |
1059 | int i; |
1060 | |
1061 | for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates)(sizeof(video_optimized_pixel_rates) / sizeof((video_optimized_pixel_rates )[0])); i++) { |
1062 | const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; |
1063 | |
1064 | if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) { |
1065 | return e; |
1066 | } |
1067 | } |
1068 | |
1069 | return NULL((void *)0); |
1070 | } |
1071 | #endif |
1072 | |
1073 | static bool_Bool dcn20_program_pix_clk( |
1074 | struct clock_source *clock_source, |
1075 | struct pixel_clk_params *pix_clk_params, |
1076 | struct pll_settings *pll_settings) |
1077 | { |
1078 | dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); |
1079 | |
1080 | return true1; |
1081 | } |
1082 | |
1083 | static const struct clock_source_funcs dcn20_clk_src_funcs = { |
1084 | .cs_power_down = dce110_clock_source_power_down, |
1085 | .program_pix_clk = dcn20_program_pix_clk, |
1086 | .get_pix_clk_dividers = dce112_get_pix_clk_dividers, |
1087 | .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz |
1088 | }; |
1089 | |
1090 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) |
1091 | static bool_Bool dcn3_program_pix_clk( |
1092 | struct clock_source *clock_source, |
1093 | struct pixel_clk_params *pix_clk_params, |
1094 | struct pll_settings *pll_settings) |
1095 | { |
1096 | struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (clock_source); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof(struct dce110_clk_src, base) );}); |
1097 | unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; |
1098 | unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; |
1099 | const struct pixel_rate_range_table_entry *e = |
1100 | look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); |
1101 | |
1102 | // For these signal types Driver to program DP_DTO without calling VBIOS Command table |
1103 | if (dc_is_dp_signal(pix_clk_params->signal_type)) { |
1104 | if (e) { |
1105 | /* Set DTO values: phase = target clock, modulo = reference clock*/ |
1106 | REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> PHASE[inst]), e->target_pixel_rate_khz * e->mult_factor , __func__); |
1107 | REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> MODULO[inst]), dp_dto_ref_khz * e->div_factor, __func__); |
1108 | } else { |
1109 | /* Set DTO values: phase = target clock, modulo = reference clock*/ |
1110 | REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> PHASE[inst]), pll_settings->actual_pix_clk_100hz * 100, __func__ ); |
1111 | REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000)dm_write_reg_func(clk_src->base.ctx, (clk_src->regs-> MODULO[inst]), dp_dto_ref_khz * 1000, __func__); |
1112 | } |
1113 | REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1)generic_reg_update_ex(clk_src->base.ctx, (clk_src->regs ->PIXEL_RATE_CNTL[inst]), 1, clk_src->cs_shift->DP_DTO0_ENABLE , clk_src->cs_mask->DP_DTO0_ENABLE, 1); |
1114 | } else |
1115 | // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table |
1116 | dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); |
1117 | |
1118 | return true1; |
1119 | } |
1120 | |
1121 | static uint32_t dcn3_get_pix_clk_dividers( |
1122 | struct clock_source *cs, |
1123 | struct pixel_clk_params *pix_clk_params, |
1124 | struct pll_settings *pll_settings) |
1125 | { |
1126 | unsigned long long actual_pix_clk_100Hz = pix_clk_params->requested_pix_clk_100hz; |
1127 | struct dce110_clk_src *clk_src; |
1128 | |
1129 | clk_src = TO_DCE110_CLK_SRC(cs)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (cs); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof (struct dce110_clk_src, base) );}); |
Value stored to 'clk_src' is never read | |
1130 | DC_LOGGER_INIT(); |
1131 | |
1132 | if (pix_clk_params == NULL((void *)0) || pll_settings == NULL((void *)0) |
1133 | || pix_clk_params->requested_pix_clk_100hz == 0) { |
1134 | DC_LOG_ERROR(__drm_err("%s: Invalid parameters!!\n", __func__) |
1135 | "%s: Invalid parameters!!\n", __func__)__drm_err("%s: Invalid parameters!!\n", __func__); |
1136 | return -1; |
1137 | } |
1138 | |
1139 | memset(pll_settings, 0, sizeof(*pll_settings))__builtin_memset((pll_settings), (0), (sizeof(*pll_settings)) ); |
1140 | /* Adjust for HDMI Type A deep color */ |
1141 | if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { |
1142 | switch (pix_clk_params->color_depth) { |
1143 | case COLOR_DEPTH_101010: |
1144 | actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2; |
1145 | break; |
1146 | case COLOR_DEPTH_121212: |
1147 | actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2; |
1148 | break; |
1149 | case COLOR_DEPTH_161616: |
1150 | actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2; |
1151 | break; |
1152 | default: |
1153 | break; |
1154 | } |
1155 | } |
1156 | pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; |
1157 | pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; |
1158 | pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; |
1159 | |
1160 | return 0; |
1161 | } |
1162 | |
1163 | static const struct clock_source_funcs dcn3_clk_src_funcs = { |
1164 | .cs_power_down = dce110_clock_source_power_down, |
1165 | .program_pix_clk = dcn3_program_pix_clk, |
1166 | .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, |
1167 | .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz |
1168 | }; |
1169 | #endif |
1170 | /*****************************************/ |
1171 | /* Constructor */ |
1172 | /*****************************************/ |
1173 | |
1174 | static const struct clock_source_funcs dce112_clk_src_funcs = { |
1175 | .cs_power_down = dce110_clock_source_power_down, |
1176 | .program_pix_clk = dce112_program_pix_clk, |
1177 | .get_pix_clk_dividers = dce112_get_pix_clk_dividers, |
1178 | .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz |
1179 | }; |
1180 | static const struct clock_source_funcs dce110_clk_src_funcs = { |
1181 | .cs_power_down = dce110_clock_source_power_down, |
1182 | .program_pix_clk = dce110_program_pix_clk, |
1183 | .get_pix_clk_dividers = dce110_get_pix_clk_dividers, |
1184 | .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz |
1185 | }; |
1186 | |
1187 | |
1188 | static void get_ss_info_from_atombios( |
1189 | struct dce110_clk_src *clk_src, |
1190 | enum as_signal_type as_signal, |
1191 | struct spread_spectrum_data *spread_spectrum_data[], |
1192 | uint32_t *ss_entries_num) |
1193 | { |
1194 | enum bp_result bp_result = BP_RESULT_FAILURE; |
1195 | struct spread_spectrum_info *ss_info; |
1196 | struct spread_spectrum_data *ss_data; |
1197 | struct spread_spectrum_info *ss_info_cur; |
1198 | struct spread_spectrum_data *ss_data_cur; |
1199 | uint32_t i; |
1200 | DC_LOGGER_INIT(); |
1201 | if (ss_entries_num == NULL((void *)0)) { |
1202 | DC_LOG_SYNC(__drm_dbg(DRM_UT_KMS, "Invalid entry !!!\n") |
1203 | "Invalid entry !!!\n")__drm_dbg(DRM_UT_KMS, "Invalid entry !!!\n"); |
1204 | return; |
1205 | } |
1206 | if (spread_spectrum_data == NULL((void *)0)) { |
1207 | DC_LOG_SYNC(__drm_dbg(DRM_UT_KMS, "Invalid array pointer!!!\n") |
1208 | "Invalid array pointer!!!\n")__drm_dbg(DRM_UT_KMS, "Invalid array pointer!!!\n"); |
1209 | return; |
1210 | } |
1211 | |
1212 | spread_spectrum_data[0] = NULL((void *)0); |
1213 | *ss_entries_num = 0; |
1214 | |
1215 | *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( |
1216 | clk_src->bios, |
1217 | as_signal); |
1218 | |
1219 | if (*ss_entries_num == 0) |
1220 | return; |
1221 | |
1222 | ss_info = kcalloc(*ss_entries_num, |
1223 | sizeof(struct spread_spectrum_info), |
1224 | GFP_KERNEL(0x0001 | 0x0004)); |
1225 | ss_info_cur = ss_info; |
1226 | if (ss_info == NULL((void *)0)) |
1227 | return; |
1228 | |
1229 | ss_data = kcalloc(*ss_entries_num, |
1230 | sizeof(struct spread_spectrum_data), |
1231 | GFP_KERNEL(0x0001 | 0x0004)); |
1232 | if (ss_data == NULL((void *)0)) |
1233 | goto out_free_info; |
1234 | |
1235 | for (i = 0, ss_info_cur = ss_info; |
1236 | i < (*ss_entries_num); |
1237 | ++i, ++ss_info_cur) { |
1238 | |
1239 | bp_result = clk_src->bios->funcs->get_spread_spectrum_info( |
1240 | clk_src->bios, |
1241 | as_signal, |
1242 | i, |
1243 | ss_info_cur); |
1244 | |
1245 | if (bp_result != BP_RESULT_OK) |
1246 | goto out_free_data; |
1247 | } |
1248 | |
1249 | for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; |
1250 | i < (*ss_entries_num); |
1251 | ++i, ++ss_info_cur, ++ss_data_cur) { |
1252 | |
1253 | if (ss_info_cur->type.STEP_AND_DELAY_INFO != false0) { |
1254 | DC_LOG_SYNC(__drm_dbg(DRM_UT_KMS, "Invalid ATOMBIOS SS Table!!!\n") |
1255 | "Invalid ATOMBIOS SS Table!!!\n")__drm_dbg(DRM_UT_KMS, "Invalid ATOMBIOS SS Table!!!\n"); |
1256 | goto out_free_data; |
1257 | } |
1258 | |
1259 | /* for HDMI check SS percentage, |
1260 | * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ |
1261 | if (as_signal == AS_SIGNAL_TYPE_HDMI |
1262 | && ss_info_cur->spread_spectrum_percentage > 6){ |
1263 | /* invalid input, do nothing */ |
1264 | DC_LOG_SYNC(__drm_dbg(DRM_UT_KMS, "Invalid SS percentage ") |
1265 | "Invalid SS percentage ")__drm_dbg(DRM_UT_KMS, "Invalid SS percentage "); |
1266 | DC_LOG_SYNC(__drm_dbg(DRM_UT_KMS, "for HDMI in ATOMBIOS info Table!!!\n") |
1267 | "for HDMI in ATOMBIOS info Table!!!\n")__drm_dbg(DRM_UT_KMS, "for HDMI in ATOMBIOS info Table!!!\n"); |
1268 | continue; |
1269 | } |
1270 | if (ss_info_cur->spread_percentage_divider == 1000) { |
1271 | /* Keep previous precision from ATOMBIOS for these |
1272 | * in case new precision set by ATOMBIOS for these |
1273 | * (otherwise all code in DCE specific classes |
1274 | * for all previous ASICs would need |
1275 | * to be updated for SS calculations, |
1276 | * Audio SS compensation and DP DTO SS compensation |
1277 | * which assumes fixed SS percentage Divider = 100)*/ |
1278 | ss_info_cur->spread_spectrum_percentage /= 10; |
1279 | ss_info_cur->spread_percentage_divider = 100; |
1280 | } |
1281 | |
1282 | ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; |
1283 | ss_data_cur->percentage = |
1284 | ss_info_cur->spread_spectrum_percentage; |
1285 | ss_data_cur->percentage_divider = |
1286 | ss_info_cur->spread_percentage_divider; |
1287 | ss_data_cur->modulation_freq_hz = |
1288 | ss_info_cur->spread_spectrum_range; |
1289 | |
1290 | if (ss_info_cur->type.CENTER_MODE) |
1291 | ss_data_cur->flags.CENTER_SPREAD = 1; |
1292 | |
1293 | if (ss_info_cur->type.EXTERNAL) |
1294 | ss_data_cur->flags.EXTERNAL_SS = 1; |
1295 | |
1296 | } |
1297 | |
1298 | *spread_spectrum_data = ss_data; |
1299 | kfree(ss_info); |
1300 | return; |
1301 | |
1302 | out_free_data: |
1303 | kfree(ss_data); |
1304 | *ss_entries_num = 0; |
1305 | out_free_info: |
1306 | kfree(ss_info); |
1307 | } |
1308 | |
1309 | static void ss_info_from_atombios_create( |
1310 | struct dce110_clk_src *clk_src) |
1311 | { |
1312 | get_ss_info_from_atombios( |
1313 | clk_src, |
1314 | AS_SIGNAL_TYPE_DISPLAY_PORT, |
1315 | &clk_src->dp_ss_params, |
1316 | &clk_src->dp_ss_params_cnt); |
1317 | get_ss_info_from_atombios( |
1318 | clk_src, |
1319 | AS_SIGNAL_TYPE_HDMI, |
1320 | &clk_src->hdmi_ss_params, |
1321 | &clk_src->hdmi_ss_params_cnt); |
1322 | get_ss_info_from_atombios( |
1323 | clk_src, |
1324 | AS_SIGNAL_TYPE_DVI, |
1325 | &clk_src->dvi_ss_params, |
1326 | &clk_src->dvi_ss_params_cnt); |
1327 | get_ss_info_from_atombios( |
1328 | clk_src, |
1329 | AS_SIGNAL_TYPE_LVDS, |
1330 | &clk_src->lvds_ss_params, |
1331 | &clk_src->lvds_ss_params_cnt); |
1332 | } |
1333 | |
1334 | static bool_Bool calc_pll_max_vco_construct( |
1335 | struct calc_pll_clock_source *calc_pll_cs, |
1336 | struct calc_pll_clock_source_init_data *init_data) |
1337 | { |
1338 | uint32_t i; |
1339 | struct dc_firmware_info *fw_info; |
1340 | if (calc_pll_cs == NULL((void *)0) || |
1341 | init_data == NULL((void *)0) || |
1342 | init_data->bp == NULL((void *)0)) |
1343 | return false0; |
1344 | |
1345 | if (!init_data->bp->fw_info_valid) |
1346 | return false0; |
1347 | |
1348 | fw_info = &init_data->bp->fw_info; |
1349 | calc_pll_cs->ctx = init_data->ctx; |
1350 | calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; |
1351 | calc_pll_cs->min_vco_khz = |
1352 | fw_info->pll_info.min_output_pxl_clk_pll_frequency; |
1353 | calc_pll_cs->max_vco_khz = |
1354 | fw_info->pll_info.max_output_pxl_clk_pll_frequency; |
1355 | |
1356 | if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) |
1357 | calc_pll_cs->max_pll_input_freq_khz = |
1358 | init_data->max_override_input_pxl_clk_pll_freq_khz; |
1359 | else |
1360 | calc_pll_cs->max_pll_input_freq_khz = |
1361 | fw_info->pll_info.max_input_pxl_clk_pll_frequency; |
1362 | |
1363 | if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) |
1364 | calc_pll_cs->min_pll_input_freq_khz = |
1365 | init_data->min_override_input_pxl_clk_pll_freq_khz; |
1366 | else |
1367 | calc_pll_cs->min_pll_input_freq_khz = |
1368 | fw_info->pll_info.min_input_pxl_clk_pll_frequency; |
1369 | |
1370 | calc_pll_cs->min_pix_clock_pll_post_divider = |
1371 | init_data->min_pix_clk_pll_post_divider; |
1372 | calc_pll_cs->max_pix_clock_pll_post_divider = |
1373 | init_data->max_pix_clk_pll_post_divider; |
1374 | calc_pll_cs->min_pll_ref_divider = |
1375 | init_data->min_pll_ref_divider; |
1376 | calc_pll_cs->max_pll_ref_divider = |
1377 | init_data->max_pll_ref_divider; |
1378 | |
1379 | if (init_data->num_fract_fb_divider_decimal_point == 0 || |
1380 | init_data->num_fract_fb_divider_decimal_point_precision > |
1381 | init_data->num_fract_fb_divider_decimal_point) { |
1382 | DC_LOG_ERROR(__drm_err("The dec point num or precision is incorrect!") |
1383 | "The dec point num or precision is incorrect!")__drm_err("The dec point num or precision is incorrect!"); |
1384 | return false0; |
1385 | } |
1386 | if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { |
1387 | DC_LOG_ERROR(__drm_err("Incorrect fract feedback divider precision num!") |
1388 | "Incorrect fract feedback divider precision num!")__drm_err("Incorrect fract feedback divider precision num!"); |
1389 | return false0; |
1390 | } |
1391 | |
1392 | calc_pll_cs->fract_fb_divider_decimal_points_num = |
1393 | init_data->num_fract_fb_divider_decimal_point; |
1394 | calc_pll_cs->fract_fb_divider_precision = |
1395 | init_data->num_fract_fb_divider_decimal_point_precision; |
1396 | calc_pll_cs->fract_fb_divider_factor = 1; |
1397 | for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) |
1398 | calc_pll_cs->fract_fb_divider_factor *= 10; |
1399 | |
1400 | calc_pll_cs->fract_fb_divider_precision_factor = 1; |
1401 | for ( |
1402 | i = 0; |
1403 | i < (calc_pll_cs->fract_fb_divider_decimal_points_num - |
1404 | calc_pll_cs->fract_fb_divider_precision); |
1405 | ++i) |
1406 | calc_pll_cs->fract_fb_divider_precision_factor *= 10; |
1407 | |
1408 | return true1; |
1409 | } |
1410 | |
1411 | bool_Bool dce110_clk_src_construct( |
1412 | struct dce110_clk_src *clk_src, |
1413 | struct dc_context *ctx, |
1414 | struct dc_bios *bios, |
1415 | enum clock_source_id id, |
1416 | const struct dce110_clk_src_regs *regs, |
1417 | const struct dce110_clk_src_shift *cs_shift, |
1418 | const struct dce110_clk_src_mask *cs_mask) |
1419 | { |
1420 | struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; |
1421 | struct calc_pll_clock_source_init_data calc_pll_cs_init_data; |
1422 | |
1423 | clk_src->base.ctx = ctx; |
1424 | clk_src->bios = bios; |
1425 | clk_src->base.id = id; |
1426 | clk_src->base.funcs = &dce110_clk_src_funcs; |
1427 | |
1428 | clk_src->regs = regs; |
1429 | clk_src->cs_shift = cs_shift; |
1430 | clk_src->cs_mask = cs_mask; |
1431 | |
1432 | if (!clk_src->bios->fw_info_valid) { |
1433 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c" , 1433); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1434 | goto unexpected_failure; |
1435 | } |
1436 | |
1437 | clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; |
1438 | |
1439 | /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ |
1440 | calc_pll_cs_init_data.bp = bios; |
1441 | calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; |
1442 | calc_pll_cs_init_data.max_pix_clk_pll_post_divider = |
1443 | clk_src->cs_mask->PLL_POST_DIV_PIXCLK; |
1444 | calc_pll_cs_init_data.min_pll_ref_divider = 1; |
1445 | calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; |
1446 | /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ |
1447 | calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; |
1448 | /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ |
1449 | calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; |
1450 | /*numberOfFractFBDividerDecimalPoints*/ |
1451 | calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = |
1452 | FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM6; |
1453 | /*number of decimal point to round off for fractional feedback divider value*/ |
1454 | calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = |
1455 | FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM6; |
1456 | calc_pll_cs_init_data.ctx = ctx; |
1457 | |
1458 | /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ |
1459 | calc_pll_cs_init_data_hdmi.bp = bios; |
1460 | calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; |
1461 | calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = |
1462 | clk_src->cs_mask->PLL_POST_DIV_PIXCLK; |
1463 | calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; |
1464 | calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; |
1465 | /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ |
1466 | calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; |
1467 | /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ |
1468 | calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; |
1469 | /*numberOfFractFBDividerDecimalPoints*/ |
1470 | calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = |
1471 | FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM6; |
1472 | /*number of decimal point to round off for fractional feedback divider value*/ |
1473 | calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = |
1474 | FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM6; |
1475 | calc_pll_cs_init_data_hdmi.ctx = ctx; |
1476 | |
1477 | clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; |
1478 | |
1479 | if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) |
1480 | return true1; |
1481 | |
1482 | /* PLL only from here on */ |
1483 | ss_info_from_atombios_create(clk_src); |
1484 | |
1485 | if (!calc_pll_max_vco_construct( |
1486 | &clk_src->calc_pll, |
1487 | &calc_pll_cs_init_data)) { |
1488 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c" , 1488); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1489 | goto unexpected_failure; |
1490 | } |
1491 | |
1492 | |
1493 | calc_pll_cs_init_data_hdmi. |
1494 | min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; |
1495 | calc_pll_cs_init_data_hdmi. |
1496 | max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; |
1497 | |
1498 | |
1499 | if (!calc_pll_max_vco_construct( |
1500 | &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { |
1501 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c" , 1501); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1502 | goto unexpected_failure; |
1503 | } |
1504 | |
1505 | return true1; |
1506 | |
1507 | unexpected_failure: |
1508 | return false0; |
1509 | } |
1510 | |
1511 | bool_Bool dce112_clk_src_construct( |
1512 | struct dce110_clk_src *clk_src, |
1513 | struct dc_context *ctx, |
1514 | struct dc_bios *bios, |
1515 | enum clock_source_id id, |
1516 | const struct dce110_clk_src_regs *regs, |
1517 | const struct dce110_clk_src_shift *cs_shift, |
1518 | const struct dce110_clk_src_mask *cs_mask) |
1519 | { |
1520 | clk_src->base.ctx = ctx; |
1521 | clk_src->bios = bios; |
1522 | clk_src->base.id = id; |
1523 | clk_src->base.funcs = &dce112_clk_src_funcs; |
1524 | |
1525 | clk_src->regs = regs; |
1526 | clk_src->cs_shift = cs_shift; |
1527 | clk_src->cs_mask = cs_mask; |
1528 | |
1529 | if (!clk_src->bios->fw_info_valid) { |
1530 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c" , 1530); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1531 | return false0; |
1532 | } |
1533 | |
1534 | clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; |
1535 | |
1536 | return true1; |
1537 | } |
1538 | |
1539 | bool_Bool dcn20_clk_src_construct( |
1540 | struct dce110_clk_src *clk_src, |
1541 | struct dc_context *ctx, |
1542 | struct dc_bios *bios, |
1543 | enum clock_source_id id, |
1544 | const struct dce110_clk_src_regs *regs, |
1545 | const struct dce110_clk_src_shift *cs_shift, |
1546 | const struct dce110_clk_src_mask *cs_mask) |
1547 | { |
1548 | bool_Bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); |
1549 | |
1550 | clk_src->base.funcs = &dcn20_clk_src_funcs; |
1551 | |
1552 | return ret; |
1553 | } |
1554 | |
1555 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) |
1556 | bool_Bool dcn3_clk_src_construct( |
1557 | struct dce110_clk_src *clk_src, |
1558 | struct dc_context *ctx, |
1559 | struct dc_bios *bios, |
1560 | enum clock_source_id id, |
1561 | const struct dce110_clk_src_regs *regs, |
1562 | const struct dce110_clk_src_shift *cs_shift, |
1563 | const struct dce110_clk_src_mask *cs_mask) |
1564 | { |
1565 | bool_Bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); |
1566 | |
1567 | clk_src->base.funcs = &dcn3_clk_src_funcs; |
1568 | |
1569 | return ret; |
1570 | } |
1571 | #endif |