/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu

Bug Summary

File:	dev/pci/drm/amd/amdgpu/amdgpu_psp.c
Warning:	line 2460, column 53 Access to field 'data' results in a dereference of a null pointer (loaded from field 'sos_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_psp.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

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1/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Author: Huang Rui
*
*/

26#include <linux/firmware.h>
27#include <linux/dma-mapping.h>

29#include "amdgpu.h"
30#include "amdgpu_psp.h"
31#include "amdgpu_ucode.h"
32#include "soc15_common.h"
33#include "psp_v3_1.h"
34#include "psp_v10_0.h"
35#include "psp_v11_0.h"
36#include "psp_v12_0.h"

38#include "amdgpu_ras.h"

40static int psp_sysfs_init(struct amdgpu_device *adev);
41static void psp_sysfs_fini(struct amdgpu_device *adev);

43static int psp_load_smu_fw(struct psp_context *psp);

45/*
* Due to DF Cstate management centralized to PMFW, the firmware
* loading sequence will be updated as below:
*   - Load KDB
*   - Load SYS_DRV
*   - Load tOS
*   - Load PMFW
*   - Setup TMR
*   - Load other non-psp fw
*   - Load ASD
*   - Load XGMI/RAS/HDCP/DTM TA if any
*
* This new sequence is required for
*   - Arcturus
*   - Navi12 and onwards
*/
61static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
62{
struct amdgpu_device *adev = psp->adev;

psp->pmfw_centralized_cstate_management = false0;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
return;

if (adev->flags & AMD_IS_APU)
return;

if ((adev->asic_type == CHIP_ARCTURUS) ||
   (adev->asic_type >= CHIP_NAVI12))
psp->pmfw_centralized_cstate_management = true1;
76}

78static int psp_early_init(void *handle)
79{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;

switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA12:
psp_v3_1_set_psp_funcs(psp);
psp->autoload_supported = false0;
break;
case CHIP_RAVEN:
psp_v10_0_set_psp_funcs(psp);
psp->autoload_supported = false0;
break;
case CHIP_VEGA20:
case CHIP_ARCTURUS:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = false0;
break;
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true1;
break;
case CHIP_RENOIR:
psp_v12_0_set_psp_funcs(psp);
break;
default:
return -EINVAL22;
}

psp->adev = adev;

psp_check_pmfw_centralized_cstate_management(psp);

return 0;
118}

120static void psp_memory_training_fini(struct psp_context *psp)
121{
struct psp_memory_training_context *ctx = &psp->mem_train_ctx;

ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
kfree(ctx->sys_cache);
ctx->sys_cache = NULL((void *)0);
127}

129static int psp_memory_training_init(struct psp_context *psp)
130{
int ret;
struct psp_memory_training_context *ctx = &psp->mem_train_ctx;

if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
DRM_DEBUG("memory training is not supported!\n")__drm_dbg(DRM_UT_CORE, "memory training is not supported!\n");
return 0;
}

ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL(0x0001 | 0x0004));
if (ctx->sys_cache == NULL((void *)0)) {
DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n")__drm_err("alloc mem_train_ctx.sys_cache failed!\n");
ret = -ENOMEM12;
goto Err_out;
}

DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
  ctx->train_data_size,__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
  ctx->p2c_train_data_offset,__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
  ctx->c2p_train_data_offset)__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset);
ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
return 0;

153Err_out:
psp_memory_training_fini(psp);
return ret;
156}

158static int psp_sw_init(void *handle)
159{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
int ret;

if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
ret = psp_init_microcode(psp)((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode
((psp)) : 0);
if (ret) {
	DRM_ERROR("Failed to load psp firmware!\n")__drm_err("Failed to load psp firmware!\n");
	return ret;
}
}

ret = psp_memory_training_init(psp);
if (ret) {
DRM_ERROR("Failed to initialize memory training!\n")__drm_err("Failed to initialize memory training!\n");
return ret;
}
ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT)((psp)->funcs->mem_training ? (psp)->funcs->mem_training
((psp), (PSP_MEM_TRAIN_COLD_BOOT)) : 0);
if (ret) {
DRM_ERROR("Failed to process memory training!\n")__drm_err("Failed to process memory training!\n");
return ret;
}

if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
ret= psp_sysfs_init(adev);
if (ret) {
	return ret;
}
}

return 0;
191}

193static int psp_sw_fini(void *handle)
194{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

psp_memory_training_fini(&adev->psp);
if (adev->psp.sos_fw) {
release_firmware(adev->psp.sos_fw);
adev->psp.sos_fw = NULL((void *)0);
}
if (adev->psp.asd_fw) {
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL((void *)0);
}
if (adev->psp.ta_fw) {
release_firmware(adev->psp.ta_fw);
adev->psp.ta_fw = NULL((void *)0);
}

if (adev->asic_type == CHIP_NAVI10 ||
   adev->asic_type == CHIP_SIENNA_CICHLID)
psp_sysfs_fini(adev);

return 0;
216}

218int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 uint32_t reg_val, uint32_t mask, bool_Bool check_changed)
220{
uint32_t val;
int i;
struct amdgpu_device *adev = psp->adev;

if (psp->adev->in_pci_err_recovery)
return 0;

for (i = 0; i < adev->usec_timeout; i++) {
val = RREG32(reg_index)amdgpu_device_rreg(adev, (reg_index), 0);
if (check_changed) {
	if (val != reg_val)
		return 0;
} else {
	if ((val & mask) == reg_val)
		return 0;
}
udelay(1);
}

return -ETIME60;
241}

243static int
244psp_cmd_submit_buf(struct psp_context *psp,
   struct amdgpu_firmware_info *ucode,
   struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
247{
int ret;
int index;
int timeout = 2000;
bool_Bool ras_intr = false0;
bool_Bool skip_unsupport = false0;

if (psp->adev->in_pci_err_recovery)
return 0;

mutex_lock(&psp->mutex)rw_enter_write(&psp->mutex);

memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE)__builtin_memset((psp->cmd_buf_mem), (0), (0x1000));

memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp))__builtin_memcpy((psp->cmd_buf_mem), (cmd), (sizeof(struct
 psp_gfx_cmd_resp)));

index = atomic_inc_return(&psp->fence_value)__sync_add_and_fetch((&psp->fence_value), 1);
ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
if (ret) {
atomic_dec(&psp->fence_value)__sync_fetch_and_sub(&psp->fence_value, 1);
mutex_unlock(&psp->mutex)rw_exit_write(&psp->mutex);
return ret;
}

amdgpu_asic_invalidate_hdp(psp->adev, NULL)(psp->adev)->asic_funcs->invalidate_hdp((psp->adev
), (((void *)0)));
while (*((unsigned int *)psp->fence_buf) != index) {
if (--timeout == 0)
	break;
/*
 * Shouldn't wait for timeout when err_event_athub occurs,
 * because gpu reset thread triggered and lock resource should
 * be released for psp resume sequence.
 */
ras_intr = amdgpu_ras_intr_triggered();
if (ras_intr)
	break;
drm_msleep(1)mdelay(1);
amdgpu_asic_invalidate_hdp(psp->adev, NULL)(psp->adev)->asic_funcs->invalidate_hdp((psp->adev
), (((void *)0)));
}

/* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND0x00000100) && amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2));

/* In some cases, psp response status is not 0 even there is no
* problem while the command is submitted. Some version of PSP FW
* doesn't write 0 to that field.
* So here we would like to only print a warning instead of an error
* during psp initialization to avoid breaking hw_init and it doesn't
* return -EINVAL.
*/
if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
if (ucode)
	DRM_WARN("failed to load ucode id (%d) ",printk("\0014" "[" "drm" "] " "failed to load ucode id (%d) "
, ucode->ucode_id)
		  ucode->ucode_id)printk("\0014" "[" "drm" "] " "failed to load ucode id (%d) "
, ucode->ucode_id);
DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",printk("\0014" "[" "drm" "] " "psp command (0x%X) failed and response status is (0x%X)\n"
, psp->cmd_buf_mem->cmd_id, psp->cmd_buf_mem->resp
.status)
	 psp->cmd_buf_mem->cmd_id,printk("\0014" "[" "drm" "] " "psp command (0x%X) failed and response status is (0x%X)\n"
, psp->cmd_buf_mem->cmd_id, psp->cmd_buf_mem->resp
.status)
	 psp->cmd_buf_mem->resp.status)printk("\0014" "[" "drm" "] " "psp command (0x%X) failed and response status is (0x%X)\n"
, psp->cmd_buf_mem->cmd_id, psp->cmd_buf_mem->resp
.status);
if (!timeout) {
	mutex_unlock(&psp->mutex)rw_exit_write(&psp->mutex);
	return -EINVAL22;
}
}

/* get xGMI session id from response buffer */
cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;

if (ucode) {
ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
}
mutex_unlock(&psp->mutex)rw_exit_write(&psp->mutex);

return ret;
321}

323static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
		 struct psp_gfx_cmd_resp *cmd,
		 uint64_t tmr_mc, uint32_t size)
326{
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
else
cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc)((u32)(tmr_mc));
cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc)((u32)(((tmr_mc) >> 16) >> 16));
cmd->cmd.cmd_setup_tmr.buf_size = size;
334}

336static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		      uint64_t pri_buf_mc, uint32_t size)
338{
cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc)((u32)(pri_buf_mc));
cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc)((u32)(((pri_buf_mc) >> 16) >> 16));
cmd->cmd.cmd_load_toc.toc_size = size;
343}

345/* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
346static int psp_load_toc(struct psp_context *psp,
	uint32_t *tmr_size)
348{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;
/* Copy toc to psp firmware private buffer */
memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size)__builtin_memcpy((psp->fw_pri_buf), (psp->toc_start_addr
), (psp->toc_bin_size));

psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);
if (!ret)
*tmr_size = psp->cmd_buf_mem->resp.tmr_size;
kfree(cmd);
return ret;
367}

369/* Set up Trusted Memory Region */
370static int psp_tmr_init(struct psp_context *psp)
371{
int ret;
int tmr_size;
void *tmr_buf;
void **pptr;

/*
* According to HW engineer, they prefer the TMR address be "naturally
* aligned" , e.g. the start address be an integer divide of TMR size.
*
* Note: this memory need be reserved till the driver
* uninitializes.
*/
tmr_size = PSP_TMR_SIZE0x400000;

/* For ASICs support RLC autoload, psp will parse the toc
* and calculate the total size of TMR needed */
if (!amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) &&
   psp->toc_start_addr &&
   psp->toc_bin_size &&
   psp->fw_pri_buf) {
ret = psp_load_toc(psp, &tmr_size);
if (ret) {
	DRM_ERROR("Failed to load toc\n")__drm_err("Failed to load toc\n");
	return ret;
}
}

pptr = amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) ? &tmr_buf : NULL((void *)0);
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE0x400000,
		      AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);

return ret;
405}

407static int psp_clear_vf_fw(struct psp_context *psp)
408{
int ret;
struct psp_gfx_cmd_resp *cmd;

if (!amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) || psp->adev->asic_type != CHIP_NAVI12)
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);
kfree(cmd);

return ret;
425}

427static bool_Bool psp_skip_tmr(struct psp_context *psp)
428{
switch (psp->adev->asic_type) {
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
return true1;
default:
return false0;
}
436}

438static int psp_tmr_load(struct psp_context *psp)
439{
int ret;
struct psp_gfx_cmd_resp *cmd;

/* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
* Already set up by host driver.
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) && psp_skip_tmr(psp))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
	     amdgpu_bo_size(psp->tmr_bo));
DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",printk("\0016" "[" "drm" "] " "reserve 0x%lx from 0x%llx for PSP TMR\n"
, amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr)
 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr)printk("\0016" "[" "drm" "] " "reserve 0x%lx from 0x%llx for PSP TMR\n"
, amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
464}

466static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
			struct psp_gfx_cmd_resp *cmd)
468{
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
else
cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
473}

475static int psp_tmr_unload(struct psp_context *psp)
476{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_tmr_unload_cmd_buf(psp, cmd);
DRM_INFO("free PSP TMR buffer\n")printk("\0016" "[" "drm" "] " "free PSP TMR buffer\n");

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
493}

495static int psp_tmr_terminate(struct psp_context *psp)
496{
int ret;
void *tmr_buf;
void **pptr;

ret = psp_tmr_unload(psp);
if (ret)
return ret;

/* free TMR memory buffer */
pptr = amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) ? &tmr_buf : NULL((void *)0);
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);

return 0;
510}

512static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		uint64_t asd_mc, uint32_t size)
514{
cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc)((u32)(asd_mc));
cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc)((u32)(((asd_mc) >> 16) >> 16));
cmd->cmd.cmd_load_ta.app_len = size;

cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
523}

525static int psp_asd_load(struct psp_context *psp)
526{
int ret;
struct psp_gfx_cmd_resp *cmd;

/* If PSP version doesn't match ASD version, asd loading will be failed.
* add workaround to bypass it for sriov now.
* TODO: add version check to make it common
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) || !psp->asd_fw)
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->asd_start_addr
), (psp->asd_ucode_size));

psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
		  psp->asd_ucode_size);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);
if (!ret) {
psp->asd_context.asd_initialized = true1;
psp->asd_context.session_id = cmd->resp.session_id;
}

kfree(cmd);

return ret;
557}

559static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		       uint32_t session_id)
561{
cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
cmd->cmd.cmd_unload_ta.session_id = session_id;
564}

566static int psp_asd_unload(struct psp_context *psp)
567{
int ret;
struct psp_gfx_cmd_resp *cmd;

if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->asd_context.asd_initialized)
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);
if (!ret)
psp->asd_context.asd_initialized = false0;

kfree(cmd);

return ret;
591}

593static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
uint32_t id, uint32_t value)
595{
cmd->cmd_id = GFX_CMD_ID_PROG_REG;
cmd->cmd.cmd_setup_reg_prog.reg_value = value;
cmd->cmd.cmd_setup_reg_prog.reg_id = id;
599}

601int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
uint32_t value)
603{
struct psp_gfx_cmd_resp *cmd = NULL((void *)0);
int ret = 0;

if (reg >= PSP_REG_LAST)
return -EINVAL22;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_reg_prog_cmd_buf(cmd, reg, value);
ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

kfree(cmd);
return ret;
619}

621static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		     uint64_t ta_bin_mc,
		     uint32_t ta_bin_size,
		     uint64_t ta_shared_mc,
		     uint32_t ta_shared_size)
626{
cmd->cmd_id 				= GFX_CMD_ID_LOAD_TA;
cmd->cmd.cmd_load_ta.app_phy_addr_lo 	= lower_32_bits(ta_bin_mc)((u32)(ta_bin_mc));
cmd->cmd.cmd_load_ta.app_phy_addr_hi 	= upper_32_bits(ta_bin_mc)((u32)(((ta_bin_mc) >> 16) >> 16));
cmd->cmd.cmd_load_ta.app_len 		= ta_bin_size;

cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc)((u32)(ta_shared_mc));
cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc)((u32)(((ta_shared_mc) >> 16) >> 16));
cmd->cmd.cmd_load_ta.cmd_buf_len 	 = ta_shared_size;
635}

637static int psp_xgmi_init_shared_buf(struct psp_context *psp)
638{
int ret;

/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for xgmi ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE0x4000,
		      PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->xgmi_context.xgmi_shared_bo,
		      &psp->xgmi_context.xgmi_shared_mc_addr,
		      &psp->xgmi_context.xgmi_shared_buf);

return ret;
652}

654static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
		       uint32_t ta_cmd_id,
		       uint32_t session_id)
657{
cmd->cmd_id 				= GFX_CMD_ID_INVOKE_CMD;
cmd->cmd.cmd_invoke_cmd.session_id 	= session_id;
cmd->cmd.cmd_invoke_cmd.ta_cmd_id 	= ta_cmd_id;
661}

663static int psp_ta_invoke(struct psp_context *psp,
  uint32_t ta_cmd_id,
  uint32_t session_id)
666{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
682}

684static int psp_xgmi_load(struct psp_context *psp)
685{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the loading in sriov for now
*/

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->ta_xgmi_start_addr
), (psp->ta_xgmi_ucode_size));

psp_prep_ta_load_cmd_buf(cmd,
		 psp->fw_pri_mc_addr,
		 psp->ta_xgmi_ucode_size,
		 psp->xgmi_context.xgmi_shared_mc_addr,
		 PSP_XGMI_SHARED_MEM_SIZE0x4000);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);

if (!ret) {
psp->xgmi_context.initialized = 1;
psp->xgmi_context.session_id = cmd->resp.session_id;
}

kfree(cmd);

return ret;
717}

719static int psp_xgmi_unload(struct psp_context *psp)
720{
int ret;
struct psp_gfx_cmd_resp *cmd;
struct amdgpu_device *adev = psp->adev;

/* XGMI TA unload currently is not supported on Arcturus */
if (adev->asic_type == CHIP_ARCTURUS)
return 0;

/*
* TODO: bypass the unloading in sriov for now
*/

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
745}

747int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
748{
return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
750}

752int psp_xgmi_terminate(struct psp_context *psp)
753{
int ret;

if (!psp->xgmi_context.initialized)
return 0;

ret = psp_xgmi_unload(psp);
if (ret)
return ret;

psp->xgmi_context.initialized = 0;

/* free xgmi shared memory */
amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
	&psp->xgmi_context.xgmi_shared_mc_addr,
	&psp->xgmi_context.xgmi_shared_buf);

return 0;
771}

773int psp_xgmi_initialize(struct psp_context *psp)
774{
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;

if (!psp->adev->psp.ta_fw ||
   !psp->adev->psp.ta_xgmi_ucode_size ||
   !psp->adev->psp.ta_xgmi_start_addr)
return -ENOENT2;

if (!psp->xgmi_context.initialized) {
ret = psp_xgmi_init_shared_buf(psp);
if (ret)
	return ret;
}

/* Load XGMI TA */
ret = psp_xgmi_load(psp);
if (ret)
return ret;

/* Initialize XGMI session */
xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory))__builtin_memset((xgmi_cmd), (0), (sizeof(struct ta_xgmi_shared_memory
)));
xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;

ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);

return ret;
802}

804int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
805{
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;

xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory))__builtin_memset((xgmi_cmd), (0), (sizeof(struct ta_xgmi_shared_memory
)));

xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;

/* Invoke xgmi ta to get hive id */
ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
if (ret)
return ret;

*hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;

return 0;
822}

824int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
825{
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;

xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory))__builtin_memset((xgmi_cmd), (0), (sizeof(struct ta_xgmi_shared_memory
)));

xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;

/* Invoke xgmi ta to get the node id */
ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
if (ret)
return ret;

*node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;

return 0;
842}

844int psp_xgmi_get_topology_info(struct psp_context *psp,
	       int number_devices,
	       struct psp_xgmi_topology_info *topology)
847{
struct ta_xgmi_shared_memory *xgmi_cmd;
struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
int i;
int ret;

if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
return -EINVAL22;

xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory))__builtin_memset((xgmi_cmd), (0), (sizeof(struct ta_xgmi_shared_memory
)));

/* Fill in the shared memory with topology information as input */
topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
topology_info_input->num_nodes = number_devices;

for (i = 0; i < topology_info_input->num_nodes; i++) {
topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
}

/* Invoke xgmi ta to get the topology information */
ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
if (ret)
return ret;

/* Read the output topology information from the shared memory */
topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
for (i = 0; i < topology->num_nodes; i++) {
topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
}

return 0;
888}

890int psp_xgmi_set_topology_info(struct psp_context *psp,
	       int number_devices,
	       struct psp_xgmi_topology_info *topology)
893{
struct ta_xgmi_shared_memory *xgmi_cmd;
struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
int i;

if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
return -EINVAL22;

xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory))__builtin_memset((xgmi_cmd), (0), (sizeof(struct ta_xgmi_shared_memory
)));

topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
topology_info_input->num_nodes = number_devices;

for (i = 0; i < topology_info_input->num_nodes; i++) {
topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
topology_info_input->nodes[i].is_sharing_enabled = 1;
topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
}

/* Invoke xgmi ta to set topology information */
return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
917}

919// ras begin
920static int psp_ras_init_shared_buf(struct psp_context *psp)
921{
int ret;

/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for ras ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE0x4000,
	PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_VRAM0x4,
	&psp->ras.ras_shared_bo,
	&psp->ras.ras_shared_mc_addr,
	&psp->ras.ras_shared_buf);

return ret;
935}

937static int psp_ras_load(struct psp_context *psp)
938{
int ret;
struct psp_gfx_cmd_resp *cmd;
struct ta_ras_shared_memory *ras_cmd;

/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->ta_ras_start_addr
), (psp->ta_ras_ucode_size));

psp_prep_ta_load_cmd_buf(cmd,
		 psp->fw_pri_mc_addr,
		 psp->ta_ras_ucode_size,
		 psp->ras.ras_shared_mc_addr,
		 PSP_RAS_SHARED_MEM_SIZE0x4000);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
	psp->fence_buf_mc_addr);

ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf;

if (!ret) {
psp->ras.session_id = cmd->resp.session_id;

if (!ras_cmd->ras_status)
	psp->ras.ras_initialized = true1;
else
	dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status)printf("drm:pid%d:%s *WARNING* " "RAS Init Status: 0x%X\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , ras_cmd
->ras_status);
}

if (ret || ras_cmd->ras_status)
amdgpu_ras_fini(psp->adev);

kfree(cmd);

return ret;
982}

984static int psp_ras_unload(struct psp_context *psp)
985{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the unloading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
	psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
1007}

1009int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1010{
struct ta_ras_shared_memory *ras_cmd;
int ret;

ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;

/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);

if (amdgpu_ras_intr_triggered())
return ret;

if (ras_cmd->if_version > RAS_TA_HOST_IF_VER0)
{
DRM_WARN("RAS: Unsupported Interface")printk("\0014" "[" "drm" "] " "RAS: Unsupported Interface");
return -EINVAL22;
}

if (!ret) {
if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
	dev_warn(psp->adev->dev, "ECC switch disabled\n")printf("drm:pid%d:%s *WARNING* " "ECC switch disabled\n", ({struct
 cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__);

	ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
}
else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
	dev_warn(psp->adev->dev,printf("drm:pid%d:%s *WARNING* " "RAS internal register access blocked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		 "RAS internal register access blocked\n")printf("drm:pid%d:%s *WARNING* " "RAS internal register access blocked\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

return ret;
1045}

1047int psp_ras_enable_features(struct psp_context *psp,
union ta_ras_cmd_input *info, bool_Bool enable)
1049{
struct ta_ras_shared_memory *ras_cmd;
int ret;

if (!psp->ras.ras_initialized)
return -EINVAL22;

ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory))__builtin_memset((ras_cmd), (0), (sizeof(struct ta_ras_shared_memory
)));

if (enable)
ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
else
ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;

ras_cmd->ras_in_message = *info;

ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
if (ret)
return -EINVAL22;

return ras_cmd->ras_status;
1071}

1073static int psp_ras_terminate(struct psp_context *psp)
1074{
int ret;

/*
* TODO: bypass the terminate in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->ras.ras_initialized)
return 0;

ret = psp_ras_unload(psp);
if (ret)
return ret;

psp->ras.ras_initialized = false0;

/* free ras shared memory */
amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
	&psp->ras.ras_shared_mc_addr,
	&psp->ras.ras_shared_buf);

return 0;
1098}

1100static int psp_ras_initialize(struct psp_context *psp)
1101{
int ret;

/*
* TODO: bypass the initialize in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->adev->psp.ta_ras_ucode_size ||
   !psp->adev->psp.ta_ras_start_addr) {
dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n")do { } while(0);
return 0;
}

if (!psp->ras.ras_initialized) {
ret = psp_ras_init_shared_buf(psp);
if (ret)
	return ret;
}

ret = psp_ras_load(psp);
if (ret)
return ret;

return 0;
1127}

1129int psp_ras_trigger_error(struct psp_context *psp,
	  struct ta_ras_trigger_error_input *info)
1131{
struct ta_ras_shared_memory *ras_cmd;
int ret;

if (!psp->ras.ras_initialized)
return -EINVAL22;

ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory))__builtin_memset((ras_cmd), (0), (sizeof(struct ta_ras_shared_memory
)));

ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
ras_cmd->ras_in_message.trigger_error = *info;

ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
if (ret)
return -EINVAL22;

/* If err_event_athub occurs error inject was successful, however
  return status from TA is no long reliable */
if (amdgpu_ras_intr_triggered())
return 0;

return ras_cmd->ras_status;
1154}
1155// ras end

1157// HDCP start
1158static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1159{
int ret;

/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for hdcp ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE0x4000,
		      PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->hdcp_context.hdcp_shared_bo,
		      &psp->hdcp_context.hdcp_shared_mc_addr,
		      &psp->hdcp_context.hdcp_shared_buf);

return ret;
1173}

1175static int psp_hdcp_load(struct psp_context *psp)
1176{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,__builtin_memcpy((psp->fw_pri_buf), (psp->ta_hdcp_start_addr
), (psp->ta_hdcp_ucode_size))
      psp->ta_hdcp_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->ta_hdcp_start_addr
), (psp->ta_hdcp_ucode_size));

psp_prep_ta_load_cmd_buf(cmd,
		 psp->fw_pri_mc_addr,
		 psp->ta_hdcp_ucode_size,
		 psp->hdcp_context.hdcp_shared_mc_addr,
		 PSP_HDCP_SHARED_MEM_SIZE0x4000);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

if (!ret) {
psp->hdcp_context.hdcp_initialized = true1;
psp->hdcp_context.session_id = cmd->resp.session_id;
rw_init(&psp->hdcp_context.mutex, "pspcp")_rw_init_flags(&psp->hdcp_context.mutex, "pspcp", 0, (
(void *)0));
}

kfree(cmd);

return ret;
1211}
1212static int psp_hdcp_initialize(struct psp_context *psp)
1213{
int ret;

/*
* TODO: bypass the initialize in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->adev->psp.ta_hdcp_ucode_size ||
   !psp->adev->psp.ta_hdcp_start_addr) {
dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n")do { } while(0);
return 0;
}

if (!psp->hdcp_context.hdcp_initialized) {
ret = psp_hdcp_init_shared_buf(psp);
if (ret)
	return ret;
}

ret = psp_hdcp_load(psp);
if (ret)
return ret;

return 0;
1239}

1241static int psp_hdcp_unload(struct psp_context *psp)
1242{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the unloading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
1263}

1265int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1266{
/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1274}

1276static int psp_hdcp_terminate(struct psp_context *psp)
1277{
int ret;

/*
* TODO: bypass the terminate in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->hdcp_context.hdcp_initialized) {
if (psp->hdcp_context.hdcp_shared_buf)
	goto out;
else
	return 0;
}

ret = psp_hdcp_unload(psp);
if (ret)
return ret;

psp->hdcp_context.hdcp_initialized = false0;

1299out:
/* free hdcp shared memory */
amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
	      &psp->hdcp_context.hdcp_shared_mc_addr,
	      &psp->hdcp_context.hdcp_shared_buf);

return 0;
1306}
1307// HDCP end

1309// DTM start
1310static int psp_dtm_init_shared_buf(struct psp_context *psp)
1311{
int ret;

/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for dtm ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE0x4000,
		      PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->dtm_context.dtm_shared_bo,
		      &psp->dtm_context.dtm_shared_mc_addr,
		      &psp->dtm_context.dtm_shared_buf);

return ret;
1325}

1327static int psp_dtm_load(struct psp_context *psp)
1328{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->ta_dtm_start_addr
), (psp->ta_dtm_ucode_size));

psp_prep_ta_load_cmd_buf(cmd,
		 psp->fw_pri_mc_addr,
		 psp->ta_dtm_ucode_size,
		 psp->dtm_context.dtm_shared_mc_addr,
		 PSP_DTM_SHARED_MEM_SIZE0x4000);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

if (!ret) {
psp->dtm_context.dtm_initialized = true1;
psp->dtm_context.session_id = cmd->resp.session_id;
rw_init(&psp->dtm_context.mutex, "pspdtm")_rw_init_flags(&psp->dtm_context.mutex, "pspdtm", 0, (
(void *)0));
}

kfree(cmd);

return ret;
1362}

1364static int psp_dtm_initialize(struct psp_context *psp)
1365{
int ret;

/*
* TODO: bypass the initialize in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->adev->psp.ta_dtm_ucode_size ||
   !psp->adev->psp.ta_dtm_start_addr) {
dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n")do { } while(0);
return 0;
}

if (!psp->dtm_context.dtm_initialized) {
ret = psp_dtm_init_shared_buf(psp);
if (ret)
	return ret;
}

ret = psp_dtm_load(psp);
if (ret)
return ret;

return 0;
1391}

1393static int psp_dtm_unload(struct psp_context *psp)
1394{
int ret;
struct psp_gfx_cmd_resp *cmd;

/*
* TODO: bypass the unloading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
1415}

1417int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1418{
/*
* TODO: bypass the loading in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1426}

1428static int psp_dtm_terminate(struct psp_context *psp)
1429{
int ret;

/*
* TODO: bypass the terminate in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->dtm_context.dtm_initialized) {
if (psp->dtm_context.dtm_shared_buf)
	goto out;
else
	return 0;
}

ret = psp_dtm_unload(psp);
if (ret)
return ret;

psp->dtm_context.dtm_initialized = false0;

1451out:
/* free hdcp shared memory */
amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
	      &psp->dtm_context.dtm_shared_mc_addr,
	      &psp->dtm_context.dtm_shared_buf);

return 0;
1458}
1459// DTM end

1461// RAP start
1462static int psp_rap_init_shared_buf(struct psp_context *psp)
1463{
int ret;

/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for rap ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE0x4000,
		      PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->rap_context.rap_shared_bo,
		      &psp->rap_context.rap_shared_mc_addr,
		      &psp->rap_context.rap_shared_buf);

return ret;
1477}

1479static int psp_rap_load(struct psp_context *psp)
1480{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

memset(psp->fw_pri_buf, 0, PSP_1_MEG)__builtin_memset((psp->fw_pri_buf), (0), (0x100000));
memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size)__builtin_memcpy((psp->fw_pri_buf), (psp->ta_rap_start_addr
), (psp->ta_rap_ucode_size));

psp_prep_ta_load_cmd_buf(cmd,
		 psp->fw_pri_mc_addr,
		 psp->ta_rap_ucode_size,
		 psp->rap_context.rap_shared_mc_addr,
		 PSP_RAP_SHARED_MEM_SIZE0x4000);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

if (!ret) {
psp->rap_context.rap_initialized = true1;
psp->rap_context.session_id = cmd->resp.session_id;
rw_init(&psp->rap_context.mutex, "psprap")_rw_init_flags(&psp->rap_context.mutex, "psprap", 0, (
(void *)0));
}

kfree(cmd);

return ret;
1508}

1510static int psp_rap_unload(struct psp_context *psp)
1511{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd, psp->fence_buf_mc_addr);

kfree(cmd);

return ret;
1526}

1528static int psp_rap_initialize(struct psp_context *psp)
1529{
int ret;

/*
* TODO: bypass the initialize in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;

if (!psp->adev->psp.ta_rap_ucode_size ||
   !psp->adev->psp.ta_rap_start_addr) {
dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n")do { } while(0);
return 0;
}

if (!psp->rap_context.rap_initialized) {
ret = psp_rap_init_shared_buf(psp);
if (ret)
	return ret;
}

ret = psp_rap_load(psp);
if (ret)
return ret;

ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE);
if (ret != TA_RAP_STATUS__SUCCESS) {
psp_rap_unload(psp);

amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
	      &psp->rap_context.rap_shared_mc_addr,
	      &psp->rap_context.rap_shared_buf);

psp->rap_context.rap_initialized = false0;

dev_warn(psp->adev->dev, "RAP TA initialize fail.\n")printf("drm:pid%d:%s *WARNING* " "RAP TA initialize fail.\n",
 ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}

return 0;
1569}

1571static int psp_rap_terminate(struct psp_context *psp)
1572{
int ret;

if (!psp->rap_context.rap_initialized)
return 0;

ret = psp_rap_unload(psp);

psp->rap_context.rap_initialized = false0;

/* free rap shared memory */
amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
	      &psp->rap_context.rap_shared_mc_addr,
	      &psp->rap_context.rap_shared_buf);

return ret;
1588}

1590int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1591{
struct ta_rap_shared_memory *rap_cmd;
int ret;

if (!psp->rap_context.rap_initialized)
return -EINVAL22;

if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
   ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
return -EINVAL22;

mutex_lock(&psp->rap_context.mutex)rw_enter_write(&psp->rap_context.mutex);

rap_cmd = (struct ta_rap_shared_memory *)
  psp->rap_context.rap_shared_buf;
memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory))__builtin_memset((rap_cmd), (0), (sizeof(struct ta_rap_shared_memory
)));

rap_cmd->cmd_id = ta_cmd_id;
rap_cmd->validation_method_id = METHOD_A;

ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
if (ret) {
mutex_unlock(&psp->rap_context.mutex)rw_exit_write(&psp->rap_context.mutex);
return ret;
}

mutex_unlock(&psp->rap_context.mutex)rw_exit_write(&psp->rap_context.mutex);

return rap_cmd->rap_status;
1620}
1621// RAP end

1623static int psp_hw_start(struct psp_context *psp)
1624{
struct amdgpu_device *adev = psp->adev;
int ret;

if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
if (psp->kdb_bin_size &&
    (psp->funcs->bootloader_load_kdb != NULL((void *)0))) {
	ret = psp_bootloader_load_kdb(psp)((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->
bootloader_load_kdb((psp)) : 0);
	if (ret) {
		DRM_ERROR("PSP load kdb failed!\n")__drm_err("PSP load kdb failed!\n");
		return ret;
	}
}

if (psp->spl_bin_size) {
	ret = psp_bootloader_load_spl(psp)((psp)->funcs->bootloader_load_spl ? (psp)->funcs->
bootloader_load_spl((psp)) : 0);
	if (ret) {
		DRM_ERROR("PSP load spl failed!\n")__drm_err("PSP load spl failed!\n");
		return ret;
	}
}

ret = psp_bootloader_load_sysdrv(psp)((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs
->bootloader_load_sysdrv((psp)) : 0);
if (ret) {
	DRM_ERROR("PSP load sysdrv failed!\n")__drm_err("PSP load sysdrv failed!\n");
	return ret;
}

ret = psp_bootloader_load_sos(psp)((psp)->funcs->bootloader_load_sos ? (psp)->funcs->
bootloader_load_sos((psp)) : 0);
if (ret) {
	DRM_ERROR("PSP load sos failed!\n")__drm_err("PSP load sos failed!\n");
	return ret;
}
}

ret = psp_ring_create(psp, PSP_RING_TYPE__KM)(psp)->funcs->ring_create((psp), (PSP_RING_TYPE__KM));
if (ret) {
DRM_ERROR("PSP create ring failed!\n")__drm_err("PSP create ring failed!\n");
return ret;
}

ret = psp_clear_vf_fw(psp);
if (ret) {
DRM_ERROR("PSP clear vf fw!\n")__drm_err("PSP clear vf fw!\n");
return ret;
}

ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n")__drm_err("PSP tmr init failed!\n");
return ret;
}

/*
* For ASICs with DF Cstate management centralized
* to PMFW, TMR setup should be performed after PMFW
* loaded and before other non-psp firmware loaded.
*/
if (psp->pmfw_centralized_cstate_management) {
ret = psp_load_smu_fw(psp);
if (ret)
	return ret;
}

ret = psp_tmr_load(psp);
if (ret) {
DRM_ERROR("PSP load tmr failed!\n")__drm_err("PSP load tmr failed!\n");
return ret;
}

return 0;
1695}

1697static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
	   enum psp_gfx_fw_type *type)
1699{
switch (ucode->ucode_id) {
case AMDGPU_UCODE_ID_SDMA0:
*type = GFX_FW_TYPE_SDMA0;
break;
case AMDGPU_UCODE_ID_SDMA1:
*type = GFX_FW_TYPE_SDMA1;
break;
case AMDGPU_UCODE_ID_SDMA2:
*type = GFX_FW_TYPE_SDMA2;
break;
case AMDGPU_UCODE_ID_SDMA3:
*type = GFX_FW_TYPE_SDMA3;
break;
case AMDGPU_UCODE_ID_SDMA4:
*type = GFX_FW_TYPE_SDMA4;
break;
case AMDGPU_UCODE_ID_SDMA5:
*type = GFX_FW_TYPE_SDMA5;
break;
case AMDGPU_UCODE_ID_SDMA6:
*type = GFX_FW_TYPE_SDMA6;
break;
case AMDGPU_UCODE_ID_SDMA7:
*type = GFX_FW_TYPE_SDMA7;
break;
case AMDGPU_UCODE_ID_CP_MES:
*type = GFX_FW_TYPE_CP_MES;
break;
case AMDGPU_UCODE_ID_CP_MES_DATA:
*type = GFX_FW_TYPE_MES_STACK;
break;
case AMDGPU_UCODE_ID_CP_CE:
*type = GFX_FW_TYPE_CP_CE;
break;
case AMDGPU_UCODE_ID_CP_PFP:
*type = GFX_FW_TYPE_CP_PFP;
break;
case AMDGPU_UCODE_ID_CP_ME:
*type = GFX_FW_TYPE_CP_ME;
break;
case AMDGPU_UCODE_ID_CP_MEC1:
*type = GFX_FW_TYPE_CP_MEC;
break;
case AMDGPU_UCODE_ID_CP_MEC1_JT:
*type = GFX_FW_TYPE_CP_MEC_ME1;
break;
case AMDGPU_UCODE_ID_CP_MEC2:
*type = GFX_FW_TYPE_CP_MEC;
break;
case AMDGPU_UCODE_ID_CP_MEC2_JT:
*type = GFX_FW_TYPE_CP_MEC_ME2;
break;
case AMDGPU_UCODE_ID_RLC_G:
*type = GFX_FW_TYPE_RLC_G;
break;
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
break;
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
*type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
break;
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
break;
case AMDGPU_UCODE_ID_RLC_IRAM:
*type = GFX_FW_TYPE_RLC_IRAM;
break;
case AMDGPU_UCODE_ID_RLC_DRAM:
*type = GFX_FW_TYPE_RLC_DRAM_BOOT;
break;
case AMDGPU_UCODE_ID_SMC:
*type = GFX_FW_TYPE_SMU;
break;
case AMDGPU_UCODE_ID_UVD:
*type = GFX_FW_TYPE_UVD;
break;
case AMDGPU_UCODE_ID_UVD1:
*type = GFX_FW_TYPE_UVD1;
break;
case AMDGPU_UCODE_ID_VCE:
*type = GFX_FW_TYPE_VCE;
break;
case AMDGPU_UCODE_ID_VCN:
*type = GFX_FW_TYPE_VCN;
break;
case AMDGPU_UCODE_ID_VCN1:
*type = GFX_FW_TYPE_VCN1;
break;
case AMDGPU_UCODE_ID_DMCU_ERAM:
*type = GFX_FW_TYPE_DMCU_ERAM;
break;
case AMDGPU_UCODE_ID_DMCU_INTV:
*type = GFX_FW_TYPE_DMCU_ISR;
break;
case AMDGPU_UCODE_ID_VCN0_RAM:
*type = GFX_FW_TYPE_VCN0_RAM;
break;
case AMDGPU_UCODE_ID_VCN1_RAM:
*type = GFX_FW_TYPE_VCN1_RAM;
break;
case AMDGPU_UCODE_ID_DMCUB:
*type = GFX_FW_TYPE_DMUB;
break;
case AMDGPU_UCODE_ID_MAXIMUM:
default:
return -EINVAL22;
}

return 0;
1809}

1811static void psp_print_fw_hdr(struct psp_context *psp,
	     struct amdgpu_firmware_info *ucode)
1813{
struct amdgpu_device *adev = psp->adev;
struct common_firmware_header *hdr;

switch (ucode->ucode_id) {
case AMDGPU_UCODE_ID_SDMA0:
case AMDGPU_UCODE_ID_SDMA1:
case AMDGPU_UCODE_ID_SDMA2:
case AMDGPU_UCODE_ID_SDMA3:
case AMDGPU_UCODE_ID_SDMA4:
case AMDGPU_UCODE_ID_SDMA5:
case AMDGPU_UCODE_ID_SDMA6:
case AMDGPU_UCODE_ID_SDMA7:
hdr = (struct common_firmware_header *)
	adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
amdgpu_ucode_print_sdma_hdr(hdr);
break;
case AMDGPU_UCODE_ID_CP_CE:
hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
amdgpu_ucode_print_gfx_hdr(hdr);
break;
case AMDGPU_UCODE_ID_CP_PFP:
hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
amdgpu_ucode_print_gfx_hdr(hdr);
break;
case AMDGPU_UCODE_ID_CP_ME:
hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
amdgpu_ucode_print_gfx_hdr(hdr);
break;
case AMDGPU_UCODE_ID_CP_MEC1:
hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
amdgpu_ucode_print_gfx_hdr(hdr);
break;
case AMDGPU_UCODE_ID_RLC_G:
hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
amdgpu_ucode_print_rlc_hdr(hdr);
break;
case AMDGPU_UCODE_ID_SMC:
hdr = (struct common_firmware_header *)adev->pm.fw->data;
amdgpu_ucode_print_smc_hdr(hdr);
break;
default:
break;
}
1857}

1859static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
		       struct psp_gfx_cmd_resp *cmd)
1861{
int ret;
uint64_t fw_mem_mc_addr = ucode->mc_addr;

memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp))__builtin_memset((cmd), (0), (sizeof(struct psp_gfx_cmd_resp)
));

cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr)((u32)(fw_mem_mc_addr));
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr)((u32)(((fw_mem_mc_addr) >> 16) >> 16));
cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;

ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
if (ret)
DRM_ERROR("Unknown firmware type\n")__drm_err("Unknown firmware type\n");

return ret;
1877}

1879static int psp_execute_np_fw_load(struct psp_context *psp,
	          struct amdgpu_firmware_info *ucode)
1881{
int ret = 0;

ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
if (ret)
return ret;

ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
		 psp->fence_buf_mc_addr);

return ret;
1892}

1894static int psp_load_smu_fw(struct psp_context *psp)
1895{
int ret;
struct amdgpu_device* adev = psp->adev;
struct amdgpu_firmware_info *ucode =
	&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
struct amdgpu_ras *ras = psp->ras.ras;

if (!ucode->fw || amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)))
return 0;


if (amdgpu_in_reset(adev) && ras && ras->supported) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
	DRM_WARN("Failed to set MP1 state prepare for reload\n")printk("\0014" "[" "drm" "] " "Failed to set MP1 state prepare for reload\n"
);
}
}

ret = psp_execute_np_fw_load(psp, ucode);

if (ret)
DRM_ERROR("PSP load smu failed!\n")__drm_err("PSP load smu failed!\n");

return ret;
1919}

1921static bool_Bool fw_load_skip_check(struct psp_context *psp,
	       struct amdgpu_firmware_info *ucode)
1923{
if (!ucode->fw)
return true1;

if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
   (psp_smu_reload_quirk(psp)((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk
((psp)) : 0) ||
    psp->autoload_supported ||
    psp->pmfw_centralized_cstate_management))
return true1;

if (amdgpu_sriov_vf(psp->adev)((psp->adev)->virt.caps & (1 << 2)) &&
  (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
   || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
/*skip ucode loading in SRIOV VF */
return true1;

if (psp->autoload_supported &&
   (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
/* skip mec JT when autoload is enabled */
return true1;

return false0;
1957}

1959static int psp_np_fw_load(struct psp_context *psp)
1960{
int i, ret;
struct amdgpu_firmware_info *ucode;
struct amdgpu_device* adev = psp->adev;

if (psp->autoload_supported &&
   !psp->pmfw_centralized_cstate_management) {
ret = psp_load_smu_fw(psp);
if (ret)
	return ret;
}

for (i = 0; i < adev->firmware.max_ucodes; i++) {
ucode = &adev->firmware.ucode[i];

if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
    !fw_load_skip_check(psp, ucode)) {
	ret = psp_load_smu_fw(psp);
	if (ret)
		return ret;
	continue;
}

if (fw_load_skip_check(psp, ucode))
	continue;

if (psp->autoload_supported &&
    (adev->asic_type == CHIP_SIENNA_CICHLID ||
     adev->asic_type == CHIP_NAVY_FLOUNDER) &&
    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
	/* PSP only receive one SDMA fw for sienna_cichlid,
	 * as all four sdma fw are same */
	continue;

psp_print_fw_hdr(psp, ucode);

ret = psp_execute_np_fw_load(psp, ucode);
if (ret)
	return ret;

/* Start rlc autoload after psp recieved all the gfx firmware */
if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ?
    AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
	ret = psp_rlc_autoload_start(psp);
	if (ret) {
		DRM_ERROR("Failed to start rlc autoload\n")__drm_err("Failed to start rlc autoload\n");
		return ret;
	}
}
}

return 0;
2014}

2016static int psp_load_fw(struct amdgpu_device *adev)
2017{
int ret;
struct psp_context *psp = &adev->psp;

if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) && amdgpu_in_reset(adev)) {
psp_ring_stop(psp, PSP_RING_TYPE__KM)(psp)->funcs->ring_stop((psp), (PSP_RING_TYPE__KM)); /* should not destroy ring, only stop */
goto skip_memalloc;
}

psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!psp->cmd)
return -ENOMEM12;

ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG0x100000, PSP_1_MEG0x100000,
			AMDGPU_GEM_DOMAIN_GTT0x2,
			&psp->fw_pri_bo,
			&psp->fw_pri_mc_addr,
			&psp->fw_pri_buf);
if (ret)
goto failed;

ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE0x1000, PAGE_SIZE(1 << 12),
			AMDGPU_GEM_DOMAIN_VRAM0x4,
			&psp->fence_buf_bo,
			&psp->fence_buf_mc_addr,
			&psp->fence_buf);
if (ret)
goto failed;

ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE0x1000, PAGE_SIZE(1 << 12),
		      AMDGPU_GEM_DOMAIN_VRAM0x4,
		      &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
		      (void **)&psp->cmd_buf_mem);
if (ret)
goto failed;

memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE)__builtin_memset((psp->fence_buf), (0), (0x1000));

ret = psp_ring_init(psp, PSP_RING_TYPE__KM)(psp)->funcs->ring_init((psp), (PSP_RING_TYPE__KM));
if (ret) {
DRM_ERROR("PSP ring init failed!\n")__drm_err("PSP ring init failed!\n");
goto failed;
}

2061skip_memalloc:
ret = psp_hw_start(psp);
if (ret)
goto failed;

ret = psp_np_fw_load(psp);
if (ret)
goto failed;

ret = psp_asd_load(psp);
if (ret) {
DRM_ERROR("PSP load asd failed!\n")__drm_err("PSP load asd failed!\n");
return ret;
}

if (psp->adev->psp.ta_fw) {
ret = psp_ras_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "RAS: Failed to initialize RAS\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
			"RAS: Failed to initialize RAS\n")printf("drm:pid%d:%s *ERROR* " "RAS: Failed to initialize RAS\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_hdcp_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "HDCP: Failed to initialize HDCP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"HDCP: Failed to initialize HDCP\n")printf("drm:pid%d:%s *ERROR* " "HDCP: Failed to initialize HDCP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_dtm_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "DTM: Failed to initialize DTM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"DTM: Failed to initialize DTM\n")printf("drm:pid%d:%s *ERROR* " "DTM: Failed to initialize DTM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_rap_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "RAP: Failed to initialize RAP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"RAP: Failed to initialize RAP\n")printf("drm:pid%d:%s *ERROR* " "RAP: Failed to initialize RAP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

return 0;

2100failed:
/*
* all cleanup jobs (xgmi terminate, ras terminate,
* ring destroy, cmd/fence/fw buffers destory,
* psp->cmd destory) are delayed to psp_hw_fini
*/
return ret;
2107}

2109static int psp_hw_init(void *handle)
2110{
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

mutex_lock(&adev->firmware.mutex)rw_enter_write(&adev->firmware.mutex);
/*
* This sequence is just used on hw_init only once, no need on
* resume.
*/
ret = amdgpu_ucode_init_bo(adev);
if (ret)
goto failed;

ret = psp_load_fw(adev);
if (ret) {
DRM_ERROR("PSP firmware loading failed\n")__drm_err("PSP firmware loading failed\n");
goto failed;
}

mutex_unlock(&adev->firmware.mutex)rw_exit_write(&adev->firmware.mutex);
return 0;

2132failed:
adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
mutex_unlock(&adev->firmware.mutex)rw_exit_write(&adev->firmware.mutex);
return -EINVAL22;
2136}

2138static int psp_hw_fini(void *handle)
2139{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
int ret;

if (psp->adev->psp.ta_fw) {
psp_ras_terminate(psp);
psp_rap_terminate(psp);
psp_dtm_terminate(psp);
psp_hdcp_terminate(psp);
}

psp_asd_unload(psp);
ret = psp_clear_vf_fw(psp);
if (ret) {
DRM_ERROR("PSP clear vf fw!\n")__drm_err("PSP clear vf fw!\n");
return ret;
}

psp_tmr_terminate(psp);
psp_ring_destroy(psp, PSP_RING_TYPE__KM)((psp)->funcs->ring_destroy((psp), (PSP_RING_TYPE__KM))
);

amdgpu_bo_free_kernel(&psp->fw_pri_bo,
	      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
amdgpu_bo_free_kernel(&psp->fence_buf_bo,
	      &psp->fence_buf_mc_addr, &psp->fence_buf);
amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
	      (void **)&psp->cmd_buf_mem);

kfree(psp->cmd);
psp->cmd = NULL((void *)0);

return 0;
2172}

2174static int psp_suspend(void *handle)
2175{
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;

if (adev->gmc.xgmi.num_physical_nodes > 1 &&
   psp->xgmi_context.initialized == 1) {
ret = psp_xgmi_terminate(psp);
if (ret) {
	DRM_ERROR("Failed to terminate xgmi ta\n")__drm_err("Failed to terminate xgmi ta\n");
	return ret;
}
}

if (psp->adev->psp.ta_fw) {
ret = psp_ras_terminate(psp);
if (ret) {
	DRM_ERROR("Failed to terminate ras ta\n")__drm_err("Failed to terminate ras ta\n");
	return ret;
}
ret = psp_hdcp_terminate(psp);
if (ret) {
	DRM_ERROR("Failed to terminate hdcp ta\n")__drm_err("Failed to terminate hdcp ta\n");
	return ret;
}
ret = psp_dtm_terminate(psp);
if (ret) {
	DRM_ERROR("Failed to terminate dtm ta\n")__drm_err("Failed to terminate dtm ta\n");
	return ret;
}
ret = psp_rap_terminate(psp);
if (ret) {
	DRM_ERROR("Failed to terminate rap ta\n")__drm_err("Failed to terminate rap ta\n");
	return ret;
}
}

ret = psp_asd_unload(psp);
if (ret) {
DRM_ERROR("Failed to unload asd\n")__drm_err("Failed to unload asd\n");
return ret;
}

ret = psp_tmr_terminate(psp);
if (ret) {
DRM_ERROR("Failed to terminate tmr\n")__drm_err("Failed to terminate tmr\n");
return ret;
}

ret = psp_ring_stop(psp, PSP_RING_TYPE__KM)(psp)->funcs->ring_stop((psp), (PSP_RING_TYPE__KM));
if (ret) {
DRM_ERROR("PSP ring stop failed\n")__drm_err("PSP ring stop failed\n");
return ret;
}

return 0;
2231}

2233static int psp_resume(void *handle)
2234{
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;

DRM_INFO("PSP is resuming...\n")printk("\0016" "[" "drm" "] " "PSP is resuming...\n");

ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME)((psp)->funcs->mem_training ? (psp)->funcs->mem_training
((psp), (PSP_MEM_TRAIN_RESUME)) : 0);
if (ret) {
DRM_ERROR("Failed to process memory training!\n")__drm_err("Failed to process memory training!\n");
return ret;
}

mutex_lock(&adev->firmware.mutex)rw_enter_write(&adev->firmware.mutex);

ret = psp_hw_start(psp);
if (ret)
goto failed;

ret = psp_np_fw_load(psp);
if (ret)
goto failed;

ret = psp_asd_load(psp);
if (ret) {
DRM_ERROR("PSP load asd failed!\n")__drm_err("PSP load asd failed!\n");
goto failed;
}

if (adev->gmc.xgmi.num_physical_nodes > 1) {
ret = psp_xgmi_initialize(psp);
/* Warning the XGMI seesion initialize failure
 * Instead of stop driver initialization
 */
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "XGMI: Failed to initialize XGMI session\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"XGMI: Failed to initialize XGMI session\n")printf("drm:pid%d:%s *ERROR* " "XGMI: Failed to initialize XGMI session\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

if (psp->adev->psp.ta_fw) {
ret = psp_ras_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "RAS: Failed to initialize RAS\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
			"RAS: Failed to initialize RAS\n")printf("drm:pid%d:%s *ERROR* " "RAS: Failed to initialize RAS\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_hdcp_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "HDCP: Failed to initialize HDCP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"HDCP: Failed to initialize HDCP\n")printf("drm:pid%d:%s *ERROR* " "HDCP: Failed to initialize HDCP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_dtm_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "DTM: Failed to initialize DTM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"DTM: Failed to initialize DTM\n")printf("drm:pid%d:%s *ERROR* " "DTM: Failed to initialize DTM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

ret = psp_rap_initialize(psp);
if (ret)
	dev_err(psp->adev->dev,printf("drm:pid%d:%s *ERROR* " "RAP: Failed to initialize RAP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
		"RAP: Failed to initialize RAP\n")printf("drm:pid%d:%s *ERROR* " "RAP: Failed to initialize RAP\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

mutex_unlock(&adev->firmware.mutex)rw_exit_write(&adev->firmware.mutex);

return 0;

2299failed:
DRM_ERROR("PSP resume failed\n")__drm_err("PSP resume failed\n");
mutex_unlock(&adev->firmware.mutex)rw_exit_write(&adev->firmware.mutex);
return ret;
2303}

2305int psp_gpu_reset(struct amdgpu_device *adev)
2306{
int ret;

if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0;

mutex_lock(&adev->psp.mutex)rw_enter_write(&adev->psp.mutex);
ret = psp_mode1_reset(&adev->psp)((&adev->psp)->funcs->mode1_reset ? (&adev->
psp)->funcs->mode1_reset((&adev->psp)) : 0);
mutex_unlock(&adev->psp.mutex)rw_exit_write(&adev->psp.mutex);

return ret;
2317}

2319int psp_rlc_autoload_start(struct psp_context *psp)
2320{
int ret;
struct psp_gfx_cmd_resp *cmd;

cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL(0x0001 | 0x0004));
if (!cmd)
return -ENOMEM12;

cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;

ret = psp_cmd_submit_buf(psp, NULL((void *)0), cmd,
		 psp->fence_buf_mc_addr);
kfree(cmd);
return ret;
2334}

2336int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
	uint64_t cmd_gpu_addr, int cmd_size)
2338{
struct amdgpu_firmware_info ucode = {0};

ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
AMDGPU_UCODE_ID_VCN0_RAM;
ucode.mc_addr = cmd_gpu_addr;
ucode.ucode_size = cmd_size;

return psp_execute_np_fw_load(&adev->psp, &ucode);
2347}

2349int psp_ring_cmd_submit(struct psp_context *psp,
	uint64_t cmd_buf_mc_addr,
	uint64_t fence_mc_addr,
	int index)
2353{
unsigned int psp_write_ptr_reg = 0;
struct psp_gfx_rb_frame *write_frame;
struct psp_ring *ring = &psp->km_ring;
struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
struct amdgpu_device *adev = psp->adev;
uint32_t ring_size_dw = ring->ring_size / 4;
uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;

/* KM (GPCOM) prepare write pointer */
psp_write_ptr_reg = psp_ring_get_wptr(psp)(psp)->funcs->ring_get_wptr((psp));

/* Update KM RB frame pointer to new frame */
/* write_frame ptr increments by size of rb_frame in bytes */
/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
if ((psp_write_ptr_reg % ring_size_dw) == 0)
write_frame = ring_buffer_start;
else
write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
/* Check invalid write_frame ptr address */
if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",__drm_err("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n"
, ring_buffer_start, ring_buffer_end, write_frame)
	  ring_buffer_start, ring_buffer_end, write_frame)__drm_err("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n"
, ring_buffer_start, ring_buffer_end, write_frame);
DRM_ERROR("write_frame is pointing to address out of bounds\n")__drm_err("write_frame is pointing to address out of bounds\n"
);
return -EINVAL22;
}

/* Initialize KM RB frame */
memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame))__builtin_memset((write_frame), (0), (sizeof(struct psp_gfx_rb_frame
)));

/* Update KM RB frame */
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr)((u32)(((cmd_buf_mc_addr) >> 16) >> 16));
write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr)((u32)(cmd_buf_mc_addr));
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr)((u32)(((fence_mc_addr) >> 16) >> 16));
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr)((u32)(fence_mc_addr));
write_frame->fence_value = index;
amdgpu_asic_flush_hdp(adev, NULL)(adev)->asic_funcs->flush_hdp((adev), (((void *)0)));

/* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
psp_ring_set_wptr(psp, psp_write_ptr_reg)(psp)->funcs->ring_set_wptr((psp), (psp_write_ptr_reg));
return 0;
2397}

2399int psp_init_asd_microcode(struct psp_context *psp,
	   const char *chip_name)
2401{
struct amdgpu_device *adev = psp->adev;
char fw_name[30];
const struct psp_firmware_header_v1_0 *asd_hdr;
int err = 0;

if (!chip_name) {
dev_err(adev->dev, "invalid chip name for asd microcode\n")printf("drm:pid%d:%s *ERROR* " "invalid chip name for asd microcode\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}

snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
if (err)
goto out;

err = amdgpu_ucode_validate(adev->psp.asd_fw);
if (err)
goto out;

asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version)((__uint32_t)(asd_hdr->header.ucode_version));
adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version)((__uint32_t)(asd_hdr->ucode_feature_version));
adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes)((__uint32_t)(asd_hdr->header.ucode_size_bytes));
adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
		le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes)((__uint32_t)(asd_hdr->header.ucode_array_offset_bytes));
return 0;
2428out:
dev_err(adev->dev, "fail to initialize asd microcode\n")printf("drm:pid%d:%s *ERROR* " "fail to initialize asd microcode\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL((void *)0);
return err;
2433}

2435int psp_init_sos_microcode(struct psp_context *psp,
	   const char *chip_name)
2437{
struct amdgpu_device *adev = psp->adev;
char fw_name[30];
const struct psp_firmware_header_v1_0 *sos_hdr;
const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
int err = 0;

if (!chip_name) {
1
Assuming 'chip_name' is non-null→
2
←
Taking false branch→
dev_err(adev->dev, "invalid chip name for sos microcode\n")printf("drm:pid%d:%s *ERROR* " "invalid chip name for sos microcode\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}

snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3
←
Calling 'request_firmware'→
7
←
Returning from 'request_firmware'→
if (err)
8
←
Assuming 'err' is 0→
9
←
Taking false branch→
goto out;

err = amdgpu_ucode_validate(adev->psp.sos_fw);
if (err)
10
←
Assuming 'err' is 0→
11
←
Taking false branch→
goto out;

sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
12
←
Access to field 'data' results in a dereference of a null pointer (loaded from field 'sos_fw')
amdgpu_ucode_print_psp_hdr(&sos_hdr->header);

switch (sos_hdr->header.header_version_major) {
case 1:
adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version)((__uint32_t)(sos_hdr->header.ucode_version));
adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version)((__uint32_t)(sos_hdr->ucode_feature_version));
adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes)((__uint32_t)(sos_hdr->sos_size_bytes));
adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes)((__uint32_t)(sos_hdr->sos_offset_bytes));
adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes)((__uint32_t)(sos_hdr->header.ucode_array_offset_bytes));
adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
		le32_to_cpu(sos_hdr->sos_offset_bytes)((__uint32_t)(sos_hdr->sos_offset_bytes));
if (sos_hdr->header.header_version_minor == 1) {
	sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes)((__uint32_t)(sos_hdr_v1_1->toc_size_bytes));
	adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
			le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes)((__uint32_t)(sos_hdr_v1_1->toc_offset_bytes));
	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes)((__uint32_t)(sos_hdr_v1_1->kdb_size_bytes));
	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
			le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes)((__uint32_t)(sos_hdr_v1_1->kdb_offset_bytes));
}
if (sos_hdr->header.header_version_minor == 2) {
	sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes)((__uint32_t)(sos_hdr_v1_2->kdb_size_bytes));
	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
				    le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes)((__uint32_t)(sos_hdr_v1_2->kdb_offset_bytes));
}
if (sos_hdr->header.header_version_minor == 3) {
	sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes)((__uint32_t)(sos_hdr_v1_3->v1_1.toc_size_bytes));
	adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
		le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes)((__uint32_t)(sos_hdr_v1_3->v1_1.toc_offset_bytes));
	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes)((__uint32_t)(sos_hdr_v1_3->v1_1.kdb_size_bytes));
	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
		le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes)((__uint32_t)(sos_hdr_v1_3->v1_1.kdb_offset_bytes));
	adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes)((__uint32_t)(sos_hdr_v1_3->spl_size_bytes));
	adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
		le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes)((__uint32_t)(sos_hdr_v1_3->spl_offset_bytes));
}
break;
default:
dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "unsupported psp sos firmware\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
	"unsupported psp sos firmware\n")printf("drm:pid%d:%s *ERROR* " "unsupported psp sos firmware\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
err = -EINVAL22;
goto out;
}

return 0;
2509out:
dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "failed to init sos firmware\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
"failed to init sos firmware\n")printf("drm:pid%d:%s *ERROR* " "failed to init sos firmware\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
release_firmware(adev->psp.sos_fw);
adev->psp.sos_fw = NULL((void *)0);

return err;
2516}

2518int parse_ta_bin_descriptor(struct psp_context *psp,
	    const struct ta_fw_bin_desc *desc,
	    const struct ta_firmware_header_v2_0 *ta_hdr)
2521{
uint8_t *ucode_start_addr  = NULL((void *)0);

if (!psp || !desc || !ta_hdr)
return -EINVAL22;

ucode_start_addr  = (uint8_t *)ta_hdr +
	    le32_to_cpu(desc->offset_bytes)((__uint32_t)(desc->offset_bytes)) +
	    le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ta_hdr->header.ucode_array_offset_bytes));

switch (desc->fw_type) {
case TA_FW_TYPE_PSP_ASD:
psp->asd_fw_version 	   = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->asd_feature_version   = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->asd_ucode_size 	   = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->asd_start_addr 	   = ucode_start_addr;
psp->asd_fw                = psp->ta_fw;
break;
case TA_FW_TYPE_PSP_XGMI:
psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->ta_xgmi_start_addr    = ucode_start_addr;
break;
case TA_FW_TYPE_PSP_RAS:
psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->ta_ras_start_addr     = ucode_start_addr;
break;
case TA_FW_TYPE_PSP_HDCP:
psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->ta_hdcp_start_addr    = ucode_start_addr;
break;
case TA_FW_TYPE_PSP_DTM:
psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->ta_dtm_start_addr     = ucode_start_addr;
break;
case TA_FW_TYPE_PSP_RAP:
psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version)((__uint32_t)(desc->fw_version));
psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes)((__uint32_t)(desc->size_bytes));
psp->ta_rap_start_addr     = ucode_start_addr;
break;
default:
dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type)printf("drm:pid%d:%s *WARNING* " "Unsupported TA type: %d\n",
 ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , desc->
fw_type);
break;
}

return 0;
2570}

2572int psp_init_ta_microcode(struct psp_context *psp,
	  const char *chip_name)
2574{
struct amdgpu_device *adev = psp->adev;
char fw_name[30];
const struct ta_firmware_header_v2_0 *ta_hdr;
int err = 0;
int ta_index = 0;

if (!chip_name) {
dev_err(adev->dev, "invalid chip name for ta microcode\n")printf("drm:pid%d:%s *ERROR* " "invalid chip name for ta microcode\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}

snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
if (err)
goto out;

err = amdgpu_ucode_validate(adev->psp.ta_fw);
if (err)
goto out;

ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;

if (le16_to_cpu(ta_hdr->header.header_version_major)((__uint16_t)(ta_hdr->header.header_version_major)) != 2) {
dev_err(adev->dev, "unsupported TA header version\n")printf("drm:pid%d:%s *ERROR* " "unsupported TA header version\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
err = -EINVAL22;
goto out;
}

if (le32_to_cpu(ta_hdr->ta_fw_bin_count)((__uint32_t)(ta_hdr->ta_fw_bin_count)) >= UCODE_MAX_TA_PACKAGING((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header
) - 4) / sizeof(struct ta_fw_bin_desc))) {
dev_err(adev->dev, "packed TA count exceeds maximum limit\n")printf("drm:pid%d:%s *ERROR* " "packed TA count exceeds maximum limit\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
err = -EINVAL22;
goto out;
}

for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count)((__uint32_t)(ta_hdr->ta_fw_bin_count)); ta_index++) {
err = parse_ta_bin_descriptor(psp,
			      &ta_hdr->ta_fw_bin[ta_index],
			      ta_hdr);
if (err)
	goto out;
}

return 0;
2618out:
dev_err(adev->dev, "fail to initialize ta microcode\n")printf("drm:pid%d:%s *ERROR* " "fail to initialize ta microcode\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
release_firmware(adev->psp.ta_fw);
adev->psp.ta_fw = NULL((void *)0);
return err;
2623}

2625static int psp_set_clockgating_state(void *handle,
		     enum amd_clockgating_state state)
2627{
return 0;
2629}

2631static int psp_set_powergating_state(void *handle,
		     enum amd_powergating_state state)
2633{
return 0;
2635}

2637static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
			 struct device_attribute *attr,
			 char *buf)
2640{
STUB()do { printf("%s: stub\n", __func__); } while(0);
return -ENOSYS78;
2643#ifdef notyet
struct drm_device *ddev = dev_get_drvdata(dev)((void *)0);
struct amdgpu_device *adev = drm_to_adev(ddev);
uint32_t fw_ver;
int ret;

if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
DRM_INFO("PSP block is not ready yet.")printk("\0016" "[" "drm" "] " "PSP block is not ready yet.");
return -EBUSY16;
}

mutex_lock(&adev->psp.mutex)rw_enter_write(&adev->psp.mutex);
ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver)((&adev->psp)->funcs->read_usbc_pd_fw ? (&adev
->psp)->funcs->read_usbc_pd_fw((&adev->psp), &
fw_ver) : -22);
mutex_unlock(&adev->psp.mutex)rw_exit_write(&adev->psp.mutex);

if (ret) {
DRM_ERROR("Failed to read USBC PD FW, err = %d", ret)__drm_err("Failed to read USBC PD FW, err = %d", ret);
return ret;
}

return snprintf(buf, PAGE_SIZE(1 << 12), "%x\n", fw_ver);
2664}

2666static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
				       struct device_attribute *attr,
				       const char *buf,
				       size_t count)
2670{
struct drm_device *ddev = dev_get_drvdata(dev)((void *)0);
struct amdgpu_device *adev = drm_to_adev(ddev);
void *cpu_addr;
dma_addr_t dma_addr;
int ret;
char fw_name[100];
const struct firmware *usbc_pd_fw;

if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
DRM_INFO("PSP block is not ready yet.")printk("\0016" "[" "drm" "] " "PSP block is not ready yet.");
return -EBUSY16;
}

snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
if (ret)
goto fail;

/* We need contiguous physical mem to place the FW  for psp to access */
cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL(0x0001 | 0x0004));

ret = dma_mapping_error(adev->dev, dma_addr);
if (ret)
goto rel_buf;

memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size)__builtin_memcpy((cpu_addr), (usbc_pd_fw->data), (usbc_pd_fw
->size));

/*
* x86 specific workaround.
* Without it the buffer is invisible in PSP.
*
* TODO Remove once PSP starts snooping CPU cache
*/
2704#ifdef CONFIG_X861
clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
2706#endif

mutex_lock(&adev->psp.mutex)rw_enter_write(&adev->psp.mutex);
ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr)((&adev->psp)->funcs->load_usbc_pd_fw ? (&adev
->psp)->funcs->load_usbc_pd_fw((&adev->psp), (
dma_addr)) : -22);
mutex_unlock(&adev->psp.mutex)rw_exit_write(&adev->psp.mutex);

2712rel_buf:
dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
release_firmware(usbc_pd_fw);

2716fail:
if (ret) {
DRM_ERROR("Failed to load USBC PD FW, err = %d", ret)__drm_err("Failed to load USBC PD FW, err = %d", ret);
return ret;
}

return count;
2723#endif
2724}

2726static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,struct device_attribute dev_attr_usbc_pd_fw
   psp_usbc_pd_fw_sysfs_read,struct device_attribute dev_attr_usbc_pd_fw
   psp_usbc_pd_fw_sysfs_write)struct device_attribute dev_attr_usbc_pd_fw;



2732const struct amd_ip_funcs psp_ip_funcs = {
.name = "psp",
.early_init = psp_early_init,
.late_init = NULL((void *)0),
.sw_init = psp_sw_init,
.sw_fini = psp_sw_fini,
.hw_init = psp_hw_init,
.hw_fini = psp_hw_fini,
.suspend = psp_suspend,
.resume = psp_resume,
.is_idle = NULL((void *)0),
.check_soft_reset = NULL((void *)0),
.wait_for_idle = NULL((void *)0),
.soft_reset = NULL((void *)0),
.set_clockgating_state = psp_set_clockgating_state,
.set_powergating_state = psp_set_powergating_state,
2748};

2750static int psp_sysfs_init(struct amdgpu_device *adev)
2751{
int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw)0;

if (ret)
DRM_ERROR("Failed to create USBC PD FW control file!")__drm_err("Failed to create USBC PD FW control file!");

return ret;
2758}

2760static void psp_sysfs_fini(struct amdgpu_device *adev)
2761{
device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
2763}

2765const struct amdgpu_ip_block_version psp_v3_1_ip_block =
2766{
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 3,
.minor = 1,
.rev = 0,
.funcs = &psp_ip_funcs,
2772};

2774const struct amdgpu_ip_block_version psp_v10_0_ip_block =
2775{
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 10,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
2781};

2783const struct amdgpu_ip_block_version psp_v11_0_ip_block =
2784{
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 11,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
2790};

2792const struct amdgpu_ip_block_version psp_v12_0_ip_block =
2793{
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 12,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
2799};

←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2 
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5 
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11 
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var))	((type)(__uintptr_t)(const void *)(var))
14#endif
15 
16struct firmware {
17	size_t size;
18	const u8 *data;
19};
20 
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23    struct device *device)
24{
25	int r;
26	struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27	    M_WAITOK0x0001 | M_ZERO0x0008);
28	r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29	if (r != 0) {
4
←
Assuming 'r' is not equal to 0→
5
←
Taking true branch→
30		free(f, M_DRM145, sizeof(struct firmware));
31		*fw = NULL((void *)0);
6
←
Null pointer value stored to field 'sos_fw'→
32		return -r;
33	} else  {
34		*fw = f;
35		return 0;
36	}
37}
38 
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41    struct device *device)
42{
43	return request_firmware(fw, name, device);
44}
45 
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47 
48static inline void
49release_firmware(const struct firmware *fw)
50{
51	if (fw)
52		free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53	free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55 
56#endif