File: | dev/pci/drm/amd/amdgpu/amdgpu_i2c.c |
Warning: | line 420, column 3 4th function call argument is an uninitialized value |
Press '?' to see keyboard shortcuts
Keyboard shortcuts:
1 | /* | |||
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |||
3 | * Copyright 2008 Red Hat Inc. | |||
4 | * | |||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
6 | * copy of this software and associated documentation files (the "Software"), | |||
7 | * to deal in the Software without restriction, including without limitation | |||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
9 | * and/or sell copies of the Software, and to permit persons to whom the | |||
10 | * Software is furnished to do so, subject to the following conditions: | |||
11 | * | |||
12 | * The above copyright notice and this permission notice shall be included in | |||
13 | * all copies or substantial portions of the Software. | |||
14 | * | |||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
21 | * OTHER DEALINGS IN THE SOFTWARE. | |||
22 | * | |||
23 | * Authors: Dave Airlie | |||
24 | * Alex Deucher | |||
25 | */ | |||
26 | ||||
27 | #include <linux/export.h> | |||
28 | #include <linux/pci.h> | |||
29 | ||||
30 | #include <drm/drm_edid.h> | |||
31 | #include <drm/amdgpu_drm.h> | |||
32 | #include "amdgpu.h" | |||
33 | #include "amdgpu_i2c.h" | |||
34 | #include "amdgpu_atombios.h" | |||
35 | #include "atom.h" | |||
36 | #include "atombios_dp.h" | |||
37 | #include "atombios_i2c.h" | |||
38 | ||||
39 | #include <dev/i2c/i2cvar.h> | |||
40 | #include <dev/i2c/i2c_bitbang.h> | |||
41 | ||||
42 | /* bit banging i2c */ | |||
43 | static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) | |||
44 | { | |||
45 | struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
46 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
47 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
48 | uint32_t temp; | |||
49 | ||||
50 | mutex_lock(&i2c->mutex)rw_enter_write(&i2c->mutex); | |||
51 | ||||
52 | /* switch the pads to ddc mode */ | |||
53 | if (rec->hw_capable) { | |||
54 | temp = RREG32(rec->mask_clk_reg)amdgpu_device_rreg(adev, (rec->mask_clk_reg), 0); | |||
55 | temp &= ~(1 << 16); | |||
56 | WREG32(rec->mask_clk_reg, temp)amdgpu_device_wreg(adev, (rec->mask_clk_reg), (temp), 0); | |||
57 | } | |||
58 | ||||
59 | /* clear the output pin values */ | |||
60 | temp = RREG32(rec->a_clk_reg)amdgpu_device_rreg(adev, (rec->a_clk_reg), 0) & ~rec->a_clk_mask; | |||
61 | WREG32(rec->a_clk_reg, temp)amdgpu_device_wreg(adev, (rec->a_clk_reg), (temp), 0); | |||
62 | ||||
63 | temp = RREG32(rec->a_data_reg)amdgpu_device_rreg(adev, (rec->a_data_reg), 0) & ~rec->a_data_mask; | |||
64 | WREG32(rec->a_data_reg, temp)amdgpu_device_wreg(adev, (rec->a_data_reg), (temp), 0); | |||
65 | ||||
66 | /* set the pins to input */ | |||
67 | temp = RREG32(rec->en_clk_reg)amdgpu_device_rreg(adev, (rec->en_clk_reg), 0) & ~rec->en_clk_mask; | |||
68 | WREG32(rec->en_clk_reg, temp)amdgpu_device_wreg(adev, (rec->en_clk_reg), (temp), 0); | |||
69 | ||||
70 | temp = RREG32(rec->en_data_reg)amdgpu_device_rreg(adev, (rec->en_data_reg), 0) & ~rec->en_data_mask; | |||
71 | WREG32(rec->en_data_reg, temp)amdgpu_device_wreg(adev, (rec->en_data_reg), (temp), 0); | |||
72 | ||||
73 | /* mask the gpio pins for software use */ | |||
74 | temp = RREG32(rec->mask_clk_reg)amdgpu_device_rreg(adev, (rec->mask_clk_reg), 0) | rec->mask_clk_mask; | |||
75 | WREG32(rec->mask_clk_reg, temp)amdgpu_device_wreg(adev, (rec->mask_clk_reg), (temp), 0); | |||
76 | temp = RREG32(rec->mask_clk_reg)amdgpu_device_rreg(adev, (rec->mask_clk_reg), 0); | |||
77 | ||||
78 | temp = RREG32(rec->mask_data_reg)amdgpu_device_rreg(adev, (rec->mask_data_reg), 0) | rec->mask_data_mask; | |||
79 | WREG32(rec->mask_data_reg, temp)amdgpu_device_wreg(adev, (rec->mask_data_reg), (temp), 0); | |||
80 | temp = RREG32(rec->mask_data_reg)amdgpu_device_rreg(adev, (rec->mask_data_reg), 0); | |||
81 | ||||
82 | return 0; | |||
83 | } | |||
84 | ||||
85 | static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) | |||
86 | { | |||
87 | struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); | |||
88 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
89 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
90 | uint32_t temp; | |||
91 | ||||
92 | /* unmask the gpio pins for software use */ | |||
93 | temp = RREG32(rec->mask_clk_reg)amdgpu_device_rreg(adev, (rec->mask_clk_reg), 0) & ~rec->mask_clk_mask; | |||
94 | WREG32(rec->mask_clk_reg, temp)amdgpu_device_wreg(adev, (rec->mask_clk_reg), (temp), 0); | |||
95 | temp = RREG32(rec->mask_clk_reg)amdgpu_device_rreg(adev, (rec->mask_clk_reg), 0); | |||
96 | ||||
97 | temp = RREG32(rec->mask_data_reg)amdgpu_device_rreg(adev, (rec->mask_data_reg), 0) & ~rec->mask_data_mask; | |||
98 | WREG32(rec->mask_data_reg, temp)amdgpu_device_wreg(adev, (rec->mask_data_reg), (temp), 0); | |||
99 | temp = RREG32(rec->mask_data_reg)amdgpu_device_rreg(adev, (rec->mask_data_reg), 0); | |||
100 | ||||
101 | mutex_unlock(&i2c->mutex)rw_exit_write(&i2c->mutex); | |||
102 | } | |||
103 | ||||
104 | static int amdgpu_i2c_get_clock(void *i2c_priv) | |||
105 | { | |||
106 | struct amdgpu_i2c_chan *i2c = i2c_priv; | |||
107 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
108 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
109 | uint32_t val; | |||
110 | ||||
111 | /* read the value off the pin */ | |||
112 | val = RREG32(rec->y_clk_reg)amdgpu_device_rreg(adev, (rec->y_clk_reg), 0); | |||
113 | val &= rec->y_clk_mask; | |||
114 | ||||
115 | return (val != 0); | |||
116 | } | |||
117 | ||||
118 | ||||
119 | static int amdgpu_i2c_get_data(void *i2c_priv) | |||
120 | { | |||
121 | struct amdgpu_i2c_chan *i2c = i2c_priv; | |||
122 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
123 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
124 | uint32_t val; | |||
125 | ||||
126 | /* read the value off the pin */ | |||
127 | val = RREG32(rec->y_data_reg)amdgpu_device_rreg(adev, (rec->y_data_reg), 0); | |||
128 | val &= rec->y_data_mask; | |||
129 | ||||
130 | return (val != 0); | |||
131 | } | |||
132 | ||||
133 | static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) | |||
134 | { | |||
135 | struct amdgpu_i2c_chan *i2c = i2c_priv; | |||
136 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
137 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
138 | uint32_t val; | |||
139 | ||||
140 | /* set pin direction */ | |||
141 | val = RREG32(rec->en_clk_reg)amdgpu_device_rreg(adev, (rec->en_clk_reg), 0) & ~rec->en_clk_mask; | |||
142 | val |= clock ? 0 : rec->en_clk_mask; | |||
143 | WREG32(rec->en_clk_reg, val)amdgpu_device_wreg(adev, (rec->en_clk_reg), (val), 0); | |||
144 | } | |||
145 | ||||
146 | static void amdgpu_i2c_set_data(void *i2c_priv, int data) | |||
147 | { | |||
148 | struct amdgpu_i2c_chan *i2c = i2c_priv; | |||
149 | struct amdgpu_device *adev = drm_to_adev(i2c->dev); | |||
150 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; | |||
151 | uint32_t val; | |||
152 | ||||
153 | /* set pin direction */ | |||
154 | val = RREG32(rec->en_data_reg)amdgpu_device_rreg(adev, (rec->en_data_reg), 0) & ~rec->en_data_mask; | |||
155 | val |= data ? 0 : rec->en_data_mask; | |||
156 | WREG32(rec->en_data_reg, val)amdgpu_device_wreg(adev, (rec->en_data_reg), (val), 0); | |||
157 | } | |||
158 | ||||
159 | void amdgpu_bb_set_bits(void *, uint32_t); | |||
160 | void amdgpu_bb_set_dir(void *, uint32_t); | |||
161 | uint32_t amdgpu_bb_read_bits(void *); | |||
162 | ||||
163 | int amdgpu_acquire_bus(void *, int); | |||
164 | void amdgpu_release_bus(void *, int); | |||
165 | int amdgpu_send_start(void *, int); | |||
166 | int amdgpu_send_stop(void *, int); | |||
167 | int amdgpu_initiate_xfer(void *, i2c_addr_t, int); | |||
168 | int amdgpu_read_byte(void *, u_int8_t *, int); | |||
169 | int amdgpu_write_byte(void *, u_int8_t, int); | |||
170 | ||||
171 | #define AMDGPU_BB_SDA(1 << 0) (1 << I2C_BIT_SDA0) | |||
172 | #define AMDGPU_BB_SCL(1 << 1) (1 << I2C_BIT_SCL1) | |||
173 | ||||
174 | struct i2c_bitbang_ops amdgpu_bbops = { | |||
175 | amdgpu_bb_set_bits, | |||
176 | amdgpu_bb_set_dir, | |||
177 | amdgpu_bb_read_bits, | |||
178 | { AMDGPU_BB_SDA(1 << 0), AMDGPU_BB_SCL(1 << 1), 0, 0 } | |||
179 | }; | |||
180 | ||||
181 | void | |||
182 | amdgpu_bb_set_bits(void *cookie, uint32_t bits) | |||
183 | { | |||
184 | amdgpu_i2c_set_clock(cookie, bits & AMDGPU_BB_SCL(1 << 1)); | |||
185 | amdgpu_i2c_set_data(cookie, bits & AMDGPU_BB_SDA(1 << 0)); | |||
186 | } | |||
187 | ||||
188 | void | |||
189 | amdgpu_bb_set_dir(void *cookie, uint32_t bits) | |||
190 | { | |||
191 | } | |||
192 | ||||
193 | uint32_t | |||
194 | amdgpu_bb_read_bits(void *cookie) | |||
195 | { | |||
196 | uint32_t bits = 0; | |||
197 | ||||
198 | if (amdgpu_i2c_get_clock(cookie)) | |||
199 | bits |= AMDGPU_BB_SCL(1 << 1); | |||
200 | if (amdgpu_i2c_get_data(cookie)) | |||
201 | bits |= AMDGPU_BB_SDA(1 << 0); | |||
202 | ||||
203 | return bits; | |||
204 | } | |||
205 | ||||
206 | int | |||
207 | amdgpu_acquire_bus(void *cookie, int flags) | |||
208 | { | |||
209 | struct amdgpu_i2c_chan *i2c = cookie; | |||
210 | amdgpu_i2c_pre_xfer(&i2c->adapter); | |||
211 | return (0); | |||
212 | } | |||
213 | ||||
214 | void | |||
215 | amdgpu_release_bus(void *cookie, int flags) | |||
216 | { | |||
217 | struct amdgpu_i2c_chan *i2c = cookie; | |||
218 | amdgpu_i2c_post_xfer(&i2c->adapter); | |||
219 | } | |||
220 | ||||
221 | int | |||
222 | amdgpu_send_start(void *cookie, int flags) | |||
223 | { | |||
224 | return (i2c_bitbang_send_start(cookie, flags, &amdgpu_bbops)); | |||
225 | } | |||
226 | ||||
227 | int | |||
228 | amdgpu_send_stop(void *cookie, int flags) | |||
229 | { | |||
230 | return (i2c_bitbang_send_stop(cookie, flags, &amdgpu_bbops)); | |||
231 | } | |||
232 | ||||
233 | int | |||
234 | amdgpu_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) | |||
235 | { | |||
236 | return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &amdgpu_bbops)); | |||
237 | } | |||
238 | ||||
239 | int | |||
240 | amdgpu_read_byte(void *cookie, u_int8_t *bytep, int flags) | |||
241 | { | |||
242 | return (i2c_bitbang_read_byte(cookie, bytep, flags, &amdgpu_bbops)); | |||
243 | } | |||
244 | ||||
245 | int | |||
246 | amdgpu_write_byte(void *cookie, u_int8_t byte, int flags) | |||
247 | { | |||
248 | return (i2c_bitbang_write_byte(cookie, byte, flags, &amdgpu_bbops)); | |||
249 | } | |||
250 | ||||
251 | static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { | |||
252 | .master_xfer = amdgpu_atombios_i2c_xfer, | |||
253 | .functionality = amdgpu_atombios_i2c_func, | |||
254 | }; | |||
255 | ||||
256 | struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, | |||
257 | const struct amdgpu_i2c_bus_rec *rec, | |||
258 | const char *name) | |||
259 | { | |||
260 | struct amdgpu_i2c_chan *i2c; | |||
261 | int ret; | |||
262 | ||||
263 | /* don't add the mm_i2c bus unless hw_i2c is enabled */ | |||
264 | if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) | |||
265 | return NULL((void *)0); | |||
266 | ||||
267 | i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL(0x0001 | 0x0004)); | |||
268 | if (i2c == NULL((void *)0)) | |||
269 | return NULL((void *)0); | |||
270 | ||||
271 | i2c->rec = *rec; | |||
272 | #ifdef __linux__ | |||
273 | i2c->adapter.owner = THIS_MODULE((void *)0); | |||
274 | i2c->adapter.class = I2C_CLASS_DDC; | |||
275 | i2c->adapter.dev.parent = &dev->pdev->dev; | |||
276 | #endif | |||
277 | i2c->dev = dev; | |||
278 | i2c_set_adapdata(&i2c->adapter, i2c); | |||
279 | rw_init(&i2c->mutex, "agiic")_rw_init_flags(&i2c->mutex, "agiic", 0, ((void *)0)); | |||
280 | if (rec->hw_capable && | |||
281 | amdgpu_hw_i2c) { | |||
282 | /* hw i2c using atom */ | |||
283 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |||
284 | "AMDGPU i2c hw bus %s", name); | |||
285 | i2c->adapter.algo = &amdgpu_atombios_i2c_algo; | |||
286 | ret = i2c_add_adapter(&i2c->adapter)0; | |||
287 | if (ret) | |||
288 | goto out_free; | |||
289 | } else { | |||
290 | /* set the amdgpu bit adapter */ | |||
291 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), | |||
292 | "AMDGPU i2c bit bus %s", name); | |||
293 | i2c->adapter.algo_data = &i2c->bit; | |||
294 | #ifdef notyet | |||
295 | i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; | |||
296 | i2c->bit.post_xfer = amdgpu_i2c_post_xfer; | |||
297 | i2c->bit.setsda = amdgpu_i2c_set_data; | |||
298 | i2c->bit.setscl = amdgpu_i2c_set_clock; | |||
299 | i2c->bit.getsda = amdgpu_i2c_get_data; | |||
300 | i2c->bit.getscl = amdgpu_i2c_get_clock; | |||
301 | i2c->bit.udelay = 10; | |||
302 | i2c->bit.timeout = usecs_to_jiffies(2200)(((uint64_t)(2200)) * hz / 1000000); /* from VESA */ | |||
303 | i2c->bit.data = i2c; | |||
304 | #else | |||
305 | i2c->bit.ic.ic_cookie = i2c; | |||
306 | i2c->bit.ic.ic_acquire_bus = amdgpu_acquire_bus; | |||
307 | i2c->bit.ic.ic_release_bus = amdgpu_release_bus; | |||
308 | i2c->bit.ic.ic_send_start = amdgpu_send_start; | |||
309 | i2c->bit.ic.ic_send_stop = amdgpu_send_stop; | |||
310 | i2c->bit.ic.ic_initiate_xfer = amdgpu_initiate_xfer; | |||
311 | i2c->bit.ic.ic_read_byte = amdgpu_read_byte; | |||
312 | i2c->bit.ic.ic_write_byte = amdgpu_write_byte; | |||
313 | #endif | |||
314 | ret = i2c_bit_add_bus(&i2c->adapter); | |||
315 | if (ret) { | |||
316 | DRM_ERROR("Failed to register bit i2c %s\n", name)__drm_err("Failed to register bit i2c %s\n", name); | |||
317 | goto out_free; | |||
318 | } | |||
319 | } | |||
320 | ||||
321 | return i2c; | |||
322 | out_free: | |||
323 | kfree(i2c); | |||
324 | return NULL((void *)0); | |||
325 | ||||
326 | } | |||
327 | ||||
328 | void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) | |||
329 | { | |||
330 | if (!i2c) | |||
331 | return; | |||
332 | WARN_ON(i2c->has_aux)({ int __ret = !!(i2c->has_aux); if (__ret) printf("WARNING %s failed at %s:%d\n" , "i2c->has_aux", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c" , 332); __builtin_expect(!!(__ret), 0); }); | |||
333 | i2c_del_adapter(&i2c->adapter); | |||
334 | kfree(i2c); | |||
335 | } | |||
336 | ||||
337 | /* Add the default buses */ | |||
338 | void amdgpu_i2c_init(struct amdgpu_device *adev) | |||
339 | { | |||
340 | if (amdgpu_hw_i2c) | |||
341 | DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n")printk("\0016" "[" "drm" "] " "hw_i2c forced on, you may experience display detection problems!\n" ); | |||
342 | ||||
343 | amdgpu_atombios_i2c_init(adev); | |||
344 | } | |||
345 | ||||
346 | /* remove all the buses */ | |||
347 | void amdgpu_i2c_fini(struct amdgpu_device *adev) | |||
348 | { | |||
349 | int i; | |||
350 | ||||
351 | for (i = 0; i < AMDGPU_MAX_I2C_BUS16; i++) { | |||
352 | if (adev->i2c_bus[i]) { | |||
353 | amdgpu_i2c_destroy(adev->i2c_bus[i]); | |||
354 | adev->i2c_bus[i] = NULL((void *)0); | |||
355 | } | |||
356 | } | |||
357 | } | |||
358 | ||||
359 | /* Add additional buses */ | |||
360 | void amdgpu_i2c_add(struct amdgpu_device *adev, | |||
361 | const struct amdgpu_i2c_bus_rec *rec, | |||
362 | const char *name) | |||
363 | { | |||
364 | struct drm_device *dev = adev_to_drm(adev); | |||
365 | int i; | |||
366 | ||||
367 | for (i = 0; i < AMDGPU_MAX_I2C_BUS16; i++) { | |||
368 | if (!adev->i2c_bus[i]) { | |||
369 | adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); | |||
370 | return; | |||
371 | } | |||
372 | } | |||
373 | } | |||
374 | ||||
375 | /* looks up bus based on id */ | |||
376 | struct amdgpu_i2c_chan * | |||
377 | amdgpu_i2c_lookup(struct amdgpu_device *adev, | |||
378 | const struct amdgpu_i2c_bus_rec *i2c_bus) | |||
379 | { | |||
380 | int i; | |||
381 | ||||
382 | for (i = 0; i < AMDGPU_MAX_I2C_BUS16; i++) { | |||
383 | if (adev->i2c_bus[i] && | |||
384 | (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { | |||
385 | return adev->i2c_bus[i]; | |||
386 | } | |||
387 | } | |||
388 | return NULL((void *)0); | |||
389 | } | |||
390 | ||||
391 | static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, | |||
392 | u8 slave_addr, | |||
393 | u8 addr, | |||
394 | u8 *val) | |||
395 | { | |||
396 | u8 out_buf[2]; | |||
397 | u8 in_buf[2]; | |||
398 | struct i2c_msg msgs[] = { | |||
399 | { | |||
400 | .addr = slave_addr, | |||
401 | .flags = 0, | |||
402 | .len = 1, | |||
403 | .buf = out_buf, | |||
404 | }, | |||
405 | { | |||
406 | .addr = slave_addr, | |||
407 | .flags = I2C_M_RD0x0001, | |||
408 | .len = 1, | |||
409 | .buf = in_buf, | |||
410 | } | |||
411 | }; | |||
412 | ||||
413 | out_buf[0] = addr; | |||
414 | out_buf[1] = 0; | |||
415 | ||||
416 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { | |||
417 | *val = in_buf[0]; | |||
418 | DRM_DEBUG("val = 0x%02x\n", *val)__drm_dbg(DRM_UT_CORE, "val = 0x%02x\n", *val); | |||
419 | } else { | |||
420 | DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x read failed\n", addr , *val) | |||
| ||||
421 | addr, *val)__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x read failed\n", addr , *val); | |||
422 | } | |||
423 | } | |||
424 | ||||
425 | static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, | |||
426 | u8 slave_addr, | |||
427 | u8 addr, | |||
428 | u8 val) | |||
429 | { | |||
430 | uint8_t out_buf[2]; | |||
431 | struct i2c_msg msg = { | |||
432 | .addr = slave_addr, | |||
433 | .flags = 0, | |||
434 | .len = 2, | |||
435 | .buf = out_buf, | |||
436 | }; | |||
437 | ||||
438 | out_buf[0] = addr; | |||
439 | out_buf[1] = val; | |||
440 | ||||
441 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) | |||
442 | DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x write failed\n", addr , val) | |||
443 | addr, val)__drm_dbg(DRM_UT_CORE, "i2c 0x%02x 0x%02x write failed\n", addr , val); | |||
444 | } | |||
445 | ||||
446 | /* ddc router switching */ | |||
447 | void | |||
448 | amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) | |||
449 | { | |||
450 | u8 val = 0; | |||
451 | ||||
452 | if (!amdgpu_connector->router.ddc_valid) | |||
453 | return; | |||
454 | ||||
455 | if (!amdgpu_connector->router_bus) | |||
456 | return; | |||
457 | ||||
458 | amdgpu_i2c_get_byte(amdgpu_connector->router_bus, | |||
459 | amdgpu_connector->router.i2c_addr, | |||
460 | 0x3, &val); | |||
461 | val &= ~amdgpu_connector->router.ddc_mux_control_pin; | |||
462 | amdgpu_i2c_put_byte(amdgpu_connector->router_bus, | |||
463 | amdgpu_connector->router.i2c_addr, | |||
464 | 0x3, val); | |||
465 | amdgpu_i2c_get_byte(amdgpu_connector->router_bus, | |||
466 | amdgpu_connector->router.i2c_addr, | |||
467 | 0x1, &val); | |||
468 | val &= ~amdgpu_connector->router.ddc_mux_control_pin; | |||
469 | val |= amdgpu_connector->router.ddc_mux_state; | |||
470 | amdgpu_i2c_put_byte(amdgpu_connector->router_bus, | |||
471 | amdgpu_connector->router.i2c_addr, | |||
472 | 0x1, val); | |||
473 | } | |||
474 | ||||
475 | /* clock/data router switching */ | |||
476 | void | |||
477 | amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector) | |||
478 | { | |||
479 | u8 val; | |||
| ||||
480 | ||||
481 | if (!amdgpu_connector->router.cd_valid) | |||
482 | return; | |||
483 | ||||
484 | if (!amdgpu_connector->router_bus) | |||
485 | return; | |||
486 | ||||
487 | amdgpu_i2c_get_byte(amdgpu_connector->router_bus, | |||
488 | amdgpu_connector->router.i2c_addr, | |||
489 | 0x3, &val); | |||
490 | val &= ~amdgpu_connector->router.cd_mux_control_pin; | |||
491 | amdgpu_i2c_put_byte(amdgpu_connector->router_bus, | |||
492 | amdgpu_connector->router.i2c_addr, | |||
493 | 0x3, val); | |||
494 | amdgpu_i2c_get_byte(amdgpu_connector->router_bus, | |||
495 | amdgpu_connector->router.i2c_addr, | |||
496 | 0x1, &val); | |||
497 | val &= ~amdgpu_connector->router.cd_mux_control_pin; | |||
498 | val |= amdgpu_connector->router.cd_mux_state; | |||
499 | amdgpu_i2c_put_byte(amdgpu_connector->router_bus, | |||
500 | amdgpu_connector->router.i2c_addr, | |||
501 | 0x1, val); | |||
502 | } |