| File: | dev/pci/drm/i915/gt/uc/intel_guc_fw.c |
| Warning: | line 51, column 2 Value stored to 'copied' is never read |
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| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright © 2014-2019 Intel Corporation |
| 4 | * |
| 5 | * Authors: |
| 6 | * Vinit Azad <vinit.azad@intel.com> |
| 7 | * Ben Widawsky <ben@bwidawsk.net> |
| 8 | * Dave Gordon <david.s.gordon@intel.com> |
| 9 | * Alex Dai <yu.dai@intel.com> |
| 10 | */ |
| 11 | |
| 12 | #include "gt/intel_gt.h" |
| 13 | #include "intel_guc_fw.h" |
| 14 | #include "i915_drv.h" |
| 15 | |
| 16 | static void guc_prepare_xfer(struct intel_uncore *uncore) |
| 17 | { |
| 18 | u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES(1<<0) | |
| 19 | GUC_ENABLE_READ_CACHE_LOGIC(1<<1) | |
| 20 | GUC_ENABLE_MIA_CACHING(1<<2) | |
| 21 | GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA(1<<9) | |
| 22 | GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA(1<<10) | |
| 23 | GUC_ENABLE_MIA_CLOCK_GATING(1<<15); |
| 24 | |
| 25 | /* Must program this register before loading the ucode with DMA */ |
| 26 | intel_uncore_write(uncore, GUC_SHIM_CONTROL((const i915_reg_t){ .reg = (0xc064) }), shim_flags); |
| 27 | |
| 28 | if (IS_GEN9_LP(uncore->i915)((0 + (&(uncore->i915)->__info)->gen == (9)) && ((&(uncore->i915)->__info)->is_lp))) |
| 29 | intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG((const i915_reg_t){ .reg = (0x138140) }), GT_DOORBELL_ENABLE(1<<0)); |
| 30 | else |
| 31 | intel_uncore_write(uncore, GEN9_GT_PM_CONFIG((const i915_reg_t){ .reg = (0x13816c) }), GT_DOORBELL_ENABLE(1<<0)); |
| 32 | |
| 33 | if (IS_GEN(uncore->i915, 9)(0 + (&(uncore->i915)->__info)->gen == (9))) { |
| 34 | /* DOP Clock Gating Enable for GuC clocks */ |
| 35 | intel_uncore_rmw(uncore, GEN7_MISCCPCTL((const i915_reg_t){ .reg = (0x9424) }), |
| 36 | 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE(1 << 4)); |
| 37 | |
| 38 | /* allows for 5us (in 10ns units) before GT can go to RC6 */ |
| 39 | intel_uncore_write(uncore, GUC_ARAT_C6DIS((const i915_reg_t){ .reg = (0xA178) }), 0x1FF); |
| 40 | } |
| 41 | } |
| 42 | |
| 43 | /* Copy RSA signature from the fw image to HW for verification */ |
| 44 | static void guc_xfer_rsa(struct intel_uc_fw *guc_fw, |
| 45 | struct intel_uncore *uncore) |
| 46 | { |
| 47 | u32 rsa[UOS_RSA_SCRATCH_COUNT64]; |
| 48 | size_t copied; |
| 49 | int i; |
| 50 | |
| 51 | copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa)); |
Value stored to 'copied' is never read | |
| 52 | GEM_BUG_ON(copied < sizeof(rsa))((void)0); |
| 53 | |
| 54 | for (i = 0; i < UOS_RSA_SCRATCH_COUNT64; i++) |
| 55 | intel_uncore_write(uncore, UOS_RSA_SCRATCH(i)((const i915_reg_t){ .reg = (0xc200 + (i) * 4) }), rsa[i]); |
| 56 | } |
| 57 | |
| 58 | /* |
| 59 | * Read the GuC status register (GUC_STATUS) and store it in the |
| 60 | * specified location; then return a boolean indicating whether |
| 61 | * the value matches either of two values representing completion |
| 62 | * of the GuC boot process. |
| 63 | * |
| 64 | * This is used for polling the GuC status in a wait_for() |
| 65 | * loop below. |
| 66 | */ |
| 67 | static inline bool_Bool guc_ready(struct intel_uncore *uncore, u32 *status) |
| 68 | { |
| 69 | u32 val = intel_uncore_read(uncore, GUC_STATUS((const i915_reg_t){ .reg = (0xc000) })); |
| 70 | u32 uk_val = val & GS_UKERNEL_MASK(0xFF << 8); |
| 71 | |
| 72 | *status = val; |
| 73 | return (uk_val == GS_UKERNEL_READY(0xF0 << 8)) || |
| 74 | ((val & GS_MIA_CORE_STATE(0x01 << 16)) && (uk_val == GS_UKERNEL_LAPIC_DONE(0x30 << 8))); |
| 75 | } |
| 76 | |
| 77 | static int guc_wait_ucode(struct intel_uncore *uncore) |
| 78 | { |
| 79 | u32 status; |
| 80 | int ret; |
| 81 | |
| 82 | /* |
| 83 | * Wait for the GuC to start up. |
| 84 | * NB: Docs recommend not using the interrupt for completion. |
| 85 | * Measurements indicate this should take no more than 20ms, so a |
| 86 | * timeout here indicates that the GuC has failed and is unusable. |
| 87 | * (Higher levels of the driver may decide to reset the GuC and |
| 88 | * attempt the ucode load again if this happens.) |
| 89 | */ |
| 90 | ret = wait_for(guc_ready(uncore, &status), 100)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (((100) * 1000))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((guc_ready (uncore, &status)))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__ <<= 1; } ret__; }); |
| 91 | DRM_DEBUG_DRIVER("GuC status %#x\n", status)__drm_dbg(DRM_UT_DRIVER, "GuC status %#x\n", status); |
| 92 | |
| 93 | if ((status & GS_BOOTROM_MASK(0x7F << 1)) == GS_BOOTROM_RSA_FAILED(0x50 << 1)) { |
| 94 | DRM_ERROR("GuC firmware signature verification failed\n")__drm_err("GuC firmware signature verification failed\n"); |
| 95 | ret = -ENOEXEC8; |
| 96 | } |
| 97 | |
| 98 | if ((status & GS_UKERNEL_MASK(0xFF << 8)) == GS_UKERNEL_EXCEPTION(0x70 << 8)) { |
| 99 | DRM_ERROR("GuC firmware exception. EIP: %#x\n",__drm_err("GuC firmware exception. EIP: %#x\n", intel_uncore_read (uncore, ((const i915_reg_t){ .reg = (0xc180 + (13) * 4) }))) |
| 100 | intel_uncore_read(uncore, SOFT_SCRATCH(13)))__drm_err("GuC firmware exception. EIP: %#x\n", intel_uncore_read (uncore, ((const i915_reg_t){ .reg = (0xc180 + (13) * 4) }))); |
| 101 | ret = -ENXIO6; |
| 102 | } |
| 103 | |
| 104 | return ret; |
| 105 | } |
| 106 | |
| 107 | /** |
| 108 | * intel_guc_fw_upload() - load GuC uCode to device |
| 109 | * @guc: intel_guc structure |
| 110 | * |
| 111 | * Called from intel_uc_init_hw() during driver load, resume from sleep and |
| 112 | * after a GPU reset. |
| 113 | * |
| 114 | * The firmware image should have already been fetched into memory, so only |
| 115 | * check that fetch succeeded, and then transfer the image to the h/w. |
| 116 | * |
| 117 | * Return: non-zero code on error |
| 118 | */ |
| 119 | int intel_guc_fw_upload(struct intel_guc *guc) |
| 120 | { |
| 121 | struct intel_gt *gt = guc_to_gt(guc); |
| 122 | struct intel_uncore *uncore = gt->uncore; |
| 123 | int ret; |
| 124 | |
| 125 | guc_prepare_xfer(uncore); |
| 126 | |
| 127 | /* |
| 128 | * Note that GuC needs the CSS header plus uKernel code to be copied |
| 129 | * by the DMA engine in one operation, whereas the RSA signature is |
| 130 | * loaded via MMIO. |
| 131 | */ |
| 132 | guc_xfer_rsa(&guc->fw, uncore); |
| 133 | |
| 134 | /* |
| 135 | * Current uCode expects the code to be loaded at 8k; locations below |
| 136 | * this are used for the stack. |
| 137 | */ |
| 138 | ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE(1<<4)); |
| 139 | if (ret) |
| 140 | goto out; |
| 141 | |
| 142 | ret = guc_wait_ucode(uncore); |
| 143 | if (ret) |
| 144 | goto out; |
| 145 | |
| 146 | intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING); |
| 147 | return 0; |
| 148 | |
| 149 | out: |
| 150 | intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL); |
| 151 | return ret; |
| 152 | } |