File: | dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c |
Warning: | line 199, column 42 Dereference of null pointer |
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1 | /* | |||
2 | * Copyright 2012-16 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | * Authors: AMD | |||
23 | * | |||
24 | */ | |||
25 | ||||
26 | #include "core_types.h" | |||
27 | #include "clk_mgr_internal.h" | |||
28 | ||||
29 | #include "dce/dce_11_0_d.h" | |||
30 | #include "dce/dce_11_0_sh_mask.h" | |||
31 | #include "dce110_clk_mgr.h" | |||
32 | #include "../clk_mgr/dce100/dce_clk_mgr.h" | |||
33 | ||||
34 | /* set register offset */ | |||
35 | #define SR(reg_name).reg_name = mmreg_name\ | |||
36 | .reg_name = mm ## reg_name | |||
37 | ||||
38 | /* set register offset with instance */ | |||
39 | #define SRI(reg_name, block, id).reg_name = mmblockid_reg_name\ | |||
40 | .reg_name = mm ## block ## id ## _ ## reg_name | |||
41 | ||||
42 | static const struct clk_mgr_registers disp_clk_regs = { | |||
43 | CLK_COMMON_REG_LIST_DCE_BASE().DPREFCLK_CNTL = 0x118, .DENTIST_DISPCLK_CNTL = 0x124 | |||
44 | }; | |||
45 | ||||
46 | static const struct clk_mgr_shift disp_clk_shift = { | |||
47 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT).DPREFCLK_SRC_SEL = 0x0, .DENTIST_DPREFCLK_WDIVIDER = 0x18 | |||
48 | }; | |||
49 | ||||
50 | static const struct clk_mgr_mask disp_clk_mask = { | |||
51 | CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK).DPREFCLK_SRC_SEL = 0x7, .DENTIST_DPREFCLK_WDIVIDER = 0x7f000000 | |||
52 | }; | |||
53 | ||||
54 | static const struct state_dependent_clocks dce110_max_clks_by_state[] = { | |||
55 | /*ClocksStateInvalid - should not be used*/ | |||
56 | { .display_clk_khz = 0, .pixel_clk_khz = 0 }, | |||
57 | /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ | |||
58 | { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, | |||
59 | /*ClocksStateLow*/ | |||
60 | { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, | |||
61 | /*ClocksStateNominal*/ | |||
62 | { .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, | |||
63 | /*ClocksStatePerformance*/ | |||
64 | { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; | |||
65 | ||||
66 | static int determine_sclk_from_bounding_box( | |||
67 | const struct dc *dc, | |||
68 | int required_sclk) | |||
69 | { | |||
70 | int i; | |||
71 | ||||
72 | /* | |||
73 | * Some asics do not give us sclk levels, so we just report the actual | |||
74 | * required sclk | |||
75 | */ | |||
76 | if (dc->sclk_lvls.num_levels == 0) | |||
77 | return required_sclk; | |||
78 | ||||
79 | for (i = 0; i < dc->sclk_lvls.num_levels; i++) { | |||
80 | if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) | |||
81 | return dc->sclk_lvls.clocks_in_khz[i]; | |||
82 | } | |||
83 | /* | |||
84 | * even maximum level could not satisfy requirement, this | |||
85 | * is unexpected at this stage, should have been caught at | |||
86 | * validation time | |||
87 | */ | |||
88 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c" , 88); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
89 | return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; | |||
90 | } | |||
91 | ||||
92 | uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) | |||
93 | { | |||
94 | uint8_t j; | |||
95 | uint32_t min_vertical_blank_time = -1; | |||
96 | ||||
97 | for (j = 0; j < context->stream_count; j++) { | |||
98 | struct dc_stream_state *stream = context->streams[j]; | |||
99 | uint32_t vertical_blank_in_pixels = 0; | |||
100 | uint32_t vertical_blank_time = 0; | |||
101 | uint32_t vertical_total_min = stream->timing.v_total; | |||
102 | struct dc_crtc_timing_adjust adjust = stream->adjust; | |||
103 | if (adjust.v_total_max != adjust.v_total_min) | |||
104 | vertical_total_min = adjust.v_total_min; | |||
105 | ||||
106 | vertical_blank_in_pixels = stream->timing.h_total * | |||
107 | (vertical_total_min | |||
108 | - stream->timing.v_addressable); | |||
109 | vertical_blank_time = vertical_blank_in_pixels | |||
110 | * 10000 / stream->timing.pix_clk_100hz; | |||
111 | ||||
112 | if (min_vertical_blank_time > vertical_blank_time) | |||
113 | min_vertical_blank_time = vertical_blank_time; | |||
114 | } | |||
115 | ||||
116 | return min_vertical_blank_time; | |||
117 | } | |||
118 | ||||
119 | void dce110_fill_display_configs( | |||
120 | const struct dc_state *context, | |||
121 | struct dm_pp_display_configuration *pp_display_cfg) | |||
122 | { | |||
123 | int j; | |||
124 | int num_cfgs = 0; | |||
125 | ||||
126 | for (j = 0; j < context->stream_count; j++) { | |||
127 | int k; | |||
128 | ||||
129 | const struct dc_stream_state *stream = context->streams[j]; | |||
130 | struct dm_pp_single_disp_config *cfg = | |||
131 | &pp_display_cfg->disp_configs[num_cfgs]; | |||
132 | const struct pipe_ctx *pipe_ctx = NULL((void *)0); | |||
133 | ||||
134 | for (k = 0; k < MAX_PIPES6; k++) | |||
135 | if (stream == context->res_ctx.pipe_ctx[k].stream) { | |||
136 | pipe_ctx = &context->res_ctx.pipe_ctx[k]; | |||
137 | break; | |||
138 | } | |||
139 | ||||
140 | ASSERT(pipe_ctx != NULL)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx != ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_ctx != ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c" , 140); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
141 | ||||
142 | /* only notify active stream */ | |||
143 | if (stream->dpms_off) | |||
144 | continue; | |||
145 | ||||
146 | num_cfgs++; | |||
147 | cfg->signal = pipe_ctx->stream->signal; | |||
148 | cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; | |||
149 | cfg->src_height = stream->src.height; | |||
150 | cfg->src_width = stream->src.width; | |||
151 | cfg->ddi_channel_mapping = | |||
152 | stream->link->ddi_channel_mapping.raw; | |||
153 | cfg->transmitter = | |||
154 | stream->link->link_enc->transmitter; | |||
155 | cfg->link_settings.lane_count = | |||
156 | stream->link->cur_link_settings.lane_count; | |||
157 | cfg->link_settings.link_rate = | |||
158 | stream->link->cur_link_settings.link_rate; | |||
159 | cfg->link_settings.link_spread = | |||
160 | stream->link->cur_link_settings.link_spread; | |||
161 | cfg->sym_clock = stream->phy_pix_clk; | |||
162 | /* Round v_refresh*/ | |||
163 | cfg->v_refresh = stream->timing.pix_clk_100hz * 100; | |||
164 | cfg->v_refresh /= stream->timing.h_total; | |||
165 | cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) | |||
166 | / stream->timing.v_total; | |||
167 | } | |||
168 | ||||
169 | pp_display_cfg->display_count = num_cfgs; | |||
170 | } | |||
171 | ||||
172 | void dce11_pplib_apply_display_requirements( | |||
173 | struct dc *dc, | |||
174 | struct dc_state *context) | |||
175 | { | |||
176 | struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; | |||
177 | int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ4; | |||
178 | ||||
179 | if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) | |||
180 | memory_type_multiplier = MEMORY_TYPE_HBM2; | |||
181 | ||||
182 | pp_display_cfg->all_displays_in_sync = | |||
183 | context->bw_ctx.bw.dce.all_displays_in_sync; | |||
184 | pp_display_cfg->nb_pstate_switch_disable = | |||
185 | context->bw_ctx.bw.dce.nbp_state_change_enable == false0; | |||
186 | pp_display_cfg->cpu_cc6_disable = | |||
187 | context->bw_ctx.bw.dce.cpuc_state_change_enable == false0; | |||
188 | pp_display_cfg->cpu_pstate_disable = | |||
189 | context->bw_ctx.bw.dce.cpup_state_change_enable == false0; | |||
190 | pp_display_cfg->cpu_pstate_separation_time = | |||
191 | context->bw_ctx.bw.dce.blackout_recovery_time_us; | |||
192 | ||||
193 | /* | |||
194 | * TODO: determine whether the bandwidth has reached memory's limitation | |||
195 | * , then change minimum memory clock based on real-time bandwidth | |||
196 | * limitation. | |||
197 | */ | |||
198 | if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev)((dc->ctx->asic_id.hw_internal_rev >= 40) && (dc->ctx->asic_id.hw_internal_rev < 0xFF)) && (context->stream_count >= 2)) { | |||
199 | pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,(((pp_display_cfg->min_memory_clock_khz)>((uint32_t) div64_s64 ( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000)))?(pp_display_cfg->min_memory_clock_khz):((uint32_t ) div64_s64( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000))) | |||
| ||||
200 | (uint32_t) div64_s64((((pp_display_cfg->min_memory_clock_khz)>((uint32_t) div64_s64 ( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000)))?(pp_display_cfg->min_memory_clock_khz):((uint32_t ) div64_s64( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000))) | |||
201 | div64_s64(dc->bw_vbios->high_yclk.value,(((pp_display_cfg->min_memory_clock_khz)>((uint32_t) div64_s64 ( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000)))?(pp_display_cfg->min_memory_clock_khz):((uint32_t ) div64_s64( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000))) | |||
202 | memory_type_multiplier), 10000))(((pp_display_cfg->min_memory_clock_khz)>((uint32_t) div64_s64 ( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000)))?(pp_display_cfg->min_memory_clock_khz):((uint32_t ) div64_s64( div64_s64(dc->bw_vbios->high_yclk.value, memory_type_multiplier ), 10000))); | |||
203 | } else { | |||
204 | pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz | |||
205 | / memory_type_multiplier; | |||
206 | } | |||
207 | ||||
208 | pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( | |||
209 | dc, | |||
210 | context->bw_ctx.bw.dce.sclk_khz); | |||
211 | ||||
212 | /* | |||
213 | * As workaround for >4x4K lightup set dcfclock to min_engine_clock value. | |||
214 | * This is not required for less than 5 displays, | |||
215 | * thus don't request decfclk in dc to avoid impact | |||
216 | * on power saving. | |||
217 | * | |||
218 | */ | |||
219 | pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ? | |||
220 | pp_display_cfg->min_engine_clock_khz : 0; | |||
221 | ||||
222 | pp_display_cfg->min_engine_clock_deep_sleep_khz | |||
223 | = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; | |||
224 | ||||
225 | pp_display_cfg->avail_mclk_switch_time_us = | |||
226 | dce110_get_min_vblank_time_us(context); | |||
227 | /* TODO: dce11.2*/ | |||
228 | pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; | |||
229 | ||||
230 | pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; | |||
231 | ||||
232 | dce110_fill_display_configs(context, pp_display_cfg); | |||
233 | ||||
234 | /* TODO: is this still applicable?*/ | |||
235 | if (pp_display_cfg->display_count == 1) { | |||
236 | const struct dc_crtc_timing *timing = | |||
237 | &context->streams[0]->timing; | |||
238 | ||||
239 | pp_display_cfg->crtc_index = | |||
240 | pp_display_cfg->disp_configs[0].pipe_idx; | |||
241 | pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; | |||
242 | } | |||
243 | ||||
244 | if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg))__builtin_memcmp((&dc->current_state->pp_display_cfg ), (pp_display_cfg), (sizeof(*pp_display_cfg))) != 0) | |||
245 | dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); | |||
246 | } | |||
247 | ||||
248 | static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, | |||
249 | struct dc_state *context, | |||
250 | bool_Bool safe_to_lower) | |||
251 | { | |||
252 | struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base)({ const __typeof( ((struct clk_mgr_internal *)0)->base ) * __mptr = (clk_mgr_base); (struct clk_mgr_internal *)( (char * )__mptr - __builtin_offsetof(struct clk_mgr_internal, base) ) ;}); | |||
253 | struct dm_pp_power_level_change_request level_change_req; | |||
254 | int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; | |||
255 | ||||
256 | /*TODO: W/A for dal3 linux, investigate why this works */ | |||
257 | if (!clk_mgr_dce->dfs_bypass_active) | |||
| ||||
258 | patched_disp_clk = patched_disp_clk * 115 / 100; | |||
259 | ||||
260 | level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); | |||
261 | /* get max clock state from PPLIB */ | |||
262 | if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) | |||
263 | || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { | |||
264 | if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) | |||
265 | clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; | |||
266 | } | |||
267 | ||||
268 | if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { | |||
269 | context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); | |||
270 | clk_mgr_base->clks.dispclk_khz = patched_disp_clk; | |||
271 | } | |||
272 | dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); | |||
273 | } | |||
274 | ||||
275 | static struct clk_mgr_funcs dce110_funcs = { | |||
276 | .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, | |||
277 | .update_clocks = dce11_update_clocks | |||
278 | }; | |||
279 | ||||
280 | void dce110_clk_mgr_construct( | |||
281 | struct dc_context *ctx, | |||
282 | struct clk_mgr_internal *clk_mgr) | |||
283 | { | |||
284 | dce_clk_mgr_construct(ctx, clk_mgr); | |||
285 | ||||
286 | memcpy(clk_mgr->max_clks_by_state,__builtin_memcpy((clk_mgr->max_clks_by_state), (dce110_max_clks_by_state ), (sizeof(dce110_max_clks_by_state))) | |||
287 | dce110_max_clks_by_state,__builtin_memcpy((clk_mgr->max_clks_by_state), (dce110_max_clks_by_state ), (sizeof(dce110_max_clks_by_state))) | |||
288 | sizeof(dce110_max_clks_by_state))__builtin_memcpy((clk_mgr->max_clks_by_state), (dce110_max_clks_by_state ), (sizeof(dce110_max_clks_by_state))); | |||
289 | ||||
290 | clk_mgr->regs = &disp_clk_regs; | |||
291 | clk_mgr->clk_mgr_shift = &disp_clk_shift; | |||
292 | clk_mgr->clk_mgr_mask = &disp_clk_mask; | |||
293 | clk_mgr->base.funcs = &dce110_funcs; | |||
294 | ||||
295 | } |