Bug Summary

File:dev/pci/drm/radeon/radeon_display.c
Warning:line 1107, column 2
Value stored to 'mod' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name radeon_display.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/radeon/radeon_display.c
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <linux/pci.h>
28#include <linux/pm_runtime.h>
29#include <linux/gcd.h>
30
31#include <asm/div64.h>
32
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_device.h>
35#include <drm/drm_drv.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_fb_helper.h>
38#include <drm/drm_fourcc.h>
39#include <drm/drm_gem_framebuffer_helper.h>
40#include <drm/drm_plane_helper.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43#include <drm/radeon_drm.h>
44
45#include "atom.h"
46#include "radeon.h"
47
48u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
49int radeon_enable_vblank_kms(struct drm_crtc *crtc);
50void radeon_disable_vblank_kms(struct drm_crtc *crtc);
51
52static void avivo_crtc_load_lut(struct drm_crtc *crtc)
53{
54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
55 struct drm_device *dev = crtc->dev;
56 struct radeon_device *rdev = dev->dev_private;
57 u16 *r, *g, *b;
58 int i;
59
60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id)__drm_dbg(DRM_UT_KMS, "%d\n", radeon_crtc->crtc_id);
61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x64c0 + radeon_crtc->crtc_offset), (0
), 0)
;
62
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x64c4 + radeon_crtc->crtc_offset), (0
), 0)
;
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x64c8 + radeon_crtc->crtc_offset), (0
), 0)
;
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x64cc + radeon_crtc->crtc_offset), (0
), 0)
;
66
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x64d0 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x64d4 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x64d8 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
70
71 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id)r100_mm_wreg(rdev, (0x6480), (radeon_crtc->crtc_id), 0);
72 WREG32(AVIVO_DC_LUT_RW_MODE, 0)r100_mm_wreg(rdev, (0x6484), (0), 0);
73 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f)r100_mm_wreg(rdev, (0x649c), (0x0000003f), 0);
74
75 WREG8(AVIVO_DC_LUT_RW_INDEX, 0)iowrite8(0, (rdev->rmmio) + (0x6488));
76 r = crtc->gamma_store;
77 g = r + crtc->gamma_size;
78 b = g + crtc->gamma_size;
79 for (i = 0; i < 256; i++) {
80 WREG32(AVIVO_DC_LUT_30_COLOR,r100_mm_wreg(rdev, (0x6494), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
81 ((*r++ & 0xffc0) << 14) |r100_mm_wreg(rdev, (0x6494), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
82 ((*g++ & 0xffc0) << 4) |r100_mm_wreg(rdev, (0x6494), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
83 (*b++ >> 6))r100_mm_wreg(rdev, (0x6494), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
;
84 }
85
86 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
87 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x6108 + radeon_crtc
->crtc_offset), 0); tmp_ &= (~1); tmp_ |= ((radeon_crtc
->crtc_id) & ~(~1)); r100_mm_wreg(rdev, (0x6108 + radeon_crtc
->crtc_offset), (tmp_), 0); } while (0)
;
88}
89
90static void dce4_crtc_load_lut(struct drm_crtc *crtc)
91{
92 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
93 struct drm_device *dev = crtc->dev;
94 struct radeon_device *rdev = dev->dev_private;
95 u16 *r, *g, *b;
96 int i;
97
98 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id)__drm_dbg(DRM_UT_KMS, "%d\n", radeon_crtc->crtc_id);
99 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a00 + radeon_crtc->crtc_offset), (0
), 0)
;
100
101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a04 + radeon_crtc->crtc_offset), (0
), 0)
;
102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a08 + radeon_crtc->crtc_offset), (0
), 0)
;
103 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a0c + radeon_crtc->crtc_offset), (0
), 0)
;
104
105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a10 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
106 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a14 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
107 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a18 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
108
109 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x69e0 + radeon_crtc->crtc_offset), (0
), 0)
;
110 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007)r100_mm_wreg(rdev, (0x69f8 + radeon_crtc->crtc_offset), (0x00000007
), 0)
;
111
112 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x69e4 + radeon_crtc->crtc_offset), (0
), 0)
;
113 r = crtc->gamma_store;
114 g = r + crtc->gamma_size;
115 b = g + crtc->gamma_size;
116 for (i = 0; i < 256; i++) {
117 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
118 ((*r++ & 0xffc0) << 14) |r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
119 ((*g++ & 0xffc0) << 4) |r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
120 (*b++ >> 6))r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
;
121 }
122}
123
124static void dce5_crtc_load_lut(struct drm_crtc *crtc)
125{
126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129 u16 *r, *g, *b;
130 int i;
131
132 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id)__drm_dbg(DRM_UT_KMS, "%d\n", radeon_crtc->crtc_id);
133
134 drm_msleep(10)mdelay(10);
135
136 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x68d4 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
137 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |r100_mm_wreg(rdev, (0x68d4 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
138 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)))r100_mm_wreg(rdev, (0x68d4 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
;
139 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x68b4 + radeon_crtc->crtc_offset), ((
1 << 4)), 0)
140 NI_GRPH_PRESCALE_BYPASS)r100_mm_wreg(rdev, (0x68b4 + radeon_crtc->crtc_offset), ((
1 << 4)), 0)
;
141 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x68c4 + radeon_crtc->crtc_offset), ((
1 << 4)), 0)
142 NI_OVL_PRESCALE_BYPASS)r100_mm_wreg(rdev, (0x68c4 + radeon_crtc->crtc_offset), ((
1 << 4)), 0)
;
143 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6840 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
144 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |r100_mm_wreg(rdev, (0x6840 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
145 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)))r100_mm_wreg(rdev, (0x6840 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
;
146
147 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a00 + radeon_crtc->crtc_offset), (0
), 0)
;
148
149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a04 + radeon_crtc->crtc_offset), (0
), 0)
;
150 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a08 + radeon_crtc->crtc_offset), (0
), 0)
;
151 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6a0c + radeon_crtc->crtc_offset), (0
), 0)
;
152
153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a10 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
154 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a14 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
155 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff)r100_mm_wreg(rdev, (0x6a18 + radeon_crtc->crtc_offset), (0xffff
), 0)
;
156
157 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x69e0 + radeon_crtc->crtc_offset), (0
), 0)
;
158 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007)r100_mm_wreg(rdev, (0x69f8 + radeon_crtc->crtc_offset), (0x00000007
), 0)
;
159
160 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x69e4 + radeon_crtc->crtc_offset), (0
), 0)
;
161 r = crtc->gamma_store;
162 g = r + crtc->gamma_size;
163 b = g + crtc->gamma_size;
164 for (i = 0; i < 256; i++) {
165 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
166 ((*r++ & 0xffc0) << 14) |r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
167 ((*g++ & 0xffc0) << 4) |r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
168 (*b++ >> 6))r100_mm_wreg(rdev, (0x69f0 + radeon_crtc->crtc_offset), ((
(*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
;
169 }
170
171 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6960 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4) |
(((0) & 0x3) << 8) | (((0) & 0x3) << 12)
)), 0)
172 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |r100_mm_wreg(rdev, (0x6960 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4) |
(((0) & 0x3) << 8) | (((0) & 0x3) << 12)
)), 0)
173 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |r100_mm_wreg(rdev, (0x6960 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4) |
(((0) & 0x3) << 8) | (((0) & 0x3) << 12)
)), 0)
174 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |r100_mm_wreg(rdev, (0x6960 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4) |
(((0) & 0x3) << 8) | (((0) & 0x3) << 12)
)), 0)
175 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)))r100_mm_wreg(rdev, (0x6960 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4) |
(((0) & 0x3) << 8) | (((0) & 0x3) << 12)
)), 0)
;
176 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6964 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
177 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |r100_mm_wreg(rdev, (0x6964 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
178 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)))r100_mm_wreg(rdev, (0x6964 + radeon_crtc->crtc_offset), ((
(((0) & 0x3) << 0) | (((0) & 0x3) << 4)))
, 0)
;
179 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6a80 + radeon_crtc->crtc_offset), ((
(((0) & 0x7) << 0) | (((0) & 0x7) << 4)))
, 0)
180 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |r100_mm_wreg(rdev, (0x6a80 + radeon_crtc->crtc_offset), ((
(((0) & 0x7) << 0) | (((0) & 0x7) << 4)))
, 0)
181 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)))r100_mm_wreg(rdev, (0x6a80 + radeon_crtc->crtc_offset), ((
(((0) & 0x7) << 0) | (((0) & 0x7) << 4)))
, 0)
;
182 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x68f0 + radeon_crtc->crtc_offset), ((
(((radeon_crtc->output_csc) & 0x7) << 0) | (((0)
& 0x7) << 4))), 0)
183 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |r100_mm_wreg(rdev, (0x68f0 + radeon_crtc->crtc_offset), ((
(((radeon_crtc->output_csc) & 0x7) << 0) | (((0)
& 0x7) << 4))), 0)
184 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)))r100_mm_wreg(rdev, (0x68f0 + radeon_crtc->crtc_offset), ((
(((radeon_crtc->output_csc) & 0x7) << 0) | (((0)
& 0x7) << 4))), 0)
;
185 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
186 WREG32(0x6940 + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6940 + radeon_crtc->crtc_offset), (0
), 0)
;
187 if (ASIC_IS_DCE8(rdev)((rdev->family >= CHIP_BONAIRE))) {
188 /* XXX this only needs to be programmed once per crtc at startup,
189 * not sure where the best place for it is
190 */
191 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6af0 + radeon_crtc->crtc_offset), ((
1 << 1)), 0)
192 CIK_CURSOR_ALPHA_BLND_ENA)r100_mm_wreg(rdev, (0x6af0 + radeon_crtc->crtc_offset), ((
1 << 1)), 0)
;
193 }
194}
195
196static void legacy_crtc_load_lut(struct drm_crtc *crtc)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 u16 *r, *g, *b;
202 int i;
203 uint32_t dac2_cntl;
204
205 dac2_cntl = RREG32(RADEON_DAC_CNTL2)r100_mm_rreg(rdev, (0x007c), 0);
206 if (radeon_crtc->crtc_id == 0)
207 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL(1 << 5);
208 else
209 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL(1 << 5);
210 WREG32(RADEON_DAC_CNTL2, dac2_cntl)r100_mm_wreg(rdev, (0x007c), (dac2_cntl), 0);
211
212 WREG8(RADEON_PALETTE_INDEX, 0)iowrite8(0, (rdev->rmmio) + (0x00b0));
213 r = crtc->gamma_store;
214 g = r + crtc->gamma_size;
215 b = g + crtc->gamma_size;
216 for (i = 0; i < 256; i++) {
217 WREG32(RADEON_PALETTE_30_DATA,r100_mm_wreg(rdev, (0x00b8), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
218 ((*r++ & 0xffc0) << 14) |r100_mm_wreg(rdev, (0x00b8), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
219 ((*g++ & 0xffc0) << 4) |r100_mm_wreg(rdev, (0x00b8), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
220 (*b++ >> 6))r100_mm_wreg(rdev, (0x00b8), (((*r++ & 0xffc0) << 14
) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0)
;
221 }
222}
223
224void radeon_crtc_load_lut(struct drm_crtc *crtc)
225{
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228
229 if (!crtc->enabled)
230 return;
231
232 if (ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)))
233 dce5_crtc_load_lut(crtc);
234 else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
235 dce4_crtc_load_lut(crtc);
236 else if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
237 avivo_crtc_load_lut(crtc);
238 else
239 legacy_crtc_load_lut(crtc);
240}
241
242static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
243 u16 *blue, uint32_t size,
244 struct drm_modeset_acquire_ctx *ctx)
245{
246 radeon_crtc_load_lut(crtc);
247
248 return 0;
249}
250
251static void radeon_crtc_destroy(struct drm_crtc *crtc)
252{
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
254
255 drm_crtc_cleanup(crtc);
256 destroy_workqueue(radeon_crtc->flip_queue);
257 kfree(radeon_crtc);
258}
259
260/**
261 * radeon_unpin_work_func - unpin old buffer object
262 *
263 * @__work - kernel work item
264 *
265 * Unpin the old frame buffer object outside of the interrupt handler
266 */
267static void radeon_unpin_work_func(struct work_struct *__work)
268{
269 struct radeon_flip_work *work =
270 container_of(__work, struct radeon_flip_work, unpin_work)({ const __typeof( ((struct radeon_flip_work *)0)->unpin_work
) *__mptr = (__work); (struct radeon_flip_work *)( (char *)__mptr
- __builtin_offsetof(struct radeon_flip_work, unpin_work) );
})
;
271 int r;
272
273 /* unpin of the old buffer */
274 r = radeon_bo_reserve(work->old_rbo, false0);
275 if (likely(r == 0)__builtin_expect(!!(r == 0), 1)) {
276 r = radeon_bo_unpin(work->old_rbo);
277 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
278 DRM_ERROR("failed to unpin buffer after flip\n")__drm_err("failed to unpin buffer after flip\n");
279 }
280 radeon_bo_unreserve(work->old_rbo);
281 } else
282 DRM_ERROR("failed to reserve buffer after flip\n")__drm_err("failed to reserve buffer after flip\n");
283
284 drm_gem_object_put(&work->old_rbo->tbo.base);
285 kfree(work);
286}
287
288void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
289{
290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
291 unsigned long flags;
292 u32 update_pending;
293 int vpos, hpos;
294
295 /* can happen during initialization */
296 if (radeon_crtc == NULL((void *)0))
297 return;
298
299 /* Skip the pageflip completion check below (based on polling) on
300 * asics which reliably support hw pageflip completion irqs. pflip
301 * irqs are a reliable and race-free method of handling pageflip
302 * completion detection. A use_pflipirq module parameter < 2 allows
303 * to override this in case of asics with faulty pflip irqs.
304 * A module parameter of 0 would only use this polling based path,
305 * a parameter of 1 would use pflip irq only as a backup to this
306 * path, as in Linux 3.16.
307 */
308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
309 return;
310
311 spin_lock_irqsave(&rdev->ddev->event_lock, flags)do { flags = 0; mtx_enter(&rdev->ddev->event_lock);
} while (0)
;
312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
314 "RADEON_FLIP_SUBMITTED(%d)\n",__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
315 radeon_crtc->flip_status,__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
316 RADEON_FLIP_SUBMITTED)__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
;
317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags)do { (void)(flags); mtx_leave(&rdev->ddev->event_lock
); } while (0)
;
318 return;
319 }
320
321 update_pending = radeon_page_flip_pending(rdev, crtc_id)(rdev)->asic->pflip.page_flip_pending((rdev), (crtc_id)
)
;
322
323 /* Has the pageflip already completed in crtc, or is it certain
324 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
325 * distance to start of "fudged earlier" vblank in vpos, distance to
326 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
327 * the last few scanlines before start of real vblank, where the vblank
328 * irq can fire, so we have sampled update_pending a bit too early and
329 * know the flip will complete at leading edge of the upcoming real
330 * vblank. On pre-AVIVO hardware, flips also complete inside the real
331 * vblank, not only at leading edge, so if update_pending for hpos >= 0
332 * == inside real vblank, the flip will complete almost immediately.
333 * Note that this method of completion handling is still not 100% race
334 * free, as we could execute before the radeon_flip_work_func managed
335 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
336 * but the flip still gets programmed into hw and completed during
337 * vblank, leading to a delayed emission of the flip completion event.
338 * This applies at least to pre-AVIVO hardware, where flips are always
339 * completing inside vblank, not only at leading edge of vblank.
340 */
341 if (update_pending &&
342 (DRM_SCANOUTPOS_VALID(1 << 0) &
343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
344 GET_DISTANCE_TO_VBLANKSTART(1 << 31),
345 &vpos, &hpos, NULL((void *)0), NULL((void *)0),
346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
347 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))))) {
348 /* crtc didn't flip in this target vblank interval,
349 * but flip is pending in crtc. Based on the current
350 * scanout position we know that the current frame is
351 * (nearly) complete and the flip will (likely)
352 * complete before the start of the next frame.
353 */
354 update_pending = 0;
355 }
356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags)do { (void)(flags); mtx_leave(&rdev->ddev->event_lock
); } while (0)
;
357 if (!update_pending)
358 radeon_crtc_handle_flip(rdev, crtc_id);
359}
360
361/**
362 * radeon_crtc_handle_flip - page flip completed
363 *
364 * @rdev: radeon device pointer
365 * @crtc_id: crtc number this event is for
366 *
367 * Called when we are sure that a page flip for this crtc is completed.
368 */
369void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
370{
371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
372 struct radeon_flip_work *work;
373 unsigned long flags;
374
375 /* this can happen at init */
376 if (radeon_crtc == NULL((void *)0))
377 return;
378
379 spin_lock_irqsave(&rdev->ddev->event_lock, flags)do { flags = 0; mtx_enter(&rdev->ddev->event_lock);
} while (0)
;
380 work = radeon_crtc->flip_work;
381 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
382 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
383 "RADEON_FLIP_SUBMITTED(%d)\n",__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
384 radeon_crtc->flip_status,__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
385 RADEON_FLIP_SUBMITTED)__drm_dbg(DRM_UT_DRIVER, "radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED
)
;
386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags)do { (void)(flags); mtx_leave(&rdev->ddev->event_lock
); } while (0)
;
387 return;
388 }
389
390 /* Pageflip completed. Clean up. */
391 radeon_crtc->flip_status = RADEON_FLIP_NONE;
392 radeon_crtc->flip_work = NULL((void *)0);
393
394 /* wakeup userspace */
395 if (work->event)
396 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
397
398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags)do { (void)(flags); mtx_leave(&rdev->ddev->event_lock
); } while (0)
;
399
400 drm_crtc_vblank_put(&radeon_crtc->base);
401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
402 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
403}
404
405/**
406 * radeon_flip_work_func - page flip framebuffer
407 *
408 * @work - kernel work item
409 *
410 * Wait for the buffer object to become idle and do the actual page flip
411 */
412static void radeon_flip_work_func(struct work_struct *__work)
413{
414 struct radeon_flip_work *work =
415 container_of(__work, struct radeon_flip_work, flip_work)({ const __typeof( ((struct radeon_flip_work *)0)->flip_work
) *__mptr = (__work); (struct radeon_flip_work *)( (char *)__mptr
- __builtin_offsetof(struct radeon_flip_work, flip_work) );}
)
;
416 struct radeon_device *rdev = work->rdev;
417 struct drm_device *dev = rdev->ddev;
418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
419
420 struct drm_crtc *crtc = &radeon_crtc->base;
421 unsigned long flags;
422 int r;
423 int vpos, hpos;
424
425 down_read(&rdev->exclusive_lock)rw_enter_read(&rdev->exclusive_lock);
426 if (work->fence) {
427 struct radeon_fence *fence;
428
429 fence = to_radeon_fence(work->fence);
430 if (fence && fence->rdev == rdev) {
431 r = radeon_fence_wait(fence, false0);
432 if (r == -EDEADLK11) {
433 up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock);
434 do {
435 r = radeon_gpu_reset(rdev);
436 } while (r == -EAGAIN35);
437 down_read(&rdev->exclusive_lock)rw_enter_read(&rdev->exclusive_lock);
438 }
439 } else
440 r = dma_fence_wait(work->fence, false0);
441
442 if (r)
443 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r)__drm_err("failed to wait on page flip fence (%d)!\n", r);
444
445 /* We continue with the page flip even if we failed to wait on
446 * the fence, otherwise the DRM core and userspace will be
447 * confused about which BO the CRTC is scanning out
448 */
449
450 dma_fence_put(work->fence);
451 work->fence = NULL((void *)0);
452 }
453
454 /* Wait until we're out of the vertical blank period before the one
455 * targeted by the flip. Always wait on pre DCE4 to avoid races with
456 * flip completion handling from vblank irq, as these old asics don't
457 * have reliable pageflip completion interrupts.
458 */
459 while (radeon_crtc->enabled &&
460 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
461 &vpos, &hpos, NULL((void *)0), NULL((void *)0),
462 &crtc->hwmode)
463 & (DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1))) ==
464 (DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1)) &&
465 (!ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) ||
466 ((int) (work->target_vblank -
467 crtc->funcs->get_vblank_counter(crtc)) > 0)))
468 usleep_range(1000, 2000);
469
470 /* We borrow the event spin lock for protecting flip_status */
471 spin_lock_irqsave(&crtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&crtc->dev->event_lock); }
while (0)
;
472
473 /* set the proper interrupt */
474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
475
476 /* do the flip (mmio) */
477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async)(rdev)->asic->pflip.page_flip((rdev), (radeon_crtc->
crtc_id), (work->base), (work->async))
;
478
479 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&crtc->dev->event_lock
); } while (0)
;
481 up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock);
482}
483
484static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
485 struct drm_framebuffer *fb,
486 struct drm_pending_vblank_event *event,
487 uint32_t page_flip_flags,
488 uint32_t target,
489 struct drm_modeset_acquire_ctx *ctx)
490{
491 struct drm_device *dev = crtc->dev;
492 struct radeon_device *rdev = dev->dev_private;
493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
494 struct drm_gem_object *obj;
495 struct radeon_flip_work *work;
496 struct radeon_bo *new_rbo;
497 uint32_t tiling_flags, pitch_pixels;
498 uint64_t base;
499 unsigned long flags;
500 int r;
501
502 work = kzalloc(sizeof *work, GFP_KERNEL(0x0001 | 0x0004));
503 if (work == NULL((void *)0))
504 return -ENOMEM12;
505
506 INIT_WORK(&work->flip_work, radeon_flip_work_func);
507 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
508
509 work->rdev = rdev;
510 work->crtc_id = radeon_crtc->crtc_id;
511 work->event = event;
512 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC0x02) != 0;
513
514 /* schedule unpin of the old buffer */
515 obj = crtc->primary->fb->obj[0];
516
517 /* take a reference to the old object */
518 drm_gem_object_get(obj);
519 work->old_rbo = gem_to_radeon_bo(obj)({ const __typeof( ((struct radeon_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct radeon_bo *)( (char *)__mptr - __builtin_offsetof
(struct radeon_bo, tbo.base) );})
;
520
521 obj = fb->obj[0];
522 new_rbo = gem_to_radeon_bo(obj)({ const __typeof( ((struct radeon_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct radeon_bo *)( (char *)__mptr - __builtin_offsetof
(struct radeon_bo, tbo.base) );})
;
523
524 /* pin the new buffer */
525 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",__drm_dbg(DRM_UT_DRIVER, "flip-ioctl() cur_rbo = %p, new_rbo = %p\n"
, work->old_rbo, new_rbo)
526 work->old_rbo, new_rbo)__drm_dbg(DRM_UT_DRIVER, "flip-ioctl() cur_rbo = %p, new_rbo = %p\n"
, work->old_rbo, new_rbo)
;
527
528 r = radeon_bo_reserve(new_rbo, false0);
529 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
530 DRM_ERROR("failed to reserve new rbo buffer before flip\n")__drm_err("failed to reserve new rbo buffer before flip\n");
531 goto cleanup;
532 }
533 /* Only 27 bit offset for legacy CRTC */
534 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM0x4,
535 ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) ? 0 : 1 << 27, &base);
536 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
537 radeon_bo_unreserve(new_rbo);
538 r = -EINVAL22;
539 DRM_ERROR("failed to pin new rbo buffer before flip\n")__drm_err("failed to pin new rbo buffer before flip\n");
540 goto cleanup;
541 }
542 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv));
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL((void *)0));
544 radeon_bo_unreserve(new_rbo);
545
546 if (!ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) {
547 /* crtc offset is from display base addr not FB location */
548 base -= radeon_crtc->legacy_display_base_addr;
549 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
550
551 if (tiling_flags & RADEON_TILING_MACRO0x1) {
552 if (ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480))
) {
553 base &= ~0x7ff;
554 } else {
555 int byteshift = fb->format->cpp[0] * 8 >> 4;
556 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
557 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
558 }
559 } else {
560 int offset = crtc->y * pitch_pixels + crtc->x;
561 switch (fb->format->cpp[0] * 8) {
562 case 8:
563 default:
564 offset *= 1;
565 break;
566 case 15:
567 case 16:
568 offset *= 2;
569 break;
570 case 24:
571 offset *= 3;
572 break;
573 case 32:
574 offset *= 4;
575 break;
576 }
577 base += offset;
578 }
579 base &= ~7;
580 }
581 work->base = base;
582 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
583 crtc->funcs->get_vblank_counter(crtc);
584
585 /* We borrow the event spin lock for protecting flip_work */
586 spin_lock_irqsave(&crtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&crtc->dev->event_lock); }
while (0)
;
587
588 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
589 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n")__drm_dbg(DRM_UT_DRIVER, "flip queue: crtc already busy\n");
590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&crtc->dev->event_lock
); } while (0)
;
591 r = -EBUSY16;
592 goto pflip_cleanup;
593 }
594 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
595 radeon_crtc->flip_work = work;
596
597 /* update crtc fb */
598 crtc->primary->fb = fb;
599
600 spin_unlock_irqrestore(&crtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&crtc->dev->event_lock
); } while (0)
;
601
602 queue_work(radeon_crtc->flip_queue, &work->flip_work);
603 return 0;
604
605pflip_cleanup:
606 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)__builtin_expect(!!(radeon_bo_reserve(new_rbo, 0) != 0), 0)) {
607 DRM_ERROR("failed to reserve new rbo in error path\n")__drm_err("failed to reserve new rbo in error path\n");
608 goto cleanup;
609 }
610 if (unlikely(radeon_bo_unpin(new_rbo) != 0)__builtin_expect(!!(radeon_bo_unpin(new_rbo) != 0), 0)) {
611 DRM_ERROR("failed to unpin new rbo in error path\n")__drm_err("failed to unpin new rbo in error path\n");
612 }
613 radeon_bo_unreserve(new_rbo);
614
615cleanup:
616 drm_gem_object_put(&work->old_rbo->tbo.base);
617 dma_fence_put(work->fence);
618 kfree(work);
619 return r;
620}
621
622static int
623radeon_crtc_set_config(struct drm_mode_set *set,
624 struct drm_modeset_acquire_ctx *ctx)
625{
626 struct drm_device *dev;
627 struct radeon_device *rdev;
628 struct drm_crtc *crtc;
629 bool_Bool active = false0;
630 int ret;
631
632 if (!set || !set->crtc)
633 return -EINVAL22;
634
635 dev = set->crtc->dev;
636
637 ret = pm_runtime_get_sync(dev->dev);
638 if (ret < 0) {
639 pm_runtime_put_autosuspend(dev->dev);
640 return ret;
641 }
642
643 ret = drm_crtc_helper_set_config(set, ctx);
644
645 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
) *__mptr = ((&dev->mode_config.crtc_list)->next);
(__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&dev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
);}))
646 if (crtc->enabled)
647 active = true1;
648
649 pm_runtime_mark_last_busy(dev->dev);
650
651 rdev = dev->dev_private;
652 /* if we have active crtcs and we don't have a power ref,
653 take the current one */
654 if (active && !rdev->have_disp_power_ref) {
655 rdev->have_disp_power_ref = true1;
656 return ret;
657 }
658 /* if we have no active crtcs, then drop the power ref
659 we got before */
660 if (!active && rdev->have_disp_power_ref) {
661 pm_runtime_put_autosuspend(dev->dev);
662 rdev->have_disp_power_ref = false0;
663 }
664
665 /* drop the power reference we got coming in here */
666 pm_runtime_put_autosuspend(dev->dev);
667 return ret;
668}
669
670static const struct drm_crtc_funcs radeon_crtc_funcs = {
671 .cursor_set2 = radeon_crtc_cursor_set2,
672 .cursor_move = radeon_crtc_cursor_move,
673 .gamma_set = radeon_crtc_gamma_set,
674 .set_config = radeon_crtc_set_config,
675 .destroy = radeon_crtc_destroy,
676 .page_flip_target = radeon_crtc_page_flip_target,
677 .get_vblank_counter = radeon_get_vblank_counter_kms,
678 .enable_vblank = radeon_enable_vblank_kms,
679 .disable_vblank = radeon_disable_vblank_kms,
680 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
681};
682
683static void radeon_crtc_init(struct drm_device *dev, int index)
684{
685 struct radeon_device *rdev = dev->dev_private;
686 struct radeon_crtc *radeon_crtc;
687
688 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT4 * sizeof(struct drm_connector *)), GFP_KERNEL(0x0001 | 0x0004));
689 if (radeon_crtc == NULL((void *)0))
690 return;
691
692 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
693
694 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
695 radeon_crtc->crtc_id = index;
696 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI1, 0);
697 rdev->mode_info.crtcs[index] = radeon_crtc;
698
699 if (rdev->family >= CHIP_BONAIRE) {
700 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH128;
701 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT128;
702 } else {
703 radeon_crtc->max_cursor_width = CURSOR_WIDTH64;
704 radeon_crtc->max_cursor_height = CURSOR_HEIGHT64;
705 }
706 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
707 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
708
709#if 0
710 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
711 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
712 radeon_crtc->mode_set.num_connectors = 0;
713#endif
714
715 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) || radeon_r4xx_atom))
716 radeon_atombios_init_crtc(dev, radeon_crtc);
717 else
718 radeon_legacy_init_crtc(dev, radeon_crtc);
719}
720
721static const char *encoder_names[38] = {
722 "NONE",
723 "INTERNAL_LVDS",
724 "INTERNAL_TMDS1",
725 "INTERNAL_TMDS2",
726 "INTERNAL_DAC1",
727 "INTERNAL_DAC2",
728 "INTERNAL_SDVOA",
729 "INTERNAL_SDVOB",
730 "SI170B",
731 "CH7303",
732 "CH7301",
733 "INTERNAL_DVO1",
734 "EXTERNAL_SDVOA",
735 "EXTERNAL_SDVOB",
736 "TITFP513",
737 "INTERNAL_LVTM1",
738 "VT1623",
739 "HDMI_SI1930",
740 "HDMI_INTERNAL",
741 "INTERNAL_KLDSCP_TMDS1",
742 "INTERNAL_KLDSCP_DVO1",
743 "INTERNAL_KLDSCP_DAC1",
744 "INTERNAL_KLDSCP_DAC2",
745 "SI178",
746 "MVPU_FPGA",
747 "INTERNAL_DDI",
748 "VT1625",
749 "HDMI_SI1932",
750 "DP_AN9801",
751 "DP_DP501",
752 "INTERNAL_UNIPHY",
753 "INTERNAL_KLDSCP_LVTMA",
754 "INTERNAL_UNIPHY1",
755 "INTERNAL_UNIPHY2",
756 "NUTMEG",
757 "TRAVIS",
758 "INTERNAL_VCE",
759 "INTERNAL_UNIPHY3",
760};
761
762static const char *hpd_names[6] = {
763 "HPD1",
764 "HPD2",
765 "HPD3",
766 "HPD4",
767 "HPD5",
768 "HPD6",
769};
770
771static void radeon_print_display_setup(struct drm_device *dev)
772{
773 struct drm_connector *connector;
774 struct radeon_connector *radeon_connector;
775 struct drm_encoder *encoder;
776 struct radeon_encoder *radeon_encoder;
777 uint32_t devices;
778 int i = 0;
779
780 DRM_INFO("Radeon Display Connectors\n")printk("\0016" "[" "drm" "] " "Radeon Display Connectors\n");
781 list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
(&dev->mode_config.connector_list); connector = ({ const
__typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*connector), head) );}))
{
782 radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );})
;
783 DRM_INFO("Connector %d:\n", i)printk("\0016" "[" "drm" "] " "Connector %d:\n", i);
784 DRM_INFO(" %s\n", connector->name)printk("\0016" "[" "drm" "] " " %s\n", connector->name);
785 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
786 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd])printk("\0016" "[" "drm" "] " " %s\n", hpd_names[radeon_connector
->hpd.hpd])
;
787 if (radeon_connector->ddc_bus) {
788 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
789 radeon_connector->ddc_bus->rec.mask_clk_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
790 radeon_connector->ddc_bus->rec.mask_data_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
791 radeon_connector->ddc_bus->rec.a_clk_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
792 radeon_connector->ddc_bus->rec.a_data_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
793 radeon_connector->ddc_bus->rec.en_clk_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
794 radeon_connector->ddc_bus->rec.en_data_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
795 radeon_connector->ddc_bus->rec.y_clk_reg,printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
796 radeon_connector->ddc_bus->rec.y_data_reg)printk("\0016" "[" "drm" "] " " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n"
, radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector
->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus
->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_data_reg
, radeon_connector->ddc_bus->rec.en_clk_reg, radeon_connector
->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus
->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg
)
;
797 if (radeon_connector->router.ddc_valid)
798 DRM_INFO(" DDC Router 0x%x/0x%x\n",printk("\0016" "[" "drm" "] " " DDC Router 0x%x/0x%x\n", radeon_connector
->router.ddc_mux_control_pin, radeon_connector->router.
ddc_mux_state)
799 radeon_connector->router.ddc_mux_control_pin,printk("\0016" "[" "drm" "] " " DDC Router 0x%x/0x%x\n", radeon_connector
->router.ddc_mux_control_pin, radeon_connector->router.
ddc_mux_state)
800 radeon_connector->router.ddc_mux_state)printk("\0016" "[" "drm" "] " " DDC Router 0x%x/0x%x\n", radeon_connector
->router.ddc_mux_control_pin, radeon_connector->router.
ddc_mux_state)
;
801 if (radeon_connector->router.cd_valid)
802 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",printk("\0016" "[" "drm" "] " " Clock/Data Router 0x%x/0x%x\n"
, radeon_connector->router.cd_mux_control_pin, radeon_connector
->router.cd_mux_state)
803 radeon_connector->router.cd_mux_control_pin,printk("\0016" "[" "drm" "] " " Clock/Data Router 0x%x/0x%x\n"
, radeon_connector->router.cd_mux_control_pin, radeon_connector
->router.cd_mux_state)
804 radeon_connector->router.cd_mux_state)printk("\0016" "[" "drm" "] " " Clock/Data Router 0x%x/0x%x\n"
, radeon_connector->router.cd_mux_control_pin, radeon_connector
->router.cd_mux_state)
;
805 } else {
806 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA1 ||
807 connector->connector_type == DRM_MODE_CONNECTOR_DVII2 ||
808 connector->connector_type == DRM_MODE_CONNECTOR_DVID3 ||
809 connector->connector_type == DRM_MODE_CONNECTOR_DVIA4 ||
810 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA11 ||
811 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB12)
812 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n")printk("\0016" "[" "drm" "] " " DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"
)
;
813 }
814 DRM_INFO(" Encoders:\n")printk("\0016" "[" "drm" "] " " Encoders:\n");
815 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}))
{
816 radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
817 devices = radeon_encoder->devices & radeon_connector->devices;
818 if (devices) {
819 if (devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ))
820 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " CRT1: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
821 if (devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ))
822 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " CRT2: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
823 if (devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ))
824 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " LCD1: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
825 if (devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ))
826 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP1: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
827 if (devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ))
828 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP2: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
829 if (devices & ATOM_DEVICE_DFP3_SUPPORT(0x1L << 0x00000009 ))
830 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP3: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
831 if (devices & ATOM_DEVICE_DFP4_SUPPORT(0x1L << 0x0000000A ))
832 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP4: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
833 if (devices & ATOM_DEVICE_DFP5_SUPPORT(0x1L << 0x0000000B ))
834 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP5: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
835 if (devices & ATOM_DEVICE_DFP6_SUPPORT(0x1L << 0x00000006 ))
836 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " DFP6: %s\n", encoder_names
[radeon_encoder->encoder_id])
;
837 if (devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ))
838 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " TV1: %s\n", encoder_names[
radeon_encoder->encoder_id])
;
839 if (devices & ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 ))
840 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id])printk("\0016" "[" "drm" "] " " CV: %s\n", encoder_names[radeon_encoder
->encoder_id])
;
841 }
842 }
843 i++;
844 }
845}
846
847static bool_Bool radeon_setup_enc_conn(struct drm_device *dev)
848{
849 struct radeon_device *rdev = dev->dev_private;
850 bool_Bool ret = false0;
851
852 if (rdev->bios) {
853 if (rdev->is_atom_bios) {
854 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
855 if (!ret)
856 ret = radeon_get_atom_connector_info_from_object_table(dev);
857 } else {
858 ret = radeon_get_legacy_connector_info_from_bios(dev);
859 if (!ret)
860 ret = radeon_get_legacy_connector_info_from_table(dev);
861 }
862 } else {
863 if (!ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
864 ret = radeon_get_legacy_connector_info_from_table(dev);
865 }
866 if (ret) {
867 radeon_setup_encoder_clones(dev);
868 radeon_print_display_setup(dev);
869 }
870
871 return ret;
872}
873
874/* avivo */
875
876/**
877 * avivo_reduce_ratio - fractional number reduction
878 *
879 * @nom: nominator
880 * @den: denominator
881 * @nom_min: minimum value for nominator
882 * @den_min: minimum value for denominator
883 *
884 * Find the greatest common divisor and apply it on both nominator and
885 * denominator, but make nominator and denominator are at least as large
886 * as their minimum values.
887 */
888static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
889 unsigned nom_min, unsigned den_min)
890{
891 unsigned tmp;
892
893 /* reduce the numbers to a simpler ratio */
894 tmp = gcd(*nom, *den);
895 *nom /= tmp;
896 *den /= tmp;
897
898 /* make sure nominator is large enough */
899 if (*nom < nom_min) {
900 tmp = DIV_ROUND_UP(nom_min, *nom)(((nom_min) + ((*nom) - 1)) / (*nom));
901 *nom *= tmp;
902 *den *= tmp;
903 }
904
905 /* make sure the denominator is large enough */
906 if (*den < den_min) {
907 tmp = DIV_ROUND_UP(den_min, *den)(((den_min) + ((*den) - 1)) / (*den));
908 *nom *= tmp;
909 *den *= tmp;
910 }
911}
912
913/**
914 * avivo_get_fb_ref_div - feedback and ref divider calculation
915 *
916 * @nom: nominator
917 * @den: denominator
918 * @post_div: post divider
919 * @fb_div_max: feedback divider maximum
920 * @ref_div_max: reference divider maximum
921 * @fb_div: resulting feedback divider
922 * @ref_div: resulting reference divider
923 *
924 * Calculate feedback and reference divider for a given post divider. Makes
925 * sure we stay within the limits.
926 */
927static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
928 unsigned fb_div_max, unsigned ref_div_max,
929 unsigned *fb_div, unsigned *ref_div)
930{
931 /* limit reference * post divider to a maximum */
932 ref_div_max = max(min(100 / post_div, ref_div_max), 1u)((((((100 / post_div)<(ref_div_max))?(100 / post_div):(ref_div_max
)))>(1u))?((((100 / post_div)<(ref_div_max))?(100 / post_div
):(ref_div_max))):(1u))
;
933
934 /* get matching reference and feedback divider */
935 *ref_div = min(max(den/post_div, 1u), ref_div_max)((((((den/post_div)>(1u))?(den/post_div):(1u)))<(ref_div_max
))?((((den/post_div)>(1u))?(den/post_div):(1u))):(ref_div_max
))
;
936 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den)(((nom * *ref_div * post_div) + ((den) / 2)) / (den));
937
938 /* limit fb divider to its maximum */
939 if (*fb_div > fb_div_max) {
940 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
941 *fb_div = fb_div_max;
942 }
943}
944
945/**
946 * radeon_compute_pll_avivo - compute PLL paramaters
947 *
948 * @pll: information about the PLL
949 * @dot_clock_p: resulting pixel clock
950 * fb_div_p: resulting feedback divider
951 * frac_fb_div_p: fractional part of the feedback divider
952 * ref_div_p: resulting reference divider
953 * post_div_p: resulting reference divider
954 *
955 * Try to calculate the PLL parameters to generate the given frequency:
956 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
957 */
958void radeon_compute_pll_avivo(struct radeon_pll *pll,
959 u32 freq,
960 u32 *dot_clock_p,
961 u32 *fb_div_p,
962 u32 *frac_fb_div_p,
963 u32 *ref_div_p,
964 u32 *post_div_p)
965{
966 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10) ?
967 freq : freq / 10;
968
969 unsigned fb_div_min, fb_div_max, fb_div;
970 unsigned post_div_min, post_div_max, post_div;
971 unsigned ref_div_min, ref_div_max, ref_div;
972 unsigned post_div_best, diff_best;
973 unsigned nom, den;
974
975 /* determine allowed feedback divider range */
976 fb_div_min = pll->min_feedback_div;
977 fb_div_max = pll->max_feedback_div;
978
979 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10)) {
980 fb_div_min *= 10;
981 fb_div_max *= 10;
982 }
983
984 /* determine allowed ref divider range */
985 if (pll->flags & RADEON_PLL_USE_REF_DIV(1 << 2))
986 ref_div_min = pll->reference_div;
987 else
988 ref_div_min = pll->min_ref_div;
989
990 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10) &&
991 pll->flags & RADEON_PLL_USE_REF_DIV(1 << 2))
992 ref_div_max = pll->reference_div;
993 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP(1 << 14))
994 /* fix for problems on RS880 */
995 ref_div_max = min(pll->max_ref_div, 7u)(((pll->max_ref_div)<(7u))?(pll->max_ref_div):(7u));
996 else
997 ref_div_max = pll->max_ref_div;
998
999 /* determine allowed post divider range */
1000 if (pll->flags & RADEON_PLL_USE_POST_DIV(1 << 12)) {
1001 post_div_min = pll->post_div;
1002 post_div_max = pll->post_div;
1003 } else {
1004 unsigned vco_min, vco_max;
1005
1006 if (pll->flags & RADEON_PLL_IS_LCD(1 << 13)) {
1007 vco_min = pll->lcd_pll_out_min;
1008 vco_max = pll->lcd_pll_out_max;
1009 } else {
1010 vco_min = pll->pll_out_min;
1011 vco_max = pll->pll_out_max;
1012 }
1013
1014 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10)) {
1015 vco_min *= 10;
1016 vco_max *= 10;
1017 }
1018
1019 post_div_min = vco_min / target_clock;
1020 if ((target_clock * post_div_min) < vco_min)
1021 ++post_div_min;
1022 if (post_div_min < pll->min_post_div)
1023 post_div_min = pll->min_post_div;
1024
1025 post_div_max = vco_max / target_clock;
1026 if ((target_clock * post_div_max) > vco_max)
1027 --post_div_max;
1028 if (post_div_max > pll->max_post_div)
1029 post_div_max = pll->max_post_div;
1030 }
1031
1032 /* represent the searched ratio as fractional number */
1033 nom = target_clock;
1034 den = pll->reference_freq;
1035
1036 /* reduce the numbers to a simpler ratio */
1037 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1038
1039 /* now search for a post divider */
1040 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP(1 << 14))
1041 post_div_best = post_div_min;
1042 else
1043 post_div_best = post_div_max;
1044 diff_best = ~0;
1045
1046 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1047 unsigned diff;
1048 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1049 ref_div_max, &fb_div, &ref_div);
1050 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1051 (ref_div * post_div));
1052
1053 if (diff < diff_best || (diff == diff_best &&
1054 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP(1 << 14)))) {
1055
1056 post_div_best = post_div;
1057 diff_best = diff;
1058 }
1059 }
1060 post_div = post_div_best;
1061
1062 /* get the feedback and reference divider for the optimal value */
1063 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1064 &fb_div, &ref_div);
1065
1066 /* reduce the numbers to a simpler ratio once more */
1067 /* this also makes sure that the reference divider is large enough */
1068 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1069
1070 /* avoid high jitter with small fractional dividers */
1071 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10) && (fb_div % 10)) {
1072 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50)(((fb_div_min)>((9 - (fb_div % 10)) * 20 + 50))?(fb_div_min
):((9 - (fb_div % 10)) * 20 + 50))
;
1073 if (fb_div < fb_div_min) {
1074 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div)(((fb_div_min) + ((fb_div) - 1)) / (fb_div));
1075 fb_div *= tmp;
1076 ref_div *= tmp;
1077 }
1078 }
1079
1080 /* and finally save the result */
1081 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10)) {
1082 *fb_div_p = fb_div / 10;
1083 *frac_fb_div_p = fb_div % 10;
1084 } else {
1085 *fb_div_p = fb_div;
1086 *frac_fb_div_p = 0;
1087 }
1088
1089 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1090 (pll->reference_freq * *frac_fb_div_p)) /
1091 (ref_div * post_div * 10);
1092 *ref_div_p = ref_div;
1093 *post_div_p = post_div;
1094
1095 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",__drm_dbg(DRM_UT_KMS, "%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, ref_div
, post_div)
1096 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,__drm_dbg(DRM_UT_KMS, "%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, ref_div
, post_div)
1097 ref_div, post_div)__drm_dbg(DRM_UT_KMS, "%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, ref_div
, post_div)
;
1098}
1099
1100/* pre-avivo */
1101static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1102{
1103 uint64_t mod;
1104
1105 n += d / 2;
1106
1107 mod = do_div(n, d)({ uint32_t __base = (d); uint32_t __rem = ((uint64_t)(n)) % __base
; (n) = ((uint64_t)(n)) / __base; __rem; })
;
Value stored to 'mod' is never read
1108 return n;
1109}
1110
1111void radeon_compute_pll_legacy(struct radeon_pll *pll,
1112 uint64_t freq,
1113 uint32_t *dot_clock_p,
1114 uint32_t *fb_div_p,
1115 uint32_t *frac_fb_div_p,
1116 uint32_t *ref_div_p,
1117 uint32_t *post_div_p)
1118{
1119 uint32_t min_ref_div = pll->min_ref_div;
1120 uint32_t max_ref_div = pll->max_ref_div;
1121 uint32_t min_post_div = pll->min_post_div;
1122 uint32_t max_post_div = pll->max_post_div;
1123 uint32_t min_fractional_feed_div = 0;
1124 uint32_t max_fractional_feed_div = 0;
1125 uint32_t best_vco = pll->best_vco;
1126 uint32_t best_post_div = 1;
1127 uint32_t best_ref_div = 1;
1128 uint32_t best_feedback_div = 1;
1129 uint32_t best_frac_feedback_div = 0;
1130 uint32_t best_freq = -1;
1131 uint32_t best_error = 0xffffffff;
1132 uint32_t best_vco_diff = 1;
1133 uint32_t post_div;
1134 u32 pll_out_min, pll_out_max;
1135
1136 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div)__drm_dbg(DRM_UT_KMS, "PLL freq %llu %u %u\n", freq, pll->
min_ref_div, pll->max_ref_div)
;
1137 freq = freq * 1000;
1138
1139 if (pll->flags & RADEON_PLL_IS_LCD(1 << 13)) {
1140 pll_out_min = pll->lcd_pll_out_min;
1141 pll_out_max = pll->lcd_pll_out_max;
1142 } else {
1143 pll_out_min = pll->pll_out_min;
1144 pll_out_max = pll->pll_out_max;
1145 }
1146
1147 if (pll_out_min > 64800)
1148 pll_out_min = 64800;
1149
1150 if (pll->flags & RADEON_PLL_USE_REF_DIV(1 << 2))
1151 min_ref_div = max_ref_div = pll->reference_div;
1152 else {
1153 while (min_ref_div < max_ref_div-1) {
1154 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1155 uint32_t pll_in = pll->reference_freq / mid;
1156 if (pll_in < pll->pll_in_min)
1157 max_ref_div = mid;
1158 else if (pll_in > pll->pll_in_max)
1159 min_ref_div = mid;
1160 else
1161 break;
1162 }
1163 }
1164
1165 if (pll->flags & RADEON_PLL_USE_POST_DIV(1 << 12))
1166 min_post_div = max_post_div = pll->post_div;
1167
1168 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV(1 << 10)) {
1169 min_fractional_feed_div = pll->min_frac_feedback_div;
1170 max_fractional_feed_div = pll->max_frac_feedback_div;
1171 }
1172
1173 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1174 uint32_t ref_div;
1175
1176 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV(1 << 1)) && (post_div & 1))
1177 continue;
1178
1179 /* legacy radeons only have a few post_divs */
1180 if (pll->flags & RADEON_PLL_LEGACY(1 << 3)) {
1181 if ((post_div == 5) ||
1182 (post_div == 7) ||
1183 (post_div == 9) ||
1184 (post_div == 10) ||
1185 (post_div == 11) ||
1186 (post_div == 13) ||
1187 (post_div == 14) ||
1188 (post_div == 15))
1189 continue;
1190 }
1191
1192 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1193 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1194 uint32_t pll_in = pll->reference_freq / ref_div;
1195 uint32_t min_feed_div = pll->min_feedback_div;
1196 uint32_t max_feed_div = pll->max_feedback_div + 1;
1197
1198 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1199 continue;
1200
1201 while (min_feed_div < max_feed_div) {
1202 uint32_t vco;
1203 uint32_t min_frac_feed_div = min_fractional_feed_div;
1204 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1205 uint32_t frac_feedback_div;
1206 uint64_t tmp;
1207
1208 feedback_div = (min_feed_div + max_feed_div) / 2;
1209
1210 tmp = (uint64_t)pll->reference_freq * feedback_div;
1211 vco = radeon_div(tmp, ref_div);
1212
1213 if (vco < pll_out_min) {
1214 min_feed_div = feedback_div + 1;
1215 continue;
1216 } else if (vco > pll_out_max) {
1217 max_feed_div = feedback_div;
1218 continue;
1219 }
1220
1221 while (min_frac_feed_div < max_frac_feed_div) {
1222 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1223 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1224 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1225 current_freq = radeon_div(tmp, ref_div * post_div);
1226
1227 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER(1 << 11)) {
1228 if (freq < current_freq)
1229 error = 0xffffffff;
1230 else
1231 error = freq - current_freq;
1232 } else
1233 error = abs(current_freq - freq);
1234 vco_diff = abs(vco - best_vco);
1235
1236 if ((best_vco == 0 && error < best_error) ||
1237 (best_vco != 0 &&
1238 ((best_error > 100 && error < best_error - 100) ||
1239 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1240 best_post_div = post_div;
1241 best_ref_div = ref_div;
1242 best_feedback_div = feedback_div;
1243 best_frac_feedback_div = frac_feedback_div;
1244 best_freq = current_freq;
1245 best_error = error;
1246 best_vco_diff = vco_diff;
1247 } else if (current_freq == freq) {
1248 if (best_freq == -1) {
1249 best_post_div = post_div;
1250 best_ref_div = ref_div;
1251 best_feedback_div = feedback_div;
1252 best_frac_feedback_div = frac_feedback_div;
1253 best_freq = current_freq;
1254 best_error = error;
1255 best_vco_diff = vco_diff;
1256 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV(1 << 4)) && (ref_div < best_ref_div)) ||
1257 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV(1 << 5)) && (ref_div > best_ref_div)) ||
1258 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV(1 << 6)) && (feedback_div < best_feedback_div)) ||
1259 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV(1 << 7)) && (feedback_div > best_feedback_div)) ||
1260 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV(1 << 8)) && (post_div < best_post_div)) ||
1261 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV(1 << 9)) && (post_div > best_post_div))) {
1262 best_post_div = post_div;
1263 best_ref_div = ref_div;
1264 best_feedback_div = feedback_div;
1265 best_frac_feedback_div = frac_feedback_div;
1266 best_freq = current_freq;
1267 best_error = error;
1268 best_vco_diff = vco_diff;
1269 }
1270 }
1271 if (current_freq < freq)
1272 min_frac_feed_div = frac_feedback_div + 1;
1273 else
1274 max_frac_feed_div = frac_feedback_div;
1275 }
1276 if (current_freq < freq)
1277 min_feed_div = feedback_div + 1;
1278 else
1279 max_feed_div = feedback_div;
1280 }
1281 }
1282 }
1283
1284 *dot_clock_p = best_freq / 10000;
1285 *fb_div_p = best_feedback_div;
1286 *frac_fb_div_p = best_frac_feedback_div;
1287 *ref_div_p = best_ref_div;
1288 *post_div_p = best_post_div;
1289 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",__drm_dbg(DRM_UT_KMS, "%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, (long long)freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div
, best_ref_div, best_post_div)
1290 (long long)freq,__drm_dbg(DRM_UT_KMS, "%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, (long long)freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div
, best_ref_div, best_post_div)
1291 best_freq / 1000, best_feedback_div, best_frac_feedback_div,__drm_dbg(DRM_UT_KMS, "%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, (long long)freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div
, best_ref_div, best_post_div)
1292 best_ref_div, best_post_div)__drm_dbg(DRM_UT_KMS, "%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n"
, (long long)freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div
, best_ref_div, best_post_div)
;
1293
1294}
1295
1296static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1297 .destroy = drm_gem_fb_destroy,
1298 .create_handle = drm_gem_fb_create_handle,
1299};
1300
1301int
1302radeon_framebuffer_init(struct drm_device *dev,
1303 struct drm_framebuffer *fb,
1304 const struct drm_mode_fb_cmd2 *mode_cmd,
1305 struct drm_gem_object *obj)
1306{
1307 int ret;
1308 fb->obj[0] = obj;
1309 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1310 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1311 if (ret) {
1312 fb->obj[0] = NULL((void *)0);
1313 return ret;
1314 }
1315 return 0;
1316}
1317
1318static struct drm_framebuffer *
1319radeon_user_framebuffer_create(struct drm_device *dev,
1320 struct drm_file *file_priv,
1321 const struct drm_mode_fb_cmd2 *mode_cmd)
1322{
1323 struct drm_gem_object *obj;
1324 struct drm_framebuffer *fb;
1325 int ret;
1326
1327 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1328 if (obj == NULL((void *)0)) {
1329 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "printf("drm:pid%d:%s *ERROR* " "No GEM object associated to handle 0x%08X, "
"can't create framebuffer\n", ({struct cpu_info *__ci; asm volatile
("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct
cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid
, __func__ , mode_cmd->handles[0])
1330 "can't create framebuffer\n", mode_cmd->handles[0])printf("drm:pid%d:%s *ERROR* " "No GEM object associated to handle 0x%08X, "
"can't create framebuffer\n", ({struct cpu_info *__ci; asm volatile
("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct
cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid
, __func__ , mode_cmd->handles[0])
;
1331 return ERR_PTR(-ENOENT2);
1332 }
1333
1334 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1335 if (obj->import_attach) {
1336 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n")__drm_dbg(DRM_UT_KMS, "Cannot create framebuffer from imported dma_buf\n"
)
;
1337 drm_gem_object_put(obj);
1338 return ERR_PTR(-EINVAL22);
1339 }
1340
1341 fb = kzalloc(sizeof(*fb), GFP_KERNEL(0x0001 | 0x0004));
1342 if (fb == NULL((void *)0)) {
1343 drm_gem_object_put(obj);
1344 return ERR_PTR(-ENOMEM12);
1345 }
1346
1347 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1348 if (ret) {
1349 kfree(fb);
1350 drm_gem_object_put(obj);
1351 return ERR_PTR(ret);
1352 }
1353
1354 return fb;
1355}
1356
1357static const struct drm_mode_config_funcs radeon_mode_funcs = {
1358 .fb_create = radeon_user_framebuffer_create,
1359 .output_poll_changed = drm_fb_helper_output_poll_changed,
1360};
1361
1362static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1363{ { 0, "driver" },
1364 { 1, "bios" },
1365};
1366
1367static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1368{ { TV_STD_NTSC, "ntsc" },
1369 { TV_STD_PAL, "pal" },
1370 { TV_STD_PAL_M, "pal-m" },
1371 { TV_STD_PAL_60, "pal-60" },
1372 { TV_STD_NTSC_J, "ntsc-j" },
1373 { TV_STD_SCART_PAL, "scart-pal" },
1374 { TV_STD_PAL_CN, "pal-cn" },
1375 { TV_STD_SECAM, "secam" },
1376};
1377
1378static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1379{ { UNDERSCAN_OFF, "off" },
1380 { UNDERSCAN_ON, "on" },
1381 { UNDERSCAN_AUTO, "auto" },
1382};
1383
1384static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1385{ { RADEON_AUDIO_DISABLE, "off" },
1386 { RADEON_AUDIO_ENABLE, "on" },
1387 { RADEON_AUDIO_AUTO, "auto" },
1388};
1389
1390/* XXX support different dither options? spatial, temporal, both, etc. */
1391static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1392{ { RADEON_FMT_DITHER_DISABLE, "off" },
1393 { RADEON_FMT_DITHER_ENABLE, "on" },
1394};
1395
1396static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1397{ { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1398 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1399 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1400 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1401};
1402
1403static int radeon_modeset_create_props(struct radeon_device *rdev)
1404{
1405 int sz;
1406
1407 if (rdev->is_atom_bios) {
1408 rdev->mode_info.coherent_mode_property =
1409 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1410 if (!rdev->mode_info.coherent_mode_property)
1411 return -ENOMEM12;
1412 }
1413
1414 if (!ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) {
1415 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list)(sizeof((radeon_tmds_pll_enum_list)) / sizeof((radeon_tmds_pll_enum_list
)[0]))
;
1416 rdev->mode_info.tmds_pll_property =
1417 drm_property_create_enum(rdev->ddev, 0,
1418 "tmds_pll",
1419 radeon_tmds_pll_enum_list, sz);
1420 }
1421
1422 rdev->mode_info.load_detect_property =
1423 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1424 if (!rdev->mode_info.load_detect_property)
1425 return -ENOMEM12;
1426
1427 drm_mode_create_scaling_mode_property(rdev->ddev);
1428
1429 sz = ARRAY_SIZE(radeon_tv_std_enum_list)(sizeof((radeon_tv_std_enum_list)) / sizeof((radeon_tv_std_enum_list
)[0]))
;
1430 rdev->mode_info.tv_std_property =
1431 drm_property_create_enum(rdev->ddev, 0,
1432 "tv standard",
1433 radeon_tv_std_enum_list, sz);
1434
1435 sz = ARRAY_SIZE(radeon_underscan_enum_list)(sizeof((radeon_underscan_enum_list)) / sizeof((radeon_underscan_enum_list
)[0]))
;
1436 rdev->mode_info.underscan_property =
1437 drm_property_create_enum(rdev->ddev, 0,
1438 "underscan",
1439 radeon_underscan_enum_list, sz);
1440
1441 rdev->mode_info.underscan_hborder_property =
1442 drm_property_create_range(rdev->ddev, 0,
1443 "underscan hborder", 0, 128);
1444 if (!rdev->mode_info.underscan_hborder_property)
1445 return -ENOMEM12;
1446
1447 rdev->mode_info.underscan_vborder_property =
1448 drm_property_create_range(rdev->ddev, 0,
1449 "underscan vborder", 0, 128);
1450 if (!rdev->mode_info.underscan_vborder_property)
1451 return -ENOMEM12;
1452
1453 sz = ARRAY_SIZE(radeon_audio_enum_list)(sizeof((radeon_audio_enum_list)) / sizeof((radeon_audio_enum_list
)[0]))
;
1454 rdev->mode_info.audio_property =
1455 drm_property_create_enum(rdev->ddev, 0,
1456 "audio",
1457 radeon_audio_enum_list, sz);
1458
1459 sz = ARRAY_SIZE(radeon_dither_enum_list)(sizeof((radeon_dither_enum_list)) / sizeof((radeon_dither_enum_list
)[0]))
;
1460 rdev->mode_info.dither_property =
1461 drm_property_create_enum(rdev->ddev, 0,
1462 "dither",
1463 radeon_dither_enum_list, sz);
1464
1465 sz = ARRAY_SIZE(radeon_output_csc_enum_list)(sizeof((radeon_output_csc_enum_list)) / sizeof((radeon_output_csc_enum_list
)[0]))
;
1466 rdev->mode_info.output_csc_property =
1467 drm_property_create_enum(rdev->ddev, 0,
1468 "output_csc",
1469 radeon_output_csc_enum_list, sz);
1470
1471 return 0;
1472}
1473
1474void radeon_update_display_priority(struct radeon_device *rdev)
1475{
1476 /* adjustment options for the display watermarks */
1477 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1478 /* set display priority to high for r3xx, rv515 chips
1479 * this avoids flickering due to underflow to the
1480 * display controllers during heavy acceleration.
1481 * Don't force high on rs4xx igp chips as it seems to
1482 * affect the sound card. See kernel bug 15982.
1483 */
1484 if ((ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480))
|| (rdev->family == CHIP_RV515)) &&
1485 !(rdev->flags & RADEON_IS_IGP))
1486 rdev->disp_priority = 2;
1487 else
1488 rdev->disp_priority = 0;
1489 } else
1490 rdev->disp_priority = radeon_disp_priority;
1491
1492}
1493
1494/*
1495 * Allocate hdmi structs and determine register offsets
1496 */
1497static void radeon_afmt_init(struct radeon_device *rdev)
1498{
1499 int i;
1500
1501 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS7; i++)
1502 rdev->mode_info.afmt[i] = NULL((void *)0);
1503
1504 if (ASIC_IS_NODCE(rdev)((rdev->family == CHIP_HAINAN))) {
1505 /* nothing to do */
1506 } else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
1507 static uint32_t eg_offsets[] = {
1508 EVERGREEN_CRTC0_REGISTER_OFFSET(0x6df0 - 0x6df0),
1509 EVERGREEN_CRTC1_REGISTER_OFFSET(0x79f0 - 0x6df0),
1510 EVERGREEN_CRTC2_REGISTER_OFFSET(0x105f0 - 0x6df0),
1511 EVERGREEN_CRTC3_REGISTER_OFFSET(0x111f0 - 0x6df0),
1512 EVERGREEN_CRTC4_REGISTER_OFFSET(0x11df0 - 0x6df0),
1513 EVERGREEN_CRTC5_REGISTER_OFFSET(0x129f0 - 0x6df0),
1514 0x13830 - 0x7030,
1515 };
1516 int num_afmt;
1517
1518 /* DCE8 has 7 audio blocks tied to DIG encoders */
1519 /* DCE6 has 6 audio blocks tied to DIG encoders */
1520 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1521 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1522 if (ASIC_IS_DCE8(rdev)((rdev->family >= CHIP_BONAIRE)))
1523 num_afmt = 7;
1524 else if (ASIC_IS_DCE6(rdev)((rdev->family >= CHIP_ARUBA)))
1525 num_afmt = 6;
1526 else if (ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)))
1527 num_afmt = 6;
1528 else if (ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
& RADEON_IS_IGP))
)
1529 num_afmt = 2;
1530 else /* DCE4 */
1531 num_afmt = 6;
1532
1533 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets))((!(num_afmt > (sizeof((eg_offsets)) / sizeof((eg_offsets)
[0])))) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/radeon/radeon_display.c"
, 1533, "!(num_afmt > (sizeof((eg_offsets)) / sizeof((eg_offsets)[0])))"
))
;
1534 for (i = 0; i < num_afmt; i++) {
1535 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL(0x0001 | 0x0004));
1536 if (rdev->mode_info.afmt[i]) {
1537 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1538 rdev->mode_info.afmt[i]->id = i;
1539 }
1540 }
1541 } else if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
1542 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1543 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL(0x0001 | 0x0004));
1544 if (rdev->mode_info.afmt[0]) {
1545 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0(0x7400 - 0x7400);
1546 rdev->mode_info.afmt[0]->id = 0;
1547 }
1548 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL(0x0001 | 0x0004));
1549 if (rdev->mode_info.afmt[1]) {
1550 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1(0x7800 - 0x7400);
1551 rdev->mode_info.afmt[1]->id = 1;
1552 }
1553 } else if (ASIC_IS_DCE2(rdev)((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690
) || (rdev->family == CHIP_RS740) || (rdev->family >=
CHIP_R600))
) {
1554 /* DCE2 has at least 1 routable audio block */
1555 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL(0x0001 | 0x0004));
1556 if (rdev->mode_info.afmt[0]) {
1557 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0(0x7400 - 0x7400);
1558 rdev->mode_info.afmt[0]->id = 0;
1559 }
1560 /* r6xx has 2 routable audio blocks */
1561 if (rdev->family >= CHIP_R600) {
1562 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL(0x0001 | 0x0004));
1563 if (rdev->mode_info.afmt[1]) {
1564 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1(0x7700 - 0x7400);
1565 rdev->mode_info.afmt[1]->id = 1;
1566 }
1567 }
1568 }
1569}
1570
1571static void radeon_afmt_fini(struct radeon_device *rdev)
1572{
1573 int i;
1574
1575 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS7; i++) {
1576 kfree(rdev->mode_info.afmt[i]);
1577 rdev->mode_info.afmt[i] = NULL((void *)0);
1578 }
1579}
1580
1581int radeon_modeset_init(struct radeon_device *rdev)
1582{
1583 int i;
1584 int ret;
1585
1586 drm_mode_config_init(rdev->ddev);
1587 rdev->mode_info.mode_config_initialized = true1;
1588
1589 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1590
1591 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1592 rdev->ddev->mode_config.async_page_flip = true1;
1593
1594 if (ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS))) {
1595 rdev->ddev->mode_config.max_width = 16384;
1596 rdev->ddev->mode_config.max_height = 16384;
1597 } else if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) {
1598 rdev->ddev->mode_config.max_width = 8192;
1599 rdev->ddev->mode_config.max_height = 8192;
1600 } else {
1601 rdev->ddev->mode_config.max_width = 4096;
1602 rdev->ddev->mode_config.max_height = 4096;
1603 }
1604
1605 rdev->ddev->mode_config.preferred_depth = 24;
1606 rdev->ddev->mode_config.prefer_shadow = 1;
1607
1608 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1609
1610 ret = radeon_modeset_create_props(rdev);
1611 if (ret) {
1612 return ret;
1613 }
1614
1615 /* init i2c buses */
1616 radeon_i2c_init(rdev);
1617
1618 /* check combios for a valid hardcoded EDID - Sun servers */
1619 if (!rdev->is_atom_bios) {
1620 /* check for hardcoded EDID in BIOS */
1621 radeon_combios_check_hardcoded_edid(rdev);
1622 }
1623
1624 /* allocate crtcs */
1625 for (i = 0; i < rdev->num_crtc; i++) {
1626 radeon_crtc_init(rdev->ddev, i);
1627 }
1628
1629 /* okay we should have all the bios connectors */
1630 ret = radeon_setup_enc_conn(rdev->ddev);
1631 if (!ret) {
1632 return ret;
1633 }
1634
1635 /* init dig PHYs, disp eng pll */
1636 if (rdev->is_atom_bios) {
1637 radeon_atom_encoder_init(rdev);
1638 radeon_atom_disp_eng_pll_init(rdev);
1639 }
1640
1641 /* initialize hpd */
1642 radeon_hpd_init(rdev)(rdev)->asic->hpd.init((rdev));
1643
1644 /* setup afmt */
1645 radeon_afmt_init(rdev);
1646
1647 radeon_fbdev_init(rdev);
1648 drm_kms_helper_poll_init(rdev->ddev);
1649
1650 /* do pm late init */
1651 ret = radeon_pm_late_init(rdev);
1652
1653 return 0;
1654}
1655
1656void radeon_modeset_fini(struct radeon_device *rdev)
1657{
1658 if (rdev->mode_info.mode_config_initialized) {
1659 drm_kms_helper_poll_fini(rdev->ddev);
1660 radeon_hpd_fini(rdev)(rdev)->asic->hpd.fini((rdev));
1661 drm_helper_force_disable_all(rdev->ddev);
1662 radeon_fbdev_fini(rdev);
1663 radeon_afmt_fini(rdev);
1664 drm_mode_config_cleanup(rdev->ddev);
1665 rdev->mode_info.mode_config_initialized = false0;
1666 }
1667
1668 kfree(rdev->mode_info.bios_hardcoded_edid);
1669
1670 /* free i2c buses */
1671 radeon_i2c_fini(rdev);
1672}
1673
1674static bool_Bool is_hdtv_mode(const struct drm_display_mode *mode)
1675{
1676 /* try and guess if this is a tv or a monitor */
1677 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1678 (mode->vdisplay == 576) || /* 576p */
1679 (mode->vdisplay == 720) || /* 720p */
1680 (mode->vdisplay == 1080)) /* 1080p */
1681 return true1;
1682 else
1683 return false0;
1684}
1685
1686bool_Bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1687 const struct drm_display_mode *mode,
1688 struct drm_display_mode *adjusted_mode)
1689{
1690 struct drm_device *dev = crtc->dev;
1691 struct radeon_device *rdev = dev->dev_private;
1692 struct drm_encoder *encoder;
1693 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );})
;
1694 struct radeon_encoder *radeon_encoder;
1695 struct drm_connector *connector;
1696 bool_Bool first = true1;
1697 u32 src_v = 1, dst_v = 1;
1698 u32 src_h = 1, dst_h = 1;
1699
1700 radeon_crtc->h_border = 0;
1701 radeon_crtc->v_border = 0;
1702
1703 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}))
{
1704 if (encoder->crtc != crtc)
1705 continue;
1706 radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
1707 connector = radeon_get_connector_for_encoder(encoder);
1708
1709 if (first) {
1710 /* set scaling */
1711 if (radeon_encoder->rmx_type == RMX_OFF)
1712 radeon_crtc->rmx_type = RMX_OFF;
1713 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1714 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1715 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1716 else
1717 radeon_crtc->rmx_type = RMX_OFF;
1718 /* copy native mode */
1719 memcpy(&radeon_crtc->native_mode,__builtin_memcpy((&radeon_crtc->native_mode), (&radeon_encoder
->native_mode), (sizeof(struct drm_display_mode)))
1720 &radeon_encoder->native_mode,__builtin_memcpy((&radeon_crtc->native_mode), (&radeon_encoder
->native_mode), (sizeof(struct drm_display_mode)))
1721 sizeof(struct drm_display_mode))__builtin_memcpy((&radeon_crtc->native_mode), (&radeon_encoder
->native_mode), (sizeof(struct drm_display_mode)))
;
1722 src_v = crtc->mode.vdisplay;
1723 dst_v = radeon_crtc->native_mode.vdisplay;
1724 src_h = crtc->mode.hdisplay;
1725 dst_h = radeon_crtc->native_mode.hdisplay;
1726
1727 /* fix up for overscan on hdmi */
1728 if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) &&
1729 (!(mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))) &&
1730 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1731 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1732 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1733 is_hdtv_mode(mode)))) {
1734 if (radeon_encoder->underscan_hborder != 0)
1735 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1736 else
1737 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1738 if (radeon_encoder->underscan_vborder != 0)
1739 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1740 else
1741 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1742 radeon_crtc->rmx_type = RMX_FULL;
1743 src_v = crtc->mode.vdisplay;
1744 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1745 src_h = crtc->mode.hdisplay;
1746 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1747 }
1748 first = false0;
1749 } else {
1750 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1751 /* WARNING: Right now this can't happen but
1752 * in the future we need to check that scaling
1753 * are consistent across different encoder
1754 * (ie all encoder can work with the same
1755 * scaling).
1756 */
1757 DRM_ERROR("Scaling not consistent across encoder.\n")__drm_err("Scaling not consistent across encoder.\n");
1758 return false0;
1759 }
1760 }
1761 }
1762 if (radeon_crtc->rmx_type != RMX_OFF) {
1763 fixed20_12 a, b;
1764 a.full = dfixed_const(src_v)(u32)(((src_v) << 12));
1765 b.full = dfixed_const(dst_v)(u32)(((dst_v) << 12));
1766 radeon_crtc->vsc.full = dfixed_div(a, b);
1767 a.full = dfixed_const(src_h)(u32)(((src_h) << 12));
1768 b.full = dfixed_const(dst_h)(u32)(((dst_h) << 12));
1769 radeon_crtc->hsc.full = dfixed_div(a, b);
1770 } else {
1771 radeon_crtc->vsc.full = dfixed_const(1)(u32)(((1) << 12));
1772 radeon_crtc->hsc.full = dfixed_const(1)(u32)(((1) << 12));
1773 }
1774 return true1;
1775}
1776
1777/*
1778 * Retrieve current video scanout position of crtc on a given gpu, and
1779 * an optional accurate timestamp of when query happened.
1780 *
1781 * \param dev Device to query.
1782 * \param crtc Crtc to query.
1783 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1784 * For driver internal use only also supports these flags:
1785 *
1786 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1787 * of a fudged earlier start of vblank.
1788 *
1789 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1790 * fudged earlier start of vblank in *vpos and the distance
1791 * to true start of vblank in *hpos.
1792 *
1793 * \param *vpos Location where vertical scanout position should be stored.
1794 * \param *hpos Location where horizontal scanout position should go.
1795 * \param *stime Target location for timestamp taken immediately before
1796 * scanout position query. Can be NULL to skip timestamp.
1797 * \param *etime Target location for timestamp taken immediately after
1798 * scanout position query. Can be NULL to skip timestamp.
1799 *
1800 * Returns vpos as a positive number while in active scanout area.
1801 * Returns vpos as a negative number inside vblank, counting the number
1802 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1803 * until start of active scanout / end of vblank."
1804 *
1805 * \return Flags, or'ed together as follows:
1806 *
1807 * DRM_SCANOUTPOS_VALID = Query successful.
1808 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1809 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1810 * this flag means that returned position may be offset by a constant but
1811 * unknown small number of scanlines wrt. real scanout position.
1812 *
1813 */
1814int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1815 unsigned int flags, int *vpos, int *hpos,
1816 ktime_t *stime, ktime_t *etime,
1817 const struct drm_display_mode *mode)
1818{
1819 u32 stat_crtc = 0, vbl = 0, position = 0;
1820 int vbl_start, vbl_end, vtotal, ret = 0;
1821 bool_Bool in_vbl = true1;
1822
1823 struct radeon_device *rdev = dev->dev_private;
1824
1825 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1826
1827 /* Get optional system timestamp before query. */
1828 if (stime)
1829 *stime = ktime_get();
1830
1831 if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
1832 if (pipe == 0) {
1833 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x6df0 - 0x6df0)), 0)
1834 EVERGREEN_CRTC0_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x6df0 - 0x6df0)), 0);
1835 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x6df0 - 0x6df0)), 0)
1836 EVERGREEN_CRTC0_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x6df0 - 0x6df0)), 0);
1837 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1838 }
1839 if (pipe == 1) {
1840 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x79f0 - 0x6df0)), 0)
1841 EVERGREEN_CRTC1_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x79f0 - 0x6df0)), 0);
1842 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x79f0 - 0x6df0)), 0)
1843 EVERGREEN_CRTC1_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x79f0 - 0x6df0)), 0);
1844 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1845 }
1846 if (pipe == 2) {
1847 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x105f0 - 0x6df0)), 0)
1848 EVERGREEN_CRTC2_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x105f0 - 0x6df0)), 0);
1849 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x105f0 - 0x6df0)), 0)
1850 EVERGREEN_CRTC2_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x105f0 - 0x6df0)), 0);
1851 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1852 }
1853 if (pipe == 3) {
1854 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x111f0 - 0x6df0)), 0)
1855 EVERGREEN_CRTC3_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x111f0 - 0x6df0)), 0);
1856 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x111f0 - 0x6df0)), 0)
1857 EVERGREEN_CRTC3_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x111f0 - 0x6df0)), 0);
1858 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1859 }
1860 if (pipe == 4) {
1861 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x11df0 - 0x6df0)), 0)
1862 EVERGREEN_CRTC4_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x11df0 - 0x6df0)), 0);
1863 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x11df0 - 0x6df0)), 0)
1864 EVERGREEN_CRTC4_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x11df0 - 0x6df0)), 0);
1865 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1866 }
1867 if (pipe == 5) {
1868 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +r100_mm_rreg(rdev, (0x6e34 + (0x129f0 - 0x6df0)), 0)
1869 EVERGREEN_CRTC5_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e34 + (0x129f0 - 0x6df0)), 0);
1870 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +r100_mm_rreg(rdev, (0x6e90 + (0x129f0 - 0x6df0)), 0)
1871 EVERGREEN_CRTC5_REGISTER_OFFSET)r100_mm_rreg(rdev, (0x6e90 + (0x129f0 - 0x6df0)), 0);
1872 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1873 }
1874 } else if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) {
1875 if (pipe == 0) {
1876 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END)r100_mm_rreg(rdev, (0x6024), 0);
1877 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION)r100_mm_rreg(rdev, (0x60a0), 0);
1878 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1879 }
1880 if (pipe == 1) {
1881 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END)r100_mm_rreg(rdev, (0x6824), 0);
1882 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION)r100_mm_rreg(rdev, (0x68a0), 0);
1883 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1884 }
1885 } else {
1886 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1887 if (pipe == 0) {
1888 /* Assume vbl_end == 0, get vbl_start from
1889 * upper 16 bits.
1890 */
1891 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP)r100_mm_rreg(rdev, (0x0208), 0) &
1892 RADEON_CRTC_V_DISP(0x07ff << 16)) >> RADEON_CRTC_V_DISP_SHIFT16;
1893 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1894 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0210), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
1895 stat_crtc = RREG32(RADEON_CRTC_STATUS)r100_mm_rreg(rdev, (0x005c), 0);
1896 if (!(stat_crtc & 1))
1897 in_vbl = false0;
1898
1899 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1900 }
1901 if (pipe == 1) {
1902 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP)r100_mm_rreg(rdev, (0x0308), 0) &
1903 RADEON_CRTC_V_DISP(0x07ff << 16)) >> RADEON_CRTC_V_DISP_SHIFT16;
1904 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0310), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
1905 stat_crtc = RREG32(RADEON_CRTC2_STATUS)r100_mm_rreg(rdev, (0x03fc), 0);
1906 if (!(stat_crtc & 1))
1907 in_vbl = false0;
1908
1909 ret |= DRM_SCANOUTPOS_VALID(1 << 0);
1910 }
1911 }
1912
1913 /* Get optional system timestamp after query. */
1914 if (etime)
1915 *etime = ktime_get();
1916
1917 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1918
1919 /* Decode into vertical and horizontal scanout position. */
1920 *vpos = position & 0x1fff;
1921 *hpos = (position >> 16) & 0x1fff;
1922
1923 /* Valid vblank area boundaries from gpu retrieved? */
1924 if (vbl > 0) {
1925 /* Yes: Decode. */
1926 ret |= DRM_SCANOUTPOS_ACCURATE(1 << 2);
1927 vbl_start = vbl & 0x1fff;
1928 vbl_end = (vbl >> 16) & 0x1fff;
1929 }
1930 else {
1931 /* No: Fake something reasonable which gives at least ok results. */
1932 vbl_start = mode->crtc_vdisplay;
1933 vbl_end = 0;
1934 }
1935
1936 /* Called from driver internal vblank counter query code? */
1937 if (flags & GET_DISTANCE_TO_VBLANKSTART(1 << 31)) {
1938 /* Caller wants distance from real vbl_start in *hpos */
1939 *hpos = *vpos - vbl_start;
1940 }
1941
1942 /* Fudge vblank to start a few scanlines earlier to handle the
1943 * problem that vblank irqs fire a few scanlines before start
1944 * of vblank. Some driver internal callers need the true vblank
1945 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1946 *
1947 * The cause of the "early" vblank irq is that the irq is triggered
1948 * by the line buffer logic when the line buffer read position enters
1949 * the vblank, whereas our crtc scanout position naturally lags the
1950 * line buffer read position.
1951 */
1952 if (!(flags & USE_REAL_VBLANKSTART(1 << 30)))
1953 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1954
1955 /* Test scanout position against vblank region. */
1956 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1957 in_vbl = false0;
1958
1959 /* In vblank? */
1960 if (in_vbl)
1961 ret |= DRM_SCANOUTPOS_IN_VBLANK(1 << 1);
1962
1963 /* Called from driver internal vblank counter query code? */
1964 if (flags & GET_DISTANCE_TO_VBLANKSTART(1 << 31)) {
1965 /* Caller wants distance from fudged earlier vbl_start */
1966 *vpos -= vbl_start;
1967 return ret;
1968 }
1969
1970 /* Check if inside vblank area and apply corrective offsets:
1971 * vpos will then be >=0 in video scanout area, but negative
1972 * within vblank area, counting down the number of lines until
1973 * start of scanout.
1974 */
1975
1976 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1977 if (in_vbl && (*vpos >= vbl_start)) {
1978 vtotal = mode->crtc_vtotal;
1979 *vpos = *vpos - vtotal;
1980 }
1981
1982 /* Correct for shifted end of vbl at vbl_end. */
1983 *vpos = *vpos - vbl_end;
1984
1985 return ret;
1986}
1987
1988bool_Bool
1989radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1990 bool_Bool in_vblank_irq, int *vpos, int *hpos,
1991 ktime_t *stime, ktime_t *etime,
1992 const struct drm_display_mode *mode)
1993{
1994 struct drm_device *dev = crtc->dev;
1995 unsigned int pipe = crtc->index;
1996
1997 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1998 stime, etime, mode);
1999}