Bug Summary

File:dev/pci/drm/amd/amdgpu/gfx_v9_0.c
Warning:line 1563, column 3
Access to field 'data' results in a dereference of a null pointer (loaded from field 'mec2_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name gfx_v9_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_gfx.h"
32#include "soc15.h"
33#include "soc15d.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_pm.h"
36
37#include "gc/gc_9_0_offset.h"
38#include "gc/gc_9_0_sh_mask.h"
39
40#include "vega10_enum.h"
41#include "hdp/hdp_4_0_offset.h"
42
43#include "soc15_common.h"
44#include "clearstate_gfx9.h"
45#include "v9_structs.h"
46
47#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
48
49#include "amdgpu_ras.h"
50
51#include "gfx_v9_4.h"
52#include "gfx_v9_0.h"
53
54#include "asic_reg/pwr/pwr_10_0_offset.h"
55#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
56
57#define GFX9_NUM_GFX_RINGS1 1
58#define GFX9_MEC_HPD_SIZE4096 4096
59#define RLCG_UCODE_LOADING_START_ADDRESS0x00002000L 0x00002000L
60#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET0x00000000L 0x00000000L
61
62#define mmGCEA_PROBE_MAP0x070c 0x070c
63#define mmGCEA_PROBE_MAP_BASE_IDX0 0
64
65MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
66MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
67MODULE_FIRMWARE("amdgpu/vega10_me.bin");
68MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
69MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
70MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
71
72MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
73MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
74MODULE_FIRMWARE("amdgpu/vega12_me.bin");
75MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
76MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
77MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
78
79MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
80MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
81MODULE_FIRMWARE("amdgpu/vega20_me.bin");
82MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
83MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
84MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
85
86MODULE_FIRMWARE("amdgpu/raven_ce.bin");
87MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
88MODULE_FIRMWARE("amdgpu/raven_me.bin");
89MODULE_FIRMWARE("amdgpu/raven_mec.bin");
90MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
91MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
92
93MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
94MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
95MODULE_FIRMWARE("amdgpu/picasso_me.bin");
96MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
97MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
98MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
99MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
100
101MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
102MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
103MODULE_FIRMWARE("amdgpu/raven2_me.bin");
104MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
105MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
106MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
107MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
108
109MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
110MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
111MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
112
113MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
114MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
115MODULE_FIRMWARE("amdgpu/renoir_me.bin");
116MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
117MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
118MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
119
120MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
121MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
122MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
123MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
124MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
125MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
126
127#define mmTCP_CHAN_STEER_0_ARCT0x0b03 0x0b03
128#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX0 0
129#define mmTCP_CHAN_STEER_1_ARCT0x0b04 0x0b04
130#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX0 0
131#define mmTCP_CHAN_STEER_2_ARCT0x0b09 0x0b09
132#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX0 0
133#define mmTCP_CHAN_STEER_3_ARCT0x0b0a 0x0b0a
134#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX0 0
135#define mmTCP_CHAN_STEER_4_ARCT0x0b0b 0x0b0b
136#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX0 0
137#define mmTCP_CHAN_STEER_5_ARCT0x0b0c 0x0b0c
138#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX0 0
139
140#define mmGOLDEN_TSC_COUNT_UPPER_Renoir0x0025 0x0025
141#define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX1 1
142#define mmGOLDEN_TSC_COUNT_LOWER_Renoir0x0026 0x0026
143#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX1 1
144
145enum ta_ras_gfx_subblock {
146 /*CPC*/
147 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
148 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
149 TA_RAS_BLOCK__GFX_CPC_UCODE,
150 TA_RAS_BLOCK__GFX_DC_STATE_ME1,
151 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
152 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
153 TA_RAS_BLOCK__GFX_DC_STATE_ME2,
154 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
155 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
156 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
157 /* CPF*/
158 TA_RAS_BLOCK__GFX_CPF_INDEX_START,
159 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
160 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
161 TA_RAS_BLOCK__GFX_CPF_TAG,
162 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
163 /* CPG*/
164 TA_RAS_BLOCK__GFX_CPG_INDEX_START,
165 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
166 TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
167 TA_RAS_BLOCK__GFX_CPG_TAG,
168 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
169 /* GDS*/
170 TA_RAS_BLOCK__GFX_GDS_INDEX_START,
171 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
172 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
173 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
174 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
175 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
176 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
177 /* SPI*/
178 TA_RAS_BLOCK__GFX_SPI_SR_MEM,
179 /* SQ*/
180 TA_RAS_BLOCK__GFX_SQ_INDEX_START,
181 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
182 TA_RAS_BLOCK__GFX_SQ_LDS_D,
183 TA_RAS_BLOCK__GFX_SQ_LDS_I,
184 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
185 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
186 /* SQC (3 ranges)*/
187 TA_RAS_BLOCK__GFX_SQC_INDEX_START,
188 /* SQC range 0*/
189 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
190 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
191 TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
192 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
193 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
194 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
195 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
196 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
197 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
198 TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
199 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
200 /* SQC range 1*/
201 TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
202 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
203 TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
204 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
205 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
206 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
207 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
208 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
209 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
210 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
211 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
212 TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
214 /* SQC range 2*/
215 TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
216 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
217 TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
218 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
219 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
220 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
221 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
222 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
223 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
224 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
225 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
226 TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
227 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
228 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
229 /* TA*/
230 TA_RAS_BLOCK__GFX_TA_INDEX_START,
231 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
232 TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
233 TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
234 TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
235 TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
236 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
237 /* TCA*/
238 TA_RAS_BLOCK__GFX_TCA_INDEX_START,
239 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
240 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
241 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
242 /* TCC (5 sub-ranges)*/
243 TA_RAS_BLOCK__GFX_TCC_INDEX_START,
244 /* TCC range 0*/
245 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
246 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
247 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
248 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
249 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
250 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
251 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
252 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
253 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
254 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
255 /* TCC range 1*/
256 TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
257 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
258 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
259 TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
260 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
261 /* TCC range 2*/
262 TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
263 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
264 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
265 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
266 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
267 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
268 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
269 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
270 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
271 TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
272 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
273 /* TCC range 3*/
274 TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
275 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
276 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
277 TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
278 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
279 /* TCC range 4*/
280 TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
281 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
282 TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
283 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
284 TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
285 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
286 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
287 /* TCI*/
288 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
289 /* TCP*/
290 TA_RAS_BLOCK__GFX_TCP_INDEX_START,
291 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
292 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
293 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
294 TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
295 TA_RAS_BLOCK__GFX_TCP_DB_RAM,
296 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
297 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
298 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
299 /* TD*/
300 TA_RAS_BLOCK__GFX_TD_INDEX_START,
301 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
302 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
303 TA_RAS_BLOCK__GFX_TD_CS_FIFO,
304 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
305 /* EA (3 sub-ranges)*/
306 TA_RAS_BLOCK__GFX_EA_INDEX_START,
307 /* EA range 0*/
308 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
309 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
310 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
311 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
312 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
313 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
314 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
315 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
316 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
317 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
318 /* EA range 1*/
319 TA_RAS_BLOCK__GFX_EA_INDEX1_START,
320 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
321 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
322 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
323 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
324 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
325 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
326 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
327 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
328 /* EA range 2*/
329 TA_RAS_BLOCK__GFX_EA_INDEX2_START,
330 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
331 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
332 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
333 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
334 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
335 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
336 /* UTC VM L2 bank*/
337 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
338 /* UTC VM walker*/
339 TA_RAS_BLOCK__UTC_VML2_WALKER,
340 /* UTC ATC L2 2MB cache*/
341 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
342 /* UTC ATC L2 4KB cache*/
343 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
344 TA_RAS_BLOCK__GFX_MAX
345};
346
347struct ras_gfx_subblock {
348 unsigned char *name;
349 int ta_subblock;
350 int hw_supported_error_type;
351 int sw_supported_error_type;
352};
353
354#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)[AMDGPU_RAS_BLOCK__subblock] = { "subblock", TA_RAS_BLOCK__subblock
, ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3
)), (((e) << 1) | ((f) << 3) | (g) | ((h) <<
2)), } \
355 [AMDGPU_RAS_BLOCK__##subblock] = { \
356 #subblock, \
357 TA_RAS_BLOCK__##subblock, \
358 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \
359 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \
360 }
361
362static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
363 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH] = { "GFX_CPC_SCRATCH", TA_RAS_BLOCK__GFX_CPC_SCRATCH
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((0) << 3) | (0) | ((1) <<
2)), },
364 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPC_UCODE] = { "GFX_CPC_UCODE", TA_RAS_BLOCK__GFX_CPC_UCODE
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((0) << 3) | (0) | ((1) <<
2)), },
365 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1] = { "GFX_DC_STATE_ME1", TA_RAS_BLOCK__GFX_DC_STATE_ME1
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (1) | ((0) <<
2)), },
366 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1] = { "GFX_DC_CSINVOC_ME1"
, TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
367 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1] = { "GFX_DC_RESTORE_ME1"
, TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
368 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2] = { "GFX_DC_STATE_ME2", TA_RAS_BLOCK__GFX_DC_STATE_ME2
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
369 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2] = { "GFX_DC_CSINVOC_ME2"
, TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
370 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2] = { "GFX_DC_RESTORE_ME2"
, TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
371 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2] = { "GFX_CPF_ROQ_ME2", TA_RAS_BLOCK__GFX_CPF_ROQ_ME2
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
372 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1] = { "GFX_CPF_ROQ_ME1", TA_RAS_BLOCK__GFX_CPF_ROQ_ME1
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (1) | ((0) <<
2)), },
373 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPF_TAG] = { "GFX_CPF_TAG", TA_RAS_BLOCK__GFX_CPF_TAG
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((0) << 3) | (0) | ((1) <<
2)), },
374 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ] = { "GFX_CPG_DMA_ROQ", TA_RAS_BLOCK__GFX_CPG_DMA_ROQ
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (1) | ((0) <<
2)), },
375 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG] = { "GFX_CPG_DMA_TAG", TA_RAS_BLOCK__GFX_CPG_DMA_TAG
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((1) << 3) | (0) | ((1) <<
2)), },
376 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPG_TAG] = { "GFX_CPG_TAG", TA_RAS_BLOCK__GFX_CPG_TAG
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((1) << 3) | (0) | ((1) <<
2)), },
377 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_MEM] = { "GFX_GDS_MEM", TA_RAS_BLOCK__GFX_GDS_MEM
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
378 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE] = { "GFX_GDS_INPUT_QUEUE"
, TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
379 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM] = { "GFX_GDS_OA_PHY_CMD_RAM_MEM"
, TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
380 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM] = { "GFX_GDS_OA_PHY_CMD_RAM_MEM"
, TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
381 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM] = { "GFX_GDS_OA_PHY_DATA_RAM_MEM"
, TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
382 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM] = { "GFX_GDS_OA_PHY_DATA_RAM_MEM"
, TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
383 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM] = { "GFX_GDS_OA_PIPE_MEM"
, TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
384 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM] = { "GFX_SPI_SR_MEM", TA_RAS_BLOCK__GFX_SPI_SR_MEM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
385 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_SGPR] = { "GFX_SQ_SGPR", TA_RAS_BLOCK__GFX_SQ_SGPR
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
386 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D] = { "GFX_SQ_LDS_D", TA_RAS_BLOCK__GFX_SQ_LDS_D
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((0) << 3) | (0) | ((1) <<
2)), },
387 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I] = { "GFX_SQ_LDS_I", TA_RAS_BLOCK__GFX_SQ_LDS_I
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
388 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_VGPR] = { "GFX_SQ_VGPR", TA_RAS_BLOCK__GFX_SQ_VGPR
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO] = { "GFX_SQC_INST_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((1) << 2)), },
390 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU0_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
391 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU0_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
392 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU0_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
393 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU0_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
394 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU1_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
395 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU1_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
396 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU1_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
397 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU1_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
398 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU2_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
399 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU2_WRITE_DATA_BUF"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
400 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU2_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
401 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU2_UTCL1_LFIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
402 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM] = { "GFX_SQC_INST_BANKA_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), }
403 1)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM] = { "GFX_SQC_INST_BANKA_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), },
404 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ((1) | ((
0) << 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), }
405 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ((1) | ((
0) << 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), },
406 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO] = { "GFX_SQC_INST_BANKA_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
407 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO] = { "GFX_SQC_INST_BANKA_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
408 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM] = { "GFX_SQC_INST_BANKA_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
409 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM] = { "GFX_SQC_INST_BANKA_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
410 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM] = { "GFX_SQC_DATA_BANKA_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
411 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM] = { "GFX_SQC_DATA_BANKA_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
412 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO] = { "GFX_SQC_DATA_BANKA_HIT_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
413 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO] = { "GFX_SQC_DATA_BANKA_HIT_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
414 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO] = { "GFX_SQC_DATA_BANKA_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
415 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO] = { "GFX_SQC_DATA_BANKA_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
416 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ((1) | ((0)
<< 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), }
417 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ((1) | ((0)
<< 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), },
418 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM] = { "GFX_SQC_DATA_BANKA_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
419 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM] = { "GFX_SQC_DATA_BANKA_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
420 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM] = { "GFX_SQC_INST_BANKB_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
421 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM] = { "GFX_SQC_INST_BANKB_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
422 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ((1) | ((
0) << 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), }
423 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ((1) | ((
0) << 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), },
424 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO] = { "GFX_SQC_INST_BANKB_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
425 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO] = { "GFX_SQC_INST_BANKB_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
426 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM] = { "GFX_SQC_INST_BANKB_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
427 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM] = { "GFX_SQC_INST_BANKB_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
428 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM] = { "GFX_SQC_DATA_BANKB_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
429 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM] = { "GFX_SQC_DATA_BANKB_TAG_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
430 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO] = { "GFX_SQC_DATA_BANKB_HIT_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
431 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO] = { "GFX_SQC_DATA_BANKB_HIT_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
432 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO] = { "GFX_SQC_DATA_BANKB_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
433 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO] = { "GFX_SQC_DATA_BANKB_MISS_FIFO"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
434 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ((1) | ((0)
<< 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), }
435 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ((1) | ((0)
<< 1) | ((0) << 2) | ((1) << 3)), (((0) <<
1) | ((0) << 3) | (0) | ((0) << 2)), },
436 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM] = { "GFX_SQC_DATA_BANKB_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
437 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM] = { "GFX_SQC_DATA_BANKB_BANK_RAM"
, TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
438 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO] = { "GFX_TA_FS_DFIFO", TA_RAS_BLOCK__GFX_TA_FS_DFIFO
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((1) << 1) | ((0) << 3) | (0) | ((1) <<
2)), },
439 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO] = { "GFX_TA_FS_AFIFO", TA_RAS_BLOCK__GFX_TA_FS_AFIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
440 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO] = { "GFX_TA_FL_LFIFO", TA_RAS_BLOCK__GFX_TA_FL_LFIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
441 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO] = { "GFX_TA_FX_LFIFO", TA_RAS_BLOCK__GFX_TA_FX_LFIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
442 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO] = { "GFX_TA_FS_CFIFO", TA_RAS_BLOCK__GFX_TA_FS_CFIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
443 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO] = { "GFX_TCA_HOLE_FIFO"
, TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO, ((1) | ((0) << 1) | (
(0) << 2) | ((1) << 3)), (((0) << 1) | ((1)
<< 3) | (1) | ((0) << 2)), },
444 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO] = { "GFX_TCA_REQ_FIFO", TA_RAS_BLOCK__GFX_TCA_REQ_FIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA] = { "GFX_TCC_CACHE_DATA"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((1) << 1) | ((
0) << 3) | (0) | ((1) << 2)), },
446 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1] = { "GFX_TCC_CACHE_DATA_BANK_0_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), }
447 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1] = { "GFX_TCC_CACHE_DATA_BANK_0_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), },
448 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0] = { "GFX_TCC_CACHE_DATA_BANK_1_0"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), }
449 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0] = { "GFX_TCC_CACHE_DATA_BANK_1_0"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), },
450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1] = { "GFX_TCC_CACHE_DATA_BANK_1_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), }
451 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1] = { "GFX_TCC_CACHE_DATA_BANK_1_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((1) << 1)
| ((0) << 3) | (0) | ((1) << 2)), },
452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0] = { "GFX_TCC_CACHE_DIRTY_BANK_0"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
453 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0] = { "GFX_TCC_CACHE_DIRTY_BANK_0"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1] = { "GFX_TCC_CACHE_DIRTY_BANK_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
455 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1] = { "GFX_TCC_CACHE_DIRTY_BANK_1"
, TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG] = { "GFX_TCC_HIGH_RATE_TAG"
, TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, ((0) | ((1) << 1
) | ((1) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG] = { "GFX_TCC_LOW_RATE_TAG"
, TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC] = { "GFX_TCC_IN_USE_DEC"
, TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER] = { "GFX_TCC_IN_USE_TRANSFER"
, TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA] = { "GFX_TCC_RETURN_DATA"
, TA_RAS_BLOCK__GFX_TCC_RETURN_DATA, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL] = { "GFX_TCC_RETURN_CONTROL"
, TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, ((1) | ((0) << 1
) | ((0) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO] = { "GFX_TCC_UC_ATOMIC_FIFO"
, TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, ((1) | ((0) << 1
) | ((0) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN] = { "GFX_TCC_WRITE_RETURN"
, TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, ((1) | ((0) << 1)
| ((0) << 2) | ((1) << 3)), (((0) << 1) | (
(1) << 3) | (1) | ((0) << 2)), },
464 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ] = { "GFX_TCC_WRITE_CACHE_READ"
, TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO] = { "GFX_TCC_SRC_FIFO", TA_RAS_BLOCK__GFX_TCC_SRC_FIFO
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
466 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM] = { "GFX_TCC_SRC_FIFO_NEXT_RAM"
, TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (1) | ((0) << 2)), },
467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO] = { "GFX_TCC_CACHE_TAG_PROBE_FIFO"
, TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
468 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO] = { "GFX_TCC_CACHE_TAG_PROBE_FIFO"
, TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO] = { "GFX_TCC_LATENCY_FIFO"
, TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO, ((1) | ((0) << 1)
| ((0) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
470 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM] = { "GFX_TCC_LATENCY_FIFO_NEXT_RAM"
, TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
471 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM] = { "GFX_TCC_LATENCY_FIFO_NEXT_RAM"
, TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
472 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN] = { "GFX_TCC_WRRET_TAG_WRITE_RETURN"
, TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
473 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN] = { "GFX_TCC_WRRET_TAG_WRITE_RETURN"
, TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER] = { "GFX_TCC_ATOMIC_RETURN_BUFFER"
, TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), }
475 0)[AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER] = { "GFX_TCC_ATOMIC_RETURN_BUFFER"
, TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
476 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM] = { "GFX_TCI_WRITE_RAM"
, TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, ((1) | ((0) << 1) | (
(0) << 2) | ((1) << 3)), (((0) << 1) | ((0)
<< 3) | (0) | ((0) << 2)), },
477 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM] = { "GFX_TCP_CACHE_RAM"
, TA_RAS_BLOCK__GFX_TCP_CACHE_RAM, ((0) | ((1) << 1) | (
(1) << 2) | ((1) << 3)), (((1) << 1) | ((0)
<< 3) | (0) | ((1) << 2)), },
478 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM] = { "GFX_TCP_LFIFO_RAM"
, TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, ((0) | ((1) << 1) | (
(1) << 2) | ((1) << 3)), (((0) << 1) | ((0)
<< 3) | (0) | ((0) << 2)), },
479 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO] = { "GFX_TCP_CMD_FIFO", TA_RAS_BLOCK__GFX_TCP_CMD_FIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
480 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO] = { "GFX_TCP_VM_FIFO", TA_RAS_BLOCK__GFX_TCP_VM_FIFO
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
481 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM] = { "GFX_TCP_DB_RAM", TA_RAS_BLOCK__GFX_TCP_DB_RAM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
482 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0] = { "GFX_TCP_UTCL1_LFIFO0"
, TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
483 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1] = { "GFX_TCP_UTCL1_LFIFO1"
, TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
484 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO] = { "GFX_TD_SS_FIFO_LO"
, TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO, ((0) | ((1) << 1) | (
(1) << 2) | ((1) << 3)), (((1) << 1) | ((0)
<< 3) | (0) | ((1) << 2)), },
485 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI] = { "GFX_TD_SS_FIFO_HI"
, TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, ((0) | ((1) << 1) | (
(1) << 2) | ((1) << 3)), (((0) << 1) | ((0)
<< 3) | (0) | ((0) << 2)), },
486 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO] = { "GFX_TD_CS_FIFO", TA_RAS_BLOCK__GFX_TD_CS_FIFO
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM] = { "GFX_EA_DRAMRD_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((1) << 1) | (
(0) << 3) | (0) | ((1) << 2)), },
488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM] = { "GFX_EA_DRAMWR_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM] = { "GFX_EA_DRAMWR_DATAMEM"
, TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, ((0) | ((1) << 1
) | ((1) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM] = { "GFX_EA_RRET_TAGMEM"
, TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM] = { "GFX_EA_WRET_TAGMEM"
, TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM] = { "GFX_EA_GMIRD_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM] = { "GFX_EA_GMIWR_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM] = { "GFX_EA_GMIWR_DATAMEM"
, TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ((0) | ((1) << 1)
| ((1) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM] = { "GFX_EA_DRAMRD_PAGEMEM"
, TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM, ((1) | ((0) << 1
) | ((0) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM] = { "GFX_EA_DRAMWR_PAGEMEM"
, TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, ((1) | ((0) << 1
) | ((0) << 2) | ((1) << 3)), (((0) << 1) |
((0) << 3) | (0) | ((0) << 2)), },
497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM] = { "GFX_EA_IORD_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM] = { "GFX_EA_IOWR_CMDMEM"
, TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
499 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM] = { "GFX_EA_IOWR_DATAMEM"
, TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, ((1) | ((0) << 1) |
((0) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
500 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM] = { "GFX_EA_GMIRD_PAGEMEM"
, TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, ((1) | ((0) << 1)
| ((0) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
501 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM] = { "GFX_EA_GMIWR_PAGEMEM"
, TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ((1) | ((0) << 1)
| ((0) << 2) | ((1) << 3)), (((0) << 1) | (
(0) << 3) | (0) | ((0) << 2)), },
502 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM] = { "GFX_EA_MAM_D0MEM", TA_RAS_BLOCK__GFX_EA_MAM_D0MEM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
503 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM] = { "GFX_EA_MAM_D1MEM", TA_RAS_BLOCK__GFX_EA_MAM_D1MEM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM] = { "GFX_EA_MAM_D2MEM", TA_RAS_BLOCK__GFX_EA_MAM_D2MEM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM] = { "GFX_EA_MAM_D3MEM", TA_RAS_BLOCK__GFX_EA_MAM_D3MEM
, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
506 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE] = { "UTC_VML2_BANK_CACHE"
, TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, ((0) | ((1) << 1) |
((1) << 2) | ((1) << 3)), (((0) << 1) | ((
0) << 3) | (0) | ((0) << 2)), },
507 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_VML2_WALKER] = { "UTC_VML2_WALKER", TA_RAS_BLOCK__UTC_VML2_WALKER
, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3
)), (((0) << 1) | ((0) << 3) | (0) | ((0) <<
2)), },
508 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK] = { "UTC_ATCL2_CACHE_2M_BANK"
, TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, ((1) | ((0) <<
1) | ((0) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
509 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK] = { "UTC_ATCL2_CACHE_4K_BANK"
, TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, ((0) | ((1) <<
1) | ((1) << 2) | ((1) << 3)), (((0) << 1)
| ((0) << 3) | (0) | ((0) << 2)), },
510};
511
512static const struct soc15_reg_golden golden_settings_gc_9_0[] =
513{
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000400 },
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000){ GC_HWIP, 0, 0, 0x060e, 0x80000000, 0x80000000 },
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 },
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 },
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 },
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000){ GC_HWIP, 0, 0, 0x030d, 0x00001000, 0x00001000 },
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dc, 0x0007ffff, 0x00000800 },
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dd, 0x0007ffff, 0x00000800 },
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87){ GC_HWIP, 0, 0, 0x11e6, 0x01ffffff, 0x00ffff87 },
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f){ GC_HWIP, 0, 0, 0x11e7, 0x01ffffff, 0x00ffff8f },
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000){ GC_HWIP, 0, 0, 0x0301, 0x03000000, 0x020a2000 },
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 },
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x4a2c0e68 },
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0xb5d3f197 },
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 },
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000003ff },
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 },
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 },
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 }
534};
535
536static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
537{
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107){ GC_HWIP, 0, 0, 0x0680, 0x0000f000, 0x00012107 },
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 },
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x08000000, 0x08000080 },
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0x08000000, 0x08000080 },
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x08000000, 0x08000080 },
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x2a114042 },
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x2a114042 },
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x08000000, 0x08000080 },
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000){ GC_HWIP, 0, 0, 0x02fd, 0x00008000, 0x00048000 },
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0x08000000, 0x08000080 },
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0x08000000, 0x08000080 },
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0x08000000, 0x08000080 },
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0x08000000, 0x08000080 },
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0x08000000, 0x08000080 },
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00020000 },
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0x0000000f, 0x01000107 },
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800){ GC_HWIP, 0, 0, 0x0525, 0x00001800, 0x00000800 },
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x08000000, 0x08000080 }
556};
557
558static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
559{
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080){ GC_HWIP, 0, 0, 0x0688, 0x0f000080, 0x04000080 },
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0x0f000000, 0x0a000000 },
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 },
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042){ GC_HWIP, 0, 0, 0x063e, 0xf3e777ff, 0x22014042 },
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042){ GC_HWIP, 0, 0, 0x0642, 0xf3e777ff, 0x22014042 },
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0x00003e00, 0x00000400 },
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xff840000, 0x04040000 },
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00030000 },
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0xffff010f, 0x01000107 },
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000){ GC_HWIP, 0, 0, 0x0542, 0x000b0000, 0x000b0000 },
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01000000, 0x01000000 }
571};
572
573static const struct soc15_reg_golden golden_settings_gc_9_1[] =
574{
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 },
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x08000000, 0x08000080 },
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0x08000000, 0x08000080 },
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x08000000, 0x08000080 },
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000420 },
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 },
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x08000000, 0x08000080 },
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 },
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 },
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0x08000000, 0x08000080 },
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0x08000000, 0x08000080 },
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0x08000000, 0x08000080 },
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0x08000000, 0x08000080 },
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0x08000000, 0x08000080 },
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 },
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 },
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00003120 },
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 },
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000000ff },
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x08000000, 0x08000080 },
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 },
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 },
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 }
599};
600
601static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
602{
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 },
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x24000042 },
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x24000042 },
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04048000 },
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000){ GC_HWIP, 0, 1, 0x0293, 0x06000000, 0x06000000 },
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00020000 },
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x00000800 }
610};
611
612static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
613{
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000){ GC_HWIP, 0, 0, 0x0688, 0xff7fffff, 0x04000000 },
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 },
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0xff7fffff, 0x0a000000 },
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x7f0fffff, 0x08000080 },
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0xff8fffff, 0x08000080 },
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x7f8fffff, 0x08000080 },
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x26013041 },
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x26013041 },
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x3f8fffff, 0x08000080 },
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 },
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0xff0fffff, 0x08000080 },
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0xff0fffff, 0x08000080 },
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0xff0fffff, 0x08000080 },
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0xff0fffff, 0x08000080 },
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0xff0fffff, 0x08000080 },
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 },
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00000010 },
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x01000000 },
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x3f8fffff, 0x08000080 },
633};
634
635static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
636{
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 },
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0xff7fffff, 0x0a000000 },
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000400 },
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042){ GC_HWIP, 0, 0, 0x063e, 0xf3e777ff, 0x24000042 },
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042){ GC_HWIP, 0, 0, 0x0642, 0xf3e777ff, 0x24000042 },
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 },
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 },
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 },
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 },
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00003120 },
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc){ GC_HWIP, 0, 0, 0x070c, 0xffffffff, 0x0000cccc },
649};
650
651static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
652{
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff){ GC_HWIP, 0, 0, 0x11b7, 0xffffffff, 0x000001ff },
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000){ GC_HWIP, 0, 1, 0x5a04, 0xffffffff, 0x00000000 },
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382){ GC_HWIP, 0, 1, 0x5a05, 0xffffffff, 0x2544c382 }
656};
657
658static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
659{
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000420 },
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 },
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 },
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 },
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000){ GC_HWIP, 0, 0, 0x030d, 0x00001000, 0x00001000 },
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dc, 0x0007ffff, 0x00000800 },
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dd, 0x0007ffff, 0x00000800 },
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87){ GC_HWIP, 0, 0, 0x11e6, 0x01ffffff, 0x0000ff87 },
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f){ GC_HWIP, 0, 0, 0x11e7, 0x01ffffff, 0x0000ff8f },
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000){ GC_HWIP, 0, 0, 0x0301, 0x03000000, 0x020a2000 },
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 },
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x4a2c0e68 },
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0xb5d3f197 },
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 },
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000003ff }
676};
677
678static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
679{
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080){ GC_HWIP, 0, 0, 0x0688, 0x00000080, 0x04000080 },
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 },
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0x0f000000, 0x0a000000 },
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x24104041 },
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x24104041 },
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 },
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0xffff03ff, 0x01000107 },
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 },
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x76325410 },
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x01000000 },
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 },
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 },
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 }
693};
694
695static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
696{
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x2a114042 },
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x10b0000 },
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e){ GC_HWIP, 0, 0, 0x0b03, 0x3fffffff, 0x346f0a4e },
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca){ GC_HWIP, 0, 0, 0x0b04, 0x3fffffff, 0x1c642ca },
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098){ GC_HWIP, 0, 0, 0x0b09, 0x3fffffff, 0x26f45098 },
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3){ GC_HWIP, 0, 0, 0x0b0a, 0x3fffffff, 0x2ebd9fe3 },
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1){ GC_HWIP, 0, 0, 0x0b0b, 0x3fffffff, 0xb90f5b1 },
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135){ GC_HWIP, 0, 0, 0x0b0c, 0x3ff, 0x135 },
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000){ GC_HWIP, 0, 0, 0x0300, 0xffffffff, 0x011A0000 },
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00){ GC_HWIP, 0, 0, 0x0305, 0xffffffff, 0x00000f00 },
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000){ GC_HWIP, 0, 0, 0x12b5, 0x30000000, 0x30000000 }
708};
709
710static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
711 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)GC_HWIP, 0, 1, 0x2200},
712 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)GC_HWIP, 0, 0, 0x0378},
713};
714
715static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
716{
717 mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
718 mmRLC_SRM_INDEX_CNTL_ADDR_10x4c8c - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
719 mmRLC_SRM_INDEX_CNTL_ADDR_20x4c8d - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
720 mmRLC_SRM_INDEX_CNTL_ADDR_30x4c8e - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
721 mmRLC_SRM_INDEX_CNTL_ADDR_40x4c8f - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
722 mmRLC_SRM_INDEX_CNTL_ADDR_50x4c90 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
723 mmRLC_SRM_INDEX_CNTL_ADDR_60x4c91 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
724 mmRLC_SRM_INDEX_CNTL_ADDR_70x4c92 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b,
725};
726
727static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
728{
729 mmRLC_SRM_INDEX_CNTL_DATA_00x4c93 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
730 mmRLC_SRM_INDEX_CNTL_DATA_10x4c94 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
731 mmRLC_SRM_INDEX_CNTL_DATA_20x4c95 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
732 mmRLC_SRM_INDEX_CNTL_DATA_30x4c96 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
733 mmRLC_SRM_INDEX_CNTL_DATA_40x4c97 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
734 mmRLC_SRM_INDEX_CNTL_DATA_50x4c98 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
735 mmRLC_SRM_INDEX_CNTL_DATA_60x4c99 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
736 mmRLC_SRM_INDEX_CNTL_DATA_70x4c9a - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93,
737};
738
739static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
740{
741 static void *scratch_reg0;
742 static void *scratch_reg1;
743 static void *scratch_reg2;
744 static void *scratch_reg3;
745 static void *spare_int;
746 static uint32_t grbm_cntl;
747 static uint32_t grbm_idx;
748
749 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX1] + mmSCRATCH_REG00x2040)*4;
750 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG10x2041)*4;
751 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG20x2042)*4;
752 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG30x2043)*4;
753 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX1] + mmRLC_SPARE_INT0x4ccc)*4;
754
755 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX0] + mmGRBM_GFX_CNTL0x0022;
756 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX1] + mmGRBM_GFX_INDEX0x2200;
757
758 if (amdgpu_sriov_runtime(adev)((adev)->virt.caps & (1 << 4))) {
759 pr_err("shouldn't call rlcg write register during runtime\n")printk("\0013" "amdgpu: " "shouldn't call rlcg write register during runtime\n"
);
760 return;
761 }
762
763 if (offset == grbm_cntl || offset == grbm_idx) {
764 if (offset == grbm_cntl)
765 writel(v, scratch_reg2)iowrite32(v, scratch_reg2);
766 else if (offset == grbm_idx)
767 writel(v, scratch_reg3)iowrite32(v, scratch_reg3);
768
769 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4))iowrite32(v, ((void *)adev->rmmio) + (offset * 4));
770 } else {
771 uint32_t i = 0;
772 uint32_t retries = 50000;
773
774 writel(v, scratch_reg0)iowrite32(v, scratch_reg0);
775 writel(offset | 0x80000000, scratch_reg1)iowrite32(offset | 0x80000000, scratch_reg1);
776 writel(1, spare_int)iowrite32(1, spare_int);
777 for (i = 0; i < retries; i++) {
778 u32 tmp;
779
780 tmp = readl(scratch_reg1)ioread32(scratch_reg1);
781 if (!(tmp & 0x80000000))
782 break;
783
784 udelay(10);
785 }
786 if (i >= retries)
787 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset)printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, offset);
788 }
789
790}
791
792#define VEGA10_GB_ADDR_CONFIG_GOLDEN0x2a114042 0x2a114042
793#define VEGA12_GB_ADDR_CONFIG_GOLDEN0x24104041 0x24104041
794#define RAVEN_GB_ADDR_CONFIG_GOLDEN0x24000042 0x24000042
795#define RAVEN2_GB_ADDR_CONFIG_GOLDEN0x26013041 0x26013041
796
797static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
798static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
799static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
800static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
801static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
802 struct amdgpu_cu_info *cu_info);
803static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
804static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
805static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
806static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
807 void *ras_error_status);
808static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
809 void *inject_if);
810static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
811
812static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
813 uint64_t queue_mask)
814{
815 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)((3 << 30) | (((0xA0) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
816 amdgpu_ring_write(kiq_ring,
817 PACKET3_SET_RESOURCES_VMID_MASK(0)((0) << 0) |
818 /* vmid_mask:0* queue_type:0 (KIQ) */
819 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)((0) << 29));
820 amdgpu_ring_write(kiq_ring,
821 lower_32_bits(queue_mask)((u32)(queue_mask))); /* queue mask lo */
822 amdgpu_ring_write(kiq_ring,
823 upper_32_bits(queue_mask)((u32)(((queue_mask) >> 16) >> 16))); /* queue mask hi */
824 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
825 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
826 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
827 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
828}
829
830static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
831 struct amdgpu_ring *ring)
832{
833 struct amdgpu_device *adev = kiq_ring->adev;
834 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
835 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
836 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
837
838 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)((3 << 30) | (((0xA2) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
839 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
840 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
841 PACKET3_MAP_QUEUES_QUEUE_SEL(0)((0) << 4) | /* Queue_Sel */
842 PACKET3_MAP_QUEUES_VMID(0)((0) << 8) | /* VMID */
843 PACKET3_MAP_QUEUES_QUEUE(ring->queue)((ring->queue) << 13) |
844 PACKET3_MAP_QUEUES_PIPE(ring->pipe)((ring->pipe) << 16) |
845 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1))(((ring->me == 1 ? 0 : 1)) << 18) |
846 /*queue_type: normal compute queue */
847 PACKET3_MAP_QUEUES_QUEUE_TYPE(0)((0) << 21) |
848 /* alloc format: all_on_one_pipe */
849 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0)((0) << 24) |
850 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
851 /* num_queues: must be 1 */
852 PACKET3_MAP_QUEUES_NUM_QUEUES(1)((1) << 29));
853 amdgpu_ring_write(kiq_ring,
854 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2));
855 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)((u32)(mqd_addr)));
856 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)((u32)(((mqd_addr) >> 16) >> 16)));
857 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)((u32)(wptr_addr)));
858 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)((u32)(((wptr_addr) >> 16) >> 16)));
859}
860
861static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
862 struct amdgpu_ring *ring,
863 enum amdgpu_unmap_queues_action action,
864 u64 gpu_addr, u64 seq)
865{
866 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
867
868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)((3 << 30) | (((0xA3) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
869 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
870 PACKET3_UNMAP_QUEUES_ACTION(action)((action) << 0) |
871 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0)((0) << 4) |
872 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
873 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)((1) << 29));
874 amdgpu_ring_write(kiq_ring,
875 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)((ring->doorbell_index) << 2));
876
877 if (action == PREEMPT_QUEUES_NO_UNMAP) {
878 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
879 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
880 amdgpu_ring_write(kiq_ring, seq);
881 } else {
882 amdgpu_ring_write(kiq_ring, 0);
883 amdgpu_ring_write(kiq_ring, 0);
884 amdgpu_ring_write(kiq_ring, 0);
885 }
886}
887
888static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
889 struct amdgpu_ring *ring,
890 u64 addr,
891 u64 seq)
892{
893 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
894
895 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)((3 << 30) | (((0xA4) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
896 amdgpu_ring_write(kiq_ring,
897 PACKET3_QUERY_STATUS_CONTEXT_ID(0)((0) << 0) |
898 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0)((0) << 28) |
899 PACKET3_QUERY_STATUS_COMMAND(2)((2) << 30));
900 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
901 amdgpu_ring_write(kiq_ring,
902 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2) |
903 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)((eng_sel) << 25));
904 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)((u32)(addr)));
905 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
906 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)((u32)(seq)));
907 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
908}
909
910static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
911 uint16_t pasid, uint32_t flush_type,
912 bool_Bool all_hub)
913{
914 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)((3 << 30) | (((0x98) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
915 amdgpu_ring_write(kiq_ring,
916 PACKET3_INVALIDATE_TLBS_DST_SEL(1)((1) << 0) |
917 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub)((all_hub) << 4) |
918 PACKET3_INVALIDATE_TLBS_PASID(pasid)((pasid) << 5) |
919 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)((flush_type) << 29));
920}
921
922static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {
923 .kiq_set_resources = gfx_v9_0_kiq_set_resources,
924 .kiq_map_queues = gfx_v9_0_kiq_map_queues,
925 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,
926 .kiq_query_status = gfx_v9_0_kiq_query_status,
927 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,
928 .set_resources_size = 8,
929 .map_queues_size = 7,
930 .unmap_queues_size = 6,
931 .query_status_size = 7,
932 .invalidate_tlbs_size = 2,
933};
934
935static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
936{
937 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs;
938}
939
940static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
941{
942 switch (adev->asic_type) {
943 case CHIP_VEGA10:
944 soc15_program_register_sequence(adev,
945 golden_settings_gc_9_0,
946 ARRAY_SIZE(golden_settings_gc_9_0)(sizeof((golden_settings_gc_9_0)) / sizeof((golden_settings_gc_9_0
)[0])));
947 soc15_program_register_sequence(adev,
948 golden_settings_gc_9_0_vg10,
949 ARRAY_SIZE(golden_settings_gc_9_0_vg10)(sizeof((golden_settings_gc_9_0_vg10)) / sizeof((golden_settings_gc_9_0_vg10
)[0])));
950 break;
951 case CHIP_VEGA12:
952 soc15_program_register_sequence(adev,
953 golden_settings_gc_9_2_1,
954 ARRAY_SIZE(golden_settings_gc_9_2_1)(sizeof((golden_settings_gc_9_2_1)) / sizeof((golden_settings_gc_9_2_1
)[0])));
955 soc15_program_register_sequence(adev,
956 golden_settings_gc_9_2_1_vg12,
957 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)(sizeof((golden_settings_gc_9_2_1_vg12)) / sizeof((golden_settings_gc_9_2_1_vg12
)[0])));
958 break;
959 case CHIP_VEGA20:
960 soc15_program_register_sequence(adev,
961 golden_settings_gc_9_0,
962 ARRAY_SIZE(golden_settings_gc_9_0)(sizeof((golden_settings_gc_9_0)) / sizeof((golden_settings_gc_9_0
)[0])));
963 soc15_program_register_sequence(adev,
964 golden_settings_gc_9_0_vg20,
965 ARRAY_SIZE(golden_settings_gc_9_0_vg20)(sizeof((golden_settings_gc_9_0_vg20)) / sizeof((golden_settings_gc_9_0_vg20
)[0])));
966 break;
967 case CHIP_ARCTURUS:
968 soc15_program_register_sequence(adev,
969 golden_settings_gc_9_4_1_arct,
970 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)(sizeof((golden_settings_gc_9_4_1_arct)) / sizeof((golden_settings_gc_9_4_1_arct
)[0])));
971 break;
972 case CHIP_RAVEN:
973 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
974 ARRAY_SIZE(golden_settings_gc_9_1)(sizeof((golden_settings_gc_9_1)) / sizeof((golden_settings_gc_9_1
)[0])));
975 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
976 soc15_program_register_sequence(adev,
977 golden_settings_gc_9_1_rv2,
978 ARRAY_SIZE(golden_settings_gc_9_1_rv2)(sizeof((golden_settings_gc_9_1_rv2)) / sizeof((golden_settings_gc_9_1_rv2
)[0])));
979 else
980 soc15_program_register_sequence(adev,
981 golden_settings_gc_9_1_rv1,
982 ARRAY_SIZE(golden_settings_gc_9_1_rv1)(sizeof((golden_settings_gc_9_1_rv1)) / sizeof((golden_settings_gc_9_1_rv1
)[0])));
983 break;
984 case CHIP_RENOIR:
985 soc15_program_register_sequence(adev,
986 golden_settings_gc_9_1_rn,
987 ARRAY_SIZE(golden_settings_gc_9_1_rn)(sizeof((golden_settings_gc_9_1_rn)) / sizeof((golden_settings_gc_9_1_rn
)[0])));
988 return; /* for renoir, don't need common goldensetting */
989 default:
990 break;
991 }
992
993 if (adev->asic_type != CHIP_ARCTURUS)
994 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
995 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)(sizeof((golden_settings_gc_9_x_common)) / sizeof((golden_settings_gc_9_x_common
)[0])));
996}
997
998static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
999{
1000 adev->gfx.scratch.num_reg = 8;
1001 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040);
1002 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1003}
14
←
Returning without writing to 'adev->gfx.mec2_fw'
→
1004
1005static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
1006 bool_Bool wc, uint32_t reg, uint32_t val)
1007{
1008 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
1009 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel)((eng_sel) << 30) |
1010 WRITE_DATA_DST_SEL(0)((0) << 8) |
1011 (wc ? WR_CONFIRM(1 << 20) : 0));
1012 amdgpu_ring_write(ring, reg);
1013 amdgpu_ring_write(ring, 0);
1014 amdgpu_ring_write(ring, val);
1015}
1016
1017static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
1018 int mem_space, int opt, uint32_t addr0,
1019 uint32_t addr1, uint32_t ref, uint32_t mask,
1020 uint32_t inv)
1021{
1022 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)((3 << 30) | (((0x3C) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
1023 amdgpu_ring_write(ring,
1024 /* memory (1) or register (0) */
1025 (WAIT_REG_MEM_MEM_SPACE(mem_space)((mem_space) << 4) |
1026 WAIT_REG_MEM_OPERATION(opt)((opt) << 6) | /* wait */
1027 WAIT_REG_MEM_FUNCTION(3)((3) << 0) | /* equal */
1028 WAIT_REG_MEM_ENGINE(eng_sel)((eng_sel) << 8)));
1029
1030 if (mem_space)
1031 BUG_ON(addr0 & 0x3)((!(addr0 & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 1031, "!(addr0 & 0x3)")); /* Dword align */
1032 amdgpu_ring_write(ring, addr0);
1033 amdgpu_ring_write(ring, addr1);
1034 amdgpu_ring_write(ring, ref);
1035 amdgpu_ring_write(ring, mask);
1036 amdgpu_ring_write(ring, inv); /* poll interval */
1037}
1038
1039static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
1040{
1041 struct amdgpu_device *adev = ring->adev;
1042 uint32_t scratch;
1043 uint32_t tmp = 0;
1044 unsigned i;
1045 int r;
1046
1047 r = amdgpu_gfx_scratch_get(adev, &scratch);
1048 if (r)
1049 return r;
1050
1051 WREG32(scratch, 0xCAFEDEAD)amdgpu_device_wreg(adev, (scratch), (0xCAFEDEAD), 0);
1052 r = amdgpu_ring_alloc(ring, 3);
1053 if (r)
1054 goto error_free_scratch;
1055
1056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
1057 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START0x0000c000));
1058 amdgpu_ring_write(ring, 0xDEADBEEF);
1059 amdgpu_ring_commit(ring);
1060
1061 for (i = 0; i < adev->usec_timeout; i++) {
1062 tmp = RREG32(scratch)amdgpu_device_rreg(adev, (scratch), 0);
1063 if (tmp == 0xDEADBEEF)
1064 break;
1065 udelay(1);
1066 }
1067
1068 if (i >= adev->usec_timeout)
1069 r = -ETIMEDOUT60;
1070
1071error_free_scratch:
1072 amdgpu_gfx_scratch_free(adev, scratch);
1073 return r;
1074}
1075
1076static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1077{
1078 struct amdgpu_device *adev = ring->adev;
1079 struct amdgpu_ib ib;
1080 struct dma_fence *f = NULL((void *)0);
1081
1082 unsigned index;
1083 uint64_t gpu_addr;
1084 uint32_t tmp;
1085 long r;
1086
1087 r = amdgpu_device_wb_get(adev, &index);
1088 if (r)
1089 return r;
1090
1091 gpu_addr = adev->wb.gpu_addr + (index * 4);
1092 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD));
1093 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
1094 r = amdgpu_ib_get(adev, NULL((void *)0), 16,
1095 AMDGPU_IB_POOL_DIRECT, &ib);
1096 if (r)
1097 goto err1;
1098
1099 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
1100 ib.ptr[1] = WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20);
1101 ib.ptr[2] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
1102 ib.ptr[3] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
1103 ib.ptr[4] = 0xDEADBEEF;
1104 ib.length_dw = 5;
1105
1106 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
1107 if (r)
1108 goto err2;
1109
1110 r = dma_fence_wait_timeout(f, false0, timeout);
1111 if (r == 0) {
1112 r = -ETIMEDOUT60;
1113 goto err2;
1114 } else if (r < 0) {
1115 goto err2;
1116 }
1117
1118 tmp = adev->wb.wb[index];
1119 if (tmp == 0xDEADBEEF)
1120 r = 0;
1121 else
1122 r = -EINVAL22;
1123
1124err2:
1125 amdgpu_ib_free(adev, &ib, NULL((void *)0));
1126 dma_fence_put(f);
1127err1:
1128 amdgpu_device_wb_free(adev, index);
1129 return r;
1130}
1131
1132
1133static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
1134{
1135 release_firmware(adev->gfx.pfp_fw);
1136 adev->gfx.pfp_fw = NULL((void *)0);
1137 release_firmware(adev->gfx.me_fw);
1138 adev->gfx.me_fw = NULL((void *)0);
1139 release_firmware(adev->gfx.ce_fw);
1140 adev->gfx.ce_fw = NULL((void *)0);
1141 release_firmware(adev->gfx.rlc_fw);
1142 adev->gfx.rlc_fw = NULL((void *)0);
1143 release_firmware(adev->gfx.mec_fw);
1144 adev->gfx.mec_fw = NULL((void *)0);
1145 release_firmware(adev->gfx.mec2_fw);
1146 adev->gfx.mec2_fw = NULL((void *)0);
1147
1148 kfree(adev->gfx.rlc.register_list_format);
1149}
1150
1151static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
1152{
1153 const struct rlc_firmware_header_v2_1 *rlc_hdr;
1154
1155 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1156 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_cntl_ucode_ver));
1157 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_cntl_feature_ver)
);
1158 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_cntl_size_bytes));
1159 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_cntl_offset_bytes
));
1160 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_gpm_ucode_ver));
1161 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_gpm_feature_ver));
1162 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_gpm_size_bytes));
1163 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_gpm_offset_bytes)
);
1164 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_srm_ucode_ver));
1165 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_srm_feature_ver));
1166 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_srm_size_bytes));
1167 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_srm_offset_bytes)
);
1168 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
1169 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length)((__uint32_t)(rlc_hdr->reg_list_format_direct_reg_list_length
));
1170}
1171
1172static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
1173{
1174 adev->gfx.me_fw_write_wait = false0;
1175 adev->gfx.mec_fw_write_wait = false0;
1176
1177 if ((adev->asic_type != CHIP_ARCTURUS) &&
1178 ((adev->gfx.mec_fw_version < 0x000001a5) ||
1179 (adev->gfx.mec_feature_version < 46) ||
1180 (adev->gfx.pfp_fw_version < 0x000000b7) ||
1181 (adev->gfx.pfp_feature_version < 46)))
1182 DRM_WARN_ONCE("CP firmware version too old, please update!")({ static int __warned; if (!__warned) { printk("\0014" "[" "drm"
"] " "CP firmware version too old, please update!"); __warned
= 1; } });
1183
1184 switch (adev->asic_type) {
1185 case CHIP_VEGA10:
1186 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1187 (adev->gfx.me_feature_version >= 42) &&
1188 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1189 (adev->gfx.pfp_feature_version >= 42))
1190 adev->gfx.me_fw_write_wait = true1;
1191
1192 if ((adev->gfx.mec_fw_version >= 0x00000193) &&
1193 (adev->gfx.mec_feature_version >= 42))
1194 adev->gfx.mec_fw_write_wait = true1;
1195 break;
1196 case CHIP_VEGA12:
1197 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1198 (adev->gfx.me_feature_version >= 44) &&
1199 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1200 (adev->gfx.pfp_feature_version >= 44))
1201 adev->gfx.me_fw_write_wait = true1;
1202
1203 if ((adev->gfx.mec_fw_version >= 0x00000196) &&
1204 (adev->gfx.mec_feature_version >= 44))
1205 adev->gfx.mec_fw_write_wait = true1;
1206 break;
1207 case CHIP_VEGA20:
1208 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1209 (adev->gfx.me_feature_version >= 44) &&
1210 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1211 (adev->gfx.pfp_feature_version >= 44))
1212 adev->gfx.me_fw_write_wait = true1;
1213
1214 if ((adev->gfx.mec_fw_version >= 0x00000197) &&
1215 (adev->gfx.mec_feature_version >= 44))
1216 adev->gfx.mec_fw_write_wait = true1;
1217 break;
1218 case CHIP_RAVEN:
1219 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1220 (adev->gfx.me_feature_version >= 42) &&
1221 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1222 (adev->gfx.pfp_feature_version >= 42))
1223 adev->gfx.me_fw_write_wait = true1;
1224
1225 if ((adev->gfx.mec_fw_version >= 0x00000192) &&
1226 (adev->gfx.mec_feature_version >= 42))
1227 adev->gfx.mec_fw_write_wait = true1;
1228 break;
1229 default:
1230 adev->gfx.me_fw_write_wait = true1;
1231 adev->gfx.mec_fw_write_wait = true1;
1232 break;
1233 }
1234}
1235
1236struct amdgpu_gfxoff_quirk {
1237 u16 chip_vendor;
1238 u16 chip_device;
1239 u16 subsys_vendor;
1240 u16 subsys_device;
1241 u8 revision;
1242};
1243
1244static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
1245 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */
1246 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1247 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
1248 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
1249 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
1250 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
1251 { 0, 0, 0, 0, 0 },
1252};
1253
1254static bool_Bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
1255{
1256 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list;
1257
1258 while (p && p->chip_device != 0) {
1259 if (pdev->vendor == p->chip_vendor &&
1260 pdev->device == p->chip_device &&
1261 pdev->subsystem_vendor == p->subsys_vendor &&
1262 pdev->subsystem_device == p->subsys_device &&
1263 pdev->revision == p->revision) {
1264 return true1;
1265 }
1266 ++p;
1267 }
1268 return false0;
1269}
1270
1271static bool_Bool is_raven_kicker(struct amdgpu_device *adev)
1272{
1273 if (adev->pm.fw_version >= 0x41e2b)
1274 return true1;
1275 else
1276 return false0;
1277}
1278
1279static bool_Bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
1280{
1281 if ((adev->asic_type == CHIP_RENOIR) &&
1282 (adev->gfx.me_fw_version >= 0x000000a5) &&
1283 (adev->gfx.me_feature_version >= 52))
1284 return true1;
1285 else
1286 return false0;
1287}
1288
1289static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
1290{
1291 if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
1292 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1293
1294 switch (adev->asic_type) {
1295 case CHIP_VEGA10:
1296 case CHIP_VEGA12:
1297 case CHIP_VEGA20:
1298 break;
1299 case CHIP_RAVEN:
1300 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1301 (adev->apu_flags & AMD_APU_IS_PICASSO)) &&
1302 ((!is_raven_kicker(adev) &&
1303 adev->gfx.rlc_fw_version < 531) ||
1304 (adev->gfx.rlc_feature_version < 1) ||
1305 !adev->gfx.rlc.is_rlc_v2_1))
1306 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1307
1308 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1309 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG(1 << 0) |
1310 AMD_PG_SUPPORT_CP(1 << 5) |
1311 AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7);
1312 break;
1313 case CHIP_RENOIR:
1314 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1315 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG(1 << 0) |
1316 AMD_PG_SUPPORT_CP(1 << 5) |
1317 AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7);
1318 break;
1319 default:
1320 break;
1321 }
1322}
1323
1324static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
1325 const char *chip_name)
1326{
1327 char fw_name[30];
1328 int err;
1329 struct amdgpu_firmware_info *info = NULL((void *)0);
1330 const struct common_firmware_header *header = NULL((void *)0);
1331 const struct gfx_firmware_header_v1_0 *cp_hdr;
1332
1333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1334 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1335 if (err)
1336 goto out;
1337 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1338 if (err)
1339 goto out;
1340 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1341 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
1342 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
1343
1344 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1345 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1346 if (err)
1347 goto out;
1348 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1349 if (err)
1350 goto out;
1351 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1352 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
1353 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
1354
1355 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1356 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1357 if (err)
1358 goto out;
1359 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1360 if (err)
1361 goto out;
1362 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1363 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
1364 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
1365
1366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1367 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1368 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1369 info->fw = adev->gfx.pfp_fw;
1370 header = (const struct common_firmware_header *)info->fw->data;
1371 adev->firmware.fw_size +=
1372 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
1373
1374 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1375 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1376 info->fw = adev->gfx.me_fw;
1377 header = (const struct common_firmware_header *)info->fw->data;
1378 adev->firmware.fw_size +=
1379 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
1380
1381 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1382 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1383 info->fw = adev->gfx.ce_fw;
1384 header = (const struct common_firmware_header *)info->fw->data;
1385 adev->firmware.fw_size +=
1386 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
1387 }
1388
1389out:
1390 if (err) {
1391 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1392 "gfx9: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1393 fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
1394 release_firmware(adev->gfx.pfp_fw);
1395 adev->gfx.pfp_fw = NULL((void *)0);
1396 release_firmware(adev->gfx.me_fw);
1397 adev->gfx.me_fw = NULL((void *)0);
1398 release_firmware(adev->gfx.ce_fw);
1399 adev->gfx.ce_fw = NULL((void *)0);
1400 }
1401 return err;
1402}
1403
1404static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
1405 const char *chip_name)
1406{
1407 char fw_name[30];
1408 int err;
1409 struct amdgpu_firmware_info *info = NULL((void *)0);
1410 const struct common_firmware_header *header = NULL((void *)0);
1411 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1412 unsigned int *tmp = NULL((void *)0);
1413 unsigned int i = 0;
1414 uint16_t version_major;
1415 uint16_t version_minor;
1416 uint32_t smu_version;
1417
1418 /*
1419 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
1420 * instead of picasso_rlc.bin.
1421 * Judgment method:
1422 * PCO AM4: revision >= 0xC8 && revision <= 0xCF
1423 * or revision >= 0xD8 && revision <= 0xDF
1424 * otherwise is PCO FP5
1425 */
1426 if (!strcmp(chip_name, "picasso") &&
1427 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
1428 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
1429 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
1430 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
1431 (smu_version >= 0x41e2b))
1432 /**
1433 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
1434 */
1435 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
1436 else
1437 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1438 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1439 if (err)
1440 goto out;
1441 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1442 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1443
1444 version_major = le16_to_cpu(rlc_hdr->header.header_version_major)((__uint16_t)(rlc_hdr->header.header_version_major));
1445 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor)((__uint16_t)(rlc_hdr->header.header_version_minor));
1446 if (version_major == 2 && version_minor == 1)
1447 adev->gfx.rlc.is_rlc_v2_1 = true1;
1448
1449 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version)((__uint32_t)(rlc_hdr->header.ucode_version));
1450 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version)((__uint32_t)(rlc_hdr->ucode_feature_version));
1451 adev->gfx.rlc.save_and_restore_offset =
1452 le32_to_cpu(rlc_hdr->save_and_restore_offset)((__uint32_t)(rlc_hdr->save_and_restore_offset));
1453 adev->gfx.rlc.clear_state_descriptor_offset =
1454 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)((__uint32_t)(rlc_hdr->clear_state_descriptor_offset));
1455 adev->gfx.rlc.avail_scratch_ram_locations =
1456 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)((__uint32_t)(rlc_hdr->avail_scratch_ram_locations));
1457 adev->gfx.rlc.reg_restore_list_size =
1458 le32_to_cpu(rlc_hdr->reg_restore_list_size)((__uint32_t)(rlc_hdr->reg_restore_list_size));
1459 adev->gfx.rlc.reg_list_format_start =
1460 le32_to_cpu(rlc_hdr->reg_list_format_start)((__uint32_t)(rlc_hdr->reg_list_format_start));
1461 adev->gfx.rlc.reg_list_format_separate_start =
1462 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)((__uint32_t)(rlc_hdr->reg_list_format_separate_start));
1463 adev->gfx.rlc.starting_offsets_start =
1464 le32_to_cpu(rlc_hdr->starting_offsets_start)((__uint32_t)(rlc_hdr->starting_offsets_start));
1465 adev->gfx.rlc.reg_list_format_size_bytes =
1466 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)((__uint32_t)(rlc_hdr->reg_list_format_size_bytes));
1467 adev->gfx.rlc.reg_list_size_bytes =
1468 le32_to_cpu(rlc_hdr->reg_list_size_bytes)((__uint32_t)(rlc_hdr->reg_list_size_bytes));
1469 adev->gfx.rlc.register_list_format =
1470 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1471 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL(0x0001 | 0x0004));
1472 if (!adev->gfx.rlc.register_list_format) {
1473 err = -ENOMEM12;
1474 goto out;
1475 }
1476
1477 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1478 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_format_array_offset_bytes)
));
1479 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1480 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i]));
1481
1482 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1483
1484 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1485 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_array_offset_bytes)));
1486 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1487 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i]));
1488
1489 if (adev->gfx.rlc.is_rlc_v2_1)
1490 gfx_v9_0_init_rlc_ext_microcode(adev);
1491
1492 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1493 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1494 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1495 info->fw = adev->gfx.rlc_fw;
1496 header = (const struct common_firmware_header *)info->fw->data;
1497 adev->firmware.fw_size +=
1498 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
1499
1500 if (adev->gfx.rlc.is_rlc_v2_1 &&
1501 adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
1502 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
1503 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
1504 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
1505 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
1506 info->fw = adev->gfx.rlc_fw;
1507 adev->firmware.fw_size +=
1508 roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_cntl_size_bytes) + (((1
<< 12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_cntl_size_bytes
))((1 << 12)) - 1)));
1509
1510 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
1511 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
1512 info->fw = adev->gfx.rlc_fw;
1513 adev->firmware.fw_size +=
1514 roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_gpm_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_gpm_size_bytes
))((1 << 12)) - 1)));
1515
1516 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
1517 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
1518 info->fw = adev->gfx.rlc_fw;
1519 adev->firmware.fw_size +=
1520 roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_srm_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_srm_size_bytes
))((1 << 12)) - 1)));
1521 }
1522 }
1523
1524out:
1525 if (err) {
1526 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1527 "gfx9: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1528 fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
1529 release_firmware(adev->gfx.rlc_fw);
1530 adev->gfx.rlc_fw = NULL((void *)0);
1531 }
1532 return err;
1533}
1534
1535static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
1536 const char *chip_name)
1537{
1538 char fw_name[30];
1539 int err;
1540 struct amdgpu_firmware_info *info = NULL((void *)0);
1541 const struct common_firmware_header *header = NULL((void *)0);
1542 const struct gfx_firmware_header_v1_0 *cp_hdr;
1543
1544 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1545 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
23
←
Calling 'request_firmware'
→
27
←
Returning from 'request_firmware'
→
1546 if (err
27.1
'err' is 0
27.1
'err' is 0
)
28
←
Taking false branch
→
1547 goto out;
1548 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1549 if (err)
29
←
Assuming 'err' is 0
→
30
←
Taking false branch
→
1550 goto out;
1551 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1552 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
1553 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
1554
1555
1556 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1557 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
31
←
Calling 'request_firmware'
→
35
←
Returning from 'request_firmware'
→
1558 if (!err) {
36
←
Assuming 'err' is 0
→
37
←
Taking true branch
→
1559 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1560 if (err)
38
←
Assuming 'err' is 0
→
39
←
Taking false branch
→
1561 goto out;
1562 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1563 adev->gfx.mec2_fw->data;
40
←
Access to field 'data' results in a dereference of a null pointer (loaded from field 'mec2_fw')
1564 adev->gfx.mec2_fw_version =
1565 le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
1566 adev->gfx.mec2_feature_version =
1567 le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
1568 } else {
1569 err = 0;
1570 adev->gfx.mec2_fw = NULL((void *)0);
1571 }
1572
1573 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1574 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1575 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1576 info->fw = adev->gfx.mec_fw;
1577 header = (const struct common_firmware_header *)info->fw->data;
1578 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1579 adev->firmware.fw_size +=
1580 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)));
1581
1582 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
1583 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
1584 info->fw = adev->gfx.mec_fw;
1585 adev->firmware.fw_size +=
1586 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE)(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)));
1587
1588 if (adev->gfx.mec2_fw) {
1589 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1590 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1591 info->fw = adev->gfx.mec2_fw;
1592 header = (const struct common_firmware_header *)info->fw->data;
1593 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1594 adev->firmware.fw_size +=
1595 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)));
1596
1597 /* TODO: Determine if MEC2 JT FW loading can be removed
1598 for all GFX V9 asic and above */
1599 if (adev->asic_type != CHIP_ARCTURUS &&
1600 adev->asic_type != CHIP_RENOIR) {
1601 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
1602 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
1603 info->fw = adev->gfx.mec2_fw;
1604 adev->firmware.fw_size +=
1605 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4,(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)))
1606 PAGE_SIZE)(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)));
1607 }
1608 }
1609 }
1610
1611out:
1612 gfx_v9_0_check_if_need_gfxoff(adev);
1613 gfx_v9_0_check_fw_write_wait(adev);
1614 if (err) {
1615 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1616 "gfx9: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
1617 fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
1618 release_firmware(adev->gfx.mec_fw);
1619 adev->gfx.mec_fw = NULL((void *)0);
1620 release_firmware(adev->gfx.mec2_fw);
1621 adev->gfx.mec2_fw = NULL((void *)0);
1622 }
1623 return err;
1624}
1625
1626static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
1627{
1628 const char *chip_name;
1629 int r;
1630
1631 DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");
1632
1633 switch (adev->asic_type) {
17
←
Control jumps to 'case CHIP_ARCTURUS:' at line 1651
→
1634 case CHIP_VEGA10:
1635 chip_name = "vega10";
1636 break;
1637 case CHIP_VEGA12:
1638 chip_name = "vega12";
1639 break;
1640 case CHIP_VEGA20:
1641 chip_name = "vega20";
1642 break;
1643 case CHIP_RAVEN:
1644 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1645 chip_name = "raven2";
1646 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1647 chip_name = "picasso";
1648 else
1649 chip_name = "raven";
1650 break;
1651 case CHIP_ARCTURUS:
1652 chip_name = "arcturus";
1653 break;
18
←
 Execution continues on line 1665
→
1654 case CHIP_RENOIR:
1655 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1656 chip_name = "renoir";
1657 else
1658 chip_name = "green_sardine";
1659 break;
1660 default:
1661 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 1661); } while (0);
1662 }
1663
1664 /* No CPG in Arcturus */
1665 if (adev->asic_type
18.1
Field 'asic_type' is equal to CHIP_ARCTURUS
18.1
Field 'asic_type' is equal to CHIP_ARCTURUS
 != CHIP_ARCTURUS) {
19
←
Taking false branch
→
1666 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
1667 if (r)
1668 return r;
1669 }
1670
1671 r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
1672 if (r)
20
←
Assuming 'r' is 0
→
21
←
Taking false branch
→
1673 return r;
1674
1675 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
22
←
Calling 'gfx_v9_0_init_cp_compute_microcode'
→
1676 if (r)
1677 return r;
1678
1679 return r;
1680}
1681
1682static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1683{
1684 u32 count = 0;
1685 const struct cs_section_def *sect = NULL((void *)0);
1686 const struct cs_extent_def *ext = NULL((void *)0);
1687
1688 /* begin clear state */
1689 count += 2;
1690 /* context control state */
1691 count += 3;
1692
1693 for (sect = gfx9_cs_data; sect->section != NULL((void *)0); ++sect) {
1694 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
1695 if (sect->id == SECT_CONTEXT)
1696 count += 2 + ext->reg_count;
1697 else
1698 return 0;
1699 }
1700 }
1701
1702 /* end clear state */
1703 count += 2;
1704 /* clear state */
1705 count += 2;
1706
1707 return count;
1708}
1709
1710static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
1711 volatile u32 *buffer)
1712{
1713 u32 count = 0, i;
1714 const struct cs_section_def *sect = NULL((void *)0);
1715 const struct cs_extent_def *ext = NULL((void *)0);
1716
1717 if (adev->gfx.rlc.cs_data == NULL((void *)0))
1718 return;
1719 if (buffer == NULL((void *)0))
1720 return;
1721
1722 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
1723 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE)((__uint32_t)((2 << 28)));
1724
1725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1))((__uint32_t)(((3 << 30) | (((0x28) & 0xFF) <<
8) | ((1) & 0x3FFF) << 16)));
1726 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
1727 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
1728
1729 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL((void *)0); ++sect) {
1730 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
1731 if (sect->id == SECT_CONTEXT) {
1732 buffer[count++] =
1733 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) <<
8) | ((ext->reg_count) & 0x3FFF) << 16)));
1734 buffer[count++] = cpu_to_le32(ext->reg_index -((__uint32_t)(ext->reg_index - 0x0000a000))
1735 PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(ext->reg_index - 0x0000a000));
1736 for (i = 0; i < ext->reg_count; i++)
1737 buffer[count++] = cpu_to_le32(ext->extent[i])((__uint32_t)(ext->extent[i]));
1738 } else {
1739 return;
1740 }
1741 }
1742 }
1743
1744 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
1745 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE)((__uint32_t)((3 << 28)));
1746
1747 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0))((__uint32_t)(((3 << 30) | (((0x12) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
1748 buffer[count++] = cpu_to_le32(0)((__uint32_t)(0));
1749}
1750
1751static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
1752{
1753 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1754 uint32_t pg_always_on_cu_num = 2;
1755 uint32_t always_on_cu_num;
1756 uint32_t i, j, k;
1757 uint32_t mask, cu_bitmap, counter;
1758
1759 if (adev->flags & AMD_IS_APU)
1760 always_on_cu_num = 4;
1761 else if (adev->asic_type == CHIP_VEGA12)
1762 always_on_cu_num = 8;
1763 else
1764 always_on_cu_num = 12;
1765
1766 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
1767 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1768 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1769 mask = 1;
1770 cu_bitmap = 0;
1771 counter = 0;
1772 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1773
1774 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1775 if (cu_info->bitmap[i][j] & mask) {
1776 if (counter == pg_always_on_cu_num)
1777 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c53)), (cu_bitmap), 0);
1778 if (counter < always_on_cu_num)
1779 cu_bitmap |= mask;
1780 else
1781 break;
1782 counter++;
1783 }
1784 mask <<= 1;
1785 }
1786
1787 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c50)), (cu_bitmap), 0);
1788 cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
1789 }
1790 }
1791 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1792 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
1793}
1794
1795static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
1796{
1797 uint32_t data;
1798
1799 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1800 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cbf)), (0x0000007F), 0);
1801 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cb8)), (0x0333A5A7), 0);
1802 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cb9)), (0x00000077), 0);
1803 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cba)), ((0x30 | 0x40 << 8 | 0x02FA << 16)),
0);
1804
1805 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1806 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1b)), (0x00000000), 0);
1807
1808 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1809 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c12)), (0x00000500), 0);
1810
1811 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
1812 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1813 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1814 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c4f)), (0xffffffff), 0);
1815
1816 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1817 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003)(((0) & ~0x000000FEL) | (0x000000FEL & ((0x0003) <<
0x1)));
1818 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((0x0010) <<
0x8)));
1819 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F)(((data) & ~0xFFFF0000L) | (0xFFFF0000L & ((0x033F) <<
0x10)));
1820 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c51)), (data), 0);
1821
1822 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1823 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c6a), 0);
1824 data &= 0x0000FFFF;
1825 data |= 0x00C00000;
1826 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6a)), (data), 0);
1827
1828 /*
1829 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1830 * programmed in gfx_v9_0_init_always_on_cu_mask()
1831 */
1832
1833 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1834 * but used for RLC_LB_CNTL configuration */
1835 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK0x00000004L;
1836 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09)(((data) & ~0x00000FF0L) | (0x00000FF0L & ((0x09) <<
0x4)));
1837 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000)(((data) & ~0xFFFFF000L) | (0xFFFFF000L & ((0x80000) <<
0xc)));
1838 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c19)), (data), 0);
1839 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
1840
1841 gfx_v9_0_init_always_on_cu_mask(adev);
1842}
1843
1844static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1845{
1846 uint32_t data;
1847
1848 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1849 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cbf)), (0x0000007F), 0);
1850 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cb8)), (0x033388F8), 0);
1851 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cb9)), (0x00000077), 0);
1852 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cba)), ((0x10 | 0x27 << 8 | 0x02FA << 16)),
0);
1853
1854 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1855 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1b)), (0x00000000), 0);
1856
1857 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1858 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c12)), (0x00000800), 0);
1859
1860 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
1861 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1862 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1863 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c4f)), (0xffffffff), 0);
1864
1865 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1866 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003)(((0) & ~0x000000FEL) | (0x000000FEL & ((0x0003) <<
0x1)));
1867 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((0x0010) <<
0x8)));
1868 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F)(((data) & ~0xFFFF0000L) | (0xFFFF0000L & ((0x033F) <<
0x10)));
1869 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c51)), (data), 0);
1870
1871 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1872 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c6a), 0);
1873 data &= 0x0000FFFF;
1874 data |= 0x00C00000;
1875 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6a)), (data), 0);
1876
1877 /*
1878 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1879 * programmed in gfx_v9_0_init_always_on_cu_mask()
1880 */
1881
1882 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1883 * but used for RLC_LB_CNTL configuration */
1884 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK0x00000004L;
1885 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09)(((data) & ~0x00000FF0L) | (0x00000FF0L & ((0x09) <<
0x4)));
1886 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000)(((data) & ~0xFFFFF000L) | (0xFFFFF000L & ((0x80000) <<
0xc)));
1887 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c19)), (data), 0);
1888 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
1889
1890 gfx_v9_0_init_always_on_cu_mask(adev);
1891}
1892
1893static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool_Bool enable)
1894{
1895 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c19), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][1] + 0x4c19), 0) & ~0x00000001L) | (enable ? 1 : 0) <<
0x0), 0);
1896}
1897
1898static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1899{
1900 return 5;
1901}
1902
1903static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1904{
1905 const struct cs_section_def *cs_data;
1906 int r;
1907
1908 adev->gfx.rlc.cs_data = gfx9_cs_data;
1909
1910 cs_data = adev->gfx.rlc.cs_data;
1911
1912 if (cs_data) {
1913 /* init clear state block */
1914 r = amdgpu_gfx_rlc_init_csb(adev);
1915 if (r)
1916 return r;
1917 }
1918
1919 if (adev->flags & AMD_IS_APU) {
1920 /* TODO: double check the cp_table_size for RV */
1921 adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048)(((96 * 5 * 4) + ((2048) - 1)) & (~((__typeof(96 * 5 * 4)
)(2048) - 1))) + (64 * 1024); /* JT + GDS */
1922 r = amdgpu_gfx_rlc_init_cpt(adev);
1923 if (r)
1924 return r;
1925 }
1926
1927 switch (adev->asic_type) {
1928 case CHIP_RAVEN:
1929 gfx_v9_0_init_lbpw(adev);
1930 break;
1931 case CHIP_VEGA20:
1932 gfx_v9_4_init_lbpw(adev);
1933 break;
1934 default:
1935 break;
1936 }
1937
1938 /* init spm vmid with 0xf */
1939 if (adev->gfx.rlc.funcs->update_spm_vmid)
1940 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1941
1942 return 0;
1943}
1944
1945static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1946{
1947 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL((void *)0), NULL((void *)0));
1948 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL((void *)0), NULL((void *)0));
1949}
1950
1951static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1952{
1953 int r;
1954 u32 *hpd;
1955 const __le32 *fw_data;
1956 unsigned fw_size;
1957 u32 *fw;
1958 size_t mec_hpd_size;
1959
1960 const struct gfx_firmware_header_v1_0 *mec_hdr;
1961
1962 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES128);
1963
1964 /* take ownership of the relevant compute queues */
1965 amdgpu_gfx_compute_queue_acquire(adev);
1966 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE4096;
1967 if (mec_hpd_size) {
1968 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE(1 << 12),
1969 AMDGPU_GEM_DOMAIN_VRAM0x4,
1970 &adev->gfx.mec.hpd_eop_obj,
1971 &adev->gfx.mec.hpd_eop_gpu_addr,
1972 (void **)&hpd);
1973 if (r) {
1974 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create HDP EOP bo failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1975 gfx_v9_0_mec_fini(adev);
1976 return r;
1977 }
1978
1979 memset(hpd, 0, mec_hpd_size)__builtin_memset((hpd), (0), (mec_hpd_size));
1980
1981 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1982 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1983 }
1984
1985 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1986
1987 fw_data = (const __le32 *)
1988 (adev->gfx.mec_fw->data +
1989 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
1990 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes)((__uint32_t)(mec_hdr->header.ucode_size_bytes));
1991
1992 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1993 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
1994 &adev->gfx.mec.mec_fw_obj,
1995 &adev->gfx.mec.mec_fw_gpu_addr,
1996 (void **)&fw);
1997 if (r) {
1998 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create mec firmware bo failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1999 gfx_v9_0_mec_fini(adev);
2000 return r;
2001 }
2002
2003 memcpy(fw, fw_data, fw_size)__builtin_memcpy((fw), (fw_data), (fw_size));
2004
2005 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2006 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2007
2008 return 0;
2009}
2010
2011static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2012{
2013 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (address
<< 0x10) | (0x00002000L)), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), ((wave <<
0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L
)), 0); } } while (0); } while (0)
2014 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (address
<< 0x10) | (0x00002000L)), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), ((wave <<
0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L
)), 0); } } while (0); } while (0)
2015 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (address
<< 0x10) | (0x00002000L)), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), ((wave <<
0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L
)), 0); } } while (0); } while (0)
2016 (address << SQ_IND_INDEX__INDEX__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (address
<< 0x10) | (0x00002000L)), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), ((wave <<
0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L
)), 0); } } while (0); } while (0)
2017 (SQ_IND_INDEX__FORCE_READ_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (address
<< 0x10) | (0x00002000L)), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), ((wave <<
0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L
)), 0); } } while (0); } while (0);
2018 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0379), 0);
2019}
2020
2021static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2022 uint32_t wave, uint32_t thread,
2023 uint32_t regno, uint32_t num, uint32_t *out)
2024{
2025 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2026 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2027 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2028 (regno << SQ_IND_INDEX__INDEX__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2029 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2030 (SQ_IND_INDEX__FORCE_READ_MASK) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0)
2031 (SQ_IND_INDEX__AUTO_INCR_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0378; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((wave << 0x0) | (simd << 0x4) | (regno
<< 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((wave << 0x0) | (simd << 0x4) | (regno <<
0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L
)), 0); } } while (0); } while (0);
2032 while (num--)
2033 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0379), 0);
2034}
2035
2036static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2037{
2038 /* type 1 wave data */
2039 dst[(*no_fields)++] = 1;
2040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS0x0012);
2041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO0x0018);
2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI0x0019);
2043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO0x027e);
2044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI0x027f);
2045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID0x0014);
2046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW00x001a);
2047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW10x001b);
2048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC0x0015);
2049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC0x0016);
2050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS0x0013);
2051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS0x0017);
2052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG00x001c);
2053 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M00x027c);
2054}
2055
2056static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
2057 uint32_t wave, uint32_t start,
2058 uint32_t size, uint32_t *dst)
2059{
2060 wave_read_regs(
2061 adev, simd, wave, 0,
2062 start + SQIND_WAVE_SGPRS_OFFSET0x00000200, size, dst);
2063}
2064
2065static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
2066 uint32_t wave, uint32_t thread,
2067 uint32_t start, uint32_t size,
2068 uint32_t *dst)
2069{
2070 wave_read_regs(
2071 adev, simd, wave, thread,
2072 start + SQIND_WAVE_VGPRS_OFFSET0x00000400, size, dst);
2073}
2074
2075static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
2076 u32 me, u32 pipe, u32 q, u32 vm)
2077{
2078 soc15_grbm_select(adev, me, pipe, q, vm);
2079}
2080
2081static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
2082 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
2083 .select_se_sh = &gfx_v9_0_select_se_sh,
2084 .read_wave_data = &gfx_v9_0_read_wave_data,
2085 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
2086 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
2087 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
2088 .ras_error_inject = &gfx_v9_0_ras_error_inject,
2089 .query_ras_error_count = &gfx_v9_0_query_ras_error_count,
2090 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,
2091};
2092
2093static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = {
2094 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
2095 .select_se_sh = &gfx_v9_0_select_se_sh,
2096 .read_wave_data = &gfx_v9_0_read_wave_data,
2097 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
2098 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
2099 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
2100 .ras_error_inject = &gfx_v9_4_ras_error_inject,
2101 .query_ras_error_count = &gfx_v9_4_query_ras_error_count,
2102 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
2103 .query_ras_error_status = &gfx_v9_4_query_ras_error_status,
2104};
2105
2106static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
2107{
2108 u32 gb_addr_config;
2109 int err;
2110
2111 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
2112
2113 switch (adev->asic_type) {
2114 case CHIP_VEGA10:
2115 adev->gfx.config.max_hw_contexts = 8;
2116 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2117 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2118 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2119 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2120 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN0x2a114042;
2121 break;
2122 case CHIP_VEGA12:
2123 adev->gfx.config.max_hw_contexts = 8;
2124 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2125 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2126 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2127 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2128 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN0x24104041;
2129 DRM_INFO("fix gfx.config for vega12\n")printk("\0016" "[" "drm" "] " "fix gfx.config for vega12\n");
2130 break;
2131 case CHIP_VEGA20:
2132 adev->gfx.config.max_hw_contexts = 8;
2133 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2134 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2135 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2136 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2137 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x063e), 0);
2138 gb_addr_config &= ~0xf3e777ff;
2139 gb_addr_config |= 0x22014042;
2140 /* check vbios table if gpu info is not available */
2141 err = amdgpu_atomfirmware_get_gfx_info(adev);
2142 if (err)
2143 return err;
2144 break;
2145 case CHIP_RAVEN:
2146 adev->gfx.config.max_hw_contexts = 8;
2147 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2148 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2149 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2150 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2151 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2152 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN0x26013041;
2153 else
2154 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN0x24000042;
2155 break;
2156 case CHIP_ARCTURUS:
2157 adev->gfx.funcs = &gfx_v9_4_gfx_funcs;
2158 adev->gfx.config.max_hw_contexts = 8;
2159 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2160 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2161 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2162 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2163 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x063e), 0);
2164 gb_addr_config &= ~0xf3e777ff;
2165 gb_addr_config |= 0x22014042;
2166 break;
2167 case CHIP_RENOIR:
2168 adev->gfx.config.max_hw_contexts = 8;
2169 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2170 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2171 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
2172 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2173 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x063e), 0);
2174 gb_addr_config &= ~0xf3e777ff;
2175 gb_addr_config |= 0x22010042;
2176 break;
2177 default:
2178 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 2178); } while (0);
2179 break;
2180 }
2181
2182 adev->gfx.config.gb_addr_config = gb_addr_config;
2183
2184 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
2185 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0)
2186 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0)
2187 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0)
2188 NUM_PIPES)(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0);
2189
2190 adev->gfx.config.max_tile_pipes =
2191 adev->gfx.config.gb_addr_config_fields.num_pipes;
2192
2193 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
2194 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00007000L) >>
0xc)
2195 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00007000L) >>
0xc)
2196 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00007000L) >>
0xc)
2197 NUM_BANKS)(((adev->gfx.config.gb_addr_config) & 0x00007000L) >>
0xc);
2198 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
2199 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6)
2200 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6)
2201 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6)
2202 MAX_COMPRESSED_FRAGS)(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6);
2203 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
2204 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a)
2205 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a)
2206 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a)
2207 NUM_RB_PER_SE)(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a);
2208 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
2209 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13)
2210 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13)
2211 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13)
2212 NUM_SHADER_ENGINES)(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13);
2213 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
2214 REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3)
2215 adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3)
2216 GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3)
2217 PIPE_INTERLEAVE_SIZE)(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3));
2218
2219 return 0;
2220}
2221
2222static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
2223 int mec, int pipe, int queue)
2224{
2225 unsigned irq_type;
2226 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
2227 unsigned int hw_prio;
2228
2229 ring = &adev->gfx.compute_ring[ring_id];
2230
2231 /* mec0 is me1 */
2232 ring->me = mec + 1;
2233 ring->pipe = pipe;
2234 ring->queue = queue;
2235
2236 ring->ring_obj = NULL((void *)0);
2237 ring->use_doorbell = true1;
2238 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
2239 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
2240 + (ring_id * GFX9_MEC_HPD_SIZE4096);
2241 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
2242
2243 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
2244 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
2245 + ring->pipe;
2246 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
2247 ring->queue) ?
2248 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
2249 /* type-2 packets are deprecated on MEC, use type-3 instead */
2250 return amdgpu_ring_init(adev, ring, 1024,
2251 &adev->gfx.eop_irq, irq_type, hw_prio);
2252}
2253
2254static int gfx_v9_0_sw_init(void *handle)
2255{
2256 int i, j, k, r, ring_id;
2257 struct amdgpu_ring *ring;
2258 struct amdgpu_kiq *kiq;
2259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2260
2261 switch (adev->asic_type) {
1
Control jumps to 'case CHIP_RENOIR:' at line 2267
→
2262 case CHIP_VEGA10:
2263 case CHIP_VEGA12:
2264 case CHIP_VEGA20:
2265 case CHIP_RAVEN:
2266 case CHIP_ARCTURUS:
2267 case CHIP_RENOIR:
2268 adev->gfx.mec.num_mec = 2;
2269 break;
2
←
 Execution continues on line 2275
→
2270 default:
2271 adev->gfx.mec.num_mec = 1;
2272 break;
2273 }
2274
2275 adev->gfx.mec.num_pipe_per_mec = 4;
2276 adev->gfx.mec.num_queue_per_pipe = 8;
2277
2278 /* EOP Event */
2279 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT181, &adev->gfx.eop_irq);
2280 if (r)
3
←
Assuming 'r' is 0
→
4
←
Taking false branch
→
2281 return r;
2282
2283 /* Privileged reg */
2284 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT184,
2285 &adev->gfx.priv_reg_irq);
2286 if (r)
5
←
Assuming 'r' is 0
→
6
←
Taking false branch
→
2287 return r;
2288
2289 /* Privileged inst */
2290 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT185,
2291 &adev->gfx.priv_inst_irq);
2292 if (r)
7
←
Assuming 'r' is 0
→
8
←
Taking false branch
→
2293 return r;
2294
2295 /* ECC error */
2296 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR197,
2297 &adev->gfx.cp_ecc_error_irq);
2298 if (r)
9
←
Assuming 'r' is 0
→
10
←
Taking false branch
→
2299 return r;
2300
2301 /* FUE error */
2302 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR201,
2303 &adev->gfx.cp_ecc_error_irq);
2304 if (r)
11
←
Assuming 'r' is 0
→
12
←
Taking false branch
→
2305 return r;
2306
2307 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE0x00000000L;
2308
2309 gfx_v9_0_scratch_init(adev);
13
←
Calling 'gfx_v9_0_scratch_init'
→
15
←
Returning from 'gfx_v9_0_scratch_init'
→
2310
2311 r = gfx_v9_0_init_microcode(adev);
16
←
Calling 'gfx_v9_0_init_microcode'
→
2312 if (r) {
2313 DRM_ERROR("Failed to load gfx firmware!\n")__drm_err("Failed to load gfx firmware!\n");
2314 return r;
2315 }
2316
2317 r = adev->gfx.rlc.funcs->init(adev);
2318 if (r) {
2319 DRM_ERROR("Failed to init rlc BOs!\n")__drm_err("Failed to init rlc BOs!\n");
2320 return r;
2321 }
2322
2323 r = gfx_v9_0_mec_init(adev);
2324 if (r) {
2325 DRM_ERROR("Failed to init MEC BOs!\n")__drm_err("Failed to init MEC BOs!\n");
2326 return r;
2327 }
2328
2329 /* set up the gfx ring */
2330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2331 ring = &adev->gfx.gfx_ring[i];
2332 ring->ring_obj = NULL((void *)0);
2333 if (!i)
2334 snprintf(ring->name, sizeof(ring->name), "gfx");
2335 else
2336 snprintf(ring->name, sizeof(ring->name), "gfx_%d", i);
2337 ring->use_doorbell = true1;
2338 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
2339 r = amdgpu_ring_init(adev, ring, 1024,
2340 &adev->gfx.eop_irq,
2341 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2342 AMDGPU_RING_PRIO_DEFAULT1);
2343 if (r)
2344 return r;
2345 }
2346
2347 /* set up the compute queues - allocate horizontally across pipes */
2348 ring_id = 0;
2349 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2350 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2351 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2352 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2353 continue;
2354
2355 r = gfx_v9_0_compute_ring_init(adev,
2356 ring_id,
2357 i, k, j);
2358 if (r)
2359 return r;
2360
2361 ring_id++;
2362 }
2363 }
2364 }
2365
2366 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE4096);
2367 if (r) {
2368 DRM_ERROR("Failed to init KIQ BOs!\n")__drm_err("Failed to init KIQ BOs!\n");
2369 return r;
2370 }
2371
2372 kiq = &adev->gfx.kiq;
2373 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2374 if (r)
2375 return r;
2376
2377 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
2378 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
2379 if (r)
2380 return r;
2381
2382 adev->gfx.ce_ram_size = 0x8000;
2383
2384 r = gfx_v9_0_gpu_early_init(adev);
2385 if (r)
2386 return r;
2387
2388 return 0;
2389}
2390
2391
2392static int gfx_v9_0_sw_fini(void *handle)
2393{
2394 int i;
2395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2396
2397 amdgpu_gfx_ras_fini(adev);
2398
2399 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2400 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2401 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2402 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2403
2404 amdgpu_gfx_mqd_sw_fini(adev);
2405 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2406 amdgpu_gfx_kiq_fini(adev);
2407
2408 gfx_v9_0_mec_fini(adev);
2409 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2410 if (adev->flags & AMD_IS_APU) {
2411 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2412 &adev->gfx.rlc.cp_table_gpu_addr,
2413 (void **)&adev->gfx.rlc.cp_table_ptr);
2414 }
2415 gfx_v9_0_free_microcode(adev);
2416
2417 return 0;
2418}
2419
2420
2421static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
2422{
2423 /* TODO */
2424}
2425
2426void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
2427 u32 instance)
2428{
2429 u32 data;
2430
2431 if (instance == 0xffffffff)
2432 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1)(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e
)));
2433 else
2434 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance)(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) <<
0x0)));
2435
2436 if (se_num == 0xffffffff)
2437 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1)(((data) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
2438 else
2439 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num)(((data) & ~0x00FF0000L) | (0x00FF0000L & ((se_num) <<
0x10)));
2440
2441 if (sh_num == 0xffffffff)
2442 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1)(((data) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
2443 else
2444 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((sh_num) <<
0x8)));
2445
2446 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x2200; if (((((adev))->virt.caps & (1 << 2))
&& !(((adev))->virt.caps & (1 << 4)))) {
uint32_t r2 = adev->reg_offset[GC_HWIP][0][1] + 0x2042; uint32_t
r3 = adev->reg_offset[GC_HWIP][0][1] + 0x2043; uint32_t grbm_cntl
= adev->reg_offset[GC_HWIP][0][0] + 0x0022; uint32_t grbm_idx
= adev->reg_offset[GC_HWIP][0][1] + 0x2200; if (target_reg
== grbm_cntl) amdgpu_device_wreg(adev, (r2), (data), 0); else
if (target_reg == grbm_idx) amdgpu_device_wreg(adev, (r3), (
data), 0); amdgpu_device_wreg(adev, (target_reg), (data), 0);
} else { amdgpu_device_wreg(adev, (target_reg), (data), 0); }
} while (0);
2447}
2448
2449static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2450{
2451 u32 data, mask;
2452
2453 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x063d), 0);
2454 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x06df), 0);
2455
2456 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK0x00FF0000L;
2457 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT0x10;
2458
2459 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2460 adev->gfx.config.max_sh_per_se);
2461
2462 return (~data) & mask;
2463}
2464
2465static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
2466{
2467 int i, j;
2468 u32 data;
2469 u32 active_rbs = 0;
2470 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2471 adev->gfx.config.max_sh_per_se;
2472
2473 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
2474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2476 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2477 data = gfx_v9_0_get_rb_active_bitmap(adev);
2478 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2479 rb_bitmap_width_per_sh);
2480 }
2481 }
2482 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2483 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
2484
2485 adev->gfx.config.backend_enable_mask = active_rbs;
2486 adev->gfx.config.num_rbs = hweight32(active_rbs);
2487}
2488
2489#define DEFAULT_SH_MEM_BASES(0x6000) (0x6000)
2490static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
2491{
2492 int i;
2493 uint32_t sh_mem_config;
2494 uint32_t sh_mem_bases;
2495
2496 /*
2497 * Configure apertures:
2498 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2499 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2500 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2501 */
2502 sh_mem_bases = DEFAULT_SH_MEM_BASES(0x6000) | (DEFAULT_SH_MEM_BASES(0x6000) << 16);
2503
2504 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
2505 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2506 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT0x3;
2507
2508 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
2509 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
2510 soc15_grbm_select(adev, 0, 0, 0, i);
2511 /* CP and shaders */
2512 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (sh_mem_config), 0); amdgpu_device_wreg(adev, (r1
), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev, (
spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), (sh_mem_config
), 0); } } while (0); } while (0);
2513 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (sh_mem_bases), 0); amdgpu_device_wreg(adev, (r1
), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev, (
spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), (sh_mem_bases)
, 0); } } while (0); } while (0);
2514 }
2515 soc15_grbm_select(adev, 0, 0, 0, 0);
2516 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
2517
2518 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
2519 acccess. These should be enabled by FW for target VMIDs. */
2520 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
2521 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1300) + 2 * i), (0), 0);
2522 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1301) + 2 * i), (0), 0);
2523 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1320) + i), (0), 0);
2524 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1330) + i), (0), 0);
2525 }
2526}
2527
2528static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
2529{
2530 int vmid;
2531
2532 /*
2533 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2534 * access. Compute VMIDs should be enabled by FW for target VMIDs,
2535 * the driver can enable them for graphics. VMID0 should maintain
2536 * access so that HWS firmware can save/restore entries.
2537 */
2538 for (vmid = 1; vmid < 16; vmid++) {
2539 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1300) + 2 * vmid), (0), 0);
2540 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1301) + 2 * vmid), (0), 0);
2541 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1320) + vmid), (0), 0);
2542 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1330) + vmid), (0), 0);
2543 }
2544}
2545
2546static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
2547{
2548 uint32_t tmp;
2549
2550 switch (adev->asic_type) {
2551 case CHIP_ARCTURUS:
2552 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0300), 0);
2553 tmp = REG_SET_FIELD(tmp, SQ_CONFIG,(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)))
2554 DISABLE_BARRIER_WAITCNT, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
2555 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0300)), (tmp), 0);
2556 break;
2557 default:
2558 break;
2559 }
2560}
2561
2562static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
2563{
2564 u32 tmp;
2565 int i;
2566
2567 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff)do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), ((amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x0000), 0) &
~0x000000FFL) | (0xff) << 0x0), 0); amdgpu_device_wreg
(adev, (r1), (((adev->reg_offset[GC_HWIP][0][0] + 0x0000) |
0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][0] + 0x0000)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0000)), ((amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x0000), 0) &
~0x000000FFL) | (0xff) << 0x0), 0); } } while (0);
2568
2569 gfx_v9_0_tiling_mode_table_init(adev);
2570
2571 gfx_v9_0_setup_rb(adev);
2572 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
2573 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x060d), 0);
2574
2575 /* XXX SH_MEM regs */
2576 /* where to put LDS, scratch, GPUVM in FSA64 space */
2577 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
2578 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_00].num_ids; i++) {
2579 soc15_grbm_select(adev, 0, 0, 0, i);
2580 /* CP and shaders */
2581 if (i == 0) {
2582 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED
) << 0x3)))
2583 SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED
) << 0x3)));
2584 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev->
gmc.noretry) << 0xc)))
2585 !!adev->gmc.noretry)(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev->
gmc.noretry) << 0xc)));
2586 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
2587 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
2588 } else {
2589 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED
) << 0x3)))
2590 SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED
) << 0x3)));
2591 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev->
gmc.noretry) << 0xc)))
2592 !!adev->gmc.noretry)(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev->
gmc.noretry) << 0xc)));
2593 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
2594 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)))
2595 (adev->gmc.private_aperture_start >> 48))(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)));
2596 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)))
2597 (adev->gmc.shared_aperture_start >> 48))(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)));
2598 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x030a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
2599 }
2600 }
2601 soc15_grbm_select(adev, 0, 0, 0, 0);
2602
2603 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
2604
2605 gfx_v9_0_init_compute_vmid(adev);
2606 gfx_v9_0_init_gds_vmid(adev);
2607 gfx_v9_0_init_sq_config(adev);
2608}
2609
2610static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2611{
2612 u32 i, j, k;
2613 u32 mask;
2614
2615 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
2616 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2617 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2618 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2619 for (k = 0; k < adev->usec_timeout; k++) {
2620 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c61), 0) == 0)
2621 break;
2622 udelay(1);
2623 }
2624 if (k == adev->usec_timeout) {
2625 gfx_v9_0_select_se_sh(adev, 0xffffffff,
2626 0xffffffff, 0xffffffff);
2627 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
2628 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n"
, i, j)
2629 i, j)printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n"
, i, j);
2630 return;
2631 }
2632 }
2633 }
2634 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2635 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
2636
2637 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK0x0000FFFFL |
2638 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK0x00010000L |
2639 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK0x00040000L |
2640 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK0x00080000L;
2641 for (k = 0; k < adev->usec_timeout; k++) {
2642 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c62), 0) & mask) == 0)
2643 break;
2644 udelay(1);
2645 }
2646}
2647
2648static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2649 bool_Bool enable)
2650{
2651 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), 0);
2652
2653 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1
: 0) << 0x13)));
2654 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1
: 0) << 0x14)));
2655 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)));
2656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1
: 0) << 0x15)));
2657
2658 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x106a)), (tmp), 0);
2659}
2660
2661static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2662{
2663 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2664 /* csib */
2665 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_gpu_addr >> 32), 0); amdgpu_device_wreg
(adev, (r1), (((adev->reg_offset[GC_HWIP][0][1] + 0x4ca3) |
0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca3)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca3)), (adev
->gfx.rlc.clear_state_gpu_addr >> 32), 0); } } while
(0)
2666 adev->gfx.rlc.clear_state_gpu_addr >> 32)do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_gpu_addr >> 32), 0); amdgpu_device_wreg
(adev, (r1), (((adev->reg_offset[GC_HWIP][0][1] + 0x4ca3) |
0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca3)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca3)), (adev
->gfx.rlc.clear_state_gpu_addr >> 32), 0); } } while
(0);
2667 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_gpu_addr & 0xfffffffc), 0); amdgpu_device_wreg
(adev, (r1), (((adev->reg_offset[GC_HWIP][0][1] + 0x4ca2) |
0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca2)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca2)), (adev
->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0); } } while
(0)
2668 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_gpu_addr & 0xfffffffc), 0); amdgpu_device_wreg
(adev, (r1), (((adev->reg_offset[GC_HWIP][0][1] + 0x4ca2) |
0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca2)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca2)), (adev
->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0); } } while
(0);
2669 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_size), 0); amdgpu_device_wreg(adev, (r1), ((
(adev->reg_offset[GC_HWIP][0][1] + 0x4ca4) | 0x80000000)),
0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (i =
0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev,
(r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); } if
(i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca4)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca4)), (adev
->gfx.rlc.clear_state_size), 0); } } while (0)
2670 adev->gfx.rlc.clear_state_size)do { if (((((adev))->virt.caps & (1 << 2)) &&
!(((adev))->virt.caps & (1 << 4)))) { uint32_t i
= 0; uint32_t retries = 50000; uint32_t r0 = adev->reg_offset
[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev->reg_offset[GC_HWIP
][0][1] + 0x2041; uint32_t spare_int = adev->reg_offset[GC_HWIP
][0][1] + 0x4ccc; amdgpu_device_wreg(adev, (r0), (adev->gfx
.rlc.clear_state_size), 0); amdgpu_device_wreg(adev, (r1), ((
(adev->reg_offset[GC_HWIP][0][1] + 0x4ca4) | 0x80000000)),
0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (i =
0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev,
(r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); } if
(i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, (adev->reg_offset[GC_HWIP][0][1] + 0x4ca4)); } else { amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4ca4)), (adev
->gfx.rlc.clear_state_size), 0); } } while (0);
2671}
2672
2673static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2674 int indirect_offset,
2675 int list_size,
2676 int *unique_indirect_regs,
2677 int unique_indirect_reg_count,
2678 int *indirect_start_offsets,
2679 int *indirect_start_offsets_count,
2680 int max_start_offsets_count)
2681{
2682 int idx;
2683
2684 for (; indirect_offset < list_size; indirect_offset++) {
2685 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count)({ int __ret = !!(*indirect_start_offsets_count >= max_start_offsets_count
); if (__ret) printf("WARNING %s failed at %s:%d\n", "*indirect_start_offsets_count >= max_start_offsets_count"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 2685); __builtin_expect
(!!(__ret), 0); });
2686 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2687 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2688
2689 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2690 indirect_offset += 2;
2691
2692 /* look for the matching indice */
2693 for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2694 if (unique_indirect_regs[idx] ==
2695 register_list_format[indirect_offset] ||
2696 !unique_indirect_regs[idx])
2697 break;
2698 }
2699
2700 BUG_ON(idx >= unique_indirect_reg_count)((!(idx >= unique_indirect_reg_count)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 2700, "!(idx >= unique_indirect_reg_count)"));
2701
2702 if (!unique_indirect_regs[idx])
2703 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2704
2705 indirect_offset++;
2706 }
2707 }
2708}
2709
2710static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2711{
2712 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2713 int unique_indirect_reg_count = 0;
2714
2715 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2716 int indirect_start_offsets_count = 0;
2717
2718 int list_size = 0;
2719 int i = 0, j = 0;
2720 u32 tmp = 0;
2721
2722 u32 *register_list_format =
2723 kmemdup(adev->gfx.rlc.register_list_format,
2724 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL(0x0001 | 0x0004));
2725 if (!register_list_format)
2726 return -ENOMEM12;
2727
2728 /* setup unique_indirect_regs array and indirect_start_offsets array */
2729 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs)(sizeof((unique_indirect_regs)) / sizeof((unique_indirect_regs
)[0]));
2730 gfx_v9_1_parse_ind_reg_list(register_list_format,
2731 adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2732 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2733 unique_indirect_regs,
2734 unique_indirect_reg_count,
2735 indirect_start_offsets,
2736 &indirect_start_offsets_count,
2737 ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets
)[0])));
2738
2739 /* enable auto inc in case it is disabled */
2740 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c80)), 0);
2741 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK0x00000002L;
2742 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c80)), (tmp), 0);
2743
2744 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2745 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c83)), (0x00000000L), 0)
2746 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c83)), (0x00000000L), 0);
2747 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2748 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c84)), (adev->gfx.rlc.register_restore[i]), 0)
2749 adev->gfx.rlc.register_restore[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c84)), (adev->gfx.rlc.register_restore[i]), 0);
2750
2751 /* load indirect register */
2752 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.reg_list_format_start), 0)
2753 adev->gfx.rlc.reg_list_format_start)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.reg_list_format_start), 0);
2754
2755 /* direct register portion */
2756 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2757 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (register_list_format[i]), 0)
2758 register_list_format[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (register_list_format[i]), 0);
2759
2760 /* indirect register portion */
2761 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2762 if (register_list_format[i] == 0xFFFFFFFF) {
2763 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (register_list_format[i++]), 0);
2764 continue;
2765 }
2766
2767 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (register_list_format[i++]), 0);
2768 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (register_list_format[i++]), 0);
2769
2770 for (j = 0; j < unique_indirect_reg_count; j++) {
2771 if (register_list_format[i] == unique_indirect_regs[j]) {
2772 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (j), 0);
2773 break;
2774 }
2775 }
2776
2777 BUG_ON(j >= unique_indirect_reg_count)((!(j >= unique_indirect_reg_count)) ? (void)0 : __assert(
"diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 2777, "!(j >= unique_indirect_reg_count)"));
2778
2779 i++;
2780 }
2781
2782 /* set save/restore list size */
2783 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2784 list_size = list_size >> 1;
2785 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.reg_restore_list_size), 0)
2786 adev->gfx.rlc.reg_restore_list_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.reg_restore_list_size), 0);
2787 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (list_size), 0);
2788
2789 /* write the starting offsets to RLC scratch ram */
2790 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.starting_offsets_start), 0)
2791 adev->gfx.rlc.starting_offsets_start)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6c)), (adev->gfx.rlc.starting_offsets_start), 0);
2792 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets
)[0])); i++)
2793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (indirect_start_offsets[i]), 0)
2794 indirect_start_offsets[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c6d)), (indirect_start_offsets[i]), 0);
2795
2796 /* load unique indirect regs*/
2797 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs)(sizeof((unique_indirect_regs)) / sizeof((unique_indirect_regs
)[0])); i++) {
2798 if (unique_indirect_regs[i] != 0) {
2799 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs
[i] & 0x3FFFF), 0)
2800 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs
[i] & 0x3FFFF), 0)
2801 unique_indirect_regs[i] & 0x3FFFF)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs
[i] & 0x3FFFF), 0);
2802
2803 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs
[i] >> 20), 0)
2804 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs
[i] >> 20), 0)
2805 unique_indirect_regs[i] >> 20)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs
[i] >> 20), 0);
2806 }
2807 }
2808
2809 kfree(register_list_format);
2810 return 0;
2811}
2812
2813static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2814{
2815 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c80), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][1] + 0x4c80), 0) & ~0x00000001L) | (1) << 0x0)
, 0);
2816}
2817
2818static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2819 bool_Bool enable)
2820{
2821 uint32_t data = 0;
2822 uint32_t default_data = 0;
2823
2824 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS))amdgpu_device_rreg(adev, ((adev->reg_offset[PWR_HWIP][0][0
] + 0x0183)), 0);
2825 if (enable) {
2826 /* enable GFXIP control over CGPG */
2827 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK0x00000001L;
2828 if(default_data != data)
2829 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0
] + 0x0183)), (data), 0);
2830
2831 /* update status */
2832 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK0x00000006L;
2833 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT0x1);
2834 if(default_data != data)
2835 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0
] + 0x0183)), (data), 0);
2836 } else {
2837 /* restore GFXIP control over GCPG */
2838 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK0x00000001L;
2839 if(default_data != data)
2840 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0
] + 0x0183)), (data), 0);
2841 }
2842}
2843
2844static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2845{
2846 uint32_t data = 0;
2847
2848 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG(1 << 0) |
2849 AMD_PG_SUPPORT_GFX_SMG(1 << 1) |
2850 AMD_PG_SUPPORT_GFX_DMG(1 << 2))) {
2851 /* init IDLE_POLL_COUNT = 60 */
2852 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x01c2)), 0);
2853 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK0xFFFF0000L;
2854 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
2855 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x01c2)), (data), 0);
2856
2857 /* init RLC PG Delay */
2858 data = 0;
2859 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT0x0);
2860 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT0x8);
2861 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT0x10);
2862 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT0x18);
2863 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c4d)), (data), 0);
2864
2865 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1f)), 0);
2866 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK0x0000FF00L;
2867 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT0x8);
2868 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1f)), (data), 0);
2869
2870 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c78)), 0);
2871 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK0x000000FFL;
2872 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT0x0);
2873 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c78)), (data), 0);
2874
2875 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c55)), 0);
2876 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK0x0007FFF8L;
2877
2878 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2879 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT0x3);
2880 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c55)), (data), 0);
2881 if (adev->asic_type != CHIP_RENOIR)
2882 pwr_10_0_gfxip_control_over_cgpg(adev, true1);
2883 }
2884}
2885
2886static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2887 bool_Bool enable)
2888{
2889 uint32_t data = 0;
2890 uint32_t default_data = 0;
2891
2892 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2893 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1
: 0) << 0x11)))
2894 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1
: 0) << 0x11)))
2895 enable ? 1 : 0)(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1
: 0) << 0x11)));
2896 if (default_data != data)
2897 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2898}
2899
2900static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2901 bool_Bool enable)
2902{
2903 uint32_t data = 0;
2904 uint32_t default_data = 0;
2905
2906 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2907 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)))
2908 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)))
2909 enable ? 1 : 0)(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)));
2910 if(default_data != data)
2911 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2912}
2913
2914static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2915 bool_Bool enable)
2916{
2917 uint32_t data = 0;
2918 uint32_t default_data = 0;
2919
2920 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2921 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0
: 1) << 0xf)))
2922 CP_PG_DISABLE,(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0
: 1) << 0xf)))
2923 enable ? 0 : 1)(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0
: 1) << 0xf)));
2924 if(default_data != data)
2925 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2926}
2927
2928static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2929 bool_Bool enable)
2930{
2931 uint32_t data, default_data;
2932
2933 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2934 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1
: 0) << 0x0)))
2935 GFX_POWER_GATING_ENABLE,(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1
: 0) << 0x0)))
2936 enable ? 1 : 0)(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1
: 0) << 0x0)));
2937 if(default_data != data)
2938 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2939}
2940
2941static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2942 bool_Bool enable)
2943{
2944 uint32_t data, default_data;
2945
2946 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2947 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1
: 0) << 0x4)))
2948 GFX_PIPELINE_PG_ENABLE,(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1
: 0) << 0x4)))
2949 enable ? 1 : 0)(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1
: 0) << 0x4)));
2950 if(default_data != data)
2951 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2952
2953 if (!enable)
2954 /* read any GFX register to wake up GFX */
2955 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x0000)), 0);
2956}
2957
2958static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2959 bool_Bool enable)
2960{
2961 uint32_t data, default_data;
2962
2963 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2964 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1
: 0) << 0x3)))
2965 STATIC_PER_CU_PG_ENABLE,(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1
: 0) << 0x3)))
2966 enable ? 1 : 0)(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1
: 0) << 0x3)));
2967 if(default_data != data)
2968 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2969}
2970
2971static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2972 bool_Bool enable)
2973{
2974 uint32_t data, default_data;
2975
2976 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), 0);
2977 data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1
: 0) << 0x2)))
2978 DYN_PER_CU_PG_ENABLE,(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1
: 0) << 0x2)))
2979 enable ? 1 : 0)(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1
: 0) << 0x2)));
2980 if(default_data != data)
2981 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (data), 0);
2982}
2983
2984static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2985{
2986 gfx_v9_0_init_csb(adev);
2987
2988 /*
2989 * Rlc save restore list is workable since v2_1.
2990 * And it's needed by gfxoff feature.
2991 */
2992 if (adev->gfx.rlc.is_rlc_v2_1) {
2993 if (adev->asic_type == CHIP_VEGA12 ||
2994 (adev->apu_flags & AMD_APU_IS_RAVEN2))
2995 gfx_v9_1_init_rlc_save_restore_list(adev);
2996 gfx_v9_0_enable_save_restore_machine(adev);
2997 }
2998
2999 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG(1 << 0) |
3000 AMD_PG_SUPPORT_GFX_SMG(1 << 1) |
3001 AMD_PG_SUPPORT_GFX_DMG(1 << 2) |
3002 AMD_PG_SUPPORT_CP(1 << 5) |
3003 AMD_PG_SUPPORT_GDS(1 << 6) |
3004 AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7))) {
3005 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1e)), (adev->gfx.rlc.cp_table_gpu_addr >> 8),
0)
3006 adev->gfx.rlc.cp_table_gpu_addr >> 8)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c1e)), (adev->gfx.rlc.cp_table_gpu_addr >> 8),
0);
3007 gfx_v9_0_init_gfx_power_gating(adev);
3008 }
3009}
3010
3011void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
3012{
3013 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][1] + 0x4c00), 0) & ~0x00000001L) | (0) << 0x0)
, 0);
3014 gfx_v9_0_enable_gui_idle_interrupt(adev, false0);
3015 gfx_v9_0_wait_for_rlc_serdes(adev);
3016}
3017
3018static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
3019{
3020 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0008), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x0008), 0) & ~0x00000004L) | (1) << 0x2)
, 0);
3021 udelay(50);
3022 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0008), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x0008), 0) & ~0x00000004L) | (0) << 0x2)
, 0);
3023 udelay(50);
3024}
3025
3026static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
3027{
3028#ifdef AMDGPU_RLC_DEBUG_RETRY
3029 u32 rlc_ucode_ver;
3030#endif
3031
3032 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][1] + 0x4c00), 0) & ~0x00000001L) | (1) << 0x0)
, 0);
3033 udelay(50);
3034
3035 /* carrizo do enable cp interrupt after cp inited */
3036 if (!(adev->flags & AMD_IS_APU)) {
3037 gfx_v9_0_enable_gui_idle_interrupt(adev, true1);
3038 udelay(50);
3039 }
3040
3041#ifdef AMDGPU_RLC_DEBUG_RETRY
3042 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
3043 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c69), 0);
3044 if(rlc_ucode_ver == 0x108) {
3045 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",printk("\0016" "[" "drm" "] " "Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n"
, rlc_ucode_ver, adev->gfx.rlc_fw_version)
3046 rlc_ucode_ver, adev->gfx.rlc_fw_version)printk("\0016" "[" "drm" "] " "Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n"
, rlc_ucode_ver, adev->gfx.rlc_fw_version);
3047 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
3048 * default is 0x9C4 to create a 100us interval */
3049 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c15)), (0x9C4), 0);
3050 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
3051 * to disable the page fault retry interrupts, default is
3052 * 0x100 (256) */
3053 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cb1)), (0x100), 0);
3054 }
3055#endif
3056}
3057
3058static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
3059{
3060 const struct rlc_firmware_header_v2_0 *hdr;
3061 const __le32 *fw_data;
3062 unsigned i, fw_size;
3063
3064 if (!adev->gfx.rlc_fw)
3065 return -EINVAL22;
3066
3067 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3068 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3069
3070 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3071 le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));
3072 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4;
3073
3074 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x583c)), (0x00002000L), 0)
3075 RLCG_UCODE_LOADING_START_ADDRESS)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x583c)), (0x00002000L), 0);
3076 for (i = 0; i < fw_size; i++)
3077 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x583d)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
3078 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x583c)), (adev->gfx.rlc_fw_version), 0);
3079
3080 return 0;
3081}
3082
3083static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
3084{
3085 int r;
3086
3087 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
3088 gfx_v9_0_init_csb(adev);
3089 return 0;
3090 }
3091
3092 adev->gfx.rlc.funcs->stop(adev);
3093
3094 /* disable CG */
3095 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (0), 0);
3096
3097 gfx_v9_0_init_pg(adev);
3098
3099 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3100 /* legacy rlc firmware loading */
3101 r = gfx_v9_0_rlc_load_microcode(adev);
3102 if (r)
3103 return r;
3104 }
3105
3106 switch (adev->asic_type) {
3107 case CHIP_RAVEN:
3108 if (amdgpu_lbpw == 0)
3109 gfx_v9_0_enable_lbpw(adev, false0);
3110 else
3111 gfx_v9_0_enable_lbpw(adev, true1);
3112 break;
3113 case CHIP_VEGA20:
3114 if (amdgpu_lbpw > 0)
3115 gfx_v9_0_enable_lbpw(adev, true1);
3116 else
3117 gfx_v9_0_enable_lbpw(adev, false0);
3118 break;
3119 default:
3120 break;
3121 }
3122
3123 adev->gfx.rlc.funcs->start(adev);
3124
3125 return 0;
3126}
3127
3128static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool_Bool enable)
3129{
3130 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x01b6), 0);
3131
3132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((enable ? 0
: 1) << 0x1c)));
3133 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1)(((tmp) & ~0x04000000L) | (0x04000000L & ((enable ? 0
: 1) << 0x1a)));
3134 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((enable ? 0
: 1) << 0x18)));
3135 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x01b6; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
3136 udelay(50);
3137}
3138
3139static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3140{
3141 const struct gfx_firmware_header_v1_0 *pfp_hdr;
3142 const struct gfx_firmware_header_v1_0 *ce_hdr;
3143 const struct gfx_firmware_header_v1_0 *me_hdr;
3144 const __le32 *fw_data;
3145 unsigned i, fw_size;
3146
3147 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3148 return -EINVAL22;
3149
3150 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3151 adev->gfx.pfp_fw->data;
3152 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3153 adev->gfx.ce_fw->data;
3154 me_hdr = (const struct gfx_firmware_header_v1_0 *)
3155 adev->gfx.me_fw->data;
3156
3157 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3158 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3159 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3160
3161 gfx_v9_0_cp_gfx_enable(adev, false0);
3162
3163 /* PFP */
3164 fw_data = (const __le32 *)
3165 (adev->gfx.pfp_fw->data +
3166 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(pfp_hdr->header.ucode_array_offset_bytes)));
3167 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes)((__uint32_t)(pfp_hdr->header.ucode_size_bytes)) / 4;
3168 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5814)), (0), 0);
3169 for (i = 0; i < fw_size; i++)
3170 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5815)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
3171 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5814)), (adev->gfx.pfp_fw_version), 0);
3172
3173 /* CE */
3174 fw_data = (const __le32 *)
3175 (adev->gfx.ce_fw->data +
3176 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ce_hdr->header.ucode_array_offset_bytes)));
3177 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes)((__uint32_t)(ce_hdr->header.ucode_size_bytes)) / 4;
3178 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5818)), (0), 0);
3179 for (i = 0; i < fw_size; i++)
3180 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5819)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
3181 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5818)), (adev->gfx.ce_fw_version), 0);
3182
3183 /* ME */
3184 fw_data = (const __le32 *)
3185 (adev->gfx.me_fw->data +
3186 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)((__uint32_t)(me_hdr->header.ucode_array_offset_bytes)));
3187 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes)((__uint32_t)(me_hdr->header.ucode_size_bytes)) / 4;
3188 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5816)), (0), 0);
3189 for (i = 0; i < fw_size; i++)
3190 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5817)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
3191 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5816)), (adev->gfx.me_fw_version), 0);
3192
3193 return 0;
3194}
3195
3196static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
3197{
3198 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3199 const struct cs_section_def *sect = NULL((void *)0);
3200 const struct cs_extent_def *ext = NULL((void *)0);
3201 int r, i, tmp;
3202
3203 /* init the CP */
3204 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10ae)), (adev->gfx.config.max_hw_contexts - 1), 0);
3205 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x104b)), (1), 0);
3206
3207 gfx_v9_0_cp_gfx_enable(adev, true1);
3208
3209 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
3210 if (r) {
3211 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r);
3212 return r;
3213 }
3214
3215 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
3216 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28));
3217
3218 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3219 amdgpu_ring_write(ring, 0x80000000);
3220 amdgpu_ring_write(ring, 0x80000000);
3221
3222 for (sect = gfx9_cs_data; sect->section != NULL((void *)0); ++sect) {
3223 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
3224 if (sect->id == SECT_CONTEXT) {
3225 amdgpu_ring_write(ring,
3226 PACKET3(PACKET3_SET_CONTEXT_REG,((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16)
3227 ext->reg_count)((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16));
3228 amdgpu_ring_write(ring,
3229 ext->reg_index - PACKET3_SET_CONTEXT_REG_START0x0000a000);
3230 for (i = 0; i < ext->reg_count; i++)
3231 amdgpu_ring_write(ring, ext->extent[i]);
3232 }
3233 }
3234 }
3235
3236 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
3237 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28));
3238
3239 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
3240 amdgpu_ring_write(ring, 0);
3241
3242 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)((3 << 30) | (((0x11) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
3243 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)((3) << 0));
3244 amdgpu_ring_write(ring, 0x8000);
3245 amdgpu_ring_write(ring, 0x8000);
3246
3247 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3248 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE(2 << 28) |
3249 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE)(adev->reg_offset[GC_HWIP][0][1] + 0x2243) - PACKET3_SET_UCONFIG_REG_START0x0000c000));
3250 amdgpu_ring_write(ring, tmp);
3251 amdgpu_ring_write(ring, 0);
3252
3253 amdgpu_ring_commit(ring);
3254
3255 return 0;
3256}
3257
3258static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
3259{
3260 struct amdgpu_ring *ring;
3261 u32 tmp;
3262 u32 rb_bufsz;
3263 u64 rb_addr, rptr_addr, wptr_gpu_addr;
3264
3265 /* Set the write pointer delay */
3266 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x01c1)), (0), 0);
3267
3268 /* set the RB to use vmid 0 */
3269 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1051)), (0), 0);
3270
3271 /* Set ring buffer size */
3272 ring = &adev->gfx.gfx_ring[0];
3273 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
3274 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
3275 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
3276#ifdef __BIG_ENDIAN
3277 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00060000L) | (0x00060000L & ((1) <<
0x11)));
3278#endif
3279 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1041)), (tmp), 0);
3280
3281 /* Initialize the ring buffer's write pointers */
3282 ring->wptr = 0;
3283 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1054)), (((u32)(ring->wptr))), 0);
3284 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1055)), (((u32)(((ring->wptr) >> 16) >> 16
))), 0);
3285
3286 /* set the wb address wether it's enabled or not */
3287 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3288 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1043)), (((u32)(rptr_addr))), 0);
3289 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1044)), (((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL), 0);
3290
3291 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3292 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1046)), (((u32)(wptr_gpu_addr))), 0);
3293 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1047)), (((u32)(((wptr_gpu_addr) >> 16) >> 16
))), 0);
3294
3295 mdelay(1);
3296 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1041)), (tmp), 0);
3297
3298 rb_addr = ring->gpu_addr >> 8;
3299 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1040)), (rb_addr), 0);
3300 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10b1)), (((u32)(((rb_addr) >> 16) >> 16))), 0
);
3301
3302 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1059), 0);
3303 if (ring->use_doorbell) {
3304 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
3305 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
3306 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
3307 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
3308 } else {
3309 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
3310 }
3311 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1059)), (tmp), 0);
3312
3313 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
3314 DOORBELL_RANGE_LOWER, ring->doorbell_index)(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
3315 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105a)), (tmp), 0);
3316
3317 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105b)), (0x0FFFFFFCL), 0)
3318 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105b)), (0x0FFFFFFCL), 0);
3319
3320
3321 /* start the ring */
3322 gfx_v9_0_cp_gfx_start(adev);
3323 ring->sched.ready = true1;
3324
3325 return 0;
3326}
3327
3328static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool_Bool enable)
3329{
3330 if (enable) {
3331 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x008d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3332 } else {
3333 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x008d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((0x40000000L | 0x10000000L)), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((0x40000000L | 0x10000000L)), 0); } } while (0); } while (
0)
3334 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x008d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), ((0x40000000L | 0x10000000L)), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, ((0x40000000L | 0x10000000L)), 0); } } while (0); } while (
0);
3335 adev->gfx.kiq.ring.sched.ready = false0;
3336 }
3337 udelay(50);
3338}
3339
3340static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3341{
3342 const struct gfx_firmware_header_v1_0 *mec_hdr;
3343 const __le32 *fw_data;
3344 unsigned i;
3345 u32 tmp;
3346
3347 if (!adev->gfx.mec_fw)
3348 return -EINVAL22;
3349
3350 gfx_v9_0_cp_compute_enable(adev, false0);
3351
3352 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3353 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3354
3355 fw_data = (const __le32 *)
3356 (adev->gfx.mec_fw->data +
3357 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
3358 tmp = 0;
3359 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
3360 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x01000000L) | (0x01000000L & ((0) <<
0x18)));
3361 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10bb)), (tmp), 0);
3362
3363 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10b9)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
), 0)
3364 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10b9)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
), 0);
3365 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10ba)), (((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16))), 0)
3366 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10ba)), (((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16))), 0);
3367
3368 /* MEC1 */
3369 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (mec_hdr->jt_offset), 0)
3370 mec_hdr->jt_offset)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (mec_hdr->jt_offset), 0);
3371 for (i = 0; i < mec_hdr->jt_size; i++)
3372 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581b)), (((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i)))), 0)
3373 le32_to_cpup(fw_data + mec_hdr->jt_offset + i))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581b)), (((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i)))), 0);
3374
3375 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (adev->gfx.mec_fw_version), 0)
3376 adev->gfx.mec_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (adev->gfx.mec_fw_version), 0);
3377 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3378
3379 return 0;
3380}
3381
3382/* KIQ functions */
3383static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
3384{
3385 uint32_t tmp;
3386 struct amdgpu_device *adev = ring->adev;
3387
3388 /* tell RLC which is KIQ queue */
3389 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4caa), 0);
3390 tmp &= 0xffffff00;
3391 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3392 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4caa; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
3393 tmp |= 0x80;
3394 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4caa; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
3395}
3396
3397static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
3398{
3399 struct amdgpu_device *adev = ring->adev;
3400
3401 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3402 if (amdgpu_gfx_is_high_priority_compute_queue(adev,
3403 ring->pipe,
3404 ring->queue)) {
3405 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
3406 mqd->cp_hqd_queue_priority =
3407 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM15;
3408 }
3409 }
3410}
3411
3412static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
3413{
3414 struct amdgpu_device *adev = ring->adev;
3415 struct v9_mqd *mqd = ring->mqd_ptr;
3416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3417 uint32_t tmp;
3418
3419 mqd->header = 0xC0310800;
3420 mqd->compute_pipelinestat_enable = 0x00000001;
3421 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3422 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3423 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3424 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3425 mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
3426 mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
3427 mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
3428 mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
3429 mqd->compute_misc_reserved = 0x00000003;
3430
3431 mqd->dynamic_cu_mask_addr_lo =
3432 lower_32_bits(ring->mqd_gpu_addr((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation
, dynamic_cu_mask)))
3433 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask))((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation
, dynamic_cu_mask)));
3434 mqd->dynamic_cu_mask_addr_hi =
3435 upper_32_bits(ring->mqd_gpu_addr((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation
, dynamic_cu_mask)) >> 16) >> 16))
3436 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask))((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation
, dynamic_cu_mask)) >> 16) >> 16));
3437
3438 eop_base_addr = ring->eop_gpu_addr >> 8;
3439 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3440 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr)((u32)(((eop_base_addr) >> 16) >> 16));
3441
3442 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3443 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x126c), 0);
3444 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(4096 / 4) - 1)) << 0x0)))
3445 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(4096 / 4) - 1)) << 0x0)));
3446
3447 mqd->cp_hqd_eop_control = tmp;
3448
3449 /* enable doorbell? */
3450 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1254), 0);
3451
3452 if (ring->use_doorbell) {
3453 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
3454 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
3455 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
3456 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
3457 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)))
3458 DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
3459 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)))
3460 DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)));
3461 } else {
3462 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
3463 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
3464 }
3465
3466 mqd->cp_hqd_pq_doorbell_control = tmp;
3467
3468 /* disable the queue if it's active */
3469 ring->wptr = 0;
3470 mqd->cp_hqd_dequeue_request = 0;
3471 mqd->cp_hqd_pq_rptr = 0;
3472 mqd->cp_hqd_pq_wptr_lo = 0;
3473 mqd->cp_hqd_pq_wptr_hi = 0;
3474
3475 /* set the pointer to the MQD */
3476 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3477 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr)((u32)(((ring->mqd_gpu_addr) >> 16) >> 16));
3478
3479 /* set MQD vmid to 0 */
3480 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1267), 0);
3481 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
3482 mqd->cp_mqd_control = tmp;
3483
3484 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3485 hqd_gpu_addr = ring->gpu_addr >> 8;
3486 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3487 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16));
3488
3489 /* set up the HQD, this is similar to CP_RB0_CNTL */
3490 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1256), 0);
3491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(ring->ring_size / 4) - 1)) << 0x0)))
3492 (order_base_2(ring->ring_size / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(ring->ring_size / 4) - 1)) << 0x0)));
3493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,(((tmp) & ~0x00003F00L) | (0x00003F00L & ((((drm_order
(4096 / 4) - 1) << 8)) << 0x8)))
3494 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8))(((tmp) & ~0x00003F00L) | (0x00003F00L & ((((drm_order
(4096 / 4) - 1) << 8)) << 0x8)));
3495#ifdef __BIG_ENDIAN
3496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1)(((tmp) & ~0x00060000L) | (0x00060000L & ((1) <<
0x11)));
3497#endif
3498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
3499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
3500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
3501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1)(((tmp) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
3502 mqd->cp_hqd_pq_control = tmp;
3503
3504 /* set the wb address whether it's enabled or not */
3505 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3506 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3507 mqd->cp_hqd_pq_rptr_report_addr_hi =
3508 upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
3509
3510 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3511 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3512 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3513 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
3514
3515 tmp = 0;
3516 /* enable the doorbell if requested */
3517 if (ring->use_doorbell) {
3518 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1254), 0);
3519 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
3520 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
3521
3522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
3523 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
3524 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)))
3525 DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
3526 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)))
3527 DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)));
3528 }
3529
3530 mqd->cp_hqd_pq_doorbell_control = tmp;
3531
3532 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3533 ring->wptr = 0;
3534 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x124f), 0);
3535
3536 /* set the vmid for the queue */
3537 mqd->cp_hqd_vmid = 0;
3538
3539 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1249), 0);
3540 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53)(((tmp) & ~0x0003FF00L) | (0x0003FF00L & ((0x53) <<
0x8)));
3541 mqd->cp_hqd_persistent_state = tmp;
3542
3543 /* set MIN_IB_AVAIL_SIZE */
3544 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x125a), 0);
3545 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3)(((tmp) & ~0x00300000L) | (0x00300000L & ((3) <<
0x14)));
3546 mqd->cp_hqd_ib_control = tmp;
3547
3548 /* set static priority for a queue/ring */
3549 gfx_v9_0_mqd_set_priority(ring, mqd);
3550 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x124c), 0);
3551
3552 /* map_queues packet doesn't need activate the queue,
3553 * so only kiq need set this field.
3554 */
3555 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3556 mqd->cp_hqd_active = 1;
3557
3558 return 0;
3559}
3560
3561static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3562{
3563 struct amdgpu_device *adev = ring->adev;
3564 struct v9_mqd *mqd = ring->mqd_ptr;
3565 int j;
3566
3567 /* disable wptr polling */
3568 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1083), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1083), 0) & ~0x80000000L) | (0) << 0x1f
), 0);
3569
3570 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_base_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_base_addr_lo), 0); } } while (0); } while
(0)
3571 mqd->cp_hqd_eop_base_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_base_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_base_addr_lo), 0); } } while (0); } while
(0);
3572 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_base_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_base_addr_hi), 0); } } while (0); } while
(0)
3573 mqd->cp_hqd_eop_base_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_base_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_base_addr_hi), 0); } } while (0); } while
(0);
3574
3575 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3576 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_control), 0); } } while (0); } while (0
)
3577 mqd->cp_hqd_eop_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x126c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_eop_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_eop_control), 0); } } while (0); } while (0
);
3578
3579 /* enable doorbell? */
3580 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_doorbell_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_doorbell_control), 0); } } while (0); } while
(0)
3581 mqd->cp_hqd_pq_doorbell_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_doorbell_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_doorbell_control), 0); } } while (0); } while
(0);
3582
3583 /* disable the queue if it's active */
3584 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1247), 0) & 1) {
3585 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (1), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (1), 0); } } while (0); } while (0);
3586 for (j = 0; j < adev->usec_timeout; j++) {
3587 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1247), 0) & 1))
3588 break;
3589 udelay(1);
3590 }
3591 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_dequeue_request), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_dequeue_request), 0); } } while (0); } while
(0)
3592 mqd->cp_hqd_dequeue_request)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_dequeue_request), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_dequeue_request), 0); } } while (0); } while
(0);
3593 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124f; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr), 0); } } while (0); } while (0)
3594 mqd->cp_hqd_pq_rptr)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124f; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr), 0); } } while (0); } while (0);
3595 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_lo), 0); } } while (0); } while (0)
3596 mqd->cp_hqd_pq_wptr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_lo), 0); } } while (0); } while (0);
3597 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_hi), 0); } } while (0); } while (0)
3598 mqd->cp_hqd_pq_wptr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_hi), 0); } } while (0); } while (0);
3599 }
3600
3601 /* set the pointer to the MQD */
3602 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1245; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_base_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_base_addr_lo), 0); } } while (0); } while (
0)
3603 mqd->cp_mqd_base_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1245; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_base_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_base_addr_lo), 0); } } while (0); } while (
0);
3604 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1246; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_base_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_base_addr_hi), 0); } } while (0); } while (
0)
3605 mqd->cp_mqd_base_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1246; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_base_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_base_addr_hi), 0); } } while (0); } while (
0);
3606
3607 /* set MQD vmid to 0 */
3608 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1267; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_control), 0); } } while (0); } while (0)
3609 mqd->cp_mqd_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1267; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_mqd_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_mqd_control), 0); } } while (0); } while (0);
3610
3611 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3612 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_base_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_base_lo), 0); } } while (0); } while (0)
3613 mqd->cp_hqd_pq_base_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_base_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_base_lo), 0); } } while (0); } while (0);
3614 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124e; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_base_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_base_hi), 0); } } while (0); } while (0)
3615 mqd->cp_hqd_pq_base_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124e; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_base_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_base_hi), 0); } } while (0); } while (0);
3616
3617 /* set up the HQD, this is similar to CP_RB0_CNTL */
3618 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1256; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_control), 0); } } while (0); } while (0)
3619 mqd->cp_hqd_pq_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1256; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_control), 0); } } while (0); } while (0);
3620
3621 /* set the wb address whether it's enabled or not */
3622 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1250; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr_report_addr_lo), 0); } } while (0);
} while (0)
3623 mqd->cp_hqd_pq_rptr_report_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1250; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr_report_addr_lo), 0); } } while (0);
} while (0);
3624 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1251; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr_report_addr_hi), 0); } } while (0);
} while (0)
3625 mqd->cp_hqd_pq_rptr_report_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1251; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_rptr_report_addr_hi), 0); } } while (0);
} while (0);
3626
3627 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3628 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1252; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0); } } while (0); }
while (0)
3629 mqd->cp_hqd_pq_wptr_poll_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1252; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0); } } while (0); }
while (0);
3630 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1253; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0); } } while (0); }
while (0)
3631 mqd->cp_hqd_pq_wptr_poll_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1253; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0); } } while (0); }
while (0);
3632
3633 /* enable the doorbell if requested */
3634 if (ring->use_doorbell) {
3635 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105c)), ((adev->doorbell_index.kiq * 2) << 2), 0
)
3636 (adev->doorbell_index.kiq * 2) << 2)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105c)), ((adev->doorbell_index.kiq * 2) << 2), 0
);
3637 /* If GC has entered CGPG, ringing doorbell > first page
3638 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
3639 * workaround this issue. And this change has to align with firmware
3640 * update.
3641 */
3642 if (check_if_enlarge_doorbell_range(adev))
3643 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105d)), ((adev->doorbell.size - 4)), 0)
3644 (adev->doorbell.size - 4))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105d)), ((adev->doorbell.size - 4)), 0);
3645 else
3646 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105d)), ((adev->doorbell_index.userqueue_end * 2) <<
2), 0)
3647 (adev->doorbell_index.userqueue_end * 2) << 2)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x105d)), ((adev->doorbell_index.userqueue_end * 2) <<
2), 0);
3648 }
3649
3650 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_doorbell_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_doorbell_control), 0); } } while (0); } while
(0)
3651 mqd->cp_hqd_pq_doorbell_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_doorbell_control), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_doorbell_control), 0); } } while (0); } while
(0);
3652
3653 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3654 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_lo), 0); } } while (0); } while (0)
3655 mqd->cp_hqd_pq_wptr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_lo), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_lo), 0); } } while (0); } while (0);
3656 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_hi), 0); } } while (0); } while (0)
3657 mqd->cp_hqd_pq_wptr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_pq_wptr_hi), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_pq_wptr_hi), 0); } } while (0); } while (0);
3658
3659 /* set the vmid for the queue */
3660 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1248; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_vmid), 0); amdgpu_device_wreg(adev
, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev
, (spare_int), (0x1), 0); for (i = 0; i < retries; i++) { u32
tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp & 0x80000000
)) break; udelay(10); } if (i >= retries) printk("\0013" "amdgpu: "
"timeout: rlcg program reg:0x%05x failed !\n", target_reg); }
else { amdgpu_device_wreg(adev, (target_reg), (mqd->cp_hqd_vmid
), 0); } } while (0); } while (0);
3661
3662 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1249; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_persistent_state), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_persistent_state), 0); } } while (0); } while
(0)
3663 mqd->cp_hqd_persistent_state)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1249; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_persistent_state), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_persistent_state), 0); } } while (0); } while
(0);
3664
3665 /* activate the queue */
3666 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1247; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_active), 0); amdgpu_device_wreg(
adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_active), 0); } } while (0); } while (0)
3667 mqd->cp_hqd_active)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1247; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (mqd->cp_hqd_active), 0); amdgpu_device_wreg(
adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (mqd->cp_hqd_active), 0); } } while (0); } while (0);
3668
3669 if (ring->use_doorbell)
3670 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x10b8), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x10b8), 0) & ~0x00000002L) | (1) << 0x1)
, 0);
3671
3672 return 0;
3673}
3674
3675static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3676{
3677 struct amdgpu_device *adev = ring->adev;
3678 int j;
3679
3680 /* disable the queue if it's active */
3681 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1247), 0) & 1) {
3682
3683 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (1), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (1), 0); } } while (0); } while (0);
3684
3685 for (j = 0; j < adev->usec_timeout; j++) {
3686 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1247), 0) & 1))
3687 break;
3688 udelay(1);
3689 }
3690
3691 if (j == AMDGPU_MAX_USEC_TIMEOUT100000) {
3692 DRM_DEBUG("KIQ dequeue request failed.\n")__drm_dbg(DRM_UT_CORE, "KIQ dequeue request failed.\n");
3693
3694 /* Manual disable if dequeue request times out */
3695 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1247; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3696 }
3697
3698 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0)
3699 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125d; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3700 }
3701
3702 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3703 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x125a; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3704 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1249; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3705 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0x40000000), 0); amdgpu_device_wreg(adev, (r1),
((target_reg | 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int
), (0x1), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0x40000000), 0); } } while (0); } while (0);
3706 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x1254; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3707 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x124f; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3708 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127c; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3709 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x127b; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (0), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (0), 0); } } while (0); } while (0);
3710
3711 return 0;
3712}
3713
3714static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3715{
3716 struct amdgpu_device *adev = ring->adev;
3717 struct v9_mqd *mqd = ring->mqd_ptr;
3718 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS8;
3719
3720 gfx_v9_0_kiq_setting(ring);
3721
3722 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3723 /* reset MQD to a clean status */
3724 if (adev->gfx.mec.mqd_backup[mqd_idx])
3725 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(struct v9_mqd_allocation)));
3726
3727 /* reset ring buffer */
3728 ring->wptr = 0;
3729 amdgpu_ring_clear_ring(ring);
3730
3731 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
3732 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3733 gfx_v9_0_kiq_init_register(ring);
3734 soc15_grbm_select(adev, 0, 0, 0, 0);
3735 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
3736 } else {
3737 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct v9_mqd_allocation
)));
3738 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3739 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3740 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
3741 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3742 gfx_v9_0_mqd_init(ring);
3743 gfx_v9_0_kiq_init_register(ring);
3744 soc15_grbm_select(adev, 0, 0, 0, 0);
3745 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
3746
3747 if (adev->gfx.mec.mqd_backup[mqd_idx])
3748 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(struct v9_mqd_allocation)));
3749 }
3750
3751 return 0;
3752}
3753
3754static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3755{
3756 struct amdgpu_device *adev = ring->adev;
3757 struct v9_mqd *mqd = ring->mqd_ptr;
3758 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3759
3760 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3761 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct v9_mqd_allocation
)));
3762 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3763 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3764 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
3765 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3766 gfx_v9_0_mqd_init(ring);
3767 soc15_grbm_select(adev, 0, 0, 0, 0);
3768 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
3769
3770 if (adev->gfx.mec.mqd_backup[mqd_idx])
3771 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(struct v9_mqd_allocation)));
3772 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3773 /* reset MQD to a clean status */
3774 if (adev->gfx.mec.mqd_backup[mqd_idx])
3775 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(struct v9_mqd_allocation)));
3776
3777 /* reset ring buffer */
3778 ring->wptr = 0;
3779 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0)({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((0)); *(volatile typeof(*((atomic64_t *)&adev
->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t *)&
adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; });
3780 amdgpu_ring_clear_ring(ring);
3781 } else {
3782 amdgpu_ring_clear_ring(ring);
3783 }
3784
3785 return 0;
3786}
3787
3788static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3789{
3790 struct amdgpu_ring *ring;
3791 int r;
3792
3793 ring = &adev->gfx.kiq.ring;
3794
3795 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
3796 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
3797 return r;
3798
3799 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3800 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
3801 return r;
3802
3803 gfx_v9_0_kiq_init_queue(ring);
3804 amdgpu_bo_kunmap(ring->mqd_obj);
3805 ring->mqd_ptr = NULL((void *)0);
3806 amdgpu_bo_unreserve(ring->mqd_obj);
3807 ring->sched.ready = true1;
3808 return 0;
3809}
3810
3811static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3812{
3813 struct amdgpu_ring *ring = NULL((void *)0);
3814 int r = 0, i;
3815
3816 gfx_v9_0_cp_compute_enable(adev, true1);
3817
3818 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3819 ring = &adev->gfx.compute_ring[i];
3820
3821 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
3822 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
3823 goto done;
3824 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3825 if (!r) {
3826 r = gfx_v9_0_kcq_init_queue(ring);
3827 amdgpu_bo_kunmap(ring->mqd_obj);
3828 ring->mqd_ptr = NULL((void *)0);
3829 }
3830 amdgpu_bo_unreserve(ring->mqd_obj);
3831 if (r)
3832 goto done;
3833 }
3834
3835 r = amdgpu_gfx_enable_kcq(adev);
3836done:
3837 return r;
3838}
3839
3840static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3841{
3842 int r, i;
3843 struct amdgpu_ring *ring;
3844
3845 if (!(adev->flags & AMD_IS_APU))
3846 gfx_v9_0_enable_gui_idle_interrupt(adev, false0);
3847
3848 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3849 if (adev->asic_type != CHIP_ARCTURUS) {
3850 /* legacy firmware loading */
3851 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3852 if (r)
3853 return r;
3854 }
3855
3856 r = gfx_v9_0_cp_compute_load_microcode(adev);
3857 if (r)
3858 return r;
3859 }
3860
3861 r = gfx_v9_0_kiq_resume(adev);
3862 if (r)
3863 return r;
3864
3865 if (adev->asic_type != CHIP_ARCTURUS) {
3866 r = gfx_v9_0_cp_gfx_resume(adev);
3867 if (r)
3868 return r;
3869 }
3870
3871 r = gfx_v9_0_kcq_resume(adev);
3872 if (r)
3873 return r;
3874
3875 if (adev->asic_type != CHIP_ARCTURUS) {
3876 ring = &adev->gfx.gfx_ring[0];
3877 r = amdgpu_ring_test_helper(ring);
3878 if (r)
3879 return r;
3880 }
3881
3882 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3883 ring = &adev->gfx.compute_ring[i];
3884 amdgpu_ring_test_helper(ring);
3885 }
3886
3887 gfx_v9_0_enable_gui_idle_interrupt(adev, true1);
3888
3889 return 0;
3890}
3891
3892static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
3893{
3894 u32 tmp;
3895
3896 if (adev->asic_type != CHIP_ARCTURUS)
3897 return;
3898
3899 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0b05), 0);
3900 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,(((tmp) & ~0x00000800L) | (0x00000800L & ((adev->df
.hash_status.hash_64k) << 0xb)))
3901 adev->df.hash_status.hash_64k)(((tmp) & ~0x00000800L) | (0x00000800L & ((adev->df
.hash_status.hash_64k) << 0xb)));
3902 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,(((tmp) & ~0x00001000L) | (0x00001000L & ((adev->df
.hash_status.hash_2m) << 0xc)))
3903 adev->df.hash_status.hash_2m)(((tmp) & ~0x00001000L) | (0x00001000L & ((adev->df
.hash_status.hash_2m) << 0xc)));
3904 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,(((tmp) & ~0x00002000L) | (0x00002000L & ((adev->df
.hash_status.hash_1g) << 0xd)))
3905 adev->df.hash_status.hash_1g)(((tmp) & ~0x00002000L) | (0x00002000L & ((adev->df
.hash_status.hash_1g) << 0xd)));
3906 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0b05)), (tmp), 0);
3907}
3908
3909static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool_Bool enable)
3910{
3911 if (adev->asic_type != CHIP_ARCTURUS)
3912 gfx_v9_0_cp_gfx_enable(adev, enable);
3913 gfx_v9_0_cp_compute_enable(adev, enable);
3914}
3915
3916static int gfx_v9_0_hw_init(void *handle)
3917{
3918 int r;
3919 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3920
3921 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
3922 gfx_v9_0_init_golden_registers(adev);
3923
3924 gfx_v9_0_constants_init(adev);
3925
3926 gfx_v9_0_init_tcp_config(adev);
3927
3928 r = adev->gfx.rlc.funcs->resume(adev);
3929 if (r)
3930 return r;
3931
3932 r = gfx_v9_0_cp_resume(adev);
3933 if (r)
3934 return r;
3935
3936 return r;
3937}
3938
3939static int gfx_v9_0_hw_fini(void *handle)
3940{
3941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3942
3943 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3944 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3945 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3946
3947 /* DF freeze and kcq disable will fail */
3948 if (!amdgpu_ras_intr_triggered())
3949 /* disable KCQ to avoid CPC touch memory not valid anymore */
3950 amdgpu_gfx_disable_kcq(adev);
3951
3952 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
3953 gfx_v9_0_cp_gfx_enable(adev, false0);
3954 /* must disable polling for SRIOV when hw finished, otherwise
3955 * CPC engine may still keep fetching WB address which is already
3956 * invalid after sw finished and trigger DMAR reading error in
3957 * hypervisor side.
3958 */
3959 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1083), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1083), 0) & ~0x80000000L) | (0) << 0x1f
), 0);
3960 return 0;
3961 }
3962
3963 /* Use deinitialize sequence from CAIL when unbinding device from driver,
3964 * otherwise KIQ is hanging when binding back
3965 */
3966 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3967 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
3968 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3969 adev->gfx.kiq.ring.pipe,
3970 adev->gfx.kiq.ring.queue, 0);
3971 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3972 soc15_grbm_select(adev, 0, 0, 0, 0);
3973 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
3974 }
3975
3976 gfx_v9_0_cp_enable(adev, false0);
3977 adev->gfx.rlc.funcs->stop(adev);
3978
3979 return 0;
3980}
3981
3982static int gfx_v9_0_suspend(void *handle)
3983{
3984 return gfx_v9_0_hw_fini(handle);
3985}
3986
3987static int gfx_v9_0_resume(void *handle)
3988{
3989 return gfx_v9_0_hw_init(handle);
3990}
3991
3992static bool_Bool gfx_v9_0_is_idle(void *handle)
3993{
3994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3995
3996 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0004), 0)) & 0x80000000L) >> 0x1f)
3997 GRBM_STATUS, GUI_ACTIVE)(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0004), 0)) & 0x80000000L) >> 0x1f))
3998 return false0;
3999 else
4000 return true1;
4001}
4002
4003static int gfx_v9_0_wait_for_idle(void *handle)
4004{
4005 unsigned i;
4006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4007
4008 for (i = 0; i < adev->usec_timeout; i++) {
4009 if (gfx_v9_0_is_idle(handle))
4010 return 0;
4011 udelay(1);
4012 }
4013 return -ETIMEDOUT60;
4014}
4015
4016static int gfx_v9_0_soft_reset(void *handle)
4017{
4018 u32 grbm_soft_reset = 0;
4019 u32 tmp;
4020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4021
4022 /* GRBM_STATUS */
4023 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0004), 0);
4024 if (tmp & (GRBM_STATUS__PA_BUSY_MASK0x02000000L | GRBM_STATUS__SC_BUSY_MASK0x01000000L |
4025 GRBM_STATUS__BCI_BUSY_MASK0x00800000L | GRBM_STATUS__SX_BUSY_MASK0x00100000L |
4026 GRBM_STATUS__TA_BUSY_MASK0x00004000L | GRBM_STATUS__VGT_BUSY_MASK0x00020000L |
4027 GRBM_STATUS__DB_BUSY_MASK0x04000000L | GRBM_STATUS__CB_BUSY_MASK0x40000000L |
4028 GRBM_STATUS__GDS_BUSY_MASK0x00008000L | GRBM_STATUS__SPI_BUSY_MASK0x00400000L |
4029 GRBM_STATUS__IA_BUSY_MASK0x00080000L | GRBM_STATUS__IA_BUSY_NO_DMA_MASK0x00040000L)) {
4030 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
4031 GRBM_SOFT_RESET, SOFT_RESET_CP, 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
4032 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)))
4033 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1)(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)));
4034 }
4035
4036 if (tmp & (GRBM_STATUS__CP_BUSY_MASK0x20000000L | GRBM_STATUS__CP_COHERENCY_BUSY_MASK0x10000000L)) {
4037 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
4038 GRBM_SOFT_RESET, SOFT_RESET_CP, 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
4039 }
4040
4041 /* GRBM_STATUS2 */
4042 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0002), 0);
4043 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)(((tmp) & 0x01000000L) >> 0x18))
4044 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
4045 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
4046
4047
4048 if (grbm_soft_reset) {
4049 /* stop the rlc */
4050 adev->gfx.rlc.funcs->stop(adev);
4051
4052 if (adev->asic_type != CHIP_ARCTURUS)
4053 /* Disable GFX parsing/prefetching */
4054 gfx_v9_0_cp_gfx_enable(adev, false0);
4055
4056 /* Disable MEC parsing/prefetching */
4057 gfx_v9_0_cp_compute_enable(adev, false0);
4058
4059 if (grbm_soft_reset) {
4060 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0008), 0);
4061 tmp |= grbm_soft_reset;
4062 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
4063 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0008)), (tmp), 0);
4064 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0008), 0);
4065
4066 udelay(50);
4067
4068 tmp &= ~grbm_soft_reset;
4069 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0008)), (tmp), 0);
4070 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0008), 0);
4071 }
4072
4073 /* Wait a little for things to settle down */
4074 udelay(50);
4075 }
4076 return 0;
4077}
4078
4079static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev)
4080{
4081 signed long r, cnt = 0;
4082 unsigned long flags;
4083 uint32_t seq, reg_val_offs = 0;
4084 uint64_t value = 0;
4085 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4086 struct amdgpu_ring *ring = &kiq->ring;
4087
4088 BUG_ON(!ring->funcs->emit_rreg)((!(!ring->funcs->emit_rreg)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 4088, "!(!ring->funcs->emit_rreg)"
));
4089
4090 spin_lock_irqsave(&kiq->ring_lock, flags)do { flags = 0; mtx_enter(&kiq->ring_lock); } while (0
);
4091 if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
4092 pr_err("critical bug! too many kiq readers\n")printk("\0013" "amdgpu: " "critical bug! too many kiq readers\n"
);
4093 goto failed_unlock;
4094 }
4095 amdgpu_ring_alloc(ring, 32);
4096 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)((3 << 30) | (((0x40) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
4097 amdgpu_ring_write(ring, 9 | /* src: register*/
4098 (5 << 8) | /* dst: memory */
4099 (1 << 16) | /* count sel */
4100 (1 << 20)); /* write confirm */
4101 amdgpu_ring_write(ring, 0);
4102 amdgpu_ring_write(ring, 0);
4103 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +((u32)(adev->wb.gpu_addr + reg_val_offs * 4))
4104 reg_val_offs * 4)((u32)(adev->wb.gpu_addr + reg_val_offs * 4)));
4105 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16))
4106 reg_val_offs * 4)((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16)));
4107 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT5000);
4108 if (r)
4109 goto failed_undo;
4110
4111 amdgpu_ring_commit(ring);
4112 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
4113
4114 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT5000);
4115
4116 /* don't wait anymore for gpu reset case because this way may
4117 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
4118 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
4119 * never return if we keep waiting in virt_kiq_rreg, which cause
4120 * gpu_recover() hang there.
4121 *
4122 * also don't wait anymore for IRQ context
4123 * */
4124 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()in_irq()))
4125 goto failed_kiq_read;
4126
4127 might_sleep()assertwaitok();
4128 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY80) {
4129 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL)mdelay(5);
4130 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT5000);
4131 }
4132
4133 if (cnt > MAX_KIQ_REG_TRY80)
4134 goto failed_kiq_read;
4135
4136 mb()do { __asm volatile("mfence" ::: "memory"); } while (0);
4137 value = (uint64_t)adev->wb.wb[reg_val_offs] |
4138 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL;
4139 amdgpu_device_wb_free(adev, reg_val_offs);
4140 return value;
4141
4142failed_undo:
4143 amdgpu_ring_undo(ring);
4144failed_unlock:
4145 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
4146failed_kiq_read:
4147 if (reg_val_offs)
4148 amdgpu_device_wb_free(adev, reg_val_offs);
4149 pr_err("failed to read gpu clock\n")printk("\0013" "amdgpu: " "failed to read gpu clock\n");
4150 return ~0;
4151}
4152
4153static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4154{
4155 uint64_t clock, clock_lo, clock_hi, hi_check;
4156
4157 switch (adev->asic_type) {
4158 case CHIP_RENOIR:
4159 preempt_disable();
4160 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0025), (1<<1));
4161 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0026), (1<<1));
4162 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0025), (1<<1));
4163 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
4164 * roughly every 42 seconds.
4165 */
4166 if (hi_check != clock_hi) {
4167 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0026), (1<<1));
4168 clock_hi = hi_check;
4169 }
4170 preempt_enable();
4171 clock = clock_lo | (clock_hi << 32ULL);
4172 break;
4173 default:
4174 amdgpu_gfx_off_ctrl(adev, false0);
4175 mutex_lock(&adev->gfx.gpu_clock_mutex)rw_enter_write(&adev->gfx.gpu_clock_mutex);
4176 if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)((adev)->virt.caps & (1 << 4))) {
4177 clock = gfx_v9_0_kiq_read_clock(adev);
4178 } else {
4179 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c26)), (1), 0);
4180 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c24), 0) |
4181 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c25), 0) << 32ULL);
4182 }
4183 mutex_unlock(&adev->gfx.gpu_clock_mutex)rw_exit_write(&adev->gfx.gpu_clock_mutex);
4184 amdgpu_gfx_off_ctrl(adev, true1);
4185 break;
4186 }
4187 return clock;
4188}
4189
4190static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4191 uint32_t vmid,
4192 uint32_t gds_base, uint32_t gds_size,
4193 uint32_t gws_base, uint32_t gws_size,
4194 uint32_t oa_base, uint32_t oa_size)
4195{
4196 struct amdgpu_device *adev = ring->adev;
4197
4198 /* GDS Base */
4199 gfx_v9_0_write_data_to_reg(ring, 0, false0,
4200 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x1300) + 2 * vmid,
4201 gds_base);
4202
4203 /* GDS Size */
4204 gfx_v9_0_write_data_to_reg(ring, 0, false0,
4205 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x1301) + 2 * vmid,
4206 gds_size);
4207
4208 /* GWS */
4209 gfx_v9_0_write_data_to_reg(ring, 0, false0,
4210 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x1320) + vmid,
4211 gws_size << GDS_GWS_VMID0__SIZE__SHIFT0x10 | gws_base);
4212
4213 /* OA */
4214 gfx_v9_0_write_data_to_reg(ring, 0, false0,
4215 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x1330) + vmid,
4216 (1 << (oa_size + oa_base)) - (1 << oa_base));
4217}
4218
4219static const u32 vgpr_init_compute_shader[] =
4220{
4221 0xb07c0000, 0xbe8000ff,
4222 0x000000f8, 0xbf110800,
4223 0x7e000280, 0x7e020280,
4224 0x7e040280, 0x7e060280,
4225 0x7e080280, 0x7e0a0280,
4226 0x7e0c0280, 0x7e0e0280,
4227 0x80808800, 0xbe803200,
4228 0xbf84fff5, 0xbf9c0000,
4229 0xd28c0001, 0x0001007f,
4230 0xd28d0001, 0x0002027e,
4231 0x10020288, 0xb8810904,
4232 0xb7814000, 0xd1196a01,
4233 0x00000301, 0xbe800087,
4234 0xbefc00c1, 0xd89c4000,
4235 0x00020201, 0xd89cc080,
4236 0x00040401, 0x320202ff,
4237 0x00000800, 0x80808100,
4238 0xbf84fff8, 0x7e020280,
4239 0xbf810000, 0x00000000,
4240};
4241
4242static const u32 sgpr_init_compute_shader[] =
4243{
4244 0xb07c0000, 0xbe8000ff,
4245 0x0000005f, 0xbee50080,
4246 0xbe812c65, 0xbe822c65,
4247 0xbe832c65, 0xbe842c65,
4248 0xbe852c65, 0xb77c0005,
4249 0x80808500, 0xbf84fff8,
4250 0xbe800080, 0xbf810000,
4251};
4252
4253static const u32 vgpr_init_compute_shader_arcturus[] = {
4254 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080,
4255 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080,
4256 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080,
4257 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080,
4258 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080,
4259 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080,
4260 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080,
4261 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080,
4262 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080,
4263 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080,
4264 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080,
4265 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080,
4266 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080,
4267 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080,
4268 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080,
4269 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080,
4270 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080,
4271 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080,
4272 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080,
4273 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080,
4274 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080,
4275 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080,
4276 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080,
4277 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080,
4278 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080,
4279 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080,
4280 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080,
4281 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080,
4282 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080,
4283 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080,
4284 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080,
4285 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080,
4286 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080,
4287 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080,
4288 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080,
4289 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080,
4290 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080,
4291 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080,
4292 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080,
4293 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080,
4294 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080,
4295 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080,
4296 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080,
4297 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080,
4298 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080,
4299 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080,
4300 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080,
4301 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080,
4302 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080,
4303 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080,
4304 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080,
4305 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080,
4306 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080,
4307 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080,
4308 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080,
4309 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080,
4310 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080,
4311 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080,
4312 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080,
4313 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080,
4314 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080,
4315 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080,
4316 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080,
4317 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080,
4318 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080,
4319 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080,
4320 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080,
4321 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080,
4322 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080,
4323 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080,
4324 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080,
4325 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080,
4326 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080,
4327 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080,
4328 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080,
4329 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080,
4330 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080,
4331 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080,
4332 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080,
4333 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080,
4334 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080,
4335 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080,
4336 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080,
4337 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080,
4338 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080,
4339 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a,
4340 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280,
4341 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000,
4342 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904,
4343 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000,
4344 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a,
4345 0xbf84fff8, 0xbf810000,
4346};
4347
4348/* When below register arrays changed, please update gpr_reg_size,
4349 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
4350 to cover all gfx9 ASICs */
4351static const struct soc15_reg_entry vgpr_init_regs[] = {
4352 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 },
4353 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 },
4354 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 4 },
4355 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 },
4356 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x3f },
4357 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x400000 }, /* 64KB LDS */
4358 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0xffffffff },
4359 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0xffffffff },
4360 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0xffffffff },
4361 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0xffffffff },
4362 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0xffffffff },
4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0xffffffff },
4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0xffffffff },
4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0xffffffff },
4366};
4367
4368static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = {
4369 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 },
4370 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 },
4371 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 4 },
4372 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 },
4373 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0xbf },
4374 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x400000 }, /* 64KB LDS */
4375 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0xffffffff },
4376 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0xffffffff },
4377 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0xffffffff },
4378 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0xffffffff },
4379 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0xffffffff },
4380 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0xffffffff },
4381 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0xffffffff },
4382 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0xffffffff },
4383};
4384
4385static const struct soc15_reg_entry sgpr1_init_regs[] = {
4386 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 },
4387 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 },
4388 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 8 },
4389 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 },
4390 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x240 }, /* (80 GPRS) */
4391 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x0 },
4392 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0x000000ff },
4393 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0x000000ff },
4394 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0x000000ff },
4395 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0x000000ff },
4396 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0x000000ff },
4397 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0x000000ff },
4398 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0x000000ff },
4399 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0x000000ff },
4400};
4401
4402static const struct soc15_reg_entry sgpr2_init_regs[] = {
4403 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 },
4404 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 },
4405 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 8 },
4406 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 },
4407 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x240 }, /* (80 GPRS) */
4408 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x0 },
4409 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0x0000ff00 },
4410 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0x0000ff00 },
4411 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0x0000ff00 },
4412 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0x0000ff00 },
4413 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0x0000ff00 },
4414 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0x0000ff00 },
4415 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0x0000ff00 },
4416 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0x0000ff00 },
4417};
4418
4419static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = {
4420 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT)GC_HWIP, 0, 0, 0x118e, 0, 1, 1},
4421 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT)GC_HWIP, 0, 0, 0x118f, 0, 1, 1},
4422 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT)GC_HWIP, 0, 0, 0x118a, 0, 1, 1},
4423 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x1189, 0, 1, 1},
4424 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT)GC_HWIP, 0, 0, 0x118d, 0, 1, 1},
4425 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x118b, 0, 1, 1},
4426 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT)GC_HWIP, 0, 0, 0x1192, 0, 1, 1},
4427 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT)GC_HWIP, 0, 0, 0x1193, 0, 1, 1},
4428 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT)GC_HWIP, 0, 0, 0x1191, 0, 1, 1},
4429 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT)GC_HWIP, 0, 0, 0x05c5, 0, 1, 1},
4430 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT)GC_HWIP, 0, 0, 0x05c6, 0, 1, 1},
4431 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED)GC_HWIP, 0, 0, 0x05c7, 0, 1, 1},
4432 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT)GC_HWIP, 0, 0, 0x0445, 0, 4, 1},
4433 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2, 0, 4, 6},
4434 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT)GC_HWIP, 0, 0, 0x03a4, 0, 4, 16},
4435 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO)GC_HWIP, 0, 0, 0x03a5, 0, 4, 16},
4436 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT)GC_HWIP, 0, 0, 0x03a3, 0, 4, 16},
4437 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82, 0, 1, 16},
4438 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT)GC_HWIP, 0, 0, 0x12b1, 0, 4, 16},
4439 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT)GC_HWIP, 0, 0, 0x0b17, 0, 4, 16},
4440 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18, 0, 4, 16},
4441 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT)GC_HWIP, 0, 0, 0x052e, 0, 4, 16},
4442 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c, 0, 4, 6},
4443 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6, 0, 4, 16},
4444 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586, 0, 4, 16},
4445 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT)GC_HWIP, 0, 0, 0x05cb, 0, 1, 1},
4446 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc, 0, 1, 1},
4447 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706, 0, 1, 32},
4448 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707, 0, 1, 32},
4449 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT)GC_HWIP, 0, 0, 0x0b60, 0, 1, 72},
4450 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83, 0, 1, 16},
4451 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT)GC_HWIP, 0, 0, 0x0bc5, 0, 1, 2},
4452 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d, 0, 4, 6},
4453};
4454
4455static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
4456{
4457 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4458 int i, r;
4459
4460 /* only support when RAS is enabled */
4461 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4462 return 0;
4463
4464 r = amdgpu_ring_alloc(ring, 7);
4465 if (r) {
4466 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",__drm_err("amdgpu: GDS workarounds failed to lock ring %s (%d).\n"
, ring->name, r)
4467 ring->name, r)__drm_err("amdgpu: GDS workarounds failed to lock ring %s (%d).\n"
, ring->name, r);
4468 return r;
4469 }
4470
4471 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1300)), (0x00000000), 0);
4472 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1301)), (adev->gds.gds_size), 0);
4473
4474 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)((3 << 30) | (((0x50) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
4475 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC(1 << 31) |
4476 PACKET3_DMA_DATA_DST_SEL(1)((1) << 20) |
4477 PACKET3_DMA_DATA_SRC_SEL(2)((2) << 29) |
4478 PACKET3_DMA_DATA_ENGINE(0)((0) << 0)));
4479 amdgpu_ring_write(ring, 0);
4480 amdgpu_ring_write(ring, 0);
4481 amdgpu_ring_write(ring, 0);
4482 amdgpu_ring_write(ring, 0);
4483 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT(1 << 30) |
4484 adev->gds.gds_size);
4485
4486 amdgpu_ring_commit(ring);
4487
4488 for (i = 0; i < adev->usec_timeout; i++) {
4489 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring))
4490 break;
4491 udelay(1);
4492 }
4493
4494 if (i >= adev->usec_timeout)
4495 r = -ETIMEDOUT60;
4496
4497 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1301)), (0x00000000), 0);
4498
4499 return r;
4500}
4501
4502static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
4503{
4504 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4505 struct amdgpu_ib ib;
4506 struct dma_fence *f = NULL((void *)0);
4507 int r, i;
4508 unsigned total_size, vgpr_offset, sgpr_offset;
4509 u64 gpu_addr;
4510
4511 int compute_dim_x = adev->gfx.config.max_shader_engines *
4512 adev->gfx.config.max_cu_per_sh *
4513 adev->gfx.config.max_sh_per_se;
4514 int sgpr_work_group_size = 5;
4515 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6;
4516 int vgpr_init_shader_size;
4517 const u32 *vgpr_init_shader_ptr;
4518 const struct soc15_reg_entry *vgpr_init_regs_ptr;
4519
4520 /* only support when RAS is enabled */
4521 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4522 return 0;
4523
4524 /* bail if the compute ring is not ready */
4525 if (!ring->sched.ready)
4526 return 0;
4527
4528 if (adev->asic_type == CHIP_ARCTURUS) {
4529 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
4530 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
4531 vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
4532 } else {
4533 vgpr_init_shader_ptr = vgpr_init_compute_shader;
4534 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader);
4535 vgpr_init_regs_ptr = vgpr_init_regs;
4536 }
4537
4538 total_size =
4539 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */
4540 total_size +=
4541 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */
4542 total_size +=
4543 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */
4544 total_size = roundup2(total_size, 256)(((total_size) + ((256) - 1)) & (~((__typeof(total_size))
(256) - 1)));
4545 vgpr_offset = total_size;
4546 total_size += roundup2(vgpr_init_shader_size, 256)(((vgpr_init_shader_size) + ((256) - 1)) & (~((__typeof(vgpr_init_shader_size
))(256) - 1)));
4547 sgpr_offset = total_size;
4548 total_size += sizeof(sgpr_init_compute_shader);
4549
4550 /* allocate an indirect buffer to put the commands in */
4551 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
4552 r = amdgpu_ib_get(adev, NULL((void *)0), total_size,
4553 AMDGPU_IB_POOL_DIRECT, &ib);
4554 if (r) {
4555 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r)__drm_err("amdgpu: failed to get ib (%d).\n", r);
4556 return r;
4557 }
4558
4559 /* load the compute shaders */
4560 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)
4561 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i];
4562
4563 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader)(sizeof((sgpr_init_compute_shader)) / sizeof((sgpr_init_compute_shader
)[0])); i++)
4564 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
4565
4566 /* init the ib length to 0 */
4567 ib.length_dw = 0;
4568
4569 /* VGPR */
4570 /* write the register state for the compute dispatch */
4571 for (i = 0; i < gpr_reg_size; i++) {
4572 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) &
0x3FFF) << 16);
4573 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])(adev->reg_offset[vgpr_init_regs_ptr[i].hwip][vgpr_init_regs_ptr
[i].inst][vgpr_init_regs_ptr[i].seg] + vgpr_init_regs_ptr[i].
reg_offset)
4574 - PACKET3_SET_SH_REG_START0x00002c00;
4575 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;
4576 }
4577 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4578 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
4579 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
4580 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c)
4581 - PACKET3_SET_SH_REG_START0x00002c00;
4582 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
4583 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
4584
4585 /* write dispatch packet */
4586 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
4587 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */
4588 ib.ptr[ib.length_dw++] = 1; /* y */
4589 ib.ptr[ib.length_dw++] = 1; /* z */
4590 ib.ptr[ib.length_dw++] =
4591 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0
)));
4592
4593 /* write CS partial flush packet */
4594 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) &
0x3FFF) << 16);
4595 ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8);
4596
4597 /* SGPR1 */
4598 /* write the register state for the compute dispatch */
4599 for (i = 0; i < gpr_reg_size; i++) {
4600 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) &
0x3FFF) << 16);
4601 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])(adev->reg_offset[sgpr1_init_regs[i].hwip][sgpr1_init_regs
[i].inst][sgpr1_init_regs[i].seg] + sgpr1_init_regs[i].reg_offset
)
4602 - PACKET3_SET_SH_REG_START0x00002c00;
4603 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4604 }
4605 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4606 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4607 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
4608 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c)
4609 - PACKET3_SET_SH_REG_START0x00002c00;
4610 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
4611 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
4612
4613 /* write dispatch packet */
4614 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
4615 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4616 ib.ptr[ib.length_dw++] = 1; /* y */
4617 ib.ptr[ib.length_dw++] = 1; /* z */
4618 ib.ptr[ib.length_dw++] =
4619 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0
)));
4620
4621 /* write CS partial flush packet */
4622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) &
0x3FFF) << 16);
4623 ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8);
4624
4625 /* SGPR2 */
4626 /* write the register state for the compute dispatch */
4627 for (i = 0; i < gpr_reg_size; i++) {
4628 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) &
0x3FFF) << 16);
4629 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])(adev->reg_offset[sgpr2_init_regs[i].hwip][sgpr2_init_regs
[i].inst][sgpr2_init_regs[i].seg] + sgpr2_init_regs[i].reg_offset
)
4630 - PACKET3_SET_SH_REG_START0x00002c00;
4631 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
4632 }
4633 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4634 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4635 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
4636 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c)
4637 - PACKET3_SET_SH_REG_START0x00002c00;
4638 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
4639 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
4640
4641 /* write dispatch packet */
4642 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
4643 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4644 ib.ptr[ib.length_dw++] = 1; /* y */
4645 ib.ptr[ib.length_dw++] = 1; /* z */
4646 ib.ptr[ib.length_dw++] =
4647 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0
)));
4648
4649 /* write CS partial flush packet */
4650 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) &
0x3FFF) << 16);
4651 ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8);
4652
4653 /* shedule the ib on the ring */
4654 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
4655 if (r) {
4656 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r)__drm_err("amdgpu: ib submit failed (%d).\n", r);
4657 goto fail;
4658 }
4659
4660 /* wait for the GPU to finish processing the IB */
4661 r = dma_fence_wait(f, false0);
4662 if (r) {
4663 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r)__drm_err("amdgpu: fence wait failed (%d).\n", r);
4664 goto fail;
4665 }
4666
4667fail:
4668 amdgpu_ib_free(adev, &ib, NULL((void *)0));
4669 dma_fence_put(f);
4670
4671 return r;
4672}
4673
4674static int gfx_v9_0_early_init(void *handle)
4675{
4676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4677
4678 if (adev->asic_type == CHIP_ARCTURUS)
4679 adev->gfx.num_gfx_rings = 0;
4680 else
4681 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS1;
4682 adev->gfx.num_compute_rings = amdgpu_num_kcq;
4683 gfx_v9_0_set_kiq_pm4_funcs(adev);
4684 gfx_v9_0_set_ring_funcs(adev);
4685 gfx_v9_0_set_irq_funcs(adev);
4686 gfx_v9_0_set_gds_init(adev);
4687 gfx_v9_0_set_rlc_funcs(adev);
4688
4689 return 0;
4690}
4691
4692static int gfx_v9_0_ecc_late_init(void *handle)
4693{
4694 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4695 int r;
4696
4697 /*
4698 * Temp workaround to fix the issue that CP firmware fails to
4699 * update read pointer when CPDMA is writing clearing operation
4700 * to GDS in suspend/resume sequence on several cards. So just
4701 * limit this operation in cold boot sequence.
4702 */
4703 if (!adev->in_suspend) {
4704 r = gfx_v9_0_do_edc_gds_workarounds(adev);
4705 if (r)
4706 return r;
4707 }
4708
4709 /* requires IBs so do in late init after IB pool is initialized */
4710 r = gfx_v9_0_do_edc_gpr_workarounds(adev);
4711 if (r)
4712 return r;
4713
4714 if (adev->gfx.funcs &&
4715 adev->gfx.funcs->reset_ras_error_count)
4716 adev->gfx.funcs->reset_ras_error_count(adev);
4717
4718 r = amdgpu_gfx_ras_late_init(adev);
4719 if (r)
4720 return r;
4721
4722 return 0;
4723}
4724
4725static int gfx_v9_0_late_init(void *handle)
4726{
4727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4728 int r;
4729
4730 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4731 if (r)
4732 return r;
4733
4734 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4735 if (r)
4736 return r;
4737
4738 r = gfx_v9_0_ecc_late_init(handle);
4739 if (r)
4740 return r;
4741
4742 return 0;
4743}
4744
4745static bool_Bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
4746{
4747 uint32_t rlc_setting;
4748
4749 /* if RLC is not enabled, do nothing */
4750 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), 0);
4751 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK0x00000001L))
4752 return false0;
4753
4754 return true1;
4755}
4756
4757static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
4758{
4759 uint32_t data;
4760 unsigned i;
4761
4762 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
4763 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT0x1);
4764 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c05)), (data), 0);
4765
4766 /* wait for RLC_SAFE_MODE */
4767 for (i = 0; i < adev->usec_timeout; i++) {
4768 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c05), 0)) & 0x00000001L) >> 0x0))
4769 break;
4770 udelay(1);
4771 }
4772}
4773
4774static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
4775{
4776 uint32_t data;
4777
4778 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
4779 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c05)), (data), 0);
4780}
4781
4782static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
4783 bool_Bool enable)
4784{
4785 amdgpu_gfx_rlc_enter_safe_mode(adev);
4786
4787 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG(1 << 0)) && enable) {
4788 gfx_v9_0_enable_gfx_cg_power_gating(adev, true1);
4789 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE(1 << 12))
4790 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true1);
4791 } else {
4792 gfx_v9_0_enable_gfx_cg_power_gating(adev, false0);
4793 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE(1 << 12))
4794 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false0);
4795 }
4796
4797 amdgpu_gfx_rlc_exit_safe_mode(adev);
4798}
4799
4800static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
4801 bool_Bool enable)
4802{
4803 /* TODO: double check if we need to perform under safe mode */
4804 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
4805
4806 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG(1 << 1)) && enable)
4807 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true1);
4808 else
4809 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false0);
4810
4811 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG(1 << 2)) && enable)
4812 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true1);
4813 else
4814 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false0);
4815
4816 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
4817}
4818
4819static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4820 bool_Bool enable)
4821{
4822 uint32_t data, def;
4823
4824 amdgpu_gfx_rlc_enter_safe_mode(adev);
4825
4826 /* It is disabled by HW by default */
4827 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG(1 << 0))) {
4828 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4829 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
4830
4831 if (adev->asic_type != CHIP_VEGA12)
4832 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK0x00000001L;
4833
4834 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
4835 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
4836 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L);
4837
4838 /* only for Vega10 & Raven1 */
4839 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L;
4840
4841 if (def != data)
4842 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
4843
4844 /* MGLS is a global flag to control all MGLS in GFX */
4845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS(1 << 1)) {
4846 /* 2 - RLC memory Light sleep */
4847 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS(1 << 7)) {
4848 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c06), 0);
4849 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
4850 if (def != data)
4851 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c06)), (data), 0);
4852 }
4853 /* 3 - CP memory Light sleep */
4854 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS(1 << 6)) {
4855 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1079), 0);
4856 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
4857 if (def != data)
4858 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1079)), (data), 0);
4859 }
4860 }
4861 } else {
4862 /* 1 - MGCG_OVERRIDE */
4863 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
4864
4865 if (adev->asic_type != CHIP_VEGA12)
4866 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK0x00000001L;
4867
4868 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L |
4869 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
4870 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
4871 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L);
4872
4873 if (def != data)
4874 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
4875
4876 /* 2 - disable MGLS in RLC */
4877 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c06), 0);
4878 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L) {
4879 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
4880 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c06)), (data), 0);
4881 }
4882
4883 /* 3 - disable MGLS in CP */
4884 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1079), 0);
4885 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L) {
4886 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
4887 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1079)), (data), 0);
4888 }
4889 }
4890
4891 amdgpu_gfx_rlc_exit_safe_mode(adev);
4892}
4893
4894static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
4895 bool_Bool enable)
4896{
4897 uint32_t data, def;
4898
4899 if (adev->asic_type == CHIP_ARCTURUS)
4900 return;
4901
4902 amdgpu_gfx_rlc_enter_safe_mode(adev);
4903
4904 /* Enable 3D CGCG/CGLS */
4905 if (enable) {
4906 /* write cmd to clear cgcg/cgls ov */
4907 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
4908 /* unset CGCG override */
4909 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK0x00000080L;
4910 /* update CGCG and CGLS override bits */
4911 if (def != data)
4912 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
4913
4914 /* enable 3Dcgcg FSM(0x0000363f) */
4915 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4cc5), 0);
4916
4917 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1 << 20))
4918 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
4919 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L;
4920 else
4921 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8;
4922
4923 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS(1 << 21))
4924 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
4925 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L;
4926 if (def != data)
4927 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cc5)), (data), 0);
4928
4929 /* set IDLE_POLL_COUNT(0x00900100) */
4930 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x01c2), 0);
4931 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
4932 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
4933 if (def != data)
4934 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x01c2)), (data), 0);
4935 } else {
4936 /* Disable CGCG/CGLS */
4937 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4cc5), 0);
4938 /* disable cgcg, cgls should be disabled */
4939 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L |
4940 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L);
4941 /* disable cgcg and cgls in FSM */
4942 if (def != data)
4943 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cc5)), (data), 0);
4944 }
4945
4946 amdgpu_gfx_rlc_exit_safe_mode(adev);
4947}
4948
4949static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4950 bool_Bool enable)
4951{
4952 uint32_t def, data;
4953
4954 amdgpu_gfx_rlc_enter_safe_mode(adev);
4955
4956 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG(1 << 2))) {
4957 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
4958 /* unset CGCG override */
4959 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK0x00000008L;
4960 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1 << 3))
4961 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK0x00000010L;
4962 else
4963 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK0x00000010L;
4964 /* update CGCG and CGLS override bits */
4965 if (def != data)
4966 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
4967
4968 /* enable cgcg FSM(0x0000363F) */
4969 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c49), 0);
4970
4971 if (adev->asic_type == CHIP_ARCTURUS)
4972 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
4973 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L;
4974 else
4975 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
4976 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L;
4977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1 << 3))
4978 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
4979 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L;
4980 if (def != data)
4981 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (data), 0);
4982
4983 /* set IDLE_POLL_COUNT(0x00900100) */
4984 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x01c2), 0);
4985 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
4986 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
4987 if (def != data)
4988 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x01c2)), (data), 0);
4989 } else {
4990 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c49), 0);
4991 /* reset CGCG/CGLS bits */
4992 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L);
4993 /* disable cgcg and cgls in FSM */
4994 if (def != data)
4995 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (data), 0);
4996 }
4997
4998 amdgpu_gfx_rlc_exit_safe_mode(adev);
4999}
5000
5001static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5002 bool_Bool enable)
5003{
5004 if (enable) {
5005 /* CGCG/CGLS should be enabled after MGCG/MGLS
5006 * === MGCG + MGLS ===
5007 */
5008 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
5009 /* === CGCG /CGLS for GFX 3D Only === */
5010 gfx_v9_0_update_3d_clock_gating(adev, enable);
5011 /* === CGCG + CGLS === */
5012 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
5013 } else {
5014 /* CGCG/CGLS should be disabled before MGCG/MGLS
5015 * === CGCG + CGLS ===
5016 */
5017 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
5018 /* === CGCG /CGLS for GFX 3D Only === */
5019 gfx_v9_0_update_3d_clock_gating(adev, enable);
5020 /* === MGCG + MGLS === */
5021 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
5022 }
5023 return 0;
5024}
5025
5026static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5027{
5028 u32 reg, data;
5029
5030 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL)(adev->reg_offset[GC_HWIP][0][1] + 0x4c71);
5031 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
5032 data = RREG32_NO_KIQ(reg)amdgpu_device_rreg(adev, (reg), (1<<1));
5033 else
5034 data = RREG32(reg)amdgpu_device_rreg(adev, (reg), 0);
5035
5036 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL;
5037 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT0x0;
5038
5039 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
5040 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c71)), (data), (1<<1));
5041 else
5042 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c71)), (data), 0);
5043}
5044
5045static bool_Bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,
5046 uint32_t offset,
5047 struct soc15_reg_rlcg *entries, int arr_size)
5048{
5049 int i;
5050 uint32_t reg;
5051
5052 if (!entries)
5053 return false0;
5054
5055 for (i = 0; i < arr_size; i++) {
5056 const struct soc15_reg_rlcg *entry;
5057
5058 entry = &entries[i];
5059 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
5060 if (offset == reg)
5061 return true1;
5062 }
5063
5064 return false0;
5065}
5066
5067static bool_Bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
5068{
5069 return gfx_v9_0_check_rlcg_range(adev, offset,
5070 (void *)rlcg_access_gc_9_0,
5071 ARRAY_SIZE(rlcg_access_gc_9_0)(sizeof((rlcg_access_gc_9_0)) / sizeof((rlcg_access_gc_9_0)[0
])));
5072}
5073
5074static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
5075 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
5076 .set_safe_mode = gfx_v9_0_set_safe_mode,
5077 .unset_safe_mode = gfx_v9_0_unset_safe_mode,
5078 .init = gfx_v9_0_rlc_init,
5079 .get_csb_size = gfx_v9_0_get_csb_size,
5080 .get_csb_buffer = gfx_v9_0_get_csb_buffer,
5081 .get_cp_table_num = gfx_v9_0_cp_jump_table_num,
5082 .resume = gfx_v9_0_rlc_resume,
5083 .stop = gfx_v9_0_rlc_stop,
5084 .reset = gfx_v9_0_rlc_reset,
5085 .start = gfx_v9_0_rlc_start,
5086 .update_spm_vmid = gfx_v9_0_update_spm_vmid,
5087 .rlcg_wreg = gfx_v9_0_rlcg_wreg,
5088 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
5089};
5090
5091static int gfx_v9_0_set_powergating_state(void *handle,
5092 enum amd_powergating_state state)
5093{
5094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5095 bool_Bool enable = (state == AMD_PG_STATE_GATE);
5096
5097 switch (adev->asic_type) {
5098 case CHIP_RAVEN:
5099 case CHIP_RENOIR:
5100 if (!enable)
5101 amdgpu_gfx_off_ctrl(adev, false0);
5102
5103 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7)) {
5104 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true1);
5105 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true1);
5106 } else {
5107 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false0);
5108 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false0);
5109 }
5110
5111 if (adev->pg_flags & AMD_PG_SUPPORT_CP(1 << 5))
5112 gfx_v9_0_enable_cp_power_gating(adev, true1);
5113 else
5114 gfx_v9_0_enable_cp_power_gating(adev, false0);
5115
5116 /* update gfx cgpg state */
5117 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
5118
5119 /* update mgcg state */
5120 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5121
5122 if (enable)
5123 amdgpu_gfx_off_ctrl(adev, true1);
5124 break;
5125 case CHIP_VEGA12:
5126 amdgpu_gfx_off_ctrl(adev, enable);
5127 break;
5128 default:
5129 break;
5130 }
5131
5132 return 0;
5133}
5134
5135static int gfx_v9_0_set_clockgating_state(void *handle,
5136 enum amd_clockgating_state state)
5137{
5138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5139
5140 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
5141 return 0;
5142
5143 switch (adev->asic_type) {
5144 case CHIP_VEGA10:
5145 case CHIP_VEGA12:
5146 case CHIP_VEGA20:
5147 case CHIP_RAVEN:
5148 case CHIP_ARCTURUS:
5149 case CHIP_RENOIR:
5150 gfx_v9_0_update_gfx_clock_gating(adev,
5151 state == AMD_CG_STATE_GATE);
5152 break;
5153 default:
5154 break;
5155 }
5156 return 0;
5157}
5158
5159static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
5160{
5161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5162 int data;
5163
5164 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
5165 *flags = 0;
5166
5167 /* AMD_CG_SUPPORT_GFX_MGCG */
5168 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c48
)));
5169 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L))
5170 *flags |= AMD_CG_SUPPORT_GFX_MGCG(1 << 0);
5171
5172 /* AMD_CG_SUPPORT_GFX_CGCG */
5173 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c49
)));
5174 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L)
5175 *flags |= AMD_CG_SUPPORT_GFX_CGCG(1 << 2);
5176
5177 /* AMD_CG_SUPPORT_GFX_CGLS */
5178 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L)
5179 *flags |= AMD_CG_SUPPORT_GFX_CGLS(1 << 3);
5180
5181 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5182 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c06
)));
5183 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L)
5184 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS(1 << 7) | AMD_CG_SUPPORT_GFX_MGLS(1 << 1);
5185
5186 /* AMD_CG_SUPPORT_GFX_CP_LS */
5187 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1079
)));
5188 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L)
5189 *flags |= AMD_CG_SUPPORT_GFX_CP_LS(1 << 6) | AMD_CG_SUPPORT_GFX_MGLS(1 << 1);
5190
5191 if (adev->asic_type != CHIP_ARCTURUS) {
5192 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5193 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4cc5
)));
5194 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L)
5195 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG(1 << 20);
5196
5197 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5198 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L)
5199 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS(1 << 21);
5200 }
5201}
5202
5203static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5204{
5205 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
5206}
5207
5208static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5209{
5210 struct amdgpu_device *adev = ring->adev;
5211 u64 wptr;
5212
5213 /* XXX check if swapping is necessary on BE */
5214 if (ring->use_doorbell) {
5215 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs])({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = *(volatile typeof(*((atomic64_t *)&adev->wb
.wb[ring->wptr_offs])) *)&(*((atomic64_t *)&adev->
wb.wb[ring->wptr_offs])); membar_datadep_consumer(); __tmp
; });
5216 } else {
5217 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1054), 0);
5218 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1055), 0) << 32;
5219 }
5220
5221 return wptr;
5222}
5223
5224static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5225{
5226 struct amdgpu_device *adev = ring->adev;
5227
5228 if (ring->use_doorbell) {
5229 /* XXX check if swapping is necessary on BE */
5230 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr)({ typeof(*((atomic64_t*)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((ring->wptr)); *(volatile typeof(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; }
);
5231 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
5232 } else {
5233 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1054)), (((u32)(ring->wptr))), 0);
5234 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1055)), (((u32)(((ring->wptr) >> 16) >> 16
))), 0);
5235 }
5236}
5237
5238static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5239{
5240 struct amdgpu_device *adev = ring->adev;
5241 u32 ref_and_mask, reg_mem_engine;
5242 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5243
5244 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5245 switch (ring->me) {
5246 case 1:
5247 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5248 break;
5249 case 2:
5250 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5251 break;
5252 default:
5253 return;
5254 }
5255 reg_mem_engine = 0;
5256 } else {
5257 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5258 reg_mem_engine = 1; /* pfp */
5259 }
5260
5261 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5262 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5263 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5264 ref_and_mask, ref_and_mask, 0x20);
5265}
5266
5267static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5268 struct amdgpu_job *job,
5269 struct amdgpu_ib *ib,
5270 uint32_t flags)
5271{
5272 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
5273 u32 header, control = 0;
5274
5275 if (ib->flags & AMDGPU_IB_FLAG_CE(1<<0))
5276 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2)((3 << 30) | (((0x33) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
5277 else
5278 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
5279
5280 control |= ib->length_dw | (vmid << 24);
5281
5282 if (amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT(1<<2))) {
5283 control |= INDIRECT_BUFFER_PRE_ENB(1)((1) << 21);
5284
5285 if (!(ib->flags & AMDGPU_IB_FLAG_CE(1<<0)) && vmid)
5286 gfx_v9_0_ring_emit_de_meta(ring);
5287 }
5288
5289 amdgpu_ring_write(ring, header);
5290 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 5290, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
5291 amdgpu_ring_write(ring,
5292#ifdef __BIG_ENDIAN
5293 (2 << 0) |
5294#endif
5295 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
5296 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
5297 amdgpu_ring_write(ring, control);
5298}
5299
5300static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5301 struct amdgpu_job *job,
5302 struct amdgpu_ib *ib,
5303 uint32_t flags)
5304{
5305 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
5306 u32 control = INDIRECT_BUFFER_VALID(1 << 23) | ib->length_dw | (vmid << 24);
5307
5308 /* Currently, there is a high possibility to get wave ID mismatch
5309 * between ME and GDS, leading to a hw deadlock, because ME generates
5310 * different wave IDs than the GDS expects. This situation happens
5311 * randomly when at least 5 compute pipes use GDS ordered append.
5312 * The wave IDs generated by ME are also wrong after suspend/resume.
5313 * Those are probably bugs somewhere else in the kernel driver.
5314 *
5315 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5316 * GDS to 0 for this ring (me/pipe).
5317 */
5318 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID(1 << 4)) {
5319 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
5320 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID0x1348);
5321 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5322 }
5323
5324 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
5325 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 5325, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
5326 amdgpu_ring_write(ring,
5327#ifdef __BIG_ENDIAN
5328 (2 << 0) |
5329#endif
5330 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
5331 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
5332 amdgpu_ring_write(ring, control);
5333}
5334
5335static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5336 u64 seq, unsigned flags)
5337{
5338 bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
5339 bool_Bool int_sel = flags & AMDGPU_FENCE_FLAG_INT(1 << 1);
5340 bool_Bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2);
5341
5342 /* RELEASE_MEM - flush caches, send int */
5343 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)((3 << 30) | (((0x49) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
5344 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN(1 << 15) |
5345 EOP_TC_NC_ACTION_EN(1 << 19)) :
5346 (EOP_TCL1_ACTION_EN(1 << 16) |
5347 EOP_TC_ACTION_EN(1 << 17) |
5348 EOP_TC_WB_ACTION_EN(1 << 15) |
5349 EOP_TC_MD_ACTION_EN(1 << 21))) |
5350 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT)((CACHE_FLUSH_AND_INV_TS_EVENT) << 0) |
5351 EVENT_INDEX(5)((5) << 8)));
5352 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1)((write64bit ? 2 : 1) << 29) | INT_SEL(int_sel ? 2 : 0)((int_sel ? 2 : 0) << 24));
5353
5354 /*
5355 * the address should be Qword aligned if 64bit write, Dword
5356 * aligned if only send 32bit data low (discard data high)
5357 */
5358 if (write64bit)
5359 BUG_ON(addr & 0x7)((!(addr & 0x7)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 5359, "!(addr & 0x7)"));
5360 else
5361 BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 5361, "!(addr & 0x3)"));
5362 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
5363 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
5364 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
5365 amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
5366 amdgpu_ring_write(ring, 0);
5367}
5368
5369static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5370{
5371 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5372 uint32_t seq = ring->fence_drv.sync_seq;
5373 uint64_t addr = ring->fence_drv.gpu_addr;
5374
5375 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
5376 lower_32_bits(addr)((u32)(addr)), upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)),
5377 seq, 0xffffffff, 4);
5378}
5379
5380static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5381 unsigned vmid, uint64_t pd_addr)
5382{
5383 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
5384
5385 /* compute doesn't have PFP */
5386 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5387 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5388 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)((3 << 30) | (((0x42) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5389 amdgpu_ring_write(ring, 0x0);
5390 }
5391}
5392
5393static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5394{
5395 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
5396}
5397
5398static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5399{
5400 u64 wptr;
5401
5402 /* XXX check if swapping is necessary on BE */
5403 if (ring->use_doorbell)
5404 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs])({ typeof(*((atomic64_t *)&ring->adev->wb.wb[ring->
wptr_offs])) __tmp = *(volatile typeof(*((atomic64_t *)&ring
->adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&ring->adev->wb.wb[ring->wptr_offs])); membar_datadep_consumer
(); __tmp; });
5405 else
5406 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 5406); } while (0);
5407 return wptr;
5408}
5409
5410static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5411{
5412 struct amdgpu_device *adev = ring->adev;
5413
5414 /* XXX check if swapping is necessary on BE */
5415 if (ring->use_doorbell) {
5416 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr)({ typeof(*((atomic64_t*)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((ring->wptr)); *(volatile typeof(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; }
);
5417 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
5418 } else{
5419 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 5419); } while (0); /* only DOORBELL method supported on gfx9 now */
5420 }
5421}
5422
5423static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5424 u64 seq, unsigned int flags)
5425{
5426 struct amdgpu_device *adev = ring->adev;
5427
5428 /* we only allocate 32bit for each seq wb address */
5429 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT)((!(flags & (1 << 0))) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 5429, "!(flags & (1 << 0))"
));
5430
5431 /* write fence seq to the "addr" */
5432 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
5433 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
5434 WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20)));
5435 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
5436 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
5437 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
5438
5439 if (flags & AMDGPU_FENCE_FLAG_INT(1 << 1)) {
5440 /* set register to trigger INT */
5441 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
5442 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
5443 WRITE_DATA_DST_SEL(0)((0) << 8) | WR_CONFIRM(1 << 20)));
5444 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)(adev->reg_offset[GC_HWIP][0][0] + 0x10b5));
5445 amdgpu_ring_write(ring, 0);
5446 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5447 }
5448}
5449
5450static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
5451{
5452 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)((3 << 30) | (((0x8B) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5453 amdgpu_ring_write(ring, 0);
5454}
5455
5456static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
5457{
5458 struct v9_ce_ib_state ce_payload = {0};
5459 uint64_t csa_addr;
5460 int cnt;
5461
5462 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
5463 csa_addr = amdgpu_csa_vaddr(ring->adev);
5464
5465 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
5466 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2)((2) << 30) |
5467 WRITE_DATA_DST_SEL(8)((8) << 8) |
5468 WR_CONFIRM(1 << 20)) |
5469 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
5470 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))((u32)(csa_addr + __builtin_offsetof(struct v9_gfx_meta_data,
ce_payload))));
5471 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))((u32)(((csa_addr + __builtin_offsetof(struct v9_gfx_meta_data
, ce_payload)) >> 16) >> 16)));
5472 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
5473}
5474
5475static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
5476{
5477 struct v9_de_ib_state de_payload = {0};
5478 uint64_t csa_addr, gds_addr;
5479 int cnt;
5480
5481 csa_addr = amdgpu_csa_vaddr(ring->adev);
5482 gds_addr = csa_addr + 4096;
5483 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr)((u32)(gds_addr));
5484 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr)((u32)(((gds_addr) >> 16) >> 16));
5485
5486 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5487 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
5488 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1)((1) << 30) |
5489 WRITE_DATA_DST_SEL(8)((8) << 8) |
5490 WR_CONFIRM(1 << 20)) |
5491 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
5492 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))((u32)(csa_addr + __builtin_offsetof(struct v9_gfx_meta_data,
de_payload))));
5493 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))((u32)(((csa_addr + __builtin_offsetof(struct v9_gfx_meta_data
, de_payload)) >> 16) >> 16)));
5494 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
5495}
5496
5497static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool_Bool start,
5498 bool_Bool secure)
5499{
5500 uint32_t v = secure ? FRAME_TMZ(1 << 0) : 0;
5501
5502 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)((3 << 30) | (((0x90) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5503 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)((start ? 0 : 1) << 28));
5504}
5505
5506static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
5507{
5508 uint32_t dw2 = 0;
5509
5510 if (amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)))
5511 gfx_v9_0_ring_emit_ce_meta(ring);
5512
5513 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5514 if (flags & AMDGPU_HAVE_CTX_SWITCH(1 << 2)) {
5515 /* set load_global_config & load_global_uconfig */
5516 dw2 |= 0x8001;
5517 /* set load_cs_sh_regs */
5518 dw2 |= 0x01000000;
5519 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5520 dw2 |= 0x10002;
5521
5522 /* set load_ce_ram if preamble presented */
5523 if (AMDGPU_PREAMBLE_IB_PRESENT(1 << 0) & flags)
5524 dw2 |= 0x10000000;
5525 } else {
5526 /* still load_ce_ram if this is the first time preamble presented
5527 * although there is no context switch happens.
5528 */
5529 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST(1 << 1) & flags)
5530 dw2 |= 0x10000000;
5531 }
5532
5533 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
5534 amdgpu_ring_write(ring, dw2);
5535 amdgpu_ring_write(ring, 0);
5536}
5537
5538static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5539{
5540 unsigned ret;
5541 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)((3 << 30) | (((0x22) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
5542 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr)));
5543 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16
)));
5544 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5545 ret = ring->wptr & ring->buf_mask;
5546 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5547 return ret;
5548}
5549
5550static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5551{
5552 unsigned cur;
5553 BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 5553, "!(offset > ring->buf_mask)"
));
5554 BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c"
, 5554, "!(ring->ring[offset] != 0x55aa55aa)"));
5555
5556 cur = (ring->wptr & ring->buf_mask) - 1;
5557 if (likely(cur > offset)__builtin_expect(!!(cur > offset), 1))
5558 ring->ring[offset] = cur - offset;
5559 else
5560 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
5561}
5562
5563static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5564 uint32_t reg_val_offs)
5565{
5566 struct amdgpu_device *adev = ring->adev;
5567
5568 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)((3 << 30) | (((0x40) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
5569 amdgpu_ring_write(ring, 0 | /* src: register*/
5570 (5 << 8) | /* dst: memory */
5571 (1 << 20)); /* write confirm */
5572 amdgpu_ring_write(ring, reg);
5573 amdgpu_ring_write(ring, 0);
5574 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +((u32)(adev->wb.gpu_addr + reg_val_offs * 4))
5575 reg_val_offs * 4)((u32)(adev->wb.gpu_addr + reg_val_offs * 4)));
5576 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16))
5577 reg_val_offs * 4)((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16)));
5578}
5579
5580static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5581 uint32_t val)
5582{
5583 uint32_t cmd = 0;
5584
5585 switch (ring->funcs->type) {
5586 case AMDGPU_RING_TYPE_GFX:
5587 cmd = WRITE_DATA_ENGINE_SEL(1)((1) << 30) | WR_CONFIRM(1 << 20);
5588 break;
5589 case AMDGPU_RING_TYPE_KIQ:
5590 cmd = (1 << 16); /* no inc addr */
5591 break;
5592 default:
5593 cmd = WR_CONFIRM(1 << 20);
5594 break;
5595 }
5596 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
5597 amdgpu_ring_write(ring, cmd);
5598 amdgpu_ring_write(ring, reg);
5599 amdgpu_ring_write(ring, 0);
5600 amdgpu_ring_write(ring, val);
5601}
5602
5603static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5604 uint32_t val, uint32_t mask)
5605{
5606 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5607}
5608
5609static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5610 uint32_t reg0, uint32_t reg1,
5611 uint32_t ref, uint32_t mask)
5612{
5613 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5614 struct amdgpu_device *adev = ring->adev;
5615 bool_Bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
5616 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
5617
5618 if (fw_version_ok)
5619 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5620 ref, mask, 0x20);
5621 else
5622 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
5623 ref, mask);
5624}
5625
5626static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
5627{
5628 struct amdgpu_device *adev = ring->adev;
5629 uint32_t value = 0;
5630
5631 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03)(((value) & ~0x00000007L) | (0x00000007L & ((0x03) <<
0x0)));
5632 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01)(((value) & ~0x00000070L) | (0x00000070L & ((0x01) <<
0x4)));
5633 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1)(((value) & ~0x00000080L) | (0x00000080L & ((1) <<
0x7)));
5634 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid)(((value) & ~0xF0000000L) | (0xF0000000L & ((vmid) <<
0x1c)));
5635 WREG32_SOC15(GC, 0, mmSQ_CMD, value)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x037b)), (value), 0);
5636}
5637
5638static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5639 enum amdgpu_interrupt_state state)
5640{
5641 switch (state) {
5642 case AMDGPU_IRQ_STATE_DISABLE:
5643 case AMDGPU_IRQ_STATE_ENABLE:
5644 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x04000000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x1a), 0)
5645 TIME_STAMP_INT_ENABLE,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x04000000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x1a), 0)
5646 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x04000000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x1a), 0);
5647 break;
5648 default:
5649 break;
5650 }
5651}
5652
5653static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5654 int me, int pipe,
5655 enum amdgpu_interrupt_state state)
5656{
5657 u32 mec_int_cntl, mec_int_cntl_reg;
5658
5659 /*
5660 * amdgpu controls only the first MEC. That's why this function only
5661 * handles the setting of interrupts for this specific MEC. All other
5662 * pipes' interrupts are set by amdkfd.
5663 */
5664
5665 if (me == 1) {
5666 switch (pipe) {
5667 case 0:
5668 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1085);
5669 break;
5670 case 1:
5671 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1086);
5672 break;
5673 case 2:
5674 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1087);
5675 break;
5676 case 3:
5677 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1088);
5678 break;
5679 default:
5680 DRM_DEBUG("invalid pipe %d\n", pipe)__drm_dbg(DRM_UT_CORE, "invalid pipe %d\n", pipe);
5681 return;
5682 }
5683 } else {
5684 DRM_DEBUG("invalid me %d\n", me)__drm_dbg(DRM_UT_CORE, "invalid me %d\n", me);
5685 return;
5686 }
5687
5688 switch (state) {
5689 case AMDGPU_IRQ_STATE_DISABLE:
5690 mec_int_cntl = RREG32(mec_int_cntl_reg)amdgpu_device_rreg(adev, (mec_int_cntl_reg), 0);
5691 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)))
5692 TIME_STAMP_INT_ENABLE, 0)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)));
5693 WREG32(mec_int_cntl_reg, mec_int_cntl)amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl), 0
);
5694 break;
5695 case AMDGPU_IRQ_STATE_ENABLE:
5696 mec_int_cntl = RREG32(mec_int_cntl_reg)amdgpu_device_rreg(adev, (mec_int_cntl_reg), 0);
5697 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)))
5698 TIME_STAMP_INT_ENABLE, 1)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)));
5699 WREG32(mec_int_cntl_reg, mec_int_cntl)amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl), 0
);
5700 break;
5701 default:
5702 break;
5703 }
5704}
5705
5706static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5707 struct amdgpu_irq_src *source,
5708 unsigned type,
5709 enum amdgpu_interrupt_state state)
5710{
5711 switch (state) {
5712 case AMDGPU_IRQ_STATE_DISABLE:
5713 case AMDGPU_IRQ_STATE_ENABLE:
5714 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0)
5715 PRIV_REG_INT_ENABLE,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0)
5716 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0);
5717 break;
5718 default:
5719 break;
5720 }
5721
5722 return 0;
5723}
5724
5725static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5726 struct amdgpu_irq_src *source,
5727 unsigned type,
5728 enum amdgpu_interrupt_state state)
5729{
5730 switch (state) {
5731 case AMDGPU_IRQ_STATE_DISABLE:
5732 case AMDGPU_IRQ_STATE_ENABLE:
5733 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0)
5734 PRIV_INSTR_INT_ENABLE,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0)
5735 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0);
5736 default:
5737 break;
5738 }
5739
5740 return 0;
5741}
5742
5743#define ENABLE_ECC_ON_ME_PIPE(me, pipe)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_MEme_PIPEpipe_INT_CNTL_BASE_IDX
] + mmCP_MEme_PIPEpipe_INT_CNTL), ((amdgpu_device_rreg(adev, (
adev->reg_offset[GC_HWIP][0][mmCP_MEme_PIPEpipe_INT_CNTL_BASE_IDX
] + mmCP_MEme_PIPEpipe_INT_CNTL), 0) & ~CP_MEme_PIPEpipe_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK
) | (1) << CP_MEme_PIPEpipe_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT
), 0) \
5744 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_ME
##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME##me##_PIPE##
pipe##_INT_CNTL), ((amdgpu_device_rreg(adev, (adev->reg_offset
[GC_HWIP][0][mmCP_ME##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME
##me##_PIPE##pipe##_INT_CNTL), 0) & ~CP_ME##me##_PIPE##pipe
##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK) | (1) << CP_ME
##me##_PIPE##pipe##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT)
, 0)
5745 CP_ECC_ERROR_INT_ENABLE, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_ME
##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME##me##_PIPE##
pipe##_INT_CNTL), ((amdgpu_device_rreg(adev, (adev->reg_offset
[GC_HWIP][0][mmCP_ME##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME
##me##_PIPE##pipe##_INT_CNTL), 0) & ~CP_ME##me##_PIPE##pipe
##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK) | (1) << CP_ME
##me##_PIPE##pipe##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT)
, 0)
5746
5747#define DISABLE_ECC_ON_ME_PIPE(me, pipe)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_MEme_PIPEpipe_INT_CNTL_BASE_IDX
] + mmCP_MEme_PIPEpipe_INT_CNTL), ((amdgpu_device_rreg(adev, (
adev->reg_offset[GC_HWIP][0][mmCP_MEme_PIPEpipe_INT_CNTL_BASE_IDX
] + mmCP_MEme_PIPEpipe_INT_CNTL), 0) & ~CP_MEme_PIPEpipe_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK
) | (0) << CP_MEme_PIPEpipe_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT
), 0) \
5748 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_ME
##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME##me##_PIPE##
pipe##_INT_CNTL), ((amdgpu_device_rreg(adev, (adev->reg_offset
[GC_HWIP][0][mmCP_ME##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME
##me##_PIPE##pipe##_INT_CNTL), 0) & ~CP_ME##me##_PIPE##pipe
##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK) | (0) << CP_ME
##me##_PIPE##pipe##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT)
, 0)
5749 CP_ECC_ERROR_INT_ENABLE, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][mmCP_ME
##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME##me##_PIPE##
pipe##_INT_CNTL), ((amdgpu_device_rreg(adev, (adev->reg_offset
[GC_HWIP][0][mmCP_ME##me##_PIPE##pipe##_INT_CNTL_BASE_IDX] + mmCP_ME
##me##_PIPE##pipe##_INT_CNTL), 0) & ~CP_ME##me##_PIPE##pipe
##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK) | (0) << CP_ME
##me##_PIPE##pipe##_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT)
, 0)
5750
5751static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5752 struct amdgpu_irq_src *source,
5753 unsigned type,
5754 enum amdgpu_interrupt_state state)
5755{
5756 switch (state) {
5757 case AMDGPU_IRQ_STATE_DISABLE:
5758 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00004000L) | (0) << 0xe)
, 0)
5759 CP_ECC_ERROR_INT_ENABLE, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00004000L) | (0) << 0xe)
, 0);
5760 DISABLE_ECC_ON_ME_PIPE(1, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1085), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1085), 0) & ~0x00004000L) | (0) << 0xe)
, 0);
5761 DISABLE_ECC_ON_ME_PIPE(1, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1086), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1086), 0) & ~0x00004000L) | (0) << 0xe)
, 0);
5762 DISABLE_ECC_ON_ME_PIPE(1, 2)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1087), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1087), 0) & ~0x00004000L) | (0) << 0xe)
, 0);
5763 DISABLE_ECC_ON_ME_PIPE(1, 3)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1088), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1088), 0) & ~0x00004000L) | (0) << 0xe)
, 0);
5764 break;
5765
5766 case AMDGPU_IRQ_STATE_ENABLE:
5767 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00004000L) | (1) << 0xe)
, 0)
5768 CP_ECC_ERROR_INT_ENABLE, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x106a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x106a), 0) & ~0x00004000L) | (1) << 0xe)
, 0);
5769 ENABLE_ECC_ON_ME_PIPE(1, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1085), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1085), 0) & ~0x00004000L) | (1) << 0xe)
, 0);
5770 ENABLE_ECC_ON_ME_PIPE(1, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1086), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1086), 0) & ~0x00004000L) | (1) << 0xe)
, 0);
5771 ENABLE_ECC_ON_ME_PIPE(1, 2)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1087), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1087), 0) & ~0x00004000L) | (1) << 0xe)
, 0);
5772 ENABLE_ECC_ON_ME_PIPE(1, 3)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1088), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1088), 0) & ~0x00004000L) | (1) << 0xe)
, 0);
5773 break;
5774 default:
5775 break;
5776 }
5777
5778 return 0;
5779}
5780
5781
5782static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5783 struct amdgpu_irq_src *src,
5784 unsigned type,
5785 enum amdgpu_interrupt_state state)
5786{
5787 switch (type) {
5788 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5789 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
5790 break;
5791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5792 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5793 break;
5794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5795 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5796 break;
5797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5798 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5799 break;
5800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5801 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5802 break;
5803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5804 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5805 break;
5806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5807 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5808 break;
5809 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5810 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5811 break;
5812 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5813 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5814 break;
5815 default:
5816 break;
5817 }
5818 return 0;
5819}
5820
5821static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
5822 struct amdgpu_irq_src *source,
5823 struct amdgpu_iv_entry *entry)
5824{
5825 int i;
5826 u8 me_id, pipe_id, queue_id;
5827 struct amdgpu_ring *ring;
5828
5829 DRM_DEBUG("IH: CP EOP\n")__drm_dbg(DRM_UT_CORE, "IH: CP EOP\n");
5830 me_id = (entry->ring_id & 0x0c) >> 2;
5831 pipe_id = (entry->ring_id & 0x03) >> 0;
5832 queue_id = (entry->ring_id & 0x70) >> 4;
5833
5834 switch (me_id) {
5835 case 0:
5836 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5837 break;
5838 case 1:
5839 case 2:
5840 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5841 ring = &adev->gfx.compute_ring[i];
5842 /* Per-queue interrupt is supported for MEC starting from VI.
5843 * The interrupt can only be enabled/disabled per pipe instead of per queue.
5844 */
5845 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
5846 amdgpu_fence_process(ring);
5847 }
5848 break;
5849 }
5850 return 0;
5851}
5852
5853static void gfx_v9_0_fault(struct amdgpu_device *adev,
5854 struct amdgpu_iv_entry *entry)
5855{
5856 u8 me_id, pipe_id, queue_id;
5857 struct amdgpu_ring *ring;
5858 int i;
5859
5860 me_id = (entry->ring_id & 0x0c) >> 2;
5861 pipe_id = (entry->ring_id & 0x03) >> 0;
5862 queue_id = (entry->ring_id & 0x70) >> 4;
5863
5864 switch (me_id) {
5865 case 0:
5866 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
5867 break;
5868 case 1:
5869 case 2:
5870 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5871 ring = &adev->gfx.compute_ring[i];
5872 if (ring->me == me_id && ring->pipe == pipe_id &&
5873 ring->queue == queue_id)
5874 drm_sched_fault(&ring->sched);
5875 }
5876 break;
5877 }
5878}
5879
5880static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
5881 struct amdgpu_irq_src *source,
5882 struct amdgpu_iv_entry *entry)
5883{
5884 DRM_ERROR("Illegal register access in command stream\n")__drm_err("Illegal register access in command stream\n");
5885 gfx_v9_0_fault(adev, entry);
5886 return 0;
5887}
5888
5889static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
5890 struct amdgpu_irq_src *source,
5891 struct amdgpu_iv_entry *entry)
5892{
5893 DRM_ERROR("Illegal instruction in command stream\n")__drm_err("Illegal instruction in command stream\n");
5894 gfx_v9_0_fault(adev, entry);
5895 return 0;
5896}
5897
5898
5899static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = {
5900 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT)GC_HWIP, 0, 0, 0x118e,
5901 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT)0x0000000CL, 0x2,
5902 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)0x00000003L, 0x0
5903 },
5904 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT)GC_HWIP, 0, 0, 0x118f,
5905 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT)0x0000000CL, 0x2,
5906 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)0x00000003L, 0x0
5907 },
5908 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT)GC_HWIP, 0, 0, 0x118a,
5909 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1)0x00000003L, 0x0,
5910 0, 0
5911 },
5912 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT)GC_HWIP, 0, 0, 0x118a,
5913 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2)0x0000000CL, 0x2,
5914 0, 0
5915 },
5916 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x1189,
5917 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT)0x0000000CL, 0x2,
5918 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)0x00000003L, 0x0
5919 },
5920 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT)GC_HWIP, 0, 0, 0x118d,
5921 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT)0x00000003L, 0x0,
5922 0, 0
5923 },
5924 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT)GC_HWIP, 0, 0, 0x118d,
5925 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT)0x00000030L, 0x4,
5926 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)0x0000000CL, 0x2
5927 },
5928 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x118b,
5929 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT)0x0000000CL, 0x2,
5930 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)0x00000003L, 0x0
5931 },
5932 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT)GC_HWIP, 0, 0, 0x1192,
5933 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1)0x00000003L, 0x0,
5934 0, 0
5935 },
5936 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT)GC_HWIP, 0, 0, 0x1193,
5937 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1)0x00000003L, 0x0,
5938 0, 0
5939 },
5940 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT)GC_HWIP, 0, 0, 0x1191,
5941 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1)0x00000003L, 0x0,
5942 0, 0
5943 },
5944 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT)GC_HWIP, 0, 0, 0x05c5,
5945 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC)0x00000030L, 0x4,
5946 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)0x00000003L, 0x0
5947 },
5948 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT)GC_HWIP, 0, 0, 0x05c5,
5949 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED)0x0000000CL, 0x2,
5950 0, 0
5951 },
5952 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT)GC_HWIP, 0, 0, 0x05cb,
5953 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC)0x00000003L, 0x0,
5954 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)0x0000000CL, 0x2
5955 },
5956 { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
5957 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT)GC_HWIP, 0, 0, 0x05cb,
5958 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC)0x00000030L, 0x4,
5959 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)0x000000C0L, 0x6
5960 },
5961 { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
5962 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT)GC_HWIP, 0, 0, 0x05cb,
5963 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED)0x00000300L, 0x8,
5964 0, 0
5965 },
5966 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
5967 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc,
5968 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC)0x00000003L, 0x0,
5969 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)0x0000000CL, 0x2
5970 },
5971 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
5972 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc,
5973 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC)0x00000030L, 0x4,
5974 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)0x000000C0L, 0x6
5975 },
5976 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
5977 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc,
5978 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC)0x00000300L, 0x8,
5979 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)0x00000C00L, 0xa
5980 },
5981 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
5982 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc,
5983 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC)0x00003000L, 0xc,
5984 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)0x0000C000L, 0xe
5985 },
5986 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT)GC_HWIP, 0, 0, 0x0445,
5987 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT)0x00000003L, 0x0,
5988 0, 0
5989 },
5990 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586,
5991 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT)0x00000003L, 0x0,
5992 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)0x0000000CL, 0x2
5993 },
5994 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586,
5995 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT)0x00000030L, 0x4,
5996 0, 0
5997 },
5998 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586,
5999 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT)0x000000C0L, 0x6,
6000 0, 0
6001 },
6002 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586,
6003 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT)0x00000300L, 0x8,
6004 0, 0
6005 },
6006 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586,
6007 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT)0x00000C00L, 0xa,
6008 0, 0
6009 },
6010 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT)GC_HWIP, 0, 0, 0x0bc5,
6011 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT)0x00000003L, 0x0,
6012 0, 0
6013 },
6014 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT)GC_HWIP, 0, 0, 0x0bc5,
6015 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT)0x0000000CL, 0x2,
6016 0, 0
6017 },
6018 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6019 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT)0x00000003L, 0x0,
6020 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)0x0000000CL, 0x2
6021 },
6022 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6023 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT)0x00000030L, 0x4,
6024 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)0x000000C0L, 0x6
6025 },
6026 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6027 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT)0x00000300L, 0x8,
6028 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)0x00000C00L, 0xa
6029 },
6030 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6031 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT)0x00003000L, 0xc,
6032 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)0x0000C000L, 0xe
6033 },
6034 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6035 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT)0x00030000L, 0x10,
6036 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)0x000C0000L, 0x12
6037 },
6038 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6039 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT)0x00300000L, 0x14,
6040 0, 0
6041 },
6042 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6043 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT)0x00C00000L, 0x16,
6044 0, 0
6045 },
6046 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6047 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT)0x03000000L, 0x18,
6048 0, 0
6049 },
6050 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6051 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT)0x0C000000L, 0x1a,
6052 0, 0
6053 },
6054 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6055 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT)0x30000000L, 0x1c,
6056 0, 0
6057 },
6058 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82,
6059 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT)0xC0000000L, 0x1e,
6060 0, 0
6061 },
6062 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6063 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT)0x00000003L, 0x0,
6064 0, 0
6065 },
6066 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6067 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT)0x0000000CL, 0x2,
6068 0, 0
6069 },
6070 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6071 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT)0x00000030L, 0x4,
6072 0, 0
6073 },
6074 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6075 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT)0x000000C0L, 0x6,
6076 0, 0
6077 },
6078 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6079 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT)0x00000300L, 0x8,
6080 0, 0
6081 },
6082 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6083 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT)0x00000C00L, 0xa,
6084 0, 0
6085 },
6086 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83,
6087 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT)0x00003000L, 0xc,
6088 0, 0
6089 },
6090 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT)GC_HWIP, 0, 0, 0x0b60,
6091 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT)0x00000003L, 0x0,
6092 0, 0
6093 },
6094 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6095 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT)0x00000003L, 0x0,
6096 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)0x0000000CL, 0x2
6097 },
6098 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6099 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT)0x00000030L, 0x4,
6100 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)0x000000C0L, 0x6
6101 },
6102 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6103 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT)0x00000300L, 0x8,
6104 0, 0
6105 },
6106 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6107 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT)0x00000C00L, 0xa,
6108 0, 0
6109 },
6110 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6111 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT)0x0000C000L, 0xe,
6112 0, 0
6113 },
6114 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6115 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT)0x00030000L, 0x10,
6116 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)0x000C0000L, 0x12
6117 },
6118 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18,
6119 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT)0x00300000L, 0x14,
6120 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)0x00C00000L, 0x16
6121 },
6122 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT)GC_HWIP, 0, 0, 0x052e,
6123 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT)0x00000003L, 0x0,
6124 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)0x0000000CL, 0x2
6125 },
6126 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT)GC_HWIP, 0, 0, 0x052e,
6127 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT)0x00000030L, 0x4,
6128 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)0x000000C0L, 0x6
6129 },
6130 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT)GC_HWIP, 0, 0, 0x052e,
6131 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT)0x00000300L, 0x8,
6132 0, 0
6133 },
6134 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6135 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT)0x00000003L, 0x0,
6136 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)0x0000000CL, 0x2
6137 },
6138 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6139 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT)0x00000030L, 0x4,
6140 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)0x000000C0L, 0x6
6141 },
6142 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6143 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT)0x00000300L, 0x8,
6144 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)0x00000C00L, 0xa
6145 },
6146 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6147 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT)0x00003000L, 0xc,
6148 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)0x0000C000L, 0xe
6149 },
6150 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6151 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT)0x00030000L, 0x10,
6152 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)0x000C0000L, 0x12
6153 },
6154 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6155 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT)0x00300000L, 0x14,
6156 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)0x00C00000L, 0x16
6157 },
6158 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6,
6159 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT)0x03000000L, 0x18,
6160 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)0x0C000000L, 0x1a
6161 },
6162 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6163 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT)0x00000003L, 0x0,
6164 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)0x0000000CL, 0x2
6165 },
6166 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6167 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT)0x00000030L, 0x4,
6168 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)0x000000C0L, 0x6
6169 },
6170 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6171 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT)0x00000300L, 0x8,
6172 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)0x00000C00L, 0xa
6173 },
6174 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6175 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT)0x00003000L, 0xc,
6176 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)0x0000C000L, 0xe
6177 },
6178 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6179 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT)0x00030000L, 0x10,
6180 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)0x000C0000L, 0x12
6181 },
6182 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2,
6183 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT)0x00300000L, 0x14,
6184 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)0x00C00000L, 0x16
6185 },
6186 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6187 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT)0x00000003L, 0x0,
6188 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)0x0000000CL, 0x2
6189 },
6190 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6191 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT)0x00000030L, 0x4,
6192 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)0x000000C0L, 0x6
6193 },
6194 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6195 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT)0x00000300L, 0x8,
6196 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)0x00000C00L, 0xa
6197 },
6198 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6199 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT)0x00003000L, 0xc,
6200 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)0x0000C000L, 0xe
6201 },
6202 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6203 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT)0x00030000L, 0x10,
6204 0, 0
6205 },
6206 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6207 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT)0x000C0000L, 0x12,
6208 0, 0
6209 },
6210 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6211 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT)0x00300000L, 0x14,
6212 0, 0
6213 },
6214 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6215 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT)0x00C00000L, 0x16,
6216 0, 0
6217 },
6218 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6219 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT)0x03000000L, 0x18,
6220 0, 0
6221 },
6222 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c,
6223 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT)0x0C000000L, 0x1a,
6224 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)0x30000000L, 0x1c
6225 },
6226 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6227 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT)0x00000003L, 0x0,
6228 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)0x0000000CL, 0x2
6229 },
6230 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6231 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT)0x00000030L, 0x4,
6232 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)0x000000C0L, 0x6
6233 },
6234 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6235 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT)0x00000300L, 0x8,
6236 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)0x00000C00L, 0xa
6237 },
6238 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6239 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT)0x00003000L, 0xc,
6240 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)0x0000C000L, 0xe
6241 },
6242 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6243 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT)0x00030000L, 0x10,
6244 0, 0
6245 },
6246 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6247 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT)0x000C0000L, 0x12,
6248 0, 0
6249 },
6250 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6251 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT)0x00300000L, 0x14,
6252 0, 0
6253 },
6254 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6255 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT)0x00C00000L, 0x16,
6256 0, 0
6257 },
6258 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d,
6259 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT)0x03000000L, 0x18,
6260 0, 0
6261 },
6262 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6263 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT)0x00000003L, 0x0,
6264 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)0x0000000CL, 0x2
6265 },
6266 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6267 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT)0x00000030L, 0x4,
6268 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)0x000000C0L, 0x6
6269 },
6270 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6271 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT)0x00000300L, 0x8,
6272 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)0x00000C00L, 0xa
6273 },
6274 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6275 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT)0x00003000L, 0xc,
6276 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)0x0000C000L, 0xe
6277 },
6278 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6279 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT)0x00030000L, 0x10,
6280 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)0x000C0000L, 0x12
6281 },
6282 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6283 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT)0x00300000L, 0x14,
6284 0, 0
6285 },
6286 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6287 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT)0x00C00000L, 0x16,
6288 0, 0
6289 },
6290 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6291 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT)0x03000000L, 0x18,
6292 0, 0
6293 },
6294 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6295 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT)0x0C000000L, 0x1a,
6296 0, 0
6297 },
6298 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706,
6299 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT)0x30000000L, 0x1c,
6300 0, 0
6301 },
6302 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6303 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT)0x00000003L, 0x0,
6304 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)0x0000000CL, 0x2
6305 },
6306 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6307 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT)0x00000030L, 0x4,
6308 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)0x000000C0L, 0x6
6309 },
6310 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6311 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT)0x00000300L, 0x8,
6312 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)0x00000C00L, 0xa
6313 },
6314 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6315 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT)0x00003000L, 0xc,
6316 0, 0
6317 },
6318 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6319 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT)0x0000C000L, 0xe,
6320 0, 0
6321 },
6322 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6323 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT)0x00030000L, 0x10,
6324 0, 0
6325 },
6326 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6327 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT)0x000C0000L, 0x12,
6328 0, 0
6329 },
6330 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6331 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT)0x00300000L, 0x14,
6332 0, 0
6333 },
6334 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707,
6335 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT)0x00C00000L, 0x16,
6336 0, 0
6337 }
6338};
6339
6340static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
6341 void *inject_if)
6342{
6343 struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
6344 int ret;
6345 struct ta_ras_trigger_error_input block_info = { 0 };
6346
6347 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6348 return -EINVAL22;
6349
6350 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)(sizeof((ras_gfx_subblocks)) / sizeof((ras_gfx_subblocks)[0])
))
6351 return -EINVAL22;
6352
6353 if (!ras_gfx_subblocks[info->head.sub_block_index].name)
6354 return -EPERM1;
6355
6356 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
6357 info->head.type)) {
6358 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",__drm_err("GFX Subblock %s, hardware do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type)
6359 ras_gfx_subblocks[info->head.sub_block_index].name,__drm_err("GFX Subblock %s, hardware do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type)
6360 info->head.type)__drm_err("GFX Subblock %s, hardware do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type);
6361 return -EPERM1;
6362 }
6363
6364 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
6365 info->head.type)) {
6366 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",__drm_err("GFX Subblock %s, driver do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type)
6367 ras_gfx_subblocks[info->head.sub_block_index].name,__drm_err("GFX Subblock %s, driver do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type)
6368 info->head.type)__drm_err("GFX Subblock %s, driver do not support type 0x%x\n"
, ras_gfx_subblocks[info->head.sub_block_index].name, info
->head.type);
6369 return -EPERM1;
6370 }
6371
6372 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
6373 block_info.sub_block_index =
6374 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
6375 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
6376 block_info.address = info->address;
6377 block_info.value = info->value;
6378
6379 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
6380 ret = psp_ras_trigger_error(&adev->psp, &block_info);
6381 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
6382
6383 return ret;
6384}
6385
6386static const char *vml2_mems[] = {
6387 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
6388 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
6389 "UTC_VML2_BANK_CACHE_0_4K_MEM0",
6390 "UTC_VML2_BANK_CACHE_0_4K_MEM1",
6391 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
6392 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
6393 "UTC_VML2_BANK_CACHE_1_4K_MEM0",
6394 "UTC_VML2_BANK_CACHE_1_4K_MEM1",
6395 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
6396 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
6397 "UTC_VML2_BANK_CACHE_2_4K_MEM0",
6398 "UTC_VML2_BANK_CACHE_2_4K_MEM1",
6399 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
6400 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
6401 "UTC_VML2_BANK_CACHE_3_4K_MEM0",
6402 "UTC_VML2_BANK_CACHE_3_4K_MEM1",
6403};
6404
6405static const char *vml2_walker_mems[] = {
6406 "UTC_VML2_CACHE_PDE0_MEM0",
6407 "UTC_VML2_CACHE_PDE0_MEM1",
6408 "UTC_VML2_CACHE_PDE1_MEM0",
6409 "UTC_VML2_CACHE_PDE1_MEM1",
6410 "UTC_VML2_CACHE_PDE2_MEM0",
6411 "UTC_VML2_CACHE_PDE2_MEM1",
6412 "UTC_VML2_RDIF_LOG_FIFO",
6413};
6414
6415static const char *atc_l2_cache_2m_mems[] = {
6416 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
6417 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
6418 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
6419 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
6420};
6421
6422static const char *atc_l2_cache_4k_mems[] = {
6423 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
6424 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
6425 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
6426 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
6427 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
6428 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
6429 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
6430 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
6431 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
6432 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
6433 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
6434 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
6435 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
6436 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
6437 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
6438 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
6439 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
6440 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
6441 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
6442 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
6443 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
6444 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
6445 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
6446 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
6447 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
6448 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
6449 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
6450 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
6451 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
6452 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
6453 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
6454 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
6455};
6456
6457static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
6458 struct ras_err_data *err_data)
6459{
6460 uint32_t i, data;
6461 uint32_t sec_count, ded_count;
6462
6463 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (255), 0);
6464 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0862)), (0), 0);
6465 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (255), 0);
6466 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0863)), (0), 0);
6467 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (255), 0);
6468 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0811)), (0), 0);
6469 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (255), 0);
6470 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0810)), (0), 0);
6471
6472 for (i = 0; i < ARRAY_SIZE(vml2_mems)(sizeof((vml2_mems)) / sizeof((vml2_mems)[0])); i++) {
6473 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (i), 0);
6474 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0862), 0);
6475
6476 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT)(((data) & 0x00003000L) >> 0xc);
6477 if (sec_count) {
6478 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6479 "SEC %d\n", i, vml2_mems[i], sec_count)do { } while(0);
6480 err_data->ce_count += sec_count;
6481 }
6482
6483 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT)(((data) & 0x0000C000L) >> 0xe);
6484 if (ded_count) {
6485 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6486 "DED %d\n", i, vml2_mems[i], ded_count)do { } while(0);
6487 err_data->ue_count += ded_count;
6488 }
6489 }
6490
6491 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems)(sizeof((vml2_walker_mems)) / sizeof((vml2_walker_mems)[0])); i++) {
6492 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (i), 0);
6493 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0863), 0);
6494
6495 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,(((data) & 0x00003000L) >> 0xc)
6496 SEC_COUNT)(((data) & 0x00003000L) >> 0xc);
6497 if (sec_count) {
6498 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6499 "SEC %d\n", i, vml2_walker_mems[i], sec_count)do { } while(0);
6500 err_data->ce_count += sec_count;
6501 }
6502
6503 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,(((data) & 0x0000C000L) >> 0xe)
6504 DED_COUNT)(((data) & 0x0000C000L) >> 0xe);
6505 if (ded_count) {
6506 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6507 "DED %d\n", i, vml2_walker_mems[i], ded_count)do { } while(0);
6508 err_data->ue_count += ded_count;
6509 }
6510 }
6511
6512 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems)(sizeof((atc_l2_cache_2m_mems)) / sizeof((atc_l2_cache_2m_mems
)[0])); i++) {
6513 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (i), 0);
6514 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0811), 0);
6515
6516 sec_count = (data & 0x00006000L) >> 0xd;
6517 if (sec_count) {
6518 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6519 "SEC %d\n", i, atc_l2_cache_2m_mems[i],do { } while(0)
6520 sec_count)do { } while(0);
6521 err_data->ce_count += sec_count;
6522 }
6523 }
6524
6525 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems)(sizeof((atc_l2_cache_4k_mems)) / sizeof((atc_l2_cache_4k_mems
)[0])); i++) {
6526 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (i), 0);
6527 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0810), 0);
6528
6529 sec_count = (data & 0x00006000L) >> 0xd;
6530 if (sec_count) {
6531 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6532 "SEC %d\n", i, atc_l2_cache_4k_mems[i],do { } while(0)
6533 sec_count)do { } while(0);
6534 err_data->ce_count += sec_count;
6535 }
6536
6537 ded_count = (data & 0x00018000L) >> 0xf;
6538 if (ded_count) {
6539 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "do { } while(0)
6540 "DED %d\n", i, atc_l2_cache_4k_mems[i],do { } while(0)
6541 ded_count)do { } while(0);
6542 err_data->ue_count += ded_count;
6543 }
6544 }
6545
6546 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (255), 0);
6547 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (255), 0);
6548 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (255), 0);
6549 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (255), 0);
6550
6551 return 0;
6552}
6553
6554static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev,
6555 const struct soc15_reg_entry *reg,
6556 uint32_t se_id, uint32_t inst_id, uint32_t value,
6557 uint32_t *sec_count, uint32_t *ded_count)
6558{
6559 uint32_t i;
6560 uint32_t sec_cnt, ded_cnt;
6561
6562 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields)(sizeof((gfx_v9_0_ras_fields)) / sizeof((gfx_v9_0_ras_fields)
[0])); i++) {
6563 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
6564 gfx_v9_0_ras_fields[i].seg != reg->seg ||
6565 gfx_v9_0_ras_fields[i].inst != reg->inst)
6566 continue;
6567
6568 sec_cnt = (value &
6569 gfx_v9_0_ras_fields[i].sec_count_mask) >>
6570 gfx_v9_0_ras_fields[i].sec_count_shift;
6571 if (sec_cnt) {
6572 dev_info(adev->dev, "GFX SubBlock %s, "do { } while(0)
6573 "Instance[%d][%d], SEC %d\n",do { } while(0)
6574 gfx_v9_0_ras_fields[i].name,do { } while(0)
6575 se_id, inst_id,do { } while(0)
6576 sec_cnt)do { } while(0);
6577 *sec_count += sec_cnt;
6578 }
6579
6580 ded_cnt = (value &
6581 gfx_v9_0_ras_fields[i].ded_count_mask) >>
6582 gfx_v9_0_ras_fields[i].ded_count_shift;
6583 if (ded_cnt) {
6584 dev_info(adev->dev, "GFX SubBlock %s, "do { } while(0)
6585 "Instance[%d][%d], DED %d\n",do { } while(0)
6586 gfx_v9_0_ras_fields[i].name,do { } while(0)
6587 se_id, inst_id,do { } while(0)
6588 ded_cnt)do { } while(0);
6589 *ded_count += ded_cnt;
6590 }
6591 }
6592
6593 return 0;
6594}
6595
6596static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev)
6597{
6598 int i, j, k;
6599
6600 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6601 return;
6602
6603 /* read back registers to clear the counters */
6604 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
6605 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs)(sizeof((gfx_v9_0_edc_counter_regs)) / sizeof((gfx_v9_0_edc_counter_regs
)[0])); i++) {
6606 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6607 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6608 gfx_v9_0_select_se_sh(adev, j, 0x0, k);
6609 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]))amdgpu_device_rreg(adev, ((adev->reg_offset[gfx_v9_0_edc_counter_regs
[i].hwip][gfx_v9_0_edc_counter_regs[i].inst][gfx_v9_0_edc_counter_regs
[i].seg] + gfx_v9_0_edc_counter_regs[i].reg_offset)), 0);
6610 }
6611 }
6612 }
6613 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2200)), (0xe0000000), 0);
6614 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
6615
6616 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (255), 0);
6617 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0862)), (0), 0);
6618 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (255), 0);
6619 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0863)), (0), 0);
6620 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (255), 0);
6621 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0811)), (0), 0);
6622 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (255), 0);
6623 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0810)), (0), 0);
6624
6625 for (i = 0; i < ARRAY_SIZE(vml2_mems)(sizeof((vml2_mems)) / sizeof((vml2_mems)[0])); i++) {
6626 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (i), 0);
6627 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0862), 0);
6628 }
6629
6630 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems)(sizeof((vml2_walker_mems)) / sizeof((vml2_walker_mems)[0])); i++) {
6631 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (i), 0);
6632 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0863), 0);
6633 }
6634
6635 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems)(sizeof((atc_l2_cache_2m_mems)) / sizeof((atc_l2_cache_2m_mems
)[0])); i++) {
6636 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (i), 0);
6637 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0811), 0);
6638 }
6639
6640 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems)(sizeof((atc_l2_cache_4k_mems)) / sizeof((atc_l2_cache_4k_mems
)[0])); i++) {
6641 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (i), 0);
6642 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0810), 0);
6643 }
6644
6645 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0860)), (255), 0);
6646 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0861)), (255), 0);
6647 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080f)), (255), 0);
6648 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x080e)), (255), 0);
6649}
6650
6651static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
6652 void *ras_error_status)
6653{
6654 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
6655 uint32_t sec_count = 0, ded_count = 0;
6656 uint32_t i, j, k;
6657 uint32_t reg_value;
6658
6659 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6660 return -EINVAL22;
6661
6662 err_data->ue_count = 0;
6663 err_data->ce_count = 0;
6664
6665 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
6666
6667 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs)(sizeof((gfx_v9_0_edc_counter_regs)) / sizeof((gfx_v9_0_edc_counter_regs
)[0])); i++) {
6668 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6669 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6670 gfx_v9_0_select_se_sh(adev, j, 0, k);
6671 reg_value =
6672 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]))amdgpu_device_rreg(adev, ((adev->reg_offset[gfx_v9_0_edc_counter_regs
[i].hwip][gfx_v9_0_edc_counter_regs[i].inst][gfx_v9_0_edc_counter_regs
[i].seg] + gfx_v9_0_edc_counter_regs[i].reg_offset)), 0);
6673 if (reg_value)
6674 gfx_v9_0_ras_error_count(adev,
6675 &gfx_v9_0_edc_counter_regs[i],
6676 j, k, reg_value,
6677 &sec_count, &ded_count);
6678 }
6679 }
6680 }
6681
6682 err_data->ce_count += sec_count;
6683 err_data->ue_count += ded_count;
6684
6685 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6686 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
6687
6688 gfx_v9_0_query_utc_edc_status(adev, err_data);
6689
6690 return 0;
6691}
6692
6693static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
6694{
6695 const unsigned int cp_coher_cntl =
6696 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1)((1) << 29) |
6697 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1)((1) << 27) |
6698 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1)((1) << 23) |
6699 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1)((1) << 22) |
6700 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1)((1) << 18);
6701
6702 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
6703 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)((3 << 30) | (((0x58) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
6704 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
6705 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6706 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
6707 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6708 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6709 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6710}
6711
6712static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
6713 .name = "gfx_v9_0",
6714 .early_init = gfx_v9_0_early_init,
6715 .late_init = gfx_v9_0_late_init,
6716 .sw_init = gfx_v9_0_sw_init,
6717 .sw_fini = gfx_v9_0_sw_fini,
6718 .hw_init = gfx_v9_0_hw_init,
6719 .hw_fini = gfx_v9_0_hw_fini,
6720 .suspend = gfx_v9_0_suspend,
6721 .resume = gfx_v9_0_resume,
6722 .is_idle = gfx_v9_0_is_idle,
6723 .wait_for_idle = gfx_v9_0_wait_for_idle,
6724 .soft_reset = gfx_v9_0_soft_reset,
6725 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
6726 .set_powergating_state = gfx_v9_0_set_powergating_state,
6727 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
6728};
6729
6730static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
6731 .type = AMDGPU_RING_TYPE_GFX,
6732 .align_mask = 0xff,
6733 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
6734 .support_64bit_ptrs = true1,
6735 .vmhub = AMDGPU_GFXHUB_00,
6736 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
6737 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
6738 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
6739 .emit_frame_size = /* totally 242 maximum if 16 IBs */
6740 5 + /* COND_EXEC */
6741 7 + /* PIPELINE_SYNC */
6742 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
6743 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
6744 2 + /* VM_FLUSH */
6745 8 + /* FENCE for VM_FLUSH */
6746 20 + /* GDS switch */
6747 4 + /* double SWITCH_BUFFER,
6748 the first COND_EXEC jump to the place just
6749 prior to this double SWITCH_BUFFER */
6750 5 + /* COND_EXEC */
6751 7 + /* HDP_flush */
6752 4 + /* VGT_flush */
6753 14 + /* CE_META */
6754 31 + /* DE_META */
6755 3 + /* CNTX_CTRL */
6756 5 + /* HDP_INVL */
6757 8 + 8 + /* FENCE x2 */
6758 2 + /* SWITCH_BUFFER */
6759 7, /* gfx_v9_0_emit_mem_sync */
6760 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
6761 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
6762 .emit_fence = gfx_v9_0_ring_emit_fence,
6763 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6764 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6765 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6766 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6767 .test_ring = gfx_v9_0_ring_test_ring,
6768 .test_ib = gfx_v9_0_ring_test_ib,
6769 .insert_nop = amdgpu_ring_insert_nop,
6770 .pad_ib = amdgpu_ring_generic_pad_ib,
6771 .emit_switch_buffer = gfx_v9_ring_emit_sb,
6772 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
6773 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
6774 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
6775 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
6776 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6777 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6778 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6779 .soft_recovery = gfx_v9_0_ring_soft_recovery,
6780 .emit_mem_sync = gfx_v9_0_emit_mem_sync,
6781};
6782
6783static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
6784 .type = AMDGPU_RING_TYPE_COMPUTE,
6785 .align_mask = 0xff,
6786 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
6787 .support_64bit_ptrs = true1,
6788 .vmhub = AMDGPU_GFXHUB_00,
6789 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6790 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6791 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6792 .emit_frame_size =
6793 20 + /* gfx_v9_0_ring_emit_gds_switch */
6794 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6795 5 + /* hdp invalidate */
6796 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6797 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
6798 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
6799 2 + /* gfx_v9_0_ring_emit_vm_flush */
6800 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6801 7, /* gfx_v9_0_emit_mem_sync */
6802 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6803 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
6804 .emit_fence = gfx_v9_0_ring_emit_fence,
6805 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6806 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6807 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6808 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6809 .test_ring = gfx_v9_0_ring_test_ring,
6810 .test_ib = gfx_v9_0_ring_test_ib,
6811 .insert_nop = amdgpu_ring_insert_nop,
6812 .pad_ib = amdgpu_ring_generic_pad_ib,
6813 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6814 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6815 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6816 .emit_mem_sync = gfx_v9_0_emit_mem_sync,
6817};
6818
6819static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
6820 .type = AMDGPU_RING_TYPE_KIQ,
6821 .align_mask = 0xff,
6822 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
6823 .support_64bit_ptrs = true1,
6824 .vmhub = AMDGPU_GFXHUB_00,
6825 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6826 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6827 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6828 .emit_frame_size =
6829 20 + /* gfx_v9_0_ring_emit_gds_switch */
6830 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6831 5 + /* hdp invalidate */
6832 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6833 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
6834 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
6835 2 + /* gfx_v9_0_ring_emit_vm_flush */
6836 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6837 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6838 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
6839 .test_ring = gfx_v9_0_ring_test_ring,
6840 .insert_nop = amdgpu_ring_insert_nop,
6841 .pad_ib = amdgpu_ring_generic_pad_ib,
6842 .emit_rreg = gfx_v9_0_ring_emit_rreg,
6843 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6844 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6845 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6846};
6847
6848static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
6849{
6850 int i;
6851
6852 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
6853
6854 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6855 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
6856
6857 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6858 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
6859}
6860
6861static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
6862 .set = gfx_v9_0_set_eop_interrupt_state,
6863 .process = gfx_v9_0_eop_irq,
6864};
6865
6866static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
6867 .set = gfx_v9_0_set_priv_reg_fault_state,
6868 .process = gfx_v9_0_priv_reg_irq,
6869};
6870
6871static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
6872 .set = gfx_v9_0_set_priv_inst_fault_state,
6873 .process = gfx_v9_0_priv_inst_irq,
6874};
6875
6876static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
6877 .set = gfx_v9_0_set_cp_ecc_error_state,
6878 .process = amdgpu_gfx_cp_ecc_error_irq,
6879};
6880
6881
6882static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
6883{
6884 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6885 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
6886
6887 adev->gfx.priv_reg_irq.num_types = 1;
6888 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
6889
6890 adev->gfx.priv_inst_irq.num_types = 1;
6891 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
6892
6893 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
6894 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
6895}
6896
6897static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
6898{
6899 switch (adev->asic_type) {
6900 case CHIP_VEGA10:
6901 case CHIP_VEGA12:
6902 case CHIP_VEGA20:
6903 case CHIP_RAVEN:
6904 case CHIP_ARCTURUS:
6905 case CHIP_RENOIR:
6906 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
6907 break;
6908 default:
6909 break;
6910 }
6911}
6912
6913static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
6914{
6915 /* init asci gds info */
6916 switch (adev->asic_type) {
6917 case CHIP_VEGA10:
6918 case CHIP_VEGA12:
6919 case CHIP_VEGA20:
6920 adev->gds.gds_size = 0x10000;
6921 break;
6922 case CHIP_RAVEN:
6923 case CHIP_ARCTURUS:
6924 adev->gds.gds_size = 0x1000;
6925 break;
6926 default:
6927 adev->gds.gds_size = 0x10000;
6928 break;
6929 }
6930
6931 switch (adev->asic_type) {
6932 case CHIP_VEGA10:
6933 case CHIP_VEGA20:
6934 adev->gds.gds_compute_max_wave_id = 0x7ff;
6935 break;
6936 case CHIP_VEGA12:
6937 adev->gds.gds_compute_max_wave_id = 0x27f;
6938 break;
6939 case CHIP_RAVEN:
6940 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
6941 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
6942 else
6943 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
6944 break;
6945 case CHIP_ARCTURUS:
6946 adev->gds.gds_compute_max_wave_id = 0xfff;
6947 break;
6948 default:
6949 /* this really depends on the chip */
6950 adev->gds.gds_compute_max_wave_id = 0x7ff;
6951 break;
6952 }
6953
6954 adev->gds.gws_size = 64;
6955 adev->gds.oa_size = 16;
6956}
6957
6958static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
6959 u32 bitmap)
6960{
6961 u32 data;
6962
6963 if (!bitmap)
6964 return;
6965
6966 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT0x10;
6967 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK0xFFFF0000L;
6968
6969 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0270)), (data), 0);
6970}
6971
6972static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
6973{
6974 u32 data, mask;
6975
6976 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x026f), 0);
6977 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0270), 0);
6978
6979 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK0xFFFF0000L;
6980 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT0x10;
6981
6982 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
6983
6984 return (~data) & mask;
6985}
6986
6987static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
6988 struct amdgpu_cu_info *cu_info)
6989{
6990 int i, j, k, counter, active_cu_number = 0;
6991 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
6992 unsigned disable_masks[4 * 4];
6993
6994 if (!adev || !cu_info)
6995 return -EINVAL22;
6996
6997 /*
6998 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
6999 */
7000 if (adev->gfx.config.max_shader_engines *
7001 adev->gfx.config.max_sh_per_se > 16)
7002 return -EINVAL22;
7003
7004 amdgpu_gfx_parse_disable_cu(disable_masks,
7005 adev->gfx.config.max_shader_engines,
7006 adev->gfx.config.max_sh_per_se);
7007
7008 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
7009 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7010 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7011 mask = 1;
7012 ao_bitmap = 0;
7013 counter = 0;
7014 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
7015 gfx_v9_0_set_user_cu_inactive_bitmap(
7016 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
7017 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
7018
7019 /*
7020 * The bitmap(and ao_cu_bitmap) in cu_info structure is
7021 * 4x4 size array, and it's usually suitable for Vega
7022 * ASICs which has 4*2 SE/SH layout.
7023 * But for Arcturus, SE/SH layout is changed to 8*1.
7024 * To mostly reduce the impact, we make it compatible
7025 * with current bitmap array as below:
7026 * SE4,SH0 --> bitmap[0][1]
7027 * SE5,SH0 --> bitmap[1][1]
7028 * SE6,SH0 --> bitmap[2][1]
7029 * SE7,SH0 --> bitmap[3][1]
7030 */
7031 cu_info->bitmap[i % 4][j + i / 4] = bitmap;
7032
7033 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7034 if (bitmap & mask) {
7035 if (counter < adev->gfx.config.max_cu_per_sh)
7036 ao_bitmap |= mask;
7037 counter ++;
7038 }
7039 mask <<= 1;
7040 }
7041 active_cu_number += counter;
7042 if (i < 2 && j < 2)
7043 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7044 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
7045 }
7046 }
7047 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7048 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
7049
7050 cu_info->number = active_cu_number;
7051 cu_info->ao_cu_mask = ao_cu_mask;
7052 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7053
7054 return 0;
7055}
7056
7057const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
7058{
7059 .type = AMD_IP_BLOCK_TYPE_GFX,
7060 .major = 9,
7061 .minor = 0,
7062 .rev = 0,
7063 .funcs = &gfx_v9_0_ip_funcs,
7064};
←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var)) ((type)(__uintptr_t)(const void *)(var))
14#endif
15
16struct firmware {
17 size_t size;
18 const u8 *data;
19};
20
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23 struct device *device)
24{
25 int r;
26 struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27 M_WAITOK0x0001 | M_ZERO0x0008);
28 r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29 if (r != 0) {
24
←
Assuming 'r' is equal to 0
→
25
←
Taking false branch
→
32
←
Assuming 'r' is not equal to 0
→
33
←
Taking true branch
→
30 free(f, M_DRM145, sizeof(struct firmware));
31 *fw = NULL((void *)0);
34
←
Null pointer value stored to field 'mec2_fw'
→
32 return -r;
33 } else {
34 *fw = f;
35 return 0;
26
←
Returning zero, which participates in a condition later
→
36 }
37}
38
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41 struct device *device)
42{
43 return request_firmware(fw, name, device);
44}
45
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47
48static inline void
49release_firmware(const struct firmware *fw)
50{
51 if (fw)
52 free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53 free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55
56#endif