Bug Summary

File:dev/pci/drm/amd/amdgpu/amdgpu_object.c
Warning:line 1014, column 24
Value stored to 'adev' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_object.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <linux/dma-buf.h>
35
36#include <drm/amdgpu_drm.h>
37#include <drm/drm_cache.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41
42/**
43 * DOC: amdgpu_object
44 *
45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46 * represents memory used by driver (VRAM, system memory, etc.). The driver
47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48 * to create/destroy/set buffer object which are then managed by the kernel TTM
49 * memory manager.
50 * The interfaces are also used internally by kernel clients, including gfx,
51 * uvd, etc. for kernel managed allocations used by the GPU.
52 *
53 */
54
55/**
56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting
57 *
58 * @bo: &amdgpu_bo buffer object
59 *
60 * This function is called when a BO stops being pinned, and updates the
61 * &amdgpu_device pin_size values accordingly.
62 */
63static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
64{
65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
66
67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM2) {
68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size)__sync_fetch_and_sub_8(&adev->vram_pin_size, amdgpu_bo_size
(bo));
69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),__sync_fetch_and_sub_8(&adev->visible_pin_size, amdgpu_vram_mgr_bo_visible_size
(bo))
70 &adev->visible_pin_size)__sync_fetch_and_sub_8(&adev->visible_pin_size, amdgpu_vram_mgr_bo_visible_size
(bo));
71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT1) {
72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size)__sync_fetch_and_sub_8(&adev->gart_pin_size, amdgpu_bo_size
(bo));
73 }
74}
75
76static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
77{
78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
80
81 if (bo->pin_count > 0)
82 amdgpu_bo_subtract_pin_size(bo);
83
84 amdgpu_bo_kunmap(bo);
85
86 if (bo->tbo.base.import_attach)
87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
88 drm_gem_object_release(&bo->tbo.base);
89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
90 if (!list_empty(&bo->shadow_list)) {
91 mutex_lock(&adev->shadow_list_lock)rw_enter_write(&adev->shadow_list_lock);
92 list_del_init(&bo->shadow_list);
93 mutex_unlock(&adev->shadow_list_lock)rw_exit_write(&adev->shadow_list_lock);
94 }
95 amdgpu_bo_unref(&bo->parent);
96
97 kfree(bo->metadata);
98 pool_put(&adev->ddev.objpl, bo);
99}
100
101/**
102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
103 * @bo: buffer object to be checked
104 *
105 * Uses destroy function associated with the object to determine if this is
106 * an &amdgpu_bo.
107 *
108 * Returns:
109 * true if the object belongs to &amdgpu_bo, false if not.
110 */
111bool_Bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
112{
113 if (bo->destroy == &amdgpu_bo_destroy)
114 return true1;
115 return false0;
116}
117
118/**
119 * amdgpu_bo_placement_from_domain - set buffer's placement
120 * @abo: &amdgpu_bo buffer object whose placement is to be set
121 * @domain: requested domain
122 *
123 * Sets buffer's placement according to requested domain and the buffer's
124 * flags.
125 */
126void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
127{
128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
129 struct ttm_placement *placement = &abo->placement;
130 struct ttm_place *places = abo->placements;
131 u64 flags = abo->flags;
132 u32 c = 0;
133
134 if (domain & AMDGPU_GEM_DOMAIN_VRAM0x4) {
135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT12;
136
137 places[c].fpfn = 0;
138 places[c].lpfn = 0;
139 places[c].mem_type = TTM_PL_VRAM2;
140 places[c].flags = TTM_PL_FLAG_WC(1 << 18) | TTM_PL_FLAG_UNCACHED(1 << 17);
141
142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0))
143 places[c].lpfn = visible_pfn;
144 else
145 places[c].flags |= TTM_PL_FLAG_TOPDOWN(1 << 22);
146
147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS(1 << 5))
148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS(1 << 19);
149 c++;
150 }
151
152 if (domain & AMDGPU_GEM_DOMAIN_GTT0x2) {
153 places[c].fpfn = 0;
154 places[c].lpfn = 0;
155 places[c].mem_type = TTM_PL_TT1;
156 places[c].flags = 0;
157 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2))
158 places[c].flags |= TTM_PL_FLAG_WC(1 << 18) |
159 TTM_PL_FLAG_UNCACHED(1 << 17);
160 else
161 places[c].flags |= TTM_PL_FLAG_CACHED(1 << 16);
162 c++;
163 }
164
165 if (domain & AMDGPU_GEM_DOMAIN_CPU0x1) {
166 places[c].fpfn = 0;
167 places[c].lpfn = 0;
168 places[c].mem_type = TTM_PL_SYSTEM0;
169 places[c].flags = 0;
170 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2))
171 places[c].flags |= TTM_PL_FLAG_WC(1 << 18) |
172 TTM_PL_FLAG_UNCACHED(1 << 17);
173 else
174 places[c].flags |= TTM_PL_FLAG_CACHED(1 << 16);
175 c++;
176 }
177
178 if (domain & AMDGPU_GEM_DOMAIN_GDS0x8) {
179 places[c].fpfn = 0;
180 places[c].lpfn = 0;
181 places[c].mem_type = AMDGPU_PL_GDS(3 + 0);
182 places[c].flags = TTM_PL_FLAG_UNCACHED(1 << 17);
183 c++;
184 }
185
186 if (domain & AMDGPU_GEM_DOMAIN_GWS0x10) {
187 places[c].fpfn = 0;
188 places[c].lpfn = 0;
189 places[c].mem_type = AMDGPU_PL_GWS(3 + 1);
190 places[c].flags = TTM_PL_FLAG_UNCACHED(1 << 17);
191 c++;
192 }
193
194 if (domain & AMDGPU_GEM_DOMAIN_OA0x20) {
195 places[c].fpfn = 0;
196 places[c].lpfn = 0;
197 places[c].mem_type = AMDGPU_PL_OA(3 + 2);
198 places[c].flags = TTM_PL_FLAG_UNCACHED(1 << 17);
199 c++;
200 }
201
202 if (!c) {
203 places[c].fpfn = 0;
204 places[c].lpfn = 0;
205 places[c].mem_type = TTM_PL_SYSTEM0;
206 places[c].flags = TTM_PL_MASK_CACHING((1 << 16) | (1 << 17) | (1 << 18));
207 c++;
208 }
209
210 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS)((!(c > 3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 210, "!(c > 3)"));
211
212 placement->num_placement = c;
213 placement->placement = places;
214
215 placement->num_busy_placement = c;
216 placement->busy_placement = places;
217}
218
219/**
220 * amdgpu_bo_create_reserved - create reserved BO for kernel use
221 *
222 * @adev: amdgpu device object
223 * @size: size for the new BO
224 * @align: alignment for the new BO
225 * @domain: where to place it
226 * @bo_ptr: used to initialize BOs in structures
227 * @gpu_addr: GPU addr of the pinned BO
228 * @cpu_addr: optional CPU address mapping
229 *
230 * Allocates and pins a BO for kernel internal use, and returns it still
231 * reserved.
232 *
233 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
234 *
235 * Returns:
236 * 0 on success, negative error code otherwise.
237 */
238int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
239 unsigned long size, int align,
240 u32 domain, struct amdgpu_bo **bo_ptr,
241 u64 *gpu_addr, void **cpu_addr)
242{
243 struct amdgpu_bo_param bp;
244 bool_Bool free = false0;
245 int r;
246
247 if (!size) {
248 amdgpu_bo_unref(bo_ptr);
249 return 0;
250 }
251
252 memset(&bp, 0, sizeof(bp))__builtin_memset((&bp), (0), (sizeof(bp)));
253 bp.size = size;
254 bp.byte_align = align;
255 bp.domain = domain;
256 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0)
257 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS(1 << 1);
258 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS(1 << 5);
259 bp.type = ttm_bo_type_kernel;
260 bp.resv = NULL((void *)0);
261
262 if (!*bo_ptr) {
263 r = amdgpu_bo_create(adev, &bp, bo_ptr);
264 if (r) {
265 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",printf("drm:pid%d:%s *ERROR* " "(%d) failed to allocate kernel bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r)
266 r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to allocate kernel bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
267 return r;
268 }
269 free = true1;
270 }
271
272 r = amdgpu_bo_reserve(*bo_ptr, false0);
273 if (r) {
274 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to reserve kernel bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
275 goto error_free;
276 }
277
278 r = amdgpu_bo_pin(*bo_ptr, domain);
279 if (r) {
280 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) kernel bo pin failed\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
281 goto error_unreserve;
282 }
283
284 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
285 if (r) {
286 dev_err(adev->dev, "%p bind failed\n", *bo_ptr)printf("drm:pid%d:%s *ERROR* " "%p bind failed\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , *bo_ptr);
287 goto error_unpin;
288 }
289
290 if (gpu_addr)
291 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
292
293 if (cpu_addr) {
294 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
295 if (r) {
296 dev_err(adev->dev, "(%d) kernel bo map failed\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) kernel bo map failed\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
297 goto error_unpin;
298 }
299 }
300
301 return 0;
302
303error_unpin:
304 amdgpu_bo_unpin(*bo_ptr);
305error_unreserve:
306 amdgpu_bo_unreserve(*bo_ptr);
307
308error_free:
309 if (free)
310 amdgpu_bo_unref(bo_ptr);
311
312 return r;
313}
314
315/**
316 * amdgpu_bo_create_kernel - create BO for kernel use
317 *
318 * @adev: amdgpu device object
319 * @size: size for the new BO
320 * @align: alignment for the new BO
321 * @domain: where to place it
322 * @bo_ptr: used to initialize BOs in structures
323 * @gpu_addr: GPU addr of the pinned BO
324 * @cpu_addr: optional CPU address mapping
325 *
326 * Allocates and pins a BO for kernel internal use.
327 *
328 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
329 *
330 * Returns:
331 * 0 on success, negative error code otherwise.
332 */
333int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
334 unsigned long size, int align,
335 u32 domain, struct amdgpu_bo **bo_ptr,
336 u64 *gpu_addr, void **cpu_addr)
337{
338 int r;
339
340 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
341 gpu_addr, cpu_addr);
342
343 if (r)
344 return r;
345
346 if (*bo_ptr)
347 amdgpu_bo_unreserve(*bo_ptr);
348
349 return 0;
350}
351
352/**
353 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
354 *
355 * @adev: amdgpu device object
356 * @offset: offset of the BO
357 * @size: size of the BO
358 * @domain: where to place it
359 * @bo_ptr: used to initialize BOs in structures
360 * @cpu_addr: optional CPU address mapping
361 *
362 * Creates a kernel BO at a specific offset in the address space of the domain.
363 *
364 * Returns:
365 * 0 on success, negative error code otherwise.
366 */
367int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
368 uint64_t offset, uint64_t size, uint32_t domain,
369 struct amdgpu_bo **bo_ptr, void **cpu_addr)
370{
371 struct ttm_operation_ctx ctx = { false0, false0 };
372 unsigned int i;
373 int r;
374
375 offset &= LINUX_PAGE_MASK(~((1 << 12) - 1));
376 size = roundup2(size, PAGE_SIZE)(((size) + (((1 << 12)) - 1)) & (~((__typeof(size))
((1 << 12)) - 1)));
377
378 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE(1 << 12), domain, bo_ptr,
379 NULL((void *)0), cpu_addr);
380 if (r)
381 return r;
382
383 if ((*bo_ptr) == NULL((void *)0))
384 return 0;
385
386 /*
387 * Remove the original mem node and create a new one at the request
388 * position.
389 */
390 if (cpu_addr)
391 amdgpu_bo_kunmap(*bo_ptr);
392
393 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
394
395 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
396 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT12;
397 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT12;
398 }
399 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
400 &(*bo_ptr)->tbo.mem, &ctx);
401 if (r)
402 goto error;
403
404 if (cpu_addr) {
405 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
406 if (r)
407 goto error;
408 }
409
410 amdgpu_bo_unreserve(*bo_ptr);
411 return 0;
412
413error:
414 amdgpu_bo_unreserve(*bo_ptr);
415 amdgpu_bo_unref(bo_ptr);
416 return r;
417}
418
419/**
420 * amdgpu_bo_free_kernel - free BO for kernel use
421 *
422 * @bo: amdgpu BO to free
423 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
424 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
425 *
426 * unmaps and unpin a BO for kernel internal use.
427 */
428void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
429 void **cpu_addr)
430{
431 if (*bo == NULL((void *)0))
432 return;
433
434 if (likely(amdgpu_bo_reserve(*bo, true) == 0)__builtin_expect(!!(amdgpu_bo_reserve(*bo, 1) == 0), 1)) {
435 if (cpu_addr)
436 amdgpu_bo_kunmap(*bo);
437
438 amdgpu_bo_unpin(*bo);
439 amdgpu_bo_unreserve(*bo);
440 }
441 amdgpu_bo_unref(bo);
442
443 if (gpu_addr)
444 *gpu_addr = 0;
445
446 if (cpu_addr)
447 *cpu_addr = NULL((void *)0);
448}
449
450/* Validate bo size is bit bigger then the request domain */
451static bool_Bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
452 unsigned long size, u32 domain)
453{
454 struct ttm_resource_manager *man = NULL((void *)0);
455
456 /*
457 * If GTT is part of requested domains the check must succeed to
458 * allow fall back to GTT
459 */
460 if (domain & AMDGPU_GEM_DOMAIN_GTT0x2) {
461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT1);
462
463 if (size < (man->size << PAGE_SHIFT12))
464 return true1;
465 else
466 goto fail;
467 }
468
469 if (domain & AMDGPU_GEM_DOMAIN_VRAM0x4) {
470 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM2);
471
472 if (size < (man->size << PAGE_SHIFT12))
473 return true1;
474 else
475 goto fail;
476 }
477
478
479 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
480 return true1;
481
482fail:
483 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,__drm_dbg(DRM_UT_CORE, "BO size %lu > total memory in domain: %llu\n"
, size, man->size << 12)
484 man->size << PAGE_SHIFT)__drm_dbg(DRM_UT_CORE, "BO size %lu > total memory in domain: %llu\n"
, size, man->size << 12);
485 return false0;
486}
487
488bool_Bool amdgpu_bo_support_uswc(u64 bo_flags)
489{
490
491#ifdef CONFIG_X86_32
492 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
493 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
494 */
495 return false0;
496#elif defined(CONFIG_X861) && !defined(CONFIG_X86_PAT1)
497 /* Don't try to enable write-combining when it can't work, or things
498 * may be slow
499 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
500 */
501
502#ifndef CONFIG_COMPILE_TEST
503#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT1 for better performance \
504 thanks to write-combining
505#endif
506
507 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2))
508 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "Please enable CONFIG_MTRR and CONFIG_X86_PAT for " "better performance thanks to write-combining\n"
); __warned = 1; } })
509 "better performance thanks to write-combining\n")({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "Please enable CONFIG_MTRR and CONFIG_X86_PAT for " "better performance thanks to write-combining\n"
); __warned = 1; } });
510 return false0;
511#else
512 /* For architectures that don't support WC memory,
513 * mask out the WC flag from the BO
514 */
515 if (!drm_arch_can_wc_memory())
516 return false0;
517
518 return true1;
519#endif
520}
521
522static int amdgpu_bo_do_create(struct amdgpu_device *adev,
523 struct amdgpu_bo_param *bp,
524 struct amdgpu_bo **bo_ptr)
525{
526 struct ttm_operation_ctx ctx = {
527 .interruptible = (bp->type != ttm_bo_type_kernel),
528 .no_wait_gpu = bp->no_wait_gpu,
529 .resv = bp->resv,
530 .flags = bp->type != ttm_bo_type_kernel ?
531 TTM_OPT_FLAG_ALLOW_RES_EVICT0x1 : 0
532 };
533 struct amdgpu_bo *bo;
534 unsigned long page_align, size = bp->size;
535 size_t acc_size;
536 int r;
537
538 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
539 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS0x10 | AMDGPU_GEM_DOMAIN_OA0x20)) {
540 /* GWS and OA don't need any alignment. */
541 page_align = bp->byte_align;
542 size <<= PAGE_SHIFT12;
543 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS0x8) {
544 /* Both size and alignment must be a multiple of 4. */
545 page_align = roundup2(bp->byte_align, 4)(((bp->byte_align) + ((4) - 1)) & (~((__typeof(bp->
byte_align))(4) - 1)));
546 size = roundup2(size, 4)(((size) + ((4) - 1)) & (~((__typeof(size))(4) - 1))) << PAGE_SHIFT12;
547 } else {
548 /* Memory should be aligned at least to a page size. */
549 page_align = roundup2(bp->byte_align, PAGE_SIZE)(((bp->byte_align) + (((1 << 12)) - 1)) & (~((__typeof
(bp->byte_align))((1 << 12)) - 1))) >> PAGE_SHIFT12;
550 size = roundup2(size, PAGE_SIZE)(((size) + (((1 << 12)) - 1)) & (~((__typeof(size))
((1 << 12)) - 1)));
551 }
552
553 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
554 return -ENOMEM12;
555
556 *bo_ptr = NULL((void *)0);
557
558 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
559 sizeof(struct amdgpu_bo));
560
561 bo = pool_get(&adev->ddev.objpl, PR_WAITOK0x0001 | PR_ZERO0x0008);
562 if (bo == NULL((void *)0))
563 return -ENOMEM12;
564 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
565 bo->adev = adev;
566 INIT_LIST_HEAD(&bo->shadow_list);
567 bo->vm_bo = NULL((void *)0);
568 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
569 bp->domain;
570 bo->allowed_domains = bo->preferred_domains;
571 if (bp->type != ttm_bo_type_kernel &&
572 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM0x4)
573 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT0x2;
574
575 bo->flags = bp->flags;
576
577 if (!amdgpu_bo_support_uswc(bo->flags))
578 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2);
579
580 bo->tbo.bdev = &adev->mman.bdev;
581 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS0x10 | AMDGPU_GEM_DOMAIN_OA0x20 |
582 AMDGPU_GEM_DOMAIN_GDS0x8))
583 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU0x1);
584 else
585 amdgpu_bo_placement_from_domain(bo, bp->domain);
586 if (bp->type == ttm_bo_type_kernel)
587 bo->tbo.priority = 1;
588
589 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
590 &bo->placement, page_align, &ctx, acc_size,
591 NULL((void *)0), bp->resv, &amdgpu_bo_destroy);
592 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
593 return r;
594
595 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
596 bo->tbo.mem.mem_type == TTM_PL_VRAM2 &&
597 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT12)
598 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
599 ctx.bytes_moved);
600 else
601 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
602
603 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED(1 << 3) &&
604 bo->tbo.mem.mem_type == TTM_PL_VRAM2) {
605 struct dma_fence *fence;
606
607 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
608 if (unlikely(r)__builtin_expect(!!(r), 0))
609 goto fail_unreserve;
610
611 amdgpu_bo_fence(bo, fence, false0);
612 dma_fence_put(bo->tbo.moving);
613 bo->tbo.moving = dma_fence_get(fence);
614 dma_fence_put(fence);
615 }
616 if (!bp->resv)
617 amdgpu_bo_unreserve(bo);
618 *bo_ptr = bo;
619
620 trace_amdgpu_bo_create(bo);
621
622 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
623 if (bp->type == ttm_bo_type_device)
624 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0);
625
626 return 0;
627
628fail_unreserve:
629 if (!bp->resv)
630 dma_resv_unlock(bo->tbo.base.resv);
631 amdgpu_bo_unref(&bo);
632 return r;
633}
634
635static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
636 unsigned long size,
637 struct amdgpu_bo *bo)
638{
639 struct amdgpu_bo_param bp;
640 int r;
641
642 if (bo->shadow)
643 return 0;
644
645 memset(&bp, 0, sizeof(bp))__builtin_memset((&bp), (0), (sizeof(bp)));
646 bp.size = size;
647 bp.domain = AMDGPU_GEM_DOMAIN_GTT0x2;
648 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2) |
649 AMDGPU_GEM_CREATE_SHADOW(1 << 4);
650 bp.type = ttm_bo_type_kernel;
651 bp.resv = bo->tbo.base.resv;
652
653 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
654 if (!r) {
655 bo->shadow->parent = amdgpu_bo_ref(bo);
656 mutex_lock(&adev->shadow_list_lock)rw_enter_write(&adev->shadow_list_lock);
657 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
658 mutex_unlock(&adev->shadow_list_lock)rw_exit_write(&adev->shadow_list_lock);
659 }
660
661 return r;
662}
663
664/**
665 * amdgpu_bo_create - create an &amdgpu_bo buffer object
666 * @adev: amdgpu device object
667 * @bp: parameters to be used for the buffer object
668 * @bo_ptr: pointer to the buffer object pointer
669 *
670 * Creates an &amdgpu_bo buffer object; and if requested, also creates a
671 * shadow object.
672 * Shadow object is used to backup the original buffer object, and is always
673 * in GTT.
674 *
675 * Returns:
676 * 0 for success or a negative error code on failure.
677 */
678int amdgpu_bo_create(struct amdgpu_device *adev,
679 struct amdgpu_bo_param *bp,
680 struct amdgpu_bo **bo_ptr)
681{
682 u64 flags = bp->flags;
683 int r;
684
685 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW(1 << 4);
686 r = amdgpu_bo_do_create(adev, bp, bo_ptr);
687 if (r)
688 return r;
689
690 if ((flags & AMDGPU_GEM_CREATE_SHADOW(1 << 4)) && !(adev->flags & AMD_IS_APU)) {
691 if (!bp->resv)
692 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,({ int __ret = !!(dma_resv_lock((*bo_ptr)->tbo.base.resv, (
(void *)0))); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "dma_resv_lock((*bo_ptr)->tbo.base.resv, ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 693); __builtin_expect(!!(__ret), 0); })
693 NULL))({ int __ret = !!(dma_resv_lock((*bo_ptr)->tbo.base.resv, (
(void *)0))); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "dma_resv_lock((*bo_ptr)->tbo.base.resv, ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 693); __builtin_expect(!!(__ret), 0); });
694
695 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
696
697 if (!bp->resv)
698 dma_resv_unlock((*bo_ptr)->tbo.base.resv);
699
700 if (r)
701 amdgpu_bo_unref(bo_ptr);
702 }
703
704 return r;
705}
706
707/**
708 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
709 * @bo: pointer to the buffer object
710 *
711 * Sets placement according to domain; and changes placement and caching
712 * policy of the buffer object according to the placement.
713 * This is used for validating shadow bos. It calls ttm_bo_validate() to
714 * make sure the buffer is resident where it needs to be.
715 *
716 * Returns:
717 * 0 for success or a negative error code on failure.
718 */
719int amdgpu_bo_validate(struct amdgpu_bo *bo)
720{
721 struct ttm_operation_ctx ctx = { false0, false0 };
722 uint32_t domain;
723 int r;
724
725 if (bo->pin_count)
726 return 0;
727
728 domain = bo->preferred_domains;
729
730retry:
731 amdgpu_bo_placement_from_domain(bo, domain);
732 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
733 if (unlikely(r == -ENOMEM)__builtin_expect(!!(r == -12), 0) && domain != bo->allowed_domains) {
734 domain = bo->allowed_domains;
735 goto retry;
736 }
737
738 return r;
739}
740
741/**
742 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
743 *
744 * @shadow: &amdgpu_bo shadow to be restored
745 * @fence: dma_fence associated with the operation
746 *
747 * Copies a buffer object's shadow content back to the object.
748 * This is used for recovering a buffer from its shadow in case of a gpu
749 * reset where vram context may be lost.
750 *
751 * Returns:
752 * 0 for success or a negative error code on failure.
753 */
754int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
755
756{
757 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
758 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
759 uint64_t shadow_addr, parent_addr;
760
761 shadow_addr = amdgpu_bo_gpu_offset(shadow);
762 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
763
764 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
765 amdgpu_bo_size(shadow), NULL((void *)0), fence,
766 true1, false0, false0);
767}
768
769/**
770 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
771 * @bo: &amdgpu_bo buffer object to be mapped
772 * @ptr: kernel virtual address to be returned
773 *
774 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
775 * amdgpu_bo_kptr() to get the kernel virtual address.
776 *
777 * Returns:
778 * 0 for success or a negative error code on failure.
779 */
780int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
781{
782 void *kptr;
783 long r;
784
785 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS(1 << 1))
786 return -EPERM1;
787
788 kptr = amdgpu_bo_kptr(bo);
789 if (kptr) {
790 if (ptr)
791 *ptr = kptr;
792 return 0;
793 }
794
795 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false0, false0,
796 MAX_SCHEDULE_TIMEOUT(0x7fffffff));
797 if (r < 0)
798 return r;
799
800 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
801 if (r)
802 return r;
803
804 if (ptr)
805 *ptr = amdgpu_bo_kptr(bo);
806
807 return 0;
808}
809
810/**
811 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
812 * @bo: &amdgpu_bo buffer object
813 *
814 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
815 *
816 * Returns:
817 * the virtual address of a buffer object area.
818 */
819void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
820{
821 bool_Bool is_iomem;
822
823 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
824}
825
826/**
827 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
828 * @bo: &amdgpu_bo buffer object to be unmapped
829 *
830 * Unmaps a kernel map set up by amdgpu_bo_kmap().
831 */
832void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
833{
834 if (bo->kmap.bo)
835 ttm_bo_kunmap(&bo->kmap);
836}
837
838/**
839 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
840 * @bo: &amdgpu_bo buffer object
841 *
842 * References the contained &ttm_buffer_object.
843 *
844 * Returns:
845 * a refcounted pointer to the &amdgpu_bo buffer object.
846 */
847struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
848{
849 if (bo == NULL((void *)0))
850 return NULL((void *)0);
851
852 ttm_bo_get(&bo->tbo);
853 return bo;
854}
855
856/**
857 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
858 * @bo: &amdgpu_bo buffer object
859 *
860 * Unreferences the contained &ttm_buffer_object and clear the pointer
861 */
862void amdgpu_bo_unref(struct amdgpu_bo **bo)
863{
864 struct ttm_buffer_object *tbo;
865
866 if ((*bo) == NULL((void *)0))
867 return;
868
869 tbo = &((*bo)->tbo);
870 ttm_bo_put(tbo);
871 *bo = NULL((void *)0);
872}
873
874/**
875 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
876 * @bo: &amdgpu_bo buffer object to be pinned
877 * @domain: domain to be pinned to
878 * @min_offset: the start of requested address range
879 * @max_offset: the end of requested address range
880 *
881 * Pins the buffer object according to requested domain and address range. If
882 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
883 * pin_count and pin_size accordingly.
884 *
885 * Pinning means to lock pages in memory along with keeping them at a fixed
886 * offset. It is required when a buffer can not be moved, for example, when
887 * a display buffer is being scanned out.
888 *
889 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
890 * where to pin a buffer if there are specific restrictions on where a buffer
891 * must be located.
892 *
893 * Returns:
894 * 0 for success or a negative error code on failure.
895 */
896int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
897 u64 min_offset, u64 max_offset)
898{
899 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
900 struct ttm_operation_ctx ctx = { false0, false0 };
901 int r, i;
902
903 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
904 return -EPERM1;
905
906 if (WARN_ON_ONCE(min_offset > max_offset)({ static int __warned; int __ret = !!(min_offset > max_offset
); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "min_offset > max_offset", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 906); __warned = 1; } __builtin_expect(!!(__ret), 0); }))
907 return -EINVAL22;
908
909 /* A shared bo cannot be migrated to VRAM */
910 if (bo->prime_shared_count) {
911 if (domain & AMDGPU_GEM_DOMAIN_GTT0x2)
912 domain = AMDGPU_GEM_DOMAIN_GTT0x2;
913 else
914 return -EINVAL22;
915 }
916
917 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
918 * See function amdgpu_display_supported_domains()
919 */
920 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
921
922 if (bo->pin_count) {
923 uint32_t mem_type = bo->tbo.mem.mem_type;
924
925 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
926 return -EINVAL22;
927
928 bo->pin_count++;
929
930 if (max_offset != 0) {
931 u64 domain_start = amdgpu_ttm_domain_start(adev,
932 mem_type);
933 WARN_ON_ONCE(max_offset <({ static int __warned; int __ret = !!(max_offset < (amdgpu_bo_gpu_offset
(bo) - domain_start)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "max_offset < (amdgpu_bo_gpu_offset(bo) - domain_start)"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 934)
; __warned = 1; } __builtin_expect(!!(__ret), 0); })
934 (amdgpu_bo_gpu_offset(bo) - domain_start))({ static int __warned; int __ret = !!(max_offset < (amdgpu_bo_gpu_offset
(bo) - domain_start)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "max_offset < (amdgpu_bo_gpu_offset(bo) - domain_start)"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 934)
; __warned = 1; } __builtin_expect(!!(__ret), 0); });
935 }
936
937 return 0;
938 }
939
940#ifdef notyet
941 if (bo->tbo.base.import_attach)
942 dma_buf_pin(bo->tbo.base.import_attach);
943#endif
944
945 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS(1 << 5);
946 /* force to pin into visible video ram */
947 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS(1 << 1)))
948 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0);
949 amdgpu_bo_placement_from_domain(bo, domain);
950 for (i = 0; i < bo->placement.num_placement; i++) {
951 unsigned fpfn, lpfn;
952
953 fpfn = min_offset >> PAGE_SHIFT12;
954 lpfn = max_offset >> PAGE_SHIFT12;
955
956 if (fpfn > bo->placements[i].fpfn)
957 bo->placements[i].fpfn = fpfn;
958 if (!bo->placements[i].lpfn ||
959 (lpfn && lpfn < bo->placements[i].lpfn))
960 bo->placements[i].lpfn = lpfn;
961 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT(1 << 21);
962 }
963
964 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
965 if (unlikely(r)__builtin_expect(!!(r), 0)) {
966 dev_err(adev->dev, "%p pin failed\n", bo)printf("drm:pid%d:%s *ERROR* " "%p pin failed\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , bo);
967 goto error;
968 }
969
970 bo->pin_count = 1;
971
972 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
973 if (domain == AMDGPU_GEM_DOMAIN_VRAM0x4) {
974 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size)__sync_fetch_and_add_8(&adev->vram_pin_size, amdgpu_bo_size
(bo));
975 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),__sync_fetch_and_add_8(&adev->visible_pin_size, amdgpu_vram_mgr_bo_visible_size
(bo))
976 &adev->visible_pin_size)__sync_fetch_and_add_8(&adev->visible_pin_size, amdgpu_vram_mgr_bo_visible_size
(bo));
977 } else if (domain == AMDGPU_GEM_DOMAIN_GTT0x2) {
978 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size)__sync_fetch_and_add_8(&adev->gart_pin_size, amdgpu_bo_size
(bo));
979 }
980
981error:
982 return r;
983}
984
985/**
986 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
987 * @bo: &amdgpu_bo buffer object to be pinned
988 * @domain: domain to be pinned to
989 *
990 * A simple wrapper to amdgpu_bo_pin_restricted().
991 * Provides a simpler API for buffers that do not have any strict restrictions
992 * on where a buffer must be located.
993 *
994 * Returns:
995 * 0 for success or a negative error code on failure.
996 */
997int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
998{
999 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1000}
1001
1002/**
1003 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1004 * @bo: &amdgpu_bo buffer object to be unpinned
1005 *
1006 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1007 * Changes placement and pin size accordingly.
1008 *
1009 * Returns:
1010 * 0 for success or a negative error code on failure.
1011 */
1012int amdgpu_bo_unpin(struct amdgpu_bo *bo)
1013{
1014 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
Value stored to 'adev' during its initialization is never read
1015 struct ttm_operation_ctx ctx = { false0, false0 };
1016 int r, i;
1017
1018 if (WARN_ON_ONCE(!bo->pin_count)({ static int __warned; int __ret = !!(!bo->pin_count); if
(__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!bo->pin_count", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 1018); __warned = 1; } __builtin_expect(!!(__ret), 0); })) {
1019 dev_warn(adev->dev, "%p unpin not necessary\n", bo)printf("drm:pid%d:%s *WARNING* " "%p unpin not necessary\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , bo);
1020 return 0;
1021 }
1022 bo->pin_count--;
1023 if (bo->pin_count)
1024 return 0;
1025
1026 amdgpu_bo_subtract_pin_size(bo);
1027
1028#ifdef notyet
1029 if (bo->tbo.base.import_attach)
1030 dma_buf_unpin(bo->tbo.base.import_attach);
1031#endif
1032
1033 for (i = 0; i < bo->placement.num_placement; i++) {
1034 bo->placements[i].lpfn = 0;
1035 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT(1 << 21);
1036 }
1037 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1038 if (unlikely(r)__builtin_expect(!!(r), 0))
1039 dev_err(adev->dev, "%p validate failed for unpin\n", bo)printf("drm:pid%d:%s *ERROR* " "%p validate failed for unpin\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , bo);
1040
1041 return r;
1042}
1043
1044/**
1045 * amdgpu_bo_evict_vram - evict VRAM buffers
1046 * @adev: amdgpu device object
1047 *
1048 * Evicts all VRAM buffers on the lru list of the memory type.
1049 * Mainly used for evicting vram at suspend time.
1050 *
1051 * Returns:
1052 * 0 for success or a negative error code on failure.
1053 */
1054int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
1055{
1056 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
1057#ifndef CONFIG_HIBERNATION
1058 if (adev->flags & AMD_IS_APU) {
1059 /* Useless to evict on IGP chips */
1060 return 0;
1061 }
1062#endif
1063 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM2);
1064}
1065
1066static const char *amdgpu_vram_names[] = {
1067 "UNKNOWN",
1068 "GDDR1",
1069 "DDR2",
1070 "GDDR3",
1071 "GDDR4",
1072 "GDDR5",
1073 "HBM",
1074 "DDR3",
1075 "DDR4",
1076 "GDDR6",
1077};
1078
1079/**
1080 * amdgpu_bo_init - initialize memory manager
1081 * @adev: amdgpu device object
1082 *
1083 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1084 *
1085 * Returns:
1086 * 0 for success or a negative error code on failure.
1087 */
1088int amdgpu_bo_init(struct amdgpu_device *adev)
1089{
1090 paddr_t start, end;
1091
1092#ifdef __linux__
1093 /* reserve PAT memory space to WC for VRAM */
1094 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1095 adev->gmc.aper_size);
1096
1097 /* Add an MTRR for the VRAM */
1098 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1099 adev->gmc.aper_size);
1100#else
1101 drm_mtrr_add(adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC(1<<1));
1102
1103 start = atop(bus_space_mmap(adev->memt, adev->gmc.aper_base, 0, 0, 0))((((adev->memt)->mmap((adev->gmc.aper_base), (0), (0
), (0)))) >> 12);
1104 end = start + atop(adev->gmc.aper_size)((adev->gmc.aper_size) >> 12);
1105 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE0x01);
1106#endif
1107 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",printk("\0016" "[" "drm" "] " "Detected VRAM RAM=%lluM, BAR=%lluM\n"
, adev->gmc.mc_vram_size >> 20, (unsigned long long)
adev->gmc.aper_size >> 20)
1108 adev->gmc.mc_vram_size >> 20,printk("\0016" "[" "drm" "] " "Detected VRAM RAM=%lluM, BAR=%lluM\n"
, adev->gmc.mc_vram_size >> 20, (unsigned long long)
adev->gmc.aper_size >> 20)
1109 (unsigned long long)adev->gmc.aper_size >> 20)printk("\0016" "[" "drm" "] " "Detected VRAM RAM=%lluM, BAR=%lluM\n"
, adev->gmc.mc_vram_size >> 20, (unsigned long long)
adev->gmc.aper_size >> 20);
1110 DRM_INFO("RAM width %dbits %s\n",printk("\0016" "[" "drm" "] " "RAM width %dbits %s\n", adev->
gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type])
1111 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type])printk("\0016" "[" "drm" "] " "RAM width %dbits %s\n", adev->
gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1112 return amdgpu_ttm_init(adev);
1113}
1114
1115/**
1116 * amdgpu_bo_late_init - late init
1117 * @adev: amdgpu device object
1118 *
1119 * Calls amdgpu_ttm_late_init() to free resources used earlier during
1120 * initialization.
1121 *
1122 * Returns:
1123 * 0 for success or a negative error code on failure.
1124 */
1125int amdgpu_bo_late_init(struct amdgpu_device *adev)
1126{
1127 amdgpu_ttm_late_init(adev);
1128
1129 return 0;
1130}
1131
1132/**
1133 * amdgpu_bo_fini - tear down memory manager
1134 * @adev: amdgpu device object
1135 *
1136 * Reverses amdgpu_bo_init() to tear down memory manager.
1137 */
1138void amdgpu_bo_fini(struct amdgpu_device *adev)
1139{
1140 amdgpu_ttm_fini(adev);
1141#ifdef __linux__
1142 arch_phys_wc_del(adev->gmc.vram_mtrr);
1143 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1144#else
1145 drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC(1<<1));
1146#endif
1147}
1148
1149#ifdef notyet
1150/**
1151 * amdgpu_bo_fbdev_mmap - mmap fbdev memory
1152 * @bo: &amdgpu_bo buffer object
1153 * @vma: vma as input from the fbdev mmap method
1154 *
1155 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo.
1156 *
1157 * Returns:
1158 * 0 for success or a negative error code on failure.
1159 */
1160int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
1161 struct vm_area_struct *vma)
1162{
1163 if (vma->vm_pgoff != 0)
1164 return -EACCES13;
1165
1166 return ttm_bo_mmap_obj(vma, &bo->tbo);
1167}
1168#endif
1169
1170/**
1171 * amdgpu_bo_set_tiling_flags - set tiling flags
1172 * @bo: &amdgpu_bo buffer object
1173 * @tiling_flags: new flags
1174 *
1175 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1176 * kernel driver to set the tiling flags on a buffer.
1177 *
1178 * Returns:
1179 * 0 for success or a negative error code on failure.
1180 */
1181int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1182{
1183 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1184
1185 if (adev->family <= AMDGPU_FAMILY_CZ135 &&
1186 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)(((__u64)(tiling_flags) >> 9) & 0x7) > 6)
1187 return -EINVAL22;
1188
1189 bo->tiling_flags = tiling_flags;
1190 return 0;
1191}
1192
1193/**
1194 * amdgpu_bo_get_tiling_flags - get tiling flags
1195 * @bo: &amdgpu_bo buffer object
1196 * @tiling_flags: returned flags
1197 *
1198 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1199 * set the tiling flags on a buffer.
1200 */
1201void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1202{
1203 dma_resv_assert_held(bo->tbo.base.resv)do { (void)(&(bo->tbo.base.resv)->lock.base); } while
(0);
1204
1205 if (tiling_flags)
1206 *tiling_flags = bo->tiling_flags;
1207}
1208
1209/**
1210 * amdgpu_bo_set_metadata - set metadata
1211 * @bo: &amdgpu_bo buffer object
1212 * @metadata: new metadata
1213 * @metadata_size: size of the new metadata
1214 * @flags: flags of the new metadata
1215 *
1216 * Sets buffer object's metadata, its size and flags.
1217 * Used via GEM ioctl.
1218 *
1219 * Returns:
1220 * 0 for success or a negative error code on failure.
1221 */
1222int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1223 uint32_t metadata_size, uint64_t flags)
1224{
1225 void *buffer;
1226
1227 if (!metadata_size) {
1228 if (bo->metadata_size) {
1229 kfree(bo->metadata);
1230 bo->metadata = NULL((void *)0);
1231 bo->metadata_size = 0;
1232 }
1233 return 0;
1234 }
1235
1236 if (metadata == NULL((void *)0))
1237 return -EINVAL22;
1238
1239 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL(0x0001 | 0x0004));
1240 if (buffer == NULL((void *)0))
1241 return -ENOMEM12;
1242
1243 kfree(bo->metadata);
1244 bo->metadata_flags = flags;
1245 bo->metadata = buffer;
1246 bo->metadata_size = metadata_size;
1247
1248 return 0;
1249}
1250
1251/**
1252 * amdgpu_bo_get_metadata - get metadata
1253 * @bo: &amdgpu_bo buffer object
1254 * @buffer: returned metadata
1255 * @buffer_size: size of the buffer
1256 * @metadata_size: size of the returned metadata
1257 * @flags: flags of the returned metadata
1258 *
1259 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1260 * less than metadata_size.
1261 * Used via GEM ioctl.
1262 *
1263 * Returns:
1264 * 0 for success or a negative error code on failure.
1265 */
1266int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1267 size_t buffer_size, uint32_t *metadata_size,
1268 uint64_t *flags)
1269{
1270 if (!buffer && !metadata_size)
1271 return -EINVAL22;
1272
1273 if (buffer) {
1274 if (buffer_size < bo->metadata_size)
1275 return -EINVAL22;
1276
1277 if (bo->metadata_size)
1278 memcpy(buffer, bo->metadata, bo->metadata_size)__builtin_memcpy((buffer), (bo->metadata), (bo->metadata_size
));
1279 }
1280
1281 if (metadata_size)
1282 *metadata_size = bo->metadata_size;
1283 if (flags)
1284 *flags = bo->metadata_flags;
1285
1286 return 0;
1287}
1288
1289/**
1290 * amdgpu_bo_move_notify - notification about a memory move
1291 * @bo: pointer to a buffer object
1292 * @evict: if this move is evicting the buffer from the graphics address space
1293 * @new_mem: new information of the bufer object
1294 *
1295 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1296 * bookkeeping.
1297 * TTM driver callback which is called when ttm moves a buffer.
1298 */
1299void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1300 bool_Bool evict,
1301 struct ttm_resource *new_mem)
1302{
1303 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1304 struct amdgpu_bo *abo;
1305 struct ttm_resource *old_mem = &bo->mem;
1306
1307 if (!amdgpu_bo_is_amdgpu_bo(bo))
1308 return;
1309
1310 abo = ttm_to_amdgpu_bo(bo);
1311 amdgpu_vm_bo_invalidate(adev, abo, evict);
1312
1313 amdgpu_bo_kunmap(abo);
1314
1315#ifdef notyet
1316 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1317 bo->mem.mem_type != TTM_PL_SYSTEM0)
1318 dma_buf_move_notify(abo->tbo.base.dma_buf);
1319#endif
1320
1321 /* remember the eviction */
1322 if (evict)
1323 atomic64_inc(&adev->num_evictions)__sync_fetch_and_add_8(&adev->num_evictions, 1);
1324
1325 /* update statistics */
1326 if (!new_mem)
1327 return;
1328
1329 /* move_notify is called before move happens */
1330 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
1331}
1332
1333/**
1334 * amdgpu_bo_release_notify - notification about a BO being released
1335 * @bo: pointer to a buffer object
1336 *
1337 * Wipes VRAM buffers whose contents should not be leaked before the
1338 * memory is released.
1339 */
1340void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1341{
1342 struct dma_fence *fence = NULL((void *)0);
1343 struct amdgpu_bo *abo;
1344 int r;
1345
1346 if (!amdgpu_bo_is_amdgpu_bo(bo))
1347 return;
1348
1349 abo = ttm_to_amdgpu_bo(bo);
1350
1351 if (abo->kfd_bo)
1352 amdgpu_amdkfd_unreserve_memory_limit(abo);
1353
1354 /* We only remove the fence if the resv has individualized. */
1355 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel({ static int __warned; int __ret = !!(bo->type == ttm_bo_type_kernel
&& bo->base.resv != &bo->base._resv); if (
__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "bo->type == ttm_bo_type_kernel && bo->base.resv != &bo->base._resv"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1356
); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1356 && bo->base.resv != &bo->base._resv)({ static int __warned; int __ret = !!(bo->type == ttm_bo_type_kernel
&& bo->base.resv != &bo->base._resv); if (
__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "bo->type == ttm_bo_type_kernel && bo->base.resv != &bo->base._resv"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1356
); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1357 if (bo->base.resv == &bo->base._resv)
1358 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1359
1360 if (bo->mem.mem_type != TTM_PL_VRAM2 || !bo->mem.mm_node ||
1361 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE(1 << 9)))
1362 return;
1363
1364 dma_resv_lock(bo->base.resv, NULL((void *)0));
1365
1366 r = amdgpu_fill_buffer(abo, AMDGPU_POISON0xd0bed0be, bo->base.resv, &fence);
1367 if (!WARN_ON(r)({ int __ret = !!(r); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "r", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c",
1367); __builtin_expect(!!(__ret), 0); })) {
1368 amdgpu_bo_fence(abo, fence, false0);
1369 dma_fence_put(fence);
1370 }
1371
1372 dma_resv_unlock(bo->base.resv);
1373}
1374
1375/**
1376 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1377 * @bo: pointer to a buffer object
1378 *
1379 * Notifies the driver we are taking a fault on this BO and have reserved it,
1380 * also performs bookkeeping.
1381 * TTM driver callback for dealing with vm faults.
1382 *
1383 * Returns:
1384 * 0 for success or a negative error code on failure.
1385 */
1386int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1387{
1388 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1389 struct ttm_operation_ctx ctx = { false0, false0 };
1390 struct amdgpu_bo *abo;
1391 unsigned long offset, size;
1392 int r;
1393
1394 if (!amdgpu_bo_is_amdgpu_bo(bo))
1395 return 0;
1396
1397 abo = ttm_to_amdgpu_bo(bo);
1398
1399 /* Remember that this BO was accessed by the CPU */
1400 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0);
1401
1402 if (bo->mem.mem_type != TTM_PL_VRAM2)
1403 return 0;
1404
1405 size = bo->mem.num_pages << PAGE_SHIFT12;
1406 offset = bo->mem.start << PAGE_SHIFT12;
1407 if ((offset + size) <= adev->gmc.visible_vram_size)
1408 return 0;
1409
1410 /* Can't move a pinned BO to visible VRAM */
1411 if (abo->pin_count > 0)
1412 return -EINVAL22;
1413
1414 /* hurrah the memory is not visible ! */
1415 atomic64_inc(&adev->num_vram_cpu_page_faults)__sync_fetch_and_add_8(&adev->num_vram_cpu_page_faults
, 1);
1416 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM0x4 |
1417 AMDGPU_GEM_DOMAIN_GTT0x2);
1418
1419 /* Avoid costly evictions; only set GTT as a busy placement */
1420 abo->placement.num_busy_placement = 1;
1421 abo->placement.busy_placement = &abo->placements[1];
1422
1423 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1424 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
1425 return r;
1426
1427 offset = bo->mem.start << PAGE_SHIFT12;
1428 /* this should never happen */
1429 if (bo->mem.mem_type == TTM_PL_VRAM2 &&
1430 (offset + size) > adev->gmc.visible_vram_size)
1431 return -EINVAL22;
1432
1433 return 0;
1434}
1435
1436/**
1437 * amdgpu_bo_fence - add fence to buffer object
1438 *
1439 * @bo: buffer object in question
1440 * @fence: fence to add
1441 * @shared: true if fence should be added shared
1442 *
1443 */
1444void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1445 bool_Bool shared)
1446{
1447 struct dma_resv *resv = bo->tbo.base.resv;
1448
1449 if (shared)
1450 dma_resv_add_shared_fence(resv, fence);
1451 else
1452 dma_resv_add_excl_fence(resv, fence);
1453}
1454
1455/**
1456 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1457 *
1458 * @adev: amdgpu device pointer
1459 * @resv: reservation object to sync to
1460 * @sync_mode: synchronization mode
1461 * @owner: fence owner
1462 * @intr: Whether the wait is interruptible
1463 *
1464 * Extract the fences from the reservation object and waits for them to finish.
1465 *
1466 * Returns:
1467 * 0 on success, errno otherwise.
1468 */
1469int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1470 enum amdgpu_sync_mode sync_mode, void *owner,
1471 bool_Bool intr)
1472{
1473 struct amdgpu_sync sync;
1474 int r;
1475
1476 amdgpu_sync_create(&sync);
1477 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1478 r = amdgpu_sync_wait(&sync, intr);
1479 amdgpu_sync_free(&sync);
1480 return r;
1481}
1482
1483/**
1484 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1485 * @bo: buffer object to wait for
1486 * @owner: fence owner
1487 * @intr: Whether the wait is interruptible
1488 *
1489 * Wrapper to wait for fences in a BO.
1490 * Returns:
1491 * 0 on success, errno otherwise.
1492 */
1493int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool_Bool intr)
1494{
1495 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1496
1497 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1498 AMDGPU_SYNC_NE_OWNER, owner, intr);
1499}
1500
1501/**
1502 * amdgpu_bo_gpu_offset - return GPU offset of bo
1503 * @bo: amdgpu object for which we query the offset
1504 *
1505 * Note: object should either be pinned or reserved when calling this
1506 * function, it might be useful to add check for this for debugging.
1507 *
1508 * Returns:
1509 * current GPU offset of the object.
1510 */
1511u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1512{
1513 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM)({ static int __warned; int __ret = !!(bo->tbo.mem.mem_type
== 0); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "bo->tbo.mem.mem_type == 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c"
, 1513); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1514 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&({ static int __warned; int __ret = !!(!dma_resv_is_locked(bo
->tbo.base.resv) && !bo->pin_count && bo
->tbo.type != ttm_bo_type_kernel); if (__ret && !__warned
) { printf("WARNING %s failed at %s:%d\n", "!dma_resv_is_locked(bo->tbo.base.resv) && !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1515
); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1515 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel)({ static int __warned; int __ret = !!(!dma_resv_is_locked(bo
->tbo.base.resv) && !bo->pin_count && bo
->tbo.type != ttm_bo_type_kernel); if (__ret && !__warned
) { printf("WARNING %s failed at %s:%d\n", "!dma_resv_is_locked(bo->tbo.base.resv) && !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1515
); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1516 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET)({ static int __warned; int __ret = !!(bo->tbo.mem.start ==
0x7fffffffffffffffL); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "bo->tbo.mem.start == 0x7fffffffffffffffL"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1516
); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1517 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&({ static int __warned; int __ret = !!(bo->tbo.mem.mem_type
== 2 && !(bo->flags & (1 << 5))); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "bo->tbo.mem.mem_type == 2 && !(bo->flags & (1 << 5))"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1518
); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1518 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS))({ static int __warned; int __ret = !!(bo->tbo.mem.mem_type
== 2 && !(bo->flags & (1 << 5))); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "bo->tbo.mem.mem_type == 2 && !(bo->flags & (1 << 5))"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c", 1518
); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1519
1520 return amdgpu_bo_gpu_offset_no_check(bo);
1521}
1522
1523/**
1524 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1525 * @bo: amdgpu object for which we query the offset
1526 *
1527 * Returns:
1528 * current GPU offset of the object without raising warnings.
1529 */
1530u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1531{
1532 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1533 uint64_t offset;
1534
1535 offset = (bo->tbo.mem.start << PAGE_SHIFT12) +
1536 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
1537
1538 return amdgpu_gmc_sign_extend(offset);
1539}
1540
1541/**
1542 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
1543 * @adev: amdgpu device object
1544 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1545 *
1546 * Returns:
1547 * Which of the allowed domains is preferred for pinning the BO for scanout.
1548 */
1549uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
1550 uint32_t domain)
1551{
1552 if (domain == (AMDGPU_GEM_DOMAIN_VRAM0x4 | AMDGPU_GEM_DOMAIN_GTT0x2)) {
1553 domain = AMDGPU_GEM_DOMAIN_VRAM0x4;
1554 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD(256*1024*1024))
1555 domain = AMDGPU_GEM_DOMAIN_GTT0x2;
1556 }
1557 return domain;
1558}