| File: | dev/pci/drm/i915/i915_vgpu.c |
| Warning: | line 192, column 27 Value stored to 'dev_priv' during its initialization is never read |
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| 1 | /* |
| 2 | * Copyright(c) 2011-2015 Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "i915_pvinfo.h" |
| 26 | #include "i915_vgpu.h" |
| 27 | |
| 28 | /** |
| 29 | * DOC: Intel GVT-g guest support |
| 30 | * |
| 31 | * Intel GVT-g is a graphics virtualization technology which shares the |
| 32 | * GPU among multiple virtual machines on a time-sharing basis. Each |
| 33 | * virtual machine is presented a virtual GPU (vGPU), which has equivalent |
| 34 | * features as the underlying physical GPU (pGPU), so i915 driver can run |
| 35 | * seamlessly in a virtual machine. This file provides vGPU specific |
| 36 | * optimizations when running in a virtual machine, to reduce the complexity |
| 37 | * of vGPU emulation and to improve the overall performance. |
| 38 | * |
| 39 | * A primary function introduced here is so-called "address space ballooning" |
| 40 | * technique. Intel GVT-g partitions global graphics memory among multiple VMs, |
| 41 | * so each VM can directly access a portion of the memory without hypervisor's |
| 42 | * intervention, e.g. filling textures or queuing commands. However with the |
| 43 | * partitioning an unmodified i915 driver would assume a smaller graphics |
| 44 | * memory starting from address ZERO, then requires vGPU emulation module to |
| 45 | * translate the graphics address between 'guest view' and 'host view', for |
| 46 | * all registers and command opcodes which contain a graphics memory address. |
| 47 | * To reduce the complexity, Intel GVT-g introduces "address space ballooning", |
| 48 | * by telling the exact partitioning knowledge to each guest i915 driver, which |
| 49 | * then reserves and prevents non-allocated portions from allocation. Thus vGPU |
| 50 | * emulation module only needs to scan and validate graphics addresses without |
| 51 | * complexity of address translation. |
| 52 | * |
| 53 | */ |
| 54 | |
| 55 | /** |
| 56 | * intel_vgpu_detect - detect virtual GPU |
| 57 | * @dev_priv: i915 device private |
| 58 | * |
| 59 | * This function is called at the initialization stage, to detect whether |
| 60 | * running on a vGPU. |
| 61 | */ |
| 62 | void intel_vgpu_detect(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 63 | { |
| 64 | #ifdef notyet |
| 65 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 66 | u64 magic; |
| 67 | u16 version_major; |
| 68 | void __iomem *shared_area; |
| 69 | |
| 70 | BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE)extern char _ctassert[(!(sizeof(struct vgt_if) != 0x1000)) ? 1 : -1 ] __attribute__((__unused__)); |
| 71 | |
| 72 | /* |
| 73 | * This is called before we setup the main MMIO BAR mappings used via |
| 74 | * the uncore structure, so we need to access the BAR directly. Since |
| 75 | * we do not support VGT on older gens, return early so we don't have |
| 76 | * to consider differently numbered or sized MMIO bars |
| 77 | */ |
| 78 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 6) |
| 79 | return; |
| 80 | |
| 81 | shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE0x78000, VGT_PVINFO_SIZE0x1000); |
| 82 | if (!shared_area) { |
| 83 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to map MMIO bar to check for VGT\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 84 | "failed to map MMIO bar to check for VGT\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to map MMIO bar to check for VGT\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 85 | return; |
| 86 | } |
| 87 | |
| 88 | magic = readq(shared_area + vgtif_offset(magic))ioread64(shared_area + (__builtin_offsetof(struct vgt_if, magic ))); |
| 89 | if (magic != VGT_MAGIC0x4776544776544776ULL) |
| 90 | goto out; |
| 91 | |
| 92 | version_major = readw(shared_area + vgtif_offset(version_major))ioread16(shared_area + (__builtin_offsetof(struct vgt_if, version_major ))); |
| 93 | if (version_major < VGT_VERSION_MAJOR1) { |
| 94 | drm_info(&dev_priv->drm, "VGT interface version mismatch!\n")do { } while(0); |
| 95 | goto out; |
| 96 | } |
| 97 | |
| 98 | dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps))ioread32(shared_area + (__builtin_offsetof(struct vgt_if, vgt_caps ))); |
| 99 | |
| 100 | dev_priv->vgpu.active = true1; |
| 101 | rw_init(&dev_priv->vgpu.lock, "vgpul")_rw_init_flags(&dev_priv->vgpu.lock, "vgpul", 0, ((void *)0)); |
| 102 | drm_info(&dev_priv->drm, "Virtual GPU for Intel GVT-g detected.\n")do { } while(0); |
| 103 | |
| 104 | out: |
| 105 | pci_iounmap(pdev, shared_area); |
| 106 | #endif |
| 107 | } |
| 108 | |
| 109 | void intel_vgpu_register(struct drm_i915_privateinteldrm_softc *i915) |
| 110 | { |
| 111 | /* |
| 112 | * Notify a valid surface after modesetting, when running inside a VM. |
| 113 | */ |
| 114 | if (intel_vgpu_active(i915)) |
| 115 | intel_uncore_write(&i915->uncore, vgtif_reg(display_ready)((const i915_reg_t){ .reg = (0x78000 + (__builtin_offsetof(struct vgt_if, display_ready))) }), |
| 116 | VGT_DRV_DISPLAY_READY1); |
| 117 | } |
| 118 | |
| 119 | bool_Bool intel_vgpu_active(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 120 | { |
| 121 | return dev_priv->vgpu.active; |
| 122 | } |
| 123 | |
| 124 | bool_Bool intel_vgpu_has_full_ppgtt(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 125 | { |
| 126 | return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT(1UL << (2)); |
| 127 | } |
| 128 | |
| 129 | bool_Bool intel_vgpu_has_hwsp_emulation(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 130 | { |
| 131 | return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION(1UL << (3)); |
| 132 | } |
| 133 | |
| 134 | bool_Bool intel_vgpu_has_huge_gtt(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 135 | { |
| 136 | return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT(1UL << (4)); |
| 137 | } |
| 138 | |
| 139 | struct _balloon_info_ { |
| 140 | /* |
| 141 | * There are up to 2 regions per mappable/unmappable graphic |
| 142 | * memory that might be ballooned. Here, index 0/1 is for mappable |
| 143 | * graphic memory, 2/3 for unmappable graphic memory. |
| 144 | */ |
| 145 | struct drm_mm_node space[4]; |
| 146 | }; |
| 147 | |
| 148 | static struct _balloon_info_ bl_info; |
| 149 | |
| 150 | static void vgt_deballoon_space(struct i915_ggtt *ggtt, |
| 151 | struct drm_mm_node *node) |
| 152 | { |
| 153 | struct drm_i915_privateinteldrm_softc *dev_priv = ggtt->vm.i915; |
| 154 | if (!drm_mm_node_allocated(node)) |
| 155 | return; |
| 156 | |
| 157 | drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n" , node->start, node->start + node->size, node->size / 1024) |
| 158 | "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n" , node->start, node->start + node->size, node->size / 1024) |
| 159 | node->start,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n" , node->start, node->start + node->size, node->size / 1024) |
| 160 | node->start + node->size,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n" , node->start, node->start + node->size, node->size / 1024) |
| 161 | node->size / 1024)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n" , node->start, node->start + node->size, node->size / 1024); |
| 162 | |
| 163 | ggtt->vm.reserved -= node->size; |
| 164 | drm_mm_remove_node(node); |
| 165 | } |
| 166 | |
| 167 | /** |
| 168 | * intel_vgt_deballoon - deballoon reserved graphics address trunks |
| 169 | * @ggtt: the global GGTT from which we reserved earlier |
| 170 | * |
| 171 | * This function is called to deallocate the ballooned-out graphic memory, when |
| 172 | * driver is unloaded or when ballooning fails. |
| 173 | */ |
| 174 | void intel_vgt_deballoon(struct i915_ggtt *ggtt) |
| 175 | { |
| 176 | struct drm_i915_privateinteldrm_softc *dev_priv = ggtt->vm.i915; |
| 177 | int i; |
| 178 | |
| 179 | if (!intel_vgpu_active(ggtt->vm.i915)) |
| 180 | return; |
| 181 | |
| 182 | drm_dbg(&dev_priv->drm, "VGT deballoon.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "VGT deballoon.\n" ); |
| 183 | |
| 184 | for (i = 0; i < 4; i++) |
| 185 | vgt_deballoon_space(ggtt, &bl_info.space[i]); |
| 186 | } |
| 187 | |
| 188 | static int vgt_balloon_space(struct i915_ggtt *ggtt, |
| 189 | struct drm_mm_node *node, |
| 190 | unsigned long start, unsigned long end) |
| 191 | { |
| 192 | struct drm_i915_privateinteldrm_softc *dev_priv = ggtt->vm.i915; |
Value stored to 'dev_priv' during its initialization is never read | |
| 193 | unsigned long size = end - start; |
| 194 | int ret; |
| 195 | |
| 196 | if (start >= end) |
| 197 | return -EINVAL22; |
| 198 | |
| 199 | drm_info(&dev_priv->drm,do { } while(0) |
| 200 | "balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",do { } while(0) |
| 201 | start, end, size / 1024)do { } while(0); |
| 202 | ret = i915_gem_gtt_reserve(&ggtt->vm, node, |
| 203 | size, start, I915_COLOR_UNEVICTABLE(-1), |
| 204 | 0); |
| 205 | if (!ret) |
| 206 | ggtt->vm.reserved += size; |
| 207 | |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | /** |
| 212 | * intel_vgt_balloon - balloon out reserved graphics address trunks |
| 213 | * @ggtt: the global GGTT from which to reserve |
| 214 | * |
| 215 | * This function is called at the initialization stage, to balloon out the |
| 216 | * graphic address space allocated to other vGPUs, by marking these spaces as |
| 217 | * reserved. The ballooning related knowledge(starting address and size of |
| 218 | * the mappable/unmappable graphic memory) is described in the vgt_if structure |
| 219 | * in a reserved mmio range. |
| 220 | * |
| 221 | * To give an example, the drawing below depicts one typical scenario after |
| 222 | * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned |
| 223 | * out each for the mappable and the non-mappable part. From the vGPU1 point of |
| 224 | * view, the total size is the same as the physical one, with the start address |
| 225 | * of its graphic space being zero. Yet there are some portions ballooned out( |
| 226 | * the shadow part, which are marked as reserved by drm allocator). From the |
| 227 | * host point of view, the graphic address space is partitioned by multiple |
| 228 | * vGPUs in different VMs. :: |
| 229 | * |
| 230 | * vGPU1 view Host view |
| 231 | * 0 ------> +-----------+ +-----------+ |
| 232 | * ^ |###########| | vGPU3 | |
| 233 | * | |###########| +-----------+ |
| 234 | * | |###########| | vGPU2 | |
| 235 | * | +-----------+ +-----------+ |
| 236 | * mappable GM | available | ==> | vGPU1 | |
| 237 | * | +-----------+ +-----------+ |
| 238 | * | |###########| | | |
| 239 | * v |###########| | Host | |
| 240 | * +=======+===========+ +===========+ |
| 241 | * ^ |###########| | vGPU3 | |
| 242 | * | |###########| +-----------+ |
| 243 | * | |###########| | vGPU2 | |
| 244 | * | +-----------+ +-----------+ |
| 245 | * unmappable GM | available | ==> | vGPU1 | |
| 246 | * | +-----------+ +-----------+ |
| 247 | * | |###########| | | |
| 248 | * | |###########| | Host | |
| 249 | * v |###########| | | |
| 250 | * total GM size ------> +-----------+ +-----------+ |
| 251 | * |
| 252 | * Returns: |
| 253 | * zero on success, non-zero if configuration invalid or ballooning failed |
| 254 | */ |
| 255 | int intel_vgt_balloon(struct i915_ggtt *ggtt) |
| 256 | { |
| 257 | struct drm_i915_privateinteldrm_softc *dev_priv = ggtt->vm.i915; |
| 258 | struct intel_uncore *uncore = &dev_priv->uncore; |
| 259 | unsigned long ggtt_end = ggtt->vm.total; |
| 260 | |
| 261 | unsigned long mappable_base, mappable_size, mappable_end; |
| 262 | unsigned long unmappable_base, unmappable_size, unmappable_end; |
| 263 | int ret; |
| 264 | |
| 265 | if (!intel_vgpu_active(ggtt->vm.i915)) |
| 266 | return 0; |
| 267 | |
| 268 | mappable_base = |
| 269 | intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base)((const i915_reg_t){ .reg = (0x78000 + (__builtin_offsetof(struct vgt_if, avail_rs.mappable_gmadr.base))) })); |
| 270 | mappable_size = |
| 271 | intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size)((const i915_reg_t){ .reg = (0x78000 + (__builtin_offsetof(struct vgt_if, avail_rs.mappable_gmadr.size))) })); |
| 272 | unmappable_base = |
| 273 | intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base)((const i915_reg_t){ .reg = (0x78000 + (__builtin_offsetof(struct vgt_if, avail_rs.nonmappable_gmadr.base))) })); |
| 274 | unmappable_size = |
| 275 | intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size)((const i915_reg_t){ .reg = (0x78000 + (__builtin_offsetof(struct vgt_if, avail_rs.nonmappable_gmadr.size))) })); |
| 276 | |
| 277 | mappable_end = mappable_base + mappable_size; |
| 278 | unmappable_end = unmappable_base + unmappable_size; |
| 279 | |
| 280 | drm_info(&dev_priv->drm, "VGT ballooning configuration:\n")do { } while(0); |
| 281 | drm_info(&dev_priv->drm,do { } while(0) |
| 282 | "Mappable graphic memory: base 0x%lx size %ldKiB\n",do { } while(0) |
| 283 | mappable_base, mappable_size / 1024)do { } while(0); |
| 284 | drm_info(&dev_priv->drm,do { } while(0) |
| 285 | "Unmappable graphic memory: base 0x%lx size %ldKiB\n",do { } while(0) |
| 286 | unmappable_base, unmappable_size / 1024)do { } while(0); |
| 287 | |
| 288 | if (mappable_end > ggtt->mappable_end || |
| 289 | unmappable_base < ggtt->mappable_end || |
| 290 | unmappable_end > ggtt_end) { |
| 291 | drm_err(&dev_priv->drm, "Invalid ballooning configuration!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Invalid ballooning configuration!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 292 | return -EINVAL22; |
| 293 | } |
| 294 | |
| 295 | /* Unmappable graphic memory ballooning */ |
| 296 | if (unmappable_base > ggtt->mappable_end) { |
| 297 | ret = vgt_balloon_space(ggtt, &bl_info.space[2], |
| 298 | ggtt->mappable_end, unmappable_base); |
| 299 | |
| 300 | if (ret) |
| 301 | goto err; |
| 302 | } |
| 303 | |
| 304 | if (unmappable_end < ggtt_end) { |
| 305 | ret = vgt_balloon_space(ggtt, &bl_info.space[3], |
| 306 | unmappable_end, ggtt_end); |
| 307 | if (ret) |
| 308 | goto err_upon_mappable; |
| 309 | } |
| 310 | |
| 311 | /* Mappable graphic memory ballooning */ |
| 312 | if (mappable_base) { |
| 313 | ret = vgt_balloon_space(ggtt, &bl_info.space[0], |
| 314 | 0, mappable_base); |
| 315 | |
| 316 | if (ret) |
| 317 | goto err_upon_unmappable; |
| 318 | } |
| 319 | |
| 320 | if (mappable_end < ggtt->mappable_end) { |
| 321 | ret = vgt_balloon_space(ggtt, &bl_info.space[1], |
| 322 | mappable_end, ggtt->mappable_end); |
| 323 | |
| 324 | if (ret) |
| 325 | goto err_below_mappable; |
| 326 | } |
| 327 | |
| 328 | drm_info(&dev_priv->drm, "VGT balloon successfully\n")do { } while(0); |
| 329 | return 0; |
| 330 | |
| 331 | err_below_mappable: |
| 332 | vgt_deballoon_space(ggtt, &bl_info.space[0]); |
| 333 | err_upon_unmappable: |
| 334 | vgt_deballoon_space(ggtt, &bl_info.space[3]); |
| 335 | err_upon_mappable: |
| 336 | vgt_deballoon_space(ggtt, &bl_info.space[2]); |
| 337 | err: |
| 338 | drm_err(&dev_priv->drm, "VGT balloon fail\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "VGT balloon fail\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 339 | return ret; |
| 340 | } |