Bug Summary

File:dev/pci/drm/amd/amdgpu/vcn_v2_5.c
Warning:line 1341, column 4
Value stored to 'r' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name vcn_v2_5.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drm_drv.h>
26
27#include "amdgpu.h"
28#include "amdgpu_vcn.h"
29#include "amdgpu_pm.h"
30#include "soc15.h"
31#include "soc15d.h"
32#include "vcn_v2_0.h"
33#include "mmsch_v1_0.h"
34
35#include "vcn/vcn_2_5_offset.h"
36#include "vcn/vcn_2_5_sh_mask.h"
37#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
38
39#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27 0x27
40#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f 0x0f
41#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10 0x10
42#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11 0x11
43#define mmUVD_NO_OP_INTERNAL_OFFSET0x29 0x29
44#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66 0x66
45#define mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d 0xc01d
46
47#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431 0x431
48#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4 0x3b4
49#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5 0x3b5
50#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c 0x25c
51
52#define VCN25_MAX_HW_INSTANCES_ARCTURUS2 2
53
54static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
55static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
56static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
57static int vcn_v2_5_set_powergating_state(void *handle,
58 enum amd_powergating_state state);
59static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
60 int inst_idx, struct dpg_pause_state *new_state);
61static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
62
63static int amdgpu_ih_clientid_vcns[] = {
64 SOC15_IH_CLIENTID_VCN,
65 SOC15_IH_CLIENTID_VCN1
66};
67
68/**
69 * vcn_v2_5_early_init - set function pointers
70 *
71 * @handle: amdgpu_device pointer
72 *
73 * Set ring and irq function pointers
74 */
75static int vcn_v2_5_early_init(void *handle)
76{
77 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
78
79 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
80 adev->vcn.num_vcn_inst = 2;
81 adev->vcn.harvest_config = 0;
82 adev->vcn.num_enc_rings = 1;
83 } else {
84 u32 harvest;
85 int i;
86 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS2;
87 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
88 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0007), 0);
89 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK0x00000002L)
90 adev->vcn.harvest_config |= 1 << i;
91 }
92 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0(1 << 0) |
93 AMDGPU_VCN_HARVEST_VCN1(1 << 1)))
94 /* both instances are harvested, disable the block */
95 return -ENOENT2;
96
97 adev->vcn.num_enc_rings = 2;
98 }
99
100 vcn_v2_5_set_dec_ring_funcs(adev);
101 vcn_v2_5_set_enc_ring_funcs(adev);
102 vcn_v2_5_set_irq_funcs(adev);
103
104 return 0;
105}
106
107/**
108 * vcn_v2_5_sw_init - sw init for VCN block
109 *
110 * @handle: amdgpu_device pointer
111 *
112 * Load firmware and sw initialization
113 */
114static int vcn_v2_5_sw_init(void *handle)
115{
116 struct amdgpu_ring *ring;
117 int i, j, r;
118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119
120 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
121 if (adev->vcn.harvest_config & (1 << j))
122 continue;
123 /* VCN DEC TRAP */
124 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
125 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124, &adev->vcn.inst[j].irq);
126 if (r)
127 return r;
128
129 /* VCN ENC TRAP */
130 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
131 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
132 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119, &adev->vcn.inst[j].irq);
133 if (r)
134 return r;
135 }
136 }
137
138 r = amdgpu_vcn_sw_init(adev);
139 if (r)
140 return r;
141
142 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
143 const struct common_firmware_header *hdr;
144 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
146 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
147 adev->firmware.fw_size +=
148 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->ucode_size_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->ucode_size_bytes
))))((1 << 12)) - 1)));
149
150 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS2) {
151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
152 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
153 adev->firmware.fw_size +=
154 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->ucode_size_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->ucode_size_bytes
))))((1 << 12)) - 1)));
155 }
156 dev_info(adev->dev, "Will use PSP to load VCN firmware\n")do { } while(0);
157 }
158
159 r = amdgpu_vcn_resume(adev);
160 if (r)
161 return r;
162
163 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
164 volatile struct amdgpu_fw_shared *fw_shared;
165
166 if (adev->vcn.harvest_config & (1 << j))
167 continue;
168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27;
169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431;
170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4;
171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5;
172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c;
173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66;
174
175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d;
176 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9)(adev->reg_offset[VCN_HWIP][j][1] + 0x001d);
177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10;
178 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0)(adev->reg_offset[VCN_HWIP][j][1] + 0x0090);
179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11;
180 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1)(adev->reg_offset[VCN_HWIP][j][1] + 0x0091);
181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f;
182 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD)(adev->reg_offset[VCN_HWIP][j][1] + 0x008f);
183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET0x29;
184 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP)(adev->reg_offset[VCN_HWIP][j][1] + 0x00a9);
185
186 ring = &adev->vcn.inst[j].ring_dec;
187 ring->use_doorbell = true1;
188
189 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
190 (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ? 2*j : 8*j);
191 snprintf(ring->name, sizeof(ring->name), "vcn_dec_%d", j);
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
193 0, AMDGPU_RING_PRIO_DEFAULT1);
194 if (r)
195 return r;
196
197 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
198 ring = &adev->vcn.inst[j].ring_enc[i];
199 ring->use_doorbell = true1;
200
201 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
202 (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ? (1 + i + 2*j) : (2 + i + 8*j));
203
204 snprintf(ring->name, sizeof(ring->name), "vcn_enc_%d.%d", j, i);
205 r = amdgpu_ring_init(adev, ring, 512,
206 &adev->vcn.inst[j].irq, 0,
207 AMDGPU_RING_PRIO_DEFAULT1);
208 if (r)
209 return r;
210 }
211
212 fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr;
213 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG)((__uint32_t)((1 << 8)));
214 }
215
216 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
217 r = amdgpu_virt_alloc_mm_table(adev);
218 if (r)
219 return r;
220 }
221
222 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15))
223 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
224
225 return 0;
226}
227
228/**
229 * vcn_v2_5_sw_fini - sw fini for VCN block
230 *
231 * @handle: amdgpu_device pointer
232 *
233 * VCN suspend and free up sw allocation
234 */
235static int vcn_v2_5_sw_fini(void *handle)
236{
237 int i, r, idx;
238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
239 volatile struct amdgpu_fw_shared *fw_shared;
240
241 if (drm_dev_enter(&adev->ddev, &idx)) {
242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
243 if (adev->vcn.harvest_config & (1 << i))
244 continue;
245 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
246 fw_shared->present_flag_0 = 0;
247 }
248 drm_dev_exit(idx);
249 }
250
251
252 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
253 amdgpu_virt_free_mm_table(adev);
254
255 r = amdgpu_vcn_suspend(adev);
256 if (r)
257 return r;
258
259 r = amdgpu_vcn_sw_fini(adev);
260
261 return r;
262}
263
264/**
265 * vcn_v2_5_hw_init - start and test VCN block
266 *
267 * @handle: amdgpu_device pointer
268 *
269 * Initialize the hardware, boot up the VCPU and do some testing
270 */
271static int vcn_v2_5_hw_init(void *handle)
272{
273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
274 struct amdgpu_ring *ring;
275 int i, j, r = 0;
276
277 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
278 r = vcn_v2_5_sriov_start(adev);
279
280 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
281 if (adev->vcn.harvest_config & (1 << j))
282 continue;
283
284 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
285 adev->vcn.inst[j].ring_enc[0].sched.ready = true1;
286 adev->vcn.inst[j].ring_enc[1].sched.ready = false0;
287 adev->vcn.inst[j].ring_enc[2].sched.ready = false0;
288 adev->vcn.inst[j].ring_dec.sched.ready = true1;
289 } else {
290
291 ring = &adev->vcn.inst[j].ring_dec;
292
293 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
294 ring->doorbell_index, j);
295
296 r = amdgpu_ring_test_helper(ring);
297 if (r)
298 goto done;
299
300 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
301 ring = &adev->vcn.inst[j].ring_enc[i];
302 r = amdgpu_ring_test_helper(ring);
303 if (r)
304 goto done;
305 }
306 }
307 }
308
309done:
310 if (!r)
311 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n"
, (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode"
)
312 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode")printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n"
, (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode"
);
313
314 return r;
315}
316
317/**
318 * vcn_v2_5_hw_fini - stop the hardware block
319 *
320 * @handle: amdgpu_device pointer
321 *
322 * Stop the VCN block, mark ring as not ready any more
323 */
324static int vcn_v2_5_hw_fini(void *handle)
325{
326 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
327 int i;
328
329 cancel_delayed_work_sync(&adev->vcn.idle_work);
330
331 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
332 if (adev->vcn.harvest_config & (1 << i))
333 continue;
334
335 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) ||
336 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
337 RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0080), 0)))
338 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
339 }
340
341 return 0;
342}
343
344/**
345 * vcn_v2_5_suspend - suspend VCN block
346 *
347 * @handle: amdgpu_device pointer
348 *
349 * HW fini and suspend VCN block
350 */
351static int vcn_v2_5_suspend(void *handle)
352{
353 int r;
354 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
355
356 r = vcn_v2_5_hw_fini(adev);
357 if (r)
358 return r;
359
360 r = amdgpu_vcn_suspend(adev);
361
362 return r;
363}
364
365/**
366 * vcn_v2_5_resume - resume VCN block
367 *
368 * @handle: amdgpu_device pointer
369 *
370 * Resume firmware and hw init VCN block
371 */
372static int vcn_v2_5_resume(void *handle)
373{
374 int r;
375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
376
377 r = amdgpu_vcn_resume(adev);
378 if (r)
379 return r;
380
381 r = vcn_v2_5_hw_init(adev);
382
383 return r;
384}
385
386/**
387 * vcn_v2_5_mc_resume - memory controller programming
388 *
389 * @adev: amdgpu_device pointer
390 *
391 * Let the VCN memory controller know it's offsets
392 */
393static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
394{
395 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
396 uint32_t offset;
397 int i;
398
399 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
400 if (adev->vcn.harvest_config & (1 << i))
401 continue;
402 /* cache window 0: fw */
403 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
404 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043c)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_lo)), 0)
405 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043c)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_lo)), 0);
406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043d)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_hi)), 0)
407 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043d)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_hi)), 0);
408 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0140)), (0), 0);
409 offset = 0;
410 } else {
411 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043c)), (((u32)(adev->vcn.inst[i].gpu_addr))), 0)
412 lower_32_bits(adev->vcn.inst[i].gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043c)), (((u32)(adev->vcn.inst[i].gpu_addr))), 0);
413 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043d)), (((u32)(((adev->vcn.inst[i].gpu_addr) >>
16) >> 16))), 0)
414 upper_32_bits(adev->vcn.inst[i].gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x043d)), (((u32)(((adev->vcn.inst[i].gpu_addr) >>
16) >> 16))), 0);
415 offset = size;
416 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0140)), (256 >> 3), 0)
417 AMDGPU_UVD_FIRMWARE_OFFSET >> 3)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0140)), (256 >> 3), 0);
418 }
419 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0141)), (size), 0);
420
421 /* cache window 1: stack */
422 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0468)), (((u32)(adev->vcn.inst[i].gpu_addr + offset)
)), 0)
423 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0468)), (((u32)(adev->vcn.inst[i].gpu_addr + offset)
)), 0);
424 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0469)), (((u32)(((adev->vcn.inst[i].gpu_addr + offset
) >> 16) >> 16))), 0)
425 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0469)), (((u32)(((adev->vcn.inst[i].gpu_addr + offset
) >> 16) >> 16))), 0);
426 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0142)), (0), 0);
427 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0143)), ((128*1024)), 0);
428
429 /* cache window 2: context */
430 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x046c)), (((u32)(adev->vcn.inst[i].gpu_addr + offset +
(128*1024)))), 0)
431 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x046c)), (((u32)(adev->vcn.inst[i].gpu_addr + offset +
(128*1024)))), 0);
432 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x046d)), (((u32)(((adev->vcn.inst[i].gpu_addr + offset
+ (128*1024)) >> 16) >> 16))), 0)
433 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x046d)), (((u32)(((adev->vcn.inst[i].gpu_addr + offset
+ (128*1024)) >> 16) >> 16))), 0);
434 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0144)), (0), 0);
435 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0145)), ((512*1024)), 0);
436
437 /* non-cache window */
438 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0438)), (((u32)(adev->vcn.inst[i].fw_shared_gpu_addr
))), 0)
439 lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0438)), (((u32)(adev->vcn.inst[i].fw_shared_gpu_addr
))), 0);
440 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0439)), (((u32)(((adev->vcn.inst[i].fw_shared_gpu_addr
) >> 16) >> 16))), 0)
441 upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0439)), (((u32)(((adev->vcn.inst[i].fw_shared_gpu_addr
) >> 16) >> 16))), 0);
442 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0152)), (0), 0);
443 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0153)), ((((sizeof(struct amdgpu_fw_shared)) + (4096 - 1
)) & ~(4096 - 1))), 0)
444 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0153)), ((((sizeof(struct amdgpu_fw_shared)) + (4096 - 1
)) & ~(4096 - 1))), 0);
445 }
446}
447
448static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect)
449{
450 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
451 uint32_t offset;
452
453 /* cache window 0: fw */
454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
455 if (!indirect) {
456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0)
457 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0)
458 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0);
459 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0)
460 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0)
461 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode
[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0);
462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
463 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
464 } else {
465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
466 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
468 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
470 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
471 }
472 offset = 0;
473 } else {
474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0
| 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool
video_range, video1_range, aon_range, aon1_range; addr = (adev
->reg_offset[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range
= ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF
& addr) < ((0x1fa00 + 0x2600))))); video1_range = (((
(0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF &
addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0)
475 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0
| 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool
video_range, video1_range, aon_range, aon1_range; addr = (adev
->reg_offset[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range
= ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF
& addr) < ((0x1fa00 + 0x2600))))); video1_range = (((
(0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF &
addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0)
476 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0
| 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool
video_range, video1_range, aon_range, aon1_range; addr = (adev
->reg_offset[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range
= ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF
& addr) < ((0x1fa00 + 0x2600))))); video1_range = (((
(0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF &
addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0);
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0)
478 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0)
479 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0);
480 offset = size;
481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0)
482 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0)
483 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0);
484 }
485
486 if (!indirect)
487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (size), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while
(0)
488 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (size), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while
(0);
489 else
490 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
491 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
492
493 /* cache window 1: stack */
494 if (!indirect) {
495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev,
((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1
<< 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0)
496 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev,
((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1
<< 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0)
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev,
((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1
<< 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0);
498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0)
499 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0)
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0);
501 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
502 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
503 } else {
504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
505 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
507 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
509 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
510 }
511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0143); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } }
while (0)
512 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0143); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } }
while (0);
513
514 /* cache window 2: context */
515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0)
516 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0)
517 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0);
518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)) >> 16) >>
16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0)
519 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)) >> 16) >>
16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0)
520 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset + (128*1024)) >> 16) >>
16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0);
521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0144); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
522 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0144); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0145); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } }
while (0)
524 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0145); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } }
while (0);
525
526 /* non-cache window */
527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].fw_shared_gpu_addr))), 0); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((
0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared_gpu_addr)); } } while (0)
528 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].fw_shared_gpu_addr))), 0); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((
0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared_gpu_addr)); } } while (0)
529 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst
[inst_idx].fw_shared_gpu_addr))), 0); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((
0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared_gpu_addr)); } } while (0);
530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared_gpu_addr) >> 16) >> 16))), 0
); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared_gpu_addr) >> 16) >> 16
)); } } while (0)
531 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared_gpu_addr) >> 16) >> 16))), 0
); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared_gpu_addr) >> 16) >> 16
)); } } while (0)
532 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared_gpu_addr) >> 16) >> 16))), 0
); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared_gpu_addr) >> 16) >> 16
)); } } while (0);
533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0152); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
534 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0152); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared
)) + (4096 - 1)) & ~(4096 - 1))), 0); amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011))
, ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0)
536 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared
)) + (4096 - 1)) & ~(4096 - 1))), 0); amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011))
, ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0)
537 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared
)) + (4096 - 1)) & ~(4096 - 1))), 0); amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011))
, ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0);
538
539 /* VCN global tiling registers */
540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (adev->gfx.config.gb_addr_config
), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x0049); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = adev->gfx.config
.gb_addr_config; } } while (0)
541 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (adev->gfx.config.gb_addr_config
), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x0049); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = adev->gfx.config
.gb_addr_config; } } while (0);
542}
543
544/**
545 * vcn_v2_5_disable_clock_gating - disable VCN clock gating
546 *
547 * @adev: amdgpu_device pointer
548 *
549 * Disable clock gating for VCN block
550 */
551static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
552{
553 uint32_t data;
554 int i;
555
556 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
557 if (adev->vcn.harvest_config & (1 << i))
558 continue;
559 /* UVD disable CGC */
560 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008a), 0);
561 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24))
562 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
563 else
564 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK0x00000001L;
565 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
566 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
567 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008a)), (data), 0);
568
569 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0088), 0);
570 data &= ~(UVD_CGC_GATE__SYS_MASK0x00000001L
571 | UVD_CGC_GATE__UDEC_MASK0x00000002L
572 | UVD_CGC_GATE__MPEG2_MASK0x00000004L
573 | UVD_CGC_GATE__REGS_MASK0x00000008L
574 | UVD_CGC_GATE__RBC_MASK0x00000010L
575 | UVD_CGC_GATE__LMI_MC_MASK0x00000020L
576 | UVD_CGC_GATE__LMI_UMC_MASK0x00000040L
577 | UVD_CGC_GATE__IDCT_MASK0x00000080L
578 | UVD_CGC_GATE__MPRD_MASK0x00000100L
579 | UVD_CGC_GATE__MPC_MASK0x00000200L
580 | UVD_CGC_GATE__LBSI_MASK0x00000400L
581 | UVD_CGC_GATE__LRBBM_MASK0x00000800L
582 | UVD_CGC_GATE__UDEC_RE_MASK0x00001000L
583 | UVD_CGC_GATE__UDEC_CM_MASK0x00002000L
584 | UVD_CGC_GATE__UDEC_IT_MASK0x00004000L
585 | UVD_CGC_GATE__UDEC_DB_MASK0x00008000L
586 | UVD_CGC_GATE__UDEC_MP_MASK0x00010000L
587 | UVD_CGC_GATE__WCB_MASK0x00020000L
588 | UVD_CGC_GATE__VCPU_MASK0x00040000L
589 | UVD_CGC_GATE__MMSCH_MASK0x00100000L);
590
591 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0088)), (data), 0);
592
593 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0088), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0xFFFFFFFF
)) != (0)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x0088), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_CGC_GATE", (unsigned)0, (unsigned)(tmp_ & (0xFFFFFFFF
))); ret = -60; break; } } } while (0); ret; });
594
595 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008a), 0);
596 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L
597 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L
598 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L
599 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L
600 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L
601 | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L
602 | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L
603 | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L
604 | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L
605 | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L
606 | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L
607 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L
608 | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L
609 | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L
610 | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L
611 | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L
612 | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L
613 | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L
614 | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L
615 | UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L);
616 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008a)), (data), 0);
617
618 /* turn on */
619 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008c), 0);
620 data |= (UVD_SUVD_CGC_GATE__SRE_MASK0x00000001L
621 | UVD_SUVD_CGC_GATE__SIT_MASK0x00000002L
622 | UVD_SUVD_CGC_GATE__SMP_MASK0x00000004L
623 | UVD_SUVD_CGC_GATE__SCM_MASK0x00000008L
624 | UVD_SUVD_CGC_GATE__SDB_MASK0x00000010L
625 | UVD_SUVD_CGC_GATE__SRE_H264_MASK0x00000020L
626 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK0x00000040L
627 | UVD_SUVD_CGC_GATE__SIT_H264_MASK0x00000080L
628 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK0x00000100L
629 | UVD_SUVD_CGC_GATE__SCM_H264_MASK0x00000200L
630 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK0x00000400L
631 | UVD_SUVD_CGC_GATE__SDB_H264_MASK0x00000800L
632 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK0x00001000L
633 | UVD_SUVD_CGC_GATE__SCLR_MASK0x00002000L
634 | UVD_SUVD_CGC_GATE__UVD_SC_MASK0x00004000L
635 | UVD_SUVD_CGC_GATE__ENT_MASK0x00008000L
636 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK0x00020000L
637 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK0x00040000L
638 | UVD_SUVD_CGC_GATE__SITE_MASK0x00080000L
639 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK0x00100000L
640 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK0x00200000L
641 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK0x00400000L
642 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK0x00800000L
643 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK0x01000000L);
644 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008c)), (data), 0);
645
646 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008e), 0);
647 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L
648 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L
649 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L
650 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L
651 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L
652 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L
653 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK0x00000040L
654 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L
655 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L
656 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L);
657 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008e)), (data), 0);
658 }
659}
660
661static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
662 uint8_t sram_sel, int inst_idx, uint8_t indirect)
663{
664 uint32_t reg_data = 0;
665
666 /* enable sw clock gating control */
667 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24))
668 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
669 else
670 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
671 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
672 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
673 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L |
674 UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L |
675 UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L |
676 UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L |
677 UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L |
678 UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L |
679 UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L |
680 UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L |
681 UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L |
682 UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L |
683 UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L |
684 UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L |
685 UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L |
686 UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L |
687 UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L |
688 UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L |
689 UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L |
690 UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L |
691 UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L |
692 UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L);
693 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008a); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while
(0)
694 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008a); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while
(0);
695
696 /* turn off clock gating */
697 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0088); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
698 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0088); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
699
700 /* turn on SUVD clock gating */
701 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (1), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while (
0)
702 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (1), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while (
0);
703
704 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
705 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008e); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
706 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008e); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
707}
708
709/**
710 * vcn_v2_5_enable_clock_gating - enable VCN clock gating
711 *
712 * @adev: amdgpu_device pointer
713 *
714 * Enable clock gating for VCN block
715 */
716static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
717{
718 uint32_t data = 0;
719 int i;
720
721 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
722 if (adev->vcn.harvest_config & (1 << i))
723 continue;
724 /* enable UVD CGC */
725 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008a), 0);
726 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24))
727 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
728 else
729 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
730 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
731 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
732 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008a)), (data), 0);
733
734 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008a), 0);
735 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L
736 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L
737 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L
738 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L
739 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L
740 | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L
741 | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L
742 | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L
743 | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L
744 | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L
745 | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L
746 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L
747 | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L
748 | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L
749 | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L
750 | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L
751 | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L
752 | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L
753 | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L);
754 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008a)), (data), 0);
755
756 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x008e), 0);
757 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L
758 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L
759 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L
760 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L
761 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L
762 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L
763 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK0x00000040L
764 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L
765 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L
766 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L);
767 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x008e)), (data), 0);
768 }
769}
770
771static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect)
772{
773 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
774 struct amdgpu_ring *ring;
775 uint32_t rb_bufsz, tmp;
776
777 /* disable register anti-hang mechanism */
778 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L
); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
779 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L
); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
780 /* enable dynamic power gating mode */
781 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0);
782 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK0x00000004L;
783 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK0x00000100L;
784 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004)), (tmp), 0);
785
786 if (indirect)
787 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
788
789 /* enable clock gating */
790 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
791
792 /* enable VCPU clock */
793 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14);
794 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L;
795 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK0x10000000L;
796 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
797 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
798
799 /* disable master interupt */
800 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
801 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
802
803 /* setup mmUVD_LMI_CTRL */
804 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK0x00000100L |
805 UVD_LMI_CTRL__REQ_MODE_MASK0x00000200L |
806 UVD_LMI_CTRL__CRC_RESET_MASK0x00004000L |
807 UVD_LMI_CTRL__MASK_MC_URGENT_MASK0x00001000L |
808 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK0x00002000L |
809 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK0x00200000L |
810 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT0x0) |
811 0x00100000L);
812 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a8); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
813 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a8); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
814
815 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0)
816 VCN, 0, mmUVD_MPC_CNTL),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0)
817 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0);
818
819 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
820 VCN, 0, mmUVD_MPC_SET_MUXA0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
821 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
822 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
823 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
824 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0);
825
826 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
827 VCN, 0, mmUVD_MPC_SET_MUXB0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
828 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
829 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
830 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
831 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP]
[inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1
| ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0);
832
833 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1
<< 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
834 VCN, 0, mmUVD_MPC_SET_MUX),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1
<< 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
835 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1
<< 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
836 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1
<< 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
837 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1
<< 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0);
838
839 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
840
841 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x10), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while
(0)
842 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x10), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while
(0);
843 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026b); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while
(0)
844 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x3), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026b); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while
(0);
845
846 /* enable LMI MC and UMC channels */
847 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
848 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
849
850 /* unblock VCPU register access */
851 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00c6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
852 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00c6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
853
854 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14);
855 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L;
856 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
857 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
858
859 /* enable master interrupt */
860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0)
861 VCN, 0, mmUVD_MASTINT_EN),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0)
862 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)
), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0);
863
864 if (indirect)
865 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
866 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
867 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
868
869 ring = &adev->vcn.inst[inst_idx].ring_dec;
870 /* force RBC into idle state */
871 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
872 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
873 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
874 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
875 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
876 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
877 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02de)), (tmp), 0);
878
879 /* Stall DPG before WPTR/RPTR reset */
880 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
881 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
882 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0);
883 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
884
885 /* set the write pointer delay */
886 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e6)), (0), 0);
887
888 /* set the wb address */
889 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02df)), ((((u32)(((ring->gpu_addr) >> 16) >>
16)) >> 2)), 0)
890 (upper_32_bits(ring->gpu_addr) >> 2))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02df)), ((((u32)(((ring->gpu_addr) >> 16) >>
16)) >> 2)), 0);
891
892 /* program the RB_BASE for ring buffer */
893 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0432)), (((u32)(ring->gpu_addr))), 0)
894 lower_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0432)), (((u32)(ring->gpu_addr))), 0);
895 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0)
896 upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
897
898 /* Initialize the ring buffer's read and write pointers */
899 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0)), (0), 0);
900
901 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0016)), (0), 0);
902
903 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0), 0);
904 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1)), (((u32)(ring->wptr))), 0)
905 lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1)), (((u32)(ring->wptr))), 0);
906
907 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
908 /* Unstall DPG */
909 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
910 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
911
912 return 0;
913}
914
915static int vcn_v2_5_start(struct amdgpu_device *adev)
916{
917 struct amdgpu_ring *ring;
918 uint32_t rb_bufsz, tmp;
919 int i, j, k, r;
920
921 if (adev->pm.dpm_enabled)
922 amdgpu_dpm_enable_uvd(adev, true1);
923
924 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
925 if (adev->vcn.harvest_config & (1 << i))
926 continue;
927 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) {
928 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
929 continue;
930 }
931
932 /* disable register anti-hang mechanism */
933 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0) & ~(~0x00000003L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_), 0); } while
(0)
934 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0) & ~(~0x00000003L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_), 0); } while
(0);
935
936 /* set uvd status busy */
937 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0080), 0) | UVD_STATUS__UVD_BUSY;
938 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0080)), (tmp), 0);
939 }
940
941 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15))
942 return 0;
943
944 /*SW clock gating */
945 vcn_v2_5_disable_clock_gating(adev);
946
947 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
948 if (adev->vcn.harvest_config & (1 << i))
949 continue;
950 /* enable VCPU clock */
951 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_
|= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
952 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_
|= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
953
954 /* disable master interrupt */
955 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while
(0)
956 ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while
(0);
957
958 /* setup mmUVD_LMI_CTRL */
959 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x04a8), 0);
960 tmp &= ~0xff;
961 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a8)), (tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L), 0)
962 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a8)), (tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L), 0)
963 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a8)), (tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L), 0)
964 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a8)), (tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L), 0)
965 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a8)), (tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L), 0);
966
967 /* setup mmUVD_MPC_CNTL */
968 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x02cc), 0);
969 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK0x00000038L;
970 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT0x3;
971 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02cc)), (tmp), 0);
972
973 /* setup UVD_MPC_SET_MUXA0 */
974 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
975 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
976 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
977 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
978 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0);
979
980 /* setup UVD_MPC_SET_MUXB0 */
981 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
982 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
983 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
984 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0)
985 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18))), 0);
986
987 /* setup mmUVD_MPC_SET_MUX */
988 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6))), 0)
989 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6))), 0)
990 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6))), 0)
991 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6))), 0);
992 }
993
994 vcn_v2_5_mc_resume(adev);
995
996 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
997 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
998 if (adev->vcn.harvest_config & (1 << i))
999 continue;
1000 /* VCN global tiling registers */
1001 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0049)), (adev->gfx.config.gb_addr_config), 0)
1002 adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0049)), (adev->gfx.config.gb_addr_config), 0);
1003 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0049)), (adev->gfx.config.gb_addr_config), 0)
1004 adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0049)), (adev->gfx.config.gb_addr_config), 0);
1005
1006 /* enable LMI MC and UMC channels */
1007 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_
|= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while
(0)
1008 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_
|= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while
(0);
1009
1010 /* unblock VCPU register access */
1011 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while
(0)
1012 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while
(0);
1013
1014 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0)
1015 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0);
1016
1017 for (k = 0; k < 10; ++k) {
1018 uint32_t status;
1019
1020 for (j = 0; j < 100; ++j) {
1021 status = RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0080), 0);
1022 if (status & 2)
1023 break;
1024 if (amdgpu_emu_mode == 1)
1025 drm_msleep(500)mdelay(500);
1026 else
1027 mdelay(10);
1028 }
1029 r = 0;
1030 if (status & 2)
1031 break;
1032
1033 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n")__drm_err("VCN decode not responding, trying to reset the VCPU!!!\n"
);
1034 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1035 UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1036 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
1037 mdelay(10);
1038 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0)
1039 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0);
1040
1041 mdelay(10);
1042 r = -1;
1043 }
1044
1045 if (r) {
1046 DRM_ERROR("VCN decode not responding, giving up!!!\n")__drm_err("VCN decode not responding, giving up!!!\n");
1047 return r;
1048 }
1049
1050 /* enable master interrupt */
1051 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0)
1052 UVD_MASTINT_EN__VCPU_EN_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0)
1053 ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0);
1054
1055 /* clear the busy bit of VCN_STATUS */
1056 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1
)); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_
), 0); } while (0)
1057 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1
)); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_
), 0); } while (0);
1058
1059 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04b0)), (0), 0);
1060
1061 ring = &adev->vcn.inst[i].ring_dec;
1062 /* force RBC into idle state */
1063 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
1064 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
1069 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02de)), (tmp), 0);
1070
1071 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1072 /* program the RB_BASE for ring buffer */
1073 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0432)), (((u32)(ring->gpu_addr))), 0)
1074 lower_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0432)), (((u32)(ring->gpu_addr))), 0);
1075 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0)
1076 upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
1077
1078 /* Initialize the ring buffer's read and write pointers */
1079 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02e0)), (0), 0);
1080
1081 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x02e0), 0);
1082 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02e1)), (((u32)(ring->wptr))), 0)
1083 lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x02e1)), (((u32)(ring->wptr))), 0);
1084 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1085
1086 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1087 ring = &adev->vcn.inst[i].ring_enc[0];
1088 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00ad)), (((u32)(ring->wptr))), 0);
1089 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00ae)), (((u32)(ring->wptr))), 0);
1090 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00aa)), (ring->gpu_addr), 0);
1091 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00ab)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
1092 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00ac)), (ring->ring_size / 4), 0);
1093 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1094
1095 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1096 ring = &adev->vcn.inst[i].ring_enc[1];
1097 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00b2)), (((u32)(ring->wptr))), 0);
1098 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00b3)), (((u32)(ring->wptr))), 0);
1099 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00af)), (ring->gpu_addr), 0);
1100 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00b0)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
1101 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x00b1)), (ring->ring_size / 4), 0);
1102 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1103 }
1104
1105 return 0;
1106}
1107
1108static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1109 struct amdgpu_mm_table *table)
1110{
1111 uint32_t data = 0, loop = 0, size = 0;
1112 uint64_t addr = table->gpu_addr;
1113 struct mmsch_v1_1_init_header *header = NULL((void *)0);
1114
1115 header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1116 size = header->total_size;
1117
1118 /*
1119 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1120 * memory descriptor location
1121 */
1122 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x000c)), (((u32)(addr))), 0);
1123 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x000d)), (((u32)(((addr) >> 16) >> 16))), 0);
1124
1125 /* 2, update vmid of descriptor */
1126 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][0][0]
+ 0x000b), 0);
1127 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK0x0000001FL;
1128 /* use domain0 for MM scheduler */
1129 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT0x0);
1130 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x000b)), (data), 0);
1131
1132 /* 3, notify mmsch about the size of this descriptor */
1133 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x000e)), (size), 0);
1134
1135 /* 4, set resp to zero */
1136 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x0013)), (0), 0);
1137
1138 /*
1139 * 5, kick off the initialization and wait until
1140 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1141 */
1142 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0
] + 0x0012)), (0x10000001), 0);
1143
1144 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][0][0]
+ 0x0013), 0);
1145 loop = 10;
1146 while ((data & 0x10000002) != 0x10000002) {
1147 udelay(100);
1148 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][0][0]
+ 0x0013), 0);
1149 loop--;
1150 if (!loop)
1151 break;
1152 }
1153
1154 if (!loop) {
1155 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data)
1156 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data)
1157 data)printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data);
1158 return -EBUSY16;
1159 }
1160
1161 return 0;
1162}
1163
1164static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1165{
1166 struct amdgpu_ring *ring;
1167 uint32_t offset, size, tmp, i, rb_bufsz;
1168 uint32_t table_size = 0;
1169 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1170 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1171 struct mmsch_v1_0_cmd_end end = { { 0 } };
1172 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1173 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1174
1175 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1176 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1177 end.cmd_header.command_type = MMSCH_COMMAND__END;
1178
1179 header->version = MMSCH_VERSION(1 << 16 | 0);
1180 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1181 init_table += header->total_size;
1182
1183 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1184 header->eng[i].table_offset = header->total_size;
1185 header->eng[i].init_status = 0;
1186 header->eng[i].table_size = 0;
1187
1188 table_size = 0;
1189
1190 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT({ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; }
1191 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),{ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; }
1192 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY){ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; };
1193
1194 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
1195 /* mc resume*/
1196 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1197 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1198 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1199 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1200 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1201 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1202 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1203 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1204 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1205 offset = 0;
1206 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1207 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1208 } else {
1209 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1210 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1211 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1212 lower_32_bits(adev->vcn.inst[i].gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1213 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1214 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1215 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1216 upper_32_bits(adev->vcn.inst[i].gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1217 offset = size;
1218 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1219 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1220 AMDGPU_UVD_FIRMWARE_OFFSET >> 3){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1221 }
1222
1223 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1224 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1225 size){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1226 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1227 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1228 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1229 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; };
1230 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1231 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1232 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1233 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1234 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1235 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1236 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1237 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1238 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1239 AMDGPU_VCN_STACK_SIZE){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1240 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1241 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1242 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1243 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1244 AMDGPU_VCN_STACK_SIZE)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1245 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1246 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1247 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1248 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1249 AMDGPU_VCN_STACK_SIZE)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1250 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1251 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1252 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1253 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1254 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1255 AMDGPU_VCN_CONTEXT_SIZE){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1256
1257 ring = &adev->vcn.inst[i].ring_enc[0];
1258 ring->wptr = 0;
1259
1260 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1261 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1262 lower_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1263 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1264 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1265 upper_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; };
1266 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1267 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1268 ring->ring_size / 4){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1269
1270 ring = &adev->vcn.inst[i].ring_dec;
1271 ring->wptr = 0;
1272 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1273 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1274 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1275 lower_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1276 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1277 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1278 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1279 upper_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; };
1280
1281 /* force RBC into idle state */
1282 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
1283 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
1284 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
1285 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
1286 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
1287 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
1288 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02de)), (tmp)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1289 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02de)), (tmp)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1290
1291 /* add end packet */
1292 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end))__builtin_memcpy(((void *)init_table), (&end), (sizeof(struct
mmsch_v1_0_cmd_end)));
1293 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1294 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1295
1296 /* refine header */
1297 header->eng[i].table_size = table_size;
1298 header->total_size += table_size;
1299 }
1300
1301 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1302}
1303
1304static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1305{
1306 uint32_t tmp;
1307
1308 /* Wait for power status to be 1 */
1309 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1310 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1311
1312 /* wait for read ptr to be equal to write ptr */
1313 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ae), 0);
1314 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ad),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ad), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_ &
(0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; });
1315
1316 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b3), 0);
1317 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b2),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b2), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RB_RPTR2", (unsigned)tmp, (unsigned)(tmp_ &
(0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; });
1318
1319 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1), 0) & 0x7FFFFFFF;
1320 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e0),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RBC_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_
& (0xFFFFFFFF))); ret = -60; break; } } } while (0); ret
; });
1321
1322 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1323 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1324
1325 /* disable dynamic power gating mode */
1326 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L
); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
1327 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L
); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
1328
1329 return 0;
1330}
1331
1332static int vcn_v2_5_stop(struct amdgpu_device *adev)
1333{
1334 uint32_t tmp;
1335 int i, r = 0;
1336
1337 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1338 if (adev->vcn.harvest_config & (1 << i))
1339 continue;
1340 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) {
1341 r = vcn_v2_5_stop_dpg_mode(adev, i);
Value stored to 'r' is never read
1342 continue;
1343 }
1344
1345 /* wait for vcn idle */
1346 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x7
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (0x7))); ret = -60; break; } } } while (0); ret; });
1347 if (r)
1348 return r;
1349
1350 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK0x00000008L |
1351 UVD_LMI_STATUS__READ_CLEAN_MASK0x00000001L |
1352 UVD_LMI_STATUS__WRITE_CLEAN_MASK0x00000002L |
1353 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK0x00000004L;
1354 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp
)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ &
(tmp))); ret = -60; break; } } } while (0); ret; });
1355 if (r)
1356 return r;
1357
1358 /* block LMI UMC channel */
1359 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x04a6), 0);
1360 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK0x00000100L;
1361 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x04a6)), (tmp), 0);
1362
1363 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK0x00000200L|
1364 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK0x00000040L;
1365 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp
)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ &
(tmp))); ret = -60; break; } } } while (0); ret; });
1366 if (r)
1367 return r;
1368
1369 /* block VCPU register access */
1370 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0)
1371 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0)
1372 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0);
1373
1374 /* reset VCPU */
1375 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1376 UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1377 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
1378
1379 /* disable VCPU clock */
1380 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L))
; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0
); } while (0)
1381 ~(UVD_VCPU_CNTL__CLK_EN_MASK))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L))
; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0
); } while (0);
1382
1383 /* clear status */
1384 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1
] + 0x0080)), (0), 0);
1385
1386 vcn_v2_5_enable_clock_gating(adev);
1387
1388 /* enable register anti-hang mechanism */
1389 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0)
1390 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0)
1391 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0);
1392 }
1393
1394 if (adev->pm.dpm_enabled)
1395 amdgpu_dpm_enable_uvd(adev, false0);
1396
1397 return 0;
1398}
1399
1400static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1401 int inst_idx, struct dpg_pause_state *new_state)
1402{
1403 struct amdgpu_ring *ring;
1404 uint32_t reg_data = 0;
1405 int ret_code = 0;
1406
1407 /* pause/unpause if state is changed */
1408 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1409 DRM_DEBUG("dpg pause state changed %d -> %d",__drm_dbg(DRM_UT_CORE, "dpg pause state changed %d -> %d",
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->
fw_based)
1410 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based)__drm_dbg(DRM_UT_CORE, "dpg pause state changed %d -> %d",
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->
fw_based);
1411 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014), 0) &
1412 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK0x00000008L);
1413
1414 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1415 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1416 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1417
1418 if (!ret_code) {
1419 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
1420
1421 /* pause DPG */
1422 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L;
1423 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014)), (reg_data), 0);
1424
1425 /* wait for ACK */
1426 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; })
1427 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; })
1428 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; });
1429
1430 /* Stall DPG before WPTR/RPTR reset */
1431 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
1432 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
1433 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0);
1434
1435 /* Restore */
1436 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1437 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1438 ring->wptr = 0;
1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00aa)), (ring->gpu_addr), 0);
1440 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ab)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
1441 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ac)), (ring->ring_size / 4), 0);
1442 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ad)), (((u32)(ring->wptr))), 0);
1443 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ae)), (((u32)(ring->wptr))), 0);
1444 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1445
1446 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1447 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1448 ring->wptr = 0;
1449 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00af)), (ring->gpu_addr), 0);
1450 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b0)), (((u32)(((ring->gpu_addr) >> 16) >>
16))), 0);
1451 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b1)), (ring->ring_size / 4), 0);
1452 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b2)), (((u32)(ring->wptr))), 0);
1453 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b3)), (((u32)(ring->wptr))), 0);
1454 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1455
1456 /* Unstall DPG */
1457 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
1458 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
1459
1460 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ =
tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } }
} while (0); ret; })
1461 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ =
tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } }
} while (0); ret; });
1462 }
1463 } else {
1464 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L;
1465 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014)), (reg_data), 0);
1466 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1467 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1468 }
1469 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1470 }
1471
1472 return 0;
1473}
1474
1475/**
1476 * vcn_v2_5_dec_ring_get_rptr - get read pointer
1477 *
1478 * @ring: amdgpu_ring pointer
1479 *
1480 * Returns the current hardware read pointer
1481 */
1482static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1483{
1484 struct amdgpu_device *adev = ring->adev;
1485
1486 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x02e0), 0);
1487}
1488
1489/**
1490 * vcn_v2_5_dec_ring_get_wptr - get write pointer
1491 *
1492 * @ring: amdgpu_ring pointer
1493 *
1494 * Returns the current hardware write pointer
1495 */
1496static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1497{
1498 struct amdgpu_device *adev = ring->adev;
1499
1500 if (ring->use_doorbell)
1501 return adev->wb.wb[ring->wptr_offs];
1502 else
1503 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x02e1), 0);
1504}
1505
1506/**
1507 * vcn_v2_5_dec_ring_set_wptr - set write pointer
1508 *
1509 * @ring: amdgpu_ring pointer
1510 *
1511 * Commits the write pointer to the hardware
1512 */
1513static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1514{
1515 struct amdgpu_device *adev = ring->adev;
1516
1517 if (ring->use_doorbell) {
1518 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1519 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1520 } else {
1521 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x02e1)), (((u32)(ring->wptr))), 0);
1522 }
1523}
1524
1525static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1526 .type = AMDGPU_RING_TYPE_VCN_DEC,
1527 .align_mask = 0xf,
1528 .vmhub = AMDGPU_MMHUB_12,
1529 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1530 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1531 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1532 .emit_frame_size =
1533 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 6 +
1534 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 8 +
1535 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1536 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1537 6,
1538 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1539 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1540 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1541 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1542 .test_ring = vcn_v2_0_dec_ring_test_ring,
1543 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1544 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1545 .insert_start = vcn_v2_0_dec_ring_insert_start,
1546 .insert_end = vcn_v2_0_dec_ring_insert_end,
1547 .pad_ib = amdgpu_ring_generic_pad_ib,
1548 .begin_use = amdgpu_vcn_ring_begin_use,
1549 .end_use = amdgpu_vcn_ring_end_use,
1550 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1551 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1552 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1553};
1554
1555/**
1556 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1557 *
1558 * @ring: amdgpu_ring pointer
1559 *
1560 * Returns the current hardware enc read pointer
1561 */
1562static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1563{
1564 struct amdgpu_device *adev = ring->adev;
1565
1566 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1567 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x00ad), 0);
1568 else
1569 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x00b2), 0);
1570}
1571
1572/**
1573 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1574 *
1575 * @ring: amdgpu_ring pointer
1576 *
1577 * Returns the current hardware enc write pointer
1578 */
1579static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1580{
1581 struct amdgpu_device *adev = ring->adev;
1582
1583 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1584 if (ring->use_doorbell)
1585 return adev->wb.wb[ring->wptr_offs];
1586 else
1587 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x00ae), 0);
1588 } else {
1589 if (ring->use_doorbell)
1590 return adev->wb.wb[ring->wptr_offs];
1591 else
1592 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring->
me][1] + 0x00b3), 0);
1593 }
1594}
1595
1596/**
1597 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1598 *
1599 * @ring: amdgpu_ring pointer
1600 *
1601 * Commits the enc write pointer to the hardware
1602 */
1603static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1604{
1605 struct amdgpu_device *adev = ring->adev;
1606
1607 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1608 if (ring->use_doorbell) {
1609 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1610 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1611 } else {
1612 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00ae)), (((u32)(ring->wptr))), 0);
1613 }
1614 } else {
1615 if (ring->use_doorbell) {
1616 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1617 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1618 } else {
1619 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00b3)), (((u32)(ring->wptr))), 0);
1620 }
1621 }
1622}
1623
1624static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1625 .type = AMDGPU_RING_TYPE_VCN_ENC,
1626 .align_mask = 0x3f,
1627 .nop = VCN_ENC_CMD_NO_OP0x00000000,
1628 .vmhub = AMDGPU_MMHUB_12,
1629 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1630 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1631 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1632 .emit_frame_size =
1633 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 +
1634 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 4 +
1635 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1636 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1637 1, /* vcn_v2_0_enc_ring_insert_end */
1638 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1639 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1640 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1641 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1642 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1643 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1644 .insert_nop = amdgpu_ring_insert_nop,
1645 .insert_end = vcn_v2_0_enc_ring_insert_end,
1646 .pad_ib = amdgpu_ring_generic_pad_ib,
1647 .begin_use = amdgpu_vcn_ring_begin_use,
1648 .end_use = amdgpu_vcn_ring_end_use,
1649 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1650 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1651 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1652};
1653
1654static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1655{
1656 int i;
1657
1658 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1659 if (adev->vcn.harvest_config & (1 << i))
1660 continue;
1661 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1662 adev->vcn.inst[i].ring_dec.me = i;
1663 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i)printk("\0016" "[" "drm" "] " "VCN(%d) decode is enabled in VM mode\n"
, i);
1664 }
1665}
1666
1667static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1668{
1669 int i, j;
1670
1671 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1672 if (adev->vcn.harvest_config & (1 << j))
1673 continue;
1674 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1675 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1676 adev->vcn.inst[j].ring_enc[i].me = j;
1677 }
1678 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j)printk("\0016" "[" "drm" "] " "VCN(%d) encode is enabled in VM mode\n"
, j);
1679 }
1680}
1681
1682static bool_Bool vcn_v2_5_is_idle(void *handle)
1683{
1684 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1685 int i, ret = 1;
1686
1687 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1688 if (adev->vcn.harvest_config & (1 << i))
1689 continue;
1690 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1]
+ 0x0080), 0) == UVD_STATUS__IDLE);
1691 }
1692
1693 return ret;
1694}
1695
1696static int vcn_v2_5_wait_for_idle(void *handle)
1697{
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699 int i, ret = 0;
1700
1701 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1702 if (adev->vcn.harvest_config & (1 << i))
1703 continue;
1704 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0
); ret; })
1705 UVD_STATUS__IDLE)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0
); ret; });
1706 if (ret)
1707 return ret;
1708 }
1709
1710 return ret;
1711}
1712
1713static int vcn_v2_5_set_clockgating_state(void *handle,
1714 enum amd_clockgating_state state)
1715{
1716 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1717 bool_Bool enable = (state == AMD_CG_STATE_GATE);
1718
1719 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1720 return 0;
1721
1722 if (enable) {
1723 if (!vcn_v2_5_is_idle(handle))
1724 return -EBUSY16;
1725 vcn_v2_5_enable_clock_gating(adev);
1726 } else {
1727 vcn_v2_5_disable_clock_gating(adev);
1728 }
1729
1730 return 0;
1731}
1732
1733static int vcn_v2_5_set_powergating_state(void *handle,
1734 enum amd_powergating_state state)
1735{
1736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1737 int ret;
1738
1739 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1740 return 0;
1741
1742 if(state == adev->vcn.cur_state)
1743 return 0;
1744
1745 if (state == AMD_PG_STATE_GATE)
1746 ret = vcn_v2_5_stop(adev);
1747 else
1748 ret = vcn_v2_5_start(adev);
1749
1750 if(!ret)
1751 adev->vcn.cur_state = state;
1752
1753 return ret;
1754}
1755
1756static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1757 struct amdgpu_irq_src *source,
1758 unsigned type,
1759 enum amdgpu_interrupt_state state)
1760{
1761 return 0;
1762}
1763
1764static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1765 struct amdgpu_irq_src *source,
1766 struct amdgpu_iv_entry *entry)
1767{
1768 uint32_t ip_instance;
1769
1770 switch (entry->client_id) {
1771 case SOC15_IH_CLIENTID_VCN:
1772 ip_instance = 0;
1773 break;
1774 case SOC15_IH_CLIENTID_VCN1:
1775 ip_instance = 1;
1776 break;
1777 default:
1778 DRM_ERROR("Unhandled client id: %d\n", entry->client_id)__drm_err("Unhandled client id: %d\n", entry->client_id);
1779 return 0;
1780 }
1781
1782 DRM_DEBUG("IH: VCN TRAP\n")__drm_dbg(DRM_UT_CORE, "IH: VCN TRAP\n");
1783
1784 switch (entry->src_id) {
1785 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124:
1786 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1787 break;
1788 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119:
1789 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1790 break;
1791 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY120:
1792 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1793 break;
1794 default:
1795 DRM_ERROR("Unhandled interrupt: %d %d\n",__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0])
1796 entry->src_id, entry->src_data[0])__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0]);
1797 break;
1798 }
1799
1800 return 0;
1801}
1802
1803static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1804 .set = vcn_v2_5_set_interrupt_state,
1805 .process = vcn_v2_5_process_interrupt,
1806};
1807
1808static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1809{
1810 int i;
1811
1812 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1813 if (adev->vcn.harvest_config & (1 << i))
1814 continue;
1815 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1816 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1817 }
1818}
1819
1820static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1821 .name = "vcn_v2_5",
1822 .early_init = vcn_v2_5_early_init,
1823 .late_init = NULL((void *)0),
1824 .sw_init = vcn_v2_5_sw_init,
1825 .sw_fini = vcn_v2_5_sw_fini,
1826 .hw_init = vcn_v2_5_hw_init,
1827 .hw_fini = vcn_v2_5_hw_fini,
1828 .suspend = vcn_v2_5_suspend,
1829 .resume = vcn_v2_5_resume,
1830 .is_idle = vcn_v2_5_is_idle,
1831 .wait_for_idle = vcn_v2_5_wait_for_idle,
1832 .check_soft_reset = NULL((void *)0),
1833 .pre_soft_reset = NULL((void *)0),
1834 .soft_reset = NULL((void *)0),
1835 .post_soft_reset = NULL((void *)0),
1836 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1837 .set_powergating_state = vcn_v2_5_set_powergating_state,
1838};
1839
1840const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1841{
1842 .type = AMD_IP_BLOCK_TYPE_VCN,
1843 .major = 2,
1844 .minor = 5,
1845 .rev = 0,
1846 .funcs = &vcn_v2_5_ip_funcs,
1847};