/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu

Bug Summary

File:	dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
Warning:	line 1403, column 6 Access to field 'sg' results in a dereference of a null pointer (loaded from variable 'ttm')
Annotated Source Code

Press '?' to see keyboard shortcuts
Show analyzer invocation
clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_ttm.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1/*
* Copyright 2009 Jerome Glisse.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
*/
26/*
* Authors:
*    Jerome Glisse <glisse@freedesktop.org>
*    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
*    Dave Airlie
*/

33#include <linux/dma-mapping.h>
34#include <linux/iommu.h>
35#include <linux/hmm.h>
36#include <linux/pagemap.h>
37#include <linux/sched/task.h>
38#include <linux/sched/mm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swap.h>
42#include <linux/swiotlb.h>
43#include <linux/dma-buf.h>
44#include <linux/sizes.h>

46#include <drm/ttm/ttm_bo_api.h>
47#include <drm/ttm/ttm_bo_driver.h>
48#include <drm/ttm/ttm_placement.h>
49#include <drm/ttm/ttm_module.h>
50#include <drm/ttm/ttm_page_alloc.h>

52#include <drm/drm_debugfs.h>
53#include <drm/amdgpu_drm.h>

55#include "amdgpu.h"
56#include "amdgpu_object.h"
57#include "amdgpu_trace.h"
58#include "amdgpu_amdkfd.h"
59#include "amdgpu_sdma.h"
60#include "amdgpu_ras.h"
61#include "amdgpu_atomfirmware.h"
62#include "bif/bif_4_1_d.h"

64#define AMDGPU_TTM_VRAM_MAX_DW_READ(size_t)128	(size_t)128

66static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
		   struct ttm_tt *ttm,
		   struct ttm_resource *bo_mem);

70static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
		    unsigned int type,
		    uint64_t size_in_page)
73{
return ttm_range_man_init(&adev->mman.bdev, type,
		  false0, size_in_page);
76}

78/**
* amdgpu_evict_flags - Compute placement flags
*
* @bo: The buffer object to evict
* @placement: Possible destination(s) for evicted BO
*
* Fill in placement data when ttm_bo_evict() is called
*/
86static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
		struct ttm_placement *placement)
88{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
static const struct ttm_place placements = {
.fpfn = 0,
.lpfn = 0,
.mem_type = TTM_PL_SYSTEM0,
.flags = TTM_PL_MASK_CACHING((1 << 16) | (1 << 17) | (1 << 18))
};

/* Don't handle scatter gather BOs */
if (bo->type == ttm_bo_type_sg) {
placement->num_placement = 0;
placement->num_busy_placement = 0;
return;
}

/* Object isn't an AMDGPU object so ignore */
if (!amdgpu_bo_is_amdgpu_bo(bo)) {
placement->placement = &placements;
placement->busy_placement = &placements;
placement->num_placement = 1;
placement->num_busy_placement = 1;
return;
}

abo = ttm_to_amdgpu_bo(bo);
switch (bo->mem.mem_type) {
case AMDGPU_PL_GDS(3 + 0):
case AMDGPU_PL_GWS(3 + 1):
case AMDGPU_PL_OA(3 + 2):
placement->num_placement = 0;
placement->num_busy_placement = 0;
return;

case TTM_PL_VRAM2:
if (!adev->mman.buffer_funcs_enabled) {
	/* Move to system memory */
	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU0x1);
} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
	   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0)) &&
	   amdgpu_bo_in_cpu_visible_vram(abo)) {

	/* Try evicting to the CPU inaccessible part of VRAM
	 * first, but only set GTT as busy placement, so this
	 * BO will be evicted to GTT rather than causing other
	 * BOs to be evicted from VRAM
	 */
	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM0x4 |
					 AMDGPU_GEM_DOMAIN_GTT0x2);
	abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT12;
	abo->placements[0].lpfn = 0;
	abo->placement.busy_placement = &abo->placements[1];
	abo->placement.num_busy_placement = 1;
} else {
	/* Move to GTT memory */
	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT0x2);
}
break;
case TTM_PL_TT1:
default:
amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU0x1);
break;
}
*placement = abo->placement;
153}

155/**
* amdgpu_verify_access - Verify access for a mmap call
*
* @bo:	The buffer object to map
* @filp: The file pointer from the process performing the mmap
*
* This is called by ttm_bo_mmap() to verify whether a process
* has the right to mmap a BO to their process space.
*/
164static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
165{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct drm_file *file_priv = (void *)filp;

/*
* Don't verify access for KFD BOs. They don't have a GEM
* object associated with them.
*/
if (abo->kfd_bo)
return 0;

if (amdgpu_ttm_tt_get_usermm(bo->ttm))
return -EPERM1;
return drm_vma_node_verify_access(&abo->tbo.base.vma_node, file_priv);
179}

181/**
* amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
*
* @bo: The bo to assign the memory to.
* @mm_node: Memory manager node for drm allocator.
* @mem: The region where the bo resides.
*
*/
189static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
		    struct drm_mm_node *mm_node,
		    struct ttm_resource *mem)
192{
uint64_t addr = 0;

if (mm_node->start != AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL) {
addr = mm_node->start << PAGE_SHIFT12;
addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
				mem->mem_type);
}
return addr;
201}

203/**
* amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
* @offset. It also modifies the offset to be within the drm_mm_node returned
*
* @mem: The region where the bo resides.
* @offset: The offset that drm_mm_node is used for finding.
*
*/
211static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
			       uint64_t *offset)
213{
struct drm_mm_node *mm_node = mem->mm_node;

while (*offset >= (mm_node->size << PAGE_SHIFT12)) {
*offset -= (mm_node->size << PAGE_SHIFT12);
++mm_node;
}
return mm_node;
221}

223/**
* amdgpu_ttm_map_buffer - Map memory into the GART windows
* @bo: buffer object to map
* @mem: memory object to map
* @mm_node: drm_mm node object to map
* @num_pages: number of pages to map
* @offset: offset into @mm_node where to start
* @window: which GART window to use
* @ring: DMA ring to use for the copy
* @tmz: if we should setup a TMZ enabled mapping
* @addr: resulting address inside the MC address space
*
* Setup one of the GART windows to access a specific piece of memory or return
* the physical address for local memory.
*/
238static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
		 struct ttm_resource *mem,
		 struct drm_mm_node *mm_node,
		 unsigned num_pages, uint64_t offset,
		 unsigned window, struct amdgpu_ring *ring,
		 bool_Bool tmz, uint64_t *addr)
244{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_job *job;
unsigned num_dw, num_bytes;
struct dma_fence *fence;
uint64_t src_addr, dst_addr;
void *cpu_addr;
uint64_t flags;
unsigned int i;
int r;

BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <((!(adev->mman.buffer_funcs->copy_max_bytes < 512 * 8
)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c"
, 256, "!(adev->mman.buffer_funcs->copy_max_bytes < 512 * 8)"
))
      AMDGPU_GTT_MAX_TRANSFER_SIZE * 8)((!(adev->mman.buffer_funcs->copy_max_bytes < 512 * 8
)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c"
, 256, "!(adev->mman.buffer_funcs->copy_max_bytes < 512 * 8)"
));

/* Map only what can't be accessed directly */
if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL) {
*addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
return 0;
}

*addr = adev->gmc.gart_start;
*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE512 *
AMDGPU_GPU_PAGE_SIZE4096;
*addr += offset & ~LINUX_PAGE_MASK(~((1 << 12) - 1));

num_dw = roundup2(adev->mman.buffer_funcs->copy_num_dw, 8)(((adev->mman.buffer_funcs->copy_num_dw) + ((8) - 1)) &
 (~((__typeof(adev->mman.buffer_funcs->copy_num_dw))(8)
 - 1)));
num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE((1 << 12) / 4096);

r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
		     AMDGPU_IB_POOL_DELAYED, &job);
if (r)
return r;

src_addr = num_dw * 4;
src_addr += job->ibs[0].gpu_addr;

dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE512 * 8;
amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,(adev)->mman.buffer_funcs->emit_copy_buffer((&job->
ibs[0]), (src_addr), (dst_addr), (num_bytes), (0))
		dst_addr, num_bytes, false)(adev)->mman.buffer_funcs->emit_copy_buffer((&job->
ibs[0]), (src_addr), (dst_addr), (num_bytes), (0));

amdgpu_ring_pad_ib(ring, &job->ibs[0])((ring)->funcs->pad_ib((ring), (&job->ibs[0])));
WARN_ON(job->ibs[0].length_dw > num_dw)({ int __ret = !!(job->ibs[0].length_dw > num_dw); if (
__ret) printf("WARNING %s failed at %s:%d\n", "job->ibs[0].length_dw > num_dw"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c", 286); __builtin_expect
(!!(__ret), 0); });

flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
if (tmz)
flags |= AMDGPU_PTE_TMZ(1ULL << 3);

cpu_addr = &job->ibs[0].ptr[num_dw];

if (mem->mem_type == TTM_PL_TT1) {
struct ttm_dma_tt *dma;
dma_addr_t *dma_address;

dma = container_of(bo->ttm, struct ttm_dma_tt, ttm)({ const __typeof( ((struct ttm_dma_tt *)0)->ttm ) *__mptr
 = (bo->ttm); (struct ttm_dma_tt *)( (char *)__mptr - __builtin_offsetof
(struct ttm_dma_tt, ttm) );});
dma_address = &dma->dma_address[offset >> PAGE_SHIFT12];
r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
		    cpu_addr);
if (r)
	goto error_free;
} else {
dma_addr_t dma_address;

dma_address = (mm_node->start << PAGE_SHIFT12) + offset;
dma_address += adev->vm_manager.vram_base_offset;

for (i = 0; i < num_pages; ++i) {
	r = amdgpu_gart_map(adev, i << PAGE_SHIFT12, 1,
			    &dma_address, flags, cpu_addr);
	if (r)
		goto error_free;

	dma_address += PAGE_SIZE(1 << 12);
}
}

r = amdgpu_job_submit(job, &adev->mman.entity,
	      AMDGPU_FENCE_OWNER_UNDEFINED((void *)0ul), &fence);
if (r)
goto error_free;

dma_fence_put(fence);

return r;

329error_free:
amdgpu_job_free(job);
return r;
332}

334/**
* amdgpu_copy_ttm_mem_to_mem - Helper function for copy
* @adev: amdgpu device
* @src: buffer/address where to read from
* @dst: buffer/address where to write to
* @size: number of bytes to copy
* @tmz: if a secure copy should be used
* @resv: resv object to sync to
* @f: Returns the last fence if multiple jobs are submitted.
*
* The function copies @size bytes from {src->mem + src->offset} to
* {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
* move and different for a BO to BO copy.
*
*/
349int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
	       const struct amdgpu_copy_mem *src,
	       const struct amdgpu_copy_mem *dst,
	       uint64_t size, bool_Bool tmz,
	       struct dma_resv *resv,
	       struct dma_fence **f)
355{
const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE512 *
			AMDGPU_GPU_PAGE_SIZE4096);

uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
struct drm_mm_node *src_mm, *dst_mm;
struct dma_fence *fence = NULL((void *)0);
int r = 0;

if (!adev->mman.buffer_funcs_enabled) {
DRM_ERROR("Trying to move memory with ring turned off.\n")__drm_err("Trying to move memory with ring turned off.\n");
return -EINVAL22;
}

src_offset = src->offset;
if (src->mem->mm_node) {
src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
src_node_size = (src_mm->size << PAGE_SHIFT12) - src_offset;
} else {
src_mm = NULL((void *)0);
src_node_size = ULLONG_MAX0xffffffffffffffffULL;
}

dst_offset = dst->offset;
if (dst->mem->mm_node) {
dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
dst_node_size = (dst_mm->size << PAGE_SHIFT12) - dst_offset;
} else {
dst_mm = NULL((void *)0);
dst_node_size = ULLONG_MAX0xffffffffffffffffULL;
}

mutex_lock(&adev->mman.gtt_window_lock)rw_enter_write(&adev->mman.gtt_window_lock);

while (size) {
uint32_t src_page_offset = src_offset & ~LINUX_PAGE_MASK(~((1 << 12) - 1));
uint32_t dst_page_offset = dst_offset & ~LINUX_PAGE_MASK(~((1 << 12) - 1));
struct dma_fence *next;
uint32_t cur_size;
uint64_t from, to;

/* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 * begins at an offset, then adjust the size accordingly
 */
cur_size = max(src_page_offset, dst_page_offset)(((src_page_offset)>(dst_page_offset))?(src_page_offset):(
dst_page_offset));
cur_size = min(min3(src_node_size, dst_node_size, size),((((((src_node_size)<((((dst_node_size)<(size))?(dst_node_size
):(size))))?(src_node_size):((((dst_node_size)<(size))?(dst_node_size
):(size)))))<((uint64_t)(GTT_MAX_BYTES - cur_size)))?((((src_node_size
)<((((dst_node_size)<(size))?(dst_node_size):(size))))?
(src_node_size):((((dst_node_size)<(size))?(dst_node_size)
:(size))))):((uint64_t)(GTT_MAX_BYTES - cur_size)))
	       (uint64_t)(GTT_MAX_BYTES - cur_size))((((((src_node_size)<((((dst_node_size)<(size))?(dst_node_size
):(size))))?(src_node_size):((((dst_node_size)<(size))?(dst_node_size
):(size)))))<((uint64_t)(GTT_MAX_BYTES - cur_size)))?((((src_node_size
)<((((dst_node_size)<(size))?(dst_node_size):(size))))?
(src_node_size):((((dst_node_size)<(size))?(dst_node_size)
:(size))))):((uint64_t)(GTT_MAX_BYTES - cur_size)));

/* Map src to window 0 and dst to window 1. */
r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
			  PFN_UP(cur_size + src_page_offset)(((cur_size + src_page_offset) + (1 << 12)-1) >> 12
),
			  src_offset, 0, ring, tmz, &from);
if (r)
	goto error;

r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
			  PFN_UP(cur_size + dst_page_offset)(((cur_size + dst_page_offset) + (1 << 12)-1) >> 12
),
			  dst_offset, 1, ring, tmz, &to);
if (r)
	goto error;

r = amdgpu_copy_buffer(ring, from, to, cur_size,
		       resv, &next, false0, true1, tmz);
if (r)
	goto error;

dma_fence_put(fence);
fence = next;

size -= cur_size;
if (!size)
	break;

src_node_size -= cur_size;
if (!src_node_size) {
	++src_mm;
	src_node_size = src_mm->size << PAGE_SHIFT12;
	src_offset = 0;
} else {
	src_offset += cur_size;
}

dst_node_size -= cur_size;
if (!dst_node_size) {
	++dst_mm;
	dst_node_size = dst_mm->size << PAGE_SHIFT12;
	dst_offset = 0;
} else {
	dst_offset += cur_size;
}
}
447error:
mutex_unlock(&adev->mman.gtt_window_lock)rw_exit_write(&adev->mman.gtt_window_lock);
if (f)
*f = dma_fence_get(fence);
dma_fence_put(fence);
return r;
453}

455/**
* amdgpu_move_blit - Copy an entire buffer to another buffer
*
* This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
* help move buffers to and from VRAM.
*/
461static int amdgpu_move_blit(struct ttm_buffer_object *bo,
	    bool_Bool evict,
	    struct ttm_resource *new_mem,
	    struct ttm_resource *old_mem)
465{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_copy_mem src, dst;
struct dma_fence *fence = NULL((void *)0);
int r;

src.bo = bo;
dst.bo = bo;
src.mem = old_mem;
dst.mem = new_mem;
src.offset = 0;
dst.offset = 0;

r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
		       new_mem->num_pages << PAGE_SHIFT12,
		       amdgpu_bo_encrypted(abo),
		       bo->base.resv, &fence);
if (r)
goto error;

/* clear the space being freed */
if (old_mem->mem_type == TTM_PL_VRAM2 &&
   (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE(1 << 9))) {
struct dma_fence *wipe_fence = NULL((void *)0);

r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON0xd0bed0be,
		       NULL((void *)0), &wipe_fence);
if (r) {
	goto error;
} else if (wipe_fence) {
	dma_fence_put(fence);
	fence = wipe_fence;
}
}

/* Always block for VM page tables before committing the new location */
if (bo->type == ttm_bo_type_kernel)
r = ttm_bo_move_accel_cleanup(bo, fence, true1, false0, new_mem);
else
r = ttm_bo_move_accel_cleanup(bo, fence, evict, true1, new_mem);
dma_fence_put(fence);
return r;

509error:
if (fence)
dma_fence_wait(fence, false0);
dma_fence_put(fence);
return r;
514}

516/**
* amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
*
* Called by amdgpu_bo_move().
*/
521static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool_Bool evict,
		struct ttm_operation_ctx *ctx,
		struct ttm_resource *new_mem)
524{
struct ttm_resource *old_mem = &bo->mem;
struct ttm_resource tmp_mem;
struct ttm_place placements;
struct ttm_placement placement;
int r;

/* create space/pages for new_mem in GTT space */
tmp_mem = *new_mem;
tmp_mem.mm_node = NULL((void *)0);
placement.num_placement = 1;
placement.placement = &placements;
placement.num_busy_placement = 1;
placement.busy_placement = &placements;
placements.fpfn = 0;
placements.lpfn = 0;
placements.mem_type = TTM_PL_TT1;
placements.flags = TTM_PL_MASK_CACHING((1 << 16) | (1 << 17) | (1 << 18));
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
pr_err("Failed to find GTT space for blit from VRAM\n")printk("\0013" "amdgpu: " "Failed to find GTT space for blit from VRAM\n"
);
return r;
}

/* set caching flags */
r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
goto out_cleanup;
}

r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
if (unlikely(r)__builtin_expect(!!(r), 0))
goto out_cleanup;

/* Bind the memory to the GTT space */
r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
goto out_cleanup;
}

/* blit VRAM to GTT */
r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
goto out_cleanup;
}

/* move BO (in tmp_mem) to new_mem */
r = ttm_bo_move_ttm(bo, ctx, new_mem);
572out_cleanup:
ttm_resource_free(bo, &tmp_mem);
return r;
575}

577/**
* amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
*
* Called by amdgpu_bo_move().
*/
582static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool_Bool evict,
		struct ttm_operation_ctx *ctx,
		struct ttm_resource *new_mem)
585{
struct ttm_resource *old_mem = &bo->mem;
struct ttm_resource tmp_mem;
struct ttm_placement placement;
struct ttm_place placements;
int r;

/* make space in GTT for old_mem buffer */
tmp_mem = *new_mem;
tmp_mem.mm_node = NULL((void *)0);
placement.num_placement = 1;
placement.placement = &placements;
placement.num_busy_placement = 1;
placement.busy_placement = &placements;
placements.fpfn = 0;
placements.lpfn = 0;
placements.mem_type = TTM_PL_TT1;
placements.flags = TTM_PL_MASK_CACHING((1 << 16) | (1 << 17) | (1 << 18));
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
pr_err("Failed to find GTT space for blit to VRAM\n")printk("\0013" "amdgpu: " "Failed to find GTT space for blit to VRAM\n"
);
return r;
}

/* move/bind old memory to GTT space */
r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
goto out_cleanup;
}

/* copy to VRAM */
r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
goto out_cleanup;
}
620out_cleanup:
ttm_resource_free(bo, &tmp_mem);
return r;
623}

625/**
* amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
*
* Called by amdgpu_bo_move()
*/
630static bool_Bool amdgpu_mem_visible(struct amdgpu_device *adev,
	       struct ttm_resource *mem)
632{
struct drm_mm_node *nodes = mem->mm_node;

if (mem->mem_type == TTM_PL_SYSTEM0 ||
   mem->mem_type == TTM_PL_TT1)
return true1;
if (mem->mem_type != TTM_PL_VRAM2)
return false0;

/* ttm_resource_ioremap only supports contiguous memory */
if (nodes->size != mem->num_pages)
return false0;

return ((nodes->start + nodes->size) << PAGE_SHIFT12)
<= adev->gmc.visible_vram_size;
647}

649/**
* amdgpu_bo_move - Move a buffer object to a new memory location
*
* Called by ttm_bo_handle_move_mem()
*/
654static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool_Bool evict,
	  struct ttm_operation_ctx *ctx,
	  struct ttm_resource *new_mem)
657{
struct amdgpu_device *adev;
struct amdgpu_bo *abo;
struct ttm_resource *old_mem = &bo->mem;
int r;

/* Can't move a pinned BO */
abo = ttm_to_amdgpu_bo(bo);
if (WARN_ON_ONCE(abo->pin_count > 0)({ static int __warned; int __ret = !!(abo->pin_count >
 0); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "abo->pin_count > 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c"
, 665); __warned = 1; } __builtin_expect(!!(__ret), 0); }))
return -EINVAL22;

adev = amdgpu_ttm_adev(bo->bdev);

if (old_mem->mem_type == TTM_PL_SYSTEM0 && bo->ttm == NULL((void *)0)) {
ttm_bo_move_null(bo, new_mem);
return 0;
}
if ((old_mem->mem_type == TTM_PL_TT1 &&
    new_mem->mem_type == TTM_PL_SYSTEM0) ||
   (old_mem->mem_type == TTM_PL_SYSTEM0 &&
    new_mem->mem_type == TTM_PL_TT1)) {
/* bind is enough */
ttm_bo_move_null(bo, new_mem);
return 0;
}
if (old_mem->mem_type == AMDGPU_PL_GDS(3 + 0) ||
   old_mem->mem_type == AMDGPU_PL_GWS(3 + 1) ||
   old_mem->mem_type == AMDGPU_PL_OA(3 + 2) ||
   new_mem->mem_type == AMDGPU_PL_GDS(3 + 0) ||
   new_mem->mem_type == AMDGPU_PL_GWS(3 + 1) ||
   new_mem->mem_type == AMDGPU_PL_OA(3 + 2)) {
/* Nothing to save here */
ttm_bo_move_null(bo, new_mem);
return 0;
}

if (!adev->mman.buffer_funcs_enabled) {
r = -ENODEV19;
goto memcpy;
}

if (old_mem->mem_type == TTM_PL_VRAM2 &&
   new_mem->mem_type == TTM_PL_SYSTEM0) {
r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
} else if (old_mem->mem_type == TTM_PL_SYSTEM0 &&
   new_mem->mem_type == TTM_PL_VRAM2) {
r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
} else {
r = amdgpu_move_blit(bo, evict,
		     new_mem, old_mem);
}

if (r) {
710memcpy:
/* Check that all memory is CPU accessible */
if (!amdgpu_mem_visible(adev, old_mem) ||
    !amdgpu_mem_visible(adev, new_mem)) {
	pr_err("Move buffer fallback to memcpy unavailable\n")printk("\0013" "amdgpu: " "Move buffer fallback to memcpy unavailable\n"
);
	return r;
}

r = ttm_bo_move_memcpy(bo, ctx, new_mem);
if (r)
	return r;
}

if (bo->type == ttm_bo_type_device &&
   new_mem->mem_type == TTM_PL_VRAM2 &&
   old_mem->mem_type != TTM_PL_VRAM2) {
/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 * accesses the BO after it's moved.
 */
abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0);
}

/* update statistics */
atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved)__sync_fetch_and_add_8(&adev->num_bytes_moved, (u64)bo
->num_pages << 12);
return 0;
735}

737/**
* amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
*
* Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
*/
742static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
743{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct drm_mm_node *mm_node = mem->mm_node;
size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT12;

switch (mem->mem_type) {
case TTM_PL_SYSTEM0:
/* system memory */
return 0;
case TTM_PL_TT1:
break;
case TTM_PL_VRAM2:
mem->bus.offset = mem->start << PAGE_SHIFT12;
/* check if it's visible */
if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
	return -EINVAL22;
/* Only physically contiguous buffers apply. In a contiguous
 * buffer, size of the first mm_node would match the number of
 * pages in ttm_resource.
 */
if (adev->mman.aper_base_kaddr &&
    (mm_node->size == mem->num_pages))
	mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
			mem->bus.offset;

mem->bus.offset += adev->gmc.aper_base;
mem->bus.is_iomem = true1;
break;
default:
return -EINVAL22;
}
return 0;
775}

777static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
			   unsigned long page_offset)
779{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
uint64_t offset = (page_offset << PAGE_SHIFT12);
struct drm_mm_node *mm;

mm = amdgpu_find_mm_node(&bo->mem, &offset);
offset += adev->gmc.aper_base;
return mm->start + (offset >> PAGE_SHIFT12);
787}

789/**
* amdgpu_ttm_domain_start - Returns GPU start address
* @adev: amdgpu device object
* @type: type of the memory
*
* Returns:
* GPU start address of a memory domain
*/

798uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
799{
switch (type) {
case TTM_PL_TT1:
return adev->gmc.gart_start;
case TTM_PL_VRAM2:
return adev->gmc.vram_start;
}

return 0;
808}

810/*
* TTM backend functions.
*/
813struct amdgpu_ttm_tt {
struct ttm_dma_tt	ttm;
struct drm_gem_object	*gobj;
u64			offset;
uint64_t		userptr;
struct task_struct	*usertask;
uint32_t		userflags;
bool_Bool			bound;
821#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)0
struct hmm_range	*range;
823#endif
824};

826#ifdef CONFIG_DRM_AMDGPU_USERPTR
827/**
* amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
* memory and start HMM tracking CPU page table update
*
* Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
* once afterwards to stop HMM tracking
*/
834int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct vm_page **pages)
835{
struct ttm_tt *ttm = bo->tbo.ttm;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct hmm_range *range;
unsigned long timeout;
struct mm_struct *mm;
unsigned long i;
int r = 0;

mm = bo->notifier.mm;
if (unlikely(!mm)__builtin_expect(!!(!mm), 0)) {
DRM_DEBUG_DRIVER("BO is not registered?\n")__drm_dbg(DRM_UT_DRIVER, "BO is not registered?\n");
return -EFAULT14;
}

/* Another get_user_pages is running at the same time?? */
if (WARN_ON(gtt->range)({ int __ret = !!(gtt->range); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "gtt->range", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c"
, 853); __builtin_expect(!!(__ret), 0); }))
return -EFAULT14;

if (!mmget_not_zero(mm)) /* Happens during process shutdown */
return -ESRCH3;

range = kzalloc(sizeof(*range), GFP_KERNEL(0x0001 | 0x0004));
if (unlikely(!range)__builtin_expect(!!(!range), 0)) {
r = -ENOMEM12;
goto out;
}
range->notifier = &bo->notifier;
range->start = bo->notifier.interval_tree.start;
range->end = bo->notifier.interval_tree.last + 1;
range->default_flags = HMM_PFN_REQ_FAULT;
if (!amdgpu_ttm_tt_is_readonly(ttm))
range->default_flags |= HMM_PFN_REQ_WRITE;

range->hmm_pfns = kvmalloc_array(ttm->num_pages,
			 sizeof(*range->hmm_pfns), GFP_KERNEL(0x0001 | 0x0004));
if (unlikely(!range->hmm_pfns)__builtin_expect(!!(!range->hmm_pfns), 0)) {
r = -ENOMEM12;
goto out_free_ranges;
}

mmap_read_lock(mm);
vma = find_vma(mm, start);
if (unlikely(!vma || start < vma->vm_start)__builtin_expect(!!(!vma || start < vma->vm_start), 0)) {
r = -EFAULT14;
goto out_unlock;
}
if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&__builtin_expect(!!((gtt->userflags & (1 << 1)) &&
 vma->vm_file), 0)
vma->vm_file)__builtin_expect(!!((gtt->userflags & (1 << 1)) &&
 vma->vm_file), 0)) {
r = -EPERM1;
goto out_unlock;
}
mmap_read_unlock(mm);
timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT)(((uint64_t)(HMM_RANGE_DEFAULT_TIMEOUT)) * hz / 1000);

892retry:
range->notifier_seq = mmu_interval_read_begin(&bo->notifier);

mmap_read_lock(mm);
r = hmm_range_fault(range);
mmap_read_unlock(mm);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
/*
 * FIXME: This timeout should encompass the retry from
 * mmu_interval_read_retry() as well.
 */
if (r == -EBUSY16 && !time_after(jiffies, timeout)((long)(timeout) - (long)(jiffies) < 0))
	goto retry;
goto out_free_pfns;
}

/*
* Due to default_flags, all pages are HMM_PFN_VALID or
* hmm_range_fault() fails. FIXME: The pages cannot be touched outside
* the notifier_lock, and mmu_interval_read_retry() must be done first.
*/
for (i = 0; i < ttm->num_pages; i++)
pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);

gtt->range = range;
mmput(mm);

return 0;

921out_unlock:
mmap_read_unlock(mm);
923out_free_pfns:
kvfree(range->hmm_pfns);
925out_free_ranges:
kfree(range);
927out:
mmput(mm);
return r;
930}

932/**
* amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
* Check if the pages backing this ttm range have been invalidated
*
* Returns: true if pages are still valid
*/
938bool_Bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
939{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
bool_Bool r = false0;

if (!gtt || !gtt->userptr)
return false0;

DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",__drm_dbg(DRM_UT_DRIVER, "user_pages_done 0x%llx pages 0x%lx\n"
, gtt->userptr, ttm->num_pages)
gtt->userptr, ttm->num_pages)__drm_dbg(DRM_UT_DRIVER, "user_pages_done 0x%llx pages 0x%lx\n"
, gtt->userptr, ttm->num_pages);

WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,({ static int __warned; int __ret = !!(!gtt->range || !gtt
->range->hmm_pfns); if (__ret && !__warned) { printf
("No user pages to check\n"); __warned = 1; } __builtin_expect
(!!(__ret), 0); })
"No user pages to check\n")({ static int __warned; int __ret = !!(!gtt->range || !gtt
->range->hmm_pfns); if (__ret && !__warned) { printf
("No user pages to check\n"); __warned = 1; } __builtin_expect
(!!(__ret), 0); });

if (gtt->range) {
/*
 * FIXME: Must always hold notifier_lock for this, and must
 * not ignore the return code.
 */
r = mmu_interval_read_retry(gtt->range->notifier,
			 gtt->range->notifier_seq);
kvfree(gtt->range->hmm_pfns);
kfree(gtt->range);
gtt->range = NULL((void *)0);
}

return !r;
965}
966#endif

968/**
* amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
*
* Called by amdgpu_cs_list_validate(). This creates the page list
* that backs user memory and will ultimately be mapped into the device
* address space.
*/
975void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct vm_page **pages)
976{
unsigned long i;

for (i = 0; i < ttm->num_pages; ++i)
ttm->pages[i] = pages ? pages[i] : NULL((void *)0);
981}

983/**
* amdgpu_ttm_tt_pin_userptr - 	prepare the sg table with the user pages
*
* Called by amdgpu_ttm_backend_bind()
**/
988static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
		     struct ttm_tt *ttm)
990{
STUB()do { printf("%s: stub\n", __func__); } while(0);
return -ENOSYS78;
993#ifdef notyet
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
int r;

int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY(1 << 0));
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;

/* Allocate an SG array and squash pages into it */
r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
		      ttm->num_pages << PAGE_SHIFT12,
		      GFP_KERNEL(0x0001 | 0x0004));
if (r)
goto release_sg;

/* Map SG to device */
r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
if (r)
goto release_sg;

/* convert SG to linear array of pages and dma addresses */
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
			 gtt->ttm.dma_address, ttm->num_pages);

return 0;

1020release_sg:
kfree(ttm->sg);
ttm->sg = NULL((void *)0);
return r;
1024#endif
1025}

1027/**
* amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
*/
1030static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
			struct ttm_tt *ttm)
1032{
STUB()do { printf("%s: stub\n", __func__); } while(0);
1034#ifdef notyet
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;

int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY(1 << 0));
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;

/* double check that we don't free the table twice */
if (!ttm->sg || !ttm->sg->sgl)
return;

/* unmap the pages mapped to the device */
dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
sg_free_table(ttm->sg);

1050#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)0
if (gtt->range) {
unsigned long i;

for (i = 0; i < ttm->num_pages; i++) {
	if (ttm->pages[i] !=
	    hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
		break;
}

WARN((i == ttm->num_pages), "Missing get_user_page_done\n")({ int __ret = !!((i == ttm->num_pages)); if (__ret) printf
("Missing get_user_page_done\n"); __builtin_expect(!!(__ret),
 0); });
}
1062#endif
1063#endif
1064}

1066static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
		struct ttm_buffer_object *tbo,
		uint64_t flags)
1069{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
struct ttm_tt *ttm = tbo->ttm;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
int r;

if (amdgpu_bo_encrypted(abo))
flags |= AMDGPU_PTE_TMZ(1ULL << 3);

if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9(1 << 8)) {
uint64_t page_idx = 1;

r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
		ttm->pages, gtt->ttm.dma_address, flags);
if (r)
	goto gart_bind_fail;

/* The memory type of the first page defaults to UC. Now
 * modify the memory type to NC from the second page of
 * the BO onward.
 */
flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK((uint64_t)(3ULL) << 57);
flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC)((uint64_t)(0) << 57);

r = amdgpu_gart_bind(adev,
		gtt->offset + (page_idx << PAGE_SHIFT12),
		ttm->num_pages - page_idx,
		&ttm->pages[page_idx],
		&(gtt->ttm.dma_address[page_idx]), flags);
} else {
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
		     ttm->pages, gtt->ttm.dma_address, flags);
}

1103gart_bind_fail:
if (r)
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",__drm_err("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages
, gtt->offset)
	  ttm->num_pages, gtt->offset)__drm_err("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages
, gtt->offset);

return r;
1109}

1111/**
* amdgpu_ttm_backend_bind - Bind GTT memory
*
* Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
* This handles binding GTT memory to the device address space.
*/
1117static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
		   struct ttm_tt *ttm,
		   struct ttm_resource *bo_mem)
1120{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = (void*)ttm;
uint64_t flags;
int r = 0;

if (!bo_mem)
return -EINVAL22;

if (gtt->bound)
return 0;

if (gtt->userptr) {
r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
if (r) {
	DRM_ERROR("failed to pin userptr\n")__drm_err("failed to pin userptr\n");
	return r;
}
}
if (!ttm->num_pages) {
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",({ int __ret = !!(1); if (__ret) printf("nothing to bind %lu pages for mreg %p back %p!\n"
, ttm->num_pages, bo_mem, ttm); __builtin_expect(!!(__ret)
, 0); })
     ttm->num_pages, bo_mem, ttm)({ int __ret = !!(1); if (__ret) printf("nothing to bind %lu pages for mreg %p back %p!\n"
, ttm->num_pages, bo_mem, ttm); __builtin_expect(!!(__ret)
, 0); });
}

if (bo_mem->mem_type == AMDGPU_PL_GDS(3 + 0) ||
   bo_mem->mem_type == AMDGPU_PL_GWS(3 + 1) ||
   bo_mem->mem_type == AMDGPU_PL_OA(3 + 2))
return -EINVAL22;

if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
gtt->offset = AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL;
return 0;
}

/* compute PTE flags relevant to this BO memory */
flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);

/* bind pages into GART page tables */
gtt->offset = (u64)bo_mem->start << PAGE_SHIFT12;
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);

if (r)
DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",__drm_err("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages
, gtt->offset)
	  ttm->num_pages, gtt->offset)__drm_err("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages
, gtt->offset);
gtt->bound = true1;
return r;
1167}

1169/**
* amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
* through AGP or GART aperture.
*
* If bo is accessible through AGP aperture, then use AGP aperture
* to access bo; otherwise allocate logical space in GART aperture
* and map bo to GART aperture.
*/
1177int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1178{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false0, false0 };
struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
struct ttm_resource tmp;
struct ttm_placement placement;
struct ttm_place placements;
uint64_t addr, flags;
int r;

if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL)
return 0;

addr = amdgpu_gmc_agp_addr(bo);
if (addr != AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL) {
bo->mem.start = addr >> PAGE_SHIFT12;
} else {

/* allocate GART space */
tmp = bo->mem;
tmp.mm_node = NULL((void *)0);
placement.num_placement = 1;
placement.placement = &placements;
placement.num_busy_placement = 1;
placement.busy_placement = &placements;
placements.fpfn = 0;
placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT12;
placements.mem_type = TTM_PL_TT1;
placements.flags = bo->mem.placement;

r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
if (unlikely(r)__builtin_expect(!!(r), 0))
	return r;

/* compute PTE flags for this buffer object */
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);

/* Bind pages */
gtt->offset = (u64)tmp.start << PAGE_SHIFT12;
r = amdgpu_ttm_gart_bind(adev, bo, flags);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
	ttm_resource_free(bo, &tmp);
	return r;
}

ttm_resource_free(bo, &bo->mem);
bo->mem = tmp;
}

return 0;
1228}

1230/**
* amdgpu_ttm_recover_gart - Rebind GTT pages
*
* Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
* rebind GTT pages during a GPU reset.
*/
1236int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1237{
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
uint64_t flags;
int r;

if (!tbo->ttm)
return 0;

flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
r = amdgpu_ttm_gart_bind(adev, tbo, flags);

return r;
1249}

1251/**
* amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
*
* Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
* ttm_tt_destroy().
*/
1257static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
		      struct ttm_tt *ttm)
1259{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
int r;

/* if the pages have userptr pinning then clear that first */
if (gtt->userptr)
amdgpu_ttm_tt_unpin_userptr(bdev, ttm);

if (!gtt->bound)
return;

if (gtt->offset == AMDGPU_BO_INVALID_OFFSET0x7fffffffffffffffL)
return;

/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
if (r)
DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",__drm_err("failed to unbind %lu pages at 0x%08llX\n", gtt->
ttm.ttm.num_pages, gtt->offset)
	  gtt->ttm.ttm.num_pages, gtt->offset)__drm_err("failed to unbind %lu pages at 0x%08llX\n", gtt->
ttm.ttm.num_pages, gtt->offset);
gtt->bound = false0;
1280}

1282static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
		       struct ttm_tt *ttm)
1284{
struct amdgpu_ttm_tt *gtt = (void *)ttm;

amdgpu_ttm_backend_unbind(bdev, ttm);
ttm_tt_destroy_common(bdev, ttm);
1289#ifdef notyet
if (gtt->usertask)
put_task_struct(gtt->usertask);
1292#endif

ttm_dma_tt_fini(&gtt->ttm);
kfree(gtt);
1296}

1298/**
* amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
*
* @bo: The buffer object to create a GTT ttm_tt object around
*
* Called by ttm_tt_create().
*/
1305static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
			   uint32_t page_flags)
1307{
struct amdgpu_ttm_tt *gtt;

gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL(0x0001 | 0x0004));
if (gtt == NULL((void *)0)) {
return NULL((void *)0);
}
gtt->gobj = &bo->base;

/* allocate space for the uninitialized page entries */
if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
kfree(gtt);
return NULL((void *)0);
}
return &gtt->ttm.ttm;
1322}

1324/**
* amdgpu_ttm_tt_populate - Map GTT pages visible to the device
*
* Map the pages of a ttm_tt object to an address space visible
* to the underlying device.
*/
1330static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
		  struct ttm_tt *ttm,
		  struct ttm_operation_ctx *ctx)
1333{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;

/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
if (gtt && gtt->userptr) {
ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL(0x0001 | 0x0004));
if (!ttm->sg)
	return -ENOMEM12;

ttm->page_flags |= TTM_PAGE_FLAG_SG(1 << 8);
ttm_tt_set_populated(ttm);
return 0;
}

if (ttm->page_flags & TTM_PAGE_FLAG_SG(1 << 8)) {
if (!ttm->sg) {
	struct dma_buf_attachment *attach;
	struct sg_table *sgt;

	attach = gtt->gobj->import_attach;
1354#ifdef notyet
	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
	if (IS_ERR(sgt))
		return PTR_ERR(sgt);
1358#else
	STUB()do { printf("%s: stub\n", __func__); } while(0);
	return -ENOSYS78;
1361#endif

	ttm->sg = sgt;
}

drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
				 gtt->ttm.dma_address,
				 ttm->num_pages);
ttm_tt_set_populated(ttm);
return 0;
}

1373#ifdef CONFIG_SWIOTLB
if (adev->need_swiotlb && swiotlb_nr_tbl()) {
return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
}
1377#endif

/* fall back to generic helper to populate the page array
* and map them to the device */
return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1382}

1384/**
* amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
*
* Unmaps pages of a ttm_tt object from the device address space and
* unpopulates the page array backing it.
*/
1390static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1391{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
struct amdgpu_device *adev;

if (gtt && gtt->userptr) {
1
Assuming 'gtt' is null→
amdgpu_ttm_tt_set_user_pages(ttm, NULL((void *)0));
kfree(ttm->sg);
ttm->sg = NULL((void *)0);
ttm->page_flags &= ~TTM_PAGE_FLAG_SG(1 << 8);
return;
}

if (ttm->sg && gtt->gobj->import_attach) {
2
←
Access to field 'sg' results in a dereference of a null pointer (loaded from variable 'ttm')
struct dma_buf_attachment *attach;

attach = gtt->gobj->import_attach;
1407#ifdef notyet
dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1409#else
STUB()do { printf("%s: stub\n", __func__); } while(0);
1411#endif
ttm->sg = NULL((void *)0);
return;
}

if (ttm->page_flags & TTM_PAGE_FLAG_SG(1 << 8))
return;

adev = amdgpu_ttm_adev(bdev);

1421#ifdef CONFIG_SWIOTLB
if (adev->need_swiotlb && swiotlb_nr_tbl()) {
ttm_dma_unpopulate(&gtt->ttm, adev->dev);
return;
}
1426#endif

/* fall back to generic helper to unmap and unpopulate array */
ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1430}

1432/**
* amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
* task
*
* @bo: The ttm_buffer_object to bind this userptr to
* @addr:  The address in the current tasks VM space to use
* @flags: Requirements of userptr object.
*
* Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
* to current task
*/
1443int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
	      uint64_t addr, uint32_t flags)
1445{
struct amdgpu_ttm_tt *gtt;

if (!bo->ttm) {
/* TODO: We want a separate TTM object type for userptrs */
bo->ttm = amdgpu_ttm_tt_create(bo, 0);
if (bo->ttm == NULL((void *)0))
	return -ENOMEM12;
}

gtt = (void*)bo->ttm;
gtt->userptr = addr;
gtt->userflags = flags;

1459#ifdef notyet
if (gtt->usertask)
put_task_struct(gtt->usertask);
gtt->usertask = current->group_leader;
get_task_struct(gtt->usertask);
1464#endif

return 0;
1467}

1469/**
* amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
*/
1472struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1473{
struct amdgpu_ttm_tt *gtt = (void *)ttm;

if (gtt == NULL((void *)0))
return NULL((void *)0);

if (gtt->usertask == NULL((void *)0))
return NULL((void *)0);

1482#ifdef notyet
return gtt->usertask->mm;
1484#else
STUB()do { printf("%s: stub\n", __func__); } while(0);
return NULL((void *)0);
1487#endif
1488}

1490/**
* amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
* address range for the current task.
*
*/
1495bool_Bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
		  unsigned long end)
1497{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
unsigned long size;

if (gtt == NULL((void *)0) || !gtt->userptr)
return false0;

/* Return false if no part of the ttm_tt object lies within
* the range
*/
size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE(1 << 12);
if (gtt->userptr > end || gtt->userptr + size <= start)
return false0;

return true1;
1512}

1514/**
* amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
*/
1517bool_Bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1518{
struct amdgpu_ttm_tt *gtt = (void *)ttm;

if (gtt == NULL((void *)0) || !gtt->userptr)
return false0;

return true1;
1525}

1527/**
* amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
*/
1530bool_Bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1531{
struct amdgpu_ttm_tt *gtt = (void *)ttm;

if (gtt == NULL((void *)0))
return false0;

return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY(1 << 0));
1538}

1540/**
* amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
*
* @ttm: The ttm_tt object to compute the flags for
* @mem: The memory registry backing this ttm_tt object
*
* Figure out the flags to use for a VM PDE (Page Directory Entry).
*/
1548uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1549{
uint64_t flags = 0;

if (mem && mem->mem_type != TTM_PL_SYSTEM0)
flags |= AMDGPU_PTE_VALID(1ULL << 0);

if (mem && mem->mem_type == TTM_PL_TT1) {
flags |= AMDGPU_PTE_SYSTEM(1ULL << 1);

if (ttm->caching_state == tt_cached)
	flags |= AMDGPU_PTE_SNOOPED(1ULL << 2);
}

return flags;
1563}

1565/**
* amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
*
* @ttm: The ttm_tt object to compute the flags for
* @mem: The memory registry backing this ttm_tt object

* Figure out the flags to use for a VM PTE (Page Table Entry).
*/
1573uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
		 struct ttm_resource *mem)
1575{
uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);

flags |= adev->gart.gart_pte_flags;
flags |= AMDGPU_PTE_READABLE(1ULL << 5);

if (!amdgpu_ttm_tt_is_readonly(ttm))
flags |= AMDGPU_PTE_WRITEABLE(1ULL << 6);

return flags;
1585}

1587/**
* amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
* object.
*
* Return true if eviction is sensible. Called by ttm_mem_evict_first() on
* behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
* it can find space for a new object and by ttm_bo_force_list_clean() which is
* used to clean out a memory space.
*/
1596static bool_Bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
			    const struct ttm_place *place)
1598{
unsigned long num_pages = bo->mem.num_pages;
struct drm_mm_node *node = bo->mem.mm_node;
struct dma_resv_list *flist;
struct dma_fence *f;
int i;

if (bo->type == ttm_bo_type_kernel &&
   !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
return false0;

/* If bo is a KFD BO, check if the bo belongs to the current process.
* If true, then return false as any KFD process needs all its BOs to
* be resident to run successfully
*/
flist = dma_resv_get_list(bo->base.resv);
if (flist) {
for (i = 0; i < flist->shared_count; ++i) {
	f = rcu_dereference_protected(flist->shared[i],(flist->shared[i])
		dma_resv_held(bo->base.resv))(flist->shared[i]);
1618#ifdef notyet
	if (amdkfd_fence_check_mm(f, current->mm))
		return false0;
1621#endif
}
}

switch (bo->mem.mem_type) {
case TTM_PL_TT1:
if (amdgpu_bo_is_amdgpu_bo(bo) &&
    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
	return false0;
return true1;

case TTM_PL_VRAM2:
/* Check each drm MM node individually */
while (num_pages) {
	if (place->fpfn < (node->start + node->size) &&
	    !(place->lpfn && place->lpfn <= node->start))
		return true1;

	num_pages -= node->size;
	++node;
}
return false0;

default:
break;
}

return ttm_bo_eviction_valuable(bo, place);
1649}

1651/**
* amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
*
* @bo:  The buffer object to read/write
* @offset:  Offset into buffer object
* @buf:  Secondary buffer to write/read from
* @len: Length in bytes of access
* @write:  true if writing
*
* This is used to access VRAM that backs a buffer object via MMIO
* access for debugging purposes.
*/
1663static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
		    unsigned long offset,
		    void *buf, int len, int write)
1666{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct drm_mm_node *nodes;
uint32_t value = 0;
int ret = 0;
uint64_t pos;
unsigned long flags;

if (bo->mem.mem_type != TTM_PL_VRAM2)
return -EIO5;

pos = offset;
nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
pos += (nodes->start << PAGE_SHIFT12);

while (len && pos < adev->gmc.mc_vram_size) {
uint64_t aligned_pos = pos & ~(uint64_t)3;
uint64_t bytes = 4 - (pos & 3);
uint32_t shift = (pos & 3) * 8;
uint32_t mask = 0xffffffff << shift;

if (len < bytes) {
	mask &= 0xffffffff >> (bytes - len) * 8;
	bytes = len;
}

if (mask != 0xffffffff) {
	spin_lock_irqsave(&adev->mmio_idx_lock, flags)do { flags = 0; mtx_enter(&adev->mmio_idx_lock); } while
 (0);
	WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000)amdgpu_device_wreg(adev, (0x0), (((uint32_t)aligned_pos) | 0x80000000
), (1<<1));
	WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31)amdgpu_device_wreg(adev, (0x6), (aligned_pos >> 31), (1
<<1));
	if (!write || mask != 0xffffffff)
		value = RREG32_NO_KIQ(mmMM_DATA)amdgpu_device_rreg(adev, (0x1), (1<<1));
	if (write) {
		value &= ~mask;
		value |= (*(uint32_t *)buf << shift) & mask;
		WREG32_NO_KIQ(mmMM_DATA, value)amdgpu_device_wreg(adev, (0x1), (value), (1<<1));
	}
	spin_unlock_irqrestore(&adev->mmio_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->mmio_idx_lock); }
 while (0);
	if (!write) {
		value = (value & mask) >> shift;
		memcpy(buf, &value, bytes)__builtin_memcpy((buf), (&value), (bytes));
	}
} else {
	bytes = (nodes->start + nodes->size) << PAGE_SHIFT12;
	bytes = min(bytes - pos, (uint64_t)len & ~0x3ull)(((bytes - pos)<((uint64_t)len & ~0x3ull))?(bytes - pos
):((uint64_t)len & ~0x3ull));

	amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
				  bytes, write);
}

ret += bytes;
buf = (uint8_t *)buf + bytes;
pos += bytes;
len -= bytes;
if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT12) {
	++nodes;
	pos = (nodes->start << PAGE_SHIFT12);
}
}

return ret;
1728}

1730static struct ttm_bo_driver amdgpu_bo_driver = {
.ttm_tt_create = &amdgpu_ttm_tt_create,
.ttm_tt_populate = &amdgpu_ttm_tt_populate,
.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
.ttm_tt_bind = &amdgpu_ttm_backend_bind,
.ttm_tt_unbind = &amdgpu_ttm_backend_unbind,
.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
.evict_flags = &amdgpu_evict_flags,
.move = &amdgpu_bo_move,
.verify_access = &amdgpu_verify_access,
.move_notify = &amdgpu_bo_move_notify,
.release_notify = &amdgpu_bo_release_notify,
.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
.access_memory = &amdgpu_ttm_access_memory,
.del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1748};

1750/*
* Firmware Reservation functions
*/
1753/**
* amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
*
* @adev: amdgpu_device pointer
*
* free fw reserved vram if it has been reserved.
*/
1760static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1761{
amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
NULL((void *)0), &adev->mman.fw_vram_usage_va);
1764}

1766/**
* amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
*
* @adev: amdgpu_device pointer
*
* create bo vram reservation from fw.
*/
1773static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1774{
uint64_t vram_size = adev->gmc.visible_vram_size;

adev->mman.fw_vram_usage_va = NULL((void *)0);
adev->mman.fw_vram_usage_reserved_bo = NULL((void *)0);

if (adev->mman.fw_vram_usage_size == 0 ||
   adev->mman.fw_vram_usage_size > vram_size)
return 0;

return amdgpu_bo_create_kernel_at(adev,
			  adev->mman.fw_vram_usage_start_offset,
			  adev->mman.fw_vram_usage_size,
			  AMDGPU_GEM_DOMAIN_VRAM0x4,
			  &adev->mman.fw_vram_usage_reserved_bo,
			  &adev->mman.fw_vram_usage_va);
1790}

1792/*
* Memoy training reservation functions
*/

1796/**
* amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
*
* @adev: amdgpu_device pointer
*
* free memory training reserved vram if it has been reserved.
*/
1803static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1804{
struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;

ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL((void *)0), NULL((void *)0));
ctx->c2p_bo = NULL((void *)0);

return 0;
1812}

1814static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1815{
struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;

memset(ctx, 0, sizeof(*ctx))__builtin_memset((ctx), (0), (sizeof(*ctx)));

ctx->c2p_train_data_offset =
roundup2((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M)((((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size
 - (1024 * 1024 * 1))) + (((1024 * 1024 * 1)) - 1)) & (~(
(__typeof((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size
 - (1024 * 1024 * 1))))((1024 * 1024 * 1)) - 1)));
ctx->p2c_train_data_offset =
(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET0x8000);
ctx->train_data_size =
GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES0x1000;

DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
	ctx->train_data_size,__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
	ctx->p2c_train_data_offset,__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset)
	ctx->c2p_train_data_offset)__drm_dbg(DRM_UT_CORE, "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n"
, ctx->train_data_size, ctx->p2c_train_data_offset, ctx
->c2p_train_data_offset);
1831}

1833/*
* reserve TMR memory at the top of VRAM which holds
* IP Discovery data and is protected by PSP.
*/
1837static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1838{
int ret;
struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
bool_Bool mem_train_support = false0;

if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
ret = amdgpu_mem_train_support(adev);
if (ret == 1)
	mem_train_support = true1;
else if (ret == -1)
	return -EINVAL22;
else
	DRM_DEBUG("memory training does not support!\n")__drm_dbg(DRM_UT_CORE, "memory training does not support!\n");
}

/*
* Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
* the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
*
* Otherwise, fallback to legacy approach to check and reserve tmr block for ip
* discovery data and G6 memory training data respectively
*/
adev->mman.discovery_tmr_size =
amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
if (!adev->mman.discovery_tmr_size)
adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET(64 << 10);

if (mem_train_support) {
/* reserve vram for mem train according to TMR location */
amdgpu_ttm_training_data_block_init(adev);
ret = amdgpu_bo_create_kernel_at(adev,
			 ctx->c2p_train_data_offset,
			 ctx->train_data_size,
			 AMDGPU_GEM_DOMAIN_VRAM0x4,
			 &ctx->c2p_bo,
			 NULL((void *)0));
if (ret) {
	DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret)__drm_err("alloc c2p_bo failed(%d)!\n", ret);
	amdgpu_ttm_training_reserve_vram_fini(adev);
	return ret;
}
ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
}

ret = amdgpu_bo_create_kernel_at(adev,
		adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
		adev->mman.discovery_tmr_size,
		AMDGPU_GEM_DOMAIN_VRAM0x4,
		&adev->mman.discovery_memory,
		NULL((void *)0));
if (ret) {
DRM_ERROR("alloc tmr failed(%d)!\n", ret)__drm_err("alloc tmr failed(%d)!\n", ret);
amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL((void *)0), NULL((void *)0));
return ret;
}

return 0;
1895}

1897/**
* amdgpu_ttm_init - Init the memory management (ttm) as well as various
* gtt/vram related fields.
*
* This initializes all of the memory space pools that the TTM layer
* will need such as the GTT space (system memory mapped to the device),
* VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
* can be mapped per VMID.
*/
1906int amdgpu_ttm_init(struct amdgpu_device *adev)
1907{
uint64_t gtt_size;
int r;
u64 vis_vram_limit;

rw_init(&adev->mman.gtt_window_lock, "gttwin")_rw_init_flags(&adev->mman.gtt_window_lock, "gttwin", 0
, ((void *)0));

/* No others user of address space so set it to 0 */
1915#ifdef notyet
r = ttm_bo_device_init(&adev->mman.bdev,
	       &amdgpu_bo_driver,
	       adev_to_drm(adev)->anon_inode->i_mapping,
	       adev_to_drm(adev)->vma_offset_manager,
	       dma_addressing_limited(adev->dev)0);
1921#else
r = ttm_bo_device_init(&adev->mman.bdev,
	       &amdgpu_bo_driver,
	       /*adev_to_drm(adev)->anon_inode->i_mapping*/NULL((void *)0),
	       adev_to_drm(adev)->vma_offset_manager,
	       dma_addressing_limited(adev->dev)0);
1927#endif
if (r) {
DRM_ERROR("failed initializing buffer object driver(%d).\n", r)__drm_err("failed initializing buffer object driver(%d).\n", r
);
return r;
}
adev->mman.bdev.iot = adev->iot;
adev->mman.bdev.memt = adev->memt;
adev->mman.bdev.dmat = adev->dmat;
adev->mman.initialized = true1;

/* We opt to avoid OOM on system pages allocations */
adev->mman.bdev.no_retry = true1;

/* Initialize VRAM pool with all of VRAM divided into pages */
r = amdgpu_vram_mgr_init(adev);
if (r) {
DRM_ERROR("Failed initializing VRAM heap.\n")__drm_err("Failed initializing VRAM heap.\n");
return r;
}

/* Reduce size of CPU-visible VRAM if requested */
vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
if (amdgpu_vis_vram_limit > 0 &&
   vis_vram_limit <= adev->gmc.visible_vram_size)
adev->gmc.visible_vram_size = vis_vram_limit;

/* Change the size here instead of the init above so only lpfn is affected */
amdgpu_ttm_set_buffer_funcs_status(adev, false0);
1955#ifdef CONFIG_64BIT1
1956#ifdef __linux__
adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
				adev->gmc.visible_vram_size);
1959#else
if (bus_space_map(adev->memt, adev->gmc.aper_base,
   adev->gmc.visible_vram_size,
   BUS_SPACE_MAP_LINEAR0x0002 | BUS_SPACE_MAP_PREFETCHABLE0x0008,
   &adev->mman.aper_bsh)) {
adev->mman.aper_base_kaddr = NULL((void *)0);
} else {
adev->mman.aper_base_kaddr = bus_space_vaddr(adev->memt,((adev->memt)->vaddr((adev->mman.aper_bsh)))
    adev->mman.aper_bsh)((adev->memt)->vaddr((adev->mman.aper_bsh)));
}
1969#endif
1970#endif

/*
*The reserved vram for firmware must be pinned to the specified
*place on the VRAM, so reserve it early.
*/
r = amdgpu_ttm_fw_reserve_vram_init(adev);
if (r) {
return r;
}

/*
* only NAVI10 and onwards ASIC support for IP discovery.
* If IP discovery enabled, a block of memory should be
* reserved for IP discovey.
*/
if (adev->mman.discovery_bin) {
r = amdgpu_ttm_reserve_tmr(adev);
if (r)
	return r;
}

/* allocate memory as required for VGA
* This is used for VGA emulation and pre-OS scanout buffers to
* avoid display artifacts while transitioning between pre-OS
* and driver.  */
r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
		       AMDGPU_GEM_DOMAIN_VRAM0x4,
		       &adev->mman.stolen_vga_memory,
		       NULL((void *)0));
if (r)
return r;
r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
		       adev->mman.stolen_extended_size,
		       AMDGPU_GEM_DOMAIN_VRAM0x4,
		       &adev->mman.stolen_extended_memory,
		       NULL((void *)0));
if (r)
return r;

DRM_INFO("amdgpu: %uM of VRAM memory ready\n",printk("\0016" "[" "drm" "] " "amdgpu: %uM of VRAM memory ready\n"
, (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)))
 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)))printk("\0016" "[" "drm" "] " "amdgpu: %uM of VRAM memory ready\n"
, (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));

/* Compute GTT size, either bsaed on 3/4th the size of RAM size
* or whatever the user passed on module init */
if (amdgpu_gtt_size == -1) {
2016#ifdef __linux__
struct sysinfo si;

si_meminfo(&si);
gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)si.totalram * si.mem_unit * 3/4)))?(((((3072ULL << 20)
)>(adev->gmc.mc_vram_size))?((3072ULL << 20)):(adev
->gmc.mc_vram_size))):(((uint64_t)si.totalram * si.mem_unit
 * 3/4)))
	       adev->gmc.mc_vram_size),(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)si.totalram * si.mem_unit * 3/4)))?(((((3072ULL << 20)
)>(adev->gmc.mc_vram_size))?((3072ULL << 20)):(adev
->gmc.mc_vram_size))):(((uint64_t)si.totalram * si.mem_unit
 * 3/4)))
	       ((uint64_t)si.totalram * si.mem_unit * 3/4))(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)si.totalram * si.mem_unit * 3/4)))?(((((3072ULL << 20)
)>(adev->gmc.mc_vram_size))?((3072ULL << 20)):(adev
->gmc.mc_vram_size))):(((uint64_t)si.totalram * si.mem_unit
 * 3/4)));
2023#else
gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)((paddr_t)(physmem) << 12) * 3/4)))?(((((3072ULL <<
 20))>(adev->gmc.mc_vram_size))?((3072ULL << 20))
:(adev->gmc.mc_vram_size))):(((uint64_t)((paddr_t)(physmem
) << 12) * 3/4)))
	       adev->gmc.mc_vram_size),(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)((paddr_t)(physmem) << 12) * 3/4)))?(((((3072ULL <<
 20))>(adev->gmc.mc_vram_size))?((3072ULL << 20))
:(adev->gmc.mc_vram_size))):(((uint64_t)((paddr_t)(physmem
) << 12) * 3/4)))
	       ((uint64_t)ptoa(physmem) * 3/4))(((((((3072ULL << 20))>(adev->gmc.mc_vram_size))?
((3072ULL << 20)):(adev->gmc.mc_vram_size)))<(((uint64_t
)((paddr_t)(physmem) << 12) * 3/4)))?(((((3072ULL <<
 20))>(adev->gmc.mc_vram_size))?((3072ULL << 20))
:(adev->gmc.mc_vram_size))):(((uint64_t)((paddr_t)(physmem
) << 12) * 3/4)));
2027#endif
}
else
gtt_size = (uint64_t)amdgpu_gtt_size << 20;

/* Initialize GTT memory pool */
r = amdgpu_gtt_mgr_init(adev, gtt_size);
if (r) {
DRM_ERROR("Failed initializing GTT heap.\n")__drm_err("Failed initializing GTT heap.\n");
return r;
}
DRM_INFO("amdgpu: %uM of GTT memory ready.\n",printk("\0016" "[" "drm" "] " "amdgpu: %uM of GTT memory ready.\n"
, (unsigned)(gtt_size / (1024 * 1024)))
 (unsigned)(gtt_size / (1024 * 1024)))printk("\0016" "[" "drm" "] " "amdgpu: %uM of GTT memory ready.\n"
, (unsigned)(gtt_size / (1024 * 1024)));

/* Initialize various on-chip memory pools */
r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS(3 + 0), adev->gds.gds_size);
if (r) {
DRM_ERROR("Failed initializing GDS heap.\n")__drm_err("Failed initializing GDS heap.\n");
return r;
}

r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS(3 + 1), adev->gds.gws_size);
if (r) {
DRM_ERROR("Failed initializing gws heap.\n")__drm_err("Failed initializing gws heap.\n");
return r;
}

r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA(3 + 2), adev->gds.oa_size);
if (r) {
DRM_ERROR("Failed initializing oa heap.\n")__drm_err("Failed initializing oa heap.\n");
return r;
}

return 0;
2061}

2063/**
* amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
*/
2066void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2067{
/* return the VGA stolen memory (if any) back to VRAM */
if (!adev->mman.keep_stolen_vga_memory)
amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL((void *)0), NULL((void *)0));
amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL((void *)0), NULL((void *)0));
2072}

2074/**
* amdgpu_ttm_fini - De-initialize the TTM memory pools
*/
2077void amdgpu_ttm_fini(struct amdgpu_device *adev)
2078{
if (!adev->mman.initialized)
return;

amdgpu_ttm_training_reserve_vram_fini(adev);
/* return the stolen vga memory back to VRAM */
if (adev->mman.keep_stolen_vga_memory)
amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL((void *)0), NULL((void *)0));
/* return the IP Discovery TMR memory back to VRAM */
amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL((void *)0), NULL((void *)0));
amdgpu_ttm_fw_reserve_vram_fini(adev);

2090#ifdef __linux__
if (adev->mman.aper_base_kaddr)
iounmap(adev->mman.aper_base_kaddr);
2093#else
if (adev->mman.aper_base_kaddr)
bus_space_unmap(adev->memt, adev->mman.aper_bsh,
    adev->gmc.visible_vram_size);
2097#endif
adev->mman.aper_base_kaddr = NULL((void *)0);

amdgpu_vram_mgr_fini(adev);
amdgpu_gtt_mgr_fini(adev);
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS(3 + 0));
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS(3 + 1));
ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA(3 + 2));
ttm_bo_device_release(&adev->mman.bdev);
adev->mman.initialized = false0;
DRM_INFO("amdgpu: ttm finalized\n")printk("\0016" "[" "drm" "] " "amdgpu: ttm finalized\n");
2108}

2110/**
* amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
*
* @adev: amdgpu_device pointer
* @enable: true when we can use buffer functions.
*
* Enable/disable use of buffer functions during suspend/resume. This should
* only be called at bootup or when userspace isn't running.
*/
2119void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool_Bool enable)
2120{
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM2);
uint64_t size;
int r;

if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
   adev->mman.buffer_funcs_enabled == enable)
return;

if (enable) {
struct amdgpu_ring *ring;
struct drm_gpu_scheduler *sched;

ring = adev->mman.buffer_funcs_ring;
sched = &ring->sched;
r = drm_sched_entity_init(&adev->mman.entity,
			  DRM_SCHED_PRIORITY_KERNEL, &sched,
			  1, NULL((void *)0));
if (r) {
	DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",__drm_err("Failed setting up TTM BO move entity (%d)\n", r)
		  r)__drm_err("Failed setting up TTM BO move entity (%d)\n", r);
	return;
}
} else {
drm_sched_entity_destroy(&adev->mman.entity);
dma_fence_put(man->move);
man->move = NULL((void *)0);
}

/* this just adjusts TTM size idea, which sets lpfn to the correct value */
if (enable)
size = adev->gmc.real_vram_size;
else
size = adev->gmc.visible_vram_size;
man->size = size >> PAGE_SHIFT12;
adev->mman.buffer_funcs_enabled = enable;
2156}

2158#ifdef __linux__

2160int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2161{
struct drm_file *file_priv = filp->private_data;
struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);

if (adev == NULL((void *)0))
return -EINVAL22;

return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2169}

2171#else

2173struct uvm_object *
2174amdgpu_mmap(struct file *filp, vm_prot_t accessprot, voff_t off, vsize_t size)
2175{
struct drm_file *file_priv = (void *)filp;
struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);

if (adev == NULL((void *)0))
return NULL((void *)0);

return ttm_bo_mmap(filp, off, size, &adev->mman.bdev);
2183}

2185#endif

2187int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
       uint64_t dst_offset, uint32_t byte_count,
       struct dma_resv *resv,
       struct dma_fence **fence, bool_Bool direct_submit,
       bool_Bool vm_needs_flush, bool_Bool tmz)
2192{
enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
AMDGPU_IB_POOL_DELAYED;
struct amdgpu_device *adev = ring->adev;
struct amdgpu_job *job;

uint32_t max_bytes;
unsigned num_loops, num_dw;
unsigned i;
int r;

if (direct_submit && !ring->sched.ready) {
DRM_ERROR("Trying to move memory with ring turned off.\n")__drm_err("Trying to move memory with ring turned off.\n");
return -EINVAL22;
}

max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
num_loops = DIV_ROUND_UP(byte_count, max_bytes)(((byte_count) + ((max_bytes) - 1)) / (max_bytes));
num_dw = roundup2(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8)(((num_loops * adev->mman.buffer_funcs->copy_num_dw) + (
(8) - 1)) & (~((__typeof(num_loops * adev->mman.buffer_funcs
->copy_num_dw))(8) - 1)));

r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
if (r)
return r;

if (vm_needs_flush) {
job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
job->vm_needs_flush = true1;
}
if (resv) {
r = amdgpu_sync_resv(adev, &job->sync, resv,
		     AMDGPU_SYNC_ALWAYS,
		     AMDGPU_FENCE_OWNER_UNDEFINED((void *)0ul));
if (r) {
	DRM_ERROR("sync failed (%d).\n", r)__drm_err("sync failed (%d).\n", r);
	goto error_free;
}
}

for (i = 0; i < num_loops; i++) {
uint32_t cur_size_in_bytes = min(byte_count, max_bytes)(((byte_count)<(max_bytes))?(byte_count):(max_bytes));

amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,(adev)->mman.buffer_funcs->emit_copy_buffer((&job->
ibs[0]), (src_offset), (dst_offset), (cur_size_in_bytes), (tmz
))
			dst_offset, cur_size_in_bytes, tmz)(adev)->mman.buffer_funcs->emit_copy_buffer((&job->
ibs[0]), (src_offset), (dst_offset), (cur_size_in_bytes), (tmz
));

src_offset += cur_size_in_bytes;
dst_offset += cur_size_in_bytes;
byte_count -= cur_size_in_bytes;
}

amdgpu_ring_pad_ib(ring, &job->ibs[0])((ring)->funcs->pad_ib((ring), (&job->ibs[0])));
WARN_ON(job->ibs[0].length_dw > num_dw)({ int __ret = !!(job->ibs[0].length_dw > num_dw); if (
__ret) printf("WARNING %s failed at %s:%d\n", "job->ibs[0].length_dw > num_dw"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c", 2242); __builtin_expect
(!!(__ret), 0); });
if (direct_submit)
r = amdgpu_job_submit_direct(job, ring, fence);
else
r = amdgpu_job_submit(job, &adev->mman.entity,
		      AMDGPU_FENCE_OWNER_UNDEFINED((void *)0ul), fence);
if (r)
goto error_free;

return r;

2253error_free:
amdgpu_job_free(job);
DRM_ERROR("Error scheduling IBs (%d)\n", r)__drm_err("Error scheduling IBs (%d)\n", r);
return r;
2257}

2259int amdgpu_fill_buffer(struct amdgpu_bo *bo,
       uint32_t src_data,
       struct dma_resv *resv,
       struct dma_fence **fence)
2263{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;

struct drm_mm_node *mm_node;
unsigned long num_pages;
unsigned int num_loops, num_dw;

struct amdgpu_job *job;
int r;

if (!adev->mman.buffer_funcs_enabled) {
DRM_ERROR("Trying to clear memory with ring turned off.\n")__drm_err("Trying to clear memory with ring turned off.\n");
return -EINVAL22;
}

if (bo->tbo.mem.mem_type == TTM_PL_TT1) {
r = amdgpu_ttm_alloc_gart(&bo->tbo);
if (r)
	return r;
}

num_pages = bo->tbo.num_pages;
mm_node = bo->tbo.mem.mm_node;
num_loops = 0;
while (num_pages) {
uint64_t byte_count = mm_node->size << PAGE_SHIFT12;

num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes)(((byte_count) + ((max_bytes) - 1)) / (max_bytes));
num_pages -= mm_node->size;
++mm_node;
}
num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;

/* for IB padding */
num_dw += 64;

r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
		     &job);
if (r)
return r;

if (resv) {
r = amdgpu_sync_resv(adev, &job->sync, resv,
		     AMDGPU_SYNC_ALWAYS,
		     AMDGPU_FENCE_OWNER_UNDEFINED((void *)0ul));
if (r) {
	DRM_ERROR("sync failed (%d).\n", r)__drm_err("sync failed (%d).\n", r);
	goto error_free;
}
}

num_pages = bo->tbo.num_pages;
mm_node = bo->tbo.mem.mm_node;

while (num_pages) {
uint64_t byte_count = mm_node->size << PAGE_SHIFT12;
uint64_t dst_addr;

dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
while (byte_count) {
	uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,({ uint64_t __min_a = (byte_count); uint64_t __min_b = (max_bytes
); __min_a < __min_b ? __min_a : __min_b; })
					   max_bytes)({ uint64_t __min_a = (byte_count); uint64_t __min_b = (max_bytes
); __min_a < __min_b ? __min_a : __min_b; });

	amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,(adev)->mman.buffer_funcs->emit_fill_buffer((&job->
ibs[0]), (src_data), (dst_addr), (cur_size_in_bytes))
				dst_addr, cur_size_in_bytes)(adev)->mman.buffer_funcs->emit_fill_buffer((&job->
ibs[0]), (src_data), (dst_addr), (cur_size_in_bytes));

	dst_addr += cur_size_in_bytes;
	byte_count -= cur_size_in_bytes;
}

num_pages -= mm_node->size;
++mm_node;
}

amdgpu_ring_pad_ib(ring, &job->ibs[0])((ring)->funcs->pad_ib((ring), (&job->ibs[0])));
WARN_ON(job->ibs[0].length_dw > num_dw)({ int __ret = !!(job->ibs[0].length_dw > num_dw); if (
__ret) printf("WARNING %s failed at %s:%d\n", "job->ibs[0].length_dw > num_dw"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c", 2340); __builtin_expect
(!!(__ret), 0); });
r = amdgpu_job_submit(job, &adev->mman.entity,
	      AMDGPU_FENCE_OWNER_UNDEFINED((void *)0ul), fence);
if (r)
goto error_free;

return 0;

2348error_free:
amdgpu_job_free(job);
return r;
2351}

2353#if defined(CONFIG_DEBUG_FS)

2355static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2356{
struct drm_info_node *node = (struct drm_info_node *)m->private;
unsigned ttm_pl = (uintptr_t)node->info_ent->data;
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
struct drm_printer p = drm_seq_file_printer(m);

man->func->debug(man, &p);
return 0;
2366}

2368static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM2},
{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT1},
{"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS(3 + 0)},
{"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS(3 + 1)},
{"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA(3 + 2)},
{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL((void *)0)},
2375#ifdef CONFIG_SWIOTLB
{"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL((void *)0)}
2377#endif
2378};

2380/**
* amdgpu_ttm_vram_read - Linear read access to VRAM
*
* Accesses VRAM via MMIO for debugging purposes.
*/
2385static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
		    size_t size, loff_t *pos)
2387{
struct amdgpu_device *adev = file_inode(f)->i_private;
ssize_t result = 0;

if (size & 0x3 || *pos & 0x3)
return -EINVAL22;

if (*pos >= adev->gmc.mc_vram_size)
return -ENXIO6;

size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos))(((size)<((size_t)(adev->gmc.mc_vram_size - *pos)))?(size
):((size_t)(adev->gmc.mc_vram_size - *pos)));
while (size) {
size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4)(((size)<((size_t)128 * 4))?(size):((size_t)128 * 4));
uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ(size_t)128];

amdgpu_device_vram_access(adev, *pos, value, bytes, false0);
if (copy_to_user(buf, value, bytes))
	return -EFAULT14;

result += bytes;
buf += bytes;
*pos += bytes;
size -= bytes;
}

return result;
2413}

2415/**
* amdgpu_ttm_vram_write - Linear write access to VRAM
*
* Accesses VRAM via MMIO for debugging purposes.
*/
2420static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
		    size_t size, loff_t *pos)
2422{
struct amdgpu_device *adev = file_inode(f)->i_private;
ssize_t result = 0;
int r;

if (size & 0x3 || *pos & 0x3)
return -EINVAL22;

if (*pos >= adev->gmc.mc_vram_size)
return -ENXIO6;

while (size) {
unsigned long flags;
uint32_t value;

if (*pos >= adev->gmc.mc_vram_size)
	return result;

r = get_user(value, (uint32_t *)buf)-copyin((uint32_t *)buf, &(value), sizeof(value));
if (r)
	return r;

spin_lock_irqsave(&adev->mmio_idx_lock, flags)do { flags = 0; mtx_enter(&adev->mmio_idx_lock); } while
 (0);
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000)amdgpu_device_wreg(adev, (0x0), (((uint32_t)*pos) | 0x80000000
), (1<<1));
WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31)amdgpu_device_wreg(adev, (0x6), (*pos >> 31), (1<<
1));
WREG32_NO_KIQ(mmMM_DATA, value)amdgpu_device_wreg(adev, (0x1), (value), (1<<1));
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->mmio_idx_lock); }
 while (0);

result += 4;
buf += 4;
*pos += 4;
size -= 4;
}

return result;
2457}

2459static const struct file_operations amdgpu_ttm_vram_fops = {
.owner = THIS_MODULE((void *)0),
.read = amdgpu_ttm_vram_read,
.write = amdgpu_ttm_vram_write,
.llseek = default_llseek,
2464};

2466#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS

2468/**
* amdgpu_ttm_gtt_read - Linear read access to GTT memory
*/
2471static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
		   size_t size, loff_t *pos)
2473{
struct amdgpu_device *adev = file_inode(f)->i_private;
ssize_t result = 0;
int r;

while (size) {
loff_t p = *pos / PAGE_SIZE(1 << 12);
unsigned off = *pos & ~LINUX_PAGE_MASK(~((1 << 12) - 1));
size_t cur_size = min_t(size_t, size, PAGE_SIZE - off)({ size_t __min_a = (size); size_t __min_b = ((1 << 12)
 - off); __min_a < __min_b ? __min_a : __min_b; });
struct vm_page *page;
void *ptr;

if (p >= adev->gart.num_cpu_pages)
	return result;

page = adev->gart.pages[p];
if (page) {
	ptr = kmap(page);
	ptr += off;

	r = copy_to_user(buf, ptr, cur_size);
	kunmap(adev->gart.pages[p]);
} else
	r = clear_user(buf, cur_size);

if (r)
	return -EFAULT14;

result += cur_size;
buf += cur_size;
*pos += cur_size;
size -= cur_size;
}

return result;
2508}

2510static const struct file_operations amdgpu_ttm_gtt_fops = {
.owner = THIS_MODULE((void *)0),
.read = amdgpu_ttm_gtt_read,
.llseek = default_llseek
2514};

2516#endif

2518/**
* amdgpu_iomem_read - Virtual read access to GPU mapped memory
*
* This function is used to read memory that has been mapped to the
* GPU and the known addresses are not physical addresses but instead
* bus addresses (e.g., what you'd put in an IB or ring buffer).
*/
2525static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
		 size_t size, loff_t *pos)
2527{
struct amdgpu_device *adev = file_inode(f)->i_private;
struct iommu_domain *dom;
ssize_t result = 0;
int r;

/* retrieve the IOMMU domain if any for this device */
dom = iommu_get_domain_for_dev(adev->dev);

while (size) {
phys_addr_t addr = *pos & LINUX_PAGE_MASK(~((1 << 12) - 1));
loff_t off = *pos & ~LINUX_PAGE_MASK(~((1 << 12) - 1));
size_t bytes = PAGE_SIZE(1 << 12) - off;
unsigned long pfn;
struct vm_page *p;
void *ptr;

bytes = bytes < size ? bytes : size;

/* Translate the bus address to a physical address.  If
 * the domain is NULL it means there is no IOMMU active
 * and the address translation is the identity
 */
addr = dom ? iommu_iova_to_phys(dom, addr) : addr;

pfn = addr >> PAGE_SHIFT12;
if (!pfn_valid(pfn))
	return -EPERM1;

p = pfn_to_page(pfn)(PHYS_TO_VM_PAGE(((paddr_t)(pfn) << 12)));
if (p->mapping != adev->mman.bdev.dev_mapping)
	return -EPERM1;

ptr = kmap(p);
r = copy_to_user(buf, ptr + off, bytes);
kunmap(p);
if (r)
	return -EFAULT14;

size -= bytes;
*pos += bytes;
result += bytes;
}

return result;
2572}

2574/**
* amdgpu_iomem_write - Virtual write access to GPU mapped memory
*
* This function is used to write memory that has been mapped to the
* GPU and the known addresses are not physical addresses but instead
* bus addresses (e.g., what you'd put in an IB or ring buffer).
*/
2581static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
		 size_t size, loff_t *pos)
2583{
struct amdgpu_device *adev = file_inode(f)->i_private;
struct iommu_domain *dom;
ssize_t result = 0;
int r;

dom = iommu_get_domain_for_dev(adev->dev);

while (size) {
phys_addr_t addr = *pos & LINUX_PAGE_MASK(~((1 << 12) - 1));
loff_t off = *pos & ~LINUX_PAGE_MASK(~((1 << 12) - 1));
size_t bytes = PAGE_SIZE(1 << 12) - off;
unsigned long pfn;
struct vm_page *p;
void *ptr;

bytes = bytes < size ? bytes : size;

addr = dom ? iommu_iova_to_phys(dom, addr) : addr;

pfn = addr >> PAGE_SHIFT12;
if (!pfn_valid(pfn))
	return -EPERM1;

p = pfn_to_page(pfn)(PHYS_TO_VM_PAGE(((paddr_t)(pfn) << 12)));
if (p->mapping != adev->mman.bdev.dev_mapping)
	return -EPERM1;

ptr = kmap(p);
r = copy_from_user(ptr + off, buf, bytes);
kunmap(p);
if (r)
	return -EFAULT14;

size -= bytes;
*pos += bytes;
result += bytes;
}

return result;
2623}

2625static const struct file_operations amdgpu_ttm_iomem_fops = {
.owner = THIS_MODULE((void *)0),
.read = amdgpu_iomem_read,
.write = amdgpu_iomem_write,
.llseek = default_llseek
2630};

2632static const struct {
char *name;
const struct file_operations *fops;
int domain;
2636} ttm_debugfs_entries[] = {
{ "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM2 },
2638#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
{ "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT1 },
2640#endif
{ "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM0 },
2642};

2644#endif

2646int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2647{
2648#if defined(CONFIG_DEBUG_FS)
unsigned count;

struct drm_minor *minor = adev_to_drm(adev)->primary;
struct dentry *ent, *root = minor->debugfs_root;

for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries)(sizeof((ttm_debugfs_entries)) / sizeof((ttm_debugfs_entries)
[0])); count++) {
ent = debugfs_create_file(
		ttm_debugfs_entries[count].name,
		S_IFREG | S_IRUGO, root,
		adev,
		ttm_debugfs_entries[count].fops);
if (IS_ERR(ent))
	return PTR_ERR(ent);
if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM2)
	i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
else if (ttm_debugfs_entries[count].domain == TTM_PL_TT1)
	i_size_write(ent->d_inode, adev->gmc.gart_size);
adev->mman.debugfs_entries[count] = ent;
}

count = ARRAY_SIZE(amdgpu_ttm_debugfs_list)(sizeof((amdgpu_ttm_debugfs_list)) / sizeof((amdgpu_ttm_debugfs_list
)[0]));

2671#ifdef CONFIG_SWIOTLB
if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
--count;
2674#endif

return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2677#else
return 0;
2679#endif
2680}