Bug Summary

File:dev/pci/drm/amd/amdgpu/hdp_v5_0.c
Warning:line 62, column 17
Although the value stored to 'hdp_clk_cntl1' is used in the enclosing expression, the value is never actually read from 'hdp_clk_cntl1'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name hdp_v5_0.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "hdp_v5_0.h"
26
27#include "hdp/hdp_5_0_0_offset.h"
28#include "hdp/hdp_5_0_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33{
34 if (!ring || !ring->funcs->emit_wreg)
35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0)amdgpu_device_wreg(adev, ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
) >> 2), (0), (1<<1));
36 else
37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0)(ring)->funcs->emit_wreg((ring), ((adev->rmmio_remap
.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2),
(0));
38}
39
40static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42{
43 if (!ring || !ring->funcs->emit_wreg) {
44 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d1, 1, (1<<1), HDP_HWIP) : amdgpu_device_wreg(
adev, (adev->reg_offset[HDP_HWIP][0][0] + 0x00d1), (1), 0)
);
45 } else {
46 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET((ring)->funcs->emit_wreg((ring), ((adev->reg_offset[
HDP_HWIP][0][0] + 0x00d1)), (1))
47 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1)(ring)->funcs->emit_wreg((ring), ((adev->reg_offset[
HDP_HWIP][0][0] + 0x00d1)), (1));
48 }
49}
50
51static void hdp_v5_0_update_mem_power_gating(struct amdgpu_device *adev,
52 bool_Bool enable)
53{
54 uint32_t hdp_clk_cntl, hdp_clk_cntl1;
55 uint32_t hdp_mem_pwr_cntl;
56
57 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS(1ULL << 15) |
58 AMD_CG_SUPPORT_HDP_DS(1ULL << 25) |
59 AMD_CG_SUPPORT_HDP_SD(1ULL << 26))))
60 return;
61
62 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d8, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d8), 0));
Although the value stored to 'hdp_clk_cntl1' is used in the enclosing expression, the value is never actually read from 'hdp_clk_cntl1'
63 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d4, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d4), 0));
64
65 /* Before doing clock/power mode switch,
66 * forced on IPH & RC clock */
67 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,(((hdp_clk_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)))
68 IPH_MEM_CLK_SOFT_OVERRIDE, 1)(((hdp_clk_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)));
69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,(((hdp_clk_cntl) & ~0x08000000L) | (0x08000000L & ((1
) << 0x1b)))
70 RC_MEM_CLK_SOFT_OVERRIDE, 1)(((hdp_clk_cntl) & ~0x08000000L) | (0x08000000L & ((1
) << 0x1b)));
71 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d8), hdp_clk_cntl, 0, HDP_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[HDP_HWIP][0][0] + 0x00d8)), (hdp_clk_cntl
), 0));
72
73 /* HDP 5.0 doesn't support dynamic power mode switch,
74 * disable clock and power gating before any changing */
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000001L) | (0x00000001L &
((0) << 0x0)))
76 IPH_MEM_POWER_CTRL_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00000001L) | (0x00000001L &
((0) << 0x0)));
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000002L) | (0x00000002L &
((0) << 0x1)))
78 IPH_MEM_POWER_LS_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00000002L) | (0x00000002L &
((0) << 0x1)));
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000004L) | (0x00000004L &
((0) << 0x2)))
80 IPH_MEM_POWER_DS_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00000004L) | (0x00000004L &
((0) << 0x2)));
81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000008L) | (0x00000008L &
((0) << 0x3)))
82 IPH_MEM_POWER_SD_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00000008L) | (0x00000008L &
((0) << 0x3)));
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00010000L) | (0x00010000L &
((0) << 0x10)))
84 RC_MEM_POWER_CTRL_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00010000L) | (0x00010000L &
((0) << 0x10)));
85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((0) << 0x11)))
86 RC_MEM_POWER_LS_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((0) << 0x11)));
87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((0) << 0x12)))
88 RC_MEM_POWER_DS_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((0) << 0x12)));
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00080000L) | (0x00080000L &
((0) << 0x13)))
90 RC_MEM_POWER_SD_EN, 0)(((hdp_mem_pwr_cntl) & ~0x00080000L) | (0x00080000L &
((0) << 0x13)));
91 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d4), hdp_mem_pwr_cntl, 0, HDP_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[HDP_HWIP][0][0] + 0x00d4)), (hdp_mem_pwr_cntl
), 0));
92
93 /* Already disabled above. The actions below are for "enabled" only */
94 if (enable) {
95 /* only one clock gating mode (LS/DS/SD) can be enabled */
96 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS(1ULL << 15)) {
97 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00000002L) | (0x00000002L &
((1) << 0x1)))
98 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000002L) | (0x00000002L &
((1) << 0x1)))
99 IPH_MEM_POWER_LS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00000002L) | (0x00000002L &
((1) << 0x1)));
100 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)))
101 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)))
102 RC_MEM_POWER_LS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)));
103 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS(1ULL << 25)) {
104 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00000004L) | (0x00000004L &
((1) << 0x2)))
105 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000004L) | (0x00000004L &
((1) << 0x2)))
106 IPH_MEM_POWER_DS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00000004L) | (0x00000004L &
((1) << 0x2)));
107 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)))
108 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)))
109 RC_MEM_POWER_DS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)));
110 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD(1ULL << 26)) {
111 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00000008L) | (0x00000008L &
((1) << 0x3)))
112 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000008L) | (0x00000008L &
((1) << 0x3)))
113 IPH_MEM_POWER_SD_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00000008L) | (0x00000008L &
((1) << 0x3)));
114 /* RC should not use shut down mode, fallback to ds or ls if allowed */
115 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS(1ULL << 25))
116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)))
117 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)))
118 RC_MEM_POWER_DS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00040000L) | (0x00040000L &
((1) << 0x12)));
119 else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS(1ULL << 15))
120 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)))
121 HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)))
122 RC_MEM_POWER_LS_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00020000L) | (0x00020000L &
((1) << 0x11)));
123 }
124
125 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
126 * be set for SRAM LS/DS/SD */
127 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS(1ULL << 15) | AMD_CG_SUPPORT_HDP_DS(1ULL << 25) |
128 AMD_CG_SUPPORT_HDP_SD(1ULL << 26))) {
129 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00000001L) | (0x00000001L &
((1) << 0x0)))
130 IPH_MEM_POWER_CTRL_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00000001L) | (0x00000001L &
((1) << 0x0)));
131 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,(((hdp_mem_pwr_cntl) & ~0x00010000L) | (0x00010000L &
((1) << 0x10)))
132 RC_MEM_POWER_CTRL_EN, 1)(((hdp_mem_pwr_cntl) & ~0x00010000L) | (0x00010000L &
((1) << 0x10)));
133 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d4), hdp_mem_pwr_cntl, 0, HDP_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[HDP_HWIP][0][0] + 0x00d4)), (hdp_mem_pwr_cntl
), 0));
134 }
135 }
136
137 /* disable IPH & RC clock override after clock/power mode changing */
138 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,(((hdp_clk_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)))
139 IPH_MEM_CLK_SOFT_OVERRIDE, 0)(((hdp_clk_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)));
140 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,(((hdp_clk_cntl) & ~0x08000000L) | (0x08000000L & ((0
) << 0x1b)))
141 RC_MEM_CLK_SOFT_OVERRIDE, 0)(((hdp_clk_cntl) & ~0x08000000L) | (0x08000000L & ((0
) << 0x1b)));
142 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d8), hdp_clk_cntl, 0, HDP_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[HDP_HWIP][0][0] + 0x00d8)), (hdp_clk_cntl
), 0));
143}
144
145static void hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
146 bool_Bool enable)
147{
148 uint32_t hdp_clk_cntl;
149
150 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG(1ULL << 16)))
151 return;
152
153 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d8, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d8), 0));
154
155 if (enable) {
156 hdp_clk_cntl &=
157 ~(uint32_t)
158 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK0x04000000L |
159 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK0x08000000L |
160 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK0x10000000L |
161 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK0x20000000L |
162 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK0x40000000L |
163 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK0x80000000L);
164 } else {
165 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK0x04000000L |
166 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK0x08000000L |
167 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK0x10000000L |
168 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK0x20000000L |
169 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK0x40000000L |
170 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK0x80000000L;
171 }
172
173 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d8), hdp_clk_cntl, 0, HDP_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[HDP_HWIP][0][0] + 0x00d8)), (hdp_clk_cntl
), 0));
174}
175
176static void hdp_v5_0_update_clock_gating(struct amdgpu_device *adev,
177 bool_Bool enable)
178{
179 hdp_v5_0_update_mem_power_gating(adev, enable);
180 hdp_v5_0_update_medium_grain_clock_gating(adev, enable);
181}
182
183static void hdp_v5_0_get_clockgating_state(struct amdgpu_device *adev,
184 u64 *flags)
185{
186 uint32_t tmp;
187
188 /* AMD_CG_SUPPORT_HDP_MGCG */
189 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d8, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d8), 0));
190 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK0x04000000L |
191 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK0x08000000L |
192 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK0x10000000L |
193 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK0x20000000L |
194 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK0x40000000L |
195 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK0x80000000L)))
196 *flags |= AMD_CG_SUPPORT_HDP_MGCG(1ULL << 16);
197
198 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
199 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d4, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d4), 0));
200 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK0x00000002L)
201 *flags |= AMD_CG_SUPPORT_HDP_LS(1ULL << 15);
202 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK0x00000004L)
203 *flags |= AMD_CG_SUPPORT_HDP_DS(1ULL << 25);
204 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK0x00000008L)
205 *flags |= AMD_CG_SUPPORT_HDP_SD(1ULL << 26);
206}
207
208static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
209{
210 u32 tmp;
211
212 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[HDP_HWIP][0][
0] + 0x00d3, 0, HDP_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[HDP_HWIP][0][0] + 0x00d3), 0));
213 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK0x00000001L;
214 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[HDP_HWIP][0]
[0] + 0x00d3), tmp, 0, HDP_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[HDP_HWIP][0][0] + 0x00d3)), (tmp), 0));
215}
216
217const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
218 .flush_hdp = hdp_v5_0_flush_hdp,
219 .invalidate_hdp = hdp_v5_0_invalidate_hdp,
220 .update_clock_gating = hdp_v5_0_update_clock_gating,
221 .get_clock_gating_state = hdp_v5_0_get_clockgating_state,
222 .init_registers = hdp_v5_0_init_registers,
223};