File: | dev/ic/com.c |
Warning: | line 1244, column 2 Value stored to 'stat' is never read |
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1 | /* $OpenBSD: com.c,v 1.178 2023/09/11 08:41:26 mvs Exp $ */ |
2 | /* $NetBSD: com.c,v 1.82.4.1 1996/06/02 09:08:00 mrg Exp $ */ |
3 | |
4 | /* |
5 | * Copyright (c) 1997 - 1999, Jason Downs. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS |
17 | * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
18 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
19 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, |
20 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
22 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
23 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
26 | * SUCH DAMAGE. |
27 | */ |
28 | /*- |
29 | * Copyright (c) 1993, 1994, 1995, 1996 |
30 | * Charles M. Hannum. All rights reserved. |
31 | * Copyright (c) 1991 The Regents of the University of California. |
32 | * All rights reserved. |
33 | * |
34 | * Redistribution and use in source and binary forms, with or without |
35 | * modification, are permitted provided that the following conditions |
36 | * are met: |
37 | * 1. Redistributions of source code must retain the above copyright |
38 | * notice, this list of conditions and the following disclaimer. |
39 | * 2. Redistributions in binary form must reproduce the above copyright |
40 | * notice, this list of conditions and the following disclaimer in the |
41 | * documentation and/or other materials provided with the distribution. |
42 | * 3. Neither the name of the University nor the names of its contributors |
43 | * may be used to endorse or promote products derived from this software |
44 | * without specific prior written permission. |
45 | * |
46 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
47 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
52 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
53 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
54 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
55 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
56 | * SUCH DAMAGE. |
57 | * |
58 | * @(#)com.c 7.5 (Berkeley) 5/16/91 |
59 | */ |
60 | |
61 | /* |
62 | * COM driver, based on HP dca driver |
63 | * uses National Semiconductor NS16450/NS16550AF UART |
64 | */ |
65 | #include <sys/param.h> |
66 | #include <sys/systm.h> |
67 | #include <sys/ioctl.h> |
68 | #include <sys/tty.h> |
69 | #include <sys/conf.h> |
70 | #include <sys/fcntl.h> |
71 | #include <sys/uio.h> |
72 | #include <sys/kernel.h> |
73 | #include <sys/syslog.h> |
74 | #include <sys/device.h> |
75 | #include <sys/vnode.h> |
76 | #ifdef DDB1 |
77 | #include <ddb/db_var.h> |
78 | #endif |
79 | |
80 | #include <machine/bus.h> |
81 | #include <machine/intr.h> |
82 | |
83 | #define COM_CONSOLE |
84 | #include <dev/cons.h> |
85 | |
86 | #include <dev/ic/comreg.h> |
87 | #include <dev/ic/comvar.h> |
88 | #include <dev/ic/ns16550reg.h> |
89 | #define com_lcr3 com_cfcr3 |
90 | |
91 | cdev_decl(com)int comopen(dev_t, int, int, struct proc *); int comclose(dev_t , int, int, struct proc *); int comread(dev_t, struct uio *, int ); int comwrite(dev_t, struct uio *, int); int comioctl(dev_t , u_long, caddr_t, int, struct proc *); int comstop(struct tty *, int); struct tty *comtty(dev_t); paddr_t commmap(dev_t, off_t , int); int comkqfilter(dev_t, struct knote *); |
92 | |
93 | static u_char tiocm_xxx2mcr(int); |
94 | |
95 | void compwroff(struct com_softc *); |
96 | void cominit(bus_space_tag_t, bus_space_handle_t, int, int); |
97 | int com_is_console(bus_space_tag_t, bus_addr_t); |
98 | |
99 | struct cfdriver com_cd = { |
100 | NULL((void *)0), "com", DV_TTY |
101 | }; |
102 | |
103 | int comdefaultrate = TTYDEF_SPEED(9600); |
104 | #ifdef COM_CONSOLE |
105 | int comconsfreq; |
106 | int comconsrate = TTYDEF_SPEED(9600); |
107 | bus_addr_t comconsaddr = 0; |
108 | int comconsattached; |
109 | bus_space_tag_t comconsiot; |
110 | bus_space_handle_t comconsioh; |
111 | int comconsunit; |
112 | tcflag_t comconscflag = TTYDEF_CFLAG(0x00000800 | 0x00000300 | 0x00004000); |
113 | #endif |
114 | |
115 | int commajor; |
116 | |
117 | #define DEVUNIT(x)(((unsigned)((x) & 0xff) | (((x) & 0xffff0000) >> 8)) & 0x7f) (minor(x)((unsigned)((x) & 0xff) | (((x) & 0xffff0000) >> 8)) & 0x7f) |
118 | #define DEVCUA(x)(((unsigned)((x) & 0xff) | (((x) & 0xffff0000) >> 8)) & 0x80) (minor(x)((unsigned)((x) & 0xff) | (((x) & 0xffff0000) >> 8)) & 0x80) |
119 | |
120 | int |
121 | comspeed(long freq, long speed) |
122 | { |
123 | #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ |
124 | |
125 | int x, err; |
126 | |
127 | if (speed == 0) |
128 | return 0; |
129 | if (speed < 0) |
130 | return -1; |
131 | x = divrnd((freq / 16), speed); |
132 | if (x <= 0) |
133 | return -1; |
134 | err = divrnd((quad_t)freq * 1000 / 16, speed * x) - 1000; |
135 | if (err < 0) |
136 | err = -err; |
137 | if (err > COM_TOLERANCE30) |
138 | return -1; |
139 | return x; |
140 | |
141 | #undef divrnd |
142 | } |
143 | |
144 | #ifdef COM_CONSOLE |
145 | int |
146 | comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) |
147 | { |
148 | int i; |
149 | |
150 | /* force access to id reg */ |
151 | bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS)((iot)->write_1((ioh), (3), (0x03))); |
152 | bus_space_write_1(iot, ioh, com_iir, 0)((iot)->write_1((ioh), (2), (0))); |
153 | for (i = 0; i < 32; i++) { |
154 | if ((bus_space_read_1(iot, ioh, com_lcr)((iot)->read_1((ioh), (3))) != LCR_8BITS0x03) || |
155 | (bus_space_read_1(iot, ioh, com_iir)((iot)->read_1((ioh), (2))) & 0x38)) { |
156 | bus_space_read_1(iot, ioh, com_data)((iot)->read_1((ioh), (0))); /* cleanup */ |
157 | } else |
158 | break; |
159 | } |
160 | if (i >= 32) |
161 | return 0; |
162 | |
163 | return 1; |
164 | } |
165 | #endif |
166 | |
167 | int |
168 | com_detach(struct device *self, int flags) |
169 | { |
170 | struct com_softc *sc = (struct com_softc *)self; |
171 | int maj, mn; |
172 | |
173 | sc->sc_swflags |= COM_SW_DEAD0x20; |
174 | |
175 | /* Locate the major number. */ |
176 | for (maj = 0; maj < nchrdev; maj++) |
177 | if (cdevsw[maj].d_open == comopen) |
178 | break; |
179 | |
180 | /* Nuke the vnodes for any open instances. */ |
181 | mn = self->dv_unit; |
182 | vdevgone(maj, mn, mn, VCHR); |
183 | |
184 | /* XXX a symbolic constant for the cua bit would be nicer. */ |
185 | mn |= 0x80; |
186 | vdevgone(maj, mn, mn, VCHR); |
187 | |
188 | timeout_del(&sc->sc_dtr_tmo); |
189 | timeout_del(&sc->sc_diag_tmo); |
190 | softintr_disestablish(sc->sc_si); |
191 | |
192 | /* Detach and free the tty. */ |
193 | if (sc->sc_tty) { |
194 | ttyfree(sc->sc_tty); |
195 | } |
196 | |
197 | return (0); |
198 | } |
199 | |
200 | int |
201 | com_activate(struct device *self, int act) |
202 | { |
203 | struct com_softc *sc = (struct com_softc *)self; |
204 | int s, rv = 0; |
205 | |
206 | switch (act) { |
207 | case DVACT_SUSPEND3: |
208 | if (timeout_del(&sc->sc_dtr_tmo)) { |
209 | /* Make sure DTR gets raised upon resume. */ |
210 | SET(sc->sc_mcr, MCR_DTR | MCR_RTS)((sc->sc_mcr) |= (0x01 | 0x02)); |
211 | } |
212 | timeout_del(&sc->sc_diag_tmo); |
213 | break; |
214 | case DVACT_RESUME4: |
215 | com_resume(sc); |
216 | break; |
217 | case DVACT_DEACTIVATE1: |
218 | if (sc->sc_hwflags & COM_HW_CONSOLE0x40) { |
219 | rv = EBUSY16; |
220 | break; |
221 | } |
222 | |
223 | s = spltty()splraise(0x9); |
224 | if (sc->disable != NULL((void *)0) && sc->enabled != 0) { |
225 | (*sc->disable)(sc); |
226 | sc->enabled = 0; |
227 | } |
228 | splx(s)spllower(s); |
229 | break; |
230 | } |
231 | return (rv); |
232 | } |
233 | |
234 | int |
235 | comopen(dev_t dev, int flag, int mode, struct proc *p) |
236 | { |
237 | int unit = DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f); |
238 | struct com_softc *sc; |
239 | struct tty *tp; |
240 | int s; |
241 | int error = 0; |
242 | |
243 | if (unit >= com_cd.cd_ndevs) |
244 | return ENXIO6; |
245 | sc = com_cd.cd_devs[unit]; |
246 | if (!sc) |
247 | return ENXIO6; |
248 | |
249 | s = spltty()splraise(0x9); |
250 | if (!sc->sc_tty) { |
251 | tp = sc->sc_tty = ttymalloc(1000000); |
252 | } else |
253 | tp = sc->sc_tty; |
254 | splx(s)spllower(s); |
255 | |
256 | tp->t_oproc = comstart; |
257 | tp->t_param = comparam; |
258 | tp->t_dev = dev; |
259 | if (!ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) { |
260 | SET(tp->t_state, TS_WOPEN)((tp->t_state) |= (0x00200)); |
261 | ttychars(tp); |
262 | tp->t_iflagt_termios.c_iflag = TTYDEF_IFLAG(0x00000002 | 0x00000100 | 0x00002000 | 0x00000200 | 0x00000800 ); |
263 | tp->t_oflagt_termios.c_oflag = TTYDEF_OFLAG(0x00000001 | 0x00000002); |
264 | #ifdef COM_CONSOLE |
265 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
266 | tp->t_cflagt_termios.c_cflag = comconscflag; |
267 | tp->t_ispeedt_termios.c_ispeed = tp->t_ospeedt_termios.c_ospeed = comconsrate; |
268 | } else |
269 | #endif |
270 | { |
271 | tp->t_cflagt_termios.c_cflag = TTYDEF_CFLAG(0x00000800 | 0x00000300 | 0x00004000); |
272 | tp->t_ispeedt_termios.c_ispeed = tp->t_ospeedt_termios.c_ospeed = comdefaultrate; |
273 | } |
274 | if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)((sc->sc_swflags) & (0x02))) |
275 | SET(tp->t_cflag, CLOCAL)((tp->t_termios.c_cflag) |= (0x00008000)); |
276 | if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)((sc->sc_swflags) & (0x04))) |
277 | SET(tp->t_cflag, CRTSCTS)((tp->t_termios.c_cflag) |= (0x00010000)); |
278 | if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)((sc->sc_swflags) & (0x08))) |
279 | SET(tp->t_cflag, MDMBUF)((tp->t_termios.c_cflag) |= (0x00100000)); |
280 | tp->t_lflagt_termios.c_lflag = TTYDEF_LFLAG(0x00000008 | 0x00000100 | 0x00000080 | 0x00000400 | 0x00000002 |0x00000001|0x00000040); |
281 | |
282 | s = spltty()splraise(0x9); |
283 | |
284 | sc->sc_initialize = 1; |
285 | comparam(tp, &tp->t_termios); |
286 | ttsetwater(tp); |
287 | |
288 | sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; |
289 | sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER((3 * (32 * 512)) / 4); |
290 | sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE(32 * 512); |
291 | |
292 | /* |
293 | * Wake up the sleepy heads. |
294 | */ |
295 | if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
296 | switch (sc->sc_uarttype) { |
297 | case COM_UART_ST166500x05: |
298 | case COM_UART_ST16650V20x06: |
299 | com_write_reg(sc, com_lcr3, LCR_EFR0xbf); |
300 | com_write_reg(sc, com_efr2, EFR_ECB0x10); |
301 | com_write_reg(sc, com_ier1, 0); |
302 | com_write_reg(sc, com_efr2, 0); |
303 | com_write_reg(sc, com_lcr3, 0); |
304 | break; |
305 | case COM_UART_TI167500x07: |
306 | com_write_reg(sc, com_ier1, 0); |
307 | break; |
308 | case COM_UART_XR17V35X0x12: |
309 | com_write_reg(sc, UART_EXAR_SLEEP0x8b, 0); |
310 | break; |
311 | } |
312 | } |
313 | |
314 | if (ISSET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) & (0x02))) { |
315 | u_int8_t fifo = FIFO_ENABLE0x01|FIFO_RCV_RST0x02|FIFO_XMT_RST0x04; |
316 | u_int8_t lcr; |
317 | |
318 | if (tp->t_ispeedt_termios.c_ispeed <= 1200) |
319 | fifo |= FIFO_TRIGGER_10x00; |
320 | else if (tp->t_ispeedt_termios.c_ispeed <= 38400) |
321 | fifo |= FIFO_TRIGGER_40x40; |
322 | else |
323 | fifo |= FIFO_TRIGGER_80x80; |
324 | if (sc->sc_uarttype == COM_UART_TI167500x07) { |
325 | fifo |= FIFO_ENABLE_64BYTE0x20; |
326 | lcr = com_read_reg(sc, com_lcr3); |
327 | com_write_reg(sc, com_lcr3, |
328 | lcr | LCR_DLAB0x80); |
329 | } |
330 | |
331 | /* |
332 | * (Re)enable and drain FIFOs. |
333 | * |
334 | * Certain SMC chips cause problems if the FIFOs are |
335 | * enabled while input is ready. Turn off the FIFO |
336 | * if necessary to clear the input. Test the input |
337 | * ready bit after enabling the FIFOs to handle races |
338 | * between enabling and fresh input. |
339 | * |
340 | * Set the FIFO threshold based on the receive speed. |
341 | */ |
342 | for (;;) { |
343 | com_write_reg(sc, com_fifo2, 0); |
344 | delay(100)(*delay_func)(100); |
345 | (void) com_read_reg(sc, com_data0); |
346 | com_write_reg(sc, com_fifo2, fifo | |
347 | FIFO_RCV_RST0x02 | FIFO_XMT_RST0x04); |
348 | delay(100)(*delay_func)(100); |
349 | if(!ISSET(com_read_reg(sc,((com_read_reg(sc, 5)) & (0x01)) |
350 | com_lsr), LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01))) |
351 | break; |
352 | } |
353 | if (sc->sc_uarttype == COM_UART_TI167500x07) |
354 | com_write_reg(sc, com_lcr3, lcr); |
355 | } |
356 | |
357 | /* Flush any pending I/O. */ |
358 | while (ISSET(com_read_reg(sc, com_lsr), LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01))) |
359 | (void) com_read_reg(sc, com_data0); |
360 | |
361 | /* You turn me on, baby! */ |
362 | sc->sc_mcr = MCR_DTR0x01 | MCR_RTS0x02; |
363 | if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)((sc->sc_hwflags) & (0x01))) |
364 | SET(sc->sc_mcr, MCR_IENABLE)((sc->sc_mcr) |= (0x08)); |
365 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
366 | sc->sc_ier = IER_ERXRDY0x1 | IER_ERLS0x4 | IER_EMSC0x8; |
367 | com_write_reg(sc, com_ier1, sc->sc_ier); |
368 | |
369 | sc->sc_msr = com_read_reg(sc, com_msr6); |
370 | if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR)((sc->sc_swflags) & (0x01)) || DEVCUA(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x80) || |
371 | ISSET(sc->sc_msr, MSR_DCD)((sc->sc_msr) & (0x80)) || ISSET(tp->t_cflag, MDMBUF)((tp->t_termios.c_cflag) & (0x00100000))) |
372 | SET(tp->t_state, TS_CARR_ON)((tp->t_state) |= (0x00008)); |
373 | else |
374 | CLR(tp->t_state, TS_CARR_ON)((tp->t_state) &= ~(0x00008)); |
375 | } else if (ISSET(tp->t_state, TS_XCLUDE)((tp->t_state) & (0x00400)) && suser(p) != 0) |
376 | return EBUSY16; |
377 | else |
378 | s = spltty()splraise(0x9); |
379 | |
380 | if (DEVCUA(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x80)) { |
381 | if (ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) { |
382 | /* Ah, but someone already is dialed in... */ |
383 | splx(s)spllower(s); |
384 | return EBUSY16; |
385 | } |
386 | sc->sc_cua = 1; /* We go into CUA mode. */ |
387 | } else { |
388 | /* tty (not cua) device; wait for carrier if necessary. */ |
389 | if (ISSET(flag, O_NONBLOCK)((flag) & (0x0004))) { |
390 | if (sc->sc_cua) { |
391 | /* Opening TTY non-blocking... but the CUA is busy. */ |
392 | splx(s)spllower(s); |
393 | return EBUSY16; |
394 | } |
395 | } else { |
396 | while (sc->sc_cua || |
397 | (!ISSET(tp->t_cflag, CLOCAL)((tp->t_termios.c_cflag) & (0x00008000)) && |
398 | !ISSET(tp->t_state, TS_CARR_ON)((tp->t_state) & (0x00008)))) { |
399 | SET(tp->t_state, TS_WOPEN)((tp->t_state) |= (0x00200)); |
400 | error = ttysleep(tp, &tp->t_rawq, TTIPRI25 | PCATCH0x100, ttopen); |
401 | /* |
402 | * If TS_WOPEN has been reset, that means the cua device |
403 | * has been closed. We don't want to fail in that case, |
404 | * so just go around again. |
405 | */ |
406 | if (error && ISSET(tp->t_state, TS_WOPEN)((tp->t_state) & (0x00200))) { |
407 | CLR(tp->t_state, TS_WOPEN)((tp->t_state) &= ~(0x00200)); |
408 | if (!sc->sc_cua && !ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) |
409 | compwroff(sc); |
410 | splx(s)spllower(s); |
411 | return error; |
412 | } |
413 | } |
414 | } |
415 | } |
416 | splx(s)spllower(s); |
417 | |
418 | return (*linesw[tp->t_line].l_open)(dev, tp, p); |
419 | } |
420 | |
421 | int |
422 | comclose(dev_t dev, int flag, int mode, struct proc *p) |
423 | { |
424 | int unit = DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f); |
425 | struct com_softc *sc = com_cd.cd_devs[unit]; |
426 | struct tty *tp = sc->sc_tty; |
427 | int s; |
428 | |
429 | #ifdef COM_CONSOLE |
430 | /* XXX This is for cons.c. */ |
431 | if (!ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) |
432 | return 0; |
433 | #endif |
434 | |
435 | if(sc->sc_swflags & COM_SW_DEAD0x20) |
436 | return 0; |
437 | |
438 | (*linesw[tp->t_line].l_close)(tp, flag, p); |
439 | s = spltty()splraise(0x9); |
440 | if (ISSET(tp->t_state, TS_WOPEN)((tp->t_state) & (0x00200))) { |
441 | /* tty device is waiting for carrier; drop dtr then re-raise */ |
442 | CLR(sc->sc_mcr, MCR_DTR | MCR_RTS)((sc->sc_mcr) &= ~(0x01 | 0x02)); |
443 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
444 | timeout_add_sec(&sc->sc_dtr_tmo, 2); |
445 | } else { |
446 | /* no one else waiting; turn off the uart */ |
447 | compwroff(sc); |
448 | } |
449 | CLR(tp->t_state, TS_BUSY | TS_FLUSH)((tp->t_state) &= ~(0x00004 | 0x00010)); |
450 | sc->sc_cua = 0; |
451 | splx(s)spllower(s); |
452 | ttyclose(tp); |
453 | |
454 | #ifdef COM_CONSOLE |
455 | #ifdef notyet /* XXXX */ |
456 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
457 | ttyfree(tp); |
458 | sc->sc_tty = 0; |
459 | } |
460 | #endif |
461 | #endif |
462 | return 0; |
463 | } |
464 | |
465 | void |
466 | compwroff(struct com_softc *sc) |
467 | { |
468 | struct tty *tp = sc->sc_tty; |
469 | |
470 | CLR(sc->sc_lcr, LCR_SBREAK)((sc->sc_lcr) &= ~(0x40)); |
471 | com_write_reg(sc, com_lcr3, sc->sc_lcr); |
472 | com_write_reg(sc, com_ier1, 0); |
473 | if (ISSET(tp->t_cflag, HUPCL)((tp->t_termios.c_cflag) & (0x00004000)) && |
474 | !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)((sc->sc_swflags) & (0x01))) { |
475 | /* XXX perhaps only clear DTR */ |
476 | sc->sc_mcr = 0; |
477 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
478 | } |
479 | |
480 | /* |
481 | * Turn FIFO off; enter sleep mode if possible. |
482 | */ |
483 | com_write_reg(sc, com_fifo2, 0); |
484 | delay(100)(*delay_func)(100); |
485 | if (ISSET(com_read_reg(sc, com_lsr), LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01))) |
486 | (void) com_read_reg(sc, com_data0); |
487 | delay(100)(*delay_func)(100); |
488 | com_write_reg(sc, com_fifo2, |
489 | FIFO_RCV_RST0x02 | FIFO_XMT_RST0x04); |
490 | |
491 | if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
492 | switch (sc->sc_uarttype) { |
493 | case COM_UART_ST166500x05: |
494 | case COM_UART_ST16650V20x06: |
495 | com_write_reg(sc, com_lcr3, LCR_EFR0xbf); |
496 | com_write_reg(sc, com_efr2, EFR_ECB0x10); |
497 | com_write_reg(sc, com_ier1, IER_SLEEP0x10); |
498 | com_write_reg(sc, com_lcr3, 0); |
499 | break; |
500 | case COM_UART_TI167500x07: |
501 | com_write_reg(sc, com_ier1, IER_SLEEP0x10); |
502 | break; |
503 | case COM_UART_XR17V35X0x12: |
504 | com_write_reg(sc, UART_EXAR_SLEEP0x8b, 0xff); |
505 | break; |
506 | } |
507 | } |
508 | } |
509 | |
510 | void |
511 | com_resume(struct com_softc *sc) |
512 | { |
513 | struct tty *tp = sc->sc_tty; |
514 | int ospeed; |
515 | |
516 | if (!tp || !ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) { |
517 | #ifdef COM_CONSOLE |
518 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) |
519 | cominit(comconsiot, comconsioh, comconsrate, |
520 | comconsfreq); |
521 | #endif |
522 | return; |
523 | } |
524 | |
525 | /* |
526 | * Wake up the sleepy heads. |
527 | */ |
528 | if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
529 | switch (sc->sc_uarttype) { |
530 | case COM_UART_ST166500x05: |
531 | case COM_UART_ST16650V20x06: |
532 | com_write_reg(sc, com_lcr3, LCR_EFR0xbf); |
533 | com_write_reg(sc, com_efr2, EFR_ECB0x10); |
534 | com_write_reg(sc, com_ier1, 0); |
535 | com_write_reg(sc, com_efr2, 0); |
536 | com_write_reg(sc, com_lcr3, 0); |
537 | break; |
538 | case COM_UART_TI167500x07: |
539 | com_write_reg(sc, com_ier1, 0); |
540 | break; |
541 | case COM_UART_XR17V35X0x12: |
542 | com_write_reg(sc, UART_EXAR_SLEEP0x8b, 0); |
543 | break; |
544 | } |
545 | } |
546 | |
547 | ospeed = comspeed(sc->sc_frequency, tp->t_ospeedt_termios.c_ospeed); |
548 | |
549 | if (ospeed != 0) { |
550 | com_write_reg(sc, com_lcr3, sc->sc_lcr | LCR_DLAB0x80); |
551 | com_write_reg(sc, com_dlbl0, ospeed); |
552 | com_write_reg(sc, com_dlbh1, ospeed >> 8); |
553 | com_write_reg(sc, com_lcr3, sc->sc_lcr); |
554 | } else { |
555 | com_write_reg(sc, com_lcr3, sc->sc_lcr); |
556 | } |
557 | |
558 | if (ISSET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) & (0x02))) { |
559 | u_int8_t fifo = FIFO_ENABLE0x01|FIFO_RCV_RST0x02|FIFO_XMT_RST0x04; |
560 | u_int8_t lcr; |
561 | |
562 | if (tp->t_ispeedt_termios.c_ispeed <= 1200) |
563 | fifo |= FIFO_TRIGGER_10x00; |
564 | else if (tp->t_ispeedt_termios.c_ispeed <= 38400) |
565 | fifo |= FIFO_TRIGGER_40x40; |
566 | else |
567 | fifo |= FIFO_TRIGGER_80x80; |
568 | if (sc->sc_uarttype == COM_UART_TI167500x07) { |
569 | fifo |= FIFO_ENABLE_64BYTE0x20; |
570 | lcr = com_read_reg(sc, com_lcr3); |
571 | com_write_reg(sc, com_lcr3, |
572 | lcr | LCR_DLAB0x80); |
573 | } |
574 | |
575 | /* |
576 | * (Re)enable and drain FIFOs. |
577 | * |
578 | * Certain SMC chips cause problems if the FIFOs are |
579 | * enabled while input is ready. Turn off the FIFO |
580 | * if necessary to clear the input. Test the input |
581 | * ready bit after enabling the FIFOs to handle races |
582 | * between enabling and fresh input. |
583 | * |
584 | * Set the FIFO threshold based on the receive speed. |
585 | */ |
586 | for (;;) { |
587 | com_write_reg(sc, com_fifo2, 0); |
588 | delay(100)(*delay_func)(100); |
589 | (void) com_read_reg(sc, com_data0); |
590 | com_write_reg(sc, com_fifo2, fifo | |
591 | FIFO_RCV_RST0x02 | FIFO_XMT_RST0x04); |
592 | delay(100)(*delay_func)(100); |
593 | if(!ISSET(com_read_reg(sc,((com_read_reg(sc, 5)) & (0x01)) |
594 | com_lsr), LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01))) |
595 | break; |
596 | } |
597 | if (sc->sc_uarttype == COM_UART_TI167500x07) |
598 | com_write_reg(sc, com_lcr3, lcr); |
599 | } |
600 | |
601 | /* You turn me on, baby! */ |
602 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
603 | com_write_reg(sc, com_ier1, sc->sc_ier); |
604 | } |
605 | |
606 | void |
607 | com_raisedtr(void *arg) |
608 | { |
609 | struct com_softc *sc = arg; |
610 | |
611 | SET(sc->sc_mcr, MCR_DTR | MCR_RTS)((sc->sc_mcr) |= (0x01 | 0x02)); |
612 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
613 | } |
614 | |
615 | int |
616 | comread(dev_t dev, struct uio *uio, int flag) |
617 | { |
618 | struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f)]; |
619 | struct tty *tp = sc->sc_tty; |
620 | |
621 | return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); |
622 | } |
623 | |
624 | int |
625 | comwrite(dev_t dev, struct uio *uio, int flag) |
626 | { |
627 | struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f)]; |
628 | struct tty *tp = sc->sc_tty; |
629 | |
630 | return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); |
631 | } |
632 | |
633 | struct tty * |
634 | comtty(dev_t dev) |
635 | { |
636 | struct com_softc *sc = com_cd.cd_devs[DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f)]; |
637 | struct tty *tp = sc->sc_tty; |
638 | |
639 | return (tp); |
640 | } |
641 | |
642 | static u_char |
643 | tiocm_xxx2mcr(int data) |
644 | { |
645 | u_char m = 0; |
646 | |
647 | if (ISSET(data, TIOCM_DTR)((data) & (0002))) |
648 | SET(m, MCR_DTR)((m) |= (0x01)); |
649 | if (ISSET(data, TIOCM_RTS)((data) & (0004))) |
650 | SET(m, MCR_RTS)((m) |= (0x02)); |
651 | return m; |
652 | } |
653 | |
654 | int |
655 | comioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) |
656 | { |
657 | int unit = DEVUNIT(dev)(((unsigned)((dev) & 0xff) | (((dev) & 0xffff0000) >> 8)) & 0x7f); |
658 | struct com_softc *sc = com_cd.cd_devs[unit]; |
659 | struct tty *tp = sc->sc_tty; |
660 | int error; |
661 | |
662 | error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); |
663 | if (error >= 0) |
664 | return error; |
665 | error = ttioctl(tp, cmd, data, flag, p); |
666 | if (error >= 0) |
667 | return error; |
668 | |
669 | switch (cmd) { |
670 | case TIOCSBRK((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('t')) << 8) | ((123))): |
671 | SET(sc->sc_lcr, LCR_SBREAK)((sc->sc_lcr) |= (0x40)); |
672 | com_write_reg(sc, com_lcr3, sc->sc_lcr); |
673 | break; |
674 | case TIOCCBRK((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('t')) << 8) | ((122))): |
675 | CLR(sc->sc_lcr, LCR_SBREAK)((sc->sc_lcr) &= ~(0x40)); |
676 | com_write_reg(sc, com_lcr3, sc->sc_lcr); |
677 | break; |
678 | case TIOCSDTR((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('t')) << 8) | ((121))): |
679 | SET(sc->sc_mcr, sc->sc_dtr)((sc->sc_mcr) |= (sc->sc_dtr)); |
680 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
681 | break; |
682 | case TIOCCDTR((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('t')) << 8) | ((120))): |
683 | CLR(sc->sc_mcr, sc->sc_dtr)((sc->sc_mcr) &= ~(sc->sc_dtr)); |
684 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
685 | break; |
686 | case TIOCMSET((unsigned long)0x80000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((109))): |
687 | CLR(sc->sc_mcr, MCR_DTR | MCR_RTS)((sc->sc_mcr) &= ~(0x01 | 0x02)); |
688 | case TIOCMBIS((unsigned long)0x80000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((108))): |
689 | SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data))((sc->sc_mcr) |= (tiocm_xxx2mcr(*(int *)data))); |
690 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
691 | break; |
692 | case TIOCMBIC((unsigned long)0x80000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((107))): |
693 | CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data))((sc->sc_mcr) &= ~(tiocm_xxx2mcr(*(int *)data))); |
694 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
695 | break; |
696 | case TIOCMGET((unsigned long)0x40000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((106))): { |
697 | u_char m; |
698 | int bits = 0; |
699 | |
700 | m = sc->sc_mcr; |
701 | if (ISSET(m, MCR_DTR)((m) & (0x01))) |
702 | SET(bits, TIOCM_DTR)((bits) |= (0002)); |
703 | if (ISSET(m, MCR_RTS)((m) & (0x02))) |
704 | SET(bits, TIOCM_RTS)((bits) |= (0004)); |
705 | m = sc->sc_msr; |
706 | if (ISSET(m, MSR_DCD)((m) & (0x80))) |
707 | SET(bits, TIOCM_CD)((bits) |= (0100)); |
708 | if (ISSET(m, MSR_CTS)((m) & (0x10))) |
709 | SET(bits, TIOCM_CTS)((bits) |= (0040)); |
710 | if (ISSET(m, MSR_DSR)((m) & (0x20))) |
711 | SET(bits, TIOCM_DSR)((bits) |= (0400)); |
712 | if (ISSET(m, MSR_RI | MSR_TERI)((m) & (0x40 | 0x04))) |
713 | SET(bits, TIOCM_RI)((bits) |= (0200)); |
714 | if (com_read_reg(sc, com_ier1)) |
715 | SET(bits, TIOCM_LE)((bits) |= (0001)); |
716 | *(int *)data = bits; |
717 | break; |
718 | } |
719 | case TIOCGFLAGS((unsigned long)0x40000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((93))): { |
720 | int driverbits, userbits = 0; |
721 | |
722 | driverbits = sc->sc_swflags; |
723 | if (ISSET(driverbits, COM_SW_SOFTCAR)((driverbits) & (0x01))) |
724 | SET(userbits, TIOCFLAG_SOFTCAR)((userbits) |= (0x01)); |
725 | if (ISSET(driverbits, COM_SW_CLOCAL)((driverbits) & (0x02))) |
726 | SET(userbits, TIOCFLAG_CLOCAL)((userbits) |= (0x02)); |
727 | if (ISSET(driverbits, COM_SW_CRTSCTS)((driverbits) & (0x04))) |
728 | SET(userbits, TIOCFLAG_CRTSCTS)((userbits) |= (0x04)); |
729 | if (ISSET(driverbits, COM_SW_MDMBUF)((driverbits) & (0x08))) |
730 | SET(userbits, TIOCFLAG_MDMBUF)((userbits) |= (0x08)); |
731 | if (ISSET(driverbits, COM_SW_PPS)((driverbits) & (0x10))) |
732 | SET(userbits, TIOCFLAG_PPS)((userbits) |= (0x10)); |
733 | |
734 | *(int *)data = userbits; |
735 | break; |
736 | } |
737 | case TIOCSFLAGS((unsigned long)0x80000000 | ((sizeof(int) & 0x1fff) << 16) | ((('t')) << 8) | ((92))): { |
738 | int userbits, driverbits = 0; |
739 | |
740 | error = suser(p); |
741 | if (error != 0) |
742 | return(EPERM1); |
743 | |
744 | userbits = *(int *)data; |
745 | if (ISSET(userbits, TIOCFLAG_SOFTCAR)((userbits) & (0x01)) || |
746 | ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) |
747 | SET(driverbits, COM_SW_SOFTCAR)((driverbits) |= (0x01)); |
748 | if (ISSET(userbits, TIOCFLAG_CLOCAL)((userbits) & (0x02))) |
749 | SET(driverbits, COM_SW_CLOCAL)((driverbits) |= (0x02)); |
750 | if (ISSET(userbits, TIOCFLAG_CRTSCTS)((userbits) & (0x04))) |
751 | SET(driverbits, COM_SW_CRTSCTS)((driverbits) |= (0x04)); |
752 | if (ISSET(userbits, TIOCFLAG_MDMBUF)((userbits) & (0x08))) |
753 | SET(driverbits, COM_SW_MDMBUF)((driverbits) |= (0x08)); |
754 | if (ISSET(userbits, TIOCFLAG_PPS)((userbits) & (0x10))) |
755 | SET(driverbits, COM_SW_PPS)((driverbits) |= (0x10)); |
756 | |
757 | sc->sc_swflags = driverbits; |
758 | break; |
759 | } |
760 | default: |
761 | return ENOTTY25; |
762 | } |
763 | |
764 | return 0; |
765 | } |
766 | |
767 | /* already called at spltty */ |
768 | int |
769 | comparam(struct tty *tp, struct termios *t) |
770 | { |
771 | struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)(((unsigned)((tp->t_dev) & 0xff) | (((tp->t_dev) & 0xffff0000) >> 8)) & 0x7f)]; |
772 | int ospeed = comspeed(sc->sc_frequency, t->c_ospeed); |
773 | u_char lcr; |
774 | tcflag_t oldcflag; |
775 | |
776 | /* Check requested parameters. */ |
777 | if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) |
778 | return EINVAL22; |
779 | |
780 | lcr = ISSET(sc->sc_lcr, LCR_SBREAK)((sc->sc_lcr) & (0x40)); |
781 | |
782 | switch (ISSET(t->c_cflag, CSIZE)((t->c_cflag) & (0x00000300))) { |
783 | case CS50x00000000: |
784 | SET(lcr, LCR_5BITS)((lcr) |= (0x00)); |
785 | break; |
786 | case CS60x00000100: |
787 | SET(lcr, LCR_6BITS)((lcr) |= (0x01)); |
788 | break; |
789 | case CS70x00000200: |
790 | SET(lcr, LCR_7BITS)((lcr) |= (0x02)); |
791 | break; |
792 | case CS80x00000300: |
793 | SET(lcr, LCR_8BITS)((lcr) |= (0x03)); |
794 | break; |
795 | } |
796 | if (ISSET(t->c_cflag, PARENB)((t->c_cflag) & (0x00001000))) { |
797 | SET(lcr, LCR_PENAB)((lcr) |= (0x08)); |
798 | if (!ISSET(t->c_cflag, PARODD)((t->c_cflag) & (0x00002000))) |
799 | SET(lcr, LCR_PEVEN)((lcr) |= (0x18)); |
800 | } |
801 | if (ISSET(t->c_cflag, CSTOPB)((t->c_cflag) & (0x00000400))) |
802 | SET(lcr, LCR_STOPB)((lcr) |= (0x04)); |
803 | |
804 | sc->sc_lcr = lcr; |
805 | |
806 | if (ospeed == 0) { |
807 | CLR(sc->sc_mcr, MCR_DTR)((sc->sc_mcr) &= ~(0x01)); |
808 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
809 | } |
810 | |
811 | /* |
812 | * Set the FIFO threshold based on the receive speed, if we are |
813 | * changing it. |
814 | */ |
815 | if (sc->sc_initialize || (tp->t_ispeedt_termios.c_ispeed != t->c_ispeed)) { |
816 | sc->sc_initialize = 0; |
817 | |
818 | if (ospeed != 0) { |
819 | /* |
820 | * Make sure the transmit FIFO is empty before |
821 | * proceeding. If we don't do this, some revisions |
822 | * of the UART will hang. Interestingly enough, |
823 | * even if we do this while the last character is |
824 | * still being pushed out, they don't hang. This |
825 | * seems good enough. |
826 | */ |
827 | while (ISSET(tp->t_state, TS_BUSY)((tp->t_state) & (0x00004))) { |
828 | int error; |
829 | |
830 | ++sc->sc_halt; |
831 | error = ttysleep(tp, &tp->t_outq, |
832 | TTOPRI26 | PCATCH0x100, "comprm"); |
833 | --sc->sc_halt; |
834 | if (error) { |
835 | comstart(tp); |
836 | return (error); |
837 | } |
838 | } |
839 | |
840 | com_write_reg(sc, com_lcr3, lcr | LCR_DLAB0x80); |
841 | com_write_reg(sc, com_dlbl0, ospeed); |
842 | com_write_reg(sc, com_dlbh1, ospeed >> 8); |
843 | com_write_reg(sc, com_lcr3, lcr); |
844 | SET(sc->sc_mcr, MCR_DTR)((sc->sc_mcr) |= (0x01)); |
845 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
846 | } else |
847 | com_write_reg(sc, com_lcr3, lcr); |
848 | |
849 | if (ISSET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) & (0x02))) { |
850 | if (sc->sc_uarttype == COM_UART_TI167500x07) { |
851 | com_write_reg(sc, com_lcr3, |
852 | lcr | LCR_DLAB0x80); |
853 | com_write_reg(sc, com_fifo2, |
854 | FIFO_ENABLE0x01 | FIFO_ENABLE_64BYTE0x20 | |
855 | (t->c_ispeed <= 1200 ? FIFO_TRIGGER_10x00 : FIFO_TRIGGER_80x80)); |
856 | com_write_reg(sc, com_lcr3, lcr); |
857 | } else |
858 | com_write_reg(sc, com_fifo2, |
859 | FIFO_ENABLE0x01 | |
860 | (t->c_ispeed <= 1200 ? FIFO_TRIGGER_10x00 : FIFO_TRIGGER_80x80)); |
861 | } |
862 | } else |
863 | com_write_reg(sc, com_lcr3, lcr); |
864 | |
865 | /* When not using CRTSCTS, RTS follows DTR. */ |
866 | if (!ISSET(t->c_cflag, CRTSCTS)((t->c_cflag) & (0x00010000))) { |
867 | if (ISSET(sc->sc_mcr, MCR_DTR)((sc->sc_mcr) & (0x01))) { |
868 | if (!ISSET(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) & (0x02))) { |
869 | SET(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) |= (0x02)); |
870 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
871 | } |
872 | } else { |
873 | if (ISSET(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) & (0x02))) { |
874 | CLR(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) &= ~(0x02)); |
875 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
876 | } |
877 | } |
878 | sc->sc_dtr = MCR_DTR0x01 | MCR_RTS0x02; |
879 | } else |
880 | sc->sc_dtr = MCR_DTR0x01; |
881 | |
882 | /* and copy to tty */ |
883 | tp->t_ispeedt_termios.c_ispeed = t->c_ispeed; |
884 | tp->t_ospeedt_termios.c_ospeed = t->c_ospeed; |
885 | oldcflag = tp->t_cflagt_termios.c_cflag; |
886 | tp->t_cflagt_termios.c_cflag = t->c_cflag; |
887 | |
888 | /* |
889 | * If DCD is off and MDMBUF is changed, ask the tty layer if we should |
890 | * stop the device. |
891 | */ |
892 | if (!ISSET(sc->sc_msr, MSR_DCD)((sc->sc_msr) & (0x80)) && |
893 | !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)((sc->sc_swflags) & (0x01)) && |
894 | ISSET(oldcflag, MDMBUF)((oldcflag) & (0x00100000)) != ISSET(tp->t_cflag, MDMBUF)((tp->t_termios.c_cflag) & (0x00100000)) && |
895 | (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { |
896 | CLR(sc->sc_mcr, sc->sc_dtr)((sc->sc_mcr) &= ~(sc->sc_dtr)); |
897 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
898 | } |
899 | |
900 | /* Just to be sure... */ |
901 | comstart(tp); |
902 | return 0; |
903 | } |
904 | |
905 | void |
906 | comstart(struct tty *tp) |
907 | { |
908 | struct com_softc *sc = com_cd.cd_devs[DEVUNIT(tp->t_dev)(((unsigned)((tp->t_dev) & 0xff) | (((tp->t_dev) & 0xffff0000) >> 8)) & 0x7f)]; |
909 | int s; |
910 | |
911 | s = spltty()splraise(0x9); |
912 | if (ISSET(tp->t_state, TS_BUSY)((tp->t_state) & (0x00004))) |
913 | goto out; |
914 | if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP)((tp->t_state) & (0x00080 | 0x00100)) || sc->sc_halt > 0) |
915 | goto stopped; |
916 | if (ISSET(tp->t_cflag, CRTSCTS)((tp->t_termios.c_cflag) & (0x00010000)) && !ISSET(sc->sc_msr, MSR_CTS)((sc->sc_msr) & (0x10))) |
917 | goto stopped; |
918 | ttwakeupwr(tp); |
919 | if (tp->t_outq.c_cc == 0) |
920 | goto stopped; |
921 | SET(tp->t_state, TS_BUSY)((tp->t_state) |= (0x00004)); |
922 | |
923 | /* Enable transmit completion interrupts. */ |
924 | if (!ISSET(sc->sc_ier, IER_ETXRDY)((sc->sc_ier) & (0x2))) { |
925 | SET(sc->sc_ier, IER_ETXRDY)((sc->sc_ier) |= (0x2)); |
926 | com_write_reg(sc, com_ier1, sc->sc_ier); |
927 | } |
928 | |
929 | if (ISSET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) & (0x02))) { |
930 | u_char buffer[256]; /* largest fifo */ |
931 | int i, n; |
932 | |
933 | n = q_to_b(&tp->t_outq, buffer, |
934 | min(sc->sc_fifolen, sizeof buffer)); |
935 | for (i = 0; i < n; i++) { |
936 | com_write_reg(sc, com_data0, buffer[i]); |
937 | } |
938 | bzero(buffer, n)__builtin_bzero((buffer), (n)); |
939 | } else if (tp->t_outq.c_cc != 0) |
940 | com_write_reg(sc, com_data0, getc(&tp->t_outq)); |
941 | out: |
942 | splx(s)spllower(s); |
943 | return; |
944 | stopped: |
945 | if (ISSET(sc->sc_ier, IER_ETXRDY)((sc->sc_ier) & (0x2))) { |
946 | CLR(sc->sc_ier, IER_ETXRDY)((sc->sc_ier) &= ~(0x2)); |
947 | com_write_reg(sc, com_ier1, sc->sc_ier); |
948 | } |
949 | splx(s)spllower(s); |
950 | } |
951 | |
952 | /* |
953 | * Stop output on a line. |
954 | */ |
955 | int |
956 | comstop(struct tty *tp, int flag) |
957 | { |
958 | int s; |
959 | |
960 | s = spltty()splraise(0x9); |
961 | if (ISSET(tp->t_state, TS_BUSY)((tp->t_state) & (0x00004))) |
962 | if (!ISSET(tp->t_state, TS_TTSTOP)((tp->t_state) & (0x00100))) |
963 | SET(tp->t_state, TS_FLUSH)((tp->t_state) |= (0x00010)); |
964 | splx(s)spllower(s); |
965 | return 0; |
966 | } |
967 | |
968 | void |
969 | comdiag(void *arg) |
970 | { |
971 | struct com_softc *sc = arg; |
972 | int overflows, floods; |
973 | int s; |
974 | |
975 | s = spltty()splraise(0x9); |
976 | sc->sc_errors = 0; |
977 | overflows = sc->sc_overflows; |
978 | sc->sc_overflows = 0; |
979 | floods = sc->sc_floods; |
980 | sc->sc_floods = 0; |
981 | splx(s)spllower(s); |
982 | log(LOG_WARNING4, "%s: %d silo overflow%s, %d ibuf overflow%s\n", |
983 | sc->sc_dev.dv_xname, |
984 | overflows, overflows == 1 ? "" : "s", |
985 | floods, floods == 1 ? "" : "s"); |
986 | } |
987 | |
988 | void |
989 | comsoft(void *arg) |
990 | { |
991 | struct com_softc *sc = (struct com_softc *)arg; |
992 | struct tty *tp; |
993 | u_char *ibufp; |
994 | u_char *ibufend; |
995 | int c; |
996 | int s; |
997 | static int lsrmap[8] = { |
998 | 0, TTY_PE0x02000000, |
999 | TTY_FE0x01000000, TTY_PE0x02000000|TTY_FE0x01000000, |
1000 | TTY_FE0x01000000, TTY_PE0x02000000|TTY_FE0x01000000, |
1001 | TTY_FE0x01000000, TTY_PE0x02000000|TTY_FE0x01000000 |
1002 | }; |
1003 | |
1004 | if (sc == NULL((void *)0) || sc->sc_ibufp == sc->sc_ibuf) |
1005 | return; |
1006 | |
1007 | tp = sc->sc_tty; |
1008 | |
1009 | s = spltty()splraise(0x9); |
1010 | |
1011 | ibufp = sc->sc_ibuf; |
1012 | ibufend = sc->sc_ibufp; |
1013 | |
1014 | if (ibufp == ibufend) { |
1015 | splx(s)spllower(s); |
1016 | return; |
1017 | } |
1018 | |
1019 | sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? |
1020 | sc->sc_ibufs[1] : sc->sc_ibufs[0]; |
1021 | sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER((3 * (32 * 512)) / 4); |
1022 | sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE(32 * 512); |
1023 | |
1024 | if (tp == NULL((void *)0) || !ISSET(tp->t_state, TS_ISOPEN)((tp->t_state) & (0x00020))) { |
1025 | splx(s)spllower(s); |
1026 | return; |
1027 | } |
1028 | |
1029 | if (ISSET(tp->t_cflag, CRTSCTS)((tp->t_termios.c_cflag) & (0x00010000)) && |
1030 | !ISSET(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) & (0x02))) { |
1031 | /* XXX */ |
1032 | SET(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) |= (0x02)); |
1033 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
1034 | } |
1035 | |
1036 | splx(s)spllower(s); |
1037 | |
1038 | while (ibufp < ibufend) { |
1039 | c = *ibufp++; |
1040 | if (ISSET(*ibufp, LSR_OE)((*ibufp) & (0x02))) { |
1041 | sc->sc_overflows++; |
1042 | if (sc->sc_errors++ == 0) |
1043 | timeout_add_sec(&sc->sc_diag_tmo, 60); |
1044 | } |
1045 | /* This is ugly, but fast. */ |
1046 | c |= lsrmap[(*ibufp++ & (LSR_BI0x10|LSR_FE0x08|LSR_PE0x04)) >> 2]; |
1047 | (*linesw[tp->t_line].l_rint)(c, tp); |
1048 | } |
1049 | } |
1050 | |
1051 | int |
1052 | comintr(void *arg) |
1053 | { |
1054 | struct com_softc *sc = arg; |
1055 | struct tty *tp; |
1056 | u_char lsr, data, msr, delta; |
1057 | |
1058 | if (!sc->sc_tty) |
1059 | return (0); /* Can't do squat. */ |
1060 | |
1061 | if (ISSET(com_read_reg(sc, com_iir), IIR_NOPEND)((com_read_reg(sc, 2)) & (0x1))) |
1062 | return (0); |
1063 | |
1064 | tp = sc->sc_tty; |
1065 | |
1066 | for (;;) { |
1067 | lsr = com_read_reg(sc, com_lsr5); |
1068 | |
1069 | if (ISSET(lsr, LSR_RXRDY)((lsr) & (0x01))) { |
1070 | u_char *p = sc->sc_ibufp; |
1071 | |
1072 | softintr_schedule(sc->sc_si)do { struct x86_soft_intrhand *__sih = (sc->sc_si); struct x86_soft_intr *__si = __sih->sih_intrhead; mtx_enter(& __si->softintr_lock); if (__sih->sih_pending == 0) { do { (__sih)->sih_q.tqe_next = ((void *)0); (__sih)->sih_q .tqe_prev = (&__si->softintr_q)->tqh_last; *(&__si ->softintr_q)->tqh_last = (__sih); (&__si->softintr_q )->tqh_last = &(__sih)->sih_q.tqe_next; } while (0) ; __sih->sih_pending = 1; softintr(__si->softintr_ssir) ; } mtx_leave(&__si->softintr_lock); } while ( 0); |
1073 | do { |
1074 | data = com_read_reg(sc, com_data0); |
1075 | if (ISSET(lsr, LSR_BI)((lsr) & (0x10))) { |
1076 | #if defined(COM_CONSOLE) && defined(DDB1) |
1077 | if (ISSET(sc->sc_hwflags,((sc->sc_hwflags) & (0x40)) |
1078 | COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
1079 | if (db_console) |
1080 | db_enter(); |
1081 | goto next; |
1082 | } |
1083 | #endif |
1084 | data = 0; |
1085 | } |
1086 | if (p >= sc->sc_ibufend) { |
1087 | sc->sc_floods++; |
1088 | if (sc->sc_errors++ == 0) |
1089 | timeout_add_sec(&sc->sc_diag_tmo, 60); |
1090 | } else { |
1091 | *p++ = data; |
1092 | *p++ = lsr; |
1093 | if (p == sc->sc_ibufhigh && |
1094 | ISSET(tp->t_cflag, CRTSCTS)((tp->t_termios.c_cflag) & (0x00010000))) { |
1095 | /* XXX */ |
1096 | CLR(sc->sc_mcr, MCR_RTS)((sc->sc_mcr) &= ~(0x02)); |
1097 | com_write_reg(sc, com_mcr4, |
1098 | sc->sc_mcr); |
1099 | } |
1100 | } |
1101 | #if defined(COM_CONSOLE) && defined(DDB1) |
1102 | next: |
1103 | #endif |
1104 | lsr = com_read_reg(sc, com_lsr5); |
1105 | } while (ISSET(lsr, LSR_RXRDY)((lsr) & (0x01))); |
1106 | |
1107 | sc->sc_ibufp = p; |
1108 | } |
1109 | msr = com_read_reg(sc, com_msr6); |
1110 | |
1111 | if (msr != sc->sc_msr) { |
1112 | delta = msr ^ sc->sc_msr; |
1113 | |
1114 | ttytstamp(tp, sc->sc_msr & MSR_CTS0x10, msr & MSR_CTS0x10, |
1115 | sc->sc_msr & MSR_DCD0x80, msr & MSR_DCD0x80); |
1116 | |
1117 | sc->sc_msr = msr; |
1118 | if (ISSET(delta, MSR_DCD)((delta) & (0x80))) { |
1119 | if (!ISSET(sc->sc_swflags, COM_SW_SOFTCAR)((sc->sc_swflags) & (0x01)) && |
1120 | (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)((msr) & (0x80))) == 0) { |
1121 | CLR(sc->sc_mcr, sc->sc_dtr)((sc->sc_mcr) &= ~(sc->sc_dtr)); |
1122 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
1123 | } |
1124 | } |
1125 | if (ISSET(delta & msr, MSR_CTS)((delta & msr) & (0x10)) && |
1126 | ISSET(tp->t_cflag, CRTSCTS)((tp->t_termios.c_cflag) & (0x00010000))) { |
1127 | /* the line is up and we want to do rts/cts flow control */ |
1128 | (*linesw[tp->t_line].l_start)(tp); |
1129 | } |
1130 | } |
1131 | |
1132 | if (ISSET(lsr, LSR_TXRDY)((lsr) & (0x20)) && ISSET(tp->t_state, TS_BUSY)((tp->t_state) & (0x00004))) { |
1133 | CLR(tp->t_state, TS_BUSY | TS_FLUSH)((tp->t_state) &= ~(0x00004 | 0x00010)); |
1134 | if (sc->sc_halt > 0) |
1135 | wakeup(&tp->t_outq); |
1136 | (*linesw[tp->t_line].l_start)(tp); |
1137 | } |
1138 | |
1139 | if (ISSET(com_read_reg(sc, com_iir), IIR_NOPEND)((com_read_reg(sc, 2)) & (0x1))) |
1140 | return (1); |
1141 | } |
1142 | } |
1143 | |
1144 | void |
1145 | cominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int frequency) |
1146 | { |
1147 | int s = splhigh()splraise(0xd); |
1148 | u_char stat; |
1149 | |
1150 | bus_space_write_1(iot, ioh, com_lcr, LCR_DLAB)((iot)->write_1((ioh), (3), (0x80))); |
1151 | rate = comspeed(frequency, rate); /* XXX not comdefaultrate? */ |
1152 | bus_space_write_1(iot, ioh, com_dlbl, rate)((iot)->write_1((ioh), (0), (rate))); |
1153 | bus_space_write_1(iot, ioh, com_dlbh, rate >> 8)((iot)->write_1((ioh), (1), (rate >> 8))); |
1154 | bus_space_write_1(iot, ioh, com_lcr, LCR_8BITS)((iot)->write_1((ioh), (3), (0x03))); |
1155 | bus_space_write_1(iot, ioh, com_mcr, MCR_DTR | MCR_RTS)((iot)->write_1((ioh), (4), (0x01 | 0x02))); |
1156 | bus_space_write_1(iot, ioh, com_ier, 0)((iot)->write_1((ioh), (1), (0))); /* Make sure they are off */ |
1157 | bus_space_write_1(iot, ioh, com_fifo,((iot)->write_1((ioh), (2), (0x01 | 0x02 | 0x04 | 0x00))) |
1158 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1)((iot)->write_1((ioh), (2), (0x01 | 0x02 | 0x04 | 0x00))); |
1159 | stat = bus_space_read_1(iot, ioh, com_iir)((iot)->read_1((ioh), (2))); |
1160 | splx(s)spllower(s); |
1161 | } |
1162 | |
1163 | #ifdef COM_CONSOLE |
1164 | void |
1165 | comcnprobe(struct consdev *cp) |
1166 | { |
1167 | bus_space_handle_t ioh; |
1168 | int found = 1; |
1169 | |
1170 | if (comconsaddr == 0) |
1171 | return; |
1172 | |
1173 | if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS8, 0, &ioh)) |
1174 | return; |
1175 | /* XXX Some com@acpi devices will fail the comprobe1() check */ |
1176 | if (comcons_reg_width != 4) |
1177 | found = comprobe1(comconsiot, ioh); |
1178 | bus_space_unmap(comconsiot, ioh, COM_NPORTS8); |
1179 | if (!found) |
1180 | return; |
1181 | |
1182 | /* Locate the major number. */ |
1183 | for (commajor = 0; commajor < nchrdev; commajor++) |
1184 | if (cdevsw[commajor].d_open == comopen) |
1185 | break; |
1186 | |
1187 | /* Initialize required fields. */ |
1188 | cp->cn_dev = makedev(commajor, comconsunit)((dev_t)((((commajor) & 0xff) << 8) | ((comconsunit ) & 0xff) | (((comconsunit) & 0xffff00) << 8))); |
1189 | cp->cn_pri = CN_HIGHPRI3; |
1190 | } |
1191 | |
1192 | void |
1193 | comcninit(struct consdev *cp) |
1194 | { |
1195 | if (bus_space_map(comconsiot, comconsaddr, COM_NPORTS8, 0, &comconsioh)) |
1196 | panic("comcninit: mapping failed"); |
1197 | |
1198 | if (comconsfreq == 0) |
1199 | comconsfreq = COM_FREQ1843200; |
1200 | |
1201 | cominit(comconsiot, comconsioh, comconsrate, comconsfreq); |
1202 | } |
1203 | |
1204 | int |
1205 | comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, |
1206 | int frequency, tcflag_t cflag) |
1207 | { |
1208 | static struct consdev comcons = { |
1209 | NULL((void *)0), NULL((void *)0), comcngetc, comcnputc, comcnpollc, NULL((void *)0), |
1210 | NODEV(dev_t)(-1), CN_LOWPRI1 |
1211 | }; |
1212 | |
1213 | #ifndef __sparc64__ |
1214 | if (bus_space_map(iot, iobase, COM_NPORTS8, 0, &comconsioh)) |
1215 | return ENOMEM12; |
1216 | #endif |
1217 | |
1218 | cominit(iot, comconsioh, rate, frequency); |
1219 | |
1220 | cn_tab = &comcons; |
1221 | |
1222 | comconsiot = iot; |
1223 | comconsaddr = iobase; |
1224 | comconscflag = cflag; |
1225 | comconsfreq = frequency; |
1226 | comconsrate = rate; |
1227 | |
1228 | return (0); |
1229 | } |
1230 | |
1231 | int |
1232 | comcngetc(dev_t dev) |
1233 | { |
1234 | int s = splhigh()splraise(0xd); |
1235 | u_char stat, c; |
1236 | |
1237 | /* Block until a character becomes available. */ |
1238 | while (!ISSET(stat = comcn_read_reg(com_lsr), LSR_RXRDY)((stat = comcn_read_reg(5)) & (0x01))) |
1239 | continue; |
1240 | |
1241 | c = comcn_read_reg(com_data0); |
1242 | |
1243 | /* Clear any interrupts generated by this transmission. */ |
1244 | stat = comcn_read_reg(com_iir2); |
Value stored to 'stat' is never read | |
1245 | splx(s)spllower(s); |
1246 | return (c); |
1247 | } |
1248 | |
1249 | /* |
1250 | * Console kernel output character routine. |
1251 | */ |
1252 | void |
1253 | comcnputc(dev_t dev, int c) |
1254 | { |
1255 | int s = spltty()splraise(0x9); |
1256 | int timo; |
1257 | |
1258 | /* Wait for any pending transmission to finish. */ |
1259 | timo = 2000; |
1260 | while (!ISSET(comcn_read_reg(com_lsr), LSR_TXRDY)((comcn_read_reg(5)) & (0x20)) && --timo) |
1261 | delay(1)(*delay_func)(1); |
1262 | |
1263 | comcn_write_reg(com_data0, (u_int8_t)(c & 0xff)); |
1264 | bus_space_barrier(comconsiot, comconsioh, 0, |
1265 | COM_NPORTS8 << comcons_reg_shift, |
1266 | (BUS_SPACE_BARRIER_READ0x01|BUS_SPACE_BARRIER_WRITE0x02)); |
1267 | |
1268 | /* Wait for this transmission to complete. */ |
1269 | timo = 2000; |
1270 | while (!ISSET(comcn_read_reg(com_lsr), LSR_TXRDY)((comcn_read_reg(5)) & (0x20)) && --timo) |
1271 | delay(1)(*delay_func)(1); |
1272 | |
1273 | splx(s)spllower(s); |
1274 | } |
1275 | |
1276 | void |
1277 | comcnpollc(dev_t dev, int on) |
1278 | { |
1279 | } |
1280 | #endif /* COM_CONSOLE */ |
1281 | |
1282 | void com_enable_debugport(struct com_softc *); |
1283 | void com_fifo_probe(struct com_softc *); |
1284 | |
1285 | #ifdef COM_CONSOLE |
1286 | void |
1287 | com_enable_debugport(struct com_softc *sc) |
1288 | { |
1289 | int s; |
1290 | |
1291 | /* Turn on line break interrupt, set carrier. */ |
1292 | s = splhigh()splraise(0xd); |
1293 | SET(sc->sc_mcr, MCR_DTR | MCR_RTS | MCR_IENABLE)((sc->sc_mcr) |= (0x01 | 0x02 | 0x08)); |
1294 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
1295 | |
1296 | splx(s)spllower(s); |
1297 | } |
1298 | #endif /* COM_CONSOLE */ |
1299 | |
1300 | void |
1301 | com_attach_subr(struct com_softc *sc) |
1302 | { |
1303 | int probe = 0; |
1304 | u_int8_t lcr, fifo; |
1305 | u_int32_t cpr; |
1306 | |
1307 | sc->sc_ier = 0; |
1308 | /* disable interrupts */ |
1309 | com_write_reg(sc, com_ier1, sc->sc_ier); |
1310 | |
1311 | #ifdef COM_CONSOLE |
1312 | if (sc->sc_iot == comconsiot && sc->sc_iobase == comconsaddr) { |
1313 | comconsattached = 1; |
1314 | delay(10000)(*delay_func)(10000); /* wait for output to finish */ |
1315 | SET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) |= (0x40)); |
1316 | SET(sc->sc_swflags, COM_SW_SOFTCAR)((sc->sc_swflags) |= (0x01)); |
1317 | } |
1318 | #endif |
1319 | |
1320 | /* |
1321 | * Probe for all known forms of UART. |
1322 | */ |
1323 | lcr = com_read_reg(sc, com_lcr3); |
1324 | com_write_reg(sc, com_lcr3, LCR_EFR0xbf); |
1325 | com_write_reg(sc, com_efr2, 0); |
1326 | com_write_reg(sc, com_lcr3, 0); |
1327 | |
1328 | com_write_reg(sc, com_fifo2, FIFO_ENABLE0x01); |
1329 | delay(100)(*delay_func)(100); |
1330 | |
1331 | /* |
1332 | * Skip specific probes if attachment code knows it already. |
1333 | */ |
1334 | if (sc->sc_uarttype == COM_UART_UNKNOWN0x00) { |
1335 | switch (com_read_reg(sc, com_iir2) >> 6) { |
1336 | case 0: |
1337 | sc->sc_uarttype = COM_UART_164500x02; |
1338 | break; |
1339 | case 2: |
1340 | sc->sc_uarttype = COM_UART_165500x03; |
1341 | break; |
1342 | case 3: |
1343 | sc->sc_uarttype = COM_UART_16550A0x04; |
1344 | break; |
1345 | default: |
1346 | sc->sc_uarttype = COM_UART_UNKNOWN0x00; |
1347 | break; |
1348 | } |
1349 | probe = 1; |
1350 | } |
1351 | |
1352 | /* Probe for ST16650s */ |
1353 | if (probe && sc->sc_uarttype == COM_UART_16550A0x04) { |
1354 | com_write_reg(sc, com_lcr3, lcr | LCR_DLAB0x80); |
1355 | if (com_read_reg(sc, com_efr2) == 0) { |
1356 | com_write_reg(sc, com_efr2, EFR_CTS0x80); |
1357 | if (com_read_reg(sc, com_efr2) != 0) |
1358 | sc->sc_uarttype = COM_UART_ST166500x05; |
1359 | com_write_reg(sc, com_efr2, 0); |
1360 | } else { |
1361 | com_write_reg(sc, com_lcr3, LCR_EFR0xbf); |
1362 | if (com_read_reg(sc, com_efr2) == 0) |
1363 | sc->sc_uarttype = COM_UART_ST16650V20x06; |
1364 | } |
1365 | } |
1366 | |
1367 | #if 0 /* until com works with large FIFOs */ |
1368 | /* Probe for XR16850s */ |
1369 | if (probe && sc->sc_uarttype == COM_UART_ST16650V20x06) { |
1370 | u_int8_t dlbl, dlbh; |
1371 | |
1372 | /* Enable latch access and get the current values. */ |
1373 | com_write_reg(sc, com_lcr3, lcr | LCR_DLAB0x80); |
1374 | dlbl = com_read_reg(sc, com_dlbl0); |
1375 | dlbh = com_read_reg(sc, com_dlbh1); |
1376 | |
1377 | /* Zero out the latch divisors */ |
1378 | com_write_reg(sc, com_dlbl0, 0); |
1379 | com_write_reg(sc, com_dlbh1, 0); |
1380 | |
1381 | if (com_read_reg(sc, com_dlbh1) == 0x10) { |
1382 | sc->sc_uarttype = COM_UART_XR168500x10; |
1383 | sc->sc_uartrev = com_read_reg(sc, com_dlbl0); |
1384 | } |
1385 | |
1386 | /* Reset to original. */ |
1387 | com_write_reg(sc, com_dlbl0, dlbl); |
1388 | com_write_reg(sc, com_dlbh1, dlbh); |
1389 | } |
1390 | #endif |
1391 | |
1392 | /* Probe for TI16750s */ |
1393 | if (probe && sc->sc_uarttype == COM_UART_16550A0x04) { |
1394 | com_write_reg(sc, com_lcr3, lcr | LCR_DLAB0x80); |
1395 | com_write_reg(sc, com_fifo2, |
1396 | FIFO_ENABLE0x01 | FIFO_ENABLE_64BYTE0x20); |
1397 | if ((com_read_reg(sc, com_iir2) >> 5) == 7) { |
1398 | #if 0 |
1399 | com_write_reg(sc, com_lcr3, 0); |
1400 | if ((com_read_reg(sc, com_iir2) >> 5) == 6) |
1401 | #endif |
1402 | sc->sc_uarttype = COM_UART_TI167500x07; |
1403 | } |
1404 | com_write_reg(sc, com_fifo2, FIFO_ENABLE0x01); |
1405 | } |
1406 | |
1407 | /* Reset the LCR (latch access is probably enabled). */ |
1408 | com_write_reg(sc, com_lcr3, lcr); |
1409 | |
1410 | /* Probe for 8250 */ |
1411 | if (probe && sc->sc_uarttype == COM_UART_164500x02) { |
1412 | u_int8_t scr0, scr1, scr2; |
1413 | |
1414 | scr0 = com_read_reg(sc, com_scratch7); |
1415 | com_write_reg(sc, com_scratch7, 0xa5); |
1416 | scr1 = com_read_reg(sc, com_scratch7); |
1417 | com_write_reg(sc, com_scratch7, 0x5a); |
1418 | scr2 = com_read_reg(sc, com_scratch7); |
1419 | com_write_reg(sc, com_scratch7, scr0); |
1420 | |
1421 | if ((scr1 != 0xa5) || (scr2 != 0x5a)) |
1422 | sc->sc_uarttype = COM_UART_82500x01; |
1423 | } |
1424 | |
1425 | /* |
1426 | * Print UART type and initialize ourself. |
1427 | */ |
1428 | switch (sc->sc_uarttype) { |
1429 | case COM_UART_UNKNOWN0x00: |
1430 | printf(": unknown uart\n"); |
1431 | break; |
1432 | case COM_UART_82500x01: |
1433 | printf(": ns8250, no fifo\n"); |
1434 | break; |
1435 | case COM_UART_164500x02: |
1436 | printf(": ns16450, no fifo\n"); |
1437 | break; |
1438 | case COM_UART_165500x03: |
1439 | printf(": ns16550, no working fifo\n"); |
1440 | break; |
1441 | case COM_UART_16550A0x04: |
1442 | if (sc->sc_fifolen == 0) |
1443 | sc->sc_fifolen = 16; |
1444 | printf(": ns16550a, %d byte fifo\n", sc->sc_fifolen); |
1445 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1446 | break; |
1447 | case COM_UART_ST166500x05: |
1448 | printf(": st16650, no working fifo\n"); |
1449 | break; |
1450 | case COM_UART_ST16650V20x06: |
1451 | if (sc->sc_fifolen == 0) |
1452 | sc->sc_fifolen = 32; |
1453 | printf(": st16650, %d byte fifo\n", sc->sc_fifolen); |
1454 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1455 | break; |
1456 | case COM_UART_ST16C6540x08: |
1457 | printf(": st16c654, 64 byte fifo\n"); |
1458 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1459 | sc->sc_fifolen = 64; |
1460 | break; |
1461 | case COM_UART_TI167500x07: |
1462 | printf(": ti16750, 64 byte fifo\n"); |
1463 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1464 | sc->sc_fifolen = 64; |
1465 | break; |
1466 | #if 0 |
1467 | case COM_UART_XR168500x10: |
1468 | printf(": xr16850 (rev %d), 128 byte fifo\n", sc->sc_uartrev); |
1469 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1470 | sc->sc_fifolen = 128; |
1471 | break; |
1472 | #ifdef COM_UART_OX16C9500x11 |
1473 | case COM_UART_OX16C9500x11: |
1474 | printf(": ox16c950 (rev %d), 128 byte fifo\n", sc->sc_uartrev); |
1475 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1476 | sc->sc_fifolen = 128; |
1477 | break; |
1478 | #endif |
1479 | #endif |
1480 | case COM_UART_XR17V35X0x12: |
1481 | printf(": xr17v35x, 256 byte fifo\n"); |
1482 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1483 | sc->sc_fifolen = 256; |
1484 | break; |
1485 | case COM_UART_DW_APB0x13: |
1486 | printf(": dw16550"); |
1487 | SET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) |= (0x02)); |
1488 | cpr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, com_cpr << 2)((sc->sc_iot)->read_4((sc->sc_ioh), (61 << 2)) ); |
1489 | sc->sc_fifolen = CPR_FIFO_MODE(cpr)(((cpr) >> 16) & 0xff) * 16; |
1490 | if (sc->sc_fifolen) { |
1491 | printf(", %d byte fifo\n", sc->sc_fifolen); |
1492 | } else { |
1493 | printf("\n"); |
1494 | /* |
1495 | * The DW-APB configuration on the Allwinner H6 SoC |
1496 | * does not provide the CPR register and will be |
1497 | * detected as having no FIFO. But it does have a |
1498 | * 256-byte FIFO and with the FIFO disabled the |
1499 | * LSR_RXRDY bit remains set even if the input |
1500 | * buffer is empty. As a workaround, treat as a |
1501 | * 1-byte FIFO. |
1502 | */ |
1503 | sc->sc_fifolen = 1; |
1504 | } |
1505 | break; |
1506 | default: |
1507 | panic("comattach: bad fifo type"); |
1508 | } |
1509 | |
1510 | #ifdef COM_CONSOLE |
1511 | if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) |
1512 | #endif |
1513 | if (sc->sc_fifolen < 256) |
1514 | com_fifo_probe(sc); |
1515 | |
1516 | if (sc->sc_fifolen == 0) { |
1517 | CLR(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) &= ~(0x02)); |
1518 | sc->sc_fifolen = 1; |
1519 | } |
1520 | |
1521 | /* clear and disable fifo */ |
1522 | /* DW-APB UART cannot turn off FIFO here (ddb will not work) */ |
1523 | fifo = (sc->sc_uarttype == COM_UART_DW_APB0x13) ? |
1524 | (FIFO_ENABLE0x01 | FIFO_TRIGGER_10x00) : 0; |
1525 | com_write_reg(sc, com_fifo2, fifo | FIFO_RCV_RST0x02 | FIFO_XMT_RST0x04); |
1526 | if (ISSET(com_read_reg(sc, com_lsr), LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01))) |
1527 | (void)com_read_reg(sc, com_data0); |
1528 | com_write_reg(sc, com_fifo2, fifo); |
1529 | |
1530 | sc->sc_mcr = 0; |
1531 | com_write_reg(sc, com_mcr4, sc->sc_mcr); |
1532 | |
1533 | #ifdef COM_CONSOLE |
1534 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) { |
1535 | int maj; |
1536 | |
1537 | /* locate the major number */ |
1538 | for (maj = 0; maj < nchrdev; maj++) |
1539 | if (cdevsw[maj].d_open == comopen) |
1540 | break; |
1541 | |
1542 | KASSERT(maj < nchrdev)((maj < nchrdev) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/ic/com.c" , 1542, "maj < nchrdev")); |
1543 | cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit)((dev_t)((((maj) & 0xff) << 8) | ((sc->sc_dev.dv_unit ) & 0xff) | (((sc->sc_dev.dv_unit) & 0xffff00) << 8))); |
1544 | |
1545 | printf("%s: console\n", sc->sc_dev.dv_xname); |
1546 | } |
1547 | #endif |
1548 | |
1549 | timeout_set(&sc->sc_diag_tmo, comdiag, sc); |
1550 | timeout_set(&sc->sc_dtr_tmo, com_raisedtr, sc); |
1551 | sc->sc_si = softintr_establish(IPL_TTY0x9, comsoft, sc); |
1552 | if (sc->sc_si == NULL((void *)0)) |
1553 | panic("%s: can't establish soft interrupt", |
1554 | sc->sc_dev.dv_xname); |
1555 | |
1556 | /* |
1557 | * If there are no enable/disable functions, assume the device |
1558 | * is always enabled. |
1559 | */ |
1560 | if (!sc->enable) |
1561 | sc->enabled = 1; |
1562 | |
1563 | #ifdef COM_CONSOLE |
1564 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)((sc->sc_hwflags) & (0x40))) |
1565 | com_enable_debugport(sc); |
1566 | #endif |
1567 | } |
1568 | |
1569 | void |
1570 | com_fifo_probe(struct com_softc *sc) |
1571 | { |
1572 | u_int8_t fifo, ier; |
1573 | int timo, len; |
1574 | |
1575 | if (!ISSET(sc->sc_hwflags, COM_HW_FIFO)((sc->sc_hwflags) & (0x02))) |
1576 | return; |
1577 | |
1578 | ier = 0; |
1579 | com_write_reg(sc, com_ier1, ier); |
1580 | com_write_reg(sc, com_lcr3, LCR_DLAB0x80); |
1581 | com_write_reg(sc, com_dlbl0, 3); |
1582 | com_write_reg(sc, com_dlbh1, 0); |
1583 | com_write_reg(sc, com_lcr3, LCR_PNONE0x00 | LCR_8BITS0x03); |
1584 | com_write_reg(sc, com_mcr4, MCR_LOOPBACK0x10); |
1585 | |
1586 | fifo = FIFO_ENABLE0x01 | FIFO_RCV_RST0x02 | FIFO_XMT_RST0x04; |
1587 | if (sc->sc_uarttype == COM_UART_TI167500x07) |
1588 | fifo |= FIFO_ENABLE_64BYTE0x20; |
1589 | |
1590 | com_write_reg(sc, com_fifo2, fifo); |
1591 | |
1592 | for (len = 0; len < 256; len++) { |
1593 | com_write_reg(sc, com_data0, (len + 1)); |
1594 | timo = 2000; |
1595 | while (!ISSET(com_read_reg(sc, com_lsr),((com_read_reg(sc, 5)) & (0x20)) |
1596 | LSR_TXRDY)((com_read_reg(sc, 5)) & (0x20)) && --timo) |
1597 | delay(1)(*delay_func)(1); |
1598 | if (!timo) |
1599 | break; |
1600 | } |
1601 | |
1602 | delay(100)(*delay_func)(100); |
1603 | |
1604 | for (len = 0; len < 256; len++) { |
1605 | timo = 2000; |
1606 | while (!ISSET(com_read_reg(sc, com_lsr),((com_read_reg(sc, 5)) & (0x01)) |
1607 | LSR_RXRDY)((com_read_reg(sc, 5)) & (0x01)) && --timo) |
1608 | delay(1)(*delay_func)(1); |
1609 | if (!timo || com_read_reg(sc, com_data0) != (len + 1)) |
1610 | break; |
1611 | } |
1612 | |
1613 | /* For safety, always use the smaller value. */ |
1614 | if (sc->sc_fifolen > len) { |
1615 | printf("%s: probed fifo depth: %d bytes\n", |
1616 | sc->sc_dev.dv_xname, len); |
1617 | sc->sc_fifolen = len; |
1618 | } |
1619 | } |
1620 | |
1621 | uint8_t |
1622 | com_read_reg(struct com_softc *sc, bus_size_t reg) |
1623 | { |
1624 | reg <<= sc->sc_reg_shift; |
1625 | |
1626 | if (sc->sc_reg_width == 4) |
1627 | return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg)((sc->sc_iot)->read_4((sc->sc_ioh), (reg))); |
1628 | else |
1629 | return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)((sc->sc_iot)->read_1((sc->sc_ioh), (reg))); |
1630 | } |
1631 | |
1632 | void |
1633 | com_write_reg(struct com_softc *sc, bus_size_t reg, uint8_t value) |
1634 | { |
1635 | reg <<= sc->sc_reg_shift; |
1636 | |
1637 | if (sc->sc_reg_width == 4) |
1638 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, value)((sc->sc_iot)->write_4((sc->sc_ioh), (reg), (value)) ); |
1639 | else |
1640 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, value)((sc->sc_iot)->write_1((sc->sc_ioh), (reg), (value)) ); |
1641 | } |
1642 | |
1643 | #ifdef COM_CONSOLE |
1644 | |
1645 | u_char comcons_reg_width; |
1646 | u_char comcons_reg_shift; |
1647 | |
1648 | uint8_t |
1649 | comcn_read_reg(bus_size_t reg) |
1650 | { |
1651 | reg <<= comcons_reg_shift; |
1652 | |
1653 | if (comcons_reg_width == 4) |
1654 | return bus_space_read_4(comconsiot, comconsioh, reg)((comconsiot)->read_4((comconsioh), (reg))); |
1655 | else |
1656 | return bus_space_read_1(comconsiot, comconsioh, reg)((comconsiot)->read_1((comconsioh), (reg))); |
1657 | } |
1658 | |
1659 | void |
1660 | comcn_write_reg(bus_size_t reg, uint8_t value) |
1661 | { |
1662 | reg <<= comcons_reg_shift; |
1663 | |
1664 | if (comcons_reg_width == 4) |
1665 | bus_space_write_4(comconsiot, comconsioh, reg, value)((comconsiot)->write_4((comconsioh), (reg), (value))); |
1666 | else |
1667 | bus_space_write_1(comconsiot, comconsioh, reg, value)((comconsiot)->write_1((comconsioh), (reg), (value))); |
1668 | } |
1669 | |
1670 | #endif |