File: | dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c |
Warning: | line 451, column 3 The left operand of '+' is a garbage value |
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1 | /* | |||
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | */ | |||
23 | ||||
24 | #define SWSMU_CODE_LAYER_L2 | |||
25 | ||||
26 | #include <linux/firmware.h> | |||
27 | #include <linux/pci.h> | |||
28 | #include <linux/i2c.h> | |||
29 | #include "amdgpu.h" | |||
30 | #include "amdgpu_dpm.h" | |||
31 | #include "amdgpu_smu.h" | |||
32 | #include "atomfirmware.h" | |||
33 | #include "amdgpu_atomfirmware.h" | |||
34 | #include "amdgpu_atombios.h" | |||
35 | #include "smu_v11_0.h" | |||
36 | #include "smu11_driver_if_sienna_cichlid.h" | |||
37 | #include "soc15_common.h" | |||
38 | #include "atom.h" | |||
39 | #include "sienna_cichlid_ppt.h" | |||
40 | #include "smu_v11_0_7_pptable.h" | |||
41 | #include "smu_v11_0_7_ppsmc.h" | |||
42 | #include "nbio/nbio_2_3_offset.h" | |||
43 | #include "nbio/nbio_2_3_sh_mask.h" | |||
44 | #include "thm/thm_11_0_2_offset.h" | |||
45 | #include "thm/thm_11_0_2_sh_mask.h" | |||
46 | #include "mp/mp_11_0_offset.h" | |||
47 | #include "mp/mp_11_0_sh_mask.h" | |||
48 | ||||
49 | #include "asic_reg/mp/mp_11_0_sh_mask.h" | |||
50 | #include "amdgpu_ras.h" | |||
51 | #include "smu_cmn.h" | |||
52 | ||||
53 | /* | |||
54 | * DO NOT use these for err/warn/info/debug messages. | |||
55 | * Use dev_err, dev_warn, dev_info and dev_dbg instead. | |||
56 | * They are more MGPU friendly. | |||
57 | */ | |||
58 | #undef pr_err | |||
59 | #undef pr_warn | |||
60 | #undef pr_info | |||
61 | #undef pr_debug | |||
62 | ||||
63 | #define FEATURE_MASK(feature)(1ULL << feature) (1ULL << feature) | |||
64 | #define SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 1) | (1ULL << 3) | (1ULL << 7) | (1ULL << 5) | (1ULL << 4) | ( 1ULL << 8) | (1ULL << 6)) ( \ | |||
65 | FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)(1ULL << 0) | \ | |||
66 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)(1ULL << 1) | \ | |||
67 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)(1ULL << 3) | \ | |||
68 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)(1ULL << 7) | \ | |||
69 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)(1ULL << 5) | \ | |||
70 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)(1ULL << 4) | \ | |||
71 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)(1ULL << 8) | \ | |||
72 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)(1ULL << 6)) | |||
73 | ||||
74 | #define SMU_11_0_7_GFX_BUSY_THRESHOLD15 15 | |||
75 | ||||
76 | #define GET_PPTABLE_MEMBER(field, member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*member) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_beige_goby_t, field )); else (*member) = (smu->smu_table.driver_pptable + __builtin_offsetof (PPTable_t, field));} while(0) do {\ | |||
77 | if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)))\ | |||
78 | (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field)__builtin_offsetof(PPTable_beige_goby_t, field));\ | |||
79 | else\ | |||
80 | (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field)__builtin_offsetof(PPTable_t, field));\ | |||
81 | } while(0) | |||
82 | ||||
83 | /* STB FIFO depth is in 64bit units */ | |||
84 | #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES8 8 | |||
85 | ||||
86 | /* | |||
87 | * SMU support ECCTABLE since version 58.70.0, | |||
88 | * use this to check whether ECCTABLE feature is supported. | |||
89 | */ | |||
90 | #define SUPPORT_ECCTABLE_SMU_VERSION0x003a4600 0x003a4600 | |||
91 | ||||
92 | static int get_table_size(struct smu_context *smu) | |||
93 | { | |||
94 | if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13))) | |||
95 | return sizeof(PPTable_beige_goby_t); | |||
96 | else | |||
97 | return sizeof(PPTable_t); | |||
98 | } | |||
99 | ||||
100 | static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { | |||
101 | MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1)[SMU_MSG_TestMessage] = {1, (0x1), (1)}, | |||
102 | MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1)[SMU_MSG_GetSmuVersion] = {1, (0x2), (1)}, | |||
103 | MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1)[SMU_MSG_GetDriverIfVersion] = {1, (0x3), (1)}, | |||
104 | MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0)[SMU_MSG_SetAllowedFeaturesMaskLow] = {1, (0x4), (0)}, | |||
105 | MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0)[SMU_MSG_SetAllowedFeaturesMaskHigh] = {1, (0x5), (0)}, | |||
106 | MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0)[SMU_MSG_EnableAllSmuFeatures] = {1, (0x6), (0)}, | |||
107 | MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0)[SMU_MSG_DisableAllSmuFeatures] = {1, (0x7), (0)}, | |||
108 | MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1)[SMU_MSG_EnableSmuFeaturesLow] = {1, (0x8), (1)}, | |||
109 | MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1)[SMU_MSG_EnableSmuFeaturesHigh] = {1, (0x9), (1)}, | |||
110 | MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1)[SMU_MSG_DisableSmuFeaturesLow] = {1, (0xA), (1)}, | |||
111 | MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1)[SMU_MSG_DisableSmuFeaturesHigh] = {1, (0xB), (1)}, | |||
112 | MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1)[SMU_MSG_GetEnabledSmuFeaturesLow] = {1, (0xC), (1)}, | |||
113 | MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1)[SMU_MSG_GetEnabledSmuFeaturesHigh] = {1, (0xD), (1)}, | |||
114 | MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1)[SMU_MSG_SetWorkloadMask] = {1, (0x22), (1)}, | |||
115 | MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0)[SMU_MSG_SetPptLimit] = {1, (0x32), (0)}, | |||
116 | MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1)[SMU_MSG_SetDriverDramAddrHigh] = {1, (0xE), (1)}, | |||
117 | MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1)[SMU_MSG_SetDriverDramAddrLow] = {1, (0xF), (1)}, | |||
118 | MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0)[SMU_MSG_SetToolsDramAddrHigh] = {1, (0x10), (0)}, | |||
119 | MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0)[SMU_MSG_SetToolsDramAddrLow] = {1, (0x11), (0)}, | |||
120 | MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1)[SMU_MSG_TransferTableSmu2Dram] = {1, (0x12), (1)}, | |||
121 | MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0)[SMU_MSG_TransferTableDram2Smu] = {1, (0x13), (0)}, | |||
122 | MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0)[SMU_MSG_UseDefaultPPTable] = {1, (0x14), (0)}, | |||
123 | MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0)[SMU_MSG_RunDcBtc] = {1, (0x36), (0)}, | |||
124 | MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0)[SMU_MSG_EnterBaco] = {1, (0x15), (0)}, | |||
125 | MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1)[SMU_MSG_SetSoftMinByFreq] = {1, (0x19), (1)}, | |||
126 | MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1)[SMU_MSG_SetSoftMaxByFreq] = {1, (0x1A), (1)}, | |||
127 | MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1)[SMU_MSG_SetHardMinByFreq] = {1, (0x1B), (1)}, | |||
128 | MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0)[SMU_MSG_SetHardMaxByFreq] = {1, (0x1C), (0)}, | |||
129 | MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1)[SMU_MSG_GetMinDpmFreq] = {1, (0x1D), (1)}, | |||
130 | MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1)[SMU_MSG_GetMaxDpmFreq] = {1, (0x1E), (1)}, | |||
131 | MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1)[SMU_MSG_GetDpmFreqByIndex] = {1, (0x1F), (1)}, | |||
132 | MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0)[SMU_MSG_SetGeminiMode] = {1, (0x3B), (0)}, | |||
133 | MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0)[SMU_MSG_SetGeminiApertureHigh] = {1, (0x3C), (0)}, | |||
134 | MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0)[SMU_MSG_SetGeminiApertureLow] = {1, (0x3D), (0)}, | |||
135 | MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0)[SMU_MSG_OverridePcieParameters] = {1, (0x20), (0)}, | |||
136 | MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0)[SMU_MSG_ReenableAcDcInterrupt] = {1, (0x34), (0)}, | |||
137 | MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0)[SMU_MSG_NotifyPowerSource] = {1, (0x35), (0)}, | |||
138 | MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0)[SMU_MSG_SetUclkFastSwitch] = {1, (0x23), (0)}, | |||
139 | MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0)[SMU_MSG_SetVideoFps] = {1, (0x25), (0)}, | |||
140 | MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1)[SMU_MSG_PrepareMp1ForUnload] = {1, (0x2E), (1)}, | |||
141 | MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0)[SMU_MSG_AllowGfxOff] = {1, (0x28), (0)}, | |||
142 | MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0)[SMU_MSG_DisallowGfxOff] = {1, (0x29), (0)}, | |||
143 | MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0)[SMU_MSG_GetPptLimit] = {1, (0x33), (0)}, | |||
144 | MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1)[SMU_MSG_GetDcModeMaxDpmFreq] = {1, (0x26), (1)}, | |||
145 | MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0)[SMU_MSG_ExitBaco] = {1, (0x16), (0)}, | |||
146 | MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0)[SMU_MSG_PowerUpVcn] = {1, (0x2A), (0)}, | |||
147 | MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0)[SMU_MSG_PowerDownVcn] = {1, (0x2B), (0)}, | |||
148 | MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0)[SMU_MSG_PowerUpJpeg] = {1, (0x2C), (0)}, | |||
149 | MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0)[SMU_MSG_PowerDownJpeg] = {1, (0x2D), (0)}, | |||
150 | MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0)[SMU_MSG_BacoAudioD3PME] = {1, (0x18), (0)}, | |||
151 | MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0)[SMU_MSG_ArmD3] = {1, (0x17), (0)}, | |||
152 | MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0)[SMU_MSG_Mode1Reset] = {1, (0x30), (0)}, | |||
153 | MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0)[SMU_MSG_SetMGpuFanBoostLimitRpm] = {1, (0x43), (0)}, | |||
154 | MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0)[SMU_MSG_SetGpoFeaturePMask] = {1, (0x45), (0)}, | |||
155 | MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0)[SMU_MSG_DisallowGpo] = {1, (0x56), (0)}, | |||
156 | MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0)[SMU_MSG_Enable2ndUSB20Port] = {1, (0x57), (0)}, | |||
157 | MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0)[SMU_MSG_DriverMode2Reset] = {1, (0x5D), (0)}, | |||
158 | }; | |||
159 | ||||
160 | static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { | |||
161 | CLK_MAP(GFXCLK, PPCLK_GFXCLK)[SMU_GFXCLK] = {1, (PPCLK_GFXCLK)}, | |||
162 | CLK_MAP(SCLK, PPCLK_GFXCLK)[SMU_SCLK] = {1, (PPCLK_GFXCLK)}, | |||
163 | CLK_MAP(SOCCLK, PPCLK_SOCCLK)[SMU_SOCCLK] = {1, (PPCLK_SOCCLK)}, | |||
164 | CLK_MAP(FCLK, PPCLK_FCLK)[SMU_FCLK] = {1, (PPCLK_FCLK)}, | |||
165 | CLK_MAP(UCLK, PPCLK_UCLK)[SMU_UCLK] = {1, (PPCLK_UCLK)}, | |||
166 | CLK_MAP(MCLK, PPCLK_UCLK)[SMU_MCLK] = {1, (PPCLK_UCLK)}, | |||
167 | CLK_MAP(DCLK, PPCLK_DCLK_0)[SMU_DCLK] = {1, (PPCLK_DCLK_0)}, | |||
168 | CLK_MAP(DCLK1, PPCLK_DCLK_1)[SMU_DCLK1] = {1, (PPCLK_DCLK_1)}, | |||
169 | CLK_MAP(VCLK, PPCLK_VCLK_0)[SMU_VCLK] = {1, (PPCLK_VCLK_0)}, | |||
170 | CLK_MAP(VCLK1, PPCLK_VCLK_1)[SMU_VCLK1] = {1, (PPCLK_VCLK_1)}, | |||
171 | CLK_MAP(DCEFCLK, PPCLK_DCEFCLK)[SMU_DCEFCLK] = {1, (PPCLK_DCEFCLK)}, | |||
172 | CLK_MAP(DISPCLK, PPCLK_DISPCLK)[SMU_DISPCLK] = {1, (PPCLK_DISPCLK)}, | |||
173 | CLK_MAP(PIXCLK, PPCLK_PIXCLK)[SMU_PIXCLK] = {1, (PPCLK_PIXCLK)}, | |||
174 | CLK_MAP(PHYCLK, PPCLK_PHYCLK)[SMU_PHYCLK] = {1, (PPCLK_PHYCLK)}, | |||
175 | }; | |||
176 | ||||
177 | static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { | |||
178 | FEA_MAP(DPM_PREFETCHER)[SMU_FEATURE_DPM_PREFETCHER_BIT] = {1, 0}, | |||
179 | FEA_MAP(DPM_GFXCLK)[SMU_FEATURE_DPM_GFXCLK_BIT] = {1, 1}, | |||
180 | FEA_MAP(DPM_GFX_GPO)[SMU_FEATURE_DPM_GFX_GPO_BIT] = {1, 2}, | |||
181 | FEA_MAP(DPM_UCLK)[SMU_FEATURE_DPM_UCLK_BIT] = {1, 3}, | |||
182 | FEA_MAP(DPM_FCLK)[SMU_FEATURE_DPM_FCLK_BIT] = {1, 4}, | |||
183 | FEA_MAP(DPM_SOCCLK)[SMU_FEATURE_DPM_SOCCLK_BIT] = {1, 5}, | |||
184 | FEA_MAP(DPM_MP0CLK)[SMU_FEATURE_DPM_MP0CLK_BIT] = {1, 6}, | |||
185 | FEA_MAP(DPM_LINK)[SMU_FEATURE_DPM_LINK_BIT] = {1, 7}, | |||
186 | FEA_MAP(DPM_DCEFCLK)[SMU_FEATURE_DPM_DCEFCLK_BIT] = {1, 8}, | |||
187 | FEA_MAP(DPM_XGMI)[SMU_FEATURE_DPM_XGMI_BIT] = {1, 9}, | |||
188 | FEA_MAP(MEM_VDDCI_SCALING)[SMU_FEATURE_MEM_VDDCI_SCALING_BIT] = {1, 10}, | |||
189 | FEA_MAP(MEM_MVDD_SCALING)[SMU_FEATURE_MEM_MVDD_SCALING_BIT] = {1, 11}, | |||
190 | FEA_MAP(DS_GFXCLK)[SMU_FEATURE_DS_GFXCLK_BIT] = {1, 12}, | |||
191 | FEA_MAP(DS_SOCCLK)[SMU_FEATURE_DS_SOCCLK_BIT] = {1, 13}, | |||
192 | FEA_MAP(DS_FCLK)[SMU_FEATURE_DS_FCLK_BIT] = {1, 14}, | |||
193 | FEA_MAP(DS_LCLK)[SMU_FEATURE_DS_LCLK_BIT] = {1, 15}, | |||
194 | FEA_MAP(DS_DCEFCLK)[SMU_FEATURE_DS_DCEFCLK_BIT] = {1, 16}, | |||
195 | FEA_MAP(DS_UCLK)[SMU_FEATURE_DS_UCLK_BIT] = {1, 17}, | |||
196 | FEA_MAP(GFX_ULV)[SMU_FEATURE_GFX_ULV_BIT] = {1, 18}, | |||
197 | FEA_MAP(FW_DSTATE)[SMU_FEATURE_FW_DSTATE_BIT] = {1, 19}, | |||
198 | FEA_MAP(GFXOFF)[SMU_FEATURE_GFXOFF_BIT] = {1, 20}, | |||
199 | FEA_MAP(BACO)[SMU_FEATURE_BACO_BIT] = {1, 21}, | |||
200 | FEA_MAP(MM_DPM_PG)[SMU_FEATURE_MM_DPM_PG_BIT] = {1, 22}, | |||
201 | FEA_MAP(RSMU_SMN_CG)[SMU_FEATURE_RSMU_SMN_CG_BIT] = {1, 44}, | |||
202 | FEA_MAP(PPT)[SMU_FEATURE_PPT_BIT] = {1, 24}, | |||
203 | FEA_MAP(TDC)[SMU_FEATURE_TDC_BIT] = {1, 25}, | |||
204 | FEA_MAP(APCC_PLUS)[SMU_FEATURE_APCC_PLUS_BIT] = {1, 26}, | |||
205 | FEA_MAP(GTHR)[SMU_FEATURE_GTHR_BIT] = {1, 27}, | |||
206 | FEA_MAP(ACDC)[SMU_FEATURE_ACDC_BIT] = {1, 28}, | |||
207 | FEA_MAP(VR0HOT)[SMU_FEATURE_VR0HOT_BIT] = {1, 29}, | |||
208 | FEA_MAP(VR1HOT)[SMU_FEATURE_VR1HOT_BIT] = {1, 30}, | |||
209 | FEA_MAP(FW_CTF)[SMU_FEATURE_FW_CTF_BIT] = {1, 31}, | |||
210 | FEA_MAP(FAN_CONTROL)[SMU_FEATURE_FAN_CONTROL_BIT] = {1, 32}, | |||
211 | FEA_MAP(THERMAL)[SMU_FEATURE_THERMAL_BIT] = {1, 33}, | |||
212 | FEA_MAP(GFX_DCS)[SMU_FEATURE_GFX_DCS_BIT] = {1, 34}, | |||
213 | FEA_MAP(RM)[SMU_FEATURE_RM_BIT] = {1, 35}, | |||
214 | FEA_MAP(LED_DISPLAY)[SMU_FEATURE_LED_DISPLAY_BIT] = {1, 36}, | |||
215 | FEA_MAP(GFX_SS)[SMU_FEATURE_GFX_SS_BIT] = {1, 37}, | |||
216 | FEA_MAP(OUT_OF_BAND_MONITOR)[SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT] = {1, 38}, | |||
217 | FEA_MAP(TEMP_DEPENDENT_VMIN)[SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT] = {1, 39}, | |||
218 | FEA_MAP(MMHUB_PG)[SMU_FEATURE_MMHUB_PG_BIT] = {1, 40}, | |||
219 | FEA_MAP(ATHUB_PG)[SMU_FEATURE_ATHUB_PG_BIT] = {1, 41}, | |||
220 | FEA_MAP(APCC_DFLL)[SMU_FEATURE_APCC_DFLL_BIT] = {1, 42}, | |||
221 | }; | |||
222 | ||||
223 | static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { | |||
224 | TAB_MAP(PPTABLE)[SMU_TABLE_PPTABLE] = {1, 0}, | |||
225 | TAB_MAP(WATERMARKS)[SMU_TABLE_WATERMARKS] = {1, 1}, | |||
226 | TAB_MAP(AVFS_PSM_DEBUG)[SMU_TABLE_AVFS_PSM_DEBUG] = {1, 2}, | |||
227 | TAB_MAP(AVFS_FUSE_OVERRIDE)[SMU_TABLE_AVFS_FUSE_OVERRIDE] = {1, 3}, | |||
228 | TAB_MAP(PMSTATUSLOG)[SMU_TABLE_PMSTATUSLOG] = {1, 4}, | |||
229 | TAB_MAP(SMU_METRICS)[SMU_TABLE_SMU_METRICS] = {1, 5}, | |||
230 | TAB_MAP(DRIVER_SMU_CONFIG)[SMU_TABLE_DRIVER_SMU_CONFIG] = {1, 6}, | |||
231 | TAB_MAP(ACTIVITY_MONITOR_COEFF)[SMU_TABLE_ACTIVITY_MONITOR_COEFF] = {1, 7}, | |||
232 | TAB_MAP(OVERDRIVE)[SMU_TABLE_OVERDRIVE] = {1, 8}, | |||
233 | TAB_MAP(I2C_COMMANDS)[SMU_TABLE_I2C_COMMANDS] = {1, 9}, | |||
234 | TAB_MAP(PACE)[SMU_TABLE_PACE] = {1, 10}, | |||
235 | TAB_MAP(ECCINFO)[SMU_TABLE_ECCINFO] = {1, 11}, | |||
236 | }; | |||
237 | ||||
238 | static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { | |||
239 | PWR_MAP(AC)[SMU_POWER_SOURCE_AC] = {1, POWER_SOURCE_AC}, | |||
240 | PWR_MAP(DC)[SMU_POWER_SOURCE_DC] = {1, POWER_SOURCE_DC}, | |||
241 | }; | |||
242 | ||||
243 | static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { | |||
244 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT)[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = {1, (0)}, | |||
245 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT)[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = {1, (1)}, | |||
246 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT)[PP_SMC_POWER_PROFILE_POWERSAVING] = {1, (2)}, | |||
247 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT)[PP_SMC_POWER_PROFILE_VIDEO] = {1, (3)}, | |||
248 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT)[PP_SMC_POWER_PROFILE_VR] = {1, (4)}, | |||
249 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT)[PP_SMC_POWER_PROFILE_COMPUTE] = {1, (5)}, | |||
250 | WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT)[PP_SMC_POWER_PROFILE_CUSTOM] = {1, (6)}, | |||
251 | }; | |||
252 | ||||
253 | static const uint8_t sienna_cichlid_throttler_map[] = { | |||
254 | [THROTTLER_TEMP_EDGE_BIT1] = (SMU_THROTTLER_TEMP_EDGE_BIT35), | |||
255 | [THROTTLER_TEMP_HOTSPOT_BIT2] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT36), | |||
256 | [THROTTLER_TEMP_MEM_BIT3] = (SMU_THROTTLER_TEMP_MEM_BIT34), | |||
257 | [THROTTLER_TEMP_VR_GFX_BIT4] = (SMU_THROTTLER_TEMP_VR_GFX_BIT38), | |||
258 | [THROTTLER_TEMP_VR_MEM0_BIT5] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT40), | |||
259 | [THROTTLER_TEMP_VR_MEM1_BIT6] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT41), | |||
260 | [THROTTLER_TEMP_VR_SOC_BIT7] = (SMU_THROTTLER_TEMP_VR_SOC_BIT39), | |||
261 | [THROTTLER_TEMP_LIQUID0_BIT8] = (SMU_THROTTLER_TEMP_LIQUID0_BIT42), | |||
262 | [THROTTLER_TEMP_LIQUID1_BIT9] = (SMU_THROTTLER_TEMP_LIQUID1_BIT43), | |||
263 | [THROTTLER_TDC_GFX_BIT11] = (SMU_THROTTLER_TDC_GFX_BIT16), | |||
264 | [THROTTLER_TDC_SOC_BIT12] = (SMU_THROTTLER_TDC_SOC_BIT17), | |||
265 | [THROTTLER_PPT0_BIT13] = (SMU_THROTTLER_PPT0_BIT0), | |||
266 | [THROTTLER_PPT1_BIT14] = (SMU_THROTTLER_PPT1_BIT1), | |||
267 | [THROTTLER_PPT2_BIT15] = (SMU_THROTTLER_PPT2_BIT2), | |||
268 | [THROTTLER_PPT3_BIT16] = (SMU_THROTTLER_PPT3_BIT3), | |||
269 | [THROTTLER_FIT_BIT17] = (SMU_THROTTLER_FIT_BIT57), | |||
270 | [THROTTLER_PPM_BIT18] = (SMU_THROTTLER_PPM_BIT56), | |||
271 | [THROTTLER_APCC_BIT19] = (SMU_THROTTLER_APCC_BIT23), | |||
272 | }; | |||
273 | ||||
274 | static int | |||
275 | sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, | |||
276 | uint32_t *feature_mask, uint32_t num) | |||
277 | { | |||
278 | struct amdgpu_device *adev = smu->adev; | |||
279 | ||||
280 | if (num > 2) | |||
281 | return -EINVAL22; | |||
282 | ||||
283 | memset(feature_mask, 0, sizeof(uint32_t) * num)__builtin_memset((feature_mask), (0), (sizeof(uint32_t) * num )); | |||
284 | ||||
285 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)(1ULL << 0) | |||
286 | | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)(1ULL << 4) | |||
287 | | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)(1ULL << 6) | |||
288 | | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)(1ULL << 13) | |||
289 | | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)(1ULL << 16) | |||
290 | | FEATURE_MASK(FEATURE_DS_FCLK_BIT)(1ULL << 14) | |||
291 | | FEATURE_MASK(FEATURE_DS_UCLK_BIT)(1ULL << 17) | |||
292 | | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)(1ULL << 19) | |||
293 | | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)(1ULL << 45) | |||
294 | | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)(1ULL << 44) | |||
295 | | FEATURE_MASK(FEATURE_GFX_SS_BIT)(1ULL << 37) | |||
296 | | FEATURE_MASK(FEATURE_VR0HOT_BIT)(1ULL << 29) | |||
297 | | FEATURE_MASK(FEATURE_PPT_BIT)(1ULL << 24) | |||
298 | | FEATURE_MASK(FEATURE_TDC_BIT)(1ULL << 25) | |||
299 | | FEATURE_MASK(FEATURE_BACO_BIT)(1ULL << 21) | |||
300 | | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)(1ULL << 42) | |||
301 | | FEATURE_MASK(FEATURE_FW_CTF_BIT)(1ULL << 31) | |||
302 | | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)(1ULL << 32) | |||
303 | | FEATURE_MASK(FEATURE_THERMAL_BIT)(1ULL << 33) | |||
304 | | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)(1ULL << 38); | |||
305 | ||||
306 | if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { | |||
307 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)(1ULL << 1); | |||
308 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT)(1ULL << 2); | |||
309 | } | |||
310 | ||||
311 | if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && | |||
312 | (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) && | |||
313 | !(adev->flags & AMD_IS_APU)) | |||
314 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT)(1ULL << 34); | |||
315 | ||||
316 | if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) | |||
317 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)(1ULL << 3) | |||
318 | | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)(1ULL << 10) | |||
319 | | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)(1ULL << 11); | |||
320 | ||||
321 | if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) | |||
322 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT)(1ULL << 7); | |||
323 | ||||
324 | if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) | |||
325 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)(1ULL << 8); | |||
326 | ||||
327 | if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) | |||
328 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)(1ULL << 5); | |||
329 | ||||
330 | if (adev->pm.pp_feature & PP_ULV_MASK) | |||
331 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT)(1ULL << 18); | |||
332 | ||||
333 | if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) | |||
334 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)(1ULL << 12); | |||
335 | ||||
336 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) | |||
337 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT)(1ULL << 20); | |||
338 | ||||
339 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB(1 << 16)) | |||
340 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT)(1ULL << 41); | |||
341 | ||||
342 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB(1 << 13)) | |||
343 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT)(1ULL << 40); | |||
344 | ||||
345 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN(1 << 14) || | |||
346 | smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG(1 << 17)) | |||
347 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT)(1ULL << 22); | |||
348 | ||||
349 | if (smu->dc_controlled_by_gpio) | |||
350 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT)(1ULL << 28); | |||
351 | ||||
352 | if (amdgpu_device_should_use_aspm(adev)) | |||
353 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT)(1ULL << 15); | |||
354 | ||||
355 | return 0; | |||
356 | } | |||
357 | ||||
358 | static void sienna_cichlid_check_bxco_support(struct smu_context *smu) | |||
359 | { | |||
360 | struct smu_table_context *table_context = &smu->smu_table; | |||
361 | struct smu_11_0_7_powerplay_table *powerplay_table = | |||
362 | table_context->power_play_table; | |||
363 | struct smu_baco_context *smu_baco = &smu->smu_baco; | |||
364 | struct amdgpu_device *adev = smu->adev; | |||
365 | uint32_t val; | |||
366 | ||||
367 | if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO0x8) { | |||
368 | val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[NBIO_HWIP][0] [2] + 0x0000, 0, NBIO_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[NBIO_HWIP][0][2] + 0x0000), 0)); | |||
369 | smu_baco->platform_support = | |||
370 | (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK0x00000080L) ? true1 : | |||
371 | false0; | |||
372 | ||||
373 | /* | |||
374 | * Disable BACO entry/exit completely on below SKUs to | |||
375 | * avoid hardware intermittent failures. | |||
376 | */ | |||
377 | if (((adev->pdev->device == 0x73A1) && | |||
378 | (adev->pdev->revision == 0x00)) || | |||
379 | ((adev->pdev->device == 0x73BF) && | |||
380 | (adev->pdev->revision == 0xCF)) || | |||
381 | ((adev->pdev->device == 0x7422) && | |||
382 | (adev->pdev->revision == 0x00)) || | |||
383 | ((adev->pdev->device == 0x73A3) && | |||
384 | (adev->pdev->revision == 0x00)) || | |||
385 | ((adev->pdev->device == 0x73E3) && | |||
386 | (adev->pdev->revision == 0x00))) | |||
387 | smu_baco->platform_support = false0; | |||
388 | ||||
389 | } | |||
390 | } | |||
391 | ||||
392 | static void sienna_cichlid_check_fan_support(struct smu_context *smu) | |||
393 | { | |||
394 | struct smu_table_context *table_context = &smu->smu_table; | |||
395 | PPTable_t *pptable = table_context->driver_pptable; | |||
396 | uint64_t features = *(uint64_t *) pptable->FeaturesToRun; | |||
397 | ||||
398 | /* Fan control is not possible if PPTable has it disabled */ | |||
399 | smu->adev->pm.no_fan = | |||
400 | !(features & (1ULL << FEATURE_FAN_CONTROL_BIT32)); | |||
401 | if (smu->adev->pm.no_fan) | |||
402 | dev_info_once(smu->adev->dev,do { } while(0) | |||
403 | "PMFW based fan control disabled")do { } while(0); | |||
404 | } | |||
405 | ||||
406 | static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) | |||
407 | { | |||
408 | struct smu_table_context *table_context = &smu->smu_table; | |||
409 | struct smu_11_0_7_powerplay_table *powerplay_table = | |||
410 | table_context->power_play_table; | |||
411 | ||||
412 | if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC0x4) | |||
413 | smu->dc_controlled_by_gpio = true1; | |||
414 | ||||
415 | sienna_cichlid_check_bxco_support(smu); | |||
416 | sienna_cichlid_check_fan_support(smu); | |||
417 | ||||
418 | table_context->thermal_controller_type = | |||
419 | powerplay_table->thermal_controller_type; | |||
420 | ||||
421 | /* | |||
422 | * Instead of having its own buffer space and get overdrive_table copied, | |||
423 | * smu->od_settings just points to the actual overdrive_table | |||
424 | */ | |||
425 | smu->od_settings = &powerplay_table->overdrive_table; | |||
426 | ||||
427 | return 0; | |||
428 | } | |||
429 | ||||
430 | static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) | |||
431 | { | |||
432 | struct atom_smc_dpm_info_v4_9 *smc_dpm_table; | |||
433 | int index, ret; | |||
434 | PPTable_beige_goby_t *ppt_beige_goby; | |||
435 | PPTable_t *ppt; | |||
436 | ||||
437 | if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13))) | |||
438 | ppt_beige_goby = smu->smu_table.driver_pptable; | |||
439 | else | |||
440 | ppt = smu->smu_table.driver_pptable; | |||
441 | ||||
442 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , smc_dpm_info) / sizeof(uint16_t)) | |||
443 | smc_dpm_info)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , smc_dpm_info) / sizeof(uint16_t)); | |||
444 | ||||
445 | ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL((void *)0), NULL((void *)0), NULL((void *)0), | |||
446 | (uint8_t **)&smc_dpm_table); | |||
447 | if (ret) | |||
448 | return ret; | |||
449 | ||||
450 | if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13))) | |||
451 | smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,({ size_t __src_offset = __builtin_offsetof(typeof(*(smc_dpm_table )), I2cControllers); size_t __src_size = sizeof(*(smc_dpm_table )) - __src_offset; size_t __dst_offset = __builtin_offsetof(typeof (*(ppt_beige_goby)), I2cControllers); size_t __dst_size = (__builtin_offsetof (typeof(*(ppt_beige_goby)), BoardReserved) + sizeof((((typeof (*(ppt_beige_goby)) *)0)->BoardReserved))) - __dst_offset; __builtin_memcpy((u8 *)(ppt_beige_goby) + __dst_offset, (u8 * )(smc_dpm_table) + __src_offset, __dst_size); }) | |||
| ||||
452 | smc_dpm_table, I2cControllers)({ size_t __src_offset = __builtin_offsetof(typeof(*(smc_dpm_table )), I2cControllers); size_t __src_size = sizeof(*(smc_dpm_table )) - __src_offset; size_t __dst_offset = __builtin_offsetof(typeof (*(ppt_beige_goby)), I2cControllers); size_t __dst_size = (__builtin_offsetof (typeof(*(ppt_beige_goby)), BoardReserved) + sizeof((((typeof (*(ppt_beige_goby)) *)0)->BoardReserved))) - __dst_offset; __builtin_memcpy((u8 *)(ppt_beige_goby) + __dst_offset, (u8 * )(smc_dpm_table) + __src_offset, __dst_size); }); | |||
453 | else | |||
454 | smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,({ size_t __src_offset = __builtin_offsetof(typeof(*(smc_dpm_table )), I2cControllers); size_t __src_size = sizeof(*(smc_dpm_table )) - __src_offset; size_t __dst_offset = __builtin_offsetof(typeof (*(ppt)), I2cControllers); size_t __dst_size = (__builtin_offsetof (typeof(*(ppt)), BoardReserved) + sizeof((((typeof(*(ppt)) *) 0)->BoardReserved))) - __dst_offset; __builtin_memcpy((u8 * )(ppt) + __dst_offset, (u8 *)(smc_dpm_table) + __src_offset, __dst_size ); }) | |||
455 | smc_dpm_table, I2cControllers)({ size_t __src_offset = __builtin_offsetof(typeof(*(smc_dpm_table )), I2cControllers); size_t __src_size = sizeof(*(smc_dpm_table )) - __src_offset; size_t __dst_offset = __builtin_offsetof(typeof (*(ppt)), I2cControllers); size_t __dst_size = (__builtin_offsetof (typeof(*(ppt)), BoardReserved) + sizeof((((typeof(*(ppt)) *) 0)->BoardReserved))) - __dst_offset; __builtin_memcpy((u8 * )(ppt) + __dst_offset, (u8 *)(smc_dpm_table) + __src_offset, __dst_size ); }); | |||
456 | ||||
457 | return 0; | |||
458 | } | |||
459 | ||||
460 | static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) | |||
461 | { | |||
462 | struct smu_table_context *table_context = &smu->smu_table; | |||
463 | struct smu_11_0_7_powerplay_table *powerplay_table = | |||
464 | table_context->power_play_table; | |||
465 | int table_size; | |||
466 | ||||
467 | table_size = get_table_size(smu); | |||
468 | memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,__builtin_memcpy((table_context->driver_pptable), (&powerplay_table ->smc_pptable), (table_size)) | |||
469 | table_size)__builtin_memcpy((table_context->driver_pptable), (&powerplay_table ->smc_pptable), (table_size)); | |||
470 | ||||
471 | return 0; | |||
472 | } | |||
473 | ||||
474 | static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) | |||
475 | { | |||
476 | struct amdgpu_device *adev = smu->adev; | |||
477 | uint32_t *board_reserved; | |||
478 | uint16_t *freq_table_gfx; | |||
479 | uint32_t i; | |||
480 | ||||
481 | /* Fix some OEM SKU specific stability issues */ | |||
482 | GET_PPTABLE_MEMBER(BoardReserved, &board_reserved)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&board_reserved) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , BoardReserved)); else (*&board_reserved) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, BoardReserved ));} while(0); | |||
483 | if ((adev->pdev->device == 0x73DF) && | |||
484 | (adev->pdev->revision == 0XC3) && | |||
485 | (adev->pdev->subsystem_device == 0x16C2) && | |||
486 | (adev->pdev->subsystem_vendor == 0x1043)) | |||
487 | board_reserved[0] = 1387; | |||
488 | ||||
489 | GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&freq_table_gfx) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , FreqTableGfx)); else (*&freq_table_gfx) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, FreqTableGfx) );} while(0); | |||
490 | if ((adev->pdev->device == 0x73DF) && | |||
491 | (adev->pdev->revision == 0XC3) && | |||
492 | ((adev->pdev->subsystem_device == 0x16C2) || | |||
493 | (adev->pdev->subsystem_device == 0x133C)) && | |||
494 | (adev->pdev->subsystem_vendor == 0x1043)) { | |||
495 | for (i = 0; i < NUM_GFXCLK_DPM_LEVELS16; i++) { | |||
496 | if (freq_table_gfx[i] > 2500) | |||
497 | freq_table_gfx[i] = 2500; | |||
498 | } | |||
499 | } | |||
500 | ||||
501 | return 0; | |||
502 | } | |||
503 | ||||
504 | static int sienna_cichlid_setup_pptable(struct smu_context *smu) | |||
505 | { | |||
506 | int ret = 0; | |||
507 | ||||
508 | ret = smu_v11_0_setup_pptable(smu); | |||
509 | if (ret) | |||
| ||||
510 | return ret; | |||
511 | ||||
512 | ret = sienna_cichlid_store_powerplay_table(smu); | |||
513 | if (ret
| |||
514 | return ret; | |||
515 | ||||
516 | ret = sienna_cichlid_append_powerplay_table(smu); | |||
517 | if (ret) | |||
518 | return ret; | |||
519 | ||||
520 | ret = sienna_cichlid_check_powerplay_table(smu); | |||
521 | if (ret) | |||
522 | return ret; | |||
523 | ||||
524 | return sienna_cichlid_patch_pptable_quirk(smu); | |||
525 | } | |||
526 | ||||
527 | static int sienna_cichlid_tables_init(struct smu_context *smu) | |||
528 | { | |||
529 | struct smu_table_context *smu_table = &smu->smu_table; | |||
530 | struct smu_table *tables = smu_table->tables; | |||
531 | int table_size; | |||
532 | ||||
533 | table_size = get_table_size(smu); | |||
534 | SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,do { tables[SMU_TABLE_PPTABLE].size = table_size; tables[SMU_TABLE_PPTABLE ].align = (1 << 12); tables[SMU_TABLE_PPTABLE].domain = 0x4; } while (0) | |||
535 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PPTABLE].size = table_size; tables[SMU_TABLE_PPTABLE ].align = (1 << 12); tables[SMU_TABLE_PPTABLE].domain = 0x4; } while (0); | |||
536 | SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t) ; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables [SMU_TABLE_WATERMARKS].domain = 0x4; } while (0) | |||
537 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t) ; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables [SMU_TABLE_WATERMARKS].domain = 0x4; } while (0); | |||
538 | SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetricsExternal_t ); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables [SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0) | |||
539 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetricsExternal_t ); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables [SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0); | |||
540 | SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t ); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables [SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0) | |||
541 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t ); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables [SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0); | |||
542 | SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),do { tables[SMU_TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t ); tables[SMU_TABLE_OVERDRIVE].align = (1 << 12); tables [SMU_TABLE_OVERDRIVE].domain = 0x4; } while (0) | |||
543 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t ); tables[SMU_TABLE_OVERDRIVE].align = (1 << 12); tables [SMU_TABLE_OVERDRIVE].domain = 0x4; } while (0); | |||
544 | SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG ].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain = 0x4; } while (0) | |||
545 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG ].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain = 0x4; } while (0); | |||
546 | SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffIntExternal_t ); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 << 12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; } while (0) | |||
547 | sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffIntExternal_t ); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 << 12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; } while (0) | |||
548 | AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffIntExternal_t ); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 << 12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; } while (0); | |||
549 | SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),do { tables[SMU_TABLE_ECCINFO].size = sizeof(EccInfoTable_t); tables[SMU_TABLE_ECCINFO].align = (1 << 12); tables[SMU_TABLE_ECCINFO ].domain = 0x4; } while (0) | |||
550 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_ECCINFO].size = sizeof(EccInfoTable_t); tables[SMU_TABLE_ECCINFO].align = (1 << 12); tables[SMU_TABLE_ECCINFO ].domain = 0x4; } while (0); | |||
551 | SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),do { tables[SMU_TABLE_DRIVER_SMU_CONFIG].size = sizeof(DriverSmuConfigExternal_t ); tables[SMU_TABLE_DRIVER_SMU_CONFIG].align = (1 << 12 ); tables[SMU_TABLE_DRIVER_SMU_CONFIG].domain = 0x4; } while ( 0) | |||
552 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_DRIVER_SMU_CONFIG].size = sizeof(DriverSmuConfigExternal_t ); tables[SMU_TABLE_DRIVER_SMU_CONFIG].align = (1 << 12 ); tables[SMU_TABLE_DRIVER_SMU_CONFIG].domain = 0x4; } while ( 0); | |||
553 | ||||
554 | smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL(0x0001 | 0x0004)); | |||
555 | if (!smu_table->metrics_table) | |||
556 | goto err0_out; | |||
557 | smu_table->metrics_time = 0; | |||
558 | ||||
559 | smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); | |||
560 | smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL(0x0001 | 0x0004)); | |||
561 | if (!smu_table->gpu_metrics_table) | |||
562 | goto err1_out; | |||
563 | ||||
564 | smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL(0x0001 | 0x0004)); | |||
565 | if (!smu_table->watermarks_table) | |||
566 | goto err2_out; | |||
567 | ||||
568 | smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL(0x0001 | 0x0004)); | |||
569 | if (!smu_table->ecc_table) | |||
570 | goto err3_out; | |||
571 | ||||
572 | smu_table->driver_smu_config_table = | |||
573 | kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL(0x0001 | 0x0004)); | |||
574 | if (!smu_table->driver_smu_config_table) | |||
575 | goto err4_out; | |||
576 | ||||
577 | return 0; | |||
578 | ||||
579 | err4_out: | |||
580 | kfree(smu_table->ecc_table); | |||
581 | err3_out: | |||
582 | kfree(smu_table->watermarks_table); | |||
583 | err2_out: | |||
584 | kfree(smu_table->gpu_metrics_table); | |||
585 | err1_out: | |||
586 | kfree(smu_table->metrics_table); | |||
587 | err0_out: | |||
588 | return -ENOMEM12; | |||
589 | } | |||
590 | ||||
591 | static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu, | |||
592 | bool_Bool use_metrics_v3, | |||
593 | bool_Bool use_metrics_v2) | |||
594 | { | |||
595 | struct smu_table_context *smu_table= &smu->smu_table; | |||
596 | SmuMetricsExternal_t *metrics_ext = | |||
597 | (SmuMetricsExternal_t *)(smu_table->metrics_table); | |||
598 | uint32_t throttler_status = 0; | |||
599 | int i; | |||
600 | ||||
601 | if (use_metrics_v3) { | |||
602 | for (i = 0; i < THROTTLER_COUNT20; i++) | |||
603 | throttler_status |= | |||
604 | (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); | |||
605 | } else if (use_metrics_v2) { | |||
606 | for (i = 0; i < THROTTLER_COUNT20; i++) | |||
607 | throttler_status |= | |||
608 | (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); | |||
609 | } else { | |||
610 | throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; | |||
611 | } | |||
612 | ||||
613 | return throttler_status; | |||
614 | } | |||
615 | ||||
616 | static int sienna_cichlid_get_power_limit(struct smu_context *smu, | |||
617 | uint32_t *current_power_limit, | |||
618 | uint32_t *default_power_limit, | |||
619 | uint32_t *max_power_limit) | |||
620 | { | |||
621 | struct smu_11_0_7_powerplay_table *powerplay_table = | |||
622 | (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; | |||
623 | uint32_t power_limit, od_percent; | |||
624 | uint16_t *table_member; | |||
625 | ||||
626 | GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , SocketPowerLimitAc)); else (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_t, SocketPowerLimitAc ));} while(0); | |||
627 | ||||
628 | if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { | |||
629 | power_limit = | |||
630 | table_member[PPT_THROTTLER_PPT0]; | |||
631 | } | |||
632 | ||||
633 | if (current_power_limit) | |||
634 | *current_power_limit = power_limit; | |||
635 | if (default_power_limit) | |||
636 | *default_power_limit = power_limit; | |||
637 | ||||
638 | if (max_power_limit) { | |||
639 | if (smu->od_enabled) { | |||
640 | od_percent = | |||
641 | le32_to_cpu(powerplay_table->overdrive_table.max[((__uint32_t)(powerplay_table->overdrive_table.max[ SMU_11_0_7_ODSETTING_POWERPERCENTAGE ])) | |||
642 | SMU_11_0_7_ODSETTING_POWERPERCENTAGE])((__uint32_t)(powerplay_table->overdrive_table.max[ SMU_11_0_7_ODSETTING_POWERPERCENTAGE ])); | |||
643 | ||||
644 | dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",do { } while(0) | |||
645 | od_percent, power_limit)do { } while(0); | |||
646 | ||||
647 | power_limit *= (100 + od_percent); | |||
648 | power_limit /= 100; | |||
649 | } | |||
650 | *max_power_limit = power_limit; | |||
651 | } | |||
652 | ||||
653 | return 0; | |||
654 | } | |||
655 | ||||
656 | static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu, | |||
657 | uint32_t *apu_percent, | |||
658 | uint32_t *dgpu_percent) | |||
659 | { | |||
660 | struct smu_table_context *smu_table = &smu->smu_table; | |||
661 | SmuMetrics_V4_t *metrics_v4 = | |||
662 | &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4); | |||
663 | uint16_t powerRatio = 0; | |||
664 | uint16_t apu_power_limit = 0; | |||
665 | uint16_t dgpu_power_limit = 0; | |||
666 | uint32_t apu_boost = 0; | |||
667 | uint32_t dgpu_boost = 0; | |||
668 | uint32_t cur_power_limit; | |||
669 | ||||
670 | if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { | |||
671 | sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL((void *)0), NULL((void *)0)); | |||
672 | apu_power_limit = metrics_v4->ApuSTAPMLimit; | |||
673 | dgpu_power_limit = cur_power_limit; | |||
674 | powerRatio = (((apu_power_limit + | |||
675 | dgpu_power_limit) * 100) / | |||
676 | metrics_v4->ApuSTAPMSmartShiftLimit); | |||
677 | if (powerRatio > 100) { | |||
678 | apu_power_limit = (apu_power_limit * 100) / | |||
679 | powerRatio; | |||
680 | dgpu_power_limit = (dgpu_power_limit * 100) / | |||
681 | powerRatio; | |||
682 | } | |||
683 | if (metrics_v4->AverageApuSocketPower > apu_power_limit && | |||
684 | apu_power_limit != 0) { | |||
685 | apu_boost = ((metrics_v4->AverageApuSocketPower - | |||
686 | apu_power_limit) * 100) / | |||
687 | apu_power_limit; | |||
688 | if (apu_boost > 100) | |||
689 | apu_boost = 100; | |||
690 | } | |||
691 | ||||
692 | if (metrics_v4->AverageSocketPower > dgpu_power_limit && | |||
693 | dgpu_power_limit != 0) { | |||
694 | dgpu_boost = ((metrics_v4->AverageSocketPower - | |||
695 | dgpu_power_limit) * 100) / | |||
696 | dgpu_power_limit; | |||
697 | if (dgpu_boost > 100) | |||
698 | dgpu_boost = 100; | |||
699 | } | |||
700 | ||||
701 | if (dgpu_boost >= apu_boost) | |||
702 | apu_boost = 0; | |||
703 | else | |||
704 | dgpu_boost = 0; | |||
705 | } | |||
706 | *apu_percent = apu_boost; | |||
707 | *dgpu_percent = dgpu_boost; | |||
708 | } | |||
709 | ||||
710 | static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, | |||
711 | MetricsMember_t member, | |||
712 | uint32_t *value) | |||
713 | { | |||
714 | struct smu_table_context *smu_table= &smu->smu_table; | |||
715 | SmuMetrics_t *metrics = | |||
716 | &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); | |||
717 | SmuMetrics_V2_t *metrics_v2 = | |||
718 | &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); | |||
719 | SmuMetrics_V3_t *metrics_v3 = | |||
720 | &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); | |||
721 | bool_Bool use_metrics_v2 = false0; | |||
722 | bool_Bool use_metrics_v3 = false0; | |||
723 | uint16_t average_gfx_activity; | |||
724 | int ret = 0; | |||
725 | uint32_t apu_percent = 0; | |||
726 | uint32_t dgpu_percent = 0; | |||
727 | ||||
728 | switch (smu->adev->ip_versions[MP1_HWIP][0]) { | |||
729 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): | |||
730 | if (smu->smc_fw_version >= 0x3A4900) | |||
731 | use_metrics_v3 = true1; | |||
732 | else if (smu->smc_fw_version >= 0x3A4300) | |||
733 | use_metrics_v2 = true1; | |||
734 | break; | |||
735 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): | |||
736 | if (smu->smc_fw_version >= 0x412D00) | |||
737 | use_metrics_v2 = true1; | |||
738 | break; | |||
739 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): | |||
740 | if (smu->smc_fw_version >= 0x3B2300) | |||
741 | use_metrics_v2 = true1; | |||
742 | break; | |||
743 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): | |||
744 | if (smu->smc_fw_version >= 0x491100) | |||
745 | use_metrics_v2 = true1; | |||
746 | break; | |||
747 | default: | |||
748 | break; | |||
749 | } | |||
750 | ||||
751 | ret = smu_cmn_get_metrics_table(smu, | |||
752 | NULL((void *)0), | |||
753 | false0); | |||
754 | if (ret) | |||
755 | return ret; | |||
756 | ||||
757 | switch (member) { | |||
758 | case METRICS_CURR_GFXCLK: | |||
759 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : | |||
760 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : | |||
761 | metrics->CurrClock[PPCLK_GFXCLK]; | |||
762 | break; | |||
763 | case METRICS_CURR_SOCCLK: | |||
764 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : | |||
765 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : | |||
766 | metrics->CurrClock[PPCLK_SOCCLK]; | |||
767 | break; | |||
768 | case METRICS_CURR_UCLK: | |||
769 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : | |||
770 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : | |||
771 | metrics->CurrClock[PPCLK_UCLK]; | |||
772 | break; | |||
773 | case METRICS_CURR_VCLK: | |||
774 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : | |||
775 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : | |||
776 | metrics->CurrClock[PPCLK_VCLK_0]; | |||
777 | break; | |||
778 | case METRICS_CURR_VCLK1: | |||
779 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : | |||
780 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : | |||
781 | metrics->CurrClock[PPCLK_VCLK_1]; | |||
782 | break; | |||
783 | case METRICS_CURR_DCLK: | |||
784 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : | |||
785 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : | |||
786 | metrics->CurrClock[PPCLK_DCLK_0]; | |||
787 | break; | |||
788 | case METRICS_CURR_DCLK1: | |||
789 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : | |||
790 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : | |||
791 | metrics->CurrClock[PPCLK_DCLK_1]; | |||
792 | break; | |||
793 | case METRICS_CURR_DCEFCLK: | |||
794 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : | |||
795 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : | |||
796 | metrics->CurrClock[PPCLK_DCEFCLK]; | |||
797 | break; | |||
798 | case METRICS_CURR_FCLK: | |||
799 | *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : | |||
800 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : | |||
801 | metrics->CurrClock[PPCLK_FCLK]; | |||
802 | break; | |||
803 | case METRICS_AVERAGE_GFXCLK: | |||
804 | average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : | |||
805 | use_metrics_v2 ? metrics_v2->AverageGfxActivity : | |||
806 | metrics->AverageGfxActivity; | |||
807 | if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD15) | |||
808 | *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : | |||
809 | use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : | |||
810 | metrics->AverageGfxclkFrequencyPostDs; | |||
811 | else | |||
812 | *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : | |||
813 | use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : | |||
814 | metrics->AverageGfxclkFrequencyPreDs; | |||
815 | break; | |||
816 | case METRICS_AVERAGE_FCLK: | |||
817 | *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : | |||
818 | use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : | |||
819 | metrics->AverageFclkFrequencyPostDs; | |||
820 | break; | |||
821 | case METRICS_AVERAGE_UCLK: | |||
822 | *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : | |||
823 | use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : | |||
824 | metrics->AverageUclkFrequencyPostDs; | |||
825 | break; | |||
826 | case METRICS_AVERAGE_GFXACTIVITY: | |||
827 | *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : | |||
828 | use_metrics_v2 ? metrics_v2->AverageGfxActivity : | |||
829 | metrics->AverageGfxActivity; | |||
830 | break; | |||
831 | case METRICS_AVERAGE_MEMACTIVITY: | |||
832 | *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : | |||
833 | use_metrics_v2 ? metrics_v2->AverageUclkActivity : | |||
834 | metrics->AverageUclkActivity; | |||
835 | break; | |||
836 | case METRICS_AVERAGE_SOCKETPOWER: | |||
837 | *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : | |||
838 | use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : | |||
839 | metrics->AverageSocketPower << 8; | |||
840 | break; | |||
841 | case METRICS_TEMPERATURE_EDGE: | |||
842 | *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : | |||
843 | use_metrics_v2 ? metrics_v2->TemperatureEdge : | |||
844 | metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
845 | break; | |||
846 | case METRICS_TEMPERATURE_HOTSPOT: | |||
847 | *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : | |||
848 | use_metrics_v2 ? metrics_v2->TemperatureHotspot : | |||
849 | metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
850 | break; | |||
851 | case METRICS_TEMPERATURE_MEM: | |||
852 | *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : | |||
853 | use_metrics_v2 ? metrics_v2->TemperatureMem : | |||
854 | metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
855 | break; | |||
856 | case METRICS_TEMPERATURE_VRGFX: | |||
857 | *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : | |||
858 | use_metrics_v2 ? metrics_v2->TemperatureVrGfx : | |||
859 | metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
860 | break; | |||
861 | case METRICS_TEMPERATURE_VRSOC: | |||
862 | *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : | |||
863 | use_metrics_v2 ? metrics_v2->TemperatureVrSoc : | |||
864 | metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
865 | break; | |||
866 | case METRICS_THROTTLER_STATUS: | |||
867 | *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); | |||
868 | break; | |||
869 | case METRICS_CURR_FANSPEED: | |||
870 | *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : | |||
871 | use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; | |||
872 | break; | |||
873 | case METRICS_UNIQUE_ID_UPPER32: | |||
874 | /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ | |||
875 | *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0; | |||
876 | break; | |||
877 | case METRICS_UNIQUE_ID_LOWER32: | |||
878 | /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ | |||
879 | *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0; | |||
880 | break; | |||
881 | case METRICS_SS_APU_SHARE: | |||
882 | sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); | |||
883 | *value = apu_percent; | |||
884 | break; | |||
885 | case METRICS_SS_DGPU_SHARE: | |||
886 | sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); | |||
887 | *value = dgpu_percent; | |||
888 | break; | |||
889 | ||||
890 | default: | |||
891 | *value = UINT_MAX0xffffffffU; | |||
892 | break; | |||
893 | } | |||
894 | ||||
895 | return ret; | |||
896 | ||||
897 | } | |||
898 | ||||
899 | static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) | |||
900 | { | |||
901 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |||
902 | ||||
903 | smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), | |||
904 | GFP_KERNEL(0x0001 | 0x0004)); | |||
905 | if (!smu_dpm->dpm_context) | |||
906 | return -ENOMEM12; | |||
907 | ||||
908 | smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); | |||
909 | ||||
910 | return 0; | |||
911 | } | |||
912 | ||||
913 | static void sienna_cichlid_stb_init(struct smu_context *smu); | |||
914 | ||||
915 | static int sienna_cichlid_init_smc_tables(struct smu_context *smu) | |||
916 | { | |||
917 | struct amdgpu_device *adev = smu->adev; | |||
918 | int ret = 0; | |||
919 | ||||
920 | ret = sienna_cichlid_tables_init(smu); | |||
921 | if (ret) | |||
922 | return ret; | |||
923 | ||||
924 | ret = sienna_cichlid_allocate_dpm_context(smu); | |||
925 | if (ret) | |||
926 | return ret; | |||
927 | ||||
928 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) | |||
929 | sienna_cichlid_stb_init(smu); | |||
930 | ||||
931 | return smu_v11_0_init_smc_tables(smu); | |||
932 | } | |||
933 | ||||
934 | static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) | |||
935 | { | |||
936 | struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; | |||
937 | struct smu_11_0_dpm_table *dpm_table; | |||
938 | struct amdgpu_device *adev = smu->adev; | |||
939 | int i, ret = 0; | |||
940 | DpmDescriptor_t *table_member; | |||
941 | ||||
942 | /* socclk dpm table setup */ | |||
943 | dpm_table = &dpm_context->dpm_tables.soc_table; | |||
944 | GET_PPTABLE_MEMBER(DpmDescriptor, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , DpmDescriptor)); else (*&table_member) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, DpmDescriptor ));} while(0); | |||
945 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { | |||
946 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
947 | SMU_SOCCLK, | |||
948 | dpm_table); | |||
949 | if (ret) | |||
950 | return ret; | |||
951 | dpm_table->is_fine_grained = | |||
952 | !table_member[PPCLK_SOCCLK].SnapToDiscrete; | |||
953 | } else { | |||
954 | dpm_table->count = 1; | |||
955 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; | |||
956 | dpm_table->dpm_levels[0].enabled = true1; | |||
957 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
958 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
959 | } | |||
960 | ||||
961 | /* gfxclk dpm table setup */ | |||
962 | dpm_table = &dpm_context->dpm_tables.gfx_table; | |||
963 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { | |||
964 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
965 | SMU_GFXCLK, | |||
966 | dpm_table); | |||
967 | if (ret) | |||
968 | return ret; | |||
969 | dpm_table->is_fine_grained = | |||
970 | !table_member[PPCLK_GFXCLK].SnapToDiscrete; | |||
971 | } else { | |||
972 | dpm_table->count = 1; | |||
973 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; | |||
974 | dpm_table->dpm_levels[0].enabled = true1; | |||
975 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
976 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
977 | } | |||
978 | ||||
979 | /* uclk dpm table setup */ | |||
980 | dpm_table = &dpm_context->dpm_tables.uclk_table; | |||
981 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { | |||
982 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
983 | SMU_UCLK, | |||
984 | dpm_table); | |||
985 | if (ret) | |||
986 | return ret; | |||
987 | dpm_table->is_fine_grained = | |||
988 | !table_member[PPCLK_UCLK].SnapToDiscrete; | |||
989 | } else { | |||
990 | dpm_table->count = 1; | |||
991 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; | |||
992 | dpm_table->dpm_levels[0].enabled = true1; | |||
993 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
994 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
995 | } | |||
996 | ||||
997 | /* fclk dpm table setup */ | |||
998 | dpm_table = &dpm_context->dpm_tables.fclk_table; | |||
999 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { | |||
1000 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1001 | SMU_FCLK, | |||
1002 | dpm_table); | |||
1003 | if (ret) | |||
1004 | return ret; | |||
1005 | dpm_table->is_fine_grained = | |||
1006 | !table_member[PPCLK_FCLK].SnapToDiscrete; | |||
1007 | } else { | |||
1008 | dpm_table->count = 1; | |||
1009 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; | |||
1010 | dpm_table->dpm_levels[0].enabled = true1; | |||
1011 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1012 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1013 | } | |||
1014 | ||||
1015 | /* vclk0/1 dpm table setup */ | |||
1016 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { | |||
1017 | if (adev->vcn.harvest_config & (1 << i)) | |||
1018 | continue; | |||
1019 | ||||
1020 | dpm_table = &dpm_context->dpm_tables.vclk_table; | |||
1021 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |||
1022 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1023 | i ? SMU_VCLK1 : SMU_VCLK, | |||
1024 | dpm_table); | |||
1025 | if (ret) | |||
1026 | return ret; | |||
1027 | dpm_table->is_fine_grained = | |||
1028 | !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; | |||
1029 | } else { | |||
1030 | dpm_table->count = 1; | |||
1031 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; | |||
1032 | dpm_table->dpm_levels[0].enabled = true1; | |||
1033 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1034 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1035 | } | |||
1036 | } | |||
1037 | ||||
1038 | /* dclk0/1 dpm table setup */ | |||
1039 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { | |||
1040 | if (adev->vcn.harvest_config & (1 << i)) | |||
1041 | continue; | |||
1042 | dpm_table = &dpm_context->dpm_tables.dclk_table; | |||
1043 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |||
1044 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1045 | i ? SMU_DCLK1 : SMU_DCLK, | |||
1046 | dpm_table); | |||
1047 | if (ret) | |||
1048 | return ret; | |||
1049 | dpm_table->is_fine_grained = | |||
1050 | !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; | |||
1051 | } else { | |||
1052 | dpm_table->count = 1; | |||
1053 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; | |||
1054 | dpm_table->dpm_levels[0].enabled = true1; | |||
1055 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1056 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1057 | } | |||
1058 | } | |||
1059 | ||||
1060 | /* dcefclk dpm table setup */ | |||
1061 | dpm_table = &dpm_context->dpm_tables.dcef_table; | |||
1062 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |||
1063 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1064 | SMU_DCEFCLK, | |||
1065 | dpm_table); | |||
1066 | if (ret) | |||
1067 | return ret; | |||
1068 | dpm_table->is_fine_grained = | |||
1069 | !table_member[PPCLK_DCEFCLK].SnapToDiscrete; | |||
1070 | } else { | |||
1071 | dpm_table->count = 1; | |||
1072 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |||
1073 | dpm_table->dpm_levels[0].enabled = true1; | |||
1074 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1075 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1076 | } | |||
1077 | ||||
1078 | /* pixelclk dpm table setup */ | |||
1079 | dpm_table = &dpm_context->dpm_tables.pixel_table; | |||
1080 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |||
1081 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1082 | SMU_PIXCLK, | |||
1083 | dpm_table); | |||
1084 | if (ret) | |||
1085 | return ret; | |||
1086 | dpm_table->is_fine_grained = | |||
1087 | !table_member[PPCLK_PIXCLK].SnapToDiscrete; | |||
1088 | } else { | |||
1089 | dpm_table->count = 1; | |||
1090 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |||
1091 | dpm_table->dpm_levels[0].enabled = true1; | |||
1092 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1093 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1094 | } | |||
1095 | ||||
1096 | /* displayclk dpm table setup */ | |||
1097 | dpm_table = &dpm_context->dpm_tables.display_table; | |||
1098 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |||
1099 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1100 | SMU_DISPCLK, | |||
1101 | dpm_table); | |||
1102 | if (ret) | |||
1103 | return ret; | |||
1104 | dpm_table->is_fine_grained = | |||
1105 | !table_member[PPCLK_DISPCLK].SnapToDiscrete; | |||
1106 | } else { | |||
1107 | dpm_table->count = 1; | |||
1108 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |||
1109 | dpm_table->dpm_levels[0].enabled = true1; | |||
1110 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1111 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1112 | } | |||
1113 | ||||
1114 | /* phyclk dpm table setup */ | |||
1115 | dpm_table = &dpm_context->dpm_tables.phy_table; | |||
1116 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |||
1117 | ret = smu_v11_0_set_single_dpm_table(smu, | |||
1118 | SMU_PHYCLK, | |||
1119 | dpm_table); | |||
1120 | if (ret) | |||
1121 | return ret; | |||
1122 | dpm_table->is_fine_grained = | |||
1123 | !table_member[PPCLK_PHYCLK].SnapToDiscrete; | |||
1124 | } else { | |||
1125 | dpm_table->count = 1; | |||
1126 | dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; | |||
1127 | dpm_table->dpm_levels[0].enabled = true1; | |||
1128 | dpm_table->min = dpm_table->dpm_levels[0].value; | |||
1129 | dpm_table->max = dpm_table->dpm_levels[0].value; | |||
1130 | } | |||
1131 | ||||
1132 | return 0; | |||
1133 | } | |||
1134 | ||||
1135 | static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool_Bool enable) | |||
1136 | { | |||
1137 | struct amdgpu_device *adev = smu->adev; | |||
1138 | int i, ret = 0; | |||
1139 | ||||
1140 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { | |||
1141 | if (adev->vcn.harvest_config & (1 << i)) | |||
1142 | continue; | |||
1143 | /* vcn dpm on is a prerequisite for vcn power gate messages */ | |||
1144 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |||
1145 | ret = smu_cmn_send_smc_msg_with_param(smu, enable ? | |||
1146 | SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, | |||
1147 | 0x10000 * i, NULL((void *)0)); | |||
1148 | if (ret) | |||
1149 | return ret; | |||
1150 | } | |||
1151 | } | |||
1152 | ||||
1153 | return ret; | |||
1154 | } | |||
1155 | ||||
1156 | static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool_Bool enable) | |||
1157 | { | |||
1158 | int ret = 0; | |||
1159 | ||||
1160 | if (enable) { | |||
1161 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |||
1162 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL((void *)0)); | |||
1163 | if (ret) | |||
1164 | return ret; | |||
1165 | } | |||
1166 | } else { | |||
1167 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { | |||
1168 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL((void *)0)); | |||
1169 | if (ret) | |||
1170 | return ret; | |||
1171 | } | |||
1172 | } | |||
1173 | ||||
1174 | return ret; | |||
1175 | } | |||
1176 | ||||
1177 | static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, | |||
1178 | enum smu_clk_type clk_type, | |||
1179 | uint32_t *value) | |||
1180 | { | |||
1181 | MetricsMember_t member_type; | |||
1182 | int clk_id = 0; | |||
1183 | ||||
1184 | clk_id = smu_cmn_to_asic_specific_index(smu, | |||
1185 | CMN2ASIC_MAPPING_CLK, | |||
1186 | clk_type); | |||
1187 | if (clk_id < 0) | |||
1188 | return clk_id; | |||
1189 | ||||
1190 | switch (clk_id) { | |||
1191 | case PPCLK_GFXCLK: | |||
1192 | member_type = METRICS_CURR_GFXCLK; | |||
1193 | break; | |||
1194 | case PPCLK_UCLK: | |||
1195 | member_type = METRICS_CURR_UCLK; | |||
1196 | break; | |||
1197 | case PPCLK_SOCCLK: | |||
1198 | member_type = METRICS_CURR_SOCCLK; | |||
1199 | break; | |||
1200 | case PPCLK_FCLK: | |||
1201 | member_type = METRICS_CURR_FCLK; | |||
1202 | break; | |||
1203 | case PPCLK_VCLK_0: | |||
1204 | member_type = METRICS_CURR_VCLK; | |||
1205 | break; | |||
1206 | case PPCLK_VCLK_1: | |||
1207 | member_type = METRICS_CURR_VCLK1; | |||
1208 | break; | |||
1209 | case PPCLK_DCLK_0: | |||
1210 | member_type = METRICS_CURR_DCLK; | |||
1211 | break; | |||
1212 | case PPCLK_DCLK_1: | |||
1213 | member_type = METRICS_CURR_DCLK1; | |||
1214 | break; | |||
1215 | case PPCLK_DCEFCLK: | |||
1216 | member_type = METRICS_CURR_DCEFCLK; | |||
1217 | break; | |||
1218 | default: | |||
1219 | return -EINVAL22; | |||
1220 | } | |||
1221 | ||||
1222 | return sienna_cichlid_get_smu_metrics_data(smu, | |||
1223 | member_type, | |||
1224 | value); | |||
1225 | ||||
1226 | } | |||
1227 | ||||
1228 | static bool_Bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) | |||
1229 | { | |||
1230 | DpmDescriptor_t *dpm_desc = NULL((void *)0); | |||
1231 | DpmDescriptor_t *table_member; | |||
1232 | uint32_t clk_index = 0; | |||
1233 | ||||
1234 | GET_PPTABLE_MEMBER(DpmDescriptor, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , DpmDescriptor)); else (*&table_member) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, DpmDescriptor ));} while(0); | |||
1235 | clk_index = smu_cmn_to_asic_specific_index(smu, | |||
1236 | CMN2ASIC_MAPPING_CLK, | |||
1237 | clk_type); | |||
1238 | dpm_desc = &table_member[clk_index]; | |||
1239 | ||||
1240 | /* 0 - Fine grained DPM, 1 - Discrete DPM */ | |||
1241 | return dpm_desc->SnapToDiscrete == 0; | |||
1242 | } | |||
1243 | ||||
1244 | static bool_Bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, | |||
1245 | enum SMU_11_0_7_ODFEATURE_CAP cap) | |||
1246 | { | |||
1247 | return od_table->cap[cap]; | |||
1248 | } | |||
1249 | ||||
1250 | static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, | |||
1251 | enum SMU_11_0_7_ODSETTING_ID setting, | |||
1252 | uint32_t *min, uint32_t *max) | |||
1253 | { | |||
1254 | if (min) | |||
1255 | *min = od_table->min[setting]; | |||
1256 | if (max) | |||
1257 | *max = od_table->max[setting]; | |||
1258 | } | |||
1259 | ||||
1260 | static int sienna_cichlid_print_clk_levels(struct smu_context *smu, | |||
1261 | enum smu_clk_type clk_type, char *buf) | |||
1262 | { | |||
1263 | struct amdgpu_device *adev = smu->adev; | |||
1264 | struct smu_table_context *table_context = &smu->smu_table; | |||
1265 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | |||
1266 | struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; | |||
1267 | uint16_t *table_member; | |||
1268 | ||||
1269 | struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; | |||
1270 | OverDriveTable_t *od_table = | |||
1271 | (OverDriveTable_t *)table_context->overdrive_table; | |||
1272 | int i, size = 0, ret = 0; | |||
1273 | uint32_t cur_value = 0, value = 0, count = 0; | |||
1274 | uint32_t freq_values[3] = {0}; | |||
1275 | uint32_t mark_index = 0; | |||
1276 | uint32_t gen_speed, lane_width; | |||
1277 | uint32_t min_value, max_value; | |||
1278 | uint32_t smu_version; | |||
1279 | ||||
1280 | smu_cmn_get_sysfs_buf(&buf, &size); | |||
1281 | ||||
1282 | switch (clk_type) { | |||
1283 | case SMU_GFXCLK: | |||
1284 | case SMU_SCLK: | |||
1285 | case SMU_SOCCLK: | |||
1286 | case SMU_MCLK: | |||
1287 | case SMU_UCLK: | |||
1288 | case SMU_FCLK: | |||
1289 | case SMU_VCLK: | |||
1290 | case SMU_VCLK1: | |||
1291 | case SMU_DCLK: | |||
1292 | case SMU_DCLK1: | |||
1293 | case SMU_DCEFCLK: | |||
1294 | ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); | |||
1295 | if (ret) | |||
1296 | goto print_clk_out; | |||
1297 | ||||
1298 | ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); | |||
1299 | if (ret) | |||
1300 | goto print_clk_out; | |||
1301 | ||||
1302 | if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |||
1303 | for (i = 0; i < count; i++) { | |||
1304 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); | |||
1305 | if (ret) | |||
1306 | goto print_clk_out; | |||
1307 | ||||
1308 | size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, | |||
1309 | cur_value == value ? "*" : ""); | |||
1310 | } | |||
1311 | } else { | |||
1312 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); | |||
1313 | if (ret) | |||
1314 | goto print_clk_out; | |||
1315 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); | |||
1316 | if (ret) | |||
1317 | goto print_clk_out; | |||
1318 | ||||
1319 | freq_values[1] = cur_value; | |||
1320 | mark_index = cur_value == freq_values[0] ? 0 : | |||
1321 | cur_value == freq_values[2] ? 2 : 1; | |||
1322 | ||||
1323 | count = 3; | |||
1324 | if (mark_index != 1) { | |||
1325 | count = 2; | |||
1326 | freq_values[1] = freq_values[2]; | |||
1327 | } | |||
1328 | ||||
1329 | for (i = 0; i < count; i++) { | |||
1330 | size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], | |||
1331 | cur_value == freq_values[i] ? "*" : ""); | |||
1332 | } | |||
1333 | ||||
1334 | } | |||
1335 | break; | |||
1336 | case SMU_PCIE: | |||
1337 | gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); | |||
1338 | lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); | |||
1339 | GET_PPTABLE_MEMBER(LclkFreq, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , LclkFreq)); else (*&table_member) = (smu->smu_table. driver_pptable + __builtin_offsetof(PPTable_t, LclkFreq));} while (0); | |||
1340 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
1341 | size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, | |||
1342 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : | |||
1343 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : | |||
1344 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : | |||
1345 | (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", | |||
1346 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : | |||
1347 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : | |||
1348 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : | |||
1349 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : | |||
1350 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : | |||
1351 | (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", | |||
1352 | table_member[i], | |||
1353 | (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && | |||
1354 | (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? | |||
1355 | "*" : ""); | |||
1356 | break; | |||
1357 | case SMU_OD_SCLK: | |||
1358 | if (!smu->od_enabled || !od_table || !od_settings) | |||
1359 | break; | |||
1360 | ||||
1361 | if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) | |||
1362 | break; | |||
1363 | ||||
1364 | size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); | |||
1365 | size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); | |||
1366 | break; | |||
1367 | ||||
1368 | case SMU_OD_MCLK: | |||
1369 | if (!smu->od_enabled || !od_table || !od_settings) | |||
1370 | break; | |||
1371 | ||||
1372 | if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) | |||
1373 | break; | |||
1374 | ||||
1375 | size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); | |||
1376 | size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); | |||
1377 | break; | |||
1378 | ||||
1379 | case SMU_OD_VDDGFX_OFFSET: | |||
1380 | if (!smu->od_enabled || !od_table || !od_settings) | |||
1381 | break; | |||
1382 | ||||
1383 | /* | |||
1384 | * OD GFX Voltage Offset functionality is supported only by 58.41.0 | |||
1385 | * and onwards SMU firmwares. | |||
1386 | */ | |||
1387 | smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
1388 | if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) && | |||
1389 | (smu_version < 0x003a2900)) | |||
1390 | break; | |||
1391 | ||||
1392 | size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); | |||
1393 | size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); | |||
1394 | break; | |||
1395 | ||||
1396 | case SMU_OD_RANGE: | |||
1397 | if (!smu->od_enabled || !od_table || !od_settings) | |||
1398 | break; | |||
1399 | ||||
1400 | size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); | |||
1401 | ||||
1402 | if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { | |||
1403 | sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, | |||
1404 | &min_value, NULL((void *)0)); | |||
1405 | sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, | |||
1406 | NULL((void *)0), &max_value); | |||
1407 | size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", | |||
1408 | min_value, max_value); | |||
1409 | } | |||
1410 | ||||
1411 | if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { | |||
1412 | sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, | |||
1413 | &min_value, NULL((void *)0)); | |||
1414 | sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, | |||
1415 | NULL((void *)0), &max_value); | |||
1416 | size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", | |||
1417 | min_value, max_value); | |||
1418 | } | |||
1419 | break; | |||
1420 | ||||
1421 | default: | |||
1422 | break; | |||
1423 | } | |||
1424 | ||||
1425 | print_clk_out: | |||
1426 | return size; | |||
1427 | } | |||
1428 | ||||
1429 | static int sienna_cichlid_force_clk_levels(struct smu_context *smu, | |||
1430 | enum smu_clk_type clk_type, uint32_t mask) | |||
1431 | { | |||
1432 | int ret = 0; | |||
1433 | uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; | |||
1434 | ||||
1435 | soft_min_level = mask ? (ffs(mask) - 1) : 0; | |||
1436 | soft_max_level = mask ? (fls(mask) - 1) : 0; | |||
1437 | ||||
1438 | switch (clk_type) { | |||
1439 | case SMU_GFXCLK: | |||
1440 | case SMU_SCLK: | |||
1441 | case SMU_SOCCLK: | |||
1442 | case SMU_MCLK: | |||
1443 | case SMU_UCLK: | |||
1444 | case SMU_FCLK: | |||
1445 | /* There is only 2 levels for fine grained DPM */ | |||
1446 | if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { | |||
1447 | soft_max_level = (soft_max_level >= 1 ? 1 : 0); | |||
1448 | soft_min_level = (soft_min_level >= 1 ? 1 : 0); | |||
1449 | } | |||
1450 | ||||
1451 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); | |||
1452 | if (ret) | |||
1453 | goto forec_level_out; | |||
1454 | ||||
1455 | ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); | |||
1456 | if (ret) | |||
1457 | goto forec_level_out; | |||
1458 | ||||
1459 | ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); | |||
1460 | if (ret) | |||
1461 | goto forec_level_out; | |||
1462 | break; | |||
1463 | case SMU_DCEFCLK: | |||
1464 | dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n")do { } while(0); | |||
1465 | break; | |||
1466 | default: | |||
1467 | break; | |||
1468 | } | |||
1469 | ||||
1470 | forec_level_out: | |||
1471 | return 0; | |||
1472 | } | |||
1473 | ||||
1474 | static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) | |||
1475 | { | |||
1476 | struct smu_11_0_dpm_context *dpm_context = | |||
1477 | smu->smu_dpm.dpm_context; | |||
1478 | struct smu_11_0_dpm_table *gfx_table = | |||
1479 | &dpm_context->dpm_tables.gfx_table; | |||
1480 | struct smu_11_0_dpm_table *mem_table = | |||
1481 | &dpm_context->dpm_tables.uclk_table; | |||
1482 | struct smu_11_0_dpm_table *soc_table = | |||
1483 | &dpm_context->dpm_tables.soc_table; | |||
1484 | struct smu_umd_pstate_table *pstate_table = | |||
1485 | &smu->pstate_table; | |||
1486 | struct amdgpu_device *adev = smu->adev; | |||
1487 | ||||
1488 | pstate_table->gfxclk_pstate.min = gfx_table->min; | |||
1489 | pstate_table->gfxclk_pstate.peak = gfx_table->max; | |||
1490 | ||||
1491 | pstate_table->uclk_pstate.min = mem_table->min; | |||
1492 | pstate_table->uclk_pstate.peak = mem_table->max; | |||
1493 | ||||
1494 | pstate_table->socclk_pstate.min = soc_table->min; | |||
1495 | pstate_table->socclk_pstate.peak = soc_table->max; | |||
1496 | ||||
1497 | switch (adev->ip_versions[MP1_HWIP][0]) { | |||
1498 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): | |||
1499 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): | |||
1500 | pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK1825; | |||
1501 | pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK1000; | |||
1502 | pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK960; | |||
1503 | break; | |||
1504 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): | |||
1505 | pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK1950; | |||
1506 | pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK676; | |||
1507 | pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK960; | |||
1508 | break; | |||
1509 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): | |||
1510 | pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK2200; | |||
1511 | pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK1000; | |||
1512 | pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK960; | |||
1513 | break; | |||
1514 | default: | |||
1515 | break; | |||
1516 | } | |||
1517 | ||||
1518 | return 0; | |||
1519 | } | |||
1520 | ||||
1521 | static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) | |||
1522 | { | |||
1523 | int ret = 0; | |||
1524 | uint32_t max_freq = 0; | |||
1525 | ||||
1526 | /* Sienna_Cichlid do not support to change display num currently */ | |||
1527 | return 0; | |||
1528 | #if 0 | |||
1529 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL((void *)0)); | |||
1530 | if (ret) | |||
1531 | return ret; | |||
1532 | #endif | |||
1533 | ||||
1534 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { | |||
1535 | ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL((void *)0), &max_freq); | |||
1536 | if (ret) | |||
1537 | return ret; | |||
1538 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); | |||
1539 | if (ret) | |||
1540 | return ret; | |||
1541 | } | |||
1542 | ||||
1543 | return ret; | |||
1544 | } | |||
1545 | ||||
1546 | static int sienna_cichlid_display_config_changed(struct smu_context *smu) | |||
1547 | { | |||
1548 | int ret = 0; | |||
1549 | ||||
1550 | if ((smu->watermarks_bitmap & WATERMARKS_EXIST(1 << 0)) && | |||
1551 | smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && | |||
1552 | smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { | |||
1553 | #if 0 | |||
1554 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, | |||
1555 | smu->display_config->num_display, | |||
1556 | NULL((void *)0)); | |||
1557 | #endif | |||
1558 | if (ret) | |||
1559 | return ret; | |||
1560 | } | |||
1561 | ||||
1562 | return ret; | |||
1563 | } | |||
1564 | ||||
1565 | static bool_Bool sienna_cichlid_is_dpm_running(struct smu_context *smu) | |||
1566 | { | |||
1567 | int ret = 0; | |||
1568 | uint64_t feature_enabled; | |||
1569 | ||||
1570 | ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); | |||
1571 | if (ret) | |||
1572 | return false0; | |||
1573 | ||||
1574 | return !!(feature_enabled & SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 1) | (1ULL << 3) | (1ULL << 7) | (1ULL << 5) | (1ULL << 4) | ( 1ULL << 8) | (1ULL << 6))); | |||
1575 | } | |||
1576 | ||||
1577 | static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, | |||
1578 | uint32_t *speed) | |||
1579 | { | |||
1580 | if (!speed) | |||
1581 | return -EINVAL22; | |||
1582 | ||||
1583 | /* | |||
1584 | * For Sienna_Cichlid and later, the fan speed(rpm) reported | |||
1585 | * by pmfw is always trustable(even when the fan control feature | |||
1586 | * disabled or 0 RPM kicked in). | |||
1587 | */ | |||
1588 | return sienna_cichlid_get_smu_metrics_data(smu, | |||
1589 | METRICS_CURR_FANSPEED, | |||
1590 | speed); | |||
1591 | } | |||
1592 | ||||
1593 | static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) | |||
1594 | { | |||
1595 | uint16_t *table_member; | |||
1596 | ||||
1597 | GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , FanMaximumRpm)); else (*&table_member) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, FanMaximumRpm ));} while(0); | |||
1598 | smu->fan_max_rpm = *table_member; | |||
1599 | ||||
1600 | return 0; | |||
1601 | } | |||
1602 | ||||
1603 | static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) | |||
1604 | { | |||
1605 | DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; | |||
1606 | DpmActivityMonitorCoeffInt_t *activity_monitor = | |||
1607 | &(activity_monitor_external.DpmActivityMonitorCoeffInt); | |||
1608 | uint32_t i, size = 0; | |||
1609 | int16_t workload_type = 0; | |||
1610 | static const char *title[] = { | |||
1611 | "PROFILE_INDEX(NAME)", | |||
1612 | "CLOCK_TYPE(NAME)", | |||
1613 | "FPS", | |||
1614 | "MinFreqType", | |||
1615 | "MinActiveFreqType", | |||
1616 | "MinActiveFreq", | |||
1617 | "BoosterFreqType", | |||
1618 | "BoosterFreq", | |||
1619 | "PD_Data_limit_c", | |||
1620 | "PD_Data_error_coeff", | |||
1621 | "PD_Data_error_rate_coeff"}; | |||
1622 | int result = 0; | |||
1623 | ||||
1624 | if (!buf) | |||
1625 | return -EINVAL22; | |||
1626 | ||||
1627 | size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", | |||
1628 | title[0], title[1], title[2], title[3], title[4], title[5], | |||
1629 | title[6], title[7], title[8], title[9], title[10]); | |||
1630 | ||||
1631 | for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { | |||
1632 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |||
1633 | workload_type = smu_cmn_to_asic_specific_index(smu, | |||
1634 | CMN2ASIC_MAPPING_WORKLOAD, | |||
1635 | i); | |||
1636 | if (workload_type < 0) | |||
1637 | return -EINVAL22; | |||
1638 | ||||
1639 | result = smu_cmn_update_table(smu, | |||
1640 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, | |||
1641 | (void *)(&activity_monitor_external), false0); | |||
1642 | if (result) { | |||
1643 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); | |||
1644 | return result; | |||
1645 | } | |||
1646 | ||||
1647 | size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", | |||
1648 | i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); | |||
1649 | ||||
1650 | size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |||
1651 | " ", | |||
1652 | 0, | |||
1653 | "GFXCLK", | |||
1654 | activity_monitor->Gfx_FPS, | |||
1655 | activity_monitor->Gfx_MinFreqStep, | |||
1656 | activity_monitor->Gfx_MinActiveFreqType, | |||
1657 | activity_monitor->Gfx_MinActiveFreq, | |||
1658 | activity_monitor->Gfx_BoosterFreqType, | |||
1659 | activity_monitor->Gfx_BoosterFreq, | |||
1660 | activity_monitor->Gfx_PD_Data_limit_c, | |||
1661 | activity_monitor->Gfx_PD_Data_error_coeff, | |||
1662 | activity_monitor->Gfx_PD_Data_error_rate_coeff); | |||
1663 | ||||
1664 | size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |||
1665 | " ", | |||
1666 | 1, | |||
1667 | "SOCCLK", | |||
1668 | activity_monitor->Fclk_FPS, | |||
1669 | activity_monitor->Fclk_MinFreqStep, | |||
1670 | activity_monitor->Fclk_MinActiveFreqType, | |||
1671 | activity_monitor->Fclk_MinActiveFreq, | |||
1672 | activity_monitor->Fclk_BoosterFreqType, | |||
1673 | activity_monitor->Fclk_BoosterFreq, | |||
1674 | activity_monitor->Fclk_PD_Data_limit_c, | |||
1675 | activity_monitor->Fclk_PD_Data_error_coeff, | |||
1676 | activity_monitor->Fclk_PD_Data_error_rate_coeff); | |||
1677 | ||||
1678 | size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", | |||
1679 | " ", | |||
1680 | 2, | |||
1681 | "MEMLK", | |||
1682 | activity_monitor->Mem_FPS, | |||
1683 | activity_monitor->Mem_MinFreqStep, | |||
1684 | activity_monitor->Mem_MinActiveFreqType, | |||
1685 | activity_monitor->Mem_MinActiveFreq, | |||
1686 | activity_monitor->Mem_BoosterFreqType, | |||
1687 | activity_monitor->Mem_BoosterFreq, | |||
1688 | activity_monitor->Mem_PD_Data_limit_c, | |||
1689 | activity_monitor->Mem_PD_Data_error_coeff, | |||
1690 | activity_monitor->Mem_PD_Data_error_rate_coeff); | |||
1691 | } | |||
1692 | ||||
1693 | return size; | |||
1694 | } | |||
1695 | ||||
1696 | static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) | |||
1697 | { | |||
1698 | ||||
1699 | DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; | |||
1700 | DpmActivityMonitorCoeffInt_t *activity_monitor = | |||
1701 | &(activity_monitor_external.DpmActivityMonitorCoeffInt); | |||
1702 | int workload_type, ret = 0; | |||
1703 | ||||
1704 | smu->power_profile_mode = input[size]; | |||
1705 | ||||
1706 | if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { | |||
1707 | dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode)printf("drm:pid%d:%s *ERROR* " "Invalid power profile mode %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , smu-> power_profile_mode); | |||
1708 | return -EINVAL22; | |||
1709 | } | |||
1710 | ||||
1711 | if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { | |||
1712 | ||||
1713 | ret = smu_cmn_update_table(smu, | |||
1714 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT6, | |||
1715 | (void *)(&activity_monitor_external), false0); | |||
1716 | if (ret) { | |||
1717 | dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); | |||
1718 | return ret; | |||
1719 | } | |||
1720 | ||||
1721 | switch (input[0]) { | |||
1722 | case 0: /* Gfxclk */ | |||
1723 | activity_monitor->Gfx_FPS = input[1]; | |||
1724 | activity_monitor->Gfx_MinFreqStep = input[2]; | |||
1725 | activity_monitor->Gfx_MinActiveFreqType = input[3]; | |||
1726 | activity_monitor->Gfx_MinActiveFreq = input[4]; | |||
1727 | activity_monitor->Gfx_BoosterFreqType = input[5]; | |||
1728 | activity_monitor->Gfx_BoosterFreq = input[6]; | |||
1729 | activity_monitor->Gfx_PD_Data_limit_c = input[7]; | |||
1730 | activity_monitor->Gfx_PD_Data_error_coeff = input[8]; | |||
1731 | activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; | |||
1732 | break; | |||
1733 | case 1: /* Socclk */ | |||
1734 | activity_monitor->Fclk_FPS = input[1]; | |||
1735 | activity_monitor->Fclk_MinFreqStep = input[2]; | |||
1736 | activity_monitor->Fclk_MinActiveFreqType = input[3]; | |||
1737 | activity_monitor->Fclk_MinActiveFreq = input[4]; | |||
1738 | activity_monitor->Fclk_BoosterFreqType = input[5]; | |||
1739 | activity_monitor->Fclk_BoosterFreq = input[6]; | |||
1740 | activity_monitor->Fclk_PD_Data_limit_c = input[7]; | |||
1741 | activity_monitor->Fclk_PD_Data_error_coeff = input[8]; | |||
1742 | activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; | |||
1743 | break; | |||
1744 | case 2: /* Memlk */ | |||
1745 | activity_monitor->Mem_FPS = input[1]; | |||
1746 | activity_monitor->Mem_MinFreqStep = input[2]; | |||
1747 | activity_monitor->Mem_MinActiveFreqType = input[3]; | |||
1748 | activity_monitor->Mem_MinActiveFreq = input[4]; | |||
1749 | activity_monitor->Mem_BoosterFreqType = input[5]; | |||
1750 | activity_monitor->Mem_BoosterFreq = input[6]; | |||
1751 | activity_monitor->Mem_PD_Data_limit_c = input[7]; | |||
1752 | activity_monitor->Mem_PD_Data_error_coeff = input[8]; | |||
1753 | activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; | |||
1754 | break; | |||
1755 | } | |||
1756 | ||||
1757 | ret = smu_cmn_update_table(smu, | |||
1758 | SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT6, | |||
1759 | (void *)(&activity_monitor_external), true1); | |||
1760 | if (ret) { | |||
1761 | dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to set activity monitor!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); | |||
1762 | return ret; | |||
1763 | } | |||
1764 | } | |||
1765 | ||||
1766 | /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ | |||
1767 | workload_type = smu_cmn_to_asic_specific_index(smu, | |||
1768 | CMN2ASIC_MAPPING_WORKLOAD, | |||
1769 | smu->power_profile_mode); | |||
1770 | if (workload_type < 0) | |||
1771 | return -EINVAL22; | |||
1772 | smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, | |||
1773 | 1 << workload_type, NULL((void *)0)); | |||
1774 | ||||
1775 | return ret; | |||
1776 | } | |||
1777 | ||||
1778 | static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) | |||
1779 | { | |||
1780 | struct smu_clocks min_clocks = {0}; | |||
1781 | struct pp_display_clock_request clock_req; | |||
1782 | int ret = 0; | |||
1783 | ||||
1784 | min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; | |||
1785 | min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; | |||
1786 | min_clocks.memory_clock = smu->display_config->min_mem_set_clock; | |||
1787 | ||||
1788 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { | |||
1789 | clock_req.clock_type = amd_pp_dcef_clock; | |||
1790 | clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; | |||
1791 | ||||
1792 | ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); | |||
1793 | if (!ret) { | |||
1794 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { | |||
1795 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
1796 | SMU_MSG_SetMinDeepSleepDcefclk, | |||
1797 | min_clocks.dcef_clock_in_sr/100, | |||
1798 | NULL((void *)0)); | |||
1799 | if (ret) { | |||
1800 | dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to set divider for DCEFCLK Failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
1801 | return ret; | |||
1802 | } | |||
1803 | } | |||
1804 | } else { | |||
1805 | dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!")do { } while(0); | |||
1806 | } | |||
1807 | } | |||
1808 | ||||
1809 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { | |||
1810 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); | |||
1811 | if (ret) { | |||
1812 | dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Set hard min uclk failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); | |||
1813 | return ret; | |||
1814 | } | |||
1815 | } | |||
1816 | ||||
1817 | return 0; | |||
1818 | } | |||
1819 | ||||
1820 | static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, | |||
1821 | struct pp_smu_wm_range_sets *clock_ranges) | |||
1822 | { | |||
1823 | Watermarks_t *table = smu->smu_table.watermarks_table; | |||
1824 | int ret = 0; | |||
1825 | int i; | |||
1826 | ||||
1827 | if (clock_ranges) { | |||
1828 | if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES4 || | |||
1829 | clock_ranges->num_writer_wm_sets > NUM_WM_RANGES4) | |||
1830 | return -EINVAL22; | |||
1831 | ||||
1832 | for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { | |||
1833 | table->WatermarkRow[WM_DCEFCLK][i].MinClock = | |||
1834 | clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; | |||
1835 | table->WatermarkRow[WM_DCEFCLK][i].MaxClock = | |||
1836 | clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; | |||
1837 | table->WatermarkRow[WM_DCEFCLK][i].MinUclk = | |||
1838 | clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; | |||
1839 | table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = | |||
1840 | clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; | |||
1841 | ||||
1842 | table->WatermarkRow[WM_DCEFCLK][i].WmSetting = | |||
1843 | clock_ranges->reader_wm_sets[i].wm_inst; | |||
1844 | } | |||
1845 | ||||
1846 | for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { | |||
1847 | table->WatermarkRow[WM_SOCCLK][i].MinClock = | |||
1848 | clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; | |||
1849 | table->WatermarkRow[WM_SOCCLK][i].MaxClock = | |||
1850 | clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; | |||
1851 | table->WatermarkRow[WM_SOCCLK][i].MinUclk = | |||
1852 | clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; | |||
1853 | table->WatermarkRow[WM_SOCCLK][i].MaxUclk = | |||
1854 | clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; | |||
1855 | ||||
1856 | table->WatermarkRow[WM_SOCCLK][i].WmSetting = | |||
1857 | clock_ranges->writer_wm_sets[i].wm_inst; | |||
1858 | } | |||
1859 | ||||
1860 | smu->watermarks_bitmap |= WATERMARKS_EXIST(1 << 0); | |||
1861 | } | |||
1862 | ||||
1863 | if ((smu->watermarks_bitmap & WATERMARKS_EXIST(1 << 0)) && | |||
1864 | !(smu->watermarks_bitmap & WATERMARKS_LOADED(1 << 1))) { | |||
1865 | ret = smu_cmn_write_watermarks_table(smu); | |||
1866 | if (ret) { | |||
1867 | dev_err(smu->adev->dev, "Failed to update WMTABLE!")printf("drm:pid%d:%s *ERROR* " "Failed to update WMTABLE!", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
1868 | return ret; | |||
1869 | } | |||
1870 | smu->watermarks_bitmap |= WATERMARKS_LOADED(1 << 1); | |||
1871 | } | |||
1872 | ||||
1873 | return 0; | |||
1874 | } | |||
1875 | ||||
1876 | static int sienna_cichlid_read_sensor(struct smu_context *smu, | |||
1877 | enum amd_pp_sensors sensor, | |||
1878 | void *data, uint32_t *size) | |||
1879 | { | |||
1880 | int ret = 0; | |||
1881 | uint16_t *temp; | |||
1882 | struct amdgpu_device *adev = smu->adev; | |||
1883 | ||||
1884 | if(!data || !size) | |||
1885 | return -EINVAL22; | |||
1886 | ||||
1887 | switch (sensor) { | |||
1888 | case AMDGPU_PP_SENSOR_MAX_FAN_RPM: | |||
1889 | GET_PPTABLE_MEMBER(FanMaximumRpm, &temp)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&temp) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_beige_goby_t, FanMaximumRpm )); else (*&temp) = (smu->smu_table.driver_pptable + __builtin_offsetof (PPTable_t, FanMaximumRpm));} while(0); | |||
1890 | *(uint16_t *)data = *temp; | |||
1891 | *size = 4; | |||
1892 | break; | |||
1893 | case AMDGPU_PP_SENSOR_MEM_LOAD: | |||
1894 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1895 | METRICS_AVERAGE_MEMACTIVITY, | |||
1896 | (uint32_t *)data); | |||
1897 | *size = 4; | |||
1898 | break; | |||
1899 | case AMDGPU_PP_SENSOR_GPU_LOAD: | |||
1900 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1901 | METRICS_AVERAGE_GFXACTIVITY, | |||
1902 | (uint32_t *)data); | |||
1903 | *size = 4; | |||
1904 | break; | |||
1905 | case AMDGPU_PP_SENSOR_GPU_POWER: | |||
1906 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1907 | METRICS_AVERAGE_SOCKETPOWER, | |||
1908 | (uint32_t *)data); | |||
1909 | *size = 4; | |||
1910 | break; | |||
1911 | case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: | |||
1912 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1913 | METRICS_TEMPERATURE_HOTSPOT, | |||
1914 | (uint32_t *)data); | |||
1915 | *size = 4; | |||
1916 | break; | |||
1917 | case AMDGPU_PP_SENSOR_EDGE_TEMP: | |||
1918 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1919 | METRICS_TEMPERATURE_EDGE, | |||
1920 | (uint32_t *)data); | |||
1921 | *size = 4; | |||
1922 | break; | |||
1923 | case AMDGPU_PP_SENSOR_MEM_TEMP: | |||
1924 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1925 | METRICS_TEMPERATURE_MEM, | |||
1926 | (uint32_t *)data); | |||
1927 | *size = 4; | |||
1928 | break; | |||
1929 | case AMDGPU_PP_SENSOR_GFX_MCLK: | |||
1930 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1931 | METRICS_CURR_UCLK, | |||
1932 | (uint32_t *)data); | |||
1933 | *(uint32_t *)data *= 100; | |||
1934 | *size = 4; | |||
1935 | break; | |||
1936 | case AMDGPU_PP_SENSOR_GFX_SCLK: | |||
1937 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1938 | METRICS_AVERAGE_GFXCLK, | |||
1939 | (uint32_t *)data); | |||
1940 | *(uint32_t *)data *= 100; | |||
1941 | *size = 4; | |||
1942 | break; | |||
1943 | case AMDGPU_PP_SENSOR_VDDGFX: | |||
1944 | ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); | |||
1945 | *size = 4; | |||
1946 | break; | |||
1947 | case AMDGPU_PP_SENSOR_SS_APU_SHARE: | |||
1948 | if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) { | |||
1949 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1950 | METRICS_SS_APU_SHARE, (uint32_t *)data); | |||
1951 | *size = 4; | |||
1952 | } else { | |||
1953 | ret = -EOPNOTSUPP45; | |||
1954 | } | |||
1955 | break; | |||
1956 | case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: | |||
1957 | if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) { | |||
1958 | ret = sienna_cichlid_get_smu_metrics_data(smu, | |||
1959 | METRICS_SS_DGPU_SHARE, (uint32_t *)data); | |||
1960 | *size = 4; | |||
1961 | } else { | |||
1962 | ret = -EOPNOTSUPP45; | |||
1963 | } | |||
1964 | break; | |||
1965 | default: | |||
1966 | ret = -EOPNOTSUPP45; | |||
1967 | break; | |||
1968 | } | |||
1969 | ||||
1970 | return ret; | |||
1971 | } | |||
1972 | ||||
1973 | static void sienna_cichlid_get_unique_id(struct smu_context *smu) | |||
1974 | { | |||
1975 | struct amdgpu_device *adev = smu->adev; | |||
1976 | uint32_t upper32 = 0, lower32 = 0; | |||
1977 | ||||
1978 | /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */ | |||
1979 | if (smu->smc_fw_version < 0x3A5300 || | |||
1980 | smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) | |||
1981 | return; | |||
1982 | ||||
1983 | if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) | |||
1984 | goto out; | |||
1985 | if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) | |||
1986 | goto out; | |||
1987 | ||||
1988 | out: | |||
1989 | ||||
1990 | adev->unique_id = ((uint64_t)upper32 << 32) | lower32; | |||
1991 | if (adev->serial[0] == '\0') | |||
1992 | snprintf(adev->serial, sizeof(adev->serial), "%016llx", adev->unique_id); | |||
1993 | } | |||
1994 | ||||
1995 | static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) | |||
1996 | { | |||
1997 | uint32_t num_discrete_levels = 0; | |||
1998 | uint16_t *dpm_levels = NULL((void *)0); | |||
1999 | uint16_t i = 0; | |||
2000 | struct smu_table_context *table_context = &smu->smu_table; | |||
2001 | DpmDescriptor_t *table_member1; | |||
2002 | uint16_t *table_member2; | |||
2003 | ||||
2004 | if (!clocks_in_khz || !num_states || !table_context->driver_pptable) | |||
2005 | return -EINVAL22; | |||
2006 | ||||
2007 | GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member1) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , DpmDescriptor)); else (*&table_member1) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, DpmDescriptor ));} while(0); | |||
2008 | num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; | |||
2009 | GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member2) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , FreqTableUclk)); else (*&table_member2) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, FreqTableUclk ));} while(0); | |||
2010 | dpm_levels = table_member2; | |||
2011 | ||||
2012 | if (num_discrete_levels == 0 || dpm_levels == NULL((void *)0)) | |||
2013 | return -EINVAL22; | |||
2014 | ||||
2015 | *num_states = num_discrete_levels; | |||
2016 | for (i = 0; i < num_discrete_levels; i++) { | |||
2017 | /* convert to khz */ | |||
2018 | *clocks_in_khz = (*dpm_levels) * 1000; | |||
2019 | clocks_in_khz++; | |||
2020 | dpm_levels++; | |||
2021 | } | |||
2022 | ||||
2023 | return 0; | |||
2024 | } | |||
2025 | ||||
2026 | static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, | |||
2027 | struct smu_temperature_range *range) | |||
2028 | { | |||
2029 | struct smu_table_context *table_context = &smu->smu_table; | |||
2030 | struct smu_11_0_7_powerplay_table *powerplay_table = | |||
2031 | table_context->power_play_table; | |||
2032 | uint16_t *table_member; | |||
2033 | uint16_t temp_edge, temp_hotspot, temp_mem; | |||
2034 | ||||
2035 | if (!range) | |||
2036 | return -EINVAL22; | |||
2037 | ||||
2038 | memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range))__builtin_memcpy((range), (&smu11_thermal_policy[0]), (sizeof (struct smu_temperature_range))); | |||
2039 | ||||
2040 | GET_PPTABLE_MEMBER(TemperatureLimit, &table_member)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member) = (smu-> smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , TemperatureLimit)); else (*&table_member) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, TemperatureLimit ));} while(0); | |||
2041 | temp_edge = table_member[TEMP_EDGE]; | |||
2042 | temp_hotspot = table_member[TEMP_HOTSPOT]; | |||
2043 | temp_mem = table_member[TEMP_MEM]; | |||
2044 | ||||
2045 | range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2046 | range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE5) * | |||
2047 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2048 | range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2049 | range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT5) * | |||
2050 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2051 | range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2052 | range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM5)* | |||
2053 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000; | |||
2054 | ||||
2055 | range->software_shutdown_temp = powerplay_table->software_shutdown_temp; | |||
2056 | ||||
2057 | return 0; | |||
2058 | } | |||
2059 | ||||
2060 | static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, | |||
2061 | bool_Bool disable_memory_clock_switch) | |||
2062 | { | |||
2063 | int ret = 0; | |||
2064 | struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = | |||
2065 | (struct smu_11_0_max_sustainable_clocks *) | |||
2066 | smu->smu_table.max_sustainable_clocks; | |||
2067 | uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; | |||
2068 | uint32_t max_memory_clock = max_sustainable_clocks->uclock; | |||
2069 | ||||
2070 | if(smu->disable_uclk_switch == disable_memory_clock_switch) | |||
2071 | return 0; | |||
2072 | ||||
2073 | if(disable_memory_clock_switch) | |||
2074 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); | |||
2075 | else | |||
2076 | ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); | |||
2077 | ||||
2078 | if(!ret) | |||
2079 | smu->disable_uclk_switch = disable_memory_clock_switch; | |||
2080 | ||||
2081 | return ret; | |||
2082 | } | |||
2083 | ||||
2084 | #ifndef MAX | |||
2085 | #define MAX(a, b)(((a)>(b))?(a):(b)) ((a) > (b) ? (a) : (b)) | |||
2086 | #endif | |||
2087 | ||||
2088 | static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, | |||
2089 | uint8_t pcie_gen_cap, | |||
2090 | uint8_t pcie_width_cap) | |||
2091 | { | |||
2092 | struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; | |||
2093 | struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; | |||
2094 | uint8_t *table_member1, *table_member2; | |||
2095 | uint8_t min_gen_speed, max_gen_speed; | |||
2096 | uint8_t min_lane_width, max_lane_width; | |||
2097 | uint32_t smu_pcie_arg; | |||
2098 | int ret, i; | |||
2099 | ||||
2100 | GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member1) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , PcieGenSpeed)); else (*&table_member1) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, PcieGenSpeed) );} while(0); | |||
2101 | GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&table_member2) = (smu ->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , PcieLaneCount)); else (*&table_member2) = (smu->smu_table .driver_pptable + __builtin_offsetof(PPTable_t, PcieLaneCount ));} while(0); | |||
2102 | ||||
2103 | min_gen_speed = MAX(0, table_member1[0])(((0)>(table_member1[0]))?(0):(table_member1[0])); | |||
2104 | max_gen_speed = MIN(pcie_gen_cap, table_member1[1])(((pcie_gen_cap)<(table_member1[1]))?(pcie_gen_cap):(table_member1 [1])); | |||
2105 | min_gen_speed = min_gen_speed > max_gen_speed ? | |||
2106 | max_gen_speed : min_gen_speed; | |||
2107 | min_lane_width = MAX(1, table_member2[0])(((1)>(table_member2[0]))?(1):(table_member2[0])); | |||
2108 | max_lane_width = MIN(pcie_width_cap, table_member2[1])(((pcie_width_cap)<(table_member2[1]))?(pcie_width_cap):(table_member2 [1])); | |||
2109 | min_lane_width = min_lane_width > max_lane_width ? | |||
2110 | max_lane_width : min_lane_width; | |||
2111 | ||||
2112 | if (!amdgpu_device_pcie_dynamic_switching_supported()) { | |||
2113 | pcie_table->pcie_gen[0] = max_gen_speed; | |||
2114 | pcie_table->pcie_lane[0] = max_lane_width; | |||
2115 | } else { | |||
2116 | pcie_table->pcie_gen[0] = min_gen_speed; | |||
2117 | pcie_table->pcie_lane[0] = min_lane_width; | |||
2118 | } | |||
2119 | pcie_table->pcie_gen[1] = max_gen_speed; | |||
2120 | pcie_table->pcie_lane[1] = max_lane_width; | |||
2121 | ||||
2122 | for (i = 0; i < NUM_LINK_LEVELS2; i++) { | |||
2123 | smu_pcie_arg = (i << 16 | | |||
2124 | pcie_table->pcie_gen[i] << 8 | | |||
2125 | pcie_table->pcie_lane[i]); | |||
2126 | ||||
2127 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
2128 | SMU_MSG_OverridePcieParameters, | |||
2129 | smu_pcie_arg, | |||
2130 | NULL((void *)0)); | |||
2131 | if (ret) | |||
2132 | return ret; | |||
2133 | } | |||
2134 | ||||
2135 | return 0; | |||
2136 | } | |||
2137 | ||||
2138 | static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, | |||
2139 | enum smu_clk_type clk_type, | |||
2140 | uint32_t *min, uint32_t *max) | |||
2141 | { | |||
2142 | return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); | |||
2143 | } | |||
2144 | ||||
2145 | static void sienna_cichlid_dump_od_table(struct smu_context *smu, | |||
2146 | OverDriveTable_t *od_table) | |||
2147 | { | |||
2148 | struct amdgpu_device *adev = smu->adev; | |||
2149 | uint32_t smu_version; | |||
2150 | ||||
2151 | dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,do { } while(0) | |||
2152 | od_table->GfxclkFmax)do { } while(0); | |||
2153 | dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,do { } while(0) | |||
2154 | od_table->UclkFmax)do { } while(0); | |||
2155 | ||||
2156 | smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
2157 | if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) && | |||
2158 | (smu_version < 0x003a2900))) | |||
2159 | dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset)do { } while(0); | |||
2160 | } | |||
2161 | ||||
2162 | static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) | |||
2163 | { | |||
2164 | OverDriveTable_t *od_table = | |||
2165 | (OverDriveTable_t *)smu->smu_table.overdrive_table; | |||
2166 | OverDriveTable_t *boot_od_table = | |||
2167 | (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; | |||
2168 | OverDriveTable_t *user_od_table = | |||
2169 | (OverDriveTable_t *)smu->smu_table.user_overdrive_table; | |||
2170 | OverDriveTable_t user_od_table_bak; | |||
2171 | int ret = 0; | |||
2172 | ||||
2173 | ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, | |||
2174 | 0, (void *)boot_od_table, false0); | |||
2175 | if (ret) { | |||
2176 | dev_err(smu->adev->dev, "Failed to get overdrive table!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get overdrive table!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2177 | return ret; | |||
2178 | } | |||
2179 | ||||
2180 | sienna_cichlid_dump_od_table(smu, boot_od_table); | |||
2181 | ||||
2182 | memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t))__builtin_memcpy((od_table), (boot_od_table), (sizeof(OverDriveTable_t ))); | |||
2183 | ||||
2184 | /* | |||
2185 | * For S3/S4/Runpm resume, we need to setup those overdrive tables again, | |||
2186 | * but we have to preserve user defined values in "user_od_table". | |||
2187 | */ | |||
2188 | if (!smu->adev->in_suspend) { | |||
2189 | memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t))__builtin_memcpy((user_od_table), (boot_od_table), (sizeof(OverDriveTable_t ))); | |||
2190 | smu->user_dpm_profile.user_od = false0; | |||
2191 | } else if (smu->user_dpm_profile.user_od) { | |||
2192 | memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t))__builtin_memcpy((&user_od_table_bak), (user_od_table), ( sizeof(OverDriveTable_t))); | |||
2193 | memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t))__builtin_memcpy((user_od_table), (boot_od_table), (sizeof(OverDriveTable_t ))); | |||
2194 | user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin; | |||
2195 | user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax; | |||
2196 | user_od_table->UclkFmin = user_od_table_bak.UclkFmin; | |||
2197 | user_od_table->UclkFmax = user_od_table_bak.UclkFmax; | |||
2198 | user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset; | |||
2199 | } | |||
2200 | ||||
2201 | return 0; | |||
2202 | } | |||
2203 | ||||
2204 | static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, | |||
2205 | struct smu_11_0_7_overdrive_table *od_table, | |||
2206 | enum SMU_11_0_7_ODSETTING_ID setting, | |||
2207 | uint32_t value) | |||
2208 | { | |||
2209 | if (value < od_table->min[setting]) { | |||
2210 | dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",printf("drm:pid%d:%s *WARNING* " "OD setting (%d, %d) is less than the minimum allowed (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , setting , value, od_table->min[setting]) | |||
2211 | setting, value, od_table->min[setting])printf("drm:pid%d:%s *WARNING* " "OD setting (%d, %d) is less than the minimum allowed (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , setting , value, od_table->min[setting]); | |||
2212 | return -EINVAL22; | |||
2213 | } | |||
2214 | if (value > od_table->max[setting]) { | |||
2215 | dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",printf("drm:pid%d:%s *WARNING* " "OD setting (%d, %d) is greater than the maximum allowed (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , setting , value, od_table->max[setting]) | |||
2216 | setting, value, od_table->max[setting])printf("drm:pid%d:%s *WARNING* " "OD setting (%d, %d) is greater than the maximum allowed (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , setting , value, od_table->max[setting]); | |||
2217 | return -EINVAL22; | |||
2218 | } | |||
2219 | ||||
2220 | return 0; | |||
2221 | } | |||
2222 | ||||
2223 | static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, | |||
2224 | enum PP_OD_DPM_TABLE_COMMAND type, | |||
2225 | long input[], uint32_t size) | |||
2226 | { | |||
2227 | struct smu_table_context *table_context = &smu->smu_table; | |||
2228 | OverDriveTable_t *od_table = | |||
2229 | (OverDriveTable_t *)table_context->overdrive_table; | |||
2230 | struct smu_11_0_7_overdrive_table *od_settings = | |||
2231 | (struct smu_11_0_7_overdrive_table *)smu->od_settings; | |||
2232 | struct amdgpu_device *adev = smu->adev; | |||
2233 | enum SMU_11_0_7_ODSETTING_ID freq_setting; | |||
2234 | uint16_t *freq_ptr; | |||
2235 | int i, ret = 0; | |||
2236 | uint32_t smu_version; | |||
2237 | ||||
2238 | if (!smu->od_enabled) { | |||
2239 | dev_warn(smu->adev->dev, "OverDrive is not enabled!\n")printf("drm:pid%d:%s *WARNING* " "OverDrive is not enabled!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2240 | return -EINVAL22; | |||
2241 | } | |||
2242 | ||||
2243 | if (!smu->od_settings) { | |||
2244 | dev_err(smu->adev->dev, "OD board limits are not set!\n")printf("drm:pid%d:%s *ERROR* " "OD board limits are not set!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2245 | return -ENOENT2; | |||
2246 | } | |||
2247 | ||||
2248 | if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { | |||
2249 | dev_err(smu->adev->dev, "Overdrive table was not initialized!\n")printf("drm:pid%d:%s *ERROR* " "Overdrive table was not initialized!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2250 | return -EINVAL22; | |||
2251 | } | |||
2252 | ||||
2253 | switch (type) { | |||
2254 | case PP_OD_EDIT_SCLK_VDDC_TABLE: | |||
2255 | if (!sienna_cichlid_is_od_feature_supported(od_settings, | |||
2256 | SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { | |||
2257 | dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n")printf("drm:pid%d:%s *WARNING* " "GFXCLK_LIMITS not supported!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2258 | return -ENOTSUPP91; | |||
2259 | } | |||
2260 | ||||
2261 | for (i = 0; i < size; i += 2) { | |||
2262 | if (i + 2 > size) { | |||
2263 | dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size)do { } while(0); | |||
2264 | return -EINVAL22; | |||
2265 | } | |||
2266 | ||||
2267 | switch (input[i]) { | |||
2268 | case 0: | |||
2269 | if (input[i + 1] > od_table->GfxclkFmax) { | |||
2270 | dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",do { } while(0) | |||
2271 | input[i + 1], od_table->GfxclkFmax)do { } while(0); | |||
2272 | return -EINVAL22; | |||
2273 | } | |||
2274 | ||||
2275 | freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; | |||
2276 | freq_ptr = &od_table->GfxclkFmin; | |||
2277 | break; | |||
2278 | ||||
2279 | case 1: | |||
2280 | if (input[i + 1] < od_table->GfxclkFmin) { | |||
2281 | dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",do { } while(0) | |||
2282 | input[i + 1], od_table->GfxclkFmin)do { } while(0); | |||
2283 | return -EINVAL22; | |||
2284 | } | |||
2285 | ||||
2286 | freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; | |||
2287 | freq_ptr = &od_table->GfxclkFmax; | |||
2288 | break; | |||
2289 | ||||
2290 | default: | |||
2291 | dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i])do { } while(0); | |||
2292 | dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n")do { } while(0); | |||
2293 | return -EINVAL22; | |||
2294 | } | |||
2295 | ||||
2296 | ret = sienna_cichlid_od_setting_check_range(smu, od_settings, | |||
2297 | freq_setting, input[i + 1]); | |||
2298 | if (ret) | |||
2299 | return ret; | |||
2300 | ||||
2301 | *freq_ptr = (uint16_t)input[i + 1]; | |||
2302 | } | |||
2303 | break; | |||
2304 | ||||
2305 | case PP_OD_EDIT_MCLK_VDDC_TABLE: | |||
2306 | if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { | |||
2307 | dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n")printf("drm:pid%d:%s *WARNING* " "UCLK_LIMITS not supported!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2308 | return -ENOTSUPP91; | |||
2309 | } | |||
2310 | ||||
2311 | for (i = 0; i < size; i += 2) { | |||
2312 | if (i + 2 > size) { | |||
2313 | dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size)do { } while(0); | |||
2314 | return -EINVAL22; | |||
2315 | } | |||
2316 | ||||
2317 | switch (input[i]) { | |||
2318 | case 0: | |||
2319 | if (input[i + 1] > od_table->UclkFmax) { | |||
2320 | dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",do { } while(0) | |||
2321 | input[i + 1], od_table->UclkFmax)do { } while(0); | |||
2322 | return -EINVAL22; | |||
2323 | } | |||
2324 | ||||
2325 | freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; | |||
2326 | freq_ptr = &od_table->UclkFmin; | |||
2327 | break; | |||
2328 | ||||
2329 | case 1: | |||
2330 | if (input[i + 1] < od_table->UclkFmin) { | |||
2331 | dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",do { } while(0) | |||
2332 | input[i + 1], od_table->UclkFmin)do { } while(0); | |||
2333 | return -EINVAL22; | |||
2334 | } | |||
2335 | ||||
2336 | freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; | |||
2337 | freq_ptr = &od_table->UclkFmax; | |||
2338 | break; | |||
2339 | ||||
2340 | default: | |||
2341 | dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i])do { } while(0); | |||
2342 | dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n")do { } while(0); | |||
2343 | return -EINVAL22; | |||
2344 | } | |||
2345 | ||||
2346 | ret = sienna_cichlid_od_setting_check_range(smu, od_settings, | |||
2347 | freq_setting, input[i + 1]); | |||
2348 | if (ret) | |||
2349 | return ret; | |||
2350 | ||||
2351 | *freq_ptr = (uint16_t)input[i + 1]; | |||
2352 | } | |||
2353 | break; | |||
2354 | ||||
2355 | case PP_OD_RESTORE_DEFAULT_TABLE: | |||
2356 | memcpy(table_context->overdrive_table,__builtin_memcpy((table_context->overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t))) | |||
2357 | table_context->boot_overdrive_table,__builtin_memcpy((table_context->overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t))) | |||
2358 | sizeof(OverDriveTable_t))__builtin_memcpy((table_context->overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t))); | |||
2359 | fallthroughdo {} while (0); | |||
2360 | ||||
2361 | case PP_OD_COMMIT_DPM_TABLE: | |||
2362 | if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))__builtin_memcmp((od_table), (table_context->user_overdrive_table ), (sizeof(OverDriveTable_t)))) { | |||
2363 | sienna_cichlid_dump_od_table(smu, od_table); | |||
2364 | ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true1); | |||
2365 | if (ret) { | |||
2366 | dev_err(smu->adev->dev, "Failed to import overdrive table!\n")printf("drm:pid%d:%s *ERROR* " "Failed to import overdrive table!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); | |||
2367 | return ret; | |||
2368 | } | |||
2369 | memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t))__builtin_memcpy((table_context->user_overdrive_table), (od_table ), (sizeof(OverDriveTable_t))); | |||
2370 | smu->user_dpm_profile.user_od = true1; | |||
2371 | ||||
2372 | if (!memcmp(table_context->user_overdrive_table,__builtin_memcmp((table_context->user_overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t))) | |||
2373 | table_context->boot_overdrive_table,__builtin_memcmp((table_context->user_overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t))) | |||
2374 | sizeof(OverDriveTable_t))__builtin_memcmp((table_context->user_overdrive_table), (table_context ->boot_overdrive_table), (sizeof(OverDriveTable_t)))) | |||
2375 | smu->user_dpm_profile.user_od = false0; | |||
2376 | } | |||
2377 | break; | |||
2378 | ||||
2379 | case PP_OD_EDIT_VDDGFX_OFFSET: | |||
2380 | if (size != 1) { | |||
2381 | dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size)do { } while(0); | |||
2382 | return -EINVAL22; | |||
2383 | } | |||
2384 | ||||
2385 | /* | |||
2386 | * OD GFX Voltage Offset functionality is supported only by 58.41.0 | |||
2387 | * and onwards SMU firmwares. | |||
2388 | */ | |||
2389 | smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
2390 | if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) && | |||
2391 | (smu_version < 0x003a2900)) { | |||
2392 | dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "printf("drm:pid%d:%s *ERROR* " "OD GFX Voltage offset functionality is supported " "only by 58.41.0 and onwards SMU firmwares!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p-> ps_pid, __func__) | |||
2393 | "only by 58.41.0 and onwards SMU firmwares!\n")printf("drm:pid%d:%s *ERROR* " "OD GFX Voltage offset functionality is supported " "only by 58.41.0 and onwards SMU firmwares!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p-> ps_pid, __func__); | |||
2394 | return -EOPNOTSUPP45; | |||
2395 | } | |||
2396 | ||||
2397 | od_table->VddGfxOffset = (int16_t)input[0]; | |||
2398 | ||||
2399 | sienna_cichlid_dump_od_table(smu, od_table); | |||
2400 | break; | |||
2401 | ||||
2402 | default: | |||
2403 | return -ENOSYS78; | |||
2404 | } | |||
2405 | ||||
2406 | return ret; | |||
2407 | } | |||
2408 | ||||
2409 | static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu) | |||
2410 | { | |||
2411 | struct smu_table_context *table_context = &smu->smu_table; | |||
2412 | OverDriveTable_t *od_table = table_context->overdrive_table; | |||
2413 | OverDriveTable_t *user_od_table = table_context->user_overdrive_table; | |||
2414 | int res; | |||
2415 | ||||
2416 | res = smu_v11_0_restore_user_od_settings(smu); | |||
2417 | if (res == 0) | |||
2418 | memcpy(od_table, user_od_table, sizeof(OverDriveTable_t))__builtin_memcpy((od_table), (user_od_table), (sizeof(OverDriveTable_t ))); | |||
2419 | ||||
2420 | return res; | |||
2421 | } | |||
2422 | ||||
2423 | static int sienna_cichlid_run_btc(struct smu_context *smu) | |||
2424 | { | |||
2425 | int res; | |||
2426 | ||||
2427 | res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL((void *)0)); | |||
2428 | if (res) | |||
2429 | dev_err(smu->adev->dev, "RunDcBtc failed!\n")printf("drm:pid%d:%s *ERROR* " "RunDcBtc failed!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); | |||
2430 | ||||
2431 | return res; | |||
2432 | } | |||
2433 | ||||
2434 | static int sienna_cichlid_baco_enter(struct smu_context *smu) | |||
2435 | { | |||
2436 | struct amdgpu_device *adev = smu->adev; | |||
2437 | ||||
2438 | if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) | |||
2439 | return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); | |||
2440 | else | |||
2441 | return smu_v11_0_baco_enter(smu); | |||
2442 | } | |||
2443 | ||||
2444 | static int sienna_cichlid_baco_exit(struct smu_context *smu) | |||
2445 | { | |||
2446 | struct amdgpu_device *adev = smu->adev; | |||
2447 | ||||
2448 | if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { | |||
2449 | /* Wait for PMFW handling for the Dstate change */ | |||
2450 | drm_msleep(10)mdelay(10); | |||
2451 | return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); | |||
2452 | } else { | |||
2453 | return smu_v11_0_baco_exit(smu); | |||
2454 | } | |||
2455 | } | |||
2456 | ||||
2457 | static bool_Bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) | |||
2458 | { | |||
2459 | struct amdgpu_device *adev = smu->adev; | |||
2460 | uint32_t val; | |||
2461 | u32 smu_version; | |||
2462 | ||||
2463 | /** | |||
2464 | * SRIOV env will not support SMU mode1 reset | |||
2465 | * PM FW support mode1 reset from 58.26 | |||
2466 | */ | |||
2467 | smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
2468 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) || (smu_version < 0x003a1a00)) | |||
2469 | return false0; | |||
2470 | ||||
2471 | /** | |||
2472 | * mode1 reset relies on PSP, so we should check if | |||
2473 | * PSP is alive. | |||
2474 | */ | |||
2475 | val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[MP0_HWIP][0][ 0] + 0x0091, 0, MP0_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[MP0_HWIP][0][0] + 0x0091), 0)); | |||
2476 | return val != 0x0; | |||
2477 | } | |||
2478 | ||||
2479 | static void beige_goby_dump_pptable(struct smu_context *smu) | |||
2480 | { | |||
2481 | struct smu_table_context *table_context = &smu->smu_table; | |||
2482 | PPTable_beige_goby_t *pptable = table_context->driver_pptable; | |||
2483 | int i; | |||
2484 | ||||
2485 | dev_info(smu->adev->dev, "Dumped PPTable:\n")do { } while(0); | |||
2486 | ||||
2487 | dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version)do { } while(0); | |||
2488 | dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0])do { } while(0); | |||
2489 | dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1])do { } while(0); | |||
2490 | ||||
2491 | for (i = 0; i < PPT_THROTTLER_COUNT; i++) { | |||
2492 | dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i])do { } while(0); | |||
2493 | dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i])do { } while(0); | |||
2494 | dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i])do { } while(0); | |||
2495 | dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i])do { } while(0); | |||
2496 | } | |||
2497 | ||||
2498 | for (i = 0; i < TDC_THROTTLER_COUNT; i++) { | |||
2499 | dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i])do { } while(0); | |||
2500 | dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i])do { } while(0); | |||
2501 | } | |||
2502 | ||||
2503 | for (i = 0; i < TEMP_COUNT; i++) { | |||
2504 | dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i])do { } while(0); | |||
2505 | } | |||
2506 | ||||
2507 | dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit)do { } while(0); | |||
2508 | dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig)do { } while(0); | |||
2509 | dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0])do { } while(0); | |||
2510 | dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1])do { } while(0); | |||
2511 | dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2])do { } while(0); | |||
2512 | ||||
2513 | dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit)do { } while(0); | |||
2514 | for (i = 0; i < NUM_SMNCLK_DPM_LEVELS2; i++) { | |||
2515 | dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i])do { } while(0); | |||
2516 | dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i])do { } while(0); | |||
2517 | } | |||
2518 | dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask)do { } while(0); | |||
2519 | ||||
2520 | dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask)do { } while(0); | |||
2521 | ||||
2522 | dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc)do { } while(0); | |||
2523 | dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx)do { } while(0); | |||
2524 | dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx)do { } while(0); | |||
2525 | dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc)do { } while(0); | |||
2526 | ||||
2527 | dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin)do { } while(0); | |||
2528 | ||||
2529 | dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold)do { } while(0); | |||
2530 | ||||
2531 | dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx)do { } while(0); | |||
2532 | dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc)do { } while(0); | |||
2533 | dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx)do { } while(0); | |||
2534 | dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc)do { } while(0); | |||
2535 | ||||
2536 | dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx)do { } while(0); | |||
2537 | dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc)do { } while(0); | |||
2538 | ||||
2539 | dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin)do { } while(0); | |||
2540 | dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin)do { } while(0); | |||
2541 | dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp)do { } while(0); | |||
2542 | dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp)do { } while(0); | |||
2543 | dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp)do { } while(0); | |||
2544 | dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp)do { } while(0); | |||
2545 | dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis)do { } while(0); | |||
2546 | dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis)do { } while(0); | |||
2547 | ||||
2548 | dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"do { } while(0) | |||
2549 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2550 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2551 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2552 | " .padding = 0x%02x\n"do { } while(0) | |||
2553 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2554 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2555 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2556 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2557 | pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,do { } while(0) | |||
2558 | pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,do { } while(0) | |||
2559 | pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,do { } while(0) | |||
2560 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,do { } while(0) | |||
2561 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,do { } while(0) | |||
2562 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,do { } while(0) | |||
2563 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,do { } while(0) | |||
2564 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,do { } while(0) | |||
2565 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,do { } while(0) | |||
2566 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,do { } while(0) | |||
2567 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16)do { } while(0); | |||
2568 | ||||
2569 | dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"do { } while(0) | |||
2570 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2571 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2572 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2573 | " .padding = 0x%02x\n"do { } while(0) | |||
2574 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2575 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2576 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2577 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2578 | pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,do { } while(0) | |||
2579 | pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,do { } while(0) | |||
2580 | pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,do { } while(0) | |||
2581 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,do { } while(0) | |||
2582 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,do { } while(0) | |||
2583 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,do { } while(0) | |||
2584 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,do { } while(0) | |||
2585 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,do { } while(0) | |||
2586 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,do { } while(0) | |||
2587 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,do { } while(0) | |||
2588 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16)do { } while(0); | |||
2589 | ||||
2590 | dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"do { } while(0) | |||
2591 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2592 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2593 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2594 | " .padding = 0x%02x\n"do { } while(0) | |||
2595 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2596 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2597 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2598 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2599 | pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,do { } while(0) | |||
2600 | pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,do { } while(0) | |||
2601 | pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,do { } while(0) | |||
2602 | pptable->DpmDescriptor[PPCLK_UCLK].Padding,do { } while(0) | |||
2603 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,do { } while(0) | |||
2604 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,do { } while(0) | |||
2605 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,do { } while(0) | |||
2606 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,do { } while(0) | |||
2607 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,do { } while(0) | |||
2608 | pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,do { } while(0) | |||
2609 | pptable->DpmDescriptor[PPCLK_UCLK].Padding16)do { } while(0); | |||
2610 | ||||
2611 | dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"do { } while(0) | |||
2612 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2613 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2614 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2615 | " .padding = 0x%02x\n"do { } while(0) | |||
2616 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2617 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2618 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2619 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2620 | pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,do { } while(0) | |||
2621 | pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,do { } while(0) | |||
2622 | pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,do { } while(0) | |||
2623 | pptable->DpmDescriptor[PPCLK_FCLK].Padding,do { } while(0) | |||
2624 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,do { } while(0) | |||
2625 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,do { } while(0) | |||
2626 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,do { } while(0) | |||
2627 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,do { } while(0) | |||
2628 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,do { } while(0) | |||
2629 | pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,do { } while(0) | |||
2630 | pptable->DpmDescriptor[PPCLK_FCLK].Padding16)do { } while(0); | |||
2631 | ||||
2632 | dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"do { } while(0) | |||
2633 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2634 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2635 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2636 | " .padding = 0x%02x\n"do { } while(0) | |||
2637 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2638 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2639 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2640 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2641 | pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,do { } while(0) | |||
2642 | pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,do { } while(0) | |||
2643 | pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,do { } while(0) | |||
2644 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,do { } while(0) | |||
2645 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,do { } while(0) | |||
2646 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,do { } while(0) | |||
2647 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,do { } while(0) | |||
2648 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,do { } while(0) | |||
2649 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,do { } while(0) | |||
2650 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,do { } while(0) | |||
2651 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16)do { } while(0); | |||
2652 | ||||
2653 | dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"do { } while(0) | |||
2654 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2655 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2656 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2657 | " .padding = 0x%02x\n"do { } while(0) | |||
2658 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2659 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2660 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2661 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2662 | pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,do { } while(0) | |||
2663 | pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,do { } while(0) | |||
2664 | pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,do { } while(0) | |||
2665 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,do { } while(0) | |||
2666 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,do { } while(0) | |||
2667 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,do { } while(0) | |||
2668 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,do { } while(0) | |||
2669 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,do { } while(0) | |||
2670 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,do { } while(0) | |||
2671 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,do { } while(0) | |||
2672 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16)do { } while(0); | |||
2673 | ||||
2674 | dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"do { } while(0) | |||
2675 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2676 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2677 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2678 | " .padding = 0x%02x\n"do { } while(0) | |||
2679 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2680 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2681 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2682 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2683 | pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,do { } while(0) | |||
2684 | pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,do { } while(0) | |||
2685 | pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,do { } while(0) | |||
2686 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,do { } while(0) | |||
2687 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,do { } while(0) | |||
2688 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,do { } while(0) | |||
2689 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,do { } while(0) | |||
2690 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,do { } while(0) | |||
2691 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,do { } while(0) | |||
2692 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,do { } while(0) | |||
2693 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16)do { } while(0); | |||
2694 | ||||
2695 | dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"do { } while(0) | |||
2696 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
2697 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
2698 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
2699 | " .padding = 0x%02x\n"do { } while(0) | |||
2700 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
2701 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
2702 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
2703 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
2704 | pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,do { } while(0) | |||
2705 | pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,do { } while(0) | |||
2706 | pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,do { } while(0) | |||
2707 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,do { } while(0) | |||
2708 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,do { } while(0) | |||
2709 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,do { } while(0) | |||
2710 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,do { } while(0) | |||
2711 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,do { } while(0) | |||
2712 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,do { } while(0) | |||
2713 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,do { } while(0) | |||
2714 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16)do { } while(0); | |||
2715 | ||||
2716 | dev_info(smu->adev->dev, "FreqTableGfx\n")do { } while(0); | |||
2717 | for (i = 0; i < NUM_GFXCLK_DPM_LEVELS16; i++) | |||
2718 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i])do { } while(0); | |||
2719 | ||||
2720 | dev_info(smu->adev->dev, "FreqTableVclk\n")do { } while(0); | |||
2721 | for (i = 0; i < NUM_VCLK_DPM_LEVELS8; i++) | |||
2722 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i])do { } while(0); | |||
2723 | ||||
2724 | dev_info(smu->adev->dev, "FreqTableDclk\n")do { } while(0); | |||
2725 | for (i = 0; i < NUM_DCLK_DPM_LEVELS8; i++) | |||
2726 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i])do { } while(0); | |||
2727 | ||||
2728 | dev_info(smu->adev->dev, "FreqTableSocclk\n")do { } while(0); | |||
2729 | for (i = 0; i < NUM_SOCCLK_DPM_LEVELS8; i++) | |||
2730 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i])do { } while(0); | |||
2731 | ||||
2732 | dev_info(smu->adev->dev, "FreqTableUclk\n")do { } while(0); | |||
2733 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
2734 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i])do { } while(0); | |||
2735 | ||||
2736 | dev_info(smu->adev->dev, "FreqTableFclk\n")do { } while(0); | |||
2737 | for (i = 0; i < NUM_FCLK_DPM_LEVELS8; i++) | |||
2738 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i])do { } while(0); | |||
2739 | ||||
2740 | dev_info(smu->adev->dev, "DcModeMaxFreq\n")do { } while(0); | |||
2741 | dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK])do { } while(0); | |||
2742 | dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK])do { } while(0); | |||
2743 | dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK])do { } while(0); | |||
2744 | dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK])do { } while(0); | |||
2745 | dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0])do { } while(0); | |||
2746 | dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0])do { } while(0); | |||
2747 | dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1])do { } while(0); | |||
2748 | dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1])do { } while(0); | |||
2749 | ||||
2750 | dev_info(smu->adev->dev, "FreqTableUclkDiv\n")do { } while(0); | |||
2751 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
2752 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i])do { } while(0); | |||
2753 | ||||
2754 | dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq)do { } while(0); | |||
2755 | dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding)do { } while(0); | |||
2756 | ||||
2757 | dev_info(smu->adev->dev, "Mp0clkFreq\n")do { } while(0); | |||
2758 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++) | |||
2759 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i])do { } while(0); | |||
2760 | ||||
2761 | dev_info(smu->adev->dev, "Mp0DpmVoltage\n")do { } while(0); | |||
2762 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++) | |||
2763 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i])do { } while(0); | |||
2764 | ||||
2765 | dev_info(smu->adev->dev, "MemVddciVoltage\n")do { } while(0); | |||
2766 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
2767 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i])do { } while(0); | |||
2768 | ||||
2769 | dev_info(smu->adev->dev, "MemMvddVoltage\n")do { } while(0); | |||
2770 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
2771 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i])do { } while(0); | |||
2772 | ||||
2773 | dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry)do { } while(0); | |||
2774 | dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit)do { } while(0); | |||
2775 | dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle)do { } while(0); | |||
2776 | dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource)do { } while(0); | |||
2777 | dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding)do { } while(0); | |||
2778 | ||||
2779 | dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask)do { } while(0); | |||
2780 | ||||
2781 | dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask)do { } while(0); | |||
2782 | dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask)do { } while(0); | |||
2783 | dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0])do { } while(0); | |||
2784 | dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow)do { } while(0); | |||
2785 | dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0])do { } while(0); | |||
2786 | dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1])do { } while(0); | |||
2787 | dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2])do { } while(0); | |||
2788 | dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3])do { } while(0); | |||
2789 | dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt)do { } while(0); | |||
2790 | dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt)do { } while(0); | |||
2791 | dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt)do { } while(0); | |||
2792 | ||||
2793 | dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage)do { } while(0); | |||
2794 | dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime)do { } while(0); | |||
2795 | dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime)do { } while(0); | |||
2796 | dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum)do { } while(0); | |||
2797 | dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis)do { } while(0); | |||
2798 | dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout)do { } while(0); | |||
2799 | ||||
2800 | dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0])do { } while(0); | |||
2801 | dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1])do { } while(0); | |||
2802 | dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2])do { } while(0); | |||
2803 | dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3])do { } while(0); | |||
2804 | dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4])do { } while(0); | |||
2805 | ||||
2806 | dev_info(smu->adev->dev, "FlopsPerByteTable\n")do { } while(0); | |||
2807 | for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS16; i++) | |||
2808 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i])do { } while(0); | |||
2809 | ||||
2810 | dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv)do { } while(0); | |||
2811 | dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0])do { } while(0); | |||
2812 | dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1])do { } while(0); | |||
2813 | dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2])do { } while(0); | |||
2814 | ||||
2815 | dev_info(smu->adev->dev, "UclkDpmPstates\n")do { } while(0); | |||
2816 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
2817 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i])do { } while(0); | |||
2818 | ||||
2819 | dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n")do { } while(0); | |||
2820 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0) | |||
2821 | pptable->UclkDpmSrcFreqRange.Fmin)do { } while(0); | |||
2822 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0) | |||
2823 | pptable->UclkDpmSrcFreqRange.Fmax)do { } while(0); | |||
2824 | dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n")do { } while(0); | |||
2825 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0) | |||
2826 | pptable->UclkDpmTargFreqRange.Fmin)do { } while(0); | |||
2827 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0) | |||
2828 | pptable->UclkDpmTargFreqRange.Fmax)do { } while(0); | |||
2829 | dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq)do { } while(0); | |||
2830 | dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding)do { } while(0); | |||
2831 | ||||
2832 | dev_info(smu->adev->dev, "PcieGenSpeed\n")do { } while(0); | |||
2833 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
2834 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i])do { } while(0); | |||
2835 | ||||
2836 | dev_info(smu->adev->dev, "PcieLaneCount\n")do { } while(0); | |||
2837 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
2838 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i])do { } while(0); | |||
2839 | ||||
2840 | dev_info(smu->adev->dev, "LclkFreq\n")do { } while(0); | |||
2841 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
2842 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i])do { } while(0); | |||
2843 | ||||
2844 | dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp)do { } while(0); | |||
2845 | dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp)do { } while(0); | |||
2846 | ||||
2847 | dev_info(smu->adev->dev, "FanGain\n")do { } while(0); | |||
2848 | for (i = 0; i < TEMP_COUNT; i++) | |||
2849 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i])do { } while(0); | |||
2850 | ||||
2851 | dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin)do { } while(0); | |||
2852 | dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm)do { } while(0); | |||
2853 | dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm)do { } while(0); | |||
2854 | dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm)do { } while(0); | |||
2855 | dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm)do { } while(0); | |||
2856 | dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature)do { } while(0); | |||
2857 | dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk)do { } while(0); | |||
2858 | dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16)do { } while(0); | |||
2859 | dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect)do { } while(0); | |||
2860 | dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding)do { } while(0); | |||
2861 | dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable)do { } while(0); | |||
2862 | dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev)do { } while(0); | |||
2863 | ||||
2864 | dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta)do { } while(0); | |||
2865 | dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta)do { } while(0); | |||
2866 | dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta)do { } while(0); | |||
2867 | dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved)do { } while(0); | |||
2868 | ||||
2869 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2870 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2871 | dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect)do { } while(0); | |||
2872 | dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs)do { } while(0); | |||
2873 | ||||
2874 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2875 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,do { } while(0) | |||
2876 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,do { } while(0) | |||
2877 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c)do { } while(0); | |||
2878 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2879 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,do { } while(0) | |||
2880 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,do { } while(0) | |||
2881 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c)do { } while(0); | |||
2882 | dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2883 | pptable->dBtcGbGfxPll.a,do { } while(0) | |||
2884 | pptable->dBtcGbGfxPll.b,do { } while(0) | |||
2885 | pptable->dBtcGbGfxPll.c)do { } while(0); | |||
2886 | dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2887 | pptable->dBtcGbGfxDfll.a,do { } while(0) | |||
2888 | pptable->dBtcGbGfxDfll.b,do { } while(0) | |||
2889 | pptable->dBtcGbGfxDfll.c)do { } while(0); | |||
2890 | dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2891 | pptable->dBtcGbSoc.a,do { } while(0) | |||
2892 | pptable->dBtcGbSoc.b,do { } while(0) | |||
2893 | pptable->dBtcGbSoc.c)do { } while(0); | |||
2894 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",do { } while(0) | |||
2895 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,do { } while(0) | |||
2896 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].b)do { } while(0); | |||
2897 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",do { } while(0) | |||
2898 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,do { } while(0) | |||
2899 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].b)do { } while(0); | |||
2900 | ||||
2901 | dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n")do { } while(0); | |||
2902 | for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS5; i++) { | |||
2903 | dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",do { } while(0) | |||
2904 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i])do { } while(0); | |||
2905 | dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",do { } while(0) | |||
2906 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i])do { } while(0); | |||
2907 | } | |||
2908 | ||||
2909 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2910 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,do { } while(0) | |||
2911 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,do { } while(0) | |||
2912 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c)do { } while(0); | |||
2913 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2914 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,do { } while(0) | |||
2915 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,do { } while(0) | |||
2916 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c)do { } while(0); | |||
2917 | ||||
2918 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2919 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2920 | ||||
2921 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2922 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2923 | dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0])do { } while(0); | |||
2924 | dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1])do { } while(0); | |||
2925 | ||||
2926 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2927 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2928 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2929 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2930 | ||||
2931 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX])do { } while(0); | |||
2932 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC])do { } while(0); | |||
2933 | ||||
2934 | dev_info(smu->adev->dev, "XgmiDpmPstates\n")do { } while(0); | |||
2935 | for (i = 0; i < NUM_XGMI_LEVELS2; i++) | |||
2936 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i])do { } while(0); | |||
2937 | dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0])do { } while(0); | |||
2938 | dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1])do { } while(0); | |||
2939 | ||||
2940 | dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides)do { } while(0); | |||
2941 | dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2942 | pptable->ReservedEquation0.a,do { } while(0) | |||
2943 | pptable->ReservedEquation0.b,do { } while(0) | |||
2944 | pptable->ReservedEquation0.c)do { } while(0); | |||
2945 | dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2946 | pptable->ReservedEquation1.a,do { } while(0) | |||
2947 | pptable->ReservedEquation1.b,do { } while(0) | |||
2948 | pptable->ReservedEquation1.c)do { } while(0); | |||
2949 | dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2950 | pptable->ReservedEquation2.a,do { } while(0) | |||
2951 | pptable->ReservedEquation2.b,do { } while(0) | |||
2952 | pptable->ReservedEquation2.c)do { } while(0); | |||
2953 | dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
2954 | pptable->ReservedEquation3.a,do { } while(0) | |||
2955 | pptable->ReservedEquation3.b,do { } while(0) | |||
2956 | pptable->ReservedEquation3.c)do { } while(0); | |||
2957 | ||||
2958 | dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0])do { } while(0); | |||
2959 | dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1])do { } while(0); | |||
2960 | dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2])do { } while(0); | |||
2961 | dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3])do { } while(0); | |||
2962 | dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4])do { } while(0); | |||
2963 | dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5])do { } while(0); | |||
2964 | dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6])do { } while(0); | |||
2965 | dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7])do { } while(0); | |||
2966 | ||||
2967 | dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0])do { } while(0); | |||
2968 | dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1])do { } while(0); | |||
2969 | dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2])do { } while(0); | |||
2970 | dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3])do { } while(0); | |||
2971 | dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4])do { } while(0); | |||
2972 | dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5])do { } while(0); | |||
2973 | ||||
2974 | for (i = 0; i < NUM_I2C_CONTROLLERS16; i++) { | |||
2975 | dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i)do { } while(0); | |||
2976 | dev_info(smu->adev->dev, " .Enabled = 0x%x\n",do { } while(0) | |||
2977 | pptable->I2cControllers[i].Enabled)do { } while(0); | |||
2978 | dev_info(smu->adev->dev, " .Speed = 0x%x\n",do { } while(0) | |||
2979 | pptable->I2cControllers[i].Speed)do { } while(0); | |||
2980 | dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",do { } while(0) | |||
2981 | pptable->I2cControllers[i].SlaveAddress)do { } while(0); | |||
2982 | dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",do { } while(0) | |||
2983 | pptable->I2cControllers[i].ControllerPort)do { } while(0); | |||
2984 | dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",do { } while(0) | |||
2985 | pptable->I2cControllers[i].ControllerName)do { } while(0); | |||
2986 | dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",do { } while(0) | |||
2987 | pptable->I2cControllers[i].ThermalThrotter)do { } while(0); | |||
2988 | dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",do { } while(0) | |||
2989 | pptable->I2cControllers[i].I2cProtocol)do { } while(0); | |||
2990 | dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",do { } while(0) | |||
2991 | pptable->I2cControllers[i].PaddingConfig)do { } while(0); | |||
2992 | } | |||
2993 | ||||
2994 | dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl)do { } while(0); | |||
2995 | dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda)do { } while(0); | |||
2996 | dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr)do { } while(0); | |||
2997 | dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0])do { } while(0); | |||
2998 | ||||
2999 | dev_info(smu->adev->dev, "Board Parameters:\n")do { } while(0); | |||
3000 | dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping)do { } while(0); | |||
3001 | dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping)do { } while(0); | |||
3002 | dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping)do { } while(0); | |||
3003 | dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping)do { } while(0); | |||
3004 | dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask)do { } while(0); | |||
3005 | dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask)do { } while(0); | |||
3006 | dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask)do { } while(0); | |||
3007 | dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask)do { } while(0); | |||
3008 | ||||
3009 | dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent)do { } while(0); | |||
3010 | dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset)do { } while(0); | |||
3011 | dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx)do { } while(0); | |||
3012 | ||||
3013 | dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent)do { } while(0); | |||
3014 | dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset)do { } while(0); | |||
3015 | dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc)do { } while(0); | |||
3016 | ||||
3017 | dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent)do { } while(0); | |||
3018 | dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset)do { } while(0); | |||
3019 | dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0)do { } while(0); | |||
3020 | ||||
3021 | dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent)do { } while(0); | |||
3022 | dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset)do { } while(0); | |||
3023 | dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1)do { } while(0); | |||
3024 | ||||
3025 | dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio)do { } while(0); | |||
3026 | ||||
3027 | dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio)do { } while(0); | |||
3028 | dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity)do { } while(0); | |||
3029 | dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio)do { } while(0); | |||
3030 | dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity)do { } while(0); | |||
3031 | dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio)do { } while(0); | |||
3032 | dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity)do { } while(0); | |||
3033 | dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio)do { } while(0); | |||
3034 | dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity)do { } while(0); | |||
3035 | dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0)do { } while(0); | |||
3036 | dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1)do { } while(0); | |||
3037 | dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2)do { } while(0); | |||
3038 | dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask)do { } while(0); | |||
3039 | dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie)do { } while(0); | |||
3040 | dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError)do { } while(0); | |||
3041 | dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0])do { } while(0); | |||
3042 | dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1])do { } while(0); | |||
3043 | ||||
3044 | dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled)do { } while(0); | |||
3045 | dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent)do { } while(0); | |||
3046 | dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq)do { } while(0); | |||
3047 | ||||
3048 | dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled)do { } while(0); | |||
3049 | dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent)do { } while(0); | |||
3050 | dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq)do { } while(0); | |||
3051 | ||||
3052 | dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding)do { } while(0); | |||
3053 | dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq)do { } while(0); | |||
3054 | ||||
3055 | dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled)do { } while(0); | |||
3056 | dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent)do { } while(0); | |||
3057 | dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq)do { } while(0); | |||
3058 | ||||
3059 | dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled)do { } while(0); | |||
3060 | dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth)do { } while(0); | |||
3061 | dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0])do { } while(0); | |||
3062 | dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1])do { } while(0); | |||
3063 | dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2])do { } while(0); | |||
3064 | ||||
3065 | dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower)do { } while(0); | |||
3066 | dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding)do { } while(0); | |||
3067 | ||||
3068 | dev_info(smu->adev->dev, "XgmiLinkSpeed\n")do { } while(0); | |||
3069 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3070 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i])do { } while(0); | |||
3071 | dev_info(smu->adev->dev, "XgmiLinkWidth\n")do { } while(0); | |||
3072 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3073 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i])do { } while(0); | |||
3074 | dev_info(smu->adev->dev, "XgmiFclkFreq\n")do { } while(0); | |||
3075 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3076 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i])do { } while(0); | |||
3077 | dev_info(smu->adev->dev, "XgmiSocVoltage\n")do { } while(0); | |||
3078 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3079 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i])do { } while(0); | |||
3080 | ||||
3081 | dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled)do { } while(0); | |||
3082 | dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled)do { } while(0); | |||
3083 | dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0])do { } while(0); | |||
3084 | dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1])do { } while(0); | |||
3085 | ||||
3086 | dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0])do { } while(0); | |||
3087 | dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1])do { } while(0); | |||
3088 | dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2])do { } while(0); | |||
3089 | dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3])do { } while(0); | |||
3090 | dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4])do { } while(0); | |||
3091 | dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5])do { } while(0); | |||
3092 | dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6])do { } while(0); | |||
3093 | dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7])do { } while(0); | |||
3094 | dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8])do { } while(0); | |||
3095 | dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9])do { } while(0); | |||
3096 | dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10])do { } while(0); | |||
3097 | ||||
3098 | dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0])do { } while(0); | |||
3099 | dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1])do { } while(0); | |||
3100 | dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2])do { } while(0); | |||
3101 | dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3])do { } while(0); | |||
3102 | dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4])do { } while(0); | |||
3103 | dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5])do { } while(0); | |||
3104 | dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6])do { } while(0); | |||
3105 | dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7])do { } while(0); | |||
3106 | } | |||
3107 | ||||
3108 | static void sienna_cichlid_dump_pptable(struct smu_context *smu) | |||
3109 | { | |||
3110 | struct smu_table_context *table_context = &smu->smu_table; | |||
3111 | PPTable_t *pptable = table_context->driver_pptable; | |||
3112 | int i; | |||
3113 | ||||
3114 | if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13))) { | |||
3115 | beige_goby_dump_pptable(smu); | |||
3116 | return; | |||
3117 | } | |||
3118 | ||||
3119 | dev_info(smu->adev->dev, "Dumped PPTable:\n")do { } while(0); | |||
3120 | ||||
3121 | dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version)do { } while(0); | |||
3122 | dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0])do { } while(0); | |||
3123 | dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1])do { } while(0); | |||
3124 | ||||
3125 | for (i = 0; i < PPT_THROTTLER_COUNT; i++) { | |||
3126 | dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i])do { } while(0); | |||
3127 | dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i])do { } while(0); | |||
3128 | dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i])do { } while(0); | |||
3129 | dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i])do { } while(0); | |||
3130 | } | |||
3131 | ||||
3132 | for (i = 0; i < TDC_THROTTLER_COUNT; i++) { | |||
3133 | dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i])do { } while(0); | |||
3134 | dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i])do { } while(0); | |||
3135 | } | |||
3136 | ||||
3137 | for (i = 0; i < TEMP_COUNT; i++) { | |||
3138 | dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i])do { } while(0); | |||
3139 | } | |||
3140 | ||||
3141 | dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit)do { } while(0); | |||
3142 | dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig)do { } while(0); | |||
3143 | dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0])do { } while(0); | |||
3144 | dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1])do { } while(0); | |||
3145 | dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2])do { } while(0); | |||
3146 | ||||
3147 | dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit)do { } while(0); | |||
3148 | for (i = 0; i < NUM_SMNCLK_DPM_LEVELS2; i++) { | |||
3149 | dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i])do { } while(0); | |||
3150 | dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i])do { } while(0); | |||
3151 | } | |||
3152 | dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask)do { } while(0); | |||
3153 | ||||
3154 | dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask)do { } while(0); | |||
3155 | ||||
3156 | dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc)do { } while(0); | |||
3157 | dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx)do { } while(0); | |||
3158 | dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx)do { } while(0); | |||
3159 | dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc)do { } while(0); | |||
3160 | ||||
3161 | dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin)do { } while(0); | |||
3162 | dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin)do { } while(0); | |||
3163 | ||||
3164 | dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold)do { } while(0); | |||
3165 | dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0])do { } while(0); | |||
3166 | dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1])do { } while(0); | |||
3167 | dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2])do { } while(0); | |||
3168 | ||||
3169 | dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx)do { } while(0); | |||
3170 | dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc)do { } while(0); | |||
3171 | dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx)do { } while(0); | |||
3172 | dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc)do { } while(0); | |||
3173 | ||||
3174 | dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx)do { } while(0); | |||
3175 | dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc)do { } while(0); | |||
3176 | ||||
3177 | dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin)do { } while(0); | |||
3178 | dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin)do { } while(0); | |||
3179 | dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp)do { } while(0); | |||
3180 | dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp)do { } while(0); | |||
3181 | dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp)do { } while(0); | |||
3182 | dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp)do { } while(0); | |||
3183 | dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis)do { } while(0); | |||
3184 | dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis)do { } while(0); | |||
3185 | ||||
3186 | dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"do { } while(0) | |||
3187 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3188 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3189 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3190 | " .padding = 0x%02x\n"do { } while(0) | |||
3191 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3192 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3193 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3194 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3195 | pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,do { } while(0) | |||
3196 | pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,do { } while(0) | |||
3197 | pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,do { } while(0) | |||
3198 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,do { } while(0) | |||
3199 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,do { } while(0) | |||
3200 | pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,do { } while(0) | |||
3201 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,do { } while(0) | |||
3202 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,do { } while(0) | |||
3203 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,do { } while(0) | |||
3204 | pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,do { } while(0) | |||
3205 | pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16)do { } while(0); | |||
3206 | ||||
3207 | dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"do { } while(0) | |||
3208 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3209 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3210 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3211 | " .padding = 0x%02x\n"do { } while(0) | |||
3212 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3213 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3214 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3215 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3216 | pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,do { } while(0) | |||
3217 | pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,do { } while(0) | |||
3218 | pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,do { } while(0) | |||
3219 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,do { } while(0) | |||
3220 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,do { } while(0) | |||
3221 | pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,do { } while(0) | |||
3222 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,do { } while(0) | |||
3223 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,do { } while(0) | |||
3224 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,do { } while(0) | |||
3225 | pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,do { } while(0) | |||
3226 | pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16)do { } while(0); | |||
3227 | ||||
3228 | dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"do { } while(0) | |||
3229 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3230 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3231 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3232 | " .padding = 0x%02x\n"do { } while(0) | |||
3233 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3234 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3235 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3236 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3237 | pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,do { } while(0) | |||
3238 | pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,do { } while(0) | |||
3239 | pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,do { } while(0) | |||
3240 | pptable->DpmDescriptor[PPCLK_UCLK].Padding,do { } while(0) | |||
3241 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,do { } while(0) | |||
3242 | pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,do { } while(0) | |||
3243 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,do { } while(0) | |||
3244 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,do { } while(0) | |||
3245 | pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,do { } while(0) | |||
3246 | pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,do { } while(0) | |||
3247 | pptable->DpmDescriptor[PPCLK_UCLK].Padding16)do { } while(0); | |||
3248 | ||||
3249 | dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"do { } while(0) | |||
3250 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3251 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3252 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3253 | " .padding = 0x%02x\n"do { } while(0) | |||
3254 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3255 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3256 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3257 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3258 | pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,do { } while(0) | |||
3259 | pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,do { } while(0) | |||
3260 | pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,do { } while(0) | |||
3261 | pptable->DpmDescriptor[PPCLK_FCLK].Padding,do { } while(0) | |||
3262 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,do { } while(0) | |||
3263 | pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,do { } while(0) | |||
3264 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,do { } while(0) | |||
3265 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,do { } while(0) | |||
3266 | pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,do { } while(0) | |||
3267 | pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,do { } while(0) | |||
3268 | pptable->DpmDescriptor[PPCLK_FCLK].Padding16)do { } while(0); | |||
3269 | ||||
3270 | dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"do { } while(0) | |||
3271 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3272 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3273 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3274 | " .padding = 0x%02x\n"do { } while(0) | |||
3275 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3276 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3277 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3278 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3279 | pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,do { } while(0) | |||
3280 | pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,do { } while(0) | |||
3281 | pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,do { } while(0) | |||
3282 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,do { } while(0) | |||
3283 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,do { } while(0) | |||
3284 | pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,do { } while(0) | |||
3285 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,do { } while(0) | |||
3286 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,do { } while(0) | |||
3287 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,do { } while(0) | |||
3288 | pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,do { } while(0) | |||
3289 | pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16)do { } while(0); | |||
3290 | ||||
3291 | dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"do { } while(0) | |||
3292 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3293 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3294 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3295 | " .padding = 0x%02x\n"do { } while(0) | |||
3296 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3297 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3298 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3299 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3300 | pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,do { } while(0) | |||
3301 | pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,do { } while(0) | |||
3302 | pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,do { } while(0) | |||
3303 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,do { } while(0) | |||
3304 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,do { } while(0) | |||
3305 | pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,do { } while(0) | |||
3306 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,do { } while(0) | |||
3307 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,do { } while(0) | |||
3308 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,do { } while(0) | |||
3309 | pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,do { } while(0) | |||
3310 | pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16)do { } while(0); | |||
3311 | ||||
3312 | dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"do { } while(0) | |||
3313 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3314 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3315 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3316 | " .padding = 0x%02x\n"do { } while(0) | |||
3317 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3318 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3319 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3320 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3321 | pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,do { } while(0) | |||
3322 | pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,do { } while(0) | |||
3323 | pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,do { } while(0) | |||
3324 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,do { } while(0) | |||
3325 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,do { } while(0) | |||
3326 | pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,do { } while(0) | |||
3327 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,do { } while(0) | |||
3328 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,do { } while(0) | |||
3329 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,do { } while(0) | |||
3330 | pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,do { } while(0) | |||
3331 | pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16)do { } while(0); | |||
3332 | ||||
3333 | dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"do { } while(0) | |||
3334 | " .VoltageMode = 0x%02x\n"do { } while(0) | |||
3335 | " .SnapToDiscrete = 0x%02x\n"do { } while(0) | |||
3336 | " .NumDiscreteLevels = 0x%02x\n"do { } while(0) | |||
3337 | " .padding = 0x%02x\n"do { } while(0) | |||
3338 | " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0) | |||
3339 | " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0) | |||
3340 | " .SsFmin = 0x%04x\n"do { } while(0) | |||
3341 | " .Padding_16 = 0x%04x\n",do { } while(0) | |||
3342 | pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,do { } while(0) | |||
3343 | pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,do { } while(0) | |||
3344 | pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,do { } while(0) | |||
3345 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,do { } while(0) | |||
3346 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,do { } while(0) | |||
3347 | pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,do { } while(0) | |||
3348 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,do { } while(0) | |||
3349 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,do { } while(0) | |||
3350 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,do { } while(0) | |||
3351 | pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,do { } while(0) | |||
3352 | pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16)do { } while(0); | |||
3353 | ||||
3354 | dev_info(smu->adev->dev, "FreqTableGfx\n")do { } while(0); | |||
3355 | for (i = 0; i < NUM_GFXCLK_DPM_LEVELS16; i++) | |||
3356 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i])do { } while(0); | |||
3357 | ||||
3358 | dev_info(smu->adev->dev, "FreqTableVclk\n")do { } while(0); | |||
3359 | for (i = 0; i < NUM_VCLK_DPM_LEVELS8; i++) | |||
3360 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i])do { } while(0); | |||
3361 | ||||
3362 | dev_info(smu->adev->dev, "FreqTableDclk\n")do { } while(0); | |||
3363 | for (i = 0; i < NUM_DCLK_DPM_LEVELS8; i++) | |||
3364 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i])do { } while(0); | |||
3365 | ||||
3366 | dev_info(smu->adev->dev, "FreqTableSocclk\n")do { } while(0); | |||
3367 | for (i = 0; i < NUM_SOCCLK_DPM_LEVELS8; i++) | |||
3368 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i])do { } while(0); | |||
3369 | ||||
3370 | dev_info(smu->adev->dev, "FreqTableUclk\n")do { } while(0); | |||
3371 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
3372 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i])do { } while(0); | |||
3373 | ||||
3374 | dev_info(smu->adev->dev, "FreqTableFclk\n")do { } while(0); | |||
3375 | for (i = 0; i < NUM_FCLK_DPM_LEVELS8; i++) | |||
3376 | dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i])do { } while(0); | |||
3377 | ||||
3378 | dev_info(smu->adev->dev, "DcModeMaxFreq\n")do { } while(0); | |||
3379 | dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK])do { } while(0); | |||
3380 | dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK])do { } while(0); | |||
3381 | dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK])do { } while(0); | |||
3382 | dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK])do { } while(0); | |||
3383 | dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0])do { } while(0); | |||
3384 | dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0])do { } while(0); | |||
3385 | dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1])do { } while(0); | |||
3386 | dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1])do { } while(0); | |||
3387 | ||||
3388 | dev_info(smu->adev->dev, "FreqTableUclkDiv\n")do { } while(0); | |||
3389 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
3390 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i])do { } while(0); | |||
3391 | ||||
3392 | dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq)do { } while(0); | |||
3393 | dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding)do { } while(0); | |||
3394 | ||||
3395 | dev_info(smu->adev->dev, "Mp0clkFreq\n")do { } while(0); | |||
3396 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++) | |||
3397 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i])do { } while(0); | |||
3398 | ||||
3399 | dev_info(smu->adev->dev, "Mp0DpmVoltage\n")do { } while(0); | |||
3400 | for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++) | |||
3401 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i])do { } while(0); | |||
3402 | ||||
3403 | dev_info(smu->adev->dev, "MemVddciVoltage\n")do { } while(0); | |||
3404 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
3405 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i])do { } while(0); | |||
3406 | ||||
3407 | dev_info(smu->adev->dev, "MemMvddVoltage\n")do { } while(0); | |||
3408 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
3409 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i])do { } while(0); | |||
3410 | ||||
3411 | dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry)do { } while(0); | |||
3412 | dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit)do { } while(0); | |||
3413 | dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle)do { } while(0); | |||
3414 | dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource)do { } while(0); | |||
3415 | dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding)do { } while(0); | |||
3416 | ||||
3417 | dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask)do { } while(0); | |||
3418 | ||||
3419 | dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask)do { } while(0); | |||
3420 | dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask)do { } while(0); | |||
3421 | dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0])do { } while(0); | |||
3422 | dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow)do { } while(0); | |||
3423 | dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0])do { } while(0); | |||
3424 | dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1])do { } while(0); | |||
3425 | dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2])do { } while(0); | |||
3426 | dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3])do { } while(0); | |||
3427 | dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt)do { } while(0); | |||
3428 | dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt)do { } while(0); | |||
3429 | dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt)do { } while(0); | |||
3430 | ||||
3431 | dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage)do { } while(0); | |||
3432 | dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime)do { } while(0); | |||
3433 | dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime)do { } while(0); | |||
3434 | dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum)do { } while(0); | |||
3435 | dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis)do { } while(0); | |||
3436 | dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout)do { } while(0); | |||
3437 | ||||
3438 | dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0])do { } while(0); | |||
3439 | dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1])do { } while(0); | |||
3440 | dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2])do { } while(0); | |||
3441 | dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3])do { } while(0); | |||
3442 | dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4])do { } while(0); | |||
3443 | ||||
3444 | dev_info(smu->adev->dev, "FlopsPerByteTable\n")do { } while(0); | |||
3445 | for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS16; i++) | |||
3446 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i])do { } while(0); | |||
3447 | ||||
3448 | dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv)do { } while(0); | |||
3449 | dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0])do { } while(0); | |||
3450 | dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1])do { } while(0); | |||
3451 | dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2])do { } while(0); | |||
3452 | ||||
3453 | dev_info(smu->adev->dev, "UclkDpmPstates\n")do { } while(0); | |||
3454 | for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++) | |||
3455 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i])do { } while(0); | |||
3456 | ||||
3457 | dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n")do { } while(0); | |||
3458 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0) | |||
3459 | pptable->UclkDpmSrcFreqRange.Fmin)do { } while(0); | |||
3460 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0) | |||
3461 | pptable->UclkDpmSrcFreqRange.Fmax)do { } while(0); | |||
3462 | dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n")do { } while(0); | |||
3463 | dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0) | |||
3464 | pptable->UclkDpmTargFreqRange.Fmin)do { } while(0); | |||
3465 | dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0) | |||
3466 | pptable->UclkDpmTargFreqRange.Fmax)do { } while(0); | |||
3467 | dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq)do { } while(0); | |||
3468 | dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding)do { } while(0); | |||
3469 | ||||
3470 | dev_info(smu->adev->dev, "PcieGenSpeed\n")do { } while(0); | |||
3471 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
3472 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i])do { } while(0); | |||
3473 | ||||
3474 | dev_info(smu->adev->dev, "PcieLaneCount\n")do { } while(0); | |||
3475 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
3476 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i])do { } while(0); | |||
3477 | ||||
3478 | dev_info(smu->adev->dev, "LclkFreq\n")do { } while(0); | |||
3479 | for (i = 0; i < NUM_LINK_LEVELS2; i++) | |||
3480 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i])do { } while(0); | |||
3481 | ||||
3482 | dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp)do { } while(0); | |||
3483 | dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp)do { } while(0); | |||
3484 | ||||
3485 | dev_info(smu->adev->dev, "FanGain\n")do { } while(0); | |||
3486 | for (i = 0; i < TEMP_COUNT; i++) | |||
3487 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i])do { } while(0); | |||
3488 | ||||
3489 | dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin)do { } while(0); | |||
3490 | dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm)do { } while(0); | |||
3491 | dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm)do { } while(0); | |||
3492 | dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm)do { } while(0); | |||
3493 | dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm)do { } while(0); | |||
3494 | dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature)do { } while(0); | |||
3495 | dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk)do { } while(0); | |||
3496 | dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16)do { } while(0); | |||
3497 | dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect)do { } while(0); | |||
3498 | dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding)do { } while(0); | |||
3499 | dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable)do { } while(0); | |||
3500 | dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev)do { } while(0); | |||
3501 | ||||
3502 | dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta)do { } while(0); | |||
3503 | dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta)do { } while(0); | |||
3504 | dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta)do { } while(0); | |||
3505 | dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved)do { } while(0); | |||
3506 | ||||
3507 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3508 | dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3509 | dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect)do { } while(0); | |||
3510 | dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs)do { } while(0); | |||
3511 | ||||
3512 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3513 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,do { } while(0) | |||
3514 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,do { } while(0) | |||
3515 | pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c)do { } while(0); | |||
3516 | dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3517 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,do { } while(0) | |||
3518 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,do { } while(0) | |||
3519 | pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c)do { } while(0); | |||
3520 | dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3521 | pptable->dBtcGbGfxPll.a,do { } while(0) | |||
3522 | pptable->dBtcGbGfxPll.b,do { } while(0) | |||
3523 | pptable->dBtcGbGfxPll.c)do { } while(0); | |||
3524 | dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3525 | pptable->dBtcGbGfxDfll.a,do { } while(0) | |||
3526 | pptable->dBtcGbGfxDfll.b,do { } while(0) | |||
3527 | pptable->dBtcGbGfxDfll.c)do { } while(0); | |||
3528 | dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3529 | pptable->dBtcGbSoc.a,do { } while(0) | |||
3530 | pptable->dBtcGbSoc.b,do { } while(0) | |||
3531 | pptable->dBtcGbSoc.c)do { } while(0); | |||
3532 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",do { } while(0) | |||
3533 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,do { } while(0) | |||
3534 | pptable->qAgingGb[AVFS_VOLTAGE_GFX].b)do { } while(0); | |||
3535 | dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",do { } while(0) | |||
3536 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,do { } while(0) | |||
3537 | pptable->qAgingGb[AVFS_VOLTAGE_SOC].b)do { } while(0); | |||
3538 | ||||
3539 | dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n")do { } while(0); | |||
3540 | for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS5; i++) { | |||
3541 | dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",do { } while(0) | |||
3542 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i])do { } while(0); | |||
3543 | dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",do { } while(0) | |||
3544 | i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i])do { } while(0); | |||
3545 | } | |||
3546 | ||||
3547 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3548 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,do { } while(0) | |||
3549 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,do { } while(0) | |||
3550 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c)do { } while(0); | |||
3551 | dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3552 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,do { } while(0) | |||
3553 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,do { } while(0) | |||
3554 | pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c)do { } while(0); | |||
3555 | ||||
3556 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3557 | dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3558 | ||||
3559 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3560 | dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3561 | dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0])do { } while(0); | |||
3562 | dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1])do { } while(0); | |||
3563 | ||||
3564 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3565 | dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3566 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3567 | dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3568 | ||||
3569 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX])do { } while(0); | |||
3570 | dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC])do { } while(0); | |||
3571 | ||||
3572 | dev_info(smu->adev->dev, "XgmiDpmPstates\n")do { } while(0); | |||
3573 | for (i = 0; i < NUM_XGMI_LEVELS2; i++) | |||
3574 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i])do { } while(0); | |||
3575 | dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0])do { } while(0); | |||
3576 | dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1])do { } while(0); | |||
3577 | ||||
3578 | dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides)do { } while(0); | |||
3579 | dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3580 | pptable->ReservedEquation0.a,do { } while(0) | |||
3581 | pptable->ReservedEquation0.b,do { } while(0) | |||
3582 | pptable->ReservedEquation0.c)do { } while(0); | |||
3583 | dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3584 | pptable->ReservedEquation1.a,do { } while(0) | |||
3585 | pptable->ReservedEquation1.b,do { } while(0) | |||
3586 | pptable->ReservedEquation1.c)do { } while(0); | |||
3587 | dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3588 | pptable->ReservedEquation2.a,do { } while(0) | |||
3589 | pptable->ReservedEquation2.b,do { } while(0) | |||
3590 | pptable->ReservedEquation2.c)do { } while(0); | |||
3591 | dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0) | |||
3592 | pptable->ReservedEquation3.a,do { } while(0) | |||
3593 | pptable->ReservedEquation3.b,do { } while(0) | |||
3594 | pptable->ReservedEquation3.c)do { } while(0); | |||
3595 | ||||
3596 | dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0])do { } while(0); | |||
3597 | dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1])do { } while(0); | |||
3598 | dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2])do { } while(0); | |||
3599 | dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3])do { } while(0); | |||
3600 | dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4])do { } while(0); | |||
3601 | dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5])do { } while(0); | |||
3602 | dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6])do { } while(0); | |||
3603 | dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7])do { } while(0); | |||
3604 | ||||
3605 | dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0])do { } while(0); | |||
3606 | dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1])do { } while(0); | |||
3607 | dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2])do { } while(0); | |||
3608 | dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3])do { } while(0); | |||
3609 | dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4])do { } while(0); | |||
3610 | dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5])do { } while(0); | |||
3611 | ||||
3612 | for (i = 0; i < NUM_I2C_CONTROLLERS16; i++) { | |||
3613 | dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i)do { } while(0); | |||
3614 | dev_info(smu->adev->dev, " .Enabled = 0x%x\n",do { } while(0) | |||
3615 | pptable->I2cControllers[i].Enabled)do { } while(0); | |||
3616 | dev_info(smu->adev->dev, " .Speed = 0x%x\n",do { } while(0) | |||
3617 | pptable->I2cControllers[i].Speed)do { } while(0); | |||
3618 | dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",do { } while(0) | |||
3619 | pptable->I2cControllers[i].SlaveAddress)do { } while(0); | |||
3620 | dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",do { } while(0) | |||
3621 | pptable->I2cControllers[i].ControllerPort)do { } while(0); | |||
3622 | dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",do { } while(0) | |||
3623 | pptable->I2cControllers[i].ControllerName)do { } while(0); | |||
3624 | dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",do { } while(0) | |||
3625 | pptable->I2cControllers[i].ThermalThrotter)do { } while(0); | |||
3626 | dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",do { } while(0) | |||
3627 | pptable->I2cControllers[i].I2cProtocol)do { } while(0); | |||
3628 | dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",do { } while(0) | |||
3629 | pptable->I2cControllers[i].PaddingConfig)do { } while(0); | |||
3630 | } | |||
3631 | ||||
3632 | dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl)do { } while(0); | |||
3633 | dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda)do { } while(0); | |||
3634 | dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr)do { } while(0); | |||
3635 | dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0])do { } while(0); | |||
3636 | ||||
3637 | dev_info(smu->adev->dev, "Board Parameters:\n")do { } while(0); | |||
3638 | dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping)do { } while(0); | |||
3639 | dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping)do { } while(0); | |||
3640 | dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping)do { } while(0); | |||
3641 | dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping)do { } while(0); | |||
3642 | dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask)do { } while(0); | |||
3643 | dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask)do { } while(0); | |||
3644 | dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask)do { } while(0); | |||
3645 | dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask)do { } while(0); | |||
3646 | ||||
3647 | dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent)do { } while(0); | |||
3648 | dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset)do { } while(0); | |||
3649 | dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx)do { } while(0); | |||
3650 | ||||
3651 | dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent)do { } while(0); | |||
3652 | dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset)do { } while(0); | |||
3653 | dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc)do { } while(0); | |||
3654 | ||||
3655 | dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent)do { } while(0); | |||
3656 | dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset)do { } while(0); | |||
3657 | dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0)do { } while(0); | |||
3658 | ||||
3659 | dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent)do { } while(0); | |||
3660 | dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset)do { } while(0); | |||
3661 | dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1)do { } while(0); | |||
3662 | ||||
3663 | dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio)do { } while(0); | |||
3664 | ||||
3665 | dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio)do { } while(0); | |||
3666 | dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity)do { } while(0); | |||
3667 | dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio)do { } while(0); | |||
3668 | dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity)do { } while(0); | |||
3669 | dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio)do { } while(0); | |||
3670 | dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity)do { } while(0); | |||
3671 | dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio)do { } while(0); | |||
3672 | dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity)do { } while(0); | |||
3673 | dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0)do { } while(0); | |||
3674 | dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1)do { } while(0); | |||
3675 | dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2)do { } while(0); | |||
3676 | dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask)do { } while(0); | |||
3677 | dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie)do { } while(0); | |||
3678 | dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError)do { } while(0); | |||
3679 | dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0])do { } while(0); | |||
3680 | dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1])do { } while(0); | |||
3681 | ||||
3682 | dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled)do { } while(0); | |||
3683 | dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent)do { } while(0); | |||
3684 | dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq)do { } while(0); | |||
3685 | ||||
3686 | dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled)do { } while(0); | |||
3687 | dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent)do { } while(0); | |||
3688 | dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq)do { } while(0); | |||
3689 | ||||
3690 | dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding)do { } while(0); | |||
3691 | dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq)do { } while(0); | |||
3692 | ||||
3693 | dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled)do { } while(0); | |||
3694 | dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent)do { } while(0); | |||
3695 | dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq)do { } while(0); | |||
3696 | ||||
3697 | dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled)do { } while(0); | |||
3698 | dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth)do { } while(0); | |||
3699 | dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0])do { } while(0); | |||
3700 | dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1])do { } while(0); | |||
3701 | dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2])do { } while(0); | |||
3702 | ||||
3703 | dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower)do { } while(0); | |||
3704 | dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding)do { } while(0); | |||
3705 | ||||
3706 | dev_info(smu->adev->dev, "XgmiLinkSpeed\n")do { } while(0); | |||
3707 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3708 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i])do { } while(0); | |||
3709 | dev_info(smu->adev->dev, "XgmiLinkWidth\n")do { } while(0); | |||
3710 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3711 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i])do { } while(0); | |||
3712 | dev_info(smu->adev->dev, "XgmiFclkFreq\n")do { } while(0); | |||
3713 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3714 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i])do { } while(0); | |||
3715 | dev_info(smu->adev->dev, "XgmiSocVoltage\n")do { } while(0); | |||
3716 | for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++) | |||
3717 | dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i])do { } while(0); | |||
3718 | ||||
3719 | dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled)do { } while(0); | |||
3720 | dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled)do { } while(0); | |||
3721 | dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0])do { } while(0); | |||
3722 | dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1])do { } while(0); | |||
3723 | ||||
3724 | dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0])do { } while(0); | |||
3725 | dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1])do { } while(0); | |||
3726 | dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2])do { } while(0); | |||
3727 | dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3])do { } while(0); | |||
3728 | dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4])do { } while(0); | |||
3729 | dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5])do { } while(0); | |||
3730 | dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6])do { } while(0); | |||
3731 | dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7])do { } while(0); | |||
3732 | dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8])do { } while(0); | |||
3733 | dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9])do { } while(0); | |||
3734 | dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10])do { } while(0); | |||
3735 | ||||
3736 | dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0])do { } while(0); | |||
3737 | dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1])do { } while(0); | |||
3738 | dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2])do { } while(0); | |||
3739 | dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3])do { } while(0); | |||
3740 | dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4])do { } while(0); | |||
3741 | dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5])do { } while(0); | |||
3742 | dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6])do { } while(0); | |||
3743 | dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7])do { } while(0); | |||
3744 | } | |||
3745 | ||||
3746 | static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, | |||
3747 | struct i2c_msg *msg, int num_msgs) | |||
3748 | { | |||
3749 | struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); | |||
3750 | struct amdgpu_device *adev = smu_i2c->adev; | |||
3751 | struct smu_context *smu = adev->powerplay.pp_handle; | |||
3752 | struct smu_table_context *smu_table = &smu->smu_table; | |||
3753 | struct smu_table *table = &smu_table->driver_table; | |||
3754 | SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; | |||
3755 | int i, j, r, c; | |||
3756 | u16 dir; | |||
3757 | ||||
3758 | if (!adev->pm.dpm_enabled) | |||
3759 | return -EBUSY16; | |||
3760 | ||||
3761 | req = kzalloc(sizeof(*req), GFP_KERNEL(0x0001 | 0x0004)); | |||
3762 | if (!req) | |||
3763 | return -ENOMEM12; | |||
3764 | ||||
3765 | req->I2CcontrollerPort = smu_i2c->port; | |||
3766 | req->I2CSpeed = I2C_SPEED_FAST_400K; | |||
3767 | req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ | |||
3768 | dir = msg[0].flags & I2C_M_RD0x0001; | |||
3769 | ||||
3770 | for (c = i = 0; i < num_msgs; i++) { | |||
3771 | for (j = 0; j < msg[i].len; j++, c++) { | |||
3772 | SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; | |||
3773 | ||||
3774 | if (!(msg[i].flags & I2C_M_RD0x0001)) { | |||
3775 | /* write */ | |||
3776 | cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK(1 << 2); | |||
3777 | cmd->ReadWriteData = msg[i].buf[j]; | |||
3778 | } | |||
3779 | ||||
3780 | if ((dir ^ msg[i].flags) & I2C_M_RD0x0001) { | |||
3781 | /* The direction changes. | |||
3782 | */ | |||
3783 | dir = msg[i].flags & I2C_M_RD0x0001; | |||
3784 | cmd->CmdConfig |= CMDCONFIG_RESTART_MASK(1 << 1); | |||
3785 | } | |||
3786 | ||||
3787 | req->NumCmds++; | |||
3788 | ||||
3789 | /* | |||
3790 | * Insert STOP if we are at the last byte of either last | |||
3791 | * message for the transaction or the client explicitly | |||
3792 | * requires a STOP at this particular message. | |||
3793 | */ | |||
3794 | if ((j == msg[i].len - 1) && | |||
3795 | ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP0x0004))) { | |||
3796 | cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK(1 << 1); | |||
3797 | cmd->CmdConfig |= CMDCONFIG_STOP_MASK(1 << 0); | |||
3798 | } | |||
3799 | } | |||
3800 | } | |||
3801 | mutex_lock(&adev->pm.mutex)rw_enter_write(&adev->pm.mutex); | |||
3802 | r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true1); | |||
3803 | mutex_unlock(&adev->pm.mutex)rw_exit_write(&adev->pm.mutex); | |||
3804 | if (r) | |||
3805 | goto fail; | |||
3806 | ||||
3807 | for (c = i = 0; i < num_msgs; i++) { | |||
3808 | if (!(msg[i].flags & I2C_M_RD0x0001)) { | |||
3809 | c += msg[i].len; | |||
3810 | continue; | |||
3811 | } | |||
3812 | for (j = 0; j < msg[i].len; j++, c++) { | |||
3813 | SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; | |||
3814 | ||||
3815 | msg[i].buf[j] = cmd->ReadWriteData; | |||
3816 | } | |||
3817 | } | |||
3818 | r = num_msgs; | |||
3819 | fail: | |||
3820 | kfree(req); | |||
3821 | return r; | |||
3822 | } | |||
3823 | ||||
3824 | static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) | |||
3825 | { | |||
3826 | return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0; | |||
3827 | } | |||
3828 | ||||
3829 | ||||
3830 | static const struct i2c_algorithm sienna_cichlid_i2c_algo = { | |||
3831 | .master_xfer = sienna_cichlid_i2c_xfer, | |||
3832 | .functionality = sienna_cichlid_i2c_func, | |||
3833 | }; | |||
3834 | ||||
3835 | static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { | |||
3836 | .flags = I2C_AQ_COMB0 | I2C_AQ_COMB_SAME_ADDR0 | I2C_AQ_NO_ZERO_LEN0, | |||
3837 | .max_read_len = MAX_SW_I2C_COMMANDS24, | |||
3838 | .max_write_len = MAX_SW_I2C_COMMANDS24, | |||
3839 | .max_comb_1st_msg_len = 2, | |||
3840 | .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS24 - 2, | |||
3841 | }; | |||
3842 | ||||
3843 | static int sienna_cichlid_i2c_control_init(struct smu_context *smu) | |||
3844 | { | |||
3845 | struct amdgpu_device *adev = smu->adev; | |||
3846 | int res, i; | |||
3847 | ||||
3848 | for (i = 0; i < MAX_SMU_I2C_BUSES2; i++) { | |||
3849 | struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; | |||
3850 | struct i2c_adapter *control = &smu_i2c->adapter; | |||
3851 | ||||
3852 | smu_i2c->adev = adev; | |||
3853 | smu_i2c->port = i; | |||
3854 | rw_init(&smu_i2c->mutex, "sciic")_rw_init_flags(&smu_i2c->mutex, "sciic", 0, ((void *)0 )); | |||
3855 | #ifdef __linux__ | |||
3856 | control->owner = THIS_MODULE((void *)0); | |||
3857 | control->class = I2C_CLASS_HWMON; | |||
3858 | control->dev.parent = &adev->pdev->dev; | |||
3859 | #endif | |||
3860 | control->algo = &sienna_cichlid_i2c_algo; | |||
3861 | snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); | |||
3862 | control->quirks = &sienna_cichlid_i2c_control_quirks; | |||
3863 | i2c_set_adapdata(control, smu_i2c); | |||
3864 | ||||
3865 | res = i2c_add_adapter(control); | |||
3866 | if (res) { | |||
3867 | DRM_ERROR("Failed to register hw i2c, err: %d\n", res)__drm_err("Failed to register hw i2c, err: %d\n", res); | |||
3868 | goto Out_err; | |||
3869 | } | |||
3870 | } | |||
3871 | /* assign the buses used for the FRU EEPROM and RAS EEPROM */ | |||
3872 | /* XXX ideally this would be something in a vbios data table */ | |||
3873 | adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; | |||
3874 | adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; | |||
3875 | ||||
3876 | return 0; | |||
3877 | Out_err: | |||
3878 | for ( ; i >= 0; i--) { | |||
3879 | struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; | |||
3880 | struct i2c_adapter *control = &smu_i2c->adapter; | |||
3881 | ||||
3882 | i2c_del_adapter(control); | |||
3883 | } | |||
3884 | return res; | |||
3885 | } | |||
3886 | ||||
3887 | static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) | |||
3888 | { | |||
3889 | struct amdgpu_device *adev = smu->adev; | |||
3890 | int i; | |||
3891 | ||||
3892 | for (i = 0; i < MAX_SMU_I2C_BUSES2; i++) { | |||
3893 | struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; | |||
3894 | struct i2c_adapter *control = &smu_i2c->adapter; | |||
3895 | ||||
3896 | i2c_del_adapter(control); | |||
3897 | } | |||
3898 | adev->pm.ras_eeprom_i2c_bus = NULL((void *)0); | |||
3899 | adev->pm.fru_eeprom_i2c_bus = NULL((void *)0); | |||
3900 | } | |||
3901 | ||||
3902 | static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, | |||
3903 | void **table) | |||
3904 | { | |||
3905 | struct smu_table_context *smu_table = &smu->smu_table; | |||
3906 | struct gpu_metrics_v1_3 *gpu_metrics = | |||
3907 | (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; | |||
3908 | SmuMetricsExternal_t metrics_external; | |||
3909 | SmuMetrics_t *metrics = | |||
3910 | &(metrics_external.SmuMetrics); | |||
3911 | SmuMetrics_V2_t *metrics_v2 = | |||
3912 | &(metrics_external.SmuMetrics_V2); | |||
3913 | SmuMetrics_V3_t *metrics_v3 = | |||
3914 | &(metrics_external.SmuMetrics_V3); | |||
3915 | struct amdgpu_device *adev = smu->adev; | |||
3916 | bool_Bool use_metrics_v2 = false0; | |||
3917 | bool_Bool use_metrics_v3 = false0; | |||
3918 | uint16_t average_gfx_activity; | |||
3919 | int ret = 0; | |||
3920 | ||||
3921 | switch (smu->adev->ip_versions[MP1_HWIP][0]) { | |||
3922 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): | |||
3923 | if (smu->smc_fw_version >= 0x3A4900) | |||
3924 | use_metrics_v3 = true1; | |||
3925 | else if (smu->smc_fw_version >= 0x3A4300) | |||
3926 | use_metrics_v2 = true1; | |||
3927 | break; | |||
3928 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): | |||
3929 | if (smu->smc_fw_version >= 0x412D00) | |||
3930 | use_metrics_v2 = true1; | |||
3931 | break; | |||
3932 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): | |||
3933 | if (smu->smc_fw_version >= 0x3B2300) | |||
3934 | use_metrics_v2 = true1; | |||
3935 | break; | |||
3936 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): | |||
3937 | if (smu->smc_fw_version >= 0x491100) | |||
3938 | use_metrics_v2 = true1; | |||
3939 | break; | |||
3940 | default: | |||
3941 | break; | |||
3942 | } | |||
3943 | ||||
3944 | ret = smu_cmn_get_metrics_table(smu, | |||
3945 | &metrics_external, | |||
3946 | true1); | |||
3947 | if (ret) | |||
3948 | return ret; | |||
3949 | ||||
3950 | smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); | |||
3951 | ||||
3952 | gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : | |||
3953 | use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; | |||
3954 | gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : | |||
3955 | use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; | |||
3956 | gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : | |||
3957 | use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; | |||
3958 | gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : | |||
3959 | use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; | |||
3960 | gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : | |||
3961 | use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; | |||
3962 | gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : | |||
3963 | use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; | |||
3964 | ||||
3965 | gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : | |||
3966 | use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; | |||
3967 | gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : | |||
3968 | use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; | |||
3969 | gpu_metrics->average_mm_activity = use_metrics_v3 ? | |||
3970 | (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : | |||
3971 | use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; | |||
3972 | ||||
3973 | gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : | |||
3974 | use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; | |||
3975 | gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : | |||
3976 | use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; | |||
3977 | ||||
3978 | if (metrics->CurrGfxVoltageOffset) | |||
3979 | gpu_metrics->voltage_gfx = | |||
3980 | (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; | |||
3981 | if (metrics->CurrMemVidOffset) | |||
3982 | gpu_metrics->voltage_mem = | |||
3983 | (155000 - 625 * metrics->CurrMemVidOffset) / 100; | |||
3984 | if (metrics->CurrSocVoltageOffset) | |||
3985 | gpu_metrics->voltage_soc = | |||
3986 | (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; | |||
3987 | ||||
3988 | average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : | |||
3989 | use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; | |||
3990 | if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD15) | |||
3991 | gpu_metrics->average_gfxclk_frequency = | |||
3992 | use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : | |||
3993 | use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : | |||
3994 | metrics->AverageGfxclkFrequencyPostDs; | |||
3995 | else | |||
3996 | gpu_metrics->average_gfxclk_frequency = | |||
3997 | use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : | |||
3998 | use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : | |||
3999 | metrics->AverageGfxclkFrequencyPreDs; | |||
4000 | ||||
4001 | gpu_metrics->average_uclk_frequency = | |||
4002 | use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : | |||
4003 | use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : | |||
4004 | metrics->AverageUclkFrequencyPostDs; | |||
4005 | gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : | |||
4006 | use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; | |||
4007 | gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : | |||
4008 | use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; | |||
4009 | gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : | |||
4010 | use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; | |||
4011 | gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : | |||
4012 | use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; | |||
4013 | ||||
4014 | gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : | |||
4015 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; | |||
4016 | gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : | |||
4017 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; | |||
4018 | gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : | |||
4019 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; | |||
4020 | gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : | |||
4021 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; | |||
4022 | gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : | |||
4023 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; | |||
4024 | gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : | |||
4025 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; | |||
4026 | gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : | |||
4027 | use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; | |||
4028 | ||||
4029 | gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); | |||
4030 | gpu_metrics->indep_throttle_status = | |||
4031 | smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, | |||
4032 | sienna_cichlid_throttler_map); | |||
4033 | ||||
4034 | gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : | |||
4035 | use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; | |||
4036 | ||||
4037 | if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) && smu->smc_fw_version > 0x003A1E00) || | |||
4038 | ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11))) && smu->smc_fw_version > 0x00410400)) { | |||
4039 | gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : | |||
4040 | use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; | |||
4041 | gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : | |||
4042 | use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; | |||
4043 | } else { | |||
4044 | gpu_metrics->pcie_link_width = | |||
4045 | smu_v11_0_get_current_pcie_link_width(smu); | |||
4046 | gpu_metrics->pcie_link_speed = | |||
4047 | smu_v11_0_get_current_pcie_link_speed(smu); | |||
4048 | } | |||
4049 | ||||
4050 | gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); | |||
4051 | ||||
4052 | *table = (void *)gpu_metrics; | |||
4053 | ||||
4054 | return sizeof(struct gpu_metrics_v1_3); | |||
4055 | } | |||
4056 | ||||
4057 | static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) | |||
4058 | { | |||
4059 | uint32_t if_version = 0xff, smu_version = 0xff; | |||
4060 | int ret = 0; | |||
4061 | ||||
4062 | ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); | |||
4063 | if (ret) | |||
4064 | return -EOPNOTSUPP45; | |||
4065 | ||||
4066 | if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION0x003a4600) | |||
4067 | ret = -EOPNOTSUPP45; | |||
4068 | ||||
4069 | return ret; | |||
4070 | } | |||
4071 | ||||
4072 | static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, | |||
4073 | void *table) | |||
4074 | { | |||
4075 | struct smu_table_context *smu_table = &smu->smu_table; | |||
4076 | EccInfoTable_t *ecc_table = NULL((void *)0); | |||
4077 | struct ecc_info_per_ch *ecc_info_per_channel = NULL((void *)0); | |||
4078 | int i, ret = 0; | |||
4079 | struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; | |||
4080 | ||||
4081 | ret = sienna_cichlid_check_ecc_table_support(smu); | |||
4082 | if (ret) | |||
4083 | return ret; | |||
4084 | ||||
4085 | ret = smu_cmn_update_table(smu, | |||
4086 | SMU_TABLE_ECCINFO, | |||
4087 | 0, | |||
4088 | smu_table->ecc_table, | |||
4089 | false0); | |||
4090 | if (ret) { | |||
4091 | dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n")do { } while(0); | |||
4092 | return ret; | |||
4093 | } | |||
4094 | ||||
4095 | ecc_table = (EccInfoTable_t *)smu_table->ecc_table; | |||
4096 | ||||
4097 | for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM16; i++) { | |||
4098 | ecc_info_per_channel = &(eccinfo->ecc[i]); | |||
4099 | ecc_info_per_channel->ce_count_lo_chip = | |||
4100 | ecc_table->EccInfo[i].ce_count_lo_chip; | |||
4101 | ecc_info_per_channel->ce_count_hi_chip = | |||
4102 | ecc_table->EccInfo[i].ce_count_hi_chip; | |||
4103 | ecc_info_per_channel->mca_umc_status = | |||
4104 | ecc_table->EccInfo[i].mca_umc_status; | |||
4105 | ecc_info_per_channel->mca_umc_addr = | |||
4106 | ecc_table->EccInfo[i].mca_umc_addr; | |||
4107 | } | |||
4108 | ||||
4109 | return ret; | |||
4110 | } | |||
4111 | static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) | |||
4112 | { | |||
4113 | uint16_t *mgpu_fan_boost_limit_rpm; | |||
4114 | ||||
4115 | GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm)do { if (smu->adev->ip_versions[MP1_HWIP][0] == (((11) << 16) | ((0) << 8) | (13))) (*&mgpu_fan_boost_limit_rpm ) = (smu->smu_table.driver_pptable + __builtin_offsetof(PPTable_beige_goby_t , MGpuFanBoostLimitRpm)); else (*&mgpu_fan_boost_limit_rpm ) = (smu->smu_table.driver_pptable + __builtin_offsetof(PPTable_t , MGpuFanBoostLimitRpm));} while(0); | |||
4116 | /* | |||
4117 | * Skip the MGpuFanBoost setting for those ASICs | |||
4118 | * which do not support it | |||
4119 | */ | |||
4120 | if (*mgpu_fan_boost_limit_rpm == 0) | |||
4121 | return 0; | |||
4122 | ||||
4123 | return smu_cmn_send_smc_msg_with_param(smu, | |||
4124 | SMU_MSG_SetMGpuFanBoostLimitRpm, | |||
4125 | 0, | |||
4126 | NULL((void *)0)); | |||
4127 | } | |||
4128 | ||||
4129 | static int sienna_cichlid_gpo_control(struct smu_context *smu, | |||
4130 | bool_Bool enablement) | |||
4131 | { | |||
4132 | uint32_t smu_version; | |||
4133 | int ret = 0; | |||
4134 | ||||
4135 | ||||
4136 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { | |||
4137 | ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
4138 | if (ret) | |||
4139 | return ret; | |||
4140 | ||||
4141 | if (enablement) { | |||
4142 | if (smu_version < 0x003a2500) { | |||
4143 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
4144 | SMU_MSG_SetGpoFeaturePMask, | |||
4145 | GFX_GPO_PACE_MASK(1 << 0) | GFX_GPO_DEM_MASK(1 << 1 ), | |||
4146 | NULL((void *)0)); | |||
4147 | } else { | |||
4148 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
4149 | SMU_MSG_DisallowGpo, | |||
4150 | 0, | |||
4151 | NULL((void *)0)); | |||
4152 | } | |||
4153 | } else { | |||
4154 | if (smu_version < 0x003a2500) { | |||
4155 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
4156 | SMU_MSG_SetGpoFeaturePMask, | |||
4157 | 0, | |||
4158 | NULL((void *)0)); | |||
4159 | } else { | |||
4160 | ret = smu_cmn_send_smc_msg_with_param(smu, | |||
4161 | SMU_MSG_DisallowGpo, | |||
4162 | 1, | |||
4163 | NULL((void *)0)); | |||
4164 | } | |||
4165 | } | |||
4166 | } | |||
4167 | ||||
4168 | return ret; | |||
4169 | } | |||
4170 | ||||
4171 | static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) | |||
4172 | { | |||
4173 | uint32_t smu_version; | |||
4174 | int ret = 0; | |||
4175 | ||||
4176 | ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
4177 | if (ret) | |||
4178 | return ret; | |||
4179 | ||||
4180 | /* | |||
4181 | * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 | |||
4182 | * onwards PMFWs. | |||
4183 | */ | |||
4184 | if (smu_version < 0x003A2D00) | |||
4185 | return 0; | |||
4186 | ||||
4187 | return smu_cmn_send_smc_msg_with_param(smu, | |||
4188 | SMU_MSG_Enable2ndUSB20Port, | |||
4189 | smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? | |||
4190 | 1 : 0, | |||
4191 | NULL((void *)0)); | |||
4192 | } | |||
4193 | ||||
4194 | static int sienna_cichlid_system_features_control(struct smu_context *smu, | |||
4195 | bool_Bool en) | |||
4196 | { | |||
4197 | int ret = 0; | |||
4198 | ||||
4199 | if (en) { | |||
4200 | ret = sienna_cichlid_notify_2nd_usb20_port(smu); | |||
4201 | if (ret) | |||
4202 | return ret; | |||
4203 | } | |||
4204 | ||||
4205 | return smu_v11_0_system_features_control(smu, en); | |||
4206 | } | |||
4207 | ||||
4208 | static int sienna_cichlid_set_mp1_state(struct smu_context *smu, | |||
4209 | enum pp_mp1_state mp1_state) | |||
4210 | { | |||
4211 | int ret; | |||
4212 | ||||
4213 | switch (mp1_state) { | |||
4214 | case PP_MP1_STATE_UNLOAD: | |||
4215 | ret = smu_cmn_set_mp1_state(smu, mp1_state); | |||
4216 | break; | |||
4217 | default: | |||
4218 | /* Ignore others */ | |||
4219 | ret = 0; | |||
4220 | } | |||
4221 | ||||
4222 | return ret; | |||
4223 | } | |||
4224 | ||||
4225 | static void sienna_cichlid_stb_init(struct smu_context *smu) | |||
4226 | { | |||
4227 | struct amdgpu_device *adev = smu->adev; | |||
4228 | uint32_t reg; | |||
4229 | ||||
4230 | reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START)adev->pcie_rreg(adev, (0x03b00000 | 0x3030204)); | |||
4231 | smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE)(((reg) & 0x80000000L) >> 0x0000001f); | |||
4232 | ||||
4233 | /* STB is disabled */ | |||
4234 | if (!smu->stb_context.enabled) | |||
4235 | return; | |||
4236 | ||||
4237 | mtx_init(&smu->stb_context.lock, IPL_NONE)do { (void)(((void *)0)); (void)(0); __mtx_init((&smu-> stb_context.lock), ((((0x0)) > 0x0 && ((0x0)) < 0x9) ? 0x9 : ((0x0)))); } while (0); | |||
4238 | ||||
4239 | /* STB buffer size in bytes as function of FIFO depth */ | |||
4240 | reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO)adev->pcie_rreg(adev, (0x03b00000 | 0x3030208)); | |||
4241 | smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH)(((reg) & 0x00000fffL) >> 0x00000000); | |||
4242 | smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES8; | |||
4243 | ||||
4244 | dev_info(smu->adev->dev, "STB initialized to %d entries",do { } while(0) | |||
4245 | smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES)do { } while(0); | |||
4246 | ||||
4247 | } | |||
4248 | ||||
4249 | static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, | |||
4250 | struct config_table_setting *table) | |||
4251 | { | |||
4252 | struct amdgpu_device *adev = smu->adev; | |||
4253 | ||||
4254 | if (!table) | |||
4255 | return -EINVAL22; | |||
4256 | ||||
4257 | table->gfxclk_average_tau = 10; | |||
4258 | table->socclk_average_tau = 10; | |||
4259 | table->fclk_average_tau = 10; | |||
4260 | table->uclk_average_tau = 10; | |||
4261 | table->gfx_activity_average_tau = 10; | |||
4262 | table->mem_activity_average_tau = 10; | |||
4263 | table->socket_power_average_tau = 100; | |||
4264 | if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7))) | |||
4265 | table->apu_socket_power_average_tau = 100; | |||
4266 | ||||
4267 | return 0; | |||
4268 | } | |||
4269 | ||||
4270 | static int sienna_cichlid_set_config_table(struct smu_context *smu, | |||
4271 | struct config_table_setting *table) | |||
4272 | { | |||
4273 | DriverSmuConfigExternal_t driver_smu_config_table; | |||
4274 | ||||
4275 | if (!table) | |||
4276 | return -EINVAL22; | |||
4277 | ||||
4278 | memset(&driver_smu_config_table,__builtin_memset((&driver_smu_config_table), (0), (sizeof (driver_smu_config_table))) | |||
4279 | 0,__builtin_memset((&driver_smu_config_table), (0), (sizeof (driver_smu_config_table))) | |||
4280 | sizeof(driver_smu_config_table))__builtin_memset((&driver_smu_config_table), (0), (sizeof (driver_smu_config_table))); | |||
4281 | driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = | |||
4282 | table->gfxclk_average_tau; | |||
4283 | driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = | |||
4284 | table->fclk_average_tau; | |||
4285 | driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = | |||
4286 | table->uclk_average_tau; | |||
4287 | driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = | |||
4288 | table->gfx_activity_average_tau; | |||
4289 | driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = | |||
4290 | table->mem_activity_average_tau; | |||
4291 | driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = | |||
4292 | table->socket_power_average_tau; | |||
4293 | ||||
4294 | return smu_cmn_update_table(smu, | |||
4295 | SMU_TABLE_DRIVER_SMU_CONFIG, | |||
4296 | 0, | |||
4297 | (void *)&driver_smu_config_table, | |||
4298 | true1); | |||
4299 | } | |||
4300 | ||||
4301 | static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, | |||
4302 | void *buf, | |||
4303 | uint32_t size) | |||
4304 | { | |||
4305 | uint32_t *p = buf; | |||
4306 | struct amdgpu_device *adev = smu->adev; | |||
4307 | ||||
4308 | /* No need to disable interrupts for now as we don't lock it yet from ISR */ | |||
4309 | spin_lock(&smu->stb_context.lock)mtx_enter(&smu->stb_context.lock); | |||
4310 | ||||
4311 | /* | |||
4312 | * Read the STB FIFO in units of 32bit since this is the accessor window | |||
4313 | * (register width) we have. | |||
4314 | */ | |||
4315 | buf = ((char *) buf) + size; | |||
4316 | while ((void *)p < buf) | |||
4317 | *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3))((__uint32_t)(adev->pcie_rreg(adev, (0x03b00000 | 0x3030600 )))); | |||
4318 | ||||
4319 | spin_unlock(&smu->stb_context.lock)mtx_leave(&smu->stb_context.lock); | |||
4320 | ||||
4321 | return 0; | |||
4322 | } | |||
4323 | ||||
4324 | static bool_Bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu) | |||
4325 | { | |||
4326 | return true1; | |||
4327 | } | |||
4328 | ||||
4329 | static int sienna_cichlid_mode2_reset(struct smu_context *smu) | |||
4330 | { | |||
4331 | u32 smu_version; | |||
4332 | int ret = 0, index; | |||
4333 | struct amdgpu_device *adev = smu->adev; | |||
4334 | int timeout = 100; | |||
4335 | ||||
4336 | smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version); | |||
4337 | ||||
4338 | index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, | |||
4339 | SMU_MSG_DriverMode2Reset); | |||
4340 | ||||
4341 | mutex_lock(&smu->message_lock)rw_enter_write(&smu->message_lock); | |||
4342 | ||||
4343 | ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, | |||
4344 | SMU_RESET_MODE_2); | |||
4345 | ||||
4346 | ret = smu_cmn_wait_for_response(smu); | |||
4347 | while (ret != 0 && timeout) { | |||
4348 | ret = smu_cmn_wait_for_response(smu); | |||
4349 | /* Wait a bit more time for getting ACK */ | |||
4350 | if (ret != 0) { | |||
4351 | --timeout; | |||
4352 | usleep_range(500, 1000); | |||
4353 | continue; | |||
4354 | } else { | |||
4355 | break; | |||
4356 | } | |||
4357 | } | |||
4358 | ||||
4359 | if (!timeout) { | |||
4360 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "failed to send mode2 message \tparam: 0x%08x response %#x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , SMU_RESET_MODE_2 , ret) | |||
4361 | "failed to send mode2 message \tparam: 0x%08x response %#x\n",printf("drm:pid%d:%s *ERROR* " "failed to send mode2 message \tparam: 0x%08x response %#x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , SMU_RESET_MODE_2 , ret) | |||
4362 | SMU_RESET_MODE_2, ret)printf("drm:pid%d:%s *ERROR* " "failed to send mode2 message \tparam: 0x%08x response %#x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , SMU_RESET_MODE_2 , ret); | |||
4363 | goto out; | |||
4364 | } | |||
4365 | ||||
4366 | dev_info(smu->adev->dev, "restore config space...\n")do { } while(0); | |||
4367 | /* Restore the config space saved during init */ | |||
4368 | amdgpu_device_load_pci_state(adev->pdev); | |||
4369 | out: | |||
4370 | mutex_unlock(&smu->message_lock)rw_exit_write(&smu->message_lock); | |||
4371 | ||||
4372 | return ret; | |||
4373 | } | |||
4374 | ||||
4375 | static const struct pptable_funcs sienna_cichlid_ppt_funcs = { | |||
4376 | .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, | |||
4377 | .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, | |||
4378 | .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, | |||
4379 | .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, | |||
4380 | .i2c_init = sienna_cichlid_i2c_control_init, | |||
4381 | .i2c_fini = sienna_cichlid_i2c_control_fini, | |||
4382 | .print_clk_levels = sienna_cichlid_print_clk_levels, | |||
4383 | .force_clk_levels = sienna_cichlid_force_clk_levels, | |||
4384 | .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, | |||
4385 | .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, | |||
4386 | .display_config_changed = sienna_cichlid_display_config_changed, | |||
4387 | .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, | |||
4388 | .is_dpm_running = sienna_cichlid_is_dpm_running, | |||
4389 | .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, | |||
4390 | .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, | |||
4391 | .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, | |||
4392 | .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, | |||
4393 | .set_watermarks_table = sienna_cichlid_set_watermarks_table, | |||
4394 | .read_sensor = sienna_cichlid_read_sensor, | |||
4395 | .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, | |||
4396 | .set_performance_level = smu_v11_0_set_performance_level, | |||
4397 | .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, | |||
4398 | .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, | |||
4399 | .get_power_limit = sienna_cichlid_get_power_limit, | |||
4400 | .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, | |||
4401 | .dump_pptable = sienna_cichlid_dump_pptable, | |||
4402 | .init_microcode = smu_v11_0_init_microcode, | |||
4403 | .load_microcode = smu_v11_0_load_microcode, | |||
4404 | .fini_microcode = smu_v11_0_fini_microcode, | |||
4405 | .init_smc_tables = sienna_cichlid_init_smc_tables, | |||
4406 | .fini_smc_tables = smu_v11_0_fini_smc_tables, | |||
4407 | .init_power = smu_v11_0_init_power, | |||
4408 | .fini_power = smu_v11_0_fini_power, | |||
4409 | .check_fw_status = smu_v11_0_check_fw_status, | |||
4410 | .setup_pptable = sienna_cichlid_setup_pptable, | |||
4411 | .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, | |||
4412 | .check_fw_version = smu_v11_0_check_fw_version, | |||
4413 | .write_pptable = smu_cmn_write_pptable, | |||
4414 | .set_driver_table_location = smu_v11_0_set_driver_table_location, | |||
4415 | .set_tool_table_location = smu_v11_0_set_tool_table_location, | |||
4416 | .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, | |||
4417 | .system_features_control = sienna_cichlid_system_features_control, | |||
4418 | .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, | |||
4419 | .send_smc_msg = smu_cmn_send_smc_msg, | |||
4420 | .init_display_count = NULL((void *)0), | |||
4421 | .set_allowed_mask = smu_v11_0_set_allowed_mask, | |||
4422 | .get_enabled_mask = smu_cmn_get_enabled_mask, | |||
4423 | .feature_is_enabled = smu_cmn_feature_is_enabled, | |||
4424 | .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, | |||
4425 | .notify_display_change = NULL((void *)0), | |||
4426 | .set_power_limit = smu_v11_0_set_power_limit, | |||
4427 | .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, | |||
4428 | .enable_thermal_alert = smu_v11_0_enable_thermal_alert, | |||
4429 | .disable_thermal_alert = smu_v11_0_disable_thermal_alert, | |||
4430 | .set_min_dcef_deep_sleep = NULL((void *)0), | |||
4431 | .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, | |||
4432 | .get_fan_control_mode = smu_v11_0_get_fan_control_mode, | |||
4433 | .set_fan_control_mode = smu_v11_0_set_fan_control_mode, | |||
4434 | .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, | |||
4435 | .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, | |||
4436 | .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, | |||
4437 | .gfx_off_control = smu_v11_0_gfx_off_control, | |||
4438 | .register_irq_handler = smu_v11_0_register_irq_handler, | |||
4439 | .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, | |||
4440 | .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, | |||
4441 | .baco_is_support = smu_v11_0_baco_is_support, | |||
4442 | .baco_get_state = smu_v11_0_baco_get_state, | |||
4443 | .baco_set_state = smu_v11_0_baco_set_state, | |||
4444 | .baco_enter = sienna_cichlid_baco_enter, | |||
4445 | .baco_exit = sienna_cichlid_baco_exit, | |||
4446 | .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, | |||
4447 | .mode1_reset = smu_v11_0_mode1_reset, | |||
4448 | .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, | |||
4449 | .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, | |||
4450 | .set_default_od_settings = sienna_cichlid_set_default_od_settings, | |||
4451 | .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, | |||
4452 | .restore_user_od_settings = sienna_cichlid_restore_user_od_settings, | |||
4453 | .run_btc = sienna_cichlid_run_btc, | |||
4454 | .set_power_source = smu_v11_0_set_power_source, | |||
4455 | .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, | |||
4456 | .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, | |||
4457 | .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, | |||
4458 | .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, | |||
4459 | .gfx_ulv_control = smu_v11_0_gfx_ulv_control, | |||
4460 | .deep_sleep_control = smu_v11_0_deep_sleep_control, | |||
4461 | .get_fan_parameters = sienna_cichlid_get_fan_parameters, | |||
4462 | .interrupt_work = smu_v11_0_interrupt_work, | |||
4463 | .gpo_control = sienna_cichlid_gpo_control, | |||
4464 | .set_mp1_state = sienna_cichlid_set_mp1_state, | |||
4465 | .stb_collect_info = sienna_cichlid_stb_get_data_direct, | |||
4466 | .get_ecc_info = sienna_cichlid_get_ecc_info, | |||
4467 | .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, | |||
4468 | .set_config_table = sienna_cichlid_set_config_table, | |||
4469 | .get_unique_id = sienna_cichlid_get_unique_id, | |||
4470 | .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported, | |||
4471 | .mode2_reset = sienna_cichlid_mode2_reset, | |||
4472 | }; | |||
4473 | ||||
4474 | void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) | |||
4475 | { | |||
4476 | smu->ppt_funcs = &sienna_cichlid_ppt_funcs; | |||
4477 | smu->message_map = sienna_cichlid_message_map; | |||
4478 | smu->clock_map = sienna_cichlid_clk_map; | |||
4479 | smu->feature_map = sienna_cichlid_feature_mask_map; | |||
4480 | smu->table_map = sienna_cichlid_table_map; | |||
4481 | smu->pwr_src_map = sienna_cichlid_pwr_src_map; | |||
4482 | smu->workload_map = sienna_cichlid_workload_map; | |||
4483 | smu_v11_0_set_smu_mailbox_registers(smu); | |||
4484 | } |