/usr/src/sys/dev/pci/drm/radeon/atombios

Bug Summary

File:	dev/pci/drm/radeon/atombios_encoders.c
Warning:	line 2785, column 1 Potential leak of memory pointed to by 'radeon_encoder'

Annotated Source Code

Press '?' to see keyboard shortcuts

Show analyzer invocation

clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name atombios_encoders.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/radeon/atombios_encoders.c

/usr/src/sys/dev/pci/drm/radeon/atombios_encoders.c

→

1/*
* Copyright 2007-11 Advanced Micro Devices, Inc.
* Copyright 2008 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Dave Airlie
*          Alex Deucher
*/

27#include <linux/backlight.h>
28#include <linux/dmi.h>
29#include <linux/pci.h>

31#include <drm/drm_crtc_helper.h>
32#include <drm/drm_file.h>
33#include <drm/radeon_drm.h>

35#include <acpi/video.h>

37#include "atom.h"
38#include "radeon_atombios.h"
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "radeon_audio.h"

43extern int atom_debug;

45static u8
46radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
47{
u8 backlight_level;
u32 bios_2_scratch;

if (rdev->family >= CHIP_R600)
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH)r100_mm_rreg(rdev, (0x172c), 0);
else
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH)r100_mm_rreg(rdev, (0x0018), 0);

backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK0x0000FF00L) >>
	   ATOM_S2_CURRENT_BL_LEVEL_SHIFT8);

return backlight_level;
60}

62static void
63radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
		       u8 backlight_level)
65{
u32 bios_2_scratch;

if (rdev->family >= CHIP_R600)
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH)r100_mm_rreg(rdev, (0x172c), 0);
else
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH)r100_mm_rreg(rdev, (0x0018), 0);

bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK0x0000FF00L;
bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT8) &
	   ATOM_S2_CURRENT_BL_LEVEL_MASK0x0000FF00L);

if (rdev->family >= CHIP_R600)
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch)r100_mm_wreg(rdev, (0x172c), (bios_2_scratch), 0);
else
WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch)r100_mm_wreg(rdev, (0x0018), (bios_2_scratch), 0);
81}

83u8
84atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
85{
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;

if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU0x0020))
return 0;

return radeon_atom_get_backlight_level_from_reg(rdev);
93}

95void
96atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
97{
struct drm_encoder *encoder = &radeon_encoder->base;
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder_atom_dig *dig;
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATIONDISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS args;
int index;

if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU0x0020))
return;

if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) &&
   radeon_encoder->enc_priv) {
dig = radeon_encoder->enc_priv;
dig->backlight_level = level;
radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, HW_Misc_Operation
)/sizeof(USHORT));
	if (dig->backlight_level == 0) {
		args.ucAction = ATOM_LCD_BLOFF(0 +2);
		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
	} else {
		args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL(1 +3);
		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		args.ucAction = ATOM_LCD_BLON(1 +2);
		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
	}
	break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
	if (dig->backlight_level == 0)
		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF2, 0, 0);
	else {
		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL4, 0, 0);
		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON3, 0, 0);
	}
	break;
default:
	break;
}
}
144}

146static u8 radeon_atom_bl_level(struct backlight_device *bd)
147{
u8 level;

/* Convert brightness to hardware level */
if (bd->props.brightness < 0)
level = 0;
else if (bd->props.brightness > RADEON_MAX_BL_LEVEL0xFF)
level = RADEON_MAX_BL_LEVEL0xFF;
else
level = bd->props.brightness;

return level;
159}

161static int radeon_atom_backlight_update_status(struct backlight_device *bd)
162{
struct radeon_backlight_privdata *pdata = bl_get_data(bd);
struct radeon_encoder *radeon_encoder = pdata->encoder;

atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));

return 0;
169}

171static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
172{
struct radeon_backlight_privdata *pdata = bl_get_data(bd);
struct radeon_encoder *radeon_encoder = pdata->encoder;
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;

return radeon_atom_get_backlight_level_from_reg(rdev);
179}

181static const struct backlight_ops radeon_atom_backlight_ops = {
.get_brightness = radeon_atom_backlight_get_brightness,
.update_status	= radeon_atom_backlight_update_status,
184};

186void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
		struct drm_connector *drm_connector)
188{
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
struct backlight_device *bd;
struct backlight_properties props;
struct radeon_backlight_privdata *pdata;
struct radeon_encoder_atom_dig *dig;
char bl_name[16];

/* Mac laptops with multiple GPUs use the gmux driver for backlight
* so don't register a backlight device
*/
if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE0x106b) &&
   (rdev->pdev->device == 0x6741) &&
   !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
return;

if (!radeon_encoder->enc_priv)
return;

if (!rdev->is_atom_bios)
return;

if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU0x0020))
return;

if (!acpi_video_backlight_use_native()) {
drm_info(dev, "Skipping radeon atom DIG backlight registration\n")do { } while(0);
return;
}

pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL(0x0001 | 0x0004));
if (!pdata) {
DRM_ERROR("Memory allocation failed\n")__drm_err("Memory allocation failed\n");
goto error;
}

memset(&props, 0, sizeof(props))__builtin_memset((&props), (0), (sizeof(props)));
props.max_brightness = RADEON_MAX_BL_LEVEL0xFF;
props.type = BACKLIGHT_RAW0;
snprintf(bl_name, sizeof(bl_name),
 "radeon_bl%d", dev->primary->index);
bd = backlight_device_register(bl_name, drm_connector->kdev,
		       pdata, &radeon_atom_backlight_ops, &props);
if (IS_ERR(bd)) {
DRM_ERROR("Backlight registration failed\n")__drm_err("Backlight registration failed\n");
goto error;
}

pdata->encoder = radeon_encoder;

dig = radeon_encoder->enc_priv;
dig->bl_dev = bd;

bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
/* Set a reasonable default here if the level is 0 otherwise
* fbdev will attempt to turn the backlight on after console
* unblanking and it will try and restore 0 which turns the backlight
* off again.
*/
if (bd->props.brightness == 0)
bd->props.brightness = RADEON_MAX_BL_LEVEL0xFF;
bd->props.power = FB_BLANK_UNBLANK0;
backlight_update_status(bd);

DRM_INFO("radeon atom DIG backlight initialized\n")printk("\0016" "[" "drm" "] " "radeon atom DIG backlight initialized\n"
);
rdev->mode_info.bl_encoder = radeon_encoder;

return;

258error:
kfree(pdata);
return;
261}

263static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
264{
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
struct backlight_device *bd = NULL((void *)0);
struct radeon_encoder_atom_dig *dig;

if (!radeon_encoder->enc_priv)
return;

if (!rdev->is_atom_bios)
return;

if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU0x0020))
return;

dig = radeon_encoder->enc_priv;
bd = dig->bl_dev;
dig->bl_dev = NULL((void *)0);

if (bd) {
struct radeon_legacy_backlight_privdata *pdata;

pdata = bl_get_data(bd);
backlight_device_unregister(bd);
kfree(pdata);

DRM_INFO("radeon atom LVDS backlight unloaded\n")printk("\0016" "[" "drm" "] " "radeon atom LVDS backlight unloaded\n"
);
}
292}

294static bool_Bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
		   const struct drm_display_mode *mode,
		   struct drm_display_mode *adjusted_mode)
297{
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;

/* set the active encoder to connector routing */
radeon_encoder_set_active_device(encoder);
drm_mode_set_crtcinfo(adjusted_mode, 0);

/* hw bug */
if ((mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
   && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;

/* vertical FP must be at least 1 */
if (mode->crtc_vsync_start == mode->crtc_vdisplay)
adjusted_mode->crtc_vsync_start++;

/* get the native mode for scaling */
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
radeon_panel_mode_fixup(encoder, adjusted_mode);
} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )))) {
struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
if (tv_dac) {
	if (tv_dac->tv_std == TV_STD_NTSC ||
	    tv_dac->tv_std == TV_STD_NTSC_J ||
	    tv_dac->tv_std == TV_STD_PAL_M)
		radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
	else
		radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
}
} else if (radeon_encoder->rmx_type != RMX_OFF) {
radeon_panel_mode_fixup(encoder, adjusted_mode);
}

if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620)) &&
   ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )) | ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) ||
    (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE0x00))) {
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
radeon_dp_set_link_config(connector, adjusted_mode);
}

return true1;
340}

342static void
343atombios_dac_setup(struct drm_encoder *encoder, int action)
344{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
DAC_ENCODER_CONTROL_PS_ALLOCATIONDAC_ENCODER_CONTROL_PARAMETERS args;
int index = 0;
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DAC1EncoderControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DAC2EncoderControl
)/sizeof(USHORT));
break;
}

args.ucAction = action;

if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 ))))
args.ucDacStandard = ATOM_DAC1_PS21;
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
args.ucDacStandard = ATOM_DAC1_CV2;
else {
switch (dac_info->tv_std) {
case TV_STD_PAL:
case TV_STD_PAL_M:
case TV_STD_SCART_PAL:
case TV_STD_SECAM:
case TV_STD_PAL_CN:
	args.ucDacStandard = ATOM_DAC1_PAL4;
	break;
case TV_STD_NTSC:
case TV_STD_NTSC_J:
case TV_STD_PAL_60:
default:
	args.ucDacStandard = ATOM_DAC1_NTSC3;
	break;
}
}
args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

392}

394static void
395atombios_tv_setup(struct drm_encoder *encoder, int action)
396{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
TV_ENCODER_CONTROL_PS_ALLOCATION args;
int index = 0;
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, TVEncoderControl
)/sizeof(USHORT));

args.sTVEncoder.ucAction = action;

if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
args.sTVEncoder.ucTvStandard = ATOM_TV_CV16;
else {
switch (dac_info->tv_std) {
case TV_STD_NTSC:
	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC1;
	break;
case TV_STD_PAL:
	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL3;
	break;
case TV_STD_PAL_M:
	args.sTVEncoder.ucTvStandard = ATOM_TV_PALM4;
	break;
case TV_STD_PAL_60:
	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL607;
	break;
case TV_STD_NTSC_J:
	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ2;
	break;
case TV_STD_SCART_PAL:
	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL3; /* ??? */
	break;
case TV_STD_SECAM:
	args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM8;
	break;
case TV_STD_PAL_CN:
	args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN5;
	break;
default:
	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC1;
	break;
}
}

args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

448}

450static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
451{
int bpc = 8;

if (encoder->crtc) {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});
bpc = radeon_crtc->bpc;
}

switch (bpc) {
case 0:
return PANEL_BPC_UNDEFINE0x00;
case 6:
return PANEL_6BIT_PER_COLOR0x01;
case 8:
default:
return PANEL_8BIT_PER_COLOR0x02;
case 10:
return PANEL_10BIT_PER_COLOR0x03;
case 12:
return PANEL_12BIT_PER_COLOR0x04;
case 16:
return PANEL_16BIT_PER_COLOR0x05;
}
474}

476union dvo_encoder_control {
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
DVO_ENCODER_CONTROL_PS_ALLOCATION_V3DVO_ENCODER_CONTROL_PARAMETERS_V3 dvo_v3;
DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4DVO_ENCODER_CONTROL_PARAMETERS_V1_4 dvo_v4;
481};

483void
484atombios_dvo_setup(struct drm_encoder *encoder, int action)
485{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
union dvo_encoder_control args;
int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DVOEncoderControl
)/sizeof(USHORT));
uint8_t frev, crev;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

/* some R4xx chips have the wrong frev */
if (rdev->family <= CHIP_RV410)
frev = 1;

switch (frev) {
case 1:
switch (crev) {
case 1:
	/* R4xx, R5xx */
	args.ext_tmds.sXTmdsEncoder.ucEnable = action;

	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL0x01;

	args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB0x00000002;
	break;
case 2:
	/* RS600/690/740 */
	args.dvo.sDVOEncoder.ucAction = action;
	args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	/* DFP1, CRT1, TV1 depending on the type of port */
	args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX0x00000003;

	if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL0x01;
	break;
case 3:
	/* R6xx */
	args.dvo_v3.ucAction = action;
	args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	args.dvo_v3.ucDVOConfig = 0; /* XXX */
	break;
case 4:
	/* DCE8 */
	args.dvo_v4.ucAction = action;
	args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	args.dvo_v4.ucDVOConfig = 0; /* XXX */
	args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
	break;
default:
	DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
	break;
}
break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
break;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
548}

550union lvds_encoder_control {
LVDS_ENCODER_CONTROL_PS_ALLOCATIONLVDS_ENCODER_CONTROL_PARAMETERS    v1;
LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2LVDS_ENCODER_CONTROL_PARAMETERS_V2 v2;
553};

555void
556atombios_digital_setup(struct drm_encoder *encoder, int action)
557{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
union lvds_encoder_control args;
int index = 0;
int hdmi_detected = 0;
uint8_t frev, crev;

if (!dig)
return;

if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3)
hdmi_detected = 1;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, MC_SEQ_Control
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, PatchMCSetting
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, MC_SEQ_Control
)/sizeof(USHORT));
else
	index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, LVTMAEncoderControl
)/sizeof(USHORT));
break;
}

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

switch (frev) {
case 1:
case 2:
switch (crev) {
case 1:
	args.v1.ucMisc = 0;
	args.v1.ucAction = action;
	if (hdmi_detected)
		args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE0x08;
	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
		if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL0x00000001)
			args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL0x01;
		if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB0x00000002)
			args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB0x00000002;
	} else {
		if (dig->linkb)
			args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB0x04;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL0x01;
		/*if (pScrn->rgbBits == 8) */
		args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB0x00000002;
	}
	break;
case 2:
case 3:
	args.v2.ucMisc = 0;
	args.v2.ucAction = action;
	if (crev == 3) {
		if (dig->coherent_mode)
			args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT0x02;
	}
	if (hdmi_detected)
		args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE0x08;
	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	args.v2.ucTruncate = 0;
	args.v2.ucSpatial = 0;
	args.v2.ucTemporal = 0;
	args.v2.ucFRC = 0;
	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
		if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL0x00000001)
			args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL0x01;
		if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL0x00000020) {
			args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN0x01;
			if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB0x00000002)
				args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH0x10;
		}
		if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL0x00000040) {
			args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN0x01;
			if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB0x00000002)
				args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH0x10;
			if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT2) & 0x3) == 2)
				args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_40x20;
		}
	} else {
		if (dig->linkb)
			args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB0x04;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL0x01;
	}
	break;
default:
	DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
	break;
}
break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
break;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
666}

668int
669atombios_get_encoder_mode(struct drm_encoder *encoder)
670{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_connector *connector;
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *dig_connector;

/* dp bridges are always DP */
if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE0x00)
return ATOM_ENCODER_MODE_DP0;

/* DVO is always DVO */
if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO10x0B) ||
   (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14))
return ATOM_ENCODER_MODE_DVO16;

connector = radeon_get_connector_for_encoder(encoder);
/* if we don't have an active device yet, just use one of
* the connectors tied to the encoder.
*/
if (!connector)
connector = radeon_get_connector_for_encoder_init(encoder);
radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});

switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DVII2:
case DRM_MODE_CONNECTOR_HDMIB12: /* HDMI-B is basically DL-DVI; analog works fine */
if (radeon_audio != 0) {
	if (radeon_connector->use_digital &&
	    (radeon_connector->audio == RADEON_AUDIO_ENABLE))
		return ATOM_ENCODER_MODE_HDMI3;
	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		 (radeon_connector->audio == RADEON_AUDIO_AUTO))
		return ATOM_ENCODER_MODE_HDMI3;
	else if (radeon_connector->use_digital)
		return ATOM_ENCODER_MODE_DVI2;
	else
		return ATOM_ENCODER_MODE_CRT15;
} else if (radeon_connector->use_digital) {
	return ATOM_ENCODER_MODE_DVI2;
} else {
	return ATOM_ENCODER_MODE_CRT15;
}
break;
case DRM_MODE_CONNECTOR_DVID3:
case DRM_MODE_CONNECTOR_HDMIA11:
default:
if (radeon_audio != 0) {
	if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
		return ATOM_ENCODER_MODE_HDMI3;
	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		 (radeon_connector->audio == RADEON_AUDIO_AUTO))
		return ATOM_ENCODER_MODE_HDMI3;
	else
		return ATOM_ENCODER_MODE_DVI2;
} else {
	return ATOM_ENCODER_MODE_DVI2;
}
break;
case DRM_MODE_CONNECTOR_LVDS7:
return ATOM_ENCODER_MODE_LVDS1;
break;
case DRM_MODE_CONNECTOR_DisplayPort10:
dig_connector = radeon_connector->con_priv;
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT0x13) ||
    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP0x14)) {
	if (radeon_audio != 0 &&
	    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
	    ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)) && !ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)))
		return ATOM_ENCODER_MODE_DP_AUDIO5;
	return ATOM_ENCODER_MODE_DP0;
} else if (radeon_audio != 0) {
	if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
		return ATOM_ENCODER_MODE_HDMI3;
	else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
		 (radeon_connector->audio == RADEON_AUDIO_AUTO))
		return ATOM_ENCODER_MODE_HDMI3;
	else
		return ATOM_ENCODER_MODE_DVI2;
} else {
	return ATOM_ENCODER_MODE_DVI2;
}
break;
case DRM_MODE_CONNECTOR_eDP14:
if (radeon_audio != 0 &&
    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
    ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)) && !ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)))
	return ATOM_ENCODER_MODE_DP_AUDIO5;
return ATOM_ENCODER_MODE_DP0;
case DRM_MODE_CONNECTOR_DVIA4:
case DRM_MODE_CONNECTOR_VGA1:
return ATOM_ENCODER_MODE_CRT15;
break;
case DRM_MODE_CONNECTOR_Composite5:
case DRM_MODE_CONNECTOR_SVIDEO6:
case DRM_MODE_CONNECTOR_9PinDIN9:
/* fix me */
return ATOM_ENCODER_MODE_TV13;
/*return ATOM_ENCODER_MODE_CV;*/
break;
}
772}

774/*
* DIG Encoder/Transmitter Setup
*
* DCE 3.0/3.1
* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
* Supports up to 3 digital outputs
* - 2 DIG encoder blocks.
* DIG1 can drive UNIPHY link A or link B
* DIG2 can drive UNIPHY link B or LVTMA
*
* DCE 3.2
* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
* Supports up to 5 digital outputs
* - 2 DIG encoder blocks.
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
*
* DCE 4.0/5.0/6.0
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
* Supports up to 6 digital outputs
* - 6 DIG encoder blocks.
* - DIG to PHY mapping is hardcoded
* DIG1 drives UNIPHY0 link A, A+B
* DIG2 drives UNIPHY0 link B
* DIG3 drives UNIPHY1 link A, A+B
* DIG4 drives UNIPHY1 link B
* DIG5 drives UNIPHY2 link A, A+B
* DIG6 drives UNIPHY2 link B
*
* DCE 4.1
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
* Supports up to 6 digital outputs
* - 2 DIG encoder blocks.
* llano
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
* ontario
* DIG1 drives UNIPHY0/1/2 link A
* DIG2 drives UNIPHY0/1/2 link B
*
* Routing
* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
* Examples:
* crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
* crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
* crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
* crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
*/

821union dig_encoder_control {
DIG_ENCODER_CONTROL_PS_ALLOCATIONDIG_ENCODER_CONTROL_PARAMETERS v1;
DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
826};

828void
829atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
830{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
union dig_encoder_control args;
int index = 0;
uint8_t frev, crev;
int dp_clock = 0;
int dp_lane_count = 0;
int hpd_id = RADEON_HPD_NONE;

if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
struct radeon_connector_atom_dig *dig_connector =
	radeon_connector->con_priv;

dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
hpd_id = radeon_connector->hpd.hpd;
}

/* no dig encoder assigned */
if (dig->dig_encoder == -1)
return;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIGxEncoderControl
)/sizeof(USHORT));
else {
if (dig->dig_encoder)
	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIG2EncoderControl
)/sizeof(USHORT));
else
	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIG1EncoderControl
)/sizeof(USHORT));
}

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

switch (frev) {
case 1:
switch (crev) {
case 1:
	args.v1.ucAction = action;
	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE0x10)
		args.v3.ucPanelMode = panel_mode;
	else
		args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);

	if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)(((args.v1.ucEncoderMode) == 0) || ((args.v1.ucEncoderMode) ==
 5)))
		args.v1.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v1.ucLaneNum = 8;
	else
		args.v1.ucLaneNum = 4;

	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER10x00;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
		args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER20x08;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER30x10;
		break;
	}
	if (dig->linkb)
		args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB0x04;
	else
		args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA0x00;

	if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)(((args.v1.ucEncoderMode) == 0) || ((args.v1.ucEncoderMode) ==
 5)) && (dp_clock == 270000))
		args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ0x01;

	break;
case 2:
case 3:
	args.v3.ucAction = action;
	args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE0x10)
		args.v3.ucPanelMode = panel_mode;
	else
		args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);

	if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)(((args.v3.ucEncoderMode) == 0) || ((args.v3.ucEncoderMode) ==
 5)))
		args.v3.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v3.ucLaneNum = 8;
	else
		args.v3.ucLaneNum = 4;

	if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)(((args.v3.ucEncoderMode) == 0) || ((args.v3.ucEncoderMode) ==
 5)) && (dp_clock == 270000))
		args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ0x01;
	if (enc_override != -1)
		args.v3.acConfig.ucDigSel = enc_override;
	else
		args.v3.acConfig.ucDigSel = dig->dig_encoder;
	args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
	break;
case 4:
	args.v4.ucAction = action;
	args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE0x10)
		args.v4.ucPanelMode = panel_mode;
	else
		args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);

	if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)(((args.v4.ucEncoderMode) == 0) || ((args.v4.ucEncoderMode) ==
 5)))
		args.v4.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v4.ucLaneNum = 8;
	else
		args.v4.ucLaneNum = 4;

	if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)(((args.v4.ucEncoderMode) == 0) || ((args.v4.ucEncoderMode) ==
 5))) {
		if (dp_clock == 540000)
			args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ0x02;
		else if (dp_clock == 324000)
			args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ0x03;
		else if (dp_clock == 270000)
			args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ0x01;
		else
			args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ0x00;
	}

	if (enc_override != -1)
		args.v4.acConfig.ucDigSel = enc_override;
	else
		args.v4.acConfig.ucDigSel = dig->dig_encoder;
	args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
	if (hpd_id == RADEON_HPD_NONE)
		args.v4.ucHPD_ID = 0;
	else
		args.v4.ucHPD_ID = hpd_id + 1;
	break;
default:
	DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
	break;
}
break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
break;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

982}

984void
985atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
986{
atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
988}

990union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PS_ALLOCATIONDIG_TRANSMITTER_CONTROL_PARAMETERS v1;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
996};

998void
999atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1000{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
struct drm_connector *connector;
union dig_transmitter_control args;
int index = 0;
uint8_t frev, crev;
bool_Bool is_dp = false0;
int pll_id = 0;
int dp_clock = 0;
int dp_lane_count = 0;
int connector_object_id = 0;
int igp_lane_info = 0;
int dig_encoder = dig->dig_encoder;
int hpd_id = RADEON_HPD_NONE;

if (action == ATOM_TRANSMITTER_ACTION_INIT7) {
connector = radeon_get_connector_for_encoder_init(encoder);
/* just needed to avoid bailing in the encoder check.  the encoder
 * isn't used for init
 */
dig_encoder = 0;
} else
connector = radeon_get_connector_for_encoder(encoder);

if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
struct radeon_connector_atom_dig *dig_connector =
	radeon_connector->con_priv;

hpd_id = radeon_connector->hpd.hpd;
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
connector_object_id =
	(radeon_connector->connector_object_id & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00;
igp_lane_info = dig_connector->igp_lane_info;
}

if (encoder->crtc) {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});
pll_id = radeon_crtc->pll_id;
}

/* no dig encoder assigned */
if (dig_encoder == -1)
return;

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)))
is_dp = true1;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DVOOutputControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIG1TransmitterControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIG2TransmitterControl
)/sizeof(USHORT));
break;
}

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

switch (frev) {
case 1:
switch (crev) {
case 1:
	args.v1.ucAction = action;
	if (action == ATOM_TRANSMITTER_ACTION_INIT7) {
		args.v1.usInitInfo = cpu_to_le16(connector_object_id)((__uint16_t)(connector_object_id));
	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH11) {
		args.v1.asMode.ucLaneSel = lane_num;
		args.v1.asMode.ucLaneSet = lane_set;
	} else {
		if (is_dp)
			args.v1.usPixelClock = cpu_to_le16(dp_clock / 10)((__uint16_t)(dp_clock / 10));
		else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10)((__uint16_t)((radeon_encoder->pixel_clock / 2) / 10));
		else
			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	}

	args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL0x00;

	if (dig_encoder)
		args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER0x08;
	else
		args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER0x00;

	if ((rdev->flags & RADEON_IS_IGP) &&
	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E)) {
		if (is_dp ||
		    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
			if (igp_lane_info & 0x1)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_30x00;
			else if (igp_lane_info & 0x2)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_70x40;
			else if (igp_lane_info & 0x4)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_110x80;
			else if (igp_lane_info & 0x8)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_150xc0;
		} else {
			if (igp_lane_info & 0x3)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_70x00;
			else if (igp_lane_info & 0xc)
				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_150x80;
		}
	}

	if (dig->linkb)
		args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB0x04;
	else
		args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA0x00;

	if (is_dp)
		args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT0x02;
	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )))) {
		if (dig->coherent_mode)
			args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT0x02;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK0x01;
	}
	break;
case 2:
	args.v2.ucAction = action;
	if (action == ATOM_TRANSMITTER_ACTION_INIT7) {
		args.v2.usInitInfo = cpu_to_le16(connector_object_id)((__uint16_t)(connector_object_id));
	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH11) {
		args.v2.asMode.ucLaneSel = lane_num;
		args.v2.asMode.ucLaneSet = lane_set;
	} else {
		if (is_dp)
			args.v2.usPixelClock = cpu_to_le16(dp_clock / 10)((__uint16_t)(dp_clock / 10));
		else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10)((__uint16_t)((radeon_encoder->pixel_clock / 2) / 10));
		else
			args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	}

	args.v2.acConfig.ucEncoderSel = dig_encoder;
	if (dig->linkb)
		args.v2.acConfig.ucLinkSel = 1;

	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		args.v2.acConfig.ucTransmitterSel = 0;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
		args.v2.acConfig.ucTransmitterSel = 1;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		args.v2.acConfig.ucTransmitterSel = 2;
		break;
	}

	if (is_dp) {
		args.v2.acConfig.fCoherentMode = 1;
		args.v2.acConfig.fDPConnector = 1;
	} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )))) {
		if (dig->coherent_mode)
			args.v2.acConfig.fCoherentMode = 1;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v2.acConfig.fDualLinkConnector = 1;
	}
	break;
case 3:
	args.v3.ucAction = action;
	if (action == ATOM_TRANSMITTER_ACTION_INIT7) {
		args.v3.usInitInfo = cpu_to_le16(connector_object_id)((__uint16_t)(connector_object_id));
	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH11) {
		args.v3.asMode.ucLaneSel = lane_num;
		args.v3.asMode.ucLaneSet = lane_set;
	} else {
		if (is_dp)
			args.v3.usPixelClock = cpu_to_le16(dp_clock / 10)((__uint16_t)(dp_clock / 10));
		else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10)((__uint16_t)((radeon_encoder->pixel_clock / 2) / 10));
		else
			args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	}

	if (is_dp)
		args.v3.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v3.ucLaneNum = 8;
	else
		args.v3.ucLaneNum = 4;

	if (dig->linkb)
		args.v3.acConfig.ucLinkSel = 1;
	if (dig_encoder & 1)
		args.v3.acConfig.ucEncoderSel = 1;

	/* Select the PLL for the PHY
	 * DP PHY should be clocked from external src if there is
	 * one.
	 */
	/* On DCE4, if there is an external clock, it generates the DP ref clock */
	if (is_dp && rdev->clock.dp_extclk)
		args.v3.acConfig.ucRefClkSource = 2; /* external src */
	else
		args.v3.acConfig.ucRefClkSource = pll_id;

	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		args.v3.acConfig.ucTransmitterSel = 0;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
		args.v3.acConfig.ucTransmitterSel = 1;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		args.v3.acConfig.ucTransmitterSel = 2;
		break;
	}

	if (is_dp)
		args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )))) {
		if (dig->coherent_mode)
			args.v3.acConfig.fCoherentMode = 1;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v3.acConfig.fDualLinkConnector = 1;
	}
	break;
case 4:
	args.v4.ucAction = action;
	if (action == ATOM_TRANSMITTER_ACTION_INIT7) {
		args.v4.usInitInfo = cpu_to_le16(connector_object_id)((__uint16_t)(connector_object_id));
	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH11) {
		args.v4.asMode.ucLaneSel = lane_num;
		args.v4.asMode.ucLaneSet = lane_set;
	} else {
		if (is_dp)
			args.v4.usPixelClock = cpu_to_le16(dp_clock / 10)((__uint16_t)(dp_clock / 10));
		else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10)((__uint16_t)((radeon_encoder->pixel_clock / 2) / 10));
		else
			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	}

	if (is_dp)
		args.v4.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v4.ucLaneNum = 8;
	else
		args.v4.ucLaneNum = 4;

	if (dig->linkb)
		args.v4.acConfig.ucLinkSel = 1;
	if (dig_encoder & 1)
		args.v4.acConfig.ucEncoderSel = 1;

	/* Select the PLL for the PHY
	 * DP PHY should be clocked from external src if there is
	 * one.
	 */
	/* On DCE5 DCPLL usually generates the DP ref clock */
	if (is_dp) {
		if (rdev->clock.dp_extclk)
			args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK3;
		else
			args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL2;
	} else
		args.v4.acConfig.ucRefClkSource = pll_id;

	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		args.v4.acConfig.ucTransmitterSel = 0;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
		args.v4.acConfig.ucTransmitterSel = 1;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		args.v4.acConfig.ucTransmitterSel = 2;
		break;
	}

	if (is_dp)
		args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )))) {
		if (dig->coherent_mode)
			args.v4.acConfig.fCoherentMode = 1;
		if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
			args.v4.acConfig.fDualLinkConnector = 1;
	}
	break;
case 5:
	args.v5.ucAction = action;
	if (is_dp)
		args.v5.usSymClock = cpu_to_le16(dp_clock / 10)((__uint16_t)(dp_clock / 10));
	else
		args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));

	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		if (dig->linkb)
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB1;
		else
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA0;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
		if (dig->linkb)
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD3;
		else
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC2;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		if (dig->linkb)
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF5;
		else
			args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE4;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
		args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG6;
		break;
	}
	if (is_dp)
		args.v5.ucLaneNum = dp_lane_count;
	else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v5.ucLaneNum = 8;
	else
		args.v5.ucLaneNum = 4;
	args.v5.ucConnObjId = connector_object_id;
	args.v5.ucDigMode = atombios_get_encoder_mode(encoder);

	if (is_dp && rdev->clock.dp_extclk)
		args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK3;
	else
		args.v5.asConfig.ucPhyClkSrcId = pll_id;

	if (is_dp)
		args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )))) {
		if (dig->coherent_mode)
			args.v5.asConfig.ucCoherentMode = 1;
	}
	if (hpd_id == RADEON_HPD_NONE)
		args.v5.asConfig.ucHPDSel = 0;
	else
		args.v5.asConfig.ucHPDSel = hpd_id + 1;
	args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
	args.v5.ucDPLaneSet = lane_set;
	break;
default:
	DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
	break;
}
break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev)__drm_err("Unknown table version %d, %d\n", frev, crev);
break;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1363}

1365void
1366atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1367{
atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1369}

1371bool_Bool
1372atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1373{
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
struct drm_device *dev = radeon_connector->base.dev;
struct radeon_device *rdev = dev->dev_private;
union dig_transmitter_control args;
int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DIG1TransmitterControl
)/sizeof(USHORT));
uint8_t frev, crev;

if (connector->connector_type != DRM_MODE_CONNECTOR_eDP14)
goto done;

if (!ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
goto done;

if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON12) &&
   (action != ATOM_TRANSMITTER_ACTION_POWER_OFF13))
goto done;

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
goto done;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

args.v1.ucAction = action;

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

/* wait for the panel to power up */
if (action == ATOM_TRANSMITTER_ACTION_POWER_ON12) {
int i;

for (i = 0; i < 300; i++) {
	if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)(rdev)->asic->hpd.sense((rdev), (radeon_connector->hpd
.hpd)))
		return true1;
	mdelay(1);
}
return false0;
}
1411done:
return true1;
1413}

1415union external_encoder_control {
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1418};

1420static void
1421atombios_external_encoder_setup(struct drm_encoder *encoder,
		struct drm_encoder *ext_encoder,
		int action)
1424{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (ext_encoder); (struct radeon_encoder *)( (char *)__mptr -
 __builtin_offsetof(struct radeon_encoder, base) );});
union external_encoder_control args;
struct drm_connector *connector;
int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ExternalEncoderControl
)/sizeof(USHORT));
u8 frev, crev;
int dp_clock = 0;
int dp_lane_count = 0;
int connector_object_id = 0;
u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK0x0700) >> ENUM_ID_SHIFT0x08;

if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT0x07)
connector = radeon_get_connector_for_encoder_init(encoder);
else
connector = radeon_get_connector_for_encoder(encoder);

if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
struct radeon_connector_atom_dig *dig_connector =
	radeon_connector->con_priv;

dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
connector_object_id =
	(radeon_connector->connector_object_id & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00;
}

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

switch (frev) {
case 1:
/* no params on frev 1 */
break;
case 2:
switch (crev) {
case 1:
case 2:
	args.v1.sDigEncoder.ucAction = action;
	args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);

	if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)(((args.v1.sDigEncoder.ucEncoderMode) == 0) || ((args.v1.sDigEncoder
.ucEncoderMode) == 5))) {
		if (dp_clock == 270000)
			args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ0x01;
		args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
	} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v1.sDigEncoder.ucLaneNum = 8;
	else
		args.v1.sDigEncoder.ucLaneNum = 4;
	break;
case 3:
	args.v3.sExtEncoder.ucAction = action;
	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT0x07)
		args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id)((__uint16_t)(connector_object_id));
	else
		args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10)((__uint16_t)(radeon_encoder->pixel_clock / 10));
	args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);

	if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)(((args.v3.sExtEncoder.ucEncoderMode) == 0) || ((args.v3.sExtEncoder
.ucEncoderMode) == 5))) {
		if (dp_clock == 270000)
			args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ0x01;
		else if (dp_clock == 540000)
			args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ0x02;
		args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
	} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
		args.v3.sExtEncoder.ucLaneNum = 8;
	else
		args.v3.sExtEncoder.ucLaneNum = 4;
	switch (ext_enum) {
	case GRAPH_OBJECT_ENUM_ID10x01:
		args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER10x00;
		break;
	case GRAPH_OBJECT_ENUM_ID20x02:
		args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER20x10;
		break;
	case GRAPH_OBJECT_ENUM_ID30x03:
		args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER30x20;
		break;
	}
	args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
	break;
default:
	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev)__drm_err("Unknown table version: %d, %d\n", frev, crev);
	return;
}
break;
default:
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev)__drm_err("Unknown table version: %d, %d\n", frev, crev);
return;
}
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1521}

1523static void
1524atombios_yuv_setup(struct drm_encoder *encoder, bool_Bool enable)
1525{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});
ENABLE_YUV_PS_ALLOCATIONENABLE_YUV_PARAMETERS args;
int index = GetIndexIntoMasterTable(COMMAND, EnableYUV)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, GetDispObjectInfo
)/sizeof(USHORT));
uint32_t temp, reg;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (rdev->family >= CHIP_R600)
reg = R600_BIOS_3_SCRATCH0x1730;
else
reg = RADEON_BIOS_3_SCRATCH0x001c;

/* XXX: fix up scratch reg handling */
temp = RREG32(reg)r100_mm_rreg(rdev, (reg), 0);
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
WREG32(reg, (ATOM_S3_TV1_ACTIVE |r100_mm_wreg(rdev, (reg), ((0x00000004L | (radeon_crtc->crtc_id
 << 18))), 0)
	     (radeon_crtc->crtc_id << 18)))r100_mm_wreg(rdev, (reg), ((0x00000004L | (radeon_crtc->crtc_id
 << 18))), 0);
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)))r100_mm_wreg(rdev, (reg), ((0x00000100L | (radeon_crtc->crtc_id
 << 24))), 0);
else
WREG32(reg, 0)r100_mm_wreg(rdev, (reg), (0), 0);

if (enable)
args.ucEnable = ATOM_ENABLE1;
args.ucCRTC = radeon_crtc->crtc_id;

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

WREG32(reg, temp)r100_mm_wreg(rdev, (reg), (temp), 0);
1558}

1560static void
1561radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1562{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATIONDISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS args;
int index = 0;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, TMDSAOutputControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DVOOutputControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, HW_Misc_Operation
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, HW_Misc_Operation
)/sizeof(USHORT));
else
	index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, LVTMAOutputControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, Gfx_Harvesting
)/sizeof(USHORT));
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, CV1OutputControl
)/sizeof(USHORT));
else
	index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DAC1OutputControl
)/sizeof(USHORT));
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, Gfx_Harvesting
)/sizeof(USHORT));
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, CV1OutputControl
)/sizeof(USHORT));
else
	index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DAC2OutputControl
)/sizeof(USHORT));
break;
default:
return;
}

switch (mode) {
case DRM_MODE_DPMS_ON0:
args.ucAction = ATOM_ENABLE1;
/* workaround for DVOOutputControl on some RS690 systems */
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI0x19) {
	u32 reg = RREG32(RADEON_BIOS_3_SCRATCH)r100_mm_rreg(rdev, (0x001c), 0);
	WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE)r100_mm_wreg(rdev, (0x001c), (reg & ~0x00000200L), 0);
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
	WREG32(RADEON_BIOS_3_SCRATCH, reg)r100_mm_wreg(rdev, (0x001c), (reg), 0);
} else
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
	if (rdev->mode_info.bl_encoder) {
		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

		atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
	} else {
		args.ucAction = ATOM_LCD_BLON(1 +2);
		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
	}
}
break;
case DRM_MODE_DPMS_STANDBY1:
case DRM_MODE_DPMS_SUSPEND2:
case DRM_MODE_DPMS_OFF3:
args.ucAction = ATOM_DISABLE0;
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
	args.ucAction = ATOM_LCD_BLOFF(0 +2);
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}
break;
}
1645}

1647static void
1648radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1649{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
struct radeon_connector *radeon_connector = NULL((void *)0);
struct radeon_connector_atom_dig *radeon_dig_connector = NULL((void *)0);
bool_Bool travis_quirk = false0;

if (connector) {
radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
radeon_dig_connector = radeon_connector->con_priv;
if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
     ENCODER_OBJECT_ID_TRAVIS0x23) &&
    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) &&
    !ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS)))
	travis_quirk = true1;
}

switch (mode) {
case DRM_MODE_DPMS_ON0:
if (ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
 & RADEON_IS_IGP)) || ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS))) {
	if (!connector)
		dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE0x00;
	else
		dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);

	/* setup and enable the encoder */
	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP0x0f, 0);
	atombios_dig_encoder_setup(encoder,
				   ATOM_ENCODER_CMD_SETUP_PANEL_MODE0x10,
				   dig->panel_mode);
	if (ext_encoder) {
		if (ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
 & RADEON_IS_IGP)) || ASIC_IS_DCE61(rdev)((rdev->family >= CHIP_ARUBA) && (rdev->flags
 & RADEON_IS_IGP)))
			atombios_external_encoder_setup(encoder, ext_encoder,
							EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP0x0f);
	}
} else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
	/* setup and enable the encoder */
	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP0x0f, 0);
} else {
	/* setup and enable the encoder and transmitter */
	atombios_dig_encoder_setup(encoder, ATOM_ENABLE1, 0);
	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP10, 0, 0);
}
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)) && connector) {
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14) {
		atombios_set_edp_panel_power(connector,
					     ATOM_TRANSMITTER_ACTION_POWER_ON12);
		radeon_dig_connector->edp_on = true1;
	}
}
/* enable the transmitter */
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE1, 0, 0);
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)) && connector) {
	/* DP_SET_POWER_D0 is set in radeon_dp_link_train */
	radeon_dp_link_train(encoder, connector);
	if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON0x0d, 0);
}
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
	if (rdev->mode_info.bl_encoder)
		atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
	else
		atombios_dig_transmitter_setup(encoder,
					       ATOM_TRANSMITTER_ACTION_LCD_BLON3, 0, 0);
}
if (ext_encoder)
	atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE1);
break;
case DRM_MODE_DPMS_STANDBY1:
case DRM_MODE_DPMS_SUSPEND2:
case DRM_MODE_DPMS_OFF3:

if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)) && connector)
		atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF0x0c, 0);
}
if (ext_encoder)
	atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE0);
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
	atombios_dig_transmitter_setup(encoder,
				       ATOM_TRANSMITTER_ACTION_LCD_BLOFF2, 0, 0);

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)) &&
    connector && !travis_quirk)
	radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D30x2);
if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
	/* disable the transmitter */
	atombios_dig_transmitter_setup(encoder,
				       ATOM_TRANSMITTER_ACTION_DISABLE0, 0, 0);
} else {
	/* disable the encoder and transmitter */
	atombios_dig_transmitter_setup(encoder,
				       ATOM_TRANSMITTER_ACTION_DISABLE0, 0, 0);
	atombios_dig_encoder_setup(encoder, ATOM_DISABLE0, 0);
}
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))(((atombios_get_encoder_mode(encoder)) == 0) || ((atombios_get_encoder_mode
(encoder)) == 5)) && connector) {
	if (travis_quirk)
		radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D30x2);
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14) {
		atombios_set_edp_panel_power(connector,
					     ATOM_TRANSMITTER_ACTION_POWER_OFF13);
		radeon_dig_connector->edp_on = false0;
	}
}
break;
}
1759}

1761static void
1762radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1763{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
int encoder_mode = atombios_get_encoder_mode(encoder);

DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",___drm_dbg(((void *)0), DRM_UT_KMS, "encoder dpms %d to mode %d, devices %08x, active_devices %08x\n"
, radeon_encoder->encoder_id, mode, radeon_encoder->devices
, radeon_encoder->active_device)
  radeon_encoder->encoder_id, mode, radeon_encoder->devices,___drm_dbg(((void *)0), DRM_UT_KMS, "encoder dpms %d to mode %d, devices %08x, active_devices %08x\n"
, radeon_encoder->encoder_id, mode, radeon_encoder->devices
, radeon_encoder->active_device)
  radeon_encoder->active_device)___drm_dbg(((void *)0), DRM_UT_KMS, "encoder dpms %d to mode %d, devices %08x, active_devices %08x\n"
, radeon_encoder->encoder_id, mode, radeon_encoder->devices
, radeon_encoder->active_device);

if ((radeon_audio != 0) &&
   ((encoder_mode == ATOM_ENCODER_MODE_HDMI3) ||
    ENCODER_MODE_IS_DP(encoder_mode)(((encoder_mode) == 0) || ((encoder_mode) == 5))))
radeon_audio_dpms(encoder, mode);

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
radeon_atom_encoder_dpms_avivo(encoder, mode);
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
radeon_atom_encoder_dpms_dig(encoder, mode);
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
if (ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS))) {
	switch (mode) {
	case DRM_MODE_DPMS_ON0:
		atombios_dvo_setup(encoder, ATOM_ENABLE1);
		break;
	case DRM_MODE_DPMS_STANDBY1:
	case DRM_MODE_DPMS_SUSPEND2:
	case DRM_MODE_DPMS_OFF3:
		atombios_dvo_setup(encoder, ATOM_DISABLE0);
		break;
	}
} else if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620)))
	radeon_atom_encoder_dpms_dig(encoder, mode);
else
	radeon_atom_encoder_dpms_avivo(encoder, mode);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
if (ASIC_IS_DCE5(rdev)((rdev->family >= CHIP_BARTS))) {
	switch (mode) {
	case DRM_MODE_DPMS_ON0:
		atombios_dac_setup(encoder, ATOM_ENABLE1);
		break;
	case DRM_MODE_DPMS_STANDBY1:
	case DRM_MODE_DPMS_SUSPEND2:
	case DRM_MODE_DPMS_OFF3:
		atombios_dac_setup(encoder, ATOM_DISABLE0);
		break;
	}
} else
	radeon_atom_encoder_dpms_avivo(encoder, mode);
break;
default:
return;
}

radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON0) ? true1 : false0);

1835}

1837union crtc_source_param {
SELECT_CRTC_SOURCE_PS_ALLOCATIONSELECT_CRTC_SOURCE_PARAMETERS v1;
SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1840};

1842static void
1843atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1844{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});
union crtc_source_param args;
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, SelectCRTC_Source
)/sizeof(USHORT));
uint8_t frev, crev;
struct radeon_encoder_atom_dig *dig;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
return;

switch (frev) {
case 1:
switch (crev) {
case 1:
default:
	if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
		args.v1.ucCRTC = radeon_crtc->crtc_id;
	else {
		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC10x04)
			args.v1.ucCRTC = radeon_crtc->crtc_id;
		else
			args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
	}
	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
		args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX0x00000003;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
	case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
		if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ))
			args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX0x00000001;
		else
			args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX0x00000009;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
	case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
		args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX0x00000007;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
			args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX0x00000002;
		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
			args.v1.ucDevice = ATOM_DEVICE_CV_INDEX0x00000008;
		else
			args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX0x00000000;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
			args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX0x00000002;
		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
			args.v1.ucDevice = ATOM_DEVICE_CV_INDEX0x00000008;
		else
			args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX0x00000004;
		break;
	}
	break;
case 2:
	args.v2.ucCRTC = radeon_crtc->crtc_id;
	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE0x00) {
		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

		if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS7)
			args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS1;
		else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA1)
			args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT15;
		else
			args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
	} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
		args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS1;
	} else {
		args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
	}
	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
		dig = radeon_encoder->enc_priv;
		switch (dig->dig_encoder) {
		case 0:
			args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID0x03;
			break;
		case 1:
			args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID0x09;
			break;
		case 2:
			args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID0x0a;
			break;
		case 3:
			args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID0x0b;
			break;
		case 4:
			args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID0x0c;
			break;
		case 5:
			args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID0x0d;
			break;
		case 6:
			args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID0x0e;
			break;
		}
		break;
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
		args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID0x07;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
			args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID0x02;
		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
			args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID0x02;
		else
			args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID0x00;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
			args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID0x02;
		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
			args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID0x02;
		else
			args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID0x04;
		break;
	}
	break;
}
break;
default:
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev)__drm_err("Unknown table version: %d, %d\n", frev, crev);
return;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

/* update scratch regs with new routing */
radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1988}

1990static void
1991atombios_apply_encoder_quirks(struct drm_encoder *encoder,
	      struct drm_display_mode *mode)
1993{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});

/* Funky macbooks */
if ((rdev->pdev->device == 0x71C5) &&
   (rdev->pdev->subsystem_vendor == 0x106b) &&
   (rdev->pdev->subsystem_device == 0x0080)) {
if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )) {
	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL)r100_mm_rreg(rdev, (0x7a94), 0);

	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN(1 << 0);
	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN(1 << 8);

	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control)r100_mm_wreg(rdev, (0x7a94), (lvtma_bit_depth_control), 0);
}
}

/* set scaler clears this on some chips */
if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) &&
   (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )))))) {
if (ASIC_IS_DCE8(rdev)((rdev->family >= CHIP_BONAIRE))) {
	if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
		WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), ((
<< 3)), 0)
		       CIK_INTERLEAVE_EN)r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), ((
<< 3)), 0);
	else
		WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), (0
), 0);
} else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
	if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
		WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), ((
<< 0)), 0)
		       EVERGREEN_INTERLEAVE_EN)r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), ((
<< 0)), 0);
	else
		WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6b00 + radeon_crtc->crtc_offset), (0
), 0);
} else {
	if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
		WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6528 + radeon_crtc->crtc_offset), ((
<< 0)), 0)
		       AVIVO_D1MODE_INTERLEAVE_EN)r100_mm_wreg(rdev, (0x6528 + radeon_crtc->crtc_offset), ((
<< 0)), 0);
	else
		WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0)r100_mm_wreg(rdev, (0x6528 + radeon_crtc->crtc_offset), (0
), 0);
}
}
2036}

2038void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2039{
if (enc_idx < 0)
return;
rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2043}

2045int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2046{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (encoder->crtc); (struct radeon_crtc *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_crtc, base) );});
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_encoder *test_encoder;
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
uint32_t dig_enc_in_use = 0;
int enc_idx = -1;

if (fe_idx >= 0) {
enc_idx = fe_idx;
goto assigned;
}
if (ASIC_IS_DCE6(rdev)((rdev->family >= CHIP_ARUBA))) {
/* DCE6 */
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
	if (dig->linkb)
		enc_idx = 1;
	else
		enc_idx = 0;
	break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
	if (dig->linkb)
		enc_idx = 3;
	else
		enc_idx = 2;
	break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
	if (dig->linkb)
		enc_idx = 5;
	else
		enc_idx = 4;
	break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
	enc_idx = 6;
	break;
}
goto assigned;
} else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
/* DCE4/5 */
if (ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
 & RADEON_IS_IGP)) && !ASIC_IS_DCE61(rdev)((rdev->family >= CHIP_ARUBA) && (rdev->flags
 & RADEON_IS_IGP))) {
	/* ontario follows DCE4 */
	if (rdev->family == CHIP_PALM) {
		if (dig->linkb)
			enc_idx = 1;
		else
			enc_idx = 0;
	} else
		/* llano follows DCE3.2 */
		enc_idx = radeon_crtc->crtc_id;
} else {
	switch (radeon_encoder->encoder_id) {
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
		if (dig->linkb)
			enc_idx = 1;
		else
			enc_idx = 0;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
		if (dig->linkb)
			enc_idx = 3;
		else
			enc_idx = 2;
		break;
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
		if (dig->linkb)
			enc_idx = 5;
		else
			enc_idx = 4;
		break;
	}
}
goto assigned;
}

/*
* On DCE32 any encoder can drive any block so usually just use crtc id,
* but Apple thinks different at least on iMac10,1, so there use linkb,
* otherwise the internal eDP panel will stay dark.
*/
if (ASIC_IS_DCE32(rdev)((rdev->family >= CHIP_RV730))) {
if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
	enc_idx = (dig->linkb) ? 1 : 0;
else
	enc_idx = radeon_crtc->crtc_id;

goto assigned;
}

/* on DCE3 - LVTMA can only be driven by DIGB */
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head)for (test_encoder = ({ const __typeof( ((__typeof(*test_encoder
) *)0)->head ) *__mptr = ((&dev->mode_config.encoder_list
)->next); (__typeof(*test_encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*test_encoder), head) );}); &test_encoder->head
 != (&dev->mode_config.encoder_list); test_encoder = (
{ const __typeof( ((__typeof(*test_encoder) *)0)->head ) *
__mptr = (test_encoder->head.next); (__typeof(*test_encoder
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*test_encoder
), head) );})) {
struct radeon_encoder *radeon_test_encoder;

if (encoder == test_encoder)
	continue;

if (!radeon_encoder_is_digital(test_encoder))
	continue;

radeon_test_encoder = to_radeon_encoder(test_encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (test_encoder); (struct radeon_encoder *)( (char *)__mptr -
 __builtin_offsetof(struct radeon_encoder, base) );});
dig = radeon_test_encoder->enc_priv;

if (dig->dig_encoder >= 0)
	dig_enc_in_use |= (1 << dig->dig_encoder);
}

if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F) {
if (dig_enc_in_use & 0x2)
	DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n")__drm_err("LVDS required digital encoder 2 but it was in use - stealing\n"
);
return 1;
}
if (!(dig_enc_in_use & 1))
return 0;
return 1;

2163assigned:
if (enc_idx == -1) {
DRM_ERROR("Got encoder index incorrect - returning 0\n")__drm_err("Got encoder index incorrect - returning 0\n");
return 0;
}
if (rdev->mode_info.active_encoders & (1 << enc_idx))
DRM_ERROR("chosen encoder in use %d\n", enc_idx)__drm_err("chosen encoder in use %d\n", enc_idx);

rdev->mode_info.active_encoders |= (1 << enc_idx);
return enc_idx;
2173}

2175/* This only needs to be called once at startup */
2176void
2177radeon_atom_encoder_init(struct radeon_device *rdev)
2178{
struct drm_device *dev = rdev->ddev;
struct drm_encoder *encoder;

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );})) {
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT7, 0, 0);
	break;
default:
	break;
}

if (ext_encoder && (ASIC_IS_DCE41(rdev)((rdev->family >= CHIP_PALM) && (rdev->flags
 & RADEON_IS_IGP)) || ASIC_IS_DCE61(rdev)((rdev->family >= CHIP_ARUBA) && (rdev->flags
 & RADEON_IS_IGP))))
	atombios_external_encoder_setup(encoder, ext_encoder,
					EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT0x07);
}
2202}

2204static void
2205radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
	     struct drm_display_mode *mode,
	     struct drm_display_mode *adjusted_mode)
2208{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
int encoder_mode;

radeon_encoder->pixel_clock = adjusted_mode->clock;

/* need to call this here rather than in prepare() since we need some crtc info */
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);

if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)) && !ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR))) {
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 ) | ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 ))))
	atombios_yuv_setup(encoder, true1);
else
	atombios_yuv_setup(encoder, false0);
}

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE1);
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
/* handled in dpms */
break;
case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
atombios_dvo_setup(encoder, ATOM_ENABLE1);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
atombios_dac_setup(encoder, ATOM_ENABLE1);
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )) | ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 ))) {
	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )) | ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
		atombios_tv_setup(encoder, ATOM_ENABLE1);
	else
		atombios_tv_setup(encoder, ATOM_DISABLE0);
}
break;
}

atombios_apply_encoder_quirks(encoder, adjusted_mode);

encoder_mode = atombios_get_encoder_mode(encoder);
if (connector && (radeon_audio != 0) &&
   ((encoder_mode == ATOM_ENCODER_MODE_HDMI3) ||
    ENCODER_MODE_IS_DP(encoder_mode)(((encoder_mode) == 0) || ((encoder_mode) == 5))))
radeon_audio_mode_set(encoder, adjusted_mode);
2267}

2269static bool_Bool
2270atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2271{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});

if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )) |
		       ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 ) |
		       ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) {
DAC_LOAD_DETECTION_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DAC_LoadDetection
)/sizeof(USHORT));
uint8_t frev, crev;

memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args)));

if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
	return false0;

args.sDacload.ucMisc = 0;

if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC10x04) ||
    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15))
	args.sDacload.ucDacType = ATOM_DAC_A0;
else
	args.sDacload.ucDacType = ATOM_DAC_B1;

if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ))
	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT)((__uint16_t)((0x1L << 0x00000000 )));
else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ))
	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT)((__uint16_t)((0x1L << 0x00000004 )));
else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )) {
	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT)((__uint16_t)((0x1L << 0x00000008 )));
	if (crev >= 3)
		args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb0x01;
} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) {
	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT)((__uint16_t)((0x1L << 0x00000002 )));
	if (crev >= 3)
		args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb0x01;
}

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

return true1;
} else
return false0;
2316}

2318static enum drm_connector_status
2319radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2320{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
uint32_t bios_0_scratch;

if (!atombios_dac_load_detect(encoder, connector)) {
DRM_DEBUG_KMS("detect returned false \n")___drm_dbg(((void *)0), DRM_UT_KMS, "detect returned false \n"
);
return connector_status_unknown;
}

if (rdev->family >= CHIP_R600)
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH)r100_mm_rreg(rdev, (0x1724), 0);
else
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH)r100_mm_rreg(rdev, (0x0010), 0);

DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices)___drm_dbg(((void *)0), DRM_UT_KMS, "Bios 0 scratch %x %08x\n"
, bios_0_scratch, radeon_encoder->devices);
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) {
if (bios_0_scratch & ATOM_S0_CRT1_MASK(0x00000001L +0x00000002L))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) {
if (bios_0_scratch & ATOM_S0_CRT2_MASK(0x00000100L +0x00000200L))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )) {
if (bios_0_scratch & (ATOM_S0_CV_MASK(0x00001000L +0x00002000L)|ATOM_S0_CV_MASK_A(0x00000010L +0x00000020L)))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) {
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE0x00000400L | ATOM_S0_TV1_COMPOSITE_A0x00000004L))
	return connector_status_connected; /* CTV */
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO0x00000800L | ATOM_S0_TV1_SVIDEO_A0x00000008L))
	return connector_status_connected; /* STV */
}
return connector_status_disconnected;
2357}

2359static enum drm_connector_status
2360radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2361{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
u32 bios_0_scratch;

if (!ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
return connector_status_unknown;

if (!ext_encoder)
return connector_status_unknown;

if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 ))) == 0)
return connector_status_unknown;

/* load detect on the dp bridge */
atombios_external_encoder_setup(encoder, ext_encoder,
			EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION0x12);

bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH)r100_mm_rreg(rdev, (0x1724), 0);

DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices)___drm_dbg(((void *)0), DRM_UT_KMS, "Bios 0 scratch %x %08x\n"
, bios_0_scratch, radeon_encoder->devices);
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) {
if (bios_0_scratch & ATOM_S0_CRT1_MASK(0x00000001L +0x00000002L))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) {
if (bios_0_scratch & ATOM_S0_CRT2_MASK(0x00000100L +0x00000200L))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )) {
if (bios_0_scratch & (ATOM_S0_CV_MASK(0x00001000L +0x00002000L)|ATOM_S0_CV_MASK_A(0x00000010L +0x00000020L)))
	return connector_status_connected;
}
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) {
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE0x00000400L | ATOM_S0_TV1_COMPOSITE_A0x00000004L))
	return connector_status_connected; /* CTV */
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO0x00000800L | ATOM_S0_TV1_SVIDEO_A0x00000008L))
	return connector_status_connected; /* STV */
}
return connector_status_disconnected;
2404}

2406void
2407radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2408{
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);

if (ext_encoder)
/* ddc_setup on the dp bridge */
atombios_external_encoder_setup(encoder, ext_encoder,
				EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP0x14);

2416}

2418static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2419{
struct radeon_device *rdev = encoder->dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

if ((radeon_encoder->active_device &
    (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 )) | ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) ||
   (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
    ENCODER_OBJECT_ID_NONE0x00)) {
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
if (dig) {
	if (dig->dig_encoder >= 0)
		radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
	dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
	if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
 << 0x0000000B ) | (0x1L << 0x00000006 ))) {
		if (rdev->family >= CHIP_R600)
			dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
		else
			/* RS600/690/740 have only 1 afmt block */
			dig->afmt = rdev->mode_info.afmt[0];
	}
}
}

radeon_atom_output_lock(encoder, true1);

if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});

/* select the clock/data port if it uses a router */
if (radeon_connector->router.cd_valid)
	radeon_router_select_cd_port(radeon_connector);

/* turn eDP panel on for mode set */
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)
	atombios_set_edp_panel_power(connector,
				     ATOM_TRANSMITTER_ACTION_POWER_ON12);
}

/* this is needed for the pll/ss setup to work correctly in some cases */
atombios_set_encoder_crtc_source(encoder);
/* set up the FMT blocks */
if (ASIC_IS_DCE8(rdev)((rdev->family >= CHIP_BONAIRE)))
dce8_program_fmt(encoder);
else if (ASIC_IS_DCE4(rdev)((rdev->family >= CHIP_CEDAR)))
dce4_program_fmt(encoder);
else if (ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620)))
dce3_program_fmt(encoder);
else if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
avivo_program_fmt(encoder);
2469}

2471static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2472{
/* need to call this here as we need the crtc set up */
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON0);
radeon_atom_output_lock(encoder, false0);
2476}

2478static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2479{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
struct radeon_encoder_atom_dig *dig;

/* check for pre-DCE3 cards with shared encoders;
* can't really use the links individually, so don't disable
* the encoder if it's in use by another connector
*/
if (!ASIC_IS_DCE3(rdev)((rdev->family >= CHIP_RV620))) {
struct drm_encoder *other_encoder;
struct radeon_encoder *other_radeon_encoder;

list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head)for (other_encoder = ({ const __typeof( ((__typeof(*other_encoder
) *)0)->head ) *__mptr = ((&dev->mode_config.encoder_list
)->next); (__typeof(*other_encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*other_encoder), head) );}); &other_encoder->
head != (&dev->mode_config.encoder_list); other_encoder
 = ({ const __typeof( ((__typeof(*other_encoder) *)0)->head
 ) *__mptr = (other_encoder->head.next); (__typeof(*other_encoder
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*other_encoder
), head) );})) {
	other_radeon_encoder = to_radeon_encoder(other_encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (other_encoder); (struct radeon_encoder *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_encoder, base) );});
	if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
	    drm_helper_encoder_in_use(other_encoder))
		goto disable_done;
}
}

radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);

switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE0);
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
/* handled in dpms */
break;
case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
atombios_dvo_setup(encoder, ATOM_DISABLE0);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
atombios_dac_setup(encoder, ATOM_DISABLE0);
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )) | ATOM_DEVICE_CV_SUPPORT(0x1L << 0x00000008 )))
	atombios_tv_setup(encoder, ATOM_DISABLE0);
break;
}

2532disable_done:
if (radeon_encoder_is_digital(encoder)) {
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3) {
	if (rdev->asic->display.hdmi_enable)
		radeon_hdmi_enable(rdev, encoder, false)(rdev)->asic->display.hdmi_enable((encoder), (0));
}
if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST5) {
	dig = radeon_encoder->enc_priv;
	radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
	dig->dig_encoder = -1;
	radeon_encoder->active_device = 0;
}
} else
radeon_encoder->active_device = 0;
2546}

2548/* these are handled by the primary encoders */
2549static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2550{

2552}

2554static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2555{

2557}

2559static void
2560radeon_atom_ext_mode_set(struct drm_encoder *encoder,
	 struct drm_display_mode *mode,
	 struct drm_display_mode *adjusted_mode)
2563{

2565}

2567static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2568{

2570}

2572static void
2573radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2574{

2576}

2578static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
.dpms = radeon_atom_ext_dpms,
.prepare = radeon_atom_ext_prepare,
.mode_set = radeon_atom_ext_mode_set,
.commit = radeon_atom_ext_commit,
.disable = radeon_atom_ext_disable,
/* no detect for TMDS/LVDS yet */
2585};

2587static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
.dpms = radeon_atom_encoder_dpms,
.mode_fixup = radeon_atom_mode_fixup,
.prepare = radeon_atom_encoder_prepare,
.mode_set = radeon_atom_encoder_mode_set,
.commit = radeon_atom_encoder_commit,
.disable = radeon_atom_encoder_disable,
.detect = radeon_atom_dig_detect,
2595};

2597static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
.dpms = radeon_atom_encoder_dpms,
.mode_fixup = radeon_atom_mode_fixup,
.prepare = radeon_atom_encoder_prepare,
.mode_set = radeon_atom_encoder_mode_set,
.commit = radeon_atom_encoder_commit,
.detect = radeon_atom_dac_detect,
2604};

2606void radeon_enc_destroy(struct drm_encoder *encoder)
2607{
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
radeon_atom_backlight_exit(radeon_encoder);
kfree(radeon_encoder->enc_priv);
drm_encoder_cleanup(encoder);
kfree(radeon_encoder);
2614}

2616static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
.destroy = radeon_enc_destroy,
2618};

2620static struct radeon_encoder_atom_dac *
2621radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2622{
struct drm_device *dev = radeon_encoder->base.dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL(0x0001 | 0x0004));

if (!dac)
return NULL((void *)0);

dac->tv_std = radeon_atombios_get_tv_info(rdev);
return dac;
2632}

2634static struct radeon_encoder_atom_dig *
2635radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2636{
int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK0x0700) >> ENUM_ID_SHIFT0x08;
struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL(0x0001 | 0x0004));

if (!dig)
return NULL((void *)0);

/* coherent mode by default */
dig->coherent_mode = true1;
dig->dig_encoder = -1;

if (encoder_enum == 2)
dig->linkb = true1;
else
dig->linkb = false0;

return dig;
2653}

2655void
2656radeon_add_atom_encoder(struct drm_device *dev,
	uint32_t encoder_enum,
	uint32_t supported_device,
	u16 caps)
2660{
struct radeon_device *rdev = dev->dev_private;
struct drm_encoder *encoder;
struct radeon_encoder *radeon_encoder;

/* see if we already added it */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );})) {
1
Loop condition is false. Execution continues on line 2676→
radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
 = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
if (radeon_encoder->encoder_enum == encoder_enum) {
	radeon_encoder->devices |= supported_device;
	return;
}

}

/* add a new one */
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL(0x0001 | 0x0004));
2
←
Calling 'kzalloc'→
4
←
Returned allocated memory→
if (!radeon_encoder)
5
←
Assuming 'radeon_encoder' is non-null→
6
←
Taking false branch→
return;

encoder = &radeon_encoder->base;
switch (rdev->num_crtc) {
7
←
Control jumps to the 'default' case at line 2686→
case 1:
encoder->possible_crtcs = 0x1;
break;
case 2:
default:
encoder->possible_crtcs = 0x3;
break;
case 4:
encoder->possible_crtcs = 0xf;
break;
case 6:
encoder->possible_crtcs = 0x3f;
break;
}

radeon_encoder->enc_priv = NULL((void *)0);
8
←
 Execution continues on line 2697→

radeon_encoder->encoder_enum = encoder_enum;
radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00;
radeon_encoder->devices = supported_device;
radeon_encoder->rmx_type = RMX_OFF;
radeon_encoder->underscan_type = UNDERSCAN_OFF;
radeon_encoder->is_ext_encoder = false0;
radeon_encoder->caps = caps;

switch (radeon_encoder->encoder_id) {
9
←
'Default' branch taken. Execution continues on line 2660→
case ENCODER_OBJECT_ID_INTERNAL_LVDS0x01:
case ENCODER_OBJECT_ID_INTERNAL_TMDS10x02:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
	radeon_encoder->rmx_type = RMX_FULL;
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
} else {
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
}
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC10x04:
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
		 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC20x05:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
		 DRM_MODE_ENCODER_TVDAC4, NULL((void *)0));
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
break;
case ENCODER_OBJECT_ID_INTERNAL_DVO10x0B:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA0x1F:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
	radeon_encoder->rmx_type = RMX_FULL;
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) {
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
} else {
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
}
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
break;
case ENCODER_OBJECT_ID_SI170B0x08:
case ENCODER_OBJECT_ID_CH73030x09:
case ENCODER_OBJECT_ID_EXTERNAL_SDVOA0x0C:
case ENCODER_OBJECT_ID_EXTERNAL_SDVOB0x0D:
case ENCODER_OBJECT_ID_TITFP5130x0E:
case ENCODER_OBJECT_ID_VT16230x10:
case ENCODER_OBJECT_ID_HDMI_SI19300x11:
case ENCODER_OBJECT_ID_TRAVIS0x23:
case ENCODER_OBJECT_ID_NUTMEG0x22:
/* these are handled by the primary encoders */
radeon_encoder->is_ext_encoder = true1;
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 ))))
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
else
	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
			 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
break;
}
2785}
10
←
Potential leak of memory pointed to by 'radeon_encoder'

←

/usr/src/sys/dev/pci/drm/include/linux/slab.h

1/* Public domain. */
2 
3#ifndef _LINUX_SLAB_H
4#define _LINUX_SLAB_H
5 
6#include <sys/types.h>
7#include <sys/malloc.h>
8 
9#include <linux/types.h>
10#include <linux/workqueue.h>
11#include <linux/gfp.h>
12 
13#include <linux/processor.h>	/* for CACHELINESIZE */
14 
15#define ARCH_KMALLOC_MINALIGN64 CACHELINESIZE64
16 
17#define ZERO_SIZE_PTR((void *)0) NULL((void *)0)
18 
19static inline void *
20kmalloc(size_t size, int flags)
21{
22	return malloc(size, M_DRM145, flags);
23}
24 
25static inline void *
26kmalloc_array(size_t n, size_t size, int flags)
27{
28	if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
29		return NULL((void *)0);
30	return malloc(n * size, M_DRM145, flags);
31}
32 
33static inline void *
34kcalloc(size_t n, size_t size, int flags)
35{
36	if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
37		return NULL((void *)0);
38	return malloc(n * size, M_DRM145, flags | M_ZERO0x0008);
39}
40 
41static inline void *
42kzalloc(size_t size, int flags)
43{
44	return malloc(size, M_DRM145, flags | M_ZERO0x0008);
3
←
Memory is allocated→
45}
46 
47static inline void
48kfree(const void *objp)
49{
50	free((void *)objp, M_DRM145, 0);
51}
52 
53#endif