File: | dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |
Warning: | line 1019, column 19 Access to field 'inst' results in a dereference of a null pointer (loaded from field 'panel_cntl') |
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1 | /* | |||
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | * Authors: AMD | |||
23 | * | |||
24 | */ | |||
25 | ||||
26 | #include "dm_services.h" | |||
27 | #include "dc.h" | |||
28 | #include "dc_bios_types.h" | |||
29 | #include "core_types.h" | |||
30 | #include "core_status.h" | |||
31 | #include "resource.h" | |||
32 | #include "dm_helpers.h" | |||
33 | #include "dce110_timing_generator.h" | |||
34 | #include "dce/dce_hwseq.h" | |||
35 | #include "gpio_service_interface.h" | |||
36 | ||||
37 | #include "dce110_compressor.h" | |||
38 | ||||
39 | #include "bios/bios_parser_helper.h" | |||
40 | #include "timing_generator.h" | |||
41 | #include "mem_input.h" | |||
42 | #include "opp.h" | |||
43 | #include "ipp.h" | |||
44 | #include "transform.h" | |||
45 | #include "stream_encoder.h" | |||
46 | #include "link_encoder.h" | |||
47 | #include "link_enc_cfg.h" | |||
48 | #include "link_hwss.h" | |||
49 | #include "dc_link_dp.h" | |||
50 | #include "dccg.h" | |||
51 | #include "clock_source.h" | |||
52 | #include "clk_mgr.h" | |||
53 | #include "abm.h" | |||
54 | #include <hw/audio.h> | |||
55 | #include "reg_helper.h" | |||
56 | #include "panel_cntl.h" | |||
57 | #include "inc/link_dpcd.h" | |||
58 | #include "dpcd_defs.h" | |||
59 | /* include DCE11 register header files */ | |||
60 | #include "dce/dce_11_0_d.h" | |||
61 | #include "dce/dce_11_0_sh_mask.h" | |||
62 | #include "custom_float.h" | |||
63 | ||||
64 | #include "atomfirmware.h" | |||
65 | ||||
66 | #include "dcn10/dcn10_hw_sequencer.h" | |||
67 | ||||
68 | #include "link/link_dp_trace.h" | |||
69 | #include "dce110_hw_sequencer.h" | |||
70 | ||||
71 | #define GAMMA_HW_POINTS_NUM256 256 | |||
72 | ||||
73 | /* | |||
74 | * All values are in milliseconds; | |||
75 | * For eDP, after power-up/power/down, | |||
76 | * 300/500 msec max. delay from LCDVCC to black video generation | |||
77 | */ | |||
78 | #define PANEL_POWER_UP_TIMEOUT300 300 | |||
79 | #define PANEL_POWER_DOWN_TIMEOUT500 500 | |||
80 | #define HPD_CHECK_INTERVAL10 10 | |||
81 | #define OLED_POST_T7_DELAY100 100 | |||
82 | #define OLED_PRE_T11_DELAY150 150 | |||
83 | ||||
84 | #define CTXhws->ctx \ | |||
85 | hws->ctx | |||
86 | ||||
87 | #define DC_LOGGER_INIT() | |||
88 | ||||
89 | #define REG(reg)hws->regs->reg\ | |||
90 | hws->regs->reg | |||
91 | ||||
92 | #undef FN | |||
93 | #define FN(reg_name, field_name)hws->shifts->field_name, hws->masks->field_name \ | |||
94 | hws->shifts->field_name, hws->masks->field_name | |||
95 | ||||
96 | struct dce110_hw_seq_reg_offsets { | |||
97 | uint32_t crtc; | |||
98 | }; | |||
99 | ||||
100 | static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { | |||
101 | { | |||
102 | .crtc = (mmCRTC0_CRTC_GSL_CONTROL0x1b7b - mmCRTC_GSL_CONTROL0x1b7b), | |||
103 | }, | |||
104 | { | |||
105 | .crtc = (mmCRTC1_CRTC_GSL_CONTROL0x1d7b - mmCRTC_GSL_CONTROL0x1b7b), | |||
106 | }, | |||
107 | { | |||
108 | .crtc = (mmCRTC2_CRTC_GSL_CONTROL0x1f7b - mmCRTC_GSL_CONTROL0x1b7b), | |||
109 | }, | |||
110 | { | |||
111 | .crtc = (mmCRTCV_GSL_CONTROL0x477b - mmCRTC_GSL_CONTROL0x1b7b), | |||
112 | } | |||
113 | }; | |||
114 | ||||
115 | #define HW_REG_BLND(reg, id)(reg + reg_offsets[id].blnd)\ | |||
116 | (reg + reg_offsets[id].blnd) | |||
117 | ||||
118 | #define HW_REG_CRTC(reg, id)(reg + reg_offsets[id].crtc)\ | |||
119 | (reg + reg_offsets[id].crtc) | |||
120 | ||||
121 | #define MAX_WATERMARK0xFFFF 0xFFFF | |||
122 | #define SAFE_NBP_MARK0x7FFF 0x7FFF | |||
123 | ||||
124 | /******************************************************************************* | |||
125 | * Private definitions | |||
126 | ******************************************************************************/ | |||
127 | /***************************PIPE_CONTROL***********************************/ | |||
128 | static void dce110_init_pte(struct dc_context *ctx) | |||
129 | { | |||
130 | uint32_t addr; | |||
131 | uint32_t value = 0; | |||
132 | uint32_t chunk_int = 0; | |||
133 | uint32_t chunk_mul = 0; | |||
134 | ||||
135 | addr = mmUNP_DVMM_PTE_CONTROL0x4629; | |||
136 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); | |||
137 | ||||
138 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) | |||
139 | value,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) | |||
140 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) | |||
141 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) | |||
142 | DVMM_USE_SINGLE_PTE)(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0); | |||
143 | ||||
144 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) | |||
145 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) | |||
146 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) | |||
147 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) | |||
148 | DVMM_PTE_BUFFER_MODE0)(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ); | |||
149 | ||||
150 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) | |||
151 | value,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) | |||
152 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) | |||
153 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) | |||
154 | DVMM_PTE_BUFFER_MODE1)(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ); | |||
155 | ||||
156 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); | |||
157 | ||||
158 | addr = mmDVMM_PTE_REQ0x330; | |||
159 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); | |||
160 | ||||
161 | chunk_int = get_reg_field_value(get_reg_field_value_ex( (value), 0xff00, 0x8) | |||
162 | value,get_reg_field_value_ex( (value), 0xff00, 0x8) | |||
163 | DVMM_PTE_REQ,get_reg_field_value_ex( (value), 0xff00, 0x8) | |||
164 | HFLIP_PTEREQ_PER_CHUNK_INT)get_reg_field_value_ex( (value), 0xff00, 0x8); | |||
165 | ||||
166 | chunk_mul = get_reg_field_value(get_reg_field_value_ex( (value), 0x3f0000, 0x10) | |||
167 | value,get_reg_field_value_ex( (value), 0x3f0000, 0x10) | |||
168 | DVMM_PTE_REQ,get_reg_field_value_ex( (value), 0x3f0000, 0x10) | |||
169 | HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER)get_reg_field_value_ex( (value), 0x3f0000, 0x10); | |||
170 | ||||
171 | if (chunk_int != 0x4 || chunk_mul != 0x4) { | |||
172 | ||||
173 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) | |||
174 | value,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) | |||
175 | 255,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) | |||
176 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) | |||
177 | MAX_PTEREQ_TO_ISSUE)(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0); | |||
178 | ||||
179 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) | |||
180 | value,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) | |||
181 | 4,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) | |||
182 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) | |||
183 | HFLIP_PTEREQ_PER_CHUNK_INT)(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8); | |||
184 | ||||
185 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) | |||
186 | value,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) | |||
187 | 4,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) | |||
188 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) | |||
189 | HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER)(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ); | |||
190 | ||||
191 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); | |||
192 | } | |||
193 | } | |||
194 | /**************************************************************************/ | |||
195 | ||||
196 | static void enable_display_pipe_clock_gating( | |||
197 | struct dc_context *ctx, | |||
198 | bool_Bool clock_gating) | |||
199 | { | |||
200 | /*TODO*/ | |||
201 | } | |||
202 | ||||
203 | static bool_Bool dce110_enable_display_power_gating( | |||
204 | struct dc *dc, | |||
205 | uint8_t controller_id, | |||
206 | struct dc_bios *dcb, | |||
207 | enum pipe_gating_control power_gating) | |||
208 | { | |||
209 | enum bp_result bp_result = BP_RESULT_OK; | |||
210 | enum bp_pipe_control_action cntl; | |||
211 | struct dc_context *ctx = dc->ctx; | |||
212 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; | |||
213 | ||||
214 | if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)(ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) | |||
215 | return true1; | |||
216 | ||||
217 | if (power_gating == PIPE_GATING_CONTROL_INIT) | |||
218 | cntl = ASIC_PIPE_INIT; | |||
219 | else if (power_gating == PIPE_GATING_CONTROL_ENABLE) | |||
220 | cntl = ASIC_PIPE_ENABLE; | |||
221 | else | |||
222 | cntl = ASIC_PIPE_DISABLE; | |||
223 | ||||
224 | if (controller_id == underlay_idx) | |||
225 | controller_id = CONTROLLER_ID_UNDERLAY0 - 1; | |||
226 | ||||
227 | if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ | |||
228 | ||||
229 | bp_result = dcb->funcs->enable_disp_power_gating( | |||
230 | dcb, controller_id + 1, cntl); | |||
231 | ||||
232 | /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 | |||
233 | * by default when command table is called | |||
234 | * | |||
235 | * Bios parser accepts controller_id = 6 as indicative of | |||
236 | * underlay pipe in dce110. But we do not support more | |||
237 | * than 3. | |||
238 | */ | |||
239 | if (controller_id < CONTROLLER_ID_MAX - 1) | |||
240 | dm_write_reg(ctx,dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__) | |||
241 | HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__) | |||
242 | 0)dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__); | |||
243 | } | |||
244 | ||||
245 | if (power_gating != PIPE_GATING_CONTROL_ENABLE) | |||
246 | dce110_init_pte(ctx); | |||
247 | ||||
248 | if (bp_result == BP_RESULT_OK) | |||
249 | return true1; | |||
250 | else | |||
251 | return false0; | |||
252 | } | |||
253 | ||||
254 | static void build_prescale_params(struct ipp_prescale_params *prescale_params, | |||
255 | const struct dc_plane_state *plane_state) | |||
256 | { | |||
257 | prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; | |||
258 | ||||
259 | switch (plane_state->format) { | |||
260 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |||
261 | prescale_params->scale = 0x2082; | |||
262 | break; | |||
263 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: | |||
264 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: | |||
265 | prescale_params->scale = 0x2020; | |||
266 | break; | |||
267 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: | |||
268 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: | |||
269 | prescale_params->scale = 0x2008; | |||
270 | break; | |||
271 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |||
272 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: | |||
273 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |||
274 | prescale_params->scale = 0x2000; | |||
275 | break; | |||
276 | default: | |||
277 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 277); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
278 | break; | |||
279 | } | |||
280 | } | |||
281 | ||||
282 | static bool_Bool | |||
283 | dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, | |||
284 | const struct dc_plane_state *plane_state) | |||
285 | { | |||
286 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; | |||
287 | const struct dc_transfer_func *tf = NULL((void *)0); | |||
288 | struct ipp_prescale_params prescale_params = { 0 }; | |||
289 | bool_Bool result = true1; | |||
290 | ||||
291 | if (ipp == NULL((void *)0)) | |||
292 | return false0; | |||
293 | ||||
294 | if (plane_state->in_transfer_func) | |||
295 | tf = plane_state->in_transfer_func; | |||
296 | ||||
297 | build_prescale_params(&prescale_params, plane_state); | |||
298 | ipp->funcs->ipp_program_prescale(ipp, &prescale_params); | |||
299 | ||||
300 | if (plane_state->gamma_correction && | |||
301 | !plane_state->gamma_correction->is_identity && | |||
302 | dce_use_lut(plane_state->format)) | |||
303 | ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); | |||
304 | ||||
305 | if (tf == NULL((void *)0)) { | |||
306 | /* Default case if no input transfer function specified */ | |||
307 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); | |||
308 | } else if (tf->type == TF_TYPE_PREDEFINED) { | |||
309 | switch (tf->tf) { | |||
310 | case TRANSFER_FUNCTION_SRGB: | |||
311 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); | |||
312 | break; | |||
313 | case TRANSFER_FUNCTION_BT709: | |||
314 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); | |||
315 | break; | |||
316 | case TRANSFER_FUNCTION_LINEAR: | |||
317 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); | |||
318 | break; | |||
319 | case TRANSFER_FUNCTION_PQ: | |||
320 | default: | |||
321 | result = false0; | |||
322 | break; | |||
323 | } | |||
324 | } else if (tf->type == TF_TYPE_BYPASS) { | |||
325 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); | |||
326 | } else { | |||
327 | /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ | |||
328 | result = false0; | |||
329 | } | |||
330 | ||||
331 | return result; | |||
332 | } | |||
333 | ||||
334 | static bool_Bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, | |||
335 | struct curve_points *arr_points, | |||
336 | uint32_t hw_points_num) | |||
337 | { | |||
338 | struct custom_float_format fmt; | |||
339 | ||||
340 | struct pwl_result_data *rgb = rgb_resulted; | |||
341 | ||||
342 | uint32_t i = 0; | |||
343 | ||||
344 | fmt.exponenta_bits = 6; | |||
345 | fmt.mantissa_bits = 12; | |||
346 | fmt.sign = true1; | |||
347 | ||||
348 | if (!convert_to_custom_float_format(arr_points[0].x, &fmt, | |||
349 | &arr_points[0].custom_float_x)) { | |||
350 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 350); do {} while (0); } while (0); | |||
351 | return false0; | |||
352 | } | |||
353 | ||||
354 | if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, | |||
355 | &arr_points[0].custom_float_offset)) { | |||
356 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 356); do {} while (0); } while (0); | |||
357 | return false0; | |||
358 | } | |||
359 | ||||
360 | if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, | |||
361 | &arr_points[0].custom_float_slope)) { | |||
362 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 362); do {} while (0); } while (0); | |||
363 | return false0; | |||
364 | } | |||
365 | ||||
366 | fmt.mantissa_bits = 10; | |||
367 | fmt.sign = false0; | |||
368 | ||||
369 | if (!convert_to_custom_float_format(arr_points[1].x, &fmt, | |||
370 | &arr_points[1].custom_float_x)) { | |||
371 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 371); do {} while (0); } while (0); | |||
372 | return false0; | |||
373 | } | |||
374 | ||||
375 | if (!convert_to_custom_float_format(arr_points[1].y, &fmt, | |||
376 | &arr_points[1].custom_float_y)) { | |||
377 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 377); do {} while (0); } while (0); | |||
378 | return false0; | |||
379 | } | |||
380 | ||||
381 | if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, | |||
382 | &arr_points[1].custom_float_slope)) { | |||
383 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 383); do {} while (0); } while (0); | |||
384 | return false0; | |||
385 | } | |||
386 | ||||
387 | fmt.mantissa_bits = 12; | |||
388 | fmt.sign = true1; | |||
389 | ||||
390 | while (i != hw_points_num) { | |||
391 | if (!convert_to_custom_float_format(rgb->red, &fmt, | |||
392 | &rgb->red_reg)) { | |||
393 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 393); do {} while (0); } while (0); | |||
394 | return false0; | |||
395 | } | |||
396 | ||||
397 | if (!convert_to_custom_float_format(rgb->green, &fmt, | |||
398 | &rgb->green_reg)) { | |||
399 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 399); do {} while (0); } while (0); | |||
400 | return false0; | |||
401 | } | |||
402 | ||||
403 | if (!convert_to_custom_float_format(rgb->blue, &fmt, | |||
404 | &rgb->blue_reg)) { | |||
405 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 405); do {} while (0); } while (0); | |||
406 | return false0; | |||
407 | } | |||
408 | ||||
409 | if (!convert_to_custom_float_format(rgb->delta_red, &fmt, | |||
410 | &rgb->delta_red_reg)) { | |||
411 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 411); do {} while (0); } while (0); | |||
412 | return false0; | |||
413 | } | |||
414 | ||||
415 | if (!convert_to_custom_float_format(rgb->delta_green, &fmt, | |||
416 | &rgb->delta_green_reg)) { | |||
417 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 417); do {} while (0); } while (0); | |||
418 | return false0; | |||
419 | } | |||
420 | ||||
421 | if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, | |||
422 | &rgb->delta_blue_reg)) { | |||
423 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 423); do {} while (0); } while (0); | |||
424 | return false0; | |||
425 | } | |||
426 | ||||
427 | ++rgb; | |||
428 | ++i; | |||
429 | } | |||
430 | ||||
431 | return true1; | |||
432 | } | |||
433 | ||||
434 | #define MAX_LOW_POINT25 25 | |||
435 | #define NUMBER_REGIONS16 16 | |||
436 | #define NUMBER_SW_SEGMENTS16 16 | |||
437 | ||||
438 | static bool_Bool | |||
439 | dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, | |||
440 | struct pwl_params *regamma_params) | |||
441 | { | |||
442 | struct curve_points *arr_points; | |||
443 | struct pwl_result_data *rgb_resulted; | |||
444 | struct pwl_result_data *rgb; | |||
445 | struct pwl_result_data *rgb_plus_1; | |||
446 | struct fixed31_32 y_r; | |||
447 | struct fixed31_32 y_g; | |||
448 | struct fixed31_32 y_b; | |||
449 | struct fixed31_32 y1_min; | |||
450 | struct fixed31_32 y3_max; | |||
451 | ||||
452 | int32_t region_start, region_end; | |||
453 | uint32_t i, j, k, seg_distr[NUMBER_REGIONS16], increment, start_index, hw_points; | |||
454 | ||||
455 | if (output_tf == NULL((void *)0) || regamma_params == NULL((void *)0) || output_tf->type == TF_TYPE_BYPASS) | |||
456 | return false0; | |||
457 | ||||
458 | arr_points = regamma_params->arr_points; | |||
459 | rgb_resulted = regamma_params->rgb_resulted; | |||
460 | hw_points = 0; | |||
461 | ||||
462 | memset(regamma_params, 0, sizeof(struct pwl_params))__builtin_memset((regamma_params), (0), (sizeof(struct pwl_params ))); | |||
463 | ||||
464 | if (output_tf->tf == TRANSFER_FUNCTION_PQ) { | |||
465 | /* 16 segments | |||
466 | * segments are from 2^-11 to 2^5 | |||
467 | */ | |||
468 | region_start = -11; | |||
469 | region_end = region_start + NUMBER_REGIONS16; | |||
470 | ||||
471 | for (i = 0; i < NUMBER_REGIONS16; i++) | |||
472 | seg_distr[i] = 4; | |||
473 | ||||
474 | } else { | |||
475 | /* 10 segments | |||
476 | * segment is from 2^-10 to 2^1 | |||
477 | * We include an extra segment for range [2^0, 2^1). This is to | |||
478 | * ensure that colors with normalized values of 1 don't miss the | |||
479 | * LUT. | |||
480 | */ | |||
481 | region_start = -10; | |||
482 | region_end = 1; | |||
483 | ||||
484 | seg_distr[0] = 4; | |||
485 | seg_distr[1] = 4; | |||
486 | seg_distr[2] = 4; | |||
487 | seg_distr[3] = 4; | |||
488 | seg_distr[4] = 4; | |||
489 | seg_distr[5] = 4; | |||
490 | seg_distr[6] = 4; | |||
491 | seg_distr[7] = 4; | |||
492 | seg_distr[8] = 4; | |||
493 | seg_distr[9] = 4; | |||
494 | seg_distr[10] = 0; | |||
495 | seg_distr[11] = -1; | |||
496 | seg_distr[12] = -1; | |||
497 | seg_distr[13] = -1; | |||
498 | seg_distr[14] = -1; | |||
499 | seg_distr[15] = -1; | |||
500 | } | |||
501 | ||||
502 | for (k = 0; k < 16; k++) { | |||
503 | if (seg_distr[k] != -1) | |||
504 | hw_points += (1 << seg_distr[k]); | |||
505 | } | |||
506 | ||||
507 | j = 0; | |||
508 | for (k = 0; k < (region_end - region_start); k++) { | |||
509 | increment = NUMBER_SW_SEGMENTS16 / (1 << seg_distr[k]); | |||
510 | start_index = (region_start + k + MAX_LOW_POINT25) * | |||
511 | NUMBER_SW_SEGMENTS16; | |||
512 | for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS16; | |||
513 | i += increment) { | |||
514 | if (j == hw_points - 1) | |||
515 | break; | |||
516 | rgb_resulted[j].red = output_tf->tf_pts.red[i]; | |||
517 | rgb_resulted[j].green = output_tf->tf_pts.green[i]; | |||
518 | rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; | |||
519 | j++; | |||
520 | } | |||
521 | } | |||
522 | ||||
523 | /* last point */ | |||
524 | start_index = (region_end + MAX_LOW_POINT25) * NUMBER_SW_SEGMENTS16; | |||
525 | rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; | |||
526 | rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; | |||
527 | rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; | |||
528 | ||||
529 | arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), | |||
530 | dc_fixpt_from_int(region_start)); | |||
531 | arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), | |||
532 | dc_fixpt_from_int(region_end)); | |||
533 | ||||
534 | y_r = rgb_resulted[0].red; | |||
535 | y_g = rgb_resulted[0].green; | |||
536 | y_b = rgb_resulted[0].blue; | |||
537 | ||||
538 | y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); | |||
539 | ||||
540 | arr_points[0].y = y1_min; | |||
541 | arr_points[0].slope = dc_fixpt_div(arr_points[0].y, | |||
542 | arr_points[0].x); | |||
543 | ||||
544 | y_r = rgb_resulted[hw_points - 1].red; | |||
545 | y_g = rgb_resulted[hw_points - 1].green; | |||
546 | y_b = rgb_resulted[hw_points - 1].blue; | |||
547 | ||||
548 | /* see comment above, m_arrPoints[1].y should be the Y value for the | |||
549 | * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) | |||
550 | */ | |||
551 | y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); | |||
552 | ||||
553 | arr_points[1].y = y3_max; | |||
554 | ||||
555 | arr_points[1].slope = dc_fixpt_zero; | |||
556 | ||||
557 | if (output_tf->tf == TRANSFER_FUNCTION_PQ) { | |||
558 | /* for PQ, we want to have a straight line from last HW X point, | |||
559 | * and the slope to be such that we hit 1.0 at 10000 nits. | |||
560 | */ | |||
561 | const struct fixed31_32 end_value = dc_fixpt_from_int(125); | |||
562 | ||||
563 | arr_points[1].slope = dc_fixpt_div( | |||
564 | dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), | |||
565 | dc_fixpt_sub(end_value, arr_points[1].x)); | |||
566 | } | |||
567 | ||||
568 | regamma_params->hw_points_num = hw_points; | |||
569 | ||||
570 | k = 0; | |||
571 | for (i = 1; i < 16; i++) { | |||
572 | if (seg_distr[k] != -1) { | |||
573 | regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; | |||
574 | regamma_params->arr_curve_points[i].offset = | |||
575 | regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); | |||
576 | } | |||
577 | k++; | |||
578 | } | |||
579 | ||||
580 | if (seg_distr[k] != -1) | |||
581 | regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; | |||
582 | ||||
583 | rgb = rgb_resulted; | |||
584 | rgb_plus_1 = rgb_resulted + 1; | |||
585 | ||||
586 | i = 1; | |||
587 | ||||
588 | while (i != hw_points + 1) { | |||
589 | if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) | |||
590 | rgb_plus_1->red = rgb->red; | |||
591 | if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) | |||
592 | rgb_plus_1->green = rgb->green; | |||
593 | if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) | |||
594 | rgb_plus_1->blue = rgb->blue; | |||
595 | ||||
596 | rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); | |||
597 | rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); | |||
598 | rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); | |||
599 | ||||
600 | ++rgb_plus_1; | |||
601 | ++rgb; | |||
602 | ++i; | |||
603 | } | |||
604 | ||||
605 | convert_to_custom_float(rgb_resulted, arr_points, hw_points); | |||
606 | ||||
607 | return true1; | |||
608 | } | |||
609 | ||||
610 | static bool_Bool | |||
611 | dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, | |||
612 | const struct dc_stream_state *stream) | |||
613 | { | |||
614 | struct transform *xfm = pipe_ctx->plane_res.xfm; | |||
615 | ||||
616 | xfm->funcs->opp_power_on_regamma_lut(xfm, true1); | |||
617 | xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM256; | |||
618 | ||||
619 | if (stream->out_transfer_func && | |||
620 | stream->out_transfer_func->type == TF_TYPE_PREDEFINED && | |||
621 | stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { | |||
622 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); | |||
623 | } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, | |||
624 | &xfm->regamma_params)) { | |||
625 | xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); | |||
626 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); | |||
627 | } else { | |||
628 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); | |||
629 | } | |||
630 | ||||
631 | xfm->funcs->opp_power_on_regamma_lut(xfm, false0); | |||
632 | ||||
633 | return true1; | |||
634 | } | |||
635 | ||||
636 | void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) | |||
637 | { | |||
638 | bool_Bool is_hdmi_tmds; | |||
639 | bool_Bool is_dp; | |||
640 | ||||
641 | ASSERT(pipe_ctx->stream)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> stream)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_ctx->stream)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 641); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
642 | ||||
643 | if (pipe_ctx->stream_res.stream_enc == NULL((void *)0)) | |||
644 | return; /* this is not root pipe */ | |||
645 | ||||
646 | is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); | |||
647 | is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); | |||
648 | ||||
649 | if (!is_hdmi_tmds && !is_dp) | |||
650 | return; | |||
651 | ||||
652 | if (is_hdmi_tmds) | |||
653 | pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( | |||
654 | pipe_ctx->stream_res.stream_enc, | |||
655 | &pipe_ctx->stream_res.encoder_info_frame); | |||
656 | else | |||
657 | pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( | |||
658 | pipe_ctx->stream_res.stream_enc, | |||
659 | &pipe_ctx->stream_res.encoder_info_frame); | |||
660 | } | |||
661 | ||||
662 | void dce110_enable_stream(struct pipe_ctx *pipe_ctx) | |||
663 | { | |||
664 | enum dc_lane_count lane_count = | |||
665 | pipe_ctx->stream->link->cur_link_settings.lane_count; | |||
666 | struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; | |||
667 | struct dc_link *link = pipe_ctx->stream->link; | |||
668 | const struct dc *dc = link->dc; | |||
669 | const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); | |||
670 | uint32_t active_total_with_borders; | |||
671 | uint32_t early_control = 0; | |||
672 | struct timing_generator *tg = pipe_ctx->stream_res.tg; | |||
673 | ||||
674 | link_hwss->setup_stream_encoder(pipe_ctx); | |||
675 | ||||
676 | dc->hwss.update_info_frame(pipe_ctx); | |||
677 | ||||
678 | /* enable early control to avoid corruption on DP monitor*/ | |||
679 | active_total_with_borders = | |||
680 | timing->h_addressable | |||
681 | + timing->h_border_left | |||
682 | + timing->h_border_right; | |||
683 | ||||
684 | if (lane_count != 0) | |||
685 | early_control = active_total_with_borders % lane_count; | |||
686 | ||||
687 | if (early_control == 0) | |||
688 | early_control = lane_count; | |||
689 | ||||
690 | tg->funcs->set_early_control(tg, early_control); | |||
691 | ||||
692 | /* enable audio only within mode set */ | |||
693 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { | |||
694 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
695 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); | |||
696 | } | |||
697 | ||||
698 | ||||
699 | ||||
700 | ||||
701 | } | |||
702 | ||||
703 | static enum bp_result link_transmitter_control( | |||
704 | struct dc_bios *bios, | |||
705 | struct bp_transmitter_control *cntl) | |||
706 | { | |||
707 | enum bp_result result; | |||
708 | ||||
709 | result = bios->funcs->transmitter_control(bios, cntl); | |||
710 | ||||
711 | return result; | |||
712 | } | |||
713 | ||||
714 | /* | |||
715 | * @brief | |||
716 | * eDP only. | |||
717 | */ | |||
718 | void dce110_edp_wait_for_hpd_ready( | |||
719 | struct dc_link *link, | |||
720 | bool_Bool power_up) | |||
721 | { | |||
722 | struct dc_context *ctx = link->ctx; | |||
723 | struct graphics_object_id connector = link->link_enc->connector; | |||
724 | struct gpio *hpd; | |||
725 | bool_Bool edp_hpd_high = false0; | |||
726 | uint32_t time_elapsed = 0; | |||
727 | uint32_t timeout = power_up ? | |||
728 | PANEL_POWER_UP_TIMEOUT300 : PANEL_POWER_DOWN_TIMEOUT500; | |||
729 | ||||
730 | if (dal_graphics_object_id_get_connector_id(connector) | |||
731 | != CONNECTOR_ID_EDP) { | |||
732 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 732); do {} while (0); } while (0); | |||
733 | return; | |||
734 | } | |||
735 | ||||
736 | if (!power_up) | |||
737 | /* | |||
738 | * From KV, we will not HPD low after turning off VCC - | |||
739 | * instead, we will check the SW timer in power_up(). | |||
740 | */ | |||
741 | return; | |||
742 | ||||
743 | /* | |||
744 | * When we power on/off the eDP panel, | |||
745 | * we need to wait until SENSE bit is high/low. | |||
746 | */ | |||
747 | ||||
748 | /* obtain HPD */ | |||
749 | /* TODO what to do with this? */ | |||
750 | hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); | |||
751 | ||||
752 | if (!hpd) { | |||
753 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 753); do {} while (0); } while (0); | |||
754 | return; | |||
755 | } | |||
756 | ||||
757 | if (link != NULL((void *)0)) { | |||
758 | if (link->panel_config.pps.extra_t3_ms > 0) { | |||
759 | int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms; | |||
760 | ||||
761 | drm_msleep(extra_t3_in_ms)mdelay(extra_t3_in_ms); | |||
762 | } | |||
763 | } | |||
764 | ||||
765 | dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); | |||
766 | ||||
767 | /* wait until timeout or panel detected */ | |||
768 | ||||
769 | do { | |||
770 | uint32_t detected = 0; | |||
771 | ||||
772 | dal_gpio_get_value(hpd, &detected); | |||
773 | ||||
774 | if (!(detected ^ power_up)) { | |||
775 | edp_hpd_high = true1; | |||
776 | break; | |||
777 | } | |||
778 | ||||
779 | drm_msleep(HPD_CHECK_INTERVAL)mdelay(10); | |||
780 | ||||
781 | time_elapsed += HPD_CHECK_INTERVAL10; | |||
782 | } while (time_elapsed < timeout); | |||
783 | ||||
784 | dal_gpio_close(hpd); | |||
785 | ||||
786 | dal_gpio_destroy_irq(&hpd); | |||
787 | ||||
788 | if (false0 == edp_hpd_high) { | |||
789 | DC_LOG_WARNING(printk("\0014" "[" "drm" "] " "%s: wait timed out!\n", __func__ ) | |||
790 | "%s: wait timed out!\n", __func__)printk("\0014" "[" "drm" "] " "%s: wait timed out!\n", __func__ ); | |||
791 | } | |||
792 | } | |||
793 | ||||
794 | void dce110_edp_power_control( | |||
795 | struct dc_link *link, | |||
796 | bool_Bool power_up) | |||
797 | { | |||
798 | struct dc_context *ctx = link->ctx; | |||
799 | struct bp_transmitter_control cntl = { 0 }; | |||
800 | enum bp_result bp_result; | |||
801 | uint8_t panel_instance; | |||
802 | ||||
803 | ||||
804 | if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) | |||
805 | != CONNECTOR_ID_EDP) { | |||
806 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 806); do {} while (0); } while (0); | |||
807 | return; | |||
808 | } | |||
809 | ||||
810 | if (!link->panel_cntl) | |||
811 | return; | |||
812 | if (power_up != | |||
813 | link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { | |||
814 | ||||
815 | unsigned long long current_ts = dm_get_timestamp(ctx); | |||
816 | unsigned long long time_since_edp_poweroff_ms = | |||
817 | div64_u64(dm_get_elapse_time_in_ns( | |||
818 | ctx, | |||
819 | current_ts, | |||
820 | dp_trace_get_edp_poweroff_timestamp(link)), 1000000); | |||
821 | unsigned long long time_since_edp_poweron_ms = | |||
822 | div64_u64(dm_get_elapse_time_in_ns( | |||
823 | ctx, | |||
824 | current_ts, | |||
825 | dp_trace_get_edp_poweron_timestamp(link)), 1000000); | |||
826 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
827 | "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
828 | __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
829 | power_up,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
830 | current_ts,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
831 | dp_trace_get_edp_poweroff_timestamp(link),___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
832 | dp_trace_get_edp_poweron_timestamp(link),___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
833 | time_since_edp_poweroff_ms,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms) | |||
834 | time_since_edp_poweron_ms)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, dp_trace_get_edp_poweroff_timestamp (link), dp_trace_get_edp_poweron_timestamp(link), time_since_edp_poweroff_ms , time_since_edp_poweron_ms); | |||
835 | ||||
836 | /* Send VBIOS command to prompt eDP panel power */ | |||
837 | if (power_up) { | |||
838 | /* edp requires a min of 500ms from LCDVDD off to on */ | |||
839 | unsigned long long remaining_min_edp_poweroff_time_ms = 500; | |||
840 | ||||
841 | /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ | |||
842 | if (link->local_sink != NULL((void *)0)) | |||
843 | remaining_min_edp_poweroff_time_ms += | |||
844 | link->panel_config.pps.extra_t12_ms; | |||
845 | ||||
846 | /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ | |||
847 | if (dp_trace_get_edp_poweroff_timestamp(link) != 0) { | |||
848 | if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) | |||
849 | remaining_min_edp_poweroff_time_ms = | |||
850 | remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; | |||
851 | else | |||
852 | remaining_min_edp_poweroff_time_ms = 0; | |||
853 | } | |||
854 | ||||
855 | if (remaining_min_edp_poweroff_time_ms) { | |||
856 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
857 | "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
858 | __func__, remaining_min_edp_poweroff_time_ms)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms); | |||
859 | drm_msleep(remaining_min_edp_poweroff_time_ms)mdelay(remaining_min_edp_poweroff_time_ms); | |||
860 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
861 | "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
862 | __func__, remaining_min_edp_poweroff_time_ms)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms); | |||
863 | dm_output_to_console("%s: wait %lld ms to power on eDP.\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: wait %lld ms to power on eDP.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
864 | __func__, remaining_min_edp_poweroff_time_ms)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: wait %lld ms to power on eDP.\n" , __func__, remaining_min_edp_poweroff_time_ms); | |||
865 | } else { | |||
866 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
867 | "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms) | |||
868 | __func__, remaining_min_edp_poweroff_time_ms)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms); | |||
869 | } | |||
870 | } | |||
871 | ||||
872 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) | |||
873 | "%s: BEGIN: Panel Power action: %s\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) | |||
874 | __func__, (power_up ? "On":"Off"))___drm_dbg(((void *)0), DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")); | |||
875 | ||||
876 | cntl.action = power_up ? | |||
877 | TRANSMITTER_CONTROL_POWER_ON : | |||
878 | TRANSMITTER_CONTROL_POWER_OFF; | |||
879 | cntl.transmitter = link->link_enc->transmitter; | |||
880 | cntl.connector_obj_id = link->link_enc->connector; | |||
881 | cntl.coherent = false0; | |||
882 | cntl.lanes_number = LANE_COUNT_FOUR; | |||
883 | cntl.hpd_sel = link->link_enc->hpd_source; | |||
884 | panel_instance = link->panel_cntl->inst; | |||
885 | ||||
886 | if (ctx->dc->ctx->dmub_srv && | |||
887 | ctx->dc->debug.dmub_command_table) { | |||
888 | if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) | |||
889 | bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, | |||
890 | LVTMA_CONTROL_POWER_ON, | |||
891 | panel_instance); | |||
892 | else | |||
893 | bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, | |||
894 | LVTMA_CONTROL_POWER_OFF, | |||
895 | panel_instance); | |||
896 | } | |||
897 | ||||
898 | bp_result = link_transmitter_control(ctx->dc_bios, &cntl); | |||
899 | ||||
900 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) | |||
901 | "%s: END: Panel Power action: %s bp_result=%u\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) | |||
902 | __func__, (power_up ? "On":"Off"),___drm_dbg(((void *)0), DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) | |||
903 | bp_result)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result); | |||
904 | ||||
905 | dp_trace_set_edp_power_timestamp(link, power_up); | |||
906 | ||||
907 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, dp_trace_get_edp_poweroff_timestamp(link), dp_trace_get_edp_poweron_timestamp (link)) | |||
908 | "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, dp_trace_get_edp_poweroff_timestamp(link), dp_trace_get_edp_poweron_timestamp (link)) | |||
909 | __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, dp_trace_get_edp_poweroff_timestamp(link), dp_trace_get_edp_poweron_timestamp (link)) | |||
910 | dp_trace_get_edp_poweroff_timestamp(link),___drm_dbg(((void *)0), DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, dp_trace_get_edp_poweroff_timestamp(link), dp_trace_get_edp_poweron_timestamp (link)) | |||
911 | dp_trace_get_edp_poweron_timestamp(link))___drm_dbg(((void *)0), DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, dp_trace_get_edp_poweroff_timestamp(link), dp_trace_get_edp_poweron_timestamp (link)); | |||
912 | ||||
913 | if (bp_result != BP_RESULT_OK) | |||
914 | DC_LOG_ERROR(__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ) | |||
915 | "%s: Panel Power bp_result: %d\n",__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ) | |||
916 | __func__, bp_result)__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ); | |||
917 | } else { | |||
918 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) | |||
919 | "%s: Skipping Panel Power action: %s\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) | |||
920 | __func__, (power_up ? "On":"Off"))___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")); | |||
921 | } | |||
922 | } | |||
923 | ||||
924 | void dce110_edp_wait_for_T12( | |||
925 | struct dc_link *link) | |||
926 | { | |||
927 | struct dc_context *ctx = link->ctx; | |||
928 | ||||
929 | if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) | |||
930 | != CONNECTOR_ID_EDP) { | |||
931 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 931); do {} while (0); } while (0); | |||
932 | return; | |||
933 | } | |||
934 | ||||
935 | if (!link->panel_cntl) | |||
936 | return; | |||
937 | ||||
938 | if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && | |||
939 | dp_trace_get_edp_poweroff_timestamp(link) != 0) { | |||
940 | unsigned int t12_duration = 500; // Default T12 as per spec | |||
941 | unsigned long long current_ts = dm_get_timestamp(ctx); | |||
942 | unsigned long long time_since_edp_poweroff_ms = | |||
943 | div64_u64(dm_get_elapse_time_in_ns( | |||
944 | ctx, | |||
945 | current_ts, | |||
946 | dp_trace_get_edp_poweroff_timestamp(link)), 1000000); | |||
947 | ||||
948 | t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 | |||
949 | ||||
950 | if (time_since_edp_poweroff_ms < t12_duration) | |||
951 | drm_msleep(t12_duration - time_since_edp_poweroff_ms)mdelay(t12_duration - time_since_edp_poweroff_ms); | |||
952 | } | |||
953 | } | |||
954 | ||||
955 | /*todo: cloned in stream enc, fix*/ | |||
956 | /* | |||
957 | * @brief | |||
958 | * eDP only. Control the backlight of the eDP panel | |||
959 | */ | |||
960 | void dce110_edp_backlight_control( | |||
961 | struct dc_link *link, | |||
962 | bool_Bool enable) | |||
963 | { | |||
964 | struct dc_context *ctx = link->ctx; | |||
965 | struct bp_transmitter_control cntl = { 0 }; | |||
966 | uint8_t panel_instance; | |||
967 | unsigned int pre_T11_delay = OLED_PRE_T11_DELAY150; | |||
968 | unsigned int post_T7_delay = OLED_POST_T7_DELAY100; | |||
969 | ||||
970 | if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) | |||
| ||||
971 | != CONNECTOR_ID_EDP) { | |||
972 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 972); do {} while (0); } while (0); | |||
973 | return; | |||
974 | } | |||
975 | ||||
976 | if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled || | |||
977 | link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || | |||
978 | link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { | |||
979 | bool_Bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); | |||
980 | ||||
981 | if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { | |||
982 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: panel already powered up/off. Do nothing.\n" , __func__) | |||
983 | "%s: panel already powered up/off. Do nothing.\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: panel already powered up/off. Do nothing.\n" , __func__) | |||
984 | __func__)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: panel already powered up/off. Do nothing.\n" , __func__); | |||
985 | return; | |||
986 | } | |||
987 | } | |||
988 | ||||
989 | /* Send VBIOS command to control eDP panel backlight */ | |||
990 | ||||
991 | DC_LOG_HW_RESUME_S3(___drm_dbg(((void *)0), DRM_UT_KMS, "%s: backlight action: %s\n" , __func__, (enable ? "On":"Off")) | |||
992 | "%s: backlight action: %s\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: backlight action: %s\n" , __func__, (enable ? "On":"Off")) | |||
993 | __func__, (enable ? "On":"Off"))___drm_dbg(((void *)0), DRM_UT_KMS, "%s: backlight action: %s\n" , __func__, (enable ? "On":"Off")); | |||
994 | ||||
995 | cntl.action = enable
| |||
996 | TRANSMITTER_CONTROL_BACKLIGHT_ON : | |||
997 | TRANSMITTER_CONTROL_BACKLIGHT_OFF; | |||
998 | ||||
999 | /*cntl.engine_id = ctx->engine;*/ | |||
1000 | cntl.transmitter = link->link_enc->transmitter; | |||
1001 | cntl.connector_obj_id = link->link_enc->connector; | |||
1002 | /*todo: unhardcode*/ | |||
1003 | cntl.lanes_number = LANE_COUNT_FOUR; | |||
1004 | cntl.hpd_sel = link->link_enc->hpd_source; | |||
1005 | cntl.signal = SIGNAL_TYPE_EDP; | |||
1006 | ||||
1007 | /* For eDP, the following delays might need to be considered | |||
1008 | * after link training completed: | |||
1009 | * idle period - min. accounts for required BS-Idle pattern, | |||
1010 | * max. allows for source frame synchronization); | |||
1011 | * 50 msec max. delay from valid video data from source | |||
1012 | * to video on dislpay or backlight enable. | |||
1013 | * | |||
1014 | * Disable the delay for now. | |||
1015 | * Enable it in the future if necessary. | |||
1016 | */ | |||
1017 | /* dc_service_sleep_in_milliseconds(50); */ | |||
1018 | /*edp 1.2*/ | |||
1019 | panel_instance = link->panel_cntl->inst; | |||
| ||||
1020 | ||||
1021 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { | |||
1022 | if (!link->dc->config.edp_no_power_sequencing) | |||
1023 | /* | |||
1024 | * Sometimes, DP receiver chip power-controlled externally by an | |||
1025 | * Embedded Controller could be treated and used as eDP, | |||
1026 | * if it drives mobile display. In this case, | |||
1027 | * we shouldn't be doing power-sequencing, hence we can skip | |||
1028 | * waiting for T7-ready. | |||
1029 | */ | |||
1030 | edp_receiver_ready_T7(link); | |||
1031 | else | |||
1032 | DC_LOG_DC("edp_receiver_ready_T7 skipped\n")___drm_dbg(((void *)0), DRM_UT_KMS, "edp_receiver_ready_T7 skipped\n" ); | |||
1033 | } | |||
1034 | ||||
1035 | if (ctx->dc->ctx->dmub_srv && | |||
1036 | ctx->dc->debug.dmub_command_table) { | |||
1037 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) | |||
1038 | ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, | |||
1039 | LVTMA_CONTROL_LCD_BLON, | |||
1040 | panel_instance); | |||
1041 | else | |||
1042 | ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, | |||
1043 | LVTMA_CONTROL_LCD_BLOFF, | |||
1044 | panel_instance); | |||
1045 | } | |||
1046 | ||||
1047 | link_transmitter_control(ctx->dc_bios, &cntl); | |||
1048 | ||||
1049 | if (enable && link->dpcd_sink_ext_caps.bits.oled) { | |||
1050 | post_T7_delay += link->panel_config.pps.extra_post_t7_ms; | |||
1051 | drm_msleep(post_T7_delay)mdelay(post_T7_delay); | |||
1052 | } | |||
1053 | ||||
1054 | if (link->dpcd_sink_ext_caps.bits.oled || | |||
1055 | link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || | |||
1056 | link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) | |||
1057 | dc_link_backlight_enable_aux(link, enable); | |||
1058 | ||||
1059 | /*edp 1.2*/ | |||
1060 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { | |||
1061 | if (!link->dc->config.edp_no_power_sequencing) | |||
1062 | /* | |||
1063 | * Sometimes, DP receiver chip power-controlled externally by an | |||
1064 | * Embedded Controller could be treated and used as eDP, | |||
1065 | * if it drives mobile display. In this case, | |||
1066 | * we shouldn't be doing power-sequencing, hence we can skip | |||
1067 | * waiting for T9-ready. | |||
1068 | */ | |||
1069 | edp_add_delay_for_T9(link); | |||
1070 | else | |||
1071 | DC_LOG_DC("edp_receiver_ready_T9 skipped\n")___drm_dbg(((void *)0), DRM_UT_KMS, "edp_receiver_ready_T9 skipped\n" ); | |||
1072 | } | |||
1073 | ||||
1074 | if (!enable && link->dpcd_sink_ext_caps.bits.oled) { | |||
1075 | pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms; | |||
1076 | drm_msleep(pre_T11_delay)mdelay(pre_T11_delay); | |||
1077 | } | |||
1078 | } | |||
1079 | ||||
1080 | void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) | |||
1081 | { | |||
1082 | /* notify audio driver for audio modes of monitor */ | |||
1083 | struct dc *dc; | |||
1084 | struct clk_mgr *clk_mgr; | |||
1085 | unsigned int i, num_audio = 1; | |||
1086 | ||||
1087 | if (!pipe_ctx->stream) | |||
1088 | return; | |||
1089 | ||||
1090 | dc = pipe_ctx->stream->ctx->dc; | |||
1091 | clk_mgr = dc->clk_mgr; | |||
1092 | ||||
1093 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true1) | |||
1094 | return; | |||
1095 | ||||
1096 | if (pipe_ctx->stream_res.audio) { | |||
1097 | for (i = 0; i < MAX_PIPES6; i++) { | |||
1098 | /*current_state not updated yet*/ | |||
1099 | if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL((void *)0)) | |||
1100 | num_audio++; | |||
1101 | } | |||
1102 | ||||
1103 | pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); | |||
1104 | ||||
1105 | if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) | |||
1106 | /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ | |||
1107 | clk_mgr->funcs->enable_pme_wa(clk_mgr); | |||
1108 | /* un-mute audio */ | |||
1109 | /* TODO: audio should be per stream rather than per link */ | |||
1110 | if (is_dp_128b_132b_signal(pipe_ctx)) | |||
1111 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( | |||
1112 | pipe_ctx->stream_res.hpo_dp_stream_enc, false0); | |||
1113 | else | |||
1114 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( | |||
1115 | pipe_ctx->stream_res.stream_enc, false0); | |||
1116 | if (pipe_ctx->stream_res.audio) | |||
1117 | pipe_ctx->stream_res.audio->enabled = true1; | |||
1118 | } | |||
1119 | ||||
1120 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1121 | dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM); | |||
1122 | } | |||
1123 | ||||
1124 | void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) | |||
1125 | { | |||
1126 | struct dc *dc; | |||
1127 | struct clk_mgr *clk_mgr; | |||
1128 | ||||
1129 | if (!pipe_ctx || !pipe_ctx->stream) | |||
1130 | return; | |||
1131 | ||||
1132 | dc = pipe_ctx->stream->ctx->dc; | |||
1133 | clk_mgr = dc->clk_mgr; | |||
1134 | ||||
1135 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false0) | |||
1136 | return; | |||
1137 | ||||
1138 | if (is_dp_128b_132b_signal(pipe_ctx)) | |||
1139 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( | |||
1140 | pipe_ctx->stream_res.hpo_dp_stream_enc, true1); | |||
1141 | else | |||
1142 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( | |||
1143 | pipe_ctx->stream_res.stream_enc, true1); | |||
1144 | if (pipe_ctx->stream_res.audio) { | |||
1145 | pipe_ctx->stream_res.audio->enabled = false0; | |||
1146 | ||||
1147 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1148 | if (is_dp_128b_132b_signal(pipe_ctx)) | |||
1149 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( | |||
1150 | pipe_ctx->stream_res.hpo_dp_stream_enc); | |||
1151 | else | |||
1152 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( | |||
1153 | pipe_ctx->stream_res.stream_enc); | |||
1154 | else | |||
1155 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( | |||
1156 | pipe_ctx->stream_res.stream_enc); | |||
1157 | ||||
1158 | if (clk_mgr->funcs->enable_pme_wa) | |||
1159 | /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ | |||
1160 | clk_mgr->funcs->enable_pme_wa(clk_mgr); | |||
1161 | ||||
1162 | /* TODO: notify audio driver for if audio modes list changed | |||
1163 | * add audio mode list change flag */ | |||
1164 | /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, | |||
1165 | * stream->stream_engine_id); | |||
1166 | */ | |||
1167 | } | |||
1168 | ||||
1169 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1170 | dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM); | |||
1171 | } | |||
1172 | ||||
1173 | void dce110_disable_stream(struct pipe_ctx *pipe_ctx) | |||
1174 | { | |||
1175 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
1176 | struct dc_link *link = stream->link; | |||
1177 | struct dc *dc = pipe_ctx->stream->ctx->dc; | |||
1178 | const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); | |||
1179 | ||||
1180 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { | |||
1181 | pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( | |||
1182 | pipe_ctx->stream_res.stream_enc); | |||
1183 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( | |||
1184 | pipe_ctx->stream_res.stream_enc); | |||
1185 | } | |||
1186 | ||||
1187 | if (is_dp_128b_132b_signal(pipe_ctx)) { | |||
1188 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( | |||
1189 | pipe_ctx->stream_res.hpo_dp_stream_enc); | |||
1190 | } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1191 | pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( | |||
1192 | pipe_ctx->stream_res.stream_enc); | |||
1193 | ||||
1194 | dc->hwss.disable_audio_stream(pipe_ctx); | |||
1195 | ||||
1196 | link_hwss->reset_stream_encoder(pipe_ctx); | |||
1197 | ||||
1198 | if (is_dp_128b_132b_signal(pipe_ctx)) { | |||
1199 | /* TODO: This looks like a bug to me as we are disabling HPO IO when | |||
1200 | * we are just disabling a single HPO stream. Shouldn't we disable HPO | |||
1201 | * HW control only when HPOs for all streams are disabled? | |||
1202 | */ | |||
1203 | if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) | |||
1204 | pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( | |||
1205 | pipe_ctx->stream->ctx->dc->hwseq, false0); | |||
1206 | } | |||
1207 | } | |||
1208 | ||||
1209 | void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, | |||
1210 | struct dc_link_settings *link_settings) | |||
1211 | { | |||
1212 | struct encoder_unblank_param params = { { 0 } }; | |||
1213 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
1214 | struct dc_link *link = stream->link; | |||
1215 | struct dce_hwseq *hws = link->dc->hwseq; | |||
1216 | ||||
1217 | /* only 3 items below are used by unblank */ | |||
1218 | params.timing = pipe_ctx->stream->timing; | |||
1219 | params.link_settings.link_rate = link_settings->link_rate; | |||
1220 | ||||
1221 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1222 | pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); | |||
1223 | ||||
1224 | if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { | |||
1225 | hws->funcs.edp_backlight_control(link, true1); | |||
1226 | } | |||
1227 | } | |||
1228 | ||||
1229 | void dce110_blank_stream(struct pipe_ctx *pipe_ctx) | |||
1230 | { | |||
1231 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
1232 | struct dc_link *link = stream->link; | |||
1233 | struct dce_hwseq *hws = link->dc->hwseq; | |||
1234 | ||||
1235 | if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { | |||
1236 | hws->funcs.edp_backlight_control(link, false0); | |||
1237 | link->dc->hwss.set_abm_immediate_disable(pipe_ctx); | |||
1238 | } | |||
1239 | ||||
1240 | if (is_dp_128b_132b_signal(pipe_ctx)) { | |||
1241 | /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ | |||
1242 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( | |||
1243 | pipe_ctx->stream_res.hpo_dp_stream_enc); | |||
1244 | } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { | |||
1245 | pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); | |||
1246 | ||||
1247 | if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { | |||
1248 | /* | |||
1249 | * After output is idle pattern some sinks need time to recognize the stream | |||
1250 | * has changed or they enter protection state and hang. | |||
1251 | */ | |||
1252 | drm_msleep(60)mdelay(60); | |||
1253 | } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { | |||
1254 | if (!link->dc->config.edp_no_power_sequencing) { | |||
1255 | /* | |||
1256 | * Sometimes, DP receiver chip power-controlled externally by an | |||
1257 | * Embedded Controller could be treated and used as eDP, | |||
1258 | * if it drives mobile display. In this case, | |||
1259 | * we shouldn't be doing power-sequencing, hence we can skip | |||
1260 | * waiting for T9-ready. | |||
1261 | */ | |||
1262 | edp_receiver_ready_T9(link); | |||
1263 | } | |||
1264 | } | |||
1265 | } | |||
1266 | ||||
1267 | } | |||
1268 | ||||
1269 | ||||
1270 | void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool_Bool enable) | |||
1271 | { | |||
1272 | if (pipe_ctx != NULL((void *)0) && pipe_ctx->stream_res.stream_enc != NULL((void *)0)) | |||
1273 | pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); | |||
1274 | } | |||
1275 | ||||
1276 | static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) | |||
1277 | { | |||
1278 | switch (crtc_id) { | |||
1279 | case CONTROLLER_ID_D0: | |||
1280 | return DTO_SOURCE_ID0; | |||
1281 | case CONTROLLER_ID_D1: | |||
1282 | return DTO_SOURCE_ID1; | |||
1283 | case CONTROLLER_ID_D2: | |||
1284 | return DTO_SOURCE_ID2; | |||
1285 | case CONTROLLER_ID_D3: | |||
1286 | return DTO_SOURCE_ID3; | |||
1287 | case CONTROLLER_ID_D4: | |||
1288 | return DTO_SOURCE_ID4; | |||
1289 | case CONTROLLER_ID_D5: | |||
1290 | return DTO_SOURCE_ID5; | |||
1291 | default: | |||
1292 | return DTO_SOURCE_UNKNOWN; | |||
1293 | } | |||
1294 | } | |||
1295 | ||||
1296 | static void build_audio_output( | |||
1297 | struct dc_state *state, | |||
1298 | const struct pipe_ctx *pipe_ctx, | |||
1299 | struct audio_output *audio_output) | |||
1300 | { | |||
1301 | const struct dc_stream_state *stream = pipe_ctx->stream; | |||
1302 | audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; | |||
1303 | ||||
1304 | audio_output->signal = pipe_ctx->stream->signal; | |||
1305 | ||||
1306 | /* audio_crtc_info */ | |||
1307 | ||||
1308 | audio_output->crtc_info.h_total = | |||
1309 | stream->timing.h_total; | |||
1310 | ||||
1311 | /* | |||
1312 | * Audio packets are sent during actual CRTC blank physical signal, we | |||
1313 | * need to specify actual active signal portion | |||
1314 | */ | |||
1315 | audio_output->crtc_info.h_active = | |||
1316 | stream->timing.h_addressable | |||
1317 | + stream->timing.h_border_left | |||
1318 | + stream->timing.h_border_right; | |||
1319 | ||||
1320 | audio_output->crtc_info.v_active = | |||
1321 | stream->timing.v_addressable | |||
1322 | + stream->timing.v_border_top | |||
1323 | + stream->timing.v_border_bottom; | |||
1324 | ||||
1325 | audio_output->crtc_info.pixel_repetition = 1; | |||
1326 | ||||
1327 | audio_output->crtc_info.interlaced = | |||
1328 | stream->timing.flags.INTERLACE; | |||
1329 | ||||
1330 | audio_output->crtc_info.refresh_rate = | |||
1331 | (stream->timing.pix_clk_100hz*100)/ | |||
1332 | (stream->timing.h_total*stream->timing.v_total); | |||
1333 | ||||
1334 | audio_output->crtc_info.color_depth = | |||
1335 | stream->timing.display_color_depth; | |||
1336 | ||||
1337 | audio_output->crtc_info.requested_pixel_clock_100Hz = | |||
1338 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; | |||
1339 | ||||
1340 | audio_output->crtc_info.calculated_pixel_clock_100Hz = | |||
1341 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; | |||
1342 | ||||
1343 | /*for HDMI, audio ACR is with deep color ratio factor*/ | |||
1344 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && | |||
1345 | audio_output->crtc_info.requested_pixel_clock_100Hz == | |||
1346 | (stream->timing.pix_clk_100hz)) { | |||
1347 | if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { | |||
1348 | audio_output->crtc_info.requested_pixel_clock_100Hz = | |||
1349 | audio_output->crtc_info.requested_pixel_clock_100Hz/2; | |||
1350 | audio_output->crtc_info.calculated_pixel_clock_100Hz = | |||
1351 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; | |||
1352 | ||||
1353 | } | |||
1354 | } | |||
1355 | ||||
1356 | if (state->clk_mgr && | |||
1357 | (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || | |||
1358 | pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { | |||
1359 | audio_output->pll_info.dp_dto_source_clock_in_khz = | |||
1360 | state->clk_mgr->funcs->get_dp_ref_clk_frequency( | |||
1361 | state->clk_mgr); | |||
1362 | } | |||
1363 | ||||
1364 | audio_output->pll_info.feed_back_divider = | |||
1365 | pipe_ctx->pll_settings.feedback_divider; | |||
1366 | ||||
1367 | audio_output->pll_info.dto_source = | |||
1368 | translate_to_dto_source( | |||
1369 | pipe_ctx->stream_res.tg->inst + 1); | |||
1370 | ||||
1371 | /* TODO hard code to enable for now. Need get from stream */ | |||
1372 | audio_output->pll_info.ss_enabled = true1; | |||
1373 | ||||
1374 | audio_output->pll_info.ss_percentage = | |||
1375 | pipe_ctx->pll_settings.ss_percentage; | |||
1376 | } | |||
1377 | ||||
1378 | static void program_scaler(const struct dc *dc, | |||
1379 | const struct pipe_ctx *pipe_ctx) | |||
1380 | { | |||
1381 | struct tg_color color = {0}; | |||
1382 | ||||
1383 | /* TOFPGA */ | |||
1384 | if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL((void *)0)) | |||
1385 | return; | |||
1386 | ||||
1387 | if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) | |||
1388 | get_surface_visual_confirm_color(pipe_ctx, &color); | |||
1389 | else | |||
1390 | color_space_to_black_color(dc, | |||
1391 | pipe_ctx->stream->output_color_space, | |||
1392 | &color); | |||
1393 | ||||
1394 | pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( | |||
1395 | pipe_ctx->plane_res.xfm, | |||
1396 | pipe_ctx->plane_res.scl_data.lb_params.depth, | |||
1397 | &pipe_ctx->stream->bit_depth_params); | |||
1398 | ||||
1399 | if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { | |||
1400 | /* | |||
1401 | * The way 420 is packed, 2 channels carry Y component, 1 channel | |||
1402 | * alternate between Cb and Cr, so both channels need the pixel | |||
1403 | * value for Y | |||
1404 | */ | |||
1405 | if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) | |||
1406 | color.color_r_cr = color.color_g_y; | |||
1407 | ||||
1408 | pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( | |||
1409 | pipe_ctx->stream_res.tg, | |||
1410 | &color); | |||
1411 | } | |||
1412 | ||||
1413 | pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, | |||
1414 | &pipe_ctx->plane_res.scl_data); | |||
1415 | } | |||
1416 | ||||
1417 | static enum dc_status dce110_enable_stream_timing( | |||
1418 | struct pipe_ctx *pipe_ctx, | |||
1419 | struct dc_state *context, | |||
1420 | struct dc *dc) | |||
1421 | { | |||
1422 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
1423 | struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. | |||
1424 | pipe_ctx[pipe_ctx->pipe_idx]; | |||
1425 | struct tg_color black_color = {0}; | |||
1426 | ||||
1427 | if (!pipe_ctx_old->stream) { | |||
1428 | ||||
1429 | /* program blank color */ | |||
1430 | color_space_to_black_color(dc, | |||
1431 | stream->output_color_space, &black_color); | |||
1432 | pipe_ctx->stream_res.tg->funcs->set_blank_color( | |||
1433 | pipe_ctx->stream_res.tg, | |||
1434 | &black_color); | |||
1435 | ||||
1436 | /* | |||
1437 | * Must blank CRTC after disabling power gating and before any | |||
1438 | * programming, otherwise CRTC will be hung in bad state | |||
1439 | */ | |||
1440 | pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true1); | |||
1441 | ||||
1442 | if (false0 == pipe_ctx->clock_source->funcs->program_pix_clk( | |||
1443 | pipe_ctx->clock_source, | |||
1444 | &pipe_ctx->stream_res.pix_clk_params, | |||
1445 | dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), | |||
1446 | &pipe_ctx->pll_settings)) { | |||
1447 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1447); do {} while (0); } while (0); | |||
1448 | return DC_ERROR_UNEXPECTED; | |||
1449 | } | |||
1450 | ||||
1451 | if (dc_is_hdmi_tmds_signal(stream->signal)) { | |||
1452 | stream->link->phy_state.symclk_ref_cnts.otg = 1; | |||
1453 | if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) | |||
1454 | stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; | |||
1455 | else | |||
1456 | stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; | |||
1457 | } | |||
1458 | ||||
1459 | pipe_ctx->stream_res.tg->funcs->program_timing( | |||
1460 | pipe_ctx->stream_res.tg, | |||
1461 | &stream->timing, | |||
1462 | 0, | |||
1463 | 0, | |||
1464 | 0, | |||
1465 | 0, | |||
1466 | pipe_ctx->stream->signal, | |||
1467 | true1); | |||
1468 | } | |||
1469 | ||||
1470 | if (!pipe_ctx_old->stream) { | |||
1471 | if (false0 == pipe_ctx->stream_res.tg->funcs->enable_crtc( | |||
1472 | pipe_ctx->stream_res.tg)) { | |||
1473 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1473); do {} while (0); } while (0); | |||
1474 | return DC_ERROR_UNEXPECTED; | |||
1475 | } | |||
1476 | } | |||
1477 | ||||
1478 | return DC_OK; | |||
1479 | } | |||
1480 | ||||
1481 | static enum dc_status apply_single_controller_ctx_to_hw( | |||
1482 | struct pipe_ctx *pipe_ctx, | |||
1483 | struct dc_state *context, | |||
1484 | struct dc *dc) | |||
1485 | { | |||
1486 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
1487 | struct dc_link *link = stream->link; | |||
1488 | struct drr_params params = {0}; | |||
1489 | unsigned int event_triggers = 0; | |||
1490 | struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; | |||
1491 | struct dce_hwseq *hws = dc->hwseq; | |||
1492 | ||||
1493 | if (hws->funcs.disable_stream_gating) { | |||
1494 | hws->funcs.disable_stream_gating(dc, pipe_ctx); | |||
1495 | } | |||
1496 | ||||
1497 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { | |||
1498 | struct audio_output audio_output; | |||
1499 | ||||
1500 | build_audio_output(context, pipe_ctx, &audio_output); | |||
1501 | ||||
1502 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1503 | if (is_dp_128b_132b_signal(pipe_ctx)) | |||
1504 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( | |||
1505 | pipe_ctx->stream_res.hpo_dp_stream_enc, | |||
1506 | pipe_ctx->stream_res.audio->inst, | |||
1507 | &pipe_ctx->stream->audio_info); | |||
1508 | else | |||
1509 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( | |||
1510 | pipe_ctx->stream_res.stream_enc, | |||
1511 | pipe_ctx->stream_res.audio->inst, | |||
1512 | &pipe_ctx->stream->audio_info); | |||
1513 | else | |||
1514 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( | |||
1515 | pipe_ctx->stream_res.stream_enc, | |||
1516 | pipe_ctx->stream_res.audio->inst, | |||
1517 | &pipe_ctx->stream->audio_info, | |||
1518 | &audio_output.crtc_info); | |||
1519 | ||||
1520 | pipe_ctx->stream_res.audio->funcs->az_configure( | |||
1521 | pipe_ctx->stream_res.audio, | |||
1522 | pipe_ctx->stream->signal, | |||
1523 | &audio_output.crtc_info, | |||
1524 | &pipe_ctx->stream->audio_info); | |||
1525 | } | |||
1526 | ||||
1527 | /* make sure no pipes syncd to the pipe being enabled */ | |||
1528 | if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) | |||
1529 | check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); | |||
1530 | ||||
1531 | pipe_ctx->stream_res.opp->funcs->opp_program_fmt( | |||
1532 | pipe_ctx->stream_res.opp, | |||
1533 | &stream->bit_depth_params, | |||
1534 | &stream->clamping); | |||
1535 | ||||
1536 | pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( | |||
1537 | pipe_ctx->stream_res.opp, | |||
1538 | COLOR_SPACE_YCBCR601, | |||
1539 | stream->timing.display_color_depth, | |||
1540 | stream->signal); | |||
1541 | ||||
1542 | while (odm_pipe) { | |||
1543 | odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( | |||
1544 | odm_pipe->stream_res.opp, | |||
1545 | COLOR_SPACE_YCBCR601, | |||
1546 | stream->timing.display_color_depth, | |||
1547 | stream->signal); | |||
1548 | ||||
1549 | odm_pipe->stream_res.opp->funcs->opp_program_fmt( | |||
1550 | odm_pipe->stream_res.opp, | |||
1551 | &stream->bit_depth_params, | |||
1552 | &stream->clamping); | |||
1553 | odm_pipe = odm_pipe->next_odm_pipe; | |||
1554 | } | |||
1555 | ||||
1556 | /* DCN3.1 FPGA Workaround | |||
1557 | * Need to enable HPO DP Stream Encoder before setting OTG master enable. | |||
1558 | * To do so, move calling function enable_stream_timing to only be done AFTER calling | |||
1559 | * function core_link_enable_stream | |||
1560 | */ | |||
1561 | if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) | |||
1562 | /* */ | |||
1563 | /* Do not touch stream timing on seamless boot optimization. */ | |||
1564 | if (!pipe_ctx->stream->apply_seamless_boot_optimization) | |||
1565 | hws->funcs.enable_stream_timing(pipe_ctx, context, dc); | |||
1566 | ||||
1567 | if (hws->funcs.setup_vupdate_interrupt) | |||
1568 | hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); | |||
1569 | ||||
1570 | params.vertical_total_min = stream->adjust.v_total_min; | |||
1571 | params.vertical_total_max = stream->adjust.v_total_max; | |||
1572 | if (pipe_ctx->stream_res.tg->funcs->set_drr) | |||
1573 | pipe_ctx->stream_res.tg->funcs->set_drr( | |||
1574 | pipe_ctx->stream_res.tg, ¶ms); | |||
1575 | ||||
1576 | // DRR should set trigger event to monitor surface update event | |||
1577 | if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) | |||
1578 | event_triggers = 0x80; | |||
1579 | /* Event triggers and num frames initialized for DRR, but can be | |||
1580 | * later updated for PSR use. Note DRR trigger events are generated | |||
1581 | * regardless of whether num frames met. | |||
1582 | */ | |||
1583 | if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) | |||
1584 | pipe_ctx->stream_res.tg->funcs->set_static_screen_control( | |||
1585 | pipe_ctx->stream_res.tg, event_triggers, 2); | |||
1586 | ||||
1587 | if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) | |||
1588 | pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( | |||
1589 | pipe_ctx->stream_res.stream_enc, | |||
1590 | pipe_ctx->stream_res.tg->inst); | |||
1591 | ||||
1592 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
1593 | dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); | |||
1594 | ||||
1595 | if (!stream->dpms_off) | |||
1596 | core_link_enable_stream(context, pipe_ctx); | |||
1597 | ||||
1598 | /* DCN3.1 FPGA Workaround | |||
1599 | * Need to enable HPO DP Stream Encoder before setting OTG master enable. | |||
1600 | * To do so, move calling function enable_stream_timing to only be done AFTER calling | |||
1601 | * function core_link_enable_stream | |||
1602 | */ | |||
1603 | if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) { | |||
1604 | if (!pipe_ctx->stream->apply_seamless_boot_optimization) | |||
1605 | hws->funcs.enable_stream_timing(pipe_ctx, context, dc); | |||
1606 | } | |||
1607 | ||||
1608 | pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL((void *)0); | |||
1609 | ||||
1610 | pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false0; | |||
1611 | ||||
1612 | return DC_OK; | |||
1613 | } | |||
1614 | ||||
1615 | /******************************************************************************/ | |||
1616 | ||||
1617 | static void power_down_encoders(struct dc *dc) | |||
1618 | { | |||
1619 | int i; | |||
1620 | ||||
1621 | for (i = 0; i < dc->link_count; i++) { | |||
1622 | enum amd_signal_type signal = dc->links[i]->connector_signal; | |||
1623 | ||||
1624 | dc_link_blank_dp_stream(dc->links[i], false0); | |||
1625 | ||||
1626 | if (signal != SIGNAL_TYPE_EDP) | |||
1627 | signal = SIGNAL_TYPE_NONE; | |||
1628 | ||||
1629 | if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) | |||
1630 | dc->links[i]->link_enc->funcs->disable_output( | |||
1631 | dc->links[i]->link_enc, signal); | |||
1632 | ||||
1633 | dc->links[i]->link_status.link_active = false0; | |||
1634 | memset(&dc->links[i]->cur_link_settings, 0,__builtin_memset((&dc->links[i]->cur_link_settings) , (0), (sizeof(dc->links[i]->cur_link_settings))) | |||
1635 | sizeof(dc->links[i]->cur_link_settings))__builtin_memset((&dc->links[i]->cur_link_settings) , (0), (sizeof(dc->links[i]->cur_link_settings))); | |||
1636 | } | |||
1637 | } | |||
1638 | ||||
1639 | static void power_down_controllers(struct dc *dc) | |||
1640 | { | |||
1641 | int i; | |||
1642 | ||||
1643 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { | |||
1644 | dc->res_pool->timing_generators[i]->funcs->disable_crtc( | |||
1645 | dc->res_pool->timing_generators[i]); | |||
1646 | } | |||
1647 | } | |||
1648 | ||||
1649 | static void power_down_clock_sources(struct dc *dc) | |||
1650 | { | |||
1651 | int i; | |||
1652 | ||||
1653 | if (dc->res_pool->dp_clock_source->funcs->cs_power_down( | |||
1654 | dc->res_pool->dp_clock_source) == false0) | |||
1655 | dm_error("Failed to power down pll! (dp clk src)\n")__drm_err("Failed to power down pll! (dp clk src)\n"); | |||
1656 | ||||
1657 | for (i = 0; i < dc->res_pool->clk_src_count; i++) { | |||
1658 | if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( | |||
1659 | dc->res_pool->clock_sources[i]) == false0) | |||
1660 | dm_error("Failed to power down pll! (clk src index=%d)\n", i)__drm_err("Failed to power down pll! (clk src index=%d)\n", i ); | |||
1661 | } | |||
1662 | } | |||
1663 | ||||
1664 | static void power_down_all_hw_blocks(struct dc *dc) | |||
1665 | { | |||
1666 | power_down_encoders(dc); | |||
1667 | ||||
1668 | power_down_controllers(dc); | |||
1669 | ||||
1670 | power_down_clock_sources(dc); | |||
1671 | ||||
1672 | if (dc->fbc_compressor) | |||
1673 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); | |||
1674 | } | |||
1675 | ||||
1676 | static void disable_vga_and_power_gate_all_controllers( | |||
1677 | struct dc *dc) | |||
1678 | { | |||
1679 | int i; | |||
1680 | struct timing_generator *tg; | |||
1681 | struct dc_context *ctx = dc->ctx; | |||
1682 | ||||
1683 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { | |||
1684 | tg = dc->res_pool->timing_generators[i]; | |||
1685 | ||||
1686 | if (tg->funcs->disable_vga) | |||
1687 | tg->funcs->disable_vga(tg); | |||
1688 | } | |||
1689 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1690 | /* Enable CLOCK gating for each pipe BEFORE controller | |||
1691 | * powergating. */ | |||
1692 | enable_display_pipe_clock_gating(ctx, | |||
1693 | true1); | |||
1694 | ||||
1695 | dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; | |||
1696 | dc->hwss.disable_plane(dc, | |||
1697 | &dc->current_state->res_ctx.pipe_ctx[i]); | |||
1698 | } | |||
1699 | } | |||
1700 | ||||
1701 | ||||
1702 | static void get_edp_streams(struct dc_state *context, | |||
1703 | struct dc_stream_state **edp_streams, | |||
1704 | int *edp_stream_num) | |||
1705 | { | |||
1706 | int i; | |||
1707 | ||||
1708 | *edp_stream_num = 0; | |||
1709 | for (i = 0; i < context->stream_count; i++) { | |||
1710 | if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { | |||
1711 | edp_streams[*edp_stream_num] = context->streams[i]; | |||
1712 | if (++(*edp_stream_num) == MAX_NUM_EDP2) | |||
1713 | return; | |||
1714 | } | |||
1715 | } | |||
1716 | } | |||
1717 | ||||
1718 | static void get_edp_links_with_sink( | |||
1719 | struct dc *dc, | |||
1720 | struct dc_link **edp_links_with_sink, | |||
1721 | int *edp_with_sink_num) | |||
1722 | { | |||
1723 | int i; | |||
1724 | ||||
1725 | /* check if there is an eDP panel not in use */ | |||
1726 | *edp_with_sink_num = 0; | |||
1727 | for (i = 0; i < dc->link_count; i++) { | |||
1728 | if (dc->links[i]->local_sink && | |||
1729 | dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { | |||
1730 | edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; | |||
1731 | if (++(*edp_with_sink_num) == MAX_NUM_EDP2) | |||
1732 | return; | |||
1733 | } | |||
1734 | } | |||
1735 | } | |||
1736 | ||||
1737 | /* | |||
1738 | * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: | |||
1739 | * 1. Power down all DC HW blocks | |||
1740 | * 2. Disable VGA engine on all controllers | |||
1741 | * 3. Enable power gating for controller | |||
1742 | * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) | |||
1743 | */ | |||
1744 | void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) | |||
1745 | { | |||
1746 | struct dc_link *edp_links_with_sink[MAX_NUM_EDP2]; | |||
1747 | struct dc_link *edp_links[MAX_NUM_EDP2]; | |||
1748 | struct dc_stream_state *edp_streams[MAX_NUM_EDP2]; | |||
1749 | struct dc_link *edp_link_with_sink = NULL((void *)0); | |||
1750 | struct dc_link *edp_link = NULL((void *)0); | |||
1751 | struct dce_hwseq *hws = dc->hwseq; | |||
1752 | int edp_with_sink_num; | |||
1753 | int edp_num; | |||
1754 | int edp_stream_num; | |||
1755 | int i; | |||
1756 | bool_Bool can_apply_edp_fast_boot = false0; | |||
1757 | bool_Bool can_apply_seamless_boot = false0; | |||
1758 | bool_Bool keep_edp_vdd_on = false0; | |||
1759 | DC_LOGGER_INIT(); | |||
1760 | ||||
1761 | ||||
1762 | get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); | |||
1763 | get_edp_links(dc, edp_links, &edp_num); | |||
1764 | ||||
1765 | if (hws->funcs.init_pipes) | |||
1766 | hws->funcs.init_pipes(dc, context); | |||
1767 | ||||
1768 | get_edp_streams(context, edp_streams, &edp_stream_num); | |||
1769 | ||||
1770 | // Check fastboot support, disable on DCE8 because of blank screens | |||
1771 | if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && | |||
1772 | dc->ctx->dce_version != DCE_VERSION_8_1 && | |||
1773 | dc->ctx->dce_version != DCE_VERSION_8_3) { | |||
1774 | for (i = 0; i < edp_num; i++) { | |||
1775 | edp_link = edp_links[i]; | |||
1776 | if (edp_link != edp_streams[0]->link) | |||
1777 | continue; | |||
1778 | // enable fastboot if backend is enabled on eDP | |||
1779 | if (edp_link->link_enc->funcs->is_dig_enabled && | |||
1780 | edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && | |||
1781 | edp_link->link_status.link_active) { | |||
1782 | struct dc_stream_state *edp_stream = edp_streams[0]; | |||
1783 | ||||
1784 | can_apply_edp_fast_boot = dc_validate_boot_timing(dc, | |||
1785 | edp_stream->sink, &edp_stream->timing); | |||
1786 | edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; | |||
1787 | if (can_apply_edp_fast_boot) | |||
1788 | DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n")___drm_dbg(((void *)0), DRM_UT_KMS, "eDP fast boot disabled to optimize link rate\n" ); | |||
1789 | ||||
1790 | break; | |||
1791 | } | |||
1792 | } | |||
1793 | // We are trying to enable eDP, don't power down VDD | |||
1794 | if (can_apply_edp_fast_boot) | |||
1795 | keep_edp_vdd_on = true1; | |||
1796 | } | |||
1797 | ||||
1798 | // Check seamless boot support | |||
1799 | for (i = 0; i < context->stream_count; i++) { | |||
1800 | if (context->streams[i]->apply_seamless_boot_optimization) { | |||
1801 | can_apply_seamless_boot = true1; | |||
1802 | break; | |||
1803 | } | |||
1804 | } | |||
1805 | ||||
1806 | /* eDP should not have stream in resume from S4 and so even with VBios post | |||
1807 | * it should get turned off | |||
1808 | */ | |||
1809 | if (edp_with_sink_num) | |||
1810 | edp_link_with_sink = edp_links_with_sink[0]; | |||
1811 | ||||
1812 | if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { | |||
1813 | if (edp_link_with_sink && !keep_edp_vdd_on) { | |||
1814 | /*turn off backlight before DP_blank and encoder powered down*/ | |||
1815 | hws->funcs.edp_backlight_control(edp_link_with_sink, false0); | |||
1816 | } | |||
1817 | /*resume from S3, no vbios posting, no need to power down again*/ | |||
1818 | clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); | |||
1819 | ||||
1820 | power_down_all_hw_blocks(dc); | |||
1821 | disable_vga_and_power_gate_all_controllers(dc); | |||
1822 | if (edp_link_with_sink && !keep_edp_vdd_on) | |||
1823 | dc->hwss.edp_power_control(edp_link_with_sink, false0); | |||
1824 | clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); | |||
1825 | } | |||
1826 | bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); | |||
1827 | } | |||
1828 | ||||
1829 | static uint32_t compute_pstate_blackout_duration( | |||
1830 | struct bw_fixed blackout_duration, | |||
1831 | const struct dc_stream_state *stream) | |||
1832 | { | |||
1833 | uint32_t total_dest_line_time_ns; | |||
1834 | uint32_t pstate_blackout_duration_ns; | |||
1835 | ||||
1836 | pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; | |||
1837 | ||||
1838 | total_dest_line_time_ns = 1000000UL * | |||
1839 | (stream->timing.h_total * 10) / | |||
1840 | stream->timing.pix_clk_100hz + | |||
1841 | pstate_blackout_duration_ns; | |||
1842 | ||||
1843 | return total_dest_line_time_ns; | |||
1844 | } | |||
1845 | ||||
1846 | static void dce110_set_displaymarks( | |||
1847 | const struct dc *dc, | |||
1848 | struct dc_state *context) | |||
1849 | { | |||
1850 | uint8_t i, num_pipes; | |||
1851 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; | |||
1852 | ||||
1853 | for (i = 0, num_pipes = 0; i < MAX_PIPES6; i++) { | |||
1854 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
1855 | uint32_t total_dest_line_time_ns; | |||
1856 | ||||
1857 | if (pipe_ctx->stream == NULL((void *)0)) | |||
1858 | continue; | |||
1859 | ||||
1860 | total_dest_line_time_ns = compute_pstate_blackout_duration( | |||
1861 | dc->bw_vbios->blackout_duration, pipe_ctx->stream); | |||
1862 | pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( | |||
1863 | pipe_ctx->plane_res.mi, | |||
1864 | context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], | |||
1865 | context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], | |||
1866 | context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], | |||
1867 | context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], | |||
1868 | total_dest_line_time_ns); | |||
1869 | if (i == underlay_idx) { | |||
1870 | num_pipes++; | |||
1871 | pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( | |||
1872 | pipe_ctx->plane_res.mi, | |||
1873 | context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], | |||
1874 | context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], | |||
1875 | context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], | |||
1876 | total_dest_line_time_ns); | |||
1877 | } | |||
1878 | num_pipes++; | |||
1879 | } | |||
1880 | } | |||
1881 | ||||
1882 | void dce110_set_safe_displaymarks( | |||
1883 | struct resource_context *res_ctx, | |||
1884 | const struct resource_pool *pool) | |||
1885 | { | |||
1886 | int i; | |||
1887 | int underlay_idx = pool->underlay_pipe_index; | |||
1888 | struct dce_watermarks max_marks = { | |||
1889 | MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF }; | |||
1890 | struct dce_watermarks nbp_marks = { | |||
1891 | SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF }; | |||
1892 | struct dce_watermarks min_marks = { 0, 0, 0, 0}; | |||
1893 | ||||
1894 | for (i = 0; i < MAX_PIPES6; i++) { | |||
1895 | if (res_ctx->pipe_ctx[i].stream == NULL((void *)0) || res_ctx->pipe_ctx[i].plane_res.mi == NULL((void *)0)) | |||
1896 | continue; | |||
1897 | ||||
1898 | res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( | |||
1899 | res_ctx->pipe_ctx[i].plane_res.mi, | |||
1900 | nbp_marks, | |||
1901 | max_marks, | |||
1902 | min_marks, | |||
1903 | max_marks, | |||
1904 | MAX_WATERMARK0xFFFF); | |||
1905 | ||||
1906 | if (i == underlay_idx) | |||
1907 | res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( | |||
1908 | res_ctx->pipe_ctx[i].plane_res.mi, | |||
1909 | nbp_marks, | |||
1910 | max_marks, | |||
1911 | max_marks, | |||
1912 | MAX_WATERMARK0xFFFF); | |||
1913 | ||||
1914 | } | |||
1915 | } | |||
1916 | ||||
1917 | /******************************************************************************* | |||
1918 | * Public functions | |||
1919 | ******************************************************************************/ | |||
1920 | ||||
1921 | static void set_drr(struct pipe_ctx **pipe_ctx, | |||
1922 | int num_pipes, struct dc_crtc_timing_adjust adjust) | |||
1923 | { | |||
1924 | int i = 0; | |||
1925 | struct drr_params params = {0}; | |||
1926 | // DRR should set trigger event to monitor surface update event | |||
1927 | unsigned int event_triggers = 0x80; | |||
1928 | // Note DRR trigger events are generated regardless of whether num frames met. | |||
1929 | unsigned int num_frames = 2; | |||
1930 | ||||
1931 | params.vertical_total_max = adjust.v_total_max; | |||
1932 | params.vertical_total_min = adjust.v_total_min; | |||
1933 | ||||
1934 | /* TODO: If multiple pipes are to be supported, you need | |||
1935 | * some GSL stuff. Static screen triggers may be programmed differently | |||
1936 | * as well. | |||
1937 | */ | |||
1938 | for (i = 0; i < num_pipes; i++) { | |||
1939 | pipe_ctx[i]->stream_res.tg->funcs->set_drr( | |||
1940 | pipe_ctx[i]->stream_res.tg, ¶ms); | |||
1941 | ||||
1942 | if (adjust.v_total_max != 0 && adjust.v_total_min != 0) | |||
1943 | pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( | |||
1944 | pipe_ctx[i]->stream_res.tg, | |||
1945 | event_triggers, num_frames); | |||
1946 | } | |||
1947 | } | |||
1948 | ||||
1949 | static void get_position(struct pipe_ctx **pipe_ctx, | |||
1950 | int num_pipes, | |||
1951 | struct crtc_position *position) | |||
1952 | { | |||
1953 | int i = 0; | |||
1954 | ||||
1955 | /* TODO: handle pipes > 1 | |||
1956 | */ | |||
1957 | for (i = 0; i < num_pipes; i++) | |||
1958 | pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); | |||
1959 | } | |||
1960 | ||||
1961 | static void set_static_screen_control(struct pipe_ctx **pipe_ctx, | |||
1962 | int num_pipes, const struct dc_static_screen_params *params) | |||
1963 | { | |||
1964 | unsigned int i; | |||
1965 | unsigned int triggers = 0; | |||
1966 | ||||
1967 | if (params->triggers.overlay_update) | |||
1968 | triggers |= 0x100; | |||
1969 | if (params->triggers.surface_update) | |||
1970 | triggers |= 0x80; | |||
1971 | if (params->triggers.cursor_update) | |||
1972 | triggers |= 0x2; | |||
1973 | if (params->triggers.force_trigger) | |||
1974 | triggers |= 0x1; | |||
1975 | ||||
1976 | if (num_pipes) { | |||
1977 | struct dc *dc = pipe_ctx[0]->stream->ctx->dc; | |||
1978 | ||||
1979 | if (dc->fbc_compressor) | |||
1980 | triggers |= 0x84; | |||
1981 | } | |||
1982 | ||||
1983 | for (i = 0; i < num_pipes; i++) | |||
1984 | pipe_ctx[i]->stream_res.tg->funcs-> | |||
1985 | set_static_screen_control(pipe_ctx[i]->stream_res.tg, | |||
1986 | triggers, params->num_frames); | |||
1987 | } | |||
1988 | ||||
1989 | /* | |||
1990 | * Check if FBC can be enabled | |||
1991 | */ | |||
1992 | static bool_Bool should_enable_fbc(struct dc *dc, | |||
1993 | struct dc_state *context, | |||
1994 | uint32_t *pipe_idx) | |||
1995 | { | |||
1996 | uint32_t i; | |||
1997 | struct pipe_ctx *pipe_ctx = NULL((void *)0); | |||
1998 | struct resource_context *res_ctx = &context->res_ctx; | |||
1999 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; | |||
2000 | ||||
2001 | ||||
2002 | ASSERT(dc->fbc_compressor)do { if (({ static int __warned; int __ret = !!(!(dc->fbc_compressor )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dc->fbc_compressor)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 2002); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2003 | ||||
2004 | /* FBC memory should be allocated */ | |||
2005 | if (!dc->ctx->fbc_gpu_addr) | |||
2006 | return false0; | |||
2007 | ||||
2008 | /* Only supports single display */ | |||
2009 | if (context->stream_count != 1) | |||
2010 | return false0; | |||
2011 | ||||
2012 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2013 | if (res_ctx->pipe_ctx[i].stream) { | |||
2014 | ||||
2015 | pipe_ctx = &res_ctx->pipe_ctx[i]; | |||
2016 | ||||
2017 | if (!pipe_ctx) | |||
2018 | continue; | |||
2019 | ||||
2020 | /* fbc not applicable on underlay pipe */ | |||
2021 | if (pipe_ctx->pipe_idx != underlay_idx) { | |||
2022 | *pipe_idx = i; | |||
2023 | break; | |||
2024 | } | |||
2025 | } | |||
2026 | } | |||
2027 | ||||
2028 | if (i == dc->res_pool->pipe_count) | |||
2029 | return false0; | |||
2030 | ||||
2031 | if (!pipe_ctx->stream->link) | |||
2032 | return false0; | |||
2033 | ||||
2034 | /* Only supports eDP */ | |||
2035 | if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) | |||
2036 | return false0; | |||
2037 | ||||
2038 | /* PSR should not be enabled */ | |||
2039 | if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) | |||
2040 | return false0; | |||
2041 | ||||
2042 | /* Nothing to compress */ | |||
2043 | if (!pipe_ctx->plane_state) | |||
2044 | return false0; | |||
2045 | ||||
2046 | /* Only for non-linear tiling */ | |||
2047 | if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) | |||
2048 | return false0; | |||
2049 | ||||
2050 | return true1; | |||
2051 | } | |||
2052 | ||||
2053 | /* | |||
2054 | * Enable FBC | |||
2055 | */ | |||
2056 | static void enable_fbc( | |||
2057 | struct dc *dc, | |||
2058 | struct dc_state *context) | |||
2059 | { | |||
2060 | uint32_t pipe_idx = 0; | |||
2061 | ||||
2062 | if (should_enable_fbc(dc, context, &pipe_idx)) { | |||
2063 | /* Program GRPH COMPRESSED ADDRESS and PITCH */ | |||
2064 | struct compr_addr_and_pitch_params params = {0, 0, 0}; | |||
2065 | struct compressor *compr = dc->fbc_compressor; | |||
2066 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; | |||
2067 | ||||
2068 | params.source_view_width = pipe_ctx->stream->timing.h_addressable; | |||
2069 | params.source_view_height = pipe_ctx->stream->timing.v_addressable; | |||
2070 | params.inst = pipe_ctx->stream_res.tg->inst; | |||
2071 | compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; | |||
2072 | ||||
2073 | compr->funcs->surface_address_and_pitch(compr, ¶ms); | |||
2074 | compr->funcs->set_fbc_invalidation_triggers(compr, 1); | |||
2075 | ||||
2076 | compr->funcs->enable_fbc(compr, ¶ms); | |||
2077 | } | |||
2078 | } | |||
2079 | ||||
2080 | static void dce110_reset_hw_ctx_wrap( | |||
2081 | struct dc *dc, | |||
2082 | struct dc_state *context) | |||
2083 | { | |||
2084 | int i; | |||
2085 | ||||
2086 | /* Reset old context */ | |||
2087 | /* look up the targets that have been removed since last commit */ | |||
2088 | for (i = 0; i < MAX_PIPES6; i++) { | |||
2089 | struct pipe_ctx *pipe_ctx_old = | |||
2090 | &dc->current_state->res_ctx.pipe_ctx[i]; | |||
2091 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2092 | ||||
2093 | /* Note: We need to disable output if clock sources change, | |||
2094 | * since bios does optimization and doesn't apply if changing | |||
2095 | * PHY when not already disabled. | |||
2096 | */ | |||
2097 | ||||
2098 | /* Skip underlay pipe since it will be handled in commit surface*/ | |||
2099 | if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) | |||
2100 | continue; | |||
2101 | ||||
2102 | if (!pipe_ctx->stream || | |||
2103 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { | |||
2104 | struct clock_source *old_clk = pipe_ctx_old->clock_source; | |||
2105 | ||||
2106 | /* Disable if new stream is null. O/w, if stream is | |||
2107 | * disabled already, no need to disable again. | |||
2108 | */ | |||
2109 | if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { | |||
2110 | core_link_disable_stream(pipe_ctx_old); | |||
2111 | ||||
2112 | /* free acquired resources*/ | |||
2113 | if (pipe_ctx_old->stream_res.audio) { | |||
2114 | /*disable az_endpoint*/ | |||
2115 | pipe_ctx_old->stream_res.audio->funcs-> | |||
2116 | az_disable(pipe_ctx_old->stream_res.audio); | |||
2117 | ||||
2118 | /*free audio*/ | |||
2119 | if (dc->caps.dynamic_audio == true1) { | |||
2120 | /*we have to dynamic arbitrate the audio endpoints*/ | |||
2121 | /*we free the resource, need reset is_audio_acquired*/ | |||
2122 | update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, | |||
2123 | pipe_ctx_old->stream_res.audio, false0); | |||
2124 | pipe_ctx_old->stream_res.audio = NULL((void *)0); | |||
2125 | } | |||
2126 | } | |||
2127 | } | |||
2128 | ||||
2129 | pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true1); | |||
2130 | if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { | |||
2131 | dm_error("DC: failed to blank crtc!\n")__drm_err("DC: failed to blank crtc!\n"); | |||
2132 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2132); do {} while (0); } while (0); | |||
2133 | } | |||
2134 | pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); | |||
2135 | pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0; | |||
2136 | pipe_ctx_old->plane_res.mi->funcs->free_mem_input( | |||
2137 | pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); | |||
2138 | ||||
2139 | if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, | |||
2140 | dc->res_pool, | |||
2141 | old_clk)) | |||
2142 | old_clk->funcs->cs_power_down(old_clk); | |||
2143 | ||||
2144 | dc->hwss.disable_plane(dc, pipe_ctx_old); | |||
2145 | ||||
2146 | pipe_ctx_old->stream = NULL((void *)0); | |||
2147 | } | |||
2148 | } | |||
2149 | } | |||
2150 | ||||
2151 | static void dce110_setup_audio_dto( | |||
2152 | struct dc *dc, | |||
2153 | struct dc_state *context) | |||
2154 | { | |||
2155 | int i; | |||
2156 | ||||
2157 | /* program audio wall clock. use HDMI as clock source if HDMI | |||
2158 | * audio active. Otherwise, use DP as clock source | |||
2159 | * first, loop to find any HDMI audio, if not, loop find DP audio | |||
2160 | */ | |||
2161 | /* Setup audio rate clock source */ | |||
2162 | /* Issue: | |||
2163 | * Audio lag happened on DP monitor when unplug a HDMI monitor | |||
2164 | * | |||
2165 | * Cause: | |||
2166 | * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL | |||
2167 | * is set to either dto0 or dto1, audio should work fine. | |||
2168 | * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, | |||
2169 | * set to dto0 will cause audio lag. | |||
2170 | * | |||
2171 | * Solution: | |||
2172 | * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, | |||
2173 | * find first available pipe with audio, setup audio wall DTO per topology | |||
2174 | * instead of per pipe. | |||
2175 | */ | |||
2176 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2177 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2178 | ||||
2179 | if (pipe_ctx->stream == NULL((void *)0)) | |||
2180 | continue; | |||
2181 | ||||
2182 | if (pipe_ctx->top_pipe) | |||
2183 | continue; | |||
2184 | if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) | |||
2185 | continue; | |||
2186 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { | |||
2187 | struct audio_output audio_output; | |||
2188 | ||||
2189 | build_audio_output(context, pipe_ctx, &audio_output); | |||
2190 | ||||
2191 | if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { | |||
2192 | struct dtbclk_dto_params dto_params = {0}; | |||
2193 | ||||
2194 | dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( | |||
2195 | dc->res_pool->dccg, &dto_params); | |||
2196 | ||||
2197 | pipe_ctx->stream_res.audio->funcs->wall_dto_setup( | |||
2198 | pipe_ctx->stream_res.audio, | |||
2199 | pipe_ctx->stream->signal, | |||
2200 | &audio_output.crtc_info, | |||
2201 | &audio_output.pll_info); | |||
2202 | } else | |||
2203 | pipe_ctx->stream_res.audio->funcs->wall_dto_setup( | |||
2204 | pipe_ctx->stream_res.audio, | |||
2205 | pipe_ctx->stream->signal, | |||
2206 | &audio_output.crtc_info, | |||
2207 | &audio_output.pll_info); | |||
2208 | break; | |||
2209 | } | |||
2210 | } | |||
2211 | ||||
2212 | /* no HDMI audio is found, try DP audio */ | |||
2213 | if (i == dc->res_pool->pipe_count) { | |||
2214 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2215 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2216 | ||||
2217 | if (pipe_ctx->stream == NULL((void *)0)) | |||
2218 | continue; | |||
2219 | ||||
2220 | if (pipe_ctx->top_pipe) | |||
2221 | continue; | |||
2222 | ||||
2223 | if (!dc_is_dp_signal(pipe_ctx->stream->signal)) | |||
2224 | continue; | |||
2225 | ||||
2226 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { | |||
2227 | struct audio_output audio_output; | |||
2228 | ||||
2229 | build_audio_output(context, pipe_ctx, &audio_output); | |||
2230 | ||||
2231 | pipe_ctx->stream_res.audio->funcs->wall_dto_setup( | |||
2232 | pipe_ctx->stream_res.audio, | |||
2233 | pipe_ctx->stream->signal, | |||
2234 | &audio_output.crtc_info, | |||
2235 | &audio_output.pll_info); | |||
2236 | break; | |||
2237 | } | |||
2238 | } | |||
2239 | } | |||
2240 | } | |||
2241 | ||||
2242 | enum dc_status dce110_apply_ctx_to_hw( | |||
2243 | struct dc *dc, | |||
2244 | struct dc_state *context) | |||
2245 | { | |||
2246 | struct dce_hwseq *hws = dc->hwseq; | |||
2247 | struct dc_bios *dcb = dc->ctx->dc_bios; | |||
2248 | enum dc_status status; | |||
2249 | int i; | |||
2250 | ||||
2251 | /* reset syncd pipes from disabled pipes */ | |||
2252 | if (dc->config.use_pipe_ctx_sync_logic) | |||
2253 | reset_syncd_pipes_from_disabled_pipes(dc, context); | |||
2254 | ||||
2255 | /* Reset old context */ | |||
2256 | /* look up the targets that have been removed since last commit */ | |||
2257 | hws->funcs.reset_hw_ctx_wrap(dc, context); | |||
2258 | ||||
2259 | /* Skip applying if no targets */ | |||
2260 | if (context->stream_count <= 0) | |||
2261 | return DC_OK; | |||
2262 | ||||
2263 | /* Apply new context */ | |||
2264 | dcb->funcs->set_scratch_critical_state(dcb, true1); | |||
2265 | ||||
2266 | /* below is for real asic only */ | |||
2267 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2268 | struct pipe_ctx *pipe_ctx_old = | |||
2269 | &dc->current_state->res_ctx.pipe_ctx[i]; | |||
2270 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2271 | ||||
2272 | if (pipe_ctx->stream == NULL((void *)0) || pipe_ctx->top_pipe) | |||
2273 | continue; | |||
2274 | ||||
2275 | if (pipe_ctx->stream == pipe_ctx_old->stream) { | |||
2276 | if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) | |||
2277 | dce_crtc_switch_to_clk_src(dc->hwseq, | |||
2278 | pipe_ctx->clock_source, i); | |||
2279 | continue; | |||
2280 | } | |||
2281 | ||||
2282 | hws->funcs.enable_display_power_gating( | |||
2283 | dc, i, dc->ctx->dc_bios, | |||
2284 | PIPE_GATING_CONTROL_DISABLE); | |||
2285 | } | |||
2286 | ||||
2287 | if (dc->fbc_compressor) | |||
2288 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); | |||
2289 | ||||
2290 | dce110_setup_audio_dto(dc, context); | |||
2291 | ||||
2292 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2293 | struct pipe_ctx *pipe_ctx_old = | |||
2294 | &dc->current_state->res_ctx.pipe_ctx[i]; | |||
2295 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2296 | ||||
2297 | if (pipe_ctx->stream == NULL((void *)0)) | |||
2298 | continue; | |||
2299 | ||||
2300 | if (pipe_ctx->stream == pipe_ctx_old->stream && | |||
2301 | pipe_ctx->stream->link->link_state_valid) { | |||
2302 | continue; | |||
2303 | } | |||
2304 | ||||
2305 | if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) | |||
2306 | continue; | |||
2307 | ||||
2308 | if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) | |||
2309 | continue; | |||
2310 | ||||
2311 | status = apply_single_controller_ctx_to_hw( | |||
2312 | pipe_ctx, | |||
2313 | context, | |||
2314 | dc); | |||
2315 | ||||
2316 | if (DC_OK != status) | |||
2317 | return status; | |||
2318 | } | |||
2319 | ||||
2320 | if (dc->fbc_compressor) | |||
2321 | enable_fbc(dc, dc->current_state); | |||
2322 | ||||
2323 | dcb->funcs->set_scratch_critical_state(dcb, false0); | |||
2324 | ||||
2325 | return DC_OK; | |||
2326 | } | |||
2327 | ||||
2328 | /******************************************************************************* | |||
2329 | * Front End programming | |||
2330 | ******************************************************************************/ | |||
2331 | static void set_default_colors(struct pipe_ctx *pipe_ctx) | |||
2332 | { | |||
2333 | struct default_adjustment default_adjust = { 0 }; | |||
2334 | ||||
2335 | default_adjust.force_hw_default = false0; | |||
2336 | default_adjust.in_color_space = pipe_ctx->plane_state->color_space; | |||
2337 | default_adjust.out_color_space = pipe_ctx->stream->output_color_space; | |||
2338 | default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; | |||
2339 | default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; | |||
2340 | ||||
2341 | /* display color depth */ | |||
2342 | default_adjust.color_depth = | |||
2343 | pipe_ctx->stream->timing.display_color_depth; | |||
2344 | ||||
2345 | /* Lb color depth */ | |||
2346 | default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; | |||
2347 | ||||
2348 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( | |||
2349 | pipe_ctx->plane_res.xfm, &default_adjust); | |||
2350 | } | |||
2351 | ||||
2352 | ||||
2353 | /******************************************************************************* | |||
2354 | * In order to turn on/off specific surface we will program | |||
2355 | * Blender + CRTC | |||
2356 | * | |||
2357 | * In case that we have two surfaces and they have a different visibility | |||
2358 | * we can't turn off the CRTC since it will turn off the entire display | |||
2359 | * | |||
2360 | * |----------------------------------------------- | | |||
2361 | * |bottom pipe|curr pipe | | | | |||
2362 | * |Surface |Surface | Blender | CRCT | | |||
2363 | * |visibility |visibility | Configuration| | | |||
2364 | * |------------------------------------------------| | |||
2365 | * | off | off | CURRENT_PIPE | blank | | |||
2366 | * | off | on | CURRENT_PIPE | unblank | | |||
2367 | * | on | off | OTHER_PIPE | unblank | | |||
2368 | * | on | on | BLENDING | unblank | | |||
2369 | * -------------------------------------------------| | |||
2370 | * | |||
2371 | ******************************************************************************/ | |||
2372 | static void program_surface_visibility(const struct dc *dc, | |||
2373 | struct pipe_ctx *pipe_ctx) | |||
2374 | { | |||
2375 | enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; | |||
2376 | bool_Bool blank_target = false0; | |||
2377 | ||||
2378 | if (pipe_ctx->bottom_pipe) { | |||
2379 | ||||
2380 | /* For now we are supporting only two pipes */ | |||
2381 | ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> bottom_pipe->bottom_pipe == ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(pipe_ctx->bottom_pipe->bottom_pipe == ((void *)0))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 2381); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2382 | ||||
2383 | if (pipe_ctx->bottom_pipe->plane_state->visible) { | |||
2384 | if (pipe_ctx->plane_state->visible) | |||
2385 | blender_mode = BLND_MODE_BLENDING; | |||
2386 | else | |||
2387 | blender_mode = BLND_MODE_OTHER_PIPE; | |||
2388 | ||||
2389 | } else if (!pipe_ctx->plane_state->visible) | |||
2390 | blank_target = true1; | |||
2391 | ||||
2392 | } else if (!pipe_ctx->plane_state->visible) | |||
2393 | blank_target = true1; | |||
2394 | ||||
2395 | dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); | |||
2396 | pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); | |||
2397 | ||||
2398 | } | |||
2399 | ||||
2400 | static void program_gamut_remap(struct pipe_ctx *pipe_ctx) | |||
2401 | { | |||
2402 | int i = 0; | |||
2403 | struct xfm_grph_csc_adjustment adjust; | |||
2404 | memset(&adjust, 0, sizeof(adjust))__builtin_memset((&adjust), (0), (sizeof(adjust))); | |||
2405 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |||
2406 | ||||
2407 | ||||
2408 | if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true1) { | |||
2409 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |||
2410 | ||||
2411 | for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE12; i++) | |||
2412 | adjust.temperature_matrix[i] = | |||
2413 | pipe_ctx->stream->gamut_remap_matrix.matrix[i]; | |||
2414 | } | |||
2415 | ||||
2416 | pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); | |||
2417 | } | |||
2418 | static void update_plane_addr(const struct dc *dc, | |||
2419 | struct pipe_ctx *pipe_ctx) | |||
2420 | { | |||
2421 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; | |||
2422 | ||||
2423 | if (plane_state == NULL((void *)0)) | |||
2424 | return; | |||
2425 | ||||
2426 | pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( | |||
2427 | pipe_ctx->plane_res.mi, | |||
2428 | &plane_state->address, | |||
2429 | plane_state->flip_immediate); | |||
2430 | ||||
2431 | plane_state->status.requested_address = plane_state->address; | |||
2432 | } | |||
2433 | ||||
2434 | static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) | |||
2435 | { | |||
2436 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; | |||
2437 | ||||
2438 | if (plane_state == NULL((void *)0)) | |||
2439 | return; | |||
2440 | ||||
2441 | plane_state->status.is_flip_pending = | |||
2442 | pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( | |||
2443 | pipe_ctx->plane_res.mi); | |||
2444 | ||||
2445 | if (plane_state->status.is_flip_pending && !plane_state->visible) | |||
2446 | pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; | |||
2447 | ||||
2448 | plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; | |||
2449 | if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && | |||
2450 | pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { | |||
2451 | plane_state->status.is_right_eye =\ | |||
2452 | !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); | |||
2453 | } | |||
2454 | } | |||
2455 | ||||
2456 | void dce110_power_down(struct dc *dc) | |||
2457 | { | |||
2458 | power_down_all_hw_blocks(dc); | |||
2459 | disable_vga_and_power_gate_all_controllers(dc); | |||
2460 | } | |||
2461 | ||||
2462 | static bool_Bool wait_for_reset_trigger_to_occur( | |||
2463 | struct dc_context *dc_ctx, | |||
2464 | struct timing_generator *tg) | |||
2465 | { | |||
2466 | bool_Bool rc = false0; | |||
2467 | ||||
2468 | /* To avoid endless loop we wait at most | |||
2469 | * frames_to_wait_on_triggered_reset frames for the reset to occur. */ | |||
2470 | const uint32_t frames_to_wait_on_triggered_reset = 10; | |||
2471 | uint32_t i; | |||
2472 | ||||
2473 | for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { | |||
2474 | ||||
2475 | if (!tg->funcs->is_counter_moving(tg)) { | |||
2476 | DC_ERROR("TG counter is not moving!\n")do { (void)(dc_ctx); __drm_err("TG counter is not moving!\n") ; } while (0); | |||
2477 | break; | |||
2478 | } | |||
2479 | ||||
2480 | if (tg->funcs->did_triggered_reset_occur(tg)) { | |||
2481 | rc = true1; | |||
2482 | /* usually occurs at i=1 */ | |||
2483 | DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: reset occurred at wait count: %d\n" , i); } while (0) | |||
2484 | i)do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: reset occurred at wait count: %d\n" , i); } while (0); | |||
2485 | break; | |||
2486 | } | |||
2487 | ||||
2488 | /* Wait for one frame. */ | |||
2489 | tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); | |||
2490 | tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); | |||
2491 | } | |||
2492 | ||||
2493 | if (false0 == rc) | |||
2494 | DC_ERROR("GSL: Timeout on reset trigger!\n")do { (void)(dc_ctx); __drm_err("GSL: Timeout on reset trigger!\n" ); } while (0); | |||
2495 | ||||
2496 | return rc; | |||
2497 | } | |||
2498 | ||||
2499 | /* Enable timing synchronization for a group of Timing Generators. */ | |||
2500 | static void dce110_enable_timing_synchronization( | |||
2501 | struct dc *dc, | |||
2502 | int group_index, | |||
2503 | int group_size, | |||
2504 | struct pipe_ctx *grouped_pipes[]) | |||
2505 | { | |||
2506 | struct dc_context *dc_ctx = dc->ctx; | |||
2507 | struct dcp_gsl_params gsl_params = { 0 }; | |||
2508 | int i; | |||
2509 | ||||
2510 | DC_SYNC_INFO("GSL: Setting-up...\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: Setting-up...\n" ); } while (0); | |||
2511 | ||||
2512 | /* Designate a single TG in the group as a master. | |||
2513 | * Since HW doesn't care which one, we always assign | |||
2514 | * the 1st one in the group. */ | |||
2515 | gsl_params.gsl_group = 0; | |||
2516 | gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; | |||
2517 | ||||
2518 | for (i = 0; i < group_size; i++) | |||
2519 | grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( | |||
2520 | grouped_pipes[i]->stream_res.tg, &gsl_params); | |||
2521 | ||||
2522 | /* Reset slave controllers on master VSync */ | |||
2523 | DC_SYNC_INFO("GSL: enabling trigger-reset\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: enabling trigger-reset\n" ); } while (0); | |||
2524 | ||||
2525 | for (i = 1 /* skip the master */; i < group_size; i++) | |||
2526 | grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( | |||
2527 | grouped_pipes[i]->stream_res.tg, | |||
2528 | gsl_params.gsl_group); | |||
2529 | ||||
2530 | for (i = 1 /* skip the master */; i < group_size; i++) { | |||
2531 | DC_SYNC_INFO("GSL: waiting for reset to occur.\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: waiting for reset to occur.\n" ); } while (0); | |||
2532 | wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); | |||
2533 | grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( | |||
2534 | grouped_pipes[i]->stream_res.tg); | |||
2535 | } | |||
2536 | ||||
2537 | /* GSL Vblank synchronization is a one time sync mechanism, assumption | |||
2538 | * is that the sync'ed displays will not drift out of sync over time*/ | |||
2539 | DC_SYNC_INFO("GSL: Restoring register states.\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: Restoring register states.\n" ); } while (0); | |||
2540 | for (i = 0; i < group_size; i++) | |||
2541 | grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); | |||
2542 | ||||
2543 | DC_SYNC_INFO("GSL: Set-up complete.\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: Set-up complete.\n" ); } while (0); | |||
2544 | } | |||
2545 | ||||
2546 | static void dce110_enable_per_frame_crtc_position_reset( | |||
2547 | struct dc *dc, | |||
2548 | int group_size, | |||
2549 | struct pipe_ctx *grouped_pipes[]) | |||
2550 | { | |||
2551 | struct dc_context *dc_ctx = dc->ctx; | |||
2552 | struct dcp_gsl_params gsl_params = { 0 }; | |||
2553 | int i; | |||
2554 | ||||
2555 | gsl_params.gsl_group = 0; | |||
2556 | gsl_params.gsl_master = 0; | |||
2557 | ||||
2558 | for (i = 0; i < group_size; i++) | |||
2559 | grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( | |||
2560 | grouped_pipes[i]->stream_res.tg, &gsl_params); | |||
2561 | ||||
2562 | DC_SYNC_INFO("GSL: enabling trigger-reset\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: enabling trigger-reset\n" ); } while (0); | |||
2563 | ||||
2564 | for (i = 1; i < group_size; i++) | |||
2565 | grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( | |||
2566 | grouped_pipes[i]->stream_res.tg, | |||
2567 | gsl_params.gsl_master, | |||
2568 | &grouped_pipes[i]->stream->triggered_crtc_reset); | |||
2569 | ||||
2570 | DC_SYNC_INFO("GSL: waiting for reset to occur.\n")do { (void)(dc_ctx); ___drm_dbg(((void *)0), DRM_UT_KMS, "GSL: waiting for reset to occur.\n" ); } while (0); | |||
2571 | for (i = 1; i < group_size; i++) | |||
2572 | wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); | |||
2573 | ||||
2574 | for (i = 0; i < group_size; i++) | |||
2575 | grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); | |||
2576 | ||||
2577 | } | |||
2578 | ||||
2579 | static void init_pipes(struct dc *dc, struct dc_state *context) | |||
2580 | { | |||
2581 | // Do nothing | |||
2582 | } | |||
2583 | ||||
2584 | static void init_hw(struct dc *dc) | |||
2585 | { | |||
2586 | int i; | |||
2587 | struct dc_bios *bp; | |||
2588 | struct transform *xfm; | |||
2589 | struct abm *abm; | |||
2590 | struct dmcu *dmcu; | |||
2591 | struct dce_hwseq *hws = dc->hwseq; | |||
2592 | uint32_t backlight = MAX_BACKLIGHT_LEVEL0xFFFF; | |||
2593 | ||||
2594 | bp = dc->ctx->dc_bios; | |||
2595 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2596 | xfm = dc->res_pool->transforms[i]; | |||
2597 | xfm->funcs->transform_reset(xfm); | |||
2598 | ||||
2599 | hws->funcs.enable_display_power_gating( | |||
2600 | dc, i, bp, | |||
2601 | PIPE_GATING_CONTROL_INIT); | |||
2602 | hws->funcs.enable_display_power_gating( | |||
2603 | dc, i, bp, | |||
2604 | PIPE_GATING_CONTROL_DISABLE); | |||
2605 | hws->funcs.enable_display_pipe_clock_gating( | |||
2606 | dc->ctx, | |||
2607 | true1); | |||
2608 | } | |||
2609 | ||||
2610 | dce_clock_gating_power_up(dc->hwseq, false0); | |||
2611 | /***************************************/ | |||
2612 | ||||
2613 | for (i = 0; i < dc->link_count; i++) { | |||
2614 | /****************************************/ | |||
2615 | /* Power up AND update implementation according to the | |||
2616 | * required signal (which may be different from the | |||
2617 | * default signal on connector). */ | |||
2618 | struct dc_link *link = dc->links[i]; | |||
2619 | ||||
2620 | link->link_enc->funcs->hw_init(link->link_enc); | |||
2621 | } | |||
2622 | ||||
2623 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2624 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; | |||
2625 | ||||
2626 | tg->funcs->disable_vga(tg); | |||
2627 | ||||
2628 | /* Blank controller using driver code instead of | |||
2629 | * command table. */ | |||
2630 | tg->funcs->set_blank(tg, true1); | |||
2631 | hwss_wait_for_blank_complete(tg); | |||
2632 | } | |||
2633 | ||||
2634 | for (i = 0; i < dc->res_pool->audio_count; i++) { | |||
2635 | struct audio *audio = dc->res_pool->audios[i]; | |||
2636 | audio->funcs->hw_init(audio); | |||
2637 | } | |||
2638 | ||||
2639 | for (i = 0; i < dc->link_count; i++) { | |||
2640 | struct dc_link *link = dc->links[i]; | |||
2641 | ||||
2642 | if (link->panel_cntl) | |||
2643 | backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); | |||
2644 | } | |||
2645 | ||||
2646 | abm = dc->res_pool->abm; | |||
2647 | if (abm != NULL((void *)0)) | |||
2648 | abm->funcs->abm_init(abm, backlight); | |||
2649 | ||||
2650 | dmcu = dc->res_pool->dmcu; | |||
2651 | if (dmcu != NULL((void *)0) && abm != NULL((void *)0)) | |||
2652 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); | |||
2653 | ||||
2654 | if (dc->fbc_compressor) | |||
2655 | dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); | |||
2656 | ||||
2657 | } | |||
2658 | ||||
2659 | ||||
2660 | void dce110_prepare_bandwidth( | |||
2661 | struct dc *dc, | |||
2662 | struct dc_state *context) | |||
2663 | { | |||
2664 | struct clk_mgr *dccg = dc->clk_mgr; | |||
2665 | ||||
2666 | dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); | |||
2667 | ||||
2668 | dccg->funcs->update_clocks( | |||
2669 | dccg, | |||
2670 | context, | |||
2671 | false0); | |||
2672 | } | |||
2673 | ||||
2674 | void dce110_optimize_bandwidth( | |||
2675 | struct dc *dc, | |||
2676 | struct dc_state *context) | |||
2677 | { | |||
2678 | struct clk_mgr *dccg = dc->clk_mgr; | |||
2679 | ||||
2680 | dce110_set_displaymarks(dc, context); | |||
2681 | ||||
2682 | dccg->funcs->update_clocks( | |||
2683 | dccg, | |||
2684 | context, | |||
2685 | true1); | |||
2686 | } | |||
2687 | ||||
2688 | static void dce110_program_front_end_for_pipe( | |||
2689 | struct dc *dc, struct pipe_ctx *pipe_ctx) | |||
2690 | { | |||
2691 | struct mem_input *mi = pipe_ctx->plane_res.mi; | |||
2692 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; | |||
2693 | struct xfm_grph_csc_adjustment adjust; | |||
2694 | struct out_csc_color_matrix tbl_entry; | |||
2695 | unsigned int i; | |||
2696 | struct dce_hwseq *hws = dc->hwseq; | |||
2697 | ||||
2698 | DC_LOGGER_INIT(); | |||
2699 | memset(&tbl_entry, 0, sizeof(tbl_entry))__builtin_memset((&tbl_entry), (0), (sizeof(tbl_entry))); | |||
2700 | ||||
2701 | memset(&adjust, 0, sizeof(adjust))__builtin_memset((&adjust), (0), (sizeof(adjust))); | |||
2702 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; | |||
2703 | ||||
2704 | dce_enable_fe_clock(dc->hwseq, mi->inst, true1); | |||
2705 | ||||
2706 | set_default_colors(pipe_ctx); | |||
2707 | if (pipe_ctx->stream->csc_color_matrix.enable_adjustment | |||
2708 | == true1) { | |||
2709 | tbl_entry.color_space = | |||
2710 | pipe_ctx->stream->output_color_space; | |||
2711 | ||||
2712 | for (i = 0; i < 12; i++) | |||
2713 | tbl_entry.regval[i] = | |||
2714 | pipe_ctx->stream->csc_color_matrix.matrix[i]; | |||
2715 | ||||
2716 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment | |||
2717 | (pipe_ctx->plane_res.xfm, &tbl_entry); | |||
2718 | } | |||
2719 | ||||
2720 | if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true1) { | |||
2721 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; | |||
2722 | ||||
2723 | for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE12; i++) | |||
2724 | adjust.temperature_matrix[i] = | |||
2725 | pipe_ctx->stream->gamut_remap_matrix.matrix[i]; | |||
2726 | } | |||
2727 | ||||
2728 | pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); | |||
2729 | ||||
2730 | pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL((void *)0); | |||
2731 | ||||
2732 | program_scaler(dc, pipe_ctx); | |||
2733 | ||||
2734 | mi->funcs->mem_input_program_surface_config( | |||
2735 | mi, | |||
2736 | plane_state->format, | |||
2737 | &plane_state->tiling_info, | |||
2738 | &plane_state->plane_size, | |||
2739 | plane_state->rotation, | |||
2740 | NULL((void *)0), | |||
2741 | false0); | |||
2742 | if (mi->funcs->set_blank) | |||
2743 | mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); | |||
2744 | ||||
2745 | if (dc->config.gpu_vm_support) | |||
2746 | mi->funcs->mem_input_program_pte_vm( | |||
2747 | pipe_ctx->plane_res.mi, | |||
2748 | plane_state->format, | |||
2749 | &plane_state->tiling_info, | |||
2750 | plane_state->rotation); | |||
2751 | ||||
2752 | /* Moved programming gamma from dc to hwss */ | |||
2753 | if (pipe_ctx->plane_state->update_flags.bits.full_update || | |||
2754 | pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || | |||
2755 | pipe_ctx->plane_state->update_flags.bits.gamma_change) | |||
2756 | hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); | |||
2757 | ||||
2758 | if (pipe_ctx->plane_state->update_flags.bits.full_update) | |||
2759 | hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); | |||
2760 | ||||
2761 | DC_LOG_SURFACE(do { } while(0) | |||
2762 | "Pipe:%d %p: addr hi:0x%x, "do { } while(0) | |||
2763 | "addr low:0x%x, "do { } while(0) | |||
2764 | "src: %d, %d, %d,"do { } while(0) | |||
2765 | " %d; dst: %d, %d, %d, %d;"do { } while(0) | |||
2766 | "clip: %d, %d, %d, %d\n",do { } while(0) | |||
2767 | pipe_ctx->pipe_idx,do { } while(0) | |||
2768 | (void *) pipe_ctx->plane_state,do { } while(0) | |||
2769 | pipe_ctx->plane_state->address.grph.addr.high_part,do { } while(0) | |||
2770 | pipe_ctx->plane_state->address.grph.addr.low_part,do { } while(0) | |||
2771 | pipe_ctx->plane_state->src_rect.x,do { } while(0) | |||
2772 | pipe_ctx->plane_state->src_rect.y,do { } while(0) | |||
2773 | pipe_ctx->plane_state->src_rect.width,do { } while(0) | |||
2774 | pipe_ctx->plane_state->src_rect.height,do { } while(0) | |||
2775 | pipe_ctx->plane_state->dst_rect.x,do { } while(0) | |||
2776 | pipe_ctx->plane_state->dst_rect.y,do { } while(0) | |||
2777 | pipe_ctx->plane_state->dst_rect.width,do { } while(0) | |||
2778 | pipe_ctx->plane_state->dst_rect.height,do { } while(0) | |||
2779 | pipe_ctx->plane_state->clip_rect.x,do { } while(0) | |||
2780 | pipe_ctx->plane_state->clip_rect.y,do { } while(0) | |||
2781 | pipe_ctx->plane_state->clip_rect.width,do { } while(0) | |||
2782 | pipe_ctx->plane_state->clip_rect.height)do { } while(0); | |||
2783 | ||||
2784 | DC_LOG_SURFACE(do { } while(0) | |||
2785 | "Pipe %d: width, height, x, y\n"do { } while(0) | |||
2786 | "viewport:%d, %d, %d, %d\n"do { } while(0) | |||
2787 | "recout: %d, %d, %d, %d\n",do { } while(0) | |||
2788 | pipe_ctx->pipe_idx,do { } while(0) | |||
2789 | pipe_ctx->plane_res.scl_data.viewport.width,do { } while(0) | |||
2790 | pipe_ctx->plane_res.scl_data.viewport.height,do { } while(0) | |||
2791 | pipe_ctx->plane_res.scl_data.viewport.x,do { } while(0) | |||
2792 | pipe_ctx->plane_res.scl_data.viewport.y,do { } while(0) | |||
2793 | pipe_ctx->plane_res.scl_data.recout.width,do { } while(0) | |||
2794 | pipe_ctx->plane_res.scl_data.recout.height,do { } while(0) | |||
2795 | pipe_ctx->plane_res.scl_data.recout.x,do { } while(0) | |||
2796 | pipe_ctx->plane_res.scl_data.recout.y)do { } while(0); | |||
2797 | } | |||
2798 | ||||
2799 | static void dce110_apply_ctx_for_surface( | |||
2800 | struct dc *dc, | |||
2801 | const struct dc_stream_state *stream, | |||
2802 | int num_planes, | |||
2803 | struct dc_state *context) | |||
2804 | { | |||
2805 | int i; | |||
2806 | ||||
2807 | if (num_planes == 0) | |||
2808 | return; | |||
2809 | ||||
2810 | if (dc->fbc_compressor) | |||
2811 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); | |||
2812 | ||||
2813 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2814 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
2815 | ||||
2816 | if (pipe_ctx->stream != stream) | |||
2817 | continue; | |||
2818 | ||||
2819 | /* Need to allocate mem before program front end for Fiji */ | |||
2820 | pipe_ctx->plane_res.mi->funcs->allocate_mem_input( | |||
2821 | pipe_ctx->plane_res.mi, | |||
2822 | pipe_ctx->stream->timing.h_total, | |||
2823 | pipe_ctx->stream->timing.v_total, | |||
2824 | pipe_ctx->stream->timing.pix_clk_100hz / 10, | |||
2825 | context->stream_count); | |||
2826 | ||||
2827 | dce110_program_front_end_for_pipe(dc, pipe_ctx); | |||
2828 | ||||
2829 | dc->hwss.update_plane_addr(dc, pipe_ctx); | |||
2830 | ||||
2831 | program_surface_visibility(dc, pipe_ctx); | |||
2832 | ||||
2833 | } | |||
2834 | ||||
2835 | if (dc->fbc_compressor) | |||
2836 | enable_fbc(dc, context); | |||
2837 | } | |||
2838 | ||||
2839 | static void dce110_post_unlock_program_front_end( | |||
2840 | struct dc *dc, | |||
2841 | struct dc_state *context) | |||
2842 | { | |||
2843 | } | |||
2844 | ||||
2845 | static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) | |||
2846 | { | |||
2847 | struct dce_hwseq *hws = dc->hwseq; | |||
2848 | int fe_idx = pipe_ctx->plane_res.mi ? | |||
2849 | pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; | |||
2850 | ||||
2851 | /* Do not power down fe when stream is active on dce*/ | |||
2852 | if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) | |||
2853 | return; | |||
2854 | ||||
2855 | hws->funcs.enable_display_power_gating( | |||
2856 | dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); | |||
2857 | ||||
2858 | dc->res_pool->transforms[fe_idx]->funcs->transform_reset( | |||
2859 | dc->res_pool->transforms[fe_idx]); | |||
2860 | } | |||
2861 | ||||
2862 | static void dce110_wait_for_mpcc_disconnect( | |||
2863 | struct dc *dc, | |||
2864 | struct resource_pool *res_pool, | |||
2865 | struct pipe_ctx *pipe_ctx) | |||
2866 | { | |||
2867 | /* do nothing*/ | |||
2868 | } | |||
2869 | ||||
2870 | static void program_output_csc(struct dc *dc, | |||
2871 | struct pipe_ctx *pipe_ctx, | |||
2872 | enum dc_color_space colorspace, | |||
2873 | uint16_t *matrix, | |||
2874 | int opp_id) | |||
2875 | { | |||
2876 | int i; | |||
2877 | struct out_csc_color_matrix tbl_entry; | |||
2878 | ||||
2879 | if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true1) { | |||
2880 | enum dc_color_space color_space = pipe_ctx->stream->output_color_space; | |||
2881 | ||||
2882 | for (i = 0; i < 12; i++) | |||
2883 | tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; | |||
2884 | ||||
2885 | tbl_entry.color_space = color_space; | |||
2886 | ||||
2887 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( | |||
2888 | pipe_ctx->plane_res.xfm, &tbl_entry); | |||
2889 | } | |||
2890 | } | |||
2891 | ||||
2892 | static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) | |||
2893 | { | |||
2894 | struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; | |||
2895 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; | |||
2896 | struct mem_input *mi = pipe_ctx->plane_res.mi; | |||
2897 | struct dc_cursor_mi_param param = { | |||
2898 | .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, | |||
2899 | .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, | |||
2900 | .viewport = pipe_ctx->plane_res.scl_data.viewport, | |||
2901 | .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, | |||
2902 | .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, | |||
2903 | .rotation = pipe_ctx->plane_state->rotation, | |||
2904 | .mirror = pipe_ctx->plane_state->horizontal_mirror | |||
2905 | }; | |||
2906 | ||||
2907 | /** | |||
2908 | * If the cursor's source viewport is clipped then we need to | |||
2909 | * translate the cursor to appear in the correct position on | |||
2910 | * the screen. | |||
2911 | * | |||
2912 | * This translation isn't affected by scaling so it needs to be | |||
2913 | * done *after* we adjust the position for the scale factor. | |||
2914 | * | |||
2915 | * This is only done by opt-in for now since there are still | |||
2916 | * some usecases like tiled display that might enable the | |||
2917 | * cursor on both streams while expecting dc to clip it. | |||
2918 | */ | |||
2919 | if (pos_cpy.translate_by_source) { | |||
2920 | pos_cpy.x += pipe_ctx->plane_state->src_rect.x; | |||
2921 | pos_cpy.y += pipe_ctx->plane_state->src_rect.y; | |||
2922 | } | |||
2923 | ||||
2924 | if (pipe_ctx->plane_state->address.type | |||
2925 | == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | |||
2926 | pos_cpy.enable = false0; | |||
2927 | ||||
2928 | if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) | |||
2929 | pos_cpy.enable = false0; | |||
2930 | ||||
2931 | if (ipp->funcs->ipp_cursor_set_position) | |||
2932 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); | |||
2933 | if (mi->funcs->set_cursor_position) | |||
2934 | mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); | |||
2935 | } | |||
2936 | ||||
2937 | static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) | |||
2938 | { | |||
2939 | struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; | |||
2940 | ||||
2941 | if (pipe_ctx->plane_res.ipp && | |||
2942 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) | |||
2943 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( | |||
2944 | pipe_ctx->plane_res.ipp, attributes); | |||
2945 | ||||
2946 | if (pipe_ctx->plane_res.mi && | |||
2947 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) | |||
2948 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( | |||
2949 | pipe_ctx->plane_res.mi, attributes); | |||
2950 | ||||
2951 | if (pipe_ctx->plane_res.xfm && | |||
2952 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) | |||
2953 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( | |||
2954 | pipe_ctx->plane_res.xfm, attributes); | |||
2955 | } | |||
2956 | ||||
2957 | bool_Bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, | |||
2958 | uint32_t backlight_pwm_u16_16, | |||
2959 | uint32_t frame_ramp) | |||
2960 | { | |||
2961 | struct dc_link *link = pipe_ctx->stream->link; | |||
2962 | struct dc *dc = link->ctx->dc; | |||
2963 | struct abm *abm = pipe_ctx->stream_res.abm; | |||
2964 | struct panel_cntl *panel_cntl = link->panel_cntl; | |||
2965 | struct dmcu *dmcu = dc->res_pool->dmcu; | |||
2966 | bool_Bool fw_set_brightness = true1; | |||
2967 | /* DMCU -1 for all controller id values, | |||
2968 | * therefore +1 here | |||
2969 | */ | |||
2970 | uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; | |||
2971 | ||||
2972 | if (abm == NULL((void *)0) || panel_cntl == NULL((void *)0) || (abm->funcs->set_backlight_level_pwm == NULL((void *)0))) | |||
2973 | return false0; | |||
2974 | ||||
2975 | if (dmcu) | |||
2976 | fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); | |||
2977 | ||||
2978 | if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) | |||
2979 | panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); | |||
2980 | else | |||
2981 | abm->funcs->set_backlight_level_pwm( | |||
2982 | abm, | |||
2983 | backlight_pwm_u16_16, | |||
2984 | frame_ramp, | |||
2985 | controller_id, | |||
2986 | link->panel_cntl->inst); | |||
2987 | ||||
2988 | return true1; | |||
2989 | } | |||
2990 | ||||
2991 | void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) | |||
2992 | { | |||
2993 | struct abm *abm = pipe_ctx->stream_res.abm; | |||
2994 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; | |||
2995 | ||||
2996 | if (abm) | |||
2997 | abm->funcs->set_abm_immediate_disable(abm, | |||
2998 | pipe_ctx->stream->link->panel_cntl->inst); | |||
2999 | ||||
3000 | if (panel_cntl) | |||
3001 | panel_cntl->funcs->store_backlight_level(panel_cntl); | |||
3002 | } | |||
3003 | ||||
3004 | void dce110_set_pipe(struct pipe_ctx *pipe_ctx) | |||
3005 | { | |||
3006 | struct abm *abm = pipe_ctx->stream_res.abm; | |||
3007 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; | |||
3008 | uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; | |||
3009 | ||||
3010 | if (abm && panel_cntl) | |||
3011 | abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); | |||
3012 | } | |||
3013 | ||||
3014 | void dce110_enable_lvds_link_output(struct dc_link *link, | |||
3015 | const struct link_resource *link_res, | |||
3016 | enum clock_source_id clock_source, | |||
3017 | uint32_t pixel_clock) | |||
3018 | { | |||
3019 | link->link_enc->funcs->enable_lvds_output( | |||
3020 | link->link_enc, | |||
3021 | clock_source, | |||
3022 | pixel_clock); | |||
3023 | link->phy_state.symclk_state = SYMCLK_ON_TX_ON; | |||
3024 | } | |||
3025 | ||||
3026 | void dce110_enable_tmds_link_output(struct dc_link *link, | |||
3027 | const struct link_resource *link_res, | |||
3028 | enum amd_signal_type signal, | |||
3029 | enum clock_source_id clock_source, | |||
3030 | enum dc_color_depth color_depth, | |||
3031 | uint32_t pixel_clock) | |||
3032 | { | |||
3033 | link->link_enc->funcs->enable_tmds_output( | |||
3034 | link->link_enc, | |||
3035 | clock_source, | |||
3036 | color_depth, | |||
3037 | signal, | |||
3038 | pixel_clock); | |||
3039 | link->phy_state.symclk_state = SYMCLK_ON_TX_ON; | |||
3040 | } | |||
3041 | ||||
3042 | void dce110_enable_dp_link_output( | |||
3043 | struct dc_link *link, | |||
3044 | const struct link_resource *link_res, | |||
3045 | enum amd_signal_type signal, | |||
3046 | enum clock_source_id clock_source, | |||
3047 | const struct dc_link_settings *link_settings) | |||
3048 | { | |||
3049 | struct dc *dc = link->ctx->dc; | |||
3050 | struct dmcu *dmcu = dc->res_pool->dmcu; | |||
3051 | struct pipe_ctx *pipes = | |||
3052 | link->dc->current_state->res_ctx.pipe_ctx; | |||
3053 | struct clock_source *dp_cs = | |||
3054 | link->dc->res_pool->dp_clock_source; | |||
3055 | const struct link_hwss *link_hwss = get_link_hwss(link, link_res); | |||
3056 | unsigned int i; | |||
3057 | ||||
3058 | ||||
3059 | if (link->connector_signal == SIGNAL_TYPE_EDP) { | |||
3060 | if (!link->dc->config.edp_no_power_sequencing) | |||
3061 | link->dc->hwss.edp_power_control(link, true1); | |||
3062 | link->dc->hwss.edp_wait_for_hpd_ready(link, true1); | |||
3063 | } | |||
3064 | ||||
3065 | /* If the current pixel clock source is not DTO(happens after | |||
3066 | * switching from HDMI passive dongle to DP on the same connector), | |||
3067 | * switch the pixel clock source to DTO. | |||
3068 | */ | |||
3069 | ||||
3070 | for (i = 0; i < MAX_PIPES6; i++) { | |||
3071 | if (pipes[i].stream != NULL((void *)0) && | |||
3072 | pipes[i].stream->link == link) { | |||
3073 | if (pipes[i].clock_source != NULL((void *)0) && | |||
3074 | pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { | |||
3075 | pipes[i].clock_source = dp_cs; | |||
3076 | pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = | |||
3077 | pipes[i].stream->timing.pix_clk_100hz; | |||
3078 | pipes[i].clock_source->funcs->program_pix_clk( | |||
3079 | pipes[i].clock_source, | |||
3080 | &pipes[i].stream_res.pix_clk_params, | |||
3081 | dp_get_link_encoding_format(link_settings), | |||
3082 | &pipes[i].pll_settings); | |||
3083 | } | |||
3084 | } | |||
3085 | } | |||
3086 | ||||
3087 | if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) { | |||
3088 | if (dc->clk_mgr->funcs->notify_link_rate_change) | |||
3089 | dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); | |||
3090 | } | |||
3091 | ||||
3092 | if (dmcu != NULL((void *)0) && dmcu->funcs->lock_phy) | |||
3093 | dmcu->funcs->lock_phy(dmcu); | |||
3094 | ||||
3095 | if (link_hwss->ext.enable_dp_link_output) | |||
3096 | link_hwss->ext.enable_dp_link_output(link, link_res, signal, | |||
3097 | clock_source, link_settings); | |||
3098 | ||||
3099 | link->phy_state.symclk_state = SYMCLK_ON_TX_ON; | |||
3100 | ||||
3101 | if (dmcu != NULL((void *)0) && dmcu->funcs->unlock_phy) | |||
3102 | dmcu->funcs->unlock_phy(dmcu); | |||
3103 | ||||
3104 | dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY); | |||
3105 | } | |||
3106 | ||||
3107 | void dce110_disable_link_output(struct dc_link *link, | |||
3108 | const struct link_resource *link_res, | |||
3109 | enum amd_signal_type signal) | |||
3110 | { | |||
3111 | struct dc *dc = link->ctx->dc; | |||
3112 | const struct link_hwss *link_hwss = get_link_hwss(link, link_res); | |||
3113 | struct dmcu *dmcu = dc->res_pool->dmcu; | |||
3114 | ||||
3115 | if (signal == SIGNAL_TYPE_EDP && | |||
3116 | link->dc->hwss.edp_backlight_control) | |||
3117 | link->dc->hwss.edp_backlight_control(link, false0); | |||
3118 | else if (dmcu != NULL((void *)0) && dmcu->funcs->lock_phy) | |||
3119 | dmcu->funcs->lock_phy(dmcu); | |||
3120 | ||||
3121 | link_hwss->disable_link_output(link, link_res, signal); | |||
3122 | link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; | |||
3123 | ||||
3124 | if (signal == SIGNAL_TYPE_EDP && | |||
3125 | link->dc->hwss.edp_backlight_control) | |||
3126 | link->dc->hwss.edp_power_control(link, false0); | |||
3127 | else if (dmcu != NULL((void *)0) && dmcu->funcs->lock_phy) | |||
3128 | dmcu->funcs->unlock_phy(dmcu); | |||
3129 | dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); | |||
3130 | } | |||
3131 | ||||
3132 | static const struct hw_sequencer_funcs dce110_funcs = { | |||
3133 | .program_gamut_remap = program_gamut_remap, | |||
3134 | .program_output_csc = program_output_csc, | |||
3135 | .init_hw = init_hw, | |||
3136 | .apply_ctx_to_hw = dce110_apply_ctx_to_hw, | |||
3137 | .apply_ctx_for_surface = dce110_apply_ctx_for_surface, | |||
3138 | .post_unlock_program_front_end = dce110_post_unlock_program_front_end, | |||
3139 | .update_plane_addr = update_plane_addr, | |||
3140 | .update_pending_status = dce110_update_pending_status, | |||
3141 | .enable_accelerated_mode = dce110_enable_accelerated_mode, | |||
3142 | .enable_timing_synchronization = dce110_enable_timing_synchronization, | |||
3143 | .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, | |||
3144 | .update_info_frame = dce110_update_info_frame, | |||
3145 | .enable_stream = dce110_enable_stream, | |||
3146 | .disable_stream = dce110_disable_stream, | |||
3147 | .unblank_stream = dce110_unblank_stream, | |||
3148 | .blank_stream = dce110_blank_stream, | |||
3149 | .enable_audio_stream = dce110_enable_audio_stream, | |||
3150 | .disable_audio_stream = dce110_disable_audio_stream, | |||
3151 | .disable_plane = dce110_power_down_fe, | |||
3152 | .pipe_control_lock = dce_pipe_control_lock, | |||
3153 | .interdependent_update_lock = NULL((void *)0), | |||
3154 | .cursor_lock = dce_pipe_control_lock, | |||
3155 | .prepare_bandwidth = dce110_prepare_bandwidth, | |||
3156 | .optimize_bandwidth = dce110_optimize_bandwidth, | |||
3157 | .set_drr = set_drr, | |||
3158 | .get_position = get_position, | |||
3159 | .set_static_screen_control = set_static_screen_control, | |||
3160 | .setup_stereo = NULL((void *)0), | |||
3161 | .set_avmute = dce110_set_avmute, | |||
3162 | .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, | |||
3163 | .edp_backlight_control = dce110_edp_backlight_control, | |||
3164 | .edp_power_control = dce110_edp_power_control, | |||
3165 | .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, | |||
3166 | .set_cursor_position = dce110_set_cursor_position, | |||
3167 | .set_cursor_attribute = dce110_set_cursor_attribute, | |||
3168 | .set_backlight_level = dce110_set_backlight_level, | |||
3169 | .set_abm_immediate_disable = dce110_set_abm_immediate_disable, | |||
3170 | .set_pipe = dce110_set_pipe, | |||
3171 | .enable_lvds_link_output = dce110_enable_lvds_link_output, | |||
3172 | .enable_tmds_link_output = dce110_enable_tmds_link_output, | |||
3173 | .enable_dp_link_output = dce110_enable_dp_link_output, | |||
3174 | .disable_link_output = dce110_disable_link_output, | |||
3175 | }; | |||
3176 | ||||
3177 | static const struct hwseq_private_funcs dce110_private_funcs = { | |||
3178 | .init_pipes = init_pipes, | |||
3179 | .update_plane_addr = update_plane_addr, | |||
3180 | .set_input_transfer_func = dce110_set_input_transfer_func, | |||
3181 | .set_output_transfer_func = dce110_set_output_transfer_func, | |||
3182 | .power_down = dce110_power_down, | |||
3183 | .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, | |||
3184 | .enable_display_power_gating = dce110_enable_display_power_gating, | |||
3185 | .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, | |||
3186 | .enable_stream_timing = dce110_enable_stream_timing, | |||
3187 | .disable_stream_gating = NULL((void *)0), | |||
3188 | .enable_stream_gating = NULL((void *)0), | |||
3189 | .edp_backlight_control = dce110_edp_backlight_control, | |||
3190 | }; | |||
3191 | ||||
3192 | void dce110_hw_sequencer_construct(struct dc *dc) | |||
3193 | { | |||
3194 | dc->hwss = dce110_funcs; | |||
3195 | dc->hwseq->funcs = dce110_private_funcs; | |||
3196 | } | |||
3197 |