| File: | dev/pci/drm/radeon/radeon_cs.c |
| Warning: | line 169, column 4 Value stored to 'need_mmap_lock' is never read |
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| 1 | /* |
| 2 | * Copyright 2008 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Jerome Glisse <glisse@freedesktop.org> |
| 26 | */ |
| 27 | |
| 28 | #include <linux/list_sort.h> |
| 29 | #include <linux/pci.h> |
| 30 | #include <linux/uaccess.h> |
| 31 | |
| 32 | #include <drm/drm_device.h> |
| 33 | #include <drm/drm_file.h> |
| 34 | #include <drm/radeon_drm.h> |
| 35 | |
| 36 | #include "radeon.h" |
| 37 | #include "radeon_reg.h" |
| 38 | #include "radeon_trace.h" |
| 39 | |
| 40 | #define RADEON_CS_MAX_PRIORITY32u 32u |
| 41 | #define RADEON_CS_NUM_BUCKETS(32u + 1) (RADEON_CS_MAX_PRIORITY32u + 1) |
| 42 | |
| 43 | /* This is based on the bucket sort with O(n) time complexity. |
| 44 | * An item with priority "i" is added to bucket[i]. The lists are then |
| 45 | * concatenated in descending order. |
| 46 | */ |
| 47 | struct radeon_cs_buckets { |
| 48 | struct list_head bucket[RADEON_CS_NUM_BUCKETS(32u + 1)]; |
| 49 | }; |
| 50 | |
| 51 | static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) |
| 52 | { |
| 53 | unsigned i; |
| 54 | |
| 55 | for (i = 0; i < RADEON_CS_NUM_BUCKETS(32u + 1); i++) |
| 56 | INIT_LIST_HEAD(&b->bucket[i]); |
| 57 | } |
| 58 | |
| 59 | static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, |
| 60 | struct list_head *item, unsigned priority) |
| 61 | { |
| 62 | /* Since buffers which appear sooner in the relocation list are |
| 63 | * likely to be used more often than buffers which appear later |
| 64 | * in the list, the sort mustn't change the ordering of buffers |
| 65 | * with the same priority, i.e. it must be stable. |
| 66 | */ |
| 67 | list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)(((priority)<(32u))?(priority):(32u))]); |
| 68 | } |
| 69 | |
| 70 | static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, |
| 71 | struct list_head *out_list) |
| 72 | { |
| 73 | unsigned i; |
| 74 | |
| 75 | /* Connect the sorted buckets in the output list. */ |
| 76 | for (i = 0; i < RADEON_CS_NUM_BUCKETS(32u + 1); i++) { |
| 77 | list_splice(&b->bucket[i], out_list); |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
| 82 | { |
| 83 | struct radeon_cs_chunk *chunk; |
| 84 | struct radeon_cs_buckets buckets; |
| 85 | unsigned i; |
| 86 | bool_Bool need_mmap_lock = false0; |
| 87 | int r; |
| 88 | |
| 89 | if (p->chunk_relocs == NULL((void *)0)) { |
| 90 | return 0; |
| 91 | } |
| 92 | chunk = p->chunk_relocs; |
| 93 | p->dma_reloc_idx = 0; |
| 94 | /* FIXME: we assume that each relocs use 4 dwords */ |
| 95 | p->nrelocs = chunk->length_dw / 4; |
| 96 | p->relocs = kvcalloc(p->nrelocs, sizeof(struct radeon_bo_list), |
| 97 | GFP_KERNEL(0x0001 | 0x0004)); |
| 98 | if (p->relocs == NULL((void *)0)) { |
| 99 | return -ENOMEM12; |
| 100 | } |
| 101 | |
| 102 | radeon_cs_buckets_init(&buckets); |
| 103 | |
| 104 | for (i = 0; i < p->nrelocs; i++) { |
| 105 | struct drm_radeon_cs_reloc *r; |
| 106 | struct drm_gem_object *gobj; |
| 107 | unsigned priority; |
| 108 | |
| 109 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; |
| 110 | gobj = drm_gem_object_lookup(p->filp, r->handle); |
| 111 | if (gobj == NULL((void *)0)) { |
| 112 | DRM_ERROR("gem object lookup failed 0x%x\n",__drm_err("gem object lookup failed 0x%x\n", r->handle) |
| 113 | r->handle)__drm_err("gem object lookup failed 0x%x\n", r->handle); |
| 114 | return -ENOENT2; |
| 115 | } |
| 116 | p->relocs[i].robj = gem_to_radeon_bo(gobj)({ const __typeof( ((struct radeon_bo *)0)->tbo.base ) *__mptr = ((gobj)); (struct radeon_bo *)( (char *)__mptr - __builtin_offsetof (struct radeon_bo, tbo.base) );}); |
| 117 | |
| 118 | /* The userspace buffer priorities are from 0 to 15. A higher |
| 119 | * number means the buffer is more important. |
| 120 | * Also, the buffers used for write have a higher priority than |
| 121 | * the buffers used for read only, which doubles the range |
| 122 | * to 0 to 31. 32 is reserved for the kernel driver. |
| 123 | */ |
| 124 | priority = (r->flags & RADEON_RELOC_PRIO_MASK(0xf << 0)) * 2 |
| 125 | + !!r->write_domain; |
| 126 | |
| 127 | /* The first reloc of an UVD job is the msg and that must be in |
| 128 | * VRAM, the second reloc is the DPB and for WMV that must be in |
| 129 | * VRAM as well. Also put everything into VRAM on AGP cards and older |
| 130 | * IGP chips to avoid image corruptions |
| 131 | */ |
| 132 | if (p->ring == R600_RING_TYPE_UVD_INDEX5 && |
| 133 | (i <= 0 || (p->rdev->flags & RADEON_IS_AGP) || |
| 134 | p->rdev->family == CHIP_RS780 || |
| 135 | p->rdev->family == CHIP_RS880)) { |
| 136 | |
| 137 | /* TODO: is this still needed for NI+ ? */ |
| 138 | p->relocs[i].preferred_domains = |
| 139 | RADEON_GEM_DOMAIN_VRAM0x4; |
| 140 | |
| 141 | p->relocs[i].allowed_domains = |
| 142 | RADEON_GEM_DOMAIN_VRAM0x4; |
| 143 | |
| 144 | /* prioritize this over any other relocation */ |
| 145 | priority = RADEON_CS_MAX_PRIORITY32u; |
| 146 | } else { |
| 147 | uint32_t domain = r->write_domain ? |
| 148 | r->write_domain : r->read_domains; |
| 149 | |
| 150 | if (domain & RADEON_GEM_DOMAIN_CPU0x1) { |
| 151 | DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "__drm_err("RADEON_GEM_DOMAIN_CPU is not valid " "for command submission\n" ) |
| 152 | "for command submission\n")__drm_err("RADEON_GEM_DOMAIN_CPU is not valid " "for command submission\n" ); |
| 153 | return -EINVAL22; |
| 154 | } |
| 155 | |
| 156 | p->relocs[i].preferred_domains = domain; |
| 157 | if (domain == RADEON_GEM_DOMAIN_VRAM0x4) |
| 158 | domain |= RADEON_GEM_DOMAIN_GTT0x2; |
| 159 | p->relocs[i].allowed_domains = domain; |
| 160 | } |
| 161 | |
| 162 | if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) { |
| 163 | uint32_t domain = p->relocs[i].preferred_domains; |
| 164 | if (!(domain & RADEON_GEM_DOMAIN_GTT0x2)) { |
| 165 | DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "__drm_err("Only RADEON_GEM_DOMAIN_GTT is " "allowed for userptr BOs\n" ) |
| 166 | "allowed for userptr BOs\n")__drm_err("Only RADEON_GEM_DOMAIN_GTT is " "allowed for userptr BOs\n" ); |
| 167 | return -EINVAL22; |
| 168 | } |
| 169 | need_mmap_lock = true1; |
Value stored to 'need_mmap_lock' is never read | |
| 170 | domain = RADEON_GEM_DOMAIN_GTT0x2; |
| 171 | p->relocs[i].preferred_domains = domain; |
| 172 | p->relocs[i].allowed_domains = domain; |
| 173 | } |
| 174 | |
| 175 | /* Objects shared as dma-bufs cannot be moved to VRAM */ |
| 176 | if (p->relocs[i].robj->prime_shared_count) { |
| 177 | p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM0x4; |
| 178 | if (!p->relocs[i].allowed_domains) { |
| 179 | DRM_ERROR("BO associated with dma-buf cannot "__drm_err("BO associated with dma-buf cannot " "be moved to VRAM\n" ) |
| 180 | "be moved to VRAM\n")__drm_err("BO associated with dma-buf cannot " "be moved to VRAM\n" ); |
| 181 | return -EINVAL22; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; |
| 186 | p->relocs[i].tv.num_shared = !r->write_domain; |
| 187 | |
| 188 | radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, |
| 189 | priority); |
| 190 | } |
| 191 | |
| 192 | radeon_cs_buckets_get_list(&buckets, &p->validated); |
| 193 | |
| 194 | if (p->cs_flags & RADEON_CS_USE_VM0x02) |
| 195 | p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, |
| 196 | &p->validated); |
| 197 | #ifdef notyet |
| 198 | if (need_mmap_lock) |
| 199 | mmap_read_lock(current->mm); |
| 200 | #endif |
| 201 | |
| 202 | r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); |
| 203 | |
| 204 | #ifdef notyet |
| 205 | if (need_mmap_lock) |
| 206 | mmap_read_unlock(current->mm); |
| 207 | #endif |
| 208 | |
| 209 | return r; |
| 210 | } |
| 211 | |
| 212 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
| 213 | { |
| 214 | p->priority = priority; |
| 215 | |
| 216 | switch (ring) { |
| 217 | default: |
| 218 | DRM_ERROR("unknown ring id: %d\n", ring)__drm_err("unknown ring id: %d\n", ring); |
| 219 | return -EINVAL22; |
| 220 | case RADEON_CS_RING_GFX0: |
| 221 | p->ring = RADEON_RING_TYPE_GFX_INDEX0; |
| 222 | break; |
| 223 | case RADEON_CS_RING_COMPUTE1: |
| 224 | if (p->rdev->family >= CHIP_TAHITI) { |
| 225 | if (p->priority > 0) |
| 226 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX1; |
| 227 | else |
| 228 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX2; |
| 229 | } else |
| 230 | p->ring = RADEON_RING_TYPE_GFX_INDEX0; |
| 231 | break; |
| 232 | case RADEON_CS_RING_DMA2: |
| 233 | if (p->rdev->family >= CHIP_CAYMAN) { |
| 234 | if (p->priority > 0) |
| 235 | p->ring = R600_RING_TYPE_DMA_INDEX3; |
| 236 | else |
| 237 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX4; |
| 238 | } else if (p->rdev->family >= CHIP_RV770) { |
| 239 | p->ring = R600_RING_TYPE_DMA_INDEX3; |
| 240 | } else { |
| 241 | return -EINVAL22; |
| 242 | } |
| 243 | break; |
| 244 | case RADEON_CS_RING_UVD3: |
| 245 | p->ring = R600_RING_TYPE_UVD_INDEX5; |
| 246 | break; |
| 247 | case RADEON_CS_RING_VCE4: |
| 248 | /* TODO: only use the low priority ring for now */ |
| 249 | p->ring = TN_RING_TYPE_VCE1_INDEX6; |
| 250 | break; |
| 251 | } |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | static int radeon_cs_sync_rings(struct radeon_cs_parser *p) |
| 256 | { |
| 257 | struct radeon_bo_list *reloc; |
| 258 | int r; |
| 259 | |
| 260 | list_for_each_entry(reloc, &p->validated, tv.head)for (reloc = ({ const __typeof( ((__typeof(*reloc) *)0)->tv .head ) *__mptr = ((&p->validated)->next); (__typeof (*reloc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*reloc ), tv.head) );}); &reloc->tv.head != (&p->validated ); reloc = ({ const __typeof( ((__typeof(*reloc) *)0)->tv. head ) *__mptr = (reloc->tv.head.next); (__typeof(*reloc) * )( (char *)__mptr - __builtin_offsetof(__typeof(*reloc), tv.head ) );})) { |
| 261 | struct dma_resv *resv; |
| 262 | |
| 263 | resv = reloc->robj->tbo.base.resv; |
| 264 | r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, |
| 265 | reloc->tv.num_shared); |
| 266 | if (r) |
| 267 | return r; |
| 268 | } |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
| 273 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
| 274 | { |
| 275 | struct drm_radeon_cs *cs = data; |
| 276 | uint64_t *chunk_array_ptr; |
| 277 | u64 size; |
| 278 | unsigned i; |
| 279 | u32 ring = RADEON_CS_RING_GFX0; |
| 280 | s32 priority = 0; |
| 281 | |
| 282 | INIT_LIST_HEAD(&p->validated); |
| 283 | |
| 284 | if (!cs->num_chunks) { |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | /* get chunks */ |
| 289 | p->idx = 0; |
| 290 | p->ib.sa_bo = NULL((void *)0); |
| 291 | p->const_ib.sa_bo = NULL((void *)0); |
| 292 | p->chunk_ib = NULL((void *)0); |
| 293 | p->chunk_relocs = NULL((void *)0); |
| 294 | p->chunk_flags = NULL((void *)0); |
| 295 | p->chunk_const_ib = NULL((void *)0); |
| 296 | p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL(0x0001 | 0x0004)); |
| 297 | if (p->chunks_array == NULL((void *)0)) { |
| 298 | return -ENOMEM12; |
| 299 | } |
| 300 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); |
| 301 | if (copy_from_user(p->chunks_array, chunk_array_ptr, |
| 302 | sizeof(uint64_t)*cs->num_chunks)) { |
| 303 | return -EFAULT14; |
| 304 | } |
| 305 | p->cs_flags = 0; |
| 306 | p->nchunks = cs->num_chunks; |
| 307 | p->chunks = kvcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL(0x0001 | 0x0004)); |
| 308 | if (p->chunks == NULL((void *)0)) { |
| 309 | return -ENOMEM12; |
| 310 | } |
| 311 | for (i = 0; i < p->nchunks; i++) { |
| 312 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL((void *)0); |
| 313 | struct drm_radeon_cs_chunk user_chunk; |
| 314 | uint32_t __user *cdata; |
| 315 | |
| 316 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; |
| 317 | if (copy_from_user(&user_chunk, chunk_ptr, |
| 318 | sizeof(struct drm_radeon_cs_chunk))) { |
| 319 | return -EFAULT14; |
| 320 | } |
| 321 | p->chunks[i].length_dw = user_chunk.length_dw; |
| 322 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS0x01) { |
| 323 | p->chunk_relocs = &p->chunks[i]; |
| 324 | } |
| 325 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB0x02) { |
| 326 | p->chunk_ib = &p->chunks[i]; |
| 327 | /* zero length IB isn't useful */ |
| 328 | if (p->chunks[i].length_dw == 0) |
| 329 | return -EINVAL22; |
| 330 | } |
| 331 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB0x04) { |
| 332 | p->chunk_const_ib = &p->chunks[i]; |
| 333 | /* zero length CONST IB isn't useful */ |
| 334 | if (p->chunks[i].length_dw == 0) |
| 335 | return -EINVAL22; |
| 336 | } |
| 337 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS0x03) { |
| 338 | p->chunk_flags = &p->chunks[i]; |
| 339 | /* zero length flags aren't useful */ |
| 340 | if (p->chunks[i].length_dw == 0) |
| 341 | return -EINVAL22; |
| 342 | } |
| 343 | |
| 344 | size = p->chunks[i].length_dw; |
| 345 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
| 346 | p->chunks[i].user_ptr = cdata; |
| 347 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB0x04) |
| 348 | continue; |
| 349 | |
| 350 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB0x02) { |
| 351 | if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) |
| 352 | continue; |
| 353 | } |
| 354 | |
| 355 | p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL(0x0001 | 0x0004)); |
| 356 | size *= sizeof(uint32_t); |
| 357 | if (p->chunks[i].kdata == NULL((void *)0)) { |
| 358 | return -ENOMEM12; |
| 359 | } |
| 360 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { |
| 361 | return -EFAULT14; |
| 362 | } |
| 363 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS0x03) { |
| 364 | p->cs_flags = p->chunks[i].kdata[0]; |
| 365 | if (p->chunks[i].length_dw > 1) |
| 366 | ring = p->chunks[i].kdata[1]; |
| 367 | if (p->chunks[i].length_dw > 2) |
| 368 | priority = (s32)p->chunks[i].kdata[2]; |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | /* these are KMS only */ |
| 373 | if (p->rdev) { |
| 374 | if ((p->cs_flags & RADEON_CS_USE_VM0x02) && |
| 375 | !p->rdev->vm_manager.enabled) { |
| 376 | DRM_ERROR("VM not active on asic!\n")__drm_err("VM not active on asic!\n"); |
| 377 | return -EINVAL22; |
| 378 | } |
| 379 | |
| 380 | if (radeon_cs_get_ring(p, ring, priority)) |
| 381 | return -EINVAL22; |
| 382 | |
| 383 | /* we only support VM on some SI+ rings */ |
| 384 | if ((p->cs_flags & RADEON_CS_USE_VM0x02) == 0) { |
| 385 | if (p->rdev->asic->ring[p->ring]->cs_parse == NULL((void *)0)) { |
| 386 | DRM_ERROR("Ring %d requires VM!\n", p->ring)__drm_err("Ring %d requires VM!\n", p->ring); |
| 387 | return -EINVAL22; |
| 388 | } |
| 389 | } else { |
| 390 | if (p->rdev->asic->ring[p->ring]->ib_parse == NULL((void *)0)) { |
| 391 | DRM_ERROR("VM not supported on ring %d!\n",__drm_err("VM not supported on ring %d!\n", p->ring) |
| 392 | p->ring)__drm_err("VM not supported on ring %d!\n", p->ring); |
| 393 | return -EINVAL22; |
| 394 | } |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | static int cmp_size_smaller_first(void *priv, const struct list_head *a, |
| 402 | const struct list_head *b) |
| 403 | { |
| 404 | struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head)({ const __typeof( ((struct radeon_bo_list *)0)->tv.head ) *__mptr = (a); (struct radeon_bo_list *)( (char *)__mptr - __builtin_offsetof (struct radeon_bo_list, tv.head) );}); |
| 405 | struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head)({ const __typeof( ((struct radeon_bo_list *)0)->tv.head ) *__mptr = (b); (struct radeon_bo_list *)( (char *)__mptr - __builtin_offsetof (struct radeon_bo_list, tv.head) );}); |
| 406 | |
| 407 | /* Sort A before B if A is smaller. */ |
| 408 | return (int)la->robj->tbo.resource->num_pages - |
| 409 | (int)lb->robj->tbo.resource->num_pages; |
| 410 | } |
| 411 | |
| 412 | /** |
| 413 | * radeon_cs_parser_fini() - clean parser states |
| 414 | * @parser: parser structure holding parsing context. |
| 415 | * @error: error number |
| 416 | * @backoff: indicator to backoff the reservation |
| 417 | * |
| 418 | * If error is set than unvalidate buffer, otherwise just free memory |
| 419 | * used by parsing context. |
| 420 | **/ |
| 421 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool_Bool backoff) |
| 422 | { |
| 423 | unsigned i; |
| 424 | |
| 425 | if (!error) { |
| 426 | /* Sort the buffer list from the smallest to largest buffer, |
| 427 | * which affects the order of buffers in the LRU list. |
| 428 | * This assures that the smallest buffers are added first |
| 429 | * to the LRU list, so they are likely to be later evicted |
| 430 | * first, instead of large buffers whose eviction is more |
| 431 | * expensive. |
| 432 | * |
| 433 | * This slightly lowers the number of bytes moved by TTM |
| 434 | * per frame under memory pressure. |
| 435 | */ |
| 436 | list_sort(NULL((void *)0), &parser->validated, cmp_size_smaller_first); |
| 437 | |
| 438 | ttm_eu_fence_buffer_objects(&parser->ticket, |
| 439 | &parser->validated, |
| 440 | &parser->ib.fence->base); |
| 441 | } else if (backoff) { |
| 442 | ttm_eu_backoff_reservation(&parser->ticket, |
| 443 | &parser->validated); |
| 444 | } |
| 445 | |
| 446 | if (parser->relocs != NULL((void *)0)) { |
| 447 | for (i = 0; i < parser->nrelocs; i++) { |
| 448 | struct radeon_bo *bo = parser->relocs[i].robj; |
| 449 | if (bo == NULL((void *)0)) |
| 450 | continue; |
| 451 | |
| 452 | drm_gem_object_put(&bo->tbo.base); |
| 453 | } |
| 454 | } |
| 455 | kfree(parser->track); |
| 456 | kvfree(parser->relocs); |
| 457 | kvfree(parser->vm_bos); |
| 458 | for (i = 0; i < parser->nchunks; i++) |
| 459 | kvfree(parser->chunks[i].kdata); |
| 460 | kvfree(parser->chunks); |
| 461 | kvfree(parser->chunks_array); |
| 462 | radeon_ib_free(parser->rdev, &parser->ib); |
| 463 | radeon_ib_free(parser->rdev, &parser->const_ib); |
| 464 | } |
| 465 | |
| 466 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
| 467 | struct radeon_cs_parser *parser) |
| 468 | { |
| 469 | int r; |
| 470 | |
| 471 | if (parser->chunk_ib == NULL((void *)0)) |
| 472 | return 0; |
| 473 | |
| 474 | if (parser->cs_flags & RADEON_CS_USE_VM0x02) |
| 475 | return 0; |
| 476 | |
| 477 | r = radeon_cs_parse(rdev, parser->ring, parser)(rdev)->asic->ring[(parser->ring)]->cs_parse((parser )); |
| 478 | if (r || parser->parser_error) { |
| 479 | DRM_ERROR("Invalid command stream !\n")__drm_err("Invalid command stream !\n"); |
| 480 | return r; |
| 481 | } |
| 482 | |
| 483 | r = radeon_cs_sync_rings(parser); |
| 484 | if (r) { |
| 485 | if (r != -ERESTARTSYS4) |
| 486 | DRM_ERROR("Failed to sync rings: %i\n", r)__drm_err("Failed to sync rings: %i\n", r); |
| 487 | return r; |
| 488 | } |
| 489 | |
| 490 | if (parser->ring == R600_RING_TYPE_UVD_INDEX5) |
| 491 | radeon_uvd_note_usage(rdev); |
| 492 | else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX6) || |
| 493 | (parser->ring == TN_RING_TYPE_VCE2_INDEX7)) |
| 494 | radeon_vce_note_usage(rdev); |
| 495 | |
| 496 | r = radeon_ib_schedule(rdev, &parser->ib, NULL((void *)0), true1); |
| 497 | if (r) { |
| 498 | DRM_ERROR("Failed to schedule IB !\n")__drm_err("Failed to schedule IB !\n"); |
| 499 | } |
| 500 | return r; |
| 501 | } |
| 502 | |
| 503 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, |
| 504 | struct radeon_vm *vm) |
| 505 | { |
| 506 | struct radeon_device *rdev = p->rdev; |
| 507 | struct radeon_bo_va *bo_va; |
| 508 | int i, r; |
| 509 | |
| 510 | r = radeon_vm_update_page_directory(rdev, vm); |
| 511 | if (r) |
| 512 | return r; |
| 513 | |
| 514 | r = radeon_vm_clear_freed(rdev, vm); |
| 515 | if (r) |
| 516 | return r; |
| 517 | |
| 518 | if (vm->ib_bo_va == NULL((void *)0)) { |
| 519 | DRM_ERROR("Tmp BO not in VM!\n")__drm_err("Tmp BO not in VM!\n"); |
| 520 | return -EINVAL22; |
| 521 | } |
| 522 | |
| 523 | r = radeon_vm_bo_update(rdev, vm->ib_bo_va, |
| 524 | rdev->ring_tmp_bo.bo->tbo.resource); |
| 525 | if (r) |
| 526 | return r; |
| 527 | |
| 528 | for (i = 0; i < p->nrelocs; i++) { |
| 529 | struct radeon_bo *bo; |
| 530 | |
| 531 | bo = p->relocs[i].robj; |
| 532 | bo_va = radeon_vm_bo_find(vm, bo); |
| 533 | if (bo_va == NULL((void *)0)) { |
| 534 | dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm)printf("drm:pid%d:%s *ERROR* " "bo %p not in vm %p\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , bo, vm); |
| 535 | return -EINVAL22; |
| 536 | } |
| 537 | |
| 538 | r = radeon_vm_bo_update(rdev, bo_va, bo->tbo.resource); |
| 539 | if (r) |
| 540 | return r; |
| 541 | |
| 542 | radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update); |
| 543 | |
| 544 | r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); |
| 545 | if (r) |
| 546 | return r; |
| 547 | } |
| 548 | |
| 549 | return radeon_vm_clear_invalids(rdev, vm); |
| 550 | } |
| 551 | |
| 552 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, |
| 553 | struct radeon_cs_parser *parser) |
| 554 | { |
| 555 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
| 556 | struct radeon_vm *vm = &fpriv->vm; |
| 557 | int r; |
| 558 | |
| 559 | if (parser->chunk_ib == NULL((void *)0)) |
| 560 | return 0; |
| 561 | if ((parser->cs_flags & RADEON_CS_USE_VM0x02) == 0) |
| 562 | return 0; |
| 563 | |
| 564 | if (parser->const_ib.length_dw) { |
| 565 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib)(rdev)->asic->ring[(parser->ring)]->ib_parse((rdev ), (&parser->const_ib)); |
| 566 | if (r) { |
| 567 | return r; |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib)(rdev)->asic->ring[(parser->ring)]->ib_parse((rdev ), (&parser->ib)); |
| 572 | if (r) { |
| 573 | return r; |
| 574 | } |
| 575 | |
| 576 | if (parser->ring == R600_RING_TYPE_UVD_INDEX5) |
| 577 | radeon_uvd_note_usage(rdev); |
| 578 | |
| 579 | mutex_lock(&vm->mutex)rw_enter_write(&vm->mutex); |
| 580 | r = radeon_bo_vm_update_pte(parser, vm); |
| 581 | if (r) { |
| 582 | goto out; |
| 583 | } |
| 584 | |
| 585 | r = radeon_cs_sync_rings(parser); |
| 586 | if (r) { |
| 587 | if (r != -ERESTARTSYS4) |
| 588 | DRM_ERROR("Failed to sync rings: %i\n", r)__drm_err("Failed to sync rings: %i\n", r); |
| 589 | goto out; |
| 590 | } |
| 591 | |
| 592 | if ((rdev->family >= CHIP_TAHITI) && |
| 593 | (parser->chunk_const_ib != NULL((void *)0))) { |
| 594 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true1); |
| 595 | } else { |
| 596 | r = radeon_ib_schedule(rdev, &parser->ib, NULL((void *)0), true1); |
| 597 | } |
| 598 | |
| 599 | out: |
| 600 | mutex_unlock(&vm->mutex)rw_exit_write(&vm->mutex); |
| 601 | return r; |
| 602 | } |
| 603 | |
| 604 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
| 605 | { |
| 606 | if (r == -EDEADLK11) { |
| 607 | r = radeon_gpu_reset(rdev); |
| 608 | if (!r) |
| 609 | r = -EAGAIN35; |
| 610 | } |
| 611 | return r; |
| 612 | } |
| 613 | |
| 614 | static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) |
| 615 | { |
| 616 | struct radeon_cs_chunk *ib_chunk; |
| 617 | struct radeon_vm *vm = NULL((void *)0); |
| 618 | int r; |
| 619 | |
| 620 | if (parser->chunk_ib == NULL((void *)0)) |
| 621 | return 0; |
| 622 | |
| 623 | if (parser->cs_flags & RADEON_CS_USE_VM0x02) { |
| 624 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
| 625 | vm = &fpriv->vm; |
| 626 | |
| 627 | if ((rdev->family >= CHIP_TAHITI) && |
| 628 | (parser->chunk_const_ib != NULL((void *)0))) { |
| 629 | ib_chunk = parser->chunk_const_ib; |
| 630 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE(64 << 10)) { |
| 631 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw)__drm_err("cs IB CONST too big: %d\n", ib_chunk->length_dw ); |
| 632 | return -EINVAL22; |
| 633 | } |
| 634 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, |
| 635 | vm, ib_chunk->length_dw * 4); |
| 636 | if (r) { |
| 637 | DRM_ERROR("Failed to get const ib !\n")__drm_err("Failed to get const ib !\n"); |
| 638 | return r; |
| 639 | } |
| 640 | parser->const_ib.is_const_ib = true1; |
| 641 | parser->const_ib.length_dw = ib_chunk->length_dw; |
| 642 | if (copy_from_user(parser->const_ib.ptr, |
| 643 | ib_chunk->user_ptr, |
| 644 | ib_chunk->length_dw * 4)) |
| 645 | return -EFAULT14; |
| 646 | } |
| 647 | |
| 648 | ib_chunk = parser->chunk_ib; |
| 649 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE(64 << 10)) { |
| 650 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw)__drm_err("cs IB too big: %d\n", ib_chunk->length_dw); |
| 651 | return -EINVAL22; |
| 652 | } |
| 653 | } |
| 654 | ib_chunk = parser->chunk_ib; |
| 655 | |
| 656 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, |
| 657 | vm, ib_chunk->length_dw * 4); |
| 658 | if (r) { |
| 659 | DRM_ERROR("Failed to get ib !\n")__drm_err("Failed to get ib !\n"); |
| 660 | return r; |
| 661 | } |
| 662 | parser->ib.length_dw = ib_chunk->length_dw; |
| 663 | if (ib_chunk->kdata) |
| 664 | memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4)__builtin_memcpy((parser->ib.ptr), (ib_chunk->kdata), ( ib_chunk->length_dw * 4)); |
| 665 | else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) |
| 666 | return -EFAULT14; |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
| 671 | { |
| 672 | struct radeon_device *rdev = dev->dev_private; |
| 673 | struct radeon_cs_parser parser; |
| 674 | int r; |
| 675 | |
| 676 | down_read(&rdev->exclusive_lock)rw_enter_read(&rdev->exclusive_lock); |
| 677 | if (!rdev->accel_working) { |
| 678 | up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock); |
| 679 | return -EBUSY16; |
| 680 | } |
| 681 | if (rdev->in_reset) { |
| 682 | up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock); |
| 683 | r = radeon_gpu_reset(rdev); |
| 684 | if (!r) |
| 685 | r = -EAGAIN35; |
| 686 | return r; |
| 687 | } |
| 688 | /* initialize parser */ |
| 689 | memset(&parser, 0, sizeof(struct radeon_cs_parser))__builtin_memset((&parser), (0), (sizeof(struct radeon_cs_parser ))); |
| 690 | parser.filp = filp; |
| 691 | parser.rdev = rdev; |
| 692 | parser.dev = rdev->dev; |
| 693 | parser.family = rdev->family; |
| 694 | r = radeon_cs_parser_init(&parser, data); |
| 695 | if (r) { |
| 696 | DRM_ERROR("Failed to initialize parser !\n")__drm_err("Failed to initialize parser !\n"); |
| 697 | radeon_cs_parser_fini(&parser, r, false0); |
| 698 | up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock); |
| 699 | r = radeon_cs_handle_lockup(rdev, r); |
| 700 | return r; |
| 701 | } |
| 702 | |
| 703 | r = radeon_cs_ib_fill(rdev, &parser); |
| 704 | if (!r) { |
| 705 | r = radeon_cs_parser_relocs(&parser); |
| 706 | if (r && r != -ERESTARTSYS4) |
| 707 | DRM_ERROR("Failed to parse relocation %d!\n", r)__drm_err("Failed to parse relocation %d!\n", r); |
| 708 | } |
| 709 | |
| 710 | if (r) { |
| 711 | radeon_cs_parser_fini(&parser, r, false0); |
| 712 | up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock); |
| 713 | r = radeon_cs_handle_lockup(rdev, r); |
| 714 | return r; |
| 715 | } |
| 716 | |
| 717 | trace_radeon_cs(&parser); |
| 718 | |
| 719 | r = radeon_cs_ib_chunk(rdev, &parser); |
| 720 | if (r) { |
| 721 | goto out; |
| 722 | } |
| 723 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
| 724 | if (r) { |
| 725 | goto out; |
| 726 | } |
| 727 | out: |
| 728 | radeon_cs_parser_fini(&parser, r, true1); |
| 729 | up_read(&rdev->exclusive_lock)rw_exit_read(&rdev->exclusive_lock); |
| 730 | r = radeon_cs_handle_lockup(rdev, r); |
| 731 | return r; |
| 732 | } |
| 733 | |
| 734 | /** |
| 735 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet |
| 736 | * @p: parser structure holding parsing context. |
| 737 | * @pkt: where to store packet information |
| 738 | * @idx: packet index |
| 739 | * |
| 740 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
| 741 | * if packet is bigger than remaining ib size. or if packets is unknown. |
| 742 | **/ |
| 743 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
| 744 | struct radeon_cs_packet *pkt, |
| 745 | unsigned idx) |
| 746 | { |
| 747 | struct radeon_cs_chunk *ib_chunk = p->chunk_ib; |
| 748 | struct radeon_device *rdev = p->rdev; |
| 749 | uint32_t header; |
| 750 | int ret = 0, i; |
| 751 | |
| 752 | if (idx >= ib_chunk->length_dw) { |
| 753 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n",__drm_err("Can not parse packet at %d after CS end %d !\n", idx , ib_chunk->length_dw) |
| 754 | idx, ib_chunk->length_dw)__drm_err("Can not parse packet at %d after CS end %d !\n", idx , ib_chunk->length_dw); |
| 755 | return -EINVAL22; |
| 756 | } |
| 757 | header = radeon_get_ib_value(p, idx); |
| 758 | pkt->idx = idx; |
| 759 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header)(((header) >> 30) & 3); |
| 760 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header)(((header) >> 16) & 0x3FFF); |
| 761 | pkt->one_reg_wr = 0; |
| 762 | switch (pkt->type) { |
| 763 | case RADEON_PACKET_TYPE00: |
| 764 | if (rdev->family < CHIP_R600) { |
| 765 | pkt->reg = R100_CP_PACKET0_GET_REG(header)(((header) & 0x1FFF) << 2); |
| 766 | pkt->one_reg_wr = |
| 767 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header)(((header) >> 15) & 1); |
| 768 | } else |
| 769 | pkt->reg = R600_CP_PACKET0_GET_REG(header)(((header) & 0xFFFF) << 2); |
| 770 | break; |
| 771 | case RADEON_PACKET_TYPE33: |
| 772 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header)(((header) >> 8) & 0xFF); |
| 773 | break; |
| 774 | case RADEON_PACKET_TYPE22: |
| 775 | pkt->count = -1; |
| 776 | break; |
| 777 | default: |
| 778 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx)__drm_err("Unknown packet type %d at %d !\n", pkt->type, idx ); |
| 779 | ret = -EINVAL22; |
| 780 | goto dump_ib; |
| 781 | } |
| 782 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
| 783 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",__drm_err("Packet (%d:%d:%d) end after CS buffer (%d) !\n", pkt ->idx, pkt->type, pkt->count, ib_chunk->length_dw ) |
| 784 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw)__drm_err("Packet (%d:%d:%d) end after CS buffer (%d) !\n", pkt ->idx, pkt->type, pkt->count, ib_chunk->length_dw ); |
| 785 | ret = -EINVAL22; |
| 786 | goto dump_ib; |
| 787 | } |
| 788 | return 0; |
| 789 | |
| 790 | dump_ib: |
| 791 | for (i = 0; i < ib_chunk->length_dw; i++) { |
| 792 | if (i == idx) |
| 793 | printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); |
| 794 | else |
| 795 | printk("\t0x%08x\n", radeon_get_ib_value(p, i)); |
| 796 | } |
| 797 | return ret; |
| 798 | } |
| 799 | |
| 800 | /** |
| 801 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP |
| 802 | * @p: structure holding the parser context. |
| 803 | * |
| 804 | * Check if the next packet is NOP relocation packet3. |
| 805 | **/ |
| 806 | bool_Bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) |
| 807 | { |
| 808 | struct radeon_cs_packet p3reloc; |
| 809 | int r; |
| 810 | |
| 811 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); |
| 812 | if (r) |
| 813 | return false0; |
| 814 | if (p3reloc.type != RADEON_PACKET_TYPE33) |
| 815 | return false0; |
| 816 | if (p3reloc.opcode != RADEON_PACKET3_NOP0x10) |
| 817 | return false0; |
| 818 | return true1; |
| 819 | } |
| 820 | |
| 821 | /** |
| 822 | * radeon_cs_dump_packet() - dump raw packet context |
| 823 | * @p: structure holding the parser context. |
| 824 | * @pkt: structure holding the packet. |
| 825 | * |
| 826 | * Used mostly for debugging and error reporting. |
| 827 | **/ |
| 828 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
| 829 | struct radeon_cs_packet *pkt) |
| 830 | { |
| 831 | volatile uint32_t *ib; |
| 832 | unsigned i; |
| 833 | unsigned idx; |
| 834 | |
| 835 | ib = p->ib.ptr; |
| 836 | idx = pkt->idx; |
| 837 | for (i = 0; i <= (pkt->count + 1); i++, idx++) |
| 838 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx])printk("\0016" "[" "drm" "] " "ib[%d]=0x%08X\n", idx, ib[idx] ); |
| 839 | } |
| 840 | |
| 841 | /** |
| 842 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet |
| 843 | * @p: parser structure holding parsing context. |
| 844 | * @cs_reloc: reloc informations |
| 845 | * @nomm: no memory management for debugging |
| 846 | * |
| 847 | * Check if next packet is relocation packet3, do bo validation and compute |
| 848 | * GPU offset using the provided start. |
| 849 | **/ |
| 850 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 851 | struct radeon_bo_list **cs_reloc, |
| 852 | int nomm) |
| 853 | { |
| 854 | struct radeon_cs_chunk *relocs_chunk; |
| 855 | struct radeon_cs_packet p3reloc; |
| 856 | unsigned idx; |
| 857 | int r; |
| 858 | |
| 859 | if (p->chunk_relocs == NULL((void *)0)) { |
| 860 | DRM_ERROR("No relocation chunk !\n")__drm_err("No relocation chunk !\n"); |
| 861 | return -EINVAL22; |
| 862 | } |
| 863 | *cs_reloc = NULL((void *)0); |
| 864 | relocs_chunk = p->chunk_relocs; |
| 865 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); |
| 866 | if (r) |
| 867 | return r; |
| 868 | p->idx += p3reloc.count + 2; |
| 869 | if (p3reloc.type != RADEON_PACKET_TYPE33 || |
| 870 | p3reloc.opcode != RADEON_PACKET3_NOP0x10) { |
| 871 | DRM_ERROR("No packet3 for relocation for packet at %d.\n",__drm_err("No packet3 for relocation for packet at %d.\n", p3reloc .idx) |
| 872 | p3reloc.idx)__drm_err("No packet3 for relocation for packet at %d.\n", p3reloc .idx); |
| 873 | radeon_cs_dump_packet(p, &p3reloc); |
| 874 | return -EINVAL22; |
| 875 | } |
| 876 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
| 877 | if (idx >= relocs_chunk->length_dw) { |
| 878 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",__drm_err("Relocs at %d after relocations chunk end %d !\n", idx , relocs_chunk->length_dw) |
| 879 | idx, relocs_chunk->length_dw)__drm_err("Relocs at %d after relocations chunk end %d !\n", idx , relocs_chunk->length_dw); |
| 880 | radeon_cs_dump_packet(p, &p3reloc); |
| 881 | return -EINVAL22; |
| 882 | } |
| 883 | /* FIXME: we assume reloc size is 4 dwords */ |
| 884 | if (nomm) { |
| 885 | *cs_reloc = p->relocs; |
| 886 | (*cs_reloc)->gpu_offset = |
| 887 | (u64)relocs_chunk->kdata[idx + 3] << 32; |
| 888 | (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; |
| 889 | } else |
| 890 | *cs_reloc = &p->relocs[(idx / 4)]; |
| 891 | return 0; |
| 892 | } |