| File: | dev/ic/aic7xxx.c |
| Warning: | line 3683, column 5 Value stored to 'data_addr' is never read |
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| 1 | /* $OpenBSD: aic7xxx.c,v 1.97 2022/01/09 05:42:38 jsg Exp $ */ |
| 2 | /* $NetBSD: aic7xxx.c,v 1.108 2003/11/02 11:07:44 wiz Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Core routines and tables shareable across OS platforms. |
| 6 | * |
| 7 | * Copyright (c) 1994-2002 Justin T. Gibbs. |
| 8 | * Copyright (c) 2000-2002 Adaptec Inc. |
| 9 | * All rights reserved. |
| 10 | * |
| 11 | * Redistribution and use in source and binary forms, with or without |
| 12 | * modification, are permitted provided that the following conditions |
| 13 | * are met: |
| 14 | * 1. Redistributions of source code must retain the above copyright |
| 15 | * notice, this list of conditions, and the following disclaimer, |
| 16 | * without modification. |
| 17 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 18 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 19 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 20 | * including a substantially similar Disclaimer requirement for further |
| 21 | * binary redistribution. |
| 22 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 23 | * of any contributors may be used to endorse or promote products derived |
| 24 | * from this software without specific prior written permission. |
| 25 | * |
| 26 | * Alternatively, this software may be distributed under the terms of the |
| 27 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 28 | * Software Foundation. |
| 29 | * |
| 30 | * NO WARRANTY |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 32 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 33 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 34 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 35 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 36 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 37 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 38 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 39 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 40 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 41 | * POSSIBILITY OF SUCH DAMAGES. |
| 42 | * |
| 43 | * $Id: aic7xxx.c,v 1.97 2022/01/09 05:42:38 jsg Exp $ |
| 44 | */ |
| 45 | /* |
| 46 | * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 |
| 47 | */ |
| 48 | |
| 49 | #include <dev/ic/aic7xxx_openbsd.h> |
| 50 | #ifdef SMALL_KERNEL |
| 51 | #define IO_EXPAND |
| 52 | #endif |
| 53 | #include <dev/ic/aic7xxx_inline.h> |
| 54 | #include <dev/microcode/aic7xxx/aicasm_insformat.h> |
| 55 | |
| 56 | /****************************** Softc Data ************************************/ |
| 57 | struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq){ ((void *)0), &(ahc_tailq).tqh_first }; |
| 58 | |
| 59 | /***************************** Lookup Tables **********************************/ |
| 60 | char *ahc_chip_names[] = |
| 61 | { |
| 62 | "NONE", |
| 63 | "aic7770", |
| 64 | "aic7850", |
| 65 | "aic7855", |
| 66 | "aic7859", |
| 67 | "aic7860", |
| 68 | "aic7870", |
| 69 | "aic7880", |
| 70 | "aic7895", |
| 71 | "aic7895C", |
| 72 | "aic7890/91", |
| 73 | "aic7896/97", |
| 74 | "aic7892", |
| 75 | "aic7899" |
| 76 | }; |
| 77 | |
| 78 | /* |
| 79 | * Hardware error codes. |
| 80 | */ |
| 81 | struct ahc_hard_error_entry { |
| 82 | uint8_t errno; |
| 83 | char *errmesg; |
| 84 | }; |
| 85 | |
| 86 | #if !defined(SMALL_KERNEL) |
| 87 | static struct ahc_hard_error_entry ahc_hard_errors[] = { |
| 88 | { ILLHADDR0x01, "Illegal Host Access" }, |
| 89 | { ILLSADDR0x02, "Illegal Sequencer Address referenced" }, |
| 90 | { ILLOPCODE0x04, "Illegal Opcode in sequencer program" }, |
| 91 | { SQPARERR0x08, "Sequencer Parity Error" }, |
| 92 | { DPARERR0x10, "Data-path Parity Error" }, |
| 93 | { MPARERR0x20, "Scratch or SCB Memory Parity Error" }, |
| 94 | { PCIERRSTAT0x40, "PCI Error detected" }, |
| 95 | { CIOPARERR0x80, "CIOBUS Parity Error" }, |
| 96 | }; |
| 97 | static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors)(sizeof(ahc_hard_errors) / sizeof(*ahc_hard_errors)); |
| 98 | #endif /* !defined(SMALL_KERNEL) */ |
| 99 | |
| 100 | static struct ahc_phase_table_entry ahc_phase_table[] = |
| 101 | { |
| 102 | { P_DATAOUT0x00, MSG_NOOP0x08, "in Data-out phase" }, |
| 103 | { P_DATAIN0x40, MSG_INITIATOR_DET_ERR0x05, "in Data-in phase" }, |
| 104 | { P_DATAOUT_DT0x20, MSG_NOOP0x08, "in DT Data-out phase" }, |
| 105 | { P_DATAIN_DT0x60, MSG_INITIATOR_DET_ERR0x05, "in DT Data-in phase" }, |
| 106 | { P_COMMAND0x80, MSG_NOOP0x08, "in Command phase" }, |
| 107 | { P_MESGOUT0xa0, MSG_NOOP0x08, "in Message-out phase" }, |
| 108 | { P_STATUS0xc0, MSG_INITIATOR_DET_ERR0x05, "in Status phase" }, |
| 109 | { P_MESGIN0xe0, MSG_PARITY_ERROR0x09, "in Message-in phase" }, |
| 110 | { P_BUSFREE0x01, MSG_NOOP0x08, "while idle" }, |
| 111 | { 0, MSG_NOOP0x08, "in unknown phase" } |
| 112 | }; |
| 113 | |
| 114 | /* |
| 115 | * In most cases we only wish to iterate over real phases, so |
| 116 | * exclude the last element from the count. |
| 117 | */ |
| 118 | static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table)(sizeof(ahc_phase_table) / sizeof(*ahc_phase_table)) - 1; |
| 119 | |
| 120 | /* |
| 121 | * Valid SCSIRATE values. (p. 3-17) |
| 122 | * Provides a mapping of transfer periods in ns to the proper value to |
| 123 | * stick in the scsixfer reg. |
| 124 | */ |
| 125 | static struct ahc_syncrate ahc_syncrates[] = |
| 126 | { |
| 127 | /* ultra2 fast/ultra period rate */ |
| 128 | { 0x42, 0x000, 9, "80.0" }, |
| 129 | { 0x03, 0x000, 10, "40.0" }, |
| 130 | { 0x04, 0x000, 11, "33.0" }, |
| 131 | { 0x05, 0x100, 12, "20.0" }, |
| 132 | { 0x06, 0x110, 15, "16.0" }, |
| 133 | { 0x07, 0x120, 18, "13.4" }, |
| 134 | { 0x08, 0x000, 25, "10.0" }, |
| 135 | { 0x19, 0x010, 31, "8.0" }, |
| 136 | { 0x1a, 0x020, 37, "6.67" }, |
| 137 | { 0x1b, 0x030, 43, "5.7" }, |
| 138 | { 0x1c, 0x040, 50, "5.0" }, |
| 139 | { 0x00, 0x050, 56, "4.4" }, |
| 140 | { 0x00, 0x060, 62, "4.0" }, |
| 141 | { 0x00, 0x070, 68, "3.6" }, |
| 142 | { 0x00, 0x000, 0, NULL((void *)0) } |
| 143 | }; |
| 144 | |
| 145 | /* Our Sequencer Program */ |
| 146 | #include <dev/microcode/aic7xxx/aic7xxx_seq.h> |
| 147 | |
| 148 | /**************************** Function Declarations ***************************/ |
| 149 | static void ahc_force_renegotiation(struct ahc_softc *ahc, |
| 150 | struct ahc_devinfo *devinfo); |
| 151 | static struct ahc_tmode_tstate* |
| 152 | ahc_alloc_tstate(struct ahc_softc *ahc, |
| 153 | u_int scsi_id, char channel); |
| 154 | #ifdef AHC_TARGET_MODE |
| 155 | static void ahc_free_tstate(struct ahc_softc *ahc, |
| 156 | u_int scsi_id, char channel, int force); |
| 157 | #endif |
| 158 | static struct ahc_syncrate* |
| 159 | ahc_devlimited_syncrate(struct ahc_softc *ahc, |
| 160 | struct ahc_initiator_tinfo *, |
| 161 | u_int *period, |
| 162 | u_int *ppr_options, |
| 163 | role_t role); |
| 164 | static void ahc_update_pending_scbs(struct ahc_softc *ahc); |
| 165 | static void ahc_fetch_devinfo(struct ahc_softc *ahc, |
| 166 | struct ahc_devinfo *devinfo); |
| 167 | static void ahc_assert_atn(struct ahc_softc *ahc); |
| 168 | static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, |
| 169 | struct ahc_devinfo *devinfo, |
| 170 | struct scb *scb); |
| 171 | static void ahc_build_transfer_msg(struct ahc_softc *ahc, |
| 172 | struct ahc_devinfo *devinfo); |
| 173 | static void ahc_construct_sdtr(struct ahc_softc *ahc, |
| 174 | struct ahc_devinfo *devinfo, |
| 175 | u_int period, u_int offset); |
| 176 | static void ahc_construct_wdtr(struct ahc_softc *ahc, |
| 177 | struct ahc_devinfo *devinfo, |
| 178 | u_int bus_width); |
| 179 | static void ahc_construct_ppr(struct ahc_softc *ahc, |
| 180 | struct ahc_devinfo *devinfo, |
| 181 | u_int period, u_int offset, |
| 182 | u_int bus_width, u_int ppr_options); |
| 183 | static void ahc_clear_msg_state(struct ahc_softc *ahc); |
| 184 | static void ahc_handle_proto_violation(struct ahc_softc *ahc); |
| 185 | static void ahc_handle_message_phase(struct ahc_softc *ahc); |
| 186 | typedef enum { |
| 187 | AHCMSG_1B, |
| 188 | AHCMSG_2B, |
| 189 | AHCMSG_EXT |
| 190 | } ahc_msgtype; |
| 191 | static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, |
| 192 | u_int msgval, int full); |
| 193 | static int ahc_parse_msg(struct ahc_softc *ahc, |
| 194 | struct ahc_devinfo *devinfo); |
| 195 | static int ahc_handle_msg_reject(struct ahc_softc *ahc, |
| 196 | struct ahc_devinfo *devinfo); |
| 197 | static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, |
| 198 | struct ahc_devinfo *devinfo); |
| 199 | static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); |
| 200 | static void ahc_handle_devreset(struct ahc_softc *ahc, |
| 201 | struct ahc_devinfo *devinfo, |
| 202 | cam_status status, char *message, |
| 203 | int verbose_level); |
| 204 | #ifdef AHC_TARGET_MODE |
| 205 | static void ahc_setup_target_msgin(struct ahc_softc *ahc, |
| 206 | struct ahc_devinfo *devinfo, |
| 207 | struct scb *scb); |
| 208 | #endif |
| 209 | |
| 210 | //static bus_dmamap_callback_t ahc_dmamap_cb; |
| 211 | static void ahc_build_free_scb_list(struct ahc_softc *ahc); |
| 212 | static int ahc_init_scbdata(struct ahc_softc *ahc); |
| 213 | static void ahc_fini_scbdata(struct ahc_softc *ahc); |
| 214 | static void ahc_qinfifo_requeue(struct ahc_softc *ahc, |
| 215 | struct scb *prev_scb, |
| 216 | struct scb *scb); |
| 217 | static int ahc_qinfifo_count(struct ahc_softc *ahc); |
| 218 | static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, |
| 219 | u_int prev, u_int scbptr); |
| 220 | static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); |
| 221 | static u_int ahc_rem_wscb(struct ahc_softc *ahc, |
| 222 | u_int scbpos, u_int prev); |
| 223 | static void ahc_reset_current_bus(struct ahc_softc *ahc); |
| 224 | #ifdef AHC_DUMP_SEQ |
| 225 | static void ahc_dumpseq(struct ahc_softc *ahc); |
| 226 | #endif |
| 227 | static int ahc_loadseq(struct ahc_softc *ahc); |
| 228 | static int ahc_check_patch(struct ahc_softc *ahc, |
| 229 | const struct patch **start_patch, |
| 230 | u_int start_instr, u_int *skip_addr); |
| 231 | static void ahc_download_instr(struct ahc_softc *ahc, |
| 232 | u_int instrptr, uint8_t *dconsts); |
| 233 | #ifdef AHC_TARGET_MODE |
| 234 | static void ahc_queue_lstate_event(struct ahc_softc *ahc, |
| 235 | struct ahc_tmode_lstate *lstate, |
| 236 | u_int initiator_id, |
| 237 | u_int event_type, |
| 238 | u_int event_arg); |
| 239 | static void ahc_update_scsiid(struct ahc_softc *ahc, |
| 240 | u_int targid_mask); |
| 241 | static int ahc_handle_target_cmd(struct ahc_softc *ahc, |
| 242 | struct target_cmd *cmd); |
| 243 | #endif |
| 244 | |
| 245 | /************************** Added for porting to NetBSD ***********************/ |
| 246 | static int ahc_createdmamem(bus_dma_tag_t tag, |
| 247 | int size, |
| 248 | int flags, |
| 249 | bus_dmamap_t *mapp, |
| 250 | caddr_t *vaddr, |
| 251 | bus_addr_t *baddr, |
| 252 | bus_dma_segment_t *seg, |
| 253 | int *nseg, |
| 254 | const char *myname, const char *what); |
| 255 | static void ahc_freedmamem(bus_dma_tag_t tag, |
| 256 | int size, |
| 257 | bus_dmamap_t map, |
| 258 | caddr_t vaddr, |
| 259 | bus_dma_segment_t *seg, |
| 260 | int nseg); |
| 261 | |
| 262 | /************************* Sequencer Execution Control ************************/ |
| 263 | /* |
| 264 | * Restart the sequencer program from address zero |
| 265 | */ |
| 266 | void |
| 267 | ahc_restart(struct ahc_softc *ahc) |
| 268 | { |
| 269 | |
| 270 | ahc_pause(ahc); |
| 271 | |
| 272 | /* No more pending messages. */ |
| 273 | ahc_clear_msg_state(ahc); |
| 274 | |
| 275 | ahc_outb(ahc, SCSISIGO, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x03), (0))); /* De-assert BSY */ |
| 276 | ahc_outb(ahc, MSG_OUT, MSG_NOOP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0x08)) ); /* No message to send */ |
| 277 | ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x02))) & ~0x80)) ); |
| 278 | ahc_outb(ahc, LASTPHASE, P_BUSFREE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3f), (0x01)) ); |
| 279 | ahc_outb(ahc, SAVED_SCSIID, 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3d), (0xFF)) ); |
| 280 | ahc_outb(ahc, SAVED_LUN, 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3e), (0xFF)) ); |
| 281 | |
| 282 | /* |
| 283 | * Ensure that the sequencer's idea of TQINPOS |
| 284 | * matches our own. The sequencer increments TQINPOS |
| 285 | * only after it sees a DMA complete and a reset could |
| 286 | * occur before the increment leaving the kernel to believe |
| 287 | * the command arrived but the sequencer to not. |
| 288 | */ |
| 289 | ahc_outb(ahc, TQINPOS, ahc->tqinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x50), (ahc-> tqinfifonext))); |
| 290 | |
| 291 | /* Always allow reselection */ |
| 292 | ahc_outb(ahc, SCSISEQ,(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x54))) & (0x20|0x10 |0x02)))) |
| 293 | ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x54))) & (0x20|0x10 |0x02)))); |
| 294 | if ((ahc->features & AHC_CMD_CHAN) != 0) { |
| 295 | /* Ensure that no DMA operations are in progress */ |
| 296 | ahc_outb(ahc, CCSCBCNT, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xef), (0))); |
| 297 | ahc_outb(ahc, CCSGCTL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xeb), (0))); |
| 298 | ahc_outb(ahc, CCSCBCTL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xee), (0))); |
| 299 | } |
| 300 | /* |
| 301 | * If we were in the process of DMA'ing SCB data into |
| 302 | * an SCB, replace that SCB on the free list. This prevents |
| 303 | * an SCB leak. |
| 304 | */ |
| 305 | if ((ahc_inb(ahc, SEQ_FLAGS2)(((ahc)->tag)->read_1(((ahc)->bsh), (0x57))) & SCB_DMA0x01) != 0) { |
| 306 | ahc_add_curscb_to_free_list(ahc); |
| 307 | ahc_outb(ahc, SEQ_FLAGS2,(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x57))) & ~0x01)) ) |
| 308 | ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA)(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x57))) & ~0x01)) ); |
| 309 | } |
| 310 | |
| 311 | /* |
| 312 | * Clear any pending sequencer interrupt. It is no |
| 313 | * longer relevant since we're resetting the Program |
| 314 | * Counter. |
| 315 | */ |
| 316 | ahc_outb(ahc, CLRINT, CLRSEQINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x01)) ); |
| 317 | |
| 318 | ahc_outb(ahc, MWI_RESIDUAL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x38), (0))); |
| 319 | ahc_outb(ahc, SEQCTL, ahc->seqctl)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (ahc-> seqctl))); |
| 320 | ahc_outb(ahc, SEQADDR0, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x62), (0))); |
| 321 | ahc_outb(ahc, SEQADDR1, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x63), (0))); |
| 322 | |
| 323 | ahc_unpause(ahc); |
| 324 | } |
| 325 | |
| 326 | /************************* Input/Output Queues ********************************/ |
| 327 | void |
| 328 | ahc_run_qoutfifo(struct ahc_softc *ahc) |
| 329 | { |
| 330 | struct scb *scb; |
| 331 | u_int scb_index; |
| 332 | |
| 333 | ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD0x02); |
| 334 | while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL0xff) { |
| 335 | |
| 336 | scb_index = ahc->qoutfifo[ahc->qoutfifonext]; |
| 337 | if ((ahc->qoutfifonext & 0x03) == 0x03) { |
| 338 | u_int modnext; |
| 339 | |
| 340 | /* |
| 341 | * Clear 32bits of QOUTFIFO at a time |
| 342 | * so that we don't clobber an incoming |
| 343 | * byte DMA to the array on architectures |
| 344 | * that only support 32bit load and store |
| 345 | * operations. |
| 346 | */ |
| 347 | modnext = ahc->qoutfifonext & ~0x3; |
| 348 | *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; |
| 349 | ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (modnext), (4), (0x01)) |
| 350 | ahc->shared_data_dmamap,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (modnext), (4), (0x01)) |
| 351 | /*offset*/modnext, /*len*/4,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (modnext), (4), (0x01)) |
| 352 | BUS_DMASYNC_PREREAD)(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (modnext), (4), (0x01)); |
| 353 | } |
| 354 | ahc->qoutfifonext++; |
| 355 | |
| 356 | scb = ahc_lookup_scb(ahc, scb_index); |
| 357 | if (scb == NULL((void *)0)) { |
| 358 | printf("%s: WARNING no command for scb %d " |
| 359 | "(cmdcmplt)\nQOUTPOS = %d\n", |
| 360 | ahc_name(ahc), scb_index, |
| 361 | (ahc->qoutfifonext - 1) & 0xFF); |
| 362 | continue; |
| 363 | } |
| 364 | |
| 365 | /* |
| 366 | * Save off the residual |
| 367 | * if there is one. |
| 368 | */ |
| 369 | ahc_update_residual(ahc, scb); |
| 370 | ahc_done(ahc, scb); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | void |
| 375 | ahc_run_untagged_queues(struct ahc_softc *ahc) |
| 376 | { |
| 377 | int i; |
| 378 | |
| 379 | for (i = 0; i < 16; i++) |
| 380 | ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); |
| 381 | } |
| 382 | |
| 383 | void |
| 384 | ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) |
| 385 | { |
| 386 | struct scb *scb; |
| 387 | |
| 388 | if (ahc->untagged_queue_lock != 0) |
| 389 | return; |
| 390 | |
| 391 | if ((scb = TAILQ_FIRST(queue)((queue)->tqh_first)) != NULL((void *)0) |
| 392 | && (scb->flags & SCB_ACTIVE) == 0) { |
| 393 | scb->flags |= SCB_ACTIVE; |
| 394 | ahc_queue_scb(ahc, scb); |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | /************************* Interrupt Handling *********************************/ |
| 399 | void |
| 400 | ahc_handle_brkadrint(struct ahc_softc *ahc) |
| 401 | { |
| 402 | /* |
| 403 | * We upset the sequencer :-( |
| 404 | * Lookup the error message |
| 405 | */ |
| 406 | #ifndef SMALL_KERNEL |
| 407 | int i; |
| 408 | int error; |
| 409 | |
| 410 | error = ahc_inb(ahc, ERROR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x92))); |
| 411 | for (i = 0; error != 1 && i < num_errors; i++) |
| 412 | error >>= 1; |
| 413 | if (i >= num_errors) |
| 414 | panic("invalid error code"); |
| 415 | printf("%s: brkadrint, %s at seqaddr = 0x%x\n", |
| 416 | ahc_name(ahc), ahc_hard_errors[i].errmesg, |
| 417 | ahc_inb(ahc, SEQADDR0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x62))) | |
| 418 | (ahc_inb(ahc, SEQADDR1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x63))) << 8)); |
| 419 | |
| 420 | ahc_dump_card_state(ahc); |
| 421 | #endif |
| 422 | |
| 423 | /* Tell everyone that this HBA is no longer available */ |
| 424 | ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD((u_int)~0), ALL_CHANNELS'\0', |
| 425 | CAM_LUN_WILDCARD-1, SCB_LIST_NULL0xff, ROLE_UNKNOWN, |
| 426 | CAM_NO_HBA); |
| 427 | |
| 428 | /* Disable all interrupt sources by resetting the controller */ |
| 429 | ahc_shutdown(ahc); |
| 430 | } |
| 431 | |
| 432 | void |
| 433 | ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) |
| 434 | { |
| 435 | struct scb *scb; |
| 436 | struct ahc_devinfo devinfo; |
| 437 | u_int scb_index; |
| 438 | |
| 439 | ahc_fetch_devinfo(ahc, &devinfo); |
| 440 | |
| 441 | /* |
| 442 | * Clear the upper byte that holds SEQINT status |
| 443 | * codes and clear the SEQINT bit. We will unpause |
| 444 | * the sequencer, if appropriate, after servicing |
| 445 | * the request. |
| 446 | */ |
| 447 | ahc_outb(ahc, CLRINT, CLRSEQINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x01)) ); |
| 448 | switch (intstat & SEQINT_MASK0xf1) { |
| 449 | case BAD_STATUS0x71: |
| 450 | { |
| 451 | struct hardware_scb *hscb; |
| 452 | |
| 453 | /* |
| 454 | * Set the default return value to 0 (don't |
| 455 | * send sense). The sense code will change |
| 456 | * this if needed. |
| 457 | */ |
| 458 | ahc_outb(ahc, RETURN_1, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x51), (0))); |
| 459 | |
| 460 | /* |
| 461 | * The sequencer will notify us when a command |
| 462 | * has an error that would be of interest to |
| 463 | * the kernel. This allows us to leave the sequencer |
| 464 | * running in the common case of command completes |
| 465 | * without error. The sequencer will already have |
| 466 | * DMA'd the SCB back up to us, so we can reference |
| 467 | * the in kernel copy directly. |
| 468 | */ |
| 469 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 470 | scb = ahc_lookup_scb(ahc, scb_index); |
| 471 | if (scb == NULL((void *)0)) { |
| 472 | ahc_print_devinfo(ahc, &devinfo); |
| 473 | printf("ahc_intr - referenced scb " |
| 474 | "not valid during seqint 0x%x scb(%d)\n", |
| 475 | intstat, scb_index); |
| 476 | ahc_dump_card_state(ahc); |
| 477 | panic("for safety"); |
| 478 | goto unpause; |
| 479 | } |
| 480 | |
| 481 | hscb = scb->hscb; |
| 482 | |
| 483 | /* Don't want to clobber the original sense code */ |
| 484 | if ((scb->flags & SCB_SENSE) != 0) { |
| 485 | /* |
| 486 | * Clear the SCB_SENSE Flag and have |
| 487 | * the sequencer do a normal command |
| 488 | * complete. |
| 489 | */ |
| 490 | scb->flags &= ~SCB_SENSE; |
| 491 | ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); |
| 492 | break; |
| 493 | } |
| 494 | ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); |
| 495 | /* Freeze the queue until the client sees the error. */ |
| 496 | ahc_freeze_devq(ahc, scb); |
| 497 | ahc_freeze_scb(scb); |
| 498 | ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); |
| 499 | switch (hscb->shared_data.status.scsi_status) { |
| 500 | case SCSI_STATUS_OK0x00: |
| 501 | printf("%s: Interrupted for status of 0 (?)\n", |
| 502 | ahc_name(ahc)); |
| 503 | break; |
| 504 | case SCSI_STATUS_CMD_TERMINATED0x22: |
| 505 | case SCSI_STATUS_CHECK_COND0x02: |
| 506 | { |
| 507 | struct ahc_dma_seg *sg; |
| 508 | struct scsi_sense *sc; |
| 509 | struct ahc_initiator_tinfo *targ_info; |
| 510 | struct ahc_tmode_tstate *tstate; |
| 511 | struct ahc_transinfo *tinfo; |
| 512 | #ifdef AHC_DEBUG |
| 513 | if (ahc_debug & AHC_SHOW_SENSE) { |
| 514 | ahc_print_path(ahc, scb); |
| 515 | printf("SCB %d: requests Check Status\n", |
| 516 | scb->hscb->tag); |
| 517 | } |
| 518 | #endif |
| 519 | |
| 520 | if (ahc_perform_autosense(scb) == 0) |
| 521 | break; |
| 522 | |
| 523 | targ_info = ahc_fetch_transinfo(ahc, |
| 524 | devinfo.channel, |
| 525 | devinfo.our_scsiid, |
| 526 | devinfo.target, |
| 527 | &tstate); |
| 528 | tinfo = &targ_info->curr; |
| 529 | sg = scb->sg_list; |
| 530 | sc = (struct scsi_sense *)(&hscb->shared_data.cdb); |
| 531 | /* |
| 532 | * Save off the residual if there is one. |
| 533 | */ |
| 534 | ahc_update_residual(ahc, scb); |
| 535 | #ifdef AHC_DEBUG |
| 536 | if (ahc_debug & AHC_SHOW_SENSE) { |
| 537 | ahc_print_path(ahc, scb); |
| 538 | printf("Sending Sense\n"); |
| 539 | } |
| 540 | #endif |
| 541 | sg->addr = ahc_get_sense_bufaddr(ahc, scb); |
| 542 | sg->len = ahc_get_sense_bufsize(ahc, scb); |
| 543 | sg->len |= AHC_DMA_LAST_SEG0x80000000; |
| 544 | |
| 545 | /* Fixup byte order */ |
| 546 | sg->addr = aic_htole32(sg->addr)((__uint32_t)(sg->addr)); |
| 547 | sg->len = aic_htole32(sg->len)((__uint32_t)(sg->len)); |
| 548 | |
| 549 | sc->opcode = REQUEST_SENSE0x03; |
| 550 | sc->byte2 = 0; |
| 551 | if (tinfo->protocol_version <= SCSI_REV_20x02 |
| 552 | && SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f) < 8) |
| 553 | sc->byte2 = SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f) << 5; |
| 554 | sc->unused[0] = 0; |
| 555 | sc->unused[1] = 0; |
| 556 | sc->length = sg->len; |
| 557 | sc->control = 0; |
| 558 | |
| 559 | /* |
| 560 | * We can't allow the target to disconnect. |
| 561 | * This will be an untagged transaction and |
| 562 | * having the target disconnect will make this |
| 563 | * transaction indistinguishable from outstanding |
| 564 | * tagged transactions. |
| 565 | */ |
| 566 | hscb->control = 0; |
| 567 | |
| 568 | /* |
| 569 | * This request sense could be because the |
| 570 | * the device lost power or in some other |
| 571 | * way has lost our transfer negotiations. |
| 572 | * Renegotiate if appropriate. Unit attention |
| 573 | * errors will be reported before any data |
| 574 | * phases occur. |
| 575 | */ |
| 576 | if (ahc_get_residual(scb) |
| 577 | == ahc_get_transfer_length(scb)) { |
| 578 | ahc_update_neg_request(ahc, &devinfo, |
| 579 | tstate, targ_info, |
| 580 | AHC_NEG_IF_NON_ASYNC); |
| 581 | } |
| 582 | if (tstate->auto_negotiate & devinfo.target_mask) { |
| 583 | hscb->control |= MK_MESSAGE0x10; |
| 584 | scb->flags &= ~SCB_NEGOTIATE; |
| 585 | scb->flags |= SCB_AUTO_NEGOTIATE; |
| 586 | } |
| 587 | hscb->cdb_len = sizeof(*sc); |
| 588 | hscb->dataptr = sg->addr; |
| 589 | hscb->datacnt = sg->len; |
| 590 | hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID0x02; |
| 591 | hscb->sgptr = aic_htole32(hscb->sgptr)((__uint32_t)(hscb->sgptr)); |
| 592 | #ifdef __OpenBSD__1 |
| 593 | bus_dmamap_sync(ahc->parent_dmat,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)) |
| 594 | ahc->scb_data->sense_dmamap,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)) |
| 595 | (scb - ahc->scb_data->scbarray) *(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)) |
| 596 | sizeof(struct scsi_sense_data),(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)) |
| 597 | sizeof(struct scsi_sense_data),(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)) |
| 598 | BUS_DMASYNC_PREREAD)(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->sense_dmamap), ((scb - ahc->scb_data ->scbarray) * sizeof(struct scsi_sense_data)), (sizeof(struct scsi_sense_data)), (0x01)); |
| 599 | bus_dmamap_sync(ahc->parent_dmat,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (scb->sg_map->sg_dmamap), (0), (scb->sg_map->sg_dmamap ->dm_mapsize), (0x04)) |
| 600 | scb->sg_map->sg_dmamap,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (scb->sg_map->sg_dmamap), (0), (scb->sg_map->sg_dmamap ->dm_mapsize), (0x04)) |
| 601 | 0, scb->sg_map->sg_dmamap->dm_mapsize,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (scb->sg_map->sg_dmamap), (0), (scb->sg_map->sg_dmamap ->dm_mapsize), (0x04)) |
| 602 | BUS_DMASYNC_PREWRITE)(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (scb->sg_map->sg_dmamap), (0), (scb->sg_map->sg_dmamap ->dm_mapsize), (0x04)); |
| 603 | bus_dmamap_sync(ahc->parent_dmat,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->hscb_dmamap), (0), (ahc->scb_data ->hscb_dmamap->dm_mapsize), (0x01 | 0x04)) |
| 604 | ahc->scb_data->hscb_dmamap,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->hscb_dmamap), (0), (ahc->scb_data ->hscb_dmamap->dm_mapsize), (0x01 | 0x04)) |
| 605 | 0, ahc->scb_data->hscb_dmamap->dm_mapsize,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->hscb_dmamap), (0), (ahc->scb_data ->hscb_dmamap->dm_mapsize), (0x01 | 0x04)) |
| 606 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->scb_data->hscb_dmamap), (0), (ahc->scb_data ->hscb_dmamap->dm_mapsize), (0x01 | 0x04)); |
| 607 | #endif |
| 608 | scb->sg_count = 1; |
| 609 | scb->flags |= SCB_SENSE; |
| 610 | ahc_qinfifo_requeue_tail(ahc, scb); |
| 611 | ahc_outb(ahc, RETURN_1, SEND_SENSE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x51), (0x40)) ); |
| 612 | /* |
| 613 | * Ensure we have enough time to actually |
| 614 | * retrieve the sense. |
| 615 | */ |
| 616 | ahc_scb_timer_reset(scb, 5 * 1000000); |
| 617 | break; |
| 618 | } |
| 619 | default: |
| 620 | break; |
| 621 | } |
| 622 | break; |
| 623 | } |
| 624 | case NO_MATCH0x31: |
| 625 | { |
| 626 | /* Ensure we don't leave the selection hardware on */ |
| 627 | ahc_outb(ahc, SCSISEQ,(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & (0x20|0x10 |0x02)))) |
| 628 | ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & (0x20|0x10 |0x02)))); |
| 629 | |
| 630 | printf("%s:%c:%d: no active SCB for reconnecting " |
| 631 | "target - issuing BUS DEVICE RESET\n", |
| 632 | ahc_name(ahc), devinfo.channel, devinfo.target); |
| 633 | printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " |
| 634 | "ARG_1 == 0x%x ACCUM = 0x%x\n", |
| 635 | ahc_inb(ahc, SAVED_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3d))), ahc_inb(ahc, SAVED_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3e))), |
| 636 | ahc_inb(ahc, ARG_1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x51))), ahc_inb(ahc, ACCUM)(((ahc)->tag)->read_1(((ahc)->bsh), (0x64)))); |
| 637 | printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " |
| 638 | "SINDEX == 0x%x\n", |
| 639 | ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))), ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))), |
| 640 | ahc_index_busy_tcl(ahc, |
| 641 | BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),(((((ahc)->tag)->read_1(((ahc)->bsh), (0x3e)))) | (( ((((ahc)->tag)->read_1(((ahc)->bsh), (0x3d)))) & 0xf0) << 4)) |
| 642 | ahc_inb(ahc, SAVED_LUN))(((((ahc)->tag)->read_1(((ahc)->bsh), (0x3e)))) | (( ((((ahc)->tag)->read_1(((ahc)->bsh), (0x3d)))) & 0xf0) << 4))), |
| 643 | ahc_inb(ahc, SINDEX)(((ahc)->tag)->read_1(((ahc)->bsh), (0x65)))); |
| 644 | printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " |
| 645 | "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", |
| 646 | ahc_inb(ahc, SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x05))), ahc_inb(ahc, SCB_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb9))), |
| 647 | ahc_inb(ahc, SCB_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0xba))), ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))), |
| 648 | ahc_inb(ahc, SCB_CONTROL)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb8)))); |
| 649 | printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", |
| 650 | ahc_inb(ahc, SCSIBUSL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x12))), ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03)))); |
| 651 | printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x01)))); |
| 652 | printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x60)))); |
| 653 | ahc_dump_card_state(ahc); |
| 654 | ahc->msgout_buf[0] = MSG_BUS_DEV_RESET0x0c; |
| 655 | ahc->msgout_len = 1; |
| 656 | ahc->msgout_index = 0; |
| 657 | ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
| 658 | ahc_outb(ahc, MSG_OUT, HOST_MSG)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0xff)) ); |
| 659 | ahc_assert_atn(ahc); |
| 660 | break; |
| 661 | } |
| 662 | case SEND_REJECT0x11: |
| 663 | { |
| 664 | u_int rejbyte = ahc_inb(ahc, ACCUM)(((ahc)->tag)->read_1(((ahc)->bsh), (0x64))); |
| 665 | printf("%s:%c:%d: Warning - unknown message received from " |
| 666 | "target (0x%x). Rejecting\n", |
| 667 | ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); |
| 668 | break; |
| 669 | } |
| 670 | case PROTO_VIOLATION0x21: |
| 671 | { |
| 672 | ahc_handle_proto_violation(ahc); |
| 673 | break; |
| 674 | } |
| 675 | case IGN_WIDE_RES0x41: |
| 676 | ahc_handle_ign_wide_residue(ahc, &devinfo); |
| 677 | break; |
| 678 | case PDATA_REINIT0x51: |
| 679 | ahc_reinitialize_dataptrs(ahc); |
| 680 | break; |
| 681 | case BAD_PHASE0x01: |
| 682 | { |
| 683 | u_int lastphase; |
| 684 | |
| 685 | lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 686 | printf("%s:%c:%d: unknown scsi bus phase %x, " |
| 687 | "lastphase = 0x%x. Attempting to continue\n", |
| 688 | ahc_name(ahc), devinfo.channel, devinfo.target, |
| 689 | lastphase, ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03)))); |
| 690 | break; |
| 691 | } |
| 692 | case MISSED_BUSFREE0xb1: |
| 693 | { |
| 694 | u_int lastphase; |
| 695 | |
| 696 | lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 697 | printf("%s:%c:%d: Missed busfree. " |
| 698 | "Lastphase = 0x%x, Curphase = 0x%x\n", |
| 699 | ahc_name(ahc), devinfo.channel, devinfo.target, |
| 700 | lastphase, ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03)))); |
| 701 | ahc_restart(ahc); |
| 702 | return; |
| 703 | } |
| 704 | case HOST_MSG_LOOP0x61: |
| 705 | { |
| 706 | /* |
| 707 | * The sequencer has encountered a message phase |
| 708 | * that requires host assistance for completion. |
| 709 | * While handling the message phase(s), we will be |
| 710 | * notified by the sequencer after each byte is |
| 711 | * transferred so we can track bus phase changes. |
| 712 | * |
| 713 | * If this is the first time we've seen a HOST_MSG_LOOP |
| 714 | * interrupt, initialize the state of the host message |
| 715 | * loop. |
| 716 | */ |
| 717 | if (ahc->msg_type == MSG_TYPE_NONE) { |
| 718 | u_int bus_phase; |
| 719 | |
| 720 | bus_phase = ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & PHASE_MASK0xe0; |
| 721 | if (bus_phase != P_MESGIN0xe0 |
| 722 | && bus_phase != P_MESGOUT0xa0) { |
| 723 | printf("ahc_intr: HOST_MSG_LOOP bad " |
| 724 | "phase 0x%x\n", |
| 725 | bus_phase); |
| 726 | /* |
| 727 | * Probably transitioned to bus free before |
| 728 | * we got here. Just punt the message. |
| 729 | */ |
| 730 | ahc_clear_intstat(ahc); |
| 731 | ahc_restart(ahc); |
| 732 | return; |
| 733 | } |
| 734 | |
| 735 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 736 | scb = ahc_lookup_scb(ahc, scb_index); |
| 737 | if (devinfo.role == ROLE_INITIATOR) { |
| 738 | if (scb == NULL((void *)0)) |
| 739 | panic("HOST_MSG_LOOP with " |
| 740 | "invalid SCB %x\n", scb_index); |
| 741 | |
| 742 | if (bus_phase == P_MESGOUT0xa0) |
| 743 | ahc_setup_initiator_msgout(ahc, |
| 744 | &devinfo, |
| 745 | scb); |
| 746 | else { |
| 747 | ahc->msg_type = |
| 748 | MSG_TYPE_INITIATOR_MSGIN; |
| 749 | ahc->msgin_index = 0; |
| 750 | } |
| 751 | } |
| 752 | #ifdef AHC_TARGET_MODE |
| 753 | else { |
| 754 | if (bus_phase == P_MESGOUT0xa0) { |
| 755 | ahc->msg_type = |
| 756 | MSG_TYPE_TARGET_MSGOUT; |
| 757 | ahc->msgin_index = 0; |
| 758 | } |
| 759 | else |
| 760 | ahc_setup_target_msgin(ahc, |
| 761 | &devinfo, |
| 762 | scb); |
| 763 | } |
| 764 | #endif |
| 765 | } |
| 766 | |
| 767 | ahc_handle_message_phase(ahc); |
| 768 | break; |
| 769 | } |
| 770 | case PERR_DETECTED0x81: |
| 771 | { |
| 772 | /* |
| 773 | * If we've cleared the parity error interrupt |
| 774 | * but the sequencer still believes that SCSIPERR |
| 775 | * is true, it must be that the parity error is |
| 776 | * for the currently presented byte on the bus, |
| 777 | * and we are not in a phase (data-in) where we will |
| 778 | * eventually ack this byte. Ack the byte and |
| 779 | * throw it away in the hope that the target will |
| 780 | * take us to message out to deliver the appropriate |
| 781 | * error message. |
| 782 | */ |
| 783 | if ((intstat & SCSIINT0x04) == 0 |
| 784 | && (ahc_inb(ahc, SSTAT1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0c))) & SCSIPERR0x04) != 0) { |
| 785 | |
| 786 | if ((ahc->features & AHC_DT) == 0) { |
| 787 | u_int curphase; |
| 788 | |
| 789 | /* |
| 790 | * The hardware will only let you ack bytes |
| 791 | * if the expected phase in SCSISIGO matches |
| 792 | * the current phase. Make sure this is |
| 793 | * currently the case. |
| 794 | */ |
| 795 | curphase = ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & PHASE_MASK0xe0; |
| 796 | ahc_outb(ahc, LASTPHASE, curphase)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3f), (curphase ))); |
| 797 | ahc_outb(ahc, SCSISIGO, curphase)(((ahc)->tag)->write_1(((ahc)->bsh), (0x03), (curphase ))); |
| 798 | } |
| 799 | if ((ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & (CDI0x80|MSGI0x20)) == 0) { |
| 800 | int wait; |
| 801 | |
| 802 | /* |
| 803 | * In a data phase. Faster to bitbucket |
| 804 | * the data than to individually ack each |
| 805 | * byte. This is also the only strategy |
| 806 | * that will work with AUTOACK enabled. |
| 807 | */ |
| 808 | ahc_outb(ahc, SXFRCTL1,(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x02))) | 0x80))) |
| 809 | ahc_inb(ahc, SXFRCTL1) | BITBUCKET)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x02))) | 0x80))); |
| 810 | wait = 5000; |
| 811 | while (--wait != 0) { |
| 812 | if ((ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) |
| 813 | & (CDI0x80|MSGI0x20)) != 0) |
| 814 | break; |
| 815 | aic_delay(100)(*delay_func)(100); |
| 816 | } |
| 817 | ahc_outb(ahc, SXFRCTL1,(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x02))) & ~0x80)) ) |
| 818 | ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x02))) & ~0x80)) ); |
| 819 | if (wait == 0) { |
| 820 | ahc_print_devinfo(ahc, &devinfo); |
| 821 | printf("Unable to clear parity error. " |
| 822 | "Resetting bus.\n"); |
| 823 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 824 | scb = ahc_lookup_scb(ahc, scb_index); |
| 825 | if (scb != NULL((void *)0)) |
| 826 | ahc_set_transaction_status(scb, |
| 827 | CAM_UNCOR_PARITY); |
| 828 | ahc_reset_channel(ahc, devinfo.channel, |
| 829 | /*init reset*/TRUE1); |
| 830 | } |
| 831 | } else { |
| 832 | ahc_inb(ahc, SCSIDATL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x06))); |
| 833 | } |
| 834 | } |
| 835 | break; |
| 836 | } |
| 837 | case DATA_OVERRUN0x91: |
| 838 | { |
| 839 | /* |
| 840 | * When the sequencer detects an overrun, it |
| 841 | * places the controller in "BITBUCKET" mode |
| 842 | * and allows the target to complete its transfer. |
| 843 | * Unfortunately, none of the counters get updated |
| 844 | * when the controller is in this mode, so we have |
| 845 | * no way of knowing how large the overrun was. |
| 846 | */ |
| 847 | u_int scbindex = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 848 | u_int lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 849 | u_int i; |
| 850 | |
| 851 | scb = ahc_lookup_scb(ahc, scbindex); |
| 852 | for (i = 0; i < num_phases; i++) { |
| 853 | if (lastphase == ahc_phase_table[i].phase) |
| 854 | break; |
| 855 | } |
| 856 | #ifdef AHC_DEBUG |
| 857 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 858 | ahc_print_path(ahc, scb); |
| 859 | printf("data overrun detected %s." |
| 860 | " Tag == 0x%x.\n", |
| 861 | ahc_phase_table[i].phasemsg, |
| 862 | scb->hscb->tag); |
| 863 | ahc_print_path(ahc, scb); |
| 864 | printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", |
| 865 | ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))) & DPHASE0x20 ? "Have" : "Haven't", |
| 866 | ahc_get_transfer_length(scb), scb->sg_count); |
| 867 | if (scb->sg_count > 0) { |
| 868 | for (i = 0; i < scb->sg_count; i++) { |
| 869 | |
| 870 | printf("sg[%d] - Addr 0x%x%x : Length %d\n", |
| 871 | i, |
| 872 | (aic_le32toh(scb->sg_list[i].len)((__uint32_t)(scb->sg_list[i].len)) >> 24 |
| 873 | & SG_HIGH_ADDR_BITS0x7f), |
| 874 | aic_le32toh(scb->sg_list[i].addr)((__uint32_t)(scb->sg_list[i].addr)), |
| 875 | aic_le32toh(scb->sg_list[i].len)((__uint32_t)(scb->sg_list[i].len)) |
| 876 | & AHC_SG_LEN_MASK0x00FFFFFF); |
| 877 | } |
| 878 | } |
| 879 | } |
| 880 | #endif |
| 881 | /* |
| 882 | * Set this and it will take effect when the |
| 883 | * target does a command complete. |
| 884 | */ |
| 885 | ahc_freeze_devq(ahc, scb); |
| 886 | if ((scb->flags & SCB_SENSE) == 0) { |
| 887 | ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); |
| 888 | } else { |
| 889 | scb->flags &= ~SCB_SENSE; |
| 890 | ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); |
| 891 | } |
| 892 | ahc_freeze_scb(scb); |
| 893 | |
| 894 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 895 | /* |
| 896 | * Clear the channel in case we return |
| 897 | * to data phase later. |
| 898 | */ |
| 899 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x10|0x02)) ) |
| 900 | ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x10|0x02)) ); |
| 901 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x10|0x02)) ) |
| 902 | ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x10|0x02)) ); |
| 903 | } |
| 904 | if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { |
| 905 | u_int dscommand1; |
| 906 | |
| 907 | /* Ensure HHADDR is 0 for future DMA operations. */ |
| 908 | dscommand1 = ahc_inb(ahc, DSCOMMAND1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x85))); |
| 909 | ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x85), (dscommand1 | 0x01))); |
| 910 | ahc_outb(ahc, HADDR, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88), (0))); |
| 911 | ahc_outb(ahc, DSCOMMAND1, dscommand1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x85), (dscommand1 ))); |
| 912 | } |
| 913 | break; |
| 914 | } |
| 915 | case MKMSG_FAILED0xa1: |
| 916 | { |
| 917 | u_int scbindex; |
| 918 | |
| 919 | printf("%s:%c:%d:%d: Attempt to issue message failed\n", |
| 920 | ahc_name(ahc), devinfo.channel, devinfo.target, |
| 921 | devinfo.lun); |
| 922 | scbindex = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 923 | scb = ahc_lookup_scb(ahc, scbindex); |
| 924 | if (scb != NULL((void *)0)) |
| 925 | /* |
| 926 | * Ensure that we didn't put a second instance of this |
| 927 | * SCB into the QINFIFO. |
| 928 | */ |
| 929 | ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb)((((scb)->hscb->scsiid) & (((((ahc))->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04), |
| 930 | SCB_GET_CHANNEL(ahc, scb)((((ahc)->features & AHC_TWIN) != 0) ? (((((scb)->hscb ->scsiid) & 0x80) != 0) ? 'B' : 'A') : 'A'), |
| 931 | SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f), scb->hscb->tag, |
| 932 | ROLE_INITIATOR, /*status*/0, |
| 933 | SEARCH_REMOVE); |
| 934 | break; |
| 935 | } |
| 936 | case NO_FREE_SCB0xd1: |
| 937 | { |
| 938 | printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); |
| 939 | ahc_dump_card_state(ahc); |
| 940 | panic("for safety"); |
| 941 | break; |
| 942 | } |
| 943 | case SCB_MISMATCH0xc1: |
| 944 | { |
| 945 | u_int scbptr; |
| 946 | |
| 947 | scbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 948 | printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", |
| 949 | scbptr, ahc_inb(ahc, ARG_1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x51))), |
| 950 | ahc->scb_data->hscbs[scbptr].tag); |
| 951 | ahc_dump_card_state(ahc); |
| 952 | panic("for safety"); |
| 953 | break; |
| 954 | } |
| 955 | case OUT_OF_RANGE0xe1: |
| 956 | { |
| 957 | #ifndef SMALL_KERNEL |
| 958 | printf("%s: BTT calculation out of range\n", ahc_name(ahc)); |
| 959 | printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " |
| 960 | "ARG_1 == 0x%x ACCUM = 0x%x\n", |
| 961 | ahc_inb(ahc, SAVED_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3d))), ahc_inb(ahc, SAVED_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3e))), |
| 962 | ahc_inb(ahc, ARG_1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x51))), ahc_inb(ahc, ACCUM)(((ahc)->tag)->read_1(((ahc)->bsh), (0x64)))); |
| 963 | printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " |
| 964 | "SINDEX == 0x%x\n, A == 0x%x\n", |
| 965 | ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))), ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))), |
| 966 | ahc_index_busy_tcl(ahc, |
| 967 | BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),(((((ahc)->tag)->read_1(((ahc)->bsh), (0x3e)))) | (( ((((ahc)->tag)->read_1(((ahc)->bsh), (0x3d)))) & 0xf0) << 4)) |
| 968 | ahc_inb(ahc, SAVED_LUN))(((((ahc)->tag)->read_1(((ahc)->bsh), (0x3e)))) | (( ((((ahc)->tag)->read_1(((ahc)->bsh), (0x3d)))) & 0xf0) << 4))), |
| 969 | ahc_inb(ahc, SINDEX)(((ahc)->tag)->read_1(((ahc)->bsh), (0x65))), |
| 970 | ahc_inb(ahc, ACCUM)(((ahc)->tag)->read_1(((ahc)->bsh), (0x64)))); |
| 971 | printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " |
| 972 | "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", |
| 973 | ahc_inb(ahc, SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x05))), ahc_inb(ahc, SCB_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb9))), |
| 974 | ahc_inb(ahc, SCB_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0xba))), ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))), |
| 975 | ahc_inb(ahc, SCB_CONTROL)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb8)))); |
| 976 | printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", |
| 977 | ahc_inb(ahc, SCSIBUSL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x12))), ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03)))); |
| 978 | #endif |
| 979 | ahc_dump_card_state(ahc); |
| 980 | panic("for safety"); |
| 981 | break; |
| 982 | } |
| 983 | default: |
| 984 | printf("ahc_intr: seqint, " |
| 985 | "intstat == 0x%x, scsisigi = 0x%x\n", |
| 986 | intstat, ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03)))); |
| 987 | break; |
| 988 | } |
| 989 | unpause: |
| 990 | /* |
| 991 | * The sequencer is paused immediately on |
| 992 | * a SEQINT, so we should restart it when |
| 993 | * we're done. |
| 994 | */ |
| 995 | ahc_unpause(ahc); |
| 996 | } |
| 997 | |
| 998 | void |
| 999 | ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) |
| 1000 | { |
| 1001 | u_int scb_index; |
| 1002 | u_int status0; |
| 1003 | u_int status; |
| 1004 | struct scb *scb; |
| 1005 | char cur_channel; |
| 1006 | char intr_channel; |
| 1007 | |
| 1008 | if ((ahc->features & AHC_TWIN) != 0 |
| 1009 | && ((ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))) & SELBUSB0x08) != 0)) |
| 1010 | cur_channel = 'B'; |
| 1011 | else |
| 1012 | cur_channel = 'A'; |
| 1013 | intr_channel = cur_channel; |
| 1014 | |
| 1015 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1016 | status0 = ahc_inb(ahc, SSTAT0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0b))) & IOERR0x08; |
| 1017 | else |
| 1018 | status0 = 0; |
| 1019 | status = ahc_inb(ahc, SSTAT1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0c))) & (SELTO0x80|SCSIRSTI0x20|BUSFREE0x08|SCSIPERR0x04); |
| 1020 | if (status == 0 && status0 == 0) { |
| 1021 | if ((ahc->features & AHC_TWIN) != 0) { |
| 1022 | /* Try the other channel */ |
| 1023 | ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x1f))) ^ 0x08))); |
| 1024 | status = ahc_inb(ahc, SSTAT1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0c))) |
| 1025 | & (SELTO0x80|SCSIRSTI0x20|BUSFREE0x08|SCSIPERR0x04); |
| 1026 | intr_channel = (cur_channel == 'A') ? 'B' : 'A'; |
| 1027 | } |
| 1028 | if (status == 0) { |
| 1029 | printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); |
| 1030 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1031 | ahc_unpause(ahc); |
| 1032 | return; |
| 1033 | } |
| 1034 | } |
| 1035 | |
| 1036 | /* Make sure the sequencer is in a safe location. */ |
| 1037 | ahc_clear_critical_section(ahc); |
| 1038 | |
| 1039 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 1040 | scb = ahc_lookup_scb(ahc, scb_index); |
| 1041 | if (scb != NULL((void *)0) |
| 1042 | && (ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))) & NOT_IDENTIFIED0x80) != 0) |
| 1043 | scb = NULL((void *)0); |
| 1044 | |
| 1045 | if ((ahc->features & AHC_ULTRA2) != 0 |
| 1046 | && (status0 & IOERR0x08) != 0) { |
| 1047 | int now_lvd; |
| 1048 | |
| 1049 | now_lvd = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))) & ENAB400x08; |
| 1050 | printf("%s: Transceiver State Has Changed to %s mode\n", |
| 1051 | ahc_name(ahc), now_lvd ? "LVD" : "SE"); |
| 1052 | ahc_outb(ahc, CLRSINT0, CLRIOERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0b), (0x08)) ); |
| 1053 | /* |
| 1054 | * When transitioning to SE mode, the reset line |
| 1055 | * glitches, triggering an arbitration bug in some |
| 1056 | * Ultra2 controllers. This bug is cleared when we |
| 1057 | * assert the reset line. Since a reset glitch has |
| 1058 | * already occurred with this transition and a |
| 1059 | * transceiver state change is handled just like |
| 1060 | * a bus reset anyway, asserting the reset line |
| 1061 | * ourselves is safe. |
| 1062 | */ |
| 1063 | ahc_reset_channel(ahc, intr_channel, |
| 1064 | /*Initiate Reset*/now_lvd == 0); |
| 1065 | } else if ((status & SCSIRSTI0x20) != 0) { |
| 1066 | printf("%s: Someone reset channel %c\n", |
| 1067 | ahc_name(ahc), intr_channel); |
| 1068 | if (intr_channel != cur_channel) |
| 1069 | ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x1f))) ^ 0x08))); |
| 1070 | ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE0); |
| 1071 | } else if ((status & SCSIPERR0x04) != 0) { |
| 1072 | /* |
| 1073 | * Determine the bus phase and queue an appropriate message. |
| 1074 | * SCSIPERR is latched true as soon as a parity error |
| 1075 | * occurs. If the sequencer acked the transfer that |
| 1076 | * caused the parity error and the currently presented |
| 1077 | * transfer on the bus has correct parity, SCSIPERR will |
| 1078 | * be cleared by CLRSCSIPERR. Use this to determine if |
| 1079 | * we should look at the last phase the sequencer recorded, |
| 1080 | * or the current phase presented on the bus. |
| 1081 | */ |
| 1082 | struct ahc_devinfo devinfo; |
| 1083 | u_int mesg_out; |
| 1084 | u_int curphase; |
| 1085 | u_int errorphase; |
| 1086 | u_int lastphase; |
| 1087 | u_int scsirate; |
| 1088 | u_int i; |
| 1089 | u_int sstat2; |
| 1090 | int silent; |
| 1091 | |
| 1092 | lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 1093 | curphase = ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & PHASE_MASK0xe0; |
| 1094 | sstat2 = ahc_inb(ahc, SSTAT2)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0d))); |
| 1095 | ahc_outb(ahc, CLRSINT1, CLRSCSIPERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x04)) ); |
| 1096 | /* |
| 1097 | * For all phases save DATA, the sequencer won't |
| 1098 | * automatically ack a byte that has a parity error |
| 1099 | * in it. So the only way that the current phase |
| 1100 | * could be 'data-in' is if the parity error is for |
| 1101 | * an already acked byte in the data phase. During |
| 1102 | * synchronous data-in transfers, we may actually |
| 1103 | * ack bytes before latching the current phase in |
| 1104 | * LASTPHASE, leading to the discrepancy between |
| 1105 | * curphase and lastphase. |
| 1106 | */ |
| 1107 | if ((ahc_inb(ahc, SSTAT1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0c))) & SCSIPERR0x04) != 0 |
| 1108 | || curphase == P_DATAIN0x40 || curphase == P_DATAIN_DT0x60) |
| 1109 | errorphase = curphase; |
| 1110 | else |
| 1111 | errorphase = lastphase; |
| 1112 | |
| 1113 | for (i = 0; i < num_phases; i++) { |
| 1114 | if (errorphase == ahc_phase_table[i].phase) |
| 1115 | break; |
| 1116 | } |
| 1117 | mesg_out = ahc_phase_table[i].mesg_out; |
| 1118 | silent = FALSE0; |
| 1119 | if (scb != NULL((void *)0)) { |
| 1120 | if (SCB_IS_SILENT(scb)(((scb)->flags & SCB_SILENT) != 0)) |
| 1121 | silent = TRUE1; |
| 1122 | else |
| 1123 | ahc_print_path(ahc, scb); |
| 1124 | scb->flags |= SCB_TRANSMISSION_ERROR; |
| 1125 | } else |
| 1126 | printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, |
| 1127 | SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))((((((ahc)->tag)->read_1(((ahc)->bsh), (0x3d)))) & ((((ahc)->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04)); |
| 1128 | scsirate = ahc_inb(ahc, SCSIRATE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x04))); |
| 1129 | if (silent == FALSE0) { |
| 1130 | printf("parity error detected %s. " |
| 1131 | "SEQADDR(0x%x) SCSIRATE(0x%x)\n", |
| 1132 | ahc_phase_table[i].phasemsg, |
| 1133 | ahc_inw(ahc, SEQADDR00x62), |
| 1134 | scsirate); |
| 1135 | if ((ahc->features & AHC_DT) != 0) { |
| 1136 | if ((sstat2 & CRCVALERR0x08) != 0) |
| 1137 | printf("\tCRC Value Mismatch\n"); |
| 1138 | if ((sstat2 & CRCENDERR0x04) != 0) |
| 1139 | printf("\tNo terminal CRC packet " |
| 1140 | "received\n"); |
| 1141 | if ((sstat2 & CRCREQERR0x02) != 0) |
| 1142 | printf("\tIllegal CRC packet " |
| 1143 | "request\n"); |
| 1144 | if ((sstat2 & DUAL_EDGE_ERR0x01) != 0) |
| 1145 | printf("\tUnexpected %sDT Data Phase\n", |
| 1146 | (scsirate & SINGLE_EDGE0x10) |
| 1147 | ? "" : "non-"); |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | if ((ahc->features & AHC_DT) != 0 |
| 1152 | && (sstat2 & DUAL_EDGE_ERR0x01) != 0) { |
| 1153 | /* |
| 1154 | * This error applies regardless of |
| 1155 | * data direction, so ignore the value |
| 1156 | * in the phase table. |
| 1157 | */ |
| 1158 | mesg_out = MSG_INITIATOR_DET_ERR0x05; |
| 1159 | } |
| 1160 | |
| 1161 | /* |
| 1162 | * We've set the hardware to assert ATN if we |
| 1163 | * get a parity error on "in" phases, so all we |
| 1164 | * need to do is stuff the message buffer with |
| 1165 | * the appropriate message. "In" phases have set |
| 1166 | * mesg_out to something other than MSG_NOP. |
| 1167 | */ |
| 1168 | if (mesg_out != MSG_NOOP0x08) { |
| 1169 | if (ahc->msg_type != MSG_TYPE_NONE) |
| 1170 | ahc->send_msg_perror = TRUE1; |
| 1171 | else |
| 1172 | ahc_outb(ahc, MSG_OUT, mesg_out)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (mesg_out ))); |
| 1173 | } |
| 1174 | /* |
| 1175 | * Force a renegotiation with this target just in |
| 1176 | * case we are out of sync for some external reason |
| 1177 | * unknown (or unreported) by the target. |
| 1178 | */ |
| 1179 | ahc_fetch_devinfo(ahc, &devinfo); |
| 1180 | ahc_force_renegotiation(ahc, &devinfo); |
| 1181 | |
| 1182 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1183 | ahc_unpause(ahc); |
| 1184 | } else if ((status & SELTO0x80) != 0) { |
| 1185 | u_int scbptr; |
| 1186 | |
| 1187 | /* Stop the selection */ |
| 1188 | ahc_outb(ahc, SCSISEQ, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (0))); |
| 1189 | |
| 1190 | /* No more pending messages */ |
| 1191 | ahc_clear_msg_state(ahc); |
| 1192 | |
| 1193 | /* Clear interrupt state */ |
| 1194 | ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x11))) & ~0x08)) ); |
| 1195 | ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x80|0x08 |0x04))); |
| 1196 | |
| 1197 | /* |
| 1198 | * Although the driver does not care about the |
| 1199 | * 'Selection in Progress' status bit, the busy |
| 1200 | * LED does. SELINGO is only cleared by a successful |
| 1201 | * selection, so we must manually clear it to insure |
| 1202 | * the LED turns off just incase no future successful |
| 1203 | * selections occur (e.g. no devices on the bus). |
| 1204 | */ |
| 1205 | ahc_outb(ahc, CLRSINT0, CLRSELINGO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0b), (0x10)) ); |
| 1206 | |
| 1207 | scbptr = ahc_inb(ahc, WAITING_SCBH)(((ahc)->tag)->read_1(((ahc)->bsh), (0x40))); |
| 1208 | ahc_outb(ahc, SCBPTR, scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (scbptr ))); |
| 1209 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 1210 | |
| 1211 | scb = ahc_lookup_scb(ahc, scb_index); |
| 1212 | if (scb == NULL((void *)0)) { |
| 1213 | printf("%s: ahc_intr - referenced scb not " |
| 1214 | "valid during SELTO scb(%d, %d)\n", |
| 1215 | ahc_name(ahc), scbptr, scb_index); |
| 1216 | ahc_dump_card_state(ahc); |
| 1217 | } else { |
| 1218 | struct ahc_devinfo devinfo; |
| 1219 | #ifdef AHC_DEBUG |
| 1220 | if ((ahc_debug & AHC_SHOW_SELTO) != 0) { |
| 1221 | ahc_print_path(ahc, scb); |
| 1222 | printf("Saw Selection Timeout for SCB 0x%x\n", |
| 1223 | scb_index); |
| 1224 | } |
| 1225 | #endif |
| 1226 | ahc_scb_devinfo(ahc, &devinfo, scb); |
| 1227 | ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); |
| 1228 | ahc_freeze_devq(ahc, scb); |
| 1229 | |
| 1230 | /* |
| 1231 | * Cancel any pending transactions on the device |
| 1232 | * now that it seems to be missing. This will |
| 1233 | * also revert us to async/narrow transfers until |
| 1234 | * we can renegotiate with the device. |
| 1235 | */ |
| 1236 | ahc_handle_devreset(ahc, &devinfo, |
| 1237 | CAM_SEL_TIMEOUT, |
| 1238 | "Selection Timeout", |
| 1239 | /*verbose_level*/1); |
| 1240 | } |
| 1241 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1242 | ahc_restart(ahc); |
| 1243 | } else if ((status & BUSFREE0x08) != 0 |
| 1244 | && (ahc_inb(ahc, SIMODE1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x11))) & ENBUSFREE0x08) != 0) { |
| 1245 | struct ahc_devinfo devinfo; |
| 1246 | u_int lastphase; |
| 1247 | u_int saved_scsiid; |
| 1248 | u_int saved_lun; |
| 1249 | u_int target; |
| 1250 | u_int initiator_role_id; |
| 1251 | char channel; |
| 1252 | int printerror; |
| 1253 | |
| 1254 | /* |
| 1255 | * Clear our selection hardware as soon as possible. |
| 1256 | * We may have an entry in the waiting Q for this target, |
| 1257 | * that is affected by this busfree and we don't want to |
| 1258 | * go about selecting the target while we handle the event. |
| 1259 | */ |
| 1260 | ahc_outb(ahc, SCSISEQ,(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & (0x20|0x10 |0x02)))) |
| 1261 | ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & (0x20|0x10 |0x02)))); |
| 1262 | |
| 1263 | /* |
| 1264 | * Disable busfree interrupts and clear the busfree |
| 1265 | * interrupt status. We do this here so that several |
| 1266 | * bus transactions occur prior to clearing the SCSIINT |
| 1267 | * latch. It can take a bit for the clearing to take effect. |
| 1268 | */ |
| 1269 | ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x11))) & ~0x08)) ); |
| 1270 | ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x08|0x04 ))); |
| 1271 | |
| 1272 | /* |
| 1273 | * Look at what phase we were last in. |
| 1274 | * If its message out, chances are pretty good |
| 1275 | * that the busfree was in response to one of |
| 1276 | * our abort requests. |
| 1277 | */ |
| 1278 | lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 1279 | saved_scsiid = ahc_inb(ahc, SAVED_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3d))); |
| 1280 | saved_lun = ahc_inb(ahc, SAVED_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3e))); |
| 1281 | target = SCSIID_TARGET(ahc, saved_scsiid)(((saved_scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04); |
| 1282 | initiator_role_id = SCSIID_OUR_ID(saved_scsiid)((saved_scsiid) & 0x0f); |
| 1283 | channel = SCSIID_CHANNEL(ahc, saved_scsiid)((((ahc)->features & AHC_TWIN) != 0) ? ((((saved_scsiid ) & 0x80) != 0) ? 'B' : 'A') : 'A'); |
| 1284 | ahc_compile_devinfo(&devinfo, initiator_role_id, |
| 1285 | target, saved_lun, channel, ROLE_INITIATOR); |
| 1286 | printerror = 1; |
| 1287 | |
| 1288 | if (lastphase == P_MESGOUT0xa0) { |
| 1289 | u_int tag; |
| 1290 | |
| 1291 | tag = SCB_LIST_NULL0xff; |
| 1292 | if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG0x0d, TRUE1) |
| 1293 | || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT0x06, TRUE1)) { |
| 1294 | if (ahc->msgout_buf[ahc->msgout_index - 1] |
| 1295 | == MSG_ABORT_TAG0x0d) |
| 1296 | tag = scb->hscb->tag; |
| 1297 | ahc_print_path(ahc, scb); |
| 1298 | printf("SCB %d - Abort%s Completed.\n", |
| 1299 | scb->hscb->tag, tag == SCB_LIST_NULL0xff ? |
| 1300 | "" : " Tag"); |
| 1301 | ahc_abort_scbs(ahc, target, channel, |
| 1302 | saved_lun, tag, |
| 1303 | ROLE_INITIATOR, |
| 1304 | CAM_REQ_ABORTED); |
| 1305 | printerror = 0; |
| 1306 | } else if (ahc_sent_msg(ahc, AHCMSG_1B, |
| 1307 | MSG_BUS_DEV_RESET0x0c, TRUE1)) { |
| 1308 | #ifdef __FreeBSD__ |
| 1309 | /* |
| 1310 | * Don't mark the user's request for this BDR |
| 1311 | * as completing with CAM_BDR_SENT. CAM3 |
| 1312 | * specifies CAM_REQ_CMP. |
| 1313 | */ |
| 1314 | if (scb != NULL((void *)0) |
| 1315 | && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV |
| 1316 | && ahc_match_scb(ahc, scb, target, channel, |
| 1317 | CAM_LUN_WILDCARD-1, |
| 1318 | SCB_LIST_NULL0xff, |
| 1319 | ROLE_INITIATOR)) { |
| 1320 | ahc_set_transaction_status(scb, CAM_REQ_CMP); |
| 1321 | } |
| 1322 | #endif |
| 1323 | ahc_compile_devinfo(&devinfo, |
| 1324 | initiator_role_id, |
| 1325 | target, |
| 1326 | CAM_LUN_WILDCARD-1, |
| 1327 | channel, |
| 1328 | ROLE_INITIATOR); |
| 1329 | ahc_handle_devreset(ahc, &devinfo, |
| 1330 | CAM_BDR_SENT, |
| 1331 | "Bus Device Reset", |
| 1332 | /*verbose_level*/0); |
| 1333 | printerror = 0; |
| 1334 | } else if (ahc_sent_msg(ahc, AHCMSG_EXT, |
| 1335 | MSG_EXT_PPR0x04, FALSE0)) { |
| 1336 | struct ahc_initiator_tinfo *tinfo; |
| 1337 | struct ahc_tmode_tstate *tstate; |
| 1338 | |
| 1339 | /* |
| 1340 | * PPR Rejected. Try non-ppr negotiation |
| 1341 | * and retry command. |
| 1342 | */ |
| 1343 | tinfo = ahc_fetch_transinfo(ahc, |
| 1344 | devinfo.channel, |
| 1345 | devinfo.our_scsiid, |
| 1346 | devinfo.target, |
| 1347 | &tstate); |
| 1348 | tinfo->curr.transport_version = 2; |
| 1349 | tinfo->goal.transport_version = 2; |
| 1350 | tinfo->goal.ppr_options = 0; |
| 1351 | ahc_qinfifo_requeue_tail(ahc, scb); |
| 1352 | printerror = 0; |
| 1353 | } else if (ahc_sent_msg(ahc, AHCMSG_EXT, |
| 1354 | MSG_EXT_WDTR0x03, FALSE0)) { |
| 1355 | /* |
| 1356 | * Negotiation Rejected. Go-narrow and |
| 1357 | * retry command. |
| 1358 | */ |
| 1359 | ahc_set_width(ahc, &devinfo, |
| 1360 | MSG_EXT_WDTR_BUS_8_BIT0x00, |
| 1361 | AHC_TRANS_CUR0x01|AHC_TRANS_GOAL0x04, |
| 1362 | /*paused*/TRUE1); |
| 1363 | ahc_qinfifo_requeue_tail(ahc, scb); |
| 1364 | printerror = 0; |
| 1365 | } else if (ahc_sent_msg(ahc, AHCMSG_EXT, |
| 1366 | MSG_EXT_SDTR0x01, FALSE0)) { |
| 1367 | /* |
| 1368 | * Negotiation Rejected. Go-async and |
| 1369 | * retry command. |
| 1370 | */ |
| 1371 | ahc_set_syncrate(ahc, &devinfo, |
| 1372 | /*syncrate*/NULL((void *)0), |
| 1373 | /*period*/0, /*offset*/0, |
| 1374 | /*ppr_options*/0, |
| 1375 | AHC_TRANS_CUR0x01|AHC_TRANS_GOAL0x04, |
| 1376 | /*paused*/TRUE1); |
| 1377 | ahc_qinfifo_requeue_tail(ahc, scb); |
| 1378 | printerror = 0; |
| 1379 | } |
| 1380 | } |
| 1381 | if (printerror != 0) { |
| 1382 | u_int i; |
| 1383 | |
| 1384 | if (scb != NULL((void *)0)) { |
| 1385 | u_int tag; |
| 1386 | |
| 1387 | if ((scb->hscb->control & TAG_ENB0x20) != 0) |
| 1388 | tag = scb->hscb->tag; |
| 1389 | else |
| 1390 | tag = SCB_LIST_NULL0xff; |
| 1391 | ahc_print_path(ahc, scb); |
| 1392 | ahc_abort_scbs(ahc, target, channel, |
| 1393 | SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f), tag, |
| 1394 | ROLE_INITIATOR, |
| 1395 | CAM_UNEXP_BUSFREE); |
| 1396 | } else { |
| 1397 | /* |
| 1398 | * We had not fully identified this connection, |
| 1399 | * so we cannot abort anything. |
| 1400 | */ |
| 1401 | printf("%s: ", ahc_name(ahc)); |
| 1402 | } |
| 1403 | for (i = 0; i < num_phases; i++) { |
| 1404 | if (lastphase == ahc_phase_table[i].phase) |
| 1405 | break; |
| 1406 | } |
| 1407 | if (lastphase != P_BUSFREE0x01) { |
| 1408 | /* |
| 1409 | * Renegotiate with this device at the |
| 1410 | * next opportunity just in case this busfree |
| 1411 | * is due to a negotiation mismatch with the |
| 1412 | * device. |
| 1413 | */ |
| 1414 | ahc_force_renegotiation(ahc, &devinfo); |
| 1415 | } |
| 1416 | printf("Unexpected busfree %s\n" |
| 1417 | "SEQADDR == 0x%x\n", |
| 1418 | ahc_phase_table[i].phasemsg, |
| 1419 | ahc_inb(ahc, SEQADDR0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x62))) |
| 1420 | | (ahc_inb(ahc, SEQADDR1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x63))) << 8)); |
| 1421 | } |
| 1422 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1423 | ahc_restart(ahc); |
| 1424 | } else { |
| 1425 | printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", |
| 1426 | ahc_name(ahc), status); |
| 1427 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1428 | } |
| 1429 | } |
| 1430 | |
| 1431 | /* |
| 1432 | * Force renegotiation to occur the next time we initiate |
| 1433 | * a command to the current device. |
| 1434 | */ |
| 1435 | void |
| 1436 | ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 1437 | { |
| 1438 | struct ahc_initiator_tinfo *targ_info; |
| 1439 | struct ahc_tmode_tstate *tstate; |
| 1440 | |
| 1441 | targ_info = ahc_fetch_transinfo(ahc, |
| 1442 | devinfo->channel, |
| 1443 | devinfo->our_scsiid, |
| 1444 | devinfo->target, |
| 1445 | &tstate); |
| 1446 | ahc_update_neg_request(ahc, devinfo, tstate, |
| 1447 | targ_info, AHC_NEG_IF_NON_ASYNC); |
| 1448 | } |
| 1449 | |
| 1450 | #define AHC_MAX_STEPS2000 2000 |
| 1451 | void |
| 1452 | ahc_clear_critical_section(struct ahc_softc *ahc) |
| 1453 | { |
| 1454 | int stepping; |
| 1455 | int steps; |
| 1456 | u_int simode0; |
| 1457 | u_int simode1; |
| 1458 | |
| 1459 | if (ahc->num_critical_sections == 0) |
| 1460 | return; |
| 1461 | |
| 1462 | stepping = FALSE0; |
| 1463 | steps = 0; |
| 1464 | simode0 = 0; |
| 1465 | simode1 = 0; |
| 1466 | for (;;) { |
| 1467 | struct cs *cs; |
| 1468 | u_int seqaddr; |
| 1469 | u_int i; |
| 1470 | |
| 1471 | seqaddr = ahc_inb(ahc, SEQADDR0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x62))) |
| 1472 | | (ahc_inb(ahc, SEQADDR1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x63))) << 8); |
| 1473 | |
| 1474 | /* |
| 1475 | * Seqaddr represents the next instruction to execute, |
| 1476 | * so we are really executing the instruction just |
| 1477 | * before it. |
| 1478 | */ |
| 1479 | cs = ahc->critical_sections; |
| 1480 | for (i = 0; i < ahc->num_critical_sections; i++, cs++) { |
| 1481 | |
| 1482 | if (cs->begin < seqaddr && cs->end >= seqaddr) |
| 1483 | break; |
| 1484 | } |
| 1485 | |
| 1486 | if (i == ahc->num_critical_sections) |
| 1487 | break; |
| 1488 | |
| 1489 | if (steps > AHC_MAX_STEPS2000) { |
| 1490 | printf("%s: Infinite loop in critical section\n", |
| 1491 | ahc_name(ahc)); |
| 1492 | ahc_dump_card_state(ahc); |
| 1493 | panic("critical section loop"); |
| 1494 | } |
| 1495 | |
| 1496 | steps++; |
| 1497 | if (stepping == FALSE0) { |
| 1498 | |
| 1499 | /* |
| 1500 | * Disable all interrupt sources so that the |
| 1501 | * sequencer will not be stuck by a pausing |
| 1502 | * interrupt condition while we attempt to |
| 1503 | * leave a critical section. |
| 1504 | */ |
| 1505 | simode0 = ahc_inb(ahc, SIMODE0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x10))); |
| 1506 | ahc_outb(ahc, SIMODE0, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x10), (0))); |
| 1507 | simode1 = ahc_inb(ahc, SIMODE1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x11))); |
| 1508 | if ((ahc->features & AHC_DT) != 0) |
| 1509 | /* |
| 1510 | * On DT class controllers, we |
| 1511 | * use the enhanced busfree logic. |
| 1512 | * Unfortunately we cannot re-enable |
| 1513 | * busfree detection within the |
| 1514 | * current connection, so we must |
| 1515 | * leave it on while single stepping. |
| 1516 | */ |
| 1517 | ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (simode1 & 0x08))); |
| 1518 | else |
| 1519 | ahc_outb(ahc, SIMODE1, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (0))); |
| 1520 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1521 | ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (ahc-> seqctl | 0x04))); |
| 1522 | stepping = TRUE1; |
| 1523 | } |
| 1524 | if ((ahc->features & AHC_DT) != 0) { |
| 1525 | ahc_outb(ahc, CLRSINT1, CLRBUSFREE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x08)) ); |
| 1526 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1527 | } |
| 1528 | ahc_outb(ahc, HCNTRL, ahc->unpause)(((ahc)->tag)->write_1(((ahc)->bsh), (0x87), (ahc-> unpause))); |
| 1529 | while (!ahc_is_paused(ahc)) |
| 1530 | aic_delay(200)(*delay_func)(200); |
| 1531 | } |
| 1532 | if (stepping) { |
| 1533 | ahc_outb(ahc, SIMODE0, simode0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x10), (simode0 ))); |
| 1534 | ahc_outb(ahc, SIMODE1, simode1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (simode1 ))); |
| 1535 | ahc_outb(ahc, SEQCTL, ahc->seqctl)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (ahc-> seqctl))); |
| 1536 | } |
| 1537 | } |
| 1538 | |
| 1539 | /* |
| 1540 | * Clear any pending interrupt status. |
| 1541 | */ |
| 1542 | void |
| 1543 | ahc_clear_intstat(struct ahc_softc *ahc) |
| 1544 | { |
| 1545 | /* Clear any interrupt conditions this may have caused */ |
| 1546 | ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x80|0x40 |0x20 |0x08|0x04|0x02| 0x01))) |
| 1547 | |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x80|0x40 |0x20 |0x08|0x04|0x02| 0x01))) |
| 1548 | CLRREQINIT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x80|0x40 |0x20 |0x08|0x04|0x02| 0x01))); |
| 1549 | ahc_flush_device_writes(ahc); |
| 1550 | ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0b), (0x40|0x20 |0x10))); |
| 1551 | ahc_flush_device_writes(ahc); |
| 1552 | ahc_outb(ahc, CLRINT, CLRSCSIINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x04)) ); |
| 1553 | ahc_flush_device_writes(ahc); |
| 1554 | } |
| 1555 | |
| 1556 | /**************************** Debugging Routines ******************************/ |
| 1557 | #ifdef AHC_DEBUG |
| 1558 | uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ |
| 1559 | |
| 1560 | void |
| 1561 | ahc_print_scb(struct scb *scb) |
| 1562 | { |
| 1563 | int i; |
| 1564 | |
| 1565 | struct hardware_scb *hscb = scb->hscb; |
| 1566 | |
| 1567 | printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", |
| 1568 | (void *)scb, |
| 1569 | hscb->control, |
| 1570 | hscb->scsiid, |
| 1571 | hscb->lun, |
| 1572 | hscb->cdb_len); |
| 1573 | printf("Shared Data: "); |
| 1574 | for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) |
| 1575 | printf("%#02x", hscb->shared_data.cdb[i]); |
| 1576 | printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", |
| 1577 | aic_le32toh(hscb->dataptr)((__uint32_t)(hscb->dataptr)), |
| 1578 | aic_le32toh(hscb->datacnt)((__uint32_t)(hscb->datacnt)), |
| 1579 | aic_le32toh(hscb->sgptr)((__uint32_t)(hscb->sgptr)), |
| 1580 | hscb->tag); |
| 1581 | if (scb->sg_count > 0) { |
| 1582 | for (i = 0; i < scb->sg_count; i++) { |
| 1583 | printf("sg[%d] - Addr 0x%x%x : Length %d\n", |
| 1584 | i, |
| 1585 | (aic_le32toh(scb->sg_list[i].len)((__uint32_t)(scb->sg_list[i].len)) >> 24 |
| 1586 | & SG_HIGH_ADDR_BITS0x7f), |
| 1587 | aic_le32toh(scb->sg_list[i].addr)((__uint32_t)(scb->sg_list[i].addr)), |
| 1588 | aic_le32toh(scb->sg_list[i].len)((__uint32_t)(scb->sg_list[i].len))); |
| 1589 | } |
| 1590 | } |
| 1591 | } |
| 1592 | #endif |
| 1593 | |
| 1594 | /************************* Transfer Negotiation *******************************/ |
| 1595 | /* |
| 1596 | * Allocate per target mode instance (ID we respond to as a target) |
| 1597 | * transfer negotiation data structures. |
| 1598 | */ |
| 1599 | static struct ahc_tmode_tstate * |
| 1600 | ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) |
| 1601 | { |
| 1602 | struct ahc_tmode_tstate *master_tstate; |
| 1603 | struct ahc_tmode_tstate *tstate; |
| 1604 | int i; |
| 1605 | |
| 1606 | master_tstate = ahc->enabled_targets[ahc->our_id]; |
| 1607 | if (channel == 'B') { |
| 1608 | scsi_id += 8; |
| 1609 | master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; |
| 1610 | } |
| 1611 | if (ahc->enabled_targets[scsi_id] != NULL((void *)0) |
| 1612 | && ahc->enabled_targets[scsi_id] != master_tstate) |
| 1613 | panic("%s: ahc_alloc_tstate - Target already allocated", |
| 1614 | ahc_name(ahc)); |
| 1615 | tstate = malloc(sizeof(*tstate), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008); |
| 1616 | if (tstate == NULL((void *)0)) |
| 1617 | return (NULL((void *)0)); |
| 1618 | |
| 1619 | /* |
| 1620 | * If we have allocated a master tstate, copy user settings from |
| 1621 | * the master tstate (taken from SRAM or the EEPROM) for this |
| 1622 | * channel, but reset our current and goal settings to async/narrow |
| 1623 | * until an initiator talks to us. |
| 1624 | */ |
| 1625 | if (master_tstate != NULL((void *)0)) { |
| 1626 | memcpy(tstate, master_tstate, sizeof(*tstate))__builtin_memcpy((tstate), (master_tstate), (sizeof(*tstate)) ); |
| 1627 | memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns))__builtin_memset((tstate->enabled_luns), (0), (sizeof(tstate ->enabled_luns))); |
| 1628 | tstate->ultraenb = 0; |
| 1629 | for (i = 0; i < AHC_NUM_TARGETS16; i++) { |
| 1630 | memset(&tstate->transinfo[i].curr, 0,__builtin_memset((&tstate->transinfo[i].curr), (0), (sizeof (tstate->transinfo[i].curr))) |
| 1631 | sizeof(tstate->transinfo[i].curr))__builtin_memset((&tstate->transinfo[i].curr), (0), (sizeof (tstate->transinfo[i].curr))); |
| 1632 | memset(&tstate->transinfo[i].goal, 0,__builtin_memset((&tstate->transinfo[i].goal), (0), (sizeof (tstate->transinfo[i].goal))) |
| 1633 | sizeof(tstate->transinfo[i].goal))__builtin_memset((&tstate->transinfo[i].goal), (0), (sizeof (tstate->transinfo[i].goal))); |
| 1634 | } |
| 1635 | } |
| 1636 | ahc->enabled_targets[scsi_id] = tstate; |
| 1637 | return (tstate); |
| 1638 | } |
| 1639 | |
| 1640 | #ifdef AHC_TARGET_MODE |
| 1641 | /* |
| 1642 | * Free per target mode instance (ID we respond to as a target) |
| 1643 | * transfer negotiation data structures. |
| 1644 | */ |
| 1645 | static void |
| 1646 | ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) |
| 1647 | { |
| 1648 | struct ahc_tmode_tstate *tstate; |
| 1649 | |
| 1650 | /* |
| 1651 | * Don't clean up our "master" tstate. |
| 1652 | * It has our default user settings. |
| 1653 | */ |
| 1654 | if (((channel == 'B' && scsi_id == ahc->our_id_b) |
| 1655 | || (channel == 'A' && scsi_id == ahc->our_id)) |
| 1656 | && force == FALSE0) |
| 1657 | return; |
| 1658 | |
| 1659 | if (channel == 'B') |
| 1660 | scsi_id += 8; |
| 1661 | tstate = ahc->enabled_targets[scsi_id]; |
| 1662 | if (tstate != NULL((void *)0)) |
| 1663 | free(tstate, M_DEVBUF2, sizeof(*tstate)); |
| 1664 | ahc->enabled_targets[scsi_id] = NULL((void *)0); |
| 1665 | } |
| 1666 | #endif |
| 1667 | |
| 1668 | /* |
| 1669 | * Called when we have an active connection to a target on the bus, |
| 1670 | * this function finds the nearest syncrate to the input period limited |
| 1671 | * by the capabilities of the bus connectivity of and sync settings for |
| 1672 | * the target. |
| 1673 | */ |
| 1674 | struct ahc_syncrate * |
| 1675 | ahc_devlimited_syncrate(struct ahc_softc *ahc, |
| 1676 | struct ahc_initiator_tinfo *tinfo, |
| 1677 | u_int *period, u_int *ppr_options, role_t role) |
| 1678 | { |
| 1679 | struct ahc_transinfo *transinfo; |
| 1680 | u_int maxsync; |
| 1681 | |
| 1682 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1683 | if ((ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))) & ENAB400x08) != 0 |
| 1684 | && (ahc_inb(ahc, SSTAT2)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0d))) & EXP_ACTIVE0x10) == 0) { |
| 1685 | maxsync = AHC_SYNCRATE_DT0; |
| 1686 | } else { |
| 1687 | maxsync = AHC_SYNCRATE_ULTRA3; |
| 1688 | /* Can't do DT on an SE bus */ |
| 1689 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ0x02; |
| 1690 | } |
| 1691 | } else if ((ahc->features & AHC_ULTRA) != 0) { |
| 1692 | maxsync = AHC_SYNCRATE_ULTRA3; |
| 1693 | } else { |
| 1694 | maxsync = AHC_SYNCRATE_FAST6; |
| 1695 | } |
| 1696 | /* |
| 1697 | * Never allow a value higher than our current goal |
| 1698 | * period otherwise we may allow a target initiated |
| 1699 | * negotiation to go above the limit as set by the |
| 1700 | * user. In the case of an initiator initiated |
| 1701 | * sync negotiation, we limit based on the user |
| 1702 | * setting. This allows the system to still accept |
| 1703 | * incoming negotiations even if target initiated |
| 1704 | * negotiation is not performed. |
| 1705 | */ |
| 1706 | if (role == ROLE_TARGET) |
| 1707 | transinfo = &tinfo->user; |
| 1708 | else |
| 1709 | transinfo = &tinfo->goal; |
| 1710 | *ppr_options &= transinfo->ppr_options; |
| 1711 | if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT0x00) { |
| 1712 | maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2)(((maxsync)>(1))?(maxsync):(1)); |
| 1713 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ0x02; |
| 1714 | } |
| 1715 | if (transinfo->period == 0) { |
| 1716 | *period = 0; |
| 1717 | *ppr_options = 0; |
| 1718 | return (NULL((void *)0)); |
| 1719 | } |
| 1720 | *period = MAX(*period, transinfo->period)(((*period)>(transinfo->period))?(*period):(transinfo-> period)); |
| 1721 | return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); |
| 1722 | } |
| 1723 | |
| 1724 | /* |
| 1725 | * Look up the valid period to SCSIRATE conversion in our table. |
| 1726 | * Return the period and offset that should be sent to the target |
| 1727 | * if this was the beginning of an SDTR. |
| 1728 | */ |
| 1729 | struct ahc_syncrate * |
| 1730 | ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, |
| 1731 | u_int *ppr_options, u_int maxsync) |
| 1732 | { |
| 1733 | struct ahc_syncrate *syncrate; |
| 1734 | |
| 1735 | if ((ahc->features & AHC_DT) == 0) |
| 1736 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ0x02; |
| 1737 | |
| 1738 | /* Skip all DT only entries if DT is not available */ |
| 1739 | if ((*ppr_options & MSG_EXT_PPR_DT_REQ0x02) == 0 |
| 1740 | && maxsync < AHC_SYNCRATE_ULTRA21) |
| 1741 | maxsync = AHC_SYNCRATE_ULTRA21; |
| 1742 | |
| 1743 | for (syncrate = &ahc_syncrates[maxsync]; |
| 1744 | syncrate->rate != NULL((void *)0); |
| 1745 | syncrate++) { |
| 1746 | |
| 1747 | /* |
| 1748 | * The Ultra2 table doesn't go as low |
| 1749 | * as for the Fast/Ultra cards. |
| 1750 | */ |
| 1751 | if ((ahc->features & AHC_ULTRA2) != 0 |
| 1752 | && (syncrate->sxfr_u2 == 0)) |
| 1753 | break; |
| 1754 | |
| 1755 | if (*period <= syncrate->period) { |
| 1756 | /* |
| 1757 | * When responding to a target that requests |
| 1758 | * sync, the requested rate may fall between |
| 1759 | * two rates that we can output, but still be |
| 1760 | * a rate that we can receive. Because of this, |
| 1761 | * we want to respond to the target with |
| 1762 | * the same rate that it sent to us even |
| 1763 | * if the period we use to send data to it |
| 1764 | * is lower. Only lower the response period |
| 1765 | * if we must. |
| 1766 | */ |
| 1767 | if (syncrate == &ahc_syncrates[maxsync]) |
| 1768 | *period = syncrate->period; |
| 1769 | |
| 1770 | /* |
| 1771 | * At some speeds, we only support |
| 1772 | * ST transfers. |
| 1773 | */ |
| 1774 | if ((syncrate->sxfr_u2 & ST_SXFR0x010) != 0) |
| 1775 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ0x02; |
| 1776 | break; |
| 1777 | } |
| 1778 | } |
| 1779 | |
| 1780 | if ((*period == 0) |
| 1781 | || (syncrate->rate == NULL((void *)0)) |
| 1782 | || ((ahc->features & AHC_ULTRA2) != 0 |
| 1783 | && (syncrate->sxfr_u2 == 0))) { |
| 1784 | /* Use asynchronous transfers. */ |
| 1785 | *period = 0; |
| 1786 | syncrate = NULL((void *)0); |
| 1787 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ0x02; |
| 1788 | } |
| 1789 | return (syncrate); |
| 1790 | } |
| 1791 | |
| 1792 | /* |
| 1793 | * Convert from an entry in our syncrate table to the SCSI equivalent |
| 1794 | * sync "period" factor. |
| 1795 | */ |
| 1796 | u_int |
| 1797 | ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) |
| 1798 | { |
| 1799 | struct ahc_syncrate *syncrate; |
| 1800 | |
| 1801 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1802 | scsirate &= SXFR_ULTRA20x0f; |
| 1803 | else |
| 1804 | scsirate &= SXFR0x70; |
| 1805 | |
| 1806 | syncrate = &ahc_syncrates[maxsync]; |
| 1807 | while (syncrate->rate != NULL((void *)0)) { |
| 1808 | |
| 1809 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1810 | if (syncrate->sxfr_u2 == 0) |
| 1811 | break; |
| 1812 | else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA20x0f)) |
| 1813 | return (syncrate->period); |
| 1814 | } else if (scsirate == (syncrate->sxfr & SXFR0x70)) { |
| 1815 | return (syncrate->period); |
| 1816 | } |
| 1817 | syncrate++; |
| 1818 | } |
| 1819 | return (0); /* async */ |
| 1820 | } |
| 1821 | |
| 1822 | /* |
| 1823 | * Truncate the given synchronous offset to a value the |
| 1824 | * current adapter type and syncrate are capable of. |
| 1825 | */ |
| 1826 | void |
| 1827 | ahc_validate_offset(struct ahc_softc *ahc, |
| 1828 | struct ahc_initiator_tinfo *tinfo, |
| 1829 | struct ahc_syncrate *syncrate, |
| 1830 | u_int *offset, int wide, role_t role) |
| 1831 | { |
| 1832 | u_int maxoffset; |
| 1833 | |
| 1834 | /* Limit offset to what we can do */ |
| 1835 | if (syncrate == NULL((void *)0)) { |
| 1836 | maxoffset = 0; |
| 1837 | } else if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1838 | maxoffset = MAX_OFFSET_ULTRA20x7f; |
| 1839 | } else { |
| 1840 | if (wide) |
| 1841 | maxoffset = MAX_OFFSET_16BIT0x08; |
| 1842 | else |
| 1843 | maxoffset = MAX_OFFSET_8BIT0x0f; |
| 1844 | } |
| 1845 | *offset = MIN(*offset, maxoffset)(((*offset)<(maxoffset))?(*offset):(maxoffset)); |
| 1846 | if (tinfo != NULL((void *)0)) { |
| 1847 | if (role == ROLE_TARGET) |
| 1848 | *offset = MIN(*offset, tinfo->user.offset)(((*offset)<(tinfo->user.offset))?(*offset):(tinfo-> user.offset)); |
| 1849 | else |
| 1850 | *offset = MIN(*offset, tinfo->goal.offset)(((*offset)<(tinfo->goal.offset))?(*offset):(tinfo-> goal.offset)); |
| 1851 | } |
| 1852 | } |
| 1853 | |
| 1854 | /* |
| 1855 | * Truncate the given transfer width parameter to a value the |
| 1856 | * current adapter type is capable of. |
| 1857 | */ |
| 1858 | void |
| 1859 | ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, |
| 1860 | u_int *bus_width, role_t role) |
| 1861 | { |
| 1862 | switch (*bus_width) { |
| 1863 | default: |
| 1864 | if (ahc->features & AHC_WIDE) { |
| 1865 | /* Respond Wide */ |
| 1866 | *bus_width = MSG_EXT_WDTR_BUS_16_BIT0x01; |
| 1867 | break; |
| 1868 | } |
| 1869 | /* FALLTHROUGH */ |
| 1870 | case MSG_EXT_WDTR_BUS_8_BIT0x00: |
| 1871 | *bus_width = MSG_EXT_WDTR_BUS_8_BIT0x00; |
| 1872 | break; |
| 1873 | } |
| 1874 | if (tinfo != NULL((void *)0)) { |
| 1875 | if (role == ROLE_TARGET) |
| 1876 | *bus_width = MIN(tinfo->user.width, *bus_width)(((tinfo->user.width)<(*bus_width))?(tinfo->user.width ):(*bus_width)); |
| 1877 | else |
| 1878 | *bus_width = MIN(tinfo->goal.width, *bus_width)(((tinfo->goal.width)<(*bus_width))?(tinfo->goal.width ):(*bus_width)); |
| 1879 | } |
| 1880 | } |
| 1881 | |
| 1882 | /* |
| 1883 | * Update the bitmask of targets for which the controller should |
| 1884 | * negotiate with at the next convenient opportunity. This currently |
| 1885 | * means the next time we send the initial identify messages for |
| 1886 | * a new transaction. |
| 1887 | */ |
| 1888 | int |
| 1889 | ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 1890 | struct ahc_tmode_tstate *tstate, |
| 1891 | struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) |
| 1892 | { |
| 1893 | u_int auto_negotiate_orig; |
| 1894 | |
| 1895 | auto_negotiate_orig = tstate->auto_negotiate; |
| 1896 | if (neg_type == AHC_NEG_ALWAYS) { |
| 1897 | /* |
| 1898 | * Force our "current" settings to be |
| 1899 | * unknown so that unless a bus reset |
| 1900 | * occurs the need to renegotiate is |
| 1901 | * recorded persistently. |
| 1902 | */ |
| 1903 | if ((ahc->features & AHC_WIDE) != 0) |
| 1904 | tinfo->curr.width = AHC_WIDTH_UNKNOWN0xFF; |
| 1905 | tinfo->curr.period = AHC_PERIOD_UNKNOWN0xFF; |
| 1906 | tinfo->curr.offset = AHC_OFFSET_UNKNOWN0xFF; |
| 1907 | } |
| 1908 | if (tinfo->curr.period != tinfo->goal.period |
| 1909 | || tinfo->curr.width != tinfo->goal.width |
| 1910 | || tinfo->curr.offset != tinfo->goal.offset |
| 1911 | || tinfo->curr.ppr_options != tinfo->goal.ppr_options |
| 1912 | || (neg_type == AHC_NEG_IF_NON_ASYNC |
| 1913 | && (tinfo->goal.offset != 0 |
| 1914 | || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT0x00 |
| 1915 | || tinfo->goal.ppr_options != 0))) |
| 1916 | tstate->auto_negotiate |= devinfo->target_mask; |
| 1917 | else |
| 1918 | tstate->auto_negotiate &= ~devinfo->target_mask; |
| 1919 | |
| 1920 | return (auto_negotiate_orig != tstate->auto_negotiate); |
| 1921 | } |
| 1922 | |
| 1923 | /* |
| 1924 | * Update the user/goal/curr tables of synchronous negotiation |
| 1925 | * parameters as well as, in the case of a current or active update, |
| 1926 | * any data structures on the host controller. In the case of an |
| 1927 | * active update, the specified target is currently talking to us on |
| 1928 | * the bus, so the transfer parameter update must take effect |
| 1929 | * immediately. |
| 1930 | */ |
| 1931 | void |
| 1932 | ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 1933 | struct ahc_syncrate *syncrate, u_int period, |
| 1934 | u_int offset, u_int ppr_options, u_int type, int paused) |
| 1935 | { |
| 1936 | struct ahc_initiator_tinfo *tinfo; |
| 1937 | struct ahc_tmode_tstate *tstate; |
| 1938 | u_int old_period; |
| 1939 | u_int old_offset; |
| 1940 | u_int old_ppr; |
| 1941 | int active; |
| 1942 | int update_needed; |
| 1943 | |
| 1944 | active = (type & AHC_TRANS_ACTIVE0x03) == AHC_TRANS_ACTIVE0x03; |
| 1945 | update_needed = 0; |
| 1946 | |
| 1947 | if (syncrate == NULL((void *)0)) { |
| 1948 | period = 0; |
| 1949 | offset = 0; |
| 1950 | } |
| 1951 | |
| 1952 | tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, |
| 1953 | devinfo->target, &tstate); |
| 1954 | |
| 1955 | if ((type & AHC_TRANS_USER0x08) != 0) { |
| 1956 | tinfo->user.period = period; |
| 1957 | tinfo->user.offset = offset; |
| 1958 | tinfo->user.ppr_options = ppr_options; |
| 1959 | } |
| 1960 | |
| 1961 | if ((type & AHC_TRANS_GOAL0x04) != 0) { |
| 1962 | tinfo->goal.period = period; |
| 1963 | tinfo->goal.offset = offset; |
| 1964 | tinfo->goal.ppr_options = ppr_options; |
| 1965 | } |
| 1966 | |
| 1967 | old_period = tinfo->curr.period; |
| 1968 | old_offset = tinfo->curr.offset; |
| 1969 | old_ppr = tinfo->curr.ppr_options; |
| 1970 | |
| 1971 | if ((type & AHC_TRANS_CUR0x01) != 0 |
| 1972 | && (old_period != period |
| 1973 | || old_offset != offset |
| 1974 | || old_ppr != ppr_options)) { |
| 1975 | u_int scsirate; |
| 1976 | |
| 1977 | update_needed++; |
| 1978 | scsirate = tinfo->scsirate; |
| 1979 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1980 | |
| 1981 | scsirate &= ~(SXFR_ULTRA20x0f|SINGLE_EDGE0x10|ENABLE_CRC0x40); |
| 1982 | if (syncrate != NULL((void *)0)) { |
| 1983 | scsirate |= syncrate->sxfr_u2; |
| 1984 | if ((ppr_options & MSG_EXT_PPR_DT_REQ0x02) != 0) |
| 1985 | scsirate |= ENABLE_CRC0x40; |
| 1986 | else |
| 1987 | scsirate |= SINGLE_EDGE0x10; |
| 1988 | } |
| 1989 | } else { |
| 1990 | |
| 1991 | scsirate &= ~(SXFR0x70|SOFS0x0f); |
| 1992 | /* |
| 1993 | * Ensure Ultra mode is set properly for |
| 1994 | * this target. |
| 1995 | */ |
| 1996 | tstate->ultraenb &= ~devinfo->target_mask; |
| 1997 | if (syncrate != NULL((void *)0)) { |
| 1998 | if (syncrate->sxfr & ULTRA_SXFR0x100) { |
| 1999 | tstate->ultraenb |= |
| 2000 | devinfo->target_mask; |
| 2001 | } |
| 2002 | scsirate |= syncrate->sxfr & SXFR0x70; |
| 2003 | scsirate |= offset & SOFS0x0f; |
| 2004 | } |
| 2005 | if (active) { |
| 2006 | u_int sxfrctl0; |
| 2007 | |
| 2008 | sxfrctl0 = ahc_inb(ahc, SXFRCTL0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x01))); |
| 2009 | sxfrctl0 &= ~FAST200x20; |
| 2010 | if (tstate->ultraenb & devinfo->target_mask) |
| 2011 | sxfrctl0 |= FAST200x20; |
| 2012 | ahc_outb(ahc, SXFRCTL0, sxfrctl0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), (sxfrctl0 ))); |
| 2013 | } |
| 2014 | } |
| 2015 | if (active) { |
| 2016 | ahc_outb(ahc, SCSIRATE, scsirate)(((ahc)->tag)->write_1(((ahc)->bsh), (0x04), (scsirate ))); |
| 2017 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 2018 | ahc_outb(ahc, SCSIOFFSET, offset)(((ahc)->tag)->write_1(((ahc)->bsh), (0x05), (offset ))); |
| 2019 | } |
| 2020 | |
| 2021 | tinfo->scsirate = scsirate; |
| 2022 | tinfo->curr.period = period; |
| 2023 | tinfo->curr.offset = offset; |
| 2024 | tinfo->curr.ppr_options = ppr_options; |
| 2025 | |
| 2026 | ahc_send_async(ahc, devinfo->channel, devinfo->target, |
| 2027 | CAM_LUN_WILDCARD-1, AC_TRANSFER_NEG, NULL((void *)0)); |
| 2028 | if (1 /*bootverbose*/) { |
| 2029 | if (offset != 0) { |
| 2030 | printf("%s: target %d synchronous at %sMHz%s, " |
| 2031 | "offset = 0x%x\n", ahc_name(ahc), |
| 2032 | devinfo->target, syncrate->rate, |
| 2033 | (ppr_options & MSG_EXT_PPR_DT_REQ0x02) |
| 2034 | ? " DT" : "", offset); |
| 2035 | } else { |
| 2036 | printf("%s: target %d using " |
| 2037 | "asynchronous transfers\n", |
| 2038 | ahc_name(ahc), devinfo->target); |
| 2039 | } |
| 2040 | } |
| 2041 | } |
| 2042 | |
| 2043 | update_needed += ahc_update_neg_request(ahc, devinfo, tstate, |
| 2044 | tinfo, AHC_NEG_TO_GOAL); |
| 2045 | |
| 2046 | if (update_needed) |
| 2047 | ahc_update_pending_scbs(ahc); |
| 2048 | } |
| 2049 | |
| 2050 | /* |
| 2051 | * Update the user/goal/curr tables of wide negotiation |
| 2052 | * parameters as well as, in the case of a current or active update, |
| 2053 | * any data structures on the host controller. In the case of an |
| 2054 | * active update, the specified target is currently talking to us on |
| 2055 | * the bus, so the transfer parameter update must take effect |
| 2056 | * immediately. |
| 2057 | */ |
| 2058 | void |
| 2059 | ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2060 | u_int width, u_int type, int paused) |
| 2061 | { |
| 2062 | struct ahc_initiator_tinfo *tinfo; |
| 2063 | struct ahc_tmode_tstate *tstate; |
| 2064 | u_int oldwidth; |
| 2065 | int active; |
| 2066 | int update_needed; |
| 2067 | |
| 2068 | active = (type & AHC_TRANS_ACTIVE0x03) == AHC_TRANS_ACTIVE0x03; |
| 2069 | update_needed = 0; |
| 2070 | tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, |
| 2071 | devinfo->target, &tstate); |
| 2072 | |
| 2073 | if ((type & AHC_TRANS_USER0x08) != 0) |
| 2074 | tinfo->user.width = width; |
| 2075 | |
| 2076 | if ((type & AHC_TRANS_GOAL0x04) != 0) |
| 2077 | tinfo->goal.width = width; |
| 2078 | |
| 2079 | oldwidth = tinfo->curr.width; |
| 2080 | if ((type & AHC_TRANS_CUR0x01) != 0 && oldwidth != width) { |
| 2081 | u_int scsirate; |
| 2082 | |
| 2083 | update_needed++; |
| 2084 | scsirate = tinfo->scsirate; |
| 2085 | scsirate &= ~WIDEXFER0x80; |
| 2086 | if (width == MSG_EXT_WDTR_BUS_16_BIT0x01) |
| 2087 | scsirate |= WIDEXFER0x80; |
| 2088 | |
| 2089 | tinfo->scsirate = scsirate; |
| 2090 | |
| 2091 | if (active) |
| 2092 | ahc_outb(ahc, SCSIRATE, scsirate)(((ahc)->tag)->write_1(((ahc)->bsh), (0x04), (scsirate ))); |
| 2093 | |
| 2094 | tinfo->curr.width = width; |
| 2095 | |
| 2096 | ahc_send_async(ahc, devinfo->channel, devinfo->target, |
| 2097 | CAM_LUN_WILDCARD-1, AC_TRANSFER_NEG, NULL((void *)0)); |
| 2098 | if (1 /*bootverbose*/) { |
| 2099 | printf("%s: target %d using %dbit transfers\n", |
| 2100 | ahc_name(ahc), devinfo->target, |
| 2101 | 8 * (0x01 << width)); |
| 2102 | } |
| 2103 | } |
| 2104 | |
| 2105 | update_needed += ahc_update_neg_request(ahc, devinfo, tstate, |
| 2106 | tinfo, AHC_NEG_TO_GOAL); |
| 2107 | if (update_needed) |
| 2108 | ahc_update_pending_scbs(ahc); |
| 2109 | } |
| 2110 | |
| 2111 | /* |
| 2112 | * Update the current state of tagged queuing for a given target. |
| 2113 | */ |
| 2114 | void |
| 2115 | ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2116 | ahc_queue_alg alg) |
| 2117 | { |
| 2118 | ahc_platform_set_tags(ahc, devinfo, alg); |
| 2119 | ahc_send_async(ahc, devinfo->channel, devinfo->target, |
| 2120 | devinfo->lun, AC_TRANSFER_NEG, &alg); |
| 2121 | } |
| 2122 | |
| 2123 | /* |
| 2124 | * When the transfer settings for a connection change, update any |
| 2125 | * in-transit SCBs to contain the new data so the hardware will |
| 2126 | * be set correctly during future (re)selections. |
| 2127 | */ |
| 2128 | static void |
| 2129 | ahc_update_pending_scbs(struct ahc_softc *ahc) |
| 2130 | { |
| 2131 | struct scb *pending_scb; |
| 2132 | int pending_scb_count; |
| 2133 | int i; |
| 2134 | int paused; |
| 2135 | u_int saved_scbptr; |
| 2136 | |
| 2137 | /* |
| 2138 | * Traverse the pending SCB list and ensure that all of the |
| 2139 | * SCBs there have the proper settings. |
| 2140 | */ |
| 2141 | pending_scb_count = 0; |
| 2142 | LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links)for((pending_scb) = ((&ahc->pending_scbs)->lh_first ); (pending_scb)!= ((void *)0); (pending_scb) = ((pending_scb )->pending_links.le_next)) { |
| 2143 | struct ahc_devinfo devinfo; |
| 2144 | struct hardware_scb *pending_hscb; |
| 2145 | struct ahc_initiator_tinfo *tinfo; |
| 2146 | struct ahc_tmode_tstate *tstate; |
| 2147 | |
| 2148 | ahc_scb_devinfo(ahc, &devinfo, pending_scb); |
| 2149 | tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, |
| 2150 | devinfo.our_scsiid, |
| 2151 | devinfo.target, &tstate); |
| 2152 | pending_hscb = pending_scb->hscb; |
| 2153 | pending_hscb->control &= ~ULTRAENB0x08; |
| 2154 | if ((tstate->ultraenb & devinfo.target_mask) != 0) |
| 2155 | pending_hscb->control |= ULTRAENB0x08; |
| 2156 | pending_hscb->scsirate = tinfo->scsirate; |
| 2157 | pending_hscb->scsioffset = tinfo->curr.offset; |
| 2158 | if ((tstate->auto_negotiate & devinfo.target_mask) == 0 |
| 2159 | && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { |
| 2160 | pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; |
| 2161 | pending_hscb->control &= ~MK_MESSAGE0x10; |
| 2162 | } |
| 2163 | ahc_sync_scb(ahc, pending_scb, |
| 2164 | BUS_DMASYNC_PREREAD0x01|BUS_DMASYNC_PREWRITE0x04); |
| 2165 | pending_scb_count++; |
| 2166 | } |
| 2167 | |
| 2168 | if (pending_scb_count == 0) |
| 2169 | return; |
| 2170 | |
| 2171 | if (ahc_is_paused(ahc)) { |
| 2172 | paused = 1; |
| 2173 | } else { |
| 2174 | paused = 0; |
| 2175 | ahc_pause(ahc); |
| 2176 | } |
| 2177 | |
| 2178 | saved_scbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 2179 | /* Ensure that the hscbs down on the card match the new information */ |
| 2180 | for (i = 0; i < ahc->scb_data->maxhscbs; i++) { |
| 2181 | struct hardware_scb *pending_hscb; |
| 2182 | u_int control; |
| 2183 | u_int scb_tag; |
| 2184 | |
| 2185 | ahc_outb(ahc, SCBPTR, i)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (i))); |
| 2186 | scb_tag = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 2187 | pending_scb = ahc_lookup_scb(ahc, scb_tag); |
| 2188 | if (pending_scb == NULL((void *)0)) |
| 2189 | continue; |
| 2190 | |
| 2191 | pending_hscb = pending_scb->hscb; |
| 2192 | control = ahc_inb(ahc, SCB_CONTROL)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb8))); |
| 2193 | control &= ~(ULTRAENB0x08|MK_MESSAGE0x10); |
| 2194 | control |= pending_hscb->control & (ULTRAENB0x08|MK_MESSAGE0x10); |
| 2195 | ahc_outb(ahc, SCB_CONTROL, control)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), (control ))); |
| 2196 | ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbd), (pending_hscb ->scsirate))); |
| 2197 | ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbe), (pending_hscb ->scsioffset))); |
| 2198 | } |
| 2199 | ahc_outb(ahc, SCBPTR, saved_scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (saved_scbptr ))); |
| 2200 | |
| 2201 | if (paused == 0) |
| 2202 | ahc_unpause(ahc); |
| 2203 | } |
| 2204 | |
| 2205 | /**************************** Pathing Information *****************************/ |
| 2206 | static void |
| 2207 | ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 2208 | { |
| 2209 | u_int saved_scsiid; |
| 2210 | role_t role; |
| 2211 | int our_id; |
| 2212 | |
| 2213 | if (ahc_inb(ahc, SSTAT0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0b))) & TARGET0x80) |
| 2214 | role = ROLE_TARGET; |
| 2215 | else |
| 2216 | role = ROLE_INITIATOR; |
| 2217 | |
| 2218 | if (role == ROLE_TARGET |
| 2219 | && (ahc->features & AHC_MULTI_TID) != 0 |
| 2220 | && (ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))) |
| 2221 | & (CMDPHASE_PENDING0x08|TARG_CMD_PENDING0x10|NO_DISCONNECT0x01)) != 0) { |
| 2222 | /* We were selected, so pull our id from TARGIDIN */ |
| 2223 | our_id = ahc_inb(ahc, TARGIDIN)(((ahc)->tag)->read_1(((ahc)->bsh), (0x18))) & OID0x0f; |
| 2224 | } else if ((ahc->features & AHC_ULTRA2) != 0) |
| 2225 | our_id = ahc_inb(ahc, SCSIID_ULTRA2)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0f))) & OID0x0f; |
| 2226 | else |
| 2227 | our_id = ahc_inb(ahc, SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x05))) & OID0x0f; |
| 2228 | |
| 2229 | saved_scsiid = ahc_inb(ahc, SAVED_SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3d))); |
| 2230 | ahc_compile_devinfo(devinfo, |
| 2231 | our_id, |
| 2232 | SCSIID_TARGET(ahc, saved_scsiid)(((saved_scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04), |
| 2233 | ahc_inb(ahc, SAVED_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3e))), |
| 2234 | SCSIID_CHANNEL(ahc, saved_scsiid)((((ahc)->features & AHC_TWIN) != 0) ? ((((saved_scsiid ) & 0x80) != 0) ? 'B' : 'A') : 'A'), |
| 2235 | role); |
| 2236 | } |
| 2237 | |
| 2238 | struct ahc_phase_table_entry* |
| 2239 | ahc_lookup_phase_entry(int phase) |
| 2240 | { |
| 2241 | struct ahc_phase_table_entry *entry; |
| 2242 | struct ahc_phase_table_entry *last_entry; |
| 2243 | |
| 2244 | /* |
| 2245 | * num_phases doesn't include the default entry which |
| 2246 | * will be returned if the phase doesn't match. |
| 2247 | */ |
| 2248 | last_entry = &ahc_phase_table[num_phases]; |
| 2249 | for (entry = ahc_phase_table; entry < last_entry; entry++) { |
| 2250 | if (phase == entry->phase) |
| 2251 | break; |
| 2252 | } |
| 2253 | return (entry); |
| 2254 | } |
| 2255 | |
| 2256 | void |
| 2257 | ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, |
| 2258 | u_int lun, char channel, role_t role) |
| 2259 | { |
| 2260 | devinfo->our_scsiid = our_id; |
| 2261 | devinfo->target = target; |
| 2262 | devinfo->lun = lun; |
| 2263 | devinfo->target_offset = target; |
| 2264 | devinfo->channel = channel; |
| 2265 | devinfo->role = role; |
| 2266 | if (channel == 'B') |
| 2267 | devinfo->target_offset += 8; |
| 2268 | devinfo->target_mask = (0x01 << devinfo->target_offset); |
| 2269 | } |
| 2270 | |
| 2271 | void |
| 2272 | ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 2273 | { |
| 2274 | printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, |
| 2275 | devinfo->target, devinfo->lun); |
| 2276 | } |
| 2277 | |
| 2278 | void |
| 2279 | ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2280 | struct scb *scb) |
| 2281 | { |
| 2282 | role_t role; |
| 2283 | int our_id; |
| 2284 | |
| 2285 | our_id = SCSIID_OUR_ID(scb->hscb->scsiid)((scb->hscb->scsiid) & 0x0f); |
| 2286 | role = ROLE_INITIATOR; |
| 2287 | if ((scb->flags & SCB_TARGET_SCB) != 0) |
| 2288 | role = ROLE_TARGET; |
| 2289 | ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb)((((scb)->hscb->scsiid) & (((((ahc))->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04), |
| 2290 | SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f), SCB_GET_CHANNEL(ahc, scb)((((ahc)->features & AHC_TWIN) != 0) ? (((((scb)->hscb ->scsiid) & 0x80) != 0) ? 'B' : 'A') : 'A'), role); |
| 2291 | } |
| 2292 | |
| 2293 | |
| 2294 | /************************ Message Phase Processing ****************************/ |
| 2295 | static void |
| 2296 | ahc_assert_atn(struct ahc_softc *ahc) |
| 2297 | { |
| 2298 | u_int scsisigo; |
| 2299 | |
| 2300 | scsisigo = ATNO0x10; |
| 2301 | if ((ahc->features & AHC_DT) == 0) |
| 2302 | scsisigo |= ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))); |
| 2303 | ahc_outb(ahc, SCSISIGO, scsisigo)(((ahc)->tag)->write_1(((ahc)->bsh), (0x03), (scsisigo ))); |
| 2304 | } |
| 2305 | |
| 2306 | /* |
| 2307 | * When an initiator transaction with the MK_MESSAGE flag either reconnects |
| 2308 | * or enters the initial message out phase, we are interrupted. Fill our |
| 2309 | * outgoing message buffer with the appropriate message and begin handing |
| 2310 | * the message phase(s) manually. |
| 2311 | */ |
| 2312 | static void |
| 2313 | ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2314 | struct scb *scb) |
| 2315 | { |
| 2316 | /* |
| 2317 | * To facilitate adding multiple messages together, |
| 2318 | * each routine should increment the index and len |
| 2319 | * variables instead of setting them explicitly. |
| 2320 | */ |
| 2321 | ahc->msgout_index = 0; |
| 2322 | ahc->msgout_len = 0; |
| 2323 | |
| 2324 | if ((scb->flags & SCB_DEVICE_RESET) == 0 |
| 2325 | && ahc_inb(ahc, MSG_OUT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3a))) == MSG_IDENTIFYFLAG0x80) { |
| 2326 | u_int identify_msg; |
| 2327 | |
| 2328 | identify_msg = MSG_IDENTIFYFLAG0x80 | SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f); |
| 2329 | if ((scb->hscb->control & DISCENB0x40) != 0) |
| 2330 | identify_msg |= MSG_IDENTIFY_DISCFLAG0x40; |
| 2331 | ahc->msgout_buf[ahc->msgout_index++] = identify_msg; |
| 2332 | ahc->msgout_len++; |
| 2333 | |
| 2334 | if ((scb->hscb->control & TAG_ENB0x20) != 0) { |
| 2335 | ahc->msgout_buf[ahc->msgout_index++] = |
| 2336 | scb->hscb->control & (TAG_ENB0x20|SCB_TAG_TYPE0x03); |
| 2337 | ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; |
| 2338 | ahc->msgout_len += 2; |
| 2339 | } |
| 2340 | } |
| 2341 | |
| 2342 | if (scb->flags & SCB_DEVICE_RESET) { |
| 2343 | ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET0x0c; |
| 2344 | ahc->msgout_len++; |
| 2345 | ahc_print_path(ahc, scb); |
| 2346 | printf("Bus Device Reset Message Sent\n"); |
| 2347 | /* |
| 2348 | * Clear our selection hardware in advance of |
| 2349 | * the busfree. We may have an entry in the waiting |
| 2350 | * Q for this target, and we don't want to go about |
| 2351 | * selecting while we handle the busfree and blow it |
| 2352 | * away. |
| 2353 | */ |
| 2354 | ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & ~0x40)) )); |
| 2355 | } else if ((scb->flags & SCB_ABORT) != 0) { |
| 2356 | if ((scb->hscb->control & TAG_ENB0x20) != 0) |
| 2357 | ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG0x0d; |
| 2358 | else |
| 2359 | ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT0x06; |
| 2360 | ahc->msgout_len++; |
| 2361 | ahc_print_path(ahc, scb); |
| 2362 | printf("Abort%s Message Sent\n", |
| 2363 | (scb->hscb->control & TAG_ENB0x20) != 0 ? " Tag" : ""); |
| 2364 | /* |
| 2365 | * Clear our selection hardware in advance of |
| 2366 | * the busfree. We may have an entry in the waiting |
| 2367 | * Q for this target, and we don't want to go about |
| 2368 | * selecting while we handle the busfree and blow it |
| 2369 | * away. |
| 2370 | */ |
| 2371 | ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & ~0x40)) )); |
| 2372 | } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { |
| 2373 | ahc_build_transfer_msg(ahc, devinfo); |
| 2374 | } else { |
| 2375 | printf("ahc_intr: AWAITING_MSG for an SCB that " |
| 2376 | "does not have a waiting message\n"); |
| 2377 | printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, |
| 2378 | devinfo->target_mask); |
| 2379 | panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " |
| 2380 | "SCB flags = %x", scb->hscb->tag, scb->hscb->control, |
| 2381 | ahc_inb(ahc, MSG_OUT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3a))), scb->flags); |
| 2382 | } |
| 2383 | |
| 2384 | /* |
| 2385 | * Clear the MK_MESSAGE flag from the SCB so we aren't |
| 2386 | * asked to send this message again. |
| 2387 | */ |
| 2388 | ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), ((((ahc )->tag)->read_1(((ahc)->bsh), (0xb8))) & ~0x10)) ); |
| 2389 | scb->hscb->control &= ~MK_MESSAGE0x10; |
| 2390 | ahc->msgout_index = 0; |
| 2391 | ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
| 2392 | } |
| 2393 | |
| 2394 | /* |
| 2395 | * Build an appropriate transfer negotiation message for the |
| 2396 | * currently active target. |
| 2397 | */ |
| 2398 | static void |
| 2399 | ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 2400 | { |
| 2401 | /* |
| 2402 | * We need to initiate transfer negotiations. |
| 2403 | * If our current and goal settings are identical, |
| 2404 | * we want to renegotiate due to a check condition. |
| 2405 | */ |
| 2406 | struct ahc_initiator_tinfo *tinfo; |
| 2407 | struct ahc_tmode_tstate *tstate; |
| 2408 | struct ahc_syncrate *rate; |
| 2409 | int dowide; |
| 2410 | int dosync; |
| 2411 | int doppr; |
| 2412 | u_int period; |
| 2413 | u_int ppr_options; |
| 2414 | u_int offset; |
| 2415 | |
| 2416 | tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, |
| 2417 | devinfo->target, &tstate); |
| 2418 | /* |
| 2419 | * Filter our period based on the current connection. |
| 2420 | * If we can't perform DT transfers on this segment (not in LVD |
| 2421 | * mode for instance), then our decision to issue a PPR message |
| 2422 | * may change. |
| 2423 | */ |
| 2424 | period = tinfo->goal.period; |
| 2425 | offset = tinfo->goal.offset; |
| 2426 | ppr_options = tinfo->goal.ppr_options; |
| 2427 | /* Target initiated PPR is not allowed in the SCSI spec */ |
| 2428 | if (devinfo->role == ROLE_TARGET) |
| 2429 | ppr_options = 0; |
| 2430 | rate = ahc_devlimited_syncrate(ahc, tinfo, &period, |
| 2431 | &ppr_options, devinfo->role); |
| 2432 | dowide = tinfo->curr.width != tinfo->goal.width; |
| 2433 | dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; |
| 2434 | /* |
| 2435 | * Only use PPR if we have options that need it, even if the device |
| 2436 | * claims to support it. There might be an expander in the way |
| 2437 | * that doesn't. |
| 2438 | */ |
| 2439 | doppr = ppr_options != 0; |
| 2440 | |
| 2441 | if (!dowide && !dosync && !doppr) { |
| 2442 | dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT0x00; |
| 2443 | dosync = tinfo->goal.offset != 0; |
| 2444 | } |
| 2445 | |
| 2446 | if (!dowide && !dosync && !doppr) { |
| 2447 | /* |
| 2448 | * Force async with a WDTR message if we have a wide bus, |
| 2449 | * or just issue an SDTR with a 0 offset. |
| 2450 | */ |
| 2451 | if ((ahc->features & AHC_WIDE) != 0) |
| 2452 | dowide = 1; |
| 2453 | else |
| 2454 | dosync = 1; |
| 2455 | |
| 2456 | if (bootverbose0) { |
| 2457 | ahc_print_devinfo(ahc, devinfo); |
| 2458 | printf("Ensuring async\n"); |
| 2459 | } |
| 2460 | } |
| 2461 | |
| 2462 | /* Target initiated PPR is not allowed in the SCSI spec */ |
| 2463 | if (devinfo->role == ROLE_TARGET) |
| 2464 | doppr = 0; |
| 2465 | |
| 2466 | /* |
| 2467 | * Both the PPR message and SDTR message require the |
| 2468 | * goal syncrate to be limited to what the target device |
| 2469 | * is capable of handling (based on whether an LVD->SE |
| 2470 | * expander is on the bus), so combine these two cases. |
| 2471 | * Regardless, guarantee that if we are using WDTR and SDTR |
| 2472 | * messages that WDTR comes first. |
| 2473 | */ |
| 2474 | if (doppr || (dosync && !dowide)) { |
| 2475 | |
| 2476 | offset = tinfo->goal.offset; |
| 2477 | ahc_validate_offset(ahc, tinfo, rate, &offset, |
| 2478 | doppr ? tinfo->goal.width |
| 2479 | : tinfo->curr.width, |
| 2480 | devinfo->role); |
| 2481 | if (doppr) { |
| 2482 | ahc_construct_ppr(ahc, devinfo, period, offset, |
| 2483 | tinfo->goal.width, ppr_options); |
| 2484 | } else { |
| 2485 | ahc_construct_sdtr(ahc, devinfo, period, offset); |
| 2486 | } |
| 2487 | } else { |
| 2488 | ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); |
| 2489 | } |
| 2490 | } |
| 2491 | |
| 2492 | /* |
| 2493 | * Build a synchronous negotiation message in our message |
| 2494 | * buffer based on the input parameters. |
| 2495 | */ |
| 2496 | static void |
| 2497 | ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2498 | u_int period, u_int offset) |
| 2499 | { |
| 2500 | if (offset == 0) |
| 2501 | period = AHC_ASYNC_XFER_PERIOD0x45; |
| 2502 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED0x01; |
| 2503 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN0x03; |
| 2504 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR0x01; |
| 2505 | ahc->msgout_buf[ahc->msgout_index++] = period; |
| 2506 | ahc->msgout_buf[ahc->msgout_index++] = offset; |
| 2507 | ahc->msgout_len += 5; |
| 2508 | if (bootverbose0) { |
| 2509 | printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", |
| 2510 | ahc_name(ahc), devinfo->channel, devinfo->target, |
| 2511 | devinfo->lun, period, offset); |
| 2512 | } |
| 2513 | } |
| 2514 | |
| 2515 | /* |
| 2516 | * Build a wide negotiation message in our message |
| 2517 | * buffer based on the input parameters. |
| 2518 | */ |
| 2519 | static void |
| 2520 | ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2521 | u_int bus_width) |
| 2522 | { |
| 2523 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED0x01; |
| 2524 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN0x02; |
| 2525 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR0x03; |
| 2526 | ahc->msgout_buf[ahc->msgout_index++] = bus_width; |
| 2527 | ahc->msgout_len += 4; |
| 2528 | if (bootverbose0) { |
| 2529 | printf("(%s:%c:%d:%d): Sending WDTR %x\n", |
| 2530 | ahc_name(ahc), devinfo->channel, devinfo->target, |
| 2531 | devinfo->lun, bus_width); |
| 2532 | } |
| 2533 | } |
| 2534 | |
| 2535 | /* |
| 2536 | * Build a parallel protocol request message in our message |
| 2537 | * buffer based on the input parameters. |
| 2538 | */ |
| 2539 | static void |
| 2540 | ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 2541 | u_int period, u_int offset, u_int bus_width, |
| 2542 | u_int ppr_options) |
| 2543 | { |
| 2544 | if (offset == 0) |
| 2545 | period = AHC_ASYNC_XFER_PERIOD0x45; |
| 2546 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED0x01; |
| 2547 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN0x06; |
| 2548 | ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR0x04; |
| 2549 | ahc->msgout_buf[ahc->msgout_index++] = period; |
| 2550 | ahc->msgout_buf[ahc->msgout_index++] = 0; |
| 2551 | ahc->msgout_buf[ahc->msgout_index++] = offset; |
| 2552 | ahc->msgout_buf[ahc->msgout_index++] = bus_width; |
| 2553 | ahc->msgout_buf[ahc->msgout_index++] = ppr_options; |
| 2554 | ahc->msgout_len += 8; |
| 2555 | if (bootverbose0) { |
| 2556 | printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " |
| 2557 | "offset %x, ppr_options %x\n", ahc_name(ahc), |
| 2558 | devinfo->channel, devinfo->target, devinfo->lun, |
| 2559 | bus_width, period, offset, ppr_options); |
| 2560 | } |
| 2561 | } |
| 2562 | |
| 2563 | /* |
| 2564 | * Clear any active message state. |
| 2565 | */ |
| 2566 | static void |
| 2567 | ahc_clear_msg_state(struct ahc_softc *ahc) |
| 2568 | { |
| 2569 | ahc->msgout_len = 0; |
| 2570 | ahc->msgin_index = 0; |
| 2571 | ahc->msg_type = MSG_TYPE_NONE; |
| 2572 | if ((ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & ATNI0x10) != 0) { |
| 2573 | /* |
| 2574 | * The target didn't care to respond to our |
| 2575 | * message request, so clear ATN. |
| 2576 | */ |
| 2577 | ahc_outb(ahc, CLRSINT1, CLRATNO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x40)) ); |
| 2578 | } |
| 2579 | ahc_outb(ahc, MSG_OUT, MSG_NOOP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0x08)) ); |
| 2580 | ahc_outb(ahc, SEQ_FLAGS2,(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x57))) & ~0x02)) ) |
| 2581 | ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING)(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x57))) & ~0x02)) ); |
| 2582 | } |
| 2583 | |
| 2584 | static void |
| 2585 | ahc_handle_proto_violation(struct ahc_softc *ahc) |
| 2586 | { |
| 2587 | struct ahc_devinfo devinfo; |
| 2588 | struct scb *scb; |
| 2589 | u_int scbid; |
| 2590 | u_int seq_flags; |
| 2591 | u_int curphase; |
| 2592 | u_int lastphase; |
| 2593 | int found; |
| 2594 | |
| 2595 | ahc_fetch_devinfo(ahc, &devinfo); |
| 2596 | scbid = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 2597 | scb = ahc_lookup_scb(ahc, scbid); |
| 2598 | seq_flags = ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))); |
| 2599 | curphase = ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & PHASE_MASK0xe0; |
| 2600 | lastphase = ahc_inb(ahc, LASTPHASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3f))); |
| 2601 | if ((seq_flags & NOT_IDENTIFIED0x80) != 0) { |
| 2602 | |
| 2603 | /* |
| 2604 | * The reconnecting target either did not send an |
| 2605 | * identify message, or did, but we didn't find an SCB |
| 2606 | * to match. |
| 2607 | */ |
| 2608 | ahc_print_devinfo(ahc, &devinfo); |
| 2609 | printf("Target did not send an IDENTIFY message. " |
| 2610 | "LASTPHASE = 0x%x.\n", lastphase); |
| 2611 | scb = NULL((void *)0); |
| 2612 | } else if (scb == NULL((void *)0)) { |
| 2613 | /* |
| 2614 | * We don't seem to have an SCB active for this |
| 2615 | * transaction. Print an error and reset the bus. |
| 2616 | */ |
| 2617 | ahc_print_devinfo(ahc, &devinfo); |
| 2618 | printf("No SCB found during protocol violation\n"); |
| 2619 | goto proto_violation_reset; |
| 2620 | } else { |
| 2621 | ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); |
| 2622 | if ((seq_flags & NO_CDB_SENT0x40) != 0) { |
| 2623 | ahc_print_path(ahc, scb); |
| 2624 | printf("No or incomplete CDB sent to device.\n"); |
| 2625 | } else if ((ahc_inb(ahc, SCB_CONTROL)(((ahc)->tag)->read_1(((ahc)->bsh), (0xb8))) & STATUS_RCVD0x80) == 0) { |
| 2626 | /* |
| 2627 | * The target never bothered to provide status to |
| 2628 | * us prior to completing the command. Since we don't |
| 2629 | * know the disposition of this command, we must attempt |
| 2630 | * to abort it. Assert ATN and prepare to send an abort |
| 2631 | * message. |
| 2632 | */ |
| 2633 | ahc_print_path(ahc, scb); |
| 2634 | printf("Completed command without status.\n"); |
| 2635 | } else { |
| 2636 | ahc_print_path(ahc, scb); |
| 2637 | printf("Unknown protocol violation.\n"); |
| 2638 | ahc_dump_card_state(ahc); |
| 2639 | } |
| 2640 | } |
| 2641 | if ((lastphase & ~P_DATAIN_DT0x60) == 0 |
| 2642 | || lastphase == P_COMMAND0x80) { |
| 2643 | proto_violation_reset: |
| 2644 | /* |
| 2645 | * Target either went directly to data/command |
| 2646 | * phase or didn't respond to our ATN. |
| 2647 | * The only safe thing to do is to blow |
| 2648 | * it away with a bus reset. |
| 2649 | */ |
| 2650 | found = ahc_reset_channel(ahc, 'A', TRUE1); |
| 2651 | printf("%s: Issued Channel %c Bus Reset. " |
| 2652 | "%d SCBs aborted\n", ahc_name(ahc), 'A', found); |
| 2653 | } else { |
| 2654 | /* |
| 2655 | * Leave the selection hardware off in case |
| 2656 | * this abort attempt will affect yet to |
| 2657 | * be sent commands. |
| 2658 | */ |
| 2659 | ahc_outb(ahc, SCSISEQ,(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & ~0x40)) ) |
| 2660 | ahc_inb(ahc, SCSISEQ) & ~ENSELO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & ~0x40)) ); |
| 2661 | ahc_assert_atn(ahc); |
| 2662 | ahc_outb(ahc, MSG_OUT, HOST_MSG)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0xff)) ); |
| 2663 | if (scb == NULL((void *)0)) { |
| 2664 | ahc_print_devinfo(ahc, &devinfo); |
| 2665 | ahc->msgout_buf[0] = MSG_ABORT_TASK0x0d; |
| 2666 | ahc->msgout_len = 1; |
| 2667 | ahc->msgout_index = 0; |
| 2668 | ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
| 2669 | } else { |
| 2670 | ahc_print_path(ahc, scb); |
| 2671 | scb->flags |= SCB_ABORT; |
| 2672 | } |
| 2673 | printf("Protocol violation %s. Attempting to abort.\n", |
| 2674 | ahc_lookup_phase_entry(curphase)->phasemsg); |
| 2675 | } |
| 2676 | } |
| 2677 | |
| 2678 | /* |
| 2679 | * Manual message loop handler. |
| 2680 | */ |
| 2681 | static void |
| 2682 | ahc_handle_message_phase(struct ahc_softc *ahc) |
| 2683 | { |
| 2684 | struct ahc_devinfo devinfo; |
| 2685 | u_int bus_phase; |
| 2686 | int end_session; |
| 2687 | |
| 2688 | ahc_fetch_devinfo(ahc, &devinfo); |
| 2689 | end_session = FALSE0; |
| 2690 | bus_phase = ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & PHASE_MASK0xe0; |
| 2691 | |
| 2692 | reswitch: |
| 2693 | switch (ahc->msg_type) { |
| 2694 | case MSG_TYPE_INITIATOR_MSGOUT: |
| 2695 | { |
| 2696 | int lastbyte; |
| 2697 | int phasemis; |
| 2698 | int msgdone; |
| 2699 | |
| 2700 | if (ahc->msgout_len == 0) |
| 2701 | panic("HOST_MSG_LOOP interrupt with no active message"); |
| 2702 | |
| 2703 | #ifdef AHC_DEBUG |
| 2704 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 2705 | ahc_print_devinfo(ahc, &devinfo); |
| 2706 | printf("INITIATOR_MSG_OUT"); |
| 2707 | } |
| 2708 | #endif |
| 2709 | phasemis = bus_phase != P_MESGOUT0xa0; |
| 2710 | if (phasemis) { |
| 2711 | #ifdef AHC_DEBUG |
| 2712 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 2713 | printf(" PHASEMIS %s\n", |
| 2714 | ahc_lookup_phase_entry(bus_phase) |
| 2715 | ->phasemsg); |
| 2716 | } |
| 2717 | #endif |
| 2718 | if (bus_phase == P_MESGIN0xe0) { |
| 2719 | /* |
| 2720 | * Change gears and see if |
| 2721 | * this messages is of interest to |
| 2722 | * us or should be passed back to |
| 2723 | * the sequencer. |
| 2724 | */ |
| 2725 | ahc_outb(ahc, CLRSINT1, CLRATNO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x40)) ); |
| 2726 | ahc->send_msg_perror = FALSE0; |
| 2727 | ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; |
| 2728 | ahc->msgin_index = 0; |
| 2729 | goto reswitch; |
| 2730 | } |
| 2731 | end_session = TRUE1; |
| 2732 | break; |
| 2733 | } |
| 2734 | |
| 2735 | if (ahc->send_msg_perror) { |
| 2736 | ahc_outb(ahc, CLRSINT1, CLRATNO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x40)) ); |
| 2737 | ahc_outb(ahc, CLRSINT1, CLRREQINIT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x01)) ); |
| 2738 | #ifdef AHC_DEBUG |
| 2739 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) |
| 2740 | printf(" byte 0x%x\n", ahc->send_msg_perror); |
| 2741 | #endif |
| 2742 | ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x06), (0x09)) ); |
| 2743 | break; |
| 2744 | } |
| 2745 | |
| 2746 | msgdone = ahc->msgout_index == ahc->msgout_len; |
| 2747 | if (msgdone) { |
| 2748 | /* |
| 2749 | * The target has requested a retry. |
| 2750 | * Re-assert ATN, reset our message index to |
| 2751 | * 0, and try again. |
| 2752 | */ |
| 2753 | ahc->msgout_index = 0; |
| 2754 | ahc_assert_atn(ahc); |
| 2755 | } |
| 2756 | |
| 2757 | lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); |
| 2758 | if (lastbyte) { |
| 2759 | /* Last byte is signified by dropping ATN */ |
| 2760 | ahc_outb(ahc, CLRSINT1, CLRATNO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x40)) ); |
| 2761 | } |
| 2762 | |
| 2763 | /* |
| 2764 | * Clear our interrupt status and present |
| 2765 | * the next byte on the bus. |
| 2766 | */ |
| 2767 | ahc_outb(ahc, CLRSINT1, CLRREQINIT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x01)) ); |
| 2768 | #ifdef AHC_DEBUG |
| 2769 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) |
| 2770 | printf(" byte 0x%x\n", |
| 2771 | ahc->msgout_buf[ahc->msgout_index]); |
| 2772 | #endif |
| 2773 | ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++])(((ahc)->tag)->write_1(((ahc)->bsh), (0x06), (ahc-> msgout_buf[ahc->msgout_index++]))); |
| 2774 | break; |
| 2775 | } |
| 2776 | case MSG_TYPE_INITIATOR_MSGIN: |
| 2777 | { |
| 2778 | int phasemis; |
| 2779 | int message_done; |
| 2780 | |
| 2781 | #ifdef AHC_DEBUG |
| 2782 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 2783 | ahc_print_devinfo(ahc, &devinfo); |
| 2784 | printf("INITIATOR_MSG_IN"); |
| 2785 | } |
| 2786 | #endif |
| 2787 | phasemis = bus_phase != P_MESGIN0xe0; |
| 2788 | if (phasemis) { |
| 2789 | #ifdef AHC_DEBUG |
| 2790 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 2791 | printf(" PHASEMIS %s\n", |
| 2792 | ahc_lookup_phase_entry(bus_phase) |
| 2793 | ->phasemsg); |
| 2794 | } |
| 2795 | #endif |
| 2796 | ahc->msgin_index = 0; |
| 2797 | if (bus_phase == P_MESGOUT0xa0 |
| 2798 | && (ahc->send_msg_perror == TRUE1 |
| 2799 | || (ahc->msgout_len != 0 |
| 2800 | && ahc->msgout_index == 0))) { |
| 2801 | ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
| 2802 | goto reswitch; |
| 2803 | } |
| 2804 | end_session = TRUE1; |
| 2805 | break; |
| 2806 | } |
| 2807 | |
| 2808 | /* Pull the byte in without acking it */ |
| 2809 | ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x12))); |
| 2810 | #ifdef AHC_DEBUG |
| 2811 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) |
| 2812 | printf(" byte 0x%x\n", |
| 2813 | ahc->msgin_buf[ahc->msgin_index]); |
| 2814 | #endif |
| 2815 | |
| 2816 | message_done = ahc_parse_msg(ahc, &devinfo); |
| 2817 | |
| 2818 | if (message_done) { |
| 2819 | /* |
| 2820 | * Clear our incoming message buffer in case there |
| 2821 | * is another message following this one. |
| 2822 | */ |
| 2823 | ahc->msgin_index = 0; |
| 2824 | |
| 2825 | /* |
| 2826 | * If this message illicited a response, |
| 2827 | * assert ATN so the target takes us to the |
| 2828 | * message out phase. |
| 2829 | */ |
| 2830 | if (ahc->msgout_len != 0) { |
| 2831 | #ifdef AHC_DEBUG |
| 2832 | if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { |
| 2833 | ahc_print_devinfo(ahc, &devinfo); |
| 2834 | printf("Asserting ATN for response\n"); |
| 2835 | } |
| 2836 | #endif |
| 2837 | ahc_assert_atn(ahc); |
| 2838 | } |
| 2839 | } else |
| 2840 | ahc->msgin_index++; |
| 2841 | |
| 2842 | if (message_done == MSGLOOP_TERMINATED) { |
| 2843 | end_session = TRUE1; |
| 2844 | } else { |
| 2845 | /* Ack the byte */ |
| 2846 | ahc_outb(ahc, CLRSINT1, CLRREQINIT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0c), (0x01)) ); |
| 2847 | ahc_inb(ahc, SCSIDATL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x06))); |
| 2848 | } |
| 2849 | break; |
| 2850 | } |
| 2851 | case MSG_TYPE_TARGET_MSGIN: |
| 2852 | { |
| 2853 | int msgdone; |
| 2854 | int msgout_request; |
| 2855 | |
| 2856 | if (ahc->msgout_len == 0) |
| 2857 | panic("Target MSGIN with no active message"); |
| 2858 | |
| 2859 | /* |
| 2860 | * If we interrupted a mesgout session, the initiator |
| 2861 | * will not know this until our first REQ. So, we |
| 2862 | * only honor mesgout requests after we've sent our |
| 2863 | * first byte. |
| 2864 | */ |
| 2865 | if ((ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & ATNI0x10) != 0 |
| 2866 | && ahc->msgout_index > 0) |
| 2867 | msgout_request = TRUE1; |
| 2868 | else |
| 2869 | msgout_request = FALSE0; |
| 2870 | |
| 2871 | if (msgout_request) { |
| 2872 | |
| 2873 | /* |
| 2874 | * Change gears and see if |
| 2875 | * this messages is of interest to |
| 2876 | * us or should be passed back to |
| 2877 | * the sequencer. |
| 2878 | */ |
| 2879 | ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; |
| 2880 | ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x03), (0xa0 | 0x04))); |
| 2881 | ahc->msgin_index = 0; |
| 2882 | /* Dummy read to REQ for first byte */ |
| 2883 | ahc_inb(ahc, SCSIDATL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x06))); |
| 2884 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))) |
| 2885 | ahc_inb(ahc, SXFRCTL0) | SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))); |
| 2886 | break; |
| 2887 | } |
| 2888 | |
| 2889 | msgdone = ahc->msgout_index == ahc->msgout_len; |
| 2890 | if (msgdone) { |
| 2891 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) & ~0x08)) ) |
| 2892 | ahc_inb(ahc, SXFRCTL0) & ~SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) & ~0x08)) ); |
| 2893 | end_session = TRUE1; |
| 2894 | break; |
| 2895 | } |
| 2896 | |
| 2897 | /* |
| 2898 | * Present the next byte on the bus. |
| 2899 | */ |
| 2900 | ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))); |
| 2901 | ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++])(((ahc)->tag)->write_1(((ahc)->bsh), (0x06), (ahc-> msgout_buf[ahc->msgout_index++]))); |
| 2902 | break; |
| 2903 | } |
| 2904 | case MSG_TYPE_TARGET_MSGOUT: |
| 2905 | { |
| 2906 | int lastbyte; |
| 2907 | int msgdone; |
| 2908 | |
| 2909 | /* |
| 2910 | * The initiator signals that this is |
| 2911 | * the last byte by dropping ATN. |
| 2912 | */ |
| 2913 | lastbyte = (ahc_inb(ahc, SCSISIGI)(((ahc)->tag)->read_1(((ahc)->bsh), (0x03))) & ATNI0x10) == 0; |
| 2914 | |
| 2915 | /* |
| 2916 | * Read the latched byte, but turn off SPIOEN first |
| 2917 | * so that we don't inadvertently cause a REQ for the |
| 2918 | * next byte. |
| 2919 | */ |
| 2920 | ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) & ~0x08)) ); |
| 2921 | ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x06))); |
| 2922 | msgdone = ahc_parse_msg(ahc, &devinfo); |
| 2923 | if (msgdone == MSGLOOP_TERMINATED) { |
| 2924 | /* |
| 2925 | * The message is *really* done in that it caused |
| 2926 | * us to go to bus free. The sequencer has already |
| 2927 | * been reset at this point, so pull the ejection |
| 2928 | * handle. |
| 2929 | */ |
| 2930 | return; |
| 2931 | } |
| 2932 | |
| 2933 | ahc->msgin_index++; |
| 2934 | |
| 2935 | /* |
| 2936 | * XXX Read spec about initiator dropping ATN too soon |
| 2937 | * and use msgdone to detect it. |
| 2938 | */ |
| 2939 | if (msgdone == MSGLOOP_MSGCOMPLETE) { |
| 2940 | ahc->msgin_index = 0; |
| 2941 | |
| 2942 | /* |
| 2943 | * If this message illicited a response, transition |
| 2944 | * to the Message in phase and send it. |
| 2945 | */ |
| 2946 | if (ahc->msgout_len != 0) { |
| 2947 | ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x03), (0xe0 | 0x04))); |
| 2948 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))) |
| 2949 | ahc_inb(ahc, SXFRCTL0) | SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))); |
| 2950 | ahc->msg_type = MSG_TYPE_TARGET_MSGIN; |
| 2951 | ahc->msgin_index = 0; |
| 2952 | break; |
| 2953 | } |
| 2954 | } |
| 2955 | |
| 2956 | if (lastbyte) |
| 2957 | end_session = TRUE1; |
| 2958 | else { |
| 2959 | /* Ask for the next byte. */ |
| 2960 | ahc_outb(ahc, SXFRCTL0,(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))) |
| 2961 | ahc_inb(ahc, SXFRCTL0) | SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x01))) | 0x08))); |
| 2962 | } |
| 2963 | |
| 2964 | break; |
| 2965 | } |
| 2966 | default: |
| 2967 | panic("Unknown REQINIT message type"); |
| 2968 | } |
| 2969 | |
| 2970 | if (end_session) { |
| 2971 | ahc_clear_msg_state(ahc); |
| 2972 | ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x51), (0x08)) ); |
| 2973 | } else |
| 2974 | ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x51), (0x04)) ); |
| 2975 | } |
| 2976 | |
| 2977 | /* |
| 2978 | * See if we sent a particular extended message to the target. |
| 2979 | * If "full" is true, return true only if the target saw the full |
| 2980 | * message. If "full" is false, return true if the target saw at |
| 2981 | * least the first byte of the message. |
| 2982 | */ |
| 2983 | static int |
| 2984 | ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) |
| 2985 | { |
| 2986 | int found; |
| 2987 | u_int index; |
| 2988 | |
| 2989 | found = FALSE0; |
| 2990 | index = 0; |
| 2991 | |
| 2992 | while (index < ahc->msgout_len) { |
| 2993 | if (ahc->msgout_buf[index] == MSG_EXTENDED0x01) { |
| 2994 | u_int end_index; |
| 2995 | |
| 2996 | end_index = index + 1 + ahc->msgout_buf[index + 1]; |
| 2997 | if (ahc->msgout_buf[index+2] == msgval |
| 2998 | && type == AHCMSG_EXT) { |
| 2999 | |
| 3000 | if (full) { |
| 3001 | if (ahc->msgout_index > end_index) |
| 3002 | found = TRUE1; |
| 3003 | } else if (ahc->msgout_index > index) |
| 3004 | found = TRUE1; |
| 3005 | } |
| 3006 | index = end_index; |
| 3007 | } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK0x20 |
| 3008 | && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE0x23) { |
| 3009 | |
| 3010 | /* Skip tag type and tag id or residue param*/ |
| 3011 | index += 2; |
| 3012 | } else { |
| 3013 | /* Single byte message */ |
| 3014 | if (type == AHCMSG_1B |
| 3015 | && ahc->msgout_buf[index] == msgval |
| 3016 | && ahc->msgout_index > index) |
| 3017 | found = TRUE1; |
| 3018 | index++; |
| 3019 | } |
| 3020 | |
| 3021 | if (found) |
| 3022 | break; |
| 3023 | } |
| 3024 | return (found); |
| 3025 | } |
| 3026 | |
| 3027 | /* |
| 3028 | * Wait for a complete incoming message, parse it, and respond accordingly. |
| 3029 | */ |
| 3030 | static int |
| 3031 | ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 3032 | { |
| 3033 | struct ahc_initiator_tinfo *tinfo; |
| 3034 | struct ahc_tmode_tstate *tstate; |
| 3035 | int reject; |
| 3036 | int done; |
| 3037 | int response; |
| 3038 | u_int targ_scsirate; |
| 3039 | |
| 3040 | done = MSGLOOP_IN_PROG; |
| 3041 | response = FALSE0; |
| 3042 | reject = FALSE0; |
| 3043 | tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, |
| 3044 | devinfo->target, &tstate); |
| 3045 | targ_scsirate = tinfo->scsirate; |
| 3046 | |
| 3047 | /* |
| 3048 | * Parse as much of the message as is available, |
| 3049 | * rejecting it if we don't support it. When |
| 3050 | * the entire message is available and has been |
| 3051 | * handled, return MSGLOOP_MSGCOMPLETE, indicating |
| 3052 | * that we have parsed an entire message. |
| 3053 | * |
| 3054 | * In the case of extended messages, we accept the length |
| 3055 | * byte outright and perform more checking once we know the |
| 3056 | * extended message type. |
| 3057 | */ |
| 3058 | switch (ahc->msgin_buf[0]) { |
| 3059 | case MSG_DISCONNECT0x04: |
| 3060 | case MSG_SAVEDATAPOINTER0x02: |
| 3061 | case MSG_CMDCOMPLETE0x00: |
| 3062 | case MSG_RESTOREPOINTERS0x03: |
| 3063 | case MSG_IGN_WIDE_RESIDUE0x23: |
| 3064 | /* |
| 3065 | * End our message loop as these are messages |
| 3066 | * the sequencer handles on its own. |
| 3067 | */ |
| 3068 | done = MSGLOOP_TERMINATED; |
| 3069 | break; |
| 3070 | case MSG_MESSAGE_REJECT0x07: |
| 3071 | response = ahc_handle_msg_reject(ahc, devinfo); |
| 3072 | /* FALLTHROUGH */ |
| 3073 | case MSG_NOOP0x08: |
| 3074 | done = MSGLOOP_MSGCOMPLETE; |
| 3075 | break; |
| 3076 | case MSG_EXTENDED0x01: |
| 3077 | { |
| 3078 | /* Wait for enough of the message to begin validation */ |
| 3079 | if (ahc->msgin_index < 2) |
| 3080 | break; |
| 3081 | switch (ahc->msgin_buf[2]) { |
| 3082 | case MSG_EXT_SDTR0x01: |
| 3083 | { |
| 3084 | struct ahc_syncrate *syncrate; |
| 3085 | u_int period; |
| 3086 | u_int ppr_options; |
| 3087 | u_int offset; |
| 3088 | u_int saved_offset; |
| 3089 | |
| 3090 | if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN0x03) { |
| 3091 | reject = TRUE1; |
| 3092 | break; |
| 3093 | } |
| 3094 | |
| 3095 | /* |
| 3096 | * Wait until we have both args before validating |
| 3097 | * and acting on this message. |
| 3098 | * |
| 3099 | * Add one to MSG_EXT_SDTR_LEN to account for |
| 3100 | * the extended message preamble. |
| 3101 | */ |
| 3102 | if (ahc->msgin_index < (MSG_EXT_SDTR_LEN0x03 + 1)) |
| 3103 | break; |
| 3104 | |
| 3105 | period = ahc->msgin_buf[3]; |
| 3106 | ppr_options = 0; |
| 3107 | saved_offset = offset = ahc->msgin_buf[4]; |
| 3108 | syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, |
| 3109 | &ppr_options, |
| 3110 | devinfo->role); |
| 3111 | ahc_validate_offset(ahc, tinfo, syncrate, &offset, |
| 3112 | targ_scsirate & WIDEXFER0x80, |
| 3113 | devinfo->role); |
| 3114 | if (bootverbose0) { |
| 3115 | printf("(%s:%c:%d:%d): Received " |
| 3116 | "SDTR period %x, offset %x\n\t" |
| 3117 | "Filtered to period %x, offset %x\n", |
| 3118 | ahc_name(ahc), devinfo->channel, |
| 3119 | devinfo->target, devinfo->lun, |
| 3120 | ahc->msgin_buf[3], saved_offset, |
| 3121 | period, offset); |
| 3122 | } |
| 3123 | ahc_set_syncrate(ahc, devinfo, |
| 3124 | syncrate, period, |
| 3125 | offset, ppr_options, |
| 3126 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3127 | /*paused*/TRUE1); |
| 3128 | |
| 3129 | /* |
| 3130 | * See if we initiated Sync Negotiation |
| 3131 | * and didn't have to fall down to async |
| 3132 | * transfers. |
| 3133 | */ |
| 3134 | if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR0x01, TRUE1)) { |
| 3135 | /* We started it */ |
| 3136 | if (saved_offset != offset) { |
| 3137 | /* Went too low - force async */ |
| 3138 | reject = TRUE1; |
| 3139 | } |
| 3140 | } else { |
| 3141 | /* |
| 3142 | * Send our own SDTR in reply |
| 3143 | */ |
| 3144 | if (bootverbose0 |
| 3145 | && devinfo->role == ROLE_INITIATOR) { |
| 3146 | printf("(%s:%c:%d:%d): Target " |
| 3147 | "Initiated SDTR\n", |
| 3148 | ahc_name(ahc), devinfo->channel, |
| 3149 | devinfo->target, devinfo->lun); |
| 3150 | } |
| 3151 | ahc->msgout_index = 0; |
| 3152 | ahc->msgout_len = 0; |
| 3153 | ahc_construct_sdtr(ahc, devinfo, |
| 3154 | period, offset); |
| 3155 | ahc->msgout_index = 0; |
| 3156 | response = TRUE1; |
| 3157 | } |
| 3158 | done = MSGLOOP_MSGCOMPLETE; |
| 3159 | break; |
| 3160 | } |
| 3161 | case MSG_EXT_WDTR0x03: |
| 3162 | { |
| 3163 | u_int bus_width; |
| 3164 | u_int saved_width; |
| 3165 | u_int sending_reply; |
| 3166 | |
| 3167 | sending_reply = FALSE0; |
| 3168 | if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN0x02) { |
| 3169 | reject = TRUE1; |
| 3170 | break; |
| 3171 | } |
| 3172 | |
| 3173 | /* |
| 3174 | * Wait until we have our arg before validating |
| 3175 | * and acting on this message. |
| 3176 | * |
| 3177 | * Add one to MSG_EXT_WDTR_LEN to account for |
| 3178 | * the extended message preamble. |
| 3179 | */ |
| 3180 | if (ahc->msgin_index < (MSG_EXT_WDTR_LEN0x02 + 1)) |
| 3181 | break; |
| 3182 | |
| 3183 | bus_width = ahc->msgin_buf[3]; |
| 3184 | saved_width = bus_width; |
| 3185 | ahc_validate_width(ahc, tinfo, &bus_width, |
| 3186 | devinfo->role); |
| 3187 | if (bootverbose0) { |
| 3188 | printf("(%s:%c:%d:%d): Received WDTR " |
| 3189 | "%x filtered to %x\n", |
| 3190 | ahc_name(ahc), devinfo->channel, |
| 3191 | devinfo->target, devinfo->lun, |
| 3192 | saved_width, bus_width); |
| 3193 | } |
| 3194 | |
| 3195 | if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR0x03, TRUE1)) { |
| 3196 | /* |
| 3197 | * Don't send a WDTR back to the |
| 3198 | * target, since we asked first. |
| 3199 | * If the width went higher than our |
| 3200 | * request, reject it. |
| 3201 | */ |
| 3202 | if (saved_width > bus_width) { |
| 3203 | reject = TRUE1; |
| 3204 | printf("(%s:%c:%d:%d): requested %dBit " |
| 3205 | "transfers. Rejecting...\n", |
| 3206 | ahc_name(ahc), devinfo->channel, |
| 3207 | devinfo->target, devinfo->lun, |
| 3208 | 8 * (0x01 << bus_width)); |
| 3209 | bus_width = 0; |
| 3210 | } |
| 3211 | } else { |
| 3212 | /* |
| 3213 | * Send our own WDTR in reply |
| 3214 | */ |
| 3215 | if (bootverbose0 |
| 3216 | && devinfo->role == ROLE_INITIATOR) { |
| 3217 | printf("(%s:%c:%d:%d): Target " |
| 3218 | "Initiated WDTR\n", |
| 3219 | ahc_name(ahc), devinfo->channel, |
| 3220 | devinfo->target, devinfo->lun); |
| 3221 | } |
| 3222 | ahc->msgout_index = 0; |
| 3223 | ahc->msgout_len = 0; |
| 3224 | ahc_construct_wdtr(ahc, devinfo, bus_width); |
| 3225 | ahc->msgout_index = 0; |
| 3226 | response = TRUE1; |
| 3227 | sending_reply = TRUE1; |
| 3228 | } |
| 3229 | /* |
| 3230 | * After a wide message, we are async, but |
| 3231 | * some devices don't seem to honor this portion |
| 3232 | * of the spec. Force a renegotiation of the |
| 3233 | * sync component of our transfer agreement even |
| 3234 | * if our goal is async. By updating our width |
| 3235 | * after forcing the negotiation, we avoid |
| 3236 | * renegotiating for width. |
| 3237 | */ |
| 3238 | ahc_update_neg_request(ahc, devinfo, tstate, |
| 3239 | tinfo, AHC_NEG_ALWAYS); |
| 3240 | ahc_set_width(ahc, devinfo, bus_width, |
| 3241 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3242 | /*paused*/TRUE1); |
| 3243 | if (sending_reply == FALSE0 && reject == FALSE0) { |
| 3244 | |
| 3245 | /* |
| 3246 | * We will always have an SDTR to send. |
| 3247 | */ |
| 3248 | ahc->msgout_index = 0; |
| 3249 | ahc->msgout_len = 0; |
| 3250 | ahc_build_transfer_msg(ahc, devinfo); |
| 3251 | ahc->msgout_index = 0; |
| 3252 | response = TRUE1; |
| 3253 | } |
| 3254 | done = MSGLOOP_MSGCOMPLETE; |
| 3255 | break; |
| 3256 | } |
| 3257 | case MSG_EXT_PPR0x04: |
| 3258 | { |
| 3259 | struct ahc_syncrate *syncrate; |
| 3260 | u_int period; |
| 3261 | u_int offset; |
| 3262 | u_int bus_width; |
| 3263 | u_int ppr_options; |
| 3264 | u_int saved_width; |
| 3265 | u_int saved_offset; |
| 3266 | u_int saved_ppr_options; |
| 3267 | |
| 3268 | if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN0x06) { |
| 3269 | reject = TRUE1; |
| 3270 | break; |
| 3271 | } |
| 3272 | |
| 3273 | /* |
| 3274 | * Wait until we have all args before validating |
| 3275 | * and acting on this message. |
| 3276 | * |
| 3277 | * Add one to MSG_EXT_PPR_LEN to account for |
| 3278 | * the extended message preamble. |
| 3279 | */ |
| 3280 | if (ahc->msgin_index < (MSG_EXT_PPR_LEN0x06 + 1)) |
| 3281 | break; |
| 3282 | |
| 3283 | period = ahc->msgin_buf[3]; |
| 3284 | offset = ahc->msgin_buf[5]; |
| 3285 | bus_width = ahc->msgin_buf[6]; |
| 3286 | saved_width = bus_width; |
| 3287 | ppr_options = ahc->msgin_buf[7]; |
| 3288 | /* |
| 3289 | * According to the spec, a DT only |
| 3290 | * period factor with no DT option |
| 3291 | * set implies async. |
| 3292 | */ |
| 3293 | if ((ppr_options & MSG_EXT_PPR_DT_REQ0x02) == 0 |
| 3294 | && period == 9) |
| 3295 | offset = 0; |
| 3296 | saved_ppr_options = ppr_options; |
| 3297 | saved_offset = offset; |
| 3298 | |
| 3299 | /* |
| 3300 | * Mask out any options we don't support |
| 3301 | * on any controller. Transfer options are |
| 3302 | * only available if we are negotiating wide. |
| 3303 | */ |
| 3304 | ppr_options &= MSG_EXT_PPR_DT_REQ0x02; |
| 3305 | if (bus_width == 0) |
| 3306 | ppr_options = 0; |
| 3307 | |
| 3308 | ahc_validate_width(ahc, tinfo, &bus_width, |
| 3309 | devinfo->role); |
| 3310 | syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, |
| 3311 | &ppr_options, |
| 3312 | devinfo->role); |
| 3313 | ahc_validate_offset(ahc, tinfo, syncrate, |
| 3314 | &offset, bus_width, |
| 3315 | devinfo->role); |
| 3316 | |
| 3317 | if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR0x04, TRUE1)) { |
| 3318 | /* |
| 3319 | * If we are unable to do any of the |
| 3320 | * requested options (we went too low), |
| 3321 | * then we'll have to reject the message. |
| 3322 | */ |
| 3323 | if (saved_width > bus_width |
| 3324 | || saved_offset != offset |
| 3325 | || saved_ppr_options != ppr_options) { |
| 3326 | reject = TRUE1; |
| 3327 | period = 0; |
| 3328 | offset = 0; |
| 3329 | bus_width = 0; |
| 3330 | ppr_options = 0; |
| 3331 | syncrate = NULL((void *)0); |
| 3332 | } |
| 3333 | } else { |
| 3334 | if (devinfo->role != ROLE_TARGET) |
| 3335 | printf("(%s:%c:%d:%d): Target " |
| 3336 | "Initiated PPR\n", |
| 3337 | ahc_name(ahc), devinfo->channel, |
| 3338 | devinfo->target, devinfo->lun); |
| 3339 | else |
| 3340 | printf("(%s:%c:%d:%d): Initiator " |
| 3341 | "Initiated PPR\n", |
| 3342 | ahc_name(ahc), devinfo->channel, |
| 3343 | devinfo->target, devinfo->lun); |
| 3344 | ahc->msgout_index = 0; |
| 3345 | ahc->msgout_len = 0; |
| 3346 | ahc_construct_ppr(ahc, devinfo, period, offset, |
| 3347 | bus_width, ppr_options); |
| 3348 | ahc->msgout_index = 0; |
| 3349 | response = TRUE1; |
| 3350 | } |
| 3351 | if (bootverbose0) { |
| 3352 | printf("(%s:%c:%d:%d): Received PPR width %x, " |
| 3353 | "period %x, offset %x,options %x\n" |
| 3354 | "\tFiltered to width %x, period %x, " |
| 3355 | "offset %x, options %x\n", |
| 3356 | ahc_name(ahc), devinfo->channel, |
| 3357 | devinfo->target, devinfo->lun, |
| 3358 | saved_width, ahc->msgin_buf[3], |
| 3359 | saved_offset, saved_ppr_options, |
| 3360 | bus_width, period, offset, ppr_options); |
| 3361 | } |
| 3362 | ahc_set_width(ahc, devinfo, bus_width, |
| 3363 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3364 | /*paused*/TRUE1); |
| 3365 | ahc_set_syncrate(ahc, devinfo, |
| 3366 | syncrate, period, |
| 3367 | offset, ppr_options, |
| 3368 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3369 | /*paused*/TRUE1); |
| 3370 | done = MSGLOOP_MSGCOMPLETE; |
| 3371 | break; |
| 3372 | } |
| 3373 | default: |
| 3374 | /* Unknown extended message. Reject it. */ |
| 3375 | reject = TRUE1; |
| 3376 | break; |
| 3377 | } |
| 3378 | break; |
| 3379 | } |
| 3380 | #ifdef AHC_TARGET_MODE |
| 3381 | case MSG_BUS_DEV_RESET0x0c: |
| 3382 | ahc_handle_devreset(ahc, devinfo, |
| 3383 | CAM_BDR_SENT, |
| 3384 | "Bus Device Reset Received", |
| 3385 | /*verbose_level*/0); |
| 3386 | ahc_restart(ahc); |
| 3387 | done = MSGLOOP_TERMINATED; |
| 3388 | break; |
| 3389 | case MSG_ABORT_TAG0x0d: |
| 3390 | case MSG_ABORT0x06: |
| 3391 | case MSG_CLEAR_QUEUE0x0e: |
| 3392 | { |
| 3393 | int tag; |
| 3394 | |
| 3395 | /* Target mode messages */ |
| 3396 | if (devinfo->role != ROLE_TARGET) { |
| 3397 | reject = TRUE1; |
| 3398 | break; |
| 3399 | } |
| 3400 | tag = SCB_LIST_NULL0xff; |
| 3401 | if (ahc->msgin_buf[0] == MSG_ABORT_TAG0x0d) |
| 3402 | tag = ahc_inb(ahc, INITIATOR_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0x56))); |
| 3403 | ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, |
| 3404 | devinfo->lun, tag, ROLE_TARGET, |
| 3405 | CAM_REQ_ABORTED); |
| 3406 | |
| 3407 | tstate = ahc->enabled_targets[devinfo->our_scsiid]; |
| 3408 | if (tstate != NULL((void *)0)) { |
| 3409 | struct ahc_tmode_lstate* lstate; |
| 3410 | |
| 3411 | lstate = tstate->enabled_luns[devinfo->lun]; |
| 3412 | if (lstate != NULL((void *)0)) { |
| 3413 | ahc_queue_lstate_event(ahc, lstate, |
| 3414 | devinfo->our_scsiid, |
| 3415 | ahc->msgin_buf[0], |
| 3416 | /*arg*/tag); |
| 3417 | ahc_send_lstate_events(ahc, lstate); |
| 3418 | } |
| 3419 | } |
| 3420 | ahc_restart(ahc); |
| 3421 | done = MSGLOOP_TERMINATED; |
| 3422 | break; |
| 3423 | } |
| 3424 | #endif |
| 3425 | case MSG_TERM_IO_PROC0x11: |
| 3426 | default: |
| 3427 | reject = TRUE1; |
| 3428 | break; |
| 3429 | } |
| 3430 | |
| 3431 | if (reject) { |
| 3432 | /* |
| 3433 | * Setup to reject the message. |
| 3434 | */ |
| 3435 | ahc->msgout_index = 0; |
| 3436 | ahc->msgout_len = 1; |
| 3437 | ahc->msgout_buf[0] = MSG_MESSAGE_REJECT0x07; |
| 3438 | done = MSGLOOP_MSGCOMPLETE; |
| 3439 | response = TRUE1; |
| 3440 | } |
| 3441 | |
| 3442 | if (done != MSGLOOP_IN_PROG && !response) |
| 3443 | /* Clear the outgoing message buffer */ |
| 3444 | ahc->msgout_len = 0; |
| 3445 | |
| 3446 | return (done); |
| 3447 | } |
| 3448 | |
| 3449 | /* |
| 3450 | * Process a message reject message. |
| 3451 | */ |
| 3452 | static int |
| 3453 | ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 3454 | { |
| 3455 | /* |
| 3456 | * What we care about here is if we had an |
| 3457 | * outstanding SDTR or WDTR message for this |
| 3458 | * target. If we did, this is a signal that |
| 3459 | * the target is refusing negotiation. |
| 3460 | */ |
| 3461 | struct scb *scb; |
| 3462 | struct ahc_initiator_tinfo *tinfo; |
| 3463 | struct ahc_tmode_tstate *tstate; |
| 3464 | u_int scb_index; |
| 3465 | u_int last_msg; |
| 3466 | int response = 0; |
| 3467 | |
| 3468 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 3469 | scb = ahc_lookup_scb(ahc, scb_index); |
| 3470 | tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, |
| 3471 | devinfo->our_scsiid, |
| 3472 | devinfo->target, &tstate); |
| 3473 | /* Might be necessary */ |
| 3474 | last_msg = ahc_inb(ahc, LAST_MSG)(((ahc)->tag)->read_1(((ahc)->bsh), (0x53))); |
| 3475 | |
| 3476 | if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR0x04, /*full*/FALSE0)) { |
| 3477 | /* |
| 3478 | * Target does not support the PPR message. |
| 3479 | * Attempt to negotiate SPI-2 style. |
| 3480 | */ |
| 3481 | if (bootverbose0) { |
| 3482 | printf("(%s:%c:%d:%d): PPR Rejected. " |
| 3483 | "Trying WDTR/SDTR\n", |
| 3484 | ahc_name(ahc), devinfo->channel, |
| 3485 | devinfo->target, devinfo->lun); |
| 3486 | } |
| 3487 | tinfo->goal.ppr_options = 0; |
| 3488 | tinfo->curr.transport_version = 2; |
| 3489 | tinfo->goal.transport_version = 2; |
| 3490 | ahc->msgout_index = 0; |
| 3491 | ahc->msgout_len = 0; |
| 3492 | ahc_build_transfer_msg(ahc, devinfo); |
| 3493 | ahc->msgout_index = 0; |
| 3494 | response = 1; |
| 3495 | } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR0x03, /*full*/FALSE0)) { |
| 3496 | |
| 3497 | /* note 8bit xfers */ |
| 3498 | printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " |
| 3499 | "8bit transfers\n", ahc_name(ahc), |
| 3500 | devinfo->channel, devinfo->target, devinfo->lun); |
| 3501 | ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT0x00, |
| 3502 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3503 | /*paused*/TRUE1); |
| 3504 | /* |
| 3505 | * No need to clear the sync rate. If the target |
| 3506 | * did not accept the command, our syncrate is |
| 3507 | * unaffected. If the target started the negotiation, |
| 3508 | * but rejected our response, we already cleared the |
| 3509 | * sync rate before sending our WDTR. |
| 3510 | */ |
| 3511 | if (tinfo->goal.offset != tinfo->curr.offset) { |
| 3512 | |
| 3513 | /* Start the sync negotiation */ |
| 3514 | ahc->msgout_index = 0; |
| 3515 | ahc->msgout_len = 0; |
| 3516 | ahc_build_transfer_msg(ahc, devinfo); |
| 3517 | ahc->msgout_index = 0; |
| 3518 | response = 1; |
| 3519 | } |
| 3520 | } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR0x01, /*full*/FALSE0)) { |
| 3521 | /* note asynch xfers and clear flag */ |
| 3522 | ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL((void *)0), /*period*/0, |
| 3523 | /*offset*/0, /*ppr_options*/0, |
| 3524 | AHC_TRANS_ACTIVE0x03|AHC_TRANS_GOAL0x04, |
| 3525 | /*paused*/TRUE1); |
| 3526 | printf("(%s:%c:%d:%d): refuses synchronous negotiation. " |
| 3527 | "Using asynchronous transfers\n", |
| 3528 | ahc_name(ahc), devinfo->channel, |
| 3529 | devinfo->target, devinfo->lun); |
| 3530 | } else if ((scb->hscb->control & MSG_SIMPLE_TASK0x20) != 0) { |
| 3531 | int tag_type; |
| 3532 | int mask; |
| 3533 | |
| 3534 | tag_type = (scb->hscb->control & MSG_SIMPLE_TASK0x20); |
| 3535 | |
| 3536 | if (tag_type == MSG_SIMPLE_TASK0x20) { |
| 3537 | printf("(%s:%c:%d:%d): refuses tagged commands. " |
| 3538 | "Performing non-tagged I/O\n", ahc_name(ahc), |
| 3539 | devinfo->channel, devinfo->target, devinfo->lun); |
| 3540 | ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); |
| 3541 | mask = ~0x23; |
| 3542 | } else { |
| 3543 | printf("(%s:%c:%d:%d): refuses %s tagged commands. " |
| 3544 | "Performing simple queue tagged I/O only\n", |
| 3545 | ahc_name(ahc), devinfo->channel, devinfo->target, |
| 3546 | devinfo->lun, tag_type == MSG_ORDERED_TASK0x22 |
| 3547 | ? "ordered" : "head of queue"); |
| 3548 | ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); |
| 3549 | mask = ~0x03; |
| 3550 | } |
| 3551 | |
| 3552 | /* |
| 3553 | * Resend the identify for this CCB as the target |
| 3554 | * may believe that the selection is invalid otherwise. |
| 3555 | */ |
| 3556 | ahc_outb(ahc, SCB_CONTROL,(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), ((((ahc )->tag)->read_1(((ahc)->bsh), (0xb8))) & mask))) |
| 3557 | ahc_inb(ahc, SCB_CONTROL) & mask)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), ((((ahc )->tag)->read_1(((ahc)->bsh), (0xb8))) & mask))); |
| 3558 | scb->hscb->control &= mask; |
| 3559 | ahc_set_transaction_tag(scb, /*enabled*/FALSE0, |
| 3560 | /*type*/MSG_SIMPLE_TASK0x20); |
| 3561 | ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0x80)) ); |
| 3562 | ahc_assert_atn(ahc); |
| 3563 | |
| 3564 | /* |
| 3565 | * This transaction is now at the head of |
| 3566 | * the untagged queue for this target. |
| 3567 | */ |
| 3568 | if ((ahc->flags & AHC_SCB_BTT) == 0) { |
| 3569 | struct scb_tailq *untagged_q; |
| 3570 | |
| 3571 | untagged_q = |
| 3572 | &(ahc->untagged_queues[devinfo->target_offset]); |
| 3573 | TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe)do { if (((scb)->links.tqe.tqe_next = (untagged_q)->tqh_first ) != ((void *)0)) (untagged_q)->tqh_first->links.tqe.tqe_prev = &(scb)->links.tqe.tqe_next; else (untagged_q)->tqh_last = &(scb)->links.tqe.tqe_next; (untagged_q)->tqh_first = (scb); (scb)->links.tqe.tqe_prev = &(untagged_q)-> tqh_first; } while (0); |
| 3574 | scb->flags |= SCB_UNTAGGEDQ; |
| 3575 | } |
| 3576 | ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun)((devinfo->lun) | (((scb->hscb->scsiid) & 0xf0) << 4)), |
| 3577 | scb->hscb->tag); |
| 3578 | |
| 3579 | /* |
| 3580 | * Requeue all tagged commands for this target |
| 3581 | * currently in our possession so they can be |
| 3582 | * converted to untagged commands. |
| 3583 | */ |
| 3584 | ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb)((((scb)->hscb->scsiid) & (((((ahc))->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04), |
| 3585 | SCB_GET_CHANNEL(ahc, scb)((((ahc)->features & AHC_TWIN) != 0) ? (((((scb)->hscb ->scsiid) & 0x80) != 0) ? 'B' : 'A') : 'A'), |
| 3586 | SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f), /*tag*/SCB_LIST_NULL0xff, |
| 3587 | ROLE_INITIATOR, CAM_REQUEUE_REQ, |
| 3588 | SEARCH_COMPLETE); |
| 3589 | } else { |
| 3590 | /* |
| 3591 | * Otherwise, we ignore it. |
| 3592 | */ |
| 3593 | printf("%s:%c:%d: Message reject for %x -- ignored\n", |
| 3594 | ahc_name(ahc), devinfo->channel, devinfo->target, |
| 3595 | last_msg); |
| 3596 | } |
| 3597 | return (response); |
| 3598 | } |
| 3599 | |
| 3600 | /* |
| 3601 | * Process an ignore wide residue message. |
| 3602 | */ |
| 3603 | static void |
| 3604 | ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) |
| 3605 | { |
| 3606 | u_int scb_index; |
| 3607 | struct scb *scb; |
| 3608 | |
| 3609 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 3610 | scb = ahc_lookup_scb(ahc, scb_index); |
| 3611 | /* |
| 3612 | * XXX Actually check data direction in the sequencer? |
| 3613 | * Perhaps add datadir to some spare bits in the hscb? |
| 3614 | */ |
| 3615 | if ((ahc_inb(ahc, SEQ_FLAGS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x3c))) & DPHASE0x20) == 0 |
| 3616 | || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { |
| 3617 | /* |
| 3618 | * Ignore the message if we haven't |
| 3619 | * seen an appropriate data phase yet. |
| 3620 | */ |
| 3621 | } else { |
| 3622 | /* |
| 3623 | * If the residual occurred on the last |
| 3624 | * transfer and the transfer request was |
| 3625 | * expected to end on an odd count, do |
| 3626 | * nothing. Otherwise, subtract a byte |
| 3627 | * and update the residual count accordingly. |
| 3628 | */ |
| 3629 | uint32_t sgptr; |
| 3630 | |
| 3631 | sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa4))); |
| 3632 | if ((sgptr & SG_LIST_NULL0x01) != 0 |
| 3633 | && (ahc_inb(ahc, SCB_LUN)(((ahc)->tag)->read_1(((ahc)->bsh), (0xba))) & SCB_XFERLEN_ODD0x80) != 0) { |
| 3634 | /* |
| 3635 | * If the residual occurred on the last |
| 3636 | * transfer and the transfer request was |
| 3637 | * expected to end on an odd count, do |
| 3638 | * nothing. |
| 3639 | */ |
| 3640 | } else { |
| 3641 | struct ahc_dma_seg *sg; |
| 3642 | uint32_t data_cnt; |
| 3643 | uint32_t data_addr; |
| 3644 | uint32_t sglen; |
| 3645 | |
| 3646 | /* Pull in all of the sgptr */ |
| 3647 | sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR0xa4); |
| 3648 | data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT0xa0); |
| 3649 | |
| 3650 | if ((sgptr & SG_LIST_NULL0x01) != 0) { |
| 3651 | /* |
| 3652 | * The residual data count is not updated |
| 3653 | * for the command run to completion case. |
| 3654 | * Explicitly zero the count. |
| 3655 | */ |
| 3656 | data_cnt &= ~AHC_SG_LEN_MASK0x00FFFFFF; |
| 3657 | } |
| 3658 | |
| 3659 | data_addr = ahc_inl(ahc, SHADDR0x14); |
| 3660 | |
| 3661 | data_cnt += 1; |
| 3662 | data_addr -= 1; |
| 3663 | sgptr &= SG_PTR_MASK0xFFFFFFF8; |
| 3664 | |
| 3665 | sg = ahc_sg_bus_to_virt(scb, sgptr); |
| 3666 | |
| 3667 | /* |
| 3668 | * The residual sg ptr points to the next S/G |
| 3669 | * to load so we must go back one. |
| 3670 | */ |
| 3671 | sg--; |
| 3672 | sglen = aic_le32toh(sg->len)((__uint32_t)(sg->len)) & AHC_SG_LEN_MASK0x00FFFFFF; |
| 3673 | if (sg != scb->sg_list |
| 3674 | && sglen < (data_cnt & AHC_SG_LEN_MASK0x00FFFFFF)) { |
| 3675 | |
| 3676 | sg--; |
| 3677 | sglen = aic_le32toh(sg->len)((__uint32_t)(sg->len)); |
| 3678 | /* |
| 3679 | * Preserve High Address and SG_LIST bits |
| 3680 | * while setting the count to 1. |
| 3681 | */ |
| 3682 | data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK0x00FFFFFF)); |
| 3683 | data_addr = aic_le32toh(sg->addr)((__uint32_t)(sg->addr)) |
Value stored to 'data_addr' is never read | |
| 3684 | + (sglen & AHC_SG_LEN_MASK0x00FFFFFF) - 1; |
| 3685 | |
| 3686 | /* |
| 3687 | * Increment sg so it points to the |
| 3688 | * "next" sg. |
| 3689 | */ |
| 3690 | sg++; |
| 3691 | sgptr = ahc_sg_virt_to_bus(scb, sg); |
| 3692 | } |
| 3693 | ahc_outl(ahc, SCB_RESIDUAL_SGPTR0xa4, sgptr); |
| 3694 | ahc_outl(ahc, SCB_RESIDUAL_DATACNT0xa0, data_cnt); |
| 3695 | /* |
| 3696 | * Toggle the "oddness" of the transfer length |
| 3697 | * to handle this mid-transfer ignore wide |
| 3698 | * residue. This ensures that the oddness is |
| 3699 | * correct for subsequent data transfers. |
| 3700 | */ |
| 3701 | ahc_outb(ahc, SCB_LUN,(((ahc)->tag)->write_1(((ahc)->bsh), (0xba), ((((ahc )->tag)->read_1(((ahc)->bsh), (0xba))) ^ 0x80))) |
| 3702 | ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD)(((ahc)->tag)->write_1(((ahc)->bsh), (0xba), ((((ahc )->tag)->read_1(((ahc)->bsh), (0xba))) ^ 0x80))); |
| 3703 | } |
| 3704 | } |
| 3705 | } |
| 3706 | |
| 3707 | |
| 3708 | /* |
| 3709 | * Reinitialize the data pointers for the active transfer |
| 3710 | * based on its current residual. |
| 3711 | */ |
| 3712 | static void |
| 3713 | ahc_reinitialize_dataptrs(struct ahc_softc *ahc) |
| 3714 | { |
| 3715 | struct scb *scb; |
| 3716 | struct ahc_dma_seg *sg; |
| 3717 | u_int scb_index; |
| 3718 | uint32_t sgptr; |
| 3719 | uint32_t resid; |
| 3720 | uint32_t dataptr; |
| 3721 | |
| 3722 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 3723 | scb = ahc_lookup_scb(ahc, scb_index); |
| 3724 | sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa4 + 3))) << 24) |
| 3725 | | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa4 + 2))) << 16) |
| 3726 | | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa4 + 1))) << 8) |
| 3727 | | ahc_inb(ahc, SCB_RESIDUAL_SGPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa4))); |
| 3728 | |
| 3729 | sgptr &= SG_PTR_MASK0xFFFFFFF8; |
| 3730 | sg = ahc_sg_bus_to_virt(scb, sgptr); |
| 3731 | |
| 3732 | /* The residual sg_ptr always points to the next sg */ |
| 3733 | sg--; |
| 3734 | |
| 3735 | resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa0 + 2))) << 16) |
| 3736 | | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa0 + 1))) << 8) |
| 3737 | | ahc_inb(ahc, SCB_RESIDUAL_DATACNT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa0))); |
| 3738 | |
| 3739 | dataptr = aic_le32toh(sg->addr)((__uint32_t)(sg->addr)) |
| 3740 | + (aic_le32toh(sg->len)((__uint32_t)(sg->len)) & AHC_SG_LEN_MASK0x00FFFFFF) |
| 3741 | - resid; |
| 3742 | if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { |
| 3743 | u_int dscommand1; |
| 3744 | |
| 3745 | dscommand1 = ahc_inb(ahc, DSCOMMAND1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x85))); |
| 3746 | ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x85), (dscommand1 | 0x01))); |
| 3747 | ahc_outb(ahc, HADDR,(((ahc)->tag)->write_1(((ahc)->bsh), (0x88), ((((__uint32_t )(sg->len)) >> 24) & 0x7f))) |
| 3748 | (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88), ((((__uint32_t )(sg->len)) >> 24) & 0x7f))); |
| 3749 | ahc_outb(ahc, DSCOMMAND1, dscommand1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x85), (dscommand1 ))); |
| 3750 | } |
| 3751 | ahc_outb(ahc, HADDR + 3, dataptr >> 24)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88 + 3), (dataptr >> 24))); |
| 3752 | ahc_outb(ahc, HADDR + 2, dataptr >> 16)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88 + 2), (dataptr >> 16))); |
| 3753 | ahc_outb(ahc, HADDR + 1, dataptr >> 8)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88 + 1), (dataptr >> 8))); |
| 3754 | ahc_outb(ahc, HADDR, dataptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x88), (dataptr ))); |
| 3755 | ahc_outb(ahc, HCNT + 2, resid >> 16)(((ahc)->tag)->write_1(((ahc)->bsh), (0x8c + 2), (resid >> 16))); |
| 3756 | ahc_outb(ahc, HCNT + 1, resid >> 8)(((ahc)->tag)->write_1(((ahc)->bsh), (0x8c + 1), (resid >> 8))); |
| 3757 | ahc_outb(ahc, HCNT, resid)(((ahc)->tag)->write_1(((ahc)->bsh), (0x8c), (resid) )); |
| 3758 | if ((ahc->features & AHC_ULTRA2) == 0) { |
| 3759 | ahc_outb(ahc, STCNT + 2, resid >> 16)(((ahc)->tag)->write_1(((ahc)->bsh), (0x08 + 2), (resid >> 16))); |
| 3760 | ahc_outb(ahc, STCNT + 1, resid >> 8)(((ahc)->tag)->write_1(((ahc)->bsh), (0x08 + 1), (resid >> 8))); |
| 3761 | ahc_outb(ahc, STCNT, resid)(((ahc)->tag)->write_1(((ahc)->bsh), (0x08), (resid) )); |
| 3762 | } |
| 3763 | } |
| 3764 | |
| 3765 | /* |
| 3766 | * Handle the effects of issuing a bus device reset message. |
| 3767 | */ |
| 3768 | static void |
| 3769 | ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 3770 | cam_status status, char *message, int verbose_level) |
| 3771 | { |
| 3772 | #ifdef AHC_TARGET_MODE |
| 3773 | struct ahc_tmode_tstate* tstate; |
| 3774 | u_int lun; |
| 3775 | #endif |
| 3776 | int found; |
| 3777 | |
| 3778 | found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, |
| 3779 | CAM_LUN_WILDCARD-1, SCB_LIST_NULL0xff, devinfo->role, |
| 3780 | status); |
| 3781 | |
| 3782 | #ifdef AHC_TARGET_MODE |
| 3783 | /* |
| 3784 | * Send an immediate notify ccb to all target mord peripheral |
| 3785 | * drivers affected by this action. |
| 3786 | */ |
| 3787 | tstate = ahc->enabled_targets[devinfo->our_scsiid]; |
| 3788 | if (tstate != NULL((void *)0)) { |
| 3789 | for (lun = 0; lun < AHC_NUM_LUNS64; lun++) { |
| 3790 | struct ahc_tmode_lstate* lstate; |
| 3791 | |
| 3792 | lstate = tstate->enabled_luns[lun]; |
| 3793 | if (lstate == NULL((void *)0)) |
| 3794 | continue; |
| 3795 | |
| 3796 | ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, |
| 3797 | MSG_BUS_DEV_RESET0x0c, /*arg*/0); |
| 3798 | ahc_send_lstate_events(ahc, lstate); |
| 3799 | } |
| 3800 | } |
| 3801 | #endif |
| 3802 | |
| 3803 | /* |
| 3804 | * Go back to async/narrow transfers and renegotiate. |
| 3805 | */ |
| 3806 | ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT0x00, |
| 3807 | AHC_TRANS_CUR0x01, /*paused*/TRUE1); |
| 3808 | ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL((void *)0), |
| 3809 | /*period*/0, /*offset*/0, /*ppr_options*/0, |
| 3810 | AHC_TRANS_CUR0x01, /*paused*/TRUE1); |
| 3811 | |
| 3812 | if (status != CAM_SEL_TIMEOUT) |
| 3813 | ahc_send_async(ahc, devinfo->channel, devinfo->target, |
| 3814 | CAM_LUN_WILDCARD-1, AC_SENT_BDR, NULL((void *)0)); |
| 3815 | |
| 3816 | if (message != NULL((void *)0) |
| 3817 | && (verbose_level <= bootverbose0)) |
| 3818 | printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), |
| 3819 | message, devinfo->channel, devinfo->target, found); |
| 3820 | } |
| 3821 | |
| 3822 | #ifdef AHC_TARGET_MODE |
| 3823 | static void |
| 3824 | ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, |
| 3825 | struct scb *scb) |
| 3826 | { |
| 3827 | |
| 3828 | /* |
| 3829 | * To facilitate adding multiple messages together, |
| 3830 | * each routine should increment the index and len |
| 3831 | * variables instead of setting them explicitly. |
| 3832 | */ |
| 3833 | ahc->msgout_index = 0; |
| 3834 | ahc->msgout_len = 0; |
| 3835 | |
| 3836 | if (scb != NULL((void *)0) && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) |
| 3837 | ahc_build_transfer_msg(ahc, devinfo); |
| 3838 | else |
| 3839 | panic("ahc_intr: AWAITING target message with no message"); |
| 3840 | |
| 3841 | ahc->msgout_index = 0; |
| 3842 | ahc->msg_type = MSG_TYPE_TARGET_MSGIN; |
| 3843 | } |
| 3844 | #endif |
| 3845 | |
| 3846 | int |
| 3847 | ahc_softc_init(struct ahc_softc *ahc) |
| 3848 | { |
| 3849 | |
| 3850 | /* The IRQMS bit is only valid on VL and EISA chips */ |
| 3851 | if ((ahc->chip & AHC_PCI) == 0) |
| 3852 | ahc->unpause = ahc_inb(ahc, HCNTRL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x87))) & IRQMS0x08; |
| 3853 | else |
| 3854 | ahc->unpause = 0; |
| 3855 | ahc->pause = ahc->unpause | PAUSE0x04; |
| 3856 | /* XXX The shared scb data stuff should be deprecated */ |
| 3857 | if (ahc->scb_data == NULL((void *)0)) { |
| 3858 | ahc->scb_data = malloc(sizeof(*ahc->scb_data), M_DEVBUF2, |
| 3859 | M_NOWAIT0x0002 | M_ZERO0x0008); |
| 3860 | if (ahc->scb_data == NULL((void *)0)) |
| 3861 | return (ENOMEM12); |
| 3862 | } |
| 3863 | |
| 3864 | return (0); |
| 3865 | } |
| 3866 | |
| 3867 | void |
| 3868 | ahc_softc_insert(struct ahc_softc *ahc) |
| 3869 | { |
| 3870 | struct ahc_softc *list_ahc; |
| 3871 | |
| 3872 | #if AHC_PCI_CONFIG1 > 0 |
| 3873 | /* |
| 3874 | * Second Function PCI devices need to inherit some |
| 3875 | * settings from function 0. |
| 3876 | */ |
| 3877 | if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI |
| 3878 | && (ahc->features & AHC_MULTI_FUNC) != 0) { |
| 3879 | TAILQ_FOREACH(list_ahc, &ahc_tailq, links)for((list_ahc) = ((&ahc_tailq)->tqh_first); (list_ahc) != ((void *)0); (list_ahc) = ((list_ahc)->links.tqe_next) ) { |
| 3880 | ahc_dev_softc_t list_pci; |
| 3881 | ahc_dev_softc_t pci; |
| 3882 | |
| 3883 | list_pci = list_ahc->dev_softc; |
| 3884 | pci = ahc->dev_softc; |
| 3885 | if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) |
| 3886 | && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { |
| 3887 | struct ahc_softc *master; |
| 3888 | struct ahc_softc *slave; |
| 3889 | |
| 3890 | if (ahc_get_pci_function(list_pci) == 0) { |
| 3891 | master = list_ahc; |
| 3892 | slave = ahc; |
| 3893 | } else { |
| 3894 | master = ahc; |
| 3895 | slave = list_ahc; |
| 3896 | } |
| 3897 | slave->flags &= ~AHC_BIOS_ENABLED; |
| 3898 | slave->flags |= |
| 3899 | master->flags & AHC_BIOS_ENABLED; |
| 3900 | slave->flags &= ~AHC_PRIMARY_CHANNEL; |
| 3901 | slave->flags |= |
| 3902 | master->flags & AHC_PRIMARY_CHANNEL; |
| 3903 | break; |
| 3904 | } |
| 3905 | } |
| 3906 | } |
| 3907 | #endif |
| 3908 | |
| 3909 | /* |
| 3910 | * Insertion sort into our list of softcs. |
| 3911 | */ |
| 3912 | list_ahc = TAILQ_FIRST(&ahc_tailq)((&ahc_tailq)->tqh_first); |
| 3913 | while (list_ahc != NULL((void *)0) |
| 3914 | && ahc_softc_comp(ahc, list_ahc) <= 0) |
| 3915 | list_ahc = TAILQ_NEXT(list_ahc, links)((list_ahc)->links.tqe_next); |
| 3916 | if (list_ahc != NULL((void *)0)) |
| 3917 | TAILQ_INSERT_BEFORE(list_ahc, ahc, links)do { (ahc)->links.tqe_prev = (list_ahc)->links.tqe_prev ; (ahc)->links.tqe_next = (list_ahc); *(list_ahc)->links .tqe_prev = (ahc); (list_ahc)->links.tqe_prev = &(ahc) ->links.tqe_next; } while (0); |
| 3918 | else |
| 3919 | TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links)do { (ahc)->links.tqe_next = ((void *)0); (ahc)->links. tqe_prev = (&ahc_tailq)->tqh_last; *(&ahc_tailq)-> tqh_last = (ahc); (&ahc_tailq)->tqh_last = &(ahc)-> links.tqe_next; } while (0); |
| 3920 | ahc->init_level++; |
| 3921 | } |
| 3922 | |
| 3923 | void |
| 3924 | ahc_set_unit(struct ahc_softc *ahc, int unit) |
| 3925 | { |
| 3926 | ahc->unit = unit; |
| 3927 | } |
| 3928 | |
| 3929 | void |
| 3930 | ahc_set_name(struct ahc_softc *ahc, char *name) |
| 3931 | { |
| 3932 | ahc->name = name; |
| 3933 | } |
| 3934 | |
| 3935 | void |
| 3936 | ahc_free(struct ahc_softc *ahc) |
| 3937 | { |
| 3938 | int i; |
| 3939 | |
| 3940 | switch (ahc->init_level) { |
| 3941 | default: |
| 3942 | case 2: |
| 3943 | ahc_shutdown(ahc); |
| 3944 | /* FALLTHROUGH */ |
| 3945 | case 1: |
| 3946 | bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap)(*(ahc->parent_dmat)->_dmamap_unload)((ahc->parent_dmat ), (ahc->shared_data_dmamap)); |
| 3947 | bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap)(*(ahc->parent_dmat)->_dmamap_destroy)((ahc->parent_dmat ), (ahc->shared_data_dmamap)); |
| 3948 | bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size)(*(ahc->parent_dmat)->_dmamem_unmap)((ahc->parent_dmat ), ((caddr_t)ahc->qoutfifo), (ahc->shared_data_size)); |
| 3949 | bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg)(*(ahc->parent_dmat)->_dmamem_free)((ahc->parent_dmat ), (&ahc->shared_data_seg), (ahc->shared_data_nseg) ); |
| 3950 | break; |
| 3951 | case 0: |
| 3952 | break; |
| 3953 | } |
| 3954 | |
| 3955 | ahc_fini_scbdata(ahc); |
| 3956 | for (i = 0; i < AHC_NUM_TARGETS16; i++) { |
| 3957 | struct ahc_tmode_tstate *tstate; |
| 3958 | |
| 3959 | tstate = ahc->enabled_targets[i]; |
| 3960 | if (tstate != NULL((void *)0)) { |
| 3961 | #ifdef AHC_TARGET_MODE |
| 3962 | int j; |
| 3963 | |
| 3964 | for (j = 0; j < AHC_NUM_LUNS64; j++) { |
| 3965 | struct ahc_tmode_lstate *lstate; |
| 3966 | |
| 3967 | lstate = tstate->enabled_luns[j]; |
| 3968 | if (lstate != NULL((void *)0)) { |
| 3969 | /*xpt_free_path(lstate->path);*/ |
| 3970 | free(lstate, M_DEVBUF2, sizeof(*lstate)); |
| 3971 | } |
| 3972 | } |
| 3973 | #endif |
| 3974 | free(tstate, M_DEVBUF2, sizeof(*tstate)); |
| 3975 | } |
| 3976 | } |
| 3977 | #ifdef AHC_TARGET_MODE |
| 3978 | if (ahc->black_hole != NULL((void *)0)) { |
| 3979 | /*xpt_free_path(ahc->black_hole->path);*/ |
| 3980 | free(ahc->black_hole, M_DEVBUF2, sizeof(*ahc->black_hole)); |
| 3981 | } |
| 3982 | #endif |
| 3983 | if (ahc->seep_config != NULL((void *)0)) |
| 3984 | free(ahc->seep_config, M_DEVBUF2, sizeof(*ahc->seep_config)); |
| 3985 | return; |
| 3986 | } |
| 3987 | |
| 3988 | void |
| 3989 | ahc_shutdown(void *arg) |
| 3990 | { |
| 3991 | struct ahc_softc *ahc; |
| 3992 | int i; |
| 3993 | |
| 3994 | ahc = (struct ahc_softc *)arg; |
| 3995 | |
| 3996 | /* This will reset most registers to 0, but not all */ |
| 3997 | ahc_reset(ahc, /*reinit*/FALSE0); |
| 3998 | ahc_outb(ahc, SCSISEQ, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (0))); |
| 3999 | ahc_outb(ahc, SXFRCTL0, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), (0))); |
| 4000 | ahc_outb(ahc, DSPCISTATUS, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x86), (0))); |
| 4001 | |
| 4002 | for (i = TARG_SCSIRATE0x20; i < SCSICONF0x5a; i++) |
| 4003 | ahc_outb(ahc, i, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (i), (0))); |
| 4004 | } |
| 4005 | |
| 4006 | /* |
| 4007 | * Reset the controller and record some information about it |
| 4008 | * that is only available just after a reset. If "reinit" is |
| 4009 | * non-zero, this reset occurred after initial configuration |
| 4010 | * and the caller requests that the chip be fully reinitialized |
| 4011 | * to a runable state. Chip interrupts are *not* enabled after |
| 4012 | * a reinitialization. The caller must enable interrupts via |
| 4013 | * ahc_intr_enable(). |
| 4014 | */ |
| 4015 | int |
| 4016 | ahc_reset(struct ahc_softc *ahc, int reinit) |
| 4017 | { |
| 4018 | u_int sblkctl; |
| 4019 | u_int sxfrctl1_a, sxfrctl1_b; |
| 4020 | int error; |
| 4021 | int wait; |
| 4022 | |
| 4023 | /* |
| 4024 | * Preserve the value of the SXFRCTL1 register for all channels. |
| 4025 | * It contains settings that affect termination and we don't want |
| 4026 | * to disturb the integrity of the bus. |
| 4027 | */ |
| 4028 | ahc_pause(ahc); |
| 4029 | sxfrctl1_b = 0; |
| 4030 | if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { |
| 4031 | /* |
| 4032 | * Save channel B's settings in case this chip |
| 4033 | * is setup for TWIN channel operation. |
| 4034 | */ |
| 4035 | sblkctl = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))); |
| 4036 | ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl | 0x08))); |
| 4037 | sxfrctl1_b = ahc_inb(ahc, SXFRCTL1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x02))); |
| 4038 | ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl & ~0x08))); |
| 4039 | } |
| 4040 | sxfrctl1_a = ahc_inb(ahc, SXFRCTL1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x02))); |
| 4041 | |
| 4042 | ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause)(((ahc)->tag)->write_1(((ahc)->bsh), (0x87), (0x01 | ahc->pause))); |
| 4043 | |
| 4044 | /* |
| 4045 | * Ensure that the reset has finished. We delay 1000us |
| 4046 | * prior to reading the register to make sure the chip |
| 4047 | * has sufficiently completed its reset to handle register |
| 4048 | * accesses. |
| 4049 | */ |
| 4050 | wait = 1000; |
| 4051 | do { |
| 4052 | aic_delay(1000)(*delay_func)(1000); |
| 4053 | } while (--wait && !(ahc_inb(ahc, HCNTRL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x87))) & CHIPRSTACK0x01)); |
| 4054 | |
| 4055 | if (wait == 0) { |
| 4056 | printf("%s: WARNING - Failed chip reset! " |
| 4057 | "Trying to initialize anyway.\n", ahc_name(ahc)); |
| 4058 | } |
| 4059 | ahc_outb(ahc, HCNTRL, ahc->pause)(((ahc)->tag)->write_1(((ahc)->bsh), (0x87), (ahc-> pause))); |
| 4060 | |
| 4061 | /* Determine channel configuration */ |
| 4062 | sblkctl = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))) & (SELBUSB0x08|SELWIDE0x02); |
| 4063 | /* No Twin Channel PCI cards */ |
| 4064 | if ((ahc->chip & AHC_PCI) != 0) |
| 4065 | sblkctl &= ~SELBUSB0x08; |
| 4066 | switch (sblkctl) { |
| 4067 | case 0: |
| 4068 | /* Single Narrow Channel */ |
| 4069 | break; |
| 4070 | case SELWIDE0x02: |
| 4071 | /* Wide Channel */ |
| 4072 | ahc->features |= AHC_WIDE; |
| 4073 | break; |
| 4074 | case SELBUSB0x08: |
| 4075 | /* Twin Channel */ |
| 4076 | ahc->features |= AHC_TWIN; |
| 4077 | break; |
| 4078 | default: |
| 4079 | printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); |
| 4080 | return(-1); |
| 4081 | } |
| 4082 | |
| 4083 | /* |
| 4084 | * Reload sxfrctl1. |
| 4085 | * |
| 4086 | * We must always initialize STPWEN to 1 before we |
| 4087 | * restore the saved values. STPWEN is initialized |
| 4088 | * to a tri-state condition which can only be cleared |
| 4089 | * by turning it on. |
| 4090 | */ |
| 4091 | if ((ahc->features & AHC_TWIN) != 0) { |
| 4092 | sblkctl = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))); |
| 4093 | ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl | 0x08))); |
| 4094 | ahc_outb(ahc, SXFRCTL1, sxfrctl1_b)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), (sxfrctl1_b ))); |
| 4095 | ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl & ~0x08))); |
| 4096 | } |
| 4097 | ahc_outb(ahc, SXFRCTL1, sxfrctl1_a)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), (sxfrctl1_a ))); |
| 4098 | |
| 4099 | error = 0; |
| 4100 | if (reinit != 0) |
| 4101 | /* |
| 4102 | * If a recovery action has forced a chip reset, |
| 4103 | * re-initialize the chip to our liking. |
| 4104 | */ |
| 4105 | error = ahc->bus_chip_init(ahc); |
| 4106 | #ifdef AHC_DUMP_SEQ |
| 4107 | else |
| 4108 | ahc_dumpseq(ahc); |
| 4109 | #endif |
| 4110 | |
| 4111 | return (error); |
| 4112 | } |
| 4113 | |
| 4114 | /* |
| 4115 | * Determine the number of SCBs available on the controller |
| 4116 | */ |
| 4117 | int |
| 4118 | ahc_probe_scbs(struct ahc_softc *ahc) { |
| 4119 | int i; |
| 4120 | |
| 4121 | for (i = 0; i < AHC_SCB_MAX255; i++) { |
| 4122 | |
| 4123 | ahc_outb(ahc, SCBPTR, i)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (i))); |
| 4124 | ahc_outb(ahc, SCB_BASE, i)(((ahc)->tag)->write_1(((ahc)->bsh), (0xa0), (i))); |
| 4125 | if (ahc_inb(ahc, SCB_BASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa0))) != i) |
| 4126 | break; |
| 4127 | ahc_outb(ahc, SCBPTR, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (0))); |
| 4128 | if (ahc_inb(ahc, SCB_BASE)(((ahc)->tag)->read_1(((ahc)->bsh), (0xa0))) != 0) |
| 4129 | break; |
| 4130 | } |
| 4131 | return (i); |
| 4132 | } |
| 4133 | |
| 4134 | #if 0 |
| 4135 | static void |
| 4136 | ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) |
| 4137 | { |
| 4138 | bus_addr_t *baddr; |
| 4139 | |
| 4140 | baddr = (bus_addr_t *)arg; |
| 4141 | *baddr = segs->ds_addr; |
| 4142 | } |
| 4143 | #endif |
| 4144 | |
| 4145 | static void |
| 4146 | ahc_build_free_scb_list(struct ahc_softc *ahc) |
| 4147 | { |
| 4148 | int scbsize; |
| 4149 | int i; |
| 4150 | |
| 4151 | scbsize = 32; |
| 4152 | if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) |
| 4153 | scbsize = 64; |
| 4154 | |
| 4155 | for (i = 0; i < ahc->scb_data->maxhscbs; i++) { |
| 4156 | int j; |
| 4157 | |
| 4158 | ahc_outb(ahc, SCBPTR, i)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (i))); |
| 4159 | |
| 4160 | /* |
| 4161 | * Touch all SCB bytes to avoid parity errors |
| 4162 | * should one of our debugging routines read |
| 4163 | * an otherwise uninitialized byte. |
| 4164 | */ |
| 4165 | for (j = 0; j < scbsize; j++) |
| 4166 | ahc_outb(ahc, SCB_BASE+j, 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0xa0 +j), (0xFF ))); |
| 4167 | |
| 4168 | /* Clear the control byte. */ |
| 4169 | ahc_outb(ahc, SCB_CONTROL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), (0))); |
| 4170 | |
| 4171 | /* Set the next pointer */ |
| 4172 | if ((ahc->flags & AHC_PAGESCBS) != 0) |
| 4173 | ahc_outb(ahc, SCB_NEXT, i+1)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), (i+1))); |
| 4174 | else |
| 4175 | ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), (0xff)) ); |
| 4176 | |
| 4177 | /* Make the tag number, SCSIID, and lun invalid */ |
| 4178 | ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbb), (0xff)) ); |
| 4179 | ahc_outb(ahc, SCB_SCSIID, 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb9), (0xFF)) ); |
| 4180 | ahc_outb(ahc, SCB_LUN, 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0xba), (0xFF)) ); |
| 4181 | } |
| 4182 | |
| 4183 | if ((ahc->flags & AHC_PAGESCBS) != 0) { |
| 4184 | /* SCB 0 heads the free list. */ |
| 4185 | ahc_outb(ahc, FREE_SCBH, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x42), (0))); |
| 4186 | } else { |
| 4187 | /* No free list. */ |
| 4188 | ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0x42), (0xff)) ); |
| 4189 | } |
| 4190 | |
| 4191 | /* Make sure that the last SCB terminates the free list */ |
| 4192 | ahc_outb(ahc, SCBPTR, i-1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (i-1))); |
| 4193 | ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), (0xff)) ); |
| 4194 | } |
| 4195 | |
| 4196 | static int |
| 4197 | ahc_init_scbdata(struct ahc_softc *ahc) |
| 4198 | { |
| 4199 | struct scb_data *scb_data; |
| 4200 | int i; |
| 4201 | |
| 4202 | scb_data = ahc->scb_data; |
| 4203 | SLIST_INIT(&scb_data->free_scbs){ ((&scb_data->free_scbs)->slh_first) = ((void *)0) ; }; |
| 4204 | SLIST_INIT(&scb_data->sg_maps){ ((&scb_data->sg_maps)->slh_first) = ((void *)0); }; |
| 4205 | |
| 4206 | mtx_init(&ahc->sc_scb_mtx, IPL_BIO)do { (void)(((void *)0)); (void)(0); __mtx_init((&ahc-> sc_scb_mtx), ((((0x3)) > 0x0 && ((0x3)) < 0x9) ? 0x9 : ((0x3)))); } while (0); |
| 4207 | scsi_iopool_init(&ahc->sc_iopool, ahc, ahc_scb_alloc, ahc_scb_free); |
| 4208 | |
| 4209 | /* Allocate SCB resources */ |
| 4210 | scb_data->scbarray = mallocarray(AHC_SCB_MAX_ALLOC(253 +1), sizeof(struct scb), |
| 4211 | M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008); |
| 4212 | if (scb_data->scbarray == NULL((void *)0)) |
| 4213 | return (ENOMEM12); |
| 4214 | |
| 4215 | /* Determine the number of hardware SCBs and initialize them */ |
| 4216 | |
| 4217 | scb_data->maxhscbs = ahc_probe_scbs(ahc); |
| 4218 | if (ahc->scb_data->maxhscbs == 0) { |
| 4219 | printf("%s: No SCB space found\n", ahc_name(ahc)); |
| 4220 | return (ENXIO6); |
| 4221 | } |
| 4222 | |
| 4223 | /* |
| 4224 | * Create our DMA tags. These tags define the kinds of device |
| 4225 | * accessible memory allocations and memory mappings we will |
| 4226 | * need to perform during normal operation. |
| 4227 | * |
| 4228 | * Unless we need to further restrict the allocation, we rely |
| 4229 | * on the restrictions of the parent dmat, hence the common |
| 4230 | * use of MAXADDR and MAXSIZE. |
| 4231 | */ |
| 4232 | |
| 4233 | if (ahc_createdmamem(ahc->parent_dmat, |
| 4234 | AHC_SCB_MAX255 * sizeof(struct hardware_scb), ahc->sc_dmaflags, |
| 4235 | &scb_data->hscb_dmamap, |
| 4236 | (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, |
| 4237 | &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), |
| 4238 | "hardware SCB structures") < 0) |
| 4239 | goto error_exit; |
| 4240 | |
| 4241 | scb_data->init_level++; |
| 4242 | |
| 4243 | if (ahc_createdmamem(ahc->parent_dmat, |
| 4244 | AHC_SCB_MAX255 * sizeof(struct scsi_sense_data), ahc->sc_dmaflags, |
| 4245 | &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, |
| 4246 | &scb_data->sense_busaddr, &scb_data->sense_seg, |
| 4247 | &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) |
| 4248 | goto error_exit; |
| 4249 | |
| 4250 | scb_data->init_level++; |
| 4251 | |
| 4252 | /* Perform initial CCB allocation */ |
| 4253 | memset(scb_data->hscbs, 0,__builtin_memset((scb_data->hscbs), (0), ((253 +1) * sizeof (struct hardware_scb))) |
| 4254 | AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb))__builtin_memset((scb_data->hscbs), (0), ((253 +1) * sizeof (struct hardware_scb))); |
| 4255 | do { |
| 4256 | i = scb_data->numscbs; |
| 4257 | ahc_alloc_scbs(ahc); |
| 4258 | } while ((i != scb_data->numscbs) && |
| 4259 | (scb_data->numscbs < AHC_SCB_MAX_ALLOC(253 +1))); |
| 4260 | |
| 4261 | if (scb_data->numscbs != AHC_SCB_MAX_ALLOC(253 +1)) { |
| 4262 | printf("%s: ahc_init_scbdata - " |
| 4263 | "Unable to allocate initial scbs\n", |
| 4264 | ahc_name(ahc)); |
| 4265 | goto error_exit; |
| 4266 | } |
| 4267 | |
| 4268 | /* |
| 4269 | * Reserve the next queued SCB. |
| 4270 | */ |
| 4271 | ahc->next_queued_scb = scsi_io_get(&ahc->sc_iopool, |
| 4272 | SCSI_POLL0x00002 | SCSI_NOSLEEP0x00001); |
| 4273 | if (ahc->next_queued_scb != NULL((void *)0)) |
| 4274 | /* Note that we were successful */ |
| 4275 | return (0); |
| 4276 | |
| 4277 | error_exit: |
| 4278 | |
| 4279 | return (ENOMEM12); |
| 4280 | } |
| 4281 | |
| 4282 | static void |
| 4283 | ahc_fini_scbdata(struct ahc_softc *ahc) |
| 4284 | { |
| 4285 | struct scb_data *scb_data; |
| 4286 | |
| 4287 | scb_data = ahc->scb_data; |
| 4288 | if (scb_data == NULL((void *)0)) |
| 4289 | return; |
| 4290 | |
| 4291 | switch (scb_data->init_level) { |
| 4292 | default: |
| 4293 | case 5: |
| 4294 | { |
| 4295 | struct sg_map_node *sg_map; |
| 4296 | |
| 4297 | while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)((&scb_data->sg_maps)->slh_first))!= NULL((void *)0)) { |
| 4298 | SLIST_REMOVE_HEAD(&scb_data->sg_maps, links)do { (&scb_data->sg_maps)->slh_first = (&scb_data ->sg_maps)->slh_first->links.sle_next; } while (0); |
| 4299 | ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE(1 << 12), |
| 4300 | sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, |
| 4301 | &sg_map->sg_dmasegs, sg_map->sg_nseg); |
| 4302 | free(sg_map, M_DEVBUF2, sizeof(*sg_map)); |
| 4303 | } |
| 4304 | } |
| 4305 | /*FALLTHROUGH*/ |
| 4306 | case 4: |
| 4307 | ahc_freedmamem(ahc->parent_dmat, |
| 4308 | AHC_SCB_MAX255 * sizeof(struct scsi_sense_data), |
| 4309 | scb_data->sense_dmamap, (caddr_t)scb_data->sense, |
| 4310 | &scb_data->sense_seg, scb_data->sense_nseg); |
| 4311 | /*FALLTHROUGH*/ |
| 4312 | case 3: |
| 4313 | ahc_freedmamem(ahc->parent_dmat, |
| 4314 | AHC_SCB_MAX255 * sizeof(struct hardware_scb), |
| 4315 | scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, |
| 4316 | &scb_data->hscb_seg, scb_data->hscb_nseg); |
| 4317 | /*FALLTHROUGH*/ |
| 4318 | case 2: |
| 4319 | case 1: |
| 4320 | case 0: |
| 4321 | break; |
| 4322 | } |
| 4323 | if (scb_data->scbarray != NULL((void *)0)) { |
| 4324 | free(scb_data->scbarray, M_DEVBUF2, |
| 4325 | AHC_SCB_MAX_ALLOC(253 +1) * sizeof(struct scb)); |
| 4326 | } |
| 4327 | } |
| 4328 | |
| 4329 | void |
| 4330 | ahc_alloc_scbs(struct ahc_softc *ahc) |
| 4331 | { |
| 4332 | struct scb_data *scb_data; |
| 4333 | struct scb *next_scb; |
| 4334 | struct sg_map_node *sg_map; |
| 4335 | bus_addr_t physaddr; |
| 4336 | struct ahc_dma_seg *segs; |
| 4337 | int newcount; |
| 4338 | int i; |
| 4339 | |
| 4340 | scb_data = ahc->scb_data; |
| 4341 | if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC(253 +1)) |
| 4342 | /* Can't allocate any more */ |
| 4343 | return; |
| 4344 | |
| 4345 | next_scb = &scb_data->scbarray[scb_data->numscbs]; |
| 4346 | |
| 4347 | sg_map = malloc(sizeof(*sg_map), M_DEVBUF2, M_NOWAIT0x0002); |
| 4348 | |
| 4349 | if (sg_map == NULL((void *)0)) |
| 4350 | return; |
| 4351 | |
| 4352 | /* Allocate S/G space for the next batch of SCBS */ |
| 4353 | if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE(1 << 12), ahc->sc_dmaflags, |
| 4354 | &sg_map->sg_dmamap, |
| 4355 | (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, |
| 4356 | &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), |
| 4357 | "SG space") < 0) { |
| 4358 | free(sg_map, M_DEVBUF2, sizeof(*sg_map)); |
| 4359 | return; |
| 4360 | } |
| 4361 | |
| 4362 | SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links)do { (sg_map)->links.sle_next = (&scb_data->sg_maps )->slh_first; (&scb_data->sg_maps)->slh_first = ( sg_map); } while (0); |
| 4363 | |
| 4364 | segs = sg_map->sg_vaddr; |
| 4365 | physaddr = sg_map->sg_physaddr; |
| 4366 | |
| 4367 | newcount = (PAGE_SIZE(1 << 12) / (AHC_NSEG((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*(16))) * sizeof(struct ahc_dma_seg))); |
| 4368 | newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs))(((newcount)<(((253 +1) - scb_data->numscbs)))?(newcount ):(((253 +1) - scb_data->numscbs))); |
| 4369 | for (i = 0; i < newcount; i++) { |
| 4370 | int error; |
| 4371 | |
| 4372 | next_scb->sg_map = sg_map; |
| 4373 | next_scb->sg_list = segs; |
| 4374 | /* |
| 4375 | * The sequencer always starts with the second entry. |
| 4376 | * The first entry is embedded in the scb. |
| 4377 | */ |
| 4378 | next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); |
| 4379 | next_scb->ahc_softc = ahc; |
| 4380 | next_scb->flags = SCB_FLAG_NONE; |
| 4381 | |
| 4382 | error = bus_dmamap_create(ahc->parent_dmat,(*(ahc->parent_dmat)->_dmamap_create)((ahc->parent_dmat ), (((((64 * 1024))<(0x00ffffff))?((64 * 1024)):(0x00ffffff ))), (((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*( 16)))), ((64 * 1024)), (0), (0x0001|0x0002|ahc->sc_dmaflags ), (&next_scb->dmamap)) |
| 4383 | AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0,(*(ahc->parent_dmat)->_dmamap_create)((ahc->parent_dmat ), (((((64 * 1024))<(0x00ffffff))?((64 * 1024)):(0x00ffffff ))), (((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*( 16)))), ((64 * 1024)), (0), (0x0001|0x0002|ahc->sc_dmaflags ), (&next_scb->dmamap)) |
| 4384 | BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags,(*(ahc->parent_dmat)->_dmamap_create)((ahc->parent_dmat ), (((((64 * 1024))<(0x00ffffff))?((64 * 1024)):(0x00ffffff ))), (((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*( 16)))), ((64 * 1024)), (0), (0x0001|0x0002|ahc->sc_dmaflags ), (&next_scb->dmamap)) |
| 4385 | &next_scb->dmamap)(*(ahc->parent_dmat)->_dmamap_create)((ahc->parent_dmat ), (((((64 * 1024))<(0x00ffffff))?((64 * 1024)):(0x00ffffff ))), (((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*( 16)))), ((64 * 1024)), (0), (0x0001|0x0002|ahc->sc_dmaflags ), (&next_scb->dmamap)); |
| 4386 | if (error != 0) |
| 4387 | break; |
| 4388 | |
| 4389 | next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; |
| 4390 | next_scb->hscb->tag = ahc->scb_data->numscbs; |
| 4391 | mtx_enter(&ahc->sc_scb_mtx); |
| 4392 | SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,do { (next_scb)->links.sle.sle_next = (&ahc->scb_data ->free_scbs)->slh_first; (&ahc->scb_data->free_scbs )->slh_first = (next_scb); } while (0) |
| 4393 | next_scb, links.sle)do { (next_scb)->links.sle.sle_next = (&ahc->scb_data ->free_scbs)->slh_first; (&ahc->scb_data->free_scbs )->slh_first = (next_scb); } while (0); |
| 4394 | mtx_leave(&ahc->sc_scb_mtx); |
| 4395 | segs += AHC_NSEG((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*(16))); |
| 4396 | physaddr += (AHC_NSEG((((((((64 * 1024)) >> 12) + 1)+((16)-1))/(16))*(16))) * sizeof(struct ahc_dma_seg)); |
| 4397 | next_scb++; |
| 4398 | ahc->scb_data->numscbs++; |
| 4399 | } |
| 4400 | } |
| 4401 | |
| 4402 | #ifndef DEBUG |
| 4403 | void |
| 4404 | ahc_controller_info(struct ahc_softc *ahc, char *buf, size_t buf_len) |
| 4405 | { |
| 4406 | int len = 0; |
| 4407 | |
| 4408 | snprintf(buf + len, buf_len - len, "%s: ", |
| 4409 | ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); |
| 4410 | len = strlen(buf); |
| 4411 | if ((ahc->features & AHC_TWIN) != 0) |
| 4412 | snprintf(buf + len, buf_len - len, |
| 4413 | "Twin Channel, primary %c, ", |
| 4414 | (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); |
| 4415 | else { |
| 4416 | const char *speed; |
| 4417 | const char *type; |
| 4418 | |
| 4419 | speed = ""; |
| 4420 | if ((ahc->features & AHC_ULTRA) != 0) { |
| 4421 | speed = "Ultra "; |
| 4422 | } else if ((ahc->features & AHC_DT) != 0) { |
| 4423 | speed = "Ultra160 "; |
| 4424 | } else if ((ahc->features & AHC_ULTRA2) != 0) { |
| 4425 | speed = "Ultra2 "; |
| 4426 | } |
| 4427 | if ((ahc->features & AHC_WIDE) != 0) { |
| 4428 | type = "Wide"; |
| 4429 | } else { |
| 4430 | type = "Single"; |
| 4431 | } |
| 4432 | snprintf(buf + len, buf_len - len, |
| 4433 | "%s%s Channel %c, ", |
| 4434 | speed, type, ahc->channel); |
| 4435 | } |
| 4436 | len = strlen(buf); |
| 4437 | |
| 4438 | if ((ahc->flags & AHC_PAGESCBS) != 0) |
| 4439 | snprintf(buf + len, buf_len - len, "%d/%d SCBs", |
| 4440 | ahc->scb_data->maxhscbs, AHC_MAX_QUEUE253); |
| 4441 | else |
| 4442 | snprintf(buf + len, buf_len - len, "%d SCBs", |
| 4443 | ahc->scb_data->maxhscbs); |
| 4444 | } |
| 4445 | #endif /* !DEBUG */ |
| 4446 | |
| 4447 | int |
| 4448 | ahc_chip_init(struct ahc_softc *ahc) |
| 4449 | { |
| 4450 | int term; |
| 4451 | int error; |
| 4452 | u_int i; |
| 4453 | u_int scsi_conf; |
| 4454 | u_int scsiseq_template; |
| 4455 | uint32_t physaddr; |
| 4456 | |
| 4457 | ahc_outb(ahc, SEQ_FLAGS, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3c), (0))); |
| 4458 | ahc_outb(ahc, SEQ_FLAGS2, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), (0))); |
| 4459 | |
| 4460 | /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ |
| 4461 | if (ahc->features & AHC_TWIN) { |
| 4462 | |
| 4463 | /* |
| 4464 | * Setup Channel B first. |
| 4465 | */ |
| 4466 | ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x1f))) | 0x08))); |
| 4467 | term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN0x01 : 0; |
| 4468 | ahc_outb(ahc, SCSIID, ahc->our_id_b)(((ahc)->tag)->write_1(((ahc)->bsh), (0x05), (ahc-> our_id_b))); |
| 4469 | scsi_conf = ahc_inb(ahc, SCSICONF + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x5a + 1))); |
| 4470 | ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((scsi_conf & (0x20|0x18)) |term|ahc->seltime_b|0x04|0x02))) |
| 4471 | |term|ahc->seltime_b|ENSTIMER|ACTNEGEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((scsi_conf & (0x20|0x18)) |term|ahc->seltime_b|0x04|0x02))); |
| 4472 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 4473 | ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x10), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x10)))|0x08))); |
| 4474 | ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (0x80|0x20 |0x04))); |
| 4475 | ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), (0x80|0x08 ))); |
| 4476 | |
| 4477 | /* Select Channel A */ |
| 4478 | ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x1f))) & ~0x08)) ); |
| 4479 | } |
| 4480 | term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN0x01 : 0; |
| 4481 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 4482 | ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id)(((ahc)->tag)->write_1(((ahc)->bsh), (0x0f), (ahc-> our_id))); |
| 4483 | else |
| 4484 | ahc_outb(ahc, SCSIID, ahc->our_id)(((ahc)->tag)->write_1(((ahc)->bsh), (0x05), (ahc-> our_id))); |
| 4485 | scsi_conf = ahc_inb(ahc, SCSICONF)(((ahc)->tag)->read_1(((ahc)->bsh), (0x5a))); |
| 4486 | ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((scsi_conf & (0x20|0x18)) |term|ahc->seltime |0x04|0x02))) |
| 4487 | |term|ahc->seltime(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((scsi_conf & (0x20|0x18)) |term|ahc->seltime |0x04|0x02))) |
| 4488 | |ENSTIMER|ACTNEGEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x02), ((scsi_conf & (0x20|0x18)) |term|ahc->seltime |0x04|0x02))); |
| 4489 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 4490 | ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x10), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x10)))|0x08))); |
| 4491 | ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (0x80|0x20 |0x04))); |
| 4492 | ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x01), (0x80|0x08 ))); |
| 4493 | |
| 4494 | /* There are no untagged SCBs active yet. */ |
| 4495 | for (i = 0; i < 16; i++) { |
| 4496 | ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)((0) | (((i << 4) & 0xf0) << 4))); |
| 4497 | if ((ahc->flags & AHC_SCB_BTT) != 0) { |
| 4498 | int lun; |
| 4499 | |
| 4500 | /* |
| 4501 | * The SCB based BTT allows an entry per |
| 4502 | * target and lun pair. |
| 4503 | */ |
| 4504 | for (lun = 1; lun < AHC_NUM_LUNS64; lun++) |
| 4505 | ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)((lun) | (((i << 4) & 0xf0) << 4))); |
| 4506 | } |
| 4507 | } |
| 4508 | |
| 4509 | /* All of our queues are empty */ |
| 4510 | for (i = 0; i < 256; i++) |
| 4511 | ahc->qoutfifo[i] = SCB_LIST_NULL0xff; |
| 4512 | ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD0x01); |
| 4513 | for (i = 0; i < 256; i++) |
| 4514 | ahc->qinfifo[i] = SCB_LIST_NULL0xff; |
| 4515 | |
| 4516 | if ((ahc->features & AHC_MULTI_TID) != 0) { |
| 4517 | ahc_outb(ahc, TARGID, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1b), (0))); |
| 4518 | ahc_outb(ahc, TARGID + 1, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1b + 1), (0) )); |
| 4519 | } |
| 4520 | |
| 4521 | /* |
| 4522 | * Tell the sequencer where it can find our arrays in memory. |
| 4523 | */ |
| 4524 | physaddr = ahc->scb_data->hscb_busaddr; |
| 4525 | ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x44), (physaddr & 0xFF))); |
| 4526 | ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x44 + 1), ((physaddr >> 8) & 0xFF))); |
| 4527 | ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x44 + 2), ((physaddr >> 16) & 0xFF))); |
| 4528 | ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x44 + 3), ((physaddr >> 24) & 0xFF))); |
| 4529 | |
| 4530 | physaddr = ahc->shared_data_busaddr; |
| 4531 | ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x48), (physaddr & 0xFF))); |
| 4532 | ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x48 + 1), ((physaddr >> 8) & 0xFF))); |
| 4533 | ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x48 + 2), ((physaddr >> 16) & 0xFF))); |
| 4534 | ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF)(((ahc)->tag)->write_1(((ahc)->bsh), (0x48 + 3), ((physaddr >> 24) & 0xFF))); |
| 4535 | |
| 4536 | /* |
| 4537 | * Initialize the group code to command length table. |
| 4538 | * This overrides the values in TARG_SCSIRATE, so only |
| 4539 | * setup the table after we have processed that information. |
| 4540 | */ |
| 4541 | ahc_outb(ahc, CMDSIZE_TABLE, 5)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30), (5))); |
| 4542 | ahc_outb(ahc, CMDSIZE_TABLE + 1, 9)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 1), (9) )); |
| 4543 | ahc_outb(ahc, CMDSIZE_TABLE + 2, 9)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 2), (9) )); |
| 4544 | ahc_outb(ahc, CMDSIZE_TABLE + 3, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 3), (0) )); |
| 4545 | ahc_outb(ahc, CMDSIZE_TABLE + 4, 15)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 4), (15 ))); |
| 4546 | ahc_outb(ahc, CMDSIZE_TABLE + 5, 11)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 5), (11 ))); |
| 4547 | ahc_outb(ahc, CMDSIZE_TABLE + 6, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 6), (0) )); |
| 4548 | ahc_outb(ahc, CMDSIZE_TABLE + 7, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x30 + 7), (0) )); |
| 4549 | |
| 4550 | if ((ahc->features & AHC_HS_MAILBOX) != 0) |
| 4551 | ahc_outb(ahc, HS_MAILBOX, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x86), (0))); |
| 4552 | |
| 4553 | /* Tell the sequencer of our initial queue positions */ |
| 4554 | if ((ahc->features & AHC_TARGETMODE) != 0) { |
| 4555 | ahc->tqinfifonext = 1; |
| 4556 | ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4f), (ahc-> tqinfifonext - 1))); |
| 4557 | ahc_outb(ahc, TQINPOS, ahc->tqinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x50), (ahc-> tqinfifonext))); |
| 4558 | } |
| 4559 | ahc->qinfifonext = 0; |
| 4560 | ahc->qoutfifonext = 0; |
| 4561 | if ((ahc->features & AHC_QUEUE_REGS) != 0) { |
| 4562 | ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256)(((ahc)->tag)->write_1(((ahc)->bsh), (0xfa), (0x06)) ); |
| 4563 | ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf4), (ahc-> qinfifonext))); |
| 4564 | ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf6), (ahc-> qinfifonext))); |
| 4565 | ahc_outb(ahc, SDSCB_QOFF, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf8), (0))); |
| 4566 | } else { |
| 4567 | ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4c), (ahc-> qinfifonext))); |
| 4568 | ahc_outb(ahc, QINPOS, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4d), (ahc-> qinfifonext))); |
| 4569 | ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4e), (ahc-> qoutfifonext))); |
| 4570 | } |
| 4571 | |
| 4572 | /* We don't have any waiting selections */ |
| 4573 | ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0x40), (0xff)) ); |
| 4574 | |
| 4575 | /* Our disconnection list is empty too */ |
| 4576 | ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0x41), (0xff)) ); |
| 4577 | |
| 4578 | /* Message out buffer starts empty */ |
| 4579 | ahc_outb(ahc, MSG_OUT, MSG_NOOP)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3a), (0x08)) ); |
| 4580 | |
| 4581 | /* |
| 4582 | * Setup the allowed SCSI Sequences based on operational mode. |
| 4583 | * If we are a target, we'll enable select in operations once |
| 4584 | * we've had a lun enabled. |
| 4585 | */ |
| 4586 | scsiseq_template = ENSELO0x40|ENAUTOATNO0x08|ENAUTOATNP0x02; |
| 4587 | if ((ahc->flags & AHC_INITIATORROLE) != 0) |
| 4588 | scsiseq_template |= ENRSELI0x10; |
| 4589 | ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template)(((ahc)->tag)->write_1(((ahc)->bsh), (0x54), (scsiseq_template ))); |
| 4590 | |
| 4591 | /* Initialize our list of free SCBs. */ |
| 4592 | ahc_build_free_scb_list(ahc); |
| 4593 | |
| 4594 | /* |
| 4595 | * Tell the sequencer which SCB will be the next one it receives. |
| 4596 | */ |
| 4597 | ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag)(((ahc)->tag)->write_1(((ahc)->bsh), (0x39), (ahc-> next_queued_scb->hscb->tag))); |
| 4598 | |
| 4599 | /* |
| 4600 | * Load the Sequencer program and Enable the adapter |
| 4601 | * in "fast" mode. |
| 4602 | */ |
| 4603 | if (bootverbose0) |
| 4604 | printf("%s: Downloading Sequencer Program...", |
| 4605 | ahc_name(ahc)); |
| 4606 | |
| 4607 | error = ahc_loadseq(ahc); |
| 4608 | if (error != 0) |
| 4609 | return (error); |
| 4610 | |
| 4611 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 4612 | int wait; |
| 4613 | |
| 4614 | /* |
| 4615 | * Wait for up to 500ms for our transceivers |
| 4616 | * to settle. If the adapter does not have |
| 4617 | * a cable attached, the transceivers may |
| 4618 | * never settle, so don't complain if we |
| 4619 | * fail here. |
| 4620 | */ |
| 4621 | for (wait = 5000; |
| 4622 | (ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))) & (ENAB400x08|ENAB200x04)) == 0 && wait; |
| 4623 | wait--) |
| 4624 | aic_delay(100)(*delay_func)(100); |
| 4625 | } |
| 4626 | ahc_restart(ahc); |
| 4627 | return (0); |
| 4628 | } |
| 4629 | |
| 4630 | /* |
| 4631 | * Start the board, ready for normal operation |
| 4632 | */ |
| 4633 | int |
| 4634 | ahc_init(struct ahc_softc *ahc) |
| 4635 | { |
| 4636 | int max_targ; |
| 4637 | u_int i; |
| 4638 | u_int scsi_conf; |
| 4639 | u_int ultraenb; |
| 4640 | u_int discenable; |
| 4641 | u_int tagenable; |
| 4642 | size_t driver_data_size; |
| 4643 | |
| 4644 | #ifdef AHC_DEBUG |
| 4645 | if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) |
| 4646 | ahc->flags |= AHC_SEQUENCER_DEBUG; |
| 4647 | #endif |
| 4648 | |
| 4649 | #ifdef AHC_PRINT_SRAM |
| 4650 | printf("Scratch Ram:"); |
| 4651 | for (i = 0x20; i < 0x5f; i++) { |
| 4652 | if (((i % 8) == 0) && (i != 0)) { |
| 4653 | printf ("\n "); |
| 4654 | } |
| 4655 | printf (" 0x%x", ahc_inb(ahc, i)(((ahc)->tag)->read_1(((ahc)->bsh), (i)))); |
| 4656 | } |
| 4657 | if ((ahc->features & AHC_MORE_SRAM) != 0) { |
| 4658 | for (i = 0x70; i < 0x7f; i++) { |
| 4659 | if (((i % 8) == 0) && (i != 0)) { |
| 4660 | printf ("\n "); |
| 4661 | } |
| 4662 | printf (" 0x%x", ahc_inb(ahc, i)(((ahc)->tag)->read_1(((ahc)->bsh), (i)))); |
| 4663 | } |
| 4664 | } |
| 4665 | printf ("\n"); |
| 4666 | /* |
| 4667 | * Reading uninitialized scratch ram may |
| 4668 | * generate parity errors. |
| 4669 | */ |
| 4670 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
| 4671 | ahc_outb(ahc, CLRINT, CLRBRKADRINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x08)) ); |
| 4672 | #endif |
| 4673 | max_targ = 15; |
| 4674 | |
| 4675 | /* |
| 4676 | * Assume we have a board at this stage and it has been reset. |
| 4677 | */ |
| 4678 | if ((ahc->flags & AHC_USEDEFAULTS) != 0) |
| 4679 | ahc->our_id = ahc->our_id_b = 7; |
| 4680 | |
| 4681 | /* |
| 4682 | * Default to allowing initiator operations. |
| 4683 | */ |
| 4684 | ahc->flags |= AHC_INITIATORROLE; |
| 4685 | |
| 4686 | /* |
| 4687 | * Only allow target mode features if this unit has them enabled. |
| 4688 | */ |
| 4689 | //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) |
| 4690 | ahc->features &= ~AHC_TARGETMODE; |
| 4691 | |
| 4692 | /* |
| 4693 | * DMA tag for our command fifos and other data in system memory |
| 4694 | * the card's sequencer must be able to access. For initiator |
| 4695 | * roles, we need to allocate space for the qinfifo and qoutfifo. |
| 4696 | * The qinfifo and qoutfifo are composed of 256 1 byte elements. |
| 4697 | * When providing for the target mode role, we must additionally |
| 4698 | * provide space for the incoming target command fifo and an extra |
| 4699 | * byte to deal with a DMA bug in some chip versions. |
| 4700 | */ |
| 4701 | driver_data_size = 2 * 256 * sizeof(uint8_t); |
| 4702 | if ((ahc->features & AHC_TARGETMODE) != 0) |
| 4703 | driver_data_size += AHC_TMODE_CMDS256 * sizeof(struct target_cmd) |
| 4704 | + /*DMA WideOdd Bug Buffer*/1; |
| 4705 | |
| 4706 | ahc->init_level++; |
| 4707 | |
| 4708 | if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, |
| 4709 | ahc->sc_dmaflags, |
| 4710 | &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, |
| 4711 | &ahc->shared_data_busaddr, &ahc->shared_data_seg, |
| 4712 | &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) |
| 4713 | return (ENOMEM12); |
| 4714 | |
| 4715 | ahc->init_level++; |
| 4716 | |
| 4717 | if ((ahc->features & AHC_TARGETMODE) != 0) { |
| 4718 | ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; |
| 4719 | ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS256]; |
| 4720 | ahc->dma_bug_buf = ahc->shared_data_busaddr |
| 4721 | + driver_data_size - 1; |
| 4722 | /* All target command blocks start out invalid. */ |
| 4723 | for (i = 0; i < AHC_TMODE_CMDS256; i++) |
| 4724 | ahc->targetcmds[i].cmd_valid = 0; |
| 4725 | ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD0x01); |
| 4726 | ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; |
| 4727 | } |
| 4728 | ahc->qinfifo = &ahc->qoutfifo[256]; |
| 4729 | |
| 4730 | ahc->init_level++; |
| 4731 | |
| 4732 | /* Allocate SCB data now that buffer_dmat is initialized */ |
| 4733 | if (ahc->scb_data->maxhscbs == 0) |
| 4734 | if (ahc_init_scbdata(ahc) != 0) |
| 4735 | return (ENOMEM12); |
| 4736 | |
| 4737 | /* |
| 4738 | * Allocate a tstate to house information for our |
| 4739 | * initiator presence on the bus as well as the user |
| 4740 | * data for any target mode initiator. |
| 4741 | */ |
| 4742 | if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL((void *)0)) { |
| 4743 | printf("%s: unable to allocate ahc_tmode_tstate. " |
| 4744 | "Failing attach\n", ahc_name(ahc)); |
| 4745 | return (ENOMEM12); |
| 4746 | } |
| 4747 | |
| 4748 | if ((ahc->features & AHC_TWIN) != 0) { |
| 4749 | if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL((void *)0)) { |
| 4750 | printf("%s: unable to allocate ahc_tmode_tstate. " |
| 4751 | "Failing attach\n", ahc_name(ahc)); |
| 4752 | return (ENOMEM12); |
| 4753 | } |
| 4754 | } |
| 4755 | |
| 4756 | ahc_outb(ahc, SEQ_FLAGS, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x3c), (0))); |
| 4757 | ahc_outb(ahc, SEQ_FLAGS2, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x57), (0))); |
| 4758 | |
| 4759 | if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC(253 +1)) { |
| 4760 | ahc->flags |= AHC_PAGESCBS; |
| 4761 | } else { |
| 4762 | ahc->flags &= ~AHC_PAGESCBS; |
| 4763 | } |
| 4764 | |
| 4765 | #ifdef AHC_DEBUG |
| 4766 | if (ahc_debug & AHC_SHOW_MISC) { |
| 4767 | printf("%s: hardware scb %u bytes; kernel scb %u bytes; " |
| 4768 | "ahc_dma %u bytes\n", |
| 4769 | ahc_name(ahc), |
| 4770 | (u_int)sizeof(struct hardware_scb), |
| 4771 | (u_int)sizeof(struct scb), |
| 4772 | (u_int)sizeof(struct ahc_dma_seg)); |
| 4773 | } |
| 4774 | #endif /* AHC_DEBUG */ |
| 4775 | |
| 4776 | /* |
| 4777 | * Look at the information that board initialization or |
| 4778 | * the board bios has left us. |
| 4779 | */ |
| 4780 | if (ahc->features & AHC_TWIN) { |
| 4781 | scsi_conf = ahc_inb(ahc, SCSICONF + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x5a + 1))); |
| 4782 | if ((scsi_conf & RESET_SCSI0x40) != 0 |
| 4783 | && (ahc->flags & AHC_INITIATORROLE) != 0) |
| 4784 | ahc->flags |= AHC_RESET_BUS_B; |
| 4785 | } |
| 4786 | |
| 4787 | scsi_conf = ahc_inb(ahc, SCSICONF)(((ahc)->tag)->read_1(((ahc)->bsh), (0x5a))); |
| 4788 | if ((scsi_conf & RESET_SCSI0x40) != 0 |
| 4789 | && (ahc->flags & AHC_INITIATORROLE) != 0) |
| 4790 | ahc->flags |= AHC_RESET_BUS_A; |
| 4791 | |
| 4792 | ultraenb = 0; |
| 4793 | tagenable = ALL_TARGETS_MASK0xFFFF; |
| 4794 | |
| 4795 | /* Grab the disconnection disable table and invert it for our needs */ |
| 4796 | if ((ahc->flags & AHC_USEDEFAULTS) != 0) { |
| 4797 | printf("%s: Host Adapter Bios disabled. Using default SCSI " |
| 4798 | "device parameters\n", ahc_name(ahc)); |
| 4799 | ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| |
| 4800 | AHC_TERM_ENB_A|AHC_TERM_ENB_B; |
| 4801 | discenable = ALL_TARGETS_MASK0xFFFF; |
| 4802 | if ((ahc->features & AHC_ULTRA) != 0) |
| 4803 | ultraenb = ALL_TARGETS_MASK0xFFFF; |
| 4804 | } else { |
| 4805 | discenable = ~((ahc_inb(ahc, DISC_DSB + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x32 + 1))) << 8) |
| 4806 | | ahc_inb(ahc, DISC_DSB)(((ahc)->tag)->read_1(((ahc)->bsh), (0x32)))); |
| 4807 | if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) |
| 4808 | ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x30 + 1))) << 8) |
| 4809 | | ahc_inb(ahc, ULTRA_ENB)(((ahc)->tag)->read_1(((ahc)->bsh), (0x30))); |
| 4810 | } |
| 4811 | |
| 4812 | if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) |
| 4813 | max_targ = 7; |
| 4814 | |
| 4815 | for (i = 0; i <= max_targ; i++) { |
| 4816 | struct ahc_initiator_tinfo *tinfo; |
| 4817 | struct ahc_tmode_tstate *tstate; |
| 4818 | u_int our_id; |
| 4819 | u_int target_id; |
| 4820 | char channel; |
| 4821 | |
| 4822 | channel = 'A'; |
| 4823 | our_id = ahc->our_id; |
| 4824 | target_id = i; |
| 4825 | if (i > 7 && (ahc->features & AHC_TWIN) != 0) { |
| 4826 | channel = 'B'; |
| 4827 | our_id = ahc->our_id_b; |
| 4828 | target_id = i % 8; |
| 4829 | } |
| 4830 | tinfo = ahc_fetch_transinfo(ahc, channel, our_id, |
| 4831 | target_id, &tstate); |
| 4832 | /* Default to async narrow across the board */ |
| 4833 | memset(tinfo, 0, sizeof(*tinfo))__builtin_memset((tinfo), (0), (sizeof(*tinfo))); |
| 4834 | if (ahc->flags & AHC_USEDEFAULTS) { |
| 4835 | if ((ahc->features & AHC_WIDE) != 0) |
| 4836 | tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT0x01; |
| 4837 | |
| 4838 | /* |
| 4839 | * These will be truncated when we determine the |
| 4840 | * connection type we have with the target. |
| 4841 | */ |
| 4842 | tinfo->user.period = ahc_syncrates->period; |
| 4843 | tinfo->user.offset = MAX_OFFSET0x7f; |
| 4844 | } else { |
| 4845 | u_int scsirate; |
| 4846 | uint16_t mask; |
| 4847 | |
| 4848 | /* Take the settings leftover in scratch RAM. */ |
| 4849 | scsirate = ahc_inb(ahc, TARG_SCSIRATE + i)(((ahc)->tag)->read_1(((ahc)->bsh), (0x20 + i))); |
| 4850 | mask = (0x01 << i); |
| 4851 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 4852 | u_int offset; |
| 4853 | u_int maxsync; |
| 4854 | |
| 4855 | if ((scsirate & SOFS0x0f) == 0x0F) { |
| 4856 | /* |
| 4857 | * Haven't negotiated yet, |
| 4858 | * so the format is different. |
| 4859 | */ |
| 4860 | scsirate = (scsirate & SXFR0x70) >> 4 |
| 4861 | | (ultraenb & mask) |
| 4862 | ? 0x08 : 0x0 |
| 4863 | | (scsirate & WIDEXFER0x80); |
| 4864 | offset = MAX_OFFSET_ULTRA20x7f; |
| 4865 | } else |
| 4866 | offset = ahc_inb(ahc, TARG_OFFSET + i)(((ahc)->tag)->read_1(((ahc)->bsh), (0x70 + i))); |
| 4867 | if ((scsirate & ~WIDEXFER0x80) == 0 && offset != 0) |
| 4868 | /* Set to the lowest sync rate, 5MHz */ |
| 4869 | scsirate |= 0x1c; |
| 4870 | maxsync = AHC_SYNCRATE_ULTRA21; |
| 4871 | if ((ahc->features & AHC_DT) != 0) |
| 4872 | maxsync = AHC_SYNCRATE_DT0; |
| 4873 | tinfo->user.period = |
| 4874 | ahc_find_period(ahc, scsirate, maxsync); |
| 4875 | if (offset == 0) |
| 4876 | tinfo->user.period = 0; |
| 4877 | else |
| 4878 | tinfo->user.offset = MAX_OFFSET0x7f; |
| 4879 | if ((scsirate & SXFR_ULTRA20x0f) <= 8/*10MHz*/ |
| 4880 | && (ahc->features & AHC_DT) != 0) |
| 4881 | tinfo->user.ppr_options = |
| 4882 | MSG_EXT_PPR_DT_REQ0x02; |
| 4883 | } else if ((scsirate & SOFS0x0f) != 0) { |
| 4884 | if ((scsirate & SXFR0x70) == 0x40 |
| 4885 | && (ultraenb & mask) != 0) { |
| 4886 | /* Treat 10MHz as a non-ultra speed */ |
| 4887 | scsirate &= ~SXFR0x70; |
| 4888 | ultraenb &= ~mask; |
| 4889 | } |
| 4890 | tinfo->user.period = |
| 4891 | ahc_find_period(ahc, scsirate, |
| 4892 | (ultraenb & mask) |
| 4893 | ? AHC_SYNCRATE_ULTRA3 |
| 4894 | : AHC_SYNCRATE_FAST6); |
| 4895 | if (tinfo->user.period != 0) |
| 4896 | tinfo->user.offset = MAX_OFFSET0x7f; |
| 4897 | } |
| 4898 | if (tinfo->user.period == 0) |
| 4899 | tinfo->user.offset = 0; |
| 4900 | if ((scsirate & WIDEXFER0x80) != 0 |
| 4901 | && (ahc->features & AHC_WIDE) != 0) |
| 4902 | tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT0x01; |
| 4903 | tinfo->user.protocol_version = 4; |
| 4904 | if ((ahc->features & AHC_DT) != 0) |
| 4905 | tinfo->user.transport_version = 3; |
| 4906 | else |
| 4907 | tinfo->user.transport_version = 2; |
| 4908 | tinfo->goal.protocol_version = 2; |
| 4909 | tinfo->goal.transport_version = 2; |
| 4910 | tinfo->curr.protocol_version = 2; |
| 4911 | tinfo->curr.transport_version = 2; |
| 4912 | } |
| 4913 | tstate->ultraenb = 0; |
| 4914 | tstate->discenable = discenable; |
| 4915 | } |
| 4916 | ahc->user_discenable = discenable; |
| 4917 | ahc->user_tagenable = tagenable; |
| 4918 | |
| 4919 | return (ahc->bus_chip_init(ahc)); |
| 4920 | } |
| 4921 | |
| 4922 | void |
| 4923 | ahc_intr_enable(struct ahc_softc *ahc, int enable) |
| 4924 | { |
| 4925 | u_int hcntrl; |
| 4926 | |
| 4927 | hcntrl = ahc_inb(ahc, HCNTRL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x87))); |
| 4928 | hcntrl &= ~INTEN0x02; |
| 4929 | ahc->pause &= ~INTEN0x02; |
| 4930 | ahc->unpause &= ~INTEN0x02; |
| 4931 | if (enable) { |
| 4932 | hcntrl |= INTEN0x02; |
| 4933 | ahc->pause |= INTEN0x02; |
| 4934 | ahc->unpause |= INTEN0x02; |
| 4935 | } |
| 4936 | ahc_outb(ahc, HCNTRL, hcntrl)(((ahc)->tag)->write_1(((ahc)->bsh), (0x87), (hcntrl ))); |
| 4937 | } |
| 4938 | |
| 4939 | /************************** Busy Target Table *********************************/ |
| 4940 | /* |
| 4941 | * Return the untagged transaction id for a given target/channel lun. |
| 4942 | * Optionally, clear the entry. |
| 4943 | */ |
| 4944 | u_int |
| 4945 | ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) |
| 4946 | { |
| 4947 | u_int scbid; |
| 4948 | u_int target_offset; |
| 4949 | |
| 4950 | if ((ahc->flags & AHC_SCB_BTT) != 0) { |
| 4951 | u_int saved_scbptr; |
| 4952 | |
| 4953 | saved_scbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 4954 | ahc_outb(ahc, SCBPTR, TCL_LUN(tcl))(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), ((tcl & (64 - 1))))); |
| 4955 | scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl))(((ahc)->tag)->read_1(((ahc)->bsh), (0xd0 + ((((tcl) >> 4) & 0xf0) >> 4)))); |
| 4956 | ahc_outb(ahc, SCBPTR, saved_scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (saved_scbptr ))); |
| 4957 | } else { |
| 4958 | target_offset = TCL_TARGET_OFFSET(tcl)((((tcl) >> 4) & 0xf0) >> 4); |
| 4959 | scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset)(((ahc)->tag)->read_1(((ahc)->bsh), (0x20 + target_offset ))); |
| 4960 | } |
| 4961 | |
| 4962 | return (scbid); |
| 4963 | } |
| 4964 | |
| 4965 | void |
| 4966 | ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) |
| 4967 | { |
| 4968 | u_int target_offset; |
| 4969 | |
| 4970 | if ((ahc->flags & AHC_SCB_BTT) != 0) { |
| 4971 | u_int saved_scbptr; |
| 4972 | |
| 4973 | saved_scbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 4974 | ahc_outb(ahc, SCBPTR, TCL_LUN(tcl))(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), ((tcl & (64 - 1))))); |
| 4975 | ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0xd0 +((((tcl) >> 4) & 0xf0) >> 4)), (0xff))); |
| 4976 | ahc_outb(ahc, SCBPTR, saved_scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (saved_scbptr ))); |
| 4977 | } else { |
| 4978 | target_offset = TCL_TARGET_OFFSET(tcl)((((tcl) >> 4) & 0xf0) >> 4); |
| 4979 | ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0x20 + target_offset ), (0xff))); |
| 4980 | } |
| 4981 | } |
| 4982 | |
| 4983 | void |
| 4984 | ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) |
| 4985 | { |
| 4986 | u_int target_offset; |
| 4987 | |
| 4988 | if ((ahc->flags & AHC_SCB_BTT) != 0) { |
| 4989 | u_int saved_scbptr; |
| 4990 | |
| 4991 | saved_scbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 4992 | ahc_outb(ahc, SCBPTR, TCL_LUN(tcl))(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), ((tcl & (64 - 1))))); |
| 4993 | ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid)(((ahc)->tag)->write_1(((ahc)->bsh), (0xd0 + ((((tcl ) >> 4) & 0xf0) >> 4)), (scbid))); |
| 4994 | ahc_outb(ahc, SCBPTR, saved_scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (saved_scbptr ))); |
| 4995 | } else { |
| 4996 | target_offset = TCL_TARGET_OFFSET(tcl)((((tcl) >> 4) & 0xf0) >> 4); |
| 4997 | ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid)(((ahc)->tag)->write_1(((ahc)->bsh), (0x20 + target_offset ), (scbid))); |
| 4998 | } |
| 4999 | } |
| 5000 | |
| 5001 | /************************** SCB and SCB queue management **********************/ |
| 5002 | int |
| 5003 | ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, |
| 5004 | char channel, int lun, u_int tag, role_t role) |
| 5005 | { |
| 5006 | char chan; |
| 5007 | int targ, slun, match; |
| 5008 | |
| 5009 | if (scb == NULL((void *)0)) |
| 5010 | return 0; |
| 5011 | |
| 5012 | targ = SCB_GET_TARGET(ahc, scb)((((scb)->hscb->scsiid) & (((((ahc))->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04); |
| 5013 | chan = SCB_GET_CHANNEL(ahc, scb)((((ahc)->features & AHC_TWIN) != 0) ? (((((scb)->hscb ->scsiid) & 0x80) != 0) ? 'B' : 'A') : 'A'); |
| 5014 | slun = SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f); |
| 5015 | |
| 5016 | match = ((chan == channel) || (channel == ALL_CHANNELS'\0')); |
| 5017 | if (match != 0) |
| 5018 | match = ((targ == target) || (target == CAM_TARGET_WILDCARD((u_int)~0))); |
| 5019 | if (match != 0) |
| 5020 | match = ((lun == slun) || (lun == CAM_LUN_WILDCARD-1)); |
| 5021 | if (match != 0) { |
| 5022 | #ifdef AHC_TARGET_MODE |
| 5023 | int group; |
| 5024 | |
| 5025 | group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); |
| 5026 | if (role == ROLE_INITIATOR) { |
| 5027 | match = (group != XPT_FC_GROUP_TMODE) |
| 5028 | && ((tag == scb->hscb->tag) |
| 5029 | || (tag == SCB_LIST_NULL0xff)); |
| 5030 | } else if (role == ROLE_TARGET) { |
| 5031 | match = (group == XPT_FC_GROUP_TMODE) |
| 5032 | && ((tag == scb->io_ctx->csio.tag_id) |
| 5033 | || (tag == SCB_LIST_NULL0xff)); |
| 5034 | } |
| 5035 | #else /* !AHC_TARGET_MODE */ |
| 5036 | match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL0xff)); |
| 5037 | #endif /* AHC_TARGET_MODE */ |
| 5038 | } |
| 5039 | |
| 5040 | return match; |
| 5041 | } |
| 5042 | |
| 5043 | void |
| 5044 | ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) |
| 5045 | { |
| 5046 | int target; |
| 5047 | char channel; |
| 5048 | int lun; |
| 5049 | |
| 5050 | target = SCB_GET_TARGET(ahc, scb)((((scb)->hscb->scsiid) & (((((ahc))->features & AHC_TWIN) != 0) ? 0x70 : 0xf0)) >> 0x04); |
| 5051 | lun = SCB_GET_LUN(scb)((scb)->hscb->lun & 0x3f); |
| 5052 | channel = SCB_GET_CHANNEL(ahc, scb)((((ahc)->features & AHC_TWIN) != 0) ? (((((scb)->hscb ->scsiid) & 0x80) != 0) ? 'B' : 'A') : 'A'); |
| 5053 | |
| 5054 | ahc_search_qinfifo(ahc, target, channel, lun, |
| 5055 | /*tag*/SCB_LIST_NULL0xff, ROLE_UNKNOWN, |
| 5056 | CAM_REQUEUE_REQ, SEARCH_COMPLETE); |
| 5057 | } |
| 5058 | |
| 5059 | void |
| 5060 | ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) |
| 5061 | { |
| 5062 | struct scb *prev_scb; |
| 5063 | |
| 5064 | prev_scb = NULL((void *)0); |
| 5065 | if (ahc_qinfifo_count(ahc) != 0) { |
| 5066 | u_int prev_tag; |
| 5067 | uint8_t prev_pos; |
| 5068 | |
| 5069 | prev_pos = ahc->qinfifonext - 1; |
| 5070 | prev_tag = ahc->qinfifo[prev_pos]; |
| 5071 | prev_scb = ahc_lookup_scb(ahc, prev_tag); |
| 5072 | } |
| 5073 | ahc_qinfifo_requeue(ahc, prev_scb, scb); |
| 5074 | if ((ahc->features & AHC_QUEUE_REGS) != 0) { |
| 5075 | ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf4), (ahc-> qinfifonext))); |
| 5076 | } else { |
| 5077 | ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4c), (ahc-> qinfifonext))); |
| 5078 | } |
| 5079 | } |
| 5080 | |
| 5081 | static void |
| 5082 | ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, |
| 5083 | struct scb *scb) |
| 5084 | { |
| 5085 | if (prev_scb == NULL((void *)0)) { |
| 5086 | ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag)(((ahc)->tag)->write_1(((ahc)->bsh), (0x39), (scb-> hscb->tag))); |
| 5087 | } else { |
| 5088 | prev_scb->hscb->next = scb->hscb->tag; |
| 5089 | ahc_sync_scb(ahc, prev_scb, |
| 5090 | BUS_DMASYNC_PREREAD0x01|BUS_DMASYNC_PREWRITE0x04); |
| 5091 | } |
| 5092 | ahc->qinfifo[ahc->qinfifonext] = scb->hscb->tag; |
| 5093 | ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (ahc->qinfifonext+256), ( 1), (0x04)) |
| 5094 | /*offset*/ahc->qinfifonext+256, /*len*/1,(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (ahc->qinfifonext+256), ( 1), (0x04)) |
| 5095 | BUS_DMASYNC_PREWRITE)(*(ahc->parent_dmat)->_dmamap_sync)((ahc->parent_dmat ), (ahc->shared_data_dmamap), (ahc->qinfifonext+256), ( 1), (0x04)); |
| 5096 | ahc->qinfifonext++; |
| 5097 | scb->hscb->next = ahc->next_queued_scb->hscb->tag; |
| 5098 | ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD0x01|BUS_DMASYNC_PREWRITE0x04); |
| 5099 | } |
| 5100 | |
| 5101 | static int |
| 5102 | ahc_qinfifo_count(struct ahc_softc *ahc) |
| 5103 | { |
| 5104 | uint8_t qinpos; |
| 5105 | uint8_t diff; |
| 5106 | |
| 5107 | if ((ahc->features & AHC_QUEUE_REGS) != 0) { |
| 5108 | qinpos = ahc_inb(ahc, SNSCB_QOFF)(((ahc)->tag)->read_1(((ahc)->bsh), (0xf6))); |
| 5109 | ahc_outb(ahc, SNSCB_QOFF, qinpos)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf6), (qinpos ))); |
| 5110 | } else |
| 5111 | qinpos = ahc_inb(ahc, QINPOS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x4d))); |
| 5112 | diff = ahc->qinfifonext - qinpos; |
| 5113 | return (diff); |
| 5114 | } |
| 5115 | |
| 5116 | int |
| 5117 | ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, |
| 5118 | int lun, u_int tag, role_t role, uint32_t status, |
| 5119 | ahc_search_action action) |
| 5120 | { |
| 5121 | struct scb *scb; |
| 5122 | struct scb *prev_scb; |
| 5123 | uint8_t qinstart; |
| 5124 | uint8_t qinpos; |
| 5125 | uint8_t qintail; |
| 5126 | uint8_t next; |
| 5127 | uint8_t prev; |
| 5128 | uint8_t curscbptr; |
| 5129 | int found; |
| 5130 | int have_qregs; |
| 5131 | |
| 5132 | qintail = ahc->qinfifonext; |
| 5133 | have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; |
| 5134 | if (have_qregs) { |
| 5135 | qinstart = ahc_inb(ahc, SNSCB_QOFF)(((ahc)->tag)->read_1(((ahc)->bsh), (0xf6))); |
| 5136 | ahc_outb(ahc, SNSCB_QOFF, qinstart)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf6), (qinstart ))); |
| 5137 | } else |
| 5138 | qinstart = ahc_inb(ahc, QINPOS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x4d))); |
| 5139 | qinpos = qinstart; |
| 5140 | found = 0; |
| 5141 | prev_scb = NULL((void *)0); |
| 5142 | |
| 5143 | if (action == SEARCH_COMPLETE) { |
| 5144 | /* |
| 5145 | * Don't attempt to run any queued untagged transactions |
| 5146 | * until we are done with the abort process. |
| 5147 | */ |
| 5148 | ahc_freeze_untagged_queues(ahc); |
| 5149 | } |
| 5150 | |
| 5151 | /* |
| 5152 | * Start with an empty queue. Entries that are not chosen |
| 5153 | * for removal will be re-added to the queue as we go. |
| 5154 | */ |
| 5155 | ahc->qinfifonext = qinpos; |
| 5156 | ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag)(((ahc)->tag)->write_1(((ahc)->bsh), (0x39), (ahc-> next_queued_scb->hscb->tag))); |
| 5157 | |
| 5158 | while (qinpos != qintail) { |
| 5159 | scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); |
| 5160 | if (scb == NULL((void *)0)) { |
| 5161 | printf("qinpos = %d, SCB index = %d\n", |
| 5162 | qinpos, ahc->qinfifo[qinpos]); |
| 5163 | panic("Loop 1"); |
| 5164 | } |
| 5165 | |
| 5166 | if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { |
| 5167 | /* |
| 5168 | * We found an scb that needs to be acted on. |
| 5169 | */ |
| 5170 | found++; |
| 5171 | switch (action) { |
| 5172 | case SEARCH_COMPLETE: |
| 5173 | { |
| 5174 | cam_status ostat; |
| 5175 | cam_status cstat; |
| 5176 | |
| 5177 | ostat = ahc_get_transaction_status(scb); |
| 5178 | if (ostat == CAM_REQ_INPROG) |
| 5179 | ahc_set_transaction_status(scb, status); |
| 5180 | cstat = ahc_get_transaction_status(scb); |
| 5181 | if (cstat != CAM_REQ_CMP) |
| 5182 | ahc_freeze_scb(scb); |
| 5183 | if ((scb->flags & SCB_ACTIVE) == 0) |
| 5184 | printf("Inactive SCB in qinfifo\n"); |
| 5185 | ahc_done(ahc, scb); |
| 5186 | |
| 5187 | /* FALLTHROUGH */ |
| 5188 | } |
| 5189 | case SEARCH_REMOVE: |
| 5190 | break; |
| 5191 | case SEARCH_COUNT: |
| 5192 | ahc_qinfifo_requeue(ahc, prev_scb, scb); |
| 5193 | prev_scb = scb; |
| 5194 | break; |
| 5195 | } |
| 5196 | } else { |
| 5197 | ahc_qinfifo_requeue(ahc, prev_scb, scb); |
| 5198 | prev_scb = scb; |
| 5199 | } |
| 5200 | qinpos++; |
| 5201 | } |
| 5202 | |
| 5203 | if ((ahc->features & AHC_QUEUE_REGS) != 0) { |
| 5204 | ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf4), (ahc-> qinfifonext))); |
| 5205 | } else { |
| 5206 | ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext)(((ahc)->tag)->write_1(((ahc)->bsh), (0x4c), (ahc-> qinfifonext))); |
| 5207 | } |
| 5208 | |
| 5209 | if (action != SEARCH_COUNT |
| 5210 | && (found != 0) |
| 5211 | && (qinstart != ahc->qinfifonext)) { |
| 5212 | /* |
| 5213 | * The sequencer may be in the process of DMA'ing |
| 5214 | * down the SCB at the beginning of the queue. |
| 5215 | * This could be problematic if either the first, |
| 5216 | * or the second SCB is removed from the queue |
| 5217 | * (the first SCB includes a pointer to the "next" |
| 5218 | * SCB to DMA). If we have removed any entries, swap |
| 5219 | * the first element in the queue with the next HSCB |
| 5220 | * so the sequencer will notice that NEXT_QUEUED_SCB |
| 5221 | * has changed during its DMA attempt and will retry |
| 5222 | * the DMA. |
| 5223 | */ |
| 5224 | scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); |
| 5225 | |
| 5226 | if (scb == NULL((void *)0)) { |
| 5227 | printf("found = %d, qinstart = %d, qinfifionext = %d\n", |
| 5228 | found, qinstart, ahc->qinfifonext); |
| 5229 | panic("First/Second Qinfifo fixup"); |
| 5230 | } |
| 5231 | /* |
| 5232 | * ahc_swap_with_next_hscb forces our next pointer to |
| 5233 | * point to the reserved SCB for future commands. Save |
| 5234 | * and restore our original next pointer to maintain |
| 5235 | * queue integrity. |
| 5236 | */ |
| 5237 | next = scb->hscb->next; |
| 5238 | ahc->scb_data->scbindex[scb->hscb->tag] = NULL((void *)0); |
| 5239 | ahc_swap_with_next_hscb(ahc, scb); |
| 5240 | scb->hscb->next = next; |
| 5241 | ahc->qinfifo[qinstart] = scb->hscb->tag; |
| 5242 | |
| 5243 | /* Tell the card about the new head of the qinfifo. */ |
| 5244 | ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag)(((ahc)->tag)->write_1(((ahc)->bsh), (0x39), (scb-> hscb->tag))); |
| 5245 | |
| 5246 | /* Fixup the tail "next" pointer. */ |
| 5247 | qintail = ahc->qinfifonext - 1; |
| 5248 | scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); |
| 5249 | scb->hscb->next = ahc->next_queued_scb->hscb->tag; |
| 5250 | } |
| 5251 | |
| 5252 | /* |
| 5253 | * Search waiting for selection list. |
| 5254 | */ |
| 5255 | curscbptr = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 5256 | next = ahc_inb(ahc, WAITING_SCBH)(((ahc)->tag)->read_1(((ahc)->bsh), (0x40))); /* Start at head of list. */ |
| 5257 | prev = SCB_LIST_NULL0xff; |
| 5258 | |
| 5259 | while (next != SCB_LIST_NULL0xff) { |
| 5260 | uint8_t scb_index; |
| 5261 | |
| 5262 | ahc_outb(ahc, SCBPTR, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (next)) ); |
| 5263 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 5264 | if (scb_index >= ahc->scb_data->numscbs) { |
| 5265 | printf("Waiting List inconsistency. " |
| 5266 | "SCB index == %d, yet numscbs == %d.", |
| 5267 | scb_index, ahc->scb_data->numscbs); |
| 5268 | ahc_dump_card_state(ahc); |
| 5269 | panic("for safety"); |
| 5270 | } |
| 5271 | scb = ahc_lookup_scb(ahc, scb_index); |
| 5272 | if (scb == NULL((void *)0)) { |
| 5273 | printf("scb_index = %d, next = %d\n", |
| 5274 | scb_index, next); |
| 5275 | panic("Waiting List traversal"); |
| 5276 | } |
| 5277 | if (ahc_match_scb(ahc, scb, target, channel, |
| 5278 | lun, SCB_LIST_NULL0xff, role)) { |
| 5279 | /* |
| 5280 | * We found an scb that needs to be acted on. |
| 5281 | */ |
| 5282 | found++; |
| 5283 | switch (action) { |
| 5284 | case SEARCH_COMPLETE: |
| 5285 | { |
| 5286 | cam_status ostat; |
| 5287 | cam_status cstat; |
| 5288 | |
| 5289 | ostat = ahc_get_transaction_status(scb); |
| 5290 | if (ostat == CAM_REQ_INPROG) |
| 5291 | ahc_set_transaction_status(scb, status); |
| 5292 | cstat = ahc_get_transaction_status(scb); |
| 5293 | if (cstat != CAM_REQ_CMP) |
| 5294 | ahc_freeze_scb(scb); |
| 5295 | if ((scb->flags & SCB_ACTIVE) == 0) |
| 5296 | printf("Inactive SCB in Wait List\n"); |
| 5297 | ahc_done(ahc, scb); |
| 5298 | /* FALLTHROUGH */ |
| 5299 | } |
| 5300 | case SEARCH_REMOVE: |
| 5301 | next = ahc_rem_wscb(ahc, next, prev); |
| 5302 | break; |
| 5303 | case SEARCH_COUNT: |
| 5304 | prev = next; |
| 5305 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5306 | break; |
| 5307 | } |
| 5308 | } else { |
| 5309 | |
| 5310 | prev = next; |
| 5311 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5312 | } |
| 5313 | } |
| 5314 | ahc_outb(ahc, SCBPTR, curscbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (curscbptr ))); |
| 5315 | |
| 5316 | found += ahc_search_untagged_queues(ahc, /*scsi_xfer*/NULL((void *)0), target, |
| 5317 | channel, lun, status, action); |
| 5318 | |
| 5319 | if (action == SEARCH_COMPLETE) |
| 5320 | ahc_release_untagged_queues(ahc); |
| 5321 | return (found); |
| 5322 | } |
| 5323 | |
| 5324 | int |
| 5325 | ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsi_xfer *xs, |
| 5326 | int target, char channel, int lun, uint32_t status, |
| 5327 | ahc_search_action action) |
| 5328 | { |
| 5329 | struct scb *scb; |
| 5330 | int maxtarget; |
| 5331 | int found; |
| 5332 | int i; |
| 5333 | |
| 5334 | if (action == SEARCH_COMPLETE) { |
| 5335 | /* |
| 5336 | * Don't attempt to run any queued untagged transactions |
| 5337 | * until we are done with the abort process. |
| 5338 | */ |
| 5339 | ahc_freeze_untagged_queues(ahc); |
| 5340 | } |
| 5341 | |
| 5342 | found = 0; |
| 5343 | i = 0; |
| 5344 | if ((ahc->flags & AHC_SCB_BTT) == 0) { |
| 5345 | |
| 5346 | maxtarget = 16; |
| 5347 | if (target != CAM_TARGET_WILDCARD((u_int)~0)) { |
| 5348 | |
| 5349 | i = target; |
| 5350 | if (channel == 'B') |
| 5351 | i += 8; |
| 5352 | maxtarget = i + 1; |
| 5353 | } |
| 5354 | } else { |
| 5355 | maxtarget = 0; |
| 5356 | } |
| 5357 | |
| 5358 | for (; i < maxtarget; i++) { |
| 5359 | struct scb_tailq *untagged_q; |
| 5360 | struct scb *next_scb; |
| 5361 | |
| 5362 | untagged_q = &(ahc->untagged_queues[i]); |
| 5363 | next_scb = TAILQ_FIRST(untagged_q)((untagged_q)->tqh_first); |
| 5364 | while (next_scb != NULL((void *)0)) { |
| 5365 | |
| 5366 | scb = next_scb; |
| 5367 | next_scb = TAILQ_NEXT(scb, links.tqe)((scb)->links.tqe.tqe_next); |
| 5368 | |
| 5369 | /* |
| 5370 | * The head of the list may be the currently |
| 5371 | * active untagged command for a device. |
| 5372 | * We're only searching for commands that |
| 5373 | * have not been started. A transaction |
| 5374 | * marked active but still in the qinfifo |
| 5375 | * is removed by the qinfifo scanning code |
| 5376 | * above. |
| 5377 | */ |
| 5378 | if ((scb->flags & SCB_ACTIVE) != 0) |
| 5379 | continue; |
| 5380 | |
| 5381 | if (ahc_match_scb(ahc, scb, target, channel, lun, |
| 5382 | SCB_LIST_NULL0xff, ROLE_INITIATOR) == 0 |
| 5383 | || (xs != NULL((void *)0) && xs != scb->xs)) |
| 5384 | continue; |
| 5385 | |
| 5386 | /* |
| 5387 | * We found an scb that needs to be acted on. |
| 5388 | */ |
| 5389 | found++; |
| 5390 | switch (action) { |
| 5391 | case SEARCH_COMPLETE: |
| 5392 | { |
| 5393 | cam_status ostat; |
| 5394 | cam_status cstat; |
| 5395 | |
| 5396 | ostat = ahc_get_transaction_status(scb); |
| 5397 | if (ostat == CAM_REQ_INPROG) |
| 5398 | ahc_set_transaction_status(scb, status); |
| 5399 | cstat = ahc_get_transaction_status(scb); |
| 5400 | if (cstat != CAM_REQ_CMP) |
| 5401 | ahc_freeze_scb(scb); |
| 5402 | ahc_done(ahc, scb); |
| 5403 | break; |
| 5404 | } |
| 5405 | case SEARCH_REMOVE: |
| 5406 | scb->flags &= ~SCB_UNTAGGEDQ; |
| 5407 | TAILQ_REMOVE(untagged_q, scb, links.tqe)do { if (((scb)->links.tqe.tqe_next) != ((void *)0)) (scb) ->links.tqe.tqe_next->links.tqe.tqe_prev = (scb)->links .tqe.tqe_prev; else (untagged_q)->tqh_last = (scb)->links .tqe.tqe_prev; *(scb)->links.tqe.tqe_prev = (scb)->links .tqe.tqe_next; ((scb)->links.tqe.tqe_prev) = ((void *)-1); ((scb)->links.tqe.tqe_next) = ((void *)-1); } while (0); |
| 5408 | break; |
| 5409 | case SEARCH_COUNT: |
| 5410 | break; |
| 5411 | } |
| 5412 | } |
| 5413 | } |
| 5414 | |
| 5415 | if (action == SEARCH_COMPLETE) |
| 5416 | ahc_release_untagged_queues(ahc); |
| 5417 | return (found); |
| 5418 | } |
| 5419 | |
| 5420 | int |
| 5421 | ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, |
| 5422 | int lun, u_int tag, int stop_on_first, int remove, |
| 5423 | int save_state) |
| 5424 | { |
| 5425 | struct scb *scbp; |
| 5426 | u_int next; |
| 5427 | u_int prev; |
| 5428 | u_int count; |
| 5429 | u_int active_scb; |
| 5430 | |
| 5431 | count = 0; |
| 5432 | next = ahc_inb(ahc, DISCONNECTED_SCBH)(((ahc)->tag)->read_1(((ahc)->bsh), (0x41))); |
| 5433 | prev = SCB_LIST_NULL0xff; |
| 5434 | |
| 5435 | if (save_state) { |
| 5436 | /* restore this when we're done */ |
| 5437 | active_scb = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 5438 | } else |
| 5439 | /* Silence compiler */ |
| 5440 | active_scb = SCB_LIST_NULL0xff; |
| 5441 | |
| 5442 | while (next != SCB_LIST_NULL0xff) { |
| 5443 | u_int scb_index; |
| 5444 | |
| 5445 | ahc_outb(ahc, SCBPTR, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (next)) ); |
| 5446 | scb_index = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 5447 | if (scb_index >= ahc->scb_data->numscbs) { |
| 5448 | printf("Disconnected List inconsistency. " |
| 5449 | "SCB index == %d, yet numscbs == %d.", |
| 5450 | scb_index, ahc->scb_data->numscbs); |
| 5451 | ahc_dump_card_state(ahc); |
| 5452 | panic("for safety"); |
| 5453 | } |
| 5454 | |
| 5455 | if (next == prev) { |
| 5456 | panic("Disconnected List Loop. " |
| 5457 | "cur SCBPTR == %x, prev SCBPTR == %x.", |
| 5458 | next, prev); |
| 5459 | } |
| 5460 | scbp = ahc_lookup_scb(ahc, scb_index); |
| 5461 | if (ahc_match_scb(ahc, scbp, target, channel, lun, |
| 5462 | tag, ROLE_INITIATOR)) { |
| 5463 | count++; |
| 5464 | if (remove) { |
| 5465 | next = |
| 5466 | ahc_rem_scb_from_disc_list(ahc, prev, next); |
| 5467 | } else { |
| 5468 | prev = next; |
| 5469 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5470 | } |
| 5471 | if (stop_on_first) |
| 5472 | break; |
| 5473 | } else { |
| 5474 | prev = next; |
| 5475 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5476 | } |
| 5477 | } |
| 5478 | if (save_state) |
| 5479 | ahc_outb(ahc, SCBPTR, active_scb)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (active_scb ))); |
| 5480 | return (count); |
| 5481 | } |
| 5482 | |
| 5483 | /* |
| 5484 | * Remove an SCB from the on chip list of disconnected transactions. |
| 5485 | * This is empty/unused if we are not performing SCB paging. |
| 5486 | */ |
| 5487 | static u_int |
| 5488 | ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) |
| 5489 | { |
| 5490 | u_int next; |
| 5491 | |
| 5492 | ahc_outb(ahc, SCBPTR, scbptr)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (scbptr ))); |
| 5493 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5494 | |
| 5495 | ahc_outb(ahc, SCB_CONTROL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), (0))); |
| 5496 | |
| 5497 | ahc_add_curscb_to_free_list(ahc); |
| 5498 | |
| 5499 | if (prev != SCB_LIST_NULL0xff) { |
| 5500 | ahc_outb(ahc, SCBPTR, prev)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (prev)) ); |
| 5501 | ahc_outb(ahc, SCB_NEXT, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), (next)) ); |
| 5502 | } else |
| 5503 | ahc_outb(ahc, DISCONNECTED_SCBH, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0x41), (next)) ); |
| 5504 | |
| 5505 | return (next); |
| 5506 | } |
| 5507 | |
| 5508 | /* |
| 5509 | * Add the SCB as selected by SCBPTR onto the on chip list of |
| 5510 | * free hardware SCBs. This list is empty/unused if we are not |
| 5511 | * performing SCB paging. |
| 5512 | */ |
| 5513 | static void |
| 5514 | ahc_add_curscb_to_free_list(struct ahc_softc *ahc) |
| 5515 | { |
| 5516 | /* |
| 5517 | * Invalidate the tag so that our abort |
| 5518 | * routines don't think it's active. |
| 5519 | */ |
| 5520 | ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbb), (0xff)) ); |
| 5521 | |
| 5522 | if ((ahc->flags & AHC_PAGESCBS) != 0) { |
| 5523 | ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH))(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x42)))))); |
| 5524 | ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR))(((ahc)->tag)->write_1(((ahc)->bsh), (0x42), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x90)))))); |
| 5525 | } |
| 5526 | } |
| 5527 | |
| 5528 | /* |
| 5529 | * Manipulate the waiting for selection list and return the |
| 5530 | * scb that follows the one that we remove. |
| 5531 | */ |
| 5532 | static u_int |
| 5533 | ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) |
| 5534 | { |
| 5535 | u_int curscb, next; |
| 5536 | |
| 5537 | /* |
| 5538 | * Select the SCB we want to abort and |
| 5539 | * pull the next pointer out of it. |
| 5540 | */ |
| 5541 | curscb = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 5542 | ahc_outb(ahc, SCBPTR, scbpos)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (scbpos ))); |
| 5543 | next = ahc_inb(ahc, SCB_NEXT)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbf))); |
| 5544 | |
| 5545 | /* Clear the necessary fields */ |
| 5546 | ahc_outb(ahc, SCB_CONTROL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0xb8), (0))); |
| 5547 | |
| 5548 | ahc_add_curscb_to_free_list(ahc); |
| 5549 | |
| 5550 | /* update the waiting list */ |
| 5551 | if (prev == SCB_LIST_NULL0xff) { |
| 5552 | /* First in the list */ |
| 5553 | ahc_outb(ahc, WAITING_SCBH, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0x40), (next)) ); |
| 5554 | |
| 5555 | /* |
| 5556 | * Ensure we aren't attempting to perform |
| 5557 | * selection for this entry. |
| 5558 | */ |
| 5559 | ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (((((ahc )->tag)->read_1(((ahc)->bsh), (0x00))) & ~0x40)) )); |
| 5560 | } else { |
| 5561 | /* |
| 5562 | * Select the scb that pointed to us |
| 5563 | * and update its next pointer. |
| 5564 | */ |
| 5565 | ahc_outb(ahc, SCBPTR, prev)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (prev)) ); |
| 5566 | ahc_outb(ahc, SCB_NEXT, next)(((ahc)->tag)->write_1(((ahc)->bsh), (0xbf), (next)) ); |
| 5567 | } |
| 5568 | |
| 5569 | /* |
| 5570 | * Point us back at the original scb position. |
| 5571 | */ |
| 5572 | ahc_outb(ahc, SCBPTR, curscb)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (curscb ))); |
| 5573 | return next; |
| 5574 | } |
| 5575 | |
| 5576 | /******************************** Error Handling ******************************/ |
| 5577 | /* |
| 5578 | * Abort all SCBs that match the given description (target/channel/lun/tag), |
| 5579 | * setting their status to the passed in status if the status has not already |
| 5580 | * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer |
| 5581 | * is paused before it is called. |
| 5582 | */ |
| 5583 | int |
| 5584 | ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, |
| 5585 | int lun, u_int tag, role_t role, uint32_t status) |
| 5586 | { |
| 5587 | struct scb *scbp; |
| 5588 | struct scb *scbp_next; |
| 5589 | u_int active_scb; |
| 5590 | int i, j; |
| 5591 | int maxtarget; |
| 5592 | int minlun; |
| 5593 | int maxlun; |
| 5594 | |
| 5595 | int found; |
| 5596 | |
| 5597 | /* |
| 5598 | * Don't attempt to run any queued untagged transactions |
| 5599 | * until we are done with the abort process. |
| 5600 | */ |
| 5601 | ahc_freeze_untagged_queues(ahc); |
| 5602 | |
| 5603 | /* restore this when we're done */ |
| 5604 | active_scb = ahc_inb(ahc, SCBPTR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x90))); |
| 5605 | |
| 5606 | found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL0xff, |
| 5607 | role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); |
| 5608 | |
| 5609 | /* |
| 5610 | * Clean out the busy target table for any untagged commands. |
| 5611 | */ |
| 5612 | i = 0; |
| 5613 | maxtarget = 16; |
| 5614 | if (target != CAM_TARGET_WILDCARD((u_int)~0)) { |
| 5615 | i = target; |
| 5616 | if (channel == 'B') |
| 5617 | i += 8; |
| 5618 | maxtarget = i + 1; |
| 5619 | } |
| 5620 | |
| 5621 | if (lun == CAM_LUN_WILDCARD-1) { |
| 5622 | |
| 5623 | /* |
| 5624 | * Unless we are using an SCB based |
| 5625 | * busy targets table, there is only |
| 5626 | * one table entry for all luns of |
| 5627 | * a target. |
| 5628 | */ |
| 5629 | minlun = 0; |
| 5630 | maxlun = 1; |
| 5631 | if ((ahc->flags & AHC_SCB_BTT) != 0) |
| 5632 | maxlun = AHC_NUM_LUNS64; |
| 5633 | } else { |
| 5634 | minlun = lun; |
| 5635 | maxlun = lun + 1; |
| 5636 | } |
| 5637 | |
| 5638 | if (role != ROLE_TARGET) { |
| 5639 | for (;i < maxtarget; i++) { |
| 5640 | for (j = minlun;j < maxlun; j++) { |
| 5641 | u_int scbid; |
| 5642 | u_int tcl; |
| 5643 | |
| 5644 | tcl = BUILD_TCL(i << 4, j)((j) | (((i << 4) & 0xf0) << 4)); |
| 5645 | scbid = ahc_index_busy_tcl(ahc, tcl); |
| 5646 | scbp = ahc_lookup_scb(ahc, scbid); |
| 5647 | if (scbp == NULL((void *)0) |
| 5648 | || ahc_match_scb(ahc, scbp, target, channel, |
| 5649 | lun, tag, role) == 0) |
| 5650 | continue; |
| 5651 | ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)((j) | (((i << 4) & 0xf0) << 4))); |
| 5652 | } |
| 5653 | } |
| 5654 | |
| 5655 | /* |
| 5656 | * Go through the disconnected list and remove any entries we |
| 5657 | * have queued for completion, 0'ing their control byte too. |
| 5658 | * We save the active SCB and restore it ourselves, so there |
| 5659 | * is no reason for this search to restore it too. |
| 5660 | */ |
| 5661 | ahc_search_disc_list(ahc, target, channel, lun, tag, |
| 5662 | /*stop_on_first*/FALSE0, /*remove*/TRUE1, |
| 5663 | /*save_state*/FALSE0); |
| 5664 | } |
| 5665 | |
| 5666 | /* |
| 5667 | * Go through the hardware SCB array looking for commands that |
| 5668 | * were active but not on any list. In some cases, these remnants |
| 5669 | * might not still have mappings in the scbindex array (e.g. unexpected |
| 5670 | * bus free with the same scb queued for an abort). Don't hold this |
| 5671 | * against them. |
| 5672 | */ |
| 5673 | for (i = 0; i < ahc->scb_data->maxhscbs; i++) { |
| 5674 | u_int scbid; |
| 5675 | |
| 5676 | ahc_outb(ahc, SCBPTR, i)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (i))); |
| 5677 | scbid = ahc_inb(ahc, SCB_TAG)(((ahc)->tag)->read_1(((ahc)->bsh), (0xbb))); |
| 5678 | scbp = ahc_lookup_scb(ahc, scbid); |
| 5679 | if ((scbp == NULL((void *)0) && scbid != SCB_LIST_NULL0xff) |
| 5680 | || (scbp != NULL((void *)0) |
| 5681 | && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) |
| 5682 | ahc_add_curscb_to_free_list(ahc); |
| 5683 | } |
| 5684 | |
| 5685 | /* |
| 5686 | * Go through the pending CCB list and look for |
| 5687 | * commands for this target that are still active. |
| 5688 | * These are other tagged commands that were |
| 5689 | * disconnected when the reset occurred. |
| 5690 | */ |
| 5691 | scbp_next = LIST_FIRST(&ahc->pending_scbs)((&ahc->pending_scbs)->lh_first); |
| 5692 | while (scbp_next != NULL((void *)0)) { |
| 5693 | scbp = scbp_next; |
| 5694 | scbp_next = LIST_NEXT(scbp, pending_links)((scbp)->pending_links.le_next); |
| 5695 | if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { |
| 5696 | cam_status ostat; |
| 5697 | |
| 5698 | ostat = ahc_get_transaction_status(scbp); |
| 5699 | if (ostat == CAM_REQ_INPROG) |
| 5700 | ahc_set_transaction_status(scbp, status); |
| 5701 | if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) |
| 5702 | ahc_freeze_scb(scbp); |
| 5703 | if ((scbp->flags & SCB_ACTIVE) == 0) |
| 5704 | printf("Inactive SCB on pending list\n"); |
| 5705 | ahc_done(ahc, scbp); |
| 5706 | found++; |
| 5707 | } |
| 5708 | } |
| 5709 | ahc_outb(ahc, SCBPTR, active_scb)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (active_scb ))); |
| 5710 | ahc_release_untagged_queues(ahc); |
| 5711 | return found; |
| 5712 | } |
| 5713 | |
| 5714 | static void |
| 5715 | ahc_reset_current_bus(struct ahc_softc *ahc) |
| 5716 | { |
| 5717 | uint8_t scsiseq; |
| 5718 | |
| 5719 | ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x11))) & ~0x20)) ); |
| 5720 | scsiseq = ahc_inb(ahc, SCSISEQ)(((ahc)->tag)->read_1(((ahc)->bsh), (0x00))); |
| 5721 | ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (scsiseq | 0x01))); |
| 5722 | ahc_flush_device_writes(ahc); |
| 5723 | aic_delay(AHC_BUSRESET_DELAY)(*delay_func)(25); |
| 5724 | /* Turn off the bus reset */ |
| 5725 | ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO)(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (scsiseq & ~0x01))); |
| 5726 | |
| 5727 | ahc_clear_intstat(ahc); |
| 5728 | |
| 5729 | /* Re-enable reset interrupts */ |
| 5730 | ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), ((((ahc )->tag)->read_1(((ahc)->bsh), (0x11))) | 0x20))); |
| 5731 | } |
| 5732 | |
| 5733 | int |
| 5734 | ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) |
| 5735 | { |
| 5736 | struct ahc_devinfo devinfo; |
| 5737 | u_int initiator, target, max_scsiid; |
| 5738 | u_int sblkctl; |
| 5739 | u_int scsiseq; |
| 5740 | u_int simode1; |
| 5741 | int found; |
| 5742 | int restart_needed; |
| 5743 | char cur_channel; |
| 5744 | |
| 5745 | ahc->pending_device = NULL((void *)0); |
| 5746 | |
| 5747 | ahc_compile_devinfo(&devinfo, |
| 5748 | CAM_TARGET_WILDCARD((u_int)~0), |
| 5749 | CAM_TARGET_WILDCARD((u_int)~0), |
| 5750 | CAM_LUN_WILDCARD-1, |
| 5751 | channel, ROLE_UNKNOWN); |
| 5752 | ahc_pause(ahc); |
| 5753 | |
| 5754 | /* Make sure the sequencer is in a safe location. */ |
| 5755 | ahc_clear_critical_section(ahc); |
| 5756 | |
| 5757 | /* |
| 5758 | * Run our command complete fifos to ensure that we perform |
| 5759 | * completion processing on any commands that 'completed' |
| 5760 | * before the reset occurred. |
| 5761 | */ |
| 5762 | ahc_run_qoutfifo(ahc); |
| 5763 | #ifdef AHC_TARGET_MODE |
| 5764 | /* |
| 5765 | * XXX - In Twin mode, the tqinfifo may have commands |
| 5766 | * for an unaffected channel in it. However, if |
| 5767 | * we have run out of ATIO resources to drain that |
| 5768 | * queue, we may not get them all out here. Further, |
| 5769 | * the blocked transactions for the reset channel |
| 5770 | * should just be killed off, irrespective of whether |
| 5771 | * we are blocked on ATIO resources. Write a routine |
| 5772 | * to compact the tqinfifo appropriately. |
| 5773 | */ |
| 5774 | if ((ahc->flags & AHC_TARGETROLE) != 0) { |
| 5775 | ahc_run_tqinfifo(ahc, /*paused*/TRUE1); |
| 5776 | } |
| 5777 | #endif |
| 5778 | |
| 5779 | /* |
| 5780 | * Reset the bus if we are initiating this reset |
| 5781 | */ |
| 5782 | sblkctl = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))); |
| 5783 | cur_channel = 'A'; |
| 5784 | if ((ahc->features & AHC_TWIN) != 0 |
| 5785 | && ((sblkctl & SELBUSB0x08) != 0)) |
| 5786 | cur_channel = 'B'; |
| 5787 | scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x54))); |
| 5788 | if (cur_channel != channel) { |
| 5789 | /* Case 1: Command for another bus is active |
| 5790 | * Stealthily reset the other bus without |
| 5791 | * upsetting the current bus. |
| 5792 | */ |
| 5793 | ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl ^ 0x08))); |
| 5794 | simode1 = ahc_inb(ahc, SIMODE1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x11))) & ~(ENBUSFREE0x08|ENSCSIRST0x20); |
| 5795 | #ifdef AHC_TARGET_MODE |
| 5796 | /* |
| 5797 | * Bus resets clear ENSELI, so we cannot |
| 5798 | * defer re-enabling bus reset interrupts |
| 5799 | * if we are in target mode. |
| 5800 | */ |
| 5801 | if ((ahc->flags & AHC_TARGETROLE) != 0) |
| 5802 | simode1 |= ENSCSIRST0x20; |
| 5803 | #endif |
| 5804 | ahc_outb(ahc, SIMODE1, simode1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (simode1 ))); |
| 5805 | if (initiate_reset) |
| 5806 | ahc_reset_current_bus(ahc); |
| 5807 | ahc_clear_intstat(ahc); |
| 5808 | ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (scsiseq & (0x20|0x10|0x02)))); |
| 5809 | ahc_outb(ahc, SBLKCTL, sblkctl)(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), (sblkctl ))); |
| 5810 | restart_needed = FALSE0; |
| 5811 | } else { |
| 5812 | /* Case 2: A command from this bus is active or we're idle */ |
| 5813 | simode1 = ahc_inb(ahc, SIMODE1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x11))) & ~(ENBUSFREE0x08|ENSCSIRST0x20); |
| 5814 | #ifdef AHC_TARGET_MODE |
| 5815 | /* |
| 5816 | * Bus resets clear ENSELI, so we cannot |
| 5817 | * defer re-enabling bus reset interrupts |
| 5818 | * if we are in target mode. |
| 5819 | */ |
| 5820 | if ((ahc->flags & AHC_TARGETROLE) != 0) |
| 5821 | simode1 |= ENSCSIRST0x20; |
| 5822 | #endif |
| 5823 | ahc_outb(ahc, SIMODE1, simode1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x11), (simode1 ))); |
| 5824 | if (initiate_reset) |
| 5825 | ahc_reset_current_bus(ahc); |
| 5826 | ahc_clear_intstat(ahc); |
| 5827 | ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP))(((ahc)->tag)->write_1(((ahc)->bsh), (0x00), (scsiseq & (0x20|0x10|0x02)))); |
| 5828 | restart_needed = TRUE1; |
| 5829 | } |
| 5830 | |
| 5831 | /* |
| 5832 | * Clean up all the state information for the |
| 5833 | * pending transactions on this bus. |
| 5834 | */ |
| 5835 | found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD((u_int)~0), channel, |
| 5836 | CAM_LUN_WILDCARD-1, SCB_LIST_NULL0xff, |
| 5837 | ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); |
| 5838 | |
| 5839 | max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; |
| 5840 | |
| 5841 | #ifdef AHC_TARGET_MODE |
| 5842 | /* |
| 5843 | * Send an immediate notify ccb to all target more peripheral |
| 5844 | * drivers affected by this action. |
| 5845 | */ |
| 5846 | for (target = 0; target <= max_scsiid; target++) { |
| 5847 | struct ahc_tmode_tstate* tstate; |
| 5848 | u_int lun; |
| 5849 | |
| 5850 | tstate = ahc->enabled_targets[target]; |
| 5851 | if (tstate == NULL((void *)0)) |
| 5852 | continue; |
| 5853 | for (lun = 0; lun < AHC_NUM_LUNS64; lun++) { |
| 5854 | struct ahc_tmode_lstate* lstate; |
| 5855 | |
| 5856 | lstate = tstate->enabled_luns[lun]; |
| 5857 | if (lstate == NULL((void *)0)) |
| 5858 | continue; |
| 5859 | |
| 5860 | ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD((u_int)~0), |
| 5861 | EVENT_TYPE_BUS_RESET0xFF, /*arg*/0); |
| 5862 | ahc_send_lstate_events(ahc, lstate); |
| 5863 | } |
| 5864 | } |
| 5865 | #endif |
| 5866 | /* Notify the XPT that a bus reset occurred */ |
| 5867 | ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD((u_int)~0), |
| 5868 | CAM_LUN_WILDCARD-1, AC_BUS_RESET, NULL((void *)0)); |
| 5869 | |
| 5870 | /* |
| 5871 | * Revert to async/narrow transfers until we renegotiate. |
| 5872 | */ |
| 5873 | for (target = 0; target <= max_scsiid; target++) { |
| 5874 | |
| 5875 | if (ahc->enabled_targets[target] == NULL((void *)0)) |
| 5876 | continue; |
| 5877 | for (initiator = 0; initiator <= max_scsiid; initiator++) { |
| 5878 | ahc_compile_devinfo(&devinfo, target, initiator, |
| 5879 | CAM_LUN_WILDCARD-1, |
| 5880 | channel, ROLE_UNKNOWN); |
| 5881 | ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT0x00, |
| 5882 | AHC_TRANS_CUR0x01, /*paused*/TRUE1); |
| 5883 | ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL((void *)0), |
| 5884 | /*period*/0, /*offset*/0, |
| 5885 | /*ppr_options*/0, AHC_TRANS_CUR0x01, |
| 5886 | /*paused*/TRUE1); |
| 5887 | } |
| 5888 | } |
| 5889 | |
| 5890 | if (restart_needed) |
| 5891 | ahc_restart(ahc); |
| 5892 | else |
| 5893 | ahc_unpause(ahc); |
| 5894 | return found; |
| 5895 | } |
| 5896 | |
| 5897 | |
| 5898 | /***************************** Residual Processing ****************************/ |
| 5899 | /* |
| 5900 | * Calculate the residual for a just completed SCB. |
| 5901 | */ |
| 5902 | void |
| 5903 | ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) |
| 5904 | { |
| 5905 | struct hardware_scb *hscb; |
| 5906 | struct status_pkt *spkt; |
| 5907 | uint32_t sgptr; |
| 5908 | uint32_t resid_sgptr; |
| 5909 | uint32_t resid; |
| 5910 | |
| 5911 | /* |
| 5912 | * 5 cases. |
| 5913 | * 1) No residual. |
| 5914 | * SG_RESID_VALID clear in sgptr. |
| 5915 | * 2) Transferless command |
| 5916 | * 3) Never performed any transfers. |
| 5917 | * sgptr has SG_FULL_RESID set. |
| 5918 | * 4) No residual but target did not |
| 5919 | * save data pointers after the |
| 5920 | * last transfer, so sgptr was |
| 5921 | * never updated. |
| 5922 | * 5) We have a partial residual. |
| 5923 | * Use residual_sgptr to determine |
| 5924 | * where we are. |
| 5925 | */ |
| 5926 | |
| 5927 | hscb = scb->hscb; |
| 5928 | sgptr = aic_le32toh(hscb->sgptr)((__uint32_t)(hscb->sgptr)); |
| 5929 | if ((sgptr & SG_RESID_VALID0x04) == 0) |
| 5930 | /* Case 1 */ |
| 5931 | return; |
| 5932 | sgptr &= ~SG_RESID_VALID0x04; |
| 5933 | |
| 5934 | if ((sgptr & SG_LIST_NULL0x01) != 0) |
| 5935 | /* Case 2 */ |
| 5936 | return; |
| 5937 | |
| 5938 | spkt = &hscb->shared_data.status; |
| 5939 | resid_sgptr = aic_le32toh(spkt->residual_sg_ptr)((__uint32_t)(spkt->residual_sg_ptr)); |
| 5940 | if ((sgptr & SG_FULL_RESID0x02) != 0) { |