Bug Summary

File:dev/ic/ar5212.c
Warning:line 1079, column 2
Value stored to 'cw_min' is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ar5212.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/ic/ar5212.c
1/* $OpenBSD: ar5212.c,v 1.60 2022/01/09 05:42:38 jsg Exp $ */
2
3/*
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * HAL interface for the Atheros AR5001 Wireless LAN chipset
21 * (AR5212 + AR5111/AR5112).
22 */
23
24#include <dev/ic/ar5xxx.h>
25#include <dev/ic/ar5212reg.h>
26#include <dev/ic/ar5212var.h>
27
28HAL_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t);
29HAL_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t);
30u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, HAL_CHIP);
31void ar5k_ar5212_fill(struct ath_hal *);
32HAL_BOOL ar5k_ar5212_txpower(struct ath_hal *, HAL_CHANNEL *, u_int);
33HAL_BOOL ar5k_ar5212_warm_reset(struct ath_hal *);
34
35/*
36 * Initial register setting for the AR5212
37 */
38static const struct ar5k_ini ar5212_ini[] = AR5K_AR5212_INI{ { 0x000c, 0x00000000 }, { 0x0034, 0x00000005 }, { 0x0040, 0x00000000
}, { 0x0044, 0x00000008 }, { 0x0048, 0x00000008 }, { 0x004c,
0x00000010 }, { 0x0050, 0x00000000 }, { 0x0054, 0x0000001f }
, { 0x0800, 0x00000000 }, { 0x0804, 0x00000000 }, { 0x0808, 0x00000000
}, { 0x080c, 0x00000000 }, { 0x0810, 0x00000000 }, { 0x0814,
0x00000000 }, { 0x0818, 0x00000000 }, { 0x081c, 0x00000000 }
, { 0x0820, 0x00000000 }, { 0x0824, 0x00000000 }, { 0x1230, 0x00000000
}, { 0x1270, 0x00000000 }, { 0x1038, 0x00000000 }, { 0x1078,
0x00000000 }, { 0x10b8, 0x00000000 }, { 0x10f8, 0x00000000 }
, { 0x1138, 0x00000000 }, { 0x1178, 0x00000000 }, { 0x11b8, 0x00000000
}, { 0x11f8, 0x00000000 }, { 0x1238, 0x00000000 }, { 0x1278,
0x00000000 }, { 0x12b8, 0x00000000 }, { 0x12f8, 0x00000000 }
, { 0x1338, 0x00000000 }, { 0x1378, 0x00000000 }, { 0x13b8, 0x00000000
}, { 0x13f8, 0x00000000 }, { 0x1438, 0x00000000 }, { 0x1478,
0x00000000 }, { 0x14b8, 0x00000000 }, { 0x14f8, 0x00000000 }
, { 0x1538, 0x00000000 }, { 0x1578, 0x00000000 }, { 0x15b8, 0x00000000
}, { 0x15f8, 0x00000000 }, { 0x1638, 0x00000000 }, { 0x1678,
0x00000000 }, { 0x16b8, 0x00000000 }, { 0x16f8, 0x00000000 }
, { 0x1738, 0x00000000 }, { 0x1778, 0x00000000 }, { 0x17b8, 0x00000000
}, { 0x17f8, 0x00000000 }, { 0x103c, 0x00000000 }, { 0x107c,
0x00000000 }, { 0x10bc, 0x00000000 }, { 0x10fc, 0x00000000 }
, { 0x113c, 0x00000000 }, { 0x117c, 0x00000000 }, { 0x11bc, 0x00000000
}, { 0x11fc, 0x00000000 }, { 0x123c, 0x00000000 }, { 0x127c,
0x00000000 }, { 0x12bc, 0x00000000 }, { 0x12fc, 0x00000000 }
, { 0x133c, 0x00000000 }, { 0x137c, 0x00000000 }, { 0x13bc, 0x00000000
}, { 0x13fc, 0x00000000 }, { 0x143c, 0x00000000 }, { 0x147c,
0x00000000 }, { 0x143c, 0x00000000 }, { 0x147c, 0x00000000 }
, { 0x8004, 0x00000000 }, { 0x8008, 0x00000000 }, { 0x800c, 0x00000000
}, { 0x8020, 0x00000000 }, { 0x8024, 0x00000000 }, { 0x8028,
0x00000030 }, { 0x802c, 0x0007ffff }, { 0x8030, 0x01ffffff }
, { 0x8034, 0x00000031 }, { 0x8038, 0x00000000 }, { 0x803c, 0x00000000
}, { 0x8048, 0x00000000 }, { 0x8054, 0x00000000 }, { 0x8058,
0x00000000 }, { 0x8080, 0x00000000 }, { 0x805c, 0x000fc78f }
, { 0x8084, 0x00000000 }, { 0x8088, 0x00000000 }, { 0x808c, 0x00000000
}, { 0x8090, 0x00000000 }, { 0x8094, 0x00000000 }, { 0x8098,
0x00000000 }, { 0x80c0, 0x2a82301a }, { 0x80c4, 0x05dc01e0 }
, { 0x80c8, 0x1f402710 }, { 0x80cc, 0x01f40000 }, { 0x80d0, 0x00001e1c
}, { 0x80d4, 0x0002aaaa }, { 0x80d8, 0x02005555 }, { 0x80dc,
0x00000000 }, { 0x80e0, 0xffffffff }, { 0x80e4, 0x0000ffff }
, { 0x80e8, 0x00000000 }, { 0x80ec, 0x00000000 }, { 0x80f0, 0x00000000
}, { 0x80f4, 0x00000000 }, { 0x80f8, 0x00000000 }, { 0x80fc,
0x00000088 }, { 0x8700, 0x00000000 }, { 0x8704, 0x0000008c }
, { 0x8708, 0x000000e4 }, { 0x870c, 0x000002d5 }, { 0x8710, 0x00000000
}, { 0x8714, 0x00000000 }, { 0x8718, 0x000000a0 }, { 0x871c,
0x000001c9 }, { 0x8720, 0x0000002c }, { 0x8724, 0x0000002c }
, { 0x8728, 0x00000030 }, { 0x872c, 0x0000003c }, { 0x8730, 0x0000002c
}, { 0x8734, 0x0000002c }, { 0x8738, 0x00000030 }, { 0x873c,
0x0000003c }, { 0x8740, 0x00000000 }, { 0x8744, 0x00000000 }
, { 0x8748, 0x00000000 }, { 0x874c, 0x00000000 }, { 0x8750, 0x00000000
}, { 0x8754, 0x00000000 }, { 0x8758, 0x00000000 }, { 0x875c,
0x00000000 }, { 0x8760, 0x000000d5 }, { 0x8764, 0x000000df }
, { 0x8768, 0x00000102 }, { 0x876c, 0x0000013a }, { 0x8770, 0x00000075
}, { 0x8774, 0x0000007f }, { 0x8778, 0x000000a2 }, { 0x877c,
0x00000000 }, { 0x8100, 0x00010002 }, { 0x8104, 0x00000001 }
, { 0x8108, 0x000000c0 }, { 0x810c, 0x00000000 }, { 0x8110, 0x00000168
}, { 0x8114, 0x00000000 }, { 0x87c0, 0x03020100 }, { 0x87c4,
0x07060504 }, { 0x87c8, 0x0b0a0908 }, { 0x87cc, 0x0f0e0d0c }
, { 0x87d0, 0x13121110 }, { 0x87d4, 0x17161514 }, { 0x87d8, 0x1b1a1918
}, { 0x87dc, 0x1f1e1d1c }, { 0x87e0, 0x03020100 }, { 0x87e4,
0x07060504 }, { 0x87e8, 0x0b0a0908 }, { 0x87ec, 0x0f0e0d0c }
, { 0x87f0, 0x13121110 }, { 0x87f4, 0x17161514 }, { 0x87f8, 0x1b1a1918
}, { 0x87fc, 0x1f1e1d1c }, { 0x980c, 0xad848e19 }, { 0x9810,
0x7d28e000 }, { 0x9814, 0x9c0a9f6b }, { 0x981c, 0x00000000 }
, { 0x9840, 0x206a017a }, { 0x9854, 0x00000859 }, { 0x9900, 0x00000000
}, { 0x9904, 0x00000000 }, { 0x9908, 0x00000000 }, { 0x990c,
0x00800000 }, { 0x9910, 0x00000001 }, { 0x991c, 0x00000c80 }
, { 0x9920, 0x05100000 }, { 0x9928, 0x00000001 }, { 0x992c, 0x00000004
}, { 0x9934, 0x1e1f2022 }, { 0x9938, 0x0a0b0c0d }, { 0x993c,
0x0000003f }, { 0x9948, 0x9280b212 }, { 0x9954, 0x5d50e188 }
, { 0x995c, 0x004b6a8e }, { 0x9968, 0x000003ce }, { 0x9970, 0x192fb515
}, { 0x9978, 0x00000001 }, { 0x997c, 0x00000000 }, { 0xa210,
0x00806333 }, { 0xa214, 0x00106c10 }, { 0xa218, 0x009c4060 }
, { 0xa21c, 0x1483800a }, { 0xa220, 0x01831061 }, { 0xa224, 0x00000400
}, { 0xa22c, 0x00000000 }, { 0xa234, 0x20202020 }, { 0x9938,
0x20202020 }, { 0xa240, 0x38490a20 }, { 0xa244, 0x00007bb6 }
, { 0xa248, 0x0fff3ffc }, }
;
39static const struct ar5k_mode ar5212_mode[] = AR5K_AR5212_MODE{ { 0xa200, { 0x00000008, 0x00000008, 0x0000000b, 0x0000000e,
0x0000000e } }, { 0x9800, { 0x00000007, 0x00000007, 0x00000007
, 0x00000007, 0x00000007 } }, { 0x1040, { 0x002ffc0f, 0x002ffc0f
, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x1044, { 0x002ffc0f
, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x1048
, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f
} }, { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f
, 0x002ffc0f } }, { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f
, 0x002ffc0f, 0x002ffc0f } }, { 0x1054, { 0x002ffc0f, 0x002ffc0f
, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x1058, { 0x002ffc0f
, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x105c
, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f
} }, { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f
, 0x002ffc0f } }, { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f
, 0x002ffc0f, 0x002ffc0f } }, { 0x1030, { 0x00000230, 0x000001e0
, 0x000000b0, 0x00000160, 0x000001e0 } }, { 0x1070, { 0x00000168
, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, { 0x10b0
, { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180
} }, { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0
, 0x00014068 } }, { 0x8014, { 0x03e803e8, 0x06e006e0, 0x04200420
, 0x08400840, 0x06e006e0 } }, { 0x9804, { 0x00000000, 0x00000003
, 0x00000000, 0x00000000, 0x00000003 } }, { 0x9820, { 0x02020200
, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, { 0x9824
, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e
} }, { 0x9844, { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2
, 0x13721c25 } }, { 0x9860, { 0x00009d10, 0x00009d10, 0x00009d18
, 0x00009d18, 0x00009d18 } }, { 0x9864, { 0x0001ce00, 0x0001ce00
, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, { 0x9868, { 0x409a4190
, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, { 0x9918
, { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8
} }, { 0x9924, { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05
, 0x10058a05 } }, { 0xa230, { 0x00000000, 0x00000000, 0x00000000
, 0x00000108, 0x00000000 } },}
;
40static const struct ar5k_mode ar5212_ar5111_mode[] = AR5K_AR5212_AR5111_MODE{ { 0xa200, { 0x00000000, 0x00000000, 0x00000003, 0x00000006,
0x00000006 } }, { 0x0030, { 0x00008015, 0x00008015, 0x00008015
, 0x00008015, 0x00008015 } }, { 0x801c, { 0x128d8fa7, 0x09880fcf
, 0x04e00f95, 0x12e00fab, 0x09880fcf } }, { 0x9828, { 0x0a020001
, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, { 0x9834
, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e
} }, { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b
, 0x0000000b } }, { 0x9848, { 0x0018da5a, 0x0018da5a, 0x0018ca69
, 0x0018ca69, 0x0018ca69 } }, { 0x9850, { 0x0de8b4e0, 0x0de8b4e0
, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, { 0x9858, { 0x7e800d2e
, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, { 0x985c
, { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e
} }, { 0x986c, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080
, 0x050cb080 } }, { 0x9914, { 0x00002710, 0x00002710, 0x0000157c
, 0x00002af8, 0x00002710 } }, { 0x9944, { 0xf7b81020, 0xf7b81020
, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } }, { 0xa20c, { 0x642c416a
, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } }, { 0xa21c
, { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a
} }, { 0x1230, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0x9808, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x982c, { 0x00022ffe, 0x00022ffe
, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, { 0x983c, { 0x00020100
, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } }, { 0x984c
, { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c
} }, { 0x9930, { 0x00004883, 0x00004883, 0x00004883, 0x00004883
, 0x00004883 } }, { 0x9940, { 0x00000004, 0x00000004, 0x00000004
, 0x00000004, 0x00000004 } }, { 0x9958, { 0x000000ff, 0x000000ff
, 0x000000ff, 0x000000ff, 0x000000ff } }, { 0x9974, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x99f8
, { 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0x00000018
} }, { 0xa204, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0xa208, { 0xd03e6788, 0xd03e6788, 0xd03e6788
, 0xd03e6788, 0xd03e6788 } }, { 0xa23c, { 0x13c889af, 0x13c889af
, 0x13c889af, 0x13c889af, 0x13c889af } },}
;
41static const struct ar5k_mode ar5212_ar5112_mode[] = AR5K_AR5212_AR5112_MODE{ { 0x0030, { 0x00008015, 0x00008015, 0x00008015, 0x00008015,
0x00008015 } }, { 0x801c, { 0x128d93a7, 0x098813cf, 0x04e01395
, 0x12e013ab, 0x098813cf } }, { 0x9828, { 0x0a020001, 0x0a020001
, 0x05020100, 0x0a020001, 0x0a020001 } }, { 0x9834, { 0x00000e0e
, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x9838
, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b
} }, { 0x9848, { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75
, 0x0018ca75 } }, { 0x9850, { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0
, 0x0de8b4e0, 0x0de8b4e0 } }, { 0x9858, { 0x7e800d2e, 0x7e800d2e
, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } }, { 0x985c, { 0x3137665e
, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, { 0x986c
, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081
} }, { 0x9914, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898
, 0x000007d0 } }, { 0x9944, { 0xf7b81020, 0xf7b81020, 0xf7b80d10
, 0xf7b81010, 0xf7b81010 } }, { 0xa204, { 0x00000000, 0x00000000
, 0x00000008, 0x00000008, 0x00000008 } }, { 0xa208, { 0xd6be6788
, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xa20c
, { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160
} }, { 0xa21c, { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a
, 0x1883800a } }, { 0x1230, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x9808, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0x982c, { 0x00022ffe
, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, { 0x983c
, { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100
} }, { 0x984c, { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c
, 0x1284613c } }, { 0x9930, { 0x00004882, 0x00004882, 0x00004882
, 0x00004882, 0x00004882 } }, { 0x9940, { 0x00000004, 0x00000004
, 0x00000004, 0x00000004, 0x00000004 } }, { 0x9958, { 0x000000ff
, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, { 0x9974
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0xa228, { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5
, 0x000001b5 } }, { 0xa23c, { 0x13c889af, 0x13c889af, 0x13c889af
, 0x13c889af, 0x13c889af } },}
;
42static const struct ar5k_mode ar5413_mode[] = AR5K_AR5413_MODE{ { 0x0030, { 0x00000015, 0x00000015, 0x00000015, 0x00000015,
0x00000015 } }, { 0x801c, { 0x128d93a7, 0x098813cf, 0x04e01395
, 0x12e013ab, 0x098813cf } }, { 0x9828, { 0x0a020001, 0x0a020001
, 0x05020100, 0x0a020001, 0x0a020001 } }, { 0x9834, { 0x00000e0e
, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x9838
, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b
} }, { 0x9848, { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63
, 0x001a1a63 } }, { 0x9850, { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da
, 0x0c98b0da, 0x0c98b0da } }, { 0x9858, { 0x7ec80d2e, 0x7ec80d2e
, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, { 0x985c, { 0x3139605e
, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, { 0x986c
, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081
} }, { 0x9914, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898
, 0x000007d0 } }, { 0x9944, { 0xf7b81000, 0xf7b81000, 0xf7b80d00
, 0xf7b81000, 0xf7b81000 } }, { 0xa204, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa208, { 0xd6be6788
, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xa20c
, { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120
} }, { 0xa21c, { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a
, 0x1883800a } }, { 0xa300, { 0x18010000, 0x18010000, 0x18010000
, 0x18010000, 0x18010000 } }, { 0xa304, { 0x30032602, 0x30032602
, 0x30032602, 0x30032602, 0x30032602 } }, { 0xa308, { 0x48073e06
, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } }, { 0xa30c
, { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a
} }, { 0xa310, { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f
, 0x641a600f } }, { 0xa314, { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b
, 0x784f6e1b, 0x784f6e1b } }, { 0xa318, { 0x868f7c5a, 0x868f7c5a
, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, { 0xa31c, { 0x90cf865b
, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, { 0xa320
, { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f
} }, { 0xa324, { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f
, 0xa3cf9f8f } }, { 0xa328, { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f
, 0xb35faf1f, 0xb35faf1f } }, { 0xa32c, { 0xbddfb99f, 0xbddfb99f
, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } }, { 0xa330, { 0xcb7fc53f
, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } }, { 0xa334
, { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf
} }, { 0x1230, { 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0
, 0x000003e0 } }, { 0x4068, { 0x00000010, 0x00000010, 0x00000010
, 0x00000010, 0x00000010 } }, { 0x8060, { 0x0000000f, 0x0000000f
, 0x0000000f, 0x0000000f, 0x0000000f } }, { 0x809c, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x80a0
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0x8118, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0x811c, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x8120, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8124, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8128
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0x812c, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0x8130, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x8134, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8138, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x813c
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0x8140, { 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9
, 0x800003f9 } }, { 0x8144, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x9808, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0x982c, { 0x0000a000
, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0x983c
, { 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0x00200400
} }, { 0x984c, { 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c
, 0x1284233c } }, { 0x9870, { 0x0000001f, 0x0000001f, 0x0000001f
, 0x0000001f, 0x0000001f } }, { 0x9874, { 0x00000080, 0x00000080
, 0x00000080, 0x00000080, 0x00000080 } }, { 0x9878, { 0x0000000e
, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, { 0x9958
, { 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff
} }, { 0x9980, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0x9984, { 0x02800000, 0x02800000, 0x02800000
, 0x02800000, 0x02800000 } }, { 0x99a0, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0x99e0, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x99e4
, { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa
} }, { 0x99e8, { 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478
, 0x3c466478 } }, { 0x99ec, { 0x000000aa, 0x000000aa, 0x000000aa
, 0x000000aa, 0x000000aa } }, { 0x99f0, { 0x0000000c, 0x0000000c
, 0x0000000c, 0x0000000c, 0x0000000c } }, { 0x99f4, { 0x000000ff
, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, { 0x99f8
, { 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000014
} }, { 0xa228, { 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5
, 0x000009b5 } }, { 0xa23c, { 0x93c889af, 0x93c889af, 0x93c889af
, 0x93c889af, 0x93c889af } }, { 0xa24c, { 0x00000001, 0x00000001
, 0x00000001, 0x00000001, 0x00000001 } }, { 0xa250, { 0x0000a000
, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0xa254
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0xa258, { 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380
, 0x0cc75380 } }, { 0xa25c, { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01
, 0x0f0f0f01, 0x0f0f0f01 } }, { 0xa260, { 0x5f690f01, 0x5f690f01
, 0x5f690f01, 0x5f690f01, 0x5f690f01 } }, { 0xa264, { 0x00418a11
, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11 } }, { 0xa268
, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
} }, { 0xa26c, { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a
, 0x0c30c16a } }, { 0xa270, { 0x00820820, 0x00820820, 0x00820820
, 0x00820820, 0x00820820 } }, { 0xa274, { 0x081b7caa, 0x081b7caa
, 0x081b7caa, 0x081b7caa, 0x081b7caa } }, { 0xa278, { 0x1ce739ce
, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } }, { 0xa27c
, { 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce
} }, { 0xa338, { 0x00000000, 0x00000000, 0x00000000, 0x00000000
, 0x00000000 } }, { 0xa33c, { 0x00000000, 0x00000000, 0x00000000
, 0x00000000, 0x00000000 } }, { 0xa340, { 0x00000000, 0x00000000
, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa344, { 0x00000000
, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa348
, { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff
} }, { 0xa34c, { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff
, 0x3fffffff } }, { 0xa350, { 0x3fffffff, 0x3fffffff, 0x3fffffff
, 0x3fffffff, 0x3fffffff } }, { 0xa354, { 0x0003ffff, 0x0003ffff
, 0x0003ffff, 0x0003ffff, 0x0003ffff } }, { 0xa358, { 0x79a8aa1f
, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } }, { 0xa35c
, { 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f
} }, { 0xa360, { 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207
, 0x0f282207 } }, { 0xa364, { 0x17601685, 0x17601685, 0x17601685
, 0x17601685, 0x17601685 } }, { 0xa368, { 0x1f801104, 0x1f801104
, 0x1f801104, 0x1f801104, 0x1f801104 } }, { 0xa36c, { 0x37a00c03
, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03 } }, { 0xa370
, { 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883
} }, { 0xa374, { 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803
, 0x57c00803 } }, { 0xa378, { 0x5fd80682, 0x5fd80682, 0x5fd80682
, 0x5fd80682, 0x5fd80682 } }, { 0xa37c, { 0x7fe00482, 0x7fe00482
, 0x7fe00482, 0x7fe00482, 0x7fe00482 } }, { 0xa380, { 0x7f3c7bba
, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } }, { 0xa384
, { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0
} },}
;
43static const struct ar5k_mode ar2413_mode[] = AR5K_AR2413_MODE{ { 0x0030, { 0, 0, 0x00000015, 0x00000015, 0x00000015 } }, {
0x801c, { 0, 0, 0x04e01395, 0x12e013ab, 0x098813cf } }, { 0x9828
, { 0, 0, 0x05020000, 0x0a020001, 0x0a020001 } }, { 0x9834, {
0, 0, 0x00000e00, 0x00000e00, 0x00000e00 } }, { 0x9838, { 0,
0, 0x0000000a, 0x0000000a, 0x0000000a } }, { 0x9848, { 0, 0,
0x001a6a64, 0x001a6a64, 0x001a6a64 } }, { 0x9850, { 0, 0, 0x0de8b0da
, 0x0c98b0da, 0x0c98b0da } }, { 0x9858, { 0, 0, 0x7ee80d2e, 0x7ec80d2e
, 0x7ec80d2e } }, { 0x985c, { 0, 0, 0x3137665e, 0x3139605e, 0x3139605e
} }, { 0x986c, { 0, 0, 0x050cb081, 0x050cb081, 0x050cb081 } }
, { 0x9914, { 0, 0, 0x0000044c, 0x00000898, 0x000007d0 } }, {
0x9944, { 0, 0, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, { 0xa204
, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa208, {
0, 0, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xa20c, { 0,
0, 0x0042c140, 0x0042c140, 0x0042c140 } }, { 0xa21c, { 0, 0,
0x1863800a, 0x1883800a, 0x1883800a } }, { 0x1230, { 0, 0, 0x000003e0
, 0x000003e0, 0x000003e0 } }, { 0x8060, { 0, 0, 0x0000000f, 0x0000000f
, 0x0000000f } }, { 0x8118, { 0, 0, 0x00000000, 0x00000000, 0x00000000
} }, { 0x811c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }
, { 0x8120, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, {
0x8124, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8128
, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0x812c, {
0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8130, { 0,
0, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8134, { 0, 0,
0x00000000, 0x00000000, 0x00000000 } }, { 0x8138, { 0, 0, 0x00000000
, 0x00000000, 0x00000000 } }, { 0x813c, { 0, 0, 0x00000000, 0x00000000
, 0x00000000 } }, { 0x8140, { 0, 0, 0x800000a8, 0x800000a8, 0x800000a8
} }, { 0x8144, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }
, { 0x9808, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, {
0x982c, { 0, 0, 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0x983c
, { 0, 0, 0x00200400, 0x00200400, 0x00200400 } }, { 0x984c, {
0, 0, 0x1284233c, 0x1284233c, 0x1284233c } }, { 0x9870, { 0,
0, 0x0000001f, 0x0000001f, 0x0000001f } }, { 0x9874, { 0, 0,
0x00000080, 0x00000080, 0x00000080 } }, { 0x9878, { 0, 0, 0x0000000e
, 0x0000000e, 0x0000000e } }, { 0x9958, { 0, 0, 0x000000ff, 0x000000ff
, 0x000000ff } }, { 0x9980, { 0, 0, 0x00000000, 0x00000000, 0x00000000
} }, { 0x9984, { 0, 0, 0x02800000, 0x02800000, 0x02800000 } }
, { 0x99a0, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, {
0x99e0, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0x99e4
, { 0, 0, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } }, { 0x99e8, {
0, 0, 0x3c466478, 0x3c466478, 0x3c466478 } }, { 0x99ec, { 0,
0, 0x000000aa, 0x000000aa, 0x000000aa } }, { 0x99f0, { 0, 0,
0x0000000c, 0x0000000c, 0x0000000c } }, { 0x99f4, { 0, 0, 0x000000ff
, 0x000000ff, 0x000000ff } }, { 0x99f8, { 0, 0, 0x00000014, 0x00000014
, 0x00000014 } }, { 0xa228, { 0, 0, 0x000009b5, 0x000009b5, 0x000009b5
} }, { 0xa23c, { 0, 0, 0x93c889af, 0x93c889af, 0x93c889af } }
, { 0xa24c, { 0, 0, 0x00000001, 0x00000001, 0x00000001 } }, {
0xa250, { 0, 0, 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0xa254
, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa258, {
0, 0, 0x0cc75380, 0x0cc75380, 0x0cc75380 } }, { 0xa25c, { 0,
0, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } }, { 0xa260, { 0, 0,
0x5f690f01, 0x5f690f01, 0x5f690f01 } }, { 0xa264, { 0, 0, 0x00418a11
, 0x00418a11, 0x00418a11 } }, { 0xa268, { 0, 0, 0x00000000, 0x00000000
, 0x00000000 } }, { 0xa26c, { 0, 0, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a
} }, { 0xa270, { 0, 0, 0x00820820, 0x00820820, 0x00820820 } }
, { 0xa274, { 0, 0, 0x001b7caa, 0x001b7caa, 0x001b7caa } }, {
0xa278, { 0, 0, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } }, { 0xa27c
, { 0, 0, 0x051701ce, 0x051701ce, 0x051701ce } }, { 0xa300, {
0, 0, 0x18010000, 0x18010000, 0x18010000 } }, { 0xa304, { 0,
0, 0x30032602, 0x30032602, 0x30032602 } }, { 0xa308, { 0, 0,
0x48073e06, 0x48073e06, 0x48073e06 } }, { 0xa30c, { 0, 0, 0x560b4c0a
, 0x560b4c0a, 0x560b4c0a } }, { 0xa310, { 0, 0, 0x641a600f, 0x641a600f
, 0x641a600f } }, { 0xa314, { 0, 0, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b
} }, { 0xa318, { 0, 0, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }
, { 0xa31c, { 0, 0, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, {
0xa320, { 0, 0, 0x9d4f970f, 0x9d4f970f, 0x9d4f970f } }, { 0xa324
, { 0, 0, 0xa5cfa18f, 0xa5cfa18f, 0xa5cfa18f } }, { 0xa328, {
0, 0, 0xb55faf1f, 0xb55faf1f, 0xb55faf1f } }, { 0xa32c, { 0,
0, 0xbddfb99f, 0xbddfb99f, 0xbddfb99f } }, { 0xa330, { 0, 0,
0xcd7fc73f, 0xcd7fc73f, 0xcd7fc73f } }, { 0xa334, { 0, 0, 0xd5ffd1bf
, 0xd5ffd1bf, 0xd5ffd1bf } }, { 0xa338, { 0, 0, 0x00000000, 0x00000000
, 0x00000000 } }, { 0xa33c, { 0, 0, 0x00000000, 0x00000000, 0x00000000
} }, { 0xa340, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }
, { 0xa344, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, {
0xa348, { 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff } }, { 0xa34c
, { 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff } }, { 0xa350, {
0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff } }, { 0xa354, { 0,
0, 0x0003ffff, 0x0003ffff, 0x0003ffff } }, { 0xa358, { 0, 0,
0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } }, { 0xa35c, { 0, 0, 0x066c420f
, 0x066c420f, 0x066c420f } }, { 0xa360, { 0, 0, 0x0f282207, 0x0f282207
, 0x0f282207 } }, { 0xa364, { 0, 0, 0x17601685, 0x17601685, 0x17601685
} }, { 0xa368, { 0, 0, 0x1f801104, 0x1f801104, 0x1f801104 } }
, { 0xa36c, { 0, 0, 0x37a00c03, 0x37a00c03, 0x37a00c03 } }, {
0xa370, { 0, 0, 0x3fc40883, 0x3fc40883, 0x3fc40883 } }, { 0xa374
, { 0, 0, 0x57c00803, 0x57c00803, 0x57c00803 } }, { 0xa378, {
0, 0, 0x5fd80682, 0x5fd80682, 0x5fd80682 } }, { 0xa37c, { 0,
0, 0x7fe00482, 0x7fe00482, 0x7fe00482 } }, { 0xa380, { 0, 0,
0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } }, { 0xa384, { 0, 0, 0xf3307ff0
, 0xf3307ff0, 0xf3307ff0 } },}
;
44static const struct ar5k_mode ar2425_mode[] = AR5K_AR2425_MODE{ { 0x0030, { 0, 0, 0, 0x00000015, 0x00000015 } }, { 0x801c, {
0, 0, 0, 0x12e013ab, 0x098813cf } }, { 0x9804, { 0, 0, 0, 0x00000000
, 0x00000003 } }, { 0x9828, { 0, 0, 0, 0x0a020001, 0x0a020001
} }, { 0x9834, { 0, 0, 0, 0x00000e0e, 0x00000e0e } }, { 0x9838
, { 0, 0, 0, 0x0000000b, 0x0000000b } }, { 0x9844, { 0, 0, 0,
0x13721422, 0x13721422 } }, { 0x9848, { 0, 0, 0, 0x00199a65,
0x00199a65 } }, { 0x9850, { 0, 0, 0, 0x0c98b0da, 0x0c98b0da }
}, { 0x9858, { 0, 0, 0, 0x7ec80d2e, 0x7ec80d2e } }, { 0x985c
, { 0, 0, 0, 0x3139605e, 0x3139605e } }, { 0x986c, { 0, 0, 0,
0x050cb081, 0x050cb081 } }, { 0x9914, { 0, 0, 0, 0x00000898,
0x000007d0 } }, { 0x9944, { 0, 0, 0, 0xf7b81000, 0xf7b81000 }
}, { 0xa204, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0xa208
, { 0, 0, 0, 0xd03e6788, 0xd03e6788 } }, { 0xa20c, { 0, 0, 0,
0x0052c140, 0x0052c140 } }, { 0xa21c, { 0, 0, 0, 0x1883800a,
0x1883800a } }, { 0xa324, { 0, 0, 0, 0xa7cfa7cf, 0xa7cfa7cf }
}, { 0xa328, { 0, 0, 0, 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa32c
, { 0, 0, 0, 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa330, { 0, 0, 0,
0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa334, { 0, 0, 0, 0xa7cfa7cf,
0xa7cfa7cf } }, { 0x1230, { 0, 0, 0, 0x000003e0, 0x000003e0 }
}, { 0x8060, { 0, 0, 0, 0x0000000f, 0x0000000f } }, { 0x809c
, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x80a0, { 0, 0, 0,
0x00000000, 0x00000000 } }, { 0x8118, { 0, 0, 0, 0x00000000,
0x00000000 } }, { 0x811c, { 0, 0, 0, 0x00000000, 0x00000000 }
}, { 0x8120, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x8124
, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x8128, { 0, 0, 0,
0x00000000, 0x00000000 } }, { 0x812c, { 0, 0, 0, 0x00000000,
0x00000000 } }, { 0x8130, { 0, 0, 0, 0x00000000, 0x00000000 }
}, { 0x8134, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x8138
, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x813c, { 0, 0, 0,
0x00000000, 0x00000000 } }, { 0x8140, { 0, 0, 0, 0x800003f9,
0x800003f9 } }, { 0x8144, { 0, 0, 0, 0x00000000, 0x00000000 }
}, { 0x9808, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x982c
, { 0, 0, 0, 0x0000a000, 0x0000a000 } }, { 0x983c, { 0, 0, 0,
0x00200400, 0x00200400 } }, { 0x984c, { 0, 0, 0, 0x1284233c,
0x1284233c } }, { 0x9870, { 0, 0, 0, 0x0000001f, 0x0000001f }
}, { 0x9874, { 0, 0, 0, 0x00000080, 0x00000080 } }, { 0x9878
, { 0, 0, 0, 0x0000000e, 0x0000000e } }, { 0x9958, { 0, 0, 0,
0x00081fff, 0x00081fff } }, { 0x9980, { 0, 0, 0, 0x00000000,
0x00000000 } }, { 0x9984, { 0, 0, 0, 0x02800000, 0x02800000 }
}, { 0x99a0, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0x99dc
, { 0, 0, 0, 0xfebadbe8, 0xfebadbe8 } }, { 0x99e0, { 0, 0, 0,
0x00000000, 0x00000000 } }, { 0x99e4, { 0, 0, 0, 0xaaaaaaaa,
0xaaaaaaaa } }, { 0x99e8, { 0, 0, 0, 0x3c466478, 0x3c466478 }
}, { 0x99ec, { 0, 0, 0, 0x000000aa, 0x000000aa } }, { 0x99f0
, { 0, 0, 0, 0x0000000c, 0x0000000c } }, { 0x99f4, { 0, 0, 0,
0x000000ff, 0x000000ff } }, { 0x99f8, { 0, 0, 0, 0x00000014,
0x00000014 } }, { 0xa228, { 0, 0, 0, 0x000009b5, 0x000009b5 }
}, { 0xa234, { 0, 0, 0, 0x20202020, 0x20202020 } }, { 0xa238
, { 0, 0, 0, 0x20202020, 0x20202020 } }, { 0xa23c, { 0, 0, 0,
0x93c889af, 0x93c889af } }, { 0xa24c, { 0, 0, 0, 0x00000001,
0x00000001 } }, { 0xa250, { 0, 0, 0, 0x0000a000, 0x0000a000 }
}, { 0xa254, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0xa258
, { 0, 0, 0, 0x0cc75380, 0x0cc75380 } }, { 0xa25c, { 0, 0, 0,
0x0f0f0f01, 0x0f0f0f01 } }, { 0xa260, { 0, 0, 0, 0x5f690f01,
0x5f690f01 } }, { 0xa264, { 0, 0, 0, 0x00418a11, 0x00418a11 }
}, { 0xa268, { 0, 0, 0, 0x00000000, 0x00000000 } }, { 0xa26c
, { 0, 0, 0, 0x0c30c166, 0x0c30c166 } }, { 0xa270, { 0, 0, 0,
0x00820820, 0x00820820 } }, { 0xa274, { 0, 0, 0, 0x081a3caa,
0x081a3caa } }, { 0xa278, { 0, 0, 0, 0x1ce739ce, 0x1ce739ce }
}, { 0xa27c, { 0, 0, 0, 0x051701ce, 0x051701ce } }, { 0xa300
, { 0, 0, 0, 0x16010000, 0x16010000 } }, { 0xa304, { 0, 0, 0,
0x2c032402, 0x2c032402 } }, { 0xa308, { 0, 0, 0, 0x48433e42,
0x48433e42 } }, { 0xa30c, { 0, 0, 0, 0x5a0f500b, 0x5a0f500b }
}, { 0xa310, { 0, 0, 0, 0x6c4b624a, 0x6c4b624a } }, { 0xa314
, { 0, 0, 0, 0x7e8b748a, 0x7e8b748a } }, { 0xa318, { 0, 0, 0,
0x96cf8ccb, 0x96cf8ccb } }, { 0xa31c, { 0, 0, 0, 0xa34f9d0f,
0xa34f9d0f } }, { 0xa320, { 0, 0, 0, 0xa7cfa58f, 0xa7cfa58f }
}, { 0xa348, { 0, 0, 0, 0x3fffffff, 0x3fffffff } }, { 0xa34c
, { 0, 0, 0, 0x3fffffff, 0x3fffffff } }, { 0xa350, { 0, 0, 0,
0x3fffffff, 0x3fffffff } }, { 0xa354, { 0, 0, 0, 0x0003ffff,
0x0003ffff } }, { 0xa358, { 0, 0, 0, 0x79a8aa1f, 0x79a8aa1f }
}, { 0xa35c, { 0, 0, 0, 0x066c420f, 0x066c420f } }, { 0xa360
, { 0, 0, 0, 0x0f282207, 0x0f282207 } }, { 0xa364, { 0, 0, 0,
0x17601685, 0x17601685 } }, { 0xa368, { 0, 0, 0, 0x1f801104,
0x1f801104 } }, { 0xa36c, { 0, 0, 0, 0x37a00c03, 0x37a00c03 }
}, { 0xa370, { 0, 0, 0, 0x3fc40883, 0x3fc40883 } }, { 0xa374
, { 0, 0, 0, 0x57c00803, 0x57c00803 } }, { 0xa378, { 0, 0, 0,
0x5fd80682, 0x5fd80682 } }, { 0xa37c, { 0, 0, 0, 0x7fe00482,
0x7fe00482 } }, { 0xa380, { 0, 0, 0, 0x7f3c7bba, 0x7f3c7bba }
}, { 0xa384, { 0, 0, 0, 0xf3307ff0, 0xf3307ff0 } },}
;
45static const struct ar5k_ini ar5111_bbgain[] = AR5K_AR5111_INI_BBGAIN{ { 0x9b00, 0x00000000 }, { 0x9b04, 0x00000020 }, { 0x9b08, 0x00000010
}, { 0x9b0c, 0x00000030 }, { 0x9b10, 0x00000008 }, { 0x9b14,
0x00000028 }, { 0x9b18, 0x00000004 }, { 0x9b1c, 0x00000024 }
, { 0x9b20, 0x00000014 }, { 0x9b24, 0x00000034 }, { 0x9b28, 0x0000000c
}, { 0x9b2c, 0x0000002c }, { 0x9b30, 0x00000002 }, { 0x9b34,
0x00000022 }, { 0x9b38, 0x00000012 }, { 0x9b3c, 0x00000032 }
, { 0x9b40, 0x0000000a }, { 0x9b44, 0x0000002a }, { 0x9b48, 0x00000006
}, { 0x9b4c, 0x00000026 }, { 0x9b50, 0x00000016 }, { 0x9b54,
0x00000036 }, { 0x9b58, 0x0000000e }, { 0x9b5c, 0x0000002e }
, { 0x9b60, 0x00000001 }, { 0x9b64, 0x00000021 }, { 0x9b68, 0x00000011
}, { 0x9b6c, 0x00000031 }, { 0x9b70, 0x00000009 }, { 0x9b74,
0x00000029 }, { 0x9b78, 0x00000005 }, { 0x9b7c, 0x00000025 }
, { 0x9b80, 0x00000015 }, { 0x9b84, 0x00000035 }, { 0x9b88, 0x0000000d
}, { 0x9b8c, 0x0000002d }, { 0x9b90, 0x00000003 }, { 0x9b94,
0x00000023 }, { 0x9b98, 0x00000013 }, { 0x9b9c, 0x00000033 }
, { 0x9ba0, 0x0000000b }, { 0x9ba4, 0x0000002b }, { 0x9ba8, 0x0000002b
}, { 0x9bac, 0x0000002b }, { 0x9bb0, 0x0000002b }, { 0x9bb4,
0x0000002b }, { 0x9bb8, 0x0000002b }, { 0x9bbc, 0x0000002b }
, { 0x9bc0, 0x0000002b }, { 0x9bc4, 0x0000002b }, { 0x9bc8, 0x0000002b
}, { 0x9bcc, 0x0000002b }, { 0x9bd0, 0x0000002b }, { 0x9bd4,
0x0000002b }, { 0x9bd8, 0x0000002b }, { 0x9bdc, 0x0000002b }
, { 0x9be0, 0x0000002b }, { 0x9be4, 0x0000002b }, { 0x9be8, 0x0000002b
}, { 0x9bec, 0x0000002b }, { 0x9bf0, 0x0000002b }, { 0x9bf4,
0x0000002b }, { 0x9bf8, 0x00000002 }, { 0x9bfc, 0x00000016 }
, }
;
46static const struct ar5k_ini ar5112_bbgain[] = AR5K_AR5112_INI_BBGAIN{ { 0x9b00, 0x00000000 }, { 0x9b04, 0x00000001 }, { 0x9b08, 0x00000002
}, { 0x9b0c, 0x00000003 }, { 0x9b10, 0x00000004 }, { 0x9b14,
0x00000005 }, { 0x9b18, 0x00000008 }, { 0x9b1c, 0x00000009 }
, { 0x9b20, 0x0000000a }, { 0x9b24, 0x0000000b }, { 0x9b28, 0x0000000c
}, { 0x9b2c, 0x0000000d }, { 0x9b30, 0x00000010 }, { 0x9b34,
0x00000011 }, { 0x9b38, 0x00000012 }, { 0x9b3c, 0x00000013 }
, { 0x9b40, 0x00000014 }, { 0x9b44, 0x00000015 }, { 0x9b48, 0x00000018
}, { 0x9b4c, 0x00000019 }, { 0x9b50, 0x0000001a }, { 0x9b54,
0x0000001b }, { 0x9b58, 0x0000001c }, { 0x9b5c, 0x0000001d }
, { 0x9b60, 0x00000020 }, { 0x9b64, 0x00000021 }, { 0x9b68, 0x00000022
}, { 0x9b6c, 0x00000023 }, { 0x9b70, 0x00000024 }, { 0x9b74,
0x00000025 }, { 0x9b78, 0x00000028 }, { 0x9b7c, 0x00000029 }
, { 0x9b80, 0x0000002a }, { 0x9b84, 0x0000002b }, { 0x9b88, 0x0000002c
}, { 0x9b8c, 0x0000002d }, { 0x9b90, 0x00000030 }, { 0x9b94,
0x00000031 }, { 0x9b98, 0x00000032 }, { 0x9b9c, 0x00000033 }
, { 0x9ba0, 0x00000034 }, { 0x9ba4, 0x00000035 }, { 0x9ba8, 0x00000035
}, { 0x9bac, 0x00000035 }, { 0x9bb0, 0x00000035 }, { 0x9bb4,
0x00000035 }, { 0x9bb8, 0x00000035 }, { 0x9bbc, 0x00000035 }
, { 0x9bc0, 0x00000035 }, { 0x9bc4, 0x00000035 }, { 0x9bc8, 0x00000035
}, { 0x9bcc, 0x00000035 }, { 0x9bd0, 0x00000035 }, { 0x9bd4,
0x00000035 }, { 0x9bd8, 0x00000035 }, { 0x9bdc, 0x00000035 }
, { 0x9be0, 0x00000035 }, { 0x9be4, 0x00000035 }, { 0x9be8, 0x00000035
}, { 0x9bec, 0x00000035 }, { 0x9bf0, 0x00000035 }, { 0x9bf4,
0x00000035 }, { 0x9bf8, 0x00000010 }, { 0x9bfc, 0x0000001a }
, }
;
47static const struct ar5k_ini ar5212_pcie[] = AR5K_AR5212_PCIE{ { 0x4080, 0x9248fc00 }, { 0x4080, 0x24924924 }, { 0x4080, 0x28000039
}, { 0x4080, 0x53160824 }, { 0x4080, 0xe5980579 }, { 0x4080,
0x001defff }, { 0x4080, 0x1aaabe40 }, { 0x4080, 0xbe105554 }
, { 0x4080, 0x000e3007 }, { 0x4084, 0x00000000 } }
;
48
49AR5K_HAL_FUNCTIONS(extern, ar5k_ar5212,)extern const HAL_RATE_TABLE *( ar5k_ar5212_get_rate_table)(struct
ath_hal *, u_int mode); extern void ( ar5k_ar5212_detach)(struct
ath_hal *); extern HAL_BOOL ( ar5k_ar5212_reset)(struct ath_hal
*, HAL_OPMODE, HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS
*status); extern void ( ar5k_ar5212_set_opmode)(struct ath_hal
*); extern HAL_BOOL ( ar5k_ar5212_calibrate)(struct ath_hal*
, HAL_CHANNEL *); extern HAL_BOOL ( ar5k_ar5212_update_tx_triglevel
)(struct ath_hal*, HAL_BOOL level); extern int ( ar5k_ar5212_setup_tx_queue
)(struct ath_hal *, HAL_TX_QUEUE, const HAL_TXQ_INFO *); extern
HAL_BOOL ( ar5k_ar5212_setup_tx_queueprops)(struct ath_hal *
, int queue, const HAL_TXQ_INFO *); extern HAL_BOOL ( ar5k_ar5212_release_tx_queue
)(struct ath_hal *, u_int queue); extern HAL_BOOL ( ar5k_ar5212_reset_tx_queue
)(struct ath_hal *, u_int queue); extern u_int32_t ( ar5k_ar5212_get_tx_buf
)(struct ath_hal *, u_int queue); extern HAL_BOOL ( ar5k_ar5212_put_tx_buf
)(struct ath_hal *, u_int, u_int32_t phys_addr); extern HAL_BOOL
( ar5k_ar5212_tx_start)(struct ath_hal *, u_int queue); extern
HAL_BOOL ( ar5k_ar5212_stop_tx_dma)(struct ath_hal *, u_int queue
); extern HAL_BOOL ( ar5k_ar5212_setup_tx_desc)(struct ath_hal
*, struct ath_desc *, u_int packet_length, u_int header_length
, HAL_PKT_TYPE type, u_int txPower, u_int tx_rate0, u_int tx_tries0
, u_int key_index, u_int antenna_mode, u_int flags, u_int rtscts_rate
, u_int rtscts_duration); extern HAL_BOOL ( ar5k_ar5212_setup_xtx_desc
)(struct ath_hal *, struct ath_desc *, u_int tx_rate1, u_int tx_tries1
, u_int tx_rate2, u_int tx_tries2, u_int tx_rate3, u_int tx_tries3
); extern HAL_BOOL ( ar5k_ar5212_fill_tx_desc)(struct ath_hal
*, struct ath_desc *, u_int segLen, HAL_BOOL firstSeg, HAL_BOOL
lastSeg); extern HAL_STATUS ( ar5k_ar5212_proc_tx_desc)(struct
ath_hal *, struct ath_desc *); extern HAL_BOOL ( ar5k_ar5212_has_veol
)(struct ath_hal *); extern u_int32_t ( ar5k_ar5212_get_rx_buf
)(struct ath_hal*); extern void ( ar5k_ar5212_put_rx_buf)(struct
ath_hal*, u_int32_t rxdp); extern void ( ar5k_ar5212_start_rx
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_stop_rx_dma
)(struct ath_hal*); extern void ( ar5k_ar5212_start_rx_pcu)(struct
ath_hal*); extern void ( ar5k_ar5212_stop_pcu_recv)(struct ath_hal
*); extern void ( ar5k_ar5212_set_mcast_filter)(struct ath_hal
*, u_int32_t filter0, u_int32_t filter1); extern HAL_BOOL ( ar5k_ar5212_set_mcast_filterindex
)(struct ath_hal*, u_int32_t index); extern HAL_BOOL ( ar5k_ar5212_clear_mcast_filter_idx
)(struct ath_hal*, u_int32_t index); extern u_int32_t ( ar5k_ar5212_get_rx_filter
)(struct ath_hal*); extern void ( ar5k_ar5212_set_rx_filter)(
struct ath_hal*, u_int32_t); extern HAL_BOOL ( ar5k_ar5212_setup_rx_desc
)(struct ath_hal *, struct ath_desc *, u_int32_t size, u_int flags
); extern HAL_STATUS ( ar5k_ar5212_proc_rx_desc)(struct ath_hal
*, struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next
); extern void ( ar5k_ar5212_set_rx_signal)(struct ath_hal *)
; extern void ( ar5k_ar5212_dump_state)(struct ath_hal *); extern
HAL_BOOL ( ar5k_ar5212_get_diag_state)(struct ath_hal *, int
, void **, u_int *); extern void ( ar5k_ar5212_get_lladdr)(struct
ath_hal *, u_int8_t *); extern HAL_BOOL ( ar5k_ar5212_set_lladdr
)(struct ath_hal *, const u_int8_t*); extern HAL_BOOL ( ar5k_ar5212_set_regdomain
)(struct ath_hal*, u_int16_t, HAL_STATUS *); extern void ( ar5k_ar5212_set_ledstate
)(struct ath_hal*, HAL_LED_STATE); extern void ( ar5k_ar5212_set_associd
)(struct ath_hal*, const u_int8_t *bssid, u_int16_t assocId, u_int16_t
timOffset); extern HAL_BOOL ( ar5k_ar5212_set_gpio_output)(struct
ath_hal *, u_int32_t gpio); extern HAL_BOOL ( ar5k_ar5212_set_gpio_input
)(struct ath_hal *, u_int32_t gpio); extern u_int32_t ( ar5k_ar5212_get_gpio
)(struct ath_hal *, u_int32_t gpio); extern HAL_BOOL ( ar5k_ar5212_set_gpio
)(struct ath_hal *, u_int32_t gpio, u_int32_t val); extern void
( ar5k_ar5212_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t
); extern u_int32_t ( ar5k_ar5212_get_tsf32)(struct ath_hal*)
; extern u_int64_t ( ar5k_ar5212_get_tsf64)(struct ath_hal*);
extern void ( ar5k_ar5212_reset_tsf)(struct ath_hal*); extern
u_int16_t ( ar5k_ar5212_get_regdomain)(struct ath_hal*); extern
HAL_BOOL ( ar5k_ar5212_detect_card_present)(struct ath_hal*)
; extern void ( ar5k_ar5212_update_mib_counters)(struct ath_hal
*, HAL_MIB_STATS*); extern HAL_BOOL ( ar5k_ar5212_is_cipher_supported
)(struct ath_hal*, HAL_CIPHER); extern HAL_RFGAIN ( ar5k_ar5212_get_rf_gain
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_set_slot_time
)(struct ath_hal*, u_int); extern u_int ( ar5k_ar5212_get_slot_time
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_set_ack_timeout
)(struct ath_hal *, u_int); extern u_int ( ar5k_ar5212_get_ack_timeout
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_set_cts_timeout
)(struct ath_hal*, u_int); extern u_int ( ar5k_ar5212_get_cts_timeout
)(struct ath_hal*); extern u_int32_t ( ar5k_ar5212_get_keycache_size
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_reset_key)(
struct ath_hal*, u_int16_t); extern HAL_BOOL ( ar5k_ar5212_is_key_valid
)(struct ath_hal *, u_int16_t); extern HAL_BOOL ( ar5k_ar5212_set_key
)(struct ath_hal*, u_int16_t, const HAL_KEYVAL *, const u_int8_t
*, int); extern HAL_BOOL ( ar5k_ar5212_set_key_lladdr)(struct
ath_hal*, u_int16_t, const u_int8_t *); extern HAL_BOOL ( ar5k_ar5212_softcrypto
)(struct ath_hal *, HAL_BOOL); extern HAL_BOOL ( ar5k_ar5212_set_power
)(struct ath_hal*, HAL_POWER_MODE mode, HAL_BOOL set_chip, u_int16_t
sleep_duration); extern HAL_POWER_MODE ( ar5k_ar5212_get_power_mode
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_query_pspoll_support
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_init_pspoll
)(struct ath_hal*); extern HAL_BOOL ( ar5k_ar5212_enable_pspoll
)(struct ath_hal *, u_int8_t *, u_int16_t); extern HAL_BOOL (
ar5k_ar5212_disable_pspoll)(struct ath_hal *); extern void (
ar5k_ar5212_init_beacon)(struct ath_hal *, u_int32_t nexttbtt
, u_int32_t intval); extern void ( ar5k_ar5212_set_beacon_timers
)(struct ath_hal *, const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t
dtimCount, u_int32_t cfpCcount); extern void ( ar5k_ar5212_reset_beacon
)(struct ath_hal *); extern HAL_BOOL ( ar5k_ar5212_wait_for_beacon
)(struct ath_hal *, bus_addr_t); extern HAL_BOOL ( ar5k_ar5212_is_intr_pending
)(struct ath_hal *); extern HAL_BOOL ( ar5k_ar5212_get_isr)(struct
ath_hal *, u_int32_t *); extern u_int32_t ( ar5k_ar5212_get_intr
)(struct ath_hal *); extern HAL_INT ( ar5k_ar5212_set_intr)(struct
ath_hal *, HAL_INT); extern HAL_BOOL ( ar5k_ar5212_get_capabilities
)(struct ath_hal *); extern void ( ar5k_ar5212_radar_alert)(struct
ath_hal *, HAL_BOOL enable); extern HAL_BOOL ( ar5k_ar5212_eeprom_is_busy
)(struct ath_hal *); extern int ( ar5k_ar5212_eeprom_read)(struct
ath_hal *, u_int32_t offset, u_int16_t *data); extern int ( ar5k_ar5212_eeprom_write
)(struct ath_hal *, u_int32_t offset, u_int16_t data); extern
HAL_BOOL ( ar5k_ar5212_get_tx_queueprops)(struct ath_hal *, int
, HAL_TXQ_INFO *); extern u_int32_t ( ar5k_ar5212_num_tx_pending
)(struct ath_hal *, u_int); extern HAL_BOOL ( ar5k_ar5212_phy_disable
)(struct ath_hal *); extern HAL_BOOL ( ar5k_ar5212_set_txpower_limit
)(struct ath_hal *, u_int); extern void ( ar5k_ar5212_set_def_antenna
)(struct ath_hal *, u_int); extern u_int ( ar5k_ar5212_get_def_antenna
)(struct ath_hal *); extern HAL_BOOL ( ar5k_ar5212_set_bssid_mask
)(struct ath_hal *, const u_int8_t*);
;
50
51void
52ar5k_ar5212_fill(struct ath_hal *hal)
53{
54 hal->ah_magic = AR5K_AR5212_MAGIC0x0000145c;
55
56 /*
57 * Init/Exit functions
58 */
59 AR5K_HAL_FUNCTION(hal, ar5212, get_rate_table)(hal)->ah_get_rate_table = ar5k_ar5212_get_rate_table;
60 AR5K_HAL_FUNCTION(hal, ar5212, detach)(hal)->ah_detach = ar5k_ar5212_detach;
61
62 /*
63 * Reset functions
64 */
65 AR5K_HAL_FUNCTION(hal, ar5212, reset)(hal)->ah_reset = ar5k_ar5212_reset;
66 AR5K_HAL_FUNCTION(hal, ar5212, set_opmode)(hal)->ah_set_opmode = ar5k_ar5212_set_opmode;
67 AR5K_HAL_FUNCTION(hal, ar5212, calibrate)(hal)->ah_calibrate = ar5k_ar5212_calibrate;
68
69 /*
70 * TX functions
71 */
72 AR5K_HAL_FUNCTION(hal, ar5212, update_tx_triglevel)(hal)->ah_update_tx_triglevel = ar5k_ar5212_update_tx_triglevel;
73 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queue)(hal)->ah_setup_tx_queue = ar5k_ar5212_setup_tx_queue;
74 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queueprops)(hal)->ah_setup_tx_queueprops = ar5k_ar5212_setup_tx_queueprops;
75 AR5K_HAL_FUNCTION(hal, ar5212, release_tx_queue)(hal)->ah_release_tx_queue = ar5k_ar5212_release_tx_queue;
76 AR5K_HAL_FUNCTION(hal, ar5212, reset_tx_queue)(hal)->ah_reset_tx_queue = ar5k_ar5212_reset_tx_queue;
77 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_buf)(hal)->ah_get_tx_buf = ar5k_ar5212_get_tx_buf;
78 AR5K_HAL_FUNCTION(hal, ar5212, put_tx_buf)(hal)->ah_put_tx_buf = ar5k_ar5212_put_tx_buf;
79 AR5K_HAL_FUNCTION(hal, ar5212, tx_start)(hal)->ah_tx_start = ar5k_ar5212_tx_start;
80 AR5K_HAL_FUNCTION(hal, ar5212, stop_tx_dma)(hal)->ah_stop_tx_dma = ar5k_ar5212_stop_tx_dma;
81 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc)(hal)->ah_setup_tx_desc = ar5k_ar5212_setup_tx_desc;
82 AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc)(hal)->ah_setup_xtx_desc = ar5k_ar5212_setup_xtx_desc;
83 AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc)(hal)->ah_fill_tx_desc = ar5k_ar5212_fill_tx_desc;
84 AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc)(hal)->ah_proc_tx_desc = ar5k_ar5212_proc_tx_desc;
85 AR5K_HAL_FUNCTION(hal, ar5212, has_veol)(hal)->ah_has_veol = ar5k_ar5212_has_veol;
86
87 /*
88 * RX functions
89 */
90 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_buf)(hal)->ah_get_rx_buf = ar5k_ar5212_get_rx_buf;
91 AR5K_HAL_FUNCTION(hal, ar5212, put_rx_buf)(hal)->ah_put_rx_buf = ar5k_ar5212_put_rx_buf;
92 AR5K_HAL_FUNCTION(hal, ar5212, start_rx)(hal)->ah_start_rx = ar5k_ar5212_start_rx;
93 AR5K_HAL_FUNCTION(hal, ar5212, stop_rx_dma)(hal)->ah_stop_rx_dma = ar5k_ar5212_stop_rx_dma;
94 AR5K_HAL_FUNCTION(hal, ar5212, start_rx_pcu)(hal)->ah_start_rx_pcu = ar5k_ar5212_start_rx_pcu;
95 AR5K_HAL_FUNCTION(hal, ar5212, stop_pcu_recv)(hal)->ah_stop_pcu_recv = ar5k_ar5212_stop_pcu_recv;
96 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filter)(hal)->ah_set_mcast_filter = ar5k_ar5212_set_mcast_filter;
97 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filterindex)(hal)->ah_set_mcast_filterindex = ar5k_ar5212_set_mcast_filterindex;
98 AR5K_HAL_FUNCTION(hal, ar5212, clear_mcast_filter_idx)(hal)->ah_clear_mcast_filter_idx = ar5k_ar5212_clear_mcast_filter_idx;
99 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_filter)(hal)->ah_get_rx_filter = ar5k_ar5212_get_rx_filter;
100 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_filter)(hal)->ah_set_rx_filter = ar5k_ar5212_set_rx_filter;
101 AR5K_HAL_FUNCTION(hal, ar5212, setup_rx_desc)(hal)->ah_setup_rx_desc = ar5k_ar5212_setup_rx_desc;
102 AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc)(hal)->ah_proc_rx_desc = ar5k_ar5212_proc_rx_desc;
103 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_signal)(hal)->ah_set_rx_signal = ar5k_ar5212_set_rx_signal;
104
105 /*
106 * Misc functions
107 */
108 AR5K_HAL_FUNCTION(hal, ar5212, dump_state)(hal)->ah_dump_state = ar5k_ar5212_dump_state;
109 AR5K_HAL_FUNCTION(hal, ar5212, get_diag_state)(hal)->ah_get_diag_state = ar5k_ar5212_get_diag_state;
110 AR5K_HAL_FUNCTION(hal, ar5212, get_lladdr)(hal)->ah_get_lladdr = ar5k_ar5212_get_lladdr;
111 AR5K_HAL_FUNCTION(hal, ar5212, set_lladdr)(hal)->ah_set_lladdr = ar5k_ar5212_set_lladdr;
112 AR5K_HAL_FUNCTION(hal, ar5212, set_regdomain)(hal)->ah_set_regdomain = ar5k_ar5212_set_regdomain;
113 AR5K_HAL_FUNCTION(hal, ar5212, set_ledstate)(hal)->ah_set_ledstate = ar5k_ar5212_set_ledstate;
114 AR5K_HAL_FUNCTION(hal, ar5212, set_associd)(hal)->ah_set_associd = ar5k_ar5212_set_associd;
115 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_input)(hal)->ah_set_gpio_input = ar5k_ar5212_set_gpio_input;
116 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_output)(hal)->ah_set_gpio_output = ar5k_ar5212_set_gpio_output;
117 AR5K_HAL_FUNCTION(hal, ar5212, get_gpio)(hal)->ah_get_gpio = ar5k_ar5212_get_gpio;
118 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio)(hal)->ah_set_gpio = ar5k_ar5212_set_gpio;
119 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_intr)(hal)->ah_set_gpio_intr = ar5k_ar5212_set_gpio_intr;
120 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf32)(hal)->ah_get_tsf32 = ar5k_ar5212_get_tsf32;
121 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf64)(hal)->ah_get_tsf64 = ar5k_ar5212_get_tsf64;
122 AR5K_HAL_FUNCTION(hal, ar5212, reset_tsf)(hal)->ah_reset_tsf = ar5k_ar5212_reset_tsf;
123 AR5K_HAL_FUNCTION(hal, ar5212, get_regdomain)(hal)->ah_get_regdomain = ar5k_ar5212_get_regdomain;
124 AR5K_HAL_FUNCTION(hal, ar5212, detect_card_present)(hal)->ah_detect_card_present = ar5k_ar5212_detect_card_present;
125 AR5K_HAL_FUNCTION(hal, ar5212, update_mib_counters)(hal)->ah_update_mib_counters = ar5k_ar5212_update_mib_counters;
126 AR5K_HAL_FUNCTION(hal, ar5212, get_rf_gain)(hal)->ah_get_rf_gain = ar5k_ar5212_get_rf_gain;
127 AR5K_HAL_FUNCTION(hal, ar5212, set_slot_time)(hal)->ah_set_slot_time = ar5k_ar5212_set_slot_time;
128 AR5K_HAL_FUNCTION(hal, ar5212, get_slot_time)(hal)->ah_get_slot_time = ar5k_ar5212_get_slot_time;
129 AR5K_HAL_FUNCTION(hal, ar5212, set_ack_timeout)(hal)->ah_set_ack_timeout = ar5k_ar5212_set_ack_timeout;
130 AR5K_HAL_FUNCTION(hal, ar5212, get_ack_timeout)(hal)->ah_get_ack_timeout = ar5k_ar5212_get_ack_timeout;
131 AR5K_HAL_FUNCTION(hal, ar5212, set_cts_timeout)(hal)->ah_set_cts_timeout = ar5k_ar5212_set_cts_timeout;
132 AR5K_HAL_FUNCTION(hal, ar5212, get_cts_timeout)(hal)->ah_get_cts_timeout = ar5k_ar5212_get_cts_timeout;
133
134 /*
135 * Key table (WEP) functions
136 */
137 AR5K_HAL_FUNCTION(hal, ar5212, is_cipher_supported)(hal)->ah_is_cipher_supported = ar5k_ar5212_is_cipher_supported;
138 AR5K_HAL_FUNCTION(hal, ar5212, get_keycache_size)(hal)->ah_get_keycache_size = ar5k_ar5212_get_keycache_size;
139 AR5K_HAL_FUNCTION(hal, ar5212, reset_key)(hal)->ah_reset_key = ar5k_ar5212_reset_key;
140 AR5K_HAL_FUNCTION(hal, ar5212, is_key_valid)(hal)->ah_is_key_valid = ar5k_ar5212_is_key_valid;
141 AR5K_HAL_FUNCTION(hal, ar5212, set_key)(hal)->ah_set_key = ar5k_ar5212_set_key;
142 AR5K_HAL_FUNCTION(hal, ar5212, set_key_lladdr)(hal)->ah_set_key_lladdr = ar5k_ar5212_set_key_lladdr;
143 AR5K_HAL_FUNCTION(hal, ar5212, softcrypto)(hal)->ah_softcrypto = ar5k_ar5212_softcrypto;
144
145 /*
146 * Power management functions
147 */
148 AR5K_HAL_FUNCTION(hal, ar5212, set_power)(hal)->ah_set_power = ar5k_ar5212_set_power;
149 AR5K_HAL_FUNCTION(hal, ar5212, get_power_mode)(hal)->ah_get_power_mode = ar5k_ar5212_get_power_mode;
150 AR5K_HAL_FUNCTION(hal, ar5212, query_pspoll_support)(hal)->ah_query_pspoll_support = ar5k_ar5212_query_pspoll_support;
151 AR5K_HAL_FUNCTION(hal, ar5212, init_pspoll)(hal)->ah_init_pspoll = ar5k_ar5212_init_pspoll;
152 AR5K_HAL_FUNCTION(hal, ar5212, enable_pspoll)(hal)->ah_enable_pspoll = ar5k_ar5212_enable_pspoll;
153 AR5K_HAL_FUNCTION(hal, ar5212, disable_pspoll)(hal)->ah_disable_pspoll = ar5k_ar5212_disable_pspoll;
154
155 /*
156 * Beacon functions
157 */
158 AR5K_HAL_FUNCTION(hal, ar5212, init_beacon)(hal)->ah_init_beacon = ar5k_ar5212_init_beacon;
159 AR5K_HAL_FUNCTION(hal, ar5212, set_beacon_timers)(hal)->ah_set_beacon_timers = ar5k_ar5212_set_beacon_timers;
160 AR5K_HAL_FUNCTION(hal, ar5212, reset_beacon)(hal)->ah_reset_beacon = ar5k_ar5212_reset_beacon;
161 AR5K_HAL_FUNCTION(hal, ar5212, wait_for_beacon)(hal)->ah_wait_for_beacon = ar5k_ar5212_wait_for_beacon;
162
163 /*
164 * Interrupt functions
165 */
166 AR5K_HAL_FUNCTION(hal, ar5212, is_intr_pending)(hal)->ah_is_intr_pending = ar5k_ar5212_is_intr_pending;
167 AR5K_HAL_FUNCTION(hal, ar5212, get_isr)(hal)->ah_get_isr = ar5k_ar5212_get_isr;
168 AR5K_HAL_FUNCTION(hal, ar5212, get_intr)(hal)->ah_get_intr = ar5k_ar5212_get_intr;
169 AR5K_HAL_FUNCTION(hal, ar5212, set_intr)(hal)->ah_set_intr = ar5k_ar5212_set_intr;
170
171 /*
172 * Chipset functions (ar5k-specific, non-HAL)
173 */
174 AR5K_HAL_FUNCTION(hal, ar5212, get_capabilities)(hal)->ah_get_capabilities = ar5k_ar5212_get_capabilities;
175 AR5K_HAL_FUNCTION(hal, ar5212, radar_alert)(hal)->ah_radar_alert = ar5k_ar5212_radar_alert;
176
177 /*
178 * EEPROM access
179 */
180 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_is_busy)(hal)->ah_eeprom_is_busy = ar5k_ar5212_eeprom_is_busy;
181 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_read)(hal)->ah_eeprom_read = ar5k_ar5212_eeprom_read;
182 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_write)(hal)->ah_eeprom_write = ar5k_ar5212_eeprom_write;
183
184 /*
185 * Unused functions or functions not implemented
186 */
187 AR5K_HAL_FUNCTION(hal, ar5212, set_bssid_mask)(hal)->ah_set_bssid_mask = ar5k_ar5212_set_bssid_mask;
188 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_queueprops)(hal)->ah_get_tx_queueprops = ar5k_ar5212_get_tx_queueprops;
189 AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending)(hal)->ah_num_tx_pending = ar5k_ar5212_num_tx_pending;
190 AR5K_HAL_FUNCTION(hal, ar5212, phy_disable)(hal)->ah_phy_disable = ar5k_ar5212_phy_disable;
191 AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit)(hal)->ah_set_txpower_limit = ar5k_ar5212_set_txpower_limit;
192 AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna)(hal)->ah_set_def_antenna = ar5k_ar5212_set_def_antenna;
193 AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna)(hal)->ah_get_def_antenna = ar5k_ar5212_get_def_antenna;
194#ifdef notyet
195 AR5K_HAL_FUNCTION(hal, ar5212, set_capability)(hal)->ah_set_capability = ar5k_ar5212_set_capability;
196 AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event)(hal)->ah_proc_mib_event = ar5k_ar5212_proc_mib_event;
197 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue)(hal)->ah_get_tx_inter_queue = ar5k_ar5212_get_tx_inter_queue;
198#endif
199}
200
201struct ath_hal *
202ar5k_ar5212_attach(u_int16_t device, void *sc, bus_space_tag_t st,
203 bus_space_handle_t sh, int *status)
204{
205 struct ath_hal *hal = (struct ath_hal*) sc;
206 u_int8_t mac[IEEE80211_ADDR_LEN6];
207 u_int32_t srev;
208
209 ar5k_ar5212_fill(hal);
210
211 /* Bring device out of sleep and reset its units */
212 if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE( 0x0080 | 0x0400 )) != AH_TRUE)
213 return (NULL((void *)0));
214
215 /* Get MAC, PHY and RADIO revisions */
216 srev = AR5K_REG_READ(AR5K_AR5212_SREV)((hal->ah_st)->read_4((hal->ah_sh), ((0x4020))));
217 hal->ah_mac_srev = srev;
218 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5212_SREV_VER)(((uint32_t)(srev) & (0x000000ff)) >> 4);
219 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5212_SREV_REV)(((uint32_t)(srev) & (0x0000000f)) >> 0);
220 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID)((hal->ah_st)->read_4((hal->ah_sh), ((0x9818)))) &
221 0x00ffffffff;
222 hal->ah_radio_5ghz_revision =
223 ar5k_ar5212_radio_revision(hal, HAL_CHIP_5GHZ);
224 hal->ah_radio_2ghz_revision =
225 ar5k_ar5212_radio_revision(hal, HAL_CHIP_2GHZ);
226
227 /* Single chip radio */
228 if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
229 hal->ah_radio_2ghz_revision = 0;
230
231 /* Identify the chipset (this has to be done in an early step) */
232 hal->ah_version = AR5K_AR5212;
233 if (device == AR5K_VERSION_DEV) {
234 hal->ah_radio = AR5K_AR5413;
235 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR54240x00000012;
236 hal->ah_radio_5ghz_revision = hal->ah_radio_2ghz_revision =
237 AR5K_SREV_VER_AR54130xa4;
238 } else if (srev == AR5K_SREV_VER_AR24250xe2) {
239 hal->ah_radio = AR5K_AR2425;
240 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR51120x00000014;
241 hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_SC20xa2;
242 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_51120x30) {
243 hal->ah_radio = AR5K_AR5111;
244 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR51110x00000018;
245 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC00x56) {
246 hal->ah_radio = AR5K_AR5112;
247 if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A0x35)
248 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR51120x00000014;
249 else
250 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A0x0000000e;
251 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC10x63) {
252 hal->ah_radio = AR5K_AR2413;
253 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A0x0000000e;
254 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC20xa2) {
255 hal->ah_radio = AR5K_AR5413;
256 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A0x0000000e;
257 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_51330xc0 &&
258 srev < AR5K_SREV_VER_AR54240xa3) {
259 hal->ah_radio = AR5K_AR2413;
260 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A0x0000000e;
261 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_51330xc0) {
262 hal->ah_radio = AR5K_AR5413;
263 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR54240x00000012;
264 }
265 hal->ah_phy = AR5K_AR5212_PHY(0)(0x9800 + ((0) << 2));
266
267 if (hal->ah_pci_express == AH_TRUE) {
268 /* PCI-Express based devices need some extra initialization */
269 ar5k_write_ini(hal, ar5212_pcie, nitems(ar5212_pcie)(sizeof((ar5212_pcie)) / sizeof((ar5212_pcie)[0])), 0);
270 }
271
272 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN6);
273 ar5k_ar5212_set_associd(hal, mac, 0, 0);
274 ar5k_ar5212_get_lladdr(hal, mac);
275 ar5k_ar5212_set_opmode(hal);
276
277 return (hal);
278}
279
280HAL_BOOL
281ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val)
282{
283 HAL_BOOL ret = AH_FALSE;
284 u_int32_t mask = val ? val : ~0;
285
286 /* Read-and-clear */
287 AR5K_REG_READ(AR5K_AR5212_RXDP)((hal->ah_st)->read_4((hal->ah_sh), ((0x000c))));
288
289 /*
290 * Reset the device and wait until success
291 */
292 AR5K_REG_WRITE(AR5K_AR5212_RC, val)((hal->ah_st)->write_4((hal->ah_sh), ((0x4000)), ((val
))))
;
293
294 /* Wait at least 128 PCI clocks */
295 AR5K_DELAY(15)(*delay_func)(15);
296
297 val &=
298 AR5K_AR5212_RC_PCU0x00000001 | AR5K_AR5212_RC_BB0x00000002;
299
300 mask &=
301 AR5K_AR5212_RC_PCU0x00000001 | AR5K_AR5212_RC_BB0x00000002;
302
303 ret = ar5k_register_timeout(hal, AR5K_AR5212_RC0x4000, mask, val, AH_FALSE);
304
305 /*
306 * Reset configuration register
307 */
308 if ((val & AR5K_AR5212_RC_PCU0x00000001) == 0)
309 AR5K_REG_WRITE(AR5K_AR5212_CFG, AR5K_AR5212_INIT_CFG)((hal->ah_st)->write_4((hal->ah_sh), ((0x0014)), ((0x00000000
))))
;
310
311 return (ret);
312}
313
314HAL_BOOL
315ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
316{
317 u_int32_t turbo, mode, clock;
318
319 turbo = 0;
320 mode = 0;
321 clock = 0;
322
323 /*
324 * Get channel mode flags
325 */
326
327 if (hal->ah_radio >= AR5K_AR5112) {
328 mode = AR5K_AR5212_PHY_MODE_RAD_AR51128;
329 clock = AR5K_AR5212_PHY_PLL_AR51120x00000040;
330 } else {
331 mode = AR5K_AR5212_PHY_MODE_RAD_AR51110;
332 clock = AR5K_AR5212_PHY_PLL_AR51110x00000000;
333 }
334
335 if (flags & IEEE80211_CHAN_2GHZ0x0080) {
336 mode |= AR5K_AR5212_PHY_MODE_FREQ_2GHZ2;
337 clock |= AR5K_AR5212_PHY_PLL_44MHZ0x000000ab;
338 } else if (flags & IEEE80211_CHAN_5GHZ0x0100) {
339 mode |= AR5K_AR5212_PHY_MODE_FREQ_5GHZ0;
340 clock |= AR5K_AR5212_PHY_PLL_40MHZ0x000000aa;
341 } else {
342 AR5K_PRINT("invalid radio frequency mode\n")printf("%s: " "invalid radio frequency mode\n", __func__);
343 return (AH_FALSE);
344 }
345
346 if (flags & IEEE80211_CHAN_CCK0x0020) {
347 mode |= AR5K_AR5212_PHY_MODE_MOD_CCK1;
348 } else if (flags & IEEE80211_CHAN_OFDM0x0040) {
349 mode |= AR5K_AR5212_PHY_MODE_MOD_OFDM0;
350 } else if (flags & IEEE80211_CHAN_DYN0x0400) {
351 mode |= AR5K_AR5212_PHY_MODE_MOD_DYN0x00000004;
352 } else {
353 AR5K_PRINT("invalid radio frequency mode\n")printf("%s: " "invalid radio frequency mode\n", __func__);
354 return (AH_FALSE);
355 }
356
357 /*
358 * Reset and wakeup the device
359 */
360
361 /* ...reset chipset and PCI device (if not PCI-E) */
362 if (hal->ah_pci_express == AH_FALSE &&
363 ar5k_ar5212_nic_reset(hal, AR5K_AR5212_RC_CHIP( 0x00000001 | 0x00000002 | 0x00000010 )) == AH_FALSE) {
364 AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n")printf("%s: " "failed to reset the AR5212 + PCI chipset\n", __func__
)
;
365 return (AH_FALSE);
366 }
367
368 /* ...wakeup */
369 if (ar5k_ar5212_set_power(hal,
370 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) {
371 AR5K_PRINT("failed to resume the AR5212 (again)\n")printf("%s: " "failed to resume the AR5212 (again)\n", __func__
)
;
372 return (AH_FALSE);
373 }
374
375 /* ...final warm reset */
376 if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) {
377 AR5K_PRINT("failed to warm reset the AR5212\n")printf("%s: " "failed to warm reset the AR5212\n", __func__);
378 return (AH_FALSE);
379 }
380
381 /* ...set the PHY operating mode */
382 AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock)((hal->ah_st)->write_4((hal->ah_sh), ((0x987c)), ((clock
))))
;
383 AR5K_DELAY(300)(*delay_func)(300);
384
385 AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode)((hal->ah_st)->write_4((hal->ah_sh), ((0x0a200)), ((
mode))))
;
386 AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo)((hal->ah_st)->write_4((hal->ah_sh), ((0x9804)), ((turbo
))))
;
387
388 return (AH_TRUE);
389}
390
391u_int16_t
392ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
393{
394 int i;
395 u_int32_t srev;
396 u_int16_t ret;
397
398 /*
399 * Set the radio chip access register
400 */
401 switch (chip) {
402 case HAL_CHIP_2GHZ:
403 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0
) << 2)))), ((0x00004007))))
;
404 break;
405 case HAL_CHIP_5GHZ:
406 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0
) << 2)))), ((0x00000007))))
;
407 break;
408 default:
409 return (0);
410 }
411
412 AR5K_DELAY(2000)(*delay_func)(2000);
413
414 /* ...wait until PHY is ready and read the selected radio revision */
415 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x34
) << 2)))), ((0x00001c16))))
;
416
417 for (i = 0; i < 8; i++)
418 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x20
) << 2)))), ((0x00010000))))
;
419 srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100))((hal->ah_st)->read_4((hal->ah_sh), (((0x9800 + ((0x100
) << 2))))))
>> 24) & 0xff;
420
421 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
422
423 /* Reset to the 5GHz mode */
424 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0
) << 2)))), ((0x00000007))))
;
425
426 return (ret);
427}
428
429const HAL_RATE_TABLE *
430ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode)
431{
432 switch (mode) {
433 case HAL_MODE_11A:
434 return (&hal->ah_rt_11a);
435 case HAL_MODE_11B:
436 return (&hal->ah_rt_11b);
437 case HAL_MODE_11G:
438 case HAL_MODE_PUREG:
439 return (&hal->ah_rt_11g);
440 case HAL_MODE_XR:
441 return (&hal->ah_rt_xr);
442 default:
443 return (NULL((void *)0));
444 }
445
446 return (NULL((void *)0));
447}
448
449void
450ar5k_ar5212_detach(struct ath_hal *hal)
451{
452 if (hal->ah_rf_banks != NULL((void *)0))
453 free(hal->ah_rf_banks, M_DEVBUF2, 0);
454
455 /*
456 * Free HAL structure, assume interrupts are down
457 */
458 free(hal, M_DEVBUF2, 0);
459}
460
461HAL_BOOL
462ar5k_ar5212_phy_disable(struct ath_hal *hal)
463{
464 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x981c)), ((0x00000002
))))
;
465 return (AH_TRUE);
466}
467
468HAL_BOOL
469ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
470 HAL_BOOL chanchange, HAL_STATUS *status)
471{
472 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
473 u_int8_t mac[IEEE80211_ADDR_LEN6];
474 u_int32_t data, s_seq, s_ant, s_led[3], dmasize;
475 u_int i, mode, freq, ee_mode, ant[2];
476 const HAL_RATE_TABLE *rt;
477
478 /* Not used, keep for HAL compatibility */
479 *status = HAL_OK0;
480
481 /*
482 * Save some registers before a reset
483 */
484 if (chanchange == AH_TRUE) {
485 s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0))((hal->ah_st)->read_4((hal->ah_sh), (((((0) <<
2) + 0x1140)))))
;
486 s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA)((hal->ah_st)->read_4((hal->ah_sh), ((0x8058))));
487 } else {
488 s_seq = 0;
489 s_ant = 1;
490 }
491
492 s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG)((hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) &
493 AR5K_AR5212_PCICFG_LEDSTATE(0x00000060 | 0x000e0000 | 0x00700000 | 0x00800000);
494 s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR)((hal->ah_st)->read_4((hal->ah_sh), ((0x4014))));
495 s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO)((hal->ah_st)->read_4((hal->ah_sh), ((0x4018))));
496
497 if (chanchange == AH_TRUE && hal->ah_rf_banks != NULL((void *)0))
498 ar5k_ar5212_get_rf_gain(hal);
499
500 if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flagschannelFlags) == AH_FALSE)
501 return (AH_FALSE);
502
503 /*
504 * Initialize operating mode
505 */
506 hal->ah_op_mode = op_mode;
507
508 if ((channel->c_channel_flagschannelFlags & CHANNEL_A(0x0100 | 0x0040)) == CHANNEL_A(0x0100 | 0x0040)) {
509 mode = AR5K_INI_VAL_11A0;
510 freq = AR5K_INI_RFGAIN_5GHZ0;
511 ee_mode = AR5K_EEPROM_MODE_11A0;
512 } else if ((channel->c_channel_flagschannelFlags & CHANNEL_B(0x0080 | 0x0020)) == CHANNEL_B(0x0080 | 0x0020)) {
513 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) {
514 mode = AR5K_INI_VAL_11B2;
515 ee_mode = AR5K_EEPROM_MODE_11B1;
516 } else {
517 mode = AR5K_INI_VAL_11G3;
518 ee_mode = AR5K_EEPROM_MODE_11G2;
519 }
520 freq = AR5K_INI_RFGAIN_2GHZ1;
521 } else if ((channel->c_channel_flagschannelFlags & (CHANNEL_G(0x0080 | 0x0400) | CHANNEL_PUREG(0x0080 | 0x0040))) ==
522 (CHANNEL_G(0x0080 | 0x0400) | CHANNEL_PUREG(0x0080 | 0x0040))) {
523 mode = AR5K_INI_VAL_11G3;
524 freq = AR5K_INI_RFGAIN_2GHZ1;
525 ee_mode = AR5K_EEPROM_MODE_11G2;
526 } else if ((channel->c_channel_flagschannelFlags & CHANNEL_XR((0x0100 | 0x0040) | 0x1000)) == CHANNEL_XR((0x0100 | 0x0040) | 0x1000)) {
527 mode = AR5K_INI_VAL_XR0;
528 freq = AR5K_INI_RFGAIN_5GHZ0;
529 ee_mode = AR5K_EEPROM_MODE_11A0;
530 } else {
531 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel)printf("%s: " "invalid channel: %d\n", __func__, channel->
channel)
;
532 return (AH_FALSE);
533 }
534
535 /* PHY access enable */
536 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0
) << 2)))), ((0x00000007))))
;
537
538 /*
539 * Write initial mode and register settings
540 */
541 ar5k_write_mode(hal, ar5212_mode, nitems(ar5212_mode)(sizeof((ar5212_mode)) / sizeof((ar5212_mode)[0])), mode);
542 ar5k_write_ini(hal, ar5212_ini, nitems(ar5212_ini)(sizeof((ar5212_ini)) / sizeof((ar5212_ini)[0])), chanchange);
543
544 switch (hal->ah_radio) {
545 case AR5K_AR5111:
546 ar5k_write_mode(hal, ar5212_ar5111_mode,
547 nitems(ar5212_ar5111_mode)(sizeof((ar5212_ar5111_mode)) / sizeof((ar5212_ar5111_mode)[0
]))
, mode);
548 break;
549 case AR5K_AR5112:
550 ar5k_write_mode(hal, ar5212_ar5112_mode,
551 nitems(ar5212_ar5112_mode)(sizeof((ar5212_ar5112_mode)) / sizeof((ar5212_ar5112_mode)[0
]))
, mode);
552 break;
553 case AR5K_AR5413:
554 ar5k_write_mode(hal, ar5413_mode,
555 nitems(ar5413_mode)(sizeof((ar5413_mode)) / sizeof((ar5413_mode)[0])), mode);
556 break;
557 case AR5K_AR2413:
558 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((648
) << 2)))), ((0x018830c6))))
;
559 ar5k_write_mode(hal, ar2413_mode,
560 nitems(ar2413_mode)(sizeof((ar2413_mode)) / sizeof((ar2413_mode)[0])), mode);
561 break;
562 case AR5K_AR2425:
563 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((648
) << 2)))), ((0x018830c6))))
;
564 if (mode == AR5K_INI_VAL_11B2)
565 mode = AR5K_INI_VAL_11G3;
566 ar5k_write_mode(hal, ar2425_mode,
567 nitems(ar2425_mode)(sizeof((ar2425_mode)) / sizeof((ar2425_mode)[0])), mode);
568 break;
569 default:
570 AR5K_PRINTF("invalid radio: %d\n", hal->ah_radio)printf("%s: " "invalid radio: %d\n", __func__, hal->ah_radio
)
;
571 return (AH_FALSE);
572 }
573
574 if (hal->ah_radio == AR5K_AR5111)
575 ar5k_write_ini(hal, ar5111_bbgain,
576 nitems(ar5111_bbgain)(sizeof((ar5111_bbgain)) / sizeof((ar5111_bbgain)[0])), chanchange);
577 else
578 ar5k_write_ini(hal, ar5112_bbgain,
579 nitems(ar5112_bbgain)(sizeof((ar5112_bbgain)) / sizeof((ar5112_bbgain)[0])), chanchange);
580
581 /*
582 * Write initial RF gain settings
583 */
584 if (ar5k_rfgain(hal, freq) == AH_FALSE)
585 return (AH_FALSE);
586
587 AR5K_DELAY(1000)(*delay_func)(1000);
588
589 /*
590 * Set rate duration table
591 */
592 rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_XR);
593
594 for (i = 0; i < rt->rt_rate_countrateCount; i++) {
595 AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code),((hal->ah_st)->write_4((hal->ah_sh), (((0x8700 + ((rt
->info[i].rateCode) << 2)))), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
596 ath_hal_computetxtime(hal, rt, 14,((hal->ah_st)->write_4((hal->ah_sh), (((0x8700 + ((rt
->info[i].rateCode) << 2)))), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
597 rt->rt_info[i].r_control_rate, AH_FALSE))((hal->ah_st)->write_4((hal->ah_sh), (((0x8700 + ((rt
->info[i].rateCode) << 2)))), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
;
598 }
599
600 rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B);
601 for (i = 0; i < rt->rt_rate_countrateCount; i++) {
602 data = AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code)(0x8700 + ((rt->info[i].rateCode) << 2));
603 AR5K_REG_WRITE(data,((hal->ah_st)->write_4((hal->ah_sh), ((data)), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
604 ath_hal_computetxtime(hal, rt, 14,((hal->ah_st)->write_4((hal->ah_sh), ((data)), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
605 rt->rt_info[i].r_control_rate, AH_FALSE))((hal->ah_st)->write_4((hal->ah_sh), ((data)), ((ath_hal_computetxtime
(hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
;
606 if (rt->rt_infoinfo[i].r_short_preambleshortPreamble) {
607 AR5K_REG_WRITE(data +((hal->ah_st)->write_4((hal->ah_sh), ((data + (rt->
info[i].shortPreamble << 2))), ((ath_hal_computetxtime(
hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
608 (rt->rt_info[i].r_short_preamble << 2),((hal->ah_st)->write_4((hal->ah_sh), ((data + (rt->
info[i].shortPreamble << 2))), ((ath_hal_computetxtime(
hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
609 ath_hal_computetxtime(hal, rt, 14,((hal->ah_st)->write_4((hal->ah_sh), ((data + (rt->
info[i].shortPreamble << 2))), ((ath_hal_computetxtime(
hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
610 rt->rt_info[i].r_control_rate, AH_FALSE))((hal->ah_st)->write_4((hal->ah_sh), ((data + (rt->
info[i].shortPreamble << 2))), ((ath_hal_computetxtime(
hal, rt, 14, rt->info[i].controlRate, AH_FALSE)))))
;
611 }
612 }
613
614 /* Fix for first revision of the AR5112 RF chipset */
615 if (hal->ah_radio >= AR5K_AR5112 &&
616 hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A0x35) {
617 AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL,((hal->ah_st)->write_4((hal->ah_sh), ((0xa204)), ((0x00000000
))))
618 AR5K_AR5212_PHY_CCKTXCTL_WORLD)((hal->ah_st)->write_4((hal->ah_sh), ((0xa204)), ((0x00000000
))))
;
619 if (channel->c_channel_flagschannelFlags & IEEE80211_CHAN_OFDM0x0040)
620 data = 0xffb81020;
621 else
622 data = 0xffb80d20;
623 AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data)((hal->ah_st)->write_4((hal->ah_sh), ((0x9944)), ((data
))))
;
624 }
625
626 /*
627 * Set TX power (XXX use txpower from net80211)
628 */
629 if (ar5k_ar5212_txpower(hal, channel,
630 AR5K_TUNE_DEFAULT_TXPOWER30) == AH_FALSE)
631 return (AH_FALSE);
632
633 /*
634 * Write RF registers
635 */
636 if (ar5k_rfregs(hal, channel, mode) == AH_FALSE)
637 return (AH_FALSE);
638
639 /*
640 * Configure additional registers
641 */
642
643 /* OFDM timings */
644 if (channel->c_channel_flagschannelFlags & IEEE80211_CHAN_OFDM0x0040) {
645 u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp,
646 ds_coef_man, clock;
647
648 clock = 40;
649 coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channelchannel;
650
651 for (coef_exp = 31; coef_exp > 0; coef_exp--)
652 if ((coef_scaled >> coef_exp) & 0x1)
653 break;
654
655 if (!coef_exp)
656 return (AH_FALSE);
657
658 coef_exp = 14 - (coef_exp - 24);
659 coef_man = coef_scaled + (1 << (24 - coef_exp - 1));
660 ds_coef_man = coef_man >> (24 - coef_exp);
661 ds_coef_exp = coef_exp - 16;
662
663 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3,((hal->ah_st)->write_4((hal->ah_sh), ((0x9814)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9814)))) &
~ (0xfffe0000)) | (((ds_coef_man) << 17) & (0xfffe0000
))))))
664 AR5K_AR5212_PHY_TIMING_3_DSC_MAN, ds_coef_man)((hal->ah_st)->write_4((hal->ah_sh), ((0x9814)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9814)))) &
~ (0xfffe0000)) | (((ds_coef_man) << 17) & (0xfffe0000
))))))
;
665 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3,((hal->ah_st)->write_4((hal->ah_sh), ((0x9814)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9814)))) &
~ (0x0001e000)) | (((ds_coef_exp) << 13) & (0x0001e000
))))))
666 AR5K_AR5212_PHY_TIMING_3_DSC_EXP, ds_coef_exp)((hal->ah_st)->write_4((hal->ah_sh), ((0x9814)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9814)))) &
~ (0x0001e000)) | (((ds_coef_exp) << 13) & (0x0001e000
))))))
;
667 }
668
669 if (hal->ah_radio == AR5K_AR5111) {
670 if (channel->c_channel_flagschannelFlags & IEEE80211_CHAN_B(0x0080 | 0x0020))
671 AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) | (0x00000008
)))))
672 AR5K_AR5212_TXCFG_B_MODE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) | (0x00000008
)))))
;
673 else
674 AR5K_REG_DISABLE_BITS(AR5K_AR5212_TXCFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x00000008)))))
675 AR5K_AR5212_TXCFG_B_MODE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x00000008)))))
;
676 }
677
678 /* Set antenna mode */
679 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x44
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x44) << 2)))))) & (0xfffffc06)) |
(hal->ah_antenna[ee_mode][0])))))
680 hal->ah_antenna[ee_mode][0], 0xfffffc06)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x44
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x44) << 2)))))) & (0xfffffc06)) |
(hal->ah_antenna[ee_mode][0])))))
;
681
682 if (freq == AR5K_INI_RFGAIN_2GHZ1)
683 ant[0] = ant[1] = HAL_ANT_FIXED_B;
684 else
685 ant[0] = ant[1] = HAL_ANT_FIXED_A;
686
687 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0,((hal->ah_st)->write_4((hal->ah_sh), ((0x9960)), ((hal
->ah_antenna[ee_mode][ant[0]]))))
688 hal->ah_antenna[ee_mode][ant[0]])((hal->ah_st)->write_4((hal->ah_sh), ((0x9960)), ((hal
->ah_antenna[ee_mode][ant[0]]))))
;
689 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1,((hal->ah_st)->write_4((hal->ah_sh), ((0x9964)), ((hal
->ah_antenna[ee_mode][ant[1]]))))
690 hal->ah_antenna[ee_mode][ant[1]])((hal->ah_st)->write_4((hal->ah_sh), ((0x9964)), ((hal
->ah_antenna[ee_mode][ant[1]]))))
;
691
692 /* Commit values from EEPROM */
693 if (hal->ah_radio == AR5K_AR5111)
694 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_FC,((hal->ah_st)->write_4((hal->ah_sh), ((0x9944)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9944)))) &
~ (0x00000038)) | (((ee->ee_tx_clip) << 3) & (0x00000038
))))))
695 AR5K_AR5212_PHY_FC_TX_CLIP, ee->ee_tx_clip)((hal->ah_st)->write_4((hal->ah_sh), ((0x9944)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9944)))) &
~ (0x00000038)) | (((ee->ee_tx_clip) << 3) & (0x00000038
))))))
;
696
697 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x5a
) << 2)))), (((((ee->ee_noise_floor_thr[ee_mode]) &
0x000001ff) | (1 << 9))))))
698 AR5K_AR5212_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]))((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x5a
) << 2)))), (((((ee->ee_noise_floor_thr[ee_mode]) &
0x000001ff) | (1 << 9))))))
;
699
700 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x11),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x11
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x11) << 2)))))) & (0xffffc07f)) |
((ee->ee_switch_settling[ee_mode] << 7) & 0x3f80
)))))
701 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x11
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x11) << 2)))))) & (0xffffc07f)) |
((ee->ee_switch_settling[ee_mode] << 7) & 0x3f80
)))))
;
702 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x12),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x12
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x12) << 2)))))) & (0xfffc0fff)) |
((ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000)))
))
703 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x12
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x12) << 2)))))) & (0xfffc0fff)) |
((ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000)))
))
;
704 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x14),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x14
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x14) << 2)))))) & (0xffff0000)) |
((ee->ee_adc_desired_size[ee_mode] & 0x00ff) | ((ee->
ee_pga_desired_size[ee_mode] << 8) & 0xff00))))))
705 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x14
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x14) << 2)))))) & (0xffff0000)) |
((ee->ee_adc_desired_size[ee_mode] & 0x00ff) | ((ee->
ee_pga_desired_size[ee_mode] << 8) & 0xff00))))))
706 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x14
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x14) << 2)))))) & (0xffff0000)) |
((ee->ee_adc_desired_size[ee_mode] & 0x00ff) | ((ee->
ee_pga_desired_size[ee_mode] << 8) & 0xff00))))))
;
707
708 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0d
) << 2)))), (((ee->ee_tx_end2xpa_disable[ee_mode] <<
24) | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | (
ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | (ee->ee_tx_frm2xpa_enable
[ee_mode])))))
709 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0d
) << 2)))), (((ee->ee_tx_end2xpa_disable[ee_mode] <<
24) | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | (
ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | (ee->ee_tx_frm2xpa_enable
[ee_mode])))))
710 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0d
) << 2)))), (((ee->ee_tx_end2xpa_disable[ee_mode] <<
24) | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | (
ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | (ee->ee_tx_frm2xpa_enable
[ee_mode])))))
711 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0d
) << 2)))), (((ee->ee_tx_end2xpa_disable[ee_mode] <<
24) | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | (
ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | (ee->ee_tx_frm2xpa_enable
[ee_mode])))))
712 (ee->ee_tx_frm2xpa_enable[ee_mode]))((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0d
) << 2)))), (((ee->ee_tx_end2xpa_disable[ee_mode] <<
24) | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | (
ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | (ee->ee_tx_frm2xpa_enable
[ee_mode])))))
;
713
714 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x0a),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0a
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x0a) << 2)))))) & (0xffff00ff)) |
(ee->ee_tx_end2xlna_enable[ee_mode] << 8)))))
715 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x0a
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x0a) << 2)))))) & (0xffff00ff)) |
(ee->ee_tx_end2xlna_enable[ee_mode] << 8)))))
;
716 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19),((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x19
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x19) << 2)))))) & (0xfff80fff)) |
((ee->ee_thr_62[ee_mode] << 12) & 0x7f000)))))
717 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x19
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x19) << 2)))))) & (0xfff80fff)) |
((ee->ee_thr_62[ee_mode] << 12) & 0x7f000)))))
;
718 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01)((hal->ah_st)->write_4((hal->ah_sh), (((0x9800 + ((0x49
) << 2)))), (((((hal->ah_st)->read_4((hal->ah_sh
), (((0x9800 + ((0x49) << 2)))))) & (0xffffff01)) |
(4)))))
;
719
720 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ,((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| (ee->ee_i_cal[ee_mode] << 5) | ee->ee_q_cal[ee_mode
])))))
721 AR5K_AR5212_PHY_IQ_CORR_ENABLE |((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| (ee->ee_i_cal[ee_mode] << 5) | ee->ee_q_cal[ee_mode
])))))
722 (ee->ee_i_cal[ee_mode] << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S) |((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| (ee->ee_i_cal[ee_mode] << 5) | ee->ee_q_cal[ee_mode
])))))
723 ee->ee_q_cal[ee_mode])((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| (ee->ee_i_cal[ee_mode] << 5) | ee->ee_q_cal[ee_mode
])))))
;
724
725 if (hal->ah_ee_versionah_capabilities.cap_eeprom.ee_version >= AR5K_EEPROM_VERSION_4_10x4001) {
726 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_GAIN_2GHZ,((hal->ah_st)->write_4((hal->ah_sh), ((0xa20c)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0xa20c)))) &
~ (0x00fc0000)) | (((ee->ee_margin_tx_rx[ee_mode]) <<
18) & (0x00fc0000))))))
727 AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX,((hal->ah_st)->write_4((hal->ah_sh), ((0xa20c)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0xa20c)))) &
~ (0x00fc0000)) | (((ee->ee_margin_tx_rx[ee_mode]) <<
18) & (0x00fc0000))))))
728 ee->ee_margin_tx_rx[ee_mode])((hal->ah_st)->write_4((hal->ah_sh), ((0xa20c)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0xa20c)))) &
~ (0x00fc0000)) | (((ee->ee_margin_tx_rx[ee_mode]) <<
18) & (0x00fc0000))))))
;
729 }
730
731 /*
732 * Restore saved values
733 */
734 AR5K_REG_WRITE(AR5K_AR5212_DCU_SEQNUM(0), s_seq)((hal->ah_st)->write_4((hal->ah_sh), (((((0) <<
2) + 0x1140))), ((s_seq))))
;
735 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, s_ant)((hal->ah_st)->write_4((hal->ah_sh), ((0x8058)), ((s_ant
))))
;
736 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, s_led[0])((hal->ah_st)->write_4((hal->ah_sh), ((0x4010)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) | (s_led
[0])))))
;
737 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, s_led[1])((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), ((s_led
[1]))))
;
738 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, s_led[2])((hal->ah_st)->write_4((hal->ah_sh), ((0x4018)), ((s_led
[2]))))
;
739
740 /*
741 * Misc
742 */
743 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN6);
744 ar5k_ar5212_set_associd(hal, mac, 0, 0);
745 ar5k_ar5212_set_opmode(hal);
746 AR5K_REG_WRITE(AR5K_AR5212_PISR, 0xffffffff)((hal->ah_st)->write_4((hal->ah_sh), ((0x0080)), ((0xffffffff
))))
;
747 AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES)((hal->ah_st)->write_4((hal->ah_sh), ((0x8018)), ((1792
))))
;
748
749 /*
750 * Set Rx/Tx DMA Configuration
751 *
752 * XXX Limit DMA size on PCI-E chipsets to 128 bytes because
753 * XXX we saw RX overruns and TX errors with higher values.
754 */
755 dmasize = hal->ah_pci_express == AH_TRUE ?
756 AR5K_AR5212_DMASIZE_128B : AR5K_AR5212_DMASIZE_512B;
757 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_SDMAMR,((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x00000007)) | (((dmasize | 0x00000100) << 0) & (
0x00000007))))))
758 dmasize | AR5K_AR5212_TXCFG_DMASIZE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x00000007)) | (((dmasize | 0x00000100) << 0) & (
0x00000007))))))
;
759 AR5K_REG_WRITE_BITS(AR5K_AR5212_RXCFG, AR5K_AR5212_RXCFG_SDMAMW,((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) &
~ (0x00000007)) | (((dmasize) << 0) & (0x00000007))
))))
760 dmasize)((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) &
~ (0x00000007)) | (((dmasize) << 0) & (0x00000007))
))))
;
761
762 /*
763 * Set channel and calibrate the PHY
764 */
765 if (ar5k_channel(hal, channel) == AH_FALSE)
766 return (AH_FALSE);
767
768 /*
769 * Enable the PHY and wait until completion
770 */
771 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x981c)), ((0x00000001
))))
;
772
773 data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY)((hal->ah_st)->read_4((hal->ah_sh), ((0x9914)))) &
774 AR5K_AR5212_PHY_RX_DELAY_M0x00003fff;
775 data = (channel->c_channel_flagschannelFlags & IEEE80211_CHAN_CCK0x0020) ?
776 ((data << 2) / 22) : (data / 10);
777
778 AR5K_DELAY(100 + data)(*delay_func)(100 + data);
779
780 /*
781 * Start calibration
782 */
783 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL,((hal->ah_st)->write_4((hal->ah_sh), ((0x9860)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9860)))) | (0x00000002
| 0x00000001)))))
784 AR5K_AR5212_PHY_AGCCTL_NF |((hal->ah_st)->write_4((hal->ah_sh), ((0x9860)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9860)))) | (0x00000002
| 0x00000001)))))
785 AR5K_AR5212_PHY_AGCCTL_CAL)((hal->ah_st)->write_4((hal->ah_sh), ((0x9860)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9860)))) | (0x00000002
| 0x00000001)))))
;
786
787 hal->ah_calibration = AH_FALSE;
788 if ((channel->c_channel_flagschannelFlags & IEEE80211_CHAN_B(0x0080 | 0x0020)) == 0) {
789 hal->ah_calibration = AH_TRUE;
790 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ,((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) &
~ (0x0000f000)) | (((15) << 12) & (0x0000f000))))))
791 AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15)((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) &
~ (0x0000f000)) | (((15) << 12) & (0x0000f000))))))
;
792 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ,((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00010000
)))))
793 AR5K_AR5212_PHY_IQ_RUN)((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00010000
)))))
;
794 }
795
796 /*
797 * Reset queues and start beacon timers at the end of the reset routine
798 */
799 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
800 AR5K_REG_WRITE_Q(AR5K_AR5212_DCU_QCUMASK(i), i)((hal->ah_st)->write_4((hal->ah_sh), (((((i) <<
2) + 0x1000))), (((1 << i)))))
;
801 if (ar5k_ar5212_reset_tx_queue(hal, i) == AH_FALSE) {
802 AR5K_PRINTF("failed to reset TX queue #%d\n", i)printf("%s: " "failed to reset TX queue #%d\n", __func__, i);
803 return (AH_FALSE);
804 }
805 }
806
807 /* Pre-enable interrupts */
808 ar5k_ar5212_set_intr(hal, HAL_INT_RX0x00000001 | HAL_INT_TX0x00000040 | HAL_INT_FATAL0x40000000);
809
810 /*
811 * Set RF kill flags if supported by the device (read from the EEPROM)
812 */
813 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)(((hal->ah_capabilities.cap_eeprom.ee_header) >> 14)
& 0x1)
) {
814 ar5k_ar5212_set_gpio_input(hal, 0);
815 if ((hal->ah_gpio[0] = ar5k_ar5212_get_gpio(hal, 0)) == 0)
816 ar5k_ar5212_set_gpio_intr(hal, 0, 1);
817 else
818 ar5k_ar5212_set_gpio_intr(hal, 0, 0);
819 }
820
821 /*
822 * Set the 32MHz reference clock
823 */
824 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, AR5K_AR5212_PHY_SCR_32MHZ)((hal->ah_st)->write_4((hal->ah_sh), ((0x9870)), ((0x0000001f
))))
;
825 AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT, AR5K_AR5212_PHY_SLMT_32MHZ)((hal->ah_st)->write_4((hal->ah_sh), ((0x9874)), ((0x0000007f
))))
;
826 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, AR5K_AR5212_PHY_SCAL_32MHZ)((hal->ah_st)->write_4((hal->ah_sh), ((0x9878)), ((0x0000000e
))))
;
827 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK, AR5K_AR5212_PHY_SCLOCK_32MHZ)((hal->ah_st)->write_4((hal->ah_sh), ((0x99f0)), ((0x0000000c
))))
;
828 AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ)((hal->ah_st)->write_4((hal->ah_sh), ((0x99f4)), ((0x000000ff
))))
;
829 AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_phy_spending)((hal->ah_st)->write_4((hal->ah_sh), ((0x99f8)), ((hal
->ah_phy_spending))))
;
830
831 /*
832 * Disable beacons and reset the register
833 */
834 AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x00800000 | 0x01000000)))))
835 AR5K_AR5212_BEACON_ENABLE | AR5K_AR5212_BEACON_RESET_TSF)((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x00800000 | 0x01000000)))))
;
836
837 return (AH_TRUE);
838}
839
840void
841ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant)
842{
843 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant)((hal->ah_st)->write_4((hal->ah_sh), ((0x8058)), ((ant
))))
;
844}
845
846u_int
847ar5k_ar5212_get_def_antenna(struct ath_hal *hal)
848{
849 return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA)((hal->ah_st)->read_4((hal->ah_sh), ((0x8058))));
850}
851
852void
853ar5k_ar5212_set_opmode(struct ath_hal *hal)
854{
855 u_int32_t pcu_reg, low_id, high_id;
856
857 pcu_reg = 0;
858
859 switch (hal->ah_op_mode) {
860#ifndef IEEE80211_STA_ONLY
861 case IEEE80211_M_IBSS:
862 pcu_reg |= AR5K_AR5212_STA_ID1_ADHOC0x00020000 |
863 AR5K_AR5212_STA_ID1_DESC_ANTENNA0x00400000;
864 break;
865
866 case IEEE80211_M_HOSTAP:
867 pcu_reg |= AR5K_AR5212_STA_ID1_AP0x00010000 |
868 AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA0x00800000;
869 break;
870#endif
871
872 case IEEE80211_M_STA:
873 case IEEE80211_M_MONITOR:
874 pcu_reg |= AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA0x00200000;
875 break;
876
877 default:
878 return;
879 }
880
881 /*
882 * Set PCU registers
883 */
884 low_id = AR5K_LOW_ID(hal->ah_sta_id)( (hal->ah_sta_id)[0] | (hal->ah_sta_id)[1] << 8 |
(hal->ah_sta_id)[2] << 16 | (hal->ah_sta_id)[3] <<
24 )
;
885 high_id = AR5K_HIGH_ID(hal->ah_sta_id)((hal->ah_sta_id)[4] | (hal->ah_sta_id)[5] << 8);
886 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x8000)), ((low_id
))))
;
887 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, pcu_reg | high_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), ((pcu_reg
| high_id))))
;
888
889 return;
890}
891
892HAL_BOOL
893ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
894{
895 u_int32_t i_pwr, q_pwr;
896 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
897
898 if (hal->ah_calibration == AH_FALSE ||
899 AR5K_REG_READ(AR5K_AR5212_PHY_IQ)((hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) & AR5K_AR5212_PHY_IQ_RUN0x00010000)
900 goto done;
901
902 hal->ah_calibration = AH_FALSE;
903
904 iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR)((hal->ah_st)->read_4((hal->ah_sh), ((0x9c18))));
905 i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I)((hal->ah_st)->read_4((hal->ah_sh), ((0x9c10))));
906 q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q)((hal->ah_st)->read_4((hal->ah_sh), ((0x9c14))));
907 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
908 q_coffd = q_pwr >> 6;
909
910 if (i_coffd == 0 || q_coffd == 0)
911 goto done;
912
913 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
914 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f;
915
916 /* Commit new IQ value */
917 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ,((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| ((u_int32_t)q_coff) | ((u_int32_t)i_coff << 5))))))
918 AR5K_AR5212_PHY_IQ_CORR_ENABLE |((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| ((u_int32_t)q_coff) | ((u_int32_t)i_coff << 5))))))
919 ((u_int32_t)q_coff) |((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| ((u_int32_t)q_coff) | ((u_int32_t)i_coff << 5))))))
920 ((u_int32_t)i_coff << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S))((hal->ah_st)->write_4((hal->ah_sh), ((0x9920)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9920)))) | (0x00000800
| ((u_int32_t)q_coff) | ((u_int32_t)i_coff << 5))))))
;
921
922 done:
923 /* Start noise floor calibration */
924 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL,((hal->ah_st)->write_4((hal->ah_sh), ((0x9860)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9860)))) | (0x00000002
)))))
925 AR5K_AR5212_PHY_AGCCTL_NF)((hal->ah_st)->write_4((hal->ah_sh), ((0x9860)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x9860)))) | (0x00000002
)))))
;
926
927 /* Request RF gain */
928 if (channel->c_channel_flagschannelFlags & IEEE80211_CHAN_5GHZ0x0100) {
929 AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE,((hal->ah_st)->write_4((hal->ah_sh), ((0x9930)), (((
((uint32_t)(hal->ah_txpower.txp_max) << 9) & (0x00007e00
)) | 0x00008000))))
930 AR5K_REG_SM(hal->ah_txpower.txp_max,((hal->ah_st)->write_4((hal->ah_sh), ((0x9930)), (((
((uint32_t)(hal->ah_txpower.txp_max) << 9) & (0x00007e00
)) | 0x00008000))))
931 AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER) |((hal->ah_st)->write_4((hal->ah_sh), ((0x9930)), (((
((uint32_t)(hal->ah_txpower.txp_max) << 9) & (0x00007e00
)) | 0x00008000))))
932 AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT)((hal->ah_st)->write_4((hal->ah_sh), ((0x9930)), (((
((uint32_t)(hal->ah_txpower.txp_max) << 9) & (0x00007e00
)) | 0x00008000))))
;
933 hal->ah_rf_gain = HAL_RFGAIN_READ_REQUESTED;
934 }
935
936 return (AH_TRUE);
937}
938
939/*
940 * Transmit functions
941 */
942
943HAL_BOOL
944ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
945{
946 u_int32_t trigger_level, imr;
947 HAL_BOOL status = AH_FALSE;
948
949 /*
950 * Disable interrupts by setting the mask
951 */
952 imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL0x80000000);
953
954 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG),(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x0030
))))) & (0x000003f0)) >> 4)
955 AR5K_AR5212_TXCFG_TXFULL)(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x0030
))))) & (0x000003f0)) >> 4)
;
956
957 if (increase == AH_FALSE) {
958 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES1)
959 goto done;
960 } else
961 trigger_level +=
962 ((AR5K_TUNE_MAX_TX_FIFO_THRES(((2300 + 4 + (3 + 1 + 4)) / 64) + 1) - trigger_level) / 2);
963
964 /*
965 * Update trigger level on success
966 */
967 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x000003f0)) | (((trigger_level) << 4) & (0x000003f0
))))))
968 AR5K_AR5212_TXCFG_TXFULL, trigger_level)((hal->ah_st)->write_4((hal->ah_sh), ((0x0030)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x0030)))) &
~ (0x000003f0)) | (((trigger_level) << 4) & (0x000003f0
))))))
;
969 status = AH_TRUE;
970
971 done:
972 /*
973 * Restore interrupt mask
974 */
975 ar5k_ar5212_set_intr(hal, imr);
976
977 return (status);
978}
979
980int
981ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
982 const HAL_TXQ_INFO *queue_info)
983{
984 u_int queue;
985
986 /*
987 * Get queue by type
988 */
989 if (queue_type == HAL_TX_QUEUE_DATA) {
990 for (queue = HAL_TX_QUEUE_ID_DATA_MIN;
991 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE;
992 queue++)
993 if (queue > HAL_TX_QUEUE_ID_DATA_MAX)
994 return (-1);
995 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) {
996 queue = HAL_TX_QUEUE_ID_PSPOLL;
997 } else if (queue_type == HAL_TX_QUEUE_BEACON) {
998 queue = HAL_TX_QUEUE_ID_BEACON;
999 } else if (queue_type == HAL_TX_QUEUE_CAB) {
1000 queue = HAL_TX_QUEUE_ID_CAB;
1001 } else
1002 return (-1);
1003
1004 /*
1005 * Setup internal queue structure
1006 */
1007 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO))__builtin_bzero((&hal->ah_txq[queue]), (sizeof(HAL_TXQ_INFO
)))
;
1008 if (queue_info != NULL((void *)0)) {
1009 if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info)
1010 != AH_TRUE)
1011 return (-1);
1012 }
1013 hal->ah_txq[queue].tqi_type = queue_type;
1014
1015 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue)do { hal->ah_txq_interrupts |= 1 << queue; } while (
0)
;
1016
1017 return (queue);
1018}
1019
1020HAL_BOOL
1021ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue,
1022 const HAL_TXQ_INFO *queue_info)
1023{
1024 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1025
1026 if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE)
1027 return (AH_FALSE);
1028
1029 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
1030
1031 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA &&
1032 (queue_info->tqi_subtype >= HAL_WME_AC_VI) &&
1033 (queue_info->tqi_subtype <= HAL_WME_UPSD))
1034 hal->ah_txq[queue].tqi_flags |=
1035 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS0x0040;
1036
1037 return (AH_TRUE);
1038}
1039
1040HAL_BOOL
1041ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue,
1042 HAL_TXQ_INFO *queue_info)
1043{
1044 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1045 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
1046 return (AH_TRUE);
1047}
1048
1049HAL_BOOL
1050ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue)
1051{
1052 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1053
1054 /* This queue will be skipped in further operations */
1055 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
1056 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue)do { hal->ah_txq_interrupts &= ~(1 << queue); } while
(0)
;
1057
1058 return (AH_FALSE);
1059}
1060
1061HAL_BOOL
1062ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue)
1063{
1064 u_int32_t cw_min, cw_max, retry_lg, retry_sh;
1065 struct ieee80211_channel *channel = (struct ieee80211_channel*)
1066 &hal->ah_current_channel;
1067 HAL_TXQ_INFO *tq;
1068
1069 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1070
1071 tq = &hal->ah_txq[queue];
1072
1073 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE)
1074 return (AH_TRUE);
1075
1076 /*
1077 * Set registers by channel mode
1078 */
1079 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN15;
Value stored to 'cw_min' is never read
1080 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX1023;
1081 hal->ah_aifs = AR5K_TUNE_AIFS2;
1082 if (IEEE80211_IS_CHAN_XR(channel)(((channel)->ic_flags & 0x1000) != 0)) {
1083 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR3;
1084 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR7;
1085 hal->ah_aifs = AR5K_TUNE_AIFS_XR0;
1086 } else if (IEEE80211_IS_CHAN_B(channel)(((channel)->ic_flags & (0x0080 | 0x0020)) == (0x0080 |
0x0020))
) {
1087 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B31;
1088 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B1023;
1089 hal->ah_aifs = AR5K_TUNE_AIFS_11B2;
1090 }
1091
1092 /*
1093 * Set retry limits
1094 */
1095 if (hal->ah_software_retry == AH_TRUE) {
1096 /* XXX Need to test this */
1097 retry_lg = hal->ah_limit_tx_retries;
1098 retry_sh = retry_lg =
1099 retry_lg > AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY0x0000000f ?
1100 AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY0x0000000f : retry_lg;
1101 } else {
1102 retry_lg = AR5K_INIT_LG_RETRY10;
1103 retry_sh = AR5K_INIT_SH_RETRY10;
1104 }
1105
1106 AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1107 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1108 AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1109 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1110 AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1111 AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
1112 AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY))((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1080))), (((((uint32_t)(32) << 14) & (0x000fc000
)) | (((uint32_t)(32) << 8) & (0x00003f00)) | (((uint32_t
)(retry_lg) << 4) & (0x000000f0)) | (((uint32_t)(retry_sh
) << 0) & (0x0000000f))))))
;
1113
1114 /*
1115 * Set initial content window (cw_min/cw_max)
1116 */
1117 cw_min = 1;
1118 while (cw_min < hal->ah_cw_min)
1119 cw_min = (cw_min << 1) | 1;
1120
1121 cw_min = tq->tqi_cw_min < 0 ?
1122 (cw_min >> (-tq->tqi_cw_min)) :
1123 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
1124 cw_max = tq->tqi_cw_max < 0 ?
1125 (cw_max >> (-tq->tqi_cw_max)) :
1126 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
1127
1128 AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1040))), (((((uint32_t)(cw_min) << 0) & (0x000003ff
)) | (((uint32_t)(cw_max) << 10) & (0x000ffc00)) | (
((uint32_t)(hal->ah_aifs + tq->tqi_aifs) << 20) &
(0x0ff00000))))))
1129 AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1040))), (((((uint32_t)(cw_min) << 0) & (0x000003ff
)) | (((uint32_t)(cw_max) << 10) & (0x000ffc00)) | (
((uint32_t)(hal->ah_aifs + tq->tqi_aifs) << 20) &
(0x0ff00000))))))
1130 AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1040))), (((((uint32_t)(cw_min) << 0) & (0x000003ff
)) | (((uint32_t)(cw_max) << 10) & (0x000ffc00)) | (
((uint32_t)(hal->ah_aifs + tq->tqi_aifs) << 20) &
(0x0ff00000))))))
1131 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1040))), (((((uint32_t)(cw_min) << 0) & (0x000003ff
)) | (((uint32_t)(cw_max) << 10) & (0x000ffc00)) | (
((uint32_t)(hal->ah_aifs + tq->tqi_aifs) << 20) &
(0x0ff00000))))))
1132 AR5K_AR5212_DCU_LCL_IFS_AIFS))((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1040))), (((((uint32_t)(cw_min) << 0) & (0x000003ff
)) | (((uint32_t)(cw_max) << 10) & (0x000ffc00)) | (
((uint32_t)(hal->ah_aifs + tq->tqi_aifs) << 20) &
(0x0ff00000))))))
;
1133
1134 /*
1135 * Set misc registers
1136 */
1137 AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((0x00000800))))
1138 AR5K_AR5212_QCU_MISC_DCU_EARLY)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((0x00000800))))
;
1139
1140 if (tq->tqi_cbr_period) {
1141 AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x08c0))), (((((uint32_t)(tq->tqi_cbr_period) <<
0) & (0x00ffffff)) | (((uint32_t)(tq->tqi_cbr_overflow_limit
) << 24) & (0xff000000))))))
1142 AR5K_REG_SM(tq->tqi_cbr_period,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x08c0))), (((((uint32_t)(tq->tqi_cbr_period) <<
0) & (0x00ffffff)) | (((uint32_t)(tq->tqi_cbr_overflow_limit
) << 24) & (0xff000000))))))
1143 AR5K_AR5212_QCU_CBRCFG_INTVAL) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x08c0))), (((((uint32_t)(tq->tqi_cbr_period) <<
0) & (0x00ffffff)) | (((uint32_t)(tq->tqi_cbr_overflow_limit
) << 24) & (0xff000000))))))
1144 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x08c0))), (((((uint32_t)(tq->tqi_cbr_period) <<
0) & (0x00ffffff)) | (((uint32_t)(tq->tqi_cbr_overflow_limit
) << 24) & (0xff000000))))))
1145 AR5K_AR5212_QCU_CBRCFG_ORN_THRES))((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x08c0))), (((((uint32_t)(tq->tqi_cbr_period) <<
0) & (0x00ffffff)) | (((uint32_t)(tq->tqi_cbr_overflow_limit
) << 24) & (0xff000000))))))
;
1146 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (1)))))
1147 AR5K_AR5212_QCU_MISC_FRSHED_CBR)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (1)))))
;
1148 if (tq->tqi_cbr_overflow_limit)
1149 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000100)))))
1150 AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000100)))))
;
1151 }
1152
1153 if (tq->tqi_ready_time) {
1154 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), (((((uint32_t)(tq->tqi_ready_time) <<
0) & (0x00ffffff)) | 0x01000000))))
1155 AR5K_REG_SM(tq->tqi_ready_time,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), (((((uint32_t)(tq->tqi_ready_time) <<
0) & (0x00ffffff)) | 0x01000000))))
1156 AR5K_AR5212_QCU_RDYTIMECFG_INTVAL) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), (((((uint32_t)(tq->tqi_ready_time) <<
0) & (0x00ffffff)) | 0x01000000))))
1157 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), (((((uint32_t)(tq->tqi_ready_time) <<
0) & (0x00ffffff)) | 0x01000000))))
;
1158 }
1159
1160 if (tq->tqi_burst_time) {
1161 AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x10c0))), (((((uint32_t)(tq->tqi_burst_time) <<
0) & (0x000fffff)) | 0x00100000))))
1162 AR5K_REG_SM(tq->tqi_burst_time,((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x10c0))), (((((uint32_t)(tq->tqi_burst_time) <<
0) & (0x000fffff)) | 0x00100000))))
1163 AR5K_AR5212_DCU_CHAN_TIME_DUR) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x10c0))), (((((uint32_t)(tq->tqi_burst_time) <<
0) & (0x000fffff)) | 0x00100000))))
1164 AR5K_AR5212_DCU_CHAN_TIME_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x10c0))), (((((uint32_t)(tq->tqi_burst_time) <<
0) & (0x000fffff)) | 0x00100000))))
;
1165
1166 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE0x0010) {
1167 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000200)))))
1168 AR5K_AR5212_QCU_MISC_TXE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000200)))))
;
1169 }
1170 }
1171
1172 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE0x0004) {
1173 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((0x00200000))))
1174 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((0x00200000))))
;
1175 }
1176
1177 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE0x0020) {
1178 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((0x00000200))))
1179 AR5K_AR5212_DCU_MISC_BACKOFF_FRAG)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((0x00000200))))
;
1180 }
1181
1182 /*
1183 * Set registers by queue type
1184 */
1185 switch (tq->tqi_type) {
1186 case HAL_TX_QUEUE_BEACON:
1187 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000040 | 0x00000080
)))))
1188 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000040 | 0x00000080
)))))
1189 AR5K_AR5212_QCU_MISC_CBREXP_BCN |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000040 | 0x00000080
)))))
1190 AR5K_AR5212_QCU_MISC_BCN_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000040 | 0x00000080
)))))
;
1191
1192 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2) | 0x00200000
| 0x00010000)))))
1193 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL <<((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2) | 0x00200000
| 0x00010000)))))
1194 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2) | 0x00200000
| 0x00010000)))))
1195 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2) | 0x00200000
| 0x00010000)))))
1196 AR5K_AR5212_DCU_MISC_BCN_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2) | 0x00200000
| 0x00010000)))))
;
1197
1198 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), ((((100 - (10 - 2) - 0) * 1024) | 0x01000000
))))
1199 ((AR5K_TUNE_BEACON_INTERVAL -((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), ((((100 - (10 - 2) - 0) * 1024) | 0x01000000
))))
1200 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) -((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), ((((100 - (10 - 2) - 0) * 1024) | 0x01000000
))))
1201 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), ((((100 - (10 - 2) - 0) * 1024) | 0x01000000
))))
1202 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0900))), ((((100 - (10 - 2) - 0) * 1024) | 0x01000000
))))
;
1203 break;
1204
1205 case HAL_TX_QUEUE_CAB:
1206 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000020 | 0x00000040
)))))
1207 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000020 | 0x00000040
)))))
1208 AR5K_AR5212_QCU_MISC_CBREXP |((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000020 | 0x00000040
)))))
1209 AR5K_AR5212_QCU_MISC_CBREXP_BCN)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (2 | 0x00000020 | 0x00000040
)))))
;
1210
1211 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2))))
))
1212 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL <<((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2))))
))
1213 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL))((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x1100))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x1100))))) | ((2 << 2))))
))
;
1214 break;
1215
1216 case HAL_TX_QUEUE_PSPOLL:
1217 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000020)))))
1218 AR5K_AR5212_QCU_MISC_CBREXP)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x09c0))), ((((hal->ah_st)->read_4((hal->ah_sh
), (((((queue) << 2) + 0x09c0))))) | (0x00000020)))))
;
1219 break;
1220
1221 case HAL_TX_QUEUE_DATA:
1222 default:
1223 break;
1224 }
1225
1226 /*
1227 * Enable tx queue in the secondary interrupt mask registers
1228 */
1229 AR5K_REG_WRITE(AR5K_AR5212_SIMR0,((hal->ah_st)->write_4((hal->ah_sh), ((0x00a4)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
)) | (((uint32_t)(hal->ah_txq_interrupts) << 16) &
(0x03ff0000))))))
1230 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) |((hal->ah_st)->write_4((hal->ah_sh), ((0x00a4)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
)) | (((uint32_t)(hal->ah_txq_interrupts) << 16) &
(0x03ff0000))))))
1231 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC))((hal->ah_st)->write_4((hal->ah_sh), ((0x00a4)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
)) | (((uint32_t)(hal->ah_txq_interrupts) << 16) &
(0x03ff0000))))))
;
1232 AR5K_REG_WRITE(AR5K_AR5212_SIMR1,((hal->ah_st)->write_4((hal->ah_sh), ((0x00a8)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
))))))
1233 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR))((hal->ah_st)->write_4((hal->ah_sh), ((0x00a8)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
))))))
;
1234 AR5K_REG_WRITE(AR5K_AR5212_SIMR2,((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
))))))
1235 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN))((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
((uint32_t)(hal->ah_txq_interrupts) << 0) & (0x000003ff
))))))
;
1236
1237 return (AH_TRUE);
1238}
1239
1240u_int32_t
1241ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue)
1242{
1243 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1244
1245 /*
1246 * Get the transmit queue descriptor pointer from the selected queue
1247 */
1248 return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue))((hal->ah_st)->read_4((hal->ah_sh), (((((queue) <<
2) + 0x0800)))))
);
1249}
1250
1251HAL_BOOL
1252ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
1253{
1254 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1255
1256 /*
1257 * Set the transmit queue descriptor pointer for the selected queue
1258 * (this won't work if the queue is still active)
1259 */
1260 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue)(((hal->ah_st)->read_4((hal->ah_sh), ((0x0840)))) &
(1 << queue))
)
1261 return (AH_FALSE);
1262
1263 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr)((hal->ah_st)->write_4((hal->ah_sh), (((((queue) <<
2) + 0x0800))), ((phys_addr))))
;
1264
1265 return (AH_TRUE);
1266}
1267
1268u_int32_t
1269ar5k_ar5212_num_tx_pending(struct ath_hal *hal, u_int queue)
1270{
1271 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1272 return (AR5K_AR5212_QCU_STS(queue)(((queue) << 2) + 0x0a00) & AR5K_AR5212_QCU_STS_FRMPENDCNT0x00000003);
1273}
1274
1275HAL_BOOL
1276ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue)
1277{
1278 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1279
1280 /* Return if queue is disabled */
1281 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXD, queue)(((hal->ah_st)->read_4((hal->ah_sh), ((0x0880)))) &
(1 << queue))
)
1282 return (AH_FALSE);
1283
1284 /* Start queue */
1285 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXE, queue)((hal->ah_st)->write_4((hal->ah_sh), ((0x0840)), (((
1 << queue)))))
;
1286
1287 return (AH_TRUE);
1288}
1289
1290HAL_BOOL
1291ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue)
1292{
1293 int i = 100, pending;
1294
1295 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num)do { if (queue >= hal->ah_capabilities.cap_queues.q_tx_num
) return (AH_FALSE); } while (0)
;
1296
1297 /*
1298 * Schedule TX disable and wait until queue is empty
1299 */
1300 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXD, queue)((hal->ah_st)->write_4((hal->ah_sh), ((0x0880)), (((
1 << queue)))))
;
1301
1302 do {
1303 pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue))((hal->ah_st)->read_4((hal->ah_sh), (((((queue) <<
2) + 0x0a00)))))
&
1304 AR5K_AR5212_QCU_STS_FRMPENDCNT0x00000003;
1305 delay(100)(*delay_func)(100);
1306 } while (--i && pending);
1307
1308 /* Clear register */
1309 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x0880)), ((0
))))
;
1310
1311 return (AH_TRUE);
1312}
1313
1314HAL_BOOL
1315ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
1316 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
1317 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
1318 u_int flags, u_int rtscts_rate, u_int rtscts_duration)
1319{
1320 struct ar5k_ar5212_tx_desc *tx_desc;
1321
1322 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
1323
1324 /*
1325 * Validate input
1326 */
1327 if (tx_tries0 == 0)
1328 return (AH_FALSE);
1329
1330 if ((tx_desc->tx_control_0 = (packet_length &
1331 AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN0x00000fff)) != packet_length)
1332 return (AH_FALSE);
1333
1334 tx_desc->tx_control_0 |=
1335 AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER)(((uint32_t)(tx_power) << 16) & (0x003f0000)) |
1336 AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT)(((uint32_t)(antenna_mode) << 25) & (0x1e000000));
1337 tx_desc->tx_control_1 =
1338 AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE)(((uint32_t)(type) << 20) & (0x00f00000));
1339 tx_desc->tx_control_2 =
1340 AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0)(((uint32_t)(tx_tries0) << 16) & (0x000f0000));
1341 tx_desc->tx_control_3 =
1342 tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE00x0000001f;
1343
1344#define _TX_FLAGS(_c, _flag) \
1345 if (flags & HAL_TXDESC_##_flag) \
1346 tx_desc->tx_control_##_c |= \
1347 AR5K_AR5212_DESC_TX_CTL##_c##_##_flag
1348
1349 _TX_FLAGS(0, CLRDMASK);
1350 _TX_FLAGS(0, VEOL);
1351 _TX_FLAGS(0, INTREQ);
1352 _TX_FLAGS(0, RTSENA);
1353 _TX_FLAGS(0, CTSENA);
1354 _TX_FLAGS(1, NOACK);
1355
1356#undef _TX_FLAGS
1357
1358 /*
1359 * WEP crap
1360 */
1361 if (key_index != HAL_TXKEYIX_INVALID((u_int32_t) - 1)) {
1362 tx_desc->tx_control_0 |=
1363 AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID0x40000000;
1364 tx_desc->tx_control_1 |=
1365 AR5K_REG_SM(key_index,(((uint32_t)(key_index) << 13) & (0x000fe000))
1366 AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX)(((uint32_t)(key_index) << 13) & (0x000fe000));
1367 }
1368
1369 /*
1370 * RTS/CTS
1371 */
1372 if (flags & (HAL_TXDESC_RTSENA0x0004 | HAL_TXDESC_CTSENA0x0008)) {
1373 if ((flags & HAL_TXDESC_RTSENA0x0004) &&
1374 (flags & HAL_TXDESC_CTSENA0x0008))
1375 return (AH_FALSE);
1376 tx_desc->tx_control_2 |=
1377 rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION0x00007fff;
1378 tx_desc->tx_control_3 |=
1379 AR5K_REG_SM(rtscts_rate,(((uint32_t)(rtscts_rate) << 20) & (0x01f00000))
1380 AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE)(((uint32_t)(rtscts_rate) << 20) & (0x01f00000));
1381 }
1382
1383 return (AH_TRUE);
1384}
1385
1386HAL_BOOL
1387ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
1388 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
1389{
1390 struct ar5k_ar5212_tx_desc *tx_desc;
1391 struct ar5k_ar5212_tx_status *tx_status;
1392
1393 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
1394 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
1395
1396 /* Clear status descriptor */
1397 bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status))__builtin_bzero((tx_status), (sizeof(struct ar5k_ar5212_tx_status
)))
;
1398
1399 /* Validate segment length and initialize the descriptor */
1400 if (segment_length & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN0x00000fff)
1401 return (AH_FALSE);
1402 tx_desc->tx_control_1 =
1403#if 0
1404 (tx_desc->tx_control_1 & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN0x00000fff) |
1405#endif
1406 segment_length;
1407
1408 if (first_segment != AH_TRUE)
1409 tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN0x00000fff;
1410
1411 if (last_segment != AH_TRUE)
1412 tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE0x00001000;
1413
1414 return (AH_TRUE);
1415}
1416
1417HAL_BOOL
1418ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
1419 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
1420 u_int tx_rate3, u_int tx_tries3)
1421{
1422 struct ar5k_ar5212_tx_desc *tx_desc;
1423
1424 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
1425
1426#define _XTX_TRIES(_n) \
1427 if (tx_tries##_n) { \
1428 tx_desc->tx_control_2 |= \
1429 AR5K_REG_SM(tx_tries##_n, \(((uint32_t)(tx_tries##_n) << AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES
##_n_S) & (AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n))
1430 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n)(((uint32_t)(tx_tries##_n) << AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES
##_n_S) & (AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n))
; \
1431 tx_desc->tx_control_3 |= \
1432 AR5K_REG_SM(tx_rate##_n, \(((uint32_t)(tx_rate##_n) << AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE
##_n_S) & (AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n))
1433 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n)(((uint32_t)(tx_rate##_n) << AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE
##_n_S) & (AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n))
; \
1434 }
1435
1436 _XTX_TRIES(1);
1437 _XTX_TRIES(2);
1438 _XTX_TRIES(3);
1439
1440#undef _XTX_TRIES
1441
1442 return (AH_TRUE);
1443}
1444
1445HAL_STATUS
1446ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
1447{
1448 struct ar5k_ar5212_tx_status *tx_status;
1449 struct ar5k_ar5212_tx_desc *tx_desc;
1450
1451 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0;
1452 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
1453
1454 /* No frame has been send or error */
1455 if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE0x00000001) == 0)
1456 return (HAL_EINPROGRESS36);
1457
1458 /*
1459 * Get descriptor status
1460 */
1461 desc->ds_us.tx.ts_tstamp =
1462 AR5K_REG_MS(tx_status->tx_status_0,(((uint32_t)(tx_status->tx_status_0) & (0xffff0000)) >>
16)
1463 AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP)(((uint32_t)(tx_status->tx_status_0) & (0xffff0000)) >>
16)
;
1464 desc->ds_us.tx.ts_shortretry =
1465 AR5K_REG_MS(tx_status->tx_status_0,(((uint32_t)(tx_status->tx_status_0) & (0x000000f0)) >>
4)
1466 AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT)(((uint32_t)(tx_status->tx_status_0) & (0x000000f0)) >>
4)
;
1467 desc->ds_us.tx.ts_longretry =
1468 AR5K_REG_MS(tx_status->tx_status_0,(((uint32_t)(tx_status->tx_status_0) & (0x00000f00)) >>
8)
1469 AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT)(((uint32_t)(tx_status->tx_status_0) & (0x00000f00)) >>
8)
;
1470 desc->ds_us.tx.ts_seqnum =
1471 AR5K_REG_MS(tx_status->tx_status_1,(((uint32_t)(tx_status->tx_status_1) & (0x00001ffe)) >>
1)
1472 AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM)(((uint32_t)(tx_status->tx_status_1) & (0x00001ffe)) >>
1)
;
1473 desc->ds_us.tx.ts_rssi =
1474 AR5K_REG_MS(tx_status->tx_status_1,(((uint32_t)(tx_status->tx_status_1) & (0x001fe000)) >>
13)
1475 AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH)(((uint32_t)(tx_status->tx_status_1) & (0x001fe000)) >>
13)
;
1476 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
1477 AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA0x01000000) ? 2 : 1;
1478 desc->ds_us.tx.ts_status = 0;
1479
1480 switch (AR5K_REG_MS(tx_status->tx_status_1,(((uint32_t)(tx_status->tx_status_1) & (0x00600000)) >>
21)
1481 AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)(((uint32_t)(tx_status->tx_status_1) & (0x00600000)) >>
21)
) {
1482 case 0:
1483 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
1484 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE00x0000001f;
1485 break;
1486 case 1:
1487 desc->ds_us.tx.ts_rate =
1488 AR5K_REG_MS(tx_desc->tx_control_3,(((uint32_t)(tx_desc->tx_control_3) & (0x000003e0)) >>
5)
1489 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1)(((uint32_t)(tx_desc->tx_control_3) & (0x000003e0)) >>
5)
;
1490 desc->ds_us.tx.ts_longretry +=
1491 AR5K_REG_MS(tx_desc->tx_control_2,(((uint32_t)(tx_desc->tx_control_2) & (0x00f00000)) >>
20)
1492 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1)(((uint32_t)(tx_desc->tx_control_2) & (0x00f00000)) >>
20)
;
1493 break;
1494 case 2:
1495 desc->ds_us.tx.ts_rate =
1496 AR5K_REG_MS(tx_desc->tx_control_3,(((uint32_t)(tx_desc->tx_control_3) & (0x00007c00)) >>
10)
1497 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2)(((uint32_t)(tx_desc->tx_control_3) & (0x00007c00)) >>
10)
;
1498 desc->ds_us.tx.ts_longretry +=
1499 AR5K_REG_MS(tx_desc->tx_control_2,(((uint32_t)(tx_desc->tx_control_2) & (0x0f000000)) >>
24)
1500 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2)(((uint32_t)(tx_desc->tx_control_2) & (0x0f000000)) >>
24)
;
1501 break;
1502 case 3:
1503 desc->ds_us.tx.ts_rate =
1504 AR5K_REG_MS(tx_desc->tx_control_3,(((uint32_t)(tx_desc->tx_control_3) & (0x000f8000)) >>
15)
1505 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3)(((uint32_t)(tx_desc->tx_control_3) & (0x000f8000)) >>
15)
;
1506 desc->ds_us.tx.ts_longretry +=
1507 AR5K_REG_MS(tx_desc->tx_control_2,(((uint32_t)(tx_desc->tx_control_2) & (0xf0000000)) >>
28)
1508 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3)(((uint32_t)(tx_desc->tx_control_2) & (0xf0000000)) >>
28)
;
1509 break;
1510 }
1511
1512 if ((tx_status->tx_status_0 &
1513 AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK0x00000001) == 0) {
1514 if (tx_status->tx_status_0 &
1515 AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES0x00000002)
1516 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY0x01;
1517
1518 if (tx_status->tx_status_0 &
1519 AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN0x00000004)
1520 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO0x04;
1521
1522 if (tx_status->tx_status_0 &
1523 AR5K_AR5212_DESC_TX_STATUS0_FILTERED0x00000008)
1524 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT0x02;
1525 }
1526
1527 return (HAL_OK0);
1528}
1529
1530HAL_BOOL
1531ar5k_ar5212_has_veol(struct ath_hal *hal)
1532{
1533 return (AH_TRUE);
1534}
1535
1536/*
1537 * Receive functions
1538 */
1539
1540u_int32_t
1541ar5k_ar5212_get_rx_buf(struct ath_hal *hal)
1542{
1543 return (AR5K_REG_READ(AR5K_AR5212_RXDP)((hal->ah_st)->read_4((hal->ah_sh), ((0x000c)))));
1544}
1545
1546void
1547ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
1548{
1549 AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr)((hal->ah_st)->write_4((hal->ah_sh), ((0x000c)), ((phys_addr
))))
;
1550}
1551
1552void
1553ar5k_ar5212_start_rx(struct ath_hal *hal)
1554{
1555 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0008)), ((0x00000004
))))
;
1556}
1557
1558HAL_BOOL
1559ar5k_ar5212_stop_rx_dma(struct ath_hal *hal)
1560{
1561 int i;
1562
1563 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXD)((hal->ah_st)->write_4((hal->ah_sh), ((0x0008)), ((0x00000020
))))
;
1564
1565 /*
1566 * It may take some time to disable the DMA receive unit
1567 */
1568 for (i = 2000;
1569 i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR)((hal->ah_st)->read_4((hal->ah_sh), ((0x0008)))) & AR5K_AR5212_CR_RXE0x00000004) != 0;
1570 i--)
1571 AR5K_DELAY(10)(*delay_func)(10);
1572
1573 return (i > 0 ? AH_TRUE : AH_FALSE);
1574}
1575
1576void
1577ar5k_ar5212_start_rx_pcu(struct ath_hal *hal)
1578{
1579 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX)((hal->ah_st)->write_4((hal->ah_sh), ((0x8048)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8048)))) &
~ (0x00000020)))))
;
1580}
1581
1582void
1583ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal)
1584{
1585 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX)((hal->ah_st)->write_4((hal->ah_sh), ((0x8048)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8048)))) | (0x00000020
)))))
;
1586}
1587
1588void
1589ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
1590 u_int32_t filter1)
1591{
1592 /* Set the multicast filter */
1593 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0)((hal->ah_st)->write_4((hal->ah_sh), ((0x8040)), ((filter0
))))
;
1594 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1)((hal->ah_st)->write_4((hal->ah_sh), ((0x8044)), ((filter1
))))
;
1595}
1596
1597HAL_BOOL
1598ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
1599{
1600 if (index >= 64) {
1601 return (AH_FALSE);
1602 } else if (index >= 32) {
1603 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1,((hal->ah_st)->write_4((hal->ah_sh), ((0x8044)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8044)))) | ((
1 << (index - 32)))))))
1604 (1 << (index - 32)))((hal->ah_st)->write_4((hal->ah_sh), ((0x8044)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8044)))) | ((
1 << (index - 32)))))))
;
1605 } else {
1606 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL0,((hal->ah_st)->write_4((hal->ah_sh), ((0x8040)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8040)))) | ((
1 << index))))))
1607 (1 << index))((hal->ah_st)->write_4((hal->ah_sh), ((0x8040)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8040)))) | ((
1 << index))))))
;
1608 }
1609
1610 return (AH_TRUE);
1611}
1612
1613HAL_BOOL
1614ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
1615{
1616
1617 if (index >= 64) {
1618 return (AH_FALSE);
1619 } else if (index >= 32) {
1620 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL1,((hal->ah_st)->write_4((hal->ah_sh), ((0x8044)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8044)))) &
~ ((1 << (index - 32)))))))
1621 (1 << (index - 32)))((hal->ah_st)->write_4((hal->ah_sh), ((0x8044)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8044)))) &
~ ((1 << (index - 32)))))))
;
1622 } else {
1623 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL0,((hal->ah_st)->write_4((hal->ah_sh), ((0x8040)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8040)))) &
~ ((1 << index))))))
1624 (1 << index))((hal->ah_st)->write_4((hal->ah_sh), ((0x8040)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8040)))) &
~ ((1 << index))))))
;
1625 }
1626
1627 return (AH_TRUE);
1628}
1629
1630u_int32_t
1631ar5k_ar5212_get_rx_filter(struct ath_hal *hal)
1632{
1633 u_int32_t data, filter = 0;
1634
1635 filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER)((hal->ah_st)->read_4((hal->ah_sh), ((0x803c))));
1636 data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL)((hal->ah_st)->read_4((hal->ah_sh), ((0x810c))));
1637
1638 if (data & AR5K_AR5212_PHY_ERR_FIL_RADAR0x00000020)
1639 filter |= HAL_RX_FILTER_PHYRADAR0x00000200;
1640 if (data & (AR5K_AR5212_PHY_ERR_FIL_OFDM0x00020000 |
1641 AR5K_AR5212_PHY_ERR_FIL_CCK0x02000000))
1642 filter |= HAL_RX_FILTER_PHYERR0x00000100;
1643
1644 return (filter);
1645}
1646
1647void
1648ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
1649{
1650 u_int32_t data = 0;
1651
1652 if (filter & HAL_RX_FILTER_PHYRADAR0x00000200)
1653 data |= AR5K_AR5212_PHY_ERR_FIL_RADAR0x00000020;
1654 if (filter & HAL_RX_FILTER_PHYERR0x00000100)
1655 data |= AR5K_AR5212_PHY_ERR_FIL_OFDM0x00020000 |
1656 AR5K_AR5212_PHY_ERR_FIL_CCK0x02000000;
1657
1658 if (data) {
1659 AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) | (0x00000010
)))))
1660 AR5K_AR5212_RXCFG_ZLFDMA)((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) | (0x00000010
)))))
;
1661 } else {
1662 AR5K_REG_DISABLE_BITS(AR5K_AR5212_RXCFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) &
~ (0x00000010)))))
1663 AR5K_AR5212_RXCFG_ZLFDMA)((hal->ah_st)->write_4((hal->ah_sh), ((0x0034)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x0034)))) &
~ (0x00000010)))))
;
1664 }
1665
1666 AR5K_REG_WRITE(AR5K_AR5212_RX_FILTER, filter & 0xff)((hal->ah_st)->write_4((hal->ah_sh), ((0x803c)), ((filter
& 0xff))))
;
1667 AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data)((hal->ah_st)->write_4((hal->ah_sh), ((0x810c)), ((data
))))
;
1668}
1669
1670HAL_BOOL
1671ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
1672 u_int32_t size, u_int flags)
1673{
1674 struct ar5k_ar5212_rx_desc *rx_desc;
1675
1676 rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0;
1677
1678 if ((rx_desc->rx_control_1 = (size &
1679 AR5K_AR5212_DESC_RX_CTL1_BUF_LEN0x00000fff)) != size)
1680 return (AH_FALSE);
1681
1682 if (flags & HAL_RXDESC_INTREQ0x0020)
1683 rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ0x00002000;
1684
1685 return (AH_TRUE);
1686}
1687
1688HAL_STATUS
1689ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
1690 u_int32_t phys_addr, struct ath_desc *next)
1691{
1692 struct ar5k_ar5212_rx_status *rx_status;
1693 struct ar5k_ar5212_rx_error *rx_err;
1694
1695 rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0];
1696
1697 /* Overlay on error */
1698 rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0];
1699
1700 /* No frame received / not ready */
1701 if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE0x00000001) == 0)
1702 return (HAL_EINPROGRESS36);
1703
1704 /*
1705 * Frame receive status
1706 */
1707 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
1708 AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN0x00000fff;
1709 desc->ds_us.rx.rs_rssi =
1710 AR5K_REG_MS(rx_status->rx_status_0,(((uint32_t)(rx_status->rx_status_0) & (0x0ff00000)) >>
20)
1711 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL)(((uint32_t)(rx_status->rx_status_0) & (0x0ff00000)) >>
20)
;
1712 desc->ds_us.rx.rs_rate =
1713 AR5K_REG_MS(rx_status->rx_status_0,(((uint32_t)(rx_status->rx_status_0) & (0x000f8000)) >>
15)
1714 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE)(((uint32_t)(rx_status->rx_status_0) & (0x000f8000)) >>
15)
;
1715 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
1716 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA0xf0000000;
1717 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
1718 AR5K_AR5212_DESC_RX_STATUS0_MORE0x00001000;
1719 desc->ds_us.rx.rs_tstamp =
1720 AR5K_REG_MS(rx_status->rx_status_1,(((uint32_t)(rx_status->rx_status_1) & (0x7fff0000)) >>
16)
1721 AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP)(((uint32_t)(rx_status->rx_status_1) & (0x7fff0000)) >>
16)
;
1722 desc->ds_us.rx.rs_status = 0;
1723
1724 /*
1725 * Key table status
1726 */
1727 if (rx_status->rx_status_1 &
1728 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID0x00000100) {
1729 desc->ds_us.rx.rs_keyix =
1730 AR5K_REG_MS(rx_status->rx_status_1,(((uint32_t)(rx_status->rx_status_1) & (0x0000fe00)) >>
9)
1731 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX)(((uint32_t)(rx_status->rx_status_1) & (0x0000fe00)) >>
9)
;
1732 } else {
1733 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID((u_int8_t) - 1);
1734 }
1735
1736 /*
1737 * Receive/descriptor errors
1738 */
1739 if ((rx_status->rx_status_1 &
1740 AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK0x00000002) == 0) {
1741 if (rx_status->rx_status_1 &
1742 AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR0x00000004)
1743 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC0x01;
1744
1745 if (rx_status->rx_status_1 &
1746 AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR0x00000010) {
1747 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY0x02;
1748 desc->ds_us.rx.rs_phyerr =
1749 AR5K_REG_MS(rx_err->rx_error_1,(((uint32_t)(rx_err->rx_error_1) & (0x0000ff00)) >>
8)
1750 AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE)(((uint32_t)(rx_err->rx_error_1) & (0x0000ff00)) >>
8)
;
1751 }
1752
1753 if (rx_status->rx_status_1 &
1754 AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR0x00000008)
1755 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT0x08;
1756
1757 if (rx_status->rx_status_1 &
1758 AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR0x00000020)
1759 desc->ds_us.rx.rs_status |= HAL_RXERR_MIC0x10;
1760 }
1761
1762 return (HAL_OK0);
1763}
1764
1765void
1766ar5k_ar5212_set_rx_signal(struct ath_hal *hal)
1767{
1768 /* Signal state monitoring is not yet supported */
1769}
1770
1771/*
1772 * Misc functions
1773 */
1774
1775void
1776ar5k_ar5212_dump_state(struct ath_hal *hal)
1777{
1778#ifdef AR5K_DEBUG
1779#define AR5K_PRINT_REGISTER(_x) \
1780 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x)((hal->ah_st)->read_4((hal->ah_sh), ((AR5K_AR5212_##
_x))))
);
1781
1782 printf("MAC registers:\n");
1783 AR5K_PRINT_REGISTER(CR);
1784 AR5K_PRINT_REGISTER(CFG);
1785 AR5K_PRINT_REGISTER(IER);
1786 AR5K_PRINT_REGISTER(TXCFG);
1787 AR5K_PRINT_REGISTER(RXCFG);
1788 AR5K_PRINT_REGISTER(MIBC);
1789 AR5K_PRINT_REGISTER(TOPS);
1790 AR5K_PRINT_REGISTER(RXNOFRM);
1791 AR5K_PRINT_REGISTER(RPGTO);
1792 AR5K_PRINT_REGISTER(RFCNT);
1793 AR5K_PRINT_REGISTER(MISC);
1794 AR5K_PRINT_REGISTER(PISR);
1795 AR5K_PRINT_REGISTER(SISR0);
1796 AR5K_PRINT_REGISTER(SISR1);
1797 AR5K_PRINT_REGISTER(SISR3);
1798 AR5K_PRINT_REGISTER(SISR4);
1799 AR5K_PRINT_REGISTER(DCM_ADDR);
1800 AR5K_PRINT_REGISTER(DCM_DATA);
1801 AR5K_PRINT_REGISTER(DCCFG);
1802 AR5K_PRINT_REGISTER(CCFG);
1803 AR5K_PRINT_REGISTER(CCFG_CUP);
1804 AR5K_PRINT_REGISTER(CPC0);
1805 AR5K_PRINT_REGISTER(CPC1);
1806 AR5K_PRINT_REGISTER(CPC2);
1807 AR5K_PRINT_REGISTER(CPCORN);
1808 AR5K_PRINT_REGISTER(QCU_TXE);
1809 AR5K_PRINT_REGISTER(QCU_TXD);
1810 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS);
1811 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT);
1812 AR5K_PRINT_REGISTER(DCU_FP);
1813 AR5K_PRINT_REGISTER(DCU_TXP);
1814 AR5K_PRINT_REGISTER(DCU_TX_FILTER);
1815 AR5K_PRINT_REGISTER(RC);
1816 AR5K_PRINT_REGISTER(SCR);
1817 AR5K_PRINT_REGISTER(INTPEND);
1818 AR5K_PRINT_REGISTER(PCICFG);
1819 AR5K_PRINT_REGISTER(GPIOCR);
1820 AR5K_PRINT_REGISTER(GPIODO);
1821 AR5K_PRINT_REGISTER(SREV);
1822 AR5K_PRINT_REGISTER(EEPROM_BASE);
1823 AR5K_PRINT_REGISTER(EEPROM_DATA);
1824 AR5K_PRINT_REGISTER(EEPROM_CMD);
1825 AR5K_PRINT_REGISTER(EEPROM_CFG);
1826 AR5K_PRINT_REGISTER(PCU_MIN);
1827 AR5K_PRINT_REGISTER(STA_ID0);
1828 AR5K_PRINT_REGISTER(STA_ID1);
1829 AR5K_PRINT_REGISTER(BSS_ID0);
1830 AR5K_PRINT_REGISTER(SLOT_TIME);
1831 AR5K_PRINT_REGISTER(TIME_OUT);
1832 AR5K_PRINT_REGISTER(RSSI_THR);
1833 AR5K_PRINT_REGISTER(BEACON);
1834 AR5K_PRINT_REGISTER(CFP_PERIOD);
1835 AR5K_PRINT_REGISTER(TIMER0);
1836 AR5K_PRINT_REGISTER(TIMER2);
1837 AR5K_PRINT_REGISTER(TIMER3);
1838 AR5K_PRINT_REGISTER(CFP_DUR);
1839 AR5K_PRINT_REGISTER(MCAST_FIL0);
1840 AR5K_PRINT_REGISTER(MCAST_FIL1);
1841 AR5K_PRINT_REGISTER(DIAG_SW);
1842 AR5K_PRINT_REGISTER(TSF_U32);
1843 AR5K_PRINT_REGISTER(ADDAC_TEST);
1844 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA);
1845 AR5K_PRINT_REGISTER(LAST_TSTP);
1846 AR5K_PRINT_REGISTER(NAV);
1847 AR5K_PRINT_REGISTER(RTS_OK);
1848 AR5K_PRINT_REGISTER(ACK_FAIL);
1849 AR5K_PRINT_REGISTER(FCS_FAIL);
1850 AR5K_PRINT_REGISTER(BEACON_CNT);
1851 AR5K_PRINT_REGISTER(TSF_PARM);
1852 AR5K_PRINT_REGISTER(RATE_DUR_0);
1853 AR5K_PRINT_REGISTER(KEYTABLE_0);
1854 printf("\n");
1855
1856 printf("PHY registers:\n");
1857 AR5K_PRINT_REGISTER(PHY_TURBO);
1858 AR5K_PRINT_REGISTER(PHY_AGC);
1859 AR5K_PRINT_REGISTER(PHY_TIMING_3);
1860 AR5K_PRINT_REGISTER(PHY_CHIP_ID);
1861 AR5K_PRINT_REGISTER(PHY_AGCCTL);
1862 AR5K_PRINT_REGISTER(PHY_NF);
1863 AR5K_PRINT_REGISTER(PHY_SCR);
1864 AR5K_PRINT_REGISTER(PHY_SLMT);
1865 AR5K_PRINT_REGISTER(PHY_SCAL);
1866 AR5K_PRINT_REGISTER(PHY_RX_DELAY);
1867 AR5K_PRINT_REGISTER(PHY_IQ);
1868 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE);
1869 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1);
1870 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2);
1871 AR5K_PRINT_REGISTER(PHY_FC);
1872 AR5K_PRINT_REGISTER(PHY_RADAR);
1873 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0);
1874 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1);
1875 printf("\n");
1876#endif
1877}
1878
1879HAL_BOOL
1880ar5k_ar5212_get_diag_state(struct ath_hal *hal, int id, void **device,
1881 u_int *size)
1882{
1883 /*
1884 * We'll ignore this right now. This seems to be some kind of an obscure
1885 * debugging interface for the binary-only HAL.
1886 */
1887 return (AH_FALSE);
1888}
1889
1890void
1891ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
1892{
1893 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN6);
1894}
1895
1896HAL_BOOL
1897ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
1898{
1899 u_int32_t low_id, high_id;
1900
1901 /* Set new station ID */
1902 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN6);
1903
1904 low_id = AR5K_LOW_ID(mac)( (mac)[0] | (mac)[1] << 8 | (mac)[2] << 16 | (mac
)[3] << 24 )
;
1905 high_id = 0x0000ffff & AR5K_HIGH_ID(mac)((mac)[4] | (mac)[5] << 8);
1906
1907 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x8000)), ((low_id
))))
;
1908 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), ((high_id
))))
;
1909
1910 return (AH_TRUE);
1911}
1912
1913HAL_BOOL
1914ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
1915 HAL_STATUS *status)
1916{
1917 ieee80211_regdomain_t ieee_regdomain;
1918
1919 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain);
1920
1921 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
1922 &ieee_regdomain) == AH_TRUE) {
1923 *status = HAL_OK0;
1924 return (AH_TRUE);
1925 }
1926
1927 *status = EIO5;
1928
1929 return (AH_FALSE);
1930}
1931
1932void
1933ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
1934{
1935 u_int32_t led;
1936
1937 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PCICFG,((hal->ah_st)->write_4((hal->ah_sh), ((0x4010)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) &
~ (0x000e0000 | 0x00000060)))))
1938 AR5K_AR5212_PCICFG_LEDMODE | AR5K_AR5212_PCICFG_LED)((hal->ah_st)->write_4((hal->ah_sh), ((0x4010)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) &
~ (0x000e0000 | 0x00000060)))))
;
1939
1940 /*
1941 * Some blinking values, define at your wish
1942 */
1943 switch (state) {
1944 case IEEE80211_S_SCAN:
1945 case IEEE80211_S_AUTH:
1946 led = AR5K_AR5212_PCICFG_LEDMODE_PROP0x00000000 |
1947 AR5K_AR5212_PCICFG_LED_PEND0x00000020;
1948 break;
1949
1950 case IEEE80211_S_INIT:
1951 led = AR5K_AR5212_PCICFG_LEDMODE_PROP0x00000000 |
1952 AR5K_AR5212_PCICFG_LED_NONE0x00000000;
1953 break;
1954
1955 case IEEE80211_S_ASSOC:
1956 case IEEE80211_S_RUN:
1957 led = AR5K_AR5212_PCICFG_LEDMODE_PROP0x00000000 |
1958 AR5K_AR5212_PCICFG_LED_ASSOC0x00000040;
1959 break;
1960
1961 default:
1962 led = AR5K_AR5212_PCICFG_LEDMODE_PROM0x00020000 |
1963 AR5K_AR5212_PCICFG_LED_NONE0x00000000;
1964 break;
1965 }
1966
1967 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, led)((hal->ah_st)->write_4((hal->ah_sh), ((0x4010)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) | (led
)))))
;
1968}
1969
1970void
1971ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
1972 u_int16_t assoc_id, u_int16_t tim_offset)
1973{
1974 u_int32_t low_id, high_id;
1975
1976 /*
1977 * Set simple BSSID mask
1978 */
1979 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, 0xfffffff)((hal->ah_st)->write_4((hal->ah_sh), ((0x80e0)), ((0xfffffff
))))
;
1980 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, 0xfffffff)((hal->ah_st)->write_4((hal->ah_sh), ((0x80e4)), ((0xfffffff
))))
;
1981
1982 /*
1983 * Set BSSID which triggers the "SME Join" operation
1984 */
1985 low_id = AR5K_LOW_ID(bssid)( (bssid)[0] | (bssid)[1] << 8 | (bssid)[2] << 16
| (bssid)[3] << 24 )
;
1986 high_id = AR5K_HIGH_ID(bssid)((bssid)[4] | (bssid)[5] << 8);
1987 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID0, low_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x8008)), ((low_id
))))
;
1988 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID1, high_id |((hal->ah_st)->write_4((hal->ah_sh), ((0x800c)), ((high_id
| ((assoc_id & 0x3fff) << 16)))))
1989 ((assoc_id & 0x3fff) << AR5K_AR5212_BSS_ID1_AID_S))((hal->ah_st)->write_4((hal->ah_sh), ((0x800c)), ((high_id
| ((assoc_id & 0x3fff) << 16)))))
;
1990 bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN6);
1991
1992 if (assoc_id == 0) {
1993 ar5k_ar5212_disable_pspoll(hal);
1994 return;
1995 }
1996
1997 AR5K_REG_WRITE(AR5K_AR5212_BEACON,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
1998 (AR5K_REG_READ(AR5K_AR5212_BEACON) &((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
1999 ~AR5K_AR5212_BEACON_TIM) |((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
2000 (((tim_offset ? tim_offset + 4 : 0) <<((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
2001 AR5K_AR5212_BEACON_TIM_S) &((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
2002 AR5K_AR5212_BEACON_TIM))((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~0x007f0000) | (((tim_offset ? tim_offset + 4 : 0) << 16
) & 0x007f0000)))))
;
2003
2004 ar5k_ar5212_enable_pspoll(hal, NULL((void *)0), 0);
2005}
2006
2007HAL_BOOL
2008ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
2009{
2010 u_int32_t low_id, high_id;
2011
2012 low_id = AR5K_LOW_ID(mask)( (mask)[0] | (mask)[1] << 8 | (mask)[2] << 16 | (
mask)[3] << 24 )
;
2013 high_id = 0x0000ffff & AR5K_HIGH_ID(mask)((mask)[4] | (mask)[5] << 8);
2014
2015 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, low_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x80e0)), ((low_id
))))
;
2016 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, high_id)((hal->ah_st)->write_4((hal->ah_sh), ((0x80e4)), ((high_id
))))
;
2017
2018 return (AH_TRUE);
2019}
2020
2021HAL_BOOL
2022ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
2023{
2024 if (gpio > AR5K_AR5212_NUM_GPIO6)
2025 return (AH_FALSE);
2026
2027 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR,((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (3 << ((gpio) * 2))))))
2028 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (3 << ((gpio) * 2))))))
2029 | AR5K_AR5212_GPIOCR_ALL(gpio))((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (3 << ((gpio) * 2))))))
;
2030
2031 return (AH_TRUE);
2032}
2033
2034HAL_BOOL
2035ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
2036{
2037 if (gpio > AR5K_AR5212_NUM_GPIO6)
2038 return (AH_FALSE);
2039
2040 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR,((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (0 << ((gpio) * 2))))))
2041 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (0 << ((gpio) * 2))))))
2042 | AR5K_AR5212_GPIOCR_NONE(gpio))((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
~ (3 << ((gpio) * 2))) | (0 << ((gpio) * 2))))))
;
2043
2044 return (AH_TRUE);
2045}
2046
2047u_int32_t
2048ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio)
2049{
2050 if (gpio > AR5K_AR5212_NUM_GPIO6)
2051 return (0xffffffff);
2052
2053 /* GPIO input magic */
2054 return (((AR5K_REG_READ(AR5K_AR5212_GPIODI)((hal->ah_st)->read_4((hal->ah_sh), ((0x401c)))) &
2055 AR5K_AR5212_GPIODI_M0x0000002f) >> gpio) & 0x1);
2056}
2057
2058HAL_BOOL
2059ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
2060{
2061 u_int32_t data;
2062
2063 if (gpio > AR5K_AR5212_NUM_GPIO6)
2064 return (0xffffffff);
2065
2066 /* GPIO output magic */
2067 data = AR5K_REG_READ(AR5K_AR5212_GPIODO)((hal->ah_st)->read_4((hal->ah_sh), ((0x4018))));
2068
2069 data &= ~(1 << gpio);
2070 data |= (val&1) << gpio;
2071
2072 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data)((hal->ah_st)->write_4((hal->ah_sh), ((0x4018)), ((data
))))
;
2073
2074 return (AH_TRUE);
2075}
2076
2077void
2078ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio,
2079 u_int32_t interrupt_level)
2080{
2081 u_int32_t data;
2082
2083 if (gpio > AR5K_AR5212_NUM_GPIO6)
2084 return;
2085
2086 /*
2087 * Set the GPIO interrupt
2088 */
2089 data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR)((hal->ah_st)->read_4((hal->ah_sh), ((0x4014)))) &
2090 ~(AR5K_AR5212_GPIOCR_INT_SEL(gpio)((gpio) << 12) | AR5K_AR5212_GPIOCR_INT_SELH0x00010000 |
2091 AR5K_AR5212_GPIOCR_INT_ENA0x00008000 | AR5K_AR5212_GPIOCR_ALL(gpio)(3 << ((gpio) * 2)))) |
2092 (AR5K_AR5212_GPIOCR_INT_SEL(gpio)((gpio) << 12) | AR5K_AR5212_GPIOCR_INT_ENA0x00008000);
2093
2094 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR,((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), ((interrupt_level
? data : (data | 0x00010000)))))
2095 interrupt_level ? data : (data | AR5K_AR5212_GPIOCR_INT_SELH))((hal->ah_st)->write_4((hal->ah_sh), ((0x4014)), ((interrupt_level
? data : (data | 0x00010000)))))
;
2096
2097 hal->ah_imr |= AR5K_AR5212_PIMR_GPIO0x01000000;
2098
2099 /* Enable GPIO interrupts */
2100 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_AR5212_PIMR_GPIO)((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00a0)))) | (0x01000000
)))))
;
2101}
2102
2103u_int32_t
2104ar5k_ar5212_get_tsf32(struct ath_hal *hal)
2105{
2106 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32)((hal->ah_st)->read_4((hal->ah_sh), ((0x804c)))));
2107}
2108
2109u_int64_t
2110ar5k_ar5212_get_tsf64(struct ath_hal *hal)
2111{
2112 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32)((hal->ah_st)->read_4((hal->ah_sh), ((0x8050))));
2113
2114 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32)((hal->ah_st)->read_4((hal->ah_sh), ((0x804c)))) | (tsf << 32));
2115}
2116
2117void
2118ar5k_ar5212_reset_tsf(struct ath_hal *hal)
2119{
2120 AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) | (0x01000000
)))))
2121 AR5K_AR5212_BEACON_RESET_TSF)((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) | (0x01000000
)))))
;
2122}
2123
2124u_int16_t
2125ar5k_ar5212_get_regdomain(struct ath_hal *hal)
2126{
2127 return (ar5k_get_regdomain(hal));
2128}
2129
2130HAL_BOOL
2131ar5k_ar5212_detect_card_present(struct ath_hal *hal)
2132{
2133 u_int16_t magic;
2134
2135 /*
2136 * Checking the EEPROM's magic value could be an indication
2137 * if the card is still present. I didn't find another suitable
2138 * way to do this.
2139 */
2140 if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC0x003d, &magic) != 0)
2141 return (AH_FALSE);
2142
2143 return (magic == AR5K_EEPROM_MAGIC_VALUE0x5aa5 ? AH_TRUE : AH_FALSE);
2144}
2145
2146void
2147ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
2148{
2149 /* Read-And-Clear */
2150 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL)((hal->ah_st)->read_4((hal->ah_sh), ((0x8090))));
2151 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL)((hal->ah_st)->read_4((hal->ah_sh), ((0x808c))));
2152 statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK)((hal->ah_st)->read_4((hal->ah_sh), ((0x8088))));
2153 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL)((hal->ah_st)->read_4((hal->ah_sh), ((0x8094))));
2154 statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT)((hal->ah_st)->read_4((hal->ah_sh), ((0x8098))));
2155
2156 /* Reset profile count registers */
2157 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_TX, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x80ec)), ((0
))))
;
2158 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RX, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x80f0)), ((0
))))
;
2159 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RXCLR, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x80f4)), ((0
))))
;
2160 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_CYCLE, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x80f8)), ((0
))))
;
2161}
2162
2163HAL_RFGAIN
2164ar5k_ar5212_get_rf_gain(struct ath_hal *hal)
2165{
2166 u_int32_t data, type;
2167
2168 if ((hal->ah_rf_banks == NULL((void *)0)) || (!hal->ah_gain.g_active))
2169 return (HAL_RFGAIN_INACTIVE);
2170
2171 if (hal->ah_rf_gain != HAL_RFGAIN_READ_REQUESTED)
2172 goto done;
2173
2174 data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE)((hal->ah_st)->read_4((hal->ah_sh), ((0x9930))));
2175
2176 if (!(data & AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT0x00008000)) {
2177 hal->ah_gain.g_current =
2178 data >> AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S25;
2179 type = AR5K_REG_MS(data, AR5K_AR5212_PHY_PAPD_PROBE_TYPE)(((uint32_t)(data) & (0x01800000)) >> 23);
2180
2181 if (type == AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK2)
2182 hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR5;
2183
2184 if (hal->ah_radio >= AR5K_AR5112) {
2185 ar5k_rfregs_gainf_corr(hal);
2186 hal->ah_gain.g_current =
2187 hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ?
2188 (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) :
2189 0;
2190 }
2191
2192 if (ar5k_rfregs_gain_readback(hal) &&
2193 AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain)((&hal->ah_gain)->g_current <= (&hal->ah_gain
)->g_low || (&hal->ah_gain)->g_current >= (&
hal->ah_gain)->g_high)
&&
2194 ar5k_rfregs_gain_adjust(hal))
2195 hal->ah_rf_gain = HAL_RFGAIN_NEED_CHANGE;
2196 }
2197
2198 done:
2199 return (hal->ah_rf_gain);
2200}
2201
2202HAL_BOOL
2203ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time)
2204{
2205 if (slot_time < HAL_SLOT_TIME_9396 || slot_time > HAL_SLOT_TIME_MAX0xffff)
2206 return (AH_FALSE);
2207
2208 AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time)((hal->ah_st)->write_4((hal->ah_sh), ((0x1070)), ((slot_time
))))
;
2209
2210 return (AH_TRUE);
2211}
2212
2213u_int
2214ar5k_ar5212_get_slot_time(struct ath_hal *hal)
2215{
2216 return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT)((hal->ah_st)->read_4((hal->ah_sh), ((0x1070)))) & 0xffff);
2217}
2218
2219HAL_BOOL
2220ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout)
2221{
2222 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK)(((uint32_t)(0xffffffff) & (0x00001fff)) >> 0))
2223 <= timeout)
2224 return (AH_FALSE);
2225
2226 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_ACK,((hal->ah_st)->write_4((hal->ah_sh), ((0x8014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8014)))) &
~ (0x00001fff)) | (((ar5k_htoclock(timeout)) << 0) &
(0x00001fff))))))
2227 ar5k_htoclock(timeout))((hal->ah_st)->write_4((hal->ah_sh), ((0x8014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8014)))) &
~ (0x00001fff)) | (((ar5k_htoclock(timeout)) << 0) &
(0x00001fff))))))
;
2228
2229 return (AH_TRUE);
2230}
2231
2232u_int
2233ar5k_ar5212_get_ack_timeout(struct ath_hal *hal)
2234{
2235 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x8014
))))) & (0x00001fff)) >> 0)
2236 AR5K_AR5212_TIME_OUT_ACK)(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x8014
))))) & (0x00001fff)) >> 0)
));
2237}
2238
2239HAL_BOOL
2240ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout)
2241{
2242 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS)(((uint32_t)(0xffffffff) & (0x1fff0000)) >> 16))
2243 <= timeout)
2244 return (AH_FALSE);
2245
2246 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_CTS,((hal->ah_st)->write_4((hal->ah_sh), ((0x8014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8014)))) &
~ (0x1fff0000)) | (((ar5k_htoclock(timeout)) << 16) &
(0x1fff0000))))))
2247 ar5k_htoclock(timeout))((hal->ah_st)->write_4((hal->ah_sh), ((0x8014)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8014)))) &
~ (0x1fff0000)) | (((ar5k_htoclock(timeout)) << 16) &
(0x1fff0000))))))
;
2248
2249 return (AH_TRUE);
2250}
2251
2252u_int
2253ar5k_ar5212_get_cts_timeout(struct ath_hal *hal)
2254{
2255 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x8014
))))) & (0x1fff0000)) >> 16)
2256 AR5K_AR5212_TIME_OUT_CTS)(((uint32_t)(((hal->ah_st)->read_4((hal->ah_sh), ((0x8014
))))) & (0x1fff0000)) >> 16)
));
2257}
2258
2259/*
2260 * Key table (WEP) functions
2261 */
2262
2263HAL_BOOL
2264ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
2265{
2266 /*
2267 * The AR5212 only supports WEP
2268 */
2269 if (cipher == HAL_CIPHER_WEP)
2270 return (AH_TRUE);
2271
2272 return (AH_FALSE);
2273}
2274
2275u_int32_t
2276ar5k_ar5212_get_keycache_size(struct ath_hal *hal)
2277{
2278 return (AR5K_AR5212_KEYCACHE_SIZE8);
2279}
2280
2281HAL_BOOL
2282ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry)
2283{
2284 int i;
2285
2286 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE)do { if (entry >= 128) return (AH_FALSE); } while (0);
2287
2288 for (i = 0; i < AR5K_AR5212_KEYCACHE_SIZE8; i++)
2289 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), 0)((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (i << 2)))), ((0))))
;
2290
2291 /* Set NULL encryption */
2292 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry),((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (5 << 2)))), ((0x00000007))))
2293 AR5K_AR5212_KEYTABLE_TYPE_NULL)((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (5 << 2)))), ((0x00000007))))
;
2294
2295 return (AH_FALSE);
2296}
2297
2298HAL_BOOL
2299ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry)
2300{
2301 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE)do { if (entry >= 128) return (AH_FALSE); } while (0);
2302
2303 /*
2304 * Check the validation flag at the end of the entry
2305 */
2306 if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry))((hal->ah_st)->read_4((hal->ah_sh), ((((0x8800 + ((entry
) << 5)) + (7 << 2))))))
&
2307 AR5K_AR5212_KEYTABLE_VALID0x00008000)
2308 return (AH_TRUE);
2309
2310 return (AH_FALSE);
2311}
2312
2313HAL_BOOL
2314ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry,
2315 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
2316{
2317 int i;
2318 u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE8 - 2];
2319
2320 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE)do { if (entry >= 128) return (AH_FALSE); } while (0);
2321
2322 bzero(&key_v, sizeof(key_v))__builtin_bzero((&key_v), (sizeof(key_v)));
2323
2324 switch (keyval->wk_len) {
2325 case AR5K_KEYVAL_LENGTH_405:
2326 bcopy(keyval->wk_key, &key_v[0], 4);
2327 bcopy(keyval->wk_key + 4, &key_v[1], 1);
2328 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_400x00000000;
2329 break;
2330
2331 case AR5K_KEYVAL_LENGTH_10413:
2332 bcopy(keyval->wk_key, &key_v[0], 4);
2333 bcopy(keyval->wk_key + 4, &key_v[1], 2);
2334 bcopy(keyval->wk_key + 6, &key_v[2], 4);
2335 bcopy(keyval->wk_key + 10, &key_v[3], 2);
2336 bcopy(keyval->wk_key + 12, &key_v[4], 1);
2337 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_1040x00000001;
2338 break;
2339
2340 case AR5K_KEYVAL_LENGTH_12816:
2341 bcopy(keyval->wk_key, &key_v[0], 4);
2342 bcopy(keyval->wk_key + 4, &key_v[1], 2);
2343 bcopy(keyval->wk_key + 6, &key_v[2], 4);
2344 bcopy(keyval->wk_key + 10, &key_v[3], 2);
2345 bcopy(keyval->wk_key + 12, &key_v[4], 4);
2346 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_1280x00000003;
2347 break;
2348
2349 default:
2350 /* Unsupported key length (not WEP40/104/128) */
2351 return (AH_FALSE);
2352 }
2353
2354 for (i = 0; i < nitems(key_v)(sizeof((key_v)) / sizeof((key_v)[0])); i++)
2355 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), key_v[i])((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (i << 2)))), ((key_v[i]))))
;
2356
2357 return (ar5k_ar5212_set_key_lladdr(hal, entry, mac));
2358}
2359
2360HAL_BOOL
2361ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
2362 const u_int8_t *mac)
2363{
2364 u_int32_t low_id, high_id;
2365 const u_int8_t *mac_v;
2366
2367 /*
2368 * Invalid entry (key table overflow)
2369 */
2370 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE)do { if (entry >= 128) return (AH_FALSE); } while (0);
2371
2372 /* MAC may be NULL if it's a broadcast key */
2373 mac_v = mac == NULL((void *)0) ? etherbroadcastaddr : mac;
2374
2375 low_id = AR5K_LOW_ID(mac_v)( (mac_v)[0] | (mac_v)[1] << 8 | (mac_v)[2] << 16
| (mac_v)[3] << 24 )
;
2376 high_id = AR5K_HIGH_ID(mac_v)((mac_v)[4] | (mac_v)[5] << 8) | AR5K_AR5212_KEYTABLE_VALID0x00008000;
2377
2378 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id)((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (6 << 2)))), ((low_id))))
;
2379 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id)((hal->ah_st)->write_4((hal->ah_sh), ((((0x8800 + ((
entry) << 5)) + (7 << 2)))), ((high_id))))
;
2380
2381 return (AH_TRUE);
2382}
2383
2384HAL_BOOL
2385ar5k_ar5212_softcrypto(struct ath_hal *hal, HAL_BOOL enable)
2386{
2387 u_int32_t bits;
2388 int i;
2389
2390 bits = AR5K_AR5212_DIAG_SW_DIS_ENC0x00000008 | AR5K_AR5212_DIAG_SW_DIS_DEC0x00000010;
2391 if (enable == AH_TRUE) {
2392 /* Disable the hardware crypto engine */
2393 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, bits)((hal->ah_st)->write_4((hal->ah_sh), ((0x8048)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8048)))) | (bits
)))))
;
2394 } else {
2395 /* Enable the hardware crypto engine */
2396 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, bits)((hal->ah_st)->write_4((hal->ah_sh), ((0x8048)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8048)))) &
~ (bits)))))
;
2397 }
2398
2399 /* Reset the key cache */
2400 for (i = 0; i < AR5K_AR5212_KEYTABLE_SIZE128; i++)
2401 ar5k_ar5212_reset_key(hal, i);
2402
2403 return (AH_TRUE);
2404}
2405
2406/*
2407 * warm reset MAC and PHY
2408 */
2409
2410HAL_BOOL
2411ar5k_ar5212_warm_reset(struct ath_hal *hal)
2412{
2413 u_int32_t flags;
2414
2415 flags = AR5K_AR5212_RC_PCU0x00000001 | AR5K_AR5212_RC_BB0x00000002;
2416 if (hal->ah_pci_express == AH_FALSE)
2417 flags |= AR5K_AR5212_RC_PCI0x00000010;
2418
2419 /* reset chipset and PCI device */
2420 if (ar5k_ar5212_nic_reset(hal, flags) == AH_FALSE)
2421 return (AH_FALSE);
2422
2423 /* wakeup */
2424 if (ar5k_ar5212_set_power(hal,
2425 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE)
2426 return (AH_FALSE);
2427
2428 /* reset chipset */
2429 if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE)
2430 return (AH_FALSE);
2431
2432 return (AH_TRUE);
2433}
2434
2435/*
2436 * Power management functions
2437 */
2438
2439HAL_BOOL
2440ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
2441 HAL_BOOL set_chip, u_int16_t sleep_duration)
2442{
2443 u_int32_t staid;
2444 int i;
2445
2446 staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1)((hal->ah_st)->read_4((hal->ah_sh), ((0x8004))));
2447
2448 switch (mode) {
2449 case HAL_PM_AUTO:
2450 staid &= ~AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA0x00200000;
2451 /* FALLTHROUGH */
2452 case HAL_PM_NETWORK_SLEEP:
2453 if (set_chip == AH_TRUE) {
2454 AR5K_REG_WRITE(AR5K_AR5212_SCR,((hal->ah_st)->write_4((hal->ah_sh), ((0x4004)), ((0x00030000
| sleep_duration))))
2455 AR5K_AR5212_SCR_SLE | sleep_duration)((hal->ah_st)->write_4((hal->ah_sh), ((0x4004)), ((0x00030000
| sleep_duration))))
;
2456 }
2457 staid |= AR5K_AR5212_STA_ID1_PWR_SV0x00040000;
2458 break;
2459
2460 case HAL_PM_FULL_SLEEP:
2461 if (set_chip == AH_TRUE)
2462 if (ar5k_ar5212_warm_reset(hal) == AH_FALSE)
2463 return (AH_FALSE);
2464 staid |= AR5K_AR5212_STA_ID1_PWR_SV0x00040000;
2465 break;
2466
2467 case HAL_PM_AWAKE:
2468 if (set_chip == AH_FALSE)
2469 goto commit;
2470
2471 AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE)((hal->ah_st)->write_4((hal->ah_sh), ((0x4004)), ((0x00000000
))))
;
2472
2473 for (i = 5000; i > 0; i--) {
2474 /* Check if the AR5212 did wake up */
2475 if ((AR5K_REG_READ(AR5K_AR5212_PCICFG)((hal->ah_st)->read_4((hal->ah_sh), ((0x4010)))) &
2476 AR5K_AR5212_PCICFG_SPWR_DN0x00010000) == 0)
2477 break;
2478
2479 /* Wait a bit and retry */
2480 AR5K_DELAY(200)(*delay_func)(200);
2481 AR5K_REG_WRITE(AR5K_AR5212_SCR,((hal->ah_st)->write_4((hal->ah_sh), ((0x4004)), ((0x00000000
))))
2482 AR5K_AR5212_SCR_SLE_WAKE)((hal->ah_st)->write_4((hal->ah_sh), ((0x4004)), ((0x00000000
))))
;
2483 }
2484
2485 /* Fail if the AR5212 didn't wake up */
2486 if (i <= 0)
2487 return (AH_FALSE);
2488
2489 staid &= ~AR5K_AR5212_STA_ID1_PWR_SV0x00040000;
2490 break;
2491
2492 default:
2493 return (AH_FALSE);
2494 }
2495
2496 commit:
2497 hal->ah_power_mode = mode;
2498
2499 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), ((staid
))))
;
2500
2501 return (AH_TRUE);
2502}
2503
2504HAL_POWER_MODE
2505ar5k_ar5212_get_power_mode(struct ath_hal *hal)
2506{
2507 return (hal->ah_power_mode);
2508}
2509
2510HAL_BOOL
2511ar5k_ar5212_query_pspoll_support(struct ath_hal *hal)
2512{
2513 /* nope */
2514 return (AH_FALSE);
2515}
2516
2517HAL_BOOL
2518ar5k_ar5212_init_pspoll(struct ath_hal *hal)
2519{
2520 /*
2521 * Not used on the AR5212
2522 */
2523 return (AH_FALSE);
2524}
2525
2526HAL_BOOL
2527ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
2528 u_int16_t assoc_id)
2529{
2530 return (AH_FALSE);
2531}
2532
2533HAL_BOOL
2534ar5k_ar5212_disable_pspoll(struct ath_hal *hal)
2535{
2536 return (AH_FALSE);
2537}
2538
2539/*
2540 * Beacon functions
2541 */
2542
2543void
2544ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
2545 u_int32_t interval)
2546{
2547 u_int32_t timer1, timer2, timer3;
2548
2549 /*
2550 * Set the additional timers by mode
2551 */
2552 switch (hal->ah_op_mode) {
2553 case HAL_M_STAIEEE80211_M_STA:
2554 timer1 = 0x0000ffff;
2555 timer2 = 0x0007ffff;
2556 break;
2557
2558 default:
2559 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP2) <<
2560 0x00000003;
2561 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP10) <<
2562 0x00000003;
2563 }
2564
2565 timer3 = next_beacon +
2566 (hal->ah_atim_window ? hal->ah_atim_window : 1);
2567
2568 /*
2569 * Enable all timers and set the beacon register
2570 * (next beacon, DMA beacon, software beacon, ATIM window time)
2571 */
2572 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, next_beacon)((hal->ah_st)->write_4((hal->ah_sh), ((0x8028)), ((next_beacon
))))
;
2573 AR5K_REG_WRITE(AR5K_AR5212_TIMER1, timer1)((hal->ah_st)->write_4((hal->ah_sh), ((0x802c)), ((timer1
))))
;
2574 AR5K_REG_WRITE(AR5K_AR5212_TIMER2, timer2)((hal->ah_st)->write_4((hal->ah_sh), ((0x8030)), ((timer2
))))
;
2575 AR5K_REG_WRITE(AR5K_AR5212_TIMER3, timer3)((hal->ah_st)->write_4((hal->ah_sh), ((0x8034)), ((timer3
))))
;
2576
2577 AR5K_REG_WRITE(AR5K_AR5212_BEACON, interval &((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), ((interval
& (0x0000ffff | 0x01000000 | 0x00800000)))))
2578 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_RESET_TSF |((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), ((interval
& (0x0000ffff | 0x01000000 | 0x00800000)))))
2579 AR5K_AR5212_BEACON_ENABLE))((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), ((interval
& (0x0000ffff | 0x01000000 | 0x00800000)))))
;
2580}
2581
2582void
2583ar5k_ar5212_set_beacon_timers(struct ath_hal *hal,
2584 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
2585 u_int32_t cfp_count)
2586{
2587 u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon;
2588
2589 /* Return on an invalid beacon state */
2590 if (state->bs_interval < 1)
2591 return;
2592
2593 interval = state->bs_intvalbs_interval;
2594 dtim = state->bs_dtimperiodbs_dtim_period;
2595
2596 /*
2597 * PCF support?
2598 */
2599 if (state->bs_cfp_period > 0) {
2600 /* Enable CFP mode and set the CFP and timer registers */
2601 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2602 state->bs_interval;
2603 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2604 state->bs_interval;
2605
2606 AR5K_REG_ENABLE_BITS(AR5K_AR5212_STA_ID1,((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) | (0x00100000
)))))
2607 AR5K_AR5212_STA_ID1_PCF)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) | (0x00100000
)))))
;
2608 AR5K_REG_WRITE(AR5K_AR5212_CFP_PERIOD, cfp_period)((hal->ah_st)->write_4((hal->ah_sh), ((0x8024)), ((cfp_period
))))
;
2609 AR5K_REG_WRITE(AR5K_AR5212_CFP_DUR, state->bs_cfp_max_duration)((hal->ah_st)->write_4((hal->ah_sh), ((0x8038)), ((state
->bs_cfp_max_duration))))
;
2610 AR5K_REG_WRITE(AR5K_AR5212_TIMER2,((hal->ah_st)->write_4((hal->ah_sh), ((0x8030)), (((
tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3))))
2611 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3)((hal->ah_st)->write_4((hal->ah_sh), ((0x8030)), (((
tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3))))
;
2612 } else {
2613 /* Disable PCF mode */
2614 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1,((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) &
~ (0x00100000)))))
2615 AR5K_AR5212_STA_ID1_PCF)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) &
~ (0x00100000)))))
;
2616 }
2617
2618 /*
2619 * Enable the beacon timer register
2620 */
2621 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, state->bs_next_beacon)((hal->ah_st)->write_4((hal->ah_sh), ((0x8028)), ((state
->bs_next_beacon))))
;
2622
2623 /*
2624 * Start the beacon timers
2625 */
2626 AR5K_REG_WRITE(AR5K_AR5212_BEACON,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
2627 (AR5K_REG_READ(AR5K_AR5212_BEACON) &~((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
2628 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_TIM)) |((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
2629 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
2630 AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
2631 AR5K_AR5212_BEACON_PERIOD))((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), (((
((hal->ah_st)->read_4((hal->ah_sh), ((0x8020)))) &
~ (0x0000ffff | 0x007f0000)) | (((uint32_t)(state->bs_tim_offset
? state->bs_tim_offset + 4 : 0) << 16) & (0x007f0000
)) | (((uint32_t)(state->bs_interval) << 0) & (0x0000ffff
))))))
;
2632
2633 /*
2634 * Write new beacon miss threshold, if it appears to be valid
2635 */
2636 if ((AR5K_AR5212_RSSI_THR_BMISS0x0000ff00 >> AR5K_AR5212_RSSI_THR_BMISS_S8) <
2637 state->bs_bmiss_threshold)
2638 return;
2639
2640 AR5K_REG_WRITE_BITS(AR5K_AR5212_RSSI_THR_M,((hal->ah_st)->write_4((hal->ah_sh), ((0x000000ff)),
(((((hal->ah_st)->read_4((hal->ah_sh), ((0x000000ff
)))) &~ (0x0000ff00)) | (((state->bs_bmiss_threshold) <<
8) & (0x0000ff00))))))
2641 AR5K_AR5212_RSSI_THR_BMISS, state->bs_bmiss_threshold)((hal->ah_st)->write_4((hal->ah_sh), ((0x000000ff)),
(((((hal->ah_st)->read_4((hal->ah_sh), ((0x000000ff
)))) &~ (0x0000ff00)) | (((state->bs_bmiss_threshold) <<
8) & (0x0000ff00))))))
;
2642
2643 /*
2644 * Set sleep registers
2645 */
2646 if ((state->bs_sleepdurationbs_sleep_duration > state->bs_interval) &&
2647 (roundup(state->bs_sleepduration, interval)((((state->bs_sleep_duration)+((interval)-1))/(interval))*
(interval))
==
2648 state->bs_sleepdurationbs_sleep_duration))
2649 interval = state->bs_sleepdurationbs_sleep_duration;
2650
2651 if (state->bs_sleepdurationbs_sleep_duration > dtim &&
2652 (dtim == 0 || roundup(state->bs_sleepduration, dtim)((((state->bs_sleep_duration)+((dtim)-1))/(dtim))*(dtim)) ==
2653 state->bs_sleepdurationbs_sleep_duration))
2654 dtim = state->bs_sleepdurationbs_sleep_duration;
2655
2656 if (interval > dtim)
2657 return;
2658
2659 next_beacon = interval == dtim ?
2660 state->bs_nextdtimbs_next_dtim: state->bs_nexttbttbs_next_beacon;
2661
2662 AR5K_REG_WRITE(AR5K_AR5212_SLEEP0,((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
2663 AR5K_REG_SM((state->bs_nextdtim - 3) << 3,((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
2664 AR5K_AR5212_SLEEP0_NEXT_DTIM) |((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
2665 AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) |((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
2666 AR5K_AR5212_SLEEP0_ENH_SLEEP_EN |((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
2667 AR5K_AR5212_SLEEP0_ASSUME_DTIM)((hal->ah_st)->write_4((hal->ah_sh), ((0x80d4)), (((
((uint32_t)((state->bs_next_dtim - 3) << 3) <<
0) & (0x0007ffff)) | (((uint32_t)(10) << 24) &
(0xff000000)) | 0x00100000 | 0x00080000))))
;
2668 AR5K_REG_WRITE(AR5K_AR5212_SLEEP1,((hal->ah_st)->write_4((hal->ah_sh), ((0x80d8)), (((
((uint32_t)((next_beacon - 3) << 3) << 0) & (
0x0007ffff)) | (((uint32_t)(10) << 24) & (0xff000000
))))))
2669 AR5K_REG_SM((next_beacon - 3) << 3,((hal->ah_st)->write_4((hal->ah_sh), ((0x80d8)), (((
((uint32_t)((next_beacon - 3) << 3) << 0) & (
0x0007ffff)) | (((uint32_t)(10) << 24) & (0xff000000
))))))
2670 AR5K_AR5212_SLEEP1_NEXT_TIM) |((hal->ah_st)->write_4((hal->ah_sh), ((0x80d8)), (((
((uint32_t)((next_beacon - 3) << 3) << 0) & (
0x0007ffff)) | (((uint32_t)(10) << 24) & (0xff000000
))))))
2671 AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO))((hal->ah_st)->write_4((hal->ah_sh), ((0x80d8)), (((
((uint32_t)((next_beacon - 3) << 3) << 0) & (
0x0007ffff)) | (((uint32_t)(10) << 24) & (0xff000000
))))))
;
2672 AR5K_REG_WRITE(AR5K_AR5212_SLEEP2,((hal->ah_st)->write_4((hal->ah_sh), ((0x80dc)), (((
((uint32_t)(interval) << 0) & (0x0000ffff)) | (((uint32_t
)(dtim) << 16) & (0xffff0000))))))
2673 AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) |((hal->ah_st)->write_4((hal->ah_sh), ((0x80dc)), (((
((uint32_t)(interval) << 0) & (0x0000ffff)) | (((uint32_t
)(dtim) << 16) & (0xffff0000))))))
2674 AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER))((hal->ah_st)->write_4((hal->ah_sh), ((0x80dc)), (((
((uint32_t)(interval) << 0) & (0x0000ffff)) | (((uint32_t
)(dtim) << 16) & (0xffff0000))))))
;
2675}
2676
2677void
2678ar5k_ar5212_reset_beacon(struct ath_hal *hal)
2679{
2680 /*
2681 * Disable beacon timer
2682 */
2683 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, 0)((hal->ah_st)->write_4((hal->ah_sh), ((0x8028)), ((0
))))
;
2684
2685 /*
2686 * Disable some beacon register values
2687 */
2688 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1,((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) &
~ (0x00200000 | 0x00100000)))))
2689 AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5212_STA_ID1_PCF)((hal->ah_st)->write_4((hal->ah_sh), ((0x8004)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x8004)))) &
~ (0x00200000 | 0x00100000)))))
;
2690 AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD)((hal->ah_st)->write_4((hal->ah_sh), ((0x8020)), ((0x0000ffff
))))
;
2691}
2692
2693HAL_BOOL
2694ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
2695{
2696 HAL_BOOL ret;
2697
2698 /*
2699 * Wait for beacon queue to be done
2700 */
2701 ret = ar5k_register_timeout(hal,
2702 AR5K_AR5212_QCU_STS(HAL_TX_QUEUE_ID_BEACON)(((HAL_TX_QUEUE_ID_BEACON) << 2) + 0x0a00),
2703 AR5K_AR5212_QCU_STS_FRMPENDCNT0x00000003, 0, AH_FALSE);
2704
2705 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)(((hal->ah_st)->read_4((hal->ah_sh), ((0x0840)))) &
(1 << HAL_TX_QUEUE_ID_BEACON))
)
2706 return (AH_FALSE);
2707
2708 return (ret);
2709}
2710
2711/*
2712 * Interrupt handling
2713 */
2714
2715HAL_BOOL
2716ar5k_ar5212_is_intr_pending(struct ath_hal *hal)
2717{
2718 return (AR5K_REG_READ(AR5K_AR5212_INTPEND)((hal->ah_st)->read_4((hal->ah_sh), ((0x4008)))) == 0 ? AH_FALSE : AH_TRUE);
2719}
2720
2721HAL_BOOL
2722ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
2723{
2724 u_int32_t data;
2725
2726 /*
2727 * Read interrupt status from the Read-And-Clear shadow register
2728 */
2729 data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR)((hal->ah_st)->read_4((hal->ah_sh), ((0x00c0))));
2730
2731 /*
2732 * Get abstract interrupt mask (HAL-compatible)
2733 */
2734 *interrupt_mask = (data & HAL_INT_COMMON( 0x00000008 | 0x00000002 | 0x00000010 | 0x00000020 | 0x00000800
| 0x00000080 | 0x00001000 | 0x00004000 | 0x00008000 | 0x00010000
| 0x00040000 | 0x01000000 )
) & hal->ah_imr;
2735
2736 if (data == HAL_INT_NOCARD0xffffffff)
2737 return (AH_FALSE);
2738
2739 if (data & (AR5K_AR5212_PISR_RXOK0x00000001 | AR5K_AR5212_PISR_RXERR0x00000004))
2740 *interrupt_mask |= HAL_INT_RX0x00000001;
2741
2742 if (data & (AR5K_AR5212_PISR_TXOK0x00000040 | AR5K_AR5212_PISR_TXERR0x00000100))
2743 *interrupt_mask |= HAL_INT_TX0x00000040;
2744
2745 if (data & (AR5K_AR5212_PISR_HIUERR0x00080000))
2746 *interrupt_mask |= HAL_INT_FATAL0x40000000;
2747
2748 /*
2749 * Special interrupt handling (not caught by the driver)
2750 */
2751 if (((*interrupt_mask) & AR5K_AR5212_PISR_RXPHY0x00004000) &&
2752 hal->ah_radar.r_enabled == AH_TRUE)
2753 ar5k_radar_alert(hal);
2754
2755 if (*interrupt_mask == 0)
2756 AR5K_PRINTF("0x%08x\n", data)printf("%s: " "0x%08x\n", __func__, data);
2757
2758 return (AH_TRUE);
2759}
2760
2761u_int32_t
2762ar5k_ar5212_get_intr(struct ath_hal *hal)
2763{
2764 /* Return the interrupt mask stored previously */
2765 return (hal->ah_imr);
2766}
2767
2768HAL_INT
2769ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask)
2770{
2771 HAL_INT old_mask, int_mask;
2772
2773 /*
2774 * Disable card interrupts to prevent any race conditions
2775 * (they will be re-enabled afterwards).
2776 */
2777 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0024)), ((0x00000000
))))
;
2778
2779 old_mask = hal->ah_imr;
2780
2781 /*
2782 * Add additional, chipset-dependent interrupt mask flags
2783 * and write them to the IMR (interrupt mask register).
2784 */
2785 int_mask = new_mask & HAL_INT_COMMON( 0x00000008 | 0x00000002 | 0x00000010 | 0x00000020 | 0x00000800
| 0x00000080 | 0x00001000 | 0x00004000 | 0x00008000 | 0x00010000
| 0x00040000 | 0x01000000 )
;
2786
2787 if (new_mask & HAL_INT_RX0x00000001)
2788 int_mask |=
2789 AR5K_AR5212_PIMR_RXOK0x00000001 |
2790 AR5K_AR5212_PIMR_RXERR0x00000004 |
2791 AR5K_AR5212_PIMR_RXORN0x00000020 |
2792 AR5K_AR5212_PIMR_RXDESC0x00000002;
2793
2794 if (new_mask & HAL_INT_TX0x00000040)
2795 int_mask |=
2796 AR5K_AR5212_PIMR_TXOK0x00000040 |
2797 AR5K_AR5212_PIMR_TXERR0x00000100 |
2798 AR5K_AR5212_PIMR_TXDESC0x00000080 |
2799 AR5K_AR5212_PIMR_TXURN0x00000800;
2800
2801 if (new_mask & HAL_INT_FATAL0x40000000) {
2802 int_mask |= AR5K_AR5212_PIMR_HIUERR0x00080000;
2803 AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2,((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00ac)))) | (0x00100000
| 0x00200000 | 0x00400000)))))
2804 AR5K_AR5212_SIMR2_MCABT |((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00ac)))) | (0x00100000
| 0x00200000 | 0x00400000)))))
2805 AR5K_AR5212_SIMR2_SSERR |((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00ac)))) | (0x00100000
| 0x00200000 | 0x00400000)))))
2806 AR5K_AR5212_SIMR2_DPERR)((hal->ah_st)->write_4((hal->ah_sh), ((0x00ac)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00ac)))) | (0x00100000
| 0x00200000 | 0x00400000)))))
;
2807 }
2808
2809 AR5K_REG_WRITE(AR5K_AR5212_PIMR, int_mask)((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), ((int_mask
))))
;
2810
2811 /* Store new interrupt mask */
2812 hal->ah_imr = new_mask;
2813
2814 /* ..re-enable interrupts */
2815 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0024)), ((0x00000001
))))
;
2816
2817 return (old_mask);
2818}
2819
2820/*
2821 * Misc internal functions
2822 */
2823
2824HAL_BOOL
2825ar5k_ar5212_get_capabilities(struct ath_hal *hal)
2826{
2827 u_int16_t ee_header;
2828 u_int a, b, g;
2829
2830 /* Capabilities stored in the EEPROM */
2831 ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
2832
2833 a = AR5K_EEPROM_HDR_11A(ee_header)(((ee_header) >> 0) & 0x1);
2834 b = AR5K_EEPROM_HDR_11B(ee_header)(((ee_header) >> 1) & 0x1);
2835 g = AR5K_EEPROM_HDR_11G(ee_header)(((ee_header) >> 2) & 0x1);
2836
2837 /*
2838 * If the EEPROM is not reporting any mode, we try 11b.
2839 * This might fix a few broken devices with invalid EEPROM.
2840 */
2841 if (!a && !b && !g)
2842 b = 1;
2843
2844 /*
2845 * XXX The AR5212 transceiver supports frequencies from 4920 to 6100GHz
2846 * XXX and from 2312 to 2732GHz. There are problems with the current
2847 * XXX ieee80211 implementation because the IEEE channel mapping
2848 * XXX does not support negative channel numbers (2312MHz is channel
2849 * XXX -19). Of course, this doesn't matter because these channels
2850 * XXX are out of range but some regulation domains like MKK (Japan)
2851 * XXX will support frequencies somewhere around 4.8GHz.
2852 */
2853
2854 /*
2855 * Set radio capabilities
2856 */
2857
2858 if (a) {
2859 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2860 hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
2861
2862 /* Set supported modes */
2863 hal->ah_capabilities.cap_mode =
2864 HAL_MODE_11A | HAL_MODE_TURBO | HAL_MODE_XR;
2865 }
2866
2867 /* This chip will support 802.11b if the 2GHz radio is connected */
2868 if (b || g) {
2869 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2870 hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
2871
2872 if (b)
2873 hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
2874#if 0
2875 if (g)
2876 hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
2877#endif
2878 }
2879
2880 /* GPIO */
2881 hal->ah_gpio_npins = AR5K_AR5212_NUM_GPIO6;
2882
2883 /* Set number of supported TX queues */
2884 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES10;
2885
2886 return (AH_TRUE);
2887}
2888
2889void
2890ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
2891{
2892 /*
2893 * Enable radar detection
2894 */
2895 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0024)), ((0x00000000
))))
;
2896
2897 if (enable == AH_TRUE) {
2898 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR,((hal->ah_st)->write_4((hal->ah_sh), ((0x9954)), ((0x00000001
))))
2899 AR5K_AR5212_PHY_RADAR_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x9954)), ((0x00000001
))))
;
2900 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR,((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00a0)))) | (0x00004000
)))))
2901 AR5K_AR5212_PIMR_RXPHY)((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00a0)))) | (0x00004000
)))))
;
2902 } else {
2903 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR,((hal->ah_st)->write_4((hal->ah_sh), ((0x9954)), ((0x00000000
))))
2904 AR5K_AR5212_PHY_RADAR_DISABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x9954)), ((0x00000000
))))
;
2905 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PIMR,((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00a0)))) &
~ (0x00004000)))))
2906 AR5K_AR5212_PIMR_RXPHY)((hal->ah_st)->write_4((hal->ah_sh), ((0x00a0)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x00a0)))) &
~ (0x00004000)))))
;
2907 }
2908
2909 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE)((hal->ah_st)->write_4((hal->ah_sh), ((0x0024)), ((0x00000001
))))
;
2910}
2911
2912/*
2913 * EEPROM access functions
2914 */
2915
2916HAL_BOOL
2917ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal)
2918{
2919 return (AR5K_REG_READ(AR5K_AR5212_CFG)((hal->ah_st)->read_4((hal->ah_sh), ((0x0014)))) & AR5K_AR5212_CFG_EEBS0x00000200 ?
2920 AH_TRUE : AH_FALSE);
2921}
2922
2923int
2924ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
2925{
2926 u_int32_t status, i;
2927
2928 /*
2929 * Initialize EEPROM access
2930 */
2931 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset)((hal->ah_st)->write_4((hal->ah_sh), ((0x6000)), (((
u_int8_t)offset))))
;
2932 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD,((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000001
)))))
2933 AR5K_AR5212_EEPROM_CMD_READ)((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000001
)))))
;
2934
2935 for (i = AR5K_TUNE_REGISTER_TIMEOUT20000; i > 0; i--) {
2936 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS)((hal->ah_st)->read_4((hal->ah_sh), ((0x600c))));
2937 if (status & AR5K_AR5212_EEPROM_STAT_RDDONE0x00000002) {
2938 if (status & AR5K_AR5212_EEPROM_STAT_RDERR0x00000001)
2939 return (EIO5);
2940 *data = (u_int16_t)
2941 (AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA)((hal->ah_st)->read_4((hal->ah_sh), ((0x6004)))) & 0xffff);
2942 return (0);
2943 }
2944 AR5K_DELAY(15)(*delay_func)(15);
2945 }
2946
2947 return (ETIMEDOUT60);
2948}
2949
2950int
2951ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
2952{
2953 u_int32_t status, timeout;
2954
2955 /* Enable eeprom access */
2956 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD,((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000004
)))))
2957 AR5K_AR5212_EEPROM_CMD_RESET)((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000004
)))))
;
2958 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD,((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000002
)))))
2959 AR5K_AR5212_EEPROM_CMD_WRITE)((hal->ah_st)->write_4((hal->ah_sh), ((0x6008)), (((
(hal->ah_st)->read_4((hal->ah_sh), ((0x6008)))) | (0x00000002
)))))
;
2960
2961 /*
2962 * Prime write pump
2963 */
2964 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset - 1)((hal->ah_st)->write_4((hal->ah_sh), ((0x6000)), (((
u_int8_t)offset - 1))))
;
2965
2966 for (timeout = 10000; timeout > 0; timeout--) {
2967 AR5K_DELAY(1)(*delay_func)(1);
2968 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS)((hal->ah_st)->read_4((hal->ah_sh), ((0x600c))));
2969 if (status & AR5K_AR5212_EEPROM_STAT_WRDONE0x00000008) {
2970 if (status & AR5K_AR5212_EEPROM_STAT_WRERR0x00000004)
2971 return (EIO5);
2972 return (0);
2973 }
2974 }
2975
2976 return (ETIMEDOUT60);
2977}
2978
2979/*
2980 * TX power setup
2981 */
2982
2983HAL_BOOL
2984ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower)
2985{
2986 HAL_BOOL tpc = hal->ah_txpower.txp_tpc;
2987 int i;
2988
2989 if (txpower > AR5K_TUNE_MAX_TXPOWER60) {
2990 AR5K_PRINTF("invalid tx power: %u\n", txpower)printf("%s: " "invalid tx power: %u\n", __func__, txpower);
2991 return (AH_FALSE);
2992 }
2993
2994 /* Reset TX power values */
2995 bzero(&hal->ah_txpower, sizeof(hal->ah_txpower))__builtin_bzero((&hal->ah_txpower), (sizeof(hal->ah_txpower
)))
;
2996 hal->ah_txpower.txp_tpc = tpc;
2997
2998 /* Initialize TX power table */
2999 ar5k_txpower_table(hal, channel, txpower);
3000
3001 /*
3002 * Write TX power values
3003 */
3004 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE64 / 2); i++) {
3005 AR5K_REG_WRITE(AR5K_AR5212_PHY_PCDAC_TXPOWER(i),((hal->ah_st)->write_4((hal->ah_sh), (((0xa180 + ((i
) << 2)))), ((((((hal->ah_txpower.txp_pcdac[(i <<
1) + 1] << 8) | 0xff) & 0xffff) << 16) | (((
hal->ah_txpower.txp_pcdac[i << 1] << 8) | 0xff
) & 0xffff)))))
3006 ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) &((hal->ah_st)->write_4((hal->ah_sh), (((0xa180 + ((i
) << 2)))), ((((((hal->ah_txpower.txp_pcdac[(i <<
1) + 1] << 8) | 0xff) & 0xffff) << 16) | (((
hal->ah_txpower.txp_pcdac[i << 1] << 8) | 0xff
) & 0xffff)))))
3007 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8)((hal->ah_st)->write_4((hal->ah_sh), (((0xa180 + ((i
) << 2)))), ((((((hal->ah_txpower.txp_pcdac[(i <<
1) + 1] << 8) | 0xff) & 0xffff) << 16) | (((
hal->ah_txpower.txp_pcdac[i << 1] << 8) | 0xff
) & 0xffff)))))
3008 | 0xff) & 0xffff))((hal->ah_st)->write_4((hal->ah_sh), (((0xa180 + ((i
) << 2)))), ((((((hal->ah_txpower.txp_pcdac[(i <<
1) + 1] << 8) | 0xff) & 0xffff) << 16) | (((
hal->ah_txpower.txp_pcdac[i << 1] << 8) | 0xff
) & 0xffff)))))
;
3009 }
3010
3011 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE1,((hal->ah_st)->write_4((hal->ah_sh), ((0x9934)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(3)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(2)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(1)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(0)]) & 0x3f) << (0)) )))))
3012 AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16)((hal->ah_st)->write_4((hal->ah_sh), ((0x9934)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(3)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(2)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(1)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(0)]) & 0x3f) << (0)) )))))
3013 | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0))((hal->ah_st)->write_4((hal->ah_sh), ((0x9934)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(3)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(2)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(1)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(0)]) & 0x3f) << (0)) )))))
;
3014
3015 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE2,((hal->ah_st)->write_4((hal->ah_sh), ((0x9938)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(7)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(6)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(5)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(4)]) & 0x3f) << (0)) )))))
3016 AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16)((hal->ah_st)->write_4((hal->ah_sh), ((0x9938)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(7)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(6)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(5)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(4)]) & 0x3f) << (0)) )))))
3017 | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0))((hal->ah_st)->write_4((hal->ah_sh), ((0x9938)), (((
((0 & 1) << ((24) + 6)) | (((hal->ah_txpower.txp_rates
[(7)]) & 0x3f) << (24)) ) | ( ((0 & 1) <<
((16) + 6)) | (((hal->ah_txpower.txp_rates[(6)]) & 0x3f
) << (16)) ) | ( ((0 & 1) << ((8) + 6)) | (((
hal->ah_txpower.txp_rates[(5)]) & 0x3f) << (8)) )
| ( ((0 & 1) << ((0) + 6)) | (((hal->ah_txpower
.txp_rates[(4)]) & 0x3f) << (0)) )))))
;
3018
3019 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE3,((hal->ah_st)->write_4((hal->ah_sh), ((0xa234)), (((
(hal->ah_txpower.txp_rates[(10)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(9)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(15)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(8)] & 0x3f) <<
(0) )))))
3020 AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16)((hal->ah_st)->write_4((hal->ah_sh), ((0xa234)), (((
(hal->ah_txpower.txp_rates[(10)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(9)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(15)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(8)] & 0x3f) <<
(0) )))))
3021 | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0))((hal->ah_st)->write_4((hal->ah_sh), ((0xa234)), (((
(hal->ah_txpower.txp_rates[(10)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(9)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(15)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(8)] & 0x3f) <<
(0) )))))
;
3022
3023 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE4,((hal->ah_st)->write_4((hal->ah_sh), ((0xa238)), (((
(hal->ah_txpower.txp_rates[(14)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(13)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(12)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(11)] & 0x3f) <<
(0) )))))
3024 AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16)((hal->ah_st)->write_4((hal->ah_sh), ((0xa238)), (((
(hal->ah_txpower.txp_rates[(14)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(13)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(12)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(11)] & 0x3f) <<
(0) )))))
3025 | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0))((hal->ah_st)->write_4((hal->ah_sh), ((0xa238)), (((
(hal->ah_txpower.txp_rates[(14)] & 0x3f) << (24
) ) | ( (hal->ah_txpower.txp_rates[(13)] & 0x3f) <<
(16) ) | ( (hal->ah_txpower.txp_rates[(12)] & 0x3f) <<
(8) ) | ( (hal->ah_txpower.txp_rates[(11)] & 0x3f) <<
(0) )))))
;
3026
3027 if (hal->ah_txpower.txp_tpc == AH_TRUE) {
3028 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX,((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x00000040
| 60))))
3029 AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x00000040
| 60))))
3030 AR5K_TUNE_MAX_TXPOWER)((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x00000040
| 60))))
;
3031 } else {
3032 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX,((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x993c
| 60))))
3033 AR5K_AR5212_PHY_TXPOWER_RATE_MAX |((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x993c
| 60))))
3034 AR5K_TUNE_MAX_TXPOWER)((hal->ah_st)->write_4((hal->ah_sh), ((0x993c)), ((0x993c
| 60))))
;
3035 }
3036
3037 return (AH_TRUE);
3038}
3039
3040HAL_BOOL
3041ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power)
3042{
3043 HAL_CHANNEL *channel = &hal->ah_current_channel;
3044
3045 AR5K_PRINTF("changing txpower to %d\n", power)printf("%s: " "changing txpower to %d\n", __func__, power);
3046 return (ar5k_ar5212_txpower(hal, channel, power));
3047}