File: | dev/pci/ahc_pci.c |
Warning: | line 821, column 2 Value stored to 'devconfig' is never read |
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1 | /* $OpenBSD: ahc_pci.c,v 1.63 2022/10/21 17:45:40 kn Exp $ */ |
2 | /* $NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $ */ |
3 | |
4 | /* |
5 | * Product specific probe and attach routines for: |
6 | * 3940, 2940, aic7895, aic7890, aic7880, |
7 | * aic7870, aic7860 and aic7850 SCSI controllers |
8 | * |
9 | * Copyright (c) 1994-2001 Justin T. Gibbs. |
10 | * Copyright (c) 2000-2001 Adaptec Inc. |
11 | * All rights reserved. |
12 | * |
13 | * Redistribution and use in source and binary forms, with or without |
14 | * modification, are permitted provided that the following conditions |
15 | * are met: |
16 | * 1. Redistributions of source code must retain the above copyright |
17 | * notice, this list of conditions, and the following disclaimer, |
18 | * without modification. |
19 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
20 | * substantially similar to the "NO WARRANTY" disclaimer below |
21 | * ("Disclaimer") and any redistribution must be conditioned upon |
22 | * including a substantially similar Disclaimer requirement for further |
23 | * binary redistribution. |
24 | * 3. Neither the names of the above-listed copyright holders nor the names |
25 | * of any contributors may be used to endorse or promote products derived |
26 | * from this software without specific prior written permission. |
27 | * |
28 | * Alternatively, this software may be distributed under the terms of the |
29 | * GNU General Public License ("GPL") version 2 as published by the Free |
30 | * Software Foundation. |
31 | * |
32 | * NO WARRANTY |
33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
34 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
35 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
36 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
37 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
38 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
39 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
40 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
41 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
42 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
43 | * POSSIBILITY OF SUCH DAMAGES. |
44 | * |
45 | * $Id: ahc_pci.c,v 1.63 2022/10/21 17:45:40 kn Exp $ |
46 | * |
47 | * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ |
48 | * |
49 | * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ |
50 | */ |
51 | /* |
52 | * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 |
53 | */ |
54 | |
55 | #include <sys/param.h> |
56 | #include <sys/systm.h> |
57 | #include <sys/malloc.h> |
58 | #include <sys/kernel.h> |
59 | #include <sys/queue.h> |
60 | #include <sys/device.h> |
61 | #include <sys/reboot.h> |
62 | |
63 | #include <machine/bus.h> |
64 | #include <machine/intr.h> |
65 | |
66 | #include <dev/pci/pcireg.h> |
67 | #include <dev/pci/pcivar.h> |
68 | |
69 | #define AHC_PCI_IOADDR0x10 PCI_MAPREG_START0x10 /* I/O Address */ |
70 | #define AHC_PCI_MEMADDR(0x10 + 4) (PCI_MAPREG_START0x10 + 4) /* Mem I/O Address */ |
71 | |
72 | #include <dev/ic/aic7xxx_openbsd.h> |
73 | #include <dev/ic/aic7xxx_inline.h> |
74 | |
75 | #ifndef __i386__ |
76 | #define AHC_ALLOW_MEMIO |
77 | #endif |
78 | |
79 | static __inline uint64_t |
80 | ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) |
81 | { |
82 | uint64_t id; |
83 | |
84 | id = subvendor |
85 | | (subdevice << 16) |
86 | | ((uint64_t)vendor << 32) |
87 | | ((uint64_t)device << 48); |
88 | |
89 | return (id); |
90 | } |
91 | |
92 | #define ID_ALL_MASK0xFFFFFFFFFFFFFFFFull 0xFFFFFFFFFFFFFFFFull |
93 | #define ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull 0xFFFFFFFF00000000ull |
94 | #define ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull 0xFFF0FFFF00000000ull |
95 | #define ID_9005_SISL_MASK0x000FFFFF00000000ull 0x000FFFFF00000000ull |
96 | #define ID_9005_SISL_ID0x0005900500000000ull 0x0005900500000000ull |
97 | #define ID_AIC78500x5078900400000000ull 0x5078900400000000ull |
98 | #define ID_AHA_2902_04_10_15_20_30C0x5078900478509004ull 0x5078900478509004ull |
99 | #define ID_AIC78550x5578900400000000ull 0x5578900400000000ull |
100 | #define ID_AIC78590x3860900400000000ull 0x3860900400000000ull |
101 | #define ID_AHA_2930CU0x3860900438699004ull 0x3860900438699004ull |
102 | #define ID_AIC78600x6078900400000000ull 0x6078900400000000ull |
103 | #define ID_AIC7860C0x6078900478609004ull 0x6078900478609004ull |
104 | #define ID_AHA_1480A0x6075900400000000ull 0x6075900400000000ull |
105 | #define ID_AHA_2940AU_00x6178900400000000ull 0x6178900400000000ull |
106 | #define ID_AHA_2940AU_10x6178900478619004ull 0x6178900478619004ull |
107 | #define ID_AHA_2940AU_CN0x2178900478219004ull 0x2178900478219004ull |
108 | #define ID_AHA_2930C_VAR0x6038900438689004ull 0x6038900438689004ull |
109 | |
110 | #define ID_AIC78700x7078900400000000ull 0x7078900400000000ull |
111 | #define ID_AHA_29400x7178900400000000ull 0x7178900400000000ull |
112 | #define ID_AHA_39400x7278900400000000ull 0x7278900400000000ull |
113 | #define ID_AHA_398X0x7378900400000000ull 0x7378900400000000ull |
114 | #define ID_AHA_29440x7478900400000000ull 0x7478900400000000ull |
115 | #define ID_AHA_39440x7578900400000000ull 0x7578900400000000ull |
116 | #define ID_AHA_49440x7678900400000000ull 0x7678900400000000ull |
117 | |
118 | #define ID_AIC78800x8078900400000000ull 0x8078900400000000ull |
119 | #define ID_AIC7880_B0x8078900478809004ull 0x8078900478809004ull |
120 | #define ID_AHA_2940U0x8178900400000000ull 0x8178900400000000ull |
121 | #define ID_AHA_3940U0x8278900400000000ull 0x8278900400000000ull |
122 | #define ID_AHA_2944U0x8478900400000000ull 0x8478900400000000ull |
123 | #define ID_AHA_3944U0x8578900400000000ull 0x8578900400000000ull |
124 | #define ID_AHA_398XU0x8378900400000000ull 0x8378900400000000ull |
125 | #define ID_AHA_4944U0x8678900400000000ull 0x8678900400000000ull |
126 | #define ID_AHA_2940UB0x8178900478819004ull 0x8178900478819004ull |
127 | #define ID_AHA_2930U0x8878900478889004ull 0x8878900478889004ull |
128 | #define ID_AHA_2940U_PRO0x8778900478879004ull 0x8778900478879004ull |
129 | #define ID_AHA_2940U_CN0x0078900478009004ull 0x0078900478009004ull |
130 | |
131 | #define ID_AIC78950x7895900478959004ull 0x7895900478959004ull |
132 | #define ID_AIC7895_ARO0x7890900478939004ull 0x7890900478939004ull |
133 | #define ID_AIC7895_ARO_MASK0xFFF0FFFFFFFFFFFFull 0xFFF0FFFFFFFFFFFFull |
134 | #define ID_AHA_2940U_DUAL0x7895900478919004ull 0x7895900478919004ull |
135 | #define ID_AHA_3940AU0x7895900478929004ull 0x7895900478929004ull |
136 | #define ID_AHA_3944AU0x7895900478949004ull 0x7895900478949004ull |
137 | |
138 | #define ID_AIC78900x001F9005000F9005ull 0x001F9005000F9005ull |
139 | #define ID_AIC7890_ARO0x00139005000F9005ull 0x00139005000F9005ull |
140 | #define ID_AAA_131U20x0013900500039005ull 0x0013900500039005ull |
141 | #define ID_AHA_2930U20x0011900501819005ull 0x0011900501819005ull |
142 | #define ID_AHA_2940U2B0x00109005A1009005ull 0x00109005A1009005ull |
143 | #define ID_AHA_2940U2_OEM0x0010900521809005ull 0x0010900521809005ull |
144 | #define ID_AHA_2940U20x00109005A1809005ull 0x00109005A1809005ull |
145 | #define ID_AHA_2950U2B0x00109005E1009005ull 0x00109005E1009005ull |
146 | |
147 | #define ID_AIC78920x008F9005FFFF9005ull 0x008F9005FFFF9005ull |
148 | #define ID_AIC7892_ARO0x00839005FFFF9005ull 0x00839005FFFF9005ull |
149 | #define ID_AHA_2915LP0x0082900502109005ull 0x0082900502109005ull |
150 | #define ID_AHA_291600x00809005E2A09005ull 0x00809005E2A09005ull |
151 | #define ID_AHA_29160_CPQ0x00809005E2A00E11ull 0x00809005E2A00E11ull |
152 | #define ID_AHA_29160N0x0080900562A09005ull 0x0080900562A09005ull |
153 | #define ID_AHA_29160C0x0080900562209005ull 0x0080900562209005ull |
154 | #define ID_AHA_29160B0x00809005E2209005ull 0x00809005E2209005ull |
155 | #define ID_AHA_19160B0x0081900562A19005ull 0x0081900562A19005ull |
156 | |
157 | #define ID_AIC78960x005F9005FFFF9005ull 0x005F9005FFFF9005ull |
158 | #define ID_AIC7896_ARO0x00539005FFFF9005ull 0x00539005FFFF9005ull |
159 | #define ID_AHA_3950U2B_00x00509005FFFF9005ull 0x00509005FFFF9005ull |
160 | #define ID_AHA_3950U2B_10x00509005F5009005ull 0x00509005F5009005ull |
161 | #define ID_AHA_3950U2D_00x00519005FFFF9005ull 0x00519005FFFF9005ull |
162 | #define ID_AHA_3950U2D_10x00519005B5009005ull 0x00519005B5009005ull |
163 | |
164 | #define ID_AIC78990x00CF9005FFFF9005ull 0x00CF9005FFFF9005ull |
165 | #define ID_AIC7899_ARO0x00C39005FFFF9005ull 0x00C39005FFFF9005ull |
166 | #define ID_AHA_3960D0x00C09005F6209005ull 0x00C09005F6209005ull |
167 | #define ID_AHA_3960D_CPQ0x00C09005F6200E11ull 0x00C09005F6200E11ull |
168 | |
169 | #define ID_AIC78100x1078900400000000ull 0x1078900400000000ull |
170 | #define ID_AIC78150x7815900400000000ull 0x7815900400000000ull |
171 | |
172 | #define DEVID_9005_TYPE(id)((id) & 0xF) ((id) & 0xF) |
173 | #define DEVID_9005_TYPE_HBA0x0 0x0 /* Standard Card */ |
174 | #define DEVID_9005_TYPE_AAA0x3 0x3 /* RAID Card */ |
175 | #define DEVID_9005_TYPE_SISL0x5 0x5 /* Container ROMB */ |
176 | #define DEVID_9005_TYPE_MB0xF 0xF /* On Motherboard */ |
177 | |
178 | #define DEVID_9005_MAXRATE(id)(((id) & 0x30) >> 4) (((id) & 0x30) >> 4) |
179 | #define DEVID_9005_MAXRATE_U1600x0 0x0 |
180 | #define DEVID_9005_MAXRATE_ULTRA20x1 0x1 |
181 | #define DEVID_9005_MAXRATE_ULTRA0x2 0x2 |
182 | #define DEVID_9005_MAXRATE_FAST0x3 0x3 |
183 | |
184 | #define DEVID_9005_MFUNC(id)(((id) & 0x40) >> 6) (((id) & 0x40) >> 6) |
185 | |
186 | #define DEVID_9005_CLASS(id)(((id) & 0xFF00) >> 8) (((id) & 0xFF00) >> 8) |
187 | #define DEVID_9005_CLASS_SPI0x0 0x0 /* Parallel SCSI */ |
188 | |
189 | #define SUBID_9005_TYPE(id)((id) & 0xF) ((id) & 0xF) |
190 | #define SUBID_9005_TYPE_MB0xF 0xF /* On Motherboard */ |
191 | #define SUBID_9005_TYPE_CARD0x0 0x0 /* Standard Card */ |
192 | #define SUBID_9005_TYPE_LCCARD0x1 0x1 /* Low Cost Card */ |
193 | #define SUBID_9005_TYPE_RAID0x3 0x3 /* Combined with Raid */ |
194 | |
195 | #define SUBID_9005_TYPE_KNOWN(id)((((id) & 0xF) == 0xF) || (((id) & 0xF) == 0x0) || (( (id) & 0xF) == 0x1) || (((id) & 0xF) == 0x3)) \ |
196 | ((((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
197 | || (((id) & 0xF) == SUBID_9005_TYPE_CARD0x0) \ |
198 | || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD0x1) \ |
199 | || (((id) & 0xF) == SUBID_9005_TYPE_RAID0x3)) |
200 | |
201 | #define SUBID_9005_MAXRATE(id)(((id) & 0x30) >> 4) (((id) & 0x30) >> 4) |
202 | #define SUBID_9005_MAXRATE_ULTRA20x0 0x0 |
203 | #define SUBID_9005_MAXRATE_ULTRA0x1 0x1 |
204 | #define SUBID_9005_MAXRATE_U1600x2 0x2 |
205 | #define SUBID_9005_MAXRATE_RESERVED0x3 0x3 |
206 | |
207 | #define SUBID_9005_SEEPTYPE(id)((((id) & 0xF) == 0xF) ? ((id) & 0xC0) >> 6 : ( (id) & 0x300) >> 8) \ |
208 | ((SUBID_9005_TYPE(id)((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
209 | ? ((id) & 0xC0) >> 6 \ |
210 | : ((id) & 0x300) >> 8) |
211 | #define SUBID_9005_SEEPTYPE_NONE0x0 0x0 |
212 | #define SUBID_9005_SEEPTYPE_1K0x1 0x1 |
213 | #define SUBID_9005_SEEPTYPE_2K_4K0x2 0x2 |
214 | #define SUBID_9005_SEEPTYPE_RESERVED0x3 0x3 |
215 | #define SUBID_9005_AUTOTERM(id)((((id) & 0xF) == 0xF) ? (((id) & 0x400) >> 10) == 0 : (((id) & 0x40) >> 6) == 0) \ |
216 | ((SUBID_9005_TYPE(id)((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
217 | ? (((id) & 0x400) >> 10) == 0 \ |
218 | : (((id) & 0x40) >> 6) == 0) |
219 | |
220 | #define SUBID_9005_NUMCHAN(id)((((id) & 0xF) == 0xF) ? ((id) & 0x300) >> 8 : ( (id) & 0xC00) >> 10) \ |
221 | ((SUBID_9005_TYPE(id)((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
222 | ? ((id) & 0x300) >> 8 \ |
223 | : ((id) & 0xC00) >> 10) |
224 | |
225 | #define SUBID_9005_LEGACYCONN(id)((((id) & 0xF) == 0xF) ? 0 : ((id) & 0x80) >> 7 ) \ |
226 | ((SUBID_9005_TYPE(id)((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
227 | ? 0 \ |
228 | : ((id) & 0x80) >> 7) |
229 | |
230 | #define SUBID_9005_MFUNCENB(id)((((id) & 0xF) == 0xF) ? ((id) & 0x800) >> 11 : ((id) & 0x1000) >> 12) \ |
231 | ((SUBID_9005_TYPE(id)((id) & 0xF) == SUBID_9005_TYPE_MB0xF) \ |
232 | ? ((id) & 0x800) >> 11 \ |
233 | : ((id) & 0x1000) >> 12) |
234 | /* |
235 | * Informational only. Should use chip register to be |
236 | * certain, but may be use in identification strings. |
237 | */ |
238 | #define SUBID_9005_CARD_SCSIWIDTH_MASK0x2000 0x2000 |
239 | #define SUBID_9005_CARD_PCIWIDTH_MASK0x4000 0x4000 |
240 | #define SUBID_9005_CARD_SEDIFF_MASK0x8000 0x8000 |
241 | |
242 | static ahc_device_setup_t ahc_aic785X_setup; |
243 | static ahc_device_setup_t ahc_aic7860_setup; |
244 | static ahc_device_setup_t ahc_apa1480_setup; |
245 | static ahc_device_setup_t ahc_aic7870_setup; |
246 | static ahc_device_setup_t ahc_aha394X_setup; |
247 | static ahc_device_setup_t ahc_aha494X_setup; |
248 | static ahc_device_setup_t ahc_aha398X_setup; |
249 | static ahc_device_setup_t ahc_aic7880_setup; |
250 | static ahc_device_setup_t ahc_aha2940Pro_setup; |
251 | static ahc_device_setup_t ahc_aha394XU_setup; |
252 | static ahc_device_setup_t ahc_aha398XU_setup; |
253 | static ahc_device_setup_t ahc_aic7890_setup; |
254 | static ahc_device_setup_t ahc_aic7892_setup; |
255 | static ahc_device_setup_t ahc_aic7895_setup; |
256 | static ahc_device_setup_t ahc_aic7896_setup; |
257 | static ahc_device_setup_t ahc_aic7899_setup; |
258 | static ahc_device_setup_t ahc_aha29160C_setup; |
259 | static ahc_device_setup_t ahc_raid_setup; |
260 | static ahc_device_setup_t ahc_aha394XX_setup; |
261 | static ahc_device_setup_t ahc_aha494XX_setup; |
262 | static ahc_device_setup_t ahc_aha398XX_setup; |
263 | |
264 | const struct ahc_pci_identity ahc_pci_ident_table [] = |
265 | { |
266 | /* aic7850 based controllers */ |
267 | { |
268 | ID_AHA_2902_04_10_15_20_30C0x5078900478509004ull, |
269 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
270 | ahc_aic785X_setup |
271 | }, |
272 | /* aic7860 based controllers */ |
273 | { |
274 | ID_AHA_2930CU0x3860900438699004ull, |
275 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
276 | ahc_aic7860_setup |
277 | }, |
278 | { |
279 | ID_AHA_1480A0x6075900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
280 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
281 | ahc_apa1480_setup |
282 | }, |
283 | { |
284 | ID_AHA_2940AU_00x6178900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
285 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
286 | ahc_aic7860_setup |
287 | }, |
288 | { |
289 | ID_AHA_2940AU_CN0x2178900478219004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
290 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
291 | ahc_aic7860_setup |
292 | }, |
293 | { |
294 | ID_AHA_2930C_VAR0x6038900438689004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
295 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
296 | ahc_aic7860_setup |
297 | }, |
298 | /* aic7870 based controllers */ |
299 | { |
300 | ID_AHA_29400x7178900400000000ull, |
301 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
302 | ahc_aic7870_setup |
303 | }, |
304 | { |
305 | ID_AHA_39400x7278900400000000ull, |
306 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
307 | ahc_aha394X_setup |
308 | }, |
309 | { |
310 | ID_AHA_398X0x7378900400000000ull, |
311 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
312 | ahc_aha398X_setup |
313 | }, |
314 | { |
315 | ID_AHA_29440x7478900400000000ull, |
316 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
317 | ahc_aic7870_setup |
318 | }, |
319 | { |
320 | ID_AHA_39440x7578900400000000ull, |
321 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
322 | ahc_aha394X_setup |
323 | }, |
324 | { |
325 | ID_AHA_49440x7678900400000000ull, |
326 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
327 | ahc_aha494X_setup |
328 | }, |
329 | /* aic7880 based controllers */ |
330 | { |
331 | ID_AHA_2940U0x8178900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
332 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
333 | ahc_aic7880_setup |
334 | }, |
335 | { |
336 | ID_AHA_3940U0x8278900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
337 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
338 | ahc_aha394XU_setup |
339 | }, |
340 | { |
341 | ID_AHA_2944U0x8478900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
342 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
343 | ahc_aic7880_setup |
344 | }, |
345 | { |
346 | ID_AHA_3944U0x8578900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
347 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
348 | ahc_aha394XU_setup |
349 | }, |
350 | { |
351 | ID_AHA_398XU0x8378900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
352 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
353 | ahc_aha398XU_setup |
354 | }, |
355 | { |
356 | /* |
357 | * XXX Don't know the slot numbers |
358 | * so we can't identify channels |
359 | */ |
360 | ID_AHA_4944U0x8678900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
361 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
362 | ahc_aic7880_setup |
363 | }, |
364 | { |
365 | ID_AHA_2930U0x8878900478889004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
366 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
367 | ahc_aic7880_setup |
368 | }, |
369 | { |
370 | ID_AHA_2940U_PRO0x8778900478879004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
371 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
372 | ahc_aha2940Pro_setup |
373 | }, |
374 | { |
375 | ID_AHA_2940U_CN0x0078900478009004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
376 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
377 | ahc_aic7880_setup |
378 | }, |
379 | /* Ignore all SISL (AAC on MB) based controllers. */ |
380 | { |
381 | ID_9005_SISL_ID0x0005900500000000ull, |
382 | ID_9005_SISL_MASK0x000FFFFF00000000ull, |
383 | NULL((void *)0) |
384 | }, |
385 | /* aic7890 based controllers */ |
386 | { |
387 | ID_AHA_2930U20x0011900501819005ull, |
388 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
389 | ahc_aic7890_setup |
390 | }, |
391 | { |
392 | ID_AHA_2940U2B0x00109005A1009005ull, |
393 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
394 | ahc_aic7890_setup |
395 | }, |
396 | { |
397 | ID_AHA_2940U2_OEM0x0010900521809005ull, |
398 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
399 | ahc_aic7890_setup |
400 | }, |
401 | { |
402 | ID_AHA_2940U20x00109005A1809005ull, |
403 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
404 | ahc_aic7890_setup |
405 | }, |
406 | { |
407 | ID_AHA_2950U2B0x00109005E1009005ull, |
408 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
409 | ahc_aic7890_setup |
410 | }, |
411 | { |
412 | ID_AIC7890_ARO0x00139005000F9005ull, |
413 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
414 | ahc_aic7890_setup |
415 | }, |
416 | { |
417 | ID_AAA_131U20x0013900500039005ull, |
418 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
419 | ahc_aic7890_setup |
420 | }, |
421 | /* aic7892 based controllers */ |
422 | { |
423 | ID_AHA_291600x00809005E2A09005ull, |
424 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
425 | ahc_aic7892_setup |
426 | }, |
427 | { |
428 | ID_AHA_29160_CPQ0x00809005E2A00E11ull, |
429 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
430 | ahc_aic7892_setup |
431 | }, |
432 | { |
433 | ID_AHA_29160N0x0080900562A09005ull, |
434 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
435 | ahc_aic7892_setup |
436 | }, |
437 | { |
438 | ID_AHA_29160C0x0080900562209005ull, |
439 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
440 | ahc_aha29160C_setup |
441 | }, |
442 | { |
443 | ID_AHA_29160B0x00809005E2209005ull, |
444 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
445 | ahc_aic7892_setup |
446 | }, |
447 | { |
448 | ID_AHA_19160B0x0081900562A19005ull, |
449 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
450 | ahc_aic7892_setup |
451 | }, |
452 | { |
453 | ID_AIC7892_ARO0x00839005FFFF9005ull, |
454 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
455 | ahc_aic7892_setup |
456 | }, |
457 | { |
458 | ID_AHA_2915LP0x0082900502109005ull, |
459 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
460 | ahc_aic7892_setup |
461 | }, |
462 | /* aic7895 based controllers */ |
463 | { |
464 | ID_AHA_2940U_DUAL0x7895900478919004ull, |
465 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
466 | ahc_aic7895_setup |
467 | }, |
468 | { |
469 | ID_AHA_3940AU0x7895900478929004ull, |
470 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
471 | ahc_aic7895_setup |
472 | }, |
473 | { |
474 | ID_AHA_3944AU0x7895900478949004ull, |
475 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
476 | ahc_aic7895_setup |
477 | }, |
478 | { |
479 | ID_AIC7895_ARO0x7890900478939004ull, |
480 | ID_AIC7895_ARO_MASK0xFFF0FFFFFFFFFFFFull, |
481 | ahc_aic7895_setup |
482 | }, |
483 | /* aic7896/97 based controllers */ |
484 | { |
485 | ID_AHA_3950U2B_00x00509005FFFF9005ull, |
486 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
487 | ahc_aic7896_setup |
488 | }, |
489 | { |
490 | ID_AHA_3950U2B_10x00509005F5009005ull, |
491 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
492 | ahc_aic7896_setup |
493 | }, |
494 | { |
495 | ID_AHA_3950U2D_00x00519005FFFF9005ull, |
496 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
497 | ahc_aic7896_setup |
498 | }, |
499 | { |
500 | ID_AHA_3950U2D_10x00519005B5009005ull, |
501 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
502 | ahc_aic7896_setup |
503 | }, |
504 | { |
505 | ID_AIC7896_ARO0x00539005FFFF9005ull, |
506 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
507 | ahc_aic7896_setup |
508 | }, |
509 | /* aic7899 based controllers */ |
510 | { |
511 | ID_AHA_3960D0x00C09005F6209005ull, |
512 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
513 | ahc_aic7899_setup |
514 | }, |
515 | { |
516 | ID_AHA_3960D_CPQ0x00C09005F6200E11ull, |
517 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
518 | ahc_aic7899_setup |
519 | }, |
520 | { |
521 | ID_AIC7899_ARO0x00C39005FFFF9005ull, |
522 | ID_ALL_MASK0xFFFFFFFFFFFFFFFFull, |
523 | ahc_aic7899_setup |
524 | }, |
525 | /* Generic chip probes for devices we don't know 'exactly' */ |
526 | { |
527 | ID_AIC78500x5078900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
528 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
529 | ahc_aic785X_setup |
530 | }, |
531 | { |
532 | ID_AIC78550x5578900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
533 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
534 | ahc_aic785X_setup |
535 | }, |
536 | { |
537 | ID_AIC78590x3860900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
538 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
539 | ahc_aic7860_setup |
540 | }, |
541 | { |
542 | ID_AIC78600x6078900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
543 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
544 | ahc_aic7860_setup |
545 | }, |
546 | { |
547 | ID_AIC78700x7078900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
548 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
549 | ahc_aic7870_setup |
550 | }, |
551 | { |
552 | ID_AIC78800x8078900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
553 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
554 | ahc_aic7880_setup |
555 | }, |
556 | { |
557 | ID_AIC78900x001F9005000F9005ull & ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
558 | ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
559 | ahc_aic7890_setup |
560 | }, |
561 | { |
562 | ID_AIC78920x008F9005FFFF9005ull & ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
563 | ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
564 | ahc_aic7892_setup |
565 | }, |
566 | { |
567 | ID_AIC78950x7895900478959004ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
568 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
569 | ahc_aic7895_setup |
570 | }, |
571 | { |
572 | ID_AIC78960x005F9005FFFF9005ull & ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
573 | ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
574 | ahc_aic7896_setup |
575 | }, |
576 | { |
577 | ID_AIC78990x00CF9005FFFF9005ull & ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
578 | ID_9005_GENERIC_MASK0xFFF0FFFF00000000ull, |
579 | ahc_aic7899_setup |
580 | }, |
581 | { |
582 | ID_AIC78100x1078900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
583 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
584 | ahc_raid_setup |
585 | }, |
586 | { |
587 | ID_AIC78150x7815900400000000ull & ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
588 | ID_DEV_VENDOR_MASK0xFFFFFFFF00000000ull, |
589 | ahc_raid_setup |
590 | } |
591 | }; |
592 | |
593 | #define AHC_394X_SLOT_CHANNEL_A4 4 |
594 | #define AHC_394X_SLOT_CHANNEL_B5 5 |
595 | |
596 | #define AHC_398X_SLOT_CHANNEL_A4 4 |
597 | #define AHC_398X_SLOT_CHANNEL_B8 8 |
598 | #define AHC_398X_SLOT_CHANNEL_C12 12 |
599 | |
600 | #define AHC_494X_SLOT_CHANNEL_A4 4 |
601 | #define AHC_494X_SLOT_CHANNEL_B5 5 |
602 | #define AHC_494X_SLOT_CHANNEL_C6 6 |
603 | #define AHC_494X_SLOT_CHANNEL_D7 7 |
604 | |
605 | #define DEVCONFIG0x40 0x40 |
606 | #define PCIERRGENDIS0x80000000ul 0x80000000ul |
607 | #define SCBSIZE320x00010000ul 0x00010000ul /* aic789X only */ |
608 | #define REXTVALID0x00001000ul 0x00001000ul /* ultra cards only */ |
609 | #define MPORTMODE0x00000400ul 0x00000400ul /* aic7870+ only */ |
610 | #define RAMPSM0x00000200ul 0x00000200ul /* aic7870+ only */ |
611 | #define VOLSENSE0x00000100ul 0x00000100ul |
612 | #define PCI64BIT0x00000080ul 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ |
613 | #define SCBRAMSEL0x00000080ul 0x00000080ul |
614 | #define MRDCEN0x00000040ul 0x00000040ul |
615 | #define EXTSCBTIME0x00000020ul 0x00000020ul /* aic7870 only */ |
616 | #define EXTSCBPEN0x00000010ul 0x00000010ul /* aic7870 only */ |
617 | #define BERREN0x00000008ul 0x00000008ul |
618 | #define DACEN0x00000004ul 0x00000004ul |
619 | #define STPWLEVEL0x00000002ul 0x00000002ul |
620 | #define DIFACTNEGEN0x00000001ul 0x00000001ul /* aic7870 only */ |
621 | |
622 | #define CSIZE_LATTIME0x0c 0x0c |
623 | #define CACHESIZE0x0000003ful 0x0000003ful /* only 5 bits */ |
624 | #define LATTIME0x0000ff00ul 0x0000ff00ul |
625 | |
626 | /* PCI STATUS definitions */ |
627 | #define DPE0x80 0x80 |
628 | #define SSE0x40 0x40 |
629 | #define RMA0x20 0x20 |
630 | #define RTA0x10 0x10 |
631 | #define STA0x08 0x08 |
632 | #define DPR0x01 0x01 |
633 | |
634 | static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, |
635 | uint16_t subvendor, uint16_t subdevice); |
636 | static int ahc_ext_scbram_present(struct ahc_softc *ahc); |
637 | static void ahc_scbram_config(struct ahc_softc *ahc, int enable, |
638 | int pcheck, int fast, int large); |
639 | static void ahc_probe_ext_scbram(struct ahc_softc *ahc); |
640 | static int ahc_pci_chip_init(struct ahc_softc *ahc); |
641 | |
642 | int ahc_pci_probe(struct device *, void *, void *); |
643 | void ahc_pci_attach(struct device *, struct device *, void *); |
644 | |
645 | |
646 | const struct cfattach ahc_pci_ca = { |
647 | sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach |
648 | }; |
649 | |
650 | const struct ahc_pci_identity * |
651 | ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) |
652 | { |
653 | u_int64_t full_id; |
654 | const struct ahc_pci_identity *entry; |
655 | u_int i; |
656 | |
657 | full_id = ahc_compose_id(PCI_PRODUCT(id)(((id) >> 16) & 0xffff), PCI_VENDOR(id)(((id) >> 0) & 0xffff), |
658 | PCI_PRODUCT(subid)(((subid) >> 16) & 0xffff), PCI_VENDOR(subid)(((subid) >> 0) & 0xffff)); |
659 | |
660 | /* |
661 | * If the second function is not hooked up, ignore it. |
662 | * Unfortunately, not all MB vendors implement the |
663 | * subdevice ID as per the Adaptec spec, so do our best |
664 | * to sanity check it prior to accepting the subdevice |
665 | * ID as valid. |
666 | */ |
667 | if (func > 0 |
668 | && ahc_9005_subdevinfo_valid(PCI_VENDOR(id)(((id) >> 0) & 0xffff), PCI_PRODUCT(id)(((id) >> 16) & 0xffff), |
669 | PCI_VENDOR(subid)(((subid) >> 0) & 0xffff), PCI_PRODUCT(subid)(((subid) >> 16) & 0xffff)) |
670 | && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid))(((((((subid) >> 16) & 0xffff)) & 0xF) == 0xF) ? (((((subid) >> 16) & 0xffff)) & 0x800) >> 11 : (((((subid) >> 16) & 0xffff)) & 0x1000) >> 12) == 0) |
671 | return (NULL((void *)0)); |
672 | |
673 | for (i = 0; i < NUM_ELEMENTS(ahc_pci_ident_table)(sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table)); i++) { |
674 | entry = &ahc_pci_ident_table[i]; |
675 | if (entry->full_id == (full_id & entry->id_mask)) |
676 | return (entry); |
677 | } |
678 | return (NULL((void *)0)); |
679 | } |
680 | |
681 | int |
682 | ahc_pci_probe(struct device *parent, void *match, void *aux) |
683 | { |
684 | struct pci_attach_args *pa = aux; |
685 | const struct ahc_pci_identity *entry; |
686 | pcireg_t subid; |
687 | |
688 | subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG0x2c); |
689 | entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); |
690 | return (entry != NULL((void *)0) && entry->setup != NULL((void *)0)) ? 1 : 0; |
691 | } |
692 | |
693 | void |
694 | ahc_pci_attach(struct device *parent, struct device *self, void *aux) |
695 | { |
696 | struct pci_attach_args *pa = aux; |
697 | const struct ahc_pci_identity *entry; |
698 | struct ahc_softc *ahc = (void *)self; |
699 | pcireg_t command; |
700 | u_int our_id = 0; |
701 | u_int sxfrctl1; |
702 | u_int scsiseq; |
703 | u_int sblkctl; |
704 | uint8_t dscommand0; |
705 | uint32_t devconfig; |
706 | int error; |
707 | pcireg_t subid; |
708 | int ioh_valid; |
709 | bus_space_tag_t st, iot; |
710 | bus_space_handle_t sh, ioh; |
711 | #ifdef AHC_ALLOW_MEMIO |
712 | int memh_valid; |
713 | bus_space_tag_t memt; |
714 | bus_space_handle_t memh; |
715 | pcireg_t memtype; |
716 | #endif |
717 | pci_intr_handle_t ih; |
718 | const char *intrstr; |
719 | struct ahc_pci_busdata *bd; |
720 | int i; |
721 | |
722 | /* |
723 | * Instead of ahc_alloc() as in FreeBSD, do the few relevant |
724 | * initializations manually. |
725 | */ |
726 | LIST_INIT(&ahc->pending_scbs)do { ((&ahc->pending_scbs)->lh_first) = ((void *)0) ; } while (0); |
727 | ahc->channel = 'A'; |
728 | ahc->seqctl = FASTMODE0x10; |
729 | for (i = 0; i < AHC_NUM_TARGETS16; i++) |
730 | TAILQ_INIT(&ahc->untagged_queues[i])do { (&ahc->untagged_queues[i])->tqh_first = ((void *)0); (&ahc->untagged_queues[i])->tqh_last = & (&ahc->untagged_queues[i])->tqh_first; } while (0); |
731 | |
732 | /* |
733 | * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b |
734 | * has been properly initialized. |
735 | */ |
736 | ahc->sc_child_b = NULL((void *)0); |
737 | |
738 | ahc->dev_softc = pa; |
739 | |
740 | ahc_set_name(ahc, ahc->sc_dev.dv_xname); |
741 | ahc->parent_dmat = pa->pa_dmat; |
742 | |
743 | subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG0x2c); |
744 | entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); |
745 | if (entry == NULL((void *)0)) |
746 | return; |
747 | |
748 | /* Keep information about the PCI bus */ |
749 | bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF2, |
750 | M_NOWAIT0x0002 | M_ZERO0x0008); |
751 | if (bd == NULL((void *)0)) { |
752 | printf("%s: unable to allocate bus-specific data\n", |
753 | ahc_name(ahc)); |
754 | return; |
755 | } |
756 | |
757 | bd->pc = pa->pa_pc; |
758 | bd->tag = pa->pa_tag; |
759 | bd->func = pa->pa_function; |
760 | bd->dev = pa->pa_device; |
761 | bd->class = pa->pa_class; |
762 | |
763 | ahc->bd = bd; |
764 | |
765 | error = entry->setup(ahc); |
766 | if (error != 0) |
767 | return; |
768 | |
769 | ioh_valid = 0; |
770 | |
771 | #ifdef AHC_ALLOW_MEMIO |
772 | memh_valid = 0; |
773 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR(0x10 + 4)); |
774 | switch (memtype) { |
775 | case PCI_MAPREG_TYPE_MEM0x00000000 | PCI_MAPREG_MEM_TYPE_32BIT0x00000000: |
776 | case PCI_MAPREG_TYPE_MEM0x00000000 | PCI_MAPREG_MEM_TYPE_64BIT0x00000004: |
777 | memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR(0x10 + 4), |
778 | memtype, 0, &memt, &memh, NULL((void *)0), NULL((void *)0), 0) == 0); |
779 | break; |
780 | default: |
781 | memh_valid = 0; |
782 | } |
783 | if (memh_valid == 0) |
784 | #endif |
785 | ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR0x10, |
786 | PCI_MAPREG_TYPE_IO0x00000001, 0, &iot, &ioh, NULL((void *)0), NULL((void *)0), 0) == 0); |
787 | #if 0 |
788 | printf("%s: mem mapping: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", |
789 | ahc_name(ahc), (u_long)memt, memh, (u_long)iot, ioh); |
790 | #endif |
791 | |
792 | if (ioh_valid) { |
793 | st = iot; |
794 | sh = ioh; |
795 | #ifdef AHC_ALLOW_MEMIO |
796 | } else if (memh_valid) { |
797 | st = memt; |
798 | sh = memh; |
799 | #endif |
800 | } else { |
801 | printf(": unable to map registers\n"); |
802 | return; |
803 | } |
804 | ahc->tag = st; |
805 | ahc->bsh = sh; |
806 | |
807 | ahc->chip |= AHC_PCI; |
808 | /* |
809 | * Before we continue probing the card, ensure that |
810 | * its interrupts are *disabled*. We don't want |
811 | * a misstep to hang the machine in an interrupt |
812 | * storm. |
813 | */ |
814 | ahc_intr_enable(ahc, FALSE0); |
815 | |
816 | /* |
817 | * XXX somehow reading this once fails on some sparc64 systems. |
818 | * This may be a problem in the sparc64 PCI code. Doing it |
819 | * twice works around it. |
820 | */ |
821 | devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG0x40); |
Value stored to 'devconfig' is never read | |
822 | devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG0x40); |
823 | |
824 | /* |
825 | * If we need to support high memory, enable dual |
826 | * address cycles. This bit must be set to enable |
827 | * high address bit generation even if we are on a |
828 | * 64bit bus (PCI64BIT set in devconfig). |
829 | */ |
830 | if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { |
831 | |
832 | if (1/*bootverbose*/) |
833 | printf("%s: Enabling 39Bit Addressing\n", |
834 | ahc_name(ahc)); |
835 | devconfig |= DACEN0x00000004ul; |
836 | } |
837 | |
838 | /* Ensure that pci error generation, a test feature, is disabled. */ |
839 | devconfig |= PCIERRGENDIS0x80000000ul; |
840 | |
841 | pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG0x40, devconfig); |
842 | |
843 | /* |
844 | * Disable PCI parity error reporting. Users typically |
845 | * do this to work around broken PCI chipsets that get |
846 | * the parity timing wrong and thus generate lots of spurious |
847 | * errors. |
848 | */ |
849 | if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) { |
850 | command = pci_conf_read(pa->pa_pc, pa->pa_tag, |
851 | PCI_COMMAND_STATUS_REG0x04); |
852 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04, |
853 | command & ~PCI_COMMAND_PARITY_ENABLE0x00000040); |
854 | } |
855 | |
856 | /* On all PCI adapters, we allow SCB paging */ |
857 | ahc->flags |= AHC_PAGESCBS; |
858 | error = ahc_softc_init(ahc); |
859 | if (error != 0) |
860 | goto error_out; |
861 | |
862 | ahc->bus_intr = ahc_pci_intr; |
863 | ahc->bus_chip_init = ahc_pci_chip_init; |
864 | |
865 | /* Remember how the card was setup in case there is no SEEPROM */ |
866 | if ((ahc_inb(ahc, HCNTRL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x87))) & POWRDN0x40) == 0) { |
867 | ahc_pause(ahc); |
868 | if ((ahc->features & AHC_ULTRA2) != 0) |
869 | our_id = ahc_inb(ahc, SCSIID_ULTRA2)(((ahc)->tag)->read_1(((ahc)->bsh), (0x0f))) & OID0x0f; |
870 | else |
871 | our_id = ahc_inb(ahc, SCSIID)(((ahc)->tag)->read_1(((ahc)->bsh), (0x05))) & OID0x0f; |
872 | sxfrctl1 = ahc_inb(ahc, SXFRCTL1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x02))) & STPWEN0x01; |
873 | scsiseq = ahc_inb(ahc, SCSISEQ)(((ahc)->tag)->read_1(((ahc)->bsh), (0x00))); |
874 | } else { |
875 | sxfrctl1 = STPWEN0x01; |
876 | our_id = 7; |
877 | scsiseq = 0; |
878 | } |
879 | |
880 | error = ahc_reset(ahc, /*reinit*/FALSE0); |
881 | if (error != 0) |
882 | goto error_out; |
883 | |
884 | if ((ahc->features & AHC_DT) != 0) { |
885 | u_int sfunct; |
886 | |
887 | /* Perform ALT-Mode Setup */ |
888 | sfunct = ahc_inb(ahc, SFUNCT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x9f))) & ~ALT_MODE0x80; |
889 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct | 0x80))); |
890 | ahc_outb(ahc, OPTIONMODE,(((ahc)->tag)->write_1(((ahc)->bsh), (0x08), (0x03|0x40 |0x10|0x08))) |
891 | OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS)(((ahc)->tag)->write_1(((ahc)->bsh), (0x08), (0x03|0x40 |0x10|0x08))); |
892 | ahc_outb(ahc, SFUNCT, sfunct)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct ))); |
893 | |
894 | /* Normal mode setup */ |
895 | ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN(((ahc)->tag)->write_1(((ahc)->bsh), (0x9d), (0x40|0x20 |0x10 |0x08))) |
896 | |TARGCRCENDEN)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9d), (0x40|0x20 |0x10 |0x08))); |
897 | } |
898 | |
899 | if (pci_intr_map(pa, &ih)) { |
900 | printf("%s: couldn't map interrupt\n", ahc_name(ahc)); |
901 | ahc_free(ahc); |
902 | return; |
903 | } |
904 | intrstr = pci_intr_string(pa->pa_pc, ih); |
905 | ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO0x3, |
906 | ahc_platform_intr, ahc, ahc->sc_dev.dv_xname); |
907 | if (ahc->ih == NULL((void *)0)) { |
908 | printf(": couldn't establish interrupt"); |
909 | if (intrstr != NULL((void *)0)) |
910 | printf(" at %s", intrstr); |
911 | printf("\n"); |
912 | ahc_free(ahc); |
913 | return; |
914 | } else |
915 | printf(": %s\n", intrstr ? intrstr : "?"); |
916 | |
917 | dscommand0 = ahc_inb(ahc, DSCOMMAND0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x84))); |
918 | dscommand0 |= MPARCKEN0x20|CACHETHEN0x80; |
919 | if ((ahc->features & AHC_ULTRA2) != 0) { |
920 | |
921 | /* |
922 | * DPARCKEN doesn't work correctly on |
923 | * some MBs so don't use it. |
924 | */ |
925 | dscommand0 &= ~DPARCKEN0x40; |
926 | } |
927 | |
928 | /* |
929 | * Handle chips that must have cache line |
930 | * streaming (dis/en)abled. |
931 | */ |
932 | if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) |
933 | dscommand0 |= CACHETHEN0x80; |
934 | |
935 | if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) |
936 | dscommand0 &= ~CACHETHEN0x80; |
937 | |
938 | ahc_outb(ahc, DSCOMMAND0, dscommand0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x84), (dscommand0 ))); |
939 | |
940 | ahc->pci_cachesize = |
941 | pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME0x0c) & CACHESIZE0x0000003ful; |
942 | ahc->pci_cachesize *= 4; |
943 | |
944 | if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 |
945 | && ahc->pci_cachesize == 4) { |
946 | pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME0x0c, 0); |
947 | ahc->pci_cachesize = 0; |
948 | } |
949 | |
950 | /* |
951 | * We cannot perform ULTRA speeds without the presence |
952 | * of the external precision resistor. |
953 | */ |
954 | if ((ahc->features & AHC_ULTRA) != 0) { |
955 | uint32_t devconfig; |
956 | |
957 | devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG0x40); |
958 | if ((devconfig & REXTVALID0x00001000ul) == 0) |
959 | ahc->features &= ~AHC_ULTRA; |
960 | } |
961 | |
962 | ahc->seep_config = malloc(sizeof(*ahc->seep_config), M_DEVBUF2, |
963 | M_NOWAIT0x0002 | M_ZERO0x0008); |
964 | if (ahc->seep_config == NULL((void *)0)) |
965 | goto error_out; |
966 | |
967 | /* See if we have a SEEPROM and perform auto-term */ |
968 | ahc_check_extport(ahc, &sxfrctl1); |
969 | |
970 | /* |
971 | * Take the LED out of diagnostic mode |
972 | */ |
973 | sblkctl = ahc_inb(ahc, SBLKCTL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x1f))); |
974 | ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)))(((ahc)->tag)->write_1(((ahc)->bsh), (0x1f), ((sblkctl & ~(0x80|0x40))))); |
975 | |
976 | if ((ahc->features & AHC_ULTRA2) != 0) { |
977 | ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX)(((ahc)->tag)->write_1(((ahc)->bsh), (0xfb), (0x07|0x70 ))); |
978 | } else { |
979 | ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100)(((ahc)->tag)->write_1(((ahc)->bsh), (0x86), (0xc0)) ); |
980 | } |
981 | |
982 | if (ahc->flags & AHC_USEDEFAULTS) { |
983 | /* |
984 | * PCI Adapter default setup |
985 | * Should only be used if the adapter does not have |
986 | * a SEEPROM. |
987 | */ |
988 | /* See if someone else set us up already */ |
989 | if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 |
990 | && scsiseq != 0) { |
991 | printf("%s: Using left over BIOS settings\n", |
992 | ahc_name(ahc)); |
993 | ahc->flags &= ~AHC_USEDEFAULTS; |
994 | ahc->flags |= AHC_BIOS_ENABLED; |
995 | } else { |
996 | /* |
997 | * Assume only one connector and always turn |
998 | * on termination. |
999 | */ |
1000 | our_id = 0x07; |
1001 | sxfrctl1 = STPWEN0x01; |
1002 | } |
1003 | ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI)(((ahc)->tag)->write_1(((ahc)->bsh), (0x5a), (our_id |0x20|0x40))); |
1004 | |
1005 | ahc->our_id = our_id; |
1006 | } |
1007 | |
1008 | /* |
1009 | * Take a look to see if we have external SRAM. |
1010 | * We currently do not attempt to use SRAM that is |
1011 | * shared among multiple controllers. |
1012 | */ |
1013 | ahc_probe_ext_scbram(ahc); |
1014 | |
1015 | /* |
1016 | * Record our termination setting for the |
1017 | * generic initialization routine. |
1018 | */ |
1019 | if ((sxfrctl1 & STPWEN0x01) != 0) |
1020 | ahc->flags |= AHC_TERM_ENB_A; |
1021 | |
1022 | /* |
1023 | * Save chip register configuration data for chip resets |
1024 | * that occur during runtime and resume events. |
1025 | */ |
1026 | ahc->bus_softc.pci_softc.devconfig = |
1027 | pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG0x40); |
1028 | ahc->bus_softc.pci_softc.command = |
1029 | pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04); |
1030 | ahc->bus_softc.pci_softc.csize_lattime = |
1031 | pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME0x0c); |
1032 | ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x84))); |
1033 | ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS)(((ahc)->tag)->read_1(((ahc)->bsh), (0x86))); |
1034 | if ((ahc->features & AHC_DT) != 0) { |
1035 | u_int sfunct; |
1036 | |
1037 | sfunct = ahc_inb(ahc, SFUNCT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x9f))) & ~ALT_MODE0x80; |
1038 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct | 0x80))); |
1039 | ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE)(((ahc)->tag)->read_1(((ahc)->bsh), (0x08))); |
1040 | ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT0x0a); |
1041 | ahc_outb(ahc, SFUNCT, sfunct)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct ))); |
1042 | ahc->bus_softc.pci_softc.crccontrol1 = |
1043 | ahc_inb(ahc, CRCCONTROL1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x9d))); |
1044 | } |
1045 | if ((ahc->features & AHC_MULTI_FUNC) != 0) |
1046 | ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR)(((ahc)->tag)->read_1(((ahc)->bsh), (0xf0))); |
1047 | |
1048 | if ((ahc->features & AHC_ULTRA2) != 0) |
1049 | ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH)(((ahc)->tag)->read_1(((ahc)->bsh), (0xfb))); |
1050 | |
1051 | /* Core initialization */ |
1052 | if (ahc_init(ahc)) |
1053 | goto error_out; |
1054 | |
1055 | ahc_attach(ahc); |
1056 | |
1057 | return; |
1058 | |
1059 | error_out: |
1060 | ahc_free(ahc); |
1061 | return; |
1062 | } |
1063 | |
1064 | static int |
1065 | ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, |
1066 | uint16_t subdevice, uint16_t subvendor) |
1067 | { |
1068 | int result; |
1069 | |
1070 | /* Default to invalid. */ |
1071 | result = 0; |
1072 | if (vendor == 0x9005 |
1073 | && subvendor == 0x9005 |
1074 | && subdevice != device |
1075 | && SUBID_9005_TYPE_KNOWN(subdevice)((((subdevice) & 0xF) == 0xF) || (((subdevice) & 0xF) == 0x0) || (((subdevice) & 0xF) == 0x1) || (((subdevice) & 0xF) == 0x3)) != 0) { |
1076 | |
1077 | switch (SUBID_9005_TYPE(subdevice)((subdevice) & 0xF)) { |
1078 | case SUBID_9005_TYPE_MB0xF: |
1079 | break; |
1080 | case SUBID_9005_TYPE_CARD0x0: |
1081 | case SUBID_9005_TYPE_LCCARD0x1: |
1082 | /* |
1083 | * Currently only trust Adaptec cards to |
1084 | * get the sub device info correct. |
1085 | */ |
1086 | if (DEVID_9005_TYPE(device)((device) & 0xF) == DEVID_9005_TYPE_HBA0x0) |
1087 | result = 1; |
1088 | break; |
1089 | case SUBID_9005_TYPE_RAID0x3: |
1090 | break; |
1091 | default: |
1092 | break; |
1093 | } |
1094 | } |
1095 | return (result); |
1096 | } |
1097 | |
1098 | |
1099 | /* |
1100 | * Test for the presence of external sram in an |
1101 | * "unshared" configuration. |
1102 | */ |
1103 | static int |
1104 | ahc_ext_scbram_present(struct ahc_softc *ahc) |
1105 | { |
1106 | u_int chip; |
1107 | int ramps; |
1108 | int single_user; |
1109 | uint32_t devconfig; |
1110 | |
1111 | chip = ahc->chip & AHC_CHIPID_MASK; |
1112 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG0x40); |
1113 | single_user = (devconfig & MPORTMODE0x00000400ul) != 0; |
1114 | |
1115 | if ((ahc->features & AHC_ULTRA2) != 0) |
1116 | ramps = (ahc_inb(ahc, DSCOMMAND0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x84))) & RAMPS0x04) != 0; |
1117 | else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) |
1118 | /* |
1119 | * External SCBRAM arbitration is flakey |
1120 | * on these chips. Unfortunately this means |
1121 | * we don't use the extra SCB ram space on the |
1122 | * 3940AUW. |
1123 | */ |
1124 | ramps = 0; |
1125 | else if (chip >= AHC_AIC7870) |
1126 | ramps = (devconfig & RAMPSM0x00000200ul) != 0; |
1127 | else |
1128 | ramps = 0; |
1129 | |
1130 | if (ramps && single_user) |
1131 | return (1); |
1132 | return (0); |
1133 | } |
1134 | |
1135 | /* |
1136 | * Enable external scbram. |
1137 | */ |
1138 | static void |
1139 | ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, |
1140 | int fast, int large) |
1141 | { |
1142 | uint32_t devconfig; |
1143 | |
1144 | if (ahc->features & AHC_MULTI_FUNC) { |
1145 | /* |
1146 | * Set the SCB Base addr (highest address bit) |
1147 | * depending on which channel we are. |
1148 | */ |
1149 | ahc_outb(ahc, SCBBADDR, ahc->bd->func)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf0), (ahc-> bd->func))); |
1150 | } |
1151 | |
1152 | ahc->flags &= ~AHC_LSCBS_ENABLED; |
1153 | if (large) |
1154 | ahc->flags |= AHC_LSCBS_ENABLED; |
1155 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG0x40); |
1156 | if ((ahc->features & AHC_ULTRA2) != 0) { |
1157 | u_int dscommand0; |
1158 | |
1159 | dscommand0 = ahc_inb(ahc, DSCOMMAND0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x84))); |
1160 | if (enable) |
1161 | dscommand0 &= ~INTSCBRAMSEL0x08; |
1162 | else |
1163 | dscommand0 |= INTSCBRAMSEL0x08; |
1164 | if (large) |
1165 | dscommand0 &= ~USCBSIZE320x02; |
1166 | else |
1167 | dscommand0 |= USCBSIZE320x02; |
1168 | ahc_outb(ahc, DSCOMMAND0, dscommand0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x84), (dscommand0 ))); |
1169 | } else { |
1170 | if (fast) |
1171 | devconfig &= ~EXTSCBTIME0x00000020ul; |
1172 | else |
1173 | devconfig |= EXTSCBTIME0x00000020ul; |
1174 | if (enable) |
1175 | devconfig &= ~SCBRAMSEL0x00000080ul; |
1176 | else |
1177 | devconfig |= SCBRAMSEL0x00000080ul; |
1178 | if (large) |
1179 | devconfig &= ~SCBSIZE320x00010000ul; |
1180 | else |
1181 | devconfig |= SCBSIZE320x00010000ul; |
1182 | } |
1183 | if (pcheck) |
1184 | devconfig |= EXTSCBPEN0x00000010ul; |
1185 | else |
1186 | devconfig &= ~EXTSCBPEN0x00000010ul; |
1187 | |
1188 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG0x40, devconfig); |
1189 | } |
1190 | |
1191 | /* |
1192 | * Take a look to see if we have external SRAM. |
1193 | * We currently do not attempt to use SRAM that is |
1194 | * shared among multiple controllers. |
1195 | */ |
1196 | static void |
1197 | ahc_probe_ext_scbram(struct ahc_softc *ahc) |
1198 | { |
1199 | int num_scbs; |
1200 | int test_num_scbs; |
1201 | int enable; |
1202 | int pcheck; |
1203 | int fast; |
1204 | int large; |
1205 | |
1206 | enable = FALSE0; |
1207 | pcheck = FALSE0; |
1208 | fast = FALSE0; |
1209 | large = FALSE0; |
1210 | num_scbs = 0; |
1211 | |
1212 | if (ahc_ext_scbram_present(ahc) == 0) |
1213 | goto done; |
1214 | |
1215 | /* |
1216 | * Probe for the best parameters to use. |
1217 | */ |
1218 | ahc_scbram_config(ahc, /*enable*/TRUE1, pcheck, fast, large); |
1219 | num_scbs = ahc_probe_scbs(ahc); |
1220 | if (num_scbs == 0) { |
1221 | /* The SRAM wasn't really present. */ |
1222 | goto done; |
1223 | } |
1224 | enable = TRUE1; |
1225 | |
1226 | /* |
1227 | * Clear any outstanding parity error |
1228 | * and ensure that parity error reporting |
1229 | * is enabled. |
1230 | */ |
1231 | ahc_outb(ahc, SEQCTL, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (0))); |
1232 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
1233 | ahc_outb(ahc, CLRINT, CLRBRKADRINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x08)) ); |
1234 | |
1235 | /* Now see if we can do parity */ |
1236 | ahc_scbram_config(ahc, enable, /*pcheck*/TRUE1, fast, large); |
1237 | num_scbs = ahc_probe_scbs(ahc); |
1238 | if ((ahc_inb(ahc, INTSTAT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x91))) & BRKADRINT0x08) == 0 |
1239 | || (ahc_inb(ahc, ERROR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x92))) & MPARERR0x20) == 0) |
1240 | pcheck = TRUE1; |
1241 | |
1242 | /* Clear any resulting parity error */ |
1243 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
1244 | ahc_outb(ahc, CLRINT, CLRBRKADRINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x08)) ); |
1245 | |
1246 | /* Now see if we can do fast timing */ |
1247 | ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE1, large); |
1248 | test_num_scbs = ahc_probe_scbs(ahc); |
1249 | if (test_num_scbs == num_scbs |
1250 | && ((ahc_inb(ahc, INTSTAT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x91))) & BRKADRINT0x08) == 0 |
1251 | || (ahc_inb(ahc, ERROR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x92))) & MPARERR0x20) == 0)) |
1252 | fast = TRUE1; |
1253 | |
1254 | /* |
1255 | * See if we can use large SCBs and still maintain |
1256 | * the same overall count of SCBs. |
1257 | */ |
1258 | if ((ahc->features & AHC_LARGE_SCBS) != 0) { |
1259 | ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE1); |
1260 | test_num_scbs = ahc_probe_scbs(ahc); |
1261 | if (test_num_scbs >= num_scbs) { |
1262 | large = TRUE1; |
1263 | num_scbs = test_num_scbs; |
1264 | if (num_scbs >= 64) { |
1265 | /* |
1266 | * We have enough space to move the |
1267 | * "busy targets table" into SCB space |
1268 | * and make it qualify all the way to the |
1269 | * lun level. |
1270 | */ |
1271 | ahc->flags |= AHC_SCB_BTT; |
1272 | } |
1273 | } |
1274 | } |
1275 | done: |
1276 | /* |
1277 | * Disable parity error reporting until we |
1278 | * can load instruction ram. |
1279 | */ |
1280 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (0x80|0x20 ))); |
1281 | /* Clear any latched parity error */ |
1282 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
1283 | ahc_outb(ahc, CLRINT, CLRBRKADRINT)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x08)) ); |
1284 | if (1/*bootverbose*/ && enable) { |
1285 | printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", |
1286 | ahc_name(ahc), fast ? "fast" : "slow", |
1287 | pcheck ? ", parity checking enabled" : "", |
1288 | large ? 64 : 32); |
1289 | } |
1290 | ahc_scbram_config(ahc, enable, pcheck, fast, large); |
1291 | } |
1292 | |
1293 | #if 0 |
1294 | /* |
1295 | * Perform some simple tests that should catch situations where |
1296 | * our registers are invalidly mapped. |
1297 | */ |
1298 | int |
1299 | ahc_pci_test_register_access(struct ahc_softc *ahc) |
1300 | { |
1301 | int error; |
1302 | u_int status1; |
1303 | uint32_t cmd; |
1304 | uint8_t hcntrl; |
1305 | |
1306 | error = EIO5; |
1307 | |
1308 | /* |
1309 | * Enable PCI error interrupt status, but suppress NMIs |
1310 | * generated by SERR raised due to target aborts. |
1311 | */ |
1312 | cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); |
1313 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, |
1314 | cmd & ~PCIM_CMD_SERRESPEN); |
1315 | |
1316 | /* |
1317 | * First a simple test to see if any |
1318 | * registers can be read. Reading |
1319 | * HCNTRL has no side effects and has |
1320 | * at least one bit that is guaranteed to |
1321 | * be zero so it is a good register to |
1322 | * use for this test. |
1323 | */ |
1324 | hcntrl = ahc_inb(ahc, HCNTRL)(((ahc)->tag)->read_1(((ahc)->bsh), (0x87))); |
1325 | if (hcntrl == 0xFF) |
1326 | goto fail; |
1327 | |
1328 | /* |
1329 | * Next create a situation where write combining |
1330 | * or read prefetching could be initiated by the |
1331 | * CPU or host bridge. Our device does not support |
1332 | * either, so look for data corruption and/or flagged |
1333 | * PCI errors. |
1334 | */ |
1335 | ahc_outb(ahc, HCNTRL, hcntrl|PAUSE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x87), (hcntrl |0x04))); |
1336 | while (ahc_is_paused(ahc) == 0) |
1337 | ; |
1338 | ahc_outb(ahc, SEQCTL, PERRORDIS)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (0x80)) ); |
1339 | ahc_outb(ahc, SCBPTR, 0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x90), (0))); |
1340 | ahc_outl(ahc, SCB_BASE0xa0, 0x5aa555aa); |
1341 | if (ahc_inl(ahc, SCB_BASE0xa0) != 0x5aa555aa) |
1342 | goto fail; |
1343 | |
1344 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, |
1345 | PCI_COMMAND_STATUS_REG0x04 + 1); |
1346 | if ((status1 & STA0x08) != 0) |
1347 | goto fail; |
1348 | |
1349 | error = 0; |
1350 | |
1351 | fail: |
1352 | /* Silently clear any latched errors. */ |
1353 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG0x04 + 1); |
1354 | ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, |
1355 | status1, /*bytes*/1); |
1356 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
1357 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS)(((ahc)->tag)->write_1(((ahc)->bsh), (0x60), (0x80|0x20 ))); |
1358 | ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); |
1359 | return (error); |
1360 | } |
1361 | #endif |
1362 | |
1363 | void |
1364 | ahc_pci_intr(struct ahc_softc *ahc) |
1365 | { |
1366 | u_int error; |
1367 | u_int status1; |
1368 | |
1369 | error = ahc_inb(ahc, ERROR)(((ahc)->tag)->read_1(((ahc)->bsh), (0x92))); |
1370 | if ((error & PCIERRSTAT0x40) == 0) |
1371 | return; |
1372 | |
1373 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG0x04); |
1374 | |
1375 | printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", |
1376 | ahc_name(ahc), |
1377 | ahc_inb(ahc, SEQADDR0)(((ahc)->tag)->read_1(((ahc)->bsh), (0x62))) | (ahc_inb(ahc, SEQADDR1)(((ahc)->tag)->read_1(((ahc)->bsh), (0x63))) << 8)); |
1378 | |
1379 | if (status1 & DPE0x80) { |
1380 | printf("%s: Data Parity Error Detected during address " |
1381 | "or write data phase\n", ahc_name(ahc)); |
1382 | } |
1383 | if (status1 & SSE0x40) { |
1384 | printf("%s: Signal System Error Detected\n", ahc_name(ahc)); |
1385 | } |
1386 | if (status1 & RMA0x20) { |
1387 | printf("%s: Received a Master Abort\n", ahc_name(ahc)); |
1388 | } |
1389 | if (status1 & RTA0x10) { |
1390 | printf("%s: Received a Target Abort\n", ahc_name(ahc)); |
1391 | } |
1392 | if (status1 & STA0x08) { |
1393 | printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); |
1394 | } |
1395 | if (status1 & DPR0x01) { |
1396 | printf("%s: Data Parity Error has been reported via PERR#\n", |
1397 | ahc_name(ahc)); |
1398 | } |
1399 | |
1400 | /* Clear latched errors. */ |
1401 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG0x04, status1); |
1402 | |
1403 | if ((status1 & (DPE0x80|SSE0x40|RMA0x20|RTA0x10|STA0x08|DPR0x01)) == 0) { |
1404 | printf("%s: Latched PCIERR interrupt with " |
1405 | "no status bits set\n", ahc_name(ahc)); |
1406 | } else { |
1407 | ahc_outb(ahc, CLRINT, CLRPARERR)(((ahc)->tag)->write_1(((ahc)->bsh), (0x92), (0x10)) ); |
1408 | } |
1409 | |
1410 | ahc_unpause(ahc); |
1411 | } |
1412 | |
1413 | static int |
1414 | ahc_pci_chip_init(struct ahc_softc *ahc) |
1415 | { |
1416 | ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0)(((ahc)->tag)->write_1(((ahc)->bsh), (0x84), (ahc-> bus_softc.pci_softc.dscommand0))); |
1417 | ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus)(((ahc)->tag)->write_1(((ahc)->bsh), (0x86), (ahc-> bus_softc.pci_softc.dspcistatus))); |
1418 | if ((ahc->features & AHC_DT) != 0) { |
1419 | u_int sfunct; |
1420 | |
1421 | sfunct = ahc_inb(ahc, SFUNCT)(((ahc)->tag)->read_1(((ahc)->bsh), (0x9f))) & ~ALT_MODE0x80; |
1422 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct | 0x80))); |
1423 | ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode)(((ahc)->tag)->write_1(((ahc)->bsh), (0x08), (ahc-> bus_softc.pci_softc.optionmode))); |
1424 | ahc_outw(ahc, TARGCRCCNT0x0a, ahc->bus_softc.pci_softc.targcrccnt); |
1425 | ahc_outb(ahc, SFUNCT, sfunct)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9f), (sfunct ))); |
1426 | ahc_outb(ahc, CRCCONTROL1,(((ahc)->tag)->write_1(((ahc)->bsh), (0x9d), (ahc-> bus_softc.pci_softc.crccontrol1))) |
1427 | ahc->bus_softc.pci_softc.crccontrol1)(((ahc)->tag)->write_1(((ahc)->bsh), (0x9d), (ahc-> bus_softc.pci_softc.crccontrol1))); |
1428 | } |
1429 | if ((ahc->features & AHC_MULTI_FUNC) != 0) |
1430 | ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr)(((ahc)->tag)->write_1(((ahc)->bsh), (0xf0), (ahc-> bus_softc.pci_softc.scbbaddr))); |
1431 | |
1432 | if ((ahc->features & AHC_ULTRA2) != 0) |
1433 | ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh)(((ahc)->tag)->write_1(((ahc)->bsh), (0xfb), (ahc-> bus_softc.pci_softc.dff_thrsh))); |
1434 | |
1435 | return (ahc_chip_init(ahc)); |
1436 | } |
1437 | |
1438 | static int |
1439 | ahc_aic785X_setup(struct ahc_softc *ahc) |
1440 | { |
1441 | uint8_t rev; |
1442 | |
1443 | ahc->channel = 'A'; |
1444 | ahc->chip = AHC_AIC7850; |
1445 | ahc->features = AHC_AIC7850_FE; |
1446 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
1447 | rev = PCI_REVISION(ahc->bd->class)(((ahc->bd->class) >> 0) & 0xff); |
1448 | if (rev >= 1) |
1449 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
1450 | ahc->instruction_ram_size = 512; |
1451 | return (0); |
1452 | } |
1453 | |
1454 | static int |
1455 | ahc_aic7860_setup(struct ahc_softc *ahc) |
1456 | { |
1457 | uint8_t rev; |
1458 | |
1459 | ahc->channel = 'A'; |
1460 | ahc->chip = AHC_AIC7860; |
1461 | ahc->features = AHC_AIC7860_FE; |
1462 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
1463 | rev = PCI_REVISION(ahc->bd->class)(((ahc->bd->class) >> 0) & 0xff); |
1464 | if (rev >= 1) |
1465 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
1466 | ahc->instruction_ram_size = 512; |
1467 | return (0); |
1468 | } |
1469 | |
1470 | static int |
1471 | ahc_apa1480_setup(struct ahc_softc *ahc) |
1472 | { |
1473 | int error; |
1474 | |
1475 | error = ahc_aic7860_setup(ahc); |
1476 | if (error != 0) |
1477 | return (error); |
1478 | ahc->features |= AHC_REMOVABLE; |
1479 | return (0); |
1480 | } |
1481 | |
1482 | static int |
1483 | ahc_aic7870_setup(struct ahc_softc *ahc) |
1484 | { |
1485 | |
1486 | ahc->channel = 'A'; |
1487 | ahc->chip = AHC_AIC7870; |
1488 | ahc->features = AHC_AIC7870_FE; |
1489 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
1490 | ahc->instruction_ram_size = 512; |
1491 | return (0); |
1492 | } |
1493 | |
1494 | static int |
1495 | ahc_aha394X_setup(struct ahc_softc *ahc) |
1496 | { |
1497 | int error; |
1498 | |
1499 | error = ahc_aic7870_setup(ahc); |
1500 | if (error == 0) |
1501 | error = ahc_aha394XX_setup(ahc); |
1502 | return (error); |
1503 | } |
1504 | |
1505 | static int |
1506 | ahc_aha398X_setup(struct ahc_softc *ahc) |
1507 | { |
1508 | int error; |
1509 | |
1510 | error = ahc_aic7870_setup(ahc); |
1511 | if (error == 0) |
1512 | error = ahc_aha398XX_setup(ahc); |
1513 | return (error); |
1514 | } |
1515 | |
1516 | static int |
1517 | ahc_aha494X_setup(struct ahc_softc *ahc) |
1518 | { |
1519 | int error; |
1520 | |
1521 | error = ahc_aic7870_setup(ahc); |
1522 | if (error == 0) |
1523 | error = ahc_aha494XX_setup(ahc); |
1524 | return (error); |
1525 | } |
1526 | |
1527 | static int |
1528 | ahc_aic7880_setup(struct ahc_softc *ahc) |
1529 | { |
1530 | uint8_t rev; |
1531 | |
1532 | ahc->channel = 'A'; |
1533 | ahc->chip = AHC_AIC7880; |
1534 | ahc->features = AHC_AIC7880_FE; |
1535 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG; |
1536 | rev = PCI_REVISION(ahc->bd->class)(((ahc->bd->class) >> 0) & 0xff); |
1537 | if (rev >= 1) { |
1538 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
1539 | } else { |
1540 | ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
1541 | } |
1542 | ahc->instruction_ram_size = 512; |
1543 | return (0); |
1544 | } |
1545 | |
1546 | static int |
1547 | ahc_aha2940Pro_setup(struct ahc_softc *ahc) |
1548 | { |
1549 | |
1550 | ahc->flags |= AHC_INT50_SPEEDFLEX; |
1551 | return (ahc_aic7880_setup(ahc)); |
1552 | } |
1553 | |
1554 | static int |
1555 | ahc_aha394XU_setup(struct ahc_softc *ahc) |
1556 | { |
1557 | int error; |
1558 | |
1559 | error = ahc_aic7880_setup(ahc); |
1560 | if (error == 0) |
1561 | error = ahc_aha394XX_setup(ahc); |
1562 | return (error); |
1563 | } |
1564 | |
1565 | static int |
1566 | ahc_aha398XU_setup(struct ahc_softc *ahc) |
1567 | { |
1568 | int error; |
1569 | |
1570 | error = ahc_aic7880_setup(ahc); |
1571 | if (error == 0) |
1572 | error = ahc_aha398XX_setup(ahc); |
1573 | return (error); |
1574 | } |
1575 | |
1576 | static int |
1577 | ahc_aic7890_setup(struct ahc_softc *ahc) |
1578 | { |
1579 | uint8_t rev; |
1580 | |
1581 | ahc->channel = 'A'; |
1582 | ahc->chip = AHC_AIC7890; |
1583 | ahc->features = AHC_AIC7890_FE; |
1584 | ahc->flags |= AHC_NEWEEPROM_FMT; |
1585 | rev = PCI_REVISION(ahc->bd->class)(((ahc->bd->class) >> 0) & 0xff); |
1586 | if (rev == 0) |
1587 | ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; |
1588 | ahc->instruction_ram_size = 768; |
1589 | return (0); |
1590 | } |
1591 | |
1592 | static int |
1593 | ahc_aic7892_setup(struct ahc_softc *ahc) |
1594 | { |
1595 | |
1596 | ahc->channel = 'A'; |
1597 | ahc->chip = AHC_AIC7892; |
1598 | ahc->features = AHC_AIC7892_FE; |
1599 | ahc->flags |= AHC_NEWEEPROM_FMT; |
1600 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
1601 | ahc->instruction_ram_size = 1024; |
1602 | return (0); |
1603 | } |
1604 | |
1605 | static int |
1606 | ahc_aic7895_setup(struct ahc_softc *ahc) |
1607 | { |
1608 | uint8_t rev; |
1609 | |
1610 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
1611 | /* |
1612 | * The 'C' revision of the aic7895 has a few additional features. |
1613 | */ |
1614 | rev = PCI_REVISION(ahc->bd->class)(((ahc->bd->class) >> 0) & 0xff); |
1615 | if (rev >= 4) { |
1616 | ahc->chip = AHC_AIC7895C; |
1617 | ahc->features = AHC_AIC7895C_FE; |
1618 | } else { |
1619 | u_int command; |
1620 | |
1621 | ahc->chip = AHC_AIC7895; |
1622 | ahc->features = AHC_AIC7895_FE; |
1623 | |
1624 | /* |
1625 | * The BIOS disables the use of MWI transactions |
1626 | * since it does not have the MWI bug work around |
1627 | * we have. Disabling MWI reduces performance, so |
1628 | * turn it on again. |
1629 | */ |
1630 | command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG0x04); |
1631 | command |= PCI_COMMAND_INVALIDATE_ENABLE0x00000010; |
1632 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG0x04, command); |
1633 | ahc->bugs |= AHC_PCI_MWI_BUG; |
1634 | } |
1635 | /* |
1636 | * XXX Does CACHETHEN really not work??? What about PCI retry? |
1637 | * on C level chips. Need to test, but for now, play it safe. |
1638 | */ |
1639 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG |
1640 | | AHC_CACHETHEN_BUG; |
1641 | |
1642 | #if 0 |
1643 | uint32_t devconfig; |
1644 | |
1645 | /* |
1646 | * Cachesize must also be zero due to stray DAC |
1647 | * problem when sitting behind some bridges. |
1648 | */ |
1649 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME0x0c, 0); |
1650 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG0x40); |
1651 | devconfig |= MRDCEN0x00000040ul; |
1652 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG0x40, devconfig); |
1653 | #endif |
1654 | ahc->flags |= AHC_NEWEEPROM_FMT; |
1655 | ahc->instruction_ram_size = 512; |
1656 | return (0); |
1657 | } |
1658 | |
1659 | static int |
1660 | ahc_aic7896_setup(struct ahc_softc *ahc) |
1661 | { |
1662 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
1663 | ahc->chip = AHC_AIC7896; |
1664 | ahc->features = AHC_AIC7896_FE; |
1665 | ahc->flags |= AHC_NEWEEPROM_FMT; |
1666 | ahc->bugs |= AHC_CACHETHEN_DIS_BUG; |
1667 | ahc->instruction_ram_size = 768; |
1668 | return (0); |
1669 | } |
1670 | |
1671 | static int |
1672 | ahc_aic7899_setup(struct ahc_softc *ahc) |
1673 | { |
1674 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
1675 | ahc->chip = AHC_AIC7899; |
1676 | ahc->features = AHC_AIC7899_FE; |
1677 | ahc->flags |= AHC_NEWEEPROM_FMT; |
1678 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
1679 | ahc->instruction_ram_size = 1024; |
1680 | return (0); |
1681 | } |
1682 | |
1683 | static int |
1684 | ahc_aha29160C_setup(struct ahc_softc *ahc) |
1685 | { |
1686 | int error; |
1687 | |
1688 | error = ahc_aic7899_setup(ahc); |
1689 | if (error != 0) |
1690 | return (error); |
1691 | ahc->features |= AHC_REMOVABLE; |
1692 | return (0); |
1693 | } |
1694 | |
1695 | static int |
1696 | ahc_raid_setup(struct ahc_softc *ahc) |
1697 | { |
1698 | printf("RAID functionality unsupported\n"); |
1699 | return (ENXIO6); |
1700 | } |
1701 | |
1702 | static int |
1703 | ahc_aha394XX_setup(struct ahc_softc *ahc) |
1704 | { |
1705 | |
1706 | switch (ahc->bd->dev) { |
1707 | case AHC_394X_SLOT_CHANNEL_A4: |
1708 | ahc->channel = 'A'; |
1709 | break; |
1710 | case AHC_394X_SLOT_CHANNEL_B5: |
1711 | ahc->channel = 'B'; |
1712 | break; |
1713 | default: |
1714 | printf("adapter at unexpected slot %d\n" |
1715 | "unable to map to a channel\n", |
1716 | ahc->bd->dev); |
1717 | ahc->channel = 'A'; |
1718 | } |
1719 | return (0); |
1720 | } |
1721 | |
1722 | static int |
1723 | ahc_aha398XX_setup(struct ahc_softc *ahc) |
1724 | { |
1725 | |
1726 | switch (ahc->bd->dev) { |
1727 | case AHC_398X_SLOT_CHANNEL_A4: |
1728 | ahc->channel = 'A'; |
1729 | break; |
1730 | case AHC_398X_SLOT_CHANNEL_B8: |
1731 | ahc->channel = 'B'; |
1732 | break; |
1733 | case AHC_398X_SLOT_CHANNEL_C12: |
1734 | ahc->channel = 'C'; |
1735 | break; |
1736 | default: |
1737 | printf("adapter at unexpected slot %d\n" |
1738 | "unable to map to a channel\n", |
1739 | ahc->bd->dev); |
1740 | ahc->channel = 'A'; |
1741 | break; |
1742 | } |
1743 | ahc->flags |= AHC_LARGE_SEEPROM; |
1744 | return (0); |
1745 | } |
1746 | |
1747 | static int |
1748 | ahc_aha494XX_setup(struct ahc_softc *ahc) |
1749 | { |
1750 | |
1751 | switch (ahc->bd->dev) { |
1752 | case AHC_494X_SLOT_CHANNEL_A4: |
1753 | ahc->channel = 'A'; |
1754 | break; |
1755 | case AHC_494X_SLOT_CHANNEL_B5: |
1756 | ahc->channel = 'B'; |
1757 | break; |
1758 | case AHC_494X_SLOT_CHANNEL_C6: |
1759 | ahc->channel = 'C'; |
1760 | break; |
1761 | case AHC_494X_SLOT_CHANNEL_D7: |
1762 | ahc->channel = 'D'; |
1763 | break; |
1764 | default: |
1765 | printf("adapter at unexpected slot %d\n" |
1766 | "unable to map to a channel\n", |
1767 | ahc->bd->dev); |
1768 | ahc->channel = 'A'; |
1769 | } |
1770 | ahc->flags |= AHC_LARGE_SEEPROM; |
1771 | return (0); |
1772 | } |