| File: | dev/pci/if_em_hw.c |
| Warning: | line 5979, column 2 Value stored to 'ret_val' is never read |
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| 1 | /******************************************************************************* |
| 2 | |
| 3 | Copyright (c) 2001-2005, Intel Corporation |
| 4 | All rights reserved. |
| 5 | |
| 6 | Redistribution and use in source and binary forms, with or without |
| 7 | modification, are permitted provided that the following conditions are met: |
| 8 | |
| 9 | 1. Redistributions of source code must retain the above copyright notice, |
| 10 | this list of conditions and the following disclaimer. |
| 11 | |
| 12 | 2. Redistributions in binary form must reproduce the above copyright |
| 13 | notice, this list of conditions and the following disclaimer in the |
| 14 | documentation and/or other materials provided with the distribution. |
| 15 | |
| 16 | 3. Neither the name of the Intel Corporation nor the names of its |
| 17 | contributors may be used to endorse or promote products derived from |
| 18 | this software without specific prior written permission. |
| 19 | |
| 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 30 | POSSIBILITY OF SUCH DAMAGE. |
| 31 | |
| 32 | *******************************************************************************/ |
| 33 | |
| 34 | /* $OpenBSD: if_em_hw.c,v 1.119 2023/12/03 00:19:25 jsg Exp $ */ |
| 35 | /* |
| 36 | * if_em_hw.c Shared functions for accessing and configuring the MAC |
| 37 | */ |
| 38 | |
| 39 | #include <sys/param.h> |
| 40 | #include <sys/systm.h> |
| 41 | #include <sys/sockio.h> |
| 42 | #include <sys/mbuf.h> |
| 43 | #include <sys/malloc.h> |
| 44 | #include <sys/kernel.h> |
| 45 | #include <sys/device.h> |
| 46 | #include <sys/socket.h> |
| 47 | #include <sys/kstat.h> |
| 48 | |
| 49 | #include <net/if.h> |
| 50 | #include <net/if_media.h> |
| 51 | |
| 52 | #include <netinet/in.h> |
| 53 | #include <netinet/if_ether.h> |
| 54 | |
| 55 | #include <uvm/uvm_extern.h> |
| 56 | |
| 57 | #include <dev/pci/pcireg.h> |
| 58 | #include <dev/pci/pcivar.h> |
| 59 | |
| 60 | #include <dev/pci/if_em.h> |
| 61 | #include <dev/pci/if_em_hw.h> |
| 62 | #include <dev/pci/if_em_soc.h> |
| 63 | |
| 64 | #include <dev/mii/rgephyreg.h> |
| 65 | |
| 66 | #define STATIC |
| 67 | |
| 68 | static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); |
| 69 | static void em_swfw_sync_release(struct em_hw *, uint16_t); |
| 70 | static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); |
| 71 | static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); |
| 72 | static int32_t em_get_software_semaphore(struct em_hw *); |
| 73 | static void em_release_software_semaphore(struct em_hw *); |
| 74 | |
| 75 | static int32_t em_check_downshift(struct em_hw *); |
| 76 | static void em_clear_vfta(struct em_hw *); |
| 77 | void em_clear_vfta_i350(struct em_hw *); |
| 78 | static int32_t em_commit_shadow_ram(struct em_hw *); |
| 79 | static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); |
| 80 | static int32_t em_config_fc_after_link_up(struct em_hw *); |
| 81 | static int32_t em_match_gig_phy(struct em_hw *); |
| 82 | static int32_t em_detect_gig_phy(struct em_hw *); |
| 83 | static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); |
| 84 | static int32_t em_get_auto_rd_done(struct em_hw *); |
| 85 | static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); |
| 86 | static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); |
| 87 | static int32_t em_get_phy_cfg_done(struct em_hw *); |
| 88 | static int32_t em_get_software_flag(struct em_hw *); |
| 89 | static int32_t em_ich8_cycle_init(struct em_hw *); |
| 90 | static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); |
| 91 | static int32_t em_id_led_init(struct em_hw *); |
| 92 | static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, |
| 93 | uint32_t); |
| 94 | static int32_t em_init_lcd_from_nvm(struct em_hw *); |
| 95 | static int32_t em_phy_no_cable_workaround(struct em_hw *); |
| 96 | static void em_init_rx_addrs(struct em_hw *); |
| 97 | static void em_initialize_hardware_bits(struct em_softc *); |
| 98 | static void em_toggle_lanphypc_pch_lpt(struct em_hw *); |
| 99 | static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force); |
| 100 | static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); |
| 101 | static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); |
| 102 | static int32_t em_mng_enable_host_if(struct em_hw *); |
| 103 | static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, |
| 104 | uint16_t *); |
| 105 | static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, |
| 106 | uint16_t *data); |
| 107 | static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); |
| 108 | static void em_put_hw_eeprom_semaphore(struct em_hw *); |
| 109 | static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); |
| 110 | static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); |
| 111 | static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); |
| 112 | static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); |
| 113 | static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); |
| 114 | static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, |
| 115 | uint16_t *); |
| 116 | static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, |
| 117 | uint16_t); |
| 118 | static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, |
| 119 | uint16_t *); |
| 120 | static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, |
| 121 | uint16_t *); |
| 122 | static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, |
| 123 | uint16_t *); |
| 124 | static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); |
| 125 | static void em_release_software_flag(struct em_hw *); |
| 126 | static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); |
| 127 | static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); |
| 128 | static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); |
| 129 | static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); |
| 130 | static void em_set_pci_express_master_disable(struct em_hw *); |
| 131 | static int32_t em_wait_autoneg(struct em_hw *); |
| 132 | static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); |
| 133 | static int32_t em_set_phy_type(struct em_hw *); |
| 134 | static void em_phy_init_script(struct em_hw *); |
| 135 | static int32_t em_setup_copper_link(struct em_hw *); |
| 136 | static int32_t em_setup_fiber_serdes_link(struct em_hw *); |
| 137 | static int32_t em_adjust_serdes_amplitude(struct em_hw *); |
| 138 | static int32_t em_phy_force_speed_duplex(struct em_hw *); |
| 139 | static int32_t em_config_mac_to_phy(struct em_hw *); |
| 140 | static void em_raise_mdi_clk(struct em_hw *, uint32_t *); |
| 141 | static void em_lower_mdi_clk(struct em_hw *, uint32_t *); |
| 142 | static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); |
| 143 | static uint16_t em_shift_in_mdi_bits(struct em_hw *); |
| 144 | static int32_t em_phy_reset_dsp(struct em_hw *); |
| 145 | static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, |
| 146 | uint16_t *); |
| 147 | static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, |
| 148 | uint16_t *); |
| 149 | static int32_t em_spi_eeprom_ready(struct em_hw *); |
| 150 | static void em_raise_ee_clk(struct em_hw *, uint32_t *); |
| 151 | static void em_lower_ee_clk(struct em_hw *, uint32_t *); |
| 152 | static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); |
| 153 | static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); |
| 154 | static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); |
| 155 | static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); |
| 156 | static int32_t em_acquire_eeprom(struct em_hw *); |
| 157 | static void em_release_eeprom(struct em_hw *); |
| 158 | static void em_standby_eeprom(struct em_hw *); |
| 159 | static int32_t em_set_vco_speed(struct em_hw *); |
| 160 | static int32_t em_polarity_reversal_workaround(struct em_hw *); |
| 161 | static int32_t em_set_phy_mode(struct em_hw *); |
| 162 | static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); |
| 163 | static uint8_t em_calculate_mng_checksum(char *, uint32_t); |
| 164 | static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); |
| 165 | static int32_t em_configure_kmrn_for_1000(struct em_hw *); |
| 166 | static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); |
| 167 | static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); |
| 168 | int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); |
| 169 | int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); |
| 170 | int32_t em_link_stall_workaround_hv(struct em_hw *); |
| 171 | int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); |
| 172 | int32_t em_k1_workaround_lv(struct em_hw *); |
| 173 | int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); |
| 174 | int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); |
| 175 | void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); |
| 176 | int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, |
| 177 | uint16_t *, boolean_t); |
| 178 | int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, |
| 179 | uint16_t *, boolean_t); |
| 180 | int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, |
| 181 | boolean_t); |
| 182 | int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); |
| 183 | void em_power_up_serdes_link_82575(struct em_hw *); |
| 184 | int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, |
| 185 | uint16_t *); |
| 186 | int32_t em_set_eee_i350(struct em_hw *); |
| 187 | int32_t em_set_eee_pchlan(struct em_hw *); |
| 188 | int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); |
| 189 | int32_t em_initialize_M88E1512_phy(struct em_hw *); |
| 190 | |
| 191 | /* IGP cable length table */ |
| 192 | static const uint16_t |
| 193 | em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE128] = |
| 194 | {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
| 195 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
| 196 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
| 197 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
| 198 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
| 199 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
| 200 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
| 201 | 110, |
| 202 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, |
| 203 | 120}; |
| 204 | |
| 205 | static const uint16_t |
| 206 | em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE113] = |
| 207 | {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
| 208 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
| 209 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
| 210 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
| 211 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
| 212 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
| 213 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, |
| 214 | 121, 124}; |
| 215 | |
| 216 | /****************************************************************************** |
| 217 | * Set the phy type member in the hw struct. |
| 218 | * |
| 219 | * hw - Struct containing variables accessed by shared code |
| 220 | *****************************************************************************/ |
| 221 | STATIC int32_t |
| 222 | em_set_phy_type(struct em_hw *hw) |
| 223 | { |
| 224 | DEBUGFUNC("em_set_phy_type");; |
| 225 | |
| 226 | if (hw->mac_type == em_undefined) |
| 227 | return -E1000_ERR_PHY_TYPE6; |
| 228 | |
| 229 | switch (hw->phy_id) { |
| 230 | case M88E1000_E_PHY_ID0x01410C50: |
| 231 | case M88E1000_I_PHY_ID0x01410C30: |
| 232 | case M88E1011_I_PHY_ID0x01410C20: |
| 233 | case M88E1111_I_PHY_ID0x01410CC0: |
| 234 | case M88E1112_E_PHY_ID0x01410C90: |
| 235 | case M88E1543_E_PHY_ID0x01410EA0: |
| 236 | case M88E1512_E_PHY_ID0x01410DD0: |
| 237 | case I210_I_PHY_ID0x01410C00: |
| 238 | case I347AT4_E_PHY_ID0x01410DC0: |
| 239 | hw->phy_type = em_phy_m88; |
| 240 | break; |
| 241 | case IGP01E1000_I_PHY_ID0x02A80380: |
| 242 | if (hw->mac_type == em_82541 || |
| 243 | hw->mac_type == em_82541_rev_2 || |
| 244 | hw->mac_type == em_82547 || |
| 245 | hw->mac_type == em_82547_rev_2) { |
| 246 | hw->phy_type = em_phy_igp; |
| 247 | break; |
| 248 | } |
| 249 | case IGP03E1000_E_PHY_ID0x02A80390: |
| 250 | case IGP04E1000_E_PHY_ID0x02A80391: |
| 251 | hw->phy_type = em_phy_igp_3; |
| 252 | break; |
| 253 | case IFE_E_PHY_ID0x02A80330: |
| 254 | case IFE_PLUS_E_PHY_ID0x02A80320: |
| 255 | case IFE_C_E_PHY_ID0x02A80310: |
| 256 | hw->phy_type = em_phy_ife; |
| 257 | break; |
| 258 | case M88E1141_E_PHY_ID0x01410CD0: |
| 259 | hw->phy_type = em_phy_oem; |
| 260 | break; |
| 261 | case I82577_E_PHY_ID0x01540050: |
| 262 | hw->phy_type = em_phy_82577; |
| 263 | break; |
| 264 | case I82578_E_PHY_ID0x004DD040: |
| 265 | hw->phy_type = em_phy_82578; |
| 266 | break; |
| 267 | case I82579_E_PHY_ID0x01540090: |
| 268 | hw->phy_type = em_phy_82579; |
| 269 | break; |
| 270 | case I217_E_PHY_ID0x015400A0: |
| 271 | hw->phy_type = em_phy_i217; |
| 272 | break; |
| 273 | case I82580_I_PHY_ID0x015403A0: |
| 274 | case I350_I_PHY_ID0x015403B0: |
| 275 | hw->phy_type = em_phy_82580; |
| 276 | break; |
| 277 | case RTL8211_E_PHY_ID0x001CC912: |
| 278 | hw->phy_type = em_phy_rtl8211; |
| 279 | break; |
| 280 | case BME1000_E_PHY_ID0x01410CB0: |
| 281 | if (hw->phy_revision == 1) { |
| 282 | hw->phy_type = em_phy_bm; |
| 283 | break; |
| 284 | } |
| 285 | /* FALLTHROUGH */ |
| 286 | case GG82563_E_PHY_ID0x01410CA0: |
| 287 | if (hw->mac_type == em_80003es2lan) { |
| 288 | hw->phy_type = em_phy_gg82563; |
| 289 | break; |
| 290 | } |
| 291 | /* FALLTHROUGH */ |
| 292 | default: |
| 293 | /* Should never have loaded on this device */ |
| 294 | hw->phy_type = em_phy_undefined; |
| 295 | return -E1000_ERR_PHY_TYPE6; |
| 296 | } |
| 297 | |
| 298 | return E1000_SUCCESS0; |
| 299 | } |
| 300 | |
| 301 | /****************************************************************************** |
| 302 | * IGP phy init script - initializes the GbE PHY |
| 303 | * |
| 304 | * hw - Struct containing variables accessed by shared code |
| 305 | *****************************************************************************/ |
| 306 | static void |
| 307 | em_phy_init_script(struct em_hw *hw) |
| 308 | { |
| 309 | uint16_t phy_saved_data; |
| 310 | DEBUGFUNC("em_phy_init_script");; |
| 311 | |
| 312 | if (hw->phy_init_script) { |
| 313 | msec_delay(20)(*delay_func)(1000*(20)); |
| 314 | /* |
| 315 | * Save off the current value of register 0x2F5B to be |
| 316 | * restored at the end of this routine. |
| 317 | */ |
| 318 | em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 319 | |
| 320 | /* Disabled the PHY transmitter */ |
| 321 | em_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 322 | msec_delay(20)(*delay_func)(1000*(20)); |
| 323 | em_write_phy_reg(hw, 0x0000, 0x0140); |
| 324 | msec_delay(5)(*delay_func)(1000*(5)); |
| 325 | |
| 326 | switch (hw->mac_type) { |
| 327 | case em_82541: |
| 328 | case em_82547: |
| 329 | em_write_phy_reg(hw, 0x1F95, 0x0001); |
| 330 | em_write_phy_reg(hw, 0x1F71, 0xBD21); |
| 331 | em_write_phy_reg(hw, 0x1F79, 0x0018); |
| 332 | em_write_phy_reg(hw, 0x1F30, 0x1600); |
| 333 | em_write_phy_reg(hw, 0x1F31, 0x0014); |
| 334 | em_write_phy_reg(hw, 0x1F32, 0x161C); |
| 335 | em_write_phy_reg(hw, 0x1F94, 0x0003); |
| 336 | em_write_phy_reg(hw, 0x1F96, 0x003F); |
| 337 | em_write_phy_reg(hw, 0x2010, 0x0008); |
| 338 | break; |
| 339 | case em_82541_rev_2: |
| 340 | case em_82547_rev_2: |
| 341 | em_write_phy_reg(hw, 0x1F73, 0x0099); |
| 342 | break; |
| 343 | default: |
| 344 | break; |
| 345 | } |
| 346 | |
| 347 | em_write_phy_reg(hw, 0x0000, 0x3300); |
| 348 | msec_delay(20)(*delay_func)(1000*(20)); |
| 349 | |
| 350 | /* Now enable the transmitter */ |
| 351 | em_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 352 | |
| 353 | if (hw->mac_type == em_82547) { |
| 354 | uint16_t fused, fine, coarse; |
| 355 | /* Move to analog registers page */ |
| 356 | em_read_phy_reg(hw, |
| 357 | IGP01E1000_ANALOG_SPARE_FUSE_STATUS0x20D1, &fused); |
| 358 | |
| 359 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED0x0100)) { |
| 360 | em_read_phy_reg(hw, |
| 361 | IGP01E1000_ANALOG_FUSE_STATUS0x20D0, &fused); |
| 362 | |
| 363 | fine = fused & |
| 364 | IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80; |
| 365 | coarse = fused & |
| 366 | IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070; |
| 367 | |
| 368 | if (coarse > |
| 369 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040) { |
| 370 | coarse -= |
| 371 | IGP01E1000_ANALOG_FUSE_COARSE_100x0010; |
| 372 | fine -= |
| 373 | IGP01E1000_ANALOG_FUSE_FINE_10x0080; |
| 374 | } else if (coarse == |
| 375 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040) |
| 376 | fine -= IGP01E1000_ANALOG_FUSE_FINE_100x0500; |
| 377 | |
| 378 | fused = (fused & |
| 379 | IGP01E1000_ANALOG_FUSE_POLY_MASK0xF000) | |
| 380 | (fine & |
| 381 | IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80) | |
| 382 | (coarse & |
| 383 | IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070); |
| 384 | |
| 385 | em_write_phy_reg(hw, |
| 386 | IGP01E1000_ANALOG_FUSE_CONTROL0x20DC, |
| 387 | fused); |
| 388 | |
| 389 | em_write_phy_reg(hw, |
| 390 | IGP01E1000_ANALOG_FUSE_BYPASS0x20DE, |
| 391 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL0x0002); |
| 392 | } |
| 393 | } |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | /****************************************************************************** |
| 398 | * Set the mac type member in the hw struct. |
| 399 | * |
| 400 | * hw - Struct containing variables accessed by shared code |
| 401 | *****************************************************************************/ |
| 402 | int32_t |
| 403 | em_set_mac_type(struct em_hw *hw) |
| 404 | { |
| 405 | DEBUGFUNC("em_set_mac_type");; |
| 406 | |
| 407 | switch (hw->device_id) { |
| 408 | case E1000_DEV_ID_825420x1000: |
| 409 | switch (hw->revision_id) { |
| 410 | case E1000_82542_2_0_REV_ID2: |
| 411 | hw->mac_type = em_82542_rev2_0; |
| 412 | break; |
| 413 | case E1000_82542_2_1_REV_ID3: |
| 414 | hw->mac_type = em_82542_rev2_1; |
| 415 | break; |
| 416 | default: |
| 417 | /* Invalid 82542 revision ID */ |
| 418 | return -E1000_ERR_MAC_TYPE5; |
| 419 | } |
| 420 | break; |
| 421 | case E1000_DEV_ID_82543GC_FIBER0x1001: |
| 422 | case E1000_DEV_ID_82543GC_COPPER0x1004: |
| 423 | hw->mac_type = em_82543; |
| 424 | break; |
| 425 | case E1000_DEV_ID_82544EI_COPPER0x1008: |
| 426 | case E1000_DEV_ID_82544EI_FIBER0x1009: |
| 427 | case E1000_DEV_ID_82544GC_COPPER0x100C: |
| 428 | case E1000_DEV_ID_82544GC_LOM0x100D: |
| 429 | hw->mac_type = em_82544; |
| 430 | break; |
| 431 | case E1000_DEV_ID_82540EM0x100E: |
| 432 | case E1000_DEV_ID_82540EM_LOM0x1015: |
| 433 | case E1000_DEV_ID_82540EP0x1017: |
| 434 | case E1000_DEV_ID_82540EP_LOM0x1016: |
| 435 | case E1000_DEV_ID_82540EP_LP0x101E: |
| 436 | hw->mac_type = em_82540; |
| 437 | break; |
| 438 | case E1000_DEV_ID_82545EM_COPPER0x100F: |
| 439 | case E1000_DEV_ID_82545EM_FIBER0x1011: |
| 440 | hw->mac_type = em_82545; |
| 441 | break; |
| 442 | case E1000_DEV_ID_82545GM_COPPER0x1026: |
| 443 | case E1000_DEV_ID_82545GM_FIBER0x1027: |
| 444 | case E1000_DEV_ID_82545GM_SERDES0x1028: |
| 445 | hw->mac_type = em_82545_rev_3; |
| 446 | break; |
| 447 | case E1000_DEV_ID_82546EB_COPPER0x1010: |
| 448 | case E1000_DEV_ID_82546EB_FIBER0x1012: |
| 449 | case E1000_DEV_ID_82546EB_QUAD_COPPER0x101D: |
| 450 | hw->mac_type = em_82546; |
| 451 | break; |
| 452 | case E1000_DEV_ID_82546GB_COPPER0x1079: |
| 453 | case E1000_DEV_ID_82546GB_FIBER0x107A: |
| 454 | case E1000_DEV_ID_82546GB_SERDES0x107B: |
| 455 | case E1000_DEV_ID_82546GB_PCIE0x108A: |
| 456 | case E1000_DEV_ID_82546GB_QUAD_COPPER0x1099: |
| 457 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5: |
| 458 | case E1000_DEV_ID_82546GB_20x109B: |
| 459 | hw->mac_type = em_82546_rev_3; |
| 460 | break; |
| 461 | case E1000_DEV_ID_82541EI0x1013: |
| 462 | case E1000_DEV_ID_82541EI_MOBILE0x1018: |
| 463 | case E1000_DEV_ID_82541ER_LOM0x1014: |
| 464 | hw->mac_type = em_82541; |
| 465 | break; |
| 466 | case E1000_DEV_ID_82541ER0x1078: |
| 467 | case E1000_DEV_ID_82541GI0x1076: |
| 468 | case E1000_DEV_ID_82541GI_LF0x107C: |
| 469 | case E1000_DEV_ID_82541GI_MOBILE0x1077: |
| 470 | hw->mac_type = em_82541_rev_2; |
| 471 | break; |
| 472 | case E1000_DEV_ID_82547EI0x1019: |
| 473 | case E1000_DEV_ID_82547EI_MOBILE0x101A: |
| 474 | hw->mac_type = em_82547; |
| 475 | break; |
| 476 | case E1000_DEV_ID_82547GI0x1075: |
| 477 | hw->mac_type = em_82547_rev_2; |
| 478 | break; |
| 479 | case E1000_DEV_ID_82571EB_AF0x10A1: |
| 480 | case E1000_DEV_ID_82571EB_AT0x10A0: |
| 481 | case E1000_DEV_ID_82571EB_COPPER0x105E: |
| 482 | case E1000_DEV_ID_82571EB_FIBER0x105F: |
| 483 | case E1000_DEV_ID_82571EB_SERDES0x1060: |
| 484 | case E1000_DEV_ID_82571EB_QUAD_COPPER0x10A4: |
| 485 | case E1000_DEV_ID_82571EB_QUAD_FIBER0x10A5: |
| 486 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP0x10BC: |
| 487 | case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9: |
| 488 | case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA: |
| 489 | case E1000_DEV_ID_82571PT_QUAD_COPPER0x10D5: |
| 490 | hw->mac_type = em_82571; |
| 491 | break; |
| 492 | case E1000_DEV_ID_82572EI_COPPER0x107D: |
| 493 | case E1000_DEV_ID_82572EI_FIBER0x107E: |
| 494 | case E1000_DEV_ID_82572EI_SERDES0x107F: |
| 495 | case E1000_DEV_ID_82572EI0x10B9: |
| 496 | hw->mac_type = em_82572; |
| 497 | break; |
| 498 | case E1000_DEV_ID_82573E0x108B: |
| 499 | case E1000_DEV_ID_82573E_IAMT0x108C: |
| 500 | case E1000_DEV_ID_82573E_PM0x10B3: |
| 501 | case E1000_DEV_ID_82573L0x109A: |
| 502 | case E1000_DEV_ID_82573L_PL_10x10B0: |
| 503 | case E1000_DEV_ID_82573L_PL_20x10B4: |
| 504 | case E1000_DEV_ID_82573V_PM0x10B2: |
| 505 | hw->mac_type = em_82573; |
| 506 | break; |
| 507 | case E1000_DEV_ID_82574L0x10D3: |
| 508 | case E1000_DEV_ID_82574LA0x10F6: |
| 509 | case E1000_DEV_ID_82583V0x150C: |
| 510 | hw->mac_type = em_82574; |
| 511 | break; |
| 512 | case E1000_DEV_ID_82575EB_PT0x10A7: |
| 513 | case E1000_DEV_ID_82575EB_PF0x10A9: |
| 514 | case E1000_DEV_ID_82575GB_QP0x10D6: |
| 515 | case E1000_DEV_ID_82575GB_QP_PM0x10E2: |
| 516 | hw->mac_type = em_82575; |
| 517 | hw->initialize_hw_bits_disable = 1; |
| 518 | break; |
| 519 | case E1000_DEV_ID_825760x10C9: |
| 520 | case E1000_DEV_ID_82576_FIBER0x10E6: |
| 521 | case E1000_DEV_ID_82576_SERDES0x10E7: |
| 522 | case E1000_DEV_ID_82576_QUAD_COPPER0x10E8: |
| 523 | case E1000_DEV_ID_82576_QUAD_CU_ET20x1526: |
| 524 | case E1000_DEV_ID_82576_NS0x150A: |
| 525 | case E1000_DEV_ID_82576_NS_SERDES0x1518: |
| 526 | case E1000_DEV_ID_82576_SERDES_QUAD0x150D: |
| 527 | hw->mac_type = em_82576; |
| 528 | hw->initialize_hw_bits_disable = 1; |
| 529 | break; |
| 530 | case E1000_DEV_ID_82580_COPPER0x150E: |
| 531 | case E1000_DEV_ID_82580_FIBER0x150F: |
| 532 | case E1000_DEV_ID_82580_QUAD_FIBER0x1527: |
| 533 | case E1000_DEV_ID_82580_SERDES0x1510: |
| 534 | case E1000_DEV_ID_82580_SGMII0x1511: |
| 535 | case E1000_DEV_ID_82580_COPPER_DUAL0x1516: |
| 536 | case E1000_DEV_ID_DH89XXCC_SGMII0x0438: |
| 537 | case E1000_DEV_ID_DH89XXCC_SERDES0x043A: |
| 538 | case E1000_DEV_ID_DH89XXCC_BACKPLANE0x043C: |
| 539 | case E1000_DEV_ID_DH89XXCC_SFP0x0440: |
| 540 | hw->mac_type = em_82580; |
| 541 | hw->initialize_hw_bits_disable = 1; |
| 542 | break; |
| 543 | case E1000_DEV_ID_I210_COPPER0x1533: |
| 544 | case E1000_DEV_ID_I210_COPPER_OEM10x1534: |
| 545 | case E1000_DEV_ID_I210_COPPER_IT0x1535: |
| 546 | case E1000_DEV_ID_I210_FIBER0x1536: |
| 547 | case E1000_DEV_ID_I210_SERDES0x1537: |
| 548 | case E1000_DEV_ID_I210_SGMII0x1538: |
| 549 | case E1000_DEV_ID_I210_COPPER_FLASHLESS0x157B: |
| 550 | case E1000_DEV_ID_I210_SERDES_FLASHLESS0x157C: |
| 551 | case E1000_DEV_ID_I211_COPPER0x1539: |
| 552 | hw->mac_type = em_i210; |
| 553 | hw->initialize_hw_bits_disable = 1; |
| 554 | hw->eee_enable = 1; |
| 555 | break; |
| 556 | case E1000_DEV_ID_I350_COPPER0x1521: |
| 557 | case E1000_DEV_ID_I350_FIBER0x1522: |
| 558 | case E1000_DEV_ID_I350_SERDES0x1523: |
| 559 | case E1000_DEV_ID_I350_SGMII0x1524: |
| 560 | case E1000_DEV_ID_I350_DA40x1546: |
| 561 | case E1000_DEV_ID_I354_BACKPLANE_1GBPS0x1F40: |
| 562 | case E1000_DEV_ID_I354_SGMII0x1F41: |
| 563 | case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS0x1F45: |
| 564 | hw->mac_type = em_i350; |
| 565 | hw->initialize_hw_bits_disable = 1; |
| 566 | hw->eee_enable = 1; |
| 567 | break; |
| 568 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT0x10BA: |
| 569 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT0x10BB: |
| 570 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT0x1096: |
| 571 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098: |
| 572 | hw->mac_type = em_80003es2lan; |
| 573 | break; |
| 574 | case E1000_DEV_ID_ICH8_IFE0x104C: |
| 575 | case E1000_DEV_ID_ICH8_IFE_G0x10C5: |
| 576 | case E1000_DEV_ID_ICH8_IFE_GT0x10C4: |
| 577 | case E1000_DEV_ID_ICH8_IGP_AMT0x104A: |
| 578 | case E1000_DEV_ID_ICH8_IGP_C0x104B: |
| 579 | case E1000_DEV_ID_ICH8_IGP_M0x104D: |
| 580 | case E1000_DEV_ID_ICH8_IGP_M_AMT0x1049: |
| 581 | case E1000_DEV_ID_ICH8_82567V_30x1501: |
| 582 | hw->mac_type = em_ich8lan; |
| 583 | break; |
| 584 | case E1000_DEV_ID_ICH9_BM0x10E5: |
| 585 | case E1000_DEV_ID_ICH9_IFE0x10C0: |
| 586 | case E1000_DEV_ID_ICH9_IFE_G0x10C2: |
| 587 | case E1000_DEV_ID_ICH9_IFE_GT0x10C3: |
| 588 | case E1000_DEV_ID_ICH9_IGP_AMT0x10BD: |
| 589 | case E1000_DEV_ID_ICH9_IGP_C0x294C: |
| 590 | case E1000_DEV_ID_ICH9_IGP_M0x10BF: |
| 591 | case E1000_DEV_ID_ICH9_IGP_M_AMT0x10F5: |
| 592 | case E1000_DEV_ID_ICH9_IGP_M_V0x10CB: |
| 593 | case E1000_DEV_ID_ICH10_R_BM_LF0x10CD: |
| 594 | case E1000_DEV_ID_ICH10_R_BM_LM0x10CC: |
| 595 | case E1000_DEV_ID_ICH10_R_BM_V0x10CE: |
| 596 | hw->mac_type = em_ich9lan; |
| 597 | break; |
| 598 | case E1000_DEV_ID_ICH10_D_BM_LF0x10DF: |
| 599 | case E1000_DEV_ID_ICH10_D_BM_LM0x10DE: |
| 600 | case E1000_DEV_ID_ICH10_D_BM_V0x1525: |
| 601 | hw->mac_type = em_ich10lan; |
| 602 | break; |
| 603 | case E1000_DEV_ID_PCH_M_HV_LC0x10EB: |
| 604 | case E1000_DEV_ID_PCH_M_HV_LM0x10EA: |
| 605 | case E1000_DEV_ID_PCH_D_HV_DC0x10F0: |
| 606 | case E1000_DEV_ID_PCH_D_HV_DM0x10EF: |
| 607 | hw->mac_type = em_pchlan; |
| 608 | hw->eee_enable = 1; |
| 609 | break; |
| 610 | case E1000_DEV_ID_PCH2_LV_LM0x1502: |
| 611 | case E1000_DEV_ID_PCH2_LV_V0x1503: |
| 612 | hw->mac_type = em_pch2lan; |
| 613 | break; |
| 614 | case E1000_DEV_ID_PCH_LPT_I217_LM0x153A: |
| 615 | case E1000_DEV_ID_PCH_LPT_I217_V0x153B: |
| 616 | case E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A: |
| 617 | case E1000_DEV_ID_PCH_LPTLP_I218_V0x1559: |
| 618 | case E1000_DEV_ID_PCH_I218_LM20x15A0: |
| 619 | case E1000_DEV_ID_PCH_I218_V20x15A1: |
| 620 | case E1000_DEV_ID_PCH_I218_LM30x15A2: |
| 621 | case E1000_DEV_ID_PCH_I218_V30x15A3: |
| 622 | hw->mac_type = em_pch_lpt; |
| 623 | break; |
| 624 | case E1000_DEV_ID_PCH_SPT_I219_LM0x156F: |
| 625 | case E1000_DEV_ID_PCH_SPT_I219_V0x1570: |
| 626 | case E1000_DEV_ID_PCH_SPT_I219_LM20x15B7: |
| 627 | case E1000_DEV_ID_PCH_SPT_I219_V20x15B8: |
| 628 | case E1000_DEV_ID_PCH_LBG_I219_LM30x15B9: |
| 629 | case E1000_DEV_ID_PCH_SPT_I219_LM40x15D7: |
| 630 | case E1000_DEV_ID_PCH_SPT_I219_V40x15D8: |
| 631 | case E1000_DEV_ID_PCH_SPT_I219_LM50x15E3: |
| 632 | case E1000_DEV_ID_PCH_SPT_I219_V50x15D6: |
| 633 | case E1000_DEV_ID_PCH_CMP_I219_LM120x0D53: |
| 634 | case E1000_DEV_ID_PCH_CMP_I219_V120x0D55: |
| 635 | hw->mac_type = em_pch_spt; |
| 636 | break; |
| 637 | case E1000_DEV_ID_PCH_CNP_I219_LM60x15BD: |
| 638 | case E1000_DEV_ID_PCH_CNP_I219_V60x15BE: |
| 639 | case E1000_DEV_ID_PCH_CNP_I219_LM70x15BB: |
| 640 | case E1000_DEV_ID_PCH_CNP_I219_V70x15BC: |
| 641 | case E1000_DEV_ID_PCH_ICP_I219_LM80x15DF: |
| 642 | case E1000_DEV_ID_PCH_ICP_I219_V80x15E0: |
| 643 | case E1000_DEV_ID_PCH_ICP_I219_LM90x15E1: |
| 644 | case E1000_DEV_ID_PCH_ICP_I219_V90x15E2: |
| 645 | case E1000_DEV_ID_PCH_CMP_I219_LM100x0D4E: |
| 646 | case E1000_DEV_ID_PCH_CMP_I219_V100x0D4F: |
| 647 | case E1000_DEV_ID_PCH_CMP_I219_LM110x0D4C: |
| 648 | case E1000_DEV_ID_PCH_CMP_I219_V110x0D4D: |
| 649 | hw->mac_type = em_pch_cnp; |
| 650 | break; |
| 651 | case E1000_DEV_ID_PCH_TGP_I219_LM130x15FB: |
| 652 | case E1000_DEV_ID_PCH_TGP_I219_V130x15FC: |
| 653 | case E1000_DEV_ID_PCH_TGP_I219_LM140x15F9: |
| 654 | case E1000_DEV_ID_PCH_TGP_I219_V140x15FA: |
| 655 | case E1000_DEV_ID_PCH_TGP_I219_LM150x15F4: |
| 656 | case E1000_DEV_ID_PCH_TGP_I219_V150x15F5: |
| 657 | hw->mac_type = em_pch_tgp; |
| 658 | break; |
| 659 | case E1000_DEV_ID_PCH_ADP_I219_LM160x1A1E: |
| 660 | case E1000_DEV_ID_PCH_ADP_I219_V160x1A1F: |
| 661 | case E1000_DEV_ID_PCH_ADP_I219_LM170x1A1C: |
| 662 | case E1000_DEV_ID_PCH_ADP_I219_V170x1A1D: |
| 663 | case E1000_DEV_ID_PCH_RPL_I219_LM220x0DC7: |
| 664 | case E1000_DEV_ID_PCH_RPL_I219_V220x0DC8: |
| 665 | case E1000_DEV_ID_PCH_RPL_I219_LM230x0DC5: |
| 666 | case E1000_DEV_ID_PCH_RPL_I219_V230x0DC6: |
| 667 | hw->mac_type = em_pch_adp; |
| 668 | break; |
| 669 | case E1000_DEV_ID_PCH_MTP_I219_LM180x550A: |
| 670 | case E1000_DEV_ID_PCH_MTP_I219_V180x550B: |
| 671 | case E1000_DEV_ID_PCH_MTP_I219_LM190x550C: |
| 672 | case E1000_DEV_ID_PCH_MTP_I219_V190x550D: |
| 673 | case E1000_DEV_ID_PCH_LNP_I219_LM200x550E: |
| 674 | case E1000_DEV_ID_PCH_LNP_I219_V200x550F: |
| 675 | case E1000_DEV_ID_PCH_LNP_I219_LM210x5510: |
| 676 | case E1000_DEV_ID_PCH_LNP_I219_V210x5511: |
| 677 | case E1000_DEV_ID_PCH_ARL_I219_LM240x57A0: |
| 678 | case E1000_DEV_ID_PCH_ARL_I219_V240x57A1: |
| 679 | hw->mac_type = em_pch_adp; /* pch_mtp */ |
| 680 | break; |
| 681 | case E1000_DEV_ID_EP80579_LAN_10x5040: |
| 682 | hw->mac_type = em_icp_xxxx; |
| 683 | hw->icp_xxxx_port_num = 0; |
| 684 | break; |
| 685 | case E1000_DEV_ID_EP80579_LAN_20x5044: |
| 686 | case E1000_DEV_ID_EP80579_LAN_40x5041: |
| 687 | hw->mac_type = em_icp_xxxx; |
| 688 | hw->icp_xxxx_port_num = 1; |
| 689 | break; |
| 690 | case E1000_DEV_ID_EP80579_LAN_30x5048: |
| 691 | case E1000_DEV_ID_EP80579_LAN_50x5045: |
| 692 | hw->mac_type = em_icp_xxxx; |
| 693 | hw->icp_xxxx_port_num = 2; |
| 694 | break; |
| 695 | case E1000_DEV_ID_EP80579_LAN_60x5049: |
| 696 | hw->mac_type = em_icp_xxxx; |
| 697 | hw->icp_xxxx_port_num = 3; |
| 698 | break; |
| 699 | default: |
| 700 | /* Should never have loaded on this device */ |
| 701 | return -E1000_ERR_MAC_TYPE5; |
| 702 | } |
| 703 | |
| 704 | switch (hw->mac_type) { |
| 705 | case em_ich8lan: |
| 706 | case em_ich9lan: |
| 707 | case em_ich10lan: |
| 708 | case em_pchlan: |
| 709 | case em_pch2lan: |
| 710 | case em_pch_lpt: |
| 711 | case em_pch_spt: |
| 712 | case em_pch_cnp: |
| 713 | case em_pch_tgp: |
| 714 | case em_pch_adp: |
| 715 | hw->swfwhw_semaphore_present = TRUE1; |
| 716 | hw->asf_firmware_present = TRUE1; |
| 717 | break; |
| 718 | case em_80003es2lan: |
| 719 | case em_82575: |
| 720 | case em_82576: |
| 721 | case em_82580: |
| 722 | case em_i210: |
| 723 | case em_i350: |
| 724 | hw->swfw_sync_present = TRUE1; |
| 725 | /* FALLTHROUGH */ |
| 726 | case em_82571: |
| 727 | case em_82572: |
| 728 | case em_82573: |
| 729 | case em_82574: |
| 730 | hw->eeprom_semaphore_present = TRUE1; |
| 731 | /* FALLTHROUGH */ |
| 732 | case em_82541: |
| 733 | case em_82547: |
| 734 | case em_82541_rev_2: |
| 735 | case em_82547_rev_2: |
| 736 | hw->asf_firmware_present = TRUE1; |
| 737 | break; |
| 738 | default: |
| 739 | break; |
| 740 | } |
| 741 | |
| 742 | return E1000_SUCCESS0; |
| 743 | } |
| 744 | |
| 745 | /** |
| 746 | * em_set_sfp_media_type_82575 - derives SFP module media type. |
| 747 | * @hw: pointer to the HW structure |
| 748 | * |
| 749 | * The media type is chosen based on SFP module. |
| 750 | * compatibility flags retrieved from SFP ID EEPROM. |
| 751 | **/ |
| 752 | STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw) |
| 753 | { |
| 754 | struct sfp_e1000_flags eth_flags; |
| 755 | int32_t ret_val = E1000_ERR_CONFIG3; |
| 756 | uint32_t ctrl_ext = 0; |
| 757 | uint8_t transceiver_type = 0; |
| 758 | int32_t timeout = 3; |
| 759 | |
| 760 | /* Turn I2C interface ON and power on sfp cage */ |
| 761 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 762 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080; |
| 763 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext | 0x02000000))); |
| 764 | |
| 765 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 766 | |
| 767 | /* Read SFP module data */ |
| 768 | while (timeout) { |
| 769 | ret_val = em_read_sfp_data_byte(hw, |
| 770 | E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET)(0x0000 + (0x00)), |
| 771 | &transceiver_type); |
| 772 | if (ret_val == E1000_SUCCESS0) |
| 773 | break; |
| 774 | msec_delay(100)(*delay_func)(1000*(100)); |
| 775 | timeout--; |
| 776 | } |
| 777 | if (ret_val != E1000_SUCCESS0) |
| 778 | goto out; |
| 779 | |
| 780 | ret_val = em_read_sfp_data_byte(hw, |
| 781 | E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET)(0x0000 + (0x06)), |
| 782 | (uint8_t *)ð_flags); |
| 783 | if (ret_val != E1000_SUCCESS0) |
| 784 | goto out; |
| 785 | |
| 786 | /* Check if there is some SFP module plugged and powered */ |
| 787 | if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP0x03) || |
| 788 | (transceiver_type == E1000_SFF_IDENTIFIER_SFF0x02)) { |
| 789 | if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { |
| 790 | hw->media_type = em_media_type_internal_serdes; |
| 791 | } else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) { |
| 792 | hw->media_type = em_media_type_internal_serdes; |
| 793 | hw->sgmii_active = TRUE1; |
| 794 | } else if (eth_flags.e1000_base_t) { |
| 795 | hw->media_type = em_media_type_copper; |
| 796 | hw->sgmii_active = TRUE1; |
| 797 | } else { |
| 798 | DEBUGOUT("PHY module has not been recognized\n"); |
| 799 | ret_val = E1000_ERR_CONFIG3; |
| 800 | goto out; |
| 801 | } |
| 802 | } else { |
| 803 | ret_val = E1000_ERR_CONFIG3; |
| 804 | goto out; |
| 805 | } |
| 806 | ret_val = E1000_SUCCESS0; |
| 807 | out: |
| 808 | /* Restore I2C interface setting */ |
| 809 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 810 | return ret_val; |
| 811 | } |
| 812 | |
| 813 | |
| 814 | /***************************************************************************** |
| 815 | * Set media type and TBI compatibility. |
| 816 | * |
| 817 | * hw - Struct containing variables accessed by shared code |
| 818 | * **************************************************************************/ |
| 819 | void |
| 820 | em_set_media_type(struct em_hw *hw) |
| 821 | { |
| 822 | uint32_t status, ctrl_ext, mdic; |
| 823 | DEBUGFUNC("em_set_media_type");; |
| 824 | |
| 825 | if (hw->mac_type != em_82543) { |
| 826 | /* tbi_compatibility is only valid on 82543 */ |
| 827 | hw->tbi_compatibility_en = FALSE0; |
| 828 | } |
| 829 | |
| 830 | if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || |
| 831 | hw->mac_type == em_82576 || |
| 832 | hw->mac_type == em_i210 || hw->mac_type == em_i350) { |
| 833 | hw->media_type = em_media_type_copper; |
| 834 | hw->sgmii_active = FALSE0; |
| 835 | |
| 836 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 837 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) { |
| 838 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000: |
| 839 | hw->media_type = em_media_type_internal_serdes; |
| 840 | ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000; |
| 841 | break; |
| 842 | case E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000: |
| 843 | mdic = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00E04))); |
| 844 | ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000; |
| 845 | if (mdic & E1000_MDICNFG_EXT_MDIO0x80000000) { |
| 846 | hw->media_type = em_media_type_copper; |
| 847 | hw->sgmii_active = TRUE1; |
| 848 | break; |
| 849 | } |
| 850 | /* FALLTHROUGH */ |
| 851 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000: |
| 852 | ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000; |
| 853 | if (em_set_sfp_media_type_82575(hw) != 0) { |
| 854 | hw->media_type = em_media_type_internal_serdes; |
| 855 | if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) == |
| 856 | E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000) { |
| 857 | hw->media_type = em_media_type_copper; |
| 858 | hw->sgmii_active = TRUE1; |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000; |
| 863 | if (hw->sgmii_active) |
| 864 | ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000; |
| 865 | else |
| 866 | ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000; |
| 867 | break; |
| 868 | default: |
| 869 | ctrl_ext &= ~E1000_CTRL_I2C_ENA0x02000000; |
| 870 | break; |
| 871 | } |
| 872 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 873 | return; |
| 874 | } |
| 875 | |
| 876 | switch (hw->device_id) { |
| 877 | case E1000_DEV_ID_82545GM_SERDES0x1028: |
| 878 | case E1000_DEV_ID_82546GB_SERDES0x107B: |
| 879 | case E1000_DEV_ID_82571EB_SERDES0x1060: |
| 880 | case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9: |
| 881 | case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA: |
| 882 | case E1000_DEV_ID_82572EI_SERDES0x107F: |
| 883 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098: |
| 884 | hw->media_type = em_media_type_internal_serdes; |
| 885 | break; |
| 886 | case E1000_DEV_ID_EP80579_LAN_10x5040: |
| 887 | case E1000_DEV_ID_EP80579_LAN_20x5044: |
| 888 | case E1000_DEV_ID_EP80579_LAN_30x5048: |
| 889 | case E1000_DEV_ID_EP80579_LAN_40x5041: |
| 890 | case E1000_DEV_ID_EP80579_LAN_50x5045: |
| 891 | case E1000_DEV_ID_EP80579_LAN_60x5049: |
| 892 | hw->media_type = em_media_type_copper; |
| 893 | break; |
| 894 | default: |
| 895 | switch (hw->mac_type) { |
| 896 | case em_82542_rev2_0: |
| 897 | case em_82542_rev2_1: |
| 898 | hw->media_type = em_media_type_fiber; |
| 899 | break; |
| 900 | case em_ich8lan: |
| 901 | case em_ich9lan: |
| 902 | case em_ich10lan: |
| 903 | case em_pchlan: |
| 904 | case em_pch2lan: |
| 905 | case em_pch_lpt: |
| 906 | case em_pch_spt: |
| 907 | case em_pch_cnp: |
| 908 | case em_pch_tgp: |
| 909 | case em_pch_adp: |
| 910 | case em_82573: |
| 911 | case em_82574: |
| 912 | /* |
| 913 | * The STATUS_TBIMODE bit is reserved or reused for |
| 914 | * the this device. |
| 915 | */ |
| 916 | hw->media_type = em_media_type_copper; |
| 917 | break; |
| 918 | default: |
| 919 | status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 920 | if (status & E1000_STATUS_TBIMODE0x00000020) { |
| 921 | hw->media_type = em_media_type_fiber; |
| 922 | /* tbi_compatibility not valid on fiber */ |
| 923 | hw->tbi_compatibility_en = FALSE0; |
| 924 | } else { |
| 925 | hw->media_type = em_media_type_copper; |
| 926 | } |
| 927 | break; |
| 928 | } |
| 929 | } |
| 930 | } |
| 931 | /****************************************************************************** |
| 932 | * Reset the transmit and receive units; mask and clear all interrupts. |
| 933 | * |
| 934 | * hw - Struct containing variables accessed by shared code |
| 935 | *****************************************************************************/ |
| 936 | int32_t |
| 937 | em_reset_hw(struct em_hw *hw) |
| 938 | { |
| 939 | uint32_t ctrl; |
| 940 | uint32_t ctrl_ext; |
| 941 | uint32_t icr; |
| 942 | uint32_t manc; |
| 943 | uint32_t led_ctrl; |
| 944 | uint32_t timeout; |
| 945 | uint32_t extcnf_ctrl; |
| 946 | int32_t ret_val; |
| 947 | DEBUGFUNC("em_reset_hw");; |
| 948 | |
| 949 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
| 950 | if (hw->mac_type == em_82542_rev2_0) { |
| 951 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 952 | em_pci_clear_mwi(hw); |
| 953 | } |
| 954 | if (hw->bus_type == em_bus_type_pci_express) { |
| 955 | /* |
| 956 | * Prevent the PCI-E bus from sticking if there is no TLP |
| 957 | * connection on the last TLP read/write transaction when MAC |
| 958 | * is reset. |
| 959 | */ |
| 960 | if (em_disable_pciex_master(hw) != E1000_SUCCESS0) { |
| 961 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | /* Set the completion timeout for 82575 chips */ |
| 966 | if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || |
| 967 | hw->mac_type == em_82576 || |
| 968 | hw->mac_type == em_i210 || hw->mac_type == em_i350) { |
| 969 | ret_val = em_set_pciex_completion_timeout(hw); |
| 970 | if (ret_val) { |
| 971 | DEBUGOUT("PCI-E Set completion timeout has failed.\n"); |
| 972 | } |
| 973 | } |
| 974 | |
| 975 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 976 | DEBUGOUT("Masking off all interrupts\n"); |
| 977 | E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register (0x000D8))), (0xffffffff))); |
| 978 | /* |
| 979 | * Disable the Transmit and Receive units. Then delay to allow any |
| 980 | * pending transactions to complete before we hit the MAC with the |
| 981 | * global reset. |
| 982 | */ |
| 983 | E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))), (0))); |
| 984 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))), (0x00000008))); |
| 985 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 986 | /* |
| 987 | * The tbi_compatibility_on Flag must be cleared when Rctl is |
| 988 | * cleared. |
| 989 | */ |
| 990 | hw->tbi_compatibility_on = FALSE0; |
| 991 | /* |
| 992 | * Delay to allow any outstanding PCI transactions to complete before |
| 993 | * resetting the device |
| 994 | */ |
| 995 | msec_delay(10)(*delay_func)(1000*(10)); |
| 996 | |
| 997 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 998 | |
| 999 | /* Must reset the PHY before resetting the MAC */ |
| 1000 | if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
| 1001 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((ctrl | 0x80000000)))); |
| 1002 | msec_delay(5)(*delay_func)(1000*(5)); |
| 1003 | } |
| 1004 | /* |
| 1005 | * Must acquire the MDIO ownership before MAC reset. Ownership |
| 1006 | * defaults to firmware after a reset. |
| 1007 | */ |
| 1008 | if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { |
| 1009 | timeout = 10; |
| 1010 | |
| 1011 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register (0x00F00))))); |
| 1012 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020; |
| 1013 | |
| 1014 | do { |
| 1015 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register (0x00F00))), (extcnf_ctrl))); |
| 1016 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register (0x00F00))))); |
| 1017 | |
| 1018 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020) |
| 1019 | break; |
| 1020 | else |
| 1021 | extcnf_ctrl |= |
| 1022 | E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020; |
| 1023 | |
| 1024 | msec_delay(2)(*delay_func)(1000*(2)); |
| 1025 | timeout--; |
| 1026 | } while (timeout); |
| 1027 | } |
| 1028 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
| 1029 | if (hw->mac_type == em_ich8lan) { |
| 1030 | /* Set Tx and Rx buffer allocation to 8k apiece. */ |
| 1031 | E1000_WRITE_REG(hw, PBA, E1000_PBA_8K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x01000 : em_translate_82542_register (0x01000))), (0x0008))); |
| 1032 | /* Set Packet Buffer Size to 16k. */ |
| 1033 | E1000_WRITE_REG(hw, PBS, E1000_PBS_16K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x01008 : em_translate_82542_register (0x01008))), (0x0010))); |
| 1034 | } |
| 1035 | /* |
| 1036 | * Issue a global reset to the MAC. This will reset the chip's |
| 1037 | * transmit, receive, DMA, and link units. It will not effect the |
| 1038 | * current PCI configuration. The global reset bit is self- |
| 1039 | * clearing, and should clear within a microsecond. |
| 1040 | */ |
| 1041 | DEBUGOUT("Issuing a global reset to MAC\n"); |
| 1042 | |
| 1043 | switch (hw->mac_type) { |
| 1044 | case em_82544: |
| 1045 | case em_82540: |
| 1046 | case em_82545: |
| 1047 | case em_82546: |
| 1048 | case em_82541: |
| 1049 | case em_82541_rev_2: |
| 1050 | /* |
| 1051 | * These controllers can't ack the 64-bit write when issuing |
| 1052 | * the reset, so use IO-mapping as a workaround to issue the |
| 1053 | * reset |
| 1054 | */ |
| 1055 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST))em_write_reg_io((hw), 0x00000, (ctrl | 0x04000000)); |
| 1056 | break; |
| 1057 | case em_82545_rev_3: |
| 1058 | case em_82546_rev_3: |
| 1059 | /* Reset is performed on a shadow of the control register */ |
| 1060 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00004 : em_translate_82542_register (0x00004))), ((ctrl | 0x04000000)))); |
| 1061 | break; |
| 1062 | case em_ich8lan: |
| 1063 | case em_ich9lan: |
| 1064 | case em_ich10lan: |
| 1065 | case em_pchlan: |
| 1066 | case em_pch2lan: |
| 1067 | case em_pch_lpt: |
| 1068 | case em_pch_spt: |
| 1069 | case em_pch_cnp: |
| 1070 | case em_pch_tgp: |
| 1071 | case em_pch_adp: |
| 1072 | if (!hw->phy_reset_disable && |
| 1073 | em_check_phy_reset_block(hw) == E1000_SUCCESS0) { |
| 1074 | /* |
| 1075 | * PHY HW reset requires MAC CORE reset at the same |
| 1076 | * time to make sure the interface between MAC and |
| 1077 | * the external PHY is reset. |
| 1078 | */ |
| 1079 | ctrl |= E1000_CTRL_PHY_RST0x80000000; |
| 1080 | /* |
| 1081 | * Gate automatic PHY configuration by hardware on |
| 1082 | * non-managed 82579 |
| 1083 | */ |
| 1084 | if ((hw->mac_type == em_pch2lan) && |
| 1085 | !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register (0x05B54))))) & E1000_FWSM_FW_VALID0x00008000)) { |
| 1086 | em_gate_hw_phy_config_ich8lan(hw, TRUE1); |
| 1087 | } |
| 1088 | } |
| 1089 | em_get_software_flag(hw); |
| 1090 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((ctrl | 0x04000000)))); |
| 1091 | /* HW reset releases software_flag */ |
| 1092 | hw->sw_flag = 0; |
| 1093 | msec_delay(20)(*delay_func)(1000*(20)); |
| 1094 | |
| 1095 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 1096 | if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && |
| 1097 | !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register (0x05B54))))) & E1000_FWSM_FW_VALID0x00008000)) { |
| 1098 | msec_delay(10)(*delay_func)(1000*(10)); |
| 1099 | em_gate_hw_phy_config_ich8lan(hw, FALSE0); |
| 1100 | } |
| 1101 | break; |
| 1102 | default: |
| 1103 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((ctrl | 0x04000000)))); |
| 1104 | break; |
| 1105 | } |
| 1106 | |
| 1107 | if (em_check_phy_reset_block(hw) == E1000_SUCCESS0) { |
| 1108 | if (hw->mac_type == em_pchlan) { |
| 1109 | ret_val = em_hv_phy_workarounds_ich8lan(hw); |
| 1110 | if (ret_val) |
| 1111 | return ret_val; |
| 1112 | } |
| 1113 | else if (hw->mac_type == em_pch2lan) { |
| 1114 | ret_val = em_lv_phy_workarounds_ich8lan(hw); |
| 1115 | if (ret_val) |
| 1116 | return ret_val; |
| 1117 | } |
| 1118 | } |
| 1119 | |
| 1120 | /* |
| 1121 | * After MAC reset, force reload of EEPROM to restore power-on |
| 1122 | * settings to device. Later controllers reload the EEPROM |
| 1123 | * automatically, so just wait for reload to complete. |
| 1124 | */ |
| 1125 | switch (hw->mac_type) { |
| 1126 | case em_82542_rev2_0: |
| 1127 | case em_82542_rev2_1: |
| 1128 | case em_82543: |
| 1129 | case em_82544: |
| 1130 | /* Wait for reset to complete */ |
| 1131 | usec_delay(10)(*delay_func)(10); |
| 1132 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1133 | ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000; |
| 1134 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 1135 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1136 | /* Wait for EEPROM reload */ |
| 1137 | msec_delay(2)(*delay_func)(1000*(2)); |
| 1138 | break; |
| 1139 | case em_82541: |
| 1140 | case em_82541_rev_2: |
| 1141 | case em_82547: |
| 1142 | case em_82547_rev_2: |
| 1143 | /* Wait for EEPROM reload */ |
| 1144 | msec_delay(20)(*delay_func)(1000*(20)); |
| 1145 | break; |
| 1146 | case em_82573: |
| 1147 | case em_82574: |
| 1148 | if (em_is_onboard_nvm_eeprom(hw) == FALSE0) { |
| 1149 | usec_delay(10)(*delay_func)(10); |
| 1150 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1151 | ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000; |
| 1152 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 1153 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1154 | } |
| 1155 | /* FALLTHROUGH */ |
| 1156 | |
| 1157 | /* Auto read done will delay 5ms or poll based on mac type */ |
| 1158 | ret_val = em_get_auto_rd_done(hw); |
| 1159 | if (ret_val) |
| 1160 | return ret_val; |
| 1161 | break; |
| 1162 | default: |
| 1163 | /* Wait for EEPROM reload (it happens automatically) */ |
| 1164 | msec_delay(5)(*delay_func)(1000*(5)); |
| 1165 | break; |
| 1166 | } |
| 1167 | |
| 1168 | /* Disable HW ARPs on ASF enabled adapters */ |
| 1169 | if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && |
| 1170 | hw->mac_type != em_icp_xxxx) { |
| 1171 | manc = E1000_READ_REG(hw, MANC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register (0x05820))))); |
| 1172 | manc &= ~(E1000_MANC_ARP_EN0x00002000); |
| 1173 | E1000_WRITE_REG(hw, MANC, manc)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register (0x05820))), (manc))); |
| 1174 | } |
| 1175 | if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
| 1176 | em_phy_init_script(hw); |
| 1177 | |
| 1178 | /* Configure activity LED after PHY reset */ |
| 1179 | led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register (0x00E00))))); |
| 1180 | led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF; |
| 1181 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000); |
| 1182 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register (0x00E00))), (led_ctrl))); |
| 1183 | } |
| 1184 | |
| 1185 | /* |
| 1186 | * For PCH, this write will make sure that any noise |
| 1187 | * will be detected as a CRC error and be dropped rather than show up |
| 1188 | * as a bad packet to the DMA engine. |
| 1189 | */ |
| 1190 | if (hw->mac_type == em_pchlan) |
| 1191 | E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F50 : em_translate_82542_register (0x05F50))), (0x65656565))); |
| 1192 | |
| 1193 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 1194 | DEBUGOUT("Masking off all interrupts\n"); |
| 1195 | E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register (0x000D8))), (0xffffffff))); |
| 1196 | |
| 1197 | /* Clear any pending interrupt events. */ |
| 1198 | icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register (0x000C0))))); |
| 1199 | |
| 1200 | /* If MWI was previously enabled, reenable it. */ |
| 1201 | if (hw->mac_type == em_82542_rev2_0) { |
| 1202 | if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010) |
| 1203 | em_pci_set_mwi(hw); |
| 1204 | } |
| 1205 | if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) { |
| 1206 | uint32_t kab = E1000_READ_REG(hw, KABGTXD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register (0x03004))))); |
| 1207 | kab |= E1000_KABGTXD_BGSQLBIAS0x00050000; |
| 1208 | E1000_WRITE_REG(hw, KABGTXD, kab)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register (0x03004))), (kab))); |
| 1209 | } |
| 1210 | |
| 1211 | if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { |
| 1212 | uint32_t mdicnfg; |
| 1213 | uint16_t nvm_data; |
| 1214 | |
| 1215 | /* clear global device reset status bit */ |
| 1216 | EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00008), (0x00100000))); |
| 1217 | |
| 1218 | em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A0x0024 + |
| 1219 | NVM_82580_LAN_FUNC_OFFSET(hw->bus_func)(hw->bus_func ? (0x40 + (0x40 * hw->bus_func)) : 0), 1, |
| 1220 | &nvm_data); |
| 1221 | |
| 1222 | mdicnfg = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00E04))); |
| 1223 | if (nvm_data & NVM_WORD24_EXT_MDIO0x0004) |
| 1224 | mdicnfg |= E1000_MDICNFG_EXT_MDIO0x80000000; |
| 1225 | if (nvm_data & NVM_WORD24_COM_MDIO0x0008) |
| 1226 | mdicnfg |= E1000_MDICNFG_COM_MDIO0x40000000; |
| 1227 | EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00E04), (mdicnfg))); |
| 1228 | } |
| 1229 | |
| 1230 | if (hw->mac_type == em_i210 || hw->mac_type == em_i350) |
| 1231 | em_set_eee_i350(hw); |
| 1232 | |
| 1233 | return E1000_SUCCESS0; |
| 1234 | } |
| 1235 | |
| 1236 | /****************************************************************************** |
| 1237 | * |
| 1238 | * Initialize a number of hardware-dependent bits |
| 1239 | * |
| 1240 | * hw: Struct containing variables accessed by shared code |
| 1241 | * |
| 1242 | *****************************************************************************/ |
| 1243 | STATIC void |
| 1244 | em_initialize_hardware_bits(struct em_softc *sc) |
| 1245 | { |
| 1246 | struct em_hw *hw = &sc->hw; |
| 1247 | struct em_queue *que; |
| 1248 | |
| 1249 | DEBUGFUNC("em_initialize_hardware_bits");; |
| 1250 | |
| 1251 | if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { |
| 1252 | /* Settings common to all silicon */ |
| 1253 | uint32_t reg_ctrl, reg_ctrl_ext; |
| 1254 | uint32_t reg_tarc0, reg_tarc1; |
| 1255 | uint32_t reg_tctl; |
| 1256 | uint32_t reg_txdctl; |
| 1257 | reg_tarc0 = E1000_READ_REG(hw, TARC0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register (0x03840))))); |
| 1258 | reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and |
| 1259 | * 27 */ |
| 1260 | FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + ( sc)->num_queues); (que)++) { |
| 1261 | reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me ) * 0x40))) : em_translate_82542_register(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que-> me) * 0x40)))))))); |
| 1262 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000; /* Set bit 22 */ |
| 1263 | E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me ) * 0x40))) : em_translate_82542_register(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que-> me) * 0x40)))))), (reg_txdctl))); |
| 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * Old code always initialized queue 1, |
| 1268 | * even when unused, keep behaviour |
| 1269 | */ |
| 1270 | if (sc->num_queues == 1) { |
| 1271 | reg_txdctl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register (((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40 )))))))); |
| 1272 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000; |
| 1273 | E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register (((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40 )))))), (reg_txdctl))); |
| 1274 | } |
| 1275 | |
| 1276 | switch (hw->mac_type) { |
| 1277 | case em_82571: |
| 1278 | case em_82572: |
| 1279 | reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))))); |
| 1280 | reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))))); |
| 1281 | |
| 1282 | /* Set the phy Tx compatible mode bits */ |
| 1283 | reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ |
| 1284 | |
| 1285 | reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ |
| 1286 | reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ |
| 1287 | |
| 1288 | if (reg_tctl & E1000_TCTL_MULR0x10000000) |
| 1289 | /* Clear bit 28 if MULR is 1b */ |
| 1290 | reg_tarc1 &= ~0x10000000; |
| 1291 | else |
| 1292 | /* Set bit 28 if MULR is 0b */ |
| 1293 | reg_tarc1 |= 0x10000000; |
| 1294 | |
| 1295 | E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))), (reg_tarc1))); |
| 1296 | break; |
| 1297 | case em_82573: |
| 1298 | case em_82574: |
| 1299 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1300 | reg_ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 1301 | |
| 1302 | reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ |
| 1303 | reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ |
| 1304 | reg_ctrl &= ~0x20000000; /* Clear bit 29 */ |
| 1305 | |
| 1306 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (reg_ctrl_ext))); |
| 1307 | E1000_WRITE_REG(hw, CTRL, reg_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (reg_ctrl))); |
| 1308 | break; |
| 1309 | case em_80003es2lan: |
| 1310 | if ((hw->media_type == em_media_type_fiber) || |
| 1311 | (hw->media_type == em_media_type_internal_serdes)) { |
| 1312 | /* Clear bit 20 */ |
| 1313 | reg_tarc0 &= ~0x00100000; |
| 1314 | } |
| 1315 | reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))))); |
| 1316 | reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))))); |
| 1317 | if (reg_tctl & E1000_TCTL_MULR0x10000000) |
| 1318 | /* Clear bit 28 if MULR is 1b */ |
| 1319 | reg_tarc1 &= ~0x10000000; |
| 1320 | else |
| 1321 | /* Set bit 28 if MULR is 0b */ |
| 1322 | reg_tarc1 |= 0x10000000; |
| 1323 | |
| 1324 | E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))), (reg_tarc1))); |
| 1325 | break; |
| 1326 | case em_ich8lan: |
| 1327 | case em_ich9lan: |
| 1328 | case em_ich10lan: |
| 1329 | case em_pchlan: |
| 1330 | case em_pch2lan: |
| 1331 | case em_pch_lpt: |
| 1332 | case em_pch_spt: |
| 1333 | case em_pch_cnp: |
| 1334 | case em_pch_tgp: |
| 1335 | case em_pch_adp: |
| 1336 | if (hw->mac_type == em_ich8lan) |
| 1337 | /* Set TARC0 bits 29 and 28 */ |
| 1338 | reg_tarc0 |= 0x30000000; |
| 1339 | |
| 1340 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1341 | reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ |
| 1342 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
| 1343 | if (hw->mac_type >= em_pchlan) |
| 1344 | reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN0x00100000; |
| 1345 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (reg_ctrl_ext))); |
| 1346 | |
| 1347 | reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, |
| 1348 | * 24, 26, 27 */ |
| 1349 | |
| 1350 | reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))))); |
| 1351 | reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))))); |
| 1352 | |
| 1353 | if (reg_tctl & E1000_TCTL_MULR0x10000000) |
| 1354 | /* Clear bit 28 if MULR is 1b */ |
| 1355 | reg_tarc1 &= ~0x10000000; |
| 1356 | else |
| 1357 | /* Set bit 28 if MULR is 0b */ |
| 1358 | reg_tarc1 |= 0x10000000; |
| 1359 | |
| 1360 | reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and |
| 1361 | * 30 */ |
| 1362 | |
| 1363 | E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register (0x03940))), (reg_tarc1))); |
| 1364 | break; |
| 1365 | default: |
| 1366 | break; |
| 1367 | } |
| 1368 | |
| 1369 | E1000_WRITE_REG(hw, TARC0, reg_tarc0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register (0x03840))), (reg_tarc0))); |
| 1370 | } |
| 1371 | } |
| 1372 | |
| 1373 | /** |
| 1374 | * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value |
| 1375 | * @hw: pointer to the HW structure |
| 1376 | * |
| 1377 | * Toggling the LANPHYPC pin value fully power-cycles the PHY and is |
| 1378 | * used to reset the PHY to a quiescent state when necessary. |
| 1379 | **/ |
| 1380 | static void |
| 1381 | em_toggle_lanphypc_pch_lpt(struct em_hw *hw) |
| 1382 | { |
| 1383 | uint32_t mac_reg; |
| 1384 | |
| 1385 | DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");; |
| 1386 | |
| 1387 | /* Set Phy Config Counter to 50msec */ |
| 1388 | mac_reg = E1000_READ_REG(hw, FEXTNVM3)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register (0x0003C))))); |
| 1389 | mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK0x0C000000; |
| 1390 | mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC0x08000000; |
| 1391 | E1000_WRITE_REG(hw, FEXTNVM3, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register (0x0003C))), (mac_reg))); |
| 1392 | |
| 1393 | /* Toggle LANPHYPC Value bit */ |
| 1394 | mac_reg = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 1395 | mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000; |
| 1396 | mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000; |
| 1397 | E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (mac_reg))); |
| 1398 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1399 | msec_delay(1)(*delay_func)(1000*(1)); |
| 1400 | mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000; |
| 1401 | E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (mac_reg))); |
| 1402 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1403 | |
| 1404 | if (hw->mac_type < em_pch_lpt) { |
| 1405 | msec_delay(50)(*delay_func)(1000*(50)); |
| 1406 | } else { |
| 1407 | uint16_t count = 20; |
| 1408 | |
| 1409 | do { |
| 1410 | msec_delay(5)(*delay_func)(1000*(5)); |
| 1411 | } while (!(E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))) & |
| 1412 | E1000_CTRL_EXT_LPCD0x00000004) && count--); |
| 1413 | |
| 1414 | msec_delay(30)(*delay_func)(1000*(30)); |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | /** |
| 1419 | * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP |
| 1420 | * @hw: pointer to the HW structure |
| 1421 | * @force: boolean indicating whether or not to force disabling ULP |
| 1422 | * |
| 1423 | * Un-configure ULP mode when link is up, the system is transitioned from |
| 1424 | * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled |
| 1425 | * system, poll for an indication from ME that ULP has been un-configured. |
| 1426 | * If not on an ME enabled system, un-configure the ULP mode by software. |
| 1427 | * |
| 1428 | * During nominal operation, this function is called when link is acquired |
| 1429 | * to disable ULP mode (force=FALSE); otherwise, for example when unloading |
| 1430 | * the driver or during Sx->S0 transitions, this is called with force=TRUE |
| 1431 | * to forcibly disable ULP. |
| 1432 | */ |
| 1433 | static int |
| 1434 | em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force) |
| 1435 | { |
| 1436 | int ret_val = E1000_SUCCESS0; |
| 1437 | uint32_t mac_reg; |
| 1438 | uint16_t phy_reg; |
| 1439 | int i = 0; |
| 1440 | |
| 1441 | if ((hw->mac_type < em_pch_lpt) || |
| 1442 | (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM0x153A) || |
| 1443 | (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V0x153B) || |
| 1444 | (hw->device_id == E1000_DEV_ID_PCH_I218_LM20x15A0) || |
| 1445 | (hw->device_id == E1000_DEV_ID_PCH_I218_V20x15A1)) |
| 1446 | return 0; |
| 1447 | |
| 1448 | if (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register (0x05B54))))) & E1000_FWSM_FW_VALID0x00008000) { |
| 1449 | if (force) { |
| 1450 | /* Request ME un-configure ULP mode in the PHY */ |
| 1451 | mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))))); |
| 1452 | mac_reg &= ~E1000_H2ME_ULP0x00000800; |
| 1453 | mac_reg |= E1000_H2ME_ENFORCE_SETTINGS0x00001000; |
| 1454 | E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))), (mac_reg))); |
| 1455 | } |
| 1456 | |
| 1457 | /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ |
| 1458 | while (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register (0x05B54))))) & E1000_FWSM_ULP_CFG_DONE0x00000400) { |
| 1459 | if (i++ == 30) { |
| 1460 | ret_val = -E1000_ERR_PHY2; |
| 1461 | goto out; |
| 1462 | } |
| 1463 | |
| 1464 | msec_delay(10)(*delay_func)(1000*(10)); |
| 1465 | } |
| 1466 | DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); |
| 1467 | |
| 1468 | if (force) { |
| 1469 | mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))))); |
| 1470 | mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS0x00001000; |
| 1471 | E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))), (mac_reg))); |
| 1472 | } else { |
| 1473 | /* Clear H2ME.ULP after ME ULP configuration */ |
| 1474 | mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))))); |
| 1475 | mac_reg &= ~E1000_H2ME_ULP0x00000800; |
| 1476 | E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register (0x05B50))), (mac_reg))); |
| 1477 | } |
| 1478 | |
| 1479 | goto out; |
| 1480 | } |
| 1481 | |
| 1482 | ret_val = em_get_software_flag(hw); |
| 1483 | if (ret_val) |
| 1484 | goto out; |
| 1485 | |
| 1486 | if (force) |
| 1487 | /* Toggle LANPHYPC Value bit */ |
| 1488 | em_toggle_lanphypc_pch_lpt(hw); |
| 1489 | |
| 1490 | /* Unforce SMBus mode in PHY */ |
| 1491 | ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg); |
| 1492 | if (ret_val) { |
| 1493 | /* The MAC might be in PCIe mode, so temporarily force to |
| 1494 | * SMBus mode in order to access the PHY. |
| 1495 | */ |
| 1496 | mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1497 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS0x00000800; |
| 1498 | E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (mac_reg))); |
| 1499 | |
| 1500 | msec_delay(50)(*delay_func)(1000*(50)); |
| 1501 | |
| 1502 | ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg); |
| 1503 | if (ret_val) |
| 1504 | goto release; |
| 1505 | } |
| 1506 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS0x0001; |
| 1507 | em_write_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), phy_reg); |
| 1508 | |
| 1509 | /* Unforce SMBus mode in MAC */ |
| 1510 | mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1511 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS0x00000800; |
| 1512 | E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (mac_reg))); |
| 1513 | |
| 1514 | /* When ULP mode was previously entered, K1 was disabled by the |
| 1515 | * hardware. Re-Enable K1 in the PHY when exiting ULP. |
| 1516 | */ |
| 1517 | ret_val = em_read_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), &phy_reg); |
| 1518 | if (ret_val) |
| 1519 | goto release; |
| 1520 | phy_reg |= HV_PM_CTRL_K1_ENABLE0x4000; |
| 1521 | em_write_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), phy_reg); |
| 1522 | |
| 1523 | /* Clear ULP enabled configuration */ |
| 1524 | ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), &phy_reg); |
| 1525 | if (ret_val) |
| 1526 | goto release; |
| 1527 | phy_reg &= ~(I218_ULP_CONFIG1_IND0x0004 | |
| 1528 | I218_ULP_CONFIG1_STICKY_ULP0x0010 | |
| 1529 | I218_ULP_CONFIG1_RESET_TO_SMBUS0x0100 | |
| 1530 | I218_ULP_CONFIG1_WOL_HOST0x0040 | |
| 1531 | I218_ULP_CONFIG1_INBAND_EXIT0x0020 | |
| 1532 | I218_ULP_CONFIG1_EN_ULP_LANPHYPC0x0400 | |
| 1533 | I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST0x0800 | |
| 1534 | I218_ULP_CONFIG1_DISABLE_SMB_PERST0x1000); |
| 1535 | em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg); |
| 1536 | |
| 1537 | /* Commit ULP changes by starting auto ULP configuration */ |
| 1538 | phy_reg |= I218_ULP_CONFIG1_START0x0001; |
| 1539 | em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg); |
| 1540 | |
| 1541 | /* Clear Disable SMBus Release on PERST# in MAC */ |
| 1542 | mac_reg = E1000_READ_REG(hw, FEXTNVM7)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register (0xe4UL))))); |
| 1543 | mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST0x00000020; |
| 1544 | E1000_WRITE_REG(hw, FEXTNVM7, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register (0xe4UL))), (mac_reg))); |
| 1545 | |
| 1546 | release: |
| 1547 | em_release_software_flag(hw); |
| 1548 | if (force) { |
| 1549 | em_phy_reset(hw); |
| 1550 | msec_delay(50)(*delay_func)(1000*(50)); |
| 1551 | } |
| 1552 | out: |
| 1553 | if (ret_val) |
| 1554 | DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); |
| 1555 | |
| 1556 | return ret_val; |
| 1557 | } |
| 1558 | |
| 1559 | /****************************************************************************** |
| 1560 | * Performs basic configuration of the adapter. |
| 1561 | * |
| 1562 | * hw - Struct containing variables accessed by shared code |
| 1563 | * |
| 1564 | * Assumes that the controller has previously been reset and is in a |
| 1565 | * post-reset uninitialized state. Initializes the receive address registers, |
| 1566 | * multicast table, and VLAN filter table. Calls routines to setup link |
| 1567 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
| 1568 | * the transmit and receive units disabled and uninitialized. |
| 1569 | *****************************************************************************/ |
| 1570 | int32_t |
| 1571 | em_init_hw(struct em_softc *sc) |
| 1572 | { |
| 1573 | struct em_hw *hw = &sc->hw; |
| 1574 | struct em_queue *que; |
| 1575 | uint32_t ctrl; |
| 1576 | uint32_t i; |
| 1577 | int32_t ret_val; |
| 1578 | uint16_t pcix_cmd_word; |
| 1579 | uint16_t pcix_stat_hi_word; |
| 1580 | uint16_t cmd_mmrbc; |
| 1581 | uint16_t stat_mmrbc; |
| 1582 | uint32_t mta_size; |
| 1583 | uint32_t reg_data; |
| 1584 | uint32_t ctrl_ext; |
| 1585 | uint32_t snoop; |
| 1586 | uint32_t fwsm; |
| 1587 | DEBUGFUNC("em_init_hw");; |
| 1588 | |
| 1589 | /* force full DMA clock frequency for ICH8 */ |
| 1590 | if (hw->mac_type == em_ich8lan) { |
| 1591 | reg_data = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1592 | reg_data &= ~0x80000000; |
| 1593 | E1000_WRITE_REG(hw, STATUS, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))), (reg_data))); |
| 1594 | } |
| 1595 | |
| 1596 | if (hw->mac_type == em_pchlan || |
| 1597 | hw->mac_type == em_pch2lan || |
| 1598 | hw->mac_type == em_pch_lpt || |
| 1599 | hw->mac_type == em_pch_spt || |
| 1600 | hw->mac_type == em_pch_cnp || |
| 1601 | hw->mac_type == em_pch_tgp || |
| 1602 | hw->mac_type == em_pch_adp) { |
| 1603 | /* |
| 1604 | * The MAC-PHY interconnect may still be in SMBus mode |
| 1605 | * after Sx->S0. Toggle the LANPHYPC Value bit to force |
| 1606 | * the interconnect to PCIe mode, but only if there is no |
| 1607 | * firmware present otherwise firmware will have done it. |
| 1608 | */ |
| 1609 | fwsm = E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register (0x05B54))))); |
| 1610 | if ((fwsm & E1000_FWSM_FW_VALID0x00008000) == 0) { |
| 1611 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 1612 | ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000; |
| 1613 | ctrl &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000; |
| 1614 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 1615 | usec_delay(10)(*delay_func)(10); |
| 1616 | ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000; |
| 1617 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 1618 | msec_delay(50)(*delay_func)(1000*(50)); |
| 1619 | } |
| 1620 | |
| 1621 | /* Gate automatic PHY configuration on non-managed 82579 */ |
| 1622 | if (hw->mac_type == em_pch2lan) |
| 1623 | em_gate_hw_phy_config_ich8lan(hw, TRUE1); |
| 1624 | |
| 1625 | em_disable_ulp_lpt_lp(hw, TRUE1); |
| 1626 | /* |
| 1627 | * Reset the PHY before any access to it. Doing so, |
| 1628 | * ensures that the PHY is in a known good state before |
| 1629 | * we read/write PHY registers. The generic reset is |
| 1630 | * sufficient here, because we haven't determined |
| 1631 | * the PHY type yet. |
| 1632 | */ |
| 1633 | em_phy_reset(hw); |
| 1634 | |
| 1635 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 1636 | if (hw->mac_type == em_pch2lan && |
| 1637 | (fwsm & E1000_FWSM_FW_VALID0x00008000) == 0) |
| 1638 | em_gate_hw_phy_config_ich8lan(hw, FALSE0); |
| 1639 | |
| 1640 | /* Set MDIO slow mode before any other MDIO access */ |
| 1641 | ret_val = em_set_mdio_slow_mode_hv(hw); |
| 1642 | if (ret_val) |
| 1643 | return ret_val; |
| 1644 | } |
| 1645 | |
| 1646 | /* Initialize Identification LED */ |
| 1647 | ret_val = em_id_led_init(hw); |
| 1648 | if (ret_val) { |
| 1649 | DEBUGOUT("Error Initializing Identification LED\n"); |
| 1650 | return ret_val; |
| 1651 | } |
| 1652 | /* Set the media type and TBI compatibility */ |
| 1653 | em_set_media_type(hw); |
| 1654 | |
| 1655 | /* Magic delay that improves problems with i219LM on HP Elitebook */ |
| 1656 | msec_delay(1)(*delay_func)(1000*(1)); |
| 1657 | /* Must be called after em_set_media_type because media_type is used */ |
| 1658 | em_initialize_hardware_bits(sc); |
| 1659 | |
| 1660 | /* Disabling VLAN filtering. */ |
| 1661 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
| 1662 | /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ |
| 1663 | if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) { |
| 1664 | if (hw->mac_type < em_82545_rev_3) |
| 1665 | E1000_WRITE_REG(hw, VET, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00038 : em_translate_82542_register (0x00038))), (0))); |
| 1666 | if (hw->mac_type == em_i350) |
| 1667 | em_clear_vfta_i350(hw); |
| 1668 | else |
| 1669 | em_clear_vfta(hw); |
| 1670 | } |
| 1671 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
| 1672 | if (hw->mac_type == em_82542_rev2_0) { |
| 1673 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 1674 | em_pci_clear_mwi(hw); |
| 1675 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))), (0x00000001))); |
| 1676 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1677 | msec_delay(5)(*delay_func)(1000*(5)); |
| 1678 | } |
| 1679 | /* |
| 1680 | * Setup the receive address. This involves initializing all of the |
| 1681 | * Receive Address Registers (RARs 0 - 15). |
| 1682 | */ |
| 1683 | em_init_rx_addrs(hw); |
| 1684 | |
| 1685 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ |
| 1686 | if (hw->mac_type == em_82542_rev2_0) { |
| 1687 | E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))), (0))); |
| 1688 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1689 | msec_delay(1)(*delay_func)(1000*(1)); |
| 1690 | if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010) |
| 1691 | em_pci_set_mwi(hw); |
| 1692 | } |
| 1693 | /* Zero out the Multicast HASH table */ |
| 1694 | DEBUGOUT("Zeroing the MTA\n"); |
| 1695 | mta_size = E1000_MC_TBL_SIZE128; |
| 1696 | if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) |
| 1697 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN32; |
| 1698 | for (i = 0; i < mta_size; i++) { |
| 1699 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register (0x05200)) + ((i) << 2)), (0))); |
| 1700 | /* |
| 1701 | * use write flush to prevent Memory Write Block (MWB) from |
| 1702 | * occurring when accessing our register space |
| 1703 | */ |
| 1704 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 1705 | } |
| 1706 | /* |
| 1707 | * Set the PCI priority bit correctly in the CTRL register. This |
| 1708 | * determines if the adapter gives priority to receives, or if it |
| 1709 | * gives equal priority to transmits and receives. Valid only on |
| 1710 | * 82542 and 82543 silicon. |
| 1711 | */ |
| 1712 | if (hw->dma_fairness && hw->mac_type <= em_82543) { |
| 1713 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 1714 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl | 0x00000004))); |
| 1715 | } |
| 1716 | switch (hw->mac_type) { |
| 1717 | case em_82545_rev_3: |
| 1718 | case em_82546_rev_3: |
| 1719 | break; |
| 1720 | default: |
| 1721 | /* |
| 1722 | * Workaround for PCI-X problem when BIOS sets MMRBC |
| 1723 | * incorrectly. |
| 1724 | */ |
| 1725 | if (hw->bus_type == em_bus_type_pcix) { |
| 1726 | em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6, |
| 1727 | &pcix_cmd_word); |
| 1728 | em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI0xEA, |
| 1729 | &pcix_stat_hi_word); |
| 1730 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK0x000C) |
| 1731 | >> PCIX_COMMAND_MMRBC_SHIFT0x2; |
| 1732 | stat_mmrbc = (pcix_stat_hi_word & |
| 1733 | PCIX_STATUS_HI_MMRBC_MASK0x0060) >> |
| 1734 | PCIX_STATUS_HI_MMRBC_SHIFT0x5; |
| 1735 | |
| 1736 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K0x3) |
| 1737 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K0x2; |
| 1738 | if (cmd_mmrbc > stat_mmrbc) { |
| 1739 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK0x000C; |
| 1740 | pcix_cmd_word |= stat_mmrbc << |
| 1741 | PCIX_COMMAND_MMRBC_SHIFT0x2; |
| 1742 | em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6, |
| 1743 | &pcix_cmd_word); |
| 1744 | } |
| 1745 | } |
| 1746 | break; |
| 1747 | } |
| 1748 | |
| 1749 | /* More time needed for PHY to initialize */ |
| 1750 | if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) |
| 1751 | msec_delay(15)(*delay_func)(1000*(15)); |
| 1752 | |
| 1753 | /* |
| 1754 | * The 82578 Rx buffer will stall if wakeup is enabled in host and |
| 1755 | * the ME. Reading the BM_WUC register will clear the host wakeup bit. |
| 1756 | * Reset the phy after disabling host wakeup to reset the Rx buffer. |
| 1757 | */ |
| 1758 | if (hw->phy_type == em_phy_82578) { |
| 1759 | em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1)(((800) << 5) | ((1) & 0x1F)), |
| 1760 | (uint16_t *)®_data); |
| 1761 | ret_val = em_phy_reset(hw); |
| 1762 | if (ret_val) |
| 1763 | return ret_val; |
| 1764 | } |
| 1765 | |
| 1766 | /* Call a subroutine to configure the link and setup flow control. */ |
| 1767 | ret_val = em_setup_link(hw); |
| 1768 | |
| 1769 | /* Set the transmit descriptor write-back policy */ |
| 1770 | if (hw->mac_type > em_82544) { |
| 1771 | FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + ( sc)->num_queues); (que)++) { |
| 1772 | ctrl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me ) * 0x40))) : em_translate_82542_register(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que-> me) * 0x40)))))))); |
| 1773 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) | |
| 1774 | E1000_TXDCTL_FULL_TX_DESC_WB0x01010000; |
| 1775 | E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me ) * 0x40))) : em_translate_82542_register(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que-> me) * 0x40)))))), (ctrl))); |
| 1776 | } |
| 1777 | } |
| 1778 | if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { |
| 1779 | em_enable_tx_pkt_filtering(hw); |
| 1780 | } |
| 1781 | switch (hw->mac_type) { |
| 1782 | default: |
| 1783 | break; |
| 1784 | case em_80003es2lan: |
| 1785 | /* Enable retransmit on late collisions */ |
| 1786 | reg_data = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))))); |
| 1787 | reg_data |= E1000_TCTL_RTLC0x01000000; |
| 1788 | E1000_WRITE_REG(hw, TCTL, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))), (reg_data))); |
| 1789 | |
| 1790 | /* Configure Gigabit Carry Extend Padding */ |
| 1791 | reg_data = E1000_READ_REG(hw, TCTL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register (0x00404))))); |
| 1792 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK0x000FFC00; |
| 1793 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX0x00010000; |
| 1794 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register (0x00404))), (reg_data))); |
| 1795 | |
| 1796 | /* Configure Transmit Inter-Packet Gap */ |
| 1797 | reg_data = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))))); |
| 1798 | reg_data &= ~E1000_TIPG_IPGT_MASK0x000003FF; |
| 1799 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008; |
| 1800 | E1000_WRITE_REG(hw, TIPG, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))), (reg_data))); |
| 1801 | |
| 1802 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register (0x05F00)) + ((0x0001) << 2)))); |
| 1803 | reg_data &= ~0x00100000; |
| 1804 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register (0x05F00)) + ((0x0001) << 2)), (reg_data))); |
| 1805 | /* FALLTHROUGH */ |
| 1806 | case em_82571: |
| 1807 | case em_82572: |
| 1808 | case em_82575: |
| 1809 | case em_82576: |
| 1810 | case em_82580: |
| 1811 | case em_i210: |
| 1812 | case em_i350: |
| 1813 | case em_ich8lan: |
| 1814 | case em_ich9lan: |
| 1815 | case em_ich10lan: |
| 1816 | case em_pchlan: |
| 1817 | case em_pch2lan: |
| 1818 | case em_pch_lpt: |
| 1819 | case em_pch_spt: |
| 1820 | case em_pch_cnp: |
| 1821 | case em_pch_tgp: |
| 1822 | case em_pch_adp: |
| 1823 | /* |
| 1824 | * Old code always initialized queue 1, |
| 1825 | * even when unused, keep behaviour |
| 1826 | */ |
| 1827 | if (sc->num_queues == 1) { |
| 1828 | ctrl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register (((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40 )))))))); |
| 1829 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) | |
| 1830 | E1000_TXDCTL_FULL_TX_DESC_WB0x01010000; |
| 1831 | E1000_WRITE_REG(hw, TXDCTL(1), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register (((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40 )))))), (ctrl))); |
| 1832 | } |
| 1833 | break; |
| 1834 | } |
| 1835 | |
| 1836 | if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { |
| 1837 | uint32_t gcr = E1000_READ_REG(hw, GCR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register (0x05B00))))); |
| 1838 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX0x08000000; |
| 1839 | E1000_WRITE_REG(hw, GCR, gcr)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register (0x05B00))), (gcr))); |
| 1840 | } |
| 1841 | /* |
| 1842 | * Clear all of the statistics registers (clear on read). It is |
| 1843 | * important that we do this after we have tried to establish link |
| 1844 | * because the symbol error count will increment wildly if there is |
| 1845 | * no link. |
| 1846 | */ |
| 1847 | em_clear_hw_cntrs(hw); |
| 1848 | /* |
| 1849 | * ICH8 No-snoop bits are opposite polarity. Set to snoop by default |
| 1850 | * after reset. |
| 1851 | */ |
| 1852 | if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) { |
| 1853 | if (hw->mac_type == em_ich8lan) |
| 1854 | snoop = PCI_EX_82566_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020); |
| 1855 | else |
| 1856 | snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020)); |
| 1857 | |
| 1858 | em_set_pci_ex_no_snoop(hw, snoop); |
| 1859 | } |
| 1860 | |
| 1861 | /* ungate DMA clock to avoid packet loss */ |
| 1862 | if (hw->mac_type >= em_pch_tgp) { |
| 1863 | uint32_t fflt_dbg = E1000_READ_REG(hw, FFLT_DBG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register (0x05F04))))); |
| 1864 | fflt_dbg |= (1 << 12); |
| 1865 | E1000_WRITE_REG(hw, FFLT_DBG, fflt_dbg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register (0x05F04))), (fflt_dbg))); |
| 1866 | } |
| 1867 | |
| 1868 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER0x1099 || |
| 1869 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5) { |
| 1870 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 1871 | /* |
| 1872 | * Relaxed ordering must be disabled to avoid a parity error |
| 1873 | * crash in a PCI slot. |
| 1874 | */ |
| 1875 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS0x00020000; |
| 1876 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 1877 | } |
| 1878 | return ret_val; |
| 1879 | } |
| 1880 | |
| 1881 | /****************************************************************************** |
| 1882 | * Adjust SERDES output amplitude based on EEPROM setting. |
| 1883 | * |
| 1884 | * hw - Struct containing variables accessed by shared code. |
| 1885 | *****************************************************************************/ |
| 1886 | static int32_t |
| 1887 | em_adjust_serdes_amplitude(struct em_hw *hw) |
| 1888 | { |
| 1889 | uint16_t eeprom_data; |
| 1890 | int32_t ret_val; |
| 1891 | DEBUGFUNC("em_adjust_serdes_amplitude");; |
| 1892 | |
| 1893 | if (hw->media_type != em_media_type_internal_serdes || |
| 1894 | hw->mac_type >= em_82575) |
| 1895 | return E1000_SUCCESS0; |
| 1896 | |
| 1897 | switch (hw->mac_type) { |
| 1898 | case em_82545_rev_3: |
| 1899 | case em_82546_rev_3: |
| 1900 | break; |
| 1901 | default: |
| 1902 | return E1000_SUCCESS0; |
| 1903 | } |
| 1904 | |
| 1905 | ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE0x0006, 1, &eeprom_data); |
| 1906 | if (ret_val) { |
| 1907 | return ret_val; |
| 1908 | } |
| 1909 | if (eeprom_data != EEPROM_RESERVED_WORD0xFFFF) { |
| 1910 | /* Adjust SERDES output amplitude only. */ |
| 1911 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK0x000F; |
| 1912 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL0x1A, |
| 1913 | eeprom_data); |
| 1914 | if (ret_val) |
| 1915 | return ret_val; |
| 1916 | } |
| 1917 | return E1000_SUCCESS0; |
| 1918 | } |
| 1919 | |
| 1920 | /****************************************************************************** |
| 1921 | * Configures flow control and link settings. |
| 1922 | * |
| 1923 | * hw - Struct containing variables accessed by shared code |
| 1924 | * |
| 1925 | * Determines which flow control settings to use. Calls the appropriate media- |
| 1926 | * specific link configuration function. Configures the flow control settings. |
| 1927 | * Assuming the adapter has a valid link partner, a valid link should be |
| 1928 | * established. Assumes the hardware has previously been reset and the |
| 1929 | * transmitter and receiver are not enabled. |
| 1930 | *****************************************************************************/ |
| 1931 | int32_t |
| 1932 | em_setup_link(struct em_hw *hw) |
| 1933 | { |
| 1934 | uint32_t ctrl_ext; |
| 1935 | int32_t ret_val; |
| 1936 | uint16_t eeprom_data; |
| 1937 | uint16_t eeprom_control2_reg_offset; |
| 1938 | DEBUGFUNC("em_setup_link");; |
| 1939 | |
| 1940 | eeprom_control2_reg_offset = |
| 1941 | (hw->mac_type != em_icp_xxxx) |
| 1942 | ? EEPROM_INIT_CONTROL2_REG0x000F |
| 1943 | : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num)((((hw->icp_xxxx_port_num) + 1) << 4) + 1); |
| 1944 | /* |
| 1945 | * In the case of the phy reset being blocked, we already have a |
| 1946 | * link. We do not have to set it up again. |
| 1947 | */ |
| 1948 | if (em_check_phy_reset_block(hw)) |
| 1949 | return E1000_SUCCESS0; |
| 1950 | /* |
| 1951 | * Read and store word 0x0F of the EEPROM. This word contains bits |
| 1952 | * that determine the hardware's default PAUSE (flow control) mode, a |
| 1953 | * bit that determines whether the HW defaults to enabling or |
| 1954 | * disabling auto-negotiation, and the direction of the SW defined |
| 1955 | * pins. If there is no SW over-ride of the flow control setting, |
| 1956 | * then the variable hw->fc will be initialized based on a value in |
| 1957 | * the EEPROM. |
| 1958 | */ |
| 1959 | if (hw->fc == E1000_FC_DEFAULT0xFF) { |
| 1960 | switch (hw->mac_type) { |
| 1961 | case em_ich8lan: |
| 1962 | case em_ich9lan: |
| 1963 | case em_ich10lan: |
| 1964 | case em_pchlan: |
| 1965 | case em_pch2lan: |
| 1966 | case em_pch_lpt: |
| 1967 | case em_pch_spt: |
| 1968 | case em_pch_cnp: |
| 1969 | case em_pch_tgp: |
| 1970 | case em_pch_adp: |
| 1971 | case em_82573: |
| 1972 | case em_82574: |
| 1973 | hw->fc = E1000_FC_FULL3; |
| 1974 | break; |
| 1975 | default: |
| 1976 | ret_val = em_read_eeprom(hw, |
| 1977 | eeprom_control2_reg_offset, 1, &eeprom_data); |
| 1978 | if (ret_val) { |
| 1979 | DEBUGOUT("EEPROM Read Error\n"); |
| 1980 | return -E1000_ERR_EEPROM1; |
| 1981 | } |
| 1982 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) == 0) |
| 1983 | hw->fc = E1000_FC_NONE0; |
| 1984 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) == |
| 1985 | EEPROM_WORD0F_ASM_DIR0x2000) |
| 1986 | hw->fc = E1000_FC_TX_PAUSE2; |
| 1987 | else |
| 1988 | hw->fc = E1000_FC_FULL3; |
| 1989 | break; |
| 1990 | } |
| 1991 | } |
| 1992 | /* |
| 1993 | * We want to save off the original Flow Control configuration just |
| 1994 | * in case we get disconnected and then reconnected into a different |
| 1995 | * hub or switch with different Flow Control capabilities. |
| 1996 | */ |
| 1997 | if (hw->mac_type == em_82542_rev2_0) |
| 1998 | hw->fc &= (~E1000_FC_TX_PAUSE2); |
| 1999 | |
| 2000 | if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) |
| 2001 | hw->fc &= (~E1000_FC_RX_PAUSE1); |
| 2002 | |
| 2003 | hw->original_fc = hw->fc; |
| 2004 | |
| 2005 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
| 2006 | /* |
| 2007 | * Take the 4 bits from EEPROM word 0x0F that determine the initial |
| 2008 | * polarity value for the SW controlled pins, and setup the Extended |
| 2009 | * Device Control reg with that info. This is needed because one of |
| 2010 | * the SW controlled pins is used for signal detection. So this |
| 2011 | * should be done before em_setup_pcs_link() or em_phy_setup() is |
| 2012 | * called. |
| 2013 | */ |
| 2014 | if (hw->mac_type == em_82543) { |
| 2015 | ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG0x000F, |
| 2016 | 1, &eeprom_data); |
| 2017 | if (ret_val) { |
| 2018 | DEBUGOUT("EEPROM Read Error\n"); |
| 2019 | return -E1000_ERR_EEPROM1; |
| 2020 | } |
| 2021 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT0x00F0) << |
| 2022 | SWDPIO__EXT_SHIFT4); |
| 2023 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (ctrl_ext))); |
| 2024 | } |
| 2025 | /* Make sure we have a valid PHY */ |
| 2026 | ret_val = em_detect_gig_phy(hw); |
| 2027 | if (ret_val) { |
| 2028 | DEBUGOUT("Error, did not detect valid phy.\n"); |
| 2029 | if (hw->mac_type == em_icp_xxxx) |
| 2030 | return E1000_DEFER_INIT15; |
| 2031 | else |
| 2032 | return ret_val; |
| 2033 | } |
| 2034 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
| 2035 | |
| 2036 | /* Call the necessary subroutine to configure the link. */ |
| 2037 | switch (hw->media_type) { |
| 2038 | case em_media_type_copper: |
| 2039 | case em_media_type_oem: |
| 2040 | ret_val = em_setup_copper_link(hw); |
| 2041 | break; |
| 2042 | default: |
| 2043 | ret_val = em_setup_fiber_serdes_link(hw); |
| 2044 | break; |
| 2045 | } |
| 2046 | /* |
| 2047 | * Initialize the flow control address, type, and PAUSE timer |
| 2048 | * registers to their default values. This is done even if flow |
| 2049 | * control is disabled, because it does not hurt anything to |
| 2050 | * initialize these registers. |
| 2051 | */ |
| 2052 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" |
| 2053 | ); |
| 2054 | |
| 2055 | /* |
| 2056 | * FCAL/H and FCT are hardcoded to standard values in |
| 2057 | * em_ich8lan / em_ich9lan / em_ich10lan. |
| 2058 | */ |
| 2059 | if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan || hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan || hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp )) { |
| 2060 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00030 : em_translate_82542_register (0x00030))), (0x8808))); |
| 2061 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x0002C : em_translate_82542_register (0x0002C))), (0x00000100))); |
| 2062 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00028 : em_translate_82542_register (0x00028))), (0x00C28001))); |
| 2063 | } |
| 2064 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00170 : em_translate_82542_register (0x00170))), (hw->fc_pause_time))); |
| 2065 | |
| 2066 | if (hw->phy_type == em_phy_82577 || |
| 2067 | hw->phy_type == em_phy_82578 || |
| 2068 | hw->phy_type == em_phy_82579 || |
| 2069 | hw->phy_type == em_phy_i217) { |
| 2070 | E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05F40 : em_translate_82542_register (0x05F40))), (0x1000))); |
| 2071 | em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27)(((769) << 5) | ((27) & 0x1F)), |
| 2072 | hw->fc_pause_time); |
| 2073 | } |
| 2074 | |
| 2075 | /* |
| 2076 | * Set the flow control receive threshold registers. Normally, these |
| 2077 | * registers will be set to a default threshold that may be adjusted |
| 2078 | * later by the driver's runtime code. However, if the ability to |
| 2079 | * transmit pause frames in not enabled, then these registers will be |
| 2080 | * set to 0. |
| 2081 | */ |
| 2082 | if (!(hw->fc & E1000_FC_TX_PAUSE2)) { |
| 2083 | E1000_WRITE_REG(hw, FCRTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register (0x02160))), (0))); |
| 2084 | E1000_WRITE_REG(hw, FCRTH, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register (0x02168))), (0))); |
| 2085 | } else { |
| 2086 | /* |
| 2087 | * We need to set up the Receive Threshold high and low water |
| 2088 | * marks as well as (optionally) enabling the transmission of |
| 2089 | * XON frames. |
| 2090 | */ |
| 2091 | if (hw->fc_send_xon) { |
| 2092 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register (0x02160))), ((hw->fc_low_water | 0x80000000)))) |
| 2093 | | E1000_FCRTL_XONE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register (0x02160))), ((hw->fc_low_water | 0x80000000)))); |
| 2094 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register (0x02168))), (hw->fc_high_water))); |
| 2095 | } else { |
| 2096 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register (0x02160))), (hw->fc_low_water))); |
| 2097 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register (0x02168))), (hw->fc_high_water))); |
| 2098 | } |
| 2099 | } |
| 2100 | return ret_val; |
| 2101 | } |
| 2102 | |
| 2103 | void |
| 2104 | em_power_up_serdes_link_82575(struct em_hw *hw) |
| 2105 | { |
| 2106 | uint32_t reg; |
| 2107 | |
| 2108 | if (hw->media_type != em_media_type_internal_serdes && |
| 2109 | hw->sgmii_active == FALSE0) |
| 2110 | return; |
| 2111 | |
| 2112 | /* Enable PCS to turn on link */ |
| 2113 | reg = E1000_READ_REG(hw, PCS_CFG0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register (0x04200))))); |
| 2114 | reg |= E1000_PCS_CFG_PCS_EN8; |
| 2115 | E1000_WRITE_REG(hw, PCS_CFG0, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register (0x04200))), (reg))); |
| 2116 | |
| 2117 | /* Power up the laser */ |
| 2118 | reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 2119 | reg &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080; |
| 2120 | E1000_WRITE_REG(hw, CTRL_EXT, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (reg))); |
| 2121 | |
| 2122 | /* flush the write to verify completion */ |
| 2123 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 2124 | delay(5)(*delay_func)(5); |
| 2125 | } |
| 2126 | |
| 2127 | /****************************************************************************** |
| 2128 | * Sets up link for a fiber based or serdes based adapter |
| 2129 | * |
| 2130 | * hw - Struct containing variables accessed by shared code |
| 2131 | * |
| 2132 | * Manipulates Physical Coding Sublayer functions in order to configure |
| 2133 | * link. Assumes the hardware has been previously reset and the transmitter |
| 2134 | * and receiver are not enabled. |
| 2135 | *****************************************************************************/ |
| 2136 | static int32_t |
| 2137 | em_setup_fiber_serdes_link(struct em_hw *hw) |
| 2138 | { |
| 2139 | uint32_t ctrl, ctrl_ext, reg; |
| 2140 | uint32_t status; |
| 2141 | uint32_t txcw = 0; |
| 2142 | uint32_t i; |
| 2143 | uint32_t signal = 0; |
| 2144 | int32_t ret_val; |
| 2145 | DEBUGFUNC("em_setup_fiber_serdes_link");; |
| 2146 | |
| 2147 | if (hw->media_type != em_media_type_internal_serdes && |
| 2148 | hw->sgmii_active == FALSE0) |
| 2149 | return -E1000_ERR_CONFIG3; |
| 2150 | |
| 2151 | /* |
| 2152 | * On 82571 and 82572 Fiber connections, SerDes loopback mode |
| 2153 | * persists until explicitly turned off or a power cycle is |
| 2154 | * performed. A read to the register does not indicate its status. |
| 2155 | * Therefore, we ensure loopback mode is disabled during |
| 2156 | * initialization. |
| 2157 | */ |
| 2158 | if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || |
| 2159 | hw->mac_type >= em_82575) |
| 2160 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00024 : em_translate_82542_register (0x00024))), (0x0400))); |
| 2161 | |
| 2162 | if (hw->mac_type >= em_82575) |
| 2163 | em_power_up_serdes_link_82575(hw); |
| 2164 | |
| 2165 | /* |
| 2166 | * On adapters with a MAC newer than 82544, SWDP 1 will be set when |
| 2167 | * the optics detect a signal. On older adapters, it will be cleared |
| 2168 | * when there is a signal. This applies to fiber media only. If |
| 2169 | * we're on serdes media, adjust the output amplitude to value set in |
| 2170 | * the EEPROM. |
| 2171 | */ |
| 2172 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 2173 | if (hw->media_type == em_media_type_fiber) |
| 2174 | signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN10x00080000 : 0; |
| 2175 | |
| 2176 | ret_val = em_adjust_serdes_amplitude(hw); |
| 2177 | if (ret_val) |
| 2178 | return ret_val; |
| 2179 | |
| 2180 | /* Take the link out of reset */ |
| 2181 | ctrl &= ~(E1000_CTRL_LRST0x00000008); |
| 2182 | |
| 2183 | if (hw->mac_type >= em_82575) { |
| 2184 | /* set both sw defined pins on 82575/82576*/ |
| 2185 | ctrl |= E1000_CTRL_SWDPIN00x00040000 | E1000_CTRL_SWDPIN10x00080000; |
| 2186 | |
| 2187 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 2188 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) { |
| 2189 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000: |
| 2190 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000: |
| 2191 | /* the backplane is always connected */ |
| 2192 | reg = E1000_READ_REG(hw, PCS_LCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register (0x04208))))); |
| 2193 | reg |= E1000_PCS_LCTL_FORCE_FCTRL0x80; |
| 2194 | reg |= E1000_PCS_LCTL_FSV_10004 | E1000_PCS_LCTL_FDV_FULL8; |
| 2195 | reg |= E1000_PCS_LCTL_FSD0x10; /* Force Speed */ |
| 2196 | DEBUGOUT("Configuring Forced Link\n"); |
| 2197 | E1000_WRITE_REG(hw, PCS_LCTL, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register (0x04208))), (reg))); |
| 2198 | em_force_mac_fc(hw); |
| 2199 | hw->autoneg_failed = 0; |
| 2200 | return E1000_SUCCESS0; |
| 2201 | break; |
| 2202 | default: |
| 2203 | /* Set switch control to serdes energy detect */ |
| 2204 | reg = E1000_READ_REG(hw, CONNSW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register (0x00034))))); |
| 2205 | reg |= E1000_CONNSW_ENRGSRC0x4; |
| 2206 | E1000_WRITE_REG(hw, CONNSW, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register (0x00034))), (reg))); |
| 2207 | break; |
| 2208 | } |
| 2209 | } |
| 2210 | |
| 2211 | /* Adjust VCO speed to improve BER performance */ |
| 2212 | ret_val = em_set_vco_speed(hw); |
| 2213 | if (ret_val) |
| 2214 | return ret_val; |
| 2215 | |
| 2216 | em_config_collision_dist(hw); |
| 2217 | /* |
| 2218 | * Check for a software override of the flow control settings, and |
| 2219 | * setup the device accordingly. If auto-negotiation is enabled, |
| 2220 | * then software will have to set the "PAUSE" bits to the correct |
| 2221 | * value in the Tranmsit Config Word Register (TXCW) and re-start |
| 2222 | * auto-negotiation. However, if auto-negotiation is disabled, then |
| 2223 | * software will have to manually configure the two flow control |
| 2224 | * enable bits in the CTRL register. |
| 2225 | * |
| 2226 | * The possible values of the "fc" parameter are: 0: Flow control is |
| 2227 | * completely disabled 1: Rx flow control is enabled (we can receive |
| 2228 | * pause frames, but not send pause frames). 2: Tx flow control is |
| 2229 | * enabled (we can send pause frames but we do not support receiving |
| 2230 | * pause frames). 3: Both Rx and TX flow control (symmetric) are |
| 2231 | * enabled. |
| 2232 | */ |
| 2233 | switch (hw->fc) { |
| 2234 | case E1000_FC_NONE0: |
| 2235 | /* |
| 2236 | * Flow control is completely disabled by a software |
| 2237 | * over-ride. |
| 2238 | */ |
| 2239 | txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020); |
| 2240 | break; |
| 2241 | case E1000_FC_RX_PAUSE1: |
| 2242 | /* |
| 2243 | * RX Flow control is enabled and TX Flow control is disabled |
| 2244 | * by a software over-ride. Since there really isn't a way to |
| 2245 | * advertise that we are capable of RX Pause ONLY, we will |
| 2246 | * advertise that we support both symmetric and asymmetric RX |
| 2247 | * PAUSE. Later, we will disable the adapter's ability to |
| 2248 | * send PAUSE frames. |
| 2249 | */ |
| 2250 | txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 | |
| 2251 | E1000_TXCW_PAUSE_MASK0x00000180); |
| 2252 | break; |
| 2253 | case E1000_FC_TX_PAUSE2: |
| 2254 | /* |
| 2255 | * TX Flow control is enabled, and RX Flow control is |
| 2256 | * disabled, by a software over-ride. |
| 2257 | */ |
| 2258 | txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 | E1000_TXCW_ASM_DIR0x00000100); |
| 2259 | break; |
| 2260 | case E1000_FC_FULL3: |
| 2261 | /* |
| 2262 | * Flow control (both RX and TX) is enabled by a software |
| 2263 | * over-ride. |
| 2264 | */ |
| 2265 | txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 | |
| 2266 | E1000_TXCW_PAUSE_MASK0x00000180); |
| 2267 | break; |
| 2268 | default: |
| 2269 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 2270 | return -E1000_ERR_CONFIG3; |
| 2271 | break; |
| 2272 | } |
| 2273 | /* |
| 2274 | * Since auto-negotiation is enabled, take the link out of reset (the |
| 2275 | * link will be in reset, because we previously reset the chip). This |
| 2276 | * will restart auto-negotiation. If auto-negotiation is successful |
| 2277 | * then the link-up status bit will be set and the flow control |
| 2278 | * enable bits (RFCE and TFCE) will be set according to their |
| 2279 | * negotiated value. |
| 2280 | */ |
| 2281 | DEBUGOUT("Auto-negotiation enabled\n"); |
| 2282 | |
| 2283 | E1000_WRITE_REG(hw, TXCW, txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register (0x00178))), (txcw))); |
| 2284 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 2285 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 2286 | |
| 2287 | hw->txcw = txcw; |
| 2288 | msec_delay(1)(*delay_func)(1000*(1)); |
| 2289 | /* |
| 2290 | * If we have a signal (the cable is plugged in) then poll for a |
| 2291 | * "Link-Up" indication in the Device Status Register. Time-out if a |
| 2292 | * link isn't seen in 500 milliseconds seconds (Auto-negotiation |
| 2293 | * should complete in less than 500 milliseconds even if the other |
| 2294 | * end is doing it in SW). For internal serdes, we just assume a |
| 2295 | * signal is present, then poll. |
| 2296 | */ |
| 2297 | if (hw->media_type == em_media_type_internal_serdes || |
| 2298 | (E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))) & E1000_CTRL_SWDPIN10x00080000) == signal) { |
| 2299 | DEBUGOUT("Looking for Link\n"); |
| 2300 | for (i = 0; i < (LINK_UP_TIMEOUT500 / 10); i++) { |
| 2301 | msec_delay(10)(*delay_func)(1000*(10)); |
| 2302 | status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 2303 | if (status & E1000_STATUS_LU0x00000002) |
| 2304 | break; |
| 2305 | } |
| 2306 | if (i == (LINK_UP_TIMEOUT500 / 10)) { |
| 2307 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
| 2308 | hw->autoneg_failed = 1; |
| 2309 | /* |
| 2310 | * AutoNeg failed to achieve a link, so we'll call |
| 2311 | * em_check_for_link. This routine will force the |
| 2312 | * link up if we detect a signal. This will allow us |
| 2313 | * to communicate with non-autonegotiating link |
| 2314 | * partners. |
| 2315 | */ |
| 2316 | ret_val = em_check_for_link(hw); |
| 2317 | if (ret_val) { |
| 2318 | DEBUGOUT("Error while checking for link\n"); |
| 2319 | return ret_val; |
| 2320 | } |
| 2321 | hw->autoneg_failed = 0; |
| 2322 | } else { |
| 2323 | hw->autoneg_failed = 0; |
| 2324 | DEBUGOUT("Valid Link Found\n"); |
| 2325 | } |
| 2326 | } else { |
| 2327 | DEBUGOUT("No Signal Detected\n"); |
| 2328 | } |
| 2329 | return E1000_SUCCESS0; |
| 2330 | } |
| 2331 | |
| 2332 | /****************************************************************************** |
| 2333 | * Make sure we have a valid PHY and change PHY mode before link setup. |
| 2334 | * |
| 2335 | * hw - Struct containing variables accessed by shared code |
| 2336 | *****************************************************************************/ |
| 2337 | static int32_t |
| 2338 | em_copper_link_preconfig(struct em_hw *hw) |
| 2339 | { |
| 2340 | uint32_t ctrl; |
| 2341 | int32_t ret_val; |
| 2342 | uint16_t phy_data; |
| 2343 | DEBUGFUNC("em_copper_link_preconfig");; |
| 2344 | |
| 2345 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 2346 | /* |
| 2347 | * With 82543, we need to force speed and duplex on the MAC equal to |
| 2348 | * what the PHY speed and duplex configuration is. In addition, we |
| 2349 | * need to perform a hardware reset on the PHY to take it out of |
| 2350 | * reset. |
| 2351 | */ |
| 2352 | if (hw->mac_type > em_82543) { |
| 2353 | ctrl |= E1000_CTRL_SLU0x00000040; |
| 2354 | ctrl &= ~(E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000); |
| 2355 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 2356 | } else { |
| 2357 | ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000 | |
| 2358 | E1000_CTRL_SLU0x00000040); |
| 2359 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 2360 | ret_val = em_phy_hw_reset(hw); |
| 2361 | if (ret_val) |
| 2362 | return ret_val; |
| 2363 | } |
| 2364 | |
| 2365 | /* Set PHY to class A mode (if necessary) */ |
| 2366 | ret_val = em_set_phy_mode(hw); |
| 2367 | if (ret_val) |
| 2368 | return ret_val; |
| 2369 | |
| 2370 | if ((hw->mac_type == em_82545_rev_3) || |
| 2371 | (hw->mac_type == em_82546_rev_3)) { |
| 2372 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 2373 | &phy_data); |
| 2374 | phy_data |= 0x00000008; |
| 2375 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 2376 | phy_data); |
| 2377 | } |
| 2378 | if (hw->mac_type <= em_82543 || |
| 2379 | hw->mac_type == em_82541 || hw->mac_type == em_82547 || |
| 2380 | hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) |
| 2381 | hw->phy_reset_disable = FALSE0; |
| 2382 | if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 || |
| 2383 | hw->mac_type == em_82576 || |
| 2384 | hw->mac_type == em_i210 || hw->mac_type == em_i350) && |
| 2385 | hw->sgmii_active) { |
| 2386 | /* allow time for SFP cage time to power up phy */ |
| 2387 | msec_delay(300)(*delay_func)(1000*(300)); |
| 2388 | |
| 2389 | /* |
| 2390 | * SFP documentation requires the following to configure the SFP module |
| 2391 | * to work on SGMII. No further documentation is given. |
| 2392 | */ |
| 2393 | em_write_phy_reg(hw, 0x1B, 0x8084); |
| 2394 | em_phy_hw_reset(hw); |
| 2395 | } |
| 2396 | |
| 2397 | return E1000_SUCCESS0; |
| 2398 | } |
| 2399 | |
| 2400 | /****************************************************************************** |
| 2401 | * Copper link setup for em_phy_igp series. |
| 2402 | * |
| 2403 | * hw - Struct containing variables accessed by shared code |
| 2404 | *****************************************************************************/ |
| 2405 | static int32_t |
| 2406 | em_copper_link_igp_setup(struct em_hw *hw) |
| 2407 | { |
| 2408 | uint32_t led_ctrl; |
| 2409 | int32_t ret_val; |
| 2410 | uint16_t phy_data; |
| 2411 | DEBUGFUNC("em_copper_link_igp_setup");; |
| 2412 | |
| 2413 | if (hw->phy_reset_disable) |
| 2414 | return E1000_SUCCESS0; |
| 2415 | |
| 2416 | ret_val = em_phy_reset(hw); |
| 2417 | if (ret_val) { |
| 2418 | DEBUGOUT("Error Resetting the PHY\n"); |
| 2419 | return ret_val; |
| 2420 | } |
| 2421 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
| 2422 | msec_delay(15)(*delay_func)(1000*(15)); |
| 2423 | if (hw->mac_type != em_ich8lan && |
| 2424 | hw->mac_type != em_ich9lan && |
| 2425 | hw->mac_type != em_ich10lan) { |
| 2426 | /* Configure activity LED after PHY reset */ |
| 2427 | led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register (0x00E00))))); |
| 2428 | led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF; |
| 2429 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000); |
| 2430 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register (0x00E00))), (led_ctrl))); |
| 2431 | } |
| 2432 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
| 2433 | if (hw->phy_type == em_phy_igp) { |
| 2434 | /* disable lplu d3 during driver init */ |
| 2435 | ret_val = em_set_d3_lplu_state(hw, FALSE0); |
| 2436 | if (ret_val) { |
| 2437 | DEBUGOUT("Error Disabling LPLU D3\n"); |
| 2438 | return ret_val; |
| 2439 | } |
| 2440 | } |
| 2441 | /* disable lplu d0 during driver init */ |
| 2442 | if (hw->mac_type == em_pchlan || |
| 2443 | hw->mac_type == em_pch2lan || |
| 2444 | hw->mac_type == em_pch_lpt || |
| 2445 | hw->mac_type == em_pch_spt || |
| 2446 | hw->mac_type == em_pch_cnp || |
| 2447 | hw->mac_type == em_pch_tgp || |
| 2448 | hw->mac_type == em_pch_adp) |
| 2449 | ret_val = em_set_lplu_state_pchlan(hw, FALSE0); |
| 2450 | else |
| 2451 | ret_val = em_set_d0_lplu_state(hw, FALSE0); |
| 2452 | if (ret_val) { |
| 2453 | DEBUGOUT("Error Disabling LPLU D0\n"); |
| 2454 | return ret_val; |
| 2455 | } |
| 2456 | /* Configure mdi-mdix settings */ |
| 2457 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, &phy_data); |
| 2458 | if (ret_val) |
| 2459 | return ret_val; |
| 2460 | |
| 2461 | if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
| 2462 | hw->dsp_config_state = em_dsp_config_disabled; |
| 2463 | /* Force MDI for earlier revs of the IGP PHY */ |
| 2464 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX0x1000 | |
| 2465 | IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000); |
| 2466 | hw->mdix = 1; |
| 2467 | |
| 2468 | } else { |
| 2469 | hw->dsp_config_state = em_dsp_config_enabled; |
| 2470 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000; |
| 2471 | |
| 2472 | switch (hw->mdix) { |
| 2473 | case 1: |
| 2474 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000; |
| 2475 | break; |
| 2476 | case 2: |
| 2477 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000; |
| 2478 | break; |
| 2479 | case 0: |
| 2480 | default: |
| 2481 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX0x1000; |
| 2482 | break; |
| 2483 | } |
| 2484 | } |
| 2485 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, phy_data); |
| 2486 | if (ret_val) |
| 2487 | return ret_val; |
| 2488 | |
| 2489 | /* set auto-master slave resolution settings */ |
| 2490 | if (hw->autoneg) { |
| 2491 | em_ms_type phy_ms_setting = hw->master_slave; |
| 2492 | if (hw->ffe_config_state == em_ffe_config_active) |
| 2493 | hw->ffe_config_state = em_ffe_config_enabled; |
| 2494 | |
| 2495 | if (hw->dsp_config_state == em_dsp_config_activated) |
| 2496 | hw->dsp_config_state = em_dsp_config_enabled; |
| 2497 | /* |
| 2498 | * when autonegotiation advertisement is only 1000Mbps then |
| 2499 | * we should disable SmartSpeed and enable Auto MasterSlave |
| 2500 | * resolution as hardware default. |
| 2501 | */ |
| 2502 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL0x0020) { |
| 2503 | /* Disable SmartSpeed */ |
| 2504 | ret_val = em_read_phy_reg(hw, |
| 2505 | IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data); |
| 2506 | if (ret_val) |
| 2507 | return ret_val; |
| 2508 | |
| 2509 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080; |
| 2510 | ret_val = em_write_phy_reg(hw, |
| 2511 | IGP01E1000_PHY_PORT_CONFIG0x10, phy_data); |
| 2512 | if (ret_val) |
| 2513 | return ret_val; |
| 2514 | /* Set auto Master/Slave resolution process */ |
| 2515 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09, |
| 2516 | &phy_data); |
| 2517 | if (ret_val) |
| 2518 | return ret_val; |
| 2519 | |
| 2520 | phy_data &= ~CR_1000T_MS_ENABLE0x1000; |
| 2521 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09, |
| 2522 | phy_data); |
| 2523 | if (ret_val) |
| 2524 | return ret_val; |
| 2525 | } |
| 2526 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09, &phy_data); |
| 2527 | if (ret_val) |
| 2528 | return ret_val; |
| 2529 | |
| 2530 | /* load defaults for future use */ |
| 2531 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE0x1000) ? |
| 2532 | ((phy_data & CR_1000T_MS_VALUE0x0800) ? em_ms_force_master : |
| 2533 | em_ms_force_slave) : em_ms_auto; |
| 2534 | |
| 2535 | switch (phy_ms_setting) { |
| 2536 | case em_ms_force_master: |
| 2537 | phy_data |= (CR_1000T_MS_ENABLE0x1000 | CR_1000T_MS_VALUE0x0800); |
| 2538 | break; |
| 2539 | case em_ms_force_slave: |
| 2540 | phy_data |= CR_1000T_MS_ENABLE0x1000; |
| 2541 | phy_data &= ~(CR_1000T_MS_VALUE0x0800); |
| 2542 | break; |
| 2543 | case em_ms_auto: |
| 2544 | phy_data &= ~CR_1000T_MS_ENABLE0x1000; |
| 2545 | break; |
| 2546 | default: |
| 2547 | break; |
| 2548 | } |
| 2549 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09, phy_data); |
| 2550 | if (ret_val) |
| 2551 | return ret_val; |
| 2552 | } |
| 2553 | return E1000_SUCCESS0; |
| 2554 | } |
| 2555 | |
| 2556 | /****************************************************************************** |
| 2557 | * Copper link setup for em_phy_gg82563 series. |
| 2558 | * |
| 2559 | * hw - Struct containing variables accessed by shared code |
| 2560 | *****************************************************************************/ |
| 2561 | static int32_t |
| 2562 | em_copper_link_ggp_setup(struct em_hw *hw) |
| 2563 | { |
| 2564 | int32_t ret_val; |
| 2565 | uint16_t phy_data; |
| 2566 | uint32_t reg_data; |
| 2567 | DEBUGFUNC("em_copper_link_ggp_setup");; |
| 2568 | |
| 2569 | if (!hw->phy_reset_disable) { |
| 2570 | |
| 2571 | /* Enable CRS on TX for half-duplex operation. */ |
| 2572 | ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)), |
| 2573 | &phy_data); |
| 2574 | if (ret_val) |
| 2575 | return ret_val; |
| 2576 | |
| 2577 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010; |
| 2578 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ |
| 2579 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ0x0007; |
| 2580 | |
| 2581 | ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)), |
| 2582 | phy_data); |
| 2583 | if (ret_val) |
| 2584 | return ret_val; |
| 2585 | /* |
| 2586 | * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 |
| 2587 | * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only |
| 2588 | * (MDI-X for 10/100Base-T modes) |
| 2589 | */ |
| 2590 | ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)), |
| 2591 | &phy_data); |
| 2592 | |
| 2593 | if (ret_val) |
| 2594 | return ret_val; |
| 2595 | |
| 2596 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK0x0060; |
| 2597 | |
| 2598 | switch (hw->mdix) { |
| 2599 | case 1: |
| 2600 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI0x0000; |
| 2601 | break; |
| 2602 | case 2: |
| 2603 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX0x0020; |
| 2604 | break; |
| 2605 | case 0: |
| 2606 | default: |
| 2607 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO0x0060; |
| 2608 | break; |
| 2609 | } |
| 2610 | /* |
| 2611 | * Options: disable_polarity_correction = 0 (default) |
| 2612 | * Automatic Correction for Reversed Cable Polarity 0 - |
| 2613 | * Disabled 1 - Enabled |
| 2614 | */ |
| 2615 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002; |
| 2616 | if (hw->disable_polarity_correction == 1) |
| 2617 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002; |
| 2618 | ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)), |
| 2619 | phy_data); |
| 2620 | |
| 2621 | if (ret_val) |
| 2622 | return ret_val; |
| 2623 | |
| 2624 | /* SW Reset the PHY so all changes take effect */ |
| 2625 | ret_val = em_phy_reset(hw); |
| 2626 | if (ret_val) { |
| 2627 | DEBUGOUT("Error Resetting the PHY\n"); |
| 2628 | return ret_val; |
| 2629 | } |
| 2630 | } /* phy_reset_disable */ |
| 2631 | if (hw->mac_type == em_80003es2lan) { |
| 2632 | /* Bypass RX and TX FIFO's */ |
| 2633 | ret_val = em_write_kmrn_reg(hw, |
| 2634 | E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL0x00000000, |
| 2635 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS0x00000008 | |
| 2636 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS0x00000800); |
| 2637 | if (ret_val) |
| 2638 | return ret_val; |
| 2639 | |
| 2640 | ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)), |
| 2641 | &phy_data); |
| 2642 | if (ret_val) |
| 2643 | return ret_val; |
| 2644 | |
| 2645 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG0x2000; |
| 2646 | ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)), |
| 2647 | phy_data); |
| 2648 | |
| 2649 | if (ret_val) |
| 2650 | return ret_val; |
| 2651 | |
| 2652 | reg_data = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))))); |
| 2653 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000); |
| 2654 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register (0x00018))), (reg_data))); |
| 2655 | |
| 2656 | ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)), |
| 2657 | &phy_data); |
| 2658 | if (ret_val) |
| 2659 | return ret_val; |
| 2660 | /* |
| 2661 | * Do not init these registers when the HW is in IAMT mode, |
| 2662 | * since the firmware will have already initialized them. We |
| 2663 | * only initialize them if the HW is not in IAMT mode. |
| 2664 | */ |
| 2665 | if (em_check_mng_mode(hw) == FALSE0) { |
| 2666 | /* Enable Electrical Idle on the PHY */ |
| 2667 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE0x0001; |
| 2668 | ret_val = em_write_phy_reg(hw, |
| 2669 | GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)), phy_data); |
| 2670 | if (ret_val) |
| 2671 | return ret_val; |
| 2672 | |
| 2673 | ret_val = em_read_phy_reg(hw, |
| 2674 | GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &phy_data); |
| 2675 | if (ret_val) |
| 2676 | return ret_val; |
| 2677 | |
| 2678 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800; |
| 2679 | ret_val = em_write_phy_reg(hw, |
| 2680 | GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), phy_data); |
| 2681 | |
| 2682 | if (ret_val) |
| 2683 | return ret_val; |
| 2684 | } |
| 2685 | /* |
| 2686 | * Workaround: Disable padding in Kumeran interface in the |
| 2687 | * MAC and in the PHY to avoid CRC errors. |
| 2688 | */ |
| 2689 | ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)), |
| 2690 | &phy_data); |
| 2691 | if (ret_val) |
| 2692 | return ret_val; |
| 2693 | phy_data |= GG82563_ICR_DIS_PADDING0x0010; |
| 2694 | ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)), |
| 2695 | phy_data); |
| 2696 | if (ret_val) |
| 2697 | return ret_val; |
| 2698 | } |
| 2699 | return E1000_SUCCESS0; |
| 2700 | } |
| 2701 | |
| 2702 | /****************************************************************************** |
| 2703 | * Copper link setup for em_phy_m88 series. |
| 2704 | * |
| 2705 | * hw - Struct containing variables accessed by shared code |
| 2706 | *****************************************************************************/ |
| 2707 | static int32_t |
| 2708 | em_copper_link_mgp_setup(struct em_hw *hw) |
| 2709 | { |
| 2710 | int32_t ret_val; |
| 2711 | uint16_t phy_data; |
| 2712 | DEBUGFUNC("em_copper_link_mgp_setup");; |
| 2713 | |
| 2714 | if (hw->phy_reset_disable) |
| 2715 | return E1000_SUCCESS0; |
| 2716 | |
| 2717 | /* disable lplu d0 during driver init */ |
| 2718 | if (hw->mac_type == em_pchlan || |
| 2719 | hw->mac_type == em_pch2lan || |
| 2720 | hw->mac_type == em_pch_lpt || |
| 2721 | hw->mac_type == em_pch_spt || |
| 2722 | hw->mac_type == em_pch_cnp || |
| 2723 | hw->mac_type == em_pch_tgp || |
| 2724 | hw->mac_type == em_pch_adp) |
| 2725 | ret_val = em_set_lplu_state_pchlan(hw, FALSE0); |
| 2726 | |
| 2727 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 2728 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, &phy_data); |
| 2729 | if (ret_val) |
| 2730 | return ret_val; |
| 2731 | |
| 2732 | if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0) { |
| 2733 | phy_data |= 0x00000008; |
| 2734 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 2735 | phy_data); |
| 2736 | if (ret_val) |
| 2737 | return ret_val; |
| 2738 | |
| 2739 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 2740 | &phy_data); |
| 2741 | if (ret_val) |
| 2742 | return ret_val; |
| 2743 | |
| 2744 | phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800; |
| 2745 | |
| 2746 | } |
| 2747 | /* For BM PHY this bit is downshift enable */ |
| 2748 | else if (hw->phy_type != em_phy_bm) |
| 2749 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800; |
| 2750 | /* |
| 2751 | * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI |
| 2752 | * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for |
| 2753 | * 10/100Base-T modes) |
| 2754 | */ |
| 2755 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060; |
| 2756 | |
| 2757 | switch (hw->mdix) { |
| 2758 | case 1: |
| 2759 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE0x0000; |
| 2760 | break; |
| 2761 | case 2: |
| 2762 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE0x0020; |
| 2763 | break; |
| 2764 | case 3: |
| 2765 | phy_data |= M88E1000_PSCR_AUTO_X_1000T0x0040; |
| 2766 | break; |
| 2767 | case 0: |
| 2768 | default: |
| 2769 | phy_data |= M88E1000_PSCR_AUTO_X_MODE0x0060; |
| 2770 | break; |
| 2771 | } |
| 2772 | /* |
| 2773 | * Options: disable_polarity_correction = 0 (default) Automatic |
| 2774 | * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled |
| 2775 | */ |
| 2776 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL0x0002; |
| 2777 | if (hw->disable_polarity_correction == 1) |
| 2778 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL0x0002; |
| 2779 | |
| 2780 | /* Enable downshift on BM (disabled by default) */ |
| 2781 | if (hw->phy_type == em_phy_bm) |
| 2782 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT0x0800; |
| 2783 | |
| 2784 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, phy_data); |
| 2785 | if (ret_val) |
| 2786 | return ret_val; |
| 2787 | |
| 2788 | if (((hw->phy_type == em_phy_m88) && |
| 2789 | (hw->phy_revision < M88E1011_I_REV_40x04) && |
| 2790 | (hw->phy_id != BME1000_E_PHY_ID0x01410CB0)) || |
| 2791 | (hw->phy_type == em_phy_oem)) { |
| 2792 | /* |
| 2793 | * Force TX_CLK in the Extended PHY Specific Control Register |
| 2794 | * to 25MHz clock. |
| 2795 | */ |
| 2796 | ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14, |
| 2797 | &phy_data); |
| 2798 | if (ret_val) |
| 2799 | return ret_val; |
| 2800 | |
| 2801 | if (hw->phy_type == em_phy_oem) { |
| 2802 | phy_data |= M88E1000_EPSCR_TX_TIME_CTRL0x0002; |
| 2803 | phy_data |= M88E1000_EPSCR_RX_TIME_CTRL0x0080; |
| 2804 | } |
| 2805 | phy_data |= M88E1000_EPSCR_TX_CLK_250x0070; |
| 2806 | |
| 2807 | if ((hw->phy_revision == E1000_REVISION_22) && |
| 2808 | (hw->phy_id == M88E1111_I_PHY_ID0x01410CC0)) { |
| 2809 | /* Vidalia Phy, set the downshift counter to 5x */ |
| 2810 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK0x0E00); |
| 2811 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X0x0800; |
| 2812 | ret_val = em_write_phy_reg(hw, |
| 2813 | M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data); |
| 2814 | if (ret_val) |
| 2815 | return ret_val; |
| 2816 | } else { |
| 2817 | /* Configure Master and Slave downshift values */ |
| 2818 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK0x0C00 | |
| 2819 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK0x0300); |
| 2820 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X0x0000 | |
| 2821 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X0x0100); |
| 2822 | ret_val = em_write_phy_reg(hw, |
| 2823 | M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data); |
| 2824 | if (ret_val) |
| 2825 | return ret_val; |
| 2826 | } |
| 2827 | } |
| 2828 | if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { |
| 2829 | /* |
| 2830 | * Set PHY page 0, register 29 to 0x0003 |
| 2831 | * The next two writes are supposed to lower BER for gig |
| 2832 | * connection |
| 2833 | */ |
| 2834 | ret_val = em_write_phy_reg(hw, BM_REG_BIAS129, 0x0003); |
| 2835 | if (ret_val) |
| 2836 | return ret_val; |
| 2837 | |
| 2838 | /* Set PHY page 0, register 30 to 0x0000 */ |
| 2839 | ret_val = em_write_phy_reg(hw, BM_REG_BIAS230, 0x0000); |
| 2840 | if (ret_val) |
| 2841 | return ret_val; |
| 2842 | } |
| 2843 | if (hw->phy_type == em_phy_82578) { |
| 2844 | ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14, |
| 2845 | &phy_data); |
| 2846 | if (ret_val) |
| 2847 | return ret_val; |
| 2848 | |
| 2849 | /* 82578 PHY - set the downshift count to 1x. */ |
| 2850 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE0x0020; |
| 2851 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK0x001C; |
| 2852 | ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14, |
| 2853 | phy_data); |
| 2854 | if (ret_val) |
| 2855 | return ret_val; |
| 2856 | } |
| 2857 | /* SW Reset the PHY so all changes take effect */ |
| 2858 | ret_val = em_phy_reset(hw); |
| 2859 | if (ret_val) { |
| 2860 | DEBUGOUT("Error Resetting the PHY\n"); |
| 2861 | return ret_val; |
| 2862 | } |
| 2863 | return E1000_SUCCESS0; |
| 2864 | } |
| 2865 | |
| 2866 | /****************************************************************************** |
| 2867 | * Copper link setup for em_phy_82577 series. |
| 2868 | * |
| 2869 | * hw - Struct containing variables accessed by shared code |
| 2870 | *****************************************************************************/ |
| 2871 | static int32_t |
| 2872 | em_copper_link_82577_setup(struct em_hw *hw) |
| 2873 | { |
| 2874 | int32_t ret_val; |
| 2875 | uint16_t phy_data; |
| 2876 | uint32_t led_ctl; |
| 2877 | DEBUGFUNC("em_copper_link_82577_setup");; |
| 2878 | |
| 2879 | if (hw->phy_reset_disable) |
| 2880 | return E1000_SUCCESS0; |
| 2881 | |
| 2882 | /* Enable CRS on TX for half-duplex operation. */ |
| 2883 | ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG22, &phy_data); |
| 2884 | if (ret_val) |
| 2885 | return ret_val; |
| 2886 | |
| 2887 | phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX(1 << 15) | |
| 2888 | I82577_PHY_CFG_ENABLE_DOWNSHIFT((1 << 10) + (1 << 11)); |
| 2889 | |
| 2890 | ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG22, phy_data); |
| 2891 | if (ret_val) |
| 2892 | return ret_val; |
| 2893 | |
| 2894 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
| 2895 | msec_delay(15)(*delay_func)(1000*(15)); |
| 2896 | led_ctl = hw->ledctl_mode1; |
| 2897 | |
| 2898 | /* disable lplu d0 during driver init */ |
| 2899 | ret_val = em_set_lplu_state_pchlan(hw, FALSE0); |
| 2900 | if (ret_val) { |
| 2901 | DEBUGOUT("Error Disabling LPLU D0\n"); |
| 2902 | return ret_val; |
| 2903 | } |
| 2904 | |
| 2905 | E1000_WRITE_REG(hw, LEDCTL, led_ctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register (0x00E00))), (led_ctl))); |
| 2906 | |
| 2907 | return E1000_SUCCESS0; |
| 2908 | } |
| 2909 | |
| 2910 | static int32_t |
| 2911 | em_copper_link_82580_setup(struct em_hw *hw) |
| 2912 | { |
| 2913 | int32_t ret_val; |
| 2914 | uint16_t phy_data; |
| 2915 | |
| 2916 | if (hw->phy_reset_disable) |
| 2917 | return E1000_SUCCESS0; |
| 2918 | |
| 2919 | ret_val = em_phy_reset(hw); |
| 2920 | if (ret_val) |
| 2921 | goto out; |
| 2922 | |
| 2923 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 2924 | ret_val = em_read_phy_reg(hw, I82580_CFG_REG22, &phy_data); |
| 2925 | if (ret_val) |
| 2926 | goto out; |
| 2927 | |
| 2928 | phy_data |= I82580_CFG_ASSERT_CRS_ON_TX(1 << 15) | |
| 2929 | I82580_CFG_ENABLE_DOWNSHIFT(3 << 10); |
| 2930 | |
| 2931 | ret_val = em_write_phy_reg(hw, I82580_CFG_REG22, phy_data); |
| 2932 | |
| 2933 | out: |
| 2934 | return ret_val; |
| 2935 | } |
| 2936 | |
| 2937 | static int32_t |
| 2938 | em_copper_link_rtl8211_setup(struct em_hw *hw) |
| 2939 | { |
| 2940 | int32_t ret_val; |
| 2941 | uint16_t phy_data; |
| 2942 | |
| 2943 | DEBUGFUNC("em_copper_link_rtl8211_setup: begin");; |
| 2944 | |
| 2945 | if (!hw) { |
| 2946 | return -1; |
| 2947 | } |
| 2948 | /* SW Reset the PHY so all changes take effect */ |
| 2949 | em_phy_hw_reset(hw); |
| 2950 | |
| 2951 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 2952 | phy_data = 0; |
| 2953 | |
| 2954 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data); |
| 2955 | if (ret_val) { |
| 2956 | printf("Unable to read RGEPHY_CR register\n"); |
| 2957 | return ret_val; |
| 2958 | } |
| 2959 | DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, |
| 2960 | hw->phy_addr, phy_data); |
| 2961 | phy_data |= RGEPHY_CR_ASSERT_CRS0x0800; |
| 2962 | |
| 2963 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data); |
| 2964 | if (ret_val) { |
| 2965 | printf("Unable to write RGEPHY_CR register\n"); |
| 2966 | return ret_val; |
| 2967 | } |
| 2968 | |
| 2969 | phy_data = 0; /* LED Control Register 0x18 */ |
| 2970 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC0x18, &phy_data); |
| 2971 | if (ret_val) { |
| 2972 | printf("Unable to read RGEPHY_LC register\n"); |
| 2973 | return ret_val; |
| 2974 | } |
| 2975 | |
| 2976 | phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ |
| 2977 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data); |
| 2978 | if (ret_val) { |
| 2979 | printf("Unable to write RGEPHY_LC register\n"); |
| 2980 | return ret_val; |
| 2981 | } |
| 2982 | /* LED Control and Definition Register 0x11, PHY spec status reg */ |
| 2983 | phy_data = 0; |
| 2984 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data); |
| 2985 | if (ret_val) { |
| 2986 | printf("Unable to read RGEPHY_SR register\n"); |
| 2987 | return ret_val; |
| 2988 | } |
| 2989 | |
| 2990 | phy_data |= 0x0010; /* LED active Low */ |
| 2991 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR0x11, phy_data); |
| 2992 | if (ret_val) { |
| 2993 | printf("Unable to write RGEPHY_SR register\n"); |
| 2994 | return ret_val; |
| 2995 | } |
| 2996 | |
| 2997 | phy_data = 0; |
| 2998 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data); |
| 2999 | if (ret_val) { |
| 3000 | printf("Unable to read RGEPHY_SR register\n"); |
| 3001 | return ret_val; |
| 3002 | } |
| 3003 | |
| 3004 | /* Switch to Page2 */ |
| 3005 | phy_data = RGEPHY_PS_PAGE_20x0002; |
| 3006 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data); |
| 3007 | if (ret_val) { |
| 3008 | printf("Unable to write PHY RGEPHY_PS register\n"); |
| 3009 | return ret_val; |
| 3010 | } |
| 3011 | |
| 3012 | phy_data = 0x0000; |
| 3013 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data); |
| 3014 | if (ret_val) { |
| 3015 | printf("Unable to write RGEPHY_LC_P2 register\n"); |
| 3016 | return ret_val; |
| 3017 | } |
| 3018 | usec_delay(5)(*delay_func)(5); |
| 3019 | |
| 3020 | |
| 3021 | /* LED Configuration Control Reg for setting for 0x1A Register */ |
| 3022 | phy_data = 0; |
| 3023 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data); |
| 3024 | if (ret_val) { |
| 3025 | printf("Unable to read RGEPHY_LC_P2 register\n"); |
| 3026 | return ret_val; |
| 3027 | } |
| 3028 | |
| 3029 | phy_data &= 0xF000; |
| 3030 | phy_data |= 0x0F24; |
| 3031 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data); |
| 3032 | if (ret_val) { |
| 3033 | printf("Unable to write RGEPHY_LC_P2 register\n"); |
| 3034 | return ret_val; |
| 3035 | } |
| 3036 | phy_data = 0; |
| 3037 | ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data); |
| 3038 | if (ret_val) { |
| 3039 | printf("Unable to read RGEPHY_LC_P2 register\n"); |
| 3040 | return ret_val; |
| 3041 | } |
| 3042 | DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); |
| 3043 | |
| 3044 | |
| 3045 | /* After setting Page2, go back to Page 0 */ |
| 3046 | phy_data = 0; |
| 3047 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data); |
| 3048 | if (ret_val) { |
| 3049 | printf("Unable to write PHY RGEPHY_PS register\n"); |
| 3050 | return ret_val; |
| 3051 | } |
| 3052 | |
| 3053 | /* pulse streching= 42-84ms, blink rate=84mm */ |
| 3054 | phy_data = 0x140 | RGEPHY_LC_PULSE_42MS0x2000 | RGEPHY_LC_LINK0x0008 | |
| 3055 | RGEPHY_LC_DUPLEX0x0004 | RGEPHY_LC_RX0x0002; |
| 3056 | |
| 3057 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data); |
| 3058 | if (ret_val) { |
| 3059 | printf("Unable to write RGEPHY_LC register\n"); |
| 3060 | return ret_val; |
| 3061 | } |
| 3062 | return E1000_SUCCESS0; |
| 3063 | } |
| 3064 | |
| 3065 | /****************************************************************************** |
| 3066 | * Setup auto-negotiation and flow control advertisements, |
| 3067 | * and then perform auto-negotiation. |
| 3068 | * |
| 3069 | * hw - Struct containing variables accessed by shared code |
| 3070 | *****************************************************************************/ |
| 3071 | int32_t |
| 3072 | em_copper_link_autoneg(struct em_hw *hw) |
| 3073 | { |
| 3074 | int32_t ret_val; |
| 3075 | uint16_t phy_data; |
| 3076 | DEBUGFUNC("em_copper_link_autoneg");; |
| 3077 | /* |
| 3078 | * Perform some bounds checking on the hw->autoneg_advertised |
| 3079 | * parameter. If this variable is zero, then set it to the default. |
| 3080 | */ |
| 3081 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F; |
| 3082 | /* |
| 3083 | * If autoneg_advertised is zero, we assume it was not defaulted by |
| 3084 | * the calling code so we set to advertise full capability. |
| 3085 | */ |
| 3086 | if (hw->autoneg_advertised == 0) |
| 3087 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F; |
| 3088 | |
| 3089 | /* IFE phy only supports 10/100 */ |
| 3090 | if (hw->phy_type == em_phy_ife) |
| 3091 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL0x000F; |
| 3092 | |
| 3093 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
| 3094 | ret_val = em_phy_setup_autoneg(hw); |
| 3095 | if (ret_val) { |
| 3096 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
| 3097 | return ret_val; |
| 3098 | } |
| 3099 | DEBUGOUT("Restarting Auto-Neg\n"); |
| 3100 | /* |
| 3101 | * Restart auto-negotiation by setting the Auto Neg Enable bit and |
| 3102 | * the Auto Neg Restart bit in the PHY control register. |
| 3103 | */ |
| 3104 | ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &phy_data); |
| 3105 | if (ret_val) |
| 3106 | return ret_val; |
| 3107 | |
| 3108 | phy_data |= (MII_CR_AUTO_NEG_EN0x1000 | MII_CR_RESTART_AUTO_NEG0x0200); |
| 3109 | ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, phy_data); |
| 3110 | if (ret_val) |
| 3111 | return ret_val; |
| 3112 | /* |
| 3113 | * Does the user want to wait for Auto-Neg to complete here, or check |
| 3114 | * at a later time (for example, callback routine). |
| 3115 | */ |
| 3116 | if (hw->wait_autoneg_complete) { |
| 3117 | ret_val = em_wait_autoneg(hw); |
| 3118 | if (ret_val) { |
| 3119 | DEBUGOUT("Error while waiting for autoneg to complete\n" |
| 3120 | ); |
| 3121 | return ret_val; |
| 3122 | } |
| 3123 | } |
| 3124 | hw->get_link_status = TRUE1; |
| 3125 | |
| 3126 | return E1000_SUCCESS0; |
| 3127 | } |
| 3128 | |
| 3129 | /****************************************************************************** |
| 3130 | * Config the MAC and the PHY after link is up. |
| 3131 | * 1) Set up the MAC to the current PHY speed/duplex |
| 3132 | * if we are on 82543. If we |
| 3133 | * are on newer silicon, we only need to configure |
| 3134 | * collision distance in the Transmit Control Register. |
| 3135 | * 2) Set up flow control on the MAC to that established with |
| 3136 | * the link partner. |
| 3137 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
| 3138 | * |
| 3139 | * hw - Struct containing variables accessed by shared code |
| 3140 | *****************************************************************************/ |
| 3141 | int32_t |
| 3142 | em_copper_link_postconfig(struct em_hw *hw) |
| 3143 | { |
| 3144 | int32_t ret_val; |
| 3145 | DEBUGFUNC("em_copper_link_postconfig");; |
| 3146 | |
| 3147 | if (hw->mac_type >= em_82544 && |
| 3148 | hw->mac_type != em_icp_xxxx) { |
| 3149 | em_config_collision_dist(hw); |
| 3150 | } else { |
| 3151 | ret_val = em_config_mac_to_phy(hw); |
| 3152 | if (ret_val) { |
| 3153 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 3154 | return ret_val; |
| 3155 | } |
| 3156 | } |
| 3157 | ret_val = em_config_fc_after_link_up(hw); |
| 3158 | if (ret_val) { |
| 3159 | DEBUGOUT("Error Configuring Flow Control\n"); |
| 3160 | return ret_val; |
| 3161 | } |
| 3162 | /* Config DSP to improve Giga link quality */ |
| 3163 | if (hw->phy_type == em_phy_igp) { |
| 3164 | ret_val = em_config_dsp_after_link_change(hw, TRUE1); |
| 3165 | if (ret_val) { |
| 3166 | DEBUGOUT("Error Configuring DSP after link up\n"); |
| 3167 | return ret_val; |
| 3168 | } |
| 3169 | } |
| 3170 | return E1000_SUCCESS0; |
| 3171 | } |
| 3172 | |
| 3173 | /****************************************************************************** |
| 3174 | * Detects which PHY is present and setup the speed and duplex |
| 3175 | * |
| 3176 | * hw - Struct containing variables accessed by shared code |
| 3177 | *****************************************************************************/ |
| 3178 | static int32_t |
| 3179 | em_setup_copper_link(struct em_hw *hw) |
| 3180 | { |
| 3181 | int32_t ret_val; |
| 3182 | uint16_t i; |
| 3183 | uint16_t phy_data; |
| 3184 | uint16_t reg_data; |
| 3185 | DEBUGFUNC("em_setup_copper_link");; |
| 3186 | |
| 3187 | switch (hw->mac_type) { |
| 3188 | case em_80003es2lan: |
| 3189 | case em_ich8lan: |
| 3190 | case em_ich9lan: |
| 3191 | case em_ich10lan: |
| 3192 | case em_pchlan: |
| 3193 | case em_pch2lan: |
| 3194 | case em_pch_lpt: |
| 3195 | case em_pch_spt: |
| 3196 | case em_pch_cnp: |
| 3197 | case em_pch_tgp: |
| 3198 | case em_pch_adp: |
| 3199 | /* |
| 3200 | * Set the mac to wait the maximum time between each |
| 3201 | * iteration and increase the max iterations when polling the |
| 3202 | * phy; this fixes erroneous timeouts at 10Mbps. |
| 3203 | */ |
| 3204 | ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4)(((0x34) << 5) | ((4) & 0x1F)), 0xFFFF); |
| 3205 | if (ret_val) |
| 3206 | return ret_val; |
| 3207 | ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)), |
| 3208 | ®_data); |
| 3209 | if (ret_val) |
| 3210 | return ret_val; |
| 3211 | reg_data |= 0x3F; |
| 3212 | ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)), |
| 3213 | reg_data); |
| 3214 | if (ret_val) |
| 3215 | return ret_val; |
| 3216 | default: |
| 3217 | break; |
| 3218 | } |
| 3219 | |
| 3220 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
| 3221 | ret_val = em_copper_link_preconfig(hw); |
| 3222 | if (ret_val) |
| 3223 | return ret_val; |
| 3224 | |
| 3225 | switch (hw->mac_type) { |
| 3226 | case em_80003es2lan: |
| 3227 | /* Kumeran registers are written-only */ |
| 3228 | reg_data = |
| 3229 | E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT0x00000500; |
| 3230 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING0x00000010; |
| 3231 | ret_val = em_write_kmrn_reg(hw, |
| 3232 | E1000_KUMCTRLSTA_OFFSET_INB_CTRL0x00000002, reg_data); |
| 3233 | if (ret_val) |
| 3234 | return ret_val; |
| 3235 | break; |
| 3236 | default: |
| 3237 | break; |
| 3238 | } |
| 3239 | |
| 3240 | if (hw->phy_type == em_phy_igp || |
| 3241 | hw->phy_type == em_phy_igp_3 || |
| 3242 | hw->phy_type == em_phy_igp_2) { |
| 3243 | ret_val = em_copper_link_igp_setup(hw); |
| 3244 | if (ret_val) |
| 3245 | return ret_val; |
| 3246 | } else if (hw->phy_type == em_phy_m88 || |
| 3247 | hw->phy_type == em_phy_bm || |
| 3248 | hw->phy_type == em_phy_oem || |
| 3249 | hw->phy_type == em_phy_82578) { |
| 3250 | ret_val = em_copper_link_mgp_setup(hw); |
| 3251 | if (ret_val) |
| 3252 | return ret_val; |
| 3253 | } else if (hw->phy_type == em_phy_gg82563) { |
| 3254 | ret_val = em_copper_link_ggp_setup(hw); |
| 3255 | if (ret_val) |
| 3256 | return ret_val; |
| 3257 | } else if (hw->phy_type == em_phy_82577 || |
| 3258 | hw->phy_type == em_phy_82579 || |
| 3259 | hw->phy_type == em_phy_i217) { |
| 3260 | ret_val = em_copper_link_82577_setup(hw); |
| 3261 | if (ret_val) |
| 3262 | return ret_val; |
| 3263 | } else if (hw->phy_type == em_phy_82580) { |
| 3264 | ret_val = em_copper_link_82580_setup(hw); |
| 3265 | if (ret_val) |
| 3266 | return ret_val; |
| 3267 | } else if (hw->phy_type == em_phy_rtl8211) { |
| 3268 | ret_val = em_copper_link_rtl8211_setup(hw); |
| 3269 | if (ret_val) |
| 3270 | return ret_val; |
| 3271 | } |
| 3272 | if (hw->autoneg) { |
| 3273 | /* |
| 3274 | * Setup autoneg and flow control advertisement and perform |
| 3275 | * autonegotiation |
| 3276 | */ |
| 3277 | ret_val = em_copper_link_autoneg(hw); |
| 3278 | if (ret_val) |
| 3279 | return ret_val; |
| 3280 | } else { |
| 3281 | /* |
| 3282 | * PHY will be set to 10H, 10F, 100H,or 100F depending on |
| 3283 | * value from forced_speed_duplex. |
| 3284 | */ |
| 3285 | DEBUGOUT("Forcing speed and duplex\n"); |
| 3286 | ret_val = em_phy_force_speed_duplex(hw); |
| 3287 | if (ret_val) { |
| 3288 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
| 3289 | return ret_val; |
| 3290 | } |
| 3291 | } |
| 3292 | /* |
| 3293 | * Check link status. Wait up to 100 microseconds for link to become |
| 3294 | * valid. |
| 3295 | */ |
| 3296 | for (i = 0; i < 10; i++) { |
| 3297 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 3298 | if (ret_val) |
| 3299 | return ret_val; |
| 3300 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 3301 | if (ret_val) |
| 3302 | return ret_val; |
| 3303 | |
| 3304 | hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0; |
| 3305 | |
| 3306 | if (phy_data & MII_SR_LINK_STATUS0x0004) { |
| 3307 | /* Config the MAC and PHY after link is up */ |
| 3308 | ret_val = em_copper_link_postconfig(hw); |
| 3309 | if (ret_val) |
| 3310 | return ret_val; |
| 3311 | |
| 3312 | DEBUGOUT("Valid link established!!!\n"); |
| 3313 | return E1000_SUCCESS0; |
| 3314 | } |
| 3315 | usec_delay(10)(*delay_func)(10); |
| 3316 | } |
| 3317 | |
| 3318 | DEBUGOUT("Unable to establish link!!!\n"); |
| 3319 | return E1000_SUCCESS0; |
| 3320 | } |
| 3321 | |
| 3322 | /****************************************************************************** |
| 3323 | * Configure the MAC-to-PHY interface for 10/100Mbps |
| 3324 | * |
| 3325 | * hw - Struct containing variables accessed by shared code |
| 3326 | *****************************************************************************/ |
| 3327 | static int32_t |
| 3328 | em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) |
| 3329 | { |
| 3330 | int32_t ret_val = E1000_SUCCESS0; |
| 3331 | uint32_t tipg; |
| 3332 | uint16_t reg_data; |
| 3333 | DEBUGFUNC("em_configure_kmrn_for_10_100");; |
| 3334 | |
| 3335 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT0x00000004; |
| 3336 | ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010, |
| 3337 | reg_data); |
| 3338 | if (ret_val) |
| 3339 | return ret_val; |
| 3340 | |
| 3341 | /* Configure Transmit Inter-Packet Gap */ |
| 3342 | tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))))); |
| 3343 | tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF; |
| 3344 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_1000x00000009; |
| 3345 | E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))), (tipg))); |
| 3346 | |
| 3347 | ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), ®_data); |
| 3348 | |
| 3349 | if (ret_val) |
| 3350 | return ret_val; |
| 3351 | |
| 3352 | if (duplex == HALF_DUPLEX1) |
| 3353 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER0x0800; |
| 3354 | else |
| 3355 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800; |
| 3356 | |
| 3357 | ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data); |
| 3358 | |
| 3359 | return ret_val; |
| 3360 | } |
| 3361 | |
| 3362 | static int32_t |
| 3363 | em_configure_kmrn_for_1000(struct em_hw *hw) |
| 3364 | { |
| 3365 | int32_t ret_val = E1000_SUCCESS0; |
| 3366 | uint16_t reg_data; |
| 3367 | uint32_t tipg; |
| 3368 | DEBUGFUNC("em_configure_kmrn_for_1000");; |
| 3369 | |
| 3370 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT0x00000000; |
| 3371 | ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010, |
| 3372 | reg_data); |
| 3373 | if (ret_val) |
| 3374 | return ret_val; |
| 3375 | |
| 3376 | /* Configure Transmit Inter-Packet Gap */ |
| 3377 | tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))))); |
| 3378 | tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF; |
| 3379 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008; |
| 3380 | E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register (0x00410))), (tipg))); |
| 3381 | |
| 3382 | ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), ®_data); |
| 3383 | |
| 3384 | if (ret_val) |
| 3385 | return ret_val; |
| 3386 | |
| 3387 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800; |
| 3388 | ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data); |
| 3389 | |
| 3390 | return ret_val; |
| 3391 | } |
| 3392 | |
| 3393 | /****************************************************************************** |
| 3394 | * Configures PHY autoneg and flow control advertisement settings |
| 3395 | * |
| 3396 | * hw - Struct containing variables accessed by shared code |
| 3397 | *****************************************************************************/ |
| 3398 | int32_t |
| 3399 | em_phy_setup_autoneg(struct em_hw *hw) |
| 3400 | { |
| 3401 | int32_t ret_val; |
| 3402 | uint16_t mii_autoneg_adv_reg; |
| 3403 | uint16_t mii_1000t_ctrl_reg; |
| 3404 | DEBUGFUNC("em_phy_setup_autoneg");; |
| 3405 | |
| 3406 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
| 3407 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04, &mii_autoneg_adv_reg); |
| 3408 | if (ret_val) |
| 3409 | return ret_val; |
| 3410 | |
| 3411 | if (hw->phy_type != em_phy_ife) { |
| 3412 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
| 3413 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09, |
| 3414 | &mii_1000t_ctrl_reg); |
| 3415 | if (ret_val) |
| 3416 | return ret_val; |
| 3417 | } else |
| 3418 | mii_1000t_ctrl_reg = 0; |
| 3419 | /* |
| 3420 | * Need to parse both autoneg_advertised and fc and set up the |
| 3421 | * appropriate PHY registers. First we will parse for |
| 3422 | * autoneg_advertised software override. Since we can advertise a |
| 3423 | * plethora of combinations, we need to check each bit individually. |
| 3424 | */ |
| 3425 | /* |
| 3426 | * First we clear all the 10/100 mb speed bits in the Auto-Neg |
| 3427 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 3428 | * the 1000Base-T Control Register (Address 9). |
| 3429 | */ |
| 3430 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK0x01E0; |
| 3431 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK0x0300; |
| 3432 | |
| 3433 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
| 3434 | |
| 3435 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 3436 | if (hw->autoneg_advertised & ADVERTISE_10_HALF0x0001) { |
| 3437 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
| 3438 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS0x0020; |
| 3439 | } |
| 3440 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 3441 | if (hw->autoneg_advertised & ADVERTISE_10_FULL0x0002) { |
| 3442 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
| 3443 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS0x0040; |
| 3444 | } |
| 3445 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 3446 | if (hw->autoneg_advertised & ADVERTISE_100_HALF0x0004) { |
| 3447 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
| 3448 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS0x0080; |
| 3449 | } |
| 3450 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 3451 | if (hw->autoneg_advertised & ADVERTISE_100_FULL0x0008) { |
| 3452 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
| 3453 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS0x0100; |
| 3454 | } |
| 3455 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 3456 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF0x0010) { |
| 3457 | DEBUGOUT("Advertise 1000mb Half duplex requested, request" |
| 3458 | " denied!\n"); |
| 3459 | } |
| 3460 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 3461 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL0x0020) { |
| 3462 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
| 3463 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS0x0200; |
| 3464 | if (hw->phy_type == em_phy_ife) { |
| 3465 | DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" |
| 3466 | " not supported.\n"); |
| 3467 | } |
| 3468 | } |
| 3469 | /* |
| 3470 | * Check for a software override of the flow control settings, and |
| 3471 | * setup the PHY advertisement registers accordingly. If |
| 3472 | * auto-negotiation is enabled, then software will have to set the |
| 3473 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
| 3474 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start |
| 3475 | * auto-negotiation. |
| 3476 | * |
| 3477 | * The possible values of the "fc" parameter are: 0: Flow control is |
| 3478 | * completely disabled 1: Rx flow control is enabled (we can receive |
| 3479 | * pause frames but not send pause frames). 2: Tx flow control is |
| 3480 | * enabled (we can send pause frames but we do not support receiving |
| 3481 | * pause frames). 3: Both Rx and TX flow control (symmetric) are |
| 3482 | * enabled. other: No software override. The flow control |
| 3483 | * configuration in the EEPROM is used. |
| 3484 | */ |
| 3485 | switch (hw->fc) { |
| 3486 | case E1000_FC_NONE0: /* 0 */ |
| 3487 | /* |
| 3488 | * Flow control (RX & TX) is completely disabled by a |
| 3489 | * software over-ride. |
| 3490 | */ |
| 3491 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400); |
| 3492 | break; |
| 3493 | case E1000_FC_RX_PAUSE1:/* 1 */ |
| 3494 | /* |
| 3495 | * RX Flow control is enabled, and TX Flow control is |
| 3496 | * disabled, by a software over-ride. |
| 3497 | */ |
| 3498 | /* |
| 3499 | * Since there really isn't a way to advertise that we are |
| 3500 | * capable of RX Pause ONLY, we will advertise that we |
| 3501 | * support both symmetric and asymmetric RX PAUSE. Later (in |
| 3502 | * em_config_fc_after_link_up) we will disable the hw's |
| 3503 | * ability to send PAUSE frames. |
| 3504 | */ |
| 3505 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400); |
| 3506 | break; |
| 3507 | case E1000_FC_TX_PAUSE2:/* 2 */ |
| 3508 | /* |
| 3509 | * TX Flow control is enabled, and RX Flow control is |
| 3510 | * disabled, by a software over-ride. |
| 3511 | */ |
| 3512 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR0x0800; |
| 3513 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE0x0400; |
| 3514 | break; |
| 3515 | case E1000_FC_FULL3: /* 3 */ |
| 3516 | /* |
| 3517 | * Flow control (both RX and TX) is enabled by a software |
| 3518 | * over-ride. |
| 3519 | */ |
| 3520 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400); |
| 3521 | break; |
| 3522 | default: |
| 3523 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 3524 | return -E1000_ERR_CONFIG3; |
| 3525 | } |
| 3526 | |
| 3527 | ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV0x04, mii_autoneg_adv_reg); |
| 3528 | if (ret_val) |
| 3529 | return ret_val; |
| 3530 | |
| 3531 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
| 3532 | |
| 3533 | if (hw->phy_type != em_phy_ife) { |
| 3534 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09, |
| 3535 | mii_1000t_ctrl_reg); |
| 3536 | if (ret_val) |
| 3537 | return ret_val; |
| 3538 | } |
| 3539 | return E1000_SUCCESS0; |
| 3540 | } |
| 3541 | /****************************************************************************** |
| 3542 | * Force PHY speed and duplex settings to hw->forced_speed_duplex |
| 3543 | * |
| 3544 | * hw - Struct containing variables accessed by shared code |
| 3545 | *****************************************************************************/ |
| 3546 | static int32_t |
| 3547 | em_phy_force_speed_duplex(struct em_hw *hw) |
| 3548 | { |
| 3549 | uint32_t ctrl; |
| 3550 | int32_t ret_val; |
| 3551 | uint16_t mii_ctrl_reg; |
| 3552 | uint16_t mii_status_reg; |
| 3553 | uint16_t phy_data; |
| 3554 | uint16_t i; |
| 3555 | DEBUGFUNC("em_phy_force_speed_duplex");; |
| 3556 | |
| 3557 | /* Turn off Flow control if we are forcing speed and duplex. */ |
| 3558 | hw->fc = E1000_FC_NONE0; |
| 3559 | |
| 3560 | DEBUGOUT1("hw->fc = %d\n", hw->fc); |
| 3561 | |
| 3562 | /* Read the Device Control Register. */ |
| 3563 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 3564 | |
| 3565 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
| 3566 | ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000); |
| 3567 | ctrl &= ~(DEVICE_SPEED_MASK0x00000300); |
| 3568 | |
| 3569 | /* Clear the Auto Speed Detect Enable bit. */ |
| 3570 | ctrl &= ~E1000_CTRL_ASDE0x00000020; |
| 3571 | |
| 3572 | /* Read the MII Control Register. */ |
| 3573 | ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &mii_ctrl_reg); |
| 3574 | if (ret_val) |
| 3575 | return ret_val; |
| 3576 | |
| 3577 | /* We need to disable autoneg in order to force link and duplex. */ |
| 3578 | |
| 3579 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN0x1000; |
| 3580 | |
| 3581 | /* Are we forcing Full or Half Duplex? */ |
| 3582 | if (hw->forced_speed_duplex == em_100_full || |
| 3583 | hw->forced_speed_duplex == em_10_full) { |
| 3584 | /* |
| 3585 | * We want to force full duplex so we SET the full duplex |
| 3586 | * bits in the Device and MII Control Registers. |
| 3587 | */ |
| 3588 | ctrl |= E1000_CTRL_FD0x00000001; |
| 3589 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX0x0100; |
| 3590 | DEBUGOUT("Full Duplex\n"); |
| 3591 | } else { |
| 3592 | /* |
| 3593 | * We want to force half duplex so we CLEAR the full duplex |
| 3594 | * bits in the Device and MII Control Registers. |
| 3595 | */ |
| 3596 | ctrl &= ~E1000_CTRL_FD0x00000001; |
| 3597 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX0x0100; |
| 3598 | DEBUGOUT("Half Duplex\n"); |
| 3599 | } |
| 3600 | |
| 3601 | /* Are we forcing 100Mbps??? */ |
| 3602 | if (hw->forced_speed_duplex == em_100_full || |
| 3603 | hw->forced_speed_duplex == em_100_half) { |
| 3604 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
| 3605 | ctrl |= E1000_CTRL_SPD_1000x00000100; |
| 3606 | mii_ctrl_reg |= MII_CR_SPEED_1000x2000; |
| 3607 | mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_100x0000); |
| 3608 | DEBUGOUT("Forcing 100mb "); |
| 3609 | } else { |
| 3610 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
| 3611 | ctrl &= ~(E1000_CTRL_SPD_10000x00000200 | E1000_CTRL_SPD_1000x00000100); |
| 3612 | mii_ctrl_reg |= MII_CR_SPEED_100x0000; |
| 3613 | mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_1000x2000); |
| 3614 | DEBUGOUT("Forcing 10mb "); |
| 3615 | } |
| 3616 | |
| 3617 | em_config_collision_dist(hw); |
| 3618 | |
| 3619 | /* Write the configured values back to the Device Control Reg. */ |
| 3620 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 3621 | |
| 3622 | if ((hw->phy_type == em_phy_m88) || |
| 3623 | (hw->phy_type == em_phy_gg82563) || |
| 3624 | (hw->phy_type == em_phy_bm) || |
| 3625 | (hw->phy_type == em_phy_oem || |
| 3626 | (hw->phy_type == em_phy_82578))) { |
| 3627 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 3628 | &phy_data); |
| 3629 | if (ret_val) |
| 3630 | return ret_val; |
| 3631 | /* |
| 3632 | * Clear Auto-Crossover to force MDI manually. M88E1000 |
| 3633 | * requires MDI forced whenever speed are duplex are forced. |
| 3634 | */ |
| 3635 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060; |
| 3636 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 3637 | phy_data); |
| 3638 | if (ret_val) |
| 3639 | return ret_val; |
| 3640 | |
| 3641 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
| 3642 | |
| 3643 | /* Need to reset the PHY or these changes will be ignored */ |
| 3644 | mii_ctrl_reg |= MII_CR_RESET0x8000; |
| 3645 | |
| 3646 | } |
| 3647 | else if (hw->phy_type == em_phy_rtl8211) { |
| 3648 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data); |
| 3649 | if(ret_val) { |
| 3650 | printf("Unable to read RGEPHY_CR register\n" |
| 3651 | ); |
| 3652 | return ret_val; |
| 3653 | } |
| 3654 | |
| 3655 | /* |
| 3656 | * Clear Auto-Crossover to force MDI manually. RTL8211 requires |
| 3657 | * MDI forced whenever speed are duplex are forced. |
| 3658 | */ |
| 3659 | |
| 3660 | phy_data |= RGEPHY_CR_MDI_MASK0x0060; // enable MDIX |
| 3661 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data); |
| 3662 | if(ret_val) { |
| 3663 | printf("Unable to write RGEPHY_CR register\n"); |
| 3664 | return ret_val; |
| 3665 | } |
| 3666 | mii_ctrl_reg |= MII_CR_RESET0x8000; |
| 3667 | |
| 3668 | } |
| 3669 | /* Disable MDI-X support for 10/100 */ |
| 3670 | else if (hw->phy_type == em_phy_ife) { |
| 3671 | ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, &phy_data); |
| 3672 | if (ret_val) |
| 3673 | return ret_val; |
| 3674 | |
| 3675 | phy_data &= ~IFE_PMC_AUTO_MDIX0x0080; |
| 3676 | phy_data &= ~IFE_PMC_FORCE_MDIX0x0040; |
| 3677 | |
| 3678 | ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, phy_data); |
| 3679 | if (ret_val) |
| 3680 | return ret_val; |
| 3681 | } else { |
| 3682 | /* |
| 3683 | * Clear Auto-Crossover to force MDI manually. IGP requires |
| 3684 | * MDI forced whenever speed or duplex are forced. |
| 3685 | */ |
| 3686 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, |
| 3687 | &phy_data); |
| 3688 | if (ret_val) |
| 3689 | return ret_val; |
| 3690 | |
| 3691 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000; |
| 3692 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000; |
| 3693 | |
| 3694 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, |
| 3695 | phy_data); |
| 3696 | if (ret_val) |
| 3697 | return ret_val; |
| 3698 | } |
| 3699 | |
| 3700 | /* Write back the modified PHY MII control register. */ |
| 3701 | ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, mii_ctrl_reg); |
| 3702 | if (ret_val) |
| 3703 | return ret_val; |
| 3704 | |
| 3705 | usec_delay(1)(*delay_func)(1); |
| 3706 | /* |
| 3707 | * The wait_autoneg_complete flag may be a little misleading here. |
| 3708 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
| 3709 | * But we do want to delay for a period while forcing only so we |
| 3710 | * don't generate false No Link messages. So we will wait here only |
| 3711 | * if the user has set wait_autoneg_complete to 1, which is the |
| 3712 | * default. |
| 3713 | */ |
| 3714 | if (hw->wait_autoneg_complete) { |
| 3715 | /* We will wait for autoneg to complete. */ |
| 3716 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
| 3717 | mii_status_reg = 0; |
| 3718 | /* |
| 3719 | * We will wait for autoneg to complete or 4.5 seconds to |
| 3720 | * expire. |
| 3721 | */ |
| 3722 | for (i = PHY_FORCE_TIME20; i > 0; i--) { |
| 3723 | /* |
| 3724 | * Read the MII Status Register and wait for Auto-Neg |
| 3725 | * Complete bit to be set. |
| 3726 | */ |
| 3727 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, |
| 3728 | &mii_status_reg); |
| 3729 | if (ret_val) |
| 3730 | return ret_val; |
| 3731 | |
| 3732 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, |
| 3733 | &mii_status_reg); |
| 3734 | if (ret_val) |
| 3735 | return ret_val; |
| 3736 | |
| 3737 | if (mii_status_reg & MII_SR_LINK_STATUS0x0004) |
| 3738 | break; |
| 3739 | msec_delay(100)(*delay_func)(1000*(100)); |
| 3740 | } |
| 3741 | if ((i == 0) && |
| 3742 | ((hw->phy_type == em_phy_m88) || |
| 3743 | (hw->phy_type == em_phy_gg82563) || |
| 3744 | (hw->phy_type == em_phy_bm))) { |
| 3745 | /* |
| 3746 | * We didn't get link. Reset the DSP and wait again |
| 3747 | * for link. |
| 3748 | */ |
| 3749 | ret_val = em_phy_reset_dsp(hw); |
| 3750 | if (ret_val) { |
| 3751 | DEBUGOUT("Error Resetting PHY DSP\n"); |
| 3752 | return ret_val; |
| 3753 | } |
| 3754 | } |
| 3755 | /* |
| 3756 | * This loop will early-out if the link condition has been |
| 3757 | * met. |
| 3758 | */ |
| 3759 | for (i = PHY_FORCE_TIME20; i > 0; i--) { |
| 3760 | if (mii_status_reg & MII_SR_LINK_STATUS0x0004) |
| 3761 | break; |
| 3762 | msec_delay(100)(*delay_func)(1000*(100)); |
| 3763 | /* |
| 3764 | * Read the MII Status Register and wait for Auto-Neg |
| 3765 | * Complete bit to be set. |
| 3766 | */ |
| 3767 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, |
| 3768 | &mii_status_reg); |
| 3769 | if (ret_val) |
| 3770 | return ret_val; |
| 3771 | |
| 3772 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, |
| 3773 | &mii_status_reg); |
| 3774 | if (ret_val) |
| 3775 | return ret_val; |
| 3776 | } |
| 3777 | } |
| 3778 | if (hw->phy_type == em_phy_m88 || |
| 3779 | hw->phy_type == em_phy_bm || |
| 3780 | hw->phy_type == em_phy_oem) { |
| 3781 | /* |
| 3782 | * Because we reset the PHY above, we need to re-force TX_CLK |
| 3783 | * in the Extended PHY Specific Control Register to 25MHz |
| 3784 | * clock. This value defaults back to a 2.5MHz clock when |
| 3785 | * the PHY is reset. |
| 3786 | */ |
| 3787 | ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14, |
| 3788 | &phy_data); |
| 3789 | if (ret_val) |
| 3790 | return ret_val; |
| 3791 | |
| 3792 | phy_data |= M88E1000_EPSCR_TX_CLK_250x0070; |
| 3793 | ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14, |
| 3794 | phy_data); |
| 3795 | if (ret_val) |
| 3796 | return ret_val; |
| 3797 | /* |
| 3798 | * In addition, because of the s/w reset above, we need to |
| 3799 | * enable CRS on TX. This must be set for both full and half |
| 3800 | * duplex operation. |
| 3801 | */ |
| 3802 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 3803 | &phy_data); |
| 3804 | if (ret_val) |
| 3805 | return ret_val; |
| 3806 | |
| 3807 | if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0) |
| 3808 | phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800; |
| 3809 | else |
| 3810 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800; |
| 3811 | |
| 3812 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, |
| 3813 | phy_data); |
| 3814 | if (ret_val) |
| 3815 | return ret_val; |
| 3816 | |
| 3817 | if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && |
| 3818 | (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || |
| 3819 | hw->forced_speed_duplex == em_10_half)) { |
| 3820 | ret_val = em_polarity_reversal_workaround(hw); |
| 3821 | if (ret_val) |
| 3822 | return ret_val; |
| 3823 | } |
| 3824 | } else if (hw->phy_type == em_phy_rtl8211) { |
| 3825 | /* |
| 3826 | * In addition, because of the s/w reset above, we need to enable |
| 3827 | * CRX on TX. This must be set for both full and half duplex |
| 3828 | * operation. |
| 3829 | */ |
| 3830 | |
| 3831 | ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data); |
| 3832 | if(ret_val) { |
| 3833 | printf("Unable to read RGEPHY_CR register\n"); |
| 3834 | return ret_val; |
| 3835 | } |
| 3836 | |
| 3837 | phy_data &= ~RGEPHY_CR_ASSERT_CRS0x0800; |
| 3838 | ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data); |
| 3839 | if(ret_val) { |
| 3840 | printf("Unable to write RGEPHY_CR register\n"); |
| 3841 | return ret_val; |
| 3842 | } |
| 3843 | } else if (hw->phy_type == em_phy_gg82563) { |
| 3844 | /* |
| 3845 | * The TX_CLK of the Extended PHY Specific Control Register |
| 3846 | * defaults to 2.5MHz on a reset. We need to re-force it |
| 3847 | * back to 25MHz, if we're not in a forced 10/duplex |
| 3848 | * configuration. |
| 3849 | */ |
| 3850 | ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)), |
| 3851 | &phy_data); |
| 3852 | if (ret_val) |
| 3853 | return ret_val; |
| 3854 | |
| 3855 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK0x0007; |
| 3856 | if ((hw->forced_speed_duplex == em_10_full) || |
| 3857 | (hw->forced_speed_duplex == em_10_half)) |
| 3858 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ0x0004; |
| 3859 | else |
| 3860 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ0x0005; |
| 3861 | |
| 3862 | /* Also due to the reset, we need to enable CRS on Tx. */ |
| 3863 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010; |
| 3864 | |
| 3865 | ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)), |
| 3866 | phy_data); |
| 3867 | if (ret_val) |
| 3868 | return ret_val; |
| 3869 | } |
| 3870 | return E1000_SUCCESS0; |
| 3871 | } |
| 3872 | |
| 3873 | /****************************************************************************** |
| 3874 | * Sets the collision distance in the Transmit Control register |
| 3875 | * |
| 3876 | * hw - Struct containing variables accessed by shared code |
| 3877 | * |
| 3878 | * Link should have been established previously. Reads the speed and duplex |
| 3879 | * information from the Device Status register. |
| 3880 | *****************************************************************************/ |
| 3881 | void |
| 3882 | em_config_collision_dist(struct em_hw *hw) |
| 3883 | { |
| 3884 | uint32_t tctl, coll_dist; |
| 3885 | DEBUGFUNC("em_config_collision_dist");; |
| 3886 | |
| 3887 | if (hw->mac_type < em_82543) |
| 3888 | coll_dist = E1000_COLLISION_DISTANCE_8254264; |
| 3889 | else |
| 3890 | coll_dist = E1000_COLLISION_DISTANCE63; |
| 3891 | |
| 3892 | tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))))); |
| 3893 | |
| 3894 | tctl &= ~E1000_TCTL_COLD0x003ff000; |
| 3895 | tctl |= coll_dist << E1000_COLD_SHIFT12; |
| 3896 | |
| 3897 | E1000_WRITE_REG(hw, TCTL, tctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register (0x00400))), (tctl))); |
| 3898 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 3899 | } |
| 3900 | |
| 3901 | /****************************************************************************** |
| 3902 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
| 3903 | * |
| 3904 | * hw - Struct containing variables accessed by shared code |
| 3905 | * mii_reg - data to write to the MII control register |
| 3906 | * |
| 3907 | * The contents of the PHY register containing the needed information need to |
| 3908 | * be passed in. |
| 3909 | *****************************************************************************/ |
| 3910 | static int32_t |
| 3911 | em_config_mac_to_phy(struct em_hw *hw) |
| 3912 | { |
| 3913 | uint32_t ctrl; |
| 3914 | int32_t ret_val; |
| 3915 | uint16_t phy_data; |
| 3916 | DEBUGFUNC("em_config_mac_to_phy");; |
| 3917 | /* |
| 3918 | * 82544 or newer MAC, Auto Speed Detection takes care of MAC |
| 3919 | * speed/duplex configuration. |
| 3920 | */ |
| 3921 | if (hw->mac_type >= em_82544 |
| 3922 | && hw->mac_type != em_icp_xxxx) |
| 3923 | return E1000_SUCCESS0; |
| 3924 | /* |
| 3925 | * Read the Device Control Register and set the bits to Force Speed |
| 3926 | * and Duplex. |
| 3927 | */ |
| 3928 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 3929 | ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000); |
| 3930 | ctrl &= ~(E1000_CTRL_SPD_SEL0x00000300 | E1000_CTRL_ILOS0x00000080); |
| 3931 | /* |
| 3932 | * Set up duplex in the Device Control and Transmit Control registers |
| 3933 | * depending on negotiated values. |
| 3934 | */ |
| 3935 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS0x11, &phy_data); |
| 3936 | if (ret_val) |
| 3937 | return ret_val; |
| 3938 | |
| 3939 | if (phy_data & M88E1000_PSSR_DPLX0x2000) |
| 3940 | ctrl |= E1000_CTRL_FD0x00000001; |
| 3941 | else |
| 3942 | ctrl &= ~E1000_CTRL_FD0x00000001; |
| 3943 | |
| 3944 | em_config_collision_dist(hw); |
| 3945 | /* |
| 3946 | * Set up speed in the Device Control register depending on |
| 3947 | * negotiated values. |
| 3948 | */ |
| 3949 | if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_1000MBS0x8000) |
| 3950 | ctrl |= E1000_CTRL_SPD_10000x00000200; |
| 3951 | else if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_100MBS0x4000) |
| 3952 | ctrl |= E1000_CTRL_SPD_1000x00000100; |
| 3953 | |
| 3954 | /* Write the configured values back to the Device Control Reg. */ |
| 3955 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 3956 | return E1000_SUCCESS0; |
| 3957 | } |
| 3958 | |
| 3959 | /****************************************************************************** |
| 3960 | * Forces the MAC's flow control settings. |
| 3961 | * |
| 3962 | * hw - Struct containing variables accessed by shared code |
| 3963 | * |
| 3964 | * Sets the TFCE and RFCE bits in the device control register to reflect |
| 3965 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
| 3966 | * software when a Copper PHY is used because autonegotiation is managed |
| 3967 | * by the PHY rather than the MAC. Software must also configure these |
| 3968 | * bits when link is forced on a fiber connection. |
| 3969 | *****************************************************************************/ |
| 3970 | int32_t |
| 3971 | em_force_mac_fc(struct em_hw *hw) |
| 3972 | { |
| 3973 | uint32_t ctrl; |
| 3974 | DEBUGFUNC("em_force_mac_fc");; |
| 3975 | |
| 3976 | /* Get the current configuration of the Device Control Register */ |
| 3977 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 3978 | /* |
| 3979 | * Because we didn't get link via the internal auto-negotiation |
| 3980 | * mechanism (we either forced link or we got link via PHY auto-neg), |
| 3981 | * we have to manually enable/disable transmit an receive flow |
| 3982 | * control. |
| 3983 | * |
| 3984 | * The "Case" statement below enables/disable flow control according to |
| 3985 | * the "hw->fc" parameter. |
| 3986 | * |
| 3987 | * The possible values of the "fc" parameter are: 0: Flow control is |
| 3988 | * completely disabled 1: Rx flow control is enabled (we can receive |
| 3989 | * pause frames but not send pause frames). 2: Tx flow control is |
| 3990 | * enabled (we can send pause frames but we do not receive |
| 3991 | * pause frames). 3: Both Rx and TX flow control (symmetric) is |
| 3992 | * enabled. other: No other values should be possible at this point. |
| 3993 | */ |
| 3994 | |
| 3995 | switch (hw->fc) { |
| 3996 | case E1000_FC_NONE0: |
| 3997 | ctrl &= (~(E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000)); |
| 3998 | break; |
| 3999 | case E1000_FC_RX_PAUSE1: |
| 4000 | ctrl &= (~E1000_CTRL_TFCE0x10000000); |
| 4001 | ctrl |= E1000_CTRL_RFCE0x08000000; |
| 4002 | break; |
| 4003 | case E1000_FC_TX_PAUSE2: |
| 4004 | ctrl &= (~E1000_CTRL_RFCE0x08000000); |
| 4005 | ctrl |= E1000_CTRL_TFCE0x10000000; |
| 4006 | break; |
| 4007 | case E1000_FC_FULL3: |
| 4008 | ctrl |= (E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000); |
| 4009 | break; |
| 4010 | default: |
| 4011 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 4012 | return -E1000_ERR_CONFIG3; |
| 4013 | } |
| 4014 | |
| 4015 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
| 4016 | if (hw->mac_type == em_82542_rev2_0) |
| 4017 | ctrl &= (~E1000_CTRL_TFCE0x10000000); |
| 4018 | |
| 4019 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 4020 | return E1000_SUCCESS0; |
| 4021 | } |
| 4022 | /****************************************************************************** |
| 4023 | * Configures flow control settings after link is established |
| 4024 | * |
| 4025 | * hw - Struct containing variables accessed by shared code |
| 4026 | * |
| 4027 | * Should be called immediately after a valid link has been established. |
| 4028 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
| 4029 | * and autonegotiation is enabled, the MAC flow control settings will be set |
| 4030 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
| 4031 | * and RFCE bits will be automatically set to the negotiated flow control mode. |
| 4032 | *****************************************************************************/ |
| 4033 | STATIC int32_t |
| 4034 | em_config_fc_after_link_up(struct em_hw *hw) |
| 4035 | { |
| 4036 | int32_t ret_val; |
| 4037 | uint16_t mii_status_reg; |
| 4038 | uint16_t mii_nway_adv_reg; |
| 4039 | uint16_t mii_nway_lp_ability_reg; |
| 4040 | uint16_t speed; |
| 4041 | uint16_t duplex; |
| 4042 | DEBUGFUNC("em_config_fc_after_link_up");; |
| 4043 | /* |
| 4044 | * Check for the case where we have fiber media and auto-neg failed |
| 4045 | * so we had to force link. In this case, we need to force the |
| 4046 | * configuration of the MAC to match the "fc" parameter. |
| 4047 | */ |
| 4048 | if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) |
| 4049 | || ((hw->media_type == em_media_type_internal_serdes) && |
| 4050 | (hw->autoneg_failed)) || |
| 4051 | ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || |
| 4052 | ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { |
| 4053 | ret_val = em_force_mac_fc(hw); |
| 4054 | if (ret_val) { |
| 4055 | DEBUGOUT("Error forcing flow control settings\n"); |
| 4056 | return ret_val; |
| 4057 | } |
| 4058 | } |
| 4059 | /* |
| 4060 | * Check for the case where we have copper media and auto-neg is |
| 4061 | * enabled. In this case, we need to check and see if Auto-Neg has |
| 4062 | * completed, and if so, how the PHY and link partner has flow |
| 4063 | * control configured. |
| 4064 | */ |
| 4065 | if ((hw->media_type == em_media_type_copper || |
| 4066 | (hw->media_type == em_media_type_oem)) && |
| 4067 | hw->autoneg) { |
| 4068 | /* |
| 4069 | * Read the MII Status Register and check to see if AutoNeg |
| 4070 | * has completed. We read this twice because this reg has |
| 4071 | * some "sticky" (latched) bits. |
| 4072 | */ |
| 4073 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg); |
| 4074 | if (ret_val) |
| 4075 | return ret_val; |
| 4076 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg); |
| 4077 | if (ret_val) |
| 4078 | return ret_val; |
| 4079 | |
| 4080 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE0x0020) { |
| 4081 | /* |
| 4082 | * The AutoNeg process has completed, so we now need |
| 4083 | * to read both the Auto Negotiation Advertisement |
| 4084 | * Register (Address 4) and the Auto_Negotiation Base |
| 4085 | * Page Ability Register (Address 5) to determine how |
| 4086 | * flow control was negotiated. |
| 4087 | */ |
| 4088 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04, |
| 4089 | &mii_nway_adv_reg); |
| 4090 | if (ret_val) |
| 4091 | return ret_val; |
| 4092 | ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05, |
| 4093 | &mii_nway_lp_ability_reg); |
| 4094 | if (ret_val) |
| 4095 | return ret_val; |
| 4096 | /* |
| 4097 | * Two bits in the Auto Negotiation Advertisement |
| 4098 | * Register (Address 4) and two bits in the Auto |
| 4099 | * Negotiation Base Page Ability Register (Address 5) |
| 4100 | * determine flow control for both the PHY and the |
| 4101 | * link partner. The following table, taken out of |
| 4102 | * the IEEE 802.3ab/D6.0 dated March 25, 1999, |
| 4103 | * describes these PAUSE resolution bits and how flow |
| 4104 | * control is determined based upon these settings. |
| 4105 | * NOTE: DC = Don't Care |
| 4106 | * |
| 4107 | * LOCAL DEVICE | LINK PARTNER | |
| 4108 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 4109 | * -------|---------|-------|---------|--------------- |
| 4110 | * 0 | 0 | DC | DC | em_fc_none |
| 4111 | * 0 | 1 | 0 | DC | em_fc_none |
| 4112 | * 0 | 1 | 1 | 0 | em_fc_none |
| 4113 | * 0 | 1 | 1 | 1 | em_fc_tx_pause |
| 4114 | * 1 | 0 | 0 | DC | em_fc_none |
| 4115 | * 1 | DC | 1 | DC | em_fc_full |
| 4116 | * 1 | 1 | 0 | 0 | em_fc_none |
| 4117 | * 1 | 1 | 0 | 1 | em_fc_rx_pause |
| 4118 | * |
| 4119 | */ |
| 4120 | /* |
| 4121 | * Are both PAUSE bits set to 1? If so, this implies |
| 4122 | * Symmetric Flow Control is enabled at both ends. |
| 4123 | * The ASM_DIR bits are irrelevant per the spec. |
| 4124 | * |
| 4125 | * For Symmetric Flow Control: |
| 4126 | * |
| 4127 | * LOCAL DEVICE | LINK PARTNER |
| 4128 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 4129 | * -------|---------|-------|---------|--------------- |
| 4130 | * 1 | DC | 1 | DC | em_fc_full |
| 4131 | * |
| 4132 | */ |
| 4133 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) && |
| 4134 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400)) { |
| 4135 | /* |
| 4136 | * Now we need to check if the user selected |
| 4137 | * RX ONLY of pause frames. In this case, we |
| 4138 | * had to advertise FULL flow control because |
| 4139 | * we could not advertise RX ONLY. Hence, we |
| 4140 | * must now check to see if we need to turn |
| 4141 | * OFF the TRANSMISSION of PAUSE frames. |
| 4142 | */ |
| 4143 | if (hw->original_fc == E1000_FC_FULL3) { |
| 4144 | hw->fc = E1000_FC_FULL3; |
| 4145 | DEBUGOUT("Flow Control = FULL.\n"); |
| 4146 | } else { |
| 4147 | hw->fc = E1000_FC_RX_PAUSE1; |
| 4148 | DEBUGOUT("Flow Control = RX PAUSE" |
| 4149 | " frames only.\n"); |
| 4150 | } |
| 4151 | } |
| 4152 | /* |
| 4153 | * For receiving PAUSE frames ONLY. |
| 4154 | * |
| 4155 | * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | |
| 4156 | * PAUSE | ASM_DIR | Result |
| 4157 | * -------|---------|-------|---------|--------------- |
| 4158 | * ----- 0 | 1 | 1 | 1 | |
| 4159 | * em_fc_tx_pause |
| 4160 | * |
| 4161 | */ |
| 4162 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) && |
| 4163 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) && |
| 4164 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) && |
| 4165 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) { |
| 4166 | hw->fc = E1000_FC_TX_PAUSE2; |
| 4167 | DEBUGOUT("Flow Control = TX PAUSE frames only." |
| 4168 | "\n"); |
| 4169 | } |
| 4170 | /* |
| 4171 | * For transmitting PAUSE frames ONLY. |
| 4172 | * |
| 4173 | * LOCAL DEVICE | LINK PARTNER |
| 4174 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 4175 | * -------|---------|-------|---------|--------------- |
| 4176 | * 1 | 1 | 0 | 1 | em_fc_rx_pause |
| 4177 | * |
| 4178 | */ |
| 4179 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) && |
| 4180 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) && |
| 4181 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) && |
| 4182 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) { |
| 4183 | hw->fc = E1000_FC_RX_PAUSE1; |
| 4184 | DEBUGOUT("Flow Control = RX PAUSE frames only." |
| 4185 | "\n"); |
| 4186 | } |
| 4187 | /* |
| 4188 | * Per the IEEE spec, at this point flow control |
| 4189 | * should be disabled. However, we want to consider |
| 4190 | * that we could be connected to a legacy switch that |
| 4191 | * doesn't advertise desired flow control, but can be |
| 4192 | * forced on the link partner. So if we advertised |
| 4193 | * no flow control, that is what we will resolve to. |
| 4194 | * If we advertised some kind of receive capability |
| 4195 | * (Rx Pause Only or Full Flow Control) and the link |
| 4196 | * partner advertised none, we will configure |
| 4197 | * ourselves to enable Rx Flow Control only. We can |
| 4198 | * do this safely for two reasons: If the link |
| 4199 | * partner really didn't want flow control enabled, |
| 4200 | * and we enable Rx, no harm done since we won't be |
| 4201 | * receiving any PAUSE frames anyway. If the intent |
| 4202 | * on the link partner was to have flow control |
| 4203 | * enabled, then by us enabling RX only, we can at |
| 4204 | * least receive pause frames and process them. This |
| 4205 | * is a good idea because in most cases, since we are |
| 4206 | * predominantly a server NIC, more times than not we |
| 4207 | * will be asked to delay transmission of packets |
| 4208 | * than asking our link partner to pause transmission |
| 4209 | * of frames. |
| 4210 | */ |
| 4211 | else if ((hw->original_fc == E1000_FC_NONE0 || |
| 4212 | hw->original_fc == E1000_FC_TX_PAUSE2) || |
| 4213 | hw->fc_strict_ieee) { |
| 4214 | hw->fc = E1000_FC_NONE0; |
| 4215 | DEBUGOUT("Flow Control = NONE.\n"); |
| 4216 | } else { |
| 4217 | hw->fc = E1000_FC_RX_PAUSE1; |
| 4218 | DEBUGOUT("Flow Control = RX PAUSE frames only." |
| 4219 | "\n"); |
| 4220 | } |
| 4221 | /* |
| 4222 | * Now we need to do one last check... If we auto- |
| 4223 | * negotiated to HALF DUPLEX, flow control should not |
| 4224 | * be enabled per IEEE 802.3 spec. |
| 4225 | */ |
| 4226 | ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); |
| 4227 | if (ret_val) { |
| 4228 | DEBUGOUT("Error getting link speed and duplex" |
| 4229 | "\n"); |
| 4230 | return ret_val; |
| 4231 | } |
| 4232 | if (duplex == HALF_DUPLEX1) |
| 4233 | hw->fc = E1000_FC_NONE0; |
| 4234 | /* |
| 4235 | * Now we call a subroutine to actually force the MAC |
| 4236 | * controller to use the correct flow control |
| 4237 | * settings. |
| 4238 | */ |
| 4239 | ret_val = em_force_mac_fc(hw); |
| 4240 | if (ret_val) { |
| 4241 | DEBUGOUT("Error forcing flow control settings" |
| 4242 | "\n"); |
| 4243 | return ret_val; |
| 4244 | } |
| 4245 | } else { |
| 4246 | DEBUGOUT("Copper PHY and Auto Neg has not completed." |
| 4247 | "\n"); |
| 4248 | } |
| 4249 | } |
| 4250 | return E1000_SUCCESS0; |
| 4251 | } |
| 4252 | /****************************************************************************** |
| 4253 | * Checks to see if the link status of the hardware has changed. |
| 4254 | * |
| 4255 | * hw - Struct containing variables accessed by shared code |
| 4256 | * |
| 4257 | * Called by any function that needs to check the link status of the adapter. |
| 4258 | *****************************************************************************/ |
| 4259 | int32_t |
| 4260 | em_check_for_link(struct em_hw *hw) |
| 4261 | { |
| 4262 | uint32_t rxcw = 0; |
| 4263 | uint32_t ctrl; |
| 4264 | uint32_t status; |
| 4265 | uint32_t rctl; |
| 4266 | uint32_t icr; |
| 4267 | uint32_t signal = 0; |
| 4268 | int32_t ret_val; |
| 4269 | uint16_t phy_data; |
| 4270 | DEBUGFUNC("em_check_for_link");; |
| 4271 | uint16_t speed, duplex; |
| 4272 | |
| 4273 | if (hw->mac_type >= em_82575 && |
| 4274 | hw->media_type != em_media_type_copper) { |
| 4275 | ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, |
| 4276 | &duplex); |
| 4277 | hw->get_link_status = hw->serdes_link_down; |
| 4278 | |
| 4279 | return (ret_val); |
| 4280 | } |
| 4281 | |
| 4282 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 4283 | status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4284 | /* |
| 4285 | * On adapters with a MAC newer than 82544, SW Defineable pin 1 will |
| 4286 | * be set when the optics detect a signal. On older adapters, it will |
| 4287 | * be cleared when there is a signal. This applies to fiber media |
| 4288 | * only. |
| 4289 | */ |
| 4290 | if ((hw->media_type == em_media_type_fiber) || |
| 4291 | (hw->media_type == em_media_type_internal_serdes)) { |
| 4292 | rxcw = E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register (0x00180))))); |
| 4293 | |
| 4294 | if (hw->media_type == em_media_type_fiber) { |
| 4295 | signal = (hw->mac_type > em_82544) ? |
| 4296 | E1000_CTRL_SWDPIN10x00080000 : 0; |
| 4297 | if (status & E1000_STATUS_LU0x00000002) |
| 4298 | hw->get_link_status = FALSE0; |
| 4299 | } |
| 4300 | } |
| 4301 | /* |
| 4302 | * If we have a copper PHY then we only want to go out to the PHY |
| 4303 | * registers to see if Auto-Neg has completed and/or if our link |
| 4304 | * status has changed. The get_link_status flag will be set if we |
| 4305 | * receive a Link Status Change interrupt or we have Rx Sequence |
| 4306 | * Errors. |
| 4307 | */ |
| 4308 | if ((hw->media_type == em_media_type_copper || |
| 4309 | (hw->media_type == em_media_type_oem)) && |
| 4310 | hw->get_link_status) { |
| 4311 | /* |
| 4312 | * First we want to see if the MII Status Register reports |
| 4313 | * link. If so, then we want to get the current speed/duplex |
| 4314 | * of the PHY. Read the register twice since the link bit is |
| 4315 | * sticky. |
| 4316 | */ |
| 4317 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 4318 | if (ret_val) |
| 4319 | return ret_val; |
| 4320 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 4321 | if (ret_val) |
| 4322 | return ret_val; |
| 4323 | |
| 4324 | hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0; |
| 4325 | |
| 4326 | if (hw->mac_type == em_pchlan) { |
| 4327 | ret_val = em_k1_gig_workaround_hv(hw, |
| 4328 | hw->icp_xxxx_is_link_up); |
| 4329 | if (ret_val) |
| 4330 | return ret_val; |
| 4331 | } |
| 4332 | |
| 4333 | if (phy_data & MII_SR_LINK_STATUS0x0004) { |
| 4334 | hw->get_link_status = FALSE0; |
| 4335 | |
| 4336 | if (hw->phy_type == em_phy_82578) { |
| 4337 | ret_val = em_link_stall_workaround_hv(hw); |
| 4338 | if (ret_val) |
| 4339 | return ret_val; |
| 4340 | } |
| 4341 | |
| 4342 | if (hw->mac_type == em_pch2lan) { |
| 4343 | ret_val = em_k1_workaround_lv(hw); |
| 4344 | if (ret_val) |
| 4345 | return ret_val; |
| 4346 | } |
| 4347 | /* Work-around I218 hang issue */ |
| 4348 | if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A) || |
| 4349 | (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V0x1559) || |
| 4350 | (hw->device_id == E1000_DEV_ID_PCH_I218_LM30x15A2) || |
| 4351 | (hw->device_id == E1000_DEV_ID_PCH_I218_V30x15A3)) { |
| 4352 | ret_val = em_k1_workaround_lpt_lp(hw, |
| 4353 | hw->icp_xxxx_is_link_up); |
| 4354 | if (ret_val) |
| 4355 | return ret_val; |
| 4356 | } |
| 4357 | |
| 4358 | /* |
| 4359 | * Check if there was DownShift, must be checked |
| 4360 | * immediately after link-up |
| 4361 | */ |
| 4362 | em_check_downshift(hw); |
| 4363 | |
| 4364 | /* Enable/Disable EEE after link up */ |
| 4365 | if (hw->mac_type == em_pch2lan || |
| 4366 | hw->mac_type == em_pch_lpt || |
| 4367 | hw->mac_type == em_pch_spt || |
| 4368 | hw->mac_type == em_pch_cnp || |
| 4369 | hw->mac_type == em_pch_tgp || |
| 4370 | hw->mac_type == em_pch_adp) { |
| 4371 | ret_val = em_set_eee_pchlan(hw); |
| 4372 | if (ret_val) |
| 4373 | return ret_val; |
| 4374 | } |
| 4375 | |
| 4376 | /* |
| 4377 | * If we are on 82544 or 82543 silicon and |
| 4378 | * speed/duplex are forced to 10H or 10F, then we |
| 4379 | * will implement the polarity reversal workaround. |
| 4380 | * We disable interrupts first, and upon returning, |
| 4381 | * place the devices interrupt state to its previous |
| 4382 | * value except for the link status change interrupt |
| 4383 | * which will happen due to the execution of this |
| 4384 | * workaround. |
| 4385 | */ |
| 4386 | if ((hw->mac_type == em_82544 || |
| 4387 | hw->mac_type == em_82543) && (!hw->autoneg) && |
| 4388 | (hw->forced_speed_duplex == em_10_full || |
| 4389 | hw->forced_speed_duplex == em_10_half)) { |
| 4390 | E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register (0x000D8))), (0xffffffff))); |
| 4391 | ret_val = em_polarity_reversal_workaround(hw); |
| 4392 | icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register (0x000C0))))); |
| 4393 | E1000_WRITE_REG(hw, ICS,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register (0x000C8))), ((icr & ~0x00000004)))) |
| 4394 | (icr & ~E1000_ICS_LSC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register (0x000C8))), ((icr & ~0x00000004)))); |
| 4395 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x000D0 : em_translate_82542_register (0x000D0))), (( 0x00000080 | 0x00000001 | 0x00000010 | 0x00000008 | 0x00000040 | 0x00000004)))); |
| 4396 | } |
| 4397 | } else { |
| 4398 | /* No link detected */ |
| 4399 | em_config_dsp_after_link_change(hw, FALSE0); |
| 4400 | return 0; |
| 4401 | } |
| 4402 | /* |
| 4403 | * If we are forcing speed/duplex, then we simply return |
| 4404 | * since we have already determined whether we have link or |
| 4405 | * not. |
| 4406 | */ |
| 4407 | if (!hw->autoneg) |
| 4408 | return -E1000_ERR_CONFIG3; |
| 4409 | |
| 4410 | /* optimize the dsp settings for the igp phy */ |
| 4411 | em_config_dsp_after_link_change(hw, TRUE1); |
| 4412 | /* |
| 4413 | * We have a M88E1000 PHY and Auto-Neg is enabled. If we |
| 4414 | * have Si on board that is 82544 or newer, Auto Speed |
| 4415 | * Detection takes care of MAC speed/duplex configuration. |
| 4416 | * So we only need to configure Collision Distance in the |
| 4417 | * MAC. Otherwise, we need to force speed/duplex on the MAC |
| 4418 | * to the current PHY speed/duplex settings. |
| 4419 | */ |
| 4420 | if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { |
| 4421 | em_config_collision_dist(hw); |
| 4422 | } else { |
| 4423 | ret_val = em_config_mac_to_phy(hw); |
| 4424 | if (ret_val) { |
| 4425 | DEBUGOUT("Error configuring MAC to PHY" |
| 4426 | " settings\n"); |
| 4427 | return ret_val; |
| 4428 | } |
| 4429 | } |
| 4430 | /* |
| 4431 | * Configure Flow Control now that Auto-Neg has completed. |
| 4432 | * First, we need to restore the desired flow control |
| 4433 | * settings because we may have had to re-autoneg with a |
| 4434 | * different link partner. |
| 4435 | */ |
| 4436 | ret_val = em_config_fc_after_link_up(hw); |
| 4437 | if (ret_val) { |
| 4438 | DEBUGOUT("Error configuring flow control\n"); |
| 4439 | return ret_val; |
| 4440 | } |
| 4441 | /* |
| 4442 | * At this point we know that we are on copper and we have |
| 4443 | * auto-negotiated link. These are conditions for checking |
| 4444 | * the link partner capability register. We use the link |
| 4445 | * speed to determine if TBI compatibility needs to be turned |
| 4446 | * on or off. If the link is not at gigabit speed, then TBI |
| 4447 | * compatibility is not needed. If we are at gigabit speed, |
| 4448 | * we turn on TBI compatibility. |
| 4449 | */ |
| 4450 | if (hw->tbi_compatibility_en) { |
| 4451 | uint16_t speed, duplex; |
| 4452 | ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); |
| 4453 | if (ret_val) { |
| 4454 | DEBUGOUT("Error getting link speed and duplex" |
| 4455 | "\n"); |
| 4456 | return ret_val; |
| 4457 | } |
| 4458 | if (speed != SPEED_10001000) { |
| 4459 | /* |
| 4460 | * If link speed is not set to gigabit speed, |
| 4461 | * we do not need to enable TBI |
| 4462 | * compatibility. |
| 4463 | */ |
| 4464 | if (hw->tbi_compatibility_on) { |
| 4465 | /* |
| 4466 | * If we previously were in the mode, |
| 4467 | * turn it off. |
| 4468 | */ |
| 4469 | rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))))); |
| 4470 | rctl &= ~E1000_RCTL_SBP0x00000004; |
| 4471 | E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))), (rctl))); |
| 4472 | hw->tbi_compatibility_on = FALSE0; |
| 4473 | } |
| 4474 | } else { |
| 4475 | /* |
| 4476 | * If TBI compatibility is was previously |
| 4477 | * off, turn it on. For compatibility with a |
| 4478 | * TBI link partner, we will store bad |
| 4479 | * packets. Some frames have an additional |
| 4480 | * byte on the end and will look like CRC |
| 4481 | * errors to the hardware. |
| 4482 | */ |
| 4483 | if (!hw->tbi_compatibility_on) { |
| 4484 | hw->tbi_compatibility_on = TRUE1; |
| 4485 | rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))))); |
| 4486 | rctl |= E1000_RCTL_SBP0x00000004; |
| 4487 | E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register (0x00100))), (rctl))); |
| 4488 | } |
| 4489 | } |
| 4490 | } |
| 4491 | } |
| 4492 | /* |
| 4493 | * If we don't have link (auto-negotiation failed or link partner |
| 4494 | * cannot auto-negotiate), the cable is plugged in (we have signal), |
| 4495 | * and our link partner is not trying to auto-negotiate with us (we |
| 4496 | * are receiving idles or data), we need to force link up. We also |
| 4497 | * need to give auto-negotiation time to complete, in case the cable |
| 4498 | * was just plugged in. The autoneg_failed flag does this. |
| 4499 | */ |
| 4500 | else if ((((hw->media_type == em_media_type_fiber) && |
| 4501 | ((ctrl & E1000_CTRL_SWDPIN10x00080000) == signal)) || |
| 4502 | (hw->media_type == em_media_type_internal_serdes)) && |
| 4503 | (!(status & E1000_STATUS_LU0x00000002)) && (!(rxcw & E1000_RXCW_C0x20000000))) { |
| 4504 | if (hw->autoneg_failed == 0) { |
| 4505 | hw->autoneg_failed = 1; |
| 4506 | return 0; |
| 4507 | } |
| 4508 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
| 4509 | |
| 4510 | /* Disable auto-negotiation in the TXCW register */ |
| 4511 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register (0x00178))), ((hw->txcw & ~0x80000000)))); |
| 4512 | |
| 4513 | /* Force link-up and also force full-duplex. */ |
| 4514 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 4515 | ctrl |= (E1000_CTRL_SLU0x00000040 | E1000_CTRL_FD0x00000001); |
| 4516 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 4517 | |
| 4518 | /* Configure Flow Control after forcing link up. */ |
| 4519 | ret_val = em_config_fc_after_link_up(hw); |
| 4520 | if (ret_val) { |
| 4521 | DEBUGOUT("Error configuring flow control\n"); |
| 4522 | return ret_val; |
| 4523 | } |
| 4524 | } |
| 4525 | /* |
| 4526 | * If we are forcing link and we are receiving /C/ ordered sets, |
| 4527 | * re-enable auto-negotiation in the TXCW register and disable forced |
| 4528 | * link in the Device Control register in an attempt to |
| 4529 | * auto-negotiate with our link partner. |
| 4530 | */ |
| 4531 | else if (((hw->media_type == em_media_type_fiber) || |
| 4532 | (hw->media_type == em_media_type_internal_serdes)) && |
| 4533 | (ctrl & E1000_CTRL_SLU0x00000040) && (rxcw & E1000_RXCW_C0x20000000)) { |
| 4534 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
| 4535 | E1000_WRITE_REG(hw, TXCW, hw->txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register (0x00178))), (hw->txcw))); |
| 4536 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((ctrl & ~0x00000040)))); |
| 4537 | |
| 4538 | hw->serdes_link_down = FALSE0; |
| 4539 | } |
| 4540 | /* |
| 4541 | * If we force link for non-auto-negotiation switch, check link |
| 4542 | * status based on MAC synchronization for internal serdes media |
| 4543 | * type. |
| 4544 | */ |
| 4545 | else if ((hw->media_type == em_media_type_internal_serdes) && |
| 4546 | !(E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register (0x00178))))))) { |
| 4547 | /* SYNCH bit and IV bit are sticky. */ |
| 4548 | usec_delay(10)(*delay_func)(10); |
| 4549 | if (E1000_RXCW_SYNCH0x40000000 & E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register (0x00180)))))) { |
| 4550 | if (!(rxcw & E1000_RXCW_IV0x08000000)) { |
| 4551 | hw->serdes_link_down = FALSE0; |
| 4552 | DEBUGOUT("SERDES: Link is up.\n"); |
| 4553 | } |
| 4554 | } else { |
| 4555 | hw->serdes_link_down = TRUE1; |
| 4556 | DEBUGOUT("SERDES: Link is down.\n"); |
| 4557 | } |
| 4558 | } |
| 4559 | if ((hw->media_type == em_media_type_internal_serdes) && |
| 4560 | (E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register (0x00178))))))) { |
| 4561 | hw->serdes_link_down = !(E1000_STATUS_LU0x00000002 & |
| 4562 | E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008)))))); |
| 4563 | } |
| 4564 | return E1000_SUCCESS0; |
| 4565 | } |
| 4566 | |
| 4567 | int32_t |
| 4568 | em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, |
| 4569 | uint16_t *duplex) |
| 4570 | { |
| 4571 | uint32_t pcs; |
| 4572 | |
| 4573 | hw->serdes_link_down = TRUE1; |
| 4574 | *speed = 0; |
| 4575 | *duplex = 0; |
| 4576 | |
| 4577 | /* |
| 4578 | * Read the PCS Status register for link state. For non-copper mode, |
| 4579 | * the status register is not accurate. The PCS status register is |
| 4580 | * used instead. |
| 4581 | */ |
| 4582 | pcs = E1000_READ_REG(hw, PCS_LSTAT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x0420C : em_translate_82542_register (0x0420C))))); |
| 4583 | |
| 4584 | /* |
| 4585 | * The link up bit determines when link is up on autoneg. The sync ok |
| 4586 | * gets set once both sides sync up and agree upon link. Stable link |
| 4587 | * can be determined by checking for both link up and link sync ok |
| 4588 | */ |
| 4589 | if ((pcs & E1000_PCS_LSTS_LINK_OK0x01) && (pcs & E1000_PCS_LSTS_SYNK_OK0x10)) { |
| 4590 | hw->serdes_link_down = FALSE0; |
| 4591 | |
| 4592 | /* Detect and store PCS speed */ |
| 4593 | if (pcs & E1000_PCS_LSTS_SPEED_10000x04) { |
| 4594 | *speed = SPEED_10001000; |
| 4595 | } else if (pcs & E1000_PCS_LSTS_SPEED_1000x02) { |
| 4596 | *speed = SPEED_100100; |
| 4597 | } else { |
| 4598 | *speed = SPEED_1010; |
| 4599 | } |
| 4600 | |
| 4601 | /* Detect and store PCS duplex */ |
| 4602 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL0x08) { |
| 4603 | *duplex = FULL_DUPLEX2; |
| 4604 | } else { |
| 4605 | *duplex = HALF_DUPLEX1; |
| 4606 | } |
| 4607 | } |
| 4608 | |
| 4609 | return (0); |
| 4610 | } |
| 4611 | |
| 4612 | |
| 4613 | /****************************************************************************** |
| 4614 | * Detects the current speed and duplex settings of the hardware. |
| 4615 | * |
| 4616 | * hw - Struct containing variables accessed by shared code |
| 4617 | * speed - Speed of the connection |
| 4618 | * duplex - Duplex setting of the connection |
| 4619 | *****************************************************************************/ |
| 4620 | int32_t |
| 4621 | em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) |
| 4622 | { |
| 4623 | uint32_t status; |
| 4624 | int32_t ret_val; |
| 4625 | uint16_t phy_data; |
| 4626 | DEBUGFUNC("em_get_speed_and_duplex");; |
| 4627 | |
| 4628 | if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) |
| 4629 | return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); |
| 4630 | |
| 4631 | if (hw->mac_type >= em_82543) { |
| 4632 | status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4633 | if (status & E1000_STATUS_SPEED_10000x00000080) { |
| 4634 | *speed = SPEED_10001000; |
| 4635 | DEBUGOUT("1000 Mbs, "); |
| 4636 | } else if (status & E1000_STATUS_SPEED_1000x00000040) { |
| 4637 | *speed = SPEED_100100; |
| 4638 | DEBUGOUT("100 Mbs, "); |
| 4639 | } else { |
| 4640 | *speed = SPEED_1010; |
| 4641 | DEBUGOUT("10 Mbs, "); |
| 4642 | } |
| 4643 | |
| 4644 | if (status & E1000_STATUS_FD0x00000001) { |
| 4645 | *duplex = FULL_DUPLEX2; |
| 4646 | DEBUGOUT("Full Duplex\n"); |
| 4647 | } else { |
| 4648 | *duplex = HALF_DUPLEX1; |
| 4649 | DEBUGOUT(" Half Duplex\n"); |
| 4650 | } |
| 4651 | } else { |
| 4652 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
| 4653 | *speed = SPEED_10001000; |
| 4654 | *duplex = FULL_DUPLEX2; |
| 4655 | } |
| 4656 | /* |
| 4657 | * IGP01 PHY may advertise full duplex operation after speed |
| 4658 | * downgrade even if it is operating at half duplex. Here we set the |
| 4659 | * duplex settings to match the duplex in the link partner's |
| 4660 | * capabilities. |
| 4661 | */ |
| 4662 | if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { |
| 4663 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP0x06, &phy_data); |
| 4664 | if (ret_val) |
| 4665 | return ret_val; |
| 4666 | |
| 4667 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS0x0001)) |
| 4668 | *duplex = HALF_DUPLEX1; |
| 4669 | else { |
| 4670 | ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05, |
| 4671 | &phy_data); |
| 4672 | if (ret_val) |
| 4673 | return ret_val; |
| 4674 | if ((*speed == SPEED_100100 && |
| 4675 | !(phy_data & NWAY_LPAR_100TX_FD_CAPS0x0100)) || |
| 4676 | (*speed == SPEED_1010 && |
| 4677 | !(phy_data & NWAY_LPAR_10T_FD_CAPS0x0040))) |
| 4678 | *duplex = HALF_DUPLEX1; |
| 4679 | } |
| 4680 | } |
| 4681 | if ((hw->mac_type == em_80003es2lan) && |
| 4682 | (hw->media_type == em_media_type_copper)) { |
| 4683 | if (*speed == SPEED_10001000) |
| 4684 | ret_val = em_configure_kmrn_for_1000(hw); |
| 4685 | else |
| 4686 | ret_val = em_configure_kmrn_for_10_100(hw, *duplex); |
| 4687 | if (ret_val) |
| 4688 | return ret_val; |
| 4689 | } |
| 4690 | if ((hw->mac_type == em_ich8lan) && |
| 4691 | (hw->phy_type == em_phy_igp_3) && |
| 4692 | (*speed == SPEED_10001000)) { |
| 4693 | ret_val = em_kumeran_lock_loss_workaround(hw); |
| 4694 | if (ret_val) |
| 4695 | return ret_val; |
| 4696 | } |
| 4697 | return E1000_SUCCESS0; |
| 4698 | } |
| 4699 | |
| 4700 | /****************************************************************************** |
| 4701 | * Blocks until autoneg completes or times out (~4.5 seconds) |
| 4702 | * |
| 4703 | * hw - Struct containing variables accessed by shared code |
| 4704 | *****************************************************************************/ |
| 4705 | STATIC int32_t |
| 4706 | em_wait_autoneg(struct em_hw *hw) |
| 4707 | { |
| 4708 | int32_t ret_val; |
| 4709 | uint16_t i; |
| 4710 | uint16_t phy_data; |
| 4711 | DEBUGFUNC("em_wait_autoneg");; |
| 4712 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
| 4713 | |
| 4714 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
| 4715 | for (i = PHY_AUTO_NEG_TIME45; i > 0; i--) { |
| 4716 | /* |
| 4717 | * Read the MII Status Register and wait for Auto-Neg |
| 4718 | * Complete bit to be set. |
| 4719 | */ |
| 4720 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 4721 | if (ret_val) |
| 4722 | return ret_val; |
| 4723 | ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data); |
| 4724 | if (ret_val) |
| 4725 | return ret_val; |
| 4726 | if (phy_data & MII_SR_AUTONEG_COMPLETE0x0020) { |
| 4727 | return E1000_SUCCESS0; |
| 4728 | } |
| 4729 | msec_delay(100)(*delay_func)(1000*(100)); |
| 4730 | } |
| 4731 | return E1000_SUCCESS0; |
| 4732 | } |
| 4733 | |
| 4734 | /****************************************************************************** |
| 4735 | * Raises the Management Data Clock |
| 4736 | * |
| 4737 | * hw - Struct containing variables accessed by shared code |
| 4738 | * ctrl - Device control register's current value |
| 4739 | *****************************************************************************/ |
| 4740 | static void |
| 4741 | em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) |
| 4742 | { |
| 4743 | /* |
| 4744 | * Raise the clock input to the Management Data Clock (by setting the |
| 4745 | * MDC bit), and then delay 10 microseconds. |
| 4746 | */ |
| 4747 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((*ctrl | 0x00200000)))); |
| 4748 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4749 | usec_delay(10)(*delay_func)(10); |
| 4750 | } |
| 4751 | |
| 4752 | /****************************************************************************** |
| 4753 | * Lowers the Management Data Clock |
| 4754 | * |
| 4755 | * hw - Struct containing variables accessed by shared code |
| 4756 | * ctrl - Device control register's current value |
| 4757 | *****************************************************************************/ |
| 4758 | static void |
| 4759 | em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) |
| 4760 | { |
| 4761 | /* |
| 4762 | * Lower the clock input to the Management Data Clock (by clearing |
| 4763 | * the MDC bit), and then delay 10 microseconds. |
| 4764 | */ |
| 4765 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), ((*ctrl & ~0x00200000)))); |
| 4766 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4767 | usec_delay(10)(*delay_func)(10); |
| 4768 | } |
| 4769 | |
| 4770 | /****************************************************************************** |
| 4771 | * Shifts data bits out to the PHY |
| 4772 | * |
| 4773 | * hw - Struct containing variables accessed by shared code |
| 4774 | * data - Data to send out to the PHY |
| 4775 | * count - Number of bits to shift out |
| 4776 | * |
| 4777 | * Bits are shifted out in MSB to LSB order. |
| 4778 | *****************************************************************************/ |
| 4779 | static void |
| 4780 | em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) |
| 4781 | { |
| 4782 | uint32_t ctrl; |
| 4783 | uint32_t mask; |
| 4784 | /* |
| 4785 | * We need to shift "count" number of bits out to the PHY. So, the |
| 4786 | * value in the "data" parameter will be shifted out to the PHY one |
| 4787 | * bit at a time. In order to do this, "data" must be broken down |
| 4788 | * into bits. |
| 4789 | */ |
| 4790 | mask = 0x01; |
| 4791 | mask <<= (count - 1); |
| 4792 | |
| 4793 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 4794 | |
| 4795 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output |
| 4796 | * pins. |
| 4797 | */ |
| 4798 | ctrl |= (E1000_CTRL_MDIO_DIR0x01000000 | E1000_CTRL_MDC_DIR0x02000000); |
| 4799 | |
| 4800 | while (mask) { |
| 4801 | /* |
| 4802 | * A "1" is shifted out to the PHY by setting the MDIO bit to |
| 4803 | * "1" and then raising and lowering the Management Data |
| 4804 | * Clock. A "0" is shifted out to the PHY by setting the MDIO |
| 4805 | * bit to "0" and then raising and lowering the clock. |
| 4806 | */ |
| 4807 | if (data & mask) |
| 4808 | ctrl |= E1000_CTRL_MDIO0x00100000; |
| 4809 | else |
| 4810 | ctrl &= ~E1000_CTRL_MDIO0x00100000; |
| 4811 | |
| 4812 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 4813 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4814 | |
| 4815 | usec_delay(10)(*delay_func)(10); |
| 4816 | |
| 4817 | em_raise_mdi_clk(hw, &ctrl); |
| 4818 | em_lower_mdi_clk(hw, &ctrl); |
| 4819 | |
| 4820 | mask = mask >> 1; |
| 4821 | } |
| 4822 | } |
| 4823 | |
| 4824 | /****************************************************************************** |
| 4825 | * Shifts data bits in from the PHY |
| 4826 | * |
| 4827 | * hw - Struct containing variables accessed by shared code |
| 4828 | * |
| 4829 | * Bits are shifted in in MSB to LSB order. |
| 4830 | *****************************************************************************/ |
| 4831 | static uint16_t |
| 4832 | em_shift_in_mdi_bits(struct em_hw *hw) |
| 4833 | { |
| 4834 | uint32_t ctrl; |
| 4835 | uint16_t data = 0; |
| 4836 | uint8_t i; |
| 4837 | /* |
| 4838 | * In order to read a register from the PHY, we need to shift in a |
| 4839 | * total of 18 bits from the PHY. The first two bit (turnaround) |
| 4840 | * times are used to avoid contention on the MDIO pin when a read |
| 4841 | * operation is performed. These two bits are ignored by us and |
| 4842 | * thrown away. Bits are "shifted in" by raising the input to the |
| 4843 | * Management Data Clock (setting the MDC bit), and then reading the |
| 4844 | * value of the MDIO bit. |
| 4845 | */ |
| 4846 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 4847 | /* |
| 4848 | * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as |
| 4849 | * input. |
| 4850 | */ |
| 4851 | ctrl &= ~E1000_CTRL_MDIO_DIR0x01000000; |
| 4852 | ctrl &= ~E1000_CTRL_MDIO0x00100000; |
| 4853 | |
| 4854 | E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))), (ctrl))); |
| 4855 | E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))); |
| 4856 | /* |
| 4857 | * Raise and Lower the clock before reading in the data. This |
| 4858 | * accounts for the turnaround bits. The first clock occurred when we |
| 4859 | * clocked out the last bit of the Register Address. |
| 4860 | */ |
| 4861 | em_raise_mdi_clk(hw, &ctrl); |
| 4862 | em_lower_mdi_clk(hw, &ctrl); |
| 4863 | |
| 4864 | for (data = 0, i = 0; i < 16; i++) { |
| 4865 | data = data << 1; |
| 4866 | em_raise_mdi_clk(hw, &ctrl); |
| 4867 | ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register (0x00000))))); |
| 4868 | /* Check to see if we shifted in a "1". */ |
| 4869 | if (ctrl & E1000_CTRL_MDIO0x00100000) |
| 4870 | data |= 1; |
| 4871 | em_lower_mdi_clk(hw, &ctrl); |
| 4872 | } |
| 4873 | |
| 4874 | em_raise_mdi_clk(hw, &ctrl); |
| 4875 | em_lower_mdi_clk(hw, &ctrl); |
| 4876 | |
| 4877 | return data; |
| 4878 | } |
| 4879 | |
| 4880 | STATIC int32_t |
| 4881 | em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) |
| 4882 | { |
| 4883 | uint32_t swfw_sync = 0; |
| 4884 | uint32_t swmask = mask; |
| 4885 | uint32_t fwmask = mask << 16; |
| 4886 | int32_t timeout = 200; |
| 4887 | DEBUGFUNC("em_swfw_sync_acquire");; |
| 4888 | |
| 4889 | if (hw->swfwhw_semaphore_present) |
| 4890 | return em_get_software_flag(hw); |
| 4891 | |
| 4892 | if (!hw->swfw_sync_present) |
| 4893 | return em_get_hw_eeprom_semaphore(hw); |
| 4894 | |
| 4895 | while (timeout) { |
| 4896 | if (em_get_hw_eeprom_semaphore(hw)) |
| 4897 | return -E1000_ERR_SWFW_SYNC13; |
| 4898 | |
| 4899 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register (0x05B5C))))); |
| 4900 | if (!(swfw_sync & (fwmask | swmask))) { |
| 4901 | break; |
| 4902 | } |
| 4903 | /* |
| 4904 | * firmware currently using resource (fwmask) |
| 4905 | * or other software thread currently using resource (swmask) |
| 4906 | */ |
| 4907 | em_put_hw_eeprom_semaphore(hw); |
| 4908 | msec_delay_irq(5)(*delay_func)(1000*(5)); |
| 4909 | timeout--; |
| 4910 | } |
| 4911 | |
| 4912 | if (!timeout) { |
| 4913 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." |
| 4914 | "\n"); |
| 4915 | return -E1000_ERR_SWFW_SYNC13; |
| 4916 | } |
| 4917 | swfw_sync |= swmask; |
| 4918 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register (0x05B5C))), (swfw_sync))); |
| 4919 | |
| 4920 | em_put_hw_eeprom_semaphore(hw); |
| 4921 | return E1000_SUCCESS0; |
| 4922 | } |
| 4923 | |
| 4924 | STATIC void |
| 4925 | em_swfw_sync_release(struct em_hw *hw, uint16_t mask) |
| 4926 | { |
| 4927 | uint32_t swfw_sync; |
| 4928 | uint32_t swmask = mask; |
| 4929 | DEBUGFUNC("em_swfw_sync_release");; |
| 4930 | |
| 4931 | if (hw->swfwhw_semaphore_present) { |
| 4932 | em_release_software_flag(hw); |
| 4933 | return; |
| 4934 | } |
| 4935 | if (!hw->swfw_sync_present) { |
| 4936 | em_put_hw_eeprom_semaphore(hw); |
| 4937 | return; |
| 4938 | } |
| 4939 | /* |
| 4940 | * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; |
| 4941 | */ |
| 4942 | while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS0); |
| 4943 | /* empty */ |
| 4944 | |
| 4945 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register (0x05B5C))))); |
| 4946 | swfw_sync &= ~swmask; |
| 4947 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register (0x05B5C))), (swfw_sync))); |
| 4948 | |
| 4949 | em_put_hw_eeprom_semaphore(hw); |
| 4950 | } |
| 4951 | |
| 4952 | /**************************************************************************** |
| 4953 | * Read BM PHY wakeup register. It works as such: |
| 4954 | * 1) Set page 769, register 17, bit 2 = 1 |
| 4955 | * 2) Set page to 800 for host (801 if we were manageability) |
| 4956 | * 3) Write the address using the address opcode (0x11) |
| 4957 | * 4) Read or write the data using the data opcode (0x12) |
| 4958 | * 5) Restore 769_17.2 to its original value |
| 4959 | ****************************************************************************/ |
| 4960 | int32_t |
| 4961 | em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, |
| 4962 | uint16_t *phy_data, boolean_t read) |
| 4963 | { |
| 4964 | int32_t ret_val; |
| 4965 | uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> ( 21 - 5)) & ~0x1F))); |
| 4966 | uint16_t phy_reg = 0; |
| 4967 | |
| 4968 | /* All operations in this function are phy address 1 */ |
| 4969 | hw->phy_addr = 1; |
| 4970 | |
| 4971 | /* Set page 769 */ |
| 4972 | em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 4973 | (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5)); |
| 4974 | |
| 4975 | ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, &phy_reg); |
| 4976 | if (ret_val) |
| 4977 | goto out; |
| 4978 | |
| 4979 | /* First clear bit 4 to avoid a power state change */ |
| 4980 | phy_reg &= ~(BM_WUC_HOST_WU_BIT(1 << 4)); |
| 4981 | ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg); |
| 4982 | if (ret_val) |
| 4983 | goto out; |
| 4984 | |
| 4985 | /* Write bit 2 = 1, and clear bit 4 to 769_17 */ |
| 4986 | ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, |
| 4987 | phy_reg | BM_WUC_ENABLE_BIT(1 << 2)); |
| 4988 | if (ret_val) |
| 4989 | goto out; |
| 4990 | |
| 4991 | /* Select page 800 */ |
| 4992 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 4993 | (BM_WUC_PAGE800 << PHY_PAGE_SHIFT5)); |
| 4994 | |
| 4995 | /* Write the page 800 offset value using opcode 0x11 */ |
| 4996 | ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE0x11, reg); |
| 4997 | if (ret_val) |
| 4998 | goto out; |
| 4999 | |
| 5000 | if (read) |
| 5001 | /* Read the page 800 value using opcode 0x12 */ |
| 5002 | ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12, |
| 5003 | phy_data); |
| 5004 | else |
| 5005 | /* Write the page 800 value using opcode 0x12 */ |
| 5006 | ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12, |
| 5007 | *phy_data); |
| 5008 | |
| 5009 | if (ret_val) |
| 5010 | goto out; |
| 5011 | |
| 5012 | /* |
| 5013 | * Restore 769_17.2 to its original value |
| 5014 | * Set page 769 |
| 5015 | */ |
| 5016 | em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 5017 | (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5)); |
| 5018 | |
| 5019 | /* Clear 769_17.2 */ |
| 5020 | ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg); |
| 5021 | if (ret_val) |
| 5022 | goto out; |
| 5023 | |
| 5024 | out: |
| 5025 | return ret_val; |
| 5026 | } |
| 5027 | |
| 5028 | /*************************************************************************** |
| 5029 | * Read HV PHY vendor specific high registers |
| 5030 | ***************************************************************************/ |
| 5031 | int32_t |
| 5032 | em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, |
| 5033 | uint16_t *phy_data, boolean_t read) |
| 5034 | { |
| 5035 | int32_t ret_val; |
| 5036 | uint32_t addr_reg = 0; |
| 5037 | uint32_t data_reg = 0; |
| 5038 | |
| 5039 | /* This takes care of the difference with desktop vs mobile phy */ |
| 5040 | addr_reg = (hw->phy_type == em_phy_82578) ? |
| 5041 | I82578_PHY_ADDR_REG29 : I82577_PHY_ADDR_REG16; |
| 5042 | data_reg = addr_reg + 1; |
| 5043 | |
| 5044 | /* All operations in this function are phy address 2 */ |
| 5045 | hw->phy_addr = 2; |
| 5046 | |
| 5047 | /* masking with 0x3F to remove the page from offset */ |
| 5048 | ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); |
| 5049 | if (ret_val) { |
| 5050 | printf("Could not write PHY the HV address register\n"); |
| 5051 | goto out; |
| 5052 | } |
| 5053 | |
| 5054 | /* Read or write the data value next */ |
| 5055 | if (read) |
| 5056 | ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); |
| 5057 | else |
| 5058 | ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); |
| 5059 | |
| 5060 | if (ret_val) { |
| 5061 | printf("Could not read data value from HV data register\n"); |
| 5062 | goto out; |
| 5063 | } |
| 5064 | |
| 5065 | out: |
| 5066 | return ret_val; |
| 5067 | } |
| 5068 | |
| 5069 | /****************************************************************************** |
| 5070 | * Reads or writes the value from a PHY register, if the value is on a specific |
| 5071 | * non zero page, sets the page first. |
| 5072 | * hw - Struct containing variables accessed by shared code |
| 5073 | * reg_addr - address of the PHY register to read |
| 5074 | *****************************************************************************/ |
| 5075 | int32_t |
| 5076 | em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, |
| 5077 | boolean_t read) |
| 5078 | { |
| 5079 | uint32_t ret_val; |
| 5080 | uint16_t swfw; |
| 5081 | uint16_t page = BM_PHY_REG_PAGE(reg_addr)((uint16_t)(((reg_addr) >> 5) & 0xFFFF)); |
| 5082 | uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> ( 21 - 5)) & ~0x1F))); |
| 5083 | |
| 5084 | DEBUGFUNC("em_access_phy_reg_hv");; |
| 5085 | |
| 5086 | swfw = E1000_SWFW_PHY0_SM0x0002; |
| 5087 | |
| 5088 | if (em_swfw_sync_acquire(hw, swfw)) |
| 5089 | return -E1000_ERR_SWFW_SYNC13; |
| 5090 | |
| 5091 | if (page == BM_WUC_PAGE800) { |
| 5092 | ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, |
| 5093 | phy_data, read); |
| 5094 | goto release; |
| 5095 | } |
| 5096 | |
| 5097 | if (page >= HV_INTC_FC_PAGE_START768) |
| 5098 | hw->phy_addr = 1; |
| 5099 | else |
| 5100 | hw->phy_addr = 2; |
| 5101 | |
| 5102 | if (page == HV_INTC_FC_PAGE_START768) |
| 5103 | page = 0; |
| 5104 | |
| 5105 | /* |
| 5106 | * Workaround MDIO accesses being disabled after entering IEEE Power |
| 5107 | * Down (whenever bit 11 of the PHY Control register is set) |
| 5108 | */ |
| 5109 | if (!read && |
| 5110 | (hw->phy_type == em_phy_82578) && |
| 5111 | (hw->phy_revision >= 1) && |
| 5112 | (hw->phy_addr == 2) && |
| 5113 | ((MAX_PHY_REG_ADDRESS0x1F & reg) == 0) && |
| 5114 | (*phy_data & (1 << 11))) { |
| 5115 | uint16_t data2 = 0x7EFF; |
| 5116 | |
| 5117 | ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
| 5118 | &data2, FALSE0); |
| 5119 | if (ret_val) |
| 5120 | return ret_val; |
| 5121 | } |
| 5122 | |
| 5123 | if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) { |
| 5124 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 5125 | (page << PHY_PAGE_SHIFT5)); |
| 5126 | if (ret_val) |
| 5127 | return ret_val; |
| 5128 | } |
| 5129 | if (read) |
| 5130 | ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg, |
| 5131 | phy_data); |
| 5132 | else |
| 5133 | ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg, |
| 5134 | *phy_data); |
| 5135 | release: |
| 5136 | em_swfw_sync_release(hw, swfw); |
| 5137 | return ret_val; |
| 5138 | } |
| 5139 | |
| 5140 | /****************************************************************************** |
| 5141 | * Reads the value from a PHY register, if the value is on a specific non zero |
| 5142 | * page, sets the page first. |
| 5143 | * hw - Struct containing variables accessed by shared code |
| 5144 | * reg_addr - address of the PHY register to read |
| 5145 | *****************************************************************************/ |
| 5146 | int32_t |
| 5147 | em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) |
| 5148 | { |
| 5149 | uint32_t ret_val; |
| 5150 | uint16_t swfw; |
| 5151 | DEBUGFUNC("em_read_phy_reg");; |
| 5152 | |
| 5153 | if (hw->mac_type == em_pchlan || |
| 5154 | hw->mac_type == em_pch2lan || |
| 5155 | hw->mac_type == em_pch_lpt || |
| 5156 | hw->mac_type == em_pch_spt || |
| 5157 | hw->mac_type == em_pch_cnp || |
| 5158 | hw->mac_type == em_pch_tgp || |
| 5159 | hw->mac_type == em_pch_adp) |
| 5160 | return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE1)); |
| 5161 | |
| 5162 | if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || |
| 5163 | (hw->mac_type == em_82576)) && |
| 5164 | (E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register (0x00008))))) & E1000_STATUS_FUNC_10x00000004)) { |
| 5165 | swfw = E1000_SWFW_PHY1_SM0x0004; |
| 5166 | } else { |
| 5167 | swfw = E1000_SWFW_PHY0_SM0x0002; |
| 5168 | } |
| 5169 | if (em_swfw_sync_acquire(hw, swfw)) |
| 5170 | return -E1000_ERR_SWFW_SYNC13; |
| 5171 | |
| 5172 | if ((hw->phy_type == em_phy_igp || |
| 5173 | hw->phy_type == em_phy_igp_3 || |
| 5174 | hw->phy_type == em_phy_igp_2) && |
| 5175 | (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) { |
| 5176 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 5177 | (uint16_t) reg_addr); |
| 5178 | if (ret_val) { |
| 5179 | em_swfw_sync_release(hw, swfw); |
| 5180 | return ret_val; |
| 5181 | } |
| 5182 | } else if (hw->phy_type == em_phy_gg82563) { |
| 5183 | if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) || |
| 5184 | (hw->mac_type == em_80003es2lan)) { |
| 5185 | /* Select Configuration Page */ |
| 5186 | if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) < |
| 5187 | GG82563_MIN_ALT_REG30) { |
| 5188 | ret_val = em_write_phy_reg_ex(hw, |
| 5189 | GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)), |
| 5190 | (uint16_t) ((uint16_t) reg_addr >> |
| 5191 | GG82563_PAGE_SHIFT5)); |
| 5192 | } else { |
| 5193 | /* |
| 5194 | * Use Alternative Page Select register to |
| 5195 | * access registers 30 and 31 |
| 5196 | */ |
| 5197 | ret_val = em_write_phy_reg_ex(hw, |
| 5198 | GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)), |
| 5199 | (uint16_t) ((uint16_t) reg_addr >> |
| 5200 | GG82563_PAGE_SHIFT5)); |
| 5201 | } |
| 5202 | |
| 5203 | if (ret_val) { |
| 5204 | em_swfw_sync_release(hw, swfw); |
| 5205 | return ret_val; |
| 5206 | } |
| 5207 | } |
| 5208 | } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { |
| 5209 | if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) { |
| 5210 | ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22, |
| 5211 | (uint16_t) ((uint16_t) reg_addr >> |
| 5212 | PHY_PAGE_SHIFT5)); |
| 5213 | if (ret_val) |
| 5214 | return ret_val; |
| 5215 | } |
| 5216 | } |
| 5217 | ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr, |
| 5218 | phy_data); |
| 5219 | |
| 5220 | em_swfw_sync_release(hw, swfw); |
| 5221 | return ret_val; |
| 5222 | } |
| 5223 | |
| 5224 | STATIC int32_t |
| 5225 | em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) |
| 5226 | { |
| 5227 | uint32_t i; |
| 5228 | uint32_t mdic = 0; |
| 5229 | DEBUGFUNC("em_read_phy_reg_ex");; |
| 5230 | |
| 5231 | /* SGMII active is only set on some specific chips */ |
| 5232 | if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { |
| 5233 | if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) { |
| 5234 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 5235 | return -E1000_ERR_PARAM4; |
| 5236 | } |
| 5237 | return em_read_phy_reg_i2c(hw, reg_addr, phy_data); |
| 5238 | } |
| 5239 | if (reg_addr > MAX_PHY_REG_ADDRESS0x1F) { |
| 5240 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 5241 | return -E1000_ERR_PARAM4; |
| 5242 | } |
| 5243 | if (hw->mac_type == em_icp_xxxx) { |
| 5244 | *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, |
| 5245 | reg_addr); |
| 5246 | return E1000_SUCCESS0; |
| 5247 | } |
| 5248 | if (hw->mac_type > em_82543) { |
| 5249 | /* |
| 5250 | * Set up Op-code, Phy Address, and register address in the |
| 5251 | * MDI Control register. The MAC will take care of |
| 5252 | * interfacing with the PHY to retrieve the desired data. |
| 5253 | */ |
| 5254 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT16) | |
| 5255 | (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) | |
| 5256 | (E1000_MDIC_OP_READ0x08000000)); |
| 5257 | |
| 5258 | E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register (0x00020))), (mdic))); |
| 5259 | |
| 5260 | /* |
| 5261 | * Poll the ready bit to see if the MDI read completed |
| 5262 | * Increasing the time out as testing showed failures with |
| 5263 | * the lower time out (from FreeBSD driver) |
| 5264 | */ |
| 5265 | for (i = 0; i < 1960; i++) { |
| 5266 | usec_delay(50)(*delay_func)(50); |
| 5267 | mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register (0x00020))))); |
| 5268 | if (mdic & E1000_MDIC_READY0x10000000) |
| 5269 | break; |
| 5270 | } |
| 5271 | if (!(mdic & E1000_MDIC_READY0x10000000)) { |
| 5272 | DEBUGOUT("MDI Read did not complete\n"); |
| 5273 | return -E1000_ERR_PHY2; |
| 5274 | } |
| 5275 | if (mdic & E1000_MDIC_ERROR0x40000000) { |
| 5276 | DEBUGOUT("MDI Error\n"); |
| 5277 | return -E1000_ERR_PHY2; |
| 5278 | } |
| 5279 | *phy_data = (uint16_t) mdic; |
| 5280 | |
| 5281 | if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || |
| 5282 | hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || |
| 5283 | hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp) |
| 5284 | usec_delay(100)(*delay_func)(100); |
| 5285 | } else { |
| 5286 | /* |
| 5287 | * We must first send a preamble through the MDIO pin to |
| 5288 | * signal the beginning of an MII instruction. This is done |
| 5289 | * by sending 32 consecutive "1" bits. |
| 5290 | */ |
| 5291 | em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32); |
| 5292 | /* |
| 5293 | * Now combine the next few fields that are required for a |
| 5294 | * read operation. We use this method instead of calling the |
| 5295 | * em_shift_out_mdi_bits routine five different times. The |
| 5296 | * format of a MII read instruction consists of a shift out |
| 5297 | * of 14 bits and is defined as follows: <Preamble><SOF><Op |
| 5298 | * Code><Phy Addr><Reg Addr> followed by a shift in of 18 |
| 5299 | * bits. This first two bits shifted in are TurnAround bits |
| 5300 | * used to avoid contention on the MDIO pin when a READ |
| 5301 | * operation is performed. These two bits are thrown away |
| 5302 | * followed by a shift in of 16 bits which contains the |
| 5303 | * desired data. |
| 5304 | */ |
| 5305 | mdic = ((reg_addr) | (hw->phy_addr << 5) | |
| 5306 | (PHY_OP_READ0x02 << 10) | (PHY_SOF0x01 << 12)); |
| 5307 | |
| 5308 | em_shift_out_mdi_bits(hw, mdic, 14); |
| 5309 | /* |
| 5310 | * Now that we've shifted out the read command to the MII, we |
| 5311 | * need to "shift in" the 16-bit value (18 total bits) of the |
| 5312 | * requested PHY register address. |
| 5313 | */ |
| 5314 | *phy_data = em_shift_in_mdi_bits(hw); |
| 5315 | } |
| 5316 | return E1000_SUCCESS0; |
| 5317 | } |
| 5318 | |
| 5319 | /****************************************************************************** |
| 5320 | * Writes a value to a PHY register |
| 5321 | * |
| 5322 | * hw - Struct containing variables accessed by shared code |
| 5323 | * reg_addr - address of the PHY register to write |
| 5324 | * data - data to write to the PHY |
| 5325 | *****************************************************************************/ |
| 5326 | int32_t |
| 5327 | em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) |
| 5328 | { |
| 5329 | uint32_t ret_val; |
| 5330 | DEBUGFUNC("em_write_phy_reg");; |
| 5331 | |
| 5332 | if (hw->mac_type == em_pchlan || |
| 5333 | hw->mac_type == em_pch2lan || |
| 5334 | hw->mac_type == em_pch_lpt || |
| 5335 | hw->mac_type == em_pch_spt || |
| 5336 | hw->mac_type == em_pch_cnp || |
| 5337 | hw->mac_type == em_pch_tgp || |
| 5338 | hw->mac_type == em_pch_adp) |
| 5339 | return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE0)); |
| 5340 | |
| 5341 | if (em_swfw_sync_acquire(hw, hw->swfw)) |
| 5342 | return -E1000_ERR_SWFW_SYNC13; |
| 5343 | |
| 5344 | if ((hw->phy_type == em_phy_igp || |
| 5345 | hw->phy_type == em_phy_igp_3 || |
| 5346 | hw->phy_type == em_phy_igp_2) && |
| 5347 | (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) { |
| 5348 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, |
| 5349 | (uint16_t) reg_addr); |
| 5350 | if (ret_val) { |
| 5351 | em_swfw_sync_release(hw, hw->swfw); |
| 5352 | return ret_val; |
| 5353 | } |
| 5354 | } else if (hw->phy_type == em_phy_gg82563) { |
| 5355 | if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) || |
| 5356 | (hw->mac_type == em_80003es2lan)) { |
| 5357 | /* Select Configuration Page */ |
| 5358 | if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) < |
| 5359 | GG82563_MIN_ALT_REG30) { |
| 5360 | ret_val = em_write_phy_reg_ex(hw, |
| 5361 | GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)), |
| 5362 | (uint16_t) ((uint16_t) reg_addr >> |
| 5363 | GG82563_PAGE_SHIFT5)); |
| 5364 | } else { |
| 5365 | /* |
| 5366 | * Use Alternative Page Select register to |
| 5367 | * access registers 30 and 31 |
| 5368 | */ |
| 5369 | ret_val = em_write_phy_reg_ex(hw, |
| 5370 | GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)), |
| 5371 | (uint16_t) ((uint16_t) reg_addr >> |
| 5372 | GG82563_PAGE_SHIFT5)); |
| 5373 | } |
| 5374 | |
| 5375 | if (ret_val) { |
| 5376 | em_swfw_sync_release(hw, hw->swfw); |
| 5377 | return ret_val; |
| 5378 | } |
| 5379 | } |
| 5380 | } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { |
| 5381 | if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) { |
| 5382 | ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22, |
| 5383 | (uint16_t) ((uint16_t) reg_addr >> |
| 5384 | PHY_PAGE_SHIFT5)); |
| 5385 | if (ret_val) |
| 5386 | return ret_val; |
| 5387 | } |
| 5388 | } |
| 5389 | ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr, |
| 5390 | phy_data); |
| 5391 | |
| 5392 | em_swfw_sync_release(hw, hw->swfw); |
| 5393 | return ret_val; |
| 5394 | } |
| 5395 | |
| 5396 | STATIC int32_t |
| 5397 | em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) |
| 5398 | { |
| 5399 | uint32_t i; |
| 5400 | uint32_t mdic = 0; |
| 5401 | DEBUGFUNC("em_write_phy_reg_ex");; |
| 5402 | |
| 5403 | /* SGMII active is only set on some specific chips */ |
| 5404 | if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { |
| 5405 | if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) { |
| 5406 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 5407 | return -E1000_ERR_PARAM4; |
| 5408 | } |
| 5409 | return em_write_phy_reg_i2c(hw, reg_addr, phy_data); |
| 5410 | } |
| 5411 | if (reg_addr > MAX_PHY_REG_ADDRESS0x1F) { |
| 5412 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 5413 | return -E1000_ERR_PARAM4; |
| 5414 | } |
| 5415 | if (hw->mac_type == em_icp_xxxx) { |
| 5416 | gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, |
| 5417 | reg_addr, phy_data); |
| 5418 | return E1000_SUCCESS0; |
| 5419 | } |
| 5420 | if (hw->mac_type > em_82543) { |
| 5421 | /* |
| 5422 | * Set up Op-code, Phy Address, register address, and data |
| 5423 | * intended for the PHY register in the MDI Control register. |
| 5424 | * The MAC will take care of interfacing with the PHY to send |
| 5425 | * the desired data. |
| 5426 | */ |
| 5427 | mdic = (((uint32_t) phy_data) | |
| 5428 | (reg_addr << E1000_MDIC_REG_SHIFT16) | |
| 5429 | (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) | |
| 5430 | (E1000_MDIC_OP_WRITE0x04000000)); |
| 5431 | |
| 5432 | E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register (0x00020))), (mdic))); |
| 5433 | |
| 5434 | /* Poll the ready bit to see if the MDI read completed */ |
| 5435 | for (i = 0; i < 641; i++) { |
| 5436 | usec_delay(5)(*delay_func)(5); |
| 5437 | mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register (0x00020))))); |
| 5438 | if (mdic & E1000_MDIC_READY0x10000000) |
| 5439 | break; |
| 5440 | } |
| 5441 | if (!(mdic & E1000_MDIC_READY0x10000000)) { |
| 5442 | DEBUGOUT("MDI Write did not complete\n"); |
| 5443 | return -E1000_ERR_PHY2; |
| 5444 | } |
| 5445 | |
| 5446 | if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || |
| 5447 | hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || |
| 5448 | hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp) |
| 5449 | usec_delay(100)(*delay_func)(100); |
| 5450 | } else { |
| 5451 | /* |
| 5452 | * We'll need to use the SW defined pins to shift the write |
| 5453 | * command out to the PHY. We first send a preamble to the |
| 5454 | * PHY to signal the beginning of the MII instruction. This |
| 5455 | * is done by sending 32 consecutive "1" bits. |
| 5456 | */ |
| 5457 | em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32); |
| 5458 | /* |
| 5459 | * Now combine the remaining required fields that will |
| 5460 | * indicate a write operation. We use this method instead of |
| 5461 | * calling the em_shift_out_mdi_bits routine for each field |
| 5462 | * in the command. The format of a MII write instruction is |
| 5463 | * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg |
| 5464 | * Addr><Turnaround><Data>. |
| 5465 | */ |
| 5466 | mdic = ((PHY_TURNAROUND0x02) | (reg_addr << 2) | |
| 5467 | (hw->phy_addr << 7) | (PHY_OP_WRITE0x01 << 12) | |
| 5468 | (PHY_SOF0x01 << 14)); |
| 5469 | mdic <<= 16; |
| 5470 | mdic |= (uint32_t) phy_data; |
| 5471 | |
| 5472 | em_shift_out_mdi_bits(hw, mdic, 32); |
| 5473 | } |
| 5474 | |
| 5475 | return E1000_SUCCESS0; |
| 5476 | } |
| 5477 | |
| 5478 | STATIC int32_t |
| 5479 | em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) |
| 5480 | { |
| 5481 | uint32_t reg_val; |
| 5482 | DEBUGFUNC("em_read_kmrn_reg");; |
| 5483 | |
| 5484 | if (em_swfw_sync_acquire(hw, hw->swfw)) |
| 5485 | return -E1000_ERR_SWFW_SYNC13; |
| 5486 | |
| 5487 | /* Write register address */ |
| 5488 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) & |
| 5489 | E1000_KUMCTRLSTA_OFFSET0x001F0000) | |
| 5490 | E1000_KUMCTRLSTA_REN0x00200000; |
| 5491 | |
| 5492 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register (0x00034))), (reg_val))); |
| 5493 | usec_delay(2)(*delay_func)(2); |
| 5494 | |
| 5495 | /* Read the data returned */ |
| 5496 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register (0x00034))))); |
| 5497 | *data = (uint16_t) reg_val; |
| 5498 | |
| 5499 | em_swfw_sync_release(hw, hw->swfw); |
| 5500 | return E1000_SUCCESS0; |
| 5501 | } |
| 5502 | |
| 5503 | STATIC int32_t |
| 5504 | em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) |
| 5505 | { |
| 5506 | uint32_t reg_val; |
| 5507 | DEBUGFUNC("em_write_kmrn_reg");; |
| 5508 | |
| 5509 | if (em_swfw_sync_acquire(hw, hw->swfw)) |
| 5510 | return -E1000_ERR_SWFW_SYNC13; |
| 5511 | |
| 5512 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) & |
| 5513 | E1000_KUMCTRLSTA_OFFSET0x001F0000) | data; |
| 5514 | |
| 5515 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register (0x00034))), (reg_val))); |
| 5516 | usec_delay(2)(*delay_func)(2); |
| 5517 | |
| 5518 | em_swfw_sync_release(hw, hw->swfw); |
| 5519 | return E1000_SUCCESS0; |
| 5520 | } |
| 5521 | |
| 5522 | /** |
| 5523 | * em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO |
| 5524 | * @hw: pointer to the HW structure |
| 5525 | * |
| 5526 | * Called to determine if the I2C pins are being used for I2C or as an |
| 5527 | * external MDIO interface since the two options are mutually exclusive. |
| 5528 | **/ |
| 5529 | int em_sgmii_uses_mdio_82575(struct em_hw *hw) |
| 5530 | { |
| 5531 | uint32_t reg = 0; |
| 5532 | int ext_mdio = 0; |
| 5533 | |
| 5534 | DEBUGFUNC("em_sgmii_uses_mdio_82575");; |
| 5535 | |
| 5536 | switch (hw->mac_type) { |
| 5537 | case em_82575: |
| 5538 | case em_82576: |
| 5539 | reg = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register (0x00020))))); |
| 5540 | ext_mdio = !!(reg & E1000_MDIC_DEST0x80000000); |
| 5541 | break; |
| 5542 | case em_82580: |
| 5543 | case em_i350: |
| 5544 | case em_i210: |
| 5545 | reg = E1000_READ_REG(hw, MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x00E04 : em_translate_82542_register (0x00E04))))); |
| 5546 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO0x80000000); |
| 5547 | break; |
| 5548 | default: |
| 5549 | break; |
| 5550 | } |
| 5551 | return ext_mdio; |
| 5552 | } |
| 5553 | |
| 5554 | /** |
| 5555 | * em_read_phy_reg_i2c - Read PHY register using i2c |
| 5556 | * @hw: pointer to the HW structure |
| 5557 | * @offset: register offset to be read |
| 5558 | * @data: pointer to the read data |
| 5559 | * |
| 5560 | * Reads the PHY register at offset using the i2c interface and stores the |
| 5561 | * retrieved information in data. |
| 5562 | **/ |
| 5563 | int32_t em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data) |
| 5564 | { |
| 5565 | uint32_t i, i2ccmd = 0; |
| 5566 | |
| 5567 | DEBUGFUNC("em_read_phy_reg_i2c");; |
| 5568 | |
| 5569 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
| 5570 | * register. The MAC will take care of interfacing with the |
| 5571 | * PHY to retrieve the desired data. |
| 5572 | */ |
| 5573 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) | |
| 5574 | (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) | |
| 5575 | (E1000_I2CCMD_OPCODE_READ0x08000000)); |
| 5576 | |
| 5577 | E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register (0x01028))), (i2ccmd))); |
| 5578 | |
| 5579 | /* Poll the ready bit to see if the I2C read completed */ |
| 5580 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) { |
| 5581 | usec_delay(50)(*delay_func)(50); |
| 5582 | i2ccmd = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register (0x01028))))); |
| 5583 | if (i2ccmd & E1000_I2CCMD_READY0x20000000) |
| 5584 | break; |
| 5585 | } |
| 5586 | if (!(i2ccmd & E1000_I2CCMD_READY0x20000000)) { |
| 5587 | DEBUGOUT("I2CCMD Read did not complete\n"); |
| 5588 | return -E1000_ERR_PHY2; |
| 5589 | } |
| 5590 | if (i2ccmd & E1000_I2CCMD_ERROR0x80000000) { |
| 5591 | DEBUGOUT("I2CCMD Error bit set\n"); |
| 5592 | return -E1000_ERR_PHY2; |
| 5593 | } |
| 5594 | |
| 5595 | /* Need to byte-swap the 16-bit value. */ |
| 5596 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); |
| 5597 | |
| 5598 | return E1000_SUCCESS0; |
| 5599 | } |
| 5600 | |
| 5601 | /** |
| 5602 | * em_write_phy_reg_i2c - Write PHY register using i2c |
| 5603 | * @hw: pointer to the HW structure |
| 5604 | * @offset: register offset to write to |
| 5605 | * @data: data to write at register offset |
| 5606 | * |
| 5607 | * Writes the data to PHY register at the offset using the i2c interface. |
| 5608 | **/ |
| 5609 | int32_t em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data) |
| 5610 | { |
| 5611 | uint32_t i, i2ccmd = 0; |
| 5612 | uint16_t phy_data_swapped; |
| 5613 | |
| 5614 | DEBUGFUNC("em_write_phy_reg_i2c");; |
| 5615 | |
| 5616 | /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/ |
| 5617 | if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) { |
| 5618 | DEBUGOUT1("PHY I2C Address %d is out of range.\n", |
| 5619 | hw->phy_addr); |
| 5620 | return -E1000_ERR_CONFIG3; |
| 5621 | } |
| 5622 | |
| 5623 | /* Swap the data bytes for the I2C interface */ |
| 5624 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); |
| 5625 | |
| 5626 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
| 5627 | * register. The MAC will take care of interfacing with the |
| 5628 | * PHY to retrieve the desired data. |
| 5629 | */ |
| 5630 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) | |
| 5631 | (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) | |
| 5632 | E1000_I2CCMD_OPCODE_WRITE0x00000000 | |
| 5633 | phy_data_swapped); |
| 5634 | |
| 5635 | E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)-> write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle ), (((hw)->mac_type >= em_82543 ? 0x01028 : em_ |