Bug Summary

File:dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
Warning:line 365, column 2
Value stored to 'misc0' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dcn10_stream_encoder.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc_bios_types.h"
28#include "dcn10_stream_encoder.h"
29#include "reg_helper.h"
30#include "hw_shared.h"
31#include "inc/link_dpcd.h"
32#include "dpcd_defs.h"
33#include "dcn30/dcn30_afmt.h"
34
35#define DC_LOGGERenc1->base.ctx->logger \
36 enc1->base.ctx->logger
37
38#define REG(reg)(enc1->regs->reg)\
39 (enc1->regs->reg)
40
41#undef FN
42#define FN(reg_name, field_name)enc1->se_shift->field_name, enc1->se_mask->field_name \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45#define VBI_LINE_00 0
46#define DP_BLANK_MAX_RETRY20 20
47#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M340000 340000
48
49
50enum {
51 DP_MST_UPDATE_MAX_RETRY = 50
52};
53
54#define CTXenc1->base.ctx \
55 enc1->base.ctx
56
57void enc1_update_generic_info_packet(
58 struct dcn10_stream_encoder *enc1,
59 uint32_t packet_index,
60 const struct dc_info_packet *info_packet)
61{
62 /* TODOFPGA Figure out a proper number for max_retries polling for lock
63 * use 50 for now.
64 */
65 uint32_t max_retries = 50;
66
67 /*we need turn on clock before programming AFMT block*/
68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_CNTL
), 1, enc1->se_shift->AFMT_AUDIO_CLOCK_EN, enc1->se_mask
->AFMT_AUDIO_CLOCK_EN, 1);
69
70 if (packet_index >= 8)
71 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c"
, 71); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
72
73 /* poll dig_update_lock is not locked -> asic internal signal
74 * assume otg master lock will unlock it
75 */
76/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
77 0, 10, max_retries);*/
78
79 /* check if HW reading GSP memory */
80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), enc1->se_shift->AFMT_GENERIC_CONFLICT, enc1->se_mask
->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__, 81)
81 0, 10, max_retries)generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), enc1->se_shift->AFMT_GENERIC_CONFLICT, enc1->se_mask
->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__, 81);
82
83 /* HW does is not reading GSP memory not reading too long ->
84 * something wrong. clear GPS memory access and notify?
85 * hw SW is writing to GSP memory
86 */
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_CONFLICT_CLR, enc1->
se_mask->AFMT_GENERIC_CONFLICT_CLR, 1);
88
89 /* choose which generic packet to use */
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_INDEX, enc1->se_mask
->AFMT_GENERIC_INDEX, packet_index)
91 AFMT_GENERIC_INDEX, packet_index)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_INDEX, enc1->se_mask
->AFMT_GENERIC_INDEX, packet_index);
92
93 /* write generic packet header
94 * (4th byte is for GENERIC0 only)
95 */
96 REG_SET_4(AFMT_GENERIC_HDR, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, info_packet->hb0, enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
info_packet->hb1, enc1->se_shift->AFMT_GENERIC_HB2,
enc1->se_mask->AFMT_GENERIC_HB2, info_packet->hb2, enc1
->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->AFMT_GENERIC_HB3
, info_packet->hb3)
97 AFMT_GENERIC_HB0, info_packet->hb0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, info_packet->hb0, enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
info_packet->hb1, enc1->se_shift->AFMT_GENERIC_HB2,
enc1->se_mask->AFMT_GENERIC_HB2, info_packet->hb2, enc1
->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->AFMT_GENERIC_HB3
, info_packet->hb3)
98 AFMT_GENERIC_HB1, info_packet->hb1,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, info_packet->hb0, enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
info_packet->hb1, enc1->se_shift->AFMT_GENERIC_HB2,
enc1->se_mask->AFMT_GENERIC_HB2, info_packet->hb2, enc1
->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->AFMT_GENERIC_HB3
, info_packet->hb3)
99 AFMT_GENERIC_HB2, info_packet->hb2,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, info_packet->hb0, enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
info_packet->hb1, enc1->se_shift->AFMT_GENERIC_HB2,
enc1->se_mask->AFMT_GENERIC_HB2, info_packet->hb2, enc1
->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->AFMT_GENERIC_HB3
, info_packet->hb3)
100 AFMT_GENERIC_HB3, info_packet->hb3)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, info_packet->hb0, enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
info_packet->hb1, enc1->se_shift->AFMT_GENERIC_HB2,
enc1->se_mask->AFMT_GENERIC_HB2, info_packet->hb2, enc1
->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->AFMT_GENERIC_HB3
, info_packet->hb3);
101
102 /* write generic packet contents
103 * (we never use last 4 bytes)
104 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
105 */
106 {
107 const uint32_t *content =
108 (const uint32_t *) &info_packet->sb[0];
109
110 REG_WRITE(AFMT_GENERIC_0, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_0
), *content++, __func__);
111 REG_WRITE(AFMT_GENERIC_1, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_1
), *content++, __func__);
112 REG_WRITE(AFMT_GENERIC_2, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_2
), *content++, __func__);
113 REG_WRITE(AFMT_GENERIC_3, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_3
), *content++, __func__);
114 REG_WRITE(AFMT_GENERIC_4, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_4
), *content++, __func__);
115 REG_WRITE(AFMT_GENERIC_5, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_5
), *content++, __func__);
116 REG_WRITE(AFMT_GENERIC_6, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_6
), *content++, __func__);
117 REG_WRITE(AFMT_GENERIC_7, *content)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_7
), *content, __func__);
118 }
119
120 switch (packet_index) {
121 case 0:
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC0_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC0_IMMEDIATE_UPDATE, 1)
123 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC0_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
124 break;
125 case 1:
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC1_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC1_IMMEDIATE_UPDATE, 1)
127 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC1_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
128 break;
129 case 2:
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC2_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC2_IMMEDIATE_UPDATE, 1)
131 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC2_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
132 break;
133 case 3:
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC3_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC3_IMMEDIATE_UPDATE, 1)
135 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC3_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
136 break;
137 case 4:
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE, 1)
139 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
140 break;
141 case 5:
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC5_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC5_IMMEDIATE_UPDATE, 1)
143 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC5_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
144 break;
145 case 6:
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC6_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC6_IMMEDIATE_UPDATE, 1)
147 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC6_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
148 break;
149 case 7:
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC7_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC7_IMMEDIATE_UPDATE, 1)
151 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC7_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
152 break;
153 default:
154 break;
155 }
156}
157
158static void enc1_update_hdmi_info_packet(
159 struct dcn10_stream_encoder *enc1,
160 uint32_t packet_index,
161 const struct dc_info_packet *info_packet)
162{
163 uint32_t cont, send, line;
164
165 if (info_packet->valid) {
166 enc1_update_generic_info_packet(
167 enc1,
168 packet_index,
169 info_packet);
170
171 /* enable transmission of packet(s) -
172 * packet transmission begins on the next frame
173 */
174 cont = 1;
175 /* send packet(s) every frame */
176 send = 1;
177 /* select line number to send packets on */
178 line = 2;
179 } else {
180 cont = 0;
181 send = 0;
182 line = 0;
183 }
184
185 /* choose which generic packet control to use */
186 switch (packet_index) {
187 case 0:
188 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
189 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
190 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
191 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line);
192 break;
193 case 1:
194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
195 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
196 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
197 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line);
198 break;
199 case 2:
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
201 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
202 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
203 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line);
204 break;
205 case 3:
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
207 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
208 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
209 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line);
210 break;
211 case 4:
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
213 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
214 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
215 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line);
216 break;
217 case 5:
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
219 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
220 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
221 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line);
222 break;
223 case 6:
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
225 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
226 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line)
227 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, cont, enc1->se_shift->HDMI_GENERIC0_SEND
, enc1->se_mask->HDMI_GENERIC0_SEND, send, enc1->se_shift
->HDMI_GENERIC0_LINE, enc1->se_mask->HDMI_GENERIC0_LINE
, line);
228 break;
229 case 7:
230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
231 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
232 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line)
233 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 3, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, cont, enc1->se_shift->HDMI_GENERIC1_SEND
, enc1->se_mask->HDMI_GENERIC1_SEND, send, enc1->se_shift
->HDMI_GENERIC1_LINE, enc1->se_mask->HDMI_GENERIC1_LINE
, line);
234 break;
235 default:
236 /* invalid HW packet index */
237 DC_LOG_WARNING(printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__)
238 "Invalid HW packet index: %s()\n",printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__)
239 __func__)printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__);
240 return;
241 }
242}
243
244/* setup stream encoder in dp mode */
245void enc1_stream_encoder_dp_set_stream_attribute(
246 struct stream_encoder *enc,
247 struct dc_crtc_timing *crtc_timing,
248 enum dc_color_space output_color_space,
249 bool_Bool use_vsc_sdp_for_colorimetry,
250 uint32_t enable_sdp_splitting)
251{
252 uint32_t h_active_start;
253 uint32_t v_active_start;
254 uint32_t misc0 = 0;
255 uint32_t misc1 = 0;
256 uint32_t h_blank;
257 uint32_t h_back_porch;
258 uint8_t synchronous_clock = 0; /* asynchronous mode */
259 uint8_t colorimetry_bpc;
260 uint8_t dp_pixel_encoding = 0;
261 uint8_t dp_component_depth = 0;
262
263 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
264 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
265
266 if (hw_crtc_timing.flags.INTERLACE) {
267 /*the input timing is in VESA spec format with Interlace flag =1*/
268 hw_crtc_timing.v_total /= 2;
269 hw_crtc_timing.v_border_top /= 2;
270 hw_crtc_timing.v_addressable /= 2;
271 hw_crtc_timing.v_border_bottom /= 2;
272 hw_crtc_timing.v_front_porch /= 2;
273 hw_crtc_timing.v_sync_width /= 2;
274 }
275
276
277 /* set pixel encoding */
278 switch (hw_crtc_timing.pixel_encoding) {
279 case PIXEL_ENCODING_YCBCR422:
280 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
281 break;
282 case PIXEL_ENCODING_YCBCR444:
283 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
284
285 if (hw_crtc_timing.flags.Y_ONLY)
286 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
287 /* HW testing only, no use case yet.
288 * Color depth of Y-only could be
289 * 8, 10, 12, 16 bits
290 */
291 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
292
293 /* Note: DP_MSA_MISC1 bit 7 is the indicator
294 * of Y-only mode.
295 * This bit is set in HW if register
296 * DP_PIXEL_ENCODING is programmed to 0x4
297 */
298 break;
299 case PIXEL_ENCODING_YCBCR420:
300 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
301 break;
302 default:
303 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
304 break;
305 }
306
307 misc1 = REG_READ(DP_MSA_MISC)dm_read_reg_func(enc1->base.ctx, (enc1->regs->DP_MSA_MISC
), __func__);
308 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
309 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
310 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
311 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
312 */
313 if (use_vsc_sdp_for_colorimetry)
314 misc1 = misc1 | 0x40;
315 else
316 misc1 = misc1 & ~0x40;
317
318 /* set color depth */
319 switch (hw_crtc_timing.display_color_depth) {
320 case COLOR_DEPTH_666:
321 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
322 break;
323 case COLOR_DEPTH_888:
324 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
325 break;
326 case COLOR_DEPTH_101010:
327 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
328 break;
329 case COLOR_DEPTH_121212:
330 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
331 break;
332 case COLOR_DEPTH_161616:
333 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
334 break;
335 default:
336 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
337 break;
338 }
339
340 /* Set DP pixel encoding and component depth */
341 REG_UPDATE_2(DP_PIXEL_FORMAT,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), 2, enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask
->DP_PIXEL_ENCODING, dp_pixel_encoding, enc1->se_shift->
DP_COMPONENT_DEPTH, enc1->se_mask->DP_COMPONENT_DEPTH, dp_component_depth
)
342 DP_PIXEL_ENCODING, dp_pixel_encoding,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), 2, enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask
->DP_PIXEL_ENCODING, dp_pixel_encoding, enc1->se_shift->
DP_COMPONENT_DEPTH, enc1->se_mask->DP_COMPONENT_DEPTH, dp_component_depth
)
343 DP_COMPONENT_DEPTH, dp_component_depth)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), 2, enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask
->DP_PIXEL_ENCODING, dp_pixel_encoding, enc1->se_shift->
DP_COMPONENT_DEPTH, enc1->se_mask->DP_COMPONENT_DEPTH, dp_component_depth
);
344
345 /* set dynamic range and YCbCr range */
346
347 switch (hw_crtc_timing.display_color_depth) {
348 case COLOR_DEPTH_666:
349 colorimetry_bpc = 0;
350 break;
351 case COLOR_DEPTH_888:
352 colorimetry_bpc = 1;
353 break;
354 case COLOR_DEPTH_101010:
355 colorimetry_bpc = 2;
356 break;
357 case COLOR_DEPTH_121212:
358 colorimetry_bpc = 3;
359 break;
360 default:
361 colorimetry_bpc = 0;
362 break;
363 }
364
365 misc0 = misc0 | synchronous_clock;
Value stored to 'misc0' is never read
366 misc0 = colorimetry_bpc << 5;
367
368 switch (output_color_space) {
369 case COLOR_SPACE_SRGB:
370 misc1 = misc1 & ~0x80; /* bit7 = 0*/
371 break;
372 case COLOR_SPACE_SRGB_LIMITED:
373 misc0 = misc0 | 0x8; /* bit3=1 */
374 misc1 = misc1 & ~0x80; /* bit7 = 0*/
375 break;
376 case COLOR_SPACE_YCBCR601:
377 case COLOR_SPACE_YCBCR601_LIMITED:
378 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
379 misc1 = misc1 & ~0x80; /* bit7 = 0*/
380 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
381 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
382 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
383 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
384 break;
385 case COLOR_SPACE_YCBCR709:
386 case COLOR_SPACE_YCBCR709_LIMITED:
387 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
388 misc1 = misc1 & ~0x80; /* bit7 = 0*/
389 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
390 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
391 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
392 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
393 break;
394 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
395 case COLOR_SPACE_2020_RGB_FULLRANGE:
396 case COLOR_SPACE_2020_YCBCR:
397 case COLOR_SPACE_XR_RGB:
398 case COLOR_SPACE_MSREF_SCRGB:
399 case COLOR_SPACE_ADOBERGB:
400 case COLOR_SPACE_DCIP3:
401 case COLOR_SPACE_XV_YCC_709:
402 case COLOR_SPACE_XV_YCC_601:
403 case COLOR_SPACE_DISPLAYNATIVE:
404 case COLOR_SPACE_DOLBYVISION:
405 case COLOR_SPACE_APPCTRL:
406 case COLOR_SPACE_CUSTOMPOINTS:
407 case COLOR_SPACE_UNKNOWN:
408 case COLOR_SPACE_YCBCR709_BLACK:
409 /* do nothing */
410 break;
411 }
412
413 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_COLORIMETRY
), 0, 1, enc1->se_shift->DP_MSA_MISC0, enc1->se_mask
->DP_MSA_MISC0, misc0);
414 REG_WRITE(DP_MSA_MISC, misc1)dm_write_reg_func(enc1->base.ctx, (enc1->regs->DP_MSA_MISC
), misc1, __func__); /* MSA_MISC1 */
415
416 /* dcn new register
417 * dc_crtc_timing is vesa dmt struct. data from edid
418 */
419 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM1
), 0, 2, enc1->se_shift->DP_MSA_HTOTAL, enc1->se_mask
->DP_MSA_HTOTAL, hw_crtc_timing.h_total, enc1->se_shift
->DP_MSA_VTOTAL, enc1->se_mask->DP_MSA_VTOTAL, hw_crtc_timing
.v_total)
420 DP_MSA_HTOTAL, hw_crtc_timing.h_total,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM1
), 0, 2, enc1->se_shift->DP_MSA_HTOTAL, enc1->se_mask
->DP_MSA_HTOTAL, hw_crtc_timing.h_total, enc1->se_shift
->DP_MSA_VTOTAL, enc1->se_mask->DP_MSA_VTOTAL, hw_crtc_timing
.v_total)
421 DP_MSA_VTOTAL, hw_crtc_timing.v_total)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM1
), 0, 2, enc1->se_shift->DP_MSA_HTOTAL, enc1->se_mask
->DP_MSA_HTOTAL, hw_crtc_timing.h_total, enc1->se_shift
->DP_MSA_VTOTAL, enc1->se_mask->DP_MSA_VTOTAL, hw_crtc_timing
.v_total);
422
423 /* calculate from vesa timing parameters
424 * h_active_start related to leading edge of sync
425 */
426
427 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
428 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
429
430 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
431 hw_crtc_timing.h_sync_width;
432
433 /* start at beginning of left border */
434 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
435
436
437 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
438 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
439 hw_crtc_timing.v_front_porch;
440
441
442 /* start at beginning of left border */
443 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM2
), 0, 2, enc1->se_shift->DP_MSA_HSTART, enc1->se_mask
->DP_MSA_HSTART, h_active_start, enc1->se_shift->DP_MSA_VSTART
, enc1->se_mask->DP_MSA_VSTART, v_active_start)
444 DP_MSA_HSTART, h_active_start,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM2
), 0, 2, enc1->se_shift->DP_MSA_HSTART, enc1->se_mask
->DP_MSA_HSTART, h_active_start, enc1->se_shift->DP_MSA_VSTART
, enc1->se_mask->DP_MSA_VSTART, v_active_start)
445 DP_MSA_VSTART, v_active_start)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM2
), 0, 2, enc1->se_shift->DP_MSA_HSTART, enc1->se_mask
->DP_MSA_HSTART, h_active_start, enc1->se_shift->DP_MSA_VSTART
, enc1->se_mask->DP_MSA_VSTART, v_active_start);
446
447 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
448 DP_MSA_HSYNCWIDTH,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
449 hw_crtc_timing.h_sync_width,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
450 DP_MSA_HSYNCPOLARITY,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
451 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
452 DP_MSA_VSYNCWIDTH,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
453 hw_crtc_timing.v_sync_width,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
454 DP_MSA_VSYNCPOLARITY,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY)
455 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM3
), 0, 4, enc1->se_shift->DP_MSA_HSYNCWIDTH, enc1->se_mask
->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width, enc1->
se_shift->DP_MSA_HSYNCPOLARITY, enc1->se_mask->DP_MSA_HSYNCPOLARITY
, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, enc1->se_shift
->DP_MSA_VSYNCWIDTH, enc1->se_mask->DP_MSA_VSYNCWIDTH
, hw_crtc_timing.v_sync_width, enc1->se_shift->DP_MSA_VSYNCPOLARITY
, enc1->se_mask->DP_MSA_VSYNCPOLARITY, !hw_crtc_timing.
flags.VSYNC_POSITIVE_POLARITY);
456
457 /* HWDITH include border or overscan */
458 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM4
), 0, 2, enc1->se_shift->DP_MSA_HWIDTH, enc1->se_mask
->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + hw_crtc_timing
.h_addressable + hw_crtc_timing.h_border_right, enc1->se_shift
->DP_MSA_VHEIGHT, enc1->se_mask->DP_MSA_VHEIGHT, hw_crtc_timing
.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing
.v_border_bottom)
459 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM4
), 0, 2, enc1->se_shift->DP_MSA_HWIDTH, enc1->se_mask
->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + hw_crtc_timing
.h_addressable + hw_crtc_timing.h_border_right, enc1->se_shift
->DP_MSA_VHEIGHT, enc1->se_mask->DP_MSA_VHEIGHT, hw_crtc_timing
.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing
.v_border_bottom)
460 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM4
), 0, 2, enc1->se_shift->DP_MSA_HWIDTH, enc1->se_mask
->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + hw_crtc_timing
.h_addressable + hw_crtc_timing.h_border_right, enc1->se_shift
->DP_MSA_VHEIGHT, enc1->se_mask->DP_MSA_VHEIGHT, hw_crtc_timing
.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing
.v_border_bottom)
461 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM4
), 0, 2, enc1->se_shift->DP_MSA_HWIDTH, enc1->se_mask
->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + hw_crtc_timing
.h_addressable + hw_crtc_timing.h_border_right, enc1->se_shift
->DP_MSA_VHEIGHT, enc1->se_mask->DP_MSA_VHEIGHT, hw_crtc_timing
.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing
.v_border_bottom)
462 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSA_TIMING_PARAM4
), 0, 2, enc1->se_shift->DP_MSA_HWIDTH, enc1->se_mask
->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + hw_crtc_timing
.h_addressable + hw_crtc_timing.h_border_right, enc1->se_shift
->DP_MSA_VHEIGHT, enc1->se_mask->DP_MSA_VHEIGHT, hw_crtc_timing
.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing
.v_border_bottom);
463}
464
465void enc1_stream_encoder_set_stream_attribute_helper(
466 struct dcn10_stream_encoder *enc1,
467 struct dc_crtc_timing *crtc_timing)
468{
469 switch (crtc_timing->pixel_encoding) {
470 case PIXEL_ENCODING_YCBCR422:
471 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->TMDS_PIXEL_ENCODING, enc1->se_mask
->TMDS_PIXEL_ENCODING, 1);
472 break;
473 default:
474 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->TMDS_PIXEL_ENCODING, enc1->se_mask
->TMDS_PIXEL_ENCODING, 0);
475 break;
476 }
477 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->TMDS_COLOR_FORMAT, enc1->se_mask
->TMDS_COLOR_FORMAT, 0);
478}
479
480/* setup stream encoder in hdmi mode */
481void enc1_stream_encoder_hdmi_set_stream_attribute(
482 struct stream_encoder *enc,
483 struct dc_crtc_timing *crtc_timing,
484 int actual_pix_clk_khz,
485 bool_Bool enable_audio)
486{
487 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
488 struct bp_encoder_control cntl = {0};
489
490 cntl.action = ENCODER_CONTROL_SETUP;
491 cntl.engine_id = enc1->base.id;
492 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
493 cntl.enable_dp_audio = enable_audio;
494 cntl.pixel_clock = actual_pix_clk_khz;
495 cntl.lanes_number = LANE_COUNT_FOUR;
496
497 if (enc1->base.bp->funcs->encoder_control(
498 enc1->base.bp, &cntl) != BP_RESULT_OK)
499 return;
500
501 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
502
503 /* setup HDMI engine */
504 REG_UPDATE_6(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
505 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
506 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
507 HDMI_DEEP_COLOR_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
508 HDMI_DATA_SCRAMBLE_EN, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
509 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
510 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 6, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_NO_EXTRA_NULL_PACKET_FILLED, enc1->se_mask->HDMI_NO_EXTRA_NULL_PACKET_FILLED
, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc1->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0);
511
512
513 switch (crtc_timing->display_color_depth) {
514 case COLOR_DEPTH_888:
515 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 1, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 0);
516 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source set to 24BPP deep color depth\n"
);
517 break;
518 case COLOR_DEPTH_101010:
519 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
520 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
521 HDMI_DEEP_COLOR_DEPTH, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
522 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0);
523 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 30BPP deep color depth"
"disabled for YCBCR422 pixel encoding\n")
524 "disabled for YCBCR422 pixel encoding\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 30BPP deep color depth"
"disabled for YCBCR422 pixel encoding\n");
525 } else {
526 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
527 HDMI_DEEP_COLOR_DEPTH, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
528 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 1, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1);
529 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 30BPP deep color depth"
"enabled for YCBCR422 non-pixel encoding\n")
530 "enabled for YCBCR422 non-pixel encoding\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 30BPP deep color depth"
"enabled for YCBCR422 non-pixel encoding\n");
531 }
532 break;
533 case COLOR_DEPTH_121212:
534 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
535 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
536 HDMI_DEEP_COLOR_DEPTH, 2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
537 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 0);
538 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 36BPP deep color depth"
"disabled for YCBCR422 pixel encoding\n")
539 "disabled for YCBCR422 pixel encoding\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 36BPP deep color depth"
"disabled for YCBCR422 pixel encoding\n");
540 } else {
541 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
542 HDMI_DEEP_COLOR_DEPTH, 2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
543 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 2, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1);
544 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 36BPP deep color depth"
"enabled for non-pixel YCBCR422 encoding\n")
545 "enabled for non-pixel YCBCR422 encoding\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source 36BPP deep color depth"
"enabled for non-pixel YCBCR422 encoding\n");
546 }
547 break;
548 case COLOR_DEPTH_161616:
549 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 3, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
550 HDMI_DEEP_COLOR_DEPTH, 3,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 3, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1)
551 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DEEP_COLOR_DEPTH, enc1->se_mask
->HDMI_DEEP_COLOR_DEPTH, 3, enc1->se_shift->HDMI_DEEP_COLOR_ENABLE
, enc1->se_mask->HDMI_DEEP_COLOR_ENABLE, 1);
552 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source deep color depth enabled in"
"reserved mode\n")
553 "reserved mode\n")___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI source deep color depth enabled in"
"reserved mode\n");
554 break;
555 default:
556 break;
557 }
558
559 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M340000) {
560 /* enable HDMI data scrambler
561 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
562 * Clock channel frequency is 1/4 of character rate.
563 */
564 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 1)
565 HDMI_DATA_SCRAMBLE_EN, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 1)
566 HDMI_CLOCK_CHANNEL_RATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 1);
567 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
568
569 /* TODO: New feature for DCE11, still need to implement */
570
571 /* enable HDMI data scrambler
572 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
573 * Clock channel frequency is the same
574 * as character rate
575 */
576 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
577 HDMI_DATA_SCRAMBLE_EN, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
578 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 2, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN, enc1->se_mask
->HDMI_DATA_SCRAMBLE_EN, 1, enc1->se_shift->HDMI_CLOCK_CHANNEL_RATE
, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE, 0);
579 }
580
581
582 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_VBI_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_GC_CONT, enc1->se_mask->
HDMI_GC_CONT, 1, enc1->se_shift->HDMI_GC_SEND, enc1->
se_mask->HDMI_GC_SEND, 1, enc1->se_shift->HDMI_NULL_SEND
, enc1->se_mask->HDMI_NULL_SEND, 1)
583 HDMI_GC_CONT, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_VBI_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_GC_CONT, enc1->se_mask->
HDMI_GC_CONT, 1, enc1->se_shift->HDMI_GC_SEND, enc1->
se_mask->HDMI_GC_SEND, 1, enc1->se_shift->HDMI_NULL_SEND
, enc1->se_mask->HDMI_NULL_SEND, 1)
584 HDMI_GC_SEND, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_VBI_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_GC_CONT, enc1->se_mask->
HDMI_GC_CONT, 1, enc1->se_shift->HDMI_GC_SEND, enc1->
se_mask->HDMI_GC_SEND, 1, enc1->se_shift->HDMI_NULL_SEND
, enc1->se_mask->HDMI_NULL_SEND, 1)
585 HDMI_NULL_SEND, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_VBI_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_GC_CONT, enc1->se_mask->
HDMI_GC_CONT, 1, enc1->se_shift->HDMI_GC_SEND, enc1->
se_mask->HDMI_GC_SEND, 1, enc1->se_shift->HDMI_NULL_SEND
, enc1->se_mask->HDMI_NULL_SEND, 1);
586
587 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_VBI_PACKET_CONTROL
), 1, enc1->se_shift->HDMI_ACP_SEND, enc1->se_mask->
HDMI_ACP_SEND, 0);
588
589 /* following belongs to audio */
590 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_INFOFRAME_CONTROL0
), 1, enc1->se_shift->HDMI_AUDIO_INFO_SEND, enc1->se_mask
->HDMI_AUDIO_INFO_SEND, 1);
591
592 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_INFOFRAME_CONTROL0
), 1, enc1->se_shift->AFMT_AUDIO_INFO_UPDATE, enc1->
se_mask->AFMT_AUDIO_INFO_UPDATE, 1);
593
594 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_INFOFRAME_CONTROL1
), 1, enc1->se_shift->HDMI_AUDIO_INFO_LINE, enc1->se_mask
->HDMI_AUDIO_INFO_LINE, 0 + 2)
595 VBI_LINE_0 + 2)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_INFOFRAME_CONTROL1
), 1, enc1->se_shift->HDMI_AUDIO_INFO_LINE, enc1->se_mask
->HDMI_AUDIO_INFO_LINE, 0 + 2);
596
597 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GC
), 1, enc1->se_shift->HDMI_GC_AVMUTE, enc1->se_mask->
HDMI_GC_AVMUTE, 0);
598}
599
600/* setup stream encoder in dvi mode */
601void enc1_stream_encoder_dvi_set_stream_attribute(
602 struct stream_encoder *enc,
603 struct dc_crtc_timing *crtc_timing,
604 bool_Bool is_dual_link)
605{
606 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
607 struct bp_encoder_control cntl = {0};
608
609 cntl.action = ENCODER_CONTROL_SETUP;
610 cntl.engine_id = enc1->base.id;
611 cntl.signal = is_dual_link ?
612 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
613 cntl.enable_dp_audio = false0;
614 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
615 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
616
617 if (enc1->base.bp->funcs->encoder_control(
618 enc1->base.bp, &cntl) != BP_RESULT_OK)
619 return;
620
621 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)do { if (({ static int __warned; int __ret = !!(!(crtc_timing
->pixel_encoding == PIXEL_ENCODING_RGB)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c"
, 621); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
622 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888)do { if (({ static int __warned; int __ret = !!(!(crtc_timing
->display_color_depth == COLOR_DEPTH_888)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(crtc_timing->display_color_depth == COLOR_DEPTH_888)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c"
, 622); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
623 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
624}
625
626void enc1_stream_encoder_set_throttled_vcp_size(
627 struct stream_encoder *enc,
628 struct fixed31_32 avg_time_slots_per_mtp)
629{
630 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
631 uint32_t x = dc_fixpt_floor(
632 avg_time_slots_per_mtp);
633 uint32_t y = dc_fixpt_ceil(
634 dc_fixpt_shl(
635 dc_fixpt_sub_int(
636 avg_time_slots_per_mtp,
637 x),
638 26));
639
640 // If y rounds up to integer, carry it over to x.
641 if (y >> 26) {
642 x += 1;
643 y = 0;
644 }
645
646 REG_SET_2(DP_MSE_RATE_CNTL, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_CNTL
), 0, 2, enc1->se_shift->DP_MSE_RATE_X, enc1->se_mask
->DP_MSE_RATE_X, x, enc1->se_shift->DP_MSE_RATE_Y, enc1
->se_mask->DP_MSE_RATE_Y, y)
647 DP_MSE_RATE_X, x,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_CNTL
), 0, 2, enc1->se_shift->DP_MSE_RATE_X, enc1->se_mask
->DP_MSE_RATE_X, x, enc1->se_shift->DP_MSE_RATE_Y, enc1
->se_mask->DP_MSE_RATE_Y, y)
648 DP_MSE_RATE_Y, y)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_CNTL
), 0, 2, enc1->se_shift->DP_MSE_RATE_X, enc1->se_mask
->DP_MSE_RATE_X, x, enc1->se_shift->DP_MSE_RATE_Y, enc1
->se_mask->DP_MSE_RATE_Y, y);
649
650 /* wait for update to be completed on the link */
651 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
652 /* is reset to 0 (not pending) */
653 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_UPDATE
), enc1->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc1->
se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 655)
654 0,generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_UPDATE
), enc1->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc1->
se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 655)
655 10, DP_MST_UPDATE_MAX_RETRY)generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_MSE_RATE_UPDATE
), enc1->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc1->
se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 655);
656}
657
658static void enc1_stream_encoder_update_hdmi_info_packets(
659 struct stream_encoder *enc,
660 const struct encoder_info_frame *info_frame)
661{
662 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
663
664 /* for bring up, disable dp double TODO */
665 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_DB_CONTROL
), 1, enc1->se_shift->HDMI_DB_DISABLE, enc1->se_mask
->HDMI_DB_DISABLE, 1);
666
667 /*Always add mandatory packets first followed by optional ones*/
668 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
669 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
670 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
671 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
672 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
673 enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
674}
675
676static void enc1_stream_encoder_stop_hdmi_info_packets(
677 struct stream_encoder *enc)
678{
679 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
680
681 /* stop generic packets 0 & 1 on HDMI */
682 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
683 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
684 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
685 HDMI_GENERIC1_SEND, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
686 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
687 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0)
688 HDMI_GENERIC0_SEND, 0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL0
), 0, 6, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0);
689
690 /* stop generic packets 2 & 3 on HDMI */
691 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
692 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
693 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
694 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
695 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
696 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
697 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL1
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0);
698
699 /* stop generic packets 2 & 3 on HDMI */
700 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
701 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
702 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
703 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
704 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
705 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
706 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL2
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0);
707
708 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
709 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
710 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
711 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
712 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
713 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0)
714 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->HDMI_GENERIC_PACKET_CONTROL3
), 0, 6, enc1->se_shift->HDMI_GENERIC0_CONT, enc1->se_mask
->HDMI_GENERIC0_CONT, 0, enc1->se_shift->HDMI_GENERIC0_LINE
, enc1->se_mask->HDMI_GENERIC0_LINE, 0, enc1->se_shift
->HDMI_GENERIC0_SEND, enc1->se_mask->HDMI_GENERIC0_SEND
, 0, enc1->se_shift->HDMI_GENERIC1_CONT, enc1->se_mask
->HDMI_GENERIC1_CONT, 0, enc1->se_shift->HDMI_GENERIC1_LINE
, enc1->se_mask->HDMI_GENERIC1_LINE, 0, enc1->se_shift
->HDMI_GENERIC1_SEND, enc1->se_mask->HDMI_GENERIC1_SEND
, 0);
715}
716
717void enc1_stream_encoder_update_dp_info_packets(
718 struct stream_encoder *enc,
719 const struct encoder_info_frame *info_frame)
720{
721 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
722 uint32_t value = 0;
723
724 if (info_frame->vsc.valid)
725 enc1_update_generic_info_packet(
726 enc1,
727 0, /* packetIndex */
728 &info_frame->vsc);
729
730 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
731 * Note that the enablement of GSP1 is not done below,
732 * it's done in FW.
733 */
734 if (info_frame->vsc.valid)
735 enc1_update_generic_info_packet(
736 enc1,
737 1, /* packetIndex */
738 &info_frame->vsc);
739
740 if (info_frame->spd.valid)
741 enc1_update_generic_info_packet(
742 enc1,
743 2, /* packetIndex */
744 &info_frame->spd);
745
746 if (info_frame->hdrsmd.valid)
747 enc1_update_generic_info_packet(
748 enc1,
749 3, /* packetIndex */
750 &info_frame->hdrsmd);
751
752 /* packetIndex 4 is used for send immediate sdp message, and please
753 * use other packetIndex (such as 5,6) for other info packet
754 */
755
756 /* enable/disable transmission of packet(s).
757 * If enabled, packet transmission begins on the next frame
758 */
759 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->se_mask
->DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
760 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_GSP2_ENABLE, enc1->se_mask
->DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
761 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
762
763 /* This bit is the master enable bit.
764 * When enabling secondary stream engine,
765 * this master bit must also be set.
766 * This register shared with audio info frame.
767 * Therefore we need to enable master bit
768 * if at least on of the fields is not 0
769 */
770 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), __func__);
771 if (value)
772 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 1);
773}
774
775void enc1_stream_encoder_send_immediate_sdp_message(
776 struct stream_encoder *enc,
777 const uint8_t *custom_sdp_message,
778 unsigned int sdp_message_size)
779{
780 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
781 uint32_t value = 0;
782
783 /* TODOFPGA Figure out a proper number for max_retries polling for lock
784 * use 50 for now.
785 */
786 uint32_t max_retries = 50;
787
788 /* check if GSP4 is transmitted */
789 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL2
), enc1->se_shift->DP_SEC_GSP4_SEND_PENDING, enc1->se_mask
->DP_SEC_GSP4_SEND_PENDING, 0, 10, max_retries, __func__, 790
)
790 0, 10, max_retries)generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL2
), enc1->se_shift->DP_SEC_GSP4_SEND_PENDING, enc1->se_mask
->DP_SEC_GSP4_SEND_PENDING, 0, 10, max_retries, __func__, 790
);
791
792 /* disable GSP4 transmitting */
793 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL2
), 1, enc1->se_shift->DP_SEC_GSP4_SEND, enc1->se_mask
->DP_SEC_GSP4_SEND, 0);
794
795 /* transmit GSP4 at the earliest time in a frame */
796 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL2
), 1, enc1->se_shift->DP_SEC_GSP4_SEND_ANY_LINE, enc1->
se_mask->DP_SEC_GSP4_SEND_ANY_LINE, 1);
797
798 /*we need turn on clock before programming AFMT block*/
799 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_CNTL
), 1, enc1->se_shift->AFMT_AUDIO_CLOCK_EN, enc1->se_mask
->AFMT_AUDIO_CLOCK_EN, 1);
800
801 /* check if HW reading GSP memory */
802 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), enc1->se_shift->AFMT_GENERIC_CONFLICT, enc1->se_mask
->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__, 803
)
803 0, 10, max_retries)generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), enc1->se_shift->AFMT_GENERIC_CONFLICT, enc1->se_mask
->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__, 803
);
804
805 /* HW does is not reading GSP memory not reading too long ->
806 * something wrong. clear GPS memory access and notify?
807 * hw SW is writing to GSP memory
808 */
809 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_CONFLICT_CLR, enc1->
se_mask->AFMT_GENERIC_CONFLICT_CLR, 1);
810
811 /* use generic packet 4 for immediate sdp message */
812 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_INDEX, enc1->se_mask
->AFMT_GENERIC_INDEX, 4)
813 AFMT_GENERIC_INDEX, 4)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_GENERIC_INDEX, enc1->se_mask
->AFMT_GENERIC_INDEX, 4);
814
815 /* write generic packet header
816 * (4th byte is for GENERIC0 only)
817 */
818 REG_SET_4(AFMT_GENERIC_HDR, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, custom_sdp_message[0], enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
custom_sdp_message[1], enc1->se_shift->AFMT_GENERIC_HB2
, enc1->se_mask->AFMT_GENERIC_HB2, custom_sdp_message[2
], enc1->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->
AFMT_GENERIC_HB3, custom_sdp_message[3])
819 AFMT_GENERIC_HB0, custom_sdp_message[0],generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, custom_sdp_message[0], enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
custom_sdp_message[1], enc1->se_shift->AFMT_GENERIC_HB2
, enc1->se_mask->AFMT_GENERIC_HB2, custom_sdp_message[2
], enc1->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->
AFMT_GENERIC_HB3, custom_sdp_message[3])
820 AFMT_GENERIC_HB1, custom_sdp_message[1],generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, custom_sdp_message[0], enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
custom_sdp_message[1], enc1->se_shift->AFMT_GENERIC_HB2
, enc1->se_mask->AFMT_GENERIC_HB2, custom_sdp_message[2
], enc1->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->
AFMT_GENERIC_HB3, custom_sdp_message[3])
821 AFMT_GENERIC_HB2, custom_sdp_message[2],generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, custom_sdp_message[0], enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
custom_sdp_message[1], enc1->se_shift->AFMT_GENERIC_HB2
, enc1->se_mask->AFMT_GENERIC_HB2, custom_sdp_message[2
], enc1->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->
AFMT_GENERIC_HB3, custom_sdp_message[3])
822 AFMT_GENERIC_HB3, custom_sdp_message[3])generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_HDR
), 0, 4, enc1->se_shift->AFMT_GENERIC_HB0, enc1->se_mask
->AFMT_GENERIC_HB0, custom_sdp_message[0], enc1->se_shift
->AFMT_GENERIC_HB1, enc1->se_mask->AFMT_GENERIC_HB1,
custom_sdp_message[1], enc1->se_shift->AFMT_GENERIC_HB2
, enc1->se_mask->AFMT_GENERIC_HB2, custom_sdp_message[2
], enc1->se_shift->AFMT_GENERIC_HB3, enc1->se_mask->
AFMT_GENERIC_HB3, custom_sdp_message[3]);
823
824 /* write generic packet contents
825 * (we never use last 4 bytes)
826 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
827 */
828 {
829 const uint32_t *content =
830 (const uint32_t *) &custom_sdp_message[4];
831
832 REG_WRITE(AFMT_GENERIC_0, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_0
), *content++, __func__);
833 REG_WRITE(AFMT_GENERIC_1, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_1
), *content++, __func__);
834 REG_WRITE(AFMT_GENERIC_2, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_2
), *content++, __func__);
835 REG_WRITE(AFMT_GENERIC_3, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_3
), *content++, __func__);
836 REG_WRITE(AFMT_GENERIC_4, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_4
), *content++, __func__);
837 REG_WRITE(AFMT_GENERIC_5, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_5
), *content++, __func__);
838 REG_WRITE(AFMT_GENERIC_6, *content++)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_6
), *content++, __func__);
839 REG_WRITE(AFMT_GENERIC_7, *content)dm_write_reg_func(enc1->base.ctx, (enc1->regs->AFMT_GENERIC_7
), *content, __func__);
840 }
841
842 /* check whether GENERIC4 registers double buffer update in immediate mode
843 * is pending
844 */
845 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING
, enc1->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING
, 0, 10, max_retries, __func__, 846)
846 0, 10, max_retries)generic_reg_wait(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING
, enc1->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING
, 0, 10, max_retries, __func__, 846);
847
848 /* atomically update double-buffered GENERIC4 registers in immediate mode
849 * (update immediately)
850 */
851 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE, 1)
852 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_VBI_PACKET_CONTROL1
), 1, enc1->se_shift->AFMT_GENERIC4_IMMEDIATE_UPDATE, enc1
->se_mask->AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
853
854 /* enable GSP4 transmitting */
855 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL2
), 1, enc1->se_shift->DP_SEC_GSP4_SEND, enc1->se_mask
->DP_SEC_GSP4_SEND, 1);
856
857 /* This bit is the master enable bit.
858 * When enabling secondary stream engine,
859 * this master bit must also be set.
860 * This register shared with audio info frame.
861 * Therefore we need to enable master bit
862 * if at least on of the fields is not 0
863 */
864 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), __func__);
865 if (value)
866 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 1);
867}
868
869void enc1_stream_encoder_stop_dp_info_packets(
870 struct stream_encoder *enc)
871{
872 /* stop generic packets on DP */
873 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
874 uint32_t value = 0;
875
876 REG_SET_10(DP_SEC_CNTL, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
877 DP_SEC_GSP0_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
878 DP_SEC_GSP1_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
879 DP_SEC_GSP2_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
880 DP_SEC_GSP3_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
881 DP_SEC_GSP4_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
882 DP_SEC_GSP5_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
883 DP_SEC_GSP6_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
884 DP_SEC_GSP7_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
885 DP_SEC_MPG_ENABLE, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0)
886 DP_SEC_STREAM_ENABLE, 0)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 0, 10, enc1->se_shift->DP_SEC_GSP0_ENABLE, enc1->
se_mask->DP_SEC_GSP0_ENABLE, 0, enc1->se_shift->DP_SEC_GSP1_ENABLE
, enc1->se_mask->DP_SEC_GSP1_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP2_ENABLE, enc1->se_mask->DP_SEC_GSP2_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP3_ENABLE, enc1->se_mask
->DP_SEC_GSP3_ENABLE, 0, enc1->se_shift->DP_SEC_GSP4_ENABLE
, enc1->se_mask->DP_SEC_GSP4_ENABLE, 0, enc1->se_shift
->DP_SEC_GSP5_ENABLE, enc1->se_mask->DP_SEC_GSP5_ENABLE
, 0, enc1->se_shift->DP_SEC_GSP6_ENABLE, enc1->se_mask
->DP_SEC_GSP6_ENABLE, 0, enc1->se_shift->DP_SEC_GSP7_ENABLE
, enc1->se_mask->DP_SEC_GSP7_ENABLE, 0, enc1->se_shift
->DP_SEC_MPG_ENABLE, enc1->se_mask->DP_SEC_MPG_ENABLE
, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 0);
887
888 /* this register shared with audio info frame.
889 * therefore we need to keep master enabled
890 * if at least one of the fields is not 0 */
891 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), __func__);
892 if (value)
893 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 1);
894
895}
896
897void enc1_stream_encoder_dp_blank(
898 struct dc_link *link,
899 struct stream_encoder *enc)
900{
901 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
902 uint32_t reg1 = 0;
903 uint32_t max_retries = DP_BLANK_MAX_RETRY20 * 10;
904
905 /* Note: For CZ, we are changing driver default to disable
906 * stream deferred to next VBLANK. If results are positive, we
907 * will make the same change to all DCE versions. There are a
908 * handful of panels that cannot handle disable stream at
909 * HBLANK and will result in a white line flash across the
910 * screen on stream disable.
911 */
912 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1)generic_reg_get(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), enc1->se_shift->DP_VID_STREAM_ENABLE, enc1->se_mask
->DP_VID_STREAM_ENABLE, &reg1);
913 if ((reg1 & 0x1) == 0)
914 /*stream not enabled*/
915 return;
916 /* Specify the video stream disable point
917 * (2 = start of the next vertical blank)
918 */
919 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), 1, enc1->se_shift->DP_VID_STREAM_DIS_DEFER, enc1->
se_mask->DP_VID_STREAM_DIS_DEFER, 2);
920 /* Larger delay to wait until VBLANK - use max retry of
921 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
922 * a little more because we may not trust delay accuracy.
923 */
924 max_retries = DP_BLANK_MAX_RETRY20 * 501;
925
926 /* disable DP stream */
927 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), 1, enc1->se_shift->DP_VID_STREAM_ENABLE, enc1->se_mask
->DP_VID_STREAM_ENABLE, 0);
928
929 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
930
931 /* the encoder stops sending the video stream
932 * at the start of the vertical blanking.
933 * Poll for DP_VID_STREAM_STATUS == 0
934 */
935
936 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), enc1->se_shift->DP_VID_STREAM_STATUS, enc1->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 938)
937 0,generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), enc1->se_shift->DP_VID_STREAM_STATUS, enc1->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 938)
938 10, max_retries)generic_reg_wait(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), enc1->se_shift->DP_VID_STREAM_STATUS, enc1->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 938);
939
940 /* Tell the DP encoder to ignore timing from CRTC, must be done after
941 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
942 * complete, stream status will be stuck in video stream enabled state,
943 * i.e. DP_VID_STREAM_STATUS stuck at 1.
944 */
945
946 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_STEER_FIFO
), 1, enc1->se_shift->DP_STEER_FIFO_RESET, enc1->se_mask
->DP_STEER_FIFO_RESET, 1);
947
948 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
949}
950
951/* output video stream to link encoder */
952void enc1_stream_encoder_dp_unblank(
953 struct dc_link *link,
954 struct stream_encoder *enc,
955 const struct encoder_unblank_param *param)
956{
957 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
958
959 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
960 uint32_t n_vid = 0x8000;
961 uint32_t m_vid;
962 uint32_t n_multiply = 0;
963 uint64_t m_vid_l = n_vid;
964
965 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
966 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
967 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
968 n_multiply = 1;
969 }
970 /* M / N = Fstream / Flink
971 * m_vid / n_vid = pixel rate / link rate
972 */
973
974 m_vid_l *= param->timing.pix_clk_100hz / 10;
975 m_vid_l = div_u64(m_vid_l,
976 param->link_settings.link_rate
977 * LINK_RATE_REF_FREQ_IN_KHZ);
978
979 m_vid = (uint32_t) m_vid_l;
980
981 /* enable auto measurement */
982
983 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_TIMING
), 1, enc1->se_shift->DP_VID_M_N_GEN_EN, enc1->se_mask
->DP_VID_M_N_GEN_EN, 0);
984
985 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
986 * therefore program initial value for Mvid and Nvid
987 */
988
989 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_N
), 1, enc1->se_shift->DP_VID_N, enc1->se_mask->DP_VID_N
, n_vid);
990
991 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_M
), 1, enc1->se_shift->DP_VID_M, enc1->se_mask->DP_VID_M
, m_vid);
992
993 REG_UPDATE_2(DP_VID_TIMING,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_TIMING
), 2, enc1->se_shift->DP_VID_M_N_GEN_EN, enc1->se_mask
->DP_VID_M_N_GEN_EN, 1, enc1->se_shift->DP_VID_N_MUL
, enc1->se_mask->DP_VID_N_MUL, n_multiply)
994 DP_VID_M_N_GEN_EN, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_TIMING
), 2, enc1->se_shift->DP_VID_M_N_GEN_EN, enc1->se_mask
->DP_VID_M_N_GEN_EN, 1, enc1->se_shift->DP_VID_N_MUL
, enc1->se_mask->DP_VID_N_MUL, n_multiply)
995 DP_VID_N_MUL, n_multiply)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_TIMING
), 2, enc1->se_shift->DP_VID_M_N_GEN_EN, enc1->se_mask
->DP_VID_M_N_GEN_EN, 1, enc1->se_shift->DP_VID_N_MUL
, enc1->se_mask->DP_VID_N_MUL, n_multiply);
996 }
997
998 /* set DIG_START to 0x1 to resync FIFO */
999
1000 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->DIG_START, enc1->se_mask->DIG_START
, 1);
1001
1002 /* switch DP encoder to CRTC data */
1003
1004 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_STEER_FIFO
), 1, enc1->se_shift->DP_STEER_FIFO_RESET, enc1->se_mask
->DP_STEER_FIFO_RESET, 0);
1005
1006 /* wait 100us for DIG/DP logic to prime
1007 * (i.e. a few video lines)
1008 */
1009 udelay(100);
1010
1011 /* the hardware would start sending video at the start of the next DP
1012 * frame (i.e. rising edge of the vblank).
1013 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1014 * register has no effect on enable transition! HW always guarantees
1015 * VID_STREAM enable at start of next frame, and this is not
1016 * programmable
1017 */
1018
1019 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_VID_STREAM_CNTL
), 1, enc1->se_shift->DP_VID_STREAM_ENABLE, enc1->se_mask
->DP_VID_STREAM_ENABLE, 1);
1020
1021 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1022}
1023
1024void enc1_stream_encoder_set_avmute(
1025 struct stream_encoder *enc,
1026 bool_Bool enable)
1027{
1028 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1029 unsigned int value = enable ? 1 : 0;
1030
1031 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_GC
), 1, enc1->se_shift->HDMI_GC_AVMUTE, enc1->se_mask->
HDMI_GC_AVMUTE, value);
1032}
1033
1034void enc1_reset_hdmi_stream_attribute(
1035 struct stream_encoder *enc)
1036{
1037 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1038
1039 REG_UPDATE_5(HDMI_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0)
1040 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0)
1041 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0)
1042 HDMI_DEEP_COLOR_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0)
1043 HDMI_DATA_SCRAMBLE_EN, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0)
1044 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_CONTROL
), 5, enc1->se_shift->HDMI_PACKET_GEN_VERSION, enc1->
se_mask->HDMI_PACKET_GEN_VERSION, 1, enc1->se_shift->
HDMI_KEEPOUT_MODE, enc1->se_mask->HDMI_KEEPOUT_MODE, 1,
enc1->se_shift->HDMI_DEEP_COLOR_ENABLE, enc1->se_mask
->HDMI_DEEP_COLOR_ENABLE, 0, enc1->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc1->se_mask->HDMI_DATA_SCRAMBLE_EN, 0, enc1->se_shift
->HDMI_CLOCK_CHANNEL_RATE, enc1->se_mask->HDMI_CLOCK_CHANNEL_RATE
, 0);
1045}
1046
1047
1048#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT0x8000 0x8000
1049#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC1 1
1050
1051#include "include/audio_types.h"
1052
1053
1054/* 25.2MHz/1.001*/
1055/* 25.2MHz/1.001*/
1056/* 25.2MHz*/
1057/* 27MHz */
1058/* 27MHz*1.001*/
1059/* 27MHz*1.001*/
1060/* 54MHz*/
1061/* 54MHz*1.001*/
1062/* 74.25MHz/1.001*/
1063/* 74.25MHz*/
1064/* 148.5MHz/1.001*/
1065/* 148.5MHz*/
1066
1067static const struct audio_clock_info audio_clock_info_table[16] = {
1068 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1069 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1070 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1071 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1072 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1073 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1074 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1075 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1076 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1077 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1078 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1079 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1080 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1081 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1082 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1083 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1084};
1085
1086static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1087 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1088 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1089 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1090 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1091 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1092 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1093 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1094 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1095 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1096 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1097 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1098 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1099 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1100 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1101};
1102
1103static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1104 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1105 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1106 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1107 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1108 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1109 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1110 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1111 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1112 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1113 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1114 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1115 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1116 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1117 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1118
1119
1120};
1121
1122static union audio_cea_channels speakers_to_channels(
1123 struct audio_speaker_flags speaker_flags)
1124{
1125 union audio_cea_channels cea_channels = {0};
1126
1127 /* these are one to one */
1128 cea_channels.channels.FL = speaker_flags.FL_FR;
1129 cea_channels.channels.FR = speaker_flags.FL_FR;
1130 cea_channels.channels.LFE = speaker_flags.LFE;
1131 cea_channels.channels.FC = speaker_flags.FC;
1132
1133 /* if Rear Left and Right exist move RC speaker to channel 7
1134 * otherwise to channel 5
1135 */
1136 if (speaker_flags.RL_RR) {
1137 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1138 cea_channels.channels.RR = speaker_flags.RL_RR;
1139 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1140 } else {
1141 cea_channels.channels.RL_RC = speaker_flags.RC;
1142 }
1143
1144 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1145 if (speaker_flags.FLC_FRC) {
1146 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1147 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1148 } else {
1149 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1150 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1151 }
1152
1153 return cea_channels;
1154}
1155
1156void get_audio_clock_info(
1157 enum dc_color_depth color_depth,
1158 uint32_t crtc_pixel_clock_100Hz,
1159 uint32_t actual_pixel_clock_100Hz,
1160 struct audio_clock_info *audio_clock_info)
1161{
1162 const struct audio_clock_info *clock_info;
1163 uint32_t index;
1164 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1165 uint32_t audio_array_size;
1166
1167 switch (color_depth) {
1168 case COLOR_DEPTH_161616:
1169 clock_info = audio_clock_info_table_48bpc;
1170 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table_48bpc)) / sizeof((audio_clock_info_table_48bpc
)[0]))
1171 audio_clock_info_table_48bpc)(sizeof((audio_clock_info_table_48bpc)) / sizeof((audio_clock_info_table_48bpc
)[0]));
1172 break;
1173 case COLOR_DEPTH_121212:
1174 clock_info = audio_clock_info_table_36bpc;
1175 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table_36bpc)) / sizeof((audio_clock_info_table_36bpc
)[0]))
1176 audio_clock_info_table_36bpc)(sizeof((audio_clock_info_table_36bpc)) / sizeof((audio_clock_info_table_36bpc
)[0]));
1177 break;
1178 default:
1179 clock_info = audio_clock_info_table;
1180 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table)) / sizeof((audio_clock_info_table
)[0]))
1181 audio_clock_info_table)(sizeof((audio_clock_info_table)) / sizeof((audio_clock_info_table
)[0]));
1182 break;
1183 }
1184
1185 if (clock_info != NULL((void *)0)) {
1186 /* search for exact pixel clock in table */
1187 for (index = 0; index < audio_array_size; index++) {
1188 if (clock_info[index].pixel_clock_in_10khz >
1189 crtc_pixel_clock_in_10khz)
1190 break; /* not match */
1191 else if (clock_info[index].pixel_clock_in_10khz ==
1192 crtc_pixel_clock_in_10khz) {
1193 /* match found */
1194 *audio_clock_info = clock_info[index];
1195 return;
1196 }
1197 }
1198 }
1199
1200 /* not found */
1201 if (actual_pixel_clock_100Hz == 0)
1202 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1203
1204 /* See HDMI spec the table entry under
1205 * pixel clock of "Other". */
1206 audio_clock_info->pixel_clock_in_10khz =
1207 actual_pixel_clock_100Hz / 100;
1208 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1209 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1210 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1211
1212 audio_clock_info->n_32khz = 4096;
1213 audio_clock_info->n_44khz = 6272;
1214 audio_clock_info->n_48khz = 6144;
1215}
1216
1217static void enc1_se_audio_setup(
1218 struct stream_encoder *enc,
1219 unsigned int az_inst,
1220 struct audio_info *audio_info)
1221{
1222 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1223
1224 uint32_t channels = 0;
1225
1226 ASSERT(audio_info)do { if (({ static int __warned; int __ret = !!(!(audio_info)
); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(audio_info)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c"
, 1226); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1227 if (audio_info == NULL((void *)0))
1228 /* This should not happen.it does so we don't get BSOD*/
1229 return;
1230
1231 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1232
1233 /* setup the audio stream source select (audio -> dig mapping) */
1234 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_SRC_CONTROL
), 0, 1, enc1->se_shift->AFMT_AUDIO_SRC_SELECT, enc1->
se_mask->AFMT_AUDIO_SRC_SELECT, az_inst);
1235
1236 /* Channel allocation */
1237 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 1, enc1->se_shift->AFMT_AUDIO_CHANNEL_ENABLE, enc1->
se_mask->AFMT_AUDIO_CHANNEL_ENABLE, channels);
1238}
1239
1240static void enc1_se_setup_hdmi_audio(
1241 struct stream_encoder *enc,
1242 const struct audio_crtc_info *crtc_info)
1243{
1244 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1245
1246 struct audio_clock_info audio_clock_info = {0};
1247
1248 /* HDMI_AUDIO_PACKET_CONTROL */
1249 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_AUDIO_PACKET_CONTROL
), 1, enc1->se_shift->HDMI_AUDIO_DELAY_EN, enc1->se_mask
->HDMI_AUDIO_DELAY_EN, 1)
1250 HDMI_AUDIO_DELAY_EN, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_AUDIO_PACKET_CONTROL
), 1, enc1->se_shift->HDMI_AUDIO_DELAY_EN, enc1->se_mask
->HDMI_AUDIO_DELAY_EN, 1);
1251
1252 /* AFMT_AUDIO_PACKET_CONTROL */
1253 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_60958_CS_UPDATE, enc1->se_mask
->AFMT_60958_CS_UPDATE, 1);
1254
1255 /* AFMT_AUDIO_PACKET_CONTROL2 */
1256 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0)
1257 AFMT_AUDIO_LAYOUT_OVRD, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0)
1258 AFMT_60958_OSF_OVRD, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0);
1259
1260 /* HDMI_ACR_PACKET_CONTROL */
1261 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_ACR_AUTO_SEND, enc1->se_mask
->HDMI_ACR_AUTO_SEND, 1, enc1->se_shift->HDMI_ACR_SOURCE
, enc1->se_mask->HDMI_ACR_SOURCE, 0, enc1->se_shift->
HDMI_ACR_AUDIO_PRIORITY, enc1->se_mask->HDMI_ACR_AUDIO_PRIORITY
, 0)
1262 HDMI_ACR_AUTO_SEND, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_ACR_AUTO_SEND, enc1->se_mask
->HDMI_ACR_AUTO_SEND, 1, enc1->se_shift->HDMI_ACR_SOURCE
, enc1->se_mask->HDMI_ACR_SOURCE, 0, enc1->se_shift->
HDMI_ACR_AUDIO_PRIORITY, enc1->se_mask->HDMI_ACR_AUDIO_PRIORITY
, 0)
1263 HDMI_ACR_SOURCE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_ACR_AUTO_SEND, enc1->se_mask
->HDMI_ACR_AUTO_SEND, 1, enc1->se_shift->HDMI_ACR_SOURCE
, enc1->se_mask->HDMI_ACR_SOURCE, 0, enc1->se_shift->
HDMI_ACR_AUDIO_PRIORITY, enc1->se_mask->HDMI_ACR_AUDIO_PRIORITY
, 0)
1264 HDMI_ACR_AUDIO_PRIORITY, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_PACKET_CONTROL
), 3, enc1->se_shift->HDMI_ACR_AUTO_SEND, enc1->se_mask
->HDMI_ACR_AUTO_SEND, 1, enc1->se_shift->HDMI_ACR_SOURCE
, enc1->se_mask->HDMI_ACR_SOURCE, 0, enc1->se_shift->
HDMI_ACR_AUDIO_PRIORITY, enc1->se_mask->HDMI_ACR_AUDIO_PRIORITY
, 0);
1265
1266 /* Program audio clock sample/regeneration parameters */
1267 get_audio_clock_info(crtc_info->color_depth,
1268 crtc_info->requested_pixel_clock_100Hz,
1269 crtc_info->calculated_pixel_clock_100Hz,
1270 &audio_clock_info);
1271 DC_LOG_HW_AUDIO(do { } while(0)
1272 "\n%s:Input::requested_pixel_clock_100Hz = %d" \do { } while(0)
1273 "calculated_pixel_clock_100Hz = %d \n", __func__, \do { } while(0)
1274 crtc_info->requested_pixel_clock_100Hz, \do { } while(0)
1275 crtc_info->calculated_pixel_clock_100Hz)do { } while(0);
1276
1277 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1278 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_32_0
), 1, enc1->se_shift->HDMI_ACR_CTS_32, enc1->se_mask
->HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1279
1280 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1281 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_32_1
), 1, enc1->se_shift->HDMI_ACR_N_32, enc1->se_mask->
HDMI_ACR_N_32, audio_clock_info.n_32khz);
1282
1283 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1284 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_44_0
), 1, enc1->se_shift->HDMI_ACR_CTS_44, enc1->se_mask
->HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1285
1286 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1287 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_44_1
), 1, enc1->se_shift->HDMI_ACR_N_44, enc1->se_mask->
HDMI_ACR_N_44, audio_clock_info.n_44khz);
1288
1289 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1290 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_48_0
), 1, enc1->se_shift->HDMI_ACR_CTS_48, enc1->se_mask
->HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1291
1292 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1293 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->HDMI_ACR_48_1
), 1, enc1->se_shift->HDMI_ACR_N_48, enc1->se_mask->
HDMI_ACR_N_48, audio_clock_info.n_48khz);
1294
1295 /* Video driver cannot know in advance which sample rate will
1296 * be used by HD Audio driver
1297 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1298 * programmed below in interruppt callback
1299 */
1300
1301 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1302 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1303 */
1304 REG_UPDATE_2(AFMT_60958_0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_0
), 2, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc1->
se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc1->se_mask->
AFMT_60958_CS_CLOCK_ACCURACY, 0)
1305 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_0
), 2, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc1->
se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc1->se_mask->
AFMT_60958_CS_CLOCK_ACCURACY, 0)
1306 AFMT_60958_CS_CLOCK_ACCURACY, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_0
), 2, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc1->
se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc1->se_mask->
AFMT_60958_CS_CLOCK_ACCURACY, 0);
1307
1308 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1309 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_1
), 1, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_R, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1310
1311 /* AFMT_60958_2 now keep this settings until
1312 * Programming guide comes out
1313 */
1314 REG_UPDATE_6(AFMT_60958_2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1315 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1316 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1317 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1318 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1319 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1320 AFMT_60958_CS_CHANNEL_NUMBER_7, 8)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_2
), 6, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_4, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc1->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc1
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc1->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc1->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc1->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc1->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1321}
1322
1323static void enc1_se_setup_dp_audio(
1324 struct stream_encoder *enc)
1325{
1326 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1327
1328 /* --- DP Audio packet configurations --- */
1329
1330 /* ATP Configuration */
1331 REG_SET(DP_SEC_AUD_N, 0,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_AUD_N
), 0, 1, enc1->se_shift->DP_SEC_AUD_N, enc1->se_mask
->DP_SEC_AUD_N, 0x8000)
1332 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_AUD_N
), 0, 1, enc1->se_shift->DP_SEC_AUD_N, enc1->se_mask
->DP_SEC_AUD_N, 0x8000);
1333
1334 /* Async/auto-calc timestamp mode */
1335 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_TIMESTAMP
), 0, 1, enc1->se_shift->DP_SEC_TIMESTAMP_MODE, enc1->
se_mask->DP_SEC_TIMESTAMP_MODE, 1)
1336 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC)generic_reg_set_ex(enc1->base.ctx, (enc1->regs->DP_SEC_TIMESTAMP
), 0, 1, enc1->se_shift->DP_SEC_TIMESTAMP_MODE, enc1->
se_mask->DP_SEC_TIMESTAMP_MODE, 1);
1337
1338 /* --- The following are the registers
1339 * copied from the SetupHDMI ---
1340 */
1341
1342 /* AFMT_AUDIO_PACKET_CONTROL */
1343 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_60958_CS_UPDATE, enc1->se_mask
->AFMT_60958_CS_UPDATE, 1);
1344
1345 /* AFMT_AUDIO_PACKET_CONTROL2 */
1346 /* Program the ATP and AIP next */
1347 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0)
1348 AFMT_AUDIO_LAYOUT_OVRD, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0)
1349 AFMT_60958_OSF_OVRD, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL2
), 2, enc1->se_shift->AFMT_AUDIO_LAYOUT_OVRD, enc1->
se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc1->se_shift->
AFMT_60958_OSF_OVRD, enc1->se_mask->AFMT_60958_OSF_OVRD
, 0);
1350
1351 /* AFMT_INFOFRAME_CONTROL0 */
1352 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_INFOFRAME_CONTROL0
), 1, enc1->se_shift->AFMT_AUDIO_INFO_UPDATE, enc1->
se_mask->AFMT_AUDIO_INFO_UPDATE, 1);
1353
1354 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1355 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_60958_0
), 1, enc1->se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc1
->se_mask->AFMT_60958_CS_CLOCK_ACCURACY, 0);
1356}
1357
1358void enc1_se_enable_audio_clock(
1359 struct stream_encoder *enc,
1360 bool_Bool enable)
1361{
1362 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1363
1364 if (REG(AFMT_CNTL)(enc1->regs->AFMT_CNTL) == 0)
1365 return; /* DCE8/10 does not have this register */
1366
1367 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_CNTL
), 1, enc1->se_shift->AFMT_AUDIO_CLOCK_EN, enc1->se_mask
->AFMT_AUDIO_CLOCK_EN, !!enable);
1368
1369 /* wait for AFMT clock to turn on,
1370 * expectation: this should complete in 1-2 reads
1371 *
1372 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1373 *
1374 * TODO: wait for clock_on does not work well. May need HW
1375 * program sequence. But audio seems work normally even without wait
1376 * for clock_on status change
1377 */
1378}
1379
1380void enc1_se_enable_dp_audio(
1381 struct stream_encoder *enc)
1382{
1383 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1384
1385 /* Enable Audio packets */
1386 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 1);
1387
1388 /* Program the ATP and AIP next */
1389 REG_UPDATE_2(DP_SEC_CNTL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 2, enc1->se_shift->DP_SEC_ATP_ENABLE, enc1->se_mask
->DP_SEC_ATP_ENABLE, 1, enc1->se_shift->DP_SEC_AIP_ENABLE
, enc1->se_mask->DP_SEC_AIP_ENABLE, 1)
1390 DP_SEC_ATP_ENABLE, 1,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 2, enc1->se_shift->DP_SEC_ATP_ENABLE, enc1->se_mask
->DP_SEC_ATP_ENABLE, 1, enc1->se_shift->DP_SEC_AIP_ENABLE
, enc1->se_mask->DP_SEC_AIP_ENABLE, 1)
1391 DP_SEC_AIP_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 2, enc1->se_shift->DP_SEC_ATP_ENABLE, enc1->se_mask
->DP_SEC_ATP_ENABLE, 1, enc1->se_shift->DP_SEC_AIP_ENABLE
, enc1->se_mask->DP_SEC_AIP_ENABLE, 1);
1392
1393 /* Program STREAM_ENABLE after all the other enables. */
1394 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 1);
1395}
1396
1397static void enc1_se_disable_dp_audio(
1398 struct stream_encoder *enc)
1399{
1400 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1401 uint32_t value = 0;
1402
1403 /* Disable Audio packets */
1404 REG_UPDATE_5(DP_SEC_CNTL,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0)
1405 DP_SEC_ASP_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0)
1406 DP_SEC_ATP_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0)
1407 DP_SEC_AIP_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0)
1408 DP_SEC_ACM_ENABLE, 0,generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0)
1409 DP_SEC_STREAM_ENABLE, 0)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 5, enc1->se_shift->DP_SEC_ASP_ENABLE, enc1->se_mask
->DP_SEC_ASP_ENABLE, 0, enc1->se_shift->DP_SEC_ATP_ENABLE
, enc1->se_mask->DP_SEC_ATP_ENABLE, 0, enc1->se_shift
->DP_SEC_AIP_ENABLE, enc1->se_mask->DP_SEC_AIP_ENABLE
, 0, enc1->se_shift->DP_SEC_ACM_ENABLE, enc1->se_mask
->DP_SEC_ACM_ENABLE, 0, enc1->se_shift->DP_SEC_STREAM_ENABLE
, enc1->se_mask->DP_SEC_STREAM_ENABLE, 0);
1410
1411 /* This register shared with encoder info frame. Therefore we need to
1412 * keep master enabled if at least on of the fields is not 0
1413 */
1414 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), __func__);
1415 if (value != 0)
1416 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DP_SEC_CNTL
), 1, enc1->se_shift->DP_SEC_STREAM_ENABLE, enc1->se_mask
->DP_SEC_STREAM_ENABLE, 1);
1417
1418}
1419
1420void enc1_se_audio_mute_control(
1421 struct stream_encoder *enc,
1422 bool_Bool mute)
1423{
1424 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1425
1426 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->AFMT_AUDIO_PACKET_CONTROL
), 1, enc1->se_shift->AFMT_AUDIO_SAMPLE_SEND, enc1->
se_mask->AFMT_AUDIO_SAMPLE_SEND, !mute);
1427}
1428
1429void enc1_se_dp_audio_setup(
1430 struct stream_encoder *enc,
1431 unsigned int az_inst,
1432 struct audio_info *info)
1433{
1434 enc1_se_audio_setup(enc, az_inst, info);
1435}
1436
1437void enc1_se_dp_audio_enable(
1438 struct stream_encoder *enc)
1439{
1440 enc1_se_enable_audio_clock(enc, true1);
1441 enc1_se_setup_dp_audio(enc);
1442 enc1_se_enable_dp_audio(enc);
1443}
1444
1445void enc1_se_dp_audio_disable(
1446 struct stream_encoder *enc)
1447{
1448 enc1_se_disable_dp_audio(enc);
1449 enc1_se_enable_audio_clock(enc, false0);
1450}
1451
1452void enc1_se_hdmi_audio_setup(
1453 struct stream_encoder *enc,
1454 unsigned int az_inst,
1455 struct audio_info *info,
1456 struct audio_crtc_info *audio_crtc_info)
1457{
1458 enc1_se_enable_audio_clock(enc, true1);
1459 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1460 enc1_se_audio_setup(enc, az_inst, info);
1461}
1462
1463void enc1_se_hdmi_audio_disable(
1464 struct stream_encoder *enc)
1465{
1466#if defined(CONFIG_DRM_AMD_DC_DCN1)
1467 if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1468 enc->afmt->funcs->afmt_powerdown(enc->afmt);
1469#endif
1470 enc1_se_enable_audio_clock(enc, false0);
1471}
1472
1473
1474void enc1_setup_stereo_sync(
1475 struct stream_encoder *enc,
1476 int tg_inst, bool_Bool enable)
1477{
1478 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1479 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->DIG_STEREOSYNC_SELECT, enc1->se_mask
->DIG_STEREOSYNC_SELECT, tg_inst);
1480 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->DIG_STEREOSYNC_GATE_EN, enc1->
se_mask->DIG_STEREOSYNC_GATE_EN, !enable);
1481}
1482
1483void enc1_dig_connect_to_otg(
1484 struct stream_encoder *enc,
1485 int tg_inst)
1486{
1487 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1488
1489 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst)generic_reg_update_ex(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), 1, enc1->se_shift->DIG_SOURCE_SELECT, enc1->se_mask
->DIG_SOURCE_SELECT, tg_inst);
1490}
1491
1492unsigned int enc1_dig_source_otg(
1493 struct stream_encoder *enc)
1494{
1495 uint32_t tg_inst = 0;
1496 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1497
1498 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst)generic_reg_get(enc1->base.ctx, (enc1->regs->DIG_FE_CNTL
), enc1->se_shift->DIG_SOURCE_SELECT, enc1->se_mask->
DIG_SOURCE_SELECT, &tg_inst);
1499
1500 return tg_inst;
1501}
1502
1503bool_Bool enc1_stream_encoder_dp_get_pixel_format(
1504 struct stream_encoder *enc,
1505 enum dc_pixel_encoding *encoding,
1506 enum dc_color_depth *depth)
1507{
1508 uint32_t hw_encoding = 0;
1509 uint32_t hw_depth = 0;
1510 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (enc); (struct dcn10_stream_encoder *)( (char *)
__mptr - __builtin_offsetof(struct dcn10_stream_encoder, base
) );});
1511
1512 if (enc == NULL((void *)0) ||
1513 encoding == NULL((void *)0) ||
1514 depth == NULL((void *)0))
1515 return false0;
1516
1517 REG_GET_2(DP_PIXEL_FORMAT,generic_reg_get2(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask->
DP_PIXEL_ENCODING, &hw_encoding, enc1->se_shift->DP_COMPONENT_DEPTH
, enc1->se_mask->DP_COMPONENT_DEPTH, &hw_depth)
1518 DP_PIXEL_ENCODING, &hw_encoding,generic_reg_get2(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask->
DP_PIXEL_ENCODING, &hw_encoding, enc1->se_shift->DP_COMPONENT_DEPTH
, enc1->se_mask->DP_COMPONENT_DEPTH, &hw_depth)
1519 DP_COMPONENT_DEPTH, &hw_depth)generic_reg_get2(enc1->base.ctx, (enc1->regs->DP_PIXEL_FORMAT
), enc1->se_shift->DP_PIXEL_ENCODING, enc1->se_mask->
DP_PIXEL_ENCODING, &hw_encoding, enc1->se_shift->DP_COMPONENT_DEPTH
, enc1->se_mask->DP_COMPONENT_DEPTH, &hw_depth);
1520
1521 switch (hw_depth) {
1522 case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1523 *depth = COLOR_DEPTH_666;
1524 break;
1525 case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1526 *depth = COLOR_DEPTH_888;
1527 break;
1528 case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1529 *depth = COLOR_DEPTH_101010;
1530 break;
1531 case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1532 *depth = COLOR_DEPTH_121212;
1533 break;
1534 case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1535 *depth = COLOR_DEPTH_161616;
1536 break;
1537 default:
1538 *depth = COLOR_DEPTH_UNDEFINED;
1539 break;
1540 }
1541
1542 switch (hw_encoding) {
1543 case DP_PIXEL_ENCODING_TYPE_RGB444:
1544 *encoding = PIXEL_ENCODING_RGB;
1545 break;
1546 case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1547 *encoding = PIXEL_ENCODING_YCBCR422;
1548 break;
1549 case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1550 case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1551 *encoding = PIXEL_ENCODING_YCBCR444;
1552 break;
1553 case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1554 *encoding = PIXEL_ENCODING_YCBCR420;
1555 break;
1556 default:
1557 *encoding = PIXEL_ENCODING_UNDEFINED;
1558 break;
1559 }
1560 return true1;
1561}
1562
1563static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1564 .dp_set_stream_attribute =
1565 enc1_stream_encoder_dp_set_stream_attribute,
1566 .hdmi_set_stream_attribute =
1567 enc1_stream_encoder_hdmi_set_stream_attribute,
1568 .dvi_set_stream_attribute =
1569 enc1_stream_encoder_dvi_set_stream_attribute,
1570 .set_throttled_vcp_size =
1571 enc1_stream_encoder_set_throttled_vcp_size,
1572 .update_hdmi_info_packets =
1573 enc1_stream_encoder_update_hdmi_info_packets,
1574 .stop_hdmi_info_packets =
1575 enc1_stream_encoder_stop_hdmi_info_packets,
1576 .update_dp_info_packets =
1577 enc1_stream_encoder_update_dp_info_packets,
1578 .send_immediate_sdp_message =
1579 enc1_stream_encoder_send_immediate_sdp_message,
1580 .stop_dp_info_packets =
1581 enc1_stream_encoder_stop_dp_info_packets,
1582 .dp_blank =
1583 enc1_stream_encoder_dp_blank,
1584 .dp_unblank =
1585 enc1_stream_encoder_dp_unblank,
1586 .audio_mute_control = enc1_se_audio_mute_control,
1587
1588 .dp_audio_setup = enc1_se_dp_audio_setup,
1589 .dp_audio_enable = enc1_se_dp_audio_enable,
1590 .dp_audio_disable = enc1_se_dp_audio_disable,
1591
1592 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1593 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1594 .setup_stereo_sync = enc1_setup_stereo_sync,
1595 .set_avmute = enc1_stream_encoder_set_avmute,
1596 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1597 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1598 .dig_source_otg = enc1_dig_source_otg,
1599
1600 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
1601};
1602
1603void dcn10_stream_encoder_construct(
1604 struct dcn10_stream_encoder *enc1,
1605 struct dc_context *ctx,
1606 struct dc_bios *bp,
1607 enum engine_id eng_id,
1608 const struct dcn10_stream_enc_registers *regs,
1609 const struct dcn10_stream_encoder_shift *se_shift,
1610 const struct dcn10_stream_encoder_mask *se_mask)
1611{
1612 enc1->base.funcs = &dcn10_str_enc_funcs;
1613 enc1->base.ctx = ctx;
1614 enc1->base.id = eng_id;
1615 enc1->base.bp = bp;
1616 enc1->regs = regs;
1617 enc1->se_shift = se_shift;
1618 enc1->se_mask = se_mask;
1619 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1620}
1621