Bug Summary

File:dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
Warning:line 1378, column 7
Branch condition evaluates to a garbage value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_dm_mst_types.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <drm/display/drm_dp_helper.h>
27#include <drm/display/drm_dp_mst_helper.h>
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include "dm_services.h"
31#include "amdgpu.h"
32#include "amdgpu_dm.h"
33#include "amdgpu_dm_mst_types.h"
34
35#ifdef CONFIG_DRM_AMD_DC_HDCP
36#include "amdgpu_dm_hdcp.h"
37#endif
38
39#include "dc.h"
40#include "dm_helpers.h"
41
42#include "dc_link_ddc.h"
43#include "dc_link_dp.h"
44#include "ddc_service_types.h"
45#include "dpcd_defs.h"
46
47#include "i2caux_interface.h"
48#include "dmub_cmd.h"
49#if defined(CONFIG_DEBUG_FS)
50#include "amdgpu_dm_debugfs.h"
51#endif
52
53#include "dc/dcn20/dcn20_resource.h"
54bool_Bool is_timing_changed(struct dc_stream_state *cur_stream,
55 struct dc_stream_state *new_stream);
56
57
58static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
59 struct drm_dp_aux_msg *msg)
60{
61 ssize_t result = 0;
62 struct aux_payload payload;
63 enum aux_return_code_type operation_result;
64 struct amdgpu_device *adev;
65 struct ddc_service *ddc;
66
67 if (WARN_ON(msg->size > 16)({ int __ret = !!(msg->size > 16); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "msg->size > 16", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c"
, 67); __builtin_expect(!!(__ret), 0); }))
68 return -E2BIG7;
69
70 payload.address = msg->address;
71 payload.data = msg->buffer;
72 payload.length = msg->size;
73 payload.reply = &msg->reply;
74 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE0x8) == 0;
75 payload.write = (msg->request & DP_AUX_I2C_READ0x1) == 0;
76 payload.mot = (msg->request & DP_AUX_I2C_MOT0x4) != 0;
77 payload.write_status_update =
78 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE0x2) != 0;
79 payload.defer_delay = 0;
80
81 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)({ const __typeof( ((struct amdgpu_dm_dp_aux *)0)->aux ) *
__mptr = ((aux)); (struct amdgpu_dm_dp_aux *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_dm_dp_aux, aux) );})->ddc_service, &payload,
82 &operation_result);
83
84 /*
85 * w/a on certain intel platform where hpd is unexpected to pull low during
86 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
87 * aux transaction is succuess in such case, therefore bypass the error
88 */
89 ddc = TO_DM_AUX(aux)({ const __typeof( ((struct amdgpu_dm_dp_aux *)0)->aux ) *
__mptr = ((aux)); (struct amdgpu_dm_dp_aux *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_dm_dp_aux, aux) );})->ddc_service;
90 adev = ddc->ctx->driver_context;
91 if (adev->dm.aux_hpd_discon_quirk) {
92 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE0x1000 &&
93 operation_result == AUX_RET_ERROR_HPD_DISCON) {
94 result = 0;
95 operation_result = AUX_RET_SUCCESS;
96 }
97 }
98
99 if (payload.write && result >= 0)
100 result = msg->size;
101
102 if (result < 0)
103 switch (operation_result) {
104 case AUX_RET_SUCCESS:
105 break;
106 case AUX_RET_ERROR_HPD_DISCON:
107 case AUX_RET_ERROR_UNKNOWN:
108 case AUX_RET_ERROR_INVALID_OPERATION:
109 case AUX_RET_ERROR_PROTOCOL_ERROR:
110 result = -EIO5;
111 break;
112 case AUX_RET_ERROR_INVALID_REPLY:
113 case AUX_RET_ERROR_ENGINE_ACQUIRE:
114 result = -EBUSY16;
115 break;
116 case AUX_RET_ERROR_TIMEOUT:
117 result = -ETIMEDOUT60;
118 break;
119 }
120
121 return result;
122}
123
124static void
125dm_dp_mst_connector_destroy(struct drm_connector *connector)
126{
127 struct amdgpu_dm_connector *aconnector =
128 to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
129
130 if (aconnector->dc_sink) {
131 dc_link_remove_remote_sink(aconnector->dc_link,
132 aconnector->dc_sink);
133 dc_sink_release(aconnector->dc_sink);
134 }
135
136 kfree(aconnector->edid);
137
138 drm_connector_cleanup(connector);
139 drm_dp_mst_put_port_malloc(aconnector->port);
140 kfree(aconnector);
141}
142
143static int
144amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
145{
146 struct amdgpu_dm_connector *amdgpu_dm_connector =
147 to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
148 int r;
149
150 r = drm_dp_mst_connector_late_register(connector,
151 amdgpu_dm_connector->port);
152 if (r < 0)
153 return r;
154
155#if defined(CONFIG_DEBUG_FS)
156 connector_debugfs_init(amdgpu_dm_connector);
157#endif
158
159 return 0;
160}
161
162static void
163amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
164{
165 struct amdgpu_dm_connector *aconnector =
166 to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
167 struct drm_dp_mst_port *port = aconnector->port;
168 struct amdgpu_dm_connector *root = aconnector->mst_port;
169 struct dc_link *dc_link = aconnector->dc_link;
170 struct dc_sink *dc_sink = aconnector->dc_sink;
171
172 drm_dp_mst_connector_early_unregister(connector, port);
173
174 /*
175 * Release dc_sink for connector which its attached port is
176 * no longer in the mst topology
177 */
178 drm_modeset_lock(&root->mst_mgr.base.lock, NULL((void *)0));
179 if (dc_sink) {
180 if (dc_link->sink_count)
181 dc_link_remove_remote_sink(dc_link, dc_sink);
182
183 dc_sink_release(dc_sink);
184 aconnector->dc_sink = NULL((void *)0);
185 aconnector->edid = NULL((void *)0);
186 }
187
188 aconnector->mst_status = MST_STATUS_DEFAULT;
189 drm_modeset_unlock(&root->mst_mgr.base.lock);
190}
191
192static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
193 .fill_modes = drm_helper_probe_single_connector_modes,
194 .destroy = dm_dp_mst_connector_destroy,
195 .reset = amdgpu_dm_connector_funcs_reset,
196 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
197 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
198 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
199 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
200 .late_register = amdgpu_dm_mst_connector_late_register,
201 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
202};
203
204#if defined(CONFIG_DRM_AMD_DC_DCN1)
205bool_Bool needs_dsc_aux_workaround(struct dc_link *link)
206{
207 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC240x90CC24 &&
208 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
209 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
210 return true1;
211
212 return false0;
213}
214
215bool_Bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
216{
217 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
218
219 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START0x50C, &branch_vendor_data, 4) == 4) {
220 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC240x90CC24 &&
221 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)(((((int)link->dpcd_caps.branch_dev_name[4] & 0xF0) ==
0x50 ? 1 : 0) && ((int)branch_vendor_data[2] == 0x5A
)) ? 1 : 0)) {
222 DRM_INFO("Synaptics Cascaded MST hub\n")printk("\0016" "[" "drm" "] " "Synaptics Cascaded MST hub\n");
223 return true1;
224 }
225 }
226
227 return false0;
228}
229
230static bool_Bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
231{
232 struct dc_sink *dc_sink = aconnector->dc_sink;
233 struct drm_dp_mst_port *port = aconnector->port;
234 u8 dsc_caps[16] = { 0 };
235 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
236 u8 *dsc_branch_dec_caps = NULL((void *)0);
237
238 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
239
240 /*
241 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
242 * because it only check the dsc/fec caps of the "port variable" and not the dock
243 *
244 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
245 *
246 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
247 *
248 */
249 if (!aconnector->dsc_aux && !port->parent->port_parent &&
250 needs_dsc_aux_workaround(aconnector->dc_link))
251 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
252
253 /* synaptics cascaded MST hub case */
254 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
255 aconnector->dsc_aux = port->mgr->aux;
256
257 if (!aconnector->dsc_aux)
258 return false0;
259
260 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT0x060, dsc_caps, 16) < 0)
261 return false0;
262
263 if (drm_dp_dpcd_read(aconnector->dsc_aux,
264 DP_DSC_BRANCH_OVERALL_THROUGHPUT_00x0a0, dsc_branch_dec_caps_raw, 3) == 3)
265 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
266
267 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
268 dsc_caps, dsc_branch_dec_caps,
269 &dc_sink->dsc_caps.dsc_dec_caps))
270 return false0;
271
272 return true1;
273}
274
275static bool_Bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
276{
277 union dp_downstream_port_present ds_port_present;
278
279 if (!aconnector->dsc_aux)
280 return false0;
281
282 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT0x005, &ds_port_present, 1) < 0) {
283 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n")printk("\0016" "[" "drm" "] " "Failed to read downstream_port_present 0x05 from DFP of branch device\n"
);
284 return false0;
285 }
286
287 aconnector->mst_downstream_port_present = ds_port_present;
288 DRM_INFO("Downstream port present %d, type %d\n",printk("\0016" "[" "drm" "] " "Downstream port present %d, type %d\n"
, ds_port_present.fields.PORT_PRESENT, ds_port_present.fields
.PORT_TYPE)
289 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE)printk("\0016" "[" "drm" "] " "Downstream port present %d, type %d\n"
, ds_port_present.fields.PORT_PRESENT, ds_port_present.fields
.PORT_TYPE);
290
291 return true1;
292}
293#endif
294
295static int dm_dp_mst_get_modes(struct drm_connector *connector)
296{
297 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
298 int ret = 0;
299
300 if (!aconnector)
301 return drm_add_edid_modes(connector, NULL((void *)0));
302
303 if (!aconnector->edid) {
304 struct edid *edid;
305 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
306
307 if (!edid) {
308 amdgpu_dm_set_mst_status(&aconnector->mst_status,
309 MST_REMOTE_EDID, false0);
310
311 drm_connector_update_edid_property(
312 &aconnector->base,
313 NULL((void *)0));
314
315 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name)___drm_dbg(((void *)0), DRM_UT_KMS, "Can't get EDID of %s. Add default remote sink."
, connector->name);
316 if (!aconnector->dc_sink) {
317 struct dc_sink *dc_sink;
318 struct dc_sink_init_data init_params = {
319 .link = aconnector->dc_link,
320 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
321
322 dc_sink = dc_link_add_remote_sink(
323 aconnector->dc_link,
324 NULL((void *)0),
325 0,
326 &init_params);
327
328 if (!dc_sink) {
329 DRM_ERROR("Unable to add a remote sink\n")__drm_err("Unable to add a remote sink\n");
330 return 0;
331 }
332
333 dc_sink->priv = aconnector;
334 aconnector->dc_sink = dc_sink;
335 }
336
337 return ret;
338 }
339
340 aconnector->edid = edid;
341 amdgpu_dm_set_mst_status(&aconnector->mst_status,
342 MST_REMOTE_EDID, true1);
343 }
344
345 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
346 dc_sink_release(aconnector->dc_sink);
347 aconnector->dc_sink = NULL((void *)0);
348 }
349
350 if (!aconnector->dc_sink) {
351 struct dc_sink *dc_sink;
352 struct dc_sink_init_data init_params = {
353 .link = aconnector->dc_link,
354 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
355 dc_sink = dc_link_add_remote_sink(
356 aconnector->dc_link,
357 (uint8_t *)aconnector->edid,
358 (aconnector->edid->extensions + 1) * EDID_LENGTH128,
359 &init_params);
360
361 if (!dc_sink) {
362 DRM_ERROR("Unable to add a remote sink\n")__drm_err("Unable to add a remote sink\n");
363 return 0;
364 }
365
366 dc_sink->priv = aconnector;
367 /* dc_link_add_remote_sink returns a new reference */
368 aconnector->dc_sink = dc_sink;
369
370 /* when display is unplugged from mst hub, connctor will be
371 * destroyed within dm_dp_mst_connector_destroy. connector
372 * hdcp perperties, like type, undesired, desired, enabled,
373 * will be lost. So, save hdcp properties into hdcp_work within
374 * amdgpu_dm_atomic_commit_tail. if the same display is
375 * plugged back with same display index, its hdcp properties
376 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
377 */
378#ifdef CONFIG_DRM_AMD_DC_HDCP
379 if (aconnector->dc_sink && connector->state) {
380 struct drm_device *dev = connector->dev;
381 struct amdgpu_device *adev = drm_to_adev(dev);
382
383 if (adev->dm.hdcp_workqueue) {
384 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
385 struct hdcp_workqueue *hdcp_w =
386 &hdcp_work[aconnector->dc_link->link_index];
387
388 connector->state->hdcp_content_type =
389 hdcp_w->hdcp_content_type[connector->index];
390 connector->state->content_protection =
391 hdcp_w->content_protection[connector->index];
392 }
393 }
394#endif
395
396 if (aconnector->dc_sink) {
397 amdgpu_dm_update_freesync_caps(
398 connector, aconnector->edid);
399
400#if defined(CONFIG_DRM_AMD_DC_DCN1)
401 if (!validate_dsc_caps_on_connector(aconnector))
402 memset(&aconnector->dc_sink->dsc_caps,__builtin_memset((&aconnector->dc_sink->dsc_caps), (
0), (sizeof(aconnector->dc_sink->dsc_caps)))
403 0, sizeof(aconnector->dc_sink->dsc_caps))__builtin_memset((&aconnector->dc_sink->dsc_caps), (
0), (sizeof(aconnector->dc_sink->dsc_caps)));
404
405 if (!retrieve_downstream_port_device(aconnector))
406 memset(&aconnector->mst_downstream_port_present,__builtin_memset((&aconnector->mst_downstream_port_present
), (0), (sizeof(aconnector->mst_downstream_port_present)))
407 0, sizeof(aconnector->mst_downstream_port_present))__builtin_memset((&aconnector->mst_downstream_port_present
), (0), (sizeof(aconnector->mst_downstream_port_present)));
408#endif
409 }
410 }
411
412 drm_connector_update_edid_property(
413 &aconnector->base, aconnector->edid);
414
415 ret = drm_add_edid_modes(connector, aconnector->edid);
416
417 return ret;
418}
419
420static struct drm_encoder *
421dm_mst_atomic_best_encoder(struct drm_connector *connector,
422 struct drm_atomic_state *state)
423{
424 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
425 connector);
426 struct drm_device *dev = connector->dev;
427 struct amdgpu_device *adev = drm_to_adev(dev);
428 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (connector_state->crtc); (struct amdgpu_crtc *)( (char *
)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );});
429
430 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
431}
432
433static int
434dm_dp_mst_detect(struct drm_connector *connector,
435 struct drm_modeset_acquire_ctx *ctx, bool_Bool force)
436{
437 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
438 struct amdgpu_dm_connector *master = aconnector->mst_port;
439 struct drm_dp_mst_port *port = aconnector->port;
440 int connection_status;
441
442 if (drm_connector_is_unregistered(connector))
443 return connector_status_disconnected;
444
445 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
446 aconnector->port);
447
448 if (port->pdt != DP_PEER_DEVICE_NONE0x0 && !port->dpcd_rev) {
449 uint8_t dpcd_rev;
450 int ret;
451
452 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV0x2200, &dpcd_rev);
453
454 if (ret == 1) {
455 port->dpcd_rev = dpcd_rev;
456
457 /* Could be DP1.2 DP Rx case*/
458 if (!dpcd_rev) {
459 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV0x000, &dpcd_rev);
460
461 if (ret == 1)
462 port->dpcd_rev = dpcd_rev;
463 }
464
465 if (!dpcd_rev)
466 DRM_DEBUG_KMS("Can't decide DPCD revision number!")___drm_dbg(((void *)0), DRM_UT_KMS, "Can't decide DPCD revision number!"
);
467 }
468
469 /*
470 * Could be legacy sink, logical port etc on DP1.2.
471 * Will get Nack under these cases when issue remote
472 * DPCD read.
473 */
474 if (ret != 1)
475 DRM_DEBUG_KMS("Can't access DPCD")___drm_dbg(((void *)0), DRM_UT_KMS, "Can't access DPCD");
476 } else if (port->pdt == DP_PEER_DEVICE_NONE0x0) {
477 port->dpcd_rev = 0;
478 }
479
480 /*
481 * Release dc_sink for connector which unplug event is notified by CSN msg
482 */
483 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
484 if (aconnector->dc_link->sink_count)
485 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
486
487 dc_sink_release(aconnector->dc_sink);
488 aconnector->dc_sink = NULL((void *)0);
489 aconnector->edid = NULL((void *)0);
490
491 amdgpu_dm_set_mst_status(&aconnector->mst_status,
492 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
493 false0);
494 }
495
496 return connection_status;
497}
498
499static int dm_dp_mst_atomic_check(struct drm_connector *connector,
500 struct drm_atomic_state *state)
501{
502 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
503 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
504 struct drm_dp_mst_port *mst_port = aconnector->port;
505
506 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
507}
508
509static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
510 .get_modes = dm_dp_mst_get_modes,
511 .mode_valid = amdgpu_dm_connector_mode_valid,
512 .atomic_best_encoder = dm_mst_atomic_best_encoder,
513 .detect_ctx = dm_dp_mst_detect,
514 .atomic_check = dm_dp_mst_atomic_check,
515};
516
517static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
518{
519 drm_encoder_cleanup(encoder);
520}
521
522static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
523 .destroy = amdgpu_dm_encoder_destroy,
524};
525
526void
527dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
528{
529 struct drm_device *dev = adev_to_drm(adev);
530 int i;
531
532 for (i = 0; i < adev->dm.display_indexes_num; i++) {
533 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
534 struct drm_encoder *encoder = &amdgpu_encoder->base;
535
536 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
537
538 drm_encoder_init(
539 dev,
540 &amdgpu_encoder->base,
541 &amdgpu_dm_encoder_funcs,
542 DRM_MODE_ENCODER_DPMST7,
543 NULL((void *)0));
544
545 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
546 }
547}
548
549static struct drm_connector *
550dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
551 struct drm_dp_mst_port *port,
552 const char *pathprop)
553{
554 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr)({ const __typeof( ((struct amdgpu_dm_connector *)0)->mst_mgr
) *__mptr = (mgr); (struct amdgpu_dm_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_dm_connector, mst_mgr) );
});
555 struct drm_device *dev = master->base.dev;
556 struct amdgpu_device *adev = drm_to_adev(dev);
557 struct amdgpu_dm_connector *aconnector;
558 struct drm_connector *connector;
559 int i;
560
561 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL(0x0001 | 0x0004));
562 if (!aconnector)
563 return NULL((void *)0);
564
565 connector = &aconnector->base;
566 aconnector->port = port;
567 aconnector->mst_port = master;
568 amdgpu_dm_set_mst_status(&aconnector->mst_status,
569 MST_PROBE, true1);
570
571 if (drm_connector_init(
572 dev,
573 connector,
574 &dm_dp_mst_connector_funcs,
575 DRM_MODE_CONNECTOR_DisplayPort10)) {
576 kfree(aconnector);
577 return NULL((void *)0);
578 }
579 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
580
581 amdgpu_dm_connector_init_helper(
582 &adev->dm,
583 aconnector,
584 DRM_MODE_CONNECTOR_DisplayPort10,
585 master->dc_link,
586 master->connector_id);
587
588 for (i = 0; i < adev->dm.display_indexes_num; i++) {
589 drm_connector_attach_encoder(&aconnector->base,
590 &adev->dm.mst_encoders[i].base);
591 }
592
593 connector->max_bpc_property = master->base.max_bpc_property;
594 if (connector->max_bpc_property)
595 drm_connector_attach_max_bpc_property(connector, 8, 16);
596
597 connector->vrr_capable_property = master->base.vrr_capable_property;
598 if (connector->vrr_capable_property)
599 drm_connector_attach_vrr_capable_property(connector);
600
601 drm_object_attach_property(
602 &connector->base,
603 dev->mode_config.path_property,
604 0);
605 drm_object_attach_property(
606 &connector->base,
607 dev->mode_config.tile_property,
608 0);
609
610 drm_connector_set_path_property(connector, pathprop);
611
612 /*
613 * Initialize connector state before adding the connectror to drm and
614 * framebuffer lists
615 */
616 amdgpu_dm_connector_funcs_reset(connector);
617
618 drm_dp_mst_get_port_malloc(port);
619
620 return connector;
621}
622
623void dm_handle_mst_sideband_msg_ready_event(
624 struct drm_dp_mst_topology_mgr *mgr,
625 enum mst_msg_ready_type msg_rdy_type)
626{
627 uint8_t esi[DP_PSR_ERROR_STATUS0x2006 - DP_SINK_COUNT_ESI0x2002] = { 0 };
628 uint8_t dret;
629 bool_Bool new_irq_handled = false0;
630 int dpcd_addr;
631 uint8_t dpcd_bytes_to_read;
632 const uint8_t max_process_count = 30;
633 uint8_t process_count = 0;
634 u8 retry;
635 struct amdgpu_dm_connector *aconnector =
636 container_of(mgr, struct amdgpu_dm_connector, mst_mgr)({ const __typeof( ((struct amdgpu_dm_connector *)0)->mst_mgr
) *__mptr = (mgr); (struct amdgpu_dm_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_dm_connector, mst_mgr) );
});
637
638
639 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
640
641 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
642 dpcd_bytes_to_read = DP_LANE0_1_STATUS0x202 - DP_SINK_COUNT0x200;
643 /* DPCD 0x200 - 0x201 for downstream IRQ */
644 dpcd_addr = DP_SINK_COUNT0x200;
645 } else {
646 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS0x2006 - DP_SINK_COUNT_ESI0x2002;
647 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
648 dpcd_addr = DP_SINK_COUNT_ESI0x2002;
649 }
650
651 mutex_lock(&aconnector->handle_mst_msg_ready)rw_enter_write(&aconnector->handle_mst_msg_ready);
652
653 while (process_count < max_process_count) {
654 u8 ack[DP_PSR_ERROR_STATUS0x2006 - DP_SINK_COUNT_ESI0x2002] = {};
655
656 process_count++;
657
658 dret = drm_dp_dpcd_read(
659 &aconnector->dm_dp_aux.aux,
660 dpcd_addr,
661 esi,
662 dpcd_bytes_to_read);
663
664 if (dret != dpcd_bytes_to_read) {
665 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!")___drm_dbg(((void *)0), DRM_UT_KMS, "DPCD read and acked number is not as expected!"
);
666 break;
667 }
668
669 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2])___drm_dbg(((void *)0), DRM_UT_DRIVER, "ESI %02x %02x %02x\n"
, esi[0], esi[1], esi[2]);
670
671 switch (msg_rdy_type) {
672 case DOWN_REP_MSG_RDY_EVENT:
673 /* Only handle DOWN_REP_MSG_RDY case*/
674 esi[1] &= DP_DOWN_REP_MSG_RDY(1 << 4);
675 break;
676 case UP_REQ_MSG_RDY_EVENT:
677 /* Only handle UP_REQ_MSG_RDY case*/
678 esi[1] &= DP_UP_REQ_MSG_RDY(1 << 5);
679 break;
680 default:
681 /* Handle both cases*/
682 esi[1] &= (DP_DOWN_REP_MSG_RDY(1 << 4) | DP_UP_REQ_MSG_RDY(1 << 5));
683 break;
684 }
685
686 if (!esi[1])
687 break;
688
689 /* handle MST irq */
690 if (aconnector->mst_mgr.mst_state)
691 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
692 esi,
693 ack,
694 &new_irq_handled);
695
696 if (new_irq_handled) {
697 /* ACK at DPCD to notify down stream */
698 for (retry = 0; retry < 3; retry++) {
699 ssize_t wret;
700
701 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
702 dpcd_addr + 1,
703 ack[1]);
704 if (wret == 1)
705 break;
706 }
707
708 if (retry == 3) {
709 DRM_ERROR("Failed to ack MST event.\n")__drm_err("Failed to ack MST event.\n");
710 break;
711 }
712
713 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
714
715 new_irq_handled = false0;
716 } else {
717 break;
718 }
719 }
720
721 mutex_unlock(&aconnector->handle_mst_msg_ready)rw_exit_write(&aconnector->handle_mst_msg_ready);
722
723 if (process_count == max_process_count)
724 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Loop exceeded max iterations\n"
);
725}
726
727static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
728{
729 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
730}
731
732static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
733 .add_connector = dm_dp_add_mst_connector,
734 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
735};
736
737void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
738 struct amdgpu_dm_connector *aconnector,
739 int link_index)
740{
741 struct dc_link_settings max_link_enc_cap = {0};
742
743 aconnector->dm_dp_aux.aux.name =
744 kasprintf(GFP_KERNEL(0x0001 | 0x0004), "AMDGPU DM aux hw bus %d",
745 link_index);
746 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
747 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
748 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
749
750 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
751 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
752 &aconnector->base);
753
754 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP14)
755 return;
756
757 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
758 aconnector->mst_mgr.cbs = &dm_mst_cbs;
759 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
760 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
761
762 drm_connector_attach_dp_subconnector_property(&aconnector->base);
763}
764
765int dm_mst_get_pbn_divider(struct dc_link *link)
766{
767 if (!link)
768 return 0;
769
770 return dc_link_bandwidth_kbps(link,
771 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
772}
773
774#if defined(CONFIG_DRM_AMD_DC_DCN1)
775
776struct dsc_mst_fairness_params {
777 struct dc_crtc_timing *timing;
778 struct dc_sink *sink;
779 struct dc_dsc_bw_range bw_range;
780 bool_Bool compression_possible;
781 struct drm_dp_mst_port *port;
782 enum dsc_clock_force_state clock_force_enable;
783 uint32_t num_slices_h;
784 uint32_t num_slices_v;
785 uint32_t bpp_overwrite;
786 struct amdgpu_dm_connector *aconnector;
787};
788
789static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
790{
791 u8 link_coding_cap;
792 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B1031;
793
794 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
795 if (link_coding_cap == DP_128b_132b_ENCODING)
796 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B1000;
797
798 return fec_overhead_multiplier_x1000;
799}
800
801static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
802{
803 u64 peak_kbps = kbps;
804
805 peak_kbps *= 1006;
806 peak_kbps *= fec_overhead_multiplier_x1000;
807 peak_kbps = div_u64(peak_kbps, 1000 * 1000);
808 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000))({ uint64_t _t = ((54 * 8 * 1000)); div64_u64((peak_kbps * 64
) + _t - 1, _t); });
809}
810
811static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
812 struct dsc_mst_fairness_vars *vars,
813 int count,
814 int k)
815{
816 struct drm_connector *drm_connector;
817 int i;
818
819 for (i = 0; i < count; i++) {
820 drm_connector = &params[i].aconnector->base;
821
822 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg))__builtin_memset((&params[i].timing->dsc_cfg), (0), (sizeof
(params[i].timing->dsc_cfg)));
823 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
824 params[i].sink->ctx->dc->res_pool->dscs[0],
825 &params[i].sink->dsc_caps.dsc_dec_caps,
826 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
827 drm_connector->display_info.max_dsc_bpp,
828 0,
829 params[i].timing,
830 &params[i].timing->dsc_cfg)) {
831 params[i].timing->flags.DSC = 1;
832
833 if (params[i].bpp_overwrite)
834 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
835 else
836 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
837
838 if (params[i].num_slices_h)
839 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
840
841 if (params[i].num_slices_v)
842 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
843 } else {
844 params[i].timing->flags.DSC = 0;
845 }
846 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
847 }
848
849 for (i = 0; i < count; i++) {
850 if (params[i].sink) {
851 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
852 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
853 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s i=%d dispname=%s\n"
, __func__, i, params[i].sink->edid_caps.display_name)
854 params[i].sink->edid_caps.display_name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s i=%d dispname=%s\n"
, __func__, i, params[i].sink->edid_caps.display_name);
855 }
856
857 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "dsc=%d bits_per_pixel=%d pbn=%d\n"
, params[i].timing->flags.DSC, params[i].timing->dsc_cfg
.bits_per_pixel, vars[i + k].pbn)
858 params[i].timing->flags.DSC,___drm_dbg(((void *)0), DRM_UT_DRIVER, "dsc=%d bits_per_pixel=%d pbn=%d\n"
, params[i].timing->flags.DSC, params[i].timing->dsc_cfg
.bits_per_pixel, vars[i + k].pbn)
859 params[i].timing->dsc_cfg.bits_per_pixel,___drm_dbg(((void *)0), DRM_UT_DRIVER, "dsc=%d bits_per_pixel=%d pbn=%d\n"
, params[i].timing->flags.DSC, params[i].timing->dsc_cfg
.bits_per_pixel, vars[i + k].pbn)
860 vars[i + k].pbn)___drm_dbg(((void *)0), DRM_UT_DRIVER, "dsc=%d bits_per_pixel=%d pbn=%d\n"
, params[i].timing->flags.DSC, params[i].timing->dsc_cfg
.bits_per_pixel, vars[i + k].pbn);
861 }
862}
863
864static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
865{
866 struct dc_dsc_config dsc_config;
867 u64 kbps;
868
869 struct drm_connector *drm_connector = &param.aconnector->base;
870 uint32_t max_dsc_target_bpp_limit_override =
871 drm_connector->display_info.max_dsc_bpp;
872
873 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
874 dc_dsc_compute_config(
875 param.sink->ctx->dc->res_pool->dscs[0],
876 &param.sink->dsc_caps.dsc_dec_caps,
877 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
878 max_dsc_target_bpp_limit_override,
879 (int) kbps, param.timing, &dsc_config);
880
881 return dsc_config.bits_per_pixel;
882}
883
884static int increase_dsc_bpp(struct drm_atomic_state *state,
885 struct drm_dp_mst_topology_state *mst_state,
886 struct dc_link *dc_link,
887 struct dsc_mst_fairness_params *params,
888 struct dsc_mst_fairness_vars *vars,
889 int count,
890 int k)
891{
892 int i;
893 bool_Bool bpp_increased[MAX_PIPES6];
894 int initial_slack[MAX_PIPES6];
895 int min_initial_slack;
896 int next_index;
897 int remaining_to_increase = 0;
898 int link_timeslots_used;
899 int fair_pbn_alloc;
900 int ret = 0;
901 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
902
903 for (i = 0; i < count; i++) {
904 if (vars[i + k].dsc_enabled) {
905 initial_slack[i] =
906 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
907 bpp_increased[i] = false0;
908 remaining_to_increase += 1;
909 } else {
910 initial_slack[i] = 0;
911 bpp_increased[i] = true1;
912 }
913 }
914
915 while (remaining_to_increase) {
916 next_index = -1;
917 min_initial_slack = -1;
918 for (i = 0; i < count; i++) {
919 if (!bpp_increased[i]) {
920 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
921 min_initial_slack = initial_slack[i];
922 next_index = i;
923 }
924 }
925 }
926
927 if (next_index == -1)
928 break;
929
930 link_timeslots_used = 0;
931
932 for (i = 0; i < count; i++)
933 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div)(((vars[i + k].pbn) + ((mst_state->pbn_div) - 1)) / (mst_state
->pbn_div));
934
935 fair_pbn_alloc =
936 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
937
938 if (initial_slack[next_index] > fair_pbn_alloc) {
939 vars[next_index].pbn += fair_pbn_alloc;
940 ret = drm_dp_atomic_find_time_slots(state,
941 params[next_index].port->mgr,
942 params[next_index].port,
943 vars[next_index].pbn);
944 if (ret < 0)
945 return ret;
946
947 ret = drm_dp_mst_atomic_check(state);
948 if (ret == 0) {
949 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
950 } else {
951 vars[next_index].pbn -= fair_pbn_alloc;
952 ret = drm_dp_atomic_find_time_slots(state,
953 params[next_index].port->mgr,
954 params[next_index].port,
955 vars[next_index].pbn);
956 if (ret < 0)
957 return ret;
958 }
959 } else {
960 vars[next_index].pbn += initial_slack[next_index];
961 ret = drm_dp_atomic_find_time_slots(state,
962 params[next_index].port->mgr,
963 params[next_index].port,
964 vars[next_index].pbn);
965 if (ret < 0)
966 return ret;
967
968 ret = drm_dp_mst_atomic_check(state);
969 if (ret == 0) {
970 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
971 } else {
972 vars[next_index].pbn -= initial_slack[next_index];
973 ret = drm_dp_atomic_find_time_slots(state,
974 params[next_index].port->mgr,
975 params[next_index].port,
976 vars[next_index].pbn);
977 if (ret < 0)
978 return ret;
979 }
980 }
981
982 bpp_increased[next_index] = true1;
983 remaining_to_increase--;
984 }
985 return 0;
986}
987
988static int try_disable_dsc(struct drm_atomic_state *state,
989 struct dc_link *dc_link,
990 struct dsc_mst_fairness_params *params,
991 struct dsc_mst_fairness_vars *vars,
992 int count,
993 int k)
994{
995 int i;
996 bool_Bool tried[MAX_PIPES6];
997 int kbps_increase[MAX_PIPES6];
998 int max_kbps_increase;
999 int next_index;
1000 int remaining_to_try = 0;
1001 int ret;
1002 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1003
1004 for (i = 0; i < count; i++) {
1005 if (vars[i + k].dsc_enabled
1006 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1007 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1008 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1009 tried[i] = false0;
1010 remaining_to_try += 1;
1011 } else {
1012 kbps_increase[i] = 0;
1013 tried[i] = true1;
1014 }
1015 }
1016
1017 while (remaining_to_try) {
1018 next_index = -1;
1019 max_kbps_increase = -1;
1020 for (i = 0; i < count; i++) {
1021 if (!tried[i]) {
1022 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1023 max_kbps_increase = kbps_increase[i];
1024 next_index = i;
1025 }
1026 }
1027 }
1028
1029 if (next_index == -1)
1030 break;
1031
1032 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1033 ret = drm_dp_atomic_find_time_slots(state,
1034 params[next_index].port->mgr,
1035 params[next_index].port,
1036 vars[next_index].pbn);
1037 if (ret < 0)
1038 return ret;
1039
1040 ret = drm_dp_mst_atomic_check(state);
1041 if (ret == 0) {
1042 vars[next_index].dsc_enabled = false0;
1043 vars[next_index].bpp_x16 = 0;
1044 } else {
1045 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);
1046 ret = drm_dp_atomic_find_time_slots(state,
1047 params[next_index].port->mgr,
1048 params[next_index].port,
1049 vars[next_index].pbn);
1050 if (ret < 0)
1051 return ret;
1052 }
1053
1054 tried[next_index] = true1;
1055 remaining_to_try--;
1056 }
1057 return 0;
1058}
1059
1060static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1061 struct dc_state *dc_state,
1062 struct dc_link *dc_link,
1063 struct dsc_mst_fairness_vars *vars,
1064 struct drm_dp_mst_topology_mgr *mgr,
1065 int *link_vars_start_index)
1066{
1067 struct dc_stream_state *stream;
1068 struct dsc_mst_fairness_params params[MAX_PIPES6];
1069 struct amdgpu_dm_connector *aconnector;
1070 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1071 int count = 0;
1072 int i, k, ret;
1073 bool_Bool debugfs_overwrite = false0;
1074 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1075
1076 memset(params, 0, sizeof(params))__builtin_memset((params), (0), (sizeof(params)));
1077
1078 if (IS_ERR(mst_state))
1079 return PTR_ERR(mst_state);
1080
1081 /* Set up params */
1082 for (i = 0; i < dc_state->stream_count; i++) {
1083 struct dc_dsc_policy dsc_policy = {0};
1084
1085 stream = dc_state->streams[i];
1086
1087 if (stream->link != dc_link)
1088 continue;
1089
1090 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1091 if (!aconnector)
1092 continue;
1093
1094 if (!aconnector->port)
1095 continue;
1096
1097 stream->timing.flags.DSC = 0;
1098
1099 params[count].timing = &stream->timing;
1100 params[count].sink = stream->sink;
1101 params[count].aconnector = aconnector;
1102 params[count].port = aconnector->port;
1103 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1104 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1105 debugfs_overwrite = true1;
1106 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1107 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1108 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1109 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1110 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
1111 if (!dc_dsc_compute_bandwidth_range(
1112 stream->sink->ctx->dc->res_pool->dscs[0],
1113 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1114 dsc_policy.min_target_bpp * 16,
1115 dsc_policy.max_target_bpp * 16,
1116 &stream->sink->dsc_caps.dsc_dec_caps,
1117 &stream->timing, &params[count].bw_range))
1118 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
1119
1120 count++;
1121 }
1122
1123 if (count == 0) {
1124 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c"
, 1124); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1125 return 0;
1126 }
1127
1128 /* k is start index of vars for current phy link used by mst hub */
1129 k = *link_vars_start_index;
1130 /* set vars start index for next mst hub phy link */
1131 *link_vars_start_index += count;
1132
1133 /* Try no compression */
1134 for (i = 0; i < count; i++) {
1135 vars[i + k].aconnector = params[i].aconnector;
1136 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1137 vars[i + k].dsc_enabled = false0;
1138 vars[i + k].bpp_x16 = 0;
1139 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1140 vars[i + k].pbn);
1141 if (ret < 0)
1142 return ret;
1143 }
1144 ret = drm_dp_mst_atomic_check(state);
1145 if (ret == 0 && !debugfs_overwrite) {
1146 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1147 return 0;
1148 } else if (ret != -ENOSPC28) {
1149 return ret;
1150 }
1151
1152 /* Try max compression */
1153 for (i = 0; i < count; i++) {
1154 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1155 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1156 vars[i + k].dsc_enabled = true1;
1157 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1158 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1159 params[i].port, vars[i + k].pbn);
1160 if (ret < 0)
1161 return ret;
1162 } else {
1163 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1164 vars[i + k].dsc_enabled = false0;
1165 vars[i + k].bpp_x16 = 0;
1166 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1167 params[i].port, vars[i + k].pbn);
1168 if (ret < 0)
1169 return ret;
1170 }
1171 }
1172 ret = drm_dp_mst_atomic_check(state);
1173 if (ret != 0)
1174 return ret;
1175
1176 /* Optimize degree of compression */
1177 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1178 if (ret < 0)
1179 return ret;
1180
1181 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1182 if (ret < 0)
1183 return ret;
1184
1185 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1186
1187 return 0;
1188}
1189
1190static bool_Bool is_dsc_need_re_compute(
1191 struct drm_atomic_state *state,
1192 struct dc_state *dc_state,
1193 struct dc_link *dc_link)
1194{
1195 int i, j;
1196 bool_Bool is_dsc_need_re_compute = false0;
1197 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES6];
1198 int new_stream_on_link_num = 0;
1199 struct amdgpu_dm_connector *aconnector;
1200 struct dc_stream_state *stream;
1201 const struct dc *dc = dc_link->dc;
1202
1203 /* only check phy used by dsc mst branch */
1204 if (dc_link->type != dc_connection_mst_branch)
1205 return false0;
1206
1207 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1208 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1209 return false0;
1210
1211 for (i = 0; i < MAX_PIPES6; i++)
1212 stream_on_link[i] = NULL((void *)0);
1213
1214 /* check if there is mode change in new request */
1215 for (i = 0; i < dc_state->stream_count; i++) {
1216 struct drm_crtc_state *new_crtc_state;
1217 struct drm_connector_state *new_conn_state;
1218
1219 stream = dc_state->streams[i];
1220 if (!stream)
1221 continue;
1222
1223 /* check if stream using the same link for mst */
1224 if (stream->link != dc_link)
1225 continue;
1226
1227 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1228 if (!aconnector)
1229 continue;
1230
1231 stream_on_link[new_stream_on_link_num] = aconnector;
1232 new_stream_on_link_num++;
1233
1234 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1235 if (!new_conn_state)
1236 continue;
1237
1238 if (IS_ERR(new_conn_state))
1239 continue;
1240
1241 if (!new_conn_state->crtc)
1242 continue;
1243
1244 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1245 if (!new_crtc_state)
1246 continue;
1247
1248 if (IS_ERR(new_crtc_state))
1249 continue;
1250
1251 if (new_crtc_state->enable && new_crtc_state->active) {
1252 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1253 new_crtc_state->connectors_changed)
1254 return true1;
1255 }
1256 }
1257
1258 /* check current_state if there stream on link but it is not in
1259 * new request state
1260 */
1261 for (i = 0; i < dc->current_state->stream_count; i++) {
1262 stream = dc->current_state->streams[i];
1263 /* only check stream on the mst hub */
1264 if (stream->link != dc_link)
1265 continue;
1266
1267 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1268 if (!aconnector)
1269 continue;
1270
1271 for (j = 0; j < new_stream_on_link_num; j++) {
1272 if (stream_on_link[j]) {
1273 if (aconnector == stream_on_link[j])
1274 break;
1275 }
1276 }
1277
1278 if (j == new_stream_on_link_num) {
1279 /* not in new state */
1280 is_dsc_need_re_compute = true1;
1281 break;
1282 }
1283 }
1284
1285 return is_dsc_need_re_compute;
1286}
1287
1288int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1289 struct dc_state *dc_state,
1290 struct dsc_mst_fairness_vars *vars)
1291{
1292 int i, j;
1293 struct dc_stream_state *stream;
1294 bool_Bool computed_streams[MAX_PIPES6];
1295 struct amdgpu_dm_connector *aconnector;
1296 struct drm_dp_mst_topology_mgr *mst_mgr;
1297 int link_vars_start_index = 0;
1298 int ret = 0;
1299
1300 for (i = 0; i < dc_state->stream_count; i++)
1301 computed_streams[i] = false0;
1302
1303 for (i = 0; i < dc_state->stream_count; i++) {
1304 stream = dc_state->streams[i];
1305
1306 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1307 continue;
1308
1309 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1310
1311 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
1312 continue;
1313
1314 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1315 continue;
1316
1317 if (computed_streams[i])
1318 continue;
1319
1320 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1321 return -EINVAL22;
1322
1323 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1324 continue;
1325
1326 mst_mgr = aconnector->port->mgr;
1327 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1328 &link_vars_start_index);
1329 if (ret != 0)
1330 return ret;
1331
1332 for (j = 0; j < dc_state->stream_count; j++) {
1333 if (dc_state->streams[j]->link == stream->link)
1334 computed_streams[j] = true1;
1335 }
1336 }
1337
1338 for (i = 0; i < dc_state->stream_count; i++) {
1339 stream = dc_state->streams[i];
1340
1341 if (stream->timing.flags.DSC == 1)
1342 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1343 return -EINVAL22;
1344 }
1345
1346 return ret;
1347}
1348
1349static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1350 struct dc_state *dc_state,
1351 struct dsc_mst_fairness_vars *vars)
1352{
1353 int i, j;
1354 struct dc_stream_state *stream;
1355 bool_Bool computed_streams[MAX_PIPES6];
1356 struct amdgpu_dm_connector *aconnector;
1357 struct drm_dp_mst_topology_mgr *mst_mgr;
1358 int link_vars_start_index = 0;
1359 int ret = 0;
1360
1361 for (i = 0; i < dc_state->stream_count; i++)
12
←
Loop condition is true. Entering loop body
→
13
←
Loop condition is false. Execution continues on line 1364
→
1362 computed_streams[i] = false0;
1363
1364 for (i = 0; i < dc_state->stream_count; i++) {
14
←
Loop condition is true. Entering loop body
→
26
←
 Execution continues on line 1364
→
27
←
The value 1 is assigned to 'i'
→
28
←
Assuming 'i' is < field 'stream_count'
→
29
←
Loop condition is true. Entering loop body
→
1365 stream = dc_state->streams[i];
1366
1367 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
15
←
Assuming field 'signal' is equal to SIGNAL_TYPE_DISPLAY_PORT_MST
→
16
←
Taking false branch
→
30
←
Assuming field 'signal' is equal to SIGNAL_TYPE_DISPLAY_PORT_MST
→
31
←
Taking false branch
→
1368 continue;
1369
1370 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1371
1372 if (!aconnector || !aconnector->dc_sink || !aconnector->port)
17
←
Assuming 'aconnector' is non-null
→
18
←
Assuming field 'dc_sink' is non-null
→
19
←
Assuming field 'port' is non-null
→
20
←
Taking false branch
→
32
←
Assuming 'aconnector' is non-null
→
33
←
Assuming field 'dc_sink' is non-null
→
34
←
Assuming field 'port' is non-null
→
35
←
Taking false branch
→
1373 continue;
1374
1375 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
21
←
Assuming field 'is_dsc_supported' is true
→
22
←
Taking false branch
→
36
←
Assuming field 'is_dsc_supported' is true
→
37
←
Taking false branch
→
1376 continue;
1377
1378 if (computed_streams[i])
23
←
Taking false branch
→
38
←
Branch condition evaluates to a garbage value
1379 continue;
1380
1381 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
24
←
Assuming the condition is true
→
25
←
Taking true branch
→
1382 continue;
1383
1384 mst_mgr = aconnector->port->mgr;
1385 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1386 &link_vars_start_index);
1387 if (ret != 0)
1388 return ret;
1389
1390 for (j = 0; j < dc_state->stream_count; j++) {
1391 if (dc_state->streams[j]->link == stream->link)
1392 computed_streams[j] = true1;
1393 }
1394 }
1395
1396 return ret;
1397}
1398
1399static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1400 struct dc_stream_state *stream)
1401{
1402 int i;
1403 struct drm_crtc *crtc;
1404 struct drm_crtc_state *new_state, *old_state;
1405
1406 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_state) = (state)
->crtcs[i].old_state, (void)(old_state) , (new_state) = (state
)->crtcs[i].new_state, (void)(new_state) , 1))) {} else {
1407 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
= (new_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});
1408
1409 if (dm_state->stream == stream)
1410 return i;
1411 }
1412 return -1;
1413}
1414
1415static bool_Bool is_link_to_dschub(struct dc_link *dc_link)
1416{
1417 union dpcd_dsc_basic_capabilities *dsc_caps =
1418 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1419
1420 /* only check phy used by dsc mst branch */
1421 if (dc_link->type != dc_connection_mst_branch)
1422 return false0;
1423
1424 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1425 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1426 return false0;
1427 return true1;
1428}
1429
1430static bool_Bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1431{
1432 int i;
1433 struct drm_crtc *crtc;
1434 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1435 bool_Bool ret = false0;
1436
1437 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
1438 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
= (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
- __builtin_offsetof(struct dm_crtc_state, base) );});
1439
1440 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1441 ret = false0;
1442 break;
1443 }
1444 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1445 if (is_link_to_dschub(dm_crtc_state->stream->link))
1446 ret = true1;
1447 }
1448 return ret;
1449}
1450
1451int pre_validate_dsc(struct drm_atomic_state *state,
1452 struct dm_atomic_state **dm_state_ptr,
1453 struct dsc_mst_fairness_vars *vars)
1454{
1455 int i;
1456 struct dm_atomic_state *dm_state;
1457 struct dc_state *local_dc_state = NULL((void *)0);
1458 int ret = 0;
1459
1460 if (!is_dsc_precompute_needed(state)) {
1
Taking false branch
→
1461 DRM_INFO_ONCE("DSC precompute is not needed.\n")({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "DSC precompute is not needed.\n"); __warned = 1; } });
1462 return 0;
1463 }
1464 ret = dm_atomic_get_state(state, dm_state_ptr);
1465 if (ret != 0) {
2
←
Assuming 'ret' is equal to 0
→
3
←
Taking false branch
→
1466 DRM_INFO_ONCE("dm_atomic_get_state() failed\n")({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "dm_atomic_get_state() failed\n"); __warned = 1; } });
1467 return ret;
1468 }
1469 dm_state = *dm_state_ptr;
1470
1471 /*
1472 * create local vailable for dc_state. copy content of streams of dm_state->context
1473 * to local variable. make sure stream pointer of local variable not the same as stream
1474 * from dm_state->context.
1475 */
1476
1477 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL(0x0001 | 0x0004));
1478 if (!local_dc_state
3.1
'local_dc_state' is non-null
)
4
←
Taking false branch
→
1479 return -ENOMEM12;
1480
1481 for (i = 0; i < local_dc_state->stream_count; i++) {
5
←
Assuming 'i' is < field 'stream_count'
→
6
←
Loop condition is true. Entering loop body
→
8
←
Assuming 'i' is >= field 'stream_count'
→
9
←
Loop condition is false. Execution continues on line 1512
→
1482 struct dc_stream_state *stream = dm_state->context->streams[i];
1483 int ind = find_crtc_index_in_state_by_stream(state, stream);
1484
1485 if (ind
6.1
'ind' is < 0
 >= 0) {
7
←
Taking false branch
→
1486 struct amdgpu_dm_connector *aconnector;
1487 struct drm_connector_state *drm_new_conn_state;
1488 struct dm_connector_state *dm_new_conn_state;
1489 struct dm_crtc_state *dm_old_crtc_state;
1490
1491 aconnector =
1492 amdgpu_dm_find_first_crtc_matching_connector(state,
1493 state->crtcs[ind].ptr);
1494 drm_new_conn_state =
1495 drm_atomic_get_new_connector_state(state,
1496 &aconnector->base);
1497 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
*__mptr = ((drm_new_conn_state)); (struct dm_connector_state
*)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
1498 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
= (state->crtcs[ind].old_state); (struct dm_crtc_state *)
( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state, base
) );});
1499
1500 local_dc_state->streams[i] =
1501 create_validate_stream_for_sink(aconnector,
1502 &state->crtcs[ind].new_state->mode,
1503 dm_new_conn_state,
1504 dm_old_crtc_state->stream);
1505 if (local_dc_state->streams[i] == NULL((void *)0)) {
1506 ret = -EINVAL22;
1507 break;
1508 }
1509 }
1510 }
1511
1512 if (ret
9.1
'ret' is equal to 0
 != 0)
10
←
Taking false branch
→
1513 goto clean_exit;
1514
1515 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
11
←
Calling 'pre_compute_mst_dsc_configs_for_state'
→
1516 if (ret != 0) {
1517 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n")({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "pre_compute_mst_dsc_configs_for_state() failed\n"); __warned
= 1; } });
1518 ret = -EINVAL22;
1519 goto clean_exit;
1520 }
1521
1522 /*
1523 * compare local_streams -> timing with dm_state->context,
1524 * if the same set crtc_state->mode-change = 0;
1525 */
1526 for (i = 0; i < local_dc_state->stream_count; i++) {
1527 struct dc_stream_state *stream = dm_state->context->streams[i];
1528
1529 if (local_dc_state->streams[i] &&
1530 is_timing_changed(stream, local_dc_state->streams[i])) {
1531 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i)({ static int __warned; if (!__warned) { printk("\0016" "[" "drm"
"] " "crtc[%d] needs mode_changed\n", i); __warned = 1; } });
1532 } else {
1533 int ind = find_crtc_index_in_state_by_stream(state, stream);
1534
1535 if (ind >= 0)
1536 state->crtcs[ind].new_state->mode_changed = 0;
1537 }
1538 }
1539clean_exit:
1540 for (i = 0; i < local_dc_state->stream_count; i++) {
1541 struct dc_stream_state *stream = dm_state->context->streams[i];
1542
1543 if (local_dc_state->streams[i] != stream)
1544 dc_stream_release(local_dc_state->streams[i]);
1545 }
1546
1547 kfree(local_dc_state);
1548
1549 return ret;
1550}
1551
1552static unsigned int kbps_from_pbn(unsigned int pbn)
1553{
1554 unsigned int kbps = pbn;
1555
1556 kbps *= (1000000 / PEAK_FACTOR_X1000);
1557 kbps *= 8;
1558 kbps *= 54;
1559 kbps /= 64;
1560
1561 return kbps;
1562}
1563
1564static bool_Bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1565 struct dc_dsc_bw_range *bw_range)
1566{
1567 struct dc_dsc_policy dsc_policy = {0};
1568
1569 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1570 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1571 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1572 dsc_policy.min_target_bpp * 16,
1573 dsc_policy.max_target_bpp * 16,
1574 &stream->sink->dsc_caps.dsc_dec_caps,
1575 &stream->timing, bw_range);
1576
1577 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1578}
1579#endif /* CONFIG_DRM_AMD_DC_DCN */
1580
1581enum dc_status dm_dp_mst_is_port_support_mode(
1582 struct amdgpu_dm_connector *aconnector,
1583 struct dc_stream_state *stream)
1584{
1585 int bpp, pbn, branch_max_throughput_mps = 0;
1586#if defined(CONFIG_DRM_AMD_DC_DCN1)
1587 struct dc_link_settings cur_link_settings;
1588 unsigned int end_to_end_bw_in_kbps = 0;
1589 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1590 unsigned int max_compressed_bw_in_kbps = 0;
1591 struct dc_dsc_bw_range bw_range = {0};
1592 struct drm_dp_mst_topology_mgr *mst_mgr;
1593
1594 /*
1595 * check if the mode could be supported if DSC pass-through is supported
1596 * AND check if there enough bandwidth available to support the mode
1597 * with DSC enabled.
1598 */
1599 if (is_dsc_common_config_possible(stream, &bw_range) &&
1600 aconnector->port->passthrough_aux) {
1601 mst_mgr = aconnector->port->mgr;
1602 mutex_lock(&mst_mgr->lock)rw_enter_write(&mst_mgr->lock);
1603
1604 cur_link_settings = stream->link->verified_link_cap;
1605
1606 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1607 &cur_link_settings
1608 );
1609 down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
1610
1611 /* pick the bottleneck */
1612 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,(((upper_link_bw_in_kbps)<(down_link_bw_in_kbps))?(upper_link_bw_in_kbps
):(down_link_bw_in_kbps))
1613 down_link_bw_in_kbps)(((upper_link_bw_in_kbps)<(down_link_bw_in_kbps))?(upper_link_bw_in_kbps
):(down_link_bw_in_kbps));
1614
1615 mutex_unlock(&mst_mgr->lock)rw_exit_write(&mst_mgr->lock);
1616
1617 /*
1618 * use the maximum dsc compression bandwidth as the required
1619 * bandwidth for the mode
1620 */
1621 max_compressed_bw_in_kbps = bw_range.min_kbps;
1622
1623 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1624 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode does not fit into DSC pass-through bandwidth validation\n"
);
1625 return DC_FAIL_BANDWIDTH_VALIDATE;
1626 }
1627 } else {
1628#endif
1629 /* check if mode could be supported within full_pbn */
1630 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1631 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false0);
1632
1633 if (pbn > aconnector->port->full_pbn)
1634 return DC_FAIL_BANDWIDTH_VALIDATE;
1635#if defined(CONFIG_DRM_AMD_DC_DCN1)
1636 }
1637#endif
1638
1639 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1640 switch (stream->timing.pixel_encoding) {
1641 case PIXEL_ENCODING_RGB:
1642 case PIXEL_ENCODING_YCBCR444:
1643 branch_max_throughput_mps =
1644 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1645 break;
1646 case PIXEL_ENCODING_YCBCR422:
1647 case PIXEL_ENCODING_YCBCR420:
1648 branch_max_throughput_mps =
1649 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1650 break;
1651 default:
1652 break;
1653 }
1654
1655 if (branch_max_throughput_mps != 0 &&
1656 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000))
1657 return DC_FAIL_BANDWIDTH_VALIDATE;
1658
1659 return DC_OK;
1660}