File: | dev/pci/drm/i915/display/intel_dpll.c |
Warning: | line 1765, column 2 Value stored to 'bestn' is never read |
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1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright © 2020 Intel Corporation |
4 | */ |
5 | |
6 | #include <linux/kernel.h> |
7 | #include <linux/string_helpers.h> |
8 | |
9 | #include "intel_crtc.h" |
10 | #include "intel_de.h" |
11 | #include "intel_display.h" |
12 | #include "intel_display_types.h" |
13 | #include "intel_dpll.h" |
14 | #include "intel_lvds.h" |
15 | #include "intel_panel.h" |
16 | #include "intel_pps.h" |
17 | #include "intel_snps_phy.h" |
18 | #include "vlv_sideband.h" |
19 | |
20 | struct intel_dpll_funcs { |
21 | int (*crtc_compute_clock)(struct intel_atomic_state *state, |
22 | struct intel_crtc *crtc); |
23 | int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, |
24 | struct intel_crtc *crtc); |
25 | }; |
26 | |
27 | struct intel_limit { |
28 | struct { |
29 | int min, max; |
30 | } dot, vco, n, m, m1, m2, p, p1; |
31 | |
32 | struct { |
33 | int dot_limit; |
34 | int p2_slow, p2_fast; |
35 | } p2; |
36 | }; |
37 | static const struct intel_limit intel_limits_i8xx_dac = { |
38 | .dot = { .min = 25000, .max = 350000 }, |
39 | .vco = { .min = 908000, .max = 1512000 }, |
40 | .n = { .min = 2, .max = 16 }, |
41 | .m = { .min = 96, .max = 140 }, |
42 | .m1 = { .min = 18, .max = 26 }, |
43 | .m2 = { .min = 6, .max = 16 }, |
44 | .p = { .min = 4, .max = 128 }, |
45 | .p1 = { .min = 2, .max = 33 }, |
46 | .p2 = { .dot_limit = 165000, |
47 | .p2_slow = 4, .p2_fast = 2 }, |
48 | }; |
49 | |
50 | static const struct intel_limit intel_limits_i8xx_dvo = { |
51 | .dot = { .min = 25000, .max = 350000 }, |
52 | .vco = { .min = 908000, .max = 1512000 }, |
53 | .n = { .min = 2, .max = 16 }, |
54 | .m = { .min = 96, .max = 140 }, |
55 | .m1 = { .min = 18, .max = 26 }, |
56 | .m2 = { .min = 6, .max = 16 }, |
57 | .p = { .min = 4, .max = 128 }, |
58 | .p1 = { .min = 2, .max = 33 }, |
59 | .p2 = { .dot_limit = 165000, |
60 | .p2_slow = 4, .p2_fast = 4 }, |
61 | }; |
62 | |
63 | static const struct intel_limit intel_limits_i8xx_lvds = { |
64 | .dot = { .min = 25000, .max = 350000 }, |
65 | .vco = { .min = 908000, .max = 1512000 }, |
66 | .n = { .min = 2, .max = 16 }, |
67 | .m = { .min = 96, .max = 140 }, |
68 | .m1 = { .min = 18, .max = 26 }, |
69 | .m2 = { .min = 6, .max = 16 }, |
70 | .p = { .min = 4, .max = 128 }, |
71 | .p1 = { .min = 1, .max = 6 }, |
72 | .p2 = { .dot_limit = 165000, |
73 | .p2_slow = 14, .p2_fast = 7 }, |
74 | }; |
75 | |
76 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
77 | .dot = { .min = 20000, .max = 400000 }, |
78 | .vco = { .min = 1400000, .max = 2800000 }, |
79 | .n = { .min = 1, .max = 6 }, |
80 | .m = { .min = 70, .max = 120 }, |
81 | .m1 = { .min = 8, .max = 18 }, |
82 | .m2 = { .min = 3, .max = 7 }, |
83 | .p = { .min = 5, .max = 80 }, |
84 | .p1 = { .min = 1, .max = 8 }, |
85 | .p2 = { .dot_limit = 200000, |
86 | .p2_slow = 10, .p2_fast = 5 }, |
87 | }; |
88 | |
89 | static const struct intel_limit intel_limits_i9xx_lvds = { |
90 | .dot = { .min = 20000, .max = 400000 }, |
91 | .vco = { .min = 1400000, .max = 2800000 }, |
92 | .n = { .min = 1, .max = 6 }, |
93 | .m = { .min = 70, .max = 120 }, |
94 | .m1 = { .min = 8, .max = 18 }, |
95 | .m2 = { .min = 3, .max = 7 }, |
96 | .p = { .min = 7, .max = 98 }, |
97 | .p1 = { .min = 1, .max = 8 }, |
98 | .p2 = { .dot_limit = 112000, |
99 | .p2_slow = 14, .p2_fast = 7 }, |
100 | }; |
101 | |
102 | |
103 | static const struct intel_limit intel_limits_g4x_sdvo = { |
104 | .dot = { .min = 25000, .max = 270000 }, |
105 | .vco = { .min = 1750000, .max = 3500000}, |
106 | .n = { .min = 1, .max = 4 }, |
107 | .m = { .min = 104, .max = 138 }, |
108 | .m1 = { .min = 17, .max = 23 }, |
109 | .m2 = { .min = 5, .max = 11 }, |
110 | .p = { .min = 10, .max = 30 }, |
111 | .p1 = { .min = 1, .max = 3}, |
112 | .p2 = { .dot_limit = 270000, |
113 | .p2_slow = 10, |
114 | .p2_fast = 10 |
115 | }, |
116 | }; |
117 | |
118 | static const struct intel_limit intel_limits_g4x_hdmi = { |
119 | .dot = { .min = 22000, .max = 400000 }, |
120 | .vco = { .min = 1750000, .max = 3500000}, |
121 | .n = { .min = 1, .max = 4 }, |
122 | .m = { .min = 104, .max = 138 }, |
123 | .m1 = { .min = 16, .max = 23 }, |
124 | .m2 = { .min = 5, .max = 11 }, |
125 | .p = { .min = 5, .max = 80 }, |
126 | .p1 = { .min = 1, .max = 8}, |
127 | .p2 = { .dot_limit = 165000, |
128 | .p2_slow = 10, .p2_fast = 5 }, |
129 | }; |
130 | |
131 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
132 | .dot = { .min = 20000, .max = 115000 }, |
133 | .vco = { .min = 1750000, .max = 3500000 }, |
134 | .n = { .min = 1, .max = 3 }, |
135 | .m = { .min = 104, .max = 138 }, |
136 | .m1 = { .min = 17, .max = 23 }, |
137 | .m2 = { .min = 5, .max = 11 }, |
138 | .p = { .min = 28, .max = 112 }, |
139 | .p1 = { .min = 2, .max = 8 }, |
140 | .p2 = { .dot_limit = 0, |
141 | .p2_slow = 14, .p2_fast = 14 |
142 | }, |
143 | }; |
144 | |
145 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
146 | .dot = { .min = 80000, .max = 224000 }, |
147 | .vco = { .min = 1750000, .max = 3500000 }, |
148 | .n = { .min = 1, .max = 3 }, |
149 | .m = { .min = 104, .max = 138 }, |
150 | .m1 = { .min = 17, .max = 23 }, |
151 | .m2 = { .min = 5, .max = 11 }, |
152 | .p = { .min = 14, .max = 42 }, |
153 | .p1 = { .min = 2, .max = 6 }, |
154 | .p2 = { .dot_limit = 0, |
155 | .p2_slow = 7, .p2_fast = 7 |
156 | }, |
157 | }; |
158 | |
159 | static const struct intel_limit pnv_limits_sdvo = { |
160 | .dot = { .min = 20000, .max = 400000}, |
161 | .vco = { .min = 1700000, .max = 3500000 }, |
162 | /* Pineview's Ncounter is a ring counter */ |
163 | .n = { .min = 3, .max = 6 }, |
164 | .m = { .min = 2, .max = 256 }, |
165 | /* Pineview only has one combined m divider, which we treat as m2. */ |
166 | .m1 = { .min = 0, .max = 0 }, |
167 | .m2 = { .min = 0, .max = 254 }, |
168 | .p = { .min = 5, .max = 80 }, |
169 | .p1 = { .min = 1, .max = 8 }, |
170 | .p2 = { .dot_limit = 200000, |
171 | .p2_slow = 10, .p2_fast = 5 }, |
172 | }; |
173 | |
174 | static const struct intel_limit pnv_limits_lvds = { |
175 | .dot = { .min = 20000, .max = 400000 }, |
176 | .vco = { .min = 1700000, .max = 3500000 }, |
177 | .n = { .min = 3, .max = 6 }, |
178 | .m = { .min = 2, .max = 256 }, |
179 | .m1 = { .min = 0, .max = 0 }, |
180 | .m2 = { .min = 0, .max = 254 }, |
181 | .p = { .min = 7, .max = 112 }, |
182 | .p1 = { .min = 1, .max = 8 }, |
183 | .p2 = { .dot_limit = 112000, |
184 | .p2_slow = 14, .p2_fast = 14 }, |
185 | }; |
186 | |
187 | /* Ironlake / Sandybridge |
188 | * |
189 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
190 | * the range value for them is (actual_value - 2). |
191 | */ |
192 | static const struct intel_limit ilk_limits_dac = { |
193 | .dot = { .min = 25000, .max = 350000 }, |
194 | .vco = { .min = 1760000, .max = 3510000 }, |
195 | .n = { .min = 1, .max = 5 }, |
196 | .m = { .min = 79, .max = 127 }, |
197 | .m1 = { .min = 12, .max = 22 }, |
198 | .m2 = { .min = 5, .max = 9 }, |
199 | .p = { .min = 5, .max = 80 }, |
200 | .p1 = { .min = 1, .max = 8 }, |
201 | .p2 = { .dot_limit = 225000, |
202 | .p2_slow = 10, .p2_fast = 5 }, |
203 | }; |
204 | |
205 | static const struct intel_limit ilk_limits_single_lvds = { |
206 | .dot = { .min = 25000, .max = 350000 }, |
207 | .vco = { .min = 1760000, .max = 3510000 }, |
208 | .n = { .min = 1, .max = 3 }, |
209 | .m = { .min = 79, .max = 118 }, |
210 | .m1 = { .min = 12, .max = 22 }, |
211 | .m2 = { .min = 5, .max = 9 }, |
212 | .p = { .min = 28, .max = 112 }, |
213 | .p1 = { .min = 2, .max = 8 }, |
214 | .p2 = { .dot_limit = 225000, |
215 | .p2_slow = 14, .p2_fast = 14 }, |
216 | }; |
217 | |
218 | static const struct intel_limit ilk_limits_dual_lvds = { |
219 | .dot = { .min = 25000, .max = 350000 }, |
220 | .vco = { .min = 1760000, .max = 3510000 }, |
221 | .n = { .min = 1, .max = 3 }, |
222 | .m = { .min = 79, .max = 127 }, |
223 | .m1 = { .min = 12, .max = 22 }, |
224 | .m2 = { .min = 5, .max = 9 }, |
225 | .p = { .min = 14, .max = 56 }, |
226 | .p1 = { .min = 2, .max = 8 }, |
227 | .p2 = { .dot_limit = 225000, |
228 | .p2_slow = 7, .p2_fast = 7 }, |
229 | }; |
230 | |
231 | /* LVDS 100mhz refclk limits. */ |
232 | static const struct intel_limit ilk_limits_single_lvds_100m = { |
233 | .dot = { .min = 25000, .max = 350000 }, |
234 | .vco = { .min = 1760000, .max = 3510000 }, |
235 | .n = { .min = 1, .max = 2 }, |
236 | .m = { .min = 79, .max = 126 }, |
237 | .m1 = { .min = 12, .max = 22 }, |
238 | .m2 = { .min = 5, .max = 9 }, |
239 | .p = { .min = 28, .max = 112 }, |
240 | .p1 = { .min = 2, .max = 8 }, |
241 | .p2 = { .dot_limit = 225000, |
242 | .p2_slow = 14, .p2_fast = 14 }, |
243 | }; |
244 | |
245 | static const struct intel_limit ilk_limits_dual_lvds_100m = { |
246 | .dot = { .min = 25000, .max = 350000 }, |
247 | .vco = { .min = 1760000, .max = 3510000 }, |
248 | .n = { .min = 1, .max = 3 }, |
249 | .m = { .min = 79, .max = 126 }, |
250 | .m1 = { .min = 12, .max = 22 }, |
251 | .m2 = { .min = 5, .max = 9 }, |
252 | .p = { .min = 14, .max = 42 }, |
253 | .p1 = { .min = 2, .max = 6 }, |
254 | .p2 = { .dot_limit = 225000, |
255 | .p2_slow = 7, .p2_fast = 7 }, |
256 | }; |
257 | |
258 | static const struct intel_limit intel_limits_vlv = { |
259 | /* |
260 | * These are based on the data rate limits (measured in fast clocks) |
261 | * since those are the strictest limits we have. The fast |
262 | * clock and actual rate limits are more relaxed, so checking |
263 | * them would make no difference. |
264 | */ |
265 | .dot = { .min = 25000, .max = 270000 }, |
266 | .vco = { .min = 4000000, .max = 6000000 }, |
267 | .n = { .min = 1, .max = 7 }, |
268 | .m1 = { .min = 2, .max = 3 }, |
269 | .m2 = { .min = 11, .max = 156 }, |
270 | .p1 = { .min = 2, .max = 3 }, |
271 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
272 | }; |
273 | |
274 | static const struct intel_limit intel_limits_chv = { |
275 | /* |
276 | * These are based on the data rate limits (measured in fast clocks) |
277 | * since those are the strictest limits we have. The fast |
278 | * clock and actual rate limits are more relaxed, so checking |
279 | * them would make no difference. |
280 | */ |
281 | .dot = { .min = 25000, .max = 540000 }, |
282 | .vco = { .min = 4800000, .max = 6480000 }, |
283 | .n = { .min = 1, .max = 1 }, |
284 | .m1 = { .min = 2, .max = 2 }, |
285 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
286 | .p1 = { .min = 2, .max = 4 }, |
287 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
288 | }; |
289 | |
290 | static const struct intel_limit intel_limits_bxt = { |
291 | .dot = { .min = 25000, .max = 594000 }, |
292 | .vco = { .min = 4800000, .max = 6700000 }, |
293 | .n = { .min = 1, .max = 1 }, |
294 | .m1 = { .min = 2, .max = 2 }, |
295 | /* FIXME: find real m2 limits */ |
296 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, |
297 | .p1 = { .min = 2, .max = 4 }, |
298 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, |
299 | }; |
300 | |
301 | /* |
302 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), |
303 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
304 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
305 | * The helpers' return value is the rate of the clock that is fed to the |
306 | * display engine's pipe which can be the above fast dot clock rate or a |
307 | * divided-down version of it. |
308 | */ |
309 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
310 | int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
311 | { |
312 | clock->m = clock->m2 + 2; |
313 | clock->p = clock->p1 * clock->p2; |
314 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!(clock->n == 0 || clock->p == 0); if ( __ret) printf("WARNING %s failed at %s:%d\n", "clock->n == 0 || clock->p == 0" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 314); __builtin_expect(!!(__ret), 0); })) |
315 | return 0; |
316 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock-> n)); |
317 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
318 | |
319 | return clock->dot; |
320 | } |
321 | |
322 | static u32 i9xx_dpll_compute_m(const struct dpll *dpll) |
323 | { |
324 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
325 | } |
326 | |
327 | int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
328 | { |
329 | clock->m = i9xx_dpll_compute_m(clock); |
330 | clock->p = clock->p1 * clock->p2; |
331 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)({ int __ret = !!(clock->n + 2 == 0 || clock->p == 0); if (__ret) printf("WARNING %s failed at %s:%d\n", "clock->n + 2 == 0 || clock->p == 0" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 331); __builtin_expect(!!(__ret), 0); })) |
332 | return 0; |
333 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2)(((refclk * clock->m) + ((clock->n + 2) / 2)) / (clock-> n + 2)); |
334 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
335 | |
336 | return clock->dot; |
337 | } |
338 | |
339 | int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
340 | { |
341 | clock->m = clock->m1 * clock->m2; |
342 | clock->p = clock->p1 * clock->p2 * 5; |
343 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!(clock->n == 0 || clock->p == 0); if ( __ret) printf("WARNING %s failed at %s:%d\n", "clock->n == 0 || clock->p == 0" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 343); __builtin_expect(!!(__ret), 0); })) |
344 | return 0; |
345 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock-> n)); |
346 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
347 | |
348 | return clock->dot; |
349 | } |
350 | |
351 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
352 | { |
353 | clock->m = clock->m1 * clock->m2; |
354 | clock->p = clock->p1 * clock->p2 * 5; |
355 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!(clock->n == 0 || clock->p == 0); if ( __ret) printf("WARNING %s failed at %s:%d\n", "clock->n == 0 || clock->p == 0" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 355); __builtin_expect(!!(__ret), 0); })) |
356 | return 0; |
357 | clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),(((mul_u32_u32(refclk, clock->m)) + ((clock->n << 22) / 2)) / (clock->n << 22)) |
358 | clock->n << 22)(((mul_u32_u32(refclk, clock->m)) + ((clock->n << 22) / 2)) / (clock->n << 22)); |
359 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
360 | |
361 | return clock->dot; |
362 | } |
363 | |
364 | /* |
365 | * Returns whether the given set of divisors are valid for a given refclk with |
366 | * the given connectors. |
367 | */ |
368 | static bool_Bool intel_pll_is_valid(struct drm_i915_privateinteldrm_softc *dev_priv, |
369 | const struct intel_limit *limit, |
370 | const struct dpll *clock) |
371 | { |
372 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
373 | return false0; |
374 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
375 | return false0; |
376 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
377 | return false0; |
378 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
379 | return false0; |
380 | |
381 | if (!IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) && !IS_LP(dev_priv)((&(dev_priv)->__info)->is_lp)) |
382 | if (clock->m1 <= clock->m2) |
383 | return false0; |
384 | |
385 | if (!IS_LP(dev_priv)((&(dev_priv)->__info)->is_lp)) { |
386 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
387 | return false0; |
388 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
389 | return false0; |
390 | } |
391 | |
392 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
393 | return false0; |
394 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
395 | * connector, etc., rather than just a single range. |
396 | */ |
397 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
398 | return false0; |
399 | |
400 | return true1; |
401 | } |
402 | |
403 | static int |
404 | i9xx_select_p2_div(const struct intel_limit *limit, |
405 | const struct intel_crtc_state *crtc_state, |
406 | int target) |
407 | { |
408 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
409 | |
410 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
411 | /* |
412 | * For LVDS just rely on its current settings for dual-channel. |
413 | * We haven't figured out how to reliably set up different |
414 | * single/dual channel state, if we even can. |
415 | */ |
416 | if (intel_is_dual_link_lvds(dev_priv)) |
417 | return limit->p2.p2_fast; |
418 | else |
419 | return limit->p2.p2_slow; |
420 | } else { |
421 | if (target < limit->p2.dot_limit) |
422 | return limit->p2.p2_slow; |
423 | else |
424 | return limit->p2.p2_fast; |
425 | } |
426 | } |
427 | |
428 | /* |
429 | * Returns a set of divisors for the desired target clock with the given |
430 | * refclk, or FALSE. |
431 | * |
432 | * Target and reference clocks are specified in kHz. |
433 | * |
434 | * If match_clock is provided, then best_clock P divider must match the P |
435 | * divider from @match_clock used for LVDS downclocking. |
436 | */ |
437 | static bool_Bool |
438 | i9xx_find_best_dpll(const struct intel_limit *limit, |
439 | struct intel_crtc_state *crtc_state, |
440 | int target, int refclk, |
441 | const struct dpll *match_clock, |
442 | struct dpll *best_clock) |
443 | { |
444 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
445 | struct dpll clock; |
446 | int err = target; |
447 | |
448 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
449 | |
450 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
451 | |
452 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
453 | clock.m1++) { |
454 | for (clock.m2 = limit->m2.min; |
455 | clock.m2 <= limit->m2.max; clock.m2++) { |
456 | if (clock.m2 >= clock.m1) |
457 | break; |
458 | for (clock.n = limit->n.min; |
459 | clock.n <= limit->n.max; clock.n++) { |
460 | for (clock.p1 = limit->p1.min; |
461 | clock.p1 <= limit->p1.max; clock.p1++) { |
462 | int this_err; |
463 | |
464 | i9xx_calc_dpll_params(refclk, &clock); |
465 | if (!intel_pll_is_valid(to_i915(dev), |
466 | limit, |
467 | &clock)) |
468 | continue; |
469 | if (match_clock && |
470 | clock.p != match_clock->p) |
471 | continue; |
472 | |
473 | this_err = abs(clock.dot - target); |
474 | if (this_err < err) { |
475 | *best_clock = clock; |
476 | err = this_err; |
477 | } |
478 | } |
479 | } |
480 | } |
481 | } |
482 | |
483 | return (err != target); |
484 | } |
485 | |
486 | /* |
487 | * Returns a set of divisors for the desired target clock with the given |
488 | * refclk, or FALSE. |
489 | * |
490 | * Target and reference clocks are specified in kHz. |
491 | * |
492 | * If match_clock is provided, then best_clock P divider must match the P |
493 | * divider from @match_clock used for LVDS downclocking. |
494 | */ |
495 | static bool_Bool |
496 | pnv_find_best_dpll(const struct intel_limit *limit, |
497 | struct intel_crtc_state *crtc_state, |
498 | int target, int refclk, |
499 | const struct dpll *match_clock, |
500 | struct dpll *best_clock) |
501 | { |
502 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
503 | struct dpll clock; |
504 | int err = target; |
505 | |
506 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
507 | |
508 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
509 | |
510 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
511 | clock.m1++) { |
512 | for (clock.m2 = limit->m2.min; |
513 | clock.m2 <= limit->m2.max; clock.m2++) { |
514 | for (clock.n = limit->n.min; |
515 | clock.n <= limit->n.max; clock.n++) { |
516 | for (clock.p1 = limit->p1.min; |
517 | clock.p1 <= limit->p1.max; clock.p1++) { |
518 | int this_err; |
519 | |
520 | pnv_calc_dpll_params(refclk, &clock); |
521 | if (!intel_pll_is_valid(to_i915(dev), |
522 | limit, |
523 | &clock)) |
524 | continue; |
525 | if (match_clock && |
526 | clock.p != match_clock->p) |
527 | continue; |
528 | |
529 | this_err = abs(clock.dot - target); |
530 | if (this_err < err) { |
531 | *best_clock = clock; |
532 | err = this_err; |
533 | } |
534 | } |
535 | } |
536 | } |
537 | } |
538 | |
539 | return (err != target); |
540 | } |
541 | |
542 | /* |
543 | * Returns a set of divisors for the desired target clock with the given |
544 | * refclk, or FALSE. |
545 | * |
546 | * Target and reference clocks are specified in kHz. |
547 | * |
548 | * If match_clock is provided, then best_clock P divider must match the P |
549 | * divider from @match_clock used for LVDS downclocking. |
550 | */ |
551 | static bool_Bool |
552 | g4x_find_best_dpll(const struct intel_limit *limit, |
553 | struct intel_crtc_state *crtc_state, |
554 | int target, int refclk, |
555 | const struct dpll *match_clock, |
556 | struct dpll *best_clock) |
557 | { |
558 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
559 | struct dpll clock; |
560 | int max_n; |
561 | bool_Bool found = false0; |
562 | /* approximately equals target * 0.00585 */ |
563 | int err_most = (target >> 8) + (target >> 9); |
564 | |
565 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
566 | |
567 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
568 | |
569 | max_n = limit->n.max; |
570 | /* based on hardware requirement, prefer smaller n to precision */ |
571 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
572 | /* based on hardware requirement, prefere larger m1,m2 */ |
573 | for (clock.m1 = limit->m1.max; |
574 | clock.m1 >= limit->m1.min; clock.m1--) { |
575 | for (clock.m2 = limit->m2.max; |
576 | clock.m2 >= limit->m2.min; clock.m2--) { |
577 | for (clock.p1 = limit->p1.max; |
578 | clock.p1 >= limit->p1.min; clock.p1--) { |
579 | int this_err; |
580 | |
581 | i9xx_calc_dpll_params(refclk, &clock); |
582 | if (!intel_pll_is_valid(to_i915(dev), |
583 | limit, |
584 | &clock)) |
585 | continue; |
586 | |
587 | this_err = abs(clock.dot - target); |
588 | if (this_err < err_most) { |
589 | *best_clock = clock; |
590 | err_most = this_err; |
591 | max_n = clock.n; |
592 | found = true1; |
593 | } |
594 | } |
595 | } |
596 | } |
597 | } |
598 | return found; |
599 | } |
600 | |
601 | /* |
602 | * Check if the calculated PLL configuration is more optimal compared to the |
603 | * best configuration and error found so far. Return the calculated error. |
604 | */ |
605 | static bool_Bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
606 | const struct dpll *calculated_clock, |
607 | const struct dpll *best_clock, |
608 | unsigned int best_error_ppm, |
609 | unsigned int *error_ppm) |
610 | { |
611 | /* |
612 | * For CHV ignore the error and consider only the P value. |
613 | * Prefer a bigger P value based on HW requirements. |
614 | */ |
615 | if (IS_CHERRYVIEW(to_i915(dev))IS_PLATFORM(to_i915(dev), INTEL_CHERRYVIEW)) { |
616 | *error_ppm = 0; |
617 | |
618 | return calculated_clock->p > best_clock->p; |
619 | } |
620 | |
621 | if (drm_WARN_ON_ONCE(dev, !target_freq)({ static int __warned; int __ret = !!((!target_freq)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string (((dev))->dev), "", "drm_WARN_ON_ONCE(" "!target_freq" ")" ); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
622 | return false0; |
623 | |
624 | *error_ppm = div_u64(1000000ULL * |
625 | abs(target_freq - calculated_clock->dot), |
626 | target_freq); |
627 | /* |
628 | * Prefer a better P value over a better (smaller) error if the error |
629 | * is small. Ensure this preference for future configurations too by |
630 | * setting the error to 0. |
631 | */ |
632 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
633 | *error_ppm = 0; |
634 | |
635 | return true1; |
636 | } |
637 | |
638 | return *error_ppm + 10 < best_error_ppm; |
639 | } |
640 | |
641 | /* |
642 | * Returns a set of divisors for the desired target clock with the given |
643 | * refclk, or FALSE. |
644 | */ |
645 | static bool_Bool |
646 | vlv_find_best_dpll(const struct intel_limit *limit, |
647 | struct intel_crtc_state *crtc_state, |
648 | int target, int refclk, |
649 | const struct dpll *match_clock, |
650 | struct dpll *best_clock) |
651 | { |
652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
653 | struct drm_device *dev = crtc->base.dev; |
654 | struct dpll clock; |
655 | unsigned int bestppm = 1000000; |
656 | /* min update 19.2 MHz */ |
657 | int max_n = min(limit->n.max, refclk / 19200)(((limit->n.max)<(refclk / 19200))?(limit->n.max):(refclk / 19200)); |
658 | bool_Bool found = false0; |
659 | |
660 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
661 | |
662 | /* based on hardware requirement, prefer smaller n to precision */ |
663 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
664 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
665 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
666 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
667 | clock.p = clock.p1 * clock.p2 * 5; |
668 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
669 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
670 | unsigned int ppm; |
671 | |
672 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)) |
673 | refclk * clock.m1)(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)); |
674 | |
675 | vlv_calc_dpll_params(refclk, &clock); |
676 | |
677 | if (!intel_pll_is_valid(to_i915(dev), |
678 | limit, |
679 | &clock)) |
680 | continue; |
681 | |
682 | if (!vlv_PLL_is_optimal(dev, target, |
683 | &clock, |
684 | best_clock, |
685 | bestppm, &ppm)) |
686 | continue; |
687 | |
688 | *best_clock = clock; |
689 | bestppm = ppm; |
690 | found = true1; |
691 | } |
692 | } |
693 | } |
694 | } |
695 | |
696 | return found; |
697 | } |
698 | |
699 | /* |
700 | * Returns a set of divisors for the desired target clock with the given |
701 | * refclk, or FALSE. |
702 | */ |
703 | static bool_Bool |
704 | chv_find_best_dpll(const struct intel_limit *limit, |
705 | struct intel_crtc_state *crtc_state, |
706 | int target, int refclk, |
707 | const struct dpll *match_clock, |
708 | struct dpll *best_clock) |
709 | { |
710 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
711 | struct drm_device *dev = crtc->base.dev; |
712 | unsigned int best_error_ppm; |
713 | struct dpll clock; |
714 | u64 m2; |
715 | int found = false0; |
716 | |
717 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
718 | best_error_ppm = 1000000; |
719 | |
720 | /* |
721 | * Based on hardware doc, the n always set to 1, and m1 always |
722 | * set to 2. If requires to support 200Mhz refclk, we need to |
723 | * revisit this because n may not 1 anymore. |
724 | */ |
725 | clock.n = 1; |
726 | clock.m1 = 2; |
727 | |
728 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
729 | for (clock.p2 = limit->p2.p2_fast; |
730 | clock.p2 >= limit->p2.p2_slow; |
731 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
732 | unsigned int error_ppm; |
733 | |
734 | clock.p = clock.p1 * clock.p2 * 5; |
735 | |
736 | m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)) |
737 | refclk * clock.m1)(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)); |
738 | |
739 | if (m2 > INT_MAX0x7fffffff/clock.m1) |
740 | continue; |
741 | |
742 | clock.m2 = m2; |
743 | |
744 | chv_calc_dpll_params(refclk, &clock); |
745 | |
746 | if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) |
747 | continue; |
748 | |
749 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
750 | best_error_ppm, &error_ppm)) |
751 | continue; |
752 | |
753 | *best_clock = clock; |
754 | best_error_ppm = error_ppm; |
755 | found = true1; |
756 | } |
757 | } |
758 | |
759 | return found; |
760 | } |
761 | |
762 | bool_Bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
763 | struct dpll *best_clock) |
764 | { |
765 | const struct intel_limit *limit = &intel_limits_bxt; |
766 | int refclk = 100000; |
767 | |
768 | return chv_find_best_dpll(limit, crtc_state, |
769 | crtc_state->port_clock, refclk, |
770 | NULL((void *)0), best_clock); |
771 | } |
772 | |
773 | u32 i9xx_dpll_compute_fp(const struct dpll *dpll) |
774 | { |
775 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
776 | } |
777 | |
778 | static u32 pnv_dpll_compute_fp(const struct dpll *dpll) |
779 | { |
780 | return (1 << dpll->n) << 16 | dpll->m2; |
781 | } |
782 | |
783 | static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, |
784 | const struct dpll *clock, |
785 | const struct dpll *reduced_clock) |
786 | { |
787 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
788 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
789 | u32 fp, fp2; |
790 | |
791 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
792 | fp = pnv_dpll_compute_fp(clock); |
793 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
794 | } else { |
795 | fp = i9xx_dpll_compute_fp(clock); |
796 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
797 | } |
798 | |
799 | crtc_state->dpll_hw_state.fp0 = fp; |
800 | crtc_state->dpll_hw_state.fp1 = fp2; |
801 | } |
802 | |
803 | static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, |
804 | const struct dpll *clock, |
805 | const struct dpll *reduced_clock) |
806 | { |
807 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
808 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
809 | u32 dpll; |
810 | |
811 | i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); |
812 | |
813 | dpll = DPLL_VGA_MODE_DIS(1 << 28); |
814 | |
815 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
816 | dpll |= DPLLB_MODE_LVDS(2 << 26); |
817 | else |
818 | dpll |= DPLLB_MODE_DAC_SERIAL(1 << 26); |
819 | |
820 | if (IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) || IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) || |
821 | IS_G33(dev_priv)IS_PLATFORM(dev_priv, INTEL_G33) || IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
822 | dpll |= (crtc_state->pixel_multiplier - 1) |
823 | << SDVO_MULTIPLIER_SHIFT_HIRES4; |
824 | } |
825 | |
826 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
827 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
828 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
829 | |
830 | if (intel_crtc_has_dp_encoder(crtc_state)) |
831 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
832 | |
833 | /* compute bitmask from p1 value */ |
834 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
835 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
836 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT0; |
837 | } else if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
838 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW15; |
839 | WARN_ON(reduced_clock->p1 != clock->p1)({ int __ret = !!(reduced_clock->p1 != clock->p1); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p1 != clock->p1" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 839); __builtin_expect(!!(__ret), 0); }); |
840 | } else { |
841 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
842 | WARN_ON(reduced_clock->p1 != clock->p1)({ int __ret = !!(reduced_clock->p1 != clock->p1); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p1 != clock->p1" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 842); __builtin_expect(!!(__ret), 0); }); |
843 | } |
844 | |
845 | switch (clock->p2) { |
846 | case 5: |
847 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24); |
848 | break; |
849 | case 7: |
850 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24); |
851 | break; |
852 | case 10: |
853 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10(0 << 24); |
854 | break; |
855 | case 14: |
856 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14(0 << 24); |
857 | break; |
858 | } |
859 | WARN_ON(reduced_clock->p2 != clock->p2)({ int __ret = !!(reduced_clock->p2 != clock->p2); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p2 != clock->p2" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 859); __builtin_expect(!!(__ret), 0); }); |
860 | |
861 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
862 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT9); |
863 | |
864 | if (crtc_state->sdvo_tv_clock) |
865 | dpll |= PLL_REF_INPUT_TVCLKINBC(2 << 13); |
866 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
867 | intel_panel_use_ssc(dev_priv)) |
868 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
869 | else |
870 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
871 | |
872 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
873 | crtc_state->dpll_hw_state.dpll = dpll; |
874 | |
875 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
876 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
877 | << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
878 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
879 | } |
880 | } |
881 | |
882 | static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, |
883 | const struct dpll *clock, |
884 | const struct dpll *reduced_clock) |
885 | { |
886 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
887 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
888 | u32 dpll; |
889 | |
890 | i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); |
891 | |
892 | dpll = DPLL_VGA_MODE_DIS(1 << 28); |
893 | |
894 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
895 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
896 | } else { |
897 | if (clock->p1 == 2) |
898 | dpll |= PLL_P1_DIVIDE_BY_TWO(1 << 21); |
899 | else |
900 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
901 | if (clock->p2 == 4) |
902 | dpll |= PLL_P2_DIVIDE_BY_4(1 << 23); |
903 | } |
904 | WARN_ON(reduced_clock->p1 != clock->p1)({ int __ret = !!(reduced_clock->p1 != clock->p1); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p1 != clock->p1" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 904); __builtin_expect(!!(__ret), 0); }); |
905 | WARN_ON(reduced_clock->p2 != clock->p2)({ int __ret = !!(reduced_clock->p2 != clock->p2); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p2 != clock->p2" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 905); __builtin_expect(!!(__ret), 0); }); |
906 | |
907 | /* |
908 | * Bspec: |
909 | * "[Almador Errata}: For the correct operation of the muxed DVO pins |
910 | * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, |
911 | * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock |
912 | * Enable) must be set to “1” in both the DPLL A Control Register |
913 | * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." |
914 | * |
915 | * For simplicity We simply keep both bits always enabled in |
916 | * both DPLLS. The spec says we should disable the DVO 2X clock |
917 | * when not needed, but this seems to work fine in practice. |
918 | */ |
919 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) || |
920 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
921 | dpll |= DPLL_DVO_2X_MODE(1 << 30); |
922 | |
923 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
924 | intel_panel_use_ssc(dev_priv)) |
925 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
926 | else |
927 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
928 | |
929 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
930 | crtc_state->dpll_hw_state.dpll = dpll; |
931 | } |
932 | |
933 | static int hsw_crtc_compute_clock(struct intel_atomic_state *state, |
934 | struct intel_crtc *crtc) |
935 | { |
936 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
937 | struct intel_crtc_state *crtc_state = |
938 | intel_atomic_get_new_crtc_state(state, crtc); |
939 | struct intel_encoder *encoder = |
940 | intel_get_crtc_new_encoder(state, crtc_state); |
941 | int ret; |
942 | |
943 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 11 && |
944 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
945 | return 0; |
946 | |
947 | ret = intel_compute_shared_dplls(state, crtc, encoder); |
948 | if (ret) |
949 | return ret; |
950 | |
951 | /* FIXME this is a mess */ |
952 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
953 | return 0; |
954 | |
955 | /* CRT dotclock is determined via other means */ |
956 | if (!crtc_state->has_pch_encoder) |
957 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
958 | |
959 | return 0; |
960 | } |
961 | |
962 | static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, |
963 | struct intel_crtc *crtc) |
964 | { |
965 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
966 | struct intel_crtc_state *crtc_state = |
967 | intel_atomic_get_new_crtc_state(state, crtc); |
968 | struct intel_encoder *encoder = |
969 | intel_get_crtc_new_encoder(state, crtc_state); |
970 | |
971 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 11 && |
972 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
973 | return 0; |
974 | |
975 | return intel_reserve_shared_dplls(state, crtc, encoder); |
976 | } |
977 | |
978 | static int dg2_crtc_compute_clock(struct intel_atomic_state *state, |
979 | struct intel_crtc *crtc) |
980 | { |
981 | struct intel_crtc_state *crtc_state = |
982 | intel_atomic_get_new_crtc_state(state, crtc); |
983 | struct intel_encoder *encoder = |
984 | intel_get_crtc_new_encoder(state, crtc_state); |
985 | int ret; |
986 | |
987 | ret = intel_mpllb_calc_state(crtc_state, encoder); |
988 | if (ret) |
989 | return ret; |
990 | |
991 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
992 | |
993 | return 0; |
994 | } |
995 | |
996 | static bool_Bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) |
997 | { |
998 | return dpll->m < factor * dpll->n; |
999 | } |
1000 | |
1001 | static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, |
1002 | const struct dpll *clock, |
1003 | const struct dpll *reduced_clock) |
1004 | { |
1005 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1006 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1007 | u32 fp, fp2; |
1008 | int factor; |
1009 | |
1010 | /* Enable autotuning of the PLL clock (if permissible) */ |
1011 | factor = 21; |
1012 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1013 | if ((intel_panel_use_ssc(dev_priv) && |
1014 | dev_priv->display.vbt.lvds_ssc_freq == 100000) || |
1015 | (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) && |
1016 | intel_is_dual_link_lvds(dev_priv))) |
1017 | factor = 25; |
1018 | } else if (crtc_state->sdvo_tv_clock) { |
1019 | factor = 20; |
1020 | } |
1021 | |
1022 | fp = i9xx_dpll_compute_fp(clock); |
1023 | if (ilk_needs_fb_cb_tune(clock, factor)) |
1024 | fp |= FP_CB_TUNE(0x3 << 22); |
1025 | |
1026 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
1027 | if (ilk_needs_fb_cb_tune(reduced_clock, factor)) |
1028 | fp2 |= FP_CB_TUNE(0x3 << 22); |
1029 | |
1030 | crtc_state->dpll_hw_state.fp0 = fp; |
1031 | crtc_state->dpll_hw_state.fp1 = fp2; |
1032 | } |
1033 | |
1034 | static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, |
1035 | const struct dpll *clock, |
1036 | const struct dpll *reduced_clock) |
1037 | { |
1038 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1039 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1040 | u32 dpll; |
1041 | |
1042 | ilk_update_pll_dividers(crtc_state, clock, reduced_clock); |
1043 | |
1044 | dpll = 0; |
1045 | |
1046 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
1047 | dpll |= DPLLB_MODE_LVDS(2 << 26); |
1048 | else |
1049 | dpll |= DPLLB_MODE_DAC_SERIAL(1 << 26); |
1050 | |
1051 | dpll |= (crtc_state->pixel_multiplier - 1) |
1052 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT9; |
1053 | |
1054 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
1055 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
1056 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
1057 | |
1058 | if (intel_crtc_has_dp_encoder(crtc_state)) |
1059 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
1060 | |
1061 | /* |
1062 | * The high speed IO clock is only really required for |
1063 | * SDVO/HDMI/DP, but we also enable it for CRT to make it |
1064 | * possible to share the DPLL between CRT and HDMI. Enabling |
1065 | * the clock needlessly does no real harm, except use up a |
1066 | * bit of power potentially. |
1067 | * |
1068 | * We'll limit this to IVB with 3 pipes, since it has only two |
1069 | * DPLLs and so DPLL sharing is the only way to get three pipes |
1070 | * driving PCH ports at the same time. On SNB we could do this, |
1071 | * and potentially avoid enabling the second DPLL, but it's not |
1072 | * clear if it''s a win or loss power wise. No point in doing |
1073 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. |
1074 | */ |
1075 | if (INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__runtime)->pipe_mask)) == 3 && |
1076 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) |
1077 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
1078 | |
1079 | /* compute bitmask from p1 value */ |
1080 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
1081 | /* also FPA1 */ |
1082 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT0; |
1083 | |
1084 | switch (clock->p2) { |
1085 | case 5: |
1086 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24); |
1087 | break; |
1088 | case 7: |
1089 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24); |
1090 | break; |
1091 | case 10: |
1092 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10(0 << 24); |
1093 | break; |
1094 | case 14: |
1095 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14(0 << 24); |
1096 | break; |
1097 | } |
1098 | WARN_ON(reduced_clock->p2 != clock->p2)({ int __ret = !!(reduced_clock->p2 != clock->p2); if ( __ret) printf("WARNING %s failed at %s:%d\n", "reduced_clock->p2 != clock->p2" , "/usr/src/sys/dev/pci/drm/i915/display/intel_dpll.c", 1098) ; __builtin_expect(!!(__ret), 0); }); |
1099 | |
1100 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
1101 | intel_panel_use_ssc(dev_priv)) |
1102 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
1103 | else |
1104 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
1105 | |
1106 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
1107 | |
1108 | crtc_state->dpll_hw_state.dpll = dpll; |
1109 | } |
1110 | |
1111 | static int ilk_crtc_compute_clock(struct intel_atomic_state *state, |
1112 | struct intel_crtc *crtc) |
1113 | { |
1114 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
1115 | struct intel_crtc_state *crtc_state = |
1116 | intel_atomic_get_new_crtc_state(state, crtc); |
1117 | const struct intel_limit *limit; |
1118 | int refclk = 120000; |
1119 | int ret; |
1120 | |
1121 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
1122 | if (!crtc_state->has_pch_encoder) |
1123 | return 0; |
1124 | |
1125 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1126 | if (intel_panel_use_ssc(dev_priv)) { |
1127 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->display.vbt.lvds_ssc_freq) |
1128 | "using SSC reference clock of %d kHz\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->display.vbt.lvds_ssc_freq) |
1129 | dev_priv->display.vbt.lvds_ssc_freq)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->display.vbt.lvds_ssc_freq); |
1130 | refclk = dev_priv->display.vbt.lvds_ssc_freq; |
1131 | } |
1132 | |
1133 | if (intel_is_dual_link_lvds(dev_priv)) { |
1134 | if (refclk == 100000) |
1135 | limit = &ilk_limits_dual_lvds_100m; |
1136 | else |
1137 | limit = &ilk_limits_dual_lvds; |
1138 | } else { |
1139 | if (refclk == 100000) |
1140 | limit = &ilk_limits_single_lvds_100m; |
1141 | else |
1142 | limit = &ilk_limits_single_lvds; |
1143 | } |
1144 | } else { |
1145 | limit = &ilk_limits_dac; |
1146 | } |
1147 | |
1148 | if (!crtc_state->clock_set && |
1149 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1150 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1151 | return -EINVAL22; |
1152 | |
1153 | ilk_compute_dpll(crtc_state, &crtc_state->dpll, |
1154 | &crtc_state->dpll); |
1155 | |
1156 | ret = intel_compute_shared_dplls(state, crtc, NULL((void *)0)); |
1157 | if (ret) |
1158 | return ret; |
1159 | |
1160 | crtc_state->port_clock = crtc_state->dpll.dot; |
1161 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1162 | |
1163 | return ret; |
1164 | } |
1165 | |
1166 | static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, |
1167 | struct intel_crtc *crtc) |
1168 | { |
1169 | struct intel_crtc_state *crtc_state = |
1170 | intel_atomic_get_new_crtc_state(state, crtc); |
1171 | |
1172 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
1173 | if (!crtc_state->has_pch_encoder) |
1174 | return 0; |
1175 | |
1176 | return intel_reserve_shared_dplls(state, crtc, NULL((void *)0)); |
1177 | } |
1178 | |
1179 | void vlv_compute_dpll(struct intel_crtc_state *crtc_state) |
1180 | { |
1181 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1182 | |
1183 | crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) | |
1184 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
1185 | if (crtc->pipe != PIPE_A) |
1186 | crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
1187 | |
1188 | /* DPLL not used with DSI, but still need the rest set up */ |
1189 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
1190 | crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE(1 << 31) | |
1191 | DPLL_EXT_BUFFER_ENABLE_VLV(1 << 30); |
1192 | |
1193 | crtc_state->dpll_hw_state.dpll_md = |
1194 | (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
1195 | } |
1196 | |
1197 | void chv_compute_dpll(struct intel_crtc_state *crtc_state) |
1198 | { |
1199 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1200 | |
1201 | crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV(1 << 13) | |
1202 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
1203 | if (crtc->pipe != PIPE_A) |
1204 | crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
1205 | |
1206 | /* DPLL not used with DSI, but still need the rest set up */ |
1207 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
1208 | crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE(1 << 31); |
1209 | |
1210 | crtc_state->dpll_hw_state.dpll_md = |
1211 | (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
1212 | } |
1213 | |
1214 | static int chv_crtc_compute_clock(struct intel_atomic_state *state, |
1215 | struct intel_crtc *crtc) |
1216 | { |
1217 | struct intel_crtc_state *crtc_state = |
1218 | intel_atomic_get_new_crtc_state(state, crtc); |
1219 | const struct intel_limit *limit = &intel_limits_chv; |
1220 | int refclk = 100000; |
1221 | |
1222 | if (!crtc_state->clock_set && |
1223 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1224 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1225 | return -EINVAL22; |
1226 | |
1227 | chv_compute_dpll(crtc_state); |
1228 | |
1229 | /* FIXME this is a mess */ |
1230 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
1231 | return 0; |
1232 | |
1233 | crtc_state->port_clock = crtc_state->dpll.dot; |
1234 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1235 | |
1236 | return 0; |
1237 | } |
1238 | |
1239 | static int vlv_crtc_compute_clock(struct intel_atomic_state *state, |
1240 | struct intel_crtc *crtc) |
1241 | { |
1242 | struct intel_crtc_state *crtc_state = |
1243 | intel_atomic_get_new_crtc_state(state, crtc); |
1244 | const struct intel_limit *limit = &intel_limits_vlv; |
1245 | int refclk = 100000; |
1246 | |
1247 | if (!crtc_state->clock_set && |
1248 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1249 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
1250 | return -EINVAL22; |
1251 | } |
1252 | |
1253 | vlv_compute_dpll(crtc_state); |
1254 | |
1255 | /* FIXME this is a mess */ |
1256 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
1257 | return 0; |
1258 | |
1259 | crtc_state->port_clock = crtc_state->dpll.dot; |
1260 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1261 | |
1262 | return 0; |
1263 | } |
1264 | |
1265 | static int g4x_crtc_compute_clock(struct intel_atomic_state *state, |
1266 | struct intel_crtc *crtc) |
1267 | { |
1268 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
1269 | struct intel_crtc_state *crtc_state = |
1270 | intel_atomic_get_new_crtc_state(state, crtc); |
1271 | const struct intel_limit *limit; |
1272 | int refclk = 96000; |
1273 | |
1274 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1275 | if (intel_panel_use_ssc(dev_priv)) { |
1276 | refclk = dev_priv->display.vbt.lvds_ssc_freq; |
1277 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1278 | "using SSC reference clock of %d kHz\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1279 | refclk)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
1280 | } |
1281 | |
1282 | if (intel_is_dual_link_lvds(dev_priv)) |
1283 | limit = &intel_limits_g4x_dual_channel_lvds; |
1284 | else |
1285 | limit = &intel_limits_g4x_single_channel_lvds; |
1286 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
1287 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
1288 | limit = &intel_limits_g4x_hdmi; |
1289 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
1290 | limit = &intel_limits_g4x_sdvo; |
1291 | } else { |
1292 | /* The option is for other outputs */ |
1293 | limit = &intel_limits_i9xx_sdvo; |
1294 | } |
1295 | |
1296 | if (!crtc_state->clock_set && |
1297 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1298 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1299 | return -EINVAL22; |
1300 | |
1301 | i9xx_compute_dpll(crtc_state, &crtc_state->dpll, |
1302 | &crtc_state->dpll); |
1303 | |
1304 | crtc_state->port_clock = crtc_state->dpll.dot; |
1305 | /* FIXME this is a mess */ |
1306 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) |
1307 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1308 | |
1309 | return 0; |
1310 | } |
1311 | |
1312 | static int pnv_crtc_compute_clock(struct intel_atomic_state *state, |
1313 | struct intel_crtc *crtc) |
1314 | { |
1315 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
1316 | struct intel_crtc_state *crtc_state = |
1317 | intel_atomic_get_new_crtc_state(state, crtc); |
1318 | const struct intel_limit *limit; |
1319 | int refclk = 96000; |
1320 | |
1321 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1322 | if (intel_panel_use_ssc(dev_priv)) { |
1323 | refclk = dev_priv->display.vbt.lvds_ssc_freq; |
1324 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1325 | "using SSC reference clock of %d kHz\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1326 | refclk)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
1327 | } |
1328 | |
1329 | limit = &pnv_limits_lvds; |
1330 | } else { |
1331 | limit = &pnv_limits_sdvo; |
1332 | } |
1333 | |
1334 | if (!crtc_state->clock_set && |
1335 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1336 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1337 | return -EINVAL22; |
1338 | |
1339 | i9xx_compute_dpll(crtc_state, &crtc_state->dpll, |
1340 | &crtc_state->dpll); |
1341 | |
1342 | crtc_state->port_clock = crtc_state->dpll.dot; |
1343 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1344 | |
1345 | return 0; |
1346 | } |
1347 | |
1348 | static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, |
1349 | struct intel_crtc *crtc) |
1350 | { |
1351 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
1352 | struct intel_crtc_state *crtc_state = |
1353 | intel_atomic_get_new_crtc_state(state, crtc); |
1354 | const struct intel_limit *limit; |
1355 | int refclk = 96000; |
1356 | |
1357 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1358 | if (intel_panel_use_ssc(dev_priv)) { |
1359 | refclk = dev_priv->display.vbt.lvds_ssc_freq; |
1360 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1361 | "using SSC reference clock of %d kHz\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1362 | refclk)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
1363 | } |
1364 | |
1365 | limit = &intel_limits_i9xx_lvds; |
1366 | } else { |
1367 | limit = &intel_limits_i9xx_sdvo; |
1368 | } |
1369 | |
1370 | if (!crtc_state->clock_set && |
1371 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1372 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1373 | return -EINVAL22; |
1374 | |
1375 | i9xx_compute_dpll(crtc_state, &crtc_state->dpll, |
1376 | &crtc_state->dpll); |
1377 | |
1378 | crtc_state->port_clock = crtc_state->dpll.dot; |
1379 | /* FIXME this is a mess */ |
1380 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) |
1381 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1382 | |
1383 | return 0; |
1384 | } |
1385 | |
1386 | static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, |
1387 | struct intel_crtc *crtc) |
1388 | { |
1389 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
1390 | struct intel_crtc_state *crtc_state = |
1391 | intel_atomic_get_new_crtc_state(state, crtc); |
1392 | const struct intel_limit *limit; |
1393 | int refclk = 48000; |
1394 | |
1395 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1396 | if (intel_panel_use_ssc(dev_priv)) { |
1397 | refclk = dev_priv->display.vbt.lvds_ssc_freq; |
1398 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1399 | "using SSC reference clock of %d kHz\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
1400 | refclk)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
1401 | } |
1402 | |
1403 | limit = &intel_limits_i8xx_lvds; |
1404 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
1405 | limit = &intel_limits_i8xx_dvo; |
1406 | } else { |
1407 | limit = &intel_limits_i8xx_dac; |
1408 | } |
1409 | |
1410 | if (!crtc_state->clock_set && |
1411 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
1412 | refclk, NULL((void *)0), &crtc_state->dpll)) |
1413 | return -EINVAL22; |
1414 | |
1415 | i8xx_compute_dpll(crtc_state, &crtc_state->dpll, |
1416 | &crtc_state->dpll); |
1417 | |
1418 | crtc_state->port_clock = crtc_state->dpll.dot; |
1419 | crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); |
1420 | |
1421 | return 0; |
1422 | } |
1423 | |
1424 | static const struct intel_dpll_funcs dg2_dpll_funcs = { |
1425 | .crtc_compute_clock = dg2_crtc_compute_clock, |
1426 | }; |
1427 | |
1428 | static const struct intel_dpll_funcs hsw_dpll_funcs = { |
1429 | .crtc_compute_clock = hsw_crtc_compute_clock, |
1430 | .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, |
1431 | }; |
1432 | |
1433 | static const struct intel_dpll_funcs ilk_dpll_funcs = { |
1434 | .crtc_compute_clock = ilk_crtc_compute_clock, |
1435 | .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, |
1436 | }; |
1437 | |
1438 | static const struct intel_dpll_funcs chv_dpll_funcs = { |
1439 | .crtc_compute_clock = chv_crtc_compute_clock, |
1440 | }; |
1441 | |
1442 | static const struct intel_dpll_funcs vlv_dpll_funcs = { |
1443 | .crtc_compute_clock = vlv_crtc_compute_clock, |
1444 | }; |
1445 | |
1446 | static const struct intel_dpll_funcs g4x_dpll_funcs = { |
1447 | .crtc_compute_clock = g4x_crtc_compute_clock, |
1448 | }; |
1449 | |
1450 | static const struct intel_dpll_funcs pnv_dpll_funcs = { |
1451 | .crtc_compute_clock = pnv_crtc_compute_clock, |
1452 | }; |
1453 | |
1454 | static const struct intel_dpll_funcs i9xx_dpll_funcs = { |
1455 | .crtc_compute_clock = i9xx_crtc_compute_clock, |
1456 | }; |
1457 | |
1458 | static const struct intel_dpll_funcs i8xx_dpll_funcs = { |
1459 | .crtc_compute_clock = i8xx_crtc_compute_clock, |
1460 | }; |
1461 | |
1462 | int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, |
1463 | struct intel_crtc *crtc) |
1464 | { |
1465 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(state->base.dev); |
1466 | struct intel_crtc_state *crtc_state = |
1467 | intel_atomic_get_new_crtc_state(state, crtc); |
1468 | int ret; |
1469 | |
1470 | drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state))({ int __ret = !!((!intel_crtc_needs_modeset(crtc_state))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915 ->drm))->dev), "", "drm_WARN_ON(" "!intel_crtc_needs_modeset(crtc_state)" ")"); __builtin_expect(!!(__ret), 0); }); |
1471 | |
1472 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
1473 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
1474 | |
1475 | if (!crtc_state->hw.enable) |
1476 | return 0; |
1477 | |
1478 | ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); |
1479 | if (ret) { |
1480 | drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n" , crtc->base.base.id, crtc->base.name) |
1481 | crtc->base.base.id, crtc->base.name)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n" , crtc->base.base.id, crtc->base.name); |
1482 | return ret; |
1483 | } |
1484 | |
1485 | return 0; |
1486 | } |
1487 | |
1488 | int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, |
1489 | struct intel_crtc *crtc) |
1490 | { |
1491 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(state->base.dev); |
1492 | struct intel_crtc_state *crtc_state = |
1493 | intel_atomic_get_new_crtc_state(state, crtc); |
1494 | int ret; |
1495 | |
1496 | drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state))({ int __ret = !!((!intel_crtc_needs_modeset(crtc_state))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915 ->drm))->dev), "", "drm_WARN_ON(" "!intel_crtc_needs_modeset(crtc_state)" ")"); __builtin_expect(!!(__ret), 0); }); |
1497 | drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll)({ int __ret = !!((!crtc_state->hw.enable && crtc_state ->shared_dpll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!crtc_state->hw.enable && crtc_state->shared_dpll" ")"); __builtin_expect(!!(__ret), 0); }); |
1498 | |
1499 | if (!crtc_state->hw.enable || crtc_state->shared_dpll) |
1500 | return 0; |
1501 | |
1502 | if (!i915->display.funcs.dpll->crtc_get_shared_dpll) |
1503 | return 0; |
1504 | |
1505 | ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); |
1506 | if (ret) { |
1507 | drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CRTC:%d:%s] Couldn't get a shared DPLL\n" , crtc->base.base.id, crtc->base.name) |
1508 | crtc->base.base.id, crtc->base.name)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CRTC:%d:%s] Couldn't get a shared DPLL\n" , crtc->base.base.id, crtc->base.name); |
1509 | return ret; |
1510 | } |
1511 | |
1512 | return 0; |
1513 | } |
1514 | |
1515 | void |
1516 | intel_dpll_init_clock_hook(struct drm_i915_privateinteldrm_softc *dev_priv) |
1517 | { |
1518 | if (IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2)) |
1519 | dev_priv->display.funcs.dpll = &dg2_dpll_funcs; |
1520 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9 || HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
1521 | dev_priv->display.funcs.dpll = &hsw_dpll_funcs; |
1522 | else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) |
1523 | dev_priv->display.funcs.dpll = &ilk_dpll_funcs; |
1524 | else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
1525 | dev_priv->display.funcs.dpll = &chv_dpll_funcs; |
1526 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)) |
1527 | dev_priv->display.funcs.dpll = &vlv_dpll_funcs; |
1528 | else if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
1529 | dev_priv->display.funcs.dpll = &g4x_dpll_funcs; |
1530 | else if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) |
1531 | dev_priv->display.funcs.dpll = &pnv_dpll_funcs; |
1532 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) != 2) |
1533 | dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; |
1534 | else |
1535 | dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; |
1536 | } |
1537 | |
1538 | static bool_Bool i9xx_has_pps(struct drm_i915_privateinteldrm_softc *dev_priv) |
1539 | { |
1540 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
1541 | return false0; |
1542 | |
1543 | return IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) || IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile); |
1544 | } |
1545 | |
1546 | void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) |
1547 | { |
1548 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1549 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1550 | u32 dpll = crtc_state->dpll_hw_state.dpll; |
1551 | enum pipe pipe = crtc->pipe; |
1552 | int i; |
1553 | |
1554 | assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder)assert_transcoder(dev_priv, crtc_state->cpu_transcoder, 0); |
1555 | |
1556 | /* PLL is protected by panel, make sure we can write it */ |
1557 | if (i9xx_has_pps(dev_priv)) |
1558 | assert_pps_unlocked(dev_priv, pipe); |
1559 | |
1560 | intel_de_write(dev_priv, FP0(pipe)((const i915_reg_t){ .reg = (((0x6040) + (pipe) * ((0x6048) - (0x6040)))) }), crtc_state->dpll_hw_state.fp0); |
1561 | intel_de_write(dev_priv, FP1(pipe)((const i915_reg_t){ .reg = (((0x6044) + (pipe) * ((0x604c) - (0x6044)))) }), crtc_state->dpll_hw_state.fp1); |
1562 | |
1563 | /* |
1564 | * Apparently we need to have VGA mode enabled prior to changing |
1565 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
1566 | * dividers, even though the register value does change. |
1567 | */ |
1568 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), dpll & ~DPLL_VGA_MODE_DIS(1 << 28)); |
1569 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
1570 | |
1571 | /* Wait for the clocks to stabilize. */ |
1572 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
1573 | udelay(150); |
1574 | |
1575 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
1576 | intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(pipe)])) }), |
1577 | crtc_state->dpll_hw_state.dpll_md); |
1578 | } else { |
1579 | /* The pixel multiplier can only be updated once the |
1580 | * DPLL is enabled and the clocks are stable. |
1581 | * |
1582 | * So write it again. |
1583 | */ |
1584 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
1585 | } |
1586 | |
1587 | /* We do this three times for luck */ |
1588 | for (i = 0; i < 3; i++) { |
1589 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
1590 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
1591 | udelay(150); /* wait for warmup */ |
1592 | } |
1593 | } |
1594 | |
1595 | static void vlv_pllb_recal_opamp(struct drm_i915_privateinteldrm_softc *dev_priv, |
1596 | enum pipe pipe) |
1597 | { |
1598 | u32 reg_val; |
1599 | |
1600 | /* |
1601 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
1602 | * and set it to a reasonable value instead. |
1603 | */ |
1604 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044)))); |
1605 | reg_val &= 0xffffff00; |
1606 | reg_val |= 0x00000030; |
1607 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044))), reg_val); |
1608 | |
1609 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW130x80ac); |
1610 | reg_val &= 0x00ffffff; |
1611 | reg_val |= 0x8c000000; |
1612 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW130x80ac, reg_val); |
1613 | |
1614 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044)))); |
1615 | reg_val &= 0xffffff00; |
1616 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044))), reg_val); |
1617 | |
1618 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW130x80ac); |
1619 | reg_val &= 0x00ffffff; |
1620 | reg_val |= 0xb0000000; |
1621 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW130x80ac, reg_val); |
1622 | } |
1623 | |
1624 | static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) |
1625 | { |
1626 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1627 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1628 | enum pipe pipe = crtc->pipe; |
1629 | u32 mdiv; |
1630 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
1631 | u32 coreclk, reg_val; |
1632 | |
1633 | vlv_dpio_get(dev_priv); |
1634 | |
1635 | bestn = crtc_state->dpll.n; |
1636 | bestm1 = crtc_state->dpll.m1; |
1637 | bestm2 = crtc_state->dpll.m2; |
1638 | bestp1 = crtc_state->dpll.p1; |
1639 | bestp2 = crtc_state->dpll.p2; |
1640 | |
1641 | /* See eDP HDMI DPIO driver vbios notes doc */ |
1642 | |
1643 | /* PLL B needs special handling */ |
1644 | if (pipe == PIPE_B) |
1645 | vlv_pllb_recal_opamp(dev_priv, pipe); |
1646 | |
1647 | /* Set up Tx target for periodic Rcomp update */ |
1648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST0xc044, 0x0100000f); |
1649 | |
1650 | /* Disable target IRef on PLL */ |
1651 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)((0x8040) + (pipe) * ((0x8060) - (0x8040)))); |
1652 | reg_val &= 0x00ffffff; |
1653 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe)((0x8040) + (pipe) * ((0x8060) - (0x8040))), reg_val); |
1654 | |
1655 | /* Disable fast lock */ |
1656 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW00x8100, 0x610); |
1657 | |
1658 | /* Set idtafcrecal before PLL is enabled */ |
1659 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT(8)) | (bestm2 & DPIO_M2DIV_MASK0xff)); |
1660 | mdiv |= ((bestp1 << DPIO_P1_SHIFT(21)) | (bestp2 << DPIO_P2_SHIFT(16))); |
1661 | mdiv |= ((bestn << DPIO_N_SHIFT(12))); |
1662 | mdiv |= (1 << DPIO_K_SHIFT(24)); |
1663 | |
1664 | /* |
1665 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
1666 | * but we don't support that). |
1667 | * Note: don't use the DAC post divider as it seems unstable. |
1668 | */ |
1669 | mdiv |= (DPIO_POST_DIV_HDMIDP1 << DPIO_POST_DIV_SHIFT(28)); |
1670 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe)((0x800c) + (pipe) * ((0x802c) - (0x800c))), mdiv); |
1671 | |
1672 | mdiv |= DPIO_ENABLE_CALIBRATION(1 << 11); |
1673 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe)((0x800c) + (pipe) * ((0x802c) - (0x800c))), mdiv); |
1674 | |
1675 | /* Set HBR and RBR LPF coefficients */ |
1676 | if (crtc_state->port_clock == 162000 || |
1677 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || |
1678 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
1679 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe)((0x8048) + (pipe) * ((0x8068) - (0x8048))), |
1680 | 0x009f0003); |
1681 | else |
1682 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe)((0x8048) + (pipe) * ((0x8068) - (0x8048))), |
1683 | 0x00d0000f); |
1684 | |
1685 | if (intel_crtc_has_dp_encoder(crtc_state)) { |
1686 | /* Use SSC source */ |
1687 | if (pipe == PIPE_A) |
1688 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
1689 | 0x0df40000); |
1690 | else |
1691 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
1692 | 0x0df70000); |
1693 | } else { /* HDMI or VGA */ |
1694 | /* Use bend source */ |
1695 | if (pipe == PIPE_A) |
1696 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
1697 | 0x0df70000); |
1698 | else |
1699 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
1700 | 0x0df40000); |
1701 | } |
1702 | |
1703 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)((0x801c) + (pipe) * ((0x803c) - (0x801c)))); |
1704 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
1705 | if (intel_crtc_has_dp_encoder(crtc_state)) |
1706 | coreclk |= 0x01000000; |
1707 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe)((0x801c) + (pipe) * ((0x803c) - (0x801c))), coreclk); |
1708 | |
1709 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe)((0x804c) + (pipe) * ((0x806c) - (0x804c))), 0x87871000); |
1710 | |
1711 | vlv_dpio_put(dev_priv); |
1712 | } |
1713 | |
1714 | static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) |
1715 | { |
1716 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1717 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1718 | enum pipe pipe = crtc->pipe; |
1719 | |
1720 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), crtc_state->dpll_hw_state.dpll); |
1721 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
1722 | udelay(150); |
1723 | |
1724 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_LOCK_VLV(1 << 15), 1)) |
1725 | drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DPLL %d failed to lock\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe); |
1726 | } |
1727 | |
1728 | void vlv_enable_pll(const struct intel_crtc_state *crtc_state) |
1729 | { |
1730 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1731 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1732 | enum pipe pipe = crtc->pipe; |
1733 | |
1734 | assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder)assert_transcoder(dev_priv, crtc_state->cpu_transcoder, 0); |
1735 | |
1736 | /* PLL is protected by panel, make sure we can write it */ |
1737 | assert_pps_unlocked(dev_priv, pipe); |
1738 | |
1739 | /* Enable Refclk */ |
1740 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), |
1741 | crtc_state->dpll_hw_state.dpll & |
1742 | ~(DPLL_VCO_ENABLE(1 << 31) | DPLL_EXT_BUFFER_ENABLE_VLV(1 << 30))); |
1743 | |
1744 | if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) { |
1745 | vlv_prepare_pll(crtc_state); |
1746 | _vlv_enable_pll(crtc_state); |
1747 | } |
1748 | |
1749 | intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(pipe)])) }), |
1750 | crtc_state->dpll_hw_state.dpll_md); |
1751 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(pipe)])) })); |
1752 | } |
1753 | |
1754 | static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) |
1755 | { |
1756 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1757 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1758 | enum pipe pipe = crtc->pipe; |
1759 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
1760 | u32 loopfilter, tribuf_calcntr; |
1761 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
1762 | u32 dpio_val; |
1763 | int vco; |
1764 | |
1765 | bestn = crtc_state->dpll.n; |
Value stored to 'bestn' is never read | |
1766 | bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; |
1767 | bestm1 = crtc_state->dpll.m1; |
1768 | bestm2 = crtc_state->dpll.m2 >> 22; |
1769 | bestp1 = crtc_state->dpll.p1; |
1770 | bestp2 = crtc_state->dpll.p2; |
1771 | vco = crtc_state->dpll.vco; |
1772 | dpio_val = 0; |
1773 | loopfilter = 0; |
1774 | |
1775 | vlv_dpio_get(dev_priv); |
1776 | |
1777 | /* p1 and p2 divider */ |
1778 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port)((0x8134) + (port) * ((0x8080) - (0x8134))), |
1779 | 5 << DPIO_CHV_S1_DIV_SHIFT21 | |
1780 | bestp1 << DPIO_CHV_P1_DIV_SHIFT13 | |
1781 | bestp2 << DPIO_CHV_P2_DIV_SHIFT8 | |
1782 | 1 << DPIO_CHV_K_DIV_SHIFT4); |
1783 | |
1784 | /* Feedback post-divider - m2 */ |
1785 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port)((0x8000) + (port) * ((0x8180) - (0x8000))), bestm2); |
1786 | |
1787 | /* Feedback refclk divider - n and m1 */ |
1788 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port)((0x8004) + (port) * ((0x8184) - (0x8004))), |
1789 | DPIO_CHV_M1_DIV_BY_2(0 << 0) | |
1790 | 1 << DPIO_CHV_N_DIV_SHIFT8); |
1791 | |
1792 | /* M2 fraction division */ |
1793 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port)((0x8008) + (port) * ((0x8188) - (0x8008))), bestm2_frac); |
1794 | |
1795 | /* M2 fraction division enable */ |
1796 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)((0x800c) + (port) * ((0x818c) - (0x800c)))); |
1797 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0) | DPIO_CHV_FRAC_DIV_EN(1 << 16)); |
1798 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT0); |
1799 | if (bestm2_frac) |
1800 | dpio_val |= DPIO_CHV_FRAC_DIV_EN(1 << 16); |
1801 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port)((0x800c) + (port) * ((0x818c) - (0x800c))), dpio_val); |
1802 | |
1803 | /* Program digital lock detect threshold */ |
1804 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)((0x8024) + (port) * ((0x81A4) - (0x8024)))); |
1805 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK(7 << 1) | |
1806 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1); |
1807 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT1); |
1808 | if (!bestm2_frac) |
1809 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1; |
1810 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port)((0x8024) + (port) * ((0x81A4) - (0x8024))), dpio_val); |
1811 | |
1812 | /* Loop filter */ |
1813 | if (vco == 5400000) { |
1814 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT0); |
1815 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT8); |
1816 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
1817 | tribuf_calcntr = 0x9; |
1818 | } else if (vco <= 6200000) { |
1819 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT0); |
1820 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT8); |
1821 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
1822 | tribuf_calcntr = 0x9; |
1823 | } else if (vco <= 6480000) { |
1824 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT0); |
1825 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT8); |
1826 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
1827 | tribuf_calcntr = 0x8; |
1828 | } else { |
1829 | /* Not supported. Apply the same limits as in the max case */ |
1830 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT0); |
1831 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT8); |
1832 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
1833 | tribuf_calcntr = 0; |
1834 | } |
1835 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port)((0x8018) + (port) * ((0x8198) - (0x8018))), loopfilter); |
1836 | |
1837 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)((0x8020) + (port) * ((0x81A0) - (0x8020)))); |
1838 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK(0x3FF << 0); |
1839 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT0); |
1840 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port)((0x8020) + (port) * ((0x81A0) - (0x8020))), dpio_val); |
1841 | |
1842 | /* AFC Recal */ |
1843 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), |
1844 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))) | |
1845 | DPIO_AFC_RECAL(1 << 14)); |
1846 | |
1847 | vlv_dpio_put(dev_priv); |
1848 | } |
1849 | |
1850 | static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) |
1851 | { |
1852 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1853 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1854 | enum pipe pipe = crtc->pipe; |
1855 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
1856 | u32 tmp; |
1857 | |
1858 | vlv_dpio_get(dev_priv); |
1859 | |
1860 | /* Enable back the 10bit clock to display controller */ |
1861 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))); |
1862 | tmp |= DPIO_DCLKP_EN(1 << 13); |
1863 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), tmp); |
1864 | |
1865 | vlv_dpio_put(dev_priv); |
1866 | |
1867 | /* |
1868 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
1869 | */ |
1870 | udelay(1); |
1871 | |
1872 | /* Enable PLL */ |
1873 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), crtc_state->dpll_hw_state.dpll); |
1874 | |
1875 | /* Check PLL is locked */ |
1876 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_LOCK_VLV(1 << 15), 1)) |
1877 | drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d failed to lock\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe); |
1878 | } |
1879 | |
1880 | void chv_enable_pll(const struct intel_crtc_state *crtc_state) |
1881 | { |
1882 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1883 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
1884 | enum pipe pipe = crtc->pipe; |
1885 | |
1886 | assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder)assert_transcoder(dev_priv, crtc_state->cpu_transcoder, 0); |
1887 | |
1888 | /* PLL is protected by panel, make sure we can write it */ |
1889 | assert_pps_unlocked(dev_priv, pipe); |
1890 | |
1891 | /* Enable Refclk and SSC */ |
1892 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), |
1893 | crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE(1 << 31)); |
1894 | |
1895 | if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) { |
1896 | chv_prepare_pll(crtc_state); |
1897 | _chv_enable_pll(crtc_state); |
1898 | } |
1899 | |
1900 | if (pipe != PIPE_A) { |
1901 | /* |
1902 | * WaPixelRepeatModeFixForC0:chv |
1903 | * |
1904 | * DPLLCMD is AWOL. Use chicken bits to propagate |
1905 | * the value from DPLLBMD to either pipe B or C. |
1906 | */ |
1907 | intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), CBR_DPLLBMD_PIPE(pipe)(1 << (7 + (pipe) * 11))); |
1908 | intel_de_write(dev_priv, DPLL_MD(PIPE_B)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(PIPE_B)] )) }), |
1909 | crtc_state->dpll_hw_state.dpll_md); |
1910 | intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), 0); |
1911 | dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; |
1912 | |
1913 | /* |
1914 | * DPLLB VGA mode also seems to cause problems. |
1915 | * We should always have it disabled. |
1916 | */ |
1917 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display.mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display.mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
1918 | (intel_de_read(dev_priv, DPLL(PIPE_B)) &({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display.mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display.mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
1919 | DPLL_VGA_MODE_DIS) == 0)({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display.mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display.mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display.mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }); |
1920 | } else { |
1921 | intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(pipe)])) }), |
1922 | crtc_state->dpll_hw_state.dpll_md); |
1923 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display.mmio_offset) + 0x603c) })[(pipe)])) })); |
1924 | } |
1925 | } |
1926 | |
1927 | /** |
1928 | * vlv_force_pll_on - forcibly enable just the PLL |
1929 | * @dev_priv: i915 private structure |
1930 | * @pipe: pipe PLL to enable |
1931 | * @dpll: PLL configuration |
1932 | * |
1933 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
1934 | * in cases where we need the PLL enabled even when @pipe is not going to |
1935 | * be enabled. |
1936 | */ |
1937 | int vlv_force_pll_on(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe, |
1938 | const struct dpll *dpll) |
1939 | { |
1940 | struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); |
1941 | struct intel_crtc_state *crtc_state; |
1942 | |
1943 | crtc_state = intel_crtc_state_alloc(crtc); |
1944 | if (!crtc_state) |
1945 | return -ENOMEM12; |
1946 | |
1947 | crtc_state->cpu_transcoder = (enum transcoder)pipe; |
1948 | crtc_state->pixel_multiplier = 1; |
1949 | crtc_state->dpll = *dpll; |
1950 | crtc_state->output_types = BIT(INTEL_OUTPUT_EDP)(1UL << (INTEL_OUTPUT_EDP)); |
1951 | |
1952 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
1953 | chv_compute_dpll(crtc_state); |
1954 | chv_enable_pll(crtc_state); |
1955 | } else { |
1956 | vlv_compute_dpll(crtc_state); |
1957 | vlv_enable_pll(crtc_state); |
1958 | } |
1959 | |
1960 | kfree(crtc_state); |
1961 | |
1962 | return 0; |
1963 | } |
1964 | |
1965 | void vlv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
1966 | { |
1967 | u32 val; |
1968 | |
1969 | /* Make sure the pipe isn't still relying on us */ |
1970 | assert_transcoder_disabled(dev_priv, (enum transcoder)pipe)assert_transcoder(dev_priv, (enum transcoder)pipe, 0); |
1971 | |
1972 | val = DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) | |
1973 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
1974 | if (pipe != PIPE_A) |
1975 | val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
1976 | |
1977 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), val); |
1978 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
1979 | } |
1980 | |
1981 | void chv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
1982 | { |
1983 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
1984 | u32 val; |
1985 | |
1986 | /* Make sure the pipe isn't still relying on us */ |
1987 | assert_transcoder_disabled(dev_priv, (enum transcoder)pipe)assert_transcoder(dev_priv, (enum transcoder)pipe, 0); |
1988 | |
1989 | val = DPLL_SSC_REF_CLK_CHV(1 << 13) | |
1990 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
1991 | if (pipe != PIPE_A) |
1992 | val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
1993 | |
1994 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), val); |
1995 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
1996 | |
1997 | vlv_dpio_get(dev_priv); |
1998 | |
1999 | /* Disable 10bit clock to display controller */ |
2000 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))); |
2001 | val &= ~DPIO_DCLKP_EN(1 << 13); |
2002 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), val); |
2003 | |
2004 | vlv_dpio_put(dev_priv); |
2005 | } |
2006 | |
2007 | void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) |
2008 | { |
2009 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
2010 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
2011 | enum pipe pipe = crtc->pipe; |
2012 | |
2013 | /* Don't disable pipe or pipe PLLs if needed */ |
2014 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
2015 | return; |
2016 | |
2017 | /* Make sure the pipe isn't still relying on us */ |
2018 | assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder)assert_transcoder(dev_priv, crtc_state->cpu_transcoder, 0); |
2019 | |
2020 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_VGA_MODE_DIS(1 << 28)); |
2021 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })); |
2022 | } |
2023 | |
2024 | |
2025 | /** |
2026 | * vlv_force_pll_off - forcibly disable just the PLL |
2027 | * @dev_priv: i915 private structure |
2028 | * @pipe: pipe PLL to disable |
2029 | * |
2030 | * Disable the PLL for @pipe. To be used in cases where we need |
2031 | * the PLL enabled even when @pipe is not going to be enabled. |
2032 | */ |
2033 | void vlv_force_pll_off(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
2034 | { |
2035 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
2036 | chv_disable_pll(dev_priv, pipe); |
2037 | else |
2038 | vlv_disable_pll(dev_priv, pipe); |
2039 | } |
2040 | |
2041 | /* Only for pre-ILK configs */ |
2042 | static void assert_pll(struct drm_i915_privateinteldrm_softc *dev_priv, |
2043 | enum pipe pipe, bool_Bool state) |
2044 | { |
2045 | bool_Bool cur_state; |
2046 | |
2047 | cur_state = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })) & DPLL_VCO_ENABLE(1 << 31); |
2048 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }) |
2049 | "PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }) |
2050 | str_on_off(state), str_on_off(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , str_on_off(state), str_on_off(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }); |
2051 | } |
2052 | |
2053 | void assert_pll_enabled(struct drm_i915_privateinteldrm_softc *i915, enum pipe pipe) |
2054 | { |
2055 | assert_pll(i915, pipe, true1); |
2056 | } |
2057 | |
2058 | void assert_pll_disabled(struct drm_i915_privateinteldrm_softc *i915, enum pipe pipe) |
2059 | { |
2060 | assert_pll(i915, pipe, false0); |
2061 | } |