Bug Summary

File:dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
Warning:line 320, column 2
Value stored to 'eng_id' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dc_link_enc_cfg.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
1/* Copyright 2021 Advanced Micro Devices, Inc. All rights reserved.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#include "link_enc_cfg.h"
26#include "resource.h"
27#include "dc_link_dp.h"
28
29#define DC_LOGGERdc->ctx->logger dc->ctx->logger
30
31/* Check whether stream is supported by DIG link encoders. */
32static bool_Bool is_dig_link_enc_stream(struct dc_stream_state *stream)
33{
34 bool_Bool is_dig_stream = false0;
35 struct link_encoder *link_enc = NULL((void *)0);
36 int i;
37
38 /* Loop over created link encoder objects. */
39 if (stream) {
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i];
42
43 /* Need to check link signal type rather than stream signal type which may not
44 * yet match.
45 */
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) {
47 if (dc_is_dp_signal(stream->signal)) {
48 /* DIGs do not support DP2.0 streams with 128b/132b encoding. */
49 struct dc_link_settings link_settings = {0};
50
51 decide_link_settings(stream, &link_settings);
52 if ((link_settings.link_rate >= LINK_RATE_LOW) &&
53 link_settings.link_rate <= LINK_RATE_HIGH3) {
54 is_dig_stream = true1;
55 break;
56 }
57 } else {
58 is_dig_stream = true1;
59 break;
60 }
61 }
62 }
63 }
64 return is_dig_stream;
65}
66
67static struct link_enc_assignment get_assignment(struct dc *dc, int i)
68{
69 struct link_enc_assignment assignment;
70
71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT)
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i];
73 else /* LINK_ENC_CFG_STEADY */
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
75
76 return assignment;
77}
78
79/* Return stream using DIG link encoder resource. NULL if unused. */
80static struct dc_stream_state *get_stream_using_link_enc(
81 struct dc_state *state,
82 enum engine_id eng_id)
83{
84 struct dc_stream_state *stream = NULL((void *)0);
85 int i;
86
87 for (i = 0; i < state->stream_count; i++) {
88 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
89
90 if ((assignment.valid == true1) && (assignment.eng_id == eng_id)) {
91 stream = state->streams[i];
92 break;
93 }
94 }
95
96 return stream;
97}
98
99static void remove_link_enc_assignment(
100 struct dc_state *state,
101 struct dc_stream_state *stream,
102 enum engine_id eng_id)
103{
104 int eng_idx;
105 int i;
106
107 if (eng_id != ENGINE_ID_UNKNOWN) {
108 eng_idx = eng_id - ENGINE_ID_DIGA;
109
110 /* stream ptr of stream in dc_state used to update correct entry in
111 * link_enc_assignments table.
112 */
113 for (i = 0; i < MAX_PIPES6; i++) {
114 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
115
116 if (assignment.valid && assignment.stream == stream) {
117 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false0;
118 /* Only add link encoder back to availability pool if not being
119 * used by any other stream (i.e. removing SST stream or last MST stream).
120 */
121 if (get_stream_using_link_enc(state, eng_id) == NULL((void *)0))
122 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = eng_id;
123
124 stream->link_enc = NULL((void *)0);
125 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id = ENGINE_ID_UNKNOWN;
126 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream = NULL((void *)0);
127 dc_stream_release(stream);
128 break;
129 }
130 }
131 }
132}
133
134static void add_link_enc_assignment(
135 struct dc_state *state,
136 struct dc_stream_state *stream,
137 enum engine_id eng_id)
138{
139 int eng_idx;
140 int i;
141
142 if (eng_id != ENGINE_ID_UNKNOWN) {
143 eng_idx = eng_id - ENGINE_ID_DIGA;
144
145 /* stream ptr of stream in dc_state used to update correct entry in
146 * link_enc_assignments table.
147 */
148 for (i = 0; i < state->stream_count; i++) {
149 if (stream == state->streams[i]) {
150 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i] = (struct link_enc_assignment){
151 .valid = true1,
152 .ep_id = (struct display_endpoint_id) {
153 .link_id = stream->link->link_id,
154 .ep_type = stream->link->ep_type},
155 .eng_id = eng_id,
156 .stream = stream};
157 dc_stream_retain(stream);
158 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = ENGINE_ID_UNKNOWN;
159 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx];
160 break;
161 }
162 }
163
164 /* Attempted to add an encoder assignment for a stream not in dc_state. */
165 ASSERT(i != state->stream_count)do { if (({ static int __warned; int __ret = !!(!(i != state->
stream_count)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(i != state->stream_count)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 165); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
166 }
167}
168
169/* Return first available DIG link encoder. */
170static enum engine_id find_first_avail_link_enc(
171 const struct dc_context *ctx,
172 const struct dc_state *state)
173{
174 enum engine_id eng_id = ENGINE_ID_UNKNOWN;
175 int i;
176
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
178 eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i];
179 if (eng_id != ENGINE_ID_UNKNOWN)
180 break;
181 }
182
183 return eng_id;
184}
185
186/* Check for availability of link encoder eng_id. */
187static bool_Bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id, struct dc_stream_state *stream)
188{
189 bool_Bool is_avail = false0;
190 int eng_idx = eng_id - ENGINE_ID_DIGA;
191
192 /* An encoder is available if it is still in the availability pool. */
193 if (eng_id != ENGINE_ID_UNKNOWN && state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] != ENGINE_ID_UNKNOWN) {
194 is_avail = true1;
195 } else {
196 struct dc_stream_state *stream_assigned = NULL((void *)0);
197
198 /* MST streams share the same link and should share the same encoder.
199 * If a stream that has already been assigned a link encoder uses as the
200 * same link as the stream checking for availability, it is an MST stream
201 * and should use the same link encoder.
202 */
203 stream_assigned = get_stream_using_link_enc(state, eng_id);
204 if (stream_assigned && stream != stream_assigned && stream->link == stream_assigned->link)
205 is_avail = true1;
206 }
207
208 return is_avail;
209}
210
211/* Test for display_endpoint_id equality. */
212static bool_Bool are_ep_ids_equal(struct display_endpoint_id *lhs, struct display_endpoint_id *rhs)
213{
214 bool_Bool are_equal = false0;
215
216 if (lhs->link_id.id == rhs->link_id.id &&
217 lhs->link_id.enum_id == rhs->link_id.enum_id &&
218 lhs->link_id.type == rhs->link_id.type &&
219 lhs->ep_type == rhs->ep_type)
220 are_equal = true1;
221
222 return are_equal;
223}
224
225static struct link_encoder *get_link_enc_used_by_link(
226 struct dc_state *state,
227 const struct dc_link *link)
228{
229 struct link_encoder *link_enc = NULL((void *)0);
230 struct display_endpoint_id ep_id;
231 int i;
232
233 ep_id = (struct display_endpoint_id) {
234 .link_id = link->link_id,
235 .ep_type = link->ep_type};
236
237 for (i = 0; i < MAX_PIPES6; i++) {
238 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
239
240 if (assignment.valid == true1 && are_ep_ids_equal(&assignment.ep_id, &ep_id))
241 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];
242 }
243
244 return link_enc;
245}
246/* Clear all link encoder assignments. */
247static void clear_enc_assignments(const struct dc *dc, struct dc_state *state)
248{
249 int i;
250
251 for (i = 0; i < MAX_PIPES6; i++) {
252 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false0;
253 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id = ENGINE_ID_UNKNOWN;
254 if (state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream != NULL((void *)0)) {
255 dc_stream_release(state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream);
256 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream = NULL((void *)0);
257 }
258 }
259
260 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {
261 if (dc->res_pool->link_encoders[i])
262 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i] = (enum engine_id) i;
263 else
264 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i] = ENGINE_ID_UNKNOWN;
265 }
266}
267
268void link_enc_cfg_init(
269 const struct dc *dc,
270 struct dc_state *state)
271{
272 clear_enc_assignments(dc, state);
273
274 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
275}
276
277void link_enc_cfg_copy(const struct dc_state *src_ctx, struct dc_state *dst_ctx)
278{
279 memcpy(&dst_ctx->res_ctx.link_enc_cfg_ctx,__builtin_memcpy((&dst_ctx->res_ctx.link_enc_cfg_ctx),
(&src_ctx->res_ctx.link_enc_cfg_ctx), (sizeof(dst_ctx
->res_ctx.link_enc_cfg_ctx)))
280 &src_ctx->res_ctx.link_enc_cfg_ctx,__builtin_memcpy((&dst_ctx->res_ctx.link_enc_cfg_ctx),
(&src_ctx->res_ctx.link_enc_cfg_ctx), (sizeof(dst_ctx
->res_ctx.link_enc_cfg_ctx)))
281 sizeof(dst_ctx->res_ctx.link_enc_cfg_ctx))__builtin_memcpy((&dst_ctx->res_ctx.link_enc_cfg_ctx),
(&src_ctx->res_ctx.link_enc_cfg_ctx), (sizeof(dst_ctx
->res_ctx.link_enc_cfg_ctx)));
282}
283
284void link_enc_cfg_link_encs_assign(
285 struct dc *dc,
286 struct dc_state *state,
287 struct dc_stream_state *streams[],
288 uint8_t stream_count)
289{
290 enum engine_id eng_id = ENGINE_ID_UNKNOWN;
291 int i;
292 int j;
293
294 ASSERT(state->stream_count == stream_count)do { if (({ static int __warned; int __ret = !!(!(state->stream_count
== stream_count)); if (__ret && !__warned) { printf(
"WARNING %s failed at %s:%d\n", "!(state->stream_count == stream_count)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 294); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
295 ASSERT(dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY)do { if (({ static int __warned; int __ret = !!(!(dc->current_state
->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY)); if
(__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 295); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
296
297 /* Release DIG link encoder resources before running assignment algorithm. */
298 for (i = 0; i < dc->current_state->stream_count; i++)
299 dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]);
300
301 for (i = 0; i < MAX_PIPES6; i++)
302 ASSERT(state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid == false)do { if (({ static int __warned; int __ret = !!(!(state->res_ctx
.link_enc_cfg_ctx.link_enc_assignments[i].valid == 0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid == 0)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 302); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
303
304 /* (a) Assign DIG link encoders to physical (unmappable) endpoints first. */
305 for (i = 0; i < stream_count; i++) {
306 struct dc_stream_state *stream = streams[i];
307
308 /* Skip stream if not supported by DIG link encoder. */
309 if (!is_dig_link_enc_stream(stream))
310 continue;
311
312 /* Physical endpoints have a fixed mapping to DIG link encoders. */
313 if (!stream->link->is_dig_mapping_flexible) {
314 eng_id = stream->link->eng_id;
315 add_link_enc_assignment(state, stream, eng_id);
316 }
317 }
318
319 /* (b) Retain previous assignments for mappable endpoints if encoders still available. */
320 eng_id = ENGINE_ID_UNKNOWN;
Value stored to 'eng_id' is never read
321
322 if (state != dc->current_state) {
323 struct dc_state *prev_state = dc->current_state;
324
325 for (i = 0; i < stream_count; i++) {
326 struct dc_stream_state *stream = state->streams[i];
327
328 /* Skip stream if not supported by DIG link encoder. */
329 if (!is_dig_link_enc_stream(stream))
330 continue;
331
332 if (!stream->link->is_dig_mapping_flexible)
333 continue;
334
335 for (j = 0; j < prev_state->stream_count; j++) {
336 struct dc_stream_state *prev_stream = prev_state->streams[j];
337
338 if (stream == prev_stream && stream->link == prev_stream->link &&
339 prev_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[j].valid) {
340 eng_id = prev_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[j].eng_id;
341 if (is_avail_link_enc(state, eng_id, stream))
342 add_link_enc_assignment(state, stream, eng_id);
343 }
344 }
345 }
346 }
347
348 /* (c) Then assign encoders to remaining mappable endpoints. */
349 eng_id = ENGINE_ID_UNKNOWN;
350
351 for (i = 0; i < stream_count; i++) {
352 struct dc_stream_state *stream = streams[i];
353
354 /* Skip stream if not supported by DIG link encoder. */
355 if (!is_dig_link_enc_stream(stream)) {
356 ASSERT(stream->link->is_dig_mapping_flexible != true)do { if (({ static int __warned; int __ret = !!(!(stream->
link->is_dig_mapping_flexible != 1)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(stream->link->is_dig_mapping_flexible != 1)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 356); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
357 continue;
358 }
359
360 /* Mappable endpoints have a flexible mapping to DIG link encoders. */
361 if (stream->link->is_dig_mapping_flexible) {
362 struct link_encoder *link_enc = NULL((void *)0);
363
364 /* Skip if encoder assignment retained in step (b) above. */
365 if (stream->link_enc)
366 continue;
367
368 /* For MST, multiple streams will share the same link / display
369 * endpoint. These streams should use the same link encoder
370 * assigned to that endpoint.
371 */
372 link_enc = get_link_enc_used_by_link(state, stream->link);
373 if (link_enc == NULL((void *)0))
374 eng_id = find_first_avail_link_enc(stream->ctx, state);
375 else
376 eng_id = link_enc->preferred_engine;
377 add_link_enc_assignment(state, stream, eng_id);
378 }
379 }
380
381 link_enc_cfg_validate(dc, state);
382
383 /* Update transient assignments. */
384 for (i = 0; i < MAX_PIPES6; i++) {
385 dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i] =
386 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
387 }
388
389 /* Log encoder assignments. */
390 for (i = 0; i < MAX_PIPES6; i++) {
391 struct link_enc_assignment assignment =
392 dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
393
394 if (assignment.valid)
395 DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: CUR %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
396 __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: CUR %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
397 assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: CUR %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
398 assignment.ep_id.link_id.enum_id - 1,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: CUR %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
399 assignment.eng_id)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: CUR %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id);
400 }
401 for (i = 0; i < MAX_PIPES6; i++) {
402 struct link_enc_assignment assignment =
403 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
404
405 if (assignment.valid)
406 DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: NEW %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
407 __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: NEW %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
408 assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: NEW %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
409 assignment.ep_id.link_id.enum_id - 1,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: NEW %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id)
410 assignment.eng_id)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: NEW %s(%d) - enc_id(%d)\n"
, __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
"PHY" : "DPIA", assignment.ep_id.link_id.enum_id - 1, assignment
.eng_id);
411 }
412
413 /* Current state mode will be set to steady once this state committed. */
414 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
415}
416
417void link_enc_cfg_link_enc_unassign(
418 struct dc_state *state,
419 struct dc_stream_state *stream)
420{
421 enum engine_id eng_id = ENGINE_ID_UNKNOWN;
422
423 /* Only DIG link encoders. */
424 if (!is_dig_link_enc_stream(stream))
425 return;
426
427 if (stream->link_enc)
428 eng_id = stream->link_enc->preferred_engine;
429
430 remove_link_enc_assignment(state, stream, eng_id);
431}
432
433bool_Bool link_enc_cfg_is_transmitter_mappable(
434 struct dc *dc,
435 struct link_encoder *link_enc)
436{
437 bool_Bool is_mappable = false0;
438 enum engine_id eng_id = link_enc->preferred_engine;
439 struct dc_stream_state *stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);
440
441 if (stream)
442 is_mappable = stream->link->is_dig_mapping_flexible;
443
444 return is_mappable;
445}
446
447struct dc_stream_state *link_enc_cfg_get_stream_using_link_enc(
448 struct dc *dc,
449 enum engine_id eng_id)
450{
451 struct dc_stream_state *stream = NULL((void *)0);
452 int i;
453
454 for (i = 0; i < MAX_PIPES6; i++) {
455 struct link_enc_assignment assignment = get_assignment(dc, i);
456
457 if ((assignment.valid == true1) && (assignment.eng_id == eng_id)) {
458 stream = assignment.stream;
459 break;
460 }
461 }
462
463 return stream;
464}
465
466struct dc_link *link_enc_cfg_get_link_using_link_enc(
467 struct dc *dc,
468 enum engine_id eng_id)
469{
470 struct dc_link *link = NULL((void *)0);
471 struct dc_stream_state *stream = NULL((void *)0);
472
473 stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);
474
475 if (stream)
476 link = stream->link;
477
478 // dm_output_to_console("%s: No link using DIG(%d).\n", __func__, eng_id);
479 return link;
480}
481
482struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
483 struct dc *dc,
484 const struct dc_link *link)
485{
486 struct link_encoder *link_enc = NULL((void *)0);
487 struct display_endpoint_id ep_id;
488 int i;
489
490 ep_id = (struct display_endpoint_id) {
491 .link_id = link->link_id,
492 .ep_type = link->ep_type};
493
494 for (i = 0; i < MAX_PIPES6; i++) {
495 struct link_enc_assignment assignment = get_assignment(dc, i);
496
497 if (assignment.valid == true1 && are_ep_ids_equal(&assignment.ep_id, &ep_id)) {
498 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];
499 break;
500 }
501 }
502
503 return link_enc;
504}
505
506struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc)
507{
508 struct link_encoder *link_enc = NULL((void *)0);
509 enum engine_id encs_assigned[MAX_DIG_LINK_ENCODERS7];
510 int i;
511
512 for (i = 0; i < MAX_DIG_LINK_ENCODERS7; i++)
513 encs_assigned[i] = ENGINE_ID_UNKNOWN;
514
515 /* Add assigned encoders to list. */
516 for (i = 0; i < MAX_PIPES6; i++) {
517 struct link_enc_assignment assignment = get_assignment(dc, i);
518
519 if (assignment.valid)
520 encs_assigned[assignment.eng_id - ENGINE_ID_DIGA] = assignment.eng_id;
521 }
522
523 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {
524 if (encs_assigned[i] == ENGINE_ID_UNKNOWN &&
525 dc->res_pool->link_encoders[i] != NULL((void *)0)) {
526 link_enc = dc->res_pool->link_encoders[i];
527 break;
528 }
529 }
530
531 return link_enc;
532}
533
534struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(
535 struct dc *dc,
536 const struct dc_stream_state *stream)
537{
538 struct link_encoder *link_enc;
539
540 link_enc = link_enc_cfg_get_link_enc_used_by_link(dc, stream->link);
541
542 return link_enc;
543}
544
545struct link_encoder *link_enc_cfg_get_link_enc(
546 const struct dc_link *link)
547{
548 struct link_encoder *link_enc = NULL((void *)0);
549
550 /* Links supporting dynamically assigned link encoder will be assigned next
551 * available encoder if one not already assigned.
552 */
553 if (link->is_dig_mapping_flexible &&
554 link->dc->res_pool->funcs->link_encs_assign) {
555 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
556 if (link_enc == NULL((void *)0))
557 link_enc = link_enc_cfg_get_next_avail_link_enc(
558 link->ctx->dc);
559 } else
560 link_enc = link->link_enc;
561
562 return link_enc;
563}
564
565struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream_current(
566 struct dc *dc,
567 const struct dc_stream_state *stream)
568{
569 struct link_encoder *link_enc = NULL((void *)0);
570 struct display_endpoint_id ep_id;
571 int i;
572
573 ep_id = (struct display_endpoint_id) {
574 .link_id = stream->link->link_id,
575 .ep_type = stream->link->ep_type};
576
577 for (i = 0; i < MAX_PIPES6; i++) {
578 struct link_enc_assignment assignment =
579 dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
580
581 if (assignment.valid == true1 && are_ep_ids_equal(&assignment.ep_id, &ep_id)) {
582 link_enc = stream->link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];
583 break;
584 }
585 }
586
587 return link_enc;
588}
589
590bool_Bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link)
591{
592 bool_Bool is_avail = true1;
593 int i;
594
595 /* An encoder is not available if it has already been assigned to a different endpoint. */
596 for (i = 0; i < MAX_PIPES6; i++) {
597 struct link_enc_assignment assignment = get_assignment(dc, i);
598 struct display_endpoint_id ep_id = (struct display_endpoint_id) {
599 .link_id = link->link_id,
600 .ep_type = link->ep_type};
601
602 if (assignment.valid && assignment.eng_id == eng_id && !are_ep_ids_equal(&ep_id, &assignment.ep_id)) {
603 is_avail = false0;
604 break;
605 }
606 }
607
608 return is_avail;
609}
610
611bool_Bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)
612{
613 bool_Bool is_valid = false0;
614 bool_Bool valid_entries = true1;
615 bool_Bool valid_stream_ptrs = true1;
616 bool_Bool valid_uniqueness = true1;
617 bool_Bool valid_avail = true1;
618 bool_Bool valid_streams = true1;
619 int i, j;
620 uint8_t valid_count = 0;
621 uint8_t dig_stream_count = 0;
622 int matching_stream_ptrs = 0;
623 int eng_ids_per_ep_id[MAX_PIPES6] = {0};
624 int ep_ids_per_eng_id[MAX_PIPES6] = {0};
625 int valid_bitmap = 0;
626
627 /* (1) No. valid entries same as stream count. */
628 for (i = 0; i < MAX_PIPES6; i++) {
629 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
630
631 if (assignment.valid)
632 valid_count++;
633
634 if (is_dig_link_enc_stream(state->streams[i]))
635 dig_stream_count++;
636 }
637 if (valid_count != dig_stream_count)
638 valid_entries = false0;
639
640 /* (2) Matching stream ptrs. */
641 for (i = 0; i < MAX_PIPES6; i++) {
642 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
643
644 if (assignment.valid) {
645 if (assignment.stream == state->streams[i])
646 matching_stream_ptrs++;
647 else
648 valid_stream_ptrs = false0;
649 }
650 }
651
652 /* (3) Each endpoint assigned unique encoder. */
653 for (i = 0; i < MAX_PIPES6; i++) {
654 struct link_enc_assignment assignment_i = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
655
656 if (assignment_i.valid) {
657 struct display_endpoint_id ep_id_i = assignment_i.ep_id;
658
659 eng_ids_per_ep_id[i]++;
660 ep_ids_per_eng_id[i]++;
661 for (j = 0; j < MAX_PIPES6; j++) {
662 struct link_enc_assignment assignment_j =
663 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[j];
664
665 if (j == i)
666 continue;
667
668 if (assignment_j.valid) {
669 struct display_endpoint_id ep_id_j = assignment_j.ep_id;
670
671 if (are_ep_ids_equal(&ep_id_i, &ep_id_j) &&
672 assignment_i.eng_id != assignment_j.eng_id) {
673 valid_uniqueness = false0;
674 eng_ids_per_ep_id[i]++;
675 } else if (!are_ep_ids_equal(&ep_id_i, &ep_id_j) &&
676 assignment_i.eng_id == assignment_j.eng_id) {
677 valid_uniqueness = false0;
678 ep_ids_per_eng_id[i]++;
679 }
680 }
681 }
682 }
683 }
684
685 /* (4) Assigned encoders not in available pool. */
686 for (i = 0; i < MAX_PIPES6; i++) {
687 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
688
689 if (assignment.valid) {
690 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) {
691 if (state->res_ctx.link_enc_cfg_ctx.link_enc_avail[j] == assignment.eng_id) {
692 valid_avail = false0;
693 break;
694 }
695 }
696 }
697 }
698
699 /* (5) All streams have valid link encoders. */
700 for (i = 0; i < state->stream_count; i++) {
701 struct dc_stream_state *stream = state->streams[i];
702
703 if (is_dig_link_enc_stream(stream) && stream->link_enc == NULL((void *)0)) {
704 valid_streams = false0;
705 break;
706 }
707 }
708
709 is_valid = valid_entries && valid_stream_ptrs && valid_uniqueness && valid_avail && valid_streams;
710 ASSERT(is_valid)do { if (({ static int __warned; int __ret = !!(!(is_valid));
if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(is_valid)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c"
, 710); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
711
712 if (is_valid == false0) {
713 valid_bitmap =
714 (valid_entries & 0x1) |
715 ((valid_stream_ptrs & 0x1) << 1) |
716 ((valid_uniqueness & 0x1) << 2) |
717 ((valid_avail & 0x1) << 3) |
718 ((valid_streams & 0x1) << 4);
719 DC_LOG_ERROR("%s: Invalid link encoder assignments - 0x%x\n", __func__, valid_bitmap)__drm_err("%s: Invalid link encoder assignments - 0x%x\n", __func__
, valid_bitmap);
720 }
721
722 return is_valid;
723}
724
725void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)
726{
727 int i = 0;
728 int num_transient_assignments = 0;
729
730 for (i = 0; i < MAX_PIPES6; i++) {
731 if (current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i].valid)
732 num_transient_assignments++;
733 }
734
735 /* Only enter transient mode if the new encoder assignments are valid. */
736 if (new_state->stream_count == num_transient_assignments) {
737 current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
738 DC_LOG_DEBUG("%s: current_state(%p) mode(%d)\n", __func__, current_state, LINK_ENC_CFG_TRANSIENT)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: current_state(%p) mode(%d)\n"
, __func__, current_state, LINK_ENC_CFG_TRANSIENT);
739 }
740}