File: | dev/pci/drm/amd/amdgpu/gfx_v9_0.c |
Warning: | line 2076, column 22 Value stored to 'ring' during its initialization is never read |
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1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/delay.h> |
25 | #include <linux/kernel.h> |
26 | #include <linux/firmware.h> |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> |
29 | |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_gfx.h" |
32 | #include "soc15.h" |
33 | #include "soc15d.h" |
34 | #include "amdgpu_atomfirmware.h" |
35 | #include "amdgpu_pm.h" |
36 | |
37 | #include "gc/gc_9_0_offset.h" |
38 | #include "gc/gc_9_0_sh_mask.h" |
39 | |
40 | #include "vega10_enum.h" |
41 | |
42 | #include "soc15_common.h" |
43 | #include "clearstate_gfx9.h" |
44 | #include "v9_structs.h" |
45 | |
46 | #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" |
47 | |
48 | #include "amdgpu_ras.h" |
49 | |
50 | #include "gfx_v9_4.h" |
51 | #include "gfx_v9_0.h" |
52 | #include "gfx_v9_4_2.h" |
53 | |
54 | #include "asic_reg/pwr/pwr_10_0_offset.h" |
55 | #include "asic_reg/pwr/pwr_10_0_sh_mask.h" |
56 | #include "asic_reg/gc/gc_9_0_default.h" |
57 | |
58 | #define GFX9_NUM_GFX_RINGS1 1 |
59 | #define GFX9_MEC_HPD_SIZE4096 4096 |
60 | #define RLCG_UCODE_LOADING_START_ADDRESS0x00002000L 0x00002000L |
61 | #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET0x00000000L 0x00000000L |
62 | |
63 | #define mmGCEA_PROBE_MAP0x070c 0x070c |
64 | #define mmGCEA_PROBE_MAP_BASE_IDX0 0 |
65 | |
66 | MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); |
67 | MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); |
68 | MODULE_FIRMWARE("amdgpu/vega10_me.bin"); |
69 | MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); |
70 | MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); |
71 | MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); |
72 | |
73 | MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); |
74 | MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); |
75 | MODULE_FIRMWARE("amdgpu/vega12_me.bin"); |
76 | MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); |
77 | MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); |
78 | MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); |
79 | |
80 | MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); |
81 | MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); |
82 | MODULE_FIRMWARE("amdgpu/vega20_me.bin"); |
83 | MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); |
84 | MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); |
85 | MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); |
86 | |
87 | MODULE_FIRMWARE("amdgpu/raven_ce.bin"); |
88 | MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); |
89 | MODULE_FIRMWARE("amdgpu/raven_me.bin"); |
90 | MODULE_FIRMWARE("amdgpu/raven_mec.bin"); |
91 | MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); |
92 | MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); |
93 | |
94 | MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); |
95 | MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); |
96 | MODULE_FIRMWARE("amdgpu/picasso_me.bin"); |
97 | MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); |
98 | MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); |
99 | MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); |
100 | MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); |
101 | |
102 | MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); |
103 | MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); |
104 | MODULE_FIRMWARE("amdgpu/raven2_me.bin"); |
105 | MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); |
106 | MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); |
107 | MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); |
108 | MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); |
109 | |
110 | MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); |
111 | MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); |
112 | |
113 | MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); |
114 | MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); |
115 | MODULE_FIRMWARE("amdgpu/renoir_me.bin"); |
116 | MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); |
117 | MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); |
118 | |
119 | MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); |
120 | MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); |
121 | MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); |
122 | MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); |
123 | MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); |
124 | MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); |
125 | |
126 | MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); |
127 | MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); |
128 | MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); |
129 | MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); |
130 | MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); |
131 | |
132 | #define mmTCP_CHAN_STEER_0_ARCT0x0b03 0x0b03 |
133 | #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX0 0 |
134 | #define mmTCP_CHAN_STEER_1_ARCT0x0b04 0x0b04 |
135 | #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX0 0 |
136 | #define mmTCP_CHAN_STEER_2_ARCT0x0b09 0x0b09 |
137 | #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX0 0 |
138 | #define mmTCP_CHAN_STEER_3_ARCT0x0b0a 0x0b0a |
139 | #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX0 0 |
140 | #define mmTCP_CHAN_STEER_4_ARCT0x0b0b 0x0b0b |
141 | #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX0 0 |
142 | #define mmTCP_CHAN_STEER_5_ARCT0x0b0c 0x0b0c |
143 | #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX0 0 |
144 | |
145 | #define mmGOLDEN_TSC_COUNT_UPPER_Renoir0x0025 0x0025 |
146 | #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX1 1 |
147 | #define mmGOLDEN_TSC_COUNT_LOWER_Renoir0x0026 0x0026 |
148 | #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX1 1 |
149 | |
150 | enum ta_ras_gfx_subblock { |
151 | /*CPC*/ |
152 | TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, |
153 | TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, |
154 | TA_RAS_BLOCK__GFX_CPC_UCODE, |
155 | TA_RAS_BLOCK__GFX_DC_STATE_ME1, |
156 | TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, |
157 | TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, |
158 | TA_RAS_BLOCK__GFX_DC_STATE_ME2, |
159 | TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, |
160 | TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, |
161 | TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, |
162 | /* CPF*/ |
163 | TA_RAS_BLOCK__GFX_CPF_INDEX_START, |
164 | TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, |
165 | TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, |
166 | TA_RAS_BLOCK__GFX_CPF_TAG, |
167 | TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, |
168 | /* CPG*/ |
169 | TA_RAS_BLOCK__GFX_CPG_INDEX_START, |
170 | TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, |
171 | TA_RAS_BLOCK__GFX_CPG_DMA_TAG, |
172 | TA_RAS_BLOCK__GFX_CPG_TAG, |
173 | TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, |
174 | /* GDS*/ |
175 | TA_RAS_BLOCK__GFX_GDS_INDEX_START, |
176 | TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, |
177 | TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, |
178 | TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, |
179 | TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, |
180 | TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, |
181 | TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, |
182 | /* SPI*/ |
183 | TA_RAS_BLOCK__GFX_SPI_SR_MEM, |
184 | /* SQ*/ |
185 | TA_RAS_BLOCK__GFX_SQ_INDEX_START, |
186 | TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, |
187 | TA_RAS_BLOCK__GFX_SQ_LDS_D, |
188 | TA_RAS_BLOCK__GFX_SQ_LDS_I, |
189 | TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ |
190 | TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, |
191 | /* SQC (3 ranges)*/ |
192 | TA_RAS_BLOCK__GFX_SQC_INDEX_START, |
193 | /* SQC range 0*/ |
194 | TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, |
195 | TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = |
196 | TA_RAS_BLOCK__GFX_SQC_INDEX0_START, |
197 | TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, |
198 | TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, |
199 | TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, |
200 | TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, |
201 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, |
202 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, |
203 | TA_RAS_BLOCK__GFX_SQC_INDEX0_END = |
204 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, |
205 | /* SQC range 1*/ |
206 | TA_RAS_BLOCK__GFX_SQC_INDEX1_START, |
207 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = |
208 | TA_RAS_BLOCK__GFX_SQC_INDEX1_START, |
209 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, |
210 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, |
211 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, |
212 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, |
213 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, |
214 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, |
215 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, |
216 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, |
217 | TA_RAS_BLOCK__GFX_SQC_INDEX1_END = |
218 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, |
219 | /* SQC range 2*/ |
220 | TA_RAS_BLOCK__GFX_SQC_INDEX2_START, |
221 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = |
222 | TA_RAS_BLOCK__GFX_SQC_INDEX2_START, |
223 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, |
224 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, |
225 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, |
226 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, |
227 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, |
228 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, |
229 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, |
230 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, |
231 | TA_RAS_BLOCK__GFX_SQC_INDEX2_END = |
232 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, |
233 | TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, |
234 | /* TA*/ |
235 | TA_RAS_BLOCK__GFX_TA_INDEX_START, |
236 | TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, |
237 | TA_RAS_BLOCK__GFX_TA_FS_AFIFO, |
238 | TA_RAS_BLOCK__GFX_TA_FL_LFIFO, |
239 | TA_RAS_BLOCK__GFX_TA_FX_LFIFO, |
240 | TA_RAS_BLOCK__GFX_TA_FS_CFIFO, |
241 | TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, |
242 | /* TCA*/ |
243 | TA_RAS_BLOCK__GFX_TCA_INDEX_START, |
244 | TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, |
245 | TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, |
246 | TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, |
247 | /* TCC (5 sub-ranges)*/ |
248 | TA_RAS_BLOCK__GFX_TCC_INDEX_START, |
249 | /* TCC range 0*/ |
250 | TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, |
251 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, |
252 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, |
253 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, |
254 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, |
255 | TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, |
256 | TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, |
257 | TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, |
258 | TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, |
259 | TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, |
260 | /* TCC range 1*/ |
261 | TA_RAS_BLOCK__GFX_TCC_INDEX1_START, |
262 | TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, |
263 | TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, |
264 | TA_RAS_BLOCK__GFX_TCC_INDEX1_END = |
265 | TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, |
266 | /* TCC range 2*/ |
267 | TA_RAS_BLOCK__GFX_TCC_INDEX2_START, |
268 | TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, |
269 | TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, |
270 | TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, |
271 | TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, |
272 | TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, |
273 | TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, |
274 | TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, |
275 | TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, |
276 | TA_RAS_BLOCK__GFX_TCC_INDEX2_END = |
277 | TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, |
278 | /* TCC range 3*/ |
279 | TA_RAS_BLOCK__GFX_TCC_INDEX3_START, |
280 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, |
281 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, |
282 | TA_RAS_BLOCK__GFX_TCC_INDEX3_END = |
283 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, |
284 | /* TCC range 4*/ |
285 | TA_RAS_BLOCK__GFX_TCC_INDEX4_START, |
286 | TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = |
287 | TA_RAS_BLOCK__GFX_TCC_INDEX4_START, |
288 | TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, |
289 | TA_RAS_BLOCK__GFX_TCC_INDEX4_END = |
290 | TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, |
291 | TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, |
292 | /* TCI*/ |
293 | TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, |
294 | /* TCP*/ |
295 | TA_RAS_BLOCK__GFX_TCP_INDEX_START, |
296 | TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, |
297 | TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, |
298 | TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, |
299 | TA_RAS_BLOCK__GFX_TCP_VM_FIFO, |
300 | TA_RAS_BLOCK__GFX_TCP_DB_RAM, |
301 | TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, |
302 | TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, |
303 | TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, |
304 | /* TD*/ |
305 | TA_RAS_BLOCK__GFX_TD_INDEX_START, |
306 | TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, |
307 | TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, |
308 | TA_RAS_BLOCK__GFX_TD_CS_FIFO, |
309 | TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, |
310 | /* EA (3 sub-ranges)*/ |
311 | TA_RAS_BLOCK__GFX_EA_INDEX_START, |
312 | /* EA range 0*/ |
313 | TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, |
314 | TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, |
315 | TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, |
316 | TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, |
317 | TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, |
318 | TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, |
319 | TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, |
320 | TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, |
321 | TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, |
322 | TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, |
323 | /* EA range 1*/ |
324 | TA_RAS_BLOCK__GFX_EA_INDEX1_START, |
325 | TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, |
326 | TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, |
327 | TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, |
328 | TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, |
329 | TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, |
330 | TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, |
331 | TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, |
332 | TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, |
333 | /* EA range 2*/ |
334 | TA_RAS_BLOCK__GFX_EA_INDEX2_START, |
335 | TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, |
336 | TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, |
337 | TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, |
338 | TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, |
339 | TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, |
340 | TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, |
341 | /* UTC VM L2 bank*/ |
342 | TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, |
343 | /* UTC VM walker*/ |
344 | TA_RAS_BLOCK__UTC_VML2_WALKER, |
345 | /* UTC ATC L2 2MB cache*/ |
346 | TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, |
347 | /* UTC ATC L2 4KB cache*/ |
348 | TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, |
349 | TA_RAS_BLOCK__GFX_MAX |
350 | }; |
351 | |
352 | struct ras_gfx_subblock { |
353 | unsigned char *name; |
354 | int ta_subblock; |
355 | int hw_supported_error_type; |
356 | int sw_supported_error_type; |
357 | }; |
358 | |
359 | #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)[AMDGPU_RAS_BLOCK__subblock] = { "subblock", TA_RAS_BLOCK__subblock , ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3 )), (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), } \ |
360 | [AMDGPU_RAS_BLOCK__##subblock] = { \ |
361 | #subblock, \ |
362 | TA_RAS_BLOCK__##subblock, \ |
363 | ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ |
364 | (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ |
365 | } |
366 | |
367 | static const struct ras_gfx_subblock ras_gfx_subblocks[] = { |
368 | AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH] = { "GFX_CPC_SCRATCH", TA_RAS_BLOCK__GFX_CPC_SCRATCH , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
369 | AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPC_UCODE] = { "GFX_CPC_UCODE", TA_RAS_BLOCK__GFX_CPC_UCODE , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
370 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1] = { "GFX_DC_STATE_ME1", TA_RAS_BLOCK__GFX_DC_STATE_ME1 , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (1) | ((0) << 2)), }, |
371 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1] = { "GFX_DC_CSINVOC_ME1" , TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
372 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1] = { "GFX_DC_RESTORE_ME1" , TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
373 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2] = { "GFX_DC_STATE_ME2", TA_RAS_BLOCK__GFX_DC_STATE_ME2 , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
374 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2] = { "GFX_DC_CSINVOC_ME2" , TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
375 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2] = { "GFX_DC_RESTORE_ME2" , TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
376 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2] = { "GFX_CPF_ROQ_ME2", TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
377 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1] = { "GFX_CPF_ROQ_ME1", TA_RAS_BLOCK__GFX_CPF_ROQ_ME1 , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (1) | ((0) << 2)), }, |
378 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPF_TAG] = { "GFX_CPF_TAG", TA_RAS_BLOCK__GFX_CPF_TAG , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
379 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ] = { "GFX_CPG_DMA_ROQ", TA_RAS_BLOCK__GFX_CPG_DMA_ROQ , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (1) | ((0) << 2)), }, |
380 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG] = { "GFX_CPG_DMA_TAG", TA_RAS_BLOCK__GFX_CPG_DMA_TAG , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((1) << 3) | (0) | ((1) << 2)), }, |
381 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1)[AMDGPU_RAS_BLOCK__GFX_CPG_TAG] = { "GFX_CPG_TAG", TA_RAS_BLOCK__GFX_CPG_TAG , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((1) << 3) | (0) | ((1) << 2)), }, |
382 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_MEM] = { "GFX_GDS_MEM", TA_RAS_BLOCK__GFX_GDS_MEM , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
383 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE] = { "GFX_GDS_INPUT_QUEUE" , TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
384 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM] = { "GFX_GDS_OA_PHY_CMD_RAM_MEM" , TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
385 | 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM] = { "GFX_GDS_OA_PHY_CMD_RAM_MEM" , TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
386 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM] = { "GFX_GDS_OA_PHY_DATA_RAM_MEM" , TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
387 | 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM] = { "GFX_GDS_OA_PHY_DATA_RAM_MEM" , TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
388 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM] = { "GFX_GDS_OA_PIPE_MEM" , TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
389 | AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM] = { "GFX_SPI_SR_MEM", TA_RAS_BLOCK__GFX_SPI_SR_MEM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
390 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_SGPR] = { "GFX_SQ_SGPR", TA_RAS_BLOCK__GFX_SQ_SGPR , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
391 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D] = { "GFX_SQ_LDS_D", TA_RAS_BLOCK__GFX_SQ_LDS_D , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
392 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I] = { "GFX_SQ_LDS_I", TA_RAS_BLOCK__GFX_SQ_LDS_I , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
393 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQ_VGPR] = { "GFX_SQ_VGPR", TA_RAS_BLOCK__GFX_SQ_VGPR , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
394 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO] = { "GFX_SQC_INST_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
395 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU0_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
396 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU0_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
397 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU0_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
398 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU0_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
399 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU1_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
400 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU1_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
401 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU1_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
402 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU1_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
403 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU2_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
404 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF] = { "GFX_SQC_DATA_CU2_WRITE_DATA_BUF" , TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
405 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU2_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
406 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO] = { "GFX_SQC_DATA_CU2_UTCL1_LFIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
407 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM] = { "GFX_SQC_INST_BANKA_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), } |
408 | 1)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM] = { "GFX_SQC_INST_BANKA_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
409 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ((1) | (( 0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
410 | 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, ((1) | (( 0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
411 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO] = { "GFX_SQC_INST_BANKA_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
412 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO] = { "GFX_SQC_INST_BANKA_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
413 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM] = { "GFX_SQC_INST_BANKA_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
414 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM] = { "GFX_SQC_INST_BANKA_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
415 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM] = { "GFX_SQC_DATA_BANKA_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
416 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM] = { "GFX_SQC_DATA_BANKA_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
417 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO] = { "GFX_SQC_DATA_BANKA_HIT_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
418 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO] = { "GFX_SQC_DATA_BANKA_HIT_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
419 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO] = { "GFX_SQC_DATA_BANKA_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
420 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO] = { "GFX_SQC_DATA_BANKA_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
421 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
422 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
423 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM] = { "GFX_SQC_DATA_BANKA_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
424 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM] = { "GFX_SQC_DATA_BANKA_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
425 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM] = { "GFX_SQC_INST_BANKB_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
426 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM] = { "GFX_SQC_INST_BANKB_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
427 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ((1) | (( 0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
428 | 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO] = { "GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, ((1) | (( 0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
429 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO] = { "GFX_SQC_INST_BANKB_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
430 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO] = { "GFX_SQC_INST_BANKB_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
431 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM] = { "GFX_SQC_INST_BANKB_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
432 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM] = { "GFX_SQC_INST_BANKB_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
433 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM] = { "GFX_SQC_DATA_BANKB_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
434 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM] = { "GFX_SQC_DATA_BANKB_TAG_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
435 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO] = { "GFX_SQC_DATA_BANKB_HIT_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
436 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO] = { "GFX_SQC_DATA_BANKB_HIT_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
437 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO] = { "GFX_SQC_DATA_BANKB_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
438 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO] = { "GFX_SQC_DATA_BANKB_MISS_FIFO" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
439 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
440 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM] = { "GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
441 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM] = { "GFX_SQC_DATA_BANKB_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
442 | 0)[AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM] = { "GFX_SQC_DATA_BANKB_BANK_RAM" , TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
443 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO] = { "GFX_TA_FS_DFIFO", TA_RAS_BLOCK__GFX_TA_FS_DFIFO , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
444 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO] = { "GFX_TA_FS_AFIFO", TA_RAS_BLOCK__GFX_TA_FS_AFIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
445 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO] = { "GFX_TA_FL_LFIFO", TA_RAS_BLOCK__GFX_TA_FL_LFIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
446 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO] = { "GFX_TA_FX_LFIFO", TA_RAS_BLOCK__GFX_TA_FX_LFIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
447 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO] = { "GFX_TA_FS_CFIFO", TA_RAS_BLOCK__GFX_TA_FS_CFIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
448 | AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO] = { "GFX_TCA_HOLE_FIFO" , TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO, ((1) | ((0) << 1) | ( (0) << 2) | ((1) << 3)), (((0) << 1) | ((1) << 3) | (1) | ((0) << 2)), }, |
449 | AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO] = { "GFX_TCA_REQ_FIFO", TA_RAS_BLOCK__GFX_TCA_REQ_FIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
450 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA] = { "GFX_TCC_CACHE_DATA" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | (( 0) << 3) | (0) | ((1) << 2)), }, |
451 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1] = { "GFX_TCC_CACHE_DATA_BANK_0_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), } |
452 | 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1] = { "GFX_TCC_CACHE_DATA_BANK_0_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
453 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0] = { "GFX_TCC_CACHE_DATA_BANK_1_0" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), } |
454 | 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0] = { "GFX_TCC_CACHE_DATA_BANK_1_0" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
455 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1] = { "GFX_TCC_CACHE_DATA_BANK_1_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), } |
456 | 1)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1] = { "GFX_TCC_CACHE_DATA_BANK_1_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
457 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0] = { "GFX_TCC_CACHE_DIRTY_BANK_0" , TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
458 | 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0] = { "GFX_TCC_CACHE_DIRTY_BANK_0" , TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
459 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1] = { "GFX_TCC_CACHE_DIRTY_BANK_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
460 | 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1] = { "GFX_TCC_CACHE_DIRTY_BANK_1" , TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
461 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG] = { "GFX_TCC_HIGH_RATE_TAG" , TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, ((0) | ((1) << 1 ) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
462 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG] = { "GFX_TCC_LOW_RATE_TAG" , TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
463 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC] = { "GFX_TCC_IN_USE_DEC" , TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
464 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER] = { "GFX_TCC_IN_USE_TRANSFER" , TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
465 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA] = { "GFX_TCC_RETURN_DATA" , TA_RAS_BLOCK__GFX_TCC_RETURN_DATA, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
466 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL] = { "GFX_TCC_RETURN_CONTROL" , TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, ((1) | ((0) << 1 ) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
467 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO] = { "GFX_TCC_UC_ATOMIC_FIFO" , TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, ((1) | ((0) << 1 ) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
468 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN] = { "GFX_TCC_WRITE_RETURN" , TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ( (1) << 3) | (1) | ((0) << 2)), }, |
469 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ] = { "GFX_TCC_WRITE_CACHE_READ" , TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
470 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO] = { "GFX_TCC_SRC_FIFO", TA_RAS_BLOCK__GFX_TCC_SRC_FIFO , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
471 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM] = { "GFX_TCC_SRC_FIFO_NEXT_RAM" , TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (1) | ((0) << 2)), }, |
472 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO] = { "GFX_TCC_CACHE_TAG_PROBE_FIFO" , TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
473 | 0)[AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO] = { "GFX_TCC_CACHE_TAG_PROBE_FIFO" , TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
474 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO] = { "GFX_TCC_LATENCY_FIFO" , TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
475 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM] = { "GFX_TCC_LATENCY_FIFO_NEXT_RAM" , TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
476 | 0)[AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM] = { "GFX_TCC_LATENCY_FIFO_NEXT_RAM" , TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
477 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN] = { "GFX_TCC_WRRET_TAG_WRITE_RETURN" , TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
478 | 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN] = { "GFX_TCC_WRRET_TAG_WRITE_RETURN" , TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
479 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,[AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER] = { "GFX_TCC_ATOMIC_RETURN_BUFFER" , TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), } |
480 | 0)[AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER] = { "GFX_TCC_ATOMIC_RETURN_BUFFER" , TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
481 | AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM] = { "GFX_TCI_WRITE_RAM" , TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, ((1) | ((0) << 1) | ( (0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
482 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM] = { "GFX_TCP_CACHE_RAM" , TA_RAS_BLOCK__GFX_TCP_CACHE_RAM, ((0) | ((1) << 1) | ( (1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
483 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM] = { "GFX_TCP_LFIFO_RAM" , TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, ((0) | ((1) << 1) | ( (1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
484 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO] = { "GFX_TCP_CMD_FIFO", TA_RAS_BLOCK__GFX_TCP_CMD_FIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
485 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO] = { "GFX_TCP_VM_FIFO", TA_RAS_BLOCK__GFX_TCP_VM_FIFO , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
486 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM] = { "GFX_TCP_DB_RAM", TA_RAS_BLOCK__GFX_TCP_DB_RAM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
487 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0] = { "GFX_TCP_UTCL1_LFIFO0" , TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
488 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1] = { "GFX_TCP_UTCL1_LFIFO1" , TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
489 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO] = { "GFX_TD_SS_FIFO_LO" , TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO, ((0) | ((1) << 1) | ( (1) << 2) | ((1) << 3)), (((1) << 1) | ((0) << 3) | (0) | ((1) << 2)), }, |
490 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI] = { "GFX_TD_SS_FIFO_HI" , TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, ((0) | ((1) << 1) | ( (1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
491 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO] = { "GFX_TD_CS_FIFO", TA_RAS_BLOCK__GFX_TD_CS_FIFO , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
492 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM] = { "GFX_EA_DRAMRD_CMDMEM" , TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((1) << 1) | ( (0) << 3) | (0) | ((1) << 2)), }, |
493 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM] = { "GFX_EA_DRAMWR_CMDMEM" , TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
494 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM] = { "GFX_EA_DRAMWR_DATAMEM" , TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, ((0) | ((1) << 1 ) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
495 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM] = { "GFX_EA_RRET_TAGMEM" , TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
496 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM] = { "GFX_EA_WRET_TAGMEM" , TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
497 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM] = { "GFX_EA_GMIRD_CMDMEM" , TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
498 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM] = { "GFX_EA_GMIWR_CMDMEM" , TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
499 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM] = { "GFX_EA_GMIWR_DATAMEM" , TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
500 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM] = { "GFX_EA_DRAMRD_PAGEMEM" , TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM, ((1) | ((0) << 1 ) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
501 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM] = { "GFX_EA_DRAMWR_PAGEMEM" , TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, ((1) | ((0) << 1 ) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
502 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM] = { "GFX_EA_IORD_CMDMEM" , TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
503 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM] = { "GFX_EA_IOWR_CMDMEM" , TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
504 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM] = { "GFX_EA_IOWR_DATAMEM" , TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
505 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM] = { "GFX_EA_GMIRD_PAGEMEM" , TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
506 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM] = { "GFX_EA_GMIWR_PAGEMEM" , TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ( (0) << 3) | (0) | ((0) << 2)), }, |
507 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM] = { "GFX_EA_MAM_D0MEM", TA_RAS_BLOCK__GFX_EA_MAM_D0MEM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
508 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM] = { "GFX_EA_MAM_D1MEM", TA_RAS_BLOCK__GFX_EA_MAM_D1MEM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
509 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM] = { "GFX_EA_MAM_D2MEM", TA_RAS_BLOCK__GFX_EA_MAM_D2MEM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
510 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM] = { "GFX_EA_MAM_D3MEM", TA_RAS_BLOCK__GFX_EA_MAM_D3MEM , ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
511 | AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE] = { "UTC_VML2_BANK_CACHE" , TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | (( 0) << 3) | (0) | ((0) << 2)), }, |
512 | AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_VML2_WALKER] = { "UTC_VML2_WALKER", TA_RAS_BLOCK__UTC_VML2_WALKER , ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3 )), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
513 | AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK] = { "UTC_ATCL2_CACHE_2M_BANK" , TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, ((1) | ((0) << 1) | ((0) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
514 | AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0)[AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK] = { "UTC_ATCL2_CACHE_4K_BANK" , TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, ((0) | ((1) << 1) | ((1) << 2) | ((1) << 3)), (((0) << 1) | ((0) << 3) | (0) | ((0) << 2)), }, |
515 | }; |
516 | |
517 | static const struct soc15_reg_golden golden_settings_gc_9_0[] = |
518 | { |
519 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000400 }, |
520 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000){ GC_HWIP, 0, 0, 0x060e, 0x80000000, 0x80000000 }, |
521 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 }, |
522 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 }, |
523 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 }, |
524 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 }, |
525 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000){ GC_HWIP, 0, 0, 0x030d, 0x00001000, 0x00001000 }, |
526 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dc, 0x0007ffff, 0x00000800 }, |
527 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dd, 0x0007ffff, 0x00000800 }, |
528 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87){ GC_HWIP, 0, 0, 0x11e6, 0x01ffffff, 0x00ffff87 }, |
529 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f){ GC_HWIP, 0, 0, 0x11e7, 0x01ffffff, 0x00ffff8f }, |
530 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000){ GC_HWIP, 0, 0, 0x0301, 0x03000000, 0x020a2000 }, |
531 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 }, |
532 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x4a2c0e68 }, |
533 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0xb5d3f197 }, |
534 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 }, |
535 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000003ff }, |
536 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 }, |
537 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 }, |
538 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 } |
539 | }; |
540 | |
541 | static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = |
542 | { |
543 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107){ GC_HWIP, 0, 0, 0x0680, 0x0000f000, 0x00012107 }, |
544 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 }, |
545 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x08000000, 0x08000080 }, |
546 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0x08000000, 0x08000080 }, |
547 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x08000000, 0x08000080 }, |
548 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x2a114042 }, |
549 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x2a114042 }, |
550 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x08000000, 0x08000080 }, |
551 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000){ GC_HWIP, 0, 0, 0x02fd, 0x00008000, 0x00048000 }, |
552 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0x08000000, 0x08000080 }, |
553 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0x08000000, 0x08000080 }, |
554 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0x08000000, 0x08000080 }, |
555 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0x08000000, 0x08000080 }, |
556 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0x08000000, 0x08000080 }, |
557 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00020000 }, |
558 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0x0000000f, 0x01000107 }, |
559 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800){ GC_HWIP, 0, 0, 0x0525, 0x00001800, 0x00000800 }, |
560 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x08000000, 0x08000080 } |
561 | }; |
562 | |
563 | static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = |
564 | { |
565 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080){ GC_HWIP, 0, 0, 0x0688, 0x0f000080, 0x04000080 }, |
566 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0x0f000000, 0x0a000000 }, |
567 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 }, |
568 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042){ GC_HWIP, 0, 0, 0x063e, 0xf3e777ff, 0x22014042 }, |
569 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042){ GC_HWIP, 0, 0, 0x0642, 0xf3e777ff, 0x22014042 }, |
570 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0x00003e00, 0x00000400 }, |
571 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xff840000, 0x04040000 }, |
572 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00030000 }, |
573 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0xffff010f, 0x01000107 }, |
574 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000){ GC_HWIP, 0, 0, 0x0542, 0x000b0000, 0x000b0000 }, |
575 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01000000, 0x01000000 } |
576 | }; |
577 | |
578 | static const struct soc15_reg_golden golden_settings_gc_9_1[] = |
579 | { |
580 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 }, |
581 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x08000000, 0x08000080 }, |
582 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0x08000000, 0x08000080 }, |
583 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x08000000, 0x08000080 }, |
584 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000420 }, |
585 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 }, |
586 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x08000000, 0x08000080 }, |
587 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 }, |
588 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 }, |
589 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 }, |
590 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0x08000000, 0x08000080 }, |
591 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0x08000000, 0x08000080 }, |
592 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0x08000000, 0x08000080 }, |
593 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0x08000000, 0x08000080 }, |
594 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0x08000000, 0x08000080 }, |
595 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 }, |
596 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 }, |
597 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00003120 }, |
598 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 }, |
599 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000000ff }, |
600 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x08000000, 0x08000080 }, |
601 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 }, |
602 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 }, |
603 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 } |
604 | }; |
605 | |
606 | static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = |
607 | { |
608 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000){ GC_HWIP, 0, 0, 0x0683, 0x30000000, 0x10000000 }, |
609 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x24000042 }, |
610 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x24000042 }, |
611 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04048000 }, |
612 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000){ GC_HWIP, 0, 1, 0x0293, 0x06000000, 0x06000000 }, |
613 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000){ GC_HWIP, 0, 0, 0x078c, 0x00030000, 0x00020000 }, |
614 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x00000800 } |
615 | }; |
616 | |
617 | static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = |
618 | { |
619 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000){ GC_HWIP, 0, 0, 0x0688, 0xff7fffff, 0x04000000 }, |
620 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 }, |
621 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0xff7fffff, 0x0a000000 }, |
622 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103d, 0x7f0fffff, 0x08000080 }, |
623 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103e, 0xff8fffff, 0x08000080 }, |
624 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x103c, 0x7f8fffff, 0x08000080 }, |
625 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x26013041 }, |
626 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x26013041 }, |
627 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x0246, 0x3f8fffff, 0x08000080 }, |
628 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 }, |
629 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb2, 0xff0fffff, 0x08000080 }, |
630 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb3, 0xff0fffff, 0x08000080 }, |
631 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb4, 0xff0fffff, 0x08000080 }, |
632 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4ccd, 0xff0fffff, 0x08000080 }, |
633 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080){ GC_HWIP, 0, 1, 0x4cb5, 0xff0fffff, 0x08000080 }, |
634 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 }, |
635 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00000010 }, |
636 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x01000000 }, |
637 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080){ GC_HWIP, 0, 0, 0x0243, 0x3f8fffff, 0x08000080 }, |
638 | }; |
639 | |
640 | static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = |
641 | { |
642 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 }, |
643 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0xff7fffff, 0x0a000000 }, |
644 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000400 }, |
645 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042){ GC_HWIP, 0, 0, 0x063e, 0xf3e777ff, 0x24000042 }, |
646 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042){ GC_HWIP, 0, 0, 0x0642, 0xf3e777ff, 0x24000042 }, |
647 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 }, |
648 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 }, |
649 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 }, |
650 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 }, |
651 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 }, |
652 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x00003120 }, |
653 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc){ GC_HWIP, 0, 0, 0x070c, 0xffffffff, 0x0000cccc }, |
654 | }; |
655 | |
656 | static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = |
657 | { |
658 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff){ GC_HWIP, 0, 0, 0x11b7, 0xffffffff, 0x000001ff }, |
659 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000){ GC_HWIP, 0, 1, 0x5a04, 0xffffffff, 0x00000000 }, |
660 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382){ GC_HWIP, 0, 1, 0x5a05, 0xffffffff, 0x2544c382 } |
661 | }; |
662 | |
663 | static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = |
664 | { |
665 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420){ GC_HWIP, 0, 0, 0x060d, 0xf00fffff, 0x00000420 }, |
666 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000){ GC_HWIP, 0, 0, 0x0640, 0x0000000f, 0x00000000 }, |
667 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024){ GC_HWIP, 0, 0, 0x02cf, 0x00000003, 0x82400024 }, |
668 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001){ GC_HWIP, 0, 0, 0x02fc, 0x3fffffff, 0x00000001 }, |
669 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 }, |
670 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000){ GC_HWIP, 0, 0, 0x030d, 0x00001000, 0x00001000 }, |
671 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dc, 0x0007ffff, 0x00000800 }, |
672 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800){ GC_HWIP, 0, 0, 0x11dd, 0x0007ffff, 0x00000800 }, |
673 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87){ GC_HWIP, 0, 0, 0x11e6, 0x01ffffff, 0x0000ff87 }, |
674 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f){ GC_HWIP, 0, 0, 0x11e7, 0x01ffffff, 0x0000ff8f }, |
675 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000){ GC_HWIP, 0, 0, 0x0301, 0x03000000, 0x020a2000 }, |
676 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x010b0000 }, |
677 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x4a2c0e68 }, |
678 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0xb5d3f197 }, |
679 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000){ GC_HWIP, 0, 0, 0x0231, 0x3fff3af3, 0x19200000 }, |
680 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x0269, 0x00000fff, 0x000003ff } |
681 | }; |
682 | |
683 | static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = |
684 | { |
685 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080){ GC_HWIP, 0, 0, 0x0688, 0x00000080, 0x04000080 }, |
686 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104){ GC_HWIP, 0, 0, 0x0680, 0xfffdf3cf, 0x00014104 }, |
687 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000){ GC_HWIP, 0, 0, 0x0682, 0x0f000000, 0x0a000000 }, |
688 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x24104041 }, |
689 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041){ GC_HWIP, 0, 0, 0x0642, 0xffff77ff, 0x24104041 }, |
690 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000){ GC_HWIP, 0, 0, 0x02fd, 0xffffffff, 0x04040000 }, |
691 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107){ GC_HWIP, 0, 1, 0x2441, 0xffff03ff, 0x01000107 }, |
692 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000){ GC_HWIP, 0, 0, 0x0b04, 0xffffffff, 0x00000000 }, |
693 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410){ GC_HWIP, 0, 0, 0x0b03, 0xffffffff, 0x76325410 }, |
694 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000){ GC_HWIP, 0, 0, 0x0525, 0x01bd9f33, 0x01000000 }, |
695 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10bd, 0x00000800, 0x00000800 }, |
696 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800){ GC_HWIP, 0, 0, 0x10be, 0x00000800, 0x00000800 }, |
697 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000){ GC_HWIP, 0, 0, 0x107f, 0x00008000, 0x00008000 } |
698 | }; |
699 | |
700 | static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = |
701 | { |
702 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042){ GC_HWIP, 0, 0, 0x063e, 0xffff77ff, 0x2a114042 }, |
703 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000){ GC_HWIP, 0, 0, 0x0542, 0xfffffeef, 0x10b0000 }, |
704 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e){ GC_HWIP, 0, 0, 0x0b03, 0x3fffffff, 0x346f0a4e }, |
705 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca){ GC_HWIP, 0, 0, 0x0b04, 0x3fffffff, 0x1c642ca }, |
706 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098){ GC_HWIP, 0, 0, 0x0b09, 0x3fffffff, 0x26f45098 }, |
707 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3){ GC_HWIP, 0, 0, 0x0b0a, 0x3fffffff, 0x2ebd9fe3 }, |
708 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1){ GC_HWIP, 0, 0, 0x0b0b, 0x3fffffff, 0xb90f5b1 }, |
709 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135){ GC_HWIP, 0, 0, 0x0b0c, 0x3ff, 0x135 }, |
710 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000){ GC_HWIP, 0, 0, 0x0300, 0xffffffff, 0x011A0000 }, |
711 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00){ GC_HWIP, 0, 0, 0x0305, 0xffffffff, 0x00000f00 }, |
712 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000){ GC_HWIP, 0, 0, 0x12b5, 0x30000000, 0x30000000 } |
713 | }; |
714 | |
715 | static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { |
716 | {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)GC_HWIP, 0, 1, 0x2200}, |
717 | {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)GC_HWIP, 0, 0, 0x0378}, |
718 | }; |
719 | |
720 | static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = |
721 | { |
722 | mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
723 | mmRLC_SRM_INDEX_CNTL_ADDR_10x4c8c - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
724 | mmRLC_SRM_INDEX_CNTL_ADDR_20x4c8d - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
725 | mmRLC_SRM_INDEX_CNTL_ADDR_30x4c8e - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
726 | mmRLC_SRM_INDEX_CNTL_ADDR_40x4c8f - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
727 | mmRLC_SRM_INDEX_CNTL_ADDR_50x4c90 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
728 | mmRLC_SRM_INDEX_CNTL_ADDR_60x4c91 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
729 | mmRLC_SRM_INDEX_CNTL_ADDR_70x4c92 - mmRLC_SRM_INDEX_CNTL_ADDR_00x4c8b, |
730 | }; |
731 | |
732 | static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = |
733 | { |
734 | mmRLC_SRM_INDEX_CNTL_DATA_00x4c93 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
735 | mmRLC_SRM_INDEX_CNTL_DATA_10x4c94 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
736 | mmRLC_SRM_INDEX_CNTL_DATA_20x4c95 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
737 | mmRLC_SRM_INDEX_CNTL_DATA_30x4c96 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
738 | mmRLC_SRM_INDEX_CNTL_DATA_40x4c97 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
739 | mmRLC_SRM_INDEX_CNTL_DATA_50x4c98 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
740 | mmRLC_SRM_INDEX_CNTL_DATA_60x4c99 - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
741 | mmRLC_SRM_INDEX_CNTL_DATA_70x4c9a - mmRLC_SRM_INDEX_CNTL_DATA_00x4c93, |
742 | }; |
743 | |
744 | #define VEGA10_GB_ADDR_CONFIG_GOLDEN0x2a114042 0x2a114042 |
745 | #define VEGA12_GB_ADDR_CONFIG_GOLDEN0x24104041 0x24104041 |
746 | #define RAVEN_GB_ADDR_CONFIG_GOLDEN0x24000042 0x24000042 |
747 | #define RAVEN2_GB_ADDR_CONFIG_GOLDEN0x26013041 0x26013041 |
748 | |
749 | static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); |
750 | static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); |
751 | static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); |
752 | static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); |
753 | static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, |
754 | struct amdgpu_cu_info *cu_info); |
755 | static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); |
756 | static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); |
757 | static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); |
758 | static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, |
759 | void *ras_error_status); |
760 | static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, |
761 | void *inject_if); |
762 | static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); |
763 | |
764 | static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, |
765 | uint64_t queue_mask) |
766 | { |
767 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)((3 << 30) | (((0xA0) & 0xFF) << 8) | ((6) & 0x3FFF) << 16)); |
768 | amdgpu_ring_write(kiq_ring, |
769 | PACKET3_SET_RESOURCES_VMID_MASK(0)((0) << 0) | |
770 | /* vmid_mask:0* queue_type:0 (KIQ) */ |
771 | PACKET3_SET_RESOURCES_QUEUE_TYPE(0)((0) << 29)); |
772 | amdgpu_ring_write(kiq_ring, |
773 | lower_32_bits(queue_mask)((u32)(queue_mask))); /* queue mask lo */ |
774 | amdgpu_ring_write(kiq_ring, |
775 | upper_32_bits(queue_mask)((u32)(((queue_mask) >> 16) >> 16))); /* queue mask hi */ |
776 | amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ |
777 | amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ |
778 | amdgpu_ring_write(kiq_ring, 0); /* oac mask */ |
779 | amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ |
780 | } |
781 | |
782 | static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, |
783 | struct amdgpu_ring *ring) |
784 | { |
785 | uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); |
786 | uint64_t wptr_addr = ring->wptr_gpu_addr; |
787 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
788 | |
789 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)((3 << 30) | (((0xA2) & 0xFF) << 8) | ((5) & 0x3FFF) << 16)); |
790 | /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ |
791 | amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
792 | PACKET3_MAP_QUEUES_QUEUE_SEL(0)((0) << 4) | /* Queue_Sel */ |
793 | PACKET3_MAP_QUEUES_VMID(0)((0) << 8) | /* VMID */ |
794 | PACKET3_MAP_QUEUES_QUEUE(ring->queue)((ring->queue) << 13) | |
795 | PACKET3_MAP_QUEUES_PIPE(ring->pipe)((ring->pipe) << 16) | |
796 | PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1))(((ring->me == 1 ? 0 : 1)) << 18) | |
797 | /*queue_type: normal compute queue */ |
798 | PACKET3_MAP_QUEUES_QUEUE_TYPE(0)((0) << 21) | |
799 | /* alloc format: all_on_one_pipe */ |
800 | PACKET3_MAP_QUEUES_ALLOC_FORMAT(0)((0) << 24) | |
801 | PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) | |
802 | /* num_queues: must be 1 */ |
803 | PACKET3_MAP_QUEUES_NUM_QUEUES(1)((1) << 29)); |
804 | amdgpu_ring_write(kiq_ring, |
805 | PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2)); |
806 | amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)((u32)(mqd_addr))); |
807 | amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)((u32)(((mqd_addr) >> 16) >> 16))); |
808 | amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)((u32)(wptr_addr))); |
809 | amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)((u32)(((wptr_addr) >> 16) >> 16))); |
810 | } |
811 | |
812 | static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, |
813 | struct amdgpu_ring *ring, |
814 | enum amdgpu_unmap_queues_action action, |
815 | u64 gpu_addr, u64 seq) |
816 | { |
817 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
818 | |
819 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)((3 << 30) | (((0xA3) & 0xFF) << 8) | ((4) & 0x3FFF) << 16)); |
820 | amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
821 | PACKET3_UNMAP_QUEUES_ACTION(action)((action) << 0) | |
822 | PACKET3_UNMAP_QUEUES_QUEUE_SEL(0)((0) << 4) | |
823 | PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) | |
824 | PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)((1) << 29)); |
825 | amdgpu_ring_write(kiq_ring, |
826 | PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)((ring->doorbell_index) << 2)); |
827 | |
828 | if (action == PREEMPT_QUEUES_NO_UNMAP) { |
829 | amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)((u32)(gpu_addr))); |
830 | amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16))); |
831 | amdgpu_ring_write(kiq_ring, seq); |
832 | } else { |
833 | amdgpu_ring_write(kiq_ring, 0); |
834 | amdgpu_ring_write(kiq_ring, 0); |
835 | amdgpu_ring_write(kiq_ring, 0); |
836 | } |
837 | } |
838 | |
839 | static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, |
840 | struct amdgpu_ring *ring, |
841 | u64 addr, |
842 | u64 seq) |
843 | { |
844 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
845 | |
846 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)((3 << 30) | (((0xA4) & 0xFF) << 8) | ((5) & 0x3FFF) << 16)); |
847 | amdgpu_ring_write(kiq_ring, |
848 | PACKET3_QUERY_STATUS_CONTEXT_ID(0)((0) << 0) | |
849 | PACKET3_QUERY_STATUS_INTERRUPT_SEL(0)((0) << 28) | |
850 | PACKET3_QUERY_STATUS_COMMAND(2)((2) << 30)); |
851 | /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
852 | amdgpu_ring_write(kiq_ring, |
853 | PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2) | |
854 | PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)((eng_sel) << 25)); |
855 | amdgpu_ring_write(kiq_ring, lower_32_bits(addr)((u32)(addr))); |
856 | amdgpu_ring_write(kiq_ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16))); |
857 | amdgpu_ring_write(kiq_ring, lower_32_bits(seq)((u32)(seq))); |
858 | amdgpu_ring_write(kiq_ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16))); |
859 | } |
860 | |
861 | static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, |
862 | uint16_t pasid, uint32_t flush_type, |
863 | bool_Bool all_hub) |
864 | { |
865 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)((3 << 30) | (((0x98) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
866 | amdgpu_ring_write(kiq_ring, |
867 | PACKET3_INVALIDATE_TLBS_DST_SEL(1)((1) << 0) | |
868 | PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub)((all_hub) << 4) | |
869 | PACKET3_INVALIDATE_TLBS_PASID(pasid)((pasid) << 5) | |
870 | PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)((flush_type) << 29)); |
871 | } |
872 | |
873 | static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { |
874 | .kiq_set_resources = gfx_v9_0_kiq_set_resources, |
875 | .kiq_map_queues = gfx_v9_0_kiq_map_queues, |
876 | .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, |
877 | .kiq_query_status = gfx_v9_0_kiq_query_status, |
878 | .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, |
879 | .set_resources_size = 8, |
880 | .map_queues_size = 7, |
881 | .unmap_queues_size = 6, |
882 | .query_status_size = 7, |
883 | .invalidate_tlbs_size = 2, |
884 | }; |
885 | |
886 | static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) |
887 | { |
888 | adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; |
889 | } |
890 | |
891 | static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) |
892 | { |
893 | switch (adev->ip_versions[GC_HWIP][0]) { |
894 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
895 | soc15_program_register_sequence(adev, |
896 | golden_settings_gc_9_0, |
897 | ARRAY_SIZE(golden_settings_gc_9_0)(sizeof((golden_settings_gc_9_0)) / sizeof((golden_settings_gc_9_0 )[0]))); |
898 | soc15_program_register_sequence(adev, |
899 | golden_settings_gc_9_0_vg10, |
900 | ARRAY_SIZE(golden_settings_gc_9_0_vg10)(sizeof((golden_settings_gc_9_0_vg10)) / sizeof((golden_settings_gc_9_0_vg10 )[0]))); |
901 | break; |
902 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
903 | soc15_program_register_sequence(adev, |
904 | golden_settings_gc_9_2_1, |
905 | ARRAY_SIZE(golden_settings_gc_9_2_1)(sizeof((golden_settings_gc_9_2_1)) / sizeof((golden_settings_gc_9_2_1 )[0]))); |
906 | soc15_program_register_sequence(adev, |
907 | golden_settings_gc_9_2_1_vg12, |
908 | ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)(sizeof((golden_settings_gc_9_2_1_vg12)) / sizeof((golden_settings_gc_9_2_1_vg12 )[0]))); |
909 | break; |
910 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
911 | soc15_program_register_sequence(adev, |
912 | golden_settings_gc_9_0, |
913 | ARRAY_SIZE(golden_settings_gc_9_0)(sizeof((golden_settings_gc_9_0)) / sizeof((golden_settings_gc_9_0 )[0]))); |
914 | soc15_program_register_sequence(adev, |
915 | golden_settings_gc_9_0_vg20, |
916 | ARRAY_SIZE(golden_settings_gc_9_0_vg20)(sizeof((golden_settings_gc_9_0_vg20)) / sizeof((golden_settings_gc_9_0_vg20 )[0]))); |
917 | break; |
918 | case IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)): |
919 | soc15_program_register_sequence(adev, |
920 | golden_settings_gc_9_4_1_arct, |
921 | ARRAY_SIZE(golden_settings_gc_9_4_1_arct)(sizeof((golden_settings_gc_9_4_1_arct)) / sizeof((golden_settings_gc_9_4_1_arct )[0]))); |
922 | break; |
923 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
924 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
925 | soc15_program_register_sequence(adev, golden_settings_gc_9_1, |
926 | ARRAY_SIZE(golden_settings_gc_9_1)(sizeof((golden_settings_gc_9_1)) / sizeof((golden_settings_gc_9_1 )[0]))); |
927 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
928 | soc15_program_register_sequence(adev, |
929 | golden_settings_gc_9_1_rv2, |
930 | ARRAY_SIZE(golden_settings_gc_9_1_rv2)(sizeof((golden_settings_gc_9_1_rv2)) / sizeof((golden_settings_gc_9_1_rv2 )[0]))); |
931 | else |
932 | soc15_program_register_sequence(adev, |
933 | golden_settings_gc_9_1_rv1, |
934 | ARRAY_SIZE(golden_settings_gc_9_1_rv1)(sizeof((golden_settings_gc_9_1_rv1)) / sizeof((golden_settings_gc_9_1_rv1 )[0]))); |
935 | break; |
936 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
937 | soc15_program_register_sequence(adev, |
938 | golden_settings_gc_9_1_rn, |
939 | ARRAY_SIZE(golden_settings_gc_9_1_rn)(sizeof((golden_settings_gc_9_1_rn)) / sizeof((golden_settings_gc_9_1_rn )[0]))); |
940 | return; /* for renoir, don't need common goldensetting */ |
941 | case IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)): |
942 | gfx_v9_4_2_init_golden_registers(adev, |
943 | adev->smuio.funcs->get_die_id(adev)); |
944 | break; |
945 | default: |
946 | break; |
947 | } |
948 | |
949 | if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1))) && |
950 | (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)))) |
951 | soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, |
952 | (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)(sizeof((golden_settings_gc_9_x_common)) / sizeof((golden_settings_gc_9_x_common )[0]))); |
953 | } |
954 | |
955 | static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, |
956 | bool_Bool wc, uint32_t reg, uint32_t val) |
957 | { |
958 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) & 0x3FFF) << 16)); |
959 | amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel)((eng_sel) << 30) | |
960 | WRITE_DATA_DST_SEL(0)((0) << 8) | |
961 | (wc ? WR_CONFIRM(1 << 20) : 0)); |
962 | amdgpu_ring_write(ring, reg); |
963 | amdgpu_ring_write(ring, 0); |
964 | amdgpu_ring_write(ring, val); |
965 | } |
966 | |
967 | static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, |
968 | int mem_space, int opt, uint32_t addr0, |
969 | uint32_t addr1, uint32_t ref, uint32_t mask, |
970 | uint32_t inv) |
971 | { |
972 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)((3 << 30) | (((0x3C) & 0xFF) << 8) | ((5) & 0x3FFF) << 16)); |
973 | amdgpu_ring_write(ring, |
974 | /* memory (1) or register (0) */ |
975 | (WAIT_REG_MEM_MEM_SPACE(mem_space)((mem_space) << 4) | |
976 | WAIT_REG_MEM_OPERATION(opt)((opt) << 6) | /* wait */ |
977 | WAIT_REG_MEM_FUNCTION(3)((3) << 0) | /* equal */ |
978 | WAIT_REG_MEM_ENGINE(eng_sel)((eng_sel) << 8))); |
979 | |
980 | if (mem_space) |
981 | BUG_ON(addr0 & 0x3)((!(addr0 & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c" , 981, "!(addr0 & 0x3)")); /* Dword align */ |
982 | amdgpu_ring_write(ring, addr0); |
983 | amdgpu_ring_write(ring, addr1); |
984 | amdgpu_ring_write(ring, ref); |
985 | amdgpu_ring_write(ring, mask); |
986 | amdgpu_ring_write(ring, inv); /* poll interval */ |
987 | } |
988 | |
989 | static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) |
990 | { |
991 | struct amdgpu_device *adev = ring->adev; |
992 | uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040); |
993 | uint32_t tmp = 0; |
994 | unsigned i; |
995 | int r; |
996 | |
997 | WREG32(scratch, 0xCAFEDEAD)amdgpu_device_wreg(adev, (scratch), (0xCAFEDEAD), 0); |
998 | r = amdgpu_ring_alloc(ring, 3); |
999 | if (r) |
1000 | return r; |
1001 | |
1002 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) & 0x3FFF) << 16)); |
1003 | amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START0x0000c000); |
1004 | amdgpu_ring_write(ring, 0xDEADBEEF); |
1005 | amdgpu_ring_commit(ring); |
1006 | |
1007 | for (i = 0; i < adev->usec_timeout; i++) { |
1008 | tmp = RREG32(scratch)amdgpu_device_rreg(adev, (scratch), 0); |
1009 | if (tmp == 0xDEADBEEF) |
1010 | break; |
1011 | udelay(1); |
1012 | } |
1013 | |
1014 | if (i >= adev->usec_timeout) |
1015 | r = -ETIMEDOUT60; |
1016 | return r; |
1017 | } |
1018 | |
1019 | static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
1020 | { |
1021 | struct amdgpu_device *adev = ring->adev; |
1022 | struct amdgpu_ib ib; |
1023 | struct dma_fence *f = NULL((void *)0); |
1024 | |
1025 | unsigned index; |
1026 | uint64_t gpu_addr; |
1027 | uint32_t tmp; |
1028 | long r; |
1029 | |
1030 | r = amdgpu_device_wb_get(adev, &index); |
1031 | if (r) |
1032 | return r; |
1033 | |
1034 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
1035 | adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD)); |
1036 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); |
1037 | |
1038 | r = amdgpu_ib_get(adev, NULL((void *)0), 20, AMDGPU_IB_POOL_DIRECT, &ib); |
1039 | if (r) |
1040 | goto err1; |
1041 | |
1042 | ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
1043 | ib.ptr[1] = WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20); |
1044 | ib.ptr[2] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
1045 | ib.ptr[3] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
1046 | ib.ptr[4] = 0xDEADBEEF; |
1047 | ib.length_dw = 5; |
1048 | |
1049 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); |
1050 | if (r) |
1051 | goto err2; |
1052 | |
1053 | r = dma_fence_wait_timeout(f, false0, timeout); |
1054 | if (r == 0) { |
1055 | r = -ETIMEDOUT60; |
1056 | goto err2; |
1057 | } else if (r < 0) { |
1058 | goto err2; |
1059 | } |
1060 | |
1061 | tmp = adev->wb.wb[index]; |
1062 | if (tmp == 0xDEADBEEF) |
1063 | r = 0; |
1064 | else |
1065 | r = -EINVAL22; |
1066 | |
1067 | err2: |
1068 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); |
1069 | dma_fence_put(f); |
1070 | err1: |
1071 | amdgpu_device_wb_free(adev, index); |
1072 | return r; |
1073 | } |
1074 | |
1075 | |
1076 | static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) |
1077 | { |
1078 | release_firmware(adev->gfx.pfp_fw); |
1079 | adev->gfx.pfp_fw = NULL((void *)0); |
1080 | release_firmware(adev->gfx.me_fw); |
1081 | adev->gfx.me_fw = NULL((void *)0); |
1082 | release_firmware(adev->gfx.ce_fw); |
1083 | adev->gfx.ce_fw = NULL((void *)0); |
1084 | release_firmware(adev->gfx.rlc_fw); |
1085 | adev->gfx.rlc_fw = NULL((void *)0); |
1086 | release_firmware(adev->gfx.mec_fw); |
1087 | adev->gfx.mec_fw = NULL((void *)0); |
1088 | release_firmware(adev->gfx.mec2_fw); |
1089 | adev->gfx.mec2_fw = NULL((void *)0); |
1090 | |
1091 | kfree(adev->gfx.rlc.register_list_format); |
1092 | } |
1093 | |
1094 | static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) |
1095 | { |
1096 | adev->gfx.me_fw_write_wait = false0; |
1097 | adev->gfx.mec_fw_write_wait = false0; |
1098 | |
1099 | if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1))) && |
1100 | ((adev->gfx.mec_fw_version < 0x000001a5) || |
1101 | (adev->gfx.mec_feature_version < 46) || |
1102 | (adev->gfx.pfp_fw_version < 0x000000b7) || |
1103 | (adev->gfx.pfp_feature_version < 46))) |
1104 | DRM_WARN_ONCE("CP firmware version too old, please update!")({ static int __warned; if (!__warned) { printk("\0014" "[" "drm" "] " "CP firmware version too old, please update!"); __warned = 1; } }); |
1105 | |
1106 | switch (adev->ip_versions[GC_HWIP][0]) { |
1107 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
1108 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1109 | (adev->gfx.me_feature_version >= 42) && |
1110 | (adev->gfx.pfp_fw_version >= 0x000000b1) && |
1111 | (adev->gfx.pfp_feature_version >= 42)) |
1112 | adev->gfx.me_fw_write_wait = true1; |
1113 | |
1114 | if ((adev->gfx.mec_fw_version >= 0x00000193) && |
1115 | (adev->gfx.mec_feature_version >= 42)) |
1116 | adev->gfx.mec_fw_write_wait = true1; |
1117 | break; |
1118 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
1119 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1120 | (adev->gfx.me_feature_version >= 44) && |
1121 | (adev->gfx.pfp_fw_version >= 0x000000b2) && |
1122 | (adev->gfx.pfp_feature_version >= 44)) |
1123 | adev->gfx.me_fw_write_wait = true1; |
1124 | |
1125 | if ((adev->gfx.mec_fw_version >= 0x00000196) && |
1126 | (adev->gfx.mec_feature_version >= 44)) |
1127 | adev->gfx.mec_fw_write_wait = true1; |
1128 | break; |
1129 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
1130 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1131 | (adev->gfx.me_feature_version >= 44) && |
1132 | (adev->gfx.pfp_fw_version >= 0x000000b2) && |
1133 | (adev->gfx.pfp_feature_version >= 44)) |
1134 | adev->gfx.me_fw_write_wait = true1; |
1135 | |
1136 | if ((adev->gfx.mec_fw_version >= 0x00000197) && |
1137 | (adev->gfx.mec_feature_version >= 44)) |
1138 | adev->gfx.mec_fw_write_wait = true1; |
1139 | break; |
1140 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
1141 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
1142 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1143 | (adev->gfx.me_feature_version >= 42) && |
1144 | (adev->gfx.pfp_fw_version >= 0x000000b1) && |
1145 | (adev->gfx.pfp_feature_version >= 42)) |
1146 | adev->gfx.me_fw_write_wait = true1; |
1147 | |
1148 | if ((adev->gfx.mec_fw_version >= 0x00000192) && |
1149 | (adev->gfx.mec_feature_version >= 42)) |
1150 | adev->gfx.mec_fw_write_wait = true1; |
1151 | break; |
1152 | default: |
1153 | adev->gfx.me_fw_write_wait = true1; |
1154 | adev->gfx.mec_fw_write_wait = true1; |
1155 | break; |
1156 | } |
1157 | } |
1158 | |
1159 | struct amdgpu_gfxoff_quirk { |
1160 | u16 chip_vendor; |
1161 | u16 chip_device; |
1162 | u16 subsys_vendor; |
1163 | u16 subsys_device; |
1164 | u8 revision; |
1165 | }; |
1166 | |
1167 | static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { |
1168 | /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ |
1169 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, |
1170 | /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ |
1171 | { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, |
1172 | /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ |
1173 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, |
1174 | /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ |
1175 | { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, |
1176 | { 0, 0, 0, 0, 0 }, |
1177 | }; |
1178 | |
1179 | static bool_Bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) |
1180 | { |
1181 | const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; |
1182 | |
1183 | while (p && p->chip_device != 0) { |
1184 | if (pdev->vendor == p->chip_vendor && |
1185 | pdev->device == p->chip_device && |
1186 | pdev->subsystem_vendor == p->subsys_vendor && |
1187 | pdev->subsystem_device == p->subsys_device && |
1188 | pdev->revision == p->revision) { |
1189 | return true1; |
1190 | } |
1191 | ++p; |
1192 | } |
1193 | return false0; |
1194 | } |
1195 | |
1196 | static bool_Bool is_raven_kicker(struct amdgpu_device *adev) |
1197 | { |
1198 | if (adev->pm.fw_version >= 0x41e2b) |
1199 | return true1; |
1200 | else |
1201 | return false0; |
1202 | } |
1203 | |
1204 | static bool_Bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) |
1205 | { |
1206 | if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0))) && |
1207 | (adev->gfx.me_fw_version >= 0x000000a5) && |
1208 | (adev->gfx.me_feature_version >= 52)) |
1209 | return true1; |
1210 | else |
1211 | return false0; |
1212 | } |
1213 | |
1214 | static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) |
1215 | { |
1216 | if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) |
1217 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
1218 | |
1219 | switch (adev->ip_versions[GC_HWIP][0]) { |
1220 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
1221 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
1222 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
1223 | break; |
1224 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
1225 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
1226 | if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || |
1227 | (adev->apu_flags & AMD_APU_IS_PICASSO)) && |
1228 | ((!is_raven_kicker(adev) && |
1229 | adev->gfx.rlc_fw_version < 531) || |
1230 | (adev->gfx.rlc_feature_version < 1) || |
1231 | !adev->gfx.rlc.is_rlc_v2_1)) |
1232 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
1233 | |
1234 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
1235 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG(1 << 0) | |
1236 | AMD_PG_SUPPORT_CP(1 << 5) | |
1237 | AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7); |
1238 | break; |
1239 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
1240 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
1241 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG(1 << 0) | |
1242 | AMD_PG_SUPPORT_CP(1 << 5) | |
1243 | AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7); |
1244 | break; |
1245 | default: |
1246 | break; |
1247 | } |
1248 | } |
1249 | |
1250 | static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, |
1251 | const char *chip_name) |
1252 | { |
1253 | char fw_name[30]; |
1254 | int err; |
1255 | |
1256 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
1257 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
1258 | if (err) |
1259 | goto out; |
1260 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
1261 | if (err) |
1262 | goto out; |
1263 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); |
1264 | |
1265 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
1266 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
1267 | if (err) |
1268 | goto out; |
1269 | err = amdgpu_ucode_validate(adev->gfx.me_fw); |
1270 | if (err) |
1271 | goto out; |
1272 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); |
1273 | |
1274 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
1275 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
1276 | if (err) |
1277 | goto out; |
1278 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
1279 | if (err) |
1280 | goto out; |
1281 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); |
1282 | |
1283 | out: |
1284 | if (err) { |
1285 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1286 | "gfx9: Failed to init firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1287 | fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ); |
1288 | release_firmware(adev->gfx.pfp_fw); |
1289 | adev->gfx.pfp_fw = NULL((void *)0); |
1290 | release_firmware(adev->gfx.me_fw); |
1291 | adev->gfx.me_fw = NULL((void *)0); |
1292 | release_firmware(adev->gfx.ce_fw); |
1293 | adev->gfx.ce_fw = NULL((void *)0); |
1294 | } |
1295 | return err; |
1296 | } |
1297 | |
1298 | static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, |
1299 | const char *chip_name) |
1300 | { |
1301 | char fw_name[30]; |
1302 | int err; |
1303 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
1304 | uint16_t version_major; |
1305 | uint16_t version_minor; |
1306 | uint32_t smu_version; |
1307 | |
1308 | /* |
1309 | * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin |
1310 | * instead of picasso_rlc.bin. |
1311 | * Judgment method: |
1312 | * PCO AM4: revision >= 0xC8 && revision <= 0xCF |
1313 | * or revision >= 0xD8 && revision <= 0xDF |
1314 | * otherwise is PCO FP5 |
1315 | */ |
1316 | if (!strcmp(chip_name, "picasso") && |
1317 | (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || |
1318 | ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) |
1319 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); |
1320 | else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && |
1321 | (smu_version >= 0x41e2b)) |
1322 | /** |
1323 | *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. |
1324 | */ |
1325 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); |
1326 | else |
1327 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); |
1328 | err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); |
1329 | if (err) |
1330 | goto out; |
1331 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
1332 | if (err) |
1333 | goto out; |
1334 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
1335 | |
1336 | version_major = le16_to_cpu(rlc_hdr->header.header_version_major)((__uint16_t)(rlc_hdr->header.header_version_major)); |
1337 | version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor)((__uint16_t)(rlc_hdr->header.header_version_minor)); |
1338 | err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); |
1339 | out: |
1340 | if (err) { |
1341 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1342 | "gfx9: Failed to init firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1343 | fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ); |
1344 | release_firmware(adev->gfx.rlc_fw); |
1345 | adev->gfx.rlc_fw = NULL((void *)0); |
1346 | } |
1347 | return err; |
1348 | } |
1349 | |
1350 | static bool_Bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) |
1351 | { |
1352 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)) || |
1353 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)) || |
1354 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0))) |
1355 | return false0; |
1356 | |
1357 | return true1; |
1358 | } |
1359 | |
1360 | static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, |
1361 | const char *chip_name) |
1362 | { |
1363 | char fw_name[30]; |
1364 | int err; |
1365 | |
1366 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) && (adev->asic_type == CHIP_ALDEBARAN)) |
1367 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); |
1368 | else |
1369 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); |
1370 | |
1371 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
1372 | if (err) |
1373 | goto out; |
1374 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
1375 | if (err) |
1376 | goto out; |
1377 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); |
1378 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); |
1379 | |
1380 | if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { |
1381 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) && (adev->asic_type == CHIP_ALDEBARAN)) |
1382 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); |
1383 | else |
1384 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); |
1385 | |
1386 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
1387 | if (!err) { |
1388 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
1389 | if (err) |
1390 | goto out; |
1391 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); |
1392 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); |
1393 | } else { |
1394 | err = 0; |
1395 | adev->gfx.mec2_fw = NULL((void *)0); |
1396 | } |
1397 | } else { |
1398 | adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; |
1399 | adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; |
1400 | } |
1401 | |
1402 | out: |
1403 | gfx_v9_0_check_if_need_gfxoff(adev); |
1404 | gfx_v9_0_check_fw_write_wait(adev); |
1405 | if (err) { |
1406 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1407 | "gfx9: Failed to init firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1408 | fw_name)printf("drm:pid%d:%s *ERROR* " "gfx9: Failed to init firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ); |
1409 | release_firmware(adev->gfx.mec_fw); |
1410 | adev->gfx.mec_fw = NULL((void *)0); |
1411 | release_firmware(adev->gfx.mec2_fw); |
1412 | adev->gfx.mec2_fw = NULL((void *)0); |
1413 | } |
1414 | return err; |
1415 | } |
1416 | |
1417 | static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) |
1418 | { |
1419 | const char *chip_name; |
1420 | int r; |
1421 | |
1422 | DRM_DEBUG("\n")___drm_dbg(((void *)0), DRM_UT_CORE, "\n"); |
1423 | |
1424 | switch (adev->ip_versions[GC_HWIP][0]) { |
1425 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
1426 | chip_name = "vega10"; |
1427 | break; |
1428 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
1429 | chip_name = "vega12"; |
1430 | break; |
1431 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
1432 | chip_name = "vega20"; |
1433 | break; |
1434 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
1435 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
1436 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1437 | chip_name = "raven2"; |
1438 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
1439 | chip_name = "picasso"; |
1440 | else |
1441 | chip_name = "raven"; |
1442 | break; |
1443 | case IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)): |
1444 | chip_name = "arcturus"; |
1445 | break; |
1446 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
1447 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1448 | chip_name = "renoir"; |
1449 | else |
1450 | chip_name = "green_sardine"; |
1451 | break; |
1452 | case IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)): |
1453 | chip_name = "aldebaran"; |
1454 | break; |
1455 | default: |
1456 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c" , 1456); } while (0); |
1457 | } |
1458 | |
1459 | /* No CPG in Arcturus */ |
1460 | if (adev->gfx.num_gfx_rings) { |
1461 | r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); |
1462 | if (r) |
1463 | return r; |
1464 | } |
1465 | |
1466 | r = gfx_v9_0_init_rlc_microcode(adev, chip_name); |
1467 | if (r) |
1468 | return r; |
1469 | |
1470 | r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); |
1471 | if (r) |
1472 | return r; |
1473 | |
1474 | return r; |
1475 | } |
1476 | |
1477 | static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) |
1478 | { |
1479 | u32 count = 0; |
1480 | const struct cs_section_def *sect = NULL((void *)0); |
1481 | const struct cs_extent_def *ext = NULL((void *)0); |
1482 | |
1483 | /* begin clear state */ |
1484 | count += 2; |
1485 | /* context control state */ |
1486 | count += 3; |
1487 | |
1488 | for (sect = gfx9_cs_data; sect->section != NULL((void *)0); ++sect) { |
1489 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
1490 | if (sect->id == SECT_CONTEXT) |
1491 | count += 2 + ext->reg_count; |
1492 | else |
1493 | return 0; |
1494 | } |
1495 | } |
1496 | |
1497 | /* end clear state */ |
1498 | count += 2; |
1499 | /* clear state */ |
1500 | count += 2; |
1501 | |
1502 | return count; |
1503 | } |
1504 | |
1505 | static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, |
1506 | volatile u32 *buffer) |
1507 | { |
1508 | u32 count = 0, i; |
1509 | const struct cs_section_def *sect = NULL((void *)0); |
1510 | const struct cs_extent_def *ext = NULL((void *)0); |
1511 | |
1512 | if (adev->gfx.rlc.cs_data == NULL((void *)0)) |
1513 | return; |
1514 | if (buffer == NULL((void *)0)) |
1515 | return; |
1516 | |
1517 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1518 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE)((__uint32_t)((2 << 28))); |
1519 | |
1520 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1))((__uint32_t)(((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) & 0x3FFF) << 16))); |
1521 | buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000)); |
1522 | buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000)); |
1523 | |
1524 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL((void *)0); ++sect) { |
1525 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
1526 | if (sect->id == SECT_CONTEXT) { |
1527 | buffer[count++] = |
1528 | cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->reg_count) & 0x3FFF) << 16))); |
1529 | buffer[count++] = cpu_to_le32(ext->reg_index -((__uint32_t)(ext->reg_index - 0x0000a000)) |
1530 | PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(ext->reg_index - 0x0000a000)); |
1531 | for (i = 0; i < ext->reg_count; i++) |
1532 | buffer[count++] = cpu_to_le32(ext->extent[i])((__uint32_t)(ext->extent[i])); |
1533 | } else { |
1534 | return; |
1535 | } |
1536 | } |
1537 | } |
1538 | |
1539 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1540 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE)((__uint32_t)((3 << 28))); |
1541 | |
1542 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0))((__uint32_t)(((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1543 | buffer[count++] = cpu_to_le32(0)((__uint32_t)(0)); |
1544 | } |
1545 | |
1546 | static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) |
1547 | { |
1548 | struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; |
1549 | uint32_t pg_always_on_cu_num = 2; |
1550 | uint32_t always_on_cu_num; |
1551 | uint32_t i, j, k; |
1552 | uint32_t mask, cu_bitmap, counter; |
1553 | |
1554 | if (adev->flags & AMD_IS_APU) |
1555 | always_on_cu_num = 4; |
1556 | else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1))) |
1557 | always_on_cu_num = 8; |
1558 | else |
1559 | always_on_cu_num = 12; |
1560 | |
1561 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
1562 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
1563 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
1564 | mask = 1; |
1565 | cu_bitmap = 0; |
1566 | counter = 0; |
1567 | gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); |
1568 | |
1569 | for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { |
1570 | if (cu_info->bitmap[i][j] & mask) { |
1571 | if (counter == pg_always_on_cu_num) |
1572 | WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c53), cu_bitmap, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c53)), (cu_bitmap ), 0)); |
1573 | if (counter < always_on_cu_num) |
1574 | cu_bitmap |= mask; |
1575 | else |
1576 | break; |
1577 | counter++; |
1578 | } |
1579 | mask <<= 1; |
1580 | } |
1581 | |
1582 | WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c50), cu_bitmap, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c50)), (cu_bitmap ), 0)); |
1583 | cu_info->ao_cu_bitmap[i][j] = cu_bitmap; |
1584 | } |
1585 | } |
1586 | gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
1587 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
1588 | } |
1589 | |
1590 | static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) |
1591 | { |
1592 | uint32_t data; |
1593 | |
1594 | /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ |
1595 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cbf), 0x0000007F, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cbf)), (0x0000007F ), 0)); |
1596 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cb8), 0x0333A5A7, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cb8)), (0x0333A5A7 ), 0)); |
1597 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cb9), 0x00000077, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cb9)), (0x00000077 ), 0)); |
1598 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cba), (0x30 | 0x40 << 8 | 0x02FA << 16), 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4cba)), ((0x30 | 0x40 << 8 | 0x02FA << 16)), 0)); |
1599 | |
1600 | /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ |
1601 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c1b), 0x00000000, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c1b)), (0x00000000 ), 0)); |
1602 | |
1603 | /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ |
1604 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c12), 0x00000500, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c12)), (0x00000500 ), 0)); |
1605 | |
1606 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
1607 | /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ |
1608 | gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
1609 | WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c4f), 0xffffffff, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c4f)), (0xffffffff ), 0)); |
1610 | |
1611 | /* set mmRLC_LB_PARAMS = 0x003F_1006 */ |
1612 | data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003)(((0) & ~0x000000FEL) | (0x000000FEL & ((0x0003) << 0x1))); |
1613 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((0x0010) << 0x8))); |
1614 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F)(((data) & ~0xFFFF0000L) | (0xFFFF0000L & ((0x033F) << 0x10))); |
1615 | WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c51), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c51)), (data), 0)); |
1616 | |
1617 | /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ |
1618 | data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c6a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c6a), 0)); |
1619 | data &= 0x0000FFFF; |
1620 | data |= 0x00C00000; |
1621 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6a), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c6a)), (data), 0)); |
1622 | |
1623 | /* |
1624 | * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), |
1625 | * programmed in gfx_v9_0_init_always_on_cu_mask() |
1626 | */ |
1627 | |
1628 | /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, |
1629 | * but used for RLC_LB_CNTL configuration */ |
1630 | data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK0x00000004L; |
1631 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09)(((data) & ~0x00000FF0L) | (0x00000FF0L & ((0x09) << 0x4))); |
1632 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000)(((data) & ~0xFFFFF000L) | (0xFFFFF000L & ((0x80000) << 0xc))); |
1633 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c19), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c19)), (data), 0)); |
1634 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
1635 | |
1636 | gfx_v9_0_init_always_on_cu_mask(adev); |
1637 | } |
1638 | |
1639 | static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) |
1640 | { |
1641 | uint32_t data; |
1642 | |
1643 | /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ |
1644 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cbf), 0x0000007F, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cbf)), (0x0000007F ), 0)); |
1645 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cb8), 0x033388F8, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cb8)), (0x033388F8 ), 0)); |
1646 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cb9), 0x00000077, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4cb9)), (0x00000077 ), 0)); |
1647 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cba), (0x10 | 0x27 << 8 | 0x02FA << 16), 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4cba)), ((0x10 | 0x27 << 8 | 0x02FA << 16)), 0)); |
1648 | |
1649 | /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ |
1650 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c1b), 0x00000000, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c1b)), (0x00000000 ), 0)); |
1651 | |
1652 | /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ |
1653 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c12), 0x00000800, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c12)), (0x00000800 ), 0)); |
1654 | |
1655 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
1656 | /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ |
1657 | gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
1658 | WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c4f), 0xffffffff, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x4c4f)), (0xffffffff ), 0)); |
1659 | |
1660 | /* set mmRLC_LB_PARAMS = 0x003F_1006 */ |
1661 | data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003)(((0) & ~0x000000FEL) | (0x000000FEL & ((0x0003) << 0x1))); |
1662 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((0x0010) << 0x8))); |
1663 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F)(((data) & ~0xFFFF0000L) | (0xFFFF0000L & ((0x033F) << 0x10))); |
1664 | WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c51), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c51)), (data), 0)); |
1665 | |
1666 | /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ |
1667 | data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c6a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c6a), 0)); |
1668 | data &= 0x0000FFFF; |
1669 | data |= 0x00C00000; |
1670 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6a), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c6a)), (data), 0)); |
1671 | |
1672 | /* |
1673 | * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), |
1674 | * programmed in gfx_v9_0_init_always_on_cu_mask() |
1675 | */ |
1676 | |
1677 | /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, |
1678 | * but used for RLC_LB_CNTL configuration */ |
1679 | data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK0x00000004L; |
1680 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09)(((data) & ~0x00000FF0L) | (0x00000FF0L & ((0x09) << 0x4))); |
1681 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000)(((data) & ~0xFFFFF000L) | (0xFFFFF000L & ((0x80000) << 0xc))); |
1682 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c19), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c19)), (data), 0)); |
1683 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
1684 | |
1685 | gfx_v9_0_init_always_on_cu_mask(adev); |
1686 | } |
1687 | |
1688 | static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool_Bool enable) |
1689 | { |
1690 | WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c19, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c19, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c19), 0)) & ~0x00000001L) | (enable ? 1 : 0) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg (adev, (adev->reg_offset[GC_HWIP][0][1] + 0x4c19), ((((((adev )->virt.caps & (1 << 2)) && adev->gfx .rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c19, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c19), 0)) & ~0x00000001L) | (enable ? 1 : 0) << 0x0), 0)); |
1691 | } |
1692 | |
1693 | static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) |
1694 | { |
1695 | if (gfx_v9_0_load_mec2_fw_bin_support(adev)) |
1696 | return 5; |
1697 | else |
1698 | return 4; |
1699 | } |
1700 | |
1701 | static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) |
1702 | { |
1703 | struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; |
1704 | |
1705 | reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; |
1706 | reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040); |
1707 | reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1)(adev->reg_offset[GC_HWIP][0][1] + 0x2041); |
1708 | reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2)(adev->reg_offset[GC_HWIP][0][1] + 0x2042); |
1709 | reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3)(adev->reg_offset[GC_HWIP][0][1] + 0x2043); |
1710 | reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x0022); |
1711 | reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX)(adev->reg_offset[GC_HWIP][0][1] + 0x2200); |
1712 | reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT)(adev->reg_offset[GC_HWIP][0][1] + 0x4ccc); |
1713 | adev->gfx.rlc.rlcg_reg_access_supported = true1; |
1714 | } |
1715 | |
1716 | static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) |
1717 | { |
1718 | const struct cs_section_def *cs_data; |
1719 | int r; |
1720 | |
1721 | adev->gfx.rlc.cs_data = gfx9_cs_data; |
1722 | |
1723 | cs_data = adev->gfx.rlc.cs_data; |
1724 | |
1725 | if (cs_data) { |
1726 | /* init clear state block */ |
1727 | r = amdgpu_gfx_rlc_init_csb(adev); |
1728 | if (r) |
1729 | return r; |
1730 | } |
1731 | |
1732 | if (adev->flags & AMD_IS_APU) { |
1733 | /* TODO: double check the cp_table_size for RV */ |
1734 | adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048)(((96 * 5 * 4) + ((2048) - 1)) & (~((__typeof(96 * 5 * 4) )(2048) - 1))) + (64 * 1024); /* JT + GDS */ |
1735 | r = amdgpu_gfx_rlc_init_cpt(adev); |
1736 | if (r) |
1737 | return r; |
1738 | } |
1739 | |
1740 | switch (adev->ip_versions[GC_HWIP][0]) { |
1741 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
1742 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
1743 | gfx_v9_0_init_lbpw(adev); |
1744 | break; |
1745 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
1746 | gfx_v9_4_init_lbpw(adev); |
1747 | break; |
1748 | default: |
1749 | break; |
1750 | } |
1751 | |
1752 | /* init spm vmid with 0xf */ |
1753 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
1754 | adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); |
1755 | |
1756 | return 0; |
1757 | } |
1758 | |
1759 | static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) |
1760 | { |
1761 | amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL((void *)0), NULL((void *)0)); |
1762 | amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL((void *)0), NULL((void *)0)); |
1763 | } |
1764 | |
1765 | static int gfx_v9_0_mec_init(struct amdgpu_device *adev) |
1766 | { |
1767 | int r; |
1768 | u32 *hpd; |
1769 | const __le32 *fw_data; |
1770 | unsigned fw_size; |
1771 | u32 *fw; |
1772 | size_t mec_hpd_size; |
1773 | |
1774 | const struct gfx_firmware_header_v1_0 *mec_hdr; |
1775 | |
1776 | bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES128); |
1777 | |
1778 | /* take ownership of the relevant compute queues */ |
1779 | amdgpu_gfx_compute_queue_acquire(adev); |
1780 | mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE4096; |
1781 | if (mec_hpd_size) { |
1782 | r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE(1 << 12), |
1783 | AMDGPU_GEM_DOMAIN_VRAM0x4, |
1784 | &adev->gfx.mec.hpd_eop_obj, |
1785 | &adev->gfx.mec.hpd_eop_gpu_addr, |
1786 | (void **)&hpd); |
1787 | if (r) { |
1788 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create HDP EOP bo failed\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
1789 | gfx_v9_0_mec_fini(adev); |
1790 | return r; |
1791 | } |
1792 | |
1793 | memset(hpd, 0, mec_hpd_size)__builtin_memset((hpd), (0), (mec_hpd_size)); |
1794 | |
1795 | amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); |
1796 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
1797 | } |
1798 | |
1799 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
1800 | |
1801 | fw_data = (const __le32 *) |
1802 | (adev->gfx.mec_fw->data + |
1803 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes))); |
1804 | fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes)((__uint32_t)(mec_hdr->header.ucode_size_bytes)); |
1805 | |
1806 | r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, |
1807 | PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2, |
1808 | &adev->gfx.mec.mec_fw_obj, |
1809 | &adev->gfx.mec.mec_fw_gpu_addr, |
1810 | (void **)&fw); |
1811 | if (r) { |
1812 | dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create mec firmware bo failed\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
1813 | gfx_v9_0_mec_fini(adev); |
1814 | return r; |
1815 | } |
1816 | |
1817 | memcpy(fw, fw_data, fw_size)__builtin_memcpy((fw), (fw_data), (fw_size)); |
1818 | |
1819 | amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); |
1820 | amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); |
1821 | |
1822 | return 0; |
1823 | } |
1824 | |
1825 | static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) |
1826 | { |
1827 | WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L)), 0)); } while (0) |
1828 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L)), 0)); } while (0) |
1829 | (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L)), 0)); } while (0) |
1830 | (address << SQ_IND_INDEX__INDEX__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L)), 0)); } while (0) |
1831 | (SQ_IND_INDEX__FORCE_READ_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((wave << 0x0) | (simd << 0x4) | (address << 0x10) | (0x00002000L)), 0)); } while (0); |
1832 | return RREG32_SOC15(GC, 0, mmSQ_IND_DATA)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0379, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0379), 0)); |
1833 | } |
1834 | |
1835 | static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, |
1836 | uint32_t wave, uint32_t thread, |
1837 | uint32_t regno, uint32_t num, uint32_t *out) |
1838 | { |
1839 | WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1840 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1841 | (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1842 | (regno << SQ_IND_INDEX__INDEX__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1843 | (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1844 | (SQ_IND_INDEX__FORCE_READ_MASK) |do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0) |
1845 | (SQ_IND_INDEX__AUTO_INCR_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x0378; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (wave << 0x0) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), ((wave << 0x0 ) | (simd << 0x4) | (regno << 0x10) | (thread << 0x6) | (0x00002000L) | (0x00001000L)), 0)); } while (0); |
1846 | while (num--) |
1847 | *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0379, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0379), 0)); |
1848 | } |
1849 | |
1850 | static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) |
1851 | { |
1852 | /* type 1 wave data */ |
1853 | dst[(*no_fields)++] = 1; |
1854 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS0x0012); |
1855 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO0x0018); |
1856 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI0x0019); |
1857 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO0x027e); |
1858 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI0x027f); |
1859 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID0x0014); |
1860 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW00x001a); |
1861 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW10x001b); |
1862 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC0x0015); |
1863 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC0x0016); |
1864 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS0x0013); |
1865 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS0x0017); |
1866 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG00x001c); |
1867 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M00x027c); |
1868 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE0x0011); |
1869 | } |
1870 | |
1871 | static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, |
1872 | uint32_t wave, uint32_t start, |
1873 | uint32_t size, uint32_t *dst) |
1874 | { |
1875 | wave_read_regs( |
1876 | adev, simd, wave, 0, |
1877 | start + SQIND_WAVE_SGPRS_OFFSET0x00000200, size, dst); |
1878 | } |
1879 | |
1880 | static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, |
1881 | uint32_t wave, uint32_t thread, |
1882 | uint32_t start, uint32_t size, |
1883 | uint32_t *dst) |
1884 | { |
1885 | wave_read_regs( |
1886 | adev, simd, wave, thread, |
1887 | start + SQIND_WAVE_VGPRS_OFFSET0x00000400, size, dst); |
1888 | } |
1889 | |
1890 | static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, |
1891 | u32 me, u32 pipe, u32 q, u32 vm) |
1892 | { |
1893 | soc15_grbm_select(adev, me, pipe, q, vm); |
1894 | } |
1895 | |
1896 | static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { |
1897 | .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, |
1898 | .select_se_sh = &gfx_v9_0_select_se_sh, |
1899 | .read_wave_data = &gfx_v9_0_read_wave_data, |
1900 | .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, |
1901 | .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, |
1902 | .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, |
1903 | }; |
1904 | |
1905 | const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { |
1906 | .ras_error_inject = &gfx_v9_0_ras_error_inject, |
1907 | .query_ras_error_count = &gfx_v9_0_query_ras_error_count, |
1908 | .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, |
1909 | }; |
1910 | |
1911 | static struct amdgpu_gfx_ras gfx_v9_0_ras = { |
1912 | .ras_block = { |
1913 | .hw_ops = &gfx_v9_0_ras_ops, |
1914 | }, |
1915 | }; |
1916 | |
1917 | static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) |
1918 | { |
1919 | u32 gb_addr_config; |
1920 | int err; |
1921 | |
1922 | adev->gfx.funcs = &gfx_v9_0_gfx_funcs; |
1923 | |
1924 | switch (adev->ip_versions[GC_HWIP][0]) { |
1925 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
1926 | adev->gfx.config.max_hw_contexts = 8; |
1927 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1928 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1929 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1930 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1931 | gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN0x2a114042; |
1932 | break; |
1933 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
1934 | adev->gfx.config.max_hw_contexts = 8; |
1935 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1936 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1937 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1938 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1939 | gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN0x24104041; |
1940 | DRM_INFO("fix gfx.config for vega12\n")printk("\0016" "[" "drm" "] " "fix gfx.config for vega12\n"); |
1941 | break; |
1942 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
1943 | adev->gfx.ras = &gfx_v9_0_ras; |
1944 | adev->gfx.config.max_hw_contexts = 8; |
1945 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1946 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1947 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1948 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1949 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x063e, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x063e), 0)); |
1950 | gb_addr_config &= ~0xf3e777ff; |
1951 | gb_addr_config |= 0x22014042; |
1952 | /* check vbios table if gpu info is not available */ |
1953 | err = amdgpu_atomfirmware_get_gfx_info(adev); |
1954 | if (err) |
1955 | return err; |
1956 | break; |
1957 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
1958 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
1959 | adev->gfx.config.max_hw_contexts = 8; |
1960 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1961 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1962 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1963 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1964 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1965 | gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN0x26013041; |
1966 | else |
1967 | gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN0x24000042; |
1968 | break; |
1969 | case IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)): |
1970 | adev->gfx.ras = &gfx_v9_4_ras; |
1971 | adev->gfx.config.max_hw_contexts = 8; |
1972 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1973 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1974 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1975 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1976 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x063e, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x063e), 0)); |
1977 | gb_addr_config &= ~0xf3e777ff; |
1978 | gb_addr_config |= 0x22014042; |
1979 | break; |
1980 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
1981 | adev->gfx.config.max_hw_contexts = 8; |
1982 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1983 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1984 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; |
1985 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1986 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x063e, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x063e), 0)); |
1987 | gb_addr_config &= ~0xf3e777ff; |
1988 | gb_addr_config |= 0x22010042; |
1989 | break; |
1990 | case IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)): |
1991 | adev->gfx.ras = &gfx_v9_4_2_ras; |
1992 | adev->gfx.config.max_hw_contexts = 8; |
1993 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1994 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1995 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1996 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; |
1997 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x063e, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x063e), 0)); |
1998 | gb_addr_config &= ~0xf3e777ff; |
1999 | gb_addr_config |= 0x22014042; |
2000 | /* check vbios table if gpu info is not available */ |
2001 | err = amdgpu_atomfirmware_get_gfx_info(adev); |
2002 | if (err) |
2003 | return err; |
2004 | break; |
2005 | default: |
2006 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c" , 2006); } while (0); |
2007 | break; |
2008 | } |
2009 | |
2010 | if (adev->gfx.ras) { |
2011 | err = amdgpu_ras_register_ras_block(adev, &adev->gfx.ras->ras_block); |
2012 | if (err) { |
2013 | DRM_ERROR("Failed to register gfx ras block!\n")__drm_err("Failed to register gfx ras block!\n"); |
2014 | return err; |
2015 | } |
2016 | |
2017 | strlcpy(adev->gfx.ras->ras_block.ras_comm.name, "gfx", |
2018 | sizeof(adev->gfx.ras->ras_block.ras_comm.name)); |
2019 | adev->gfx.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; |
2020 | adev->gfx.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; |
2021 | adev->gfx.ras_if = &adev->gfx.ras->ras_block.ras_comm; |
2022 | |
2023 | /* If not define special ras_late_init function, use gfx default ras_late_init */ |
2024 | if (!adev->gfx.ras->ras_block.ras_late_init) |
2025 | adev->gfx.ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; |
2026 | |
2027 | /* If not defined special ras_cb function, use default ras_cb */ |
2028 | if (!adev->gfx.ras->ras_block.ras_cb) |
2029 | adev->gfx.ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; |
2030 | } |
2031 | |
2032 | adev->gfx.config.gb_addr_config = gb_addr_config; |
2033 | |
2034 | adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << |
2035 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00000007L) >> 0x0) |
2036 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >> 0x0) |
2037 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >> 0x0) |
2038 | NUM_PIPES)(((adev->gfx.config.gb_addr_config) & 0x00000007L) >> 0x0); |
2039 | |
2040 | adev->gfx.config.max_tile_pipes = |
2041 | adev->gfx.config.gb_addr_config_fields.num_pipes; |
2042 | |
2043 | adev->gfx.config.gb_addr_config_fields.num_banks = 1 << |
2044 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00007000L) >> 0xc) |
2045 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00007000L) >> 0xc) |
2046 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00007000L) >> 0xc) |
2047 | NUM_BANKS)(((adev->gfx.config.gb_addr_config) & 0x00007000L) >> 0xc); |
2048 | adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << |
2049 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x000000C0L) >> 0x6) |
2050 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >> 0x6) |
2051 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >> 0x6) |
2052 | MAX_COMPRESSED_FRAGS)(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >> 0x6); |
2053 | adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << |
2054 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x0C000000L) >> 0x1a) |
2055 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >> 0x1a) |
2056 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >> 0x1a) |
2057 | NUM_RB_PER_SE)(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >> 0x1a); |
2058 | adev->gfx.config.gb_addr_config_fields.num_se = 1 << |
2059 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00180000L) >> 0x13) |
2060 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >> 0x13) |
2061 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >> 0x13) |
2062 | NUM_SHADER_ENGINES)(((adev->gfx.config.gb_addr_config) & 0x00180000L) >> 0x13); |
2063 | adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + |
2064 | REG_GET_FIELD((((adev->gfx.config.gb_addr_config) & 0x00000038L) >> 0x3) |
2065 | adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >> 0x3) |
2066 | GB_ADDR_CONFIG,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >> 0x3) |
2067 | PIPE_INTERLEAVE_SIZE)(((adev->gfx.config.gb_addr_config) & 0x00000038L) >> 0x3)); |
2068 | |
2069 | return 0; |
2070 | } |
2071 | |
2072 | static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, |
2073 | int mec, int pipe, int queue) |
2074 | { |
2075 | unsigned irq_type; |
2076 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; |
Value stored to 'ring' during its initialization is never read | |
2077 | unsigned int hw_prio; |
2078 | |
2079 | ring = &adev->gfx.compute_ring[ring_id]; |
2080 | |
2081 | /* mec0 is me1 */ |
2082 | ring->me = mec + 1; |
2083 | ring->pipe = pipe; |
2084 | ring->queue = queue; |
2085 | |
2086 | ring->ring_obj = NULL((void *)0); |
2087 | ring->use_doorbell = true1; |
2088 | ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; |
2089 | ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr |
2090 | + (ring_id * GFX9_MEC_HPD_SIZE4096); |
2091 | snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); |
2092 | |
2093 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP |
2094 | + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) |
2095 | + ring->pipe; |
2096 | hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? |
2097 | AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; |
2098 | /* type-2 packets are deprecated on MEC, use type-3 instead */ |
2099 | return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, |
2100 | hw_prio, NULL((void *)0)); |
2101 | } |
2102 | |
2103 | static int gfx_v9_0_sw_init(void *handle) |
2104 | { |
2105 | int i, j, k, r, ring_id; |
2106 | struct amdgpu_ring *ring; |
2107 | struct amdgpu_kiq *kiq; |
2108 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2109 | |
2110 | switch (adev->ip_versions[GC_HWIP][0]) { |
2111 | case IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)): |
2112 | case IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)): |
2113 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
2114 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
2115 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
2116 | case IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)): |
2117 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
2118 | case IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)): |
2119 | adev->gfx.mec.num_mec = 2; |
2120 | break; |
2121 | default: |
2122 | adev->gfx.mec.num_mec = 1; |
2123 | break; |
2124 | } |
2125 | |
2126 | adev->gfx.mec.num_pipe_per_mec = 4; |
2127 | adev->gfx.mec.num_queue_per_pipe = 8; |
2128 | |
2129 | /* EOP Event */ |
2130 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT181, &adev->gfx.eop_irq); |
2131 | if (r) |
2132 | return r; |
2133 | |
2134 | /* Privileged reg */ |
2135 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT184, |
2136 | &adev->gfx.priv_reg_irq); |
2137 | if (r) |
2138 | return r; |
2139 | |
2140 | /* Privileged inst */ |
2141 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT185, |
2142 | &adev->gfx.priv_inst_irq); |
2143 | if (r) |
2144 | return r; |
2145 | |
2146 | /* ECC error */ |
2147 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR197, |
2148 | &adev->gfx.cp_ecc_error_irq); |
2149 | if (r) |
2150 | return r; |
2151 | |
2152 | /* FUE error */ |
2153 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR201, |
2154 | &adev->gfx.cp_ecc_error_irq); |
2155 | if (r) |
2156 | return r; |
2157 | |
2158 | adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE0x00000000L; |
2159 | |
2160 | r = gfx_v9_0_init_microcode(adev); |
2161 | if (r) { |
2162 | DRM_ERROR("Failed to load gfx firmware!\n")__drm_err("Failed to load gfx firmware!\n"); |
2163 | return r; |
2164 | } |
2165 | |
2166 | if (adev->gfx.rlc.funcs) { |
2167 | if (adev->gfx.rlc.funcs->init) { |
2168 | r = adev->gfx.rlc.funcs->init(adev); |
2169 | if (r) { |
2170 | dev_err(adev->dev, "Failed to init rlc BOs!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init rlc BOs!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
2171 | return r; |
2172 | } |
2173 | } |
2174 | } |
2175 | |
2176 | r = gfx_v9_0_mec_init(adev); |
2177 | if (r) { |
2178 | DRM_ERROR("Failed to init MEC BOs!\n")__drm_err("Failed to init MEC BOs!\n"); |
2179 | return r; |
2180 | } |
2181 | |
2182 | /* set up the gfx ring */ |
2183 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
2184 | ring = &adev->gfx.gfx_ring[i]; |
2185 | ring->ring_obj = NULL((void *)0); |
2186 | if (!i) |
2187 | snprintf(ring->name, sizeof(ring->name), "gfx"); |
2188 | else |
2189 | snprintf(ring->name, sizeof(ring->name), "gfx_%d", i); |
2190 | ring->use_doorbell = true1; |
2191 | ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; |
2192 | r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, |
2193 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, |
2194 | AMDGPU_RING_PRIO_DEFAULT, NULL((void *)0)); |
2195 | if (r) |
2196 | return r; |
2197 | } |
2198 | |
2199 | /* set up the compute queues - allocate horizontally across pipes */ |
2200 | ring_id = 0; |
2201 | for (i = 0; i < adev->gfx.mec.num_mec; ++i) { |
2202 | for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { |
2203 | for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { |
2204 | if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) |
2205 | continue; |
2206 | |
2207 | r = gfx_v9_0_compute_ring_init(adev, |
2208 | ring_id, |
2209 | i, k, j); |
2210 | if (r) |
2211 | return r; |
2212 | |
2213 | ring_id++; |
2214 | } |
2215 | } |
2216 | } |
2217 | |
2218 | r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE4096); |
2219 | if (r) { |
2220 | DRM_ERROR("Failed to init KIQ BOs!\n")__drm_err("Failed to init KIQ BOs!\n"); |
2221 | return r; |
2222 | } |
2223 | |
2224 | kiq = &adev->gfx.kiq; |
2225 | r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); |
2226 | if (r) |
2227 | return r; |
2228 | |
2229 | /* create MQD for all compute queues as wel as KIQ for SRIOV case */ |
2230 | r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); |
2231 | if (r) |
2232 | return r; |
2233 | |
2234 | adev->gfx.ce_ram_size = 0x8000; |
2235 | |
2236 | r = gfx_v9_0_gpu_early_init(adev); |
2237 | if (r) |
2238 | return r; |
2239 | |
2240 | return 0; |
2241 | } |
2242 | |
2243 | |
2244 | static int gfx_v9_0_sw_fini(void *handle) |
2245 | { |
2246 | int i; |
2247 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2248 | |
2249 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
2250 | amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); |
2251 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
2252 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
2253 | |
2254 | amdgpu_gfx_mqd_sw_fini(adev); |
2255 | amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); |
2256 | amdgpu_gfx_kiq_fini(adev); |
2257 | |
2258 | gfx_v9_0_mec_fini(adev); |
2259 | amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, |
2260 | &adev->gfx.rlc.clear_state_gpu_addr, |
2261 | (void **)&adev->gfx.rlc.cs_ptr); |
2262 | if (adev->flags & AMD_IS_APU) { |
2263 | amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, |
2264 | &adev->gfx.rlc.cp_table_gpu_addr, |
2265 | (void **)&adev->gfx.rlc.cp_table_ptr); |
2266 | } |
2267 | gfx_v9_0_free_microcode(adev); |
2268 | |
2269 | return 0; |
2270 | } |
2271 | |
2272 | |
2273 | static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) |
2274 | { |
2275 | /* TODO */ |
2276 | } |
2277 | |
2278 | void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, |
2279 | u32 instance) |
2280 | { |
2281 | u32 data; |
2282 | |
2283 | if (instance == 0xffffffff) |
2284 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1)(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e ))); |
2285 | else |
2286 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance)(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) << 0x0))); |
2287 | |
2288 | if (se_num == 0xffffffff) |
2289 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1)(((data) & ~0x80000000L) | (0x80000000L & ((1) << 0x1f))); |
2290 | else |
2291 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num)(((data) & ~0x00FF0000L) | (0x00FF0000L & ((se_num) << 0x10))); |
2292 | |
2293 | if (sh_num == 0xffffffff) |
2294 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1)(((data) & ~0x20000000L) | (0x20000000L & ((1) << 0x1d))); |
2295 | else |
2296 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((sh_num) << 0x8))); |
2297 | |
2298 | WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x2200), data, (1<<2), GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x2200)), (data ), 0)); |
2299 | } |
2300 | |
2301 | static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) |
2302 | { |
2303 | u32 data, mask; |
2304 | |
2305 | data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x063d, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x063d), 0)); |
2306 | data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x06df, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x06df), 0)); |
2307 | |
2308 | data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK0x00FF0000L; |
2309 | data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT0x10; |
2310 | |
2311 | mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / |
2312 | adev->gfx.config.max_sh_per_se); |
2313 | |
2314 | return (~data) & mask; |
2315 | } |
2316 | |
2317 | static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) |
2318 | { |
2319 | int i, j; |
2320 | u32 data; |
2321 | u32 active_rbs = 0; |
2322 | u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / |
2323 | adev->gfx.config.max_sh_per_se; |
2324 | |
2325 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
2326 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
2327 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
2328 | gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); |
2329 | data = gfx_v9_0_get_rb_active_bitmap(adev); |
2330 | active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * |
2331 | rb_bitmap_width_per_sh); |
2332 | } |
2333 | } |
2334 | gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
2335 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
2336 | |
2337 | adev->gfx.config.backend_enable_mask = active_rbs; |
2338 | adev->gfx.config.num_rbs = hweight32(active_rbs); |
2339 | } |
2340 | |
2341 | #define DEFAULT_SH_MEM_BASES(0x6000) (0x6000) |
2342 | static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) |
2343 | { |
2344 | int i; |
2345 | uint32_t sh_mem_config; |
2346 | uint32_t sh_mem_bases; |
2347 | |
2348 | /* |
2349 | * Configure apertures: |
2350 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) |
2351 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) |
2352 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) |
2353 | */ |
2354 | sh_mem_bases = DEFAULT_SH_MEM_BASES(0x6000) | (DEFAULT_SH_MEM_BASES(0x6000) << 16); |
2355 | |
2356 | sh_mem_config = SH_MEM_ADDRESS_MODE_64 | |
2357 | SH_MEM_ALIGNMENT_MODE_UNALIGNED << |
2358 | SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT0x3; |
2359 | |
2360 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
2361 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) { |
2362 | soc15_grbm_select(adev, 0, 0, 0, i); |
2363 | /* CP and shaders */ |
2364 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, sh_mem_config, (1<< 2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), (sh_mem_config ), 0)); } while (0); |
2365 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, sh_mem_bases, (1<< 2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), (sh_mem_bases ), 0)); } while (0); |
2366 | } |
2367 | soc15_grbm_select(adev, 0, 0, 0, 0); |
2368 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
2369 | |
2370 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA |
2371 | access. These should be enabled by FW for target VMIDs. */ |
2372 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) { |
2373 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1300) + 2 * i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1300) + 2 * i), (0 ), 0)); |
2374 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1301) + 2 * i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1301) + 2 * i), (0 ), 0)); |
2375 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1320) + i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[GC_HWIP][0][0] + 0x1320) + i), (0), 0)); |
2376 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1330) + i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[GC_HWIP][0][0] + 0x1330) + i), (0), 0)); |
2377 | } |
2378 | } |
2379 | |
2380 | static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) |
2381 | { |
2382 | int vmid; |
2383 | |
2384 | /* |
2385 | * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA |
2386 | * access. Compute VMIDs should be enabled by FW for target VMIDs, |
2387 | * the driver can enable them for graphics. VMID0 should maintain |
2388 | * access so that HWS firmware can save/restore entries. |
2389 | */ |
2390 | for (vmid = 1; vmid < AMDGPU_NUM_VMID16; vmid++) { |
2391 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1300) + 2 * vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg( adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1300) + 2 * vmid ), (0), 0)); |
2392 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1301) + 2 * vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg( adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1301) + 2 * vmid ), (0), 0)); |
2393 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1320) + vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1320) + vmid), (0) , 0)); |
2394 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1330) + vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1330) + vmid), (0) , 0)); |
2395 | } |
2396 | } |
2397 | |
2398 | static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) |
2399 | { |
2400 | uint32_t tmp; |
2401 | |
2402 | switch (adev->ip_versions[GC_HWIP][0]) { |
2403 | case IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)): |
2404 | tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0300, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0300), 0)); |
2405 | tmp = REG_SET_FIELD(tmp, SQ_CONFIG,(((tmp) & ~0x00000001L) | (0x00000001L & ((1) << 0x0))) |
2406 | DISABLE_BARRIER_WAITCNT, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) << 0x0))); |
2407 | WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0300), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0300)), (tmp), 0)); |
2408 | break; |
2409 | default: |
2410 | break; |
2411 | } |
2412 | } |
2413 | |
2414 | static void gfx_v9_0_constants_init(struct amdgpu_device *adev) |
2415 | { |
2416 | u32 tmp; |
2417 | int i; |
2418 | |
2419 | WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0000), (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0000, (1<<2), GC_HWIP) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x0000), 0)) & ~0x000000FFL ) | (0xff) << 0x0, (1<<2), GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0000)), ((((( (adev)->virt.caps & (1 << 2)) && adev-> gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0000, (1<<2), GC_HWIP) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x0000), 0)) & ~0x000000FFL ) | (0xff) << 0x0), 0)); |
2420 | |
2421 | gfx_v9_0_tiling_mode_table_init(adev); |
2422 | |
2423 | if (adev->gfx.num_gfx_rings) |
2424 | gfx_v9_0_setup_rb(adev); |
2425 | gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); |
2426 | adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x060d, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x060d), 0)); |
2427 | |
2428 | /* XXX SH_MEM regs */ |
2429 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
2430 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
2431 | for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_00].num_ids; i++) { |
2432 | soc15_grbm_select(adev, 0, 0, 0, i); |
2433 | /* CP and shaders */ |
2434 | if (i == 0) { |
2435 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))) |
2436 | SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))); |
2437 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev-> gmc.noretry) << 0xc))) |
2438 | !!adev->gmc.noretry)(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev-> gmc.noretry) << 0xc))); |
2439 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
2440 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
2441 | } else { |
2442 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))) |
2443 | SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((0) & ~0x00000018L) | (0x00000018L & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))); |
2444 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev-> gmc.noretry) << 0xc))) |
2445 | !!adev->gmc.noretry)(((tmp) & ~0x00001000L) | (0x00001000L & ((!!adev-> gmc.noretry) << 0xc))); |
2446 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
2447 | tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc .private_aperture_start >> 48)) << 0x0))) |
2448 | (adev->gmc.private_aperture_start >> 48))(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc .private_aperture_start >> 48)) << 0x0))); |
2449 | tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev-> gmc.shared_aperture_start >> 48)) << 0x10))) |
2450 | (adev->gmc.shared_aperture_start >> 48))(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev-> gmc.shared_aperture_start >> 48)) << 0x10))); |
2451 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x030a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
2452 | } |
2453 | } |
2454 | soc15_grbm_select(adev, 0, 0, 0, 0); |
2455 | |
2456 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
2457 | |
2458 | gfx_v9_0_init_compute_vmid(adev); |
2459 | gfx_v9_0_init_gds_vmid(adev); |
2460 | gfx_v9_0_init_sq_config(adev); |
2461 | } |
2462 | |
2463 | static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) |
2464 | { |
2465 | u32 i, j, k; |
2466 | u32 mask; |
2467 | |
2468 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
2469 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
2470 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
2471 | gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); |
2472 | for (k = 0; k < adev->usec_timeout; k++) { |
2473 | if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c61, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c61), 0)) == 0) |
2474 | break; |
2475 | udelay(1); |
2476 | } |
2477 | if (k == adev->usec_timeout) { |
2478 | gfx_v9_0_select_se_sh(adev, 0xffffffff, |
2479 | 0xffffffff, 0xffffffff); |
2480 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
2481 | DRM_INFO("Timeout wait for RLC serdes %u,%u\n",printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n" , i, j) |
2482 | i, j)printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n" , i, j); |
2483 | return; |
2484 | } |
2485 | } |
2486 | } |
2487 | gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
2488 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
2489 | |
2490 | mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK0x0000FFFFL | |
2491 | RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK0x00010000L | |
2492 | RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK0x00040000L | |
2493 | RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK0x00080000L; |
2494 | for (k = 0; k < adev->usec_timeout; k++) { |
2495 | if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c62, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c62), 0)) & mask) == 0) |
2496 | break; |
2497 | udelay(1); |
2498 | } |
2499 | } |
2500 | |
2501 | static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, |
2502 | bool_Bool enable) |
2503 | { |
2504 | u32 tmp; |
2505 | |
2506 | /* These interrupts should be enabled to drive DS clock */ |
2507 | |
2508 | tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x106a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x106a), 0)); |
2509 | |
2510 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1 : 0) << 0x13))); |
2511 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1 : 0) << 0x14))); |
2512 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))); |
2513 | if(adev->gfx.num_gfx_rings) |
2514 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1 : 0) << 0x15))); |
2515 | |
2516 | WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x106a), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x106a)), (tmp), 0)); |
2517 | } |
2518 | |
2519 | static void gfx_v9_0_init_csb(struct amdgpu_device *adev) |
2520 | { |
2521 | adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); |
2522 | /* csib */ |
2523 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca3), adev->gfx.rlc.clear_state_gpu_addr >> 32 , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, ((adev-> reg_offset[GC_HWIP][0][1] + 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0)) |
2524 | adev->gfx.rlc.clear_state_gpu_addr >> 32)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca3), adev->gfx.rlc.clear_state_gpu_addr >> 32 , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, ((adev-> reg_offset[GC_HWIP][0][1] + 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0)); |
2525 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca2), adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, ((adev-> reg_offset[GC_HWIP][0][1] + 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0)) |
2526 | adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca2), adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, ((adev-> reg_offset[GC_HWIP][0][1] + 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0)); |
2527 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca4), adev->gfx.rlc.clear_state_size, (1<<2) , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4ca4)), (adev->gfx.rlc.clear_state_size), 0)) |
2528 | adev->gfx.rlc.clear_state_size)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4ca4), adev->gfx.rlc.clear_state_size, (1<<2) , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4ca4)), (adev->gfx.rlc.clear_state_size), 0)); |
2529 | } |
2530 | |
2531 | static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, |
2532 | int indirect_offset, |
2533 | int list_size, |
2534 | int *unique_indirect_regs, |
2535 | int unique_indirect_reg_count, |
2536 | int *indirect_start_offsets, |
2537 | int *indirect_start_offsets_count, |
2538 | int max_start_offsets_count) |
2539 | { |
2540 | int idx; |
2541 | |
2542 | for (; indirect_offset < list_size; indirect_offset++) { |
2543 | WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count)({ int __ret = !!(*indirect_start_offsets_count >= max_start_offsets_count ); if (__ret) printf("WARNING %s failed at %s:%d\n", "*indirect_start_offsets_count >= max_start_offsets_count" , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 2543); __builtin_expect (!!(__ret), 0); }); |
2544 | indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; |
2545 | *indirect_start_offsets_count = *indirect_start_offsets_count + 1; |
2546 | |
2547 | while (register_list_format[indirect_offset] != 0xFFFFFFFF) { |
2548 | indirect_offset += 2; |
2549 | |
2550 | /* look for the matching indice */ |
2551 | for (idx = 0; idx < unique_indirect_reg_count; idx++) { |
2552 | if (unique_indirect_regs[idx] == |
2553 | register_list_format[indirect_offset] || |
2554 | !unique_indirect_regs[idx]) |
2555 | break; |
2556 | } |
2557 | |
2558 | BUG_ON(idx >= unique_indirect_reg_count)((!(idx >= unique_indirect_reg_count)) ? (void)0 : __assert ("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c" , 2558, "!(idx >= unique_indirect_reg_count)")); |
2559 | |
2560 | if (!unique_indirect_regs[idx]) |
2561 | unique_indirect_regs[idx] = register_list_format[indirect_offset]; |
2562 | |
2563 | indirect_offset++; |
2564 | } |
2565 | } |
2566 | } |
2567 | |
2568 | static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) |
2569 | { |
2570 | int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; |
2571 | int unique_indirect_reg_count = 0; |
2572 | |
2573 | int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; |
2574 | int indirect_start_offsets_count = 0; |
2575 | |
2576 | int list_size = 0; |
2577 | int i = 0, j = 0; |
2578 | u32 tmp = 0; |
2579 | |
2580 | u32 *register_list_format = |
2581 | kmemdup(adev->gfx.rlc.register_list_format, |
2582 | adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL(0x0001 | 0x0004)); |
2583 | if (!register_list_format) |
2584 | return -ENOMEM12; |
2585 | |
2586 | /* setup unique_indirect_regs array and indirect_start_offsets array */ |
2587 | unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs)(sizeof((unique_indirect_regs)) / sizeof((unique_indirect_regs )[0])); |
2588 | gfx_v9_1_parse_ind_reg_list(register_list_format, |
2589 | adev->gfx.rlc.reg_list_format_direct_reg_list_length, |
2590 | adev->gfx.rlc.reg_list_format_size_bytes >> 2, |
2591 | unique_indirect_regs, |
2592 | unique_indirect_reg_count, |
2593 | indirect_start_offsets, |
2594 | &indirect_start_offsets_count, |
2595 | ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets )[0]))); |
2596 | |
2597 | /* enable auto inc in case it is disabled */ |
2598 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c80)), 0); |
2599 | tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK0x00000002L; |
2600 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c80)), (tmp), 0); |
2601 | |
2602 | /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ |
2603 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c83)), (0x00000000L), 0) |
2604 | RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c83)), (0x00000000L), 0); |
2605 | for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) |
2606 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c84)), (adev->gfx.rlc.register_restore[i]), 0) |
2607 | adev->gfx.rlc.register_restore[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c84)), (adev->gfx.rlc.register_restore[i]), 0); |
2608 | |
2609 | /* load indirect register */ |
2610 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.reg_list_format_start), 0) |
2611 | adev->gfx.rlc.reg_list_format_start)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.reg_list_format_start), 0); |
2612 | |
2613 | /* direct register portion */ |
2614 | for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) |
2615 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (register_list_format[i]), 0) |
2616 | register_list_format[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (register_list_format[i]), 0); |
2617 | |
2618 | /* indirect register portion */ |
2619 | while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { |
2620 | if (register_list_format[i] == 0xFFFFFFFF) { |
2621 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6d), register_list_format[i++], 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (register_list_format [i++]), 0)); |
2622 | continue; |
2623 | } |
2624 | |
2625 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6d), register_list_format[i++], 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (register_list_format [i++]), 0)); |
2626 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++])((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6d), register_list_format[i++], 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (register_list_format [i++]), 0)); |
2627 | |
2628 | for (j = 0; j < unique_indirect_reg_count; j++) { |
2629 | if (register_list_format[i] == unique_indirect_regs[j]) { |
2630 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c6d), j, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (j), 0)); |
2631 | break; |
2632 | } |
2633 | } |
2634 | |
2635 | BUG_ON(j >= unique_indirect_reg_count)((!(j >= unique_indirect_reg_count)) ? (void)0 : __assert( "diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c" , 2635, "!(j >= unique_indirect_reg_count)")); |
2636 | |
2637 | i++; |
2638 | } |
2639 | |
2640 | /* set save/restore list size */ |
2641 | list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; |
2642 | list_size = list_size >> 1; |
2643 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.reg_restore_list_size), 0) |
2644 | adev->gfx.rlc.reg_restore_list_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.reg_restore_list_size), 0); |
2645 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (list_size), 0); |
2646 | |
2647 | /* write the starting offsets to RLC scratch ram */ |
2648 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.starting_offsets_start), 0) |
2649 | adev->gfx.rlc.starting_offsets_start)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6c)), (adev->gfx.rlc.starting_offsets_start), 0); |
2650 | for (i = 0; i < ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets )[0])); i++) |
2651 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (indirect_start_offsets[i]), 0) |
2652 | indirect_start_offsets[i])amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c6d)), (indirect_start_offsets[i]), 0); |
2653 | |
2654 | /* load unique indirect regs*/ |
2655 | for (i = 0; i < ARRAY_SIZE(unique_indirect_regs)(sizeof((unique_indirect_regs)) / sizeof((unique_indirect_regs )[0])); i++) { |
2656 | if (unique_indirect_regs[i] != 0) { |
2657 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs [i] & 0x3FFFF), 0) |
2658 | + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs [i] & 0x3FFFF), 0) |
2659 | unique_indirect_regs[i] & 0x3FFFF)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c8b) + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i]), (unique_indirect_regs [i] & 0x3FFFF), 0); |
2660 | |
2661 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs [i] >> 20), 0) |
2662 | + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs [i] >> 20), 0) |
2663 | unique_indirect_regs[i] >> 20)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c93) + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i]), (unique_indirect_regs [i] >> 20), 0); |
2664 | } |
2665 | } |
2666 | |
2667 | kfree(register_list_format); |
2668 | return 0; |
2669 | } |
2670 | |
2671 | static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) |
2672 | { |
2673 | WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c80, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c80, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c80), 0)) & ~0x00000001L) | (1) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][1] + 0x4c80), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][1] + 0x4c80, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [1] + 0x4c80), 0)) & ~0x00000001L) | (1) << 0x0), 0 )); |
2674 | } |
2675 | |
2676 | static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, |
2677 | bool_Bool enable) |
2678 | { |
2679 | uint32_t data = 0; |
2680 | uint32_t default_data = 0; |
2681 | |
2682 | default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS))amdgpu_device_rreg(adev, ((adev->reg_offset[PWR_HWIP][0][0 ] + 0x0183)), 0); |
2683 | if (enable) { |
2684 | /* enable GFXIP control over CGPG */ |
2685 | data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK0x00000001L; |
2686 | if(default_data != data) |
2687 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0 ] + 0x0183)), (data), 0); |
2688 | |
2689 | /* update status */ |
2690 | data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK0x00000006L; |
2691 | data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT0x1); |
2692 | if(default_data != data) |
2693 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0 ] + 0x0183)), (data), 0); |
2694 | } else { |
2695 | /* restore GFXIP control over GCPG */ |
2696 | data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK0x00000001L; |
2697 | if(default_data != data) |
2698 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data)amdgpu_device_wreg(adev, ((adev->reg_offset[PWR_HWIP][0][0 ] + 0x0183)), (data), 0); |
2699 | } |
2700 | } |
2701 | |
2702 | static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) |
2703 | { |
2704 | uint32_t data = 0; |
2705 | |
2706 | if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG(1 << 0) | |
2707 | AMD_PG_SUPPORT_GFX_SMG(1 << 1) | |
2708 | AMD_PG_SUPPORT_GFX_DMG(1 << 2))) { |
2709 | /* init IDLE_POLL_COUNT = 60 */ |
2710 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x01c2)), 0); |
2711 | data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK0xFFFF0000L; |
2712 | data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10); |
2713 | WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x01c2)), (data), 0); |
2714 | |
2715 | /* init RLC PG Delay */ |
2716 | data = 0; |
2717 | data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT0x0); |
2718 | data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT0x8); |
2719 | data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT0x10); |
2720 | data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT0x18); |
2721 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c4d)), (data), 0); |
2722 | |
2723 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c1f)), 0); |
2724 | data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK0x0000FF00L; |
2725 | data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT0x8); |
2726 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c1f)), (data), 0); |
2727 | |
2728 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c78)), 0); |
2729 | data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK0x000000FFL; |
2730 | data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT0x0); |
2731 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c78)), (data), 0); |
2732 | |
2733 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c55)), 0); |
2734 | data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK0x0007FFF8L; |
2735 | |
2736 | /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ |
2737 | data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT0x3); |
2738 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c55)), (data), 0); |
2739 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0))) |
2740 | pwr_10_0_gfxip_control_over_cgpg(adev, true1); |
2741 | } |
2742 | } |
2743 | |
2744 | static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, |
2745 | bool_Bool enable) |
2746 | { |
2747 | uint32_t data = 0; |
2748 | uint32_t default_data = 0; |
2749 | |
2750 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2751 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1 : 0) << 0x11))) |
2752 | SMU_CLK_SLOWDOWN_ON_PU_ENABLE,(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1 : 0) << 0x11))) |
2753 | enable ? 1 : 0)(((data) & ~0x00020000L) | (0x00020000L & ((enable ? 1 : 0) << 0x11))); |
2754 | if (default_data != data) |
2755 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2756 | } |
2757 | |
2758 | static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, |
2759 | bool_Bool enable) |
2760 | { |
2761 | uint32_t data = 0; |
2762 | uint32_t default_data = 0; |
2763 | |
2764 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2765 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))) |
2766 | SMU_CLK_SLOWDOWN_ON_PD_ENABLE,(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))) |
2767 | enable ? 1 : 0)(((data) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))); |
2768 | if(default_data != data) |
2769 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2770 | } |
2771 | |
2772 | static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, |
2773 | bool_Bool enable) |
2774 | { |
2775 | uint32_t data = 0; |
2776 | uint32_t default_data = 0; |
2777 | |
2778 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2779 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0 : 1) << 0xf))) |
2780 | CP_PG_DISABLE,(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0 : 1) << 0xf))) |
2781 | enable ? 0 : 1)(((data) & ~0x00008000L) | (0x00008000L & ((enable ? 0 : 1) << 0xf))); |
2782 | if(default_data != data) |
2783 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2784 | } |
2785 | |
2786 | static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, |
2787 | bool_Bool enable) |
2788 | { |
2789 | uint32_t data, default_data; |
2790 | |
2791 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2792 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1 : 0) << 0x0))) |
2793 | GFX_POWER_GATING_ENABLE,(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1 : 0) << 0x0))) |
2794 | enable ? 1 : 0)(((data) & ~0x00000001L) | (0x00000001L & ((enable ? 1 : 0) << 0x0))); |
2795 | if(default_data != data) |
2796 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2797 | } |
2798 | |
2799 | static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, |
2800 | bool_Bool enable) |
2801 | { |
2802 | uint32_t data, default_data; |
2803 | |
2804 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2805 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1 : 0) << 0x4))) |
2806 | GFX_PIPELINE_PG_ENABLE,(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1 : 0) << 0x4))) |
2807 | enable ? 1 : 0)(((data) & ~0x00000010L) | (0x00000010L & ((enable ? 1 : 0) << 0x4))); |
2808 | if(default_data != data) |
2809 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2810 | |
2811 | if (!enable) |
2812 | /* read any GFX register to wake up GFX */ |
2813 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x0000)), 0); |
2814 | } |
2815 | |
2816 | static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, |
2817 | bool_Bool enable) |
2818 | { |
2819 | uint32_t data, default_data; |
2820 | |
2821 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2822 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1 : 0) << 0x3))) |
2823 | STATIC_PER_CU_PG_ENABLE,(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1 : 0) << 0x3))) |
2824 | enable ? 1 : 0)(((data) & ~0x00000008L) | (0x00000008L & ((enable ? 1 : 0) << 0x3))); |
2825 | if(default_data != data) |
2826 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2827 | } |
2828 | |
2829 | static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, |
2830 | bool_Bool enable) |
2831 | { |
2832 | uint32_t data, default_data; |
2833 | |
2834 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), 0); |
2835 | data = REG_SET_FIELD(data, RLC_PG_CNTL,(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1 : 0) << 0x2))) |
2836 | DYN_PER_CU_PG_ENABLE,(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1 : 0) << 0x2))) |
2837 | enable ? 1 : 0)(((data) & ~0x00000004L) | (0x00000004L & ((enable ? 1 : 0) << 0x2))); |
2838 | if(default_data != data) |
2839 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0); |
2840 | } |
2841 | |
2842 | static void gfx_v9_0_init_pg(struct amdgpu_device *adev) |
2843 | { |
2844 | gfx_v9_0_init_csb(adev); |
2845 | |
2846 | /* |
2847 | * Rlc save restore list is workable since v2_1. |
2848 | * And it's needed by gfxoff feature. |
2849 | */ |
2850 | if (adev->gfx.rlc.is_rlc_v2_1) { |
2851 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1)) || |
2852 | (adev->apu_flags & AMD_APU_IS_RAVEN2)) |
2853 | gfx_v9_1_init_rlc_save_restore_list(adev); |
2854 | gfx_v9_0_enable_save_restore_machine(adev); |
2855 | } |
2856 | |
2857 | if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG(1 << 0) | |
2858 | AMD_PG_SUPPORT_GFX_SMG(1 << 1) | |
2859 | AMD_PG_SUPPORT_GFX_DMG(1 << 2) | |
2860 | AMD_PG_SUPPORT_CP(1 << 5) | |
2861 | AMD_PG_SUPPORT_GDS(1 << 6) | |
2862 | AMD_PG_SUPPORT_RLC_SMU_HS(1 << 7))) { |
2863 | WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c1e), adev->gfx.rlc.cp_table_gpu_addr >> 8, 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4c1e)), (adev->gfx.rlc.cp_table_gpu_addr >> 8), 0)) |
2864 | adev->gfx.rlc.cp_table_gpu_addr >> 8)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c1e), adev->gfx.rlc.cp_table_gpu_addr >> 8, 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][1] + 0x4c1e)), (adev->gfx.rlc.cp_table_gpu_addr >> 8), 0)); |
2865 | gfx_v9_0_init_gfx_power_gating(adev); |
2866 | } |
2867 | } |
2868 | |
2869 | static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) |
2870 | { |
2871 | WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c00, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c00), 0)) & ~0x00000001L) | (0) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][1] + 0x4c00), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][1] + 0x4c00, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [1] + 0x4c00), 0)) & ~0x00000001L) | (0) << 0x0), 0 )); |
2872 | gfx_v9_0_enable_gui_idle_interrupt(adev, false0); |
2873 | gfx_v9_0_wait_for_rlc_serdes(adev); |
2874 | } |
2875 | |
2876 | static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) |
2877 | { |
2878 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0008), 0)) & ~0x00000004L) | (1) << 0x2, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][0] + 0x0008), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][0] + 0x0008, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [0] + 0x0008), 0)) & ~0x00000004L) | (1) << 0x2), 0 )); |
2879 | udelay(50); |
2880 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0008), 0)) & ~0x00000004L) | (0) << 0x2, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][0] + 0x0008), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][0] + 0x0008, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [0] + 0x0008), 0)) & ~0x00000004L) | (0) << 0x2), 0 )); |
2881 | udelay(50); |
2882 | } |
2883 | |
2884 | static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) |
2885 | { |
2886 | #ifdef AMDGPU_RLC_DEBUG_RETRY |
2887 | u32 rlc_ucode_ver; |
2888 | #endif |
2889 | |
2890 | WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c00, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c00), 0)) & ~0x00000001L) | (1) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][1] + 0x4c00), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][1] + 0x4c00, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [1] + 0x4c00), 0)) & ~0x00000001L) | (1) << 0x0), 0 )); |
2891 | udelay(50); |
2892 | |
2893 | /* carrizo do enable cp interrupt after cp inited */ |
2894 | if (!(adev->flags & AMD_IS_APU)) { |
2895 | gfx_v9_0_enable_gui_idle_interrupt(adev, true1); |
2896 | udelay(50); |
2897 | } |
2898 | |
2899 | #ifdef AMDGPU_RLC_DEBUG_RETRY |
2900 | /* RLC_GPM_GENERAL_6 : RLC Ucode version */ |
2901 | rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c69, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c69), 0)); |
2902 | if(rlc_ucode_ver == 0x108) { |
2903 | DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",printk("\0016" "[" "drm" "] " "Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n" , rlc_ucode_ver, adev->gfx.rlc_fw_version) |
2904 | rlc_ucode_ver, adev->gfx.rlc_fw_version)printk("\0016" "[" "drm" "] " "Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n" , rlc_ucode_ver, adev->gfx.rlc_fw_version); |
2905 | /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, |
2906 | * default is 0x9C4 to create a 100us interval */ |
2907 | WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c15), 0x9C4, 0, GC_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[GC_HWIP][0][1] + 0x4c15)), (0x9C4), 0)); |
2908 | /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr |
2909 | * to disable the page fault retry interrupts, default is |
2910 | * 0x100 (256) */ |
2911 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4cb1), 0x100, 0, GC_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[GC_HWIP][0][1] + 0x4cb1)), (0x100), 0)); |
2912 | } |
2913 | #endif |
2914 | } |
2915 | |
2916 | static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) |
2917 | { |
2918 | const struct rlc_firmware_header_v2_0 *hdr; |
2919 | const __le32 *fw_data; |
2920 | unsigned i, fw_size; |
2921 | |
2922 | if (!adev->gfx.rlc_fw) |
2923 | return -EINVAL22; |
2924 | |
2925 | hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
2926 | amdgpu_ucode_print_rlc_hdr(&hdr->header); |
2927 | |
2928 | fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + |
2929 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes))); |
2930 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4; |
2931 | |
2932 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x583c), 0x00002000L, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x583c)), (0x00002000L ), 0)) |
2933 | RLCG_UCODE_LOADING_START_ADDRESS)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x583c), 0x00002000L, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][1] + 0x583c)), (0x00002000L ), 0)); |
2934 | for (i = 0; i < fw_size; i++) |
2935 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x583d), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0 ][1] + 0x583d)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))) , 0)); |
2936 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x583c), adev->gfx.rlc_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x583c)), (adev ->gfx.rlc_fw_version), 0)); |
2937 | |
2938 | return 0; |
2939 | } |
2940 | |
2941 | static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) |
2942 | { |
2943 | int r; |
2944 | |
2945 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
2946 | gfx_v9_0_init_csb(adev); |
2947 | return 0; |
2948 | } |
2949 | |
2950 | adev->gfx.rlc.funcs->stop(adev); |
2951 | |
2952 | /* disable CG */ |
2953 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c49), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x4c49)), (0), 0)); |
2954 | |
2955 | gfx_v9_0_init_pg(adev); |
2956 | |
2957 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
2958 | /* legacy rlc firmware loading */ |
2959 | r = gfx_v9_0_rlc_load_microcode(adev); |
2960 | if (r) |
2961 | return r; |
2962 | } |
2963 | |
2964 | switch (adev->ip_versions[GC_HWIP][0]) { |
2965 | case IP_VERSION(9, 2, 2)(((9) << 16) | ((2) << 8) | (2)): |
2966 | case IP_VERSION(9, 1, 0)(((9) << 16) | ((1) << 8) | (0)): |
2967 | if (amdgpu_lbpw == 0) |
2968 | gfx_v9_0_enable_lbpw(adev, false0); |
2969 | else |
2970 | gfx_v9_0_enable_lbpw(adev, true1); |
2971 | break; |
2972 | case IP_VERSION(9, 4, 0)(((9) << 16) | ((4) << 8) | (0)): |
2973 | if (amdgpu_lbpw > 0) |
2974 | gfx_v9_0_enable_lbpw(adev, true1); |
2975 | else |
2976 | gfx_v9_0_enable_lbpw(adev, false0); |
2977 | break; |
2978 | default: |
2979 | break; |
2980 | } |
2981 | |
2982 | adev->gfx.rlc.funcs->start(adev); |
2983 | |
2984 | return 0; |
2985 | } |
2986 | |
2987 | static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool_Bool enable) |
2988 | { |
2989 | u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x01b6, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x01b6), 0)); |
2990 | |
2991 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((enable ? 0 : 1) << 0x1c))); |
2992 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1)(((tmp) & ~0x04000000L) | (0x04000000L & ((enable ? 0 : 1) << 0x1a))); |
2993 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((enable ? 0 : 1) << 0x18))); |
2994 | WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x01b6; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
2995 | udelay(50); |
2996 | } |
2997 | |
2998 | static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) |
2999 | { |
3000 | const struct gfx_firmware_header_v1_0 *pfp_hdr; |
3001 | const struct gfx_firmware_header_v1_0 *ce_hdr; |
3002 | const struct gfx_firmware_header_v1_0 *me_hdr; |
3003 | const __le32 *fw_data; |
3004 | unsigned i, fw_size; |
3005 | |
3006 | if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) |
3007 | return -EINVAL22; |
3008 | |
3009 | pfp_hdr = (const struct gfx_firmware_header_v1_0 *) |
3010 | adev->gfx.pfp_fw->data; |
3011 | ce_hdr = (const struct gfx_firmware_header_v1_0 *) |
3012 | adev->gfx.ce_fw->data; |
3013 | me_hdr = (const struct gfx_firmware_header_v1_0 *) |
3014 | adev->gfx.me_fw->data; |
3015 | |
3016 | amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); |
3017 | amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); |
3018 | amdgpu_ucode_print_gfx_hdr(&me_hdr->header); |
3019 | |
3020 | gfx_v9_0_cp_gfx_enable(adev, false0); |
3021 | |
3022 | /* PFP */ |
3023 | fw_data = (const __le32 *) |
3024 | (adev->gfx.pfp_fw->data + |
3025 | le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(pfp_hdr->header.ucode_array_offset_bytes))); |
3026 | fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes)((__uint32_t)(pfp_hdr->header.ucode_size_bytes)) / 4; |
3027 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5814), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x5814)), (0), 0)); |
3028 | for (i = 0; i < fw_size; i++) |
3029 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5815), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0 ][1] + 0x5815)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))) , 0)); |
3030 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5814), adev->gfx.pfp_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5814)), (adev ->gfx.pfp_fw_version), 0)); |
3031 | |
3032 | /* CE */ |
3033 | fw_data = (const __le32 *) |
3034 | (adev->gfx.ce_fw->data + |
3035 | le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ce_hdr->header.ucode_array_offset_bytes))); |
3036 | fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes)((__uint32_t)(ce_hdr->header.ucode_size_bytes)) / 4; |
3037 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5818), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x5818)), (0), 0)); |
3038 | for (i = 0; i < fw_size; i++) |
3039 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5819), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0 ][1] + 0x5819)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))) , 0)); |
3040 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5818), adev->gfx.ce_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5818)), (adev ->gfx.ce_fw_version), 0)); |
3041 | |
3042 | /* ME */ |
3043 | fw_data = (const __le32 *) |
3044 | (adev->gfx.me_fw->data + |
3045 | le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)((__uint32_t)(me_hdr->header.ucode_array_offset_bytes))); |
3046 | fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes)((__uint32_t)(me_hdr->header.ucode_size_bytes)) / 4; |
3047 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5816), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x5816)), (0), 0)); |
3048 | for (i = 0; i < fw_size; i++) |
3049 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5817), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0 ][1] + 0x5817)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))) , 0)); |
3050 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x5816), adev->gfx.me_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5816)), (adev ->gfx.me_fw_version), 0)); |
3051 | |
3052 | return 0; |
3053 | } |
3054 | |
3055 | static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) |
3056 | { |
3057 | struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; |
3058 | const struct cs_section_def *sect = NULL((void *)0); |
3059 | const struct cs_extent_def *ext = NULL((void *)0); |
3060 | int r, i, tmp; |
3061 | |
3062 | /* init the CP */ |
3063 | WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10ae), adev->gfx.config.max_hw_contexts - 1, 0, GC_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0 ][0] + 0x10ae)), (adev->gfx.config.max_hw_contexts - 1), 0 )); |
3064 | WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x104b), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x104b)), (1), 0)); |
3065 | |
3066 | gfx_v9_0_cp_gfx_enable(adev, true1); |
3067 | |
3068 | r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); |
3069 | if (r) { |
3070 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r); |
3071 | return r; |
3072 | } |
3073 | |
3074 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
3075 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28)); |
3076 | |
3077 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) & 0x3FFF) << 16)); |
3078 | amdgpu_ring_write(ring, 0x80000000); |
3079 | amdgpu_ring_write(ring, 0x80000000); |
3080 | |
3081 | for (sect = gfx9_cs_data; sect->section != NULL((void *)0); ++sect) { |
3082 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
3083 | if (sect->id == SECT_CONTEXT) { |
3084 | amdgpu_ring_write(ring, |
3085 | PACKET3(PACKET3_SET_CONTEXT_REG,((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext-> reg_count) & 0x3FFF) << 16) |
3086 | ext->reg_count)((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext-> reg_count) & 0x3FFF) << 16)); |
3087 | amdgpu_ring_write(ring, |
3088 | ext->reg_index - PACKET3_SET_CONTEXT_REG_START0x0000a000); |
3089 | for (i = 0; i < ext->reg_count; i++) |
3090 | amdgpu_ring_write(ring, ext->extent[i]); |
3091 | } |
3092 | } |
3093 | } |
3094 | |
3095 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
3096 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28)); |
3097 | |
3098 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
3099 | amdgpu_ring_write(ring, 0); |
3100 | |
3101 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)((3 << 30) | (((0x11) & 0xFF) << 8) | ((2) & 0x3FFF) << 16)); |
3102 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)((3) << 0)); |
3103 | amdgpu_ring_write(ring, 0x8000); |
3104 | amdgpu_ring_write(ring, 0x8000); |
3105 | |
3106 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) & 0x3FFF) << 16)); |
3107 | tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE(2 << 28) | |
3108 | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE)(adev->reg_offset[GC_HWIP][0][1] + 0x2243) - PACKET3_SET_UCONFIG_REG_START0x0000c000)); |
3109 | amdgpu_ring_write(ring, tmp); |
3110 | amdgpu_ring_write(ring, 0); |
3111 | |
3112 | amdgpu_ring_commit(ring); |
3113 | |
3114 | return 0; |
3115 | } |
3116 | |
3117 | static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) |
3118 | { |
3119 | struct amdgpu_ring *ring; |
3120 | u32 tmp; |
3121 | u32 rb_bufsz; |
3122 | u64 rb_addr, rptr_addr, wptr_gpu_addr; |
3123 | |
3124 | /* Set the write pointer delay */ |
3125 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x01c1), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x01c1)), (0), 0)); |
3126 | |
3127 | /* set the RB to use vmid 0 */ |
3128 | WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1051), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x1051)), (0), 0)); |
3129 | |
3130 | /* Set ring buffer size */ |
3131 | ring = &adev->gfx.gfx_ring[0]; |
3132 | rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8); |
3133 | tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) << 0x0))); |
3134 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz - 2) << 0x8))); |
3135 | #ifdef __BIG_ENDIAN |
3136 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00060000L) | (0x00060000L & ((1) << 0x11))); |
3137 | #endif |
3138 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1041), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x1041)), (tmp), 0)); |
3139 | |
3140 | /* Initialize the ring buffer's write pointers */ |
3141 | ring->wptr = 0; |
3142 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1054), ((u32)(ring->wptr)), 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1054)), (((u32 )(ring->wptr))), 0)); |
3143 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1055), ((u32)(((ring->wptr) >> 16) >> 16 )), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x1055)), (((u32)(((ring->wptr) >> 16) >> 16))), 0)); |
3144 | |
3145 | /* set the wb address wether it's enabled or not */ |
3146 | rptr_addr = ring->rptr_gpu_addr; |
3147 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1043), ((u32)(rptr_addr)), 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1043)), (((u32 )(rptr_addr))), 0)); |
3148 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1044), ((u32)(((rptr_addr) >> 16) >> 16)) & 0x0000FFFFL, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev-> reg_offset[GC_HWIP][0][0] + 0x1044)), (((u32)(((rptr_addr) >> 16) >> 16)) & 0x0000FFFFL), 0)); |
3149 | |
3150 | wptr_gpu_addr = ring->wptr_gpu_addr; |
3151 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1046), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1046)), (((u32 )(wptr_gpu_addr))), 0)); |
3152 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1047), ((u32)(((wptr_gpu_addr) >> 16) >> 16 )), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x1047)), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0)); |
3153 | |
3154 | mdelay(1); |
3155 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1041), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x1041)), (tmp), 0)); |
3156 | |
3157 | rb_addr = ring->gpu_addr >> 8; |
3158 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1040), rb_addr, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1040)), (rb_addr), 0 )); |
3159 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10b1), ((u32)(((rb_addr) >> 16) >> 16)), 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][0] + 0x10b1)), (((u32)(((rb_addr) >> 16) >> 16 ))), 0)); |
3160 | |
3161 | tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1059, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1059), 0)); |
3162 | if (ring->use_doorbell) { |
3163 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))) |
3164 | DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))); |
3165 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e))) |
3166 | DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e))); |
3167 | } else { |
3168 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) << 0x1e))); |
3169 | } |
3170 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1059), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x1059)), (tmp), 0)); |
3171 | |
3172 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))) |
3173 | DOORBELL_RANGE_LOWER, ring->doorbell_index)(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))); |
3174 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105a), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x105a)), (tmp), 0)); |
3175 | |
3176 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105b), 0x0FFFFFFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x105b)), (0x0FFFFFFCL ), 0)) |
3177 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105b), 0x0FFFFFFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x105b)), (0x0FFFFFFCL ), 0)); |
3178 | |
3179 | |
3180 | /* start the ring */ |
3181 | gfx_v9_0_cp_gfx_start(adev); |
3182 | ring->sched.ready = true1; |
3183 | |
3184 | return 0; |
3185 | } |
3186 | |
3187 | static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool_Bool enable) |
3188 | { |
3189 | if (enable) { |
3190 | WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x008d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3191 | } else { |
3192 | WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x008d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (0x40000000L | 0x10000000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((0x40000000L | 0x10000000L)), 0)); } while (0) |
3193 | (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK))do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x008d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, (0x40000000L | 0x10000000L ), (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), ((0x40000000L | 0x10000000L)), 0)); } while (0); |
3194 | adev->gfx.kiq.ring.sched.ready = false0; |
3195 | } |
3196 | udelay(50); |
3197 | } |
3198 | |
3199 | static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) |
3200 | { |
3201 | const struct gfx_firmware_header_v1_0 *mec_hdr; |
3202 | const __le32 *fw_data; |
3203 | unsigned i; |
3204 | u32 tmp; |
3205 | |
3206 | if (!adev->gfx.mec_fw) |
3207 | return -EINVAL22; |
3208 | |
3209 | gfx_v9_0_cp_compute_enable(adev, false0); |
3210 | |
3211 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
3212 | amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); |
3213 | |
3214 | fw_data = (const __le32 *) |
3215 | (adev->gfx.mec_fw->data + |
3216 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes))); |
3217 | tmp = 0; |
3218 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) << 0x0))); |
3219 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x01000000L) | (0x01000000L & ((0) << 0x18))); |
3220 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10bb), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x10bb)), (tmp), 0)); |
3221 | |
3222 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10b9), adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000 , 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x10b9)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000), 0)) |
3223 | adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10b9), adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000 , 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x10b9)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000), 0)); |
3224 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10ba), ((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][0] + 0x10ba)), (((u32)(((adev ->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16))), 0) ) |
3225 | upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x10ba), ((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][0] + 0x10ba)), (((u32)(((adev ->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16))), 0) ); |
3226 | |
3227 | /* MEC1 */ |
3228 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581a), mec_hdr->jt_offset, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581a)), (mec_hdr ->jt_offset), 0)) |
3229 | mec_hdr->jt_offset)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581a), mec_hdr->jt_offset, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581a)), (mec_hdr ->jt_offset), 0)); |
3230 | for (i = 0; i < mec_hdr->jt_size; i++) |
3231 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581b), ((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr ->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581b)), (((__uint32_t )(*(__uint32_t *)(fw_data + mec_hdr->jt_offset + i)))), 0) ) |
3232 | le32_to_cpup(fw_data + mec_hdr->jt_offset + i))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581b), ((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr ->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581b)), (((__uint32_t )(*(__uint32_t *)(fw_data + mec_hdr->jt_offset + i)))), 0) ); |
3233 | |
3234 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581a), adev->gfx.mec_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581a)), (adev ->gfx.mec_fw_version), 0)) |
3235 | adev->gfx.mec_fw_version)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x581a), adev->gfx.mec_fw_version, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581a)), (adev ->gfx.mec_fw_version), 0)); |
3236 | /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ |
3237 | |
3238 | return 0; |
3239 | } |
3240 | |
3241 | /* KIQ functions */ |
3242 | static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) |
3243 | { |
3244 | uint32_t tmp; |
3245 | struct amdgpu_device *adev = ring->adev; |
3246 | |
3247 | /* tell RLC which is KIQ queue */ |
3248 | tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4caa, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4caa), 0)); |
3249 | tmp &= 0xffffff00; |
3250 | tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); |
3251 | WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1] + 0x4caa; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
3252 | tmp |= 0x80; |
3253 | WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1] + 0x4caa; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while (0); |
3254 | } |
3255 | |
3256 | static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) |
3257 | { |
3258 | struct amdgpu_device *adev = ring->adev; |
3259 | |
3260 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { |
3261 | if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { |
3262 | mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; |
3263 | mqd->cp_hqd_queue_priority = |
3264 | AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM15; |
3265 | } |
3266 | } |
3267 | } |
3268 | |
3269 | static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) |
3270 | { |
3271 | struct amdgpu_device *adev = ring->adev; |
3272 | struct v9_mqd *mqd = ring->mqd_ptr; |
3273 | uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; |
3274 | uint32_t tmp; |
3275 | |
3276 | mqd->header = 0xC0310800; |
3277 | mqd->compute_pipelinestat_enable = 0x00000001; |
3278 | mqd->compute_static_thread_mgmt_se0 = 0xffffffff; |
3279 | mqd->compute_static_thread_mgmt_se1 = 0xffffffff; |
3280 | mqd->compute_static_thread_mgmt_se2 = 0xffffffff; |
3281 | mqd->compute_static_thread_mgmt_se3 = 0xffffffff; |
3282 | mqd->compute_static_thread_mgmt_se4 = 0xffffffff; |
3283 | mqd->compute_static_thread_mgmt_se5 = 0xffffffff; |
3284 | mqd->compute_static_thread_mgmt_se6 = 0xffffffff; |
3285 | mqd->compute_static_thread_mgmt_se7 = 0xffffffff; |
3286 | mqd->compute_misc_reserved = 0x00000003; |
3287 | |
3288 | mqd->dynamic_cu_mask_addr_lo = |
3289 | lower_32_bits(ring->mqd_gpu_addr((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation , dynamic_cu_mask))) |
3290 | + offsetof(struct v9_mqd_allocation, dynamic_cu_mask))((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation , dynamic_cu_mask))); |
3291 | mqd->dynamic_cu_mask_addr_hi = |
3292 | upper_32_bits(ring->mqd_gpu_addr((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation , dynamic_cu_mask)) >> 16) >> 16)) |
3293 | + offsetof(struct v9_mqd_allocation, dynamic_cu_mask))((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct v9_mqd_allocation , dynamic_cu_mask)) >> 16) >> 16)); |
3294 | |
3295 | eop_base_addr = ring->eop_gpu_addr >> 8; |
3296 | mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; |
3297 | mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr)((u32)(((eop_base_addr) >> 16) >> 16)); |
3298 | |
3299 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
3300 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x126c, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x126c), 0)); |
3301 | tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order (4096 / 4) - 1)) << 0x0))) |
3302 | (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order (4096 / 4) - 1)) << 0x0))); |
3303 | |
3304 | mqd->cp_hqd_eop_control = tmp; |
3305 | |
3306 | /* enable doorbell? */ |
3307 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1254, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1254), 0)); |
3308 | |
3309 | if (ring->use_doorbell) { |
3310 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))) |
3311 | DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index ) << 0x2))); |
3312 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e))) |
3313 | DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e))); |
3314 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) << 0x1c))) |
3315 | DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) << 0x1c))); |
3316 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) << 0x1f))) |
3317 | DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) << 0x1f))); |
3318 | } else { |
3319 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) << 0x1e))) |
3320 | DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) << 0x1e))); |
3321 | } |
3322 | |
3323 | mqd->cp_hqd_pq_doorbell_control = tmp; |
3324 | |
3325 | /* disable the queue if it's active */ |
3326 | ring->wptr = 0; |
3327 | mqd->cp_hqd_dequeue_request = 0; |
3328 | mqd->cp_hqd_pq_rptr = 0; |
3329 | mqd->cp_hqd_pq_wptr_lo = 0; |
3330 | mqd->cp_hqd_pq_wptr_hi = 0; |
3331 | |
3332 | /* set the pointer to the MQD */ |
3333 | mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; |
3334 | mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr)((u32)(((ring->mqd_gpu_addr) >> 16) >> 16)); |
3335 | |
3336 | /* set MQD vmid to 0 */ |
3337 | tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1267, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1267), 0)); |
3338 | tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) << 0x0))); |
3339 | mqd->cp_mqd_control = tmp; |
3340 | |
3341 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
3342 | hqd_gpu_addr = ring->gpu_addr >> 8; |
3343 | mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; |
3344 | mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16)); |
3345 | |
3346 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
3347 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1256, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1256), 0)); |
3348 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order (ring->ring_size / 4) - 1)) << 0x0))) |
3349 | (order_base_2(ring->ring_size / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order (ring->ring_size / 4) - 1)) << 0x0))); |
3350 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,(((tmp) & ~0x00003F00L) | (0x00003F00L & (((drm_order (4096 / 4) - 1)) << 0x8))) |
3351 | (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1))(((tmp) & ~0x00003F00L) | (0x00003F00L & (((drm_order (4096 / 4) - 1)) << 0x8))); |
3352 | #ifdef __BIG_ENDIAN |
3353 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1)(((tmp) & ~0x00060000L) | (0x00060000L & ((1) << 0x11))); |
3354 | #endif |
3355 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) << 0x1c))); |
3356 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) << 0x1d))); |
3357 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e))); |
3358 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1)(((tmp) & ~0x80000000L) | (0x80000000L & ((1) << 0x1f))); |
3359 | mqd->cp_hqd_pq_control = tmp; |
3360 | |
3361 | /* set the wb address whether it's enabled or not */ |
3362 | wb_gpu_addr = ring->rptr_gpu_addr; |
3363 | mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; |
3364 | mqd->cp_hqd_pq_rptr_report_addr_hi = |
3365 | upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff; |
3366 | |
3367 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
3368 | wb_gpu_addr = ring->wptr_gpu_addr; |
3369 | mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; |
3370 | mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff; |
3371 | |
3372 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
3373 | ring->wptr = 0; |
3374 | mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x124f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x124f), 0)); |
3375 | |
3376 | /* set the vmid for the queue */ |
3377 | mqd->cp_hqd_vmid = 0; |
3378 | |
3379 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1249, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1249), 0)); |
3380 | tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53)(((tmp) & ~0x0003FF00L) | (0x0003FF00L & ((0x53) << 0x8))); |
3381 | mqd->cp_hqd_persistent_state = tmp; |
3382 | |
3383 | /* set MIN_IB_AVAIL_SIZE */ |
3384 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x125a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x125a), 0)); |
3385 | tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3)(((tmp) & ~0x00300000L) | (0x00300000L & ((3) << 0x14))); |
3386 | mqd->cp_hqd_ib_control = tmp; |
3387 | |
3388 | /* set static priority for a queue/ring */ |
3389 | gfx_v9_0_mqd_set_priority(ring, mqd); |
3390 | mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x124c, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x124c), 0)); |
3391 | |
3392 | /* map_queues packet doesn't need activate the queue, |
3393 | * so only kiq need set this field. |
3394 | */ |
3395 | if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) |
3396 | mqd->cp_hqd_active = 1; |
3397 | |
3398 | return 0; |
3399 | } |
3400 | |
3401 | static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) |
3402 | { |
3403 | struct amdgpu_device *adev = ring->adev; |
3404 | struct v9_mqd *mqd = ring->mqd_ptr; |
3405 | int j; |
3406 | |
3407 | /* disable wptr polling */ |
3408 | WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1083, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1083, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1083), 0)) & ~0x80000000L) | (0) << 0x1f, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][0] + 0x1083), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][0] + 0x1083, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [0] + 0x1083), 0)) & ~0x80000000L) | (0) << 0x1f), 0 )); |
3409 | |
3410 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_base_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_base_addr_lo), 0)); } while (0) |
3411 | mqd->cp_hqd_eop_base_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_base_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_base_addr_lo), 0)); } while (0); |
3412 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_base_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_base_addr_hi), 0)); } while (0) |
3413 | mqd->cp_hqd_eop_base_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_base_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_base_addr_hi), 0)); } while (0); |
3414 | |
3415 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
3416 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_control), 0)); } while (0) |
3417 | mqd->cp_hqd_eop_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x126c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_eop_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_eop_control), 0)); } while (0); |
3418 | |
3419 | /* enable doorbell? */ |
3420 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_doorbell_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_doorbell_control), 0)); } while (0) |
3421 | mqd->cp_hqd_pq_doorbell_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_doorbell_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_doorbell_control), 0)); } while (0); |
3422 | |
3423 | /* disable the queue if it's active */ |
3424 | if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1247, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1247), 0)) & 1) { |
3425 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 1, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (1), 0)); } while ( 0); |
3426 | for (j = 0; j < adev->usec_timeout; j++) { |
3427 | if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1247, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1247), 0)) & 1)) |
3428 | break; |
3429 | udelay(1); |
3430 | } |
3431 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_dequeue_request , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_dequeue_request), 0)); } while (0) |
3432 | mqd->cp_hqd_dequeue_request)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_dequeue_request , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_dequeue_request), 0)); } while (0); |
3433 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124f; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr), 0)); } while (0) |
3434 | mqd->cp_hqd_pq_rptr)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124f; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr), 0)); } while (0); |
3435 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_lo), 0)); } while (0) |
3436 | mqd->cp_hqd_pq_wptr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_lo), 0)); } while (0); |
3437 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_hi), 0)); } while (0) |
3438 | mqd->cp_hqd_pq_wptr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_hi), 0)); } while (0); |
3439 | } |
3440 | |
3441 | /* set the pointer to the MQD */ |
3442 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1245; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_base_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_base_addr_lo), 0)); } while (0) |
3443 | mqd->cp_mqd_base_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1245; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_base_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_base_addr_lo), 0)); } while (0); |
3444 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1246; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_base_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_base_addr_hi), 0)); } while (0) |
3445 | mqd->cp_mqd_base_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1246; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_base_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_base_addr_hi), 0)); } while (0); |
3446 | |
3447 | /* set MQD vmid to 0 */ |
3448 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1267; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_control), 0)); } while (0) |
3449 | mqd->cp_mqd_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1267; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_mqd_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_mqd_control), 0)); } while (0); |
3450 | |
3451 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
3452 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_base_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_base_lo), 0)); } while (0) |
3453 | mqd->cp_hqd_pq_base_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_base_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_base_lo), 0)); } while (0); |
3454 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124e; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_base_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_base_hi), 0)); } while (0) |
3455 | mqd->cp_hqd_pq_base_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124e; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_base_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_base_hi), 0)); } while (0); |
3456 | |
3457 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
3458 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1256; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_control), 0)); } while (0) |
3459 | mqd->cp_hqd_pq_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1256; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_control), 0)); } while (0); |
3460 | |
3461 | /* set the wb address whether it's enabled or not */ |
3462 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1250; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr_report_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0)); } while (0) |
3463 | mqd->cp_hqd_pq_rptr_report_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1250; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr_report_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0)); } while (0); |
3464 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1251; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr_report_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0)); } while (0) |
3465 | mqd->cp_hqd_pq_rptr_report_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1251; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_rptr_report_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0)); } while (0); |
3466 | |
3467 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
3468 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1252; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_poll_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0)); } while (0) |
3469 | mqd->cp_hqd_pq_wptr_poll_addr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1252; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_poll_addr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0)); } while (0); |
3470 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1253; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_poll_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0)); } while (0) |
3471 | mqd->cp_hqd_pq_wptr_poll_addr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1253; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_poll_addr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0)); } while (0); |
3472 | |
3473 | /* enable the doorbell if requested */ |
3474 | if (ring->use_doorbell) { |
3475 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105c), (adev->doorbell_index.kiq * 2) << 2, 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][0] + 0x105c)), ((adev->doorbell_index.kiq * 2) << 2), 0)) |
3476 | (adev->doorbell_index.kiq * 2) << 2)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105c), (adev->doorbell_index.kiq * 2) << 2, 0 , GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP ][0][0] + 0x105c)), ((adev->doorbell_index.kiq * 2) << 2), 0)); |
3477 | /* If GC has entered CGPG, ringing doorbell > first page |
3478 | * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to |
3479 | * workaround this issue. And this change has to align with firmware |
3480 | * update. |
3481 | */ |
3482 | if (check_if_enlarge_doorbell_range(adev)) |
3483 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105d), (adev->doorbell.size - 4), 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x105d)), ((adev ->doorbell.size - 4)), 0)) |
3484 | (adev->doorbell.size - 4))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105d), (adev->doorbell.size - 4), 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x105d)), ((adev ->doorbell.size - 4)), 0)); |
3485 | else |
3486 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105d), (adev->doorbell_index.userqueue_end * 2) << 2, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x105d)), ((adev->doorbell_index.userqueue_end * 2) << 2), 0)) |
3487 | (adev->doorbell_index.userqueue_end * 2) << 2)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x105d), (adev->doorbell_index.userqueue_end * 2) << 2, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [GC_HWIP][0][0] + 0x105d)), ((adev->doorbell_index.userqueue_end * 2) << 2), 0)); |
3488 | } |
3489 | |
3490 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_doorbell_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_doorbell_control), 0)); } while (0) |
3491 | mqd->cp_hqd_pq_doorbell_control)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_doorbell_control , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_doorbell_control), 0)); } while (0); |
3492 | |
3493 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
3494 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_lo), 0)); } while (0) |
3495 | mqd->cp_hqd_pq_wptr_lo)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_lo , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_lo), 0)); } while (0); |
3496 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_hi), 0)); } while (0) |
3497 | mqd->cp_hqd_pq_wptr_hi)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_pq_wptr_hi , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_pq_wptr_hi), 0)); } while (0); |
3498 | |
3499 | /* set the vmid for the queue */ |
3500 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1248; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_vmid, ( 1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg) , (mqd->cp_hqd_vmid), 0)); } while (0); |
3501 | |
3502 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1249; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_persistent_state , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_persistent_state), 0)); } while (0) |
3503 | mqd->cp_hqd_persistent_state)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1249; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_persistent_state , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_persistent_state), 0)); } while (0); |
3504 | |
3505 | /* activate the queue */ |
3506 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1247; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_active , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_active), 0)); } while (0) |
3507 | mqd->cp_hqd_active)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1247; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, mqd->cp_hqd_active , (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg ), (mqd->cp_hqd_active), 0)); } while (0); |
3508 | |
3509 | if (ring->use_doorbell) |
3510 | WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x10b8, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x10b8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x10b8), 0)) & ~0x00000002L) | (1) << 0x1, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][0] + 0x10b8), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][0] + 0x10b8, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [0] + 0x10b8), 0)) & ~0x00000002L) | (1) << 0x1), 0 )); |
3511 | |
3512 | return 0; |
3513 | } |
3514 | |
3515 | static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) |
3516 | { |
3517 | struct amdgpu_device *adev = ring->adev; |
3518 | int j; |
3519 | |
3520 | /* disable the queue if it's active */ |
3521 | if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1247, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1247), 0)) & 1) { |
3522 | |
3523 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 1, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (1), 0)); } while ( 0); |
3524 | |
3525 | for (j = 0; j < adev->usec_timeout; j++) { |
3526 | if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1247, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1247), 0)) & 1)) |
3527 | break; |
3528 | udelay(1); |
3529 | } |
3530 | |
3531 | if (j == AMDGPU_MAX_USEC_TIMEOUT100000) { |
3532 | DRM_DEBUG("KIQ dequeue request failed.\n")___drm_dbg(((void *)0), DRM_UT_CORE, "KIQ dequeue request failed.\n" ); |
3533 | |
3534 | /* Manual disable if dequeue request times out */ |
3535 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1247; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3536 | } |
3537 | |
3538 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0) |
3539 | 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125d; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3540 | } |
3541 | |
3542 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3543 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x125a; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3544 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1249; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3545 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0x40000000, (1<< 2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg), (0x40000000 ), 0)); } while (0); |
3546 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x1254; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3547 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x124f; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3548 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127c; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3549 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0] + 0x127b; ((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, target_reg, 0, (1<<2), GC_HWIP ) : amdgpu_device_wreg(adev, (target_reg), (0), 0)); } while ( 0); |
3550 | |
3551 | return 0; |
3552 | } |
3553 | |
3554 | static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) |
3555 | { |
3556 | struct amdgpu_device *adev = ring->adev; |
3557 | struct v9_mqd *mqd = ring->mqd_ptr; |
3558 | int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS8; |
3559 | struct v9_mqd *tmp_mqd; |
3560 | |
3561 | gfx_v9_0_kiq_setting(ring); |
3562 | |
3563 | /* GPU could be in bad state during probe, driver trigger the reset |
3564 | * after load the SMU, in this case , the mqd is not be initialized. |
3565 | * driver need to re-init the mqd. |
3566 | * check mqd->cp_hqd_pq_control since this value should not be 0 |
3567 | */ |
3568 | tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; |
3569 | if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ |
3570 | /* for GPU_RESET case , reset MQD to a clean status */ |
3571 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
3572 | memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx] ), (sizeof(struct v9_mqd_allocation))); |
3573 | |
3574 | /* reset ring buffer */ |
3575 | ring->wptr = 0; |
3576 | amdgpu_ring_clear_ring(ring); |
3577 | |
3578 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3579 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
3580 | gfx_v9_0_kiq_init_register(ring); |
3581 | soc15_grbm_select(adev, 0, 0, 0, 0); |
3582 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3583 | } else { |
3584 | memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct v9_mqd_allocation ))); |
3585 | ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; |
3586 | ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; |
3587 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3588 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
3589 | gfx_v9_0_mqd_init(ring); |
3590 | gfx_v9_0_kiq_init_register(ring); |
3591 | soc15_grbm_select(adev, 0, 0, 0, 0); |
3592 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3593 | |
3594 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
3595 | memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd ), (sizeof(struct v9_mqd_allocation))); |
3596 | } |
3597 | |
3598 | return 0; |
3599 | } |
3600 | |
3601 | static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) |
3602 | { |
3603 | struct amdgpu_device *adev = ring->adev; |
3604 | struct v9_mqd *mqd = ring->mqd_ptr; |
3605 | int mqd_idx = ring - &adev->gfx.compute_ring[0]; |
3606 | struct v9_mqd *tmp_mqd; |
3607 | |
3608 | /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control |
3609 | * is not be initialized before |
3610 | */ |
3611 | tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; |
3612 | |
3613 | if (!tmp_mqd->cp_hqd_pq_control || |
3614 | (!amdgpu_in_reset(adev) && !adev->in_suspend)) { |
3615 | memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct v9_mqd_allocation ))); |
3616 | ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; |
3617 | ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; |
3618 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3619 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
3620 | gfx_v9_0_mqd_init(ring); |
3621 | soc15_grbm_select(adev, 0, 0, 0, 0); |
3622 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3623 | |
3624 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
3625 | memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd ), (sizeof(struct v9_mqd_allocation))); |
3626 | } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ |
3627 | /* reset MQD to a clean status */ |
3628 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
3629 | memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx] ), (sizeof(struct v9_mqd_allocation))); |
3630 | |
3631 | /* reset ring buffer */ |
3632 | ring->wptr = 0; |
3633 | atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = (( 0)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr )) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp ; }); |
3634 | amdgpu_ring_clear_ring(ring); |
3635 | } else { |
3636 | amdgpu_ring_clear_ring(ring); |
3637 | } |
3638 | |
3639 | return 0; |
3640 | } |
3641 | |
3642 | static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) |
3643 | { |
3644 | struct amdgpu_ring *ring; |
3645 | int r; |
3646 | |
3647 | ring = &adev->gfx.kiq.ring; |
3648 | |
3649 | r = amdgpu_bo_reserve(ring->mqd_obj, false0); |
3650 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
3651 | return r; |
3652 | |
3653 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); |
3654 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) { |
3655 | amdgpu_bo_unreserve(ring->mqd_obj); |
3656 | return r; |
3657 | } |
3658 | |
3659 | gfx_v9_0_kiq_init_queue(ring); |
3660 | amdgpu_bo_kunmap(ring->mqd_obj); |
3661 | ring->mqd_ptr = NULL((void *)0); |
3662 | amdgpu_bo_unreserve(ring->mqd_obj); |
3663 | ring->sched.ready = true1; |
3664 | return 0; |
3665 | } |
3666 | |
3667 | static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) |
3668 | { |
3669 | struct amdgpu_ring *ring = NULL((void *)0); |
3670 | int r = 0, i; |
3671 | |
3672 | gfx_v9_0_cp_compute_enable(adev, true1); |
3673 | |
3674 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
3675 | ring = &adev->gfx.compute_ring[i]; |
3676 | |
3677 | r = amdgpu_bo_reserve(ring->mqd_obj, false0); |
3678 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
3679 | goto done; |
3680 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); |
3681 | if (!r) { |
3682 | r = gfx_v9_0_kcq_init_queue(ring); |
3683 | amdgpu_bo_kunmap(ring->mqd_obj); |
3684 | ring->mqd_ptr = NULL((void *)0); |
3685 | } |
3686 | amdgpu_bo_unreserve(ring->mqd_obj); |
3687 | if (r) |
3688 | goto done; |
3689 | } |
3690 | |
3691 | r = amdgpu_gfx_enable_kcq(adev); |
3692 | done: |
3693 | return r; |
3694 | } |
3695 | |
3696 | static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) |
3697 | { |
3698 | int r, i; |
3699 | struct amdgpu_ring *ring; |
3700 | |
3701 | if (!(adev->flags & AMD_IS_APU)) |
3702 | gfx_v9_0_enable_gui_idle_interrupt(adev, false0); |
3703 | |
3704 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
3705 | if (adev->gfx.num_gfx_rings) { |
3706 | /* legacy firmware loading */ |
3707 | r = gfx_v9_0_cp_gfx_load_microcode(adev); |
3708 | if (r) |
3709 | return r; |
3710 | } |
3711 | |
3712 | r = gfx_v9_0_cp_compute_load_microcode(adev); |
3713 | if (r) |
3714 | return r; |
3715 | } |
3716 | |
3717 | r = gfx_v9_0_kiq_resume(adev); |
3718 | if (r) |
3719 | return r; |
3720 | |
3721 | if (adev->gfx.num_gfx_rings) { |
3722 | r = gfx_v9_0_cp_gfx_resume(adev); |
3723 | if (r) |
3724 | return r; |
3725 | } |
3726 | |
3727 | r = gfx_v9_0_kcq_resume(adev); |
3728 | if (r) |
3729 | return r; |
3730 | |
3731 | if (adev->gfx.num_gfx_rings) { |
3732 | ring = &adev->gfx.gfx_ring[0]; |
3733 | r = amdgpu_ring_test_helper(ring); |
3734 | if (r) |
3735 | return r; |
3736 | } |
3737 | |
3738 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
3739 | ring = &adev->gfx.compute_ring[i]; |
3740 | amdgpu_ring_test_helper(ring); |
3741 | } |
3742 | |
3743 | gfx_v9_0_enable_gui_idle_interrupt(adev, true1); |
3744 | |
3745 | return 0; |
3746 | } |
3747 | |
3748 | static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) |
3749 | { |
3750 | u32 tmp; |
3751 | |
3752 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)) && |
3753 | adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2))) |
3754 | return; |
3755 | |
3756 | tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0b05, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0b05), 0)); |
3757 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,(((tmp) & ~0x00000800L) | (0x00000800L & ((adev->df .hash_status.hash_64k) << 0xb))) |
3758 | adev->df.hash_status.hash_64k)(((tmp) & ~0x00000800L) | (0x00000800L & ((adev->df .hash_status.hash_64k) << 0xb))); |
3759 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,(((tmp) & ~0x00001000L) | (0x00001000L & ((adev->df .hash_status.hash_2m) << 0xc))) |
3760 | adev->df.hash_status.hash_2m)(((tmp) & ~0x00001000L) | (0x00001000L & ((adev->df .hash_status.hash_2m) << 0xc))); |
3761 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,(((tmp) & ~0x00002000L) | (0x00002000L & ((adev->df .hash_status.hash_1g) << 0xd))) |
3762 | adev->df.hash_status.hash_1g)(((tmp) & ~0x00002000L) | (0x00002000L & ((adev->df .hash_status.hash_1g) << 0xd))); |
3763 | WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0b05), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0b05)), (tmp), 0)); |
3764 | } |
3765 | |
3766 | static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool_Bool enable) |
3767 | { |
3768 | if (adev->gfx.num_gfx_rings) |
3769 | gfx_v9_0_cp_gfx_enable(adev, enable); |
3770 | gfx_v9_0_cp_compute_enable(adev, enable); |
3771 | } |
3772 | |
3773 | static int gfx_v9_0_hw_init(void *handle) |
3774 | { |
3775 | int r; |
3776 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3777 | |
3778 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
3779 | gfx_v9_0_init_golden_registers(adev); |
3780 | |
3781 | gfx_v9_0_constants_init(adev); |
3782 | |
3783 | gfx_v9_0_init_tcp_config(adev); |
3784 | |
3785 | r = adev->gfx.rlc.funcs->resume(adev); |
3786 | if (r) |
3787 | return r; |
3788 | |
3789 | r = gfx_v9_0_cp_resume(adev); |
3790 | if (r) |
3791 | return r; |
3792 | |
3793 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2))) |
3794 | gfx_v9_4_2_set_power_brake_sequence(adev); |
3795 | |
3796 | return r; |
3797 | } |
3798 | |
3799 | static int gfx_v9_0_hw_fini(void *handle) |
3800 | { |
3801 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3802 | |
3803 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
3804 | amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); |
3805 | amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); |
3806 | amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); |
3807 | |
3808 | /* DF freeze and kcq disable will fail */ |
3809 | if (!amdgpu_ras_intr_triggered()) |
3810 | /* disable KCQ to avoid CPC touch memory not valid anymore */ |
3811 | amdgpu_gfx_disable_kcq(adev); |
3812 | |
3813 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
3814 | gfx_v9_0_cp_gfx_enable(adev, false0); |
3815 | /* must disable polling for SRIOV when hw finished, otherwise |
3816 | * CPC engine may still keep fetching WB address which is already |
3817 | * invalid after sw finished and trigger DMAR reading error in |
3818 | * hypervisor side. |
3819 | */ |
3820 | WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1083, (((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1083, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1083), 0)) & ~0x80000000L) | (0) << 0x1f, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev ->reg_offset[GC_HWIP][0][0] + 0x1083), ((((((adev)->virt .caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[GC_HWIP][0][0] + 0x1083, 0, GC_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0] [0] + 0x1083), 0)) & ~0x80000000L) | (0) << 0x1f), 0 )); |
3821 | return 0; |
3822 | } |
3823 | |
3824 | /* Use deinitialize sequence from CAIL when unbinding device from driver, |
3825 | * otherwise KIQ is hanging when binding back |
3826 | */ |
3827 | if (!amdgpu_in_reset(adev) && !adev->in_suspend) { |
3828 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3829 | soc15_grbm_select(adev, adev->gfx.kiq.ring.me, |
3830 | adev->gfx.kiq.ring.pipe, |
3831 | adev->gfx.kiq.ring.queue, 0); |
3832 | gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); |
3833 | soc15_grbm_select(adev, 0, 0, 0, 0); |
3834 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3835 | } |
3836 | |
3837 | gfx_v9_0_cp_enable(adev, false0); |
3838 | |
3839 | /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ |
3840 | if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || |
3841 | (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)))) { |
3842 | dev_dbg(adev->dev, "Skipping RLC halt\n")do { } while(0); |
3843 | return 0; |
3844 | } |
3845 | |
3846 | adev->gfx.rlc.funcs->stop(adev); |
3847 | return 0; |
3848 | } |
3849 | |
3850 | static int gfx_v9_0_suspend(void *handle) |
3851 | { |
3852 | return gfx_v9_0_hw_fini(handle); |
3853 | } |
3854 | |
3855 | static int gfx_v9_0_resume(void *handle) |
3856 | { |
3857 | return gfx_v9_0_hw_init(handle); |
3858 | } |
3859 | |
3860 | static bool_Bool gfx_v9_0_is_idle(void *handle) |
3861 | { |
3862 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3863 | |
3864 | if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0004, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0004), 0))) & 0x80000000L) >> 0x1f) |
3865 | GRBM_STATUS, GUI_ACTIVE)(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0004, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0004), 0))) & 0x80000000L) >> 0x1f)) |
3866 | return false0; |
3867 | else |
3868 | return true1; |
3869 | } |
3870 | |
3871 | static int gfx_v9_0_wait_for_idle(void *handle) |
3872 | { |
3873 | unsigned i; |
3874 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3875 | |
3876 | for (i = 0; i < adev->usec_timeout; i++) { |
3877 | if (gfx_v9_0_is_idle(handle)) |
3878 | return 0; |
3879 | udelay(1); |
3880 | } |
3881 | return -ETIMEDOUT60; |
3882 | } |
3883 | |
3884 | static int gfx_v9_0_soft_reset(void *handle) |
3885 | { |
3886 | u32 grbm_soft_reset = 0; |
3887 | u32 tmp; |
3888 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3889 | |
3890 | /* GRBM_STATUS */ |
3891 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0004, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0004), 0)); |
3892 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK0x02000000L | GRBM_STATUS__SC_BUSY_MASK0x01000000L | |
3893 | GRBM_STATUS__BCI_BUSY_MASK0x00800000L | GRBM_STATUS__SX_BUSY_MASK0x00100000L | |
3894 | GRBM_STATUS__TA_BUSY_MASK0x00004000L | GRBM_STATUS__VGT_BUSY_MASK0x00020000L | |
3895 | GRBM_STATUS__DB_BUSY_MASK0x04000000L | GRBM_STATUS__CB_BUSY_MASK0x40000000L | |
3896 | GRBM_STATUS__GDS_BUSY_MASK0x00008000L | GRBM_STATUS__SPI_BUSY_MASK0x00400000L | |
3897 | GRBM_STATUS__IA_BUSY_MASK0x00080000L | GRBM_STATUS__IA_BUSY_NO_DMA_MASK0x00040000L)) { |
3898 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & ( (1) << 0x0))) |
3899 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & ( (1) << 0x0))); |
3900 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & ( (1) << 0x10))) |
3901 | GRBM_SOFT_RESET, SOFT_RESET_GFX, 1)(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & ( (1) << 0x10))); |
3902 | } |
3903 | |
3904 | if (tmp & (GRBM_STATUS__CP_BUSY_MASK0x20000000L | GRBM_STATUS__CP_COHERENCY_BUSY_MASK0x10000000L)) { |
3905 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & ( (1) << 0x0))) |
3906 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & ( (1) << 0x0))); |
3907 | } |
3908 | |
3909 | /* GRBM_STATUS2 */ |
3910 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0002, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0002), 0)); |
3911 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)(((tmp) & 0x01000000L) >> 0x18)) |
3912 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & ( (1) << 0x2))) |
3913 | GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & ( (1) << 0x2))); |
3914 | |
3915 | |
3916 | if (grbm_soft_reset) { |
3917 | /* stop the rlc */ |
3918 | adev->gfx.rlc.funcs->stop(adev); |
3919 | |
3920 | if (adev->gfx.num_gfx_rings) |
3921 | /* Disable GFX parsing/prefetching */ |
3922 | gfx_v9_0_cp_gfx_enable(adev, false0); |
3923 | |
3924 | /* Disable MEC parsing/prefetching */ |
3925 | gfx_v9_0_cp_compute_enable(adev, false0); |
3926 | |
3927 | if (grbm_soft_reset) { |
3928 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0008), 0)); |
3929 | tmp |= grbm_soft_reset; |
3930 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); |
3931 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0008), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0008)), (tmp), 0)); |
3932 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0008), 0)); |
3933 | |
3934 | udelay(50); |
3935 | |
3936 | tmp &= ~grbm_soft_reset; |
3937 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0008), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0008)), (tmp), 0)); |
3938 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0008, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0008), 0)); |
3939 | } |
3940 | |
3941 | /* Wait a little for things to settle down */ |
3942 | udelay(50); |
3943 | } |
3944 | return 0; |
3945 | } |
3946 | |
3947 | static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) |
3948 | { |
3949 | signed long r, cnt = 0; |
3950 | unsigned long flags; |
3951 | uint32_t seq, reg_val_offs = 0; |
3952 | uint64_t value = 0; |
3953 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; |
3954 | struct amdgpu_ring *ring = &kiq->ring; |
3955 | |
3956 | BUG_ON(!ring->funcs->emit_rreg)((!(!ring->funcs->emit_rreg)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c", 3956, "!(!ring->funcs->emit_rreg)" )); |
3957 | |
3958 | spin_lock_irqsave(&kiq->ring_lock, flags)do { flags = 0; mtx_enter(&kiq->ring_lock); } while (0 ); |
3959 | if (amdgpu_device_wb_get(adev, ®_val_offs)) { |
3960 | pr_err("critical bug! too many kiq readers\n")printk("\0013" "amdgpu: " "critical bug! too many kiq readers\n" ); |
3961 | goto failed_unlock; |
3962 | } |
3963 | amdgpu_ring_alloc(ring, 32); |
3964 | amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)((3 << 30) | (((0x40) & 0xFF) << 8) | ((4) & 0x3FFF) << 16)); |
3965 | amdgpu_ring_write(ring, 9 | /* src: register*/ |
3966 | (5 << 8) | /* dst: memory */ |
3967 | (1 << 16) | /* count sel */ |
3968 | (1 << 20)); /* write confirm */ |
3969 | amdgpu_ring_write(ring, 0); |
3970 | amdgpu_ring_write(ring, 0); |
3971 | amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +((u32)(adev->wb.gpu_addr + reg_val_offs * 4)) |
3972 | reg_val_offs * 4)((u32)(adev->wb.gpu_addr + reg_val_offs * 4))); |
3973 | amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16 ) >> 16)) |
3974 | reg_val_offs * 4)((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16 ) >> 16))); |
3975 | r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT5000); |
3976 | if (r) |
3977 | goto failed_undo; |
3978 | |
3979 | amdgpu_ring_commit(ring); |
3980 | spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while (0); |
3981 | |
3982 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT5000); |
3983 | |
3984 | /* don't wait anymore for gpu reset case because this way may |
3985 | * block gpu_recover() routine forever, e.g. this virt_kiq_rreg |
3986 | * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will |
3987 | * never return if we keep waiting in virt_kiq_rreg, which cause |
3988 | * gpu_recover() hang there. |
3989 | * |
3990 | * also don't wait anymore for IRQ context |
3991 | * */ |
3992 | if (r < 1 && (amdgpu_in_reset(adev))) |
3993 | goto failed_kiq_read; |
3994 | |
3995 | might_sleep()assertwaitok(); |
3996 | while (r < 1 && cnt++ < MAX_KIQ_REG_TRY1000) { |
3997 | drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL)mdelay(5); |
3998 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT5000); |
3999 | } |
4000 | |
4001 | if (cnt > MAX_KIQ_REG_TRY1000) |
4002 | goto failed_kiq_read; |
4003 | |
4004 | mb()do { __asm volatile("mfence" ::: "memory"); } while (0); |
4005 | value = (uint64_t)adev->wb.wb[reg_val_offs] | |
4006 | (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; |
4007 | amdgpu_device_wb_free(adev, reg_val_offs); |
4008 | return value; |
4009 | |
4010 | failed_undo: |
4011 | amdgpu_ring_undo(ring); |
4012 | failed_unlock: |
4013 | spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while (0); |
4014 | failed_kiq_read: |
4015 | if (reg_val_offs) |
4016 | amdgpu_device_wb_free(adev, reg_val_offs); |
4017 | pr_err("failed to read gpu clock\n")printk("\0013" "amdgpu: " "failed to read gpu clock\n"); |
4018 | return ~0; |
4019 | } |
4020 | |
4021 | static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) |
4022 | { |
4023 | uint64_t clock, clock_lo, clock_hi, hi_check; |
4024 | |
4025 | switch (adev->ip_versions[GC_HWIP][0]) { |
4026 | case IP_VERSION(9, 3, 0)(((9) << 16) | ((3) << 8) | (0)): |
4027 | preempt_disable(); |
4028 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0 ][1] + 0x0025, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0025), 0)); |
4029 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0 ][1] + 0x0026, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0026), 0)); |
4030 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0 ][1] + 0x0025, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0025), 0)); |
4031 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over |
4032 | * roughly every 42 seconds. |
4033 | */ |
4034 | if (hi_check != clock_hi) { |
4035 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0 ][1] + 0x0026, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0026), 0)); |
4036 | clock_hi = hi_check; |
4037 | } |
4038 | preempt_enable(); |
4039 | clock = clock_lo | (clock_hi << 32ULL); |
4040 | break; |
4041 | default: |
4042 | amdgpu_gfx_off_ctrl(adev, false0); |
4043 | mutex_lock(&adev->gfx.gpu_clock_mutex)rw_enter_write(&adev->gfx.gpu_clock_mutex); |
4044 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1)(((9) << 16) | ((0) << 8) | (1)) && amdgpu_sriov_runtime(adev)((adev)->virt.caps & (1 << 4))) { |
4045 | clock = gfx_v9_0_kiq_read_clock(adev); |
4046 | } else { |
4047 | WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c26), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][1] + 0x4c26)), (1), 0)); |
4048 | clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c24, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c24), 0)) | |
4049 | ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c25, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c25), 0)) << 32ULL); |
4050 | } |
4051 | mutex_unlock(&adev->gfx.gpu_clock_mutex)rw_exit_write(&adev->gfx.gpu_clock_mutex); |
4052 | amdgpu_gfx_off_ctrl(adev, true1); |
4053 | break; |
4054 | } |
4055 | return clock; |
4056 | } |
4057 | |
4058 | static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, |
4059 | uint32_t vmid, |
4060 | uint32_t gds_base, uint32_t gds_size, |
4061 | uint32_t gws_base, uint32_t gws_size, |
4062 | uint32_t oa_base, uint32_t oa_size) |
4063 | { |
4064 | struct amdgpu_device *adev = ring->adev; |
4065 | |
4066 | /* GDS Base */ |
4067 | gfx_v9_0_write_data_to_reg(ring, 0, false0, |
4068 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x1300) + 2 * vmid, |
4069 | gds_base); |
4070 | |
4071 | /* GDS Size */ |
4072 | gfx_v9_0_write_data_to_reg(ring, 0, false0, |
4073 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x1301) + 2 * vmid, |
4074 | gds_size); |
4075 | |
4076 | /* GWS */ |
4077 | gfx_v9_0_write_data_to_reg(ring, 0, false0, |
4078 | SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x1320) + vmid, |
4079 | gws_size << GDS_GWS_VMID0__SIZE__SHIFT0x10 | gws_base); |
4080 | |
4081 | /* OA */ |
4082 | gfx_v9_0_write_data_to_reg(ring, 0, false0, |
4083 | SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x1330) + vmid, |
4084 | (1 << (oa_size + oa_base)) - (1 << oa_base)); |
4085 | } |
4086 | |
4087 | static const u32 vgpr_init_compute_shader[] = |
4088 | { |
4089 | 0xb07c0000, 0xbe8000ff, |
4090 | 0x000000f8, 0xbf110800, |
4091 | 0x7e000280, 0x7e020280, |
4092 | 0x7e040280, 0x7e060280, |
4093 | 0x7e080280, 0x7e0a0280, |
4094 | 0x7e0c0280, 0x7e0e0280, |
4095 | 0x80808800, 0xbe803200, |
4096 | 0xbf84fff5, 0xbf9c0000, |
4097 | 0xd28c0001, 0x0001007f, |
4098 | 0xd28d0001, 0x0002027e, |
4099 | 0x10020288, 0xb8810904, |
4100 | 0xb7814000, 0xd1196a01, |
4101 | 0x00000301, 0xbe800087, |
4102 | 0xbefc00c1, 0xd89c4000, |
4103 | 0x00020201, 0xd89cc080, |
4104 | 0x00040401, 0x320202ff, |
4105 | 0x00000800, 0x80808100, |
4106 | 0xbf84fff8, 0x7e020280, |
4107 | 0xbf810000, 0x00000000, |
4108 | }; |
4109 | |
4110 | static const u32 sgpr_init_compute_shader[] = |
4111 | { |
4112 | 0xb07c0000, 0xbe8000ff, |
4113 | 0x0000005f, 0xbee50080, |
4114 | 0xbe812c65, 0xbe822c65, |
4115 | 0xbe832c65, 0xbe842c65, |
4116 | 0xbe852c65, 0xb77c0005, |
4117 | 0x80808500, 0xbf84fff8, |
4118 | 0xbe800080, 0xbf810000, |
4119 | }; |
4120 | |
4121 | static const u32 vgpr_init_compute_shader_arcturus[] = { |
4122 | 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, |
4123 | 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, |
4124 | 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, |
4125 | 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, |
4126 | 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, |
4127 | 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, |
4128 | 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, |
4129 | 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, |
4130 | 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, |
4131 | 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, |
4132 | 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, |
4133 | 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, |
4134 | 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, |
4135 | 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, |
4136 | 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, |
4137 | 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, |
4138 | 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, |
4139 | 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, |
4140 | 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, |
4141 | 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, |
4142 | 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, |
4143 | 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, |
4144 | 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, |
4145 | 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, |
4146 | 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, |
4147 | 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, |
4148 | 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, |
4149 | 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, |
4150 | 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, |
4151 | 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, |
4152 | 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, |
4153 | 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, |
4154 | 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, |
4155 | 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, |
4156 | 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, |
4157 | 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, |
4158 | 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, |
4159 | 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, |
4160 | 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, |
4161 | 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, |
4162 | 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, |
4163 | 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, |
4164 | 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, |
4165 | 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, |
4166 | 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, |
4167 | 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, |
4168 | 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, |
4169 | 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, |
4170 | 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, |
4171 | 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, |
4172 | 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, |
4173 | 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, |
4174 | 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, |
4175 | 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, |
4176 | 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, |
4177 | 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, |
4178 | 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, |
4179 | 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, |
4180 | 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, |
4181 | 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, |
4182 | 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, |
4183 | 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, |
4184 | 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, |
4185 | 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, |
4186 | 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, |
4187 | 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, |
4188 | 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, |
4189 | 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, |
4190 | 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, |
4191 | 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, |
4192 | 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, |
4193 | 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, |
4194 | 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, |
4195 | 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, |
4196 | 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, |
4197 | 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, |
4198 | 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, |
4199 | 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, |
4200 | 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, |
4201 | 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, |
4202 | 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, |
4203 | 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, |
4204 | 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, |
4205 | 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, |
4206 | 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, |
4207 | 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, |
4208 | 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, |
4209 | 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, |
4210 | 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, |
4211 | 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, |
4212 | 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, |
4213 | 0xbf84fff8, 0xbf810000, |
4214 | }; |
4215 | |
4216 | /* When below register arrays changed, please update gpr_reg_size, |
4217 | and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, |
4218 | to cover all gfx9 ASICs */ |
4219 | static const struct soc15_reg_entry vgpr_init_regs[] = { |
4220 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 }, |
4221 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 }, |
4222 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 4 }, |
4223 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 }, |
4224 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x3f }, |
4225 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x400000 }, /* 64KB LDS */ |
4226 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0xffffffff }, |
4227 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0xffffffff }, |
4228 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0xffffffff }, |
4229 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0xffffffff }, |
4230 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0xffffffff }, |
4231 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0xffffffff }, |
4232 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0xffffffff }, |
4233 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0xffffffff }, |
4234 | }; |
4235 | |
4236 | static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { |
4237 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 }, |
4238 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 }, |
4239 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 4 }, |
4240 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 }, |
4241 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0xbf }, |
4242 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x400000 }, /* 64KB LDS */ |
4243 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0xffffffff }, |
4244 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0xffffffff }, |
4245 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0xffffffff }, |
4246 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0xffffffff }, |
4247 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0xffffffff }, |
4248 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0xffffffff }, |
4249 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0xffffffff }, |
4250 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0xffffffff }, |
4251 | }; |
4252 | |
4253 | static const struct soc15_reg_entry sgpr1_init_regs[] = { |
4254 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 }, |
4255 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 }, |
4256 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 8 }, |
4257 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 }, |
4258 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x240 }, /* (80 GPRS) */ |
4259 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x0 }, |
4260 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0x000000ff }, |
4261 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0x000000ff }, |
4262 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0x000000ff }, |
4263 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0x000000ff }, |
4264 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0x000000ff }, |
4265 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0x000000ff }, |
4266 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0x000000ff }, |
4267 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0x000000ff }, |
4268 | }; |
4269 | |
4270 | static const struct soc15_reg_entry sgpr2_init_regs[] = { |
4271 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS)GC_HWIP, 0, 0, 0x0e15, 0x0000000 }, |
4272 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X)GC_HWIP, 0, 0, 0x0e07, 0x40 }, |
4273 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y)GC_HWIP, 0, 0, 0x0e08, 8 }, |
4274 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z)GC_HWIP, 0, 0, 0x0e09, 1 }, |
4275 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1)GC_HWIP, 0, 0, 0x0e12, 0x240 }, /* (80 GPRS) */ |
4276 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2)GC_HWIP, 0, 0, 0x0e13, 0x0 }, |
4277 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0)GC_HWIP, 0, 0, 0x0e16, 0x0000ff00 }, |
4278 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1)GC_HWIP, 0, 0, 0x0e17, 0x0000ff00 }, |
4279 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2)GC_HWIP, 0, 0, 0x0e19, 0x0000ff00 }, |
4280 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3)GC_HWIP, 0, 0, 0x0e1a, 0x0000ff00 }, |
4281 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4)GC_HWIP, 0, 0, 0x0e25, 0x0000ff00 }, |
4282 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5)GC_HWIP, 0, 0, 0x0e26, 0x0000ff00 }, |
4283 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6)GC_HWIP, 0, 0, 0x0e27, 0x0000ff00 }, |
4284 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7)GC_HWIP, 0, 0, 0x0e28, 0x0000ff00 }, |
4285 | }; |
4286 | |
4287 | static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { |
4288 | { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT)GC_HWIP, 0, 0, 0x118e, 0, 1, 1}, |
4289 | { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT)GC_HWIP, 0, 0, 0x118f, 0, 1, 1}, |
4290 | { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT)GC_HWIP, 0, 0, 0x118a, 0, 1, 1}, |
4291 | { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x1189, 0, 1, 1}, |
4292 | { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT)GC_HWIP, 0, 0, 0x118d, 0, 1, 1}, |
4293 | { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT)GC_HWIP, 0, 0, 0x118b, 0, 1, 1}, |
4294 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT)GC_HWIP, 0, 0, 0x1192, 0, 1, 1}, |
4295 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT)GC_HWIP, 0, 0, 0x1193, 0, 1, 1}, |
4296 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT)GC_HWIP, 0, 0, 0x1191, 0, 1, 1}, |
4297 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT)GC_HWIP, 0, 0, 0x05c5, 0, 1, 1}, |
4298 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT)GC_HWIP, 0, 0, 0x05c6, 0, 1, 1}, |
4299 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED)GC_HWIP, 0, 0, 0x05c7, 0, 1, 1}, |
4300 | { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT)GC_HWIP, 0, 0, 0x0445, 0, 4, 1}, |
4301 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT)GC_HWIP, 0, 0, 0x03a2, 0, 4, 6}, |
4302 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT)GC_HWIP, 0, 0, 0x03a4, 0, 4, 16}, |
4303 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO)GC_HWIP, 0, 0, 0x03a5, 0, 4, 16}, |
4304 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT)GC_HWIP, 0, 0, 0x03a3, 0, 4, 16}, |
4305 | { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT)GC_HWIP, 0, 0, 0x0b82, 0, 1, 16}, |
4306 | { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT)GC_HWIP, 0, 0, 0x12b1, 0, 4, 16}, |
4307 | { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT)GC_HWIP, 0, 0, 0x0b17, 0, 4, 16}, |
4308 | { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW)GC_HWIP, 0, 0, 0x0b18, 0, 4, 16}, |
4309 | { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT)GC_HWIP, 0, 0, 0x052e, 0, 4, 16}, |
4310 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2)GC_HWIP, 0, 0, 0x032c, 0, 4, 6}, |
4311 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT)GC_HWIP, 0, 0, 0x03a6, 0, 4, 16}, |
4312 | { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT)GC_HWIP, 0, 0, 0x0586, 0, 4, 16}, |
4313 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT)GC_HWIP, 0, 0, 0x05cb, 0, 1, 1}, |
4314 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT)GC_HWIP, 0, 0, 0x05cc, 0, 1, 1}, |
4315 | { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT)GC_HWIP, 0, 0, 0x0706, 0, 1, 32}, |
4316 | { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2)GC_HWIP, 0, 0, 0x0707, 0, 1, 32}, |
4317 | { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT)GC_HWIP, 0, 0, 0x0b60, 0, 1, 72}, |
4318 | { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2)GC_HWIP, 0, 0, 0x0b83, 0, 1, 16}, |
4319 | { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT)GC_HWIP, 0, 0, 0x0bc5, 0, 1, 2}, |
4320 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3)GC_HWIP, 0, 0, 0x032d, 0, 4, 6}, |
4321 | }; |
4322 | |
4323 | static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) |
4324 | { |
4325 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; |
4326 | int i, r; |
4327 | |
4328 | /* only support when RAS is enabled */ |
4329 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
4330 | return 0; |
4331 | |
4332 | r = amdgpu_ring_alloc(ring, 7); |
4333 | if (r) { |
4334 | DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",__drm_err("amdgpu: GDS workarounds failed to lock ring %s (%d).\n" , ring->name, r) |
4335 | ring->name, r)__drm_err("amdgpu: GDS workarounds failed to lock ring %s (%d).\n" , ring->name, r); |
4336 | return r; |
4337 | } |
4338 | |
4339 | WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1300), 0x00000000, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1300)), (0x00000000 ), 0)); |
4340 | WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1301), adev->gds.gds_size, 0, GC_HWIP) : amdgpu_device_wreg (adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1301)), (adev ->gds.gds_size), 0)); |
4341 | |
4342 | amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)((3 << 30) | (((0x50) & 0xFF) << 8) | ((5) & 0x3FFF) << 16)); |
4343 | amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC(1 << 31) | |
4344 | PACKET3_DMA_DATA_DST_SEL(1)((1) << 20) | |
4345 | PACKET3_DMA_DATA_SRC_SEL(2)((2) << 29) | |
4346 | PACKET3_DMA_DATA_ENGINE(0)((0) << 0))); |
4347 | amdgpu_ring_write(ring, 0); |
4348 | amdgpu_ring_write(ring, 0); |
4349 | amdgpu_ring_write(ring, 0); |
4350 | amdgpu_ring_write(ring, 0); |
4351 | amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT(1 << 30) | |
4352 | adev->gds.gds_size); |
4353 | |
4354 | amdgpu_ring_commit(ring); |
4355 | |
4356 | for (i = 0; i < adev->usec_timeout; i++) { |
4357 | if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) |
4358 | break; |
4359 | udelay(1); |
4360 | } |
4361 | |
4362 | if (i >= adev->usec_timeout) |
4363 | r = -ETIMEDOUT60; |
4364 | |
4365 | WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1301), 0x00000000, 0, GC_HWIP) : amdgpu_device_wreg(adev , ((adev->reg_offset[GC_HWIP][0][0] + 0x1301)), (0x00000000 ), 0)); |
4366 | |
4367 | return r; |
4368 | } |
4369 | |
4370 | static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) |
4371 | { |
4372 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; |
4373 | struct amdgpu_ib ib; |
4374 | struct dma_fence *f = NULL((void *)0); |
4375 | int r, i; |
4376 | unsigned total_size, vgpr_offset, sgpr_offset; |
4377 | u64 gpu_addr; |
4378 | |
4379 | int compute_dim_x = adev->gfx.config.max_shader_engines * |
4380 | adev->gfx.config.max_cu_per_sh * |
4381 | adev->gfx.config.max_sh_per_se; |
4382 | int sgpr_work_group_size = 5; |
4383 | int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; |
4384 | int vgpr_init_shader_size; |
4385 | const u32 *vgpr_init_shader_ptr; |
4386 | const struct soc15_reg_entry *vgpr_init_regs_ptr; |
4387 | |
4388 | /* only support when RAS is enabled */ |
4389 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
4390 | return 0; |
4391 | |
4392 | /* bail if the compute ring is not ready */ |
4393 | if (!ring->sched.ready) |
4394 | return 0; |
4395 | |
4396 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1))) { |
4397 | vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; |
4398 | vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); |
4399 | vgpr_init_regs_ptr = vgpr_init_regs_arcturus; |
4400 | } else { |
4401 | vgpr_init_shader_ptr = vgpr_init_compute_shader; |
4402 | vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); |
4403 | vgpr_init_regs_ptr = vgpr_init_regs; |
4404 | } |
4405 | |
4406 | total_size = |
4407 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ |
4408 | total_size += |
4409 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ |
4410 | total_size += |
4411 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ |
4412 | total_size = roundup2(total_size, 256)(((total_size) + ((256) - 1)) & (~((__typeof(total_size)) (256) - 1))); |
4413 | vgpr_offset = total_size; |
4414 | total_size += roundup2(vgpr_init_shader_size, 256)(((vgpr_init_shader_size) + ((256) - 1)) & (~((__typeof(vgpr_init_shader_size ))(256) - 1))); |
4415 | sgpr_offset = total_size; |
4416 | total_size += sizeof(sgpr_init_compute_shader); |
4417 | |
4418 | /* allocate an indirect buffer to put the commands in */ |
4419 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); |
4420 | r = amdgpu_ib_get(adev, NULL((void *)0), total_size, |
4421 | AMDGPU_IB_POOL_DIRECT, &ib); |
4422 | if (r) { |
4423 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r)__drm_err("amdgpu: failed to get ib (%d).\n", r); |
4424 | return r; |
4425 | } |
4426 | |
4427 | /* load the compute shaders */ |
4428 | for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) |
4429 | ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; |
4430 | |
4431 | for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader)(sizeof((sgpr_init_compute_shader)) / sizeof((sgpr_init_compute_shader )[0])); i++) |
4432 | ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; |
4433 | |
4434 | /* init the ib length to 0 */ |
4435 | ib.length_dw = 0; |
4436 | |
4437 | /* VGPR */ |
4438 | /* write the register state for the compute dispatch */ |
4439 | for (i = 0; i < gpr_reg_size; i++) { |
4440 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
4441 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])(adev->reg_offset[vgpr_init_regs_ptr[i].hwip][vgpr_init_regs_ptr [i].inst][vgpr_init_regs_ptr[i].seg] + vgpr_init_regs_ptr[i]. reg_offset) |
4442 | - PACKET3_SET_SH_REG_START0x00002c00; |
4443 | ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; |
4444 | } |
4445 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
4446 | gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; |
4447 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
4448 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c) |
4449 | - PACKET3_SET_SH_REG_START0x00002c00; |
4450 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
4451 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
4452 | |
4453 | /* write dispatch packet */ |
4454 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
4455 | ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ |
4456 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4457 | ib.ptr[ib.length_dw++] = 1; /* z */ |
4458 | ib.ptr[ib.length_dw++] = |
4459 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0 ))); |
4460 | |
4461 | /* write CS partial flush packet */ |
4462 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
4463 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
4464 | |
4465 | /* SGPR1 */ |
4466 | /* write the register state for the compute dispatch */ |
4467 | for (i = 0; i < gpr_reg_size; i++) { |
4468 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
4469 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])(adev->reg_offset[sgpr1_init_regs[i].hwip][sgpr1_init_regs [i].inst][sgpr1_init_regs[i].seg] + sgpr1_init_regs[i].reg_offset ) |
4470 | - PACKET3_SET_SH_REG_START0x00002c00; |
4471 | ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; |
4472 | } |
4473 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
4474 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
4475 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
4476 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c) |
4477 | - PACKET3_SET_SH_REG_START0x00002c00; |
4478 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
4479 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
4480 | |
4481 | /* write dispatch packet */ |
4482 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
4483 | ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ |
4484 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4485 | ib.ptr[ib.length_dw++] = 1; /* z */ |
4486 | ib.ptr[ib.length_dw++] = |
4487 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0 ))); |
4488 | |
4489 | /* write CS partial flush packet */ |
4490 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
4491 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
4492 | |
4493 | /* SGPR2 */ |
4494 | /* write the register state for the compute dispatch */ |
4495 | for (i = 0; i < gpr_reg_size; i++) { |
4496 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
4497 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])(adev->reg_offset[sgpr2_init_regs[i].hwip][sgpr2_init_regs [i].inst][sgpr2_init_regs[i].seg] + sgpr2_init_regs[i].reg_offset ) |
4498 | - PACKET3_SET_SH_REG_START0x00002c00; |
4499 | ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; |
4500 | } |
4501 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
4502 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
4503 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
4504 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)(adev->reg_offset[GC_HWIP][0][0] + 0x0e0c) |
4505 | - PACKET3_SET_SH_REG_START0x00002c00; |
4506 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
4507 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
4508 | |
4509 | /* write dispatch packet */ |
4510 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
4511 | ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ |
4512 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4513 | ib.ptr[ib.length_dw++] = 1; /* z */ |
4514 | ib.ptr[ib.length_dw++] = |
4515 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x00000001L) | (0x00000001L & ((1) << 0x0 ))); |
4516 | |
4517 | /* write CS partial flush packet */ |
4518 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
4519 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
4520 | |
4521 | /* shedule the ib on the ring */ |
4522 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); |
4523 | if (r) { |
4524 | DRM_ERROR("amdgpu: ib submit failed (%d).\n", r)__drm_err("amdgpu: ib submit failed (%d).\n", r); |
4525 | goto fail; |
4526 | } |
4527 | |
4528 | /* wait for the GPU to finish processing the IB */ |
4529 | r = dma_fence_wait(f, false0); |
4530 | if (r) { |
4531 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r)__drm_err("amdgpu: fence wait failed (%d).\n", r); |
4532 | goto fail; |
4533 | } |
4534 | |
4535 | fail: |
4536 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); |
4537 | dma_fence_put(f); |
4538 | |
4539 | return r; |
4540 | } |
4541 | |
4542 | static int gfx_v9_0_early_init(void *handle) |
4543 | { |
4544 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4545 | |
4546 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)(((9) << 16) | ((4) << 8) | (1)) || |
4547 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2))) |
4548 | adev->gfx.num_gfx_rings = 0; |
4549 | else |
4550 | adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS1; |
4551 | adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),(((amdgpu_gfx_get_num_kcq(adev))<(8))?(amdgpu_gfx_get_num_kcq (adev)):(8)) |
4552 | AMDGPU_MAX_COMPUTE_RINGS)(((amdgpu_gfx_get_num_kcq(adev))<(8))?(amdgpu_gfx_get_num_kcq (adev)):(8)); |
4553 | gfx_v9_0_set_kiq_pm4_funcs(adev); |
4554 | gfx_v9_0_set_ring_funcs(adev); |
4555 | gfx_v9_0_set_irq_funcs(adev); |
4556 | gfx_v9_0_set_gds_init(adev); |
4557 | gfx_v9_0_set_rlc_funcs(adev); |
4558 | |
4559 | /* init rlcg reg access ctrl */ |
4560 | gfx_v9_0_init_rlcg_reg_access_ctrl(adev); |
4561 | |
4562 | return 0; |
4563 | } |
4564 | |
4565 | static int gfx_v9_0_ecc_late_init(void *handle) |
4566 | { |
4567 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4568 | int r; |
4569 | |
4570 | /* |
4571 | * Temp workaround to fix the issue that CP firmware fails to |
4572 | * update read pointer when CPDMA is writing clearing operation |
4573 | * to GDS in suspend/resume sequence on several cards. So just |
4574 | * limit this operation in cold boot sequence. |
4575 | */ |
4576 | if ((!adev->in_suspend) && |
4577 | (adev->gds.gds_size)) { |
4578 | r = gfx_v9_0_do_edc_gds_workarounds(adev); |
4579 | if (r) |
4580 | return r; |
4581 | } |
4582 | |
4583 | /* requires IBs so do in late init after IB pool is initialized */ |
4584 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2))) |
4585 | r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); |
4586 | else |
4587 | r = gfx_v9_0_do_edc_gpr_workarounds(adev); |
4588 | |
4589 | if (r) |
4590 | return r; |
4591 | |
4592 | if (adev->gfx.ras && |
4593 | adev->gfx.ras->enable_watchdog_timer) |
4594 | adev->gfx.ras->enable_watchdog_timer(adev); |
4595 | |
4596 | return 0; |
4597 | } |
4598 | |
4599 | static int gfx_v9_0_late_init(void *handle) |
4600 | { |
4601 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4602 | int r; |
4603 | |
4604 | r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); |
4605 | if (r) |
4606 | return r; |
4607 | |
4608 | r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); |
4609 | if (r) |
4610 | return r; |
4611 | |
4612 | r = gfx_v9_0_ecc_late_init(handle); |
4613 | if (r) |
4614 | return r; |
4615 | |
4616 | return 0; |
4617 | } |
4618 | |
4619 | static bool_Bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) |
4620 | { |
4621 | uint32_t rlc_setting; |
4622 | |
4623 | /* if RLC is not enabled, do nothing */ |
4624 | rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c00), 0)); |
4625 | if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK0x00000001L)) |
4626 | return false0; |
4627 | |
4628 | return true1; |
4629 | } |
4630 | |
4631 | static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) |
4632 | { |
4633 | uint32_t data; |
4634 | unsigned i; |
4635 | |
4636 | data = RLC_SAFE_MODE__CMD_MASK0x00000001L; |
4637 | data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT0x1); |
4638 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c05)), (data), 0)); |
4639 | |
4640 | /* wait for RLC_SAFE_MODE */ |
4641 | for (i = 0; i < adev->usec_timeout; i++) { |
4642 | if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c05, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c05), 0))) & 0x00000001L) >> 0x0)) |
4643 | break; |
4644 | udelay(1); |
4645 | } |
4646 | } |
4647 | |
4648 | static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) |
4649 | { |
4650 | uint32_t data; |
4651 | |
4652 | data = RLC_SAFE_MODE__CMD_MASK0x00000001L; |
4653 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c05)), (data), 0)); |
4654 | } |
4655 | |
4656 | static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, |
4657 | bool_Bool enable) |
4658 | { |
4659 | amdgpu_gfx_rlc_enter_safe_mode(adev); |
4660 | |
4661 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG(1 << 0)) && enable) { |
4662 | gfx_v9_0_enable_gfx_cg_power_gating(adev, true1); |
4663 | if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE(1 << 12)) |
4664 | gfx_v9_0_enable_gfx_pipeline_powergating(adev, true1); |
4665 | } else { |
4666 | gfx_v9_0_enable_gfx_cg_power_gating(adev, false0); |
4667 | if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE(1 << 12)) |
4668 | gfx_v9_0_enable_gfx_pipeline_powergating(adev, false0); |
4669 | } |
4670 | |
4671 | amdgpu_gfx_rlc_exit_safe_mode(adev); |
4672 | } |
4673 | |
4674 | static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, |
4675 | bool_Bool enable) |
4676 | { |
4677 | /* TODO: double check if we need to perform under safe mode */ |
4678 | /* gfx_v9_0_enter_rlc_safe_mode(adev); */ |
4679 | |
4680 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG(1 << 1)) && enable) |
4681 | gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true1); |
4682 | else |
4683 | gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false0); |
4684 | |
4685 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG(1 << 2)) && enable) |
4686 | gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true1); |
4687 | else |
4688 | gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false0); |
4689 | |
4690 | /* gfx_v9_0_exit_rlc_safe_mode(adev); */ |
4691 | } |
4692 | |
4693 | static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
4694 | bool_Bool enable) |
4695 | { |
4696 | uint32_t data, def; |
4697 | |
4698 | amdgpu_gfx_rlc_enter_safe_mode(adev); |
4699 | |
4700 | /* It is disabled by HW by default */ |
4701 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0))) { |
4702 | /* 1 - RLC_CGTT_MGCG_OVERRIDE */ |
4703 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c48), 0)); |
4704 | |
4705 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1))) |
4706 | data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK0x00000001L; |
4707 | |
4708 | data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L | |
4709 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L | |
4710 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L); |
4711 | |
4712 | /* only for Vega10 & Raven1 */ |
4713 | data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L; |
4714 | |
4715 | if (def != data) |
4716 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0)); |
4717 | |
4718 | /* MGLS is a global flag to control all MGLS in GFX */ |
4719 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS(1ULL << 1)) { |
4720 | /* 2 - RLC memory Light sleep */ |
4721 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS(1ULL << 7)) { |
4722 | def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c06, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c06), 0)); |
4723 | data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L; |
4724 | if (def != data) |
4725 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c06), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c06)), (data), 0)); |
4726 | } |
4727 | /* 3 - CP memory Light sleep */ |
4728 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS(1ULL << 6)) { |
4729 | def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1079, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1079), 0)); |
4730 | data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L; |
4731 | if (def != data) |
4732 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1079), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][0] + 0x1079)), (data), 0)); |
4733 | } |
4734 | } |
4735 | } else { |
4736 | /* 1 - MGCG_OVERRIDE */ |
4737 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c48), 0)); |
4738 | |
4739 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)(((9) << 16) | ((2) << 8) | (1))) |
4740 | data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK0x00000001L; |
4741 | |
4742 | data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L | |
4743 | RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L | |
4744 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L | |
4745 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L); |
4746 | |
4747 | if (def != data) |
4748 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0)); |
4749 | |
4750 | /* 2 - disable MGLS in RLC */ |
4751 | data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c06, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c06), 0)); |
4752 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L) { |
4753 | data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L; |
4754 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c06), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c06)), (data), 0)); |
4755 | } |
4756 | |
4757 | /* 3 - disable MGLS in CP */ |
4758 | data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x1079, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x1079), 0)); |
4759 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L) { |
4760 | data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L; |
4761 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x1079), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][0] + 0x1079)), (data), 0)); |
4762 | } |
4763 | } |
4764 | |
4765 | amdgpu_gfx_rlc_exit_safe_mode(adev); |
4766 | } |
4767 | |
4768 | static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, |
4769 | bool_Bool enable) |
4770 | { |
4771 | uint32_t data, def; |
4772 | |
4773 | if (!adev->gfx.num_gfx_rings) |
4774 | return; |
4775 | |
4776 | amdgpu_gfx_rlc_enter_safe_mode(adev); |
4777 | |
4778 | /* Enable 3D CGCG/CGLS */ |
4779 | if (enable) { |
4780 | /* write cmd to clear cgcg/cgls ov */ |
4781 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4c48), 0)); |
4782 | /* unset CGCG override */ |
4783 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK0x00000080L; |
4784 | /* update CGCG and CGLS override bits */ |
4785 | if (def != data) |
4786 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0)); |
4787 | |
4788 | /* enable 3Dcgcg FSM(0x0000363f) */ |
4789 | def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1 ] + 0x4cc5, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][1] + 0x4cc5), 0)); |
4790 | |
4791 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20)) |
479 |