/usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppevvmath.h

Bug Summary

File:	dev/pci/drm/amd/pm/powerplay/hwmgr/ppevvmath.h
Warning:	line 223, column 18 The result of the left shift is undefined because the left operand is negative

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name ppatomctrl.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

/usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

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1/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
23#include "pp_debug.h"
24#include <linux/module.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include "atom.h"
28#include "ppatomctrl.h"
29#include "atombios.h"
30#include "cgs_common.h"
31#include "ppevvmath.h"

33#define MEM_ID_MASK0xff000000           0xff000000
34#define MEM_ID_SHIFT24          24
35#define CLOCK_RANGE_MASK0x00ffffff      0x00ffffff
36#define CLOCK_RANGE_SHIFT0     0
37#define LOW_NIBBLE_MASK0xf       0xf
38#define DATA_EQU_PREV0         0
39#define DATA_FROM_TABLE4       4

41union voltage_object_info {
struct _ATOM_VOLTAGE_OBJECT_INFO v1;
struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
45};

47static int atomctrl_retrieve_ac_timing(
uint8_t index,
ATOM_INIT_REG_BLOCK *reg_block,
pp_atomctrl_mc_reg_table *table)
51{
uint32_t i, j;
uint8_t tmem_id;
ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize)((__uint16_t)(reg_block->usRegIndexTblSize)));

uint8_t num_ranges = 0;

while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK0x00000000 &&
	num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES20) {
tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK0xff000000) >> MEM_ID_SHIFT24);

if (index == tmem_id) {
	table->mc_reg_table_entry[num_ranges].mclk_max =
		(uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK0x00ffffff) >>
				CLOCK_RANGE_SHIFT0);

	for (i = 0, j = 1; i < table->last; i++) {
		if ((table->mc_reg_address[i].uc_pre_reg_data &
					LOW_NIBBLE_MASK0xf) == DATA_FROM_TABLE4) {
			table->mc_reg_table_entry[num_ranges].mc_data[i] =
				(uint32_t)*((uint32_t *)reg_data + j);
			j++;
		} else if ((table->mc_reg_address[i].uc_pre_reg_data &
					LOW_NIBBLE_MASK0xf) == DATA_EQU_PREV0) {
			table->mc_reg_table_entry[num_ranges].mc_data[i] =
				table->mc_reg_table_entry[num_ranges].mc_data[i-1];
		}
	}
	num_ranges++;
}

reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
	((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)((__uint16_t)(reg_block->usRegDataBlkSize))) ;
}

PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),do { if (!((*(uint32_t *)reg_data == 0x00000000))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid VramInfo table."); return -1; } }
 while (0)
	"Invalid VramInfo table.", return -1)do { if (!((*(uint32_t *)reg_data == 0x00000000))) { printk("\0014"
 "amdgpu: " "%s\n", "Invalid VramInfo table."); return -1; } }
 while (0);
table->num_entries = num_ranges;

return 0;
92}

94/**
* atomctrl_set_mc_reg_address_table - Get memory clock AC timing registers index from VBIOS table
* VBIOS set end of memory clock AC timing registers by ucPreRegDataLength bit6 = 1
* @reg_block: the address ATOM_INIT_REG_BLOCK
* @table: the address of MCRegTable
* Return:   0
*/
101static int atomctrl_set_mc_reg_address_table(
ATOM_INIT_REG_BLOCK *reg_block,
pp_atomctrl_mc_reg_table *table)
104{
uint8_t i = 0;
uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize)((__uint16_t)(reg_block->usRegIndexTblSize)))
	/ sizeof(ATOM_INIT_REG_INDEX_FORMAT));
ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];

num_entries--;        /* subtract 1 data end mark entry */

PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE),do { if (!((num_entries <= 32))) { printk("\0014" "amdgpu: "
 "%s\n", "Invalid VramInfo table."); return -1; } } while (0)
	"Invalid VramInfo table.", return -1)do { if (!((num_entries <= 32))) { printk("\0014" "amdgpu: "
 "%s\n", "Invalid VramInfo table."); return -1; } } while (0);

/* ucPreRegDataLength bit6 = 1 is the end of memory clock AC timing registers */
while ((!(format->ucPreRegDataLength & ACCESS_PLACEHOLDER0x80)) &&
	(i < num_entries)) {
table->mc_reg_address[i].s1 =
	(uint16_t)(le16_to_cpu(format->usRegIndex)((__uint16_t)(format->usRegIndex)));
table->mc_reg_address[i].uc_pre_reg_data =
	format->ucPreRegDataLength;

i++;
format = (ATOM_INIT_REG_INDEX_FORMAT *)
	((uint8_t *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
}

table->last = i;
return 0;
130}

132int atomctrl_initialize_mc_reg_table(
struct pp_hwmgr *hwmgr,
uint8_t module_index,
pp_atomctrl_mc_reg_table *table)
136{
ATOM_VRAM_INFO_HEADER_V2_1 *vram_info;
ATOM_INIT_REG_BLOCK *reg_block;
int result = 0;
u8 frev, crev;
u16 size;

vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
smu_atom_get_data_table(hwmgr->adev,
		GetIndexIntoMasterTable(DATA, VRAM_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, VRAM_Info
) / sizeof(USHORT)), &size, &frev, &crev);

if (module_index >= vram_info->ucNumOfVRAMModule) {
pr_err("Invalid VramInfo table.")printk("\0013" "amdgpu: " "Invalid VramInfo table.");
result = -1;
} else if (vram_info->sHeader.ucTableFormatRevision < 2) {
pr_err("Invalid VramInfo table.")printk("\0013" "amdgpu: " "Invalid VramInfo table.");
result = -1;
}

if (0 == result) {
reg_block = (ATOM_INIT_REG_BLOCK *)
	((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset)((__uint16_t)(vram_info->usMemClkPatchTblOffset)));
result = atomctrl_set_mc_reg_address_table(reg_block, table);
}

if (0 == result) {
result = atomctrl_retrieve_ac_timing(module_index,
			reg_block, table);
}

return result;
167}

169int atomctrl_initialize_mc_reg_table_v2_2(
struct pp_hwmgr *hwmgr,
uint8_t module_index,
pp_atomctrl_mc_reg_table *table)
173{
ATOM_VRAM_INFO_HEADER_V2_2 *vram_info;
ATOM_INIT_REG_BLOCK *reg_block;
int result = 0;
u8 frev, crev;
u16 size;

vram_info = (ATOM_VRAM_INFO_HEADER_V2_2 *)
smu_atom_get_data_table(hwmgr->adev,
		GetIndexIntoMasterTable(DATA, VRAM_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, VRAM_Info
) / sizeof(USHORT)), &size, &frev, &crev);

if (module_index >= vram_info->ucNumOfVRAMModule) {
pr_err("Invalid VramInfo table.")printk("\0013" "amdgpu: " "Invalid VramInfo table.");
result = -1;
} else if (vram_info->sHeader.ucTableFormatRevision < 2) {
pr_err("Invalid VramInfo table.")printk("\0013" "amdgpu: " "Invalid VramInfo table.");
result = -1;
}

if (0 == result) {
reg_block = (ATOM_INIT_REG_BLOCK *)
	((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset)((__uint16_t)(vram_info->usMemClkPatchTblOffset)));
result = atomctrl_set_mc_reg_address_table(reg_block, table);
}

if (0 == result) {
result = atomctrl_retrieve_ac_timing(module_index,
			reg_block, table);
}

return result;
204}

206/*
* Set DRAM timings based on engine clock and memory clock.
*/
209int atomctrl_set_engine_dram_timings_rv770(
struct pp_hwmgr *hwmgr,
uint32_t engine_clock,
uint32_t memory_clock)
213{
struct amdgpu_device *adev = hwmgr->adev;

SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;

/* They are both in 10KHz Units. */
engine_clock_parameters.ulTargetEngineClock =
cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) |((__uint32_t)((engine_clock & 0x00FFFFFF) | ((2 << 24
))))
	    ((COMPUTE_ENGINE_PLL_PARAM << 24)))((__uint32_t)((engine_clock & 0x00FFFFFF) | ((2 << 24
))));

/* in 10 khz units.*/
engine_clock_parameters.sReserved.ulClock =
cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK)((__uint32_t)(memory_clock & 0x00FFFFFF));

return amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DynamicMemorySettings
) / sizeof(USHORT)),
	(uint32_t *)&engine_clock_parameters);
230}

232/*
* Private Function to get the PowerPlay Table Address.
* WARNING: The tabled returned by this function is in
* dynamically allocated memory.
* The caller has to release if by calling kfree.
*/
238static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device)
239{
int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, VoltageObjectInfo
) / sizeof(USHORT));
u8 frev, crev;
u16 size;
union voltage_object_info *voltage_info;

voltage_info = (union voltage_object_info *)
smu_atom_get_data_table(device, index,
	&size, &frev, &crev);

if (voltage_info != NULL((void *)0))
return (ATOM_VOLTAGE_OBJECT_INFO *) &(voltage_info->v3);
else
return NULL((void *)0);
253}

255static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3(
const ATOM_VOLTAGE_OBJECT_INFO_V3_1 * voltage_object_info_table,
uint8_t voltage_type, uint8_t voltage_mode)
258{
unsigned int size = le16_to_cpu(voltage_object_info_table->sHeader.usStructureSize)((__uint16_t)(voltage_object_info_table->sHeader.usStructureSize
));
unsigned int offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0])__builtin_offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj
[0]);
uint8_t *start = (uint8_t *)voltage_object_info_table;

while (offset < size) {
const ATOM_VOLTAGE_OBJECT_V3 *voltage_object =
	(const ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);

if (voltage_type == voltage_object->asGpioVoltageObj.sHeader.ucVoltageType &&
	voltage_mode == voltage_object->asGpioVoltageObj.sHeader.ucVoltageMode)
	return voltage_object;

offset += le16_to_cpu(voltage_object->asGpioVoltageObj.sHeader.usSize)((__uint16_t)(voltage_object->asGpioVoltageObj.sHeader.usSize
));
}

return NULL((void *)0);
275}

277/**
* atomctrl_get_memory_pll_dividers_si
*
* @hwmgr:           input parameter: pointer to HwMgr
* @clock_value:     input parameter: memory clock
* @mpll_param:      output parameter: memory clock parameters
* @strobe_mode:     input parameter: 1 for strobe mode,  0 for performance mode
*/
285int atomctrl_get_memory_pll_dividers_si(
struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_memory_clock_param *mpll_param,
bool_Bool strobe_mode)
290{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
int result;

mpll_parameters.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));
mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryClockParam
) / sizeof(USHORT)),
(uint32_t *)&mpll_parameters);

if (0 == result) {
mpll_param->mpll_fb_divider.clk_frac =
	le16_to_cpu(mpll_parameters.ulFbDiv.usFbDivFrac)((__uint16_t)(mpll_parameters.ulFbDiv.usFbDivFrac));
mpll_param->mpll_fb_divider.cl_kf =
	le16_to_cpu(mpll_parameters.ulFbDiv.usFbDiv)((__uint16_t)(mpll_parameters.ulFbDiv.usFbDiv));
mpll_param->mpll_post_divider =
	(uint32_t)mpll_parameters.ucPostDiv;
mpll_param->vco_mode =
	(uint32_t)(mpll_parameters.ucPllCntlFlag &
			MPLL_CNTL_FLAG_VCO_MODE_MASK0x03);
mpll_param->yclk_sel =
	(uint32_t)((mpll_parameters.ucPllCntlFlag &
				MPLL_CNTL_FLAG_BYPASS_DQ_PLL0x04) ? 1 : 0);
mpll_param->qdr =
	(uint32_t)((mpll_parameters.ucPllCntlFlag &
				MPLL_CNTL_FLAG_QDR_ENABLE0x08) ? 1 : 0);
mpll_param->half_rate =
	(uint32_t)((mpll_parameters.ucPllCntlFlag &
				MPLL_CNTL_FLAG_AD_HALF_RATE0x10) ? 1 : 0);
mpll_param->dll_speed =
	(uint32_t)(mpll_parameters.ucDllSpeed);
mpll_param->bw_ctrl =
	(uint32_t)(mpll_parameters.ucBWCntl);
}

return result;
328}

330/**
* atomctrl_get_memory_pll_dividers_vi
*
* @hwmgr:                 input parameter: pointer to HwMgr
* @clock_value:           input parameter: memory clock
* @mpll_param:            output parameter: memory clock parameters
*/
337int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
339{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
int result;

mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryClockParam
) / sizeof(USHORT)),
	(uint32_t *)&mpll_parameters);

if (!result)
mpll_param->mpll_post_divider =
		(uint32_t)mpll_parameters.ulClock.ucPostDiv;

return result;
355}

357int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
			uint32_t clock_value,
			pp_atomctrl_memory_clock_param_ai *mpll_param)
360{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0};
int result;

mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryClockParam
) / sizeof(USHORT)),
	(uint32_t *)&mpll_parameters);

/* VEGAM's mpll takes sometime to finish computing */
udelay(10);

if (!result) {
mpll_param->ulMclk_fcw_int =
	le16_to_cpu(mpll_parameters.usMclk_fcw_int)((__uint16_t)(mpll_parameters.usMclk_fcw_int));
mpll_param->ulMclk_fcw_frac =
	le16_to_cpu(mpll_parameters.usMclk_fcw_frac)((__uint16_t)(mpll_parameters.usMclk_fcw_frac));
mpll_param->ulClock =
	le32_to_cpu(mpll_parameters.ulClock.ulClock)((__uint32_t)(mpll_parameters.ulClock.ulClock));
mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
}

return result;
385}

387int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
			  uint32_t clock_value,
			  pp_atomctrl_clock_dividers_kong *dividers)
390{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
int result;

pll_parameters.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryEnginePLL
) / sizeof(USHORT)),
(uint32_t *)&pll_parameters);

if (0 == result) {
dividers->pll_post_divider = pll_parameters.ucPostDiv;
dividers->real_clock = le32_to_cpu(pll_parameters.ulClock)((__uint32_t)(pll_parameters.ulClock));
}

return result;
407}

409int atomctrl_get_engine_pll_dividers_vi(
struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_clock_dividers_vi *dividers)
413{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
int result;

pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));
pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK0x01;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryEnginePLL
) / sizeof(USHORT)),
(uint32_t *)&pll_patameters);

if (0 == result) {
dividers->pll_post_divider =
	pll_patameters.ulClock.ucPostDiv;
dividers->real_clock =
	le32_to_cpu(pll_patameters.ulClock.ulClock)((__uint32_t)(pll_patameters.ulClock.ulClock));

dividers->ul_fb_div.ul_fb_div_frac =
	le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac)((__uint16_t)(pll_patameters.ulFbDiv.usFbDivFrac));
dividers->ul_fb_div.ul_fb_div =
	le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv)((__uint16_t)(pll_patameters.ulFbDiv.usFbDiv));

dividers->uc_pll_ref_div =
	pll_patameters.ucPllRefDiv;
dividers->uc_pll_post_div =
	pll_patameters.ucPllPostDiv;
dividers->uc_pll_cntl_flag =
	pll_patameters.ucPllCntlFlag;
}

return result;
445}

447int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_clock_dividers_ai *dividers)
450{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
int result;

pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));
pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK0x01;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryEnginePLL
) / sizeof(USHORT)),
(uint32_t *)&pll_patameters);

if (0 == result) {
dividers->usSclk_fcw_frac     = le16_to_cpu(pll_patameters.usSclk_fcw_frac)((__uint16_t)(pll_patameters.usSclk_fcw_frac));
dividers->usSclk_fcw_int      = le16_to_cpu(pll_patameters.usSclk_fcw_int)((__uint16_t)(pll_patameters.usSclk_fcw_int));
dividers->ucSclkPostDiv       = pll_patameters.ucSclkPostDiv;
dividers->ucSclkVcoMode       = pll_patameters.ucSclkVcoMode;
dividers->ucSclkPllRange      = pll_patameters.ucSclkPllRange;
dividers->ucSscEnable         = pll_patameters.ucSscEnable;
dividers->usSsc_fcw1_frac     = le16_to_cpu(pll_patameters.usSsc_fcw1_frac)((__uint16_t)(pll_patameters.usSsc_fcw1_frac));
dividers->usSsc_fcw1_int      = le16_to_cpu(pll_patameters.usSsc_fcw1_int)((__uint16_t)(pll_patameters.usSsc_fcw1_int));
dividers->usPcc_fcw_int       = le16_to_cpu(pll_patameters.usPcc_fcw_int)((__uint16_t)(pll_patameters.usPcc_fcw_int));
dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac)((__uint16_t)(pll_patameters.usSsc_fcw_slew_frac));
dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac)((__uint16_t)(pll_patameters.usPcc_fcw_slew_frac));
}
return result;
476}

478int atomctrl_get_dfs_pll_dividers_vi(
struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_clock_dividers_vi *dividers)
482{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
int result;

pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value)((__uint32_t)(clock_value));
pll_patameters.ulClock.ucPostDiv =
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK0x00;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ComputeMemoryEnginePLL
) / sizeof(USHORT)),
(uint32_t *)&pll_patameters);

if (0 == result) {
dividers->pll_post_divider =
	pll_patameters.ulClock.ucPostDiv;
dividers->real_clock =
	le32_to_cpu(pll_patameters.ulClock.ulClock)((__uint32_t)(pll_patameters.ulClock.ulClock));

dividers->ul_fb_div.ul_fb_div_frac =
	le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac)((__uint16_t)(pll_patameters.ulFbDiv.usFbDivFrac));
dividers->ul_fb_div.ul_fb_div =
	le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv)((__uint16_t)(pll_patameters.ulFbDiv.usFbDiv));

dividers->uc_pll_ref_div =
	pll_patameters.ucPllRefDiv;
dividers->uc_pll_post_div =
	pll_patameters.ucPllPostDiv;
dividers->uc_pll_cntl_flag =
	pll_patameters.ucPllCntlFlag;
}

return result;
515}

517/*
* Get the reference clock in 10KHz
*/
520uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
521{
ATOM_FIRMWARE_INFO *fw_info;
u8 frev, crev;
u16 size;
uint32_t clock;

fw_info = (ATOM_FIRMWARE_INFO *)
smu_atom_get_data_table(hwmgr->adev,
	GetIndexIntoMasterTable(DATA, FirmwareInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, FirmwareInfo
) / sizeof(USHORT)),
	&size, &frev, &crev);

if (fw_info == NULL((void *)0))
clock = 2700;
else
clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock)((__uint16_t)(fw_info->usReferenceClock)));

return clock;
538}

540/*
* Returns true if the given voltage type is controlled by GPIO pins.
* voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC,
* SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
*/
546bool_Bool atomctrl_is_voltage_controlled_by_gpio_v3(
struct pp_hwmgr *hwmgr,
uint8_t voltage_type,
uint8_t voltage_mode)
550{
ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
bool_Bool ret;

PP_ASSERT_WITH_CODE((NULL != voltage_info),do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return 0;;
 } } while (0)
	"Could not find Voltage Table in BIOS.", return false;)do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return 0;;
 } } while (0);

ret = (NULL((void *)0) != atomctrl_lookup_voltage_type_v3
	(voltage_info, voltage_type, voltage_mode)) ? true1 : false0;

return ret;
562}

564int atomctrl_get_voltage_table_v3(
struct pp_hwmgr *hwmgr,
uint8_t voltage_type,
uint8_t voltage_mode,
pp_atomctrl_voltage_table *voltage_table)
569{
ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
unsigned int i;

PP_ASSERT_WITH_CODE((NULL != voltage_info),do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return -1;
; } } while (0)
	"Could not find Voltage Table in BIOS.", return -1;)do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return -1;
; } } while (0);

voltage_object = atomctrl_lookup_voltage_type_v3
(voltage_info, voltage_type, voltage_mode);

if (voltage_object == NULL((void *)0))
return -1;

PP_ASSERT_WITH_CODE(do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0)
	(voltage_object->asGpioVoltageObj.ucGpioEntryNum <=do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0)
	PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES),do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0)
	"Too many voltage entries!",do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0)
	return -1;do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0)
	)do { if (!((voltage_object->asGpioVoltageObj.ucGpioEntryNum
 <= 32))) { printk("\0014" "amdgpu: " "%s\n", "Too many voltage entries!"
); return -1;; } } while (0);

for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) {
voltage_table->entries[i].value =
	le16_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue)((__uint16_t)(voltage_object->asGpioVoltageObj.asVolGpioLut
[i].usVoltageValue));
voltage_table->entries[i].smio_low =
	le32_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId)((__uint32_t)(voltage_object->asGpioVoltageObj.asVolGpioLut
[i].ulVoltageId));
}

voltage_table->mask_low    =
le32_to_cpu(voltage_object->asGpioVoltageObj.ulGpioMaskVal)((__uint32_t)(voltage_object->asGpioVoltageObj.ulGpioMaskVal
));
voltage_table->count      =
voltage_object->asGpioVoltageObj.ucGpioEntryNum;
voltage_table->phase_delay =
voltage_object->asGpioVoltageObj.ucPhaseDelay;

return 0;
606}

608static bool_Bool atomctrl_lookup_gpio_pin(
ATOM_GPIO_PIN_LUT * gpio_lookup_table,
const uint32_t pinId,
pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
612{
unsigned int size = le16_to_cpu(gpio_lookup_table->sHeader.usStructureSize)((__uint16_t)(gpio_lookup_table->sHeader.usStructureSize));
unsigned int offset = offsetof(ATOM_GPIO_PIN_LUT, asGPIO_Pin[0])__builtin_offsetof(ATOM_GPIO_PIN_LUT, asGPIO_Pin[0]);
uint8_t *start = (uint8_t *)gpio_lookup_table;

while (offset < size) {
const ATOM_GPIO_PIN_ASSIGNMENT *pin_assignment =
	(const ATOM_GPIO_PIN_ASSIGNMENT *)(start + offset);

if (pinId == pin_assignment->ucGPIO_ID) {
	gpio_pin_assignment->uc_gpio_pin_bit_shift =
		pin_assignment->ucGpioPinBitShift;
	gpio_pin_assignment->us_gpio_pin_aindex =
		le16_to_cpu(pin_assignment->usGpioPin_AIndex)((__uint16_t)(pin_assignment->usGpioPin_AIndex));
	return true1;
}

offset += offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID)__builtin_offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID) + 1;
}

return false0;
633}

635/*
* Private Function to get the PowerPlay Table Address.
* WARNING: The tabled returned by this function is in
* dynamically allocated memory.
* The caller has to release if by calling kfree.
*/
641static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device)
642{
u8 frev, crev;
u16 size;
void *table_address;

table_address = (ATOM_GPIO_PIN_LUT *)
smu_atom_get_data_table(device,
		GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, GPIO_Pin_LUT
) / sizeof(USHORT)),
		&size, &frev, &crev);

PP_ASSERT_WITH_CODE((NULL != table_address),do { if (!((((void *)0) != table_address))) { printk("\0014" "amdgpu: "
 "%s\n", "Error retrieving BIOS Table Address!"); return ((void
 *)0);; } } while (0)
	"Error retrieving BIOS Table Address!", return NULL;)do { if (!((((void *)0) != table_address))) { printk("\0014" "amdgpu: "
 "%s\n", "Error retrieving BIOS Table Address!"); return ((void
 *)0);; } } while (0);

return (ATOM_GPIO_PIN_LUT *)table_address;
656}

658/*
* Returns 1 if the given pin id find in lookup table.
*/
661bool_Bool atomctrl_get_pp_assign_pin(
struct pp_hwmgr *hwmgr,
const uint32_t pinId,
pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
665{
bool_Bool bRet = false0;
ATOM_GPIO_PIN_LUT *gpio_lookup_table =
get_gpio_lookup_table(hwmgr->adev);

PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),do { if (!((((void *)0) != gpio_lookup_table))) { printk("\0014"
 "amdgpu: " "%s\n", "Could not find GPIO lookup Table in BIOS."
); return 0; } } while (0)
	"Could not find GPIO lookup Table in BIOS.", return false)do { if (!((((void *)0) != gpio_lookup_table))) { printk("\0014"
 "amdgpu: " "%s\n", "Could not find GPIO lookup Table in BIOS."
); return 0; } } while (0);

bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId,
gpio_pin_assignment);

return bRet;
677}

679int atomctrl_calculate_voltage_evv_on_sclk(
struct pp_hwmgr *hwmgr,
uint8_t voltage_type,
uint32_t sclk,
uint16_t virtual_voltage_Id,
uint16_t *voltage,
uint16_t dpm_level,
bool_Bool debug)
687{
ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
struct amdgpu_device *adev = hwmgr->adev;
EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
EFUSE_LOGISTIC_FUNC_PARAM sKt_Beta_fuse;
EFUSE_LOGISTIC_FUNC_PARAM sKv_m_fuse;
EFUSE_LOGISTIC_FUNC_PARAM sKv_b_fuse;
EFUSE_INPUT_PARAMETER sInput_FuseValues;
READ_EFUSE_VALUE_PARAMETER sOutput_FuseValues;

uint32_t ul_RO_fused, ul_CACb_fused, ul_CACm_fused, ul_Kt_Beta_fused, ul_Kv_m_fused, ul_Kv_b_fused;
fInt fSM_A0, fSM_A1, fSM_A2, fSM_A3, fSM_A4, fSM_A5, fSM_A6, fSM_A7;
fInt fMargin_RO_a, fMargin_RO_b, fMargin_RO_c, fMargin_fixed, fMargin_FMAX_mean, fMargin_Plat_mean, fMargin_FMAX_sigma, fMargin_Plat_sigma, fMargin_DC_sigma;
fInt fLkg_FT, repeat;
fInt fMicro_FMAX, fMicro_CR, fSigma_FMAX, fSigma_CR, fSigma_DC, fDC_SCLK, fSquared_Sigma_DC, fSquared_Sigma_CR, fSquared_Sigma_FMAX;
fInt fRLL_LoadLine, fDerateTDP, fVDDC_base, fA_Term, fC_Term, fB_Term, fRO_DC_margin;
fInt fRO_fused, fCACm_fused, fCACb_fused, fKv_m_fused, fKv_b_fused, fKt_Beta_fused, fFT_Lkg_V0NORM;
fInt fSclk_margin, fSclk, fEVV_V;
fInt fV_min, fV_max, fT_prod, fLKG_Factor, fT_FT, fV_FT, fV_x, fTDP_Power, fTDP_Power_right, fTDP_Power_left, fTDP_Current, fV_NL;
uint32_t ul_FT_Lkg_V0NORM;
fInt fLn_MaxDivMin, fMin, fAverage, fRange;
fInt fRoots[2];
fInt fStepSize = GetScaledFraction(625, 100000);

int result;

getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
	smu_atom_get_data_table(hwmgr->adev,
			GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, ASIC_ProfilingInfo
) / sizeof(USHORT)),
			NULL((void *)0), NULL((void *)0), NULL((void *)0));

if (!getASICProfilingInfo)
1
Assuming 'getASICProfilingInfo' is non-null→
return -1;

if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
2
←
Assuming field 'ucTableFormatRevision' is >= 3→
   (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 &&
3
←
Assuming field 'ucTableFormatRevision' is not equal to 3→
    getASICProfilingInfo->asHeader.ucTableContentRevision < 4))
return -1;

/*-----------------------------------------------------------
*GETTING MULTI-STEP PARAMETERS RELATED TO CURRENT DPM LEVEL
*-----------------------------------------------------------
*/
fRLL_LoadLine = Divide(getASICProfilingInfo->ulLoadLineSlop, 1000);

switch (dpm_level) {
4
←
Control jumps to the 'default' case at line 756→
case 1:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM1)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM1)), 1000);
break;
case 2:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM2)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM2)), 1000);
break;
case 3:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM3)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM3)), 1000);
break;
case 4:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM4)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM4)), 1000);
break;
case 5:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM5)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM5)), 1000);
break;
case 6:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM6)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM6)), 1000);
break;
case 7:
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM7)), 1000);
break;
default:
pr_err("DPM Level not supported\n")printk("\0013" "amdgpu: " "DPM Level not supported\n");
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0)((__uint32_t)(getASICProfilingInfo->ulTdpDerateDPM0)), 1000);
}

/*-------------------------
* DECODING FUSE VALUES
* ------------------------
*/
/*Decode RO_Fused*/
sRO_fuse = getASICProfilingInfo->sRoFuse;

sInput_FuseValues.usEfuseIndex = sRO_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sRO_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sRO_fuse.ucEfuseLength;

sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
5
←
Assuming 'result' is 0→
6
←
Taking false branch→
return result;

/* Finally, the actual fuse value */
ul_RO_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fMin = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseMin)((__uint32_t)(sRO_fuse.ulEfuseMin)), 1);
fRange = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseEncodeRange)((__uint32_t)(sRO_fuse.ulEfuseEncodeRange)), 1);
fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength);

sCACm_fuse = getASICProfilingInfo->sCACm;

sInput_FuseValues.usEfuseIndex = sCACm_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sCACm_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sCACm_fuse.ucEfuseLength;

sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
7
←
Assuming 'result' is 0→
8
←
Taking false branch→
return result;

ul_CACm_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fMin = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseMin)((__uint32_t)(sCACm_fuse.ulEfuseMin)), 1000);
fRange = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseEncodeRange)((__uint32_t)(sCACm_fuse.ulEfuseEncodeRange)), 1000);

fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength);

sCACb_fuse = getASICProfilingInfo->sCACb;

sInput_FuseValues.usEfuseIndex = sCACb_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sCACb_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
9
←
Assuming 'result' is 0→
10
←
Taking false branch→
return result;

ul_CACb_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fMin = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseMin)((__uint32_t)(sCACb_fuse.ulEfuseMin)), 1000);
fRange = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseEncodeRange)((__uint32_t)(sCACb_fuse.ulEfuseEncodeRange)), 1000);

fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength);

sKt_Beta_fuse = getASICProfilingInfo->sKt_b;

sInput_FuseValues.usEfuseIndex = sKt_Beta_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sKt_Beta_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sKt_Beta_fuse.ucEfuseLength;

sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
11
←
Assuming 'result' is 0→
12
←
Taking false branch→
return result;

ul_Kt_Beta_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fAverage = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeAverage)((__uint32_t)(sKt_Beta_fuse.ulEfuseEncodeAverage)), 1000);
fRange = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeRange)((__uint32_t)(sKt_Beta_fuse.ulEfuseEncodeRange)), 1000);

fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused,
13
←
Calling 'fDecodeLogisticFuse'→
	fAverage, fRange, sKt_Beta_fuse.ucEfuseLength);

sKv_m_fuse = getASICProfilingInfo->sKv_m;

sInput_FuseValues.usEfuseIndex = sKv_m_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sKv_m_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sKv_m_fuse.ucEfuseLength;

sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);
if (result)
return result;

ul_Kv_m_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fAverage = GetScaledFraction(le32_to_cpu(sKv_m_fuse.ulEfuseEncodeAverage)((__uint32_t)(sKv_m_fuse.ulEfuseEncodeAverage)), 1000);
fRange = GetScaledFraction((le32_to_cpu(sKv_m_fuse.ulEfuseEncodeRange)((__uint32_t)(sKv_m_fuse.ulEfuseEncodeRange)) & 0x7fffffff), 1000);
fRange = fMultiply(fRange, ConvertToFraction(-1));

fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused,
	fAverage, fRange, sKv_m_fuse.ucEfuseLength);

sKv_b_fuse = getASICProfilingInfo->sKv_b;

sInput_FuseValues.usEfuseIndex = sKv_b_fuse.usEfuseIndex;
sInput_FuseValues.ucBitShift = sKv_b_fuse.ucEfuseBitLSB;
sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
return result;

ul_Kv_b_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fAverage = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeAverage)((__uint32_t)(sKv_b_fuse.ulEfuseEncodeAverage)), 1000);
fRange = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeRange)((__uint32_t)(sKv_b_fuse.ulEfuseEncodeRange)), 1000);

fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused,
	fAverage, fRange, sKv_b_fuse.ucEfuseLength);

/* Decoding the Leakage - No special struct container */
/*
* usLkgEuseIndex=56
* ucLkgEfuseBitLSB=6
* ucLkgEfuseLength=10
* ulLkgEncodeLn_MaxDivMin=69077
* ulLkgEncodeMax=1000000
* ulLkgEncodeMin=1000
* ulEfuseLogisticAlpha=13
*/

sInput_FuseValues.usEfuseIndex = getASICProfilingInfo->usLkgEuseIndex;
sInput_FuseValues.ucBitShift = getASICProfilingInfo->ucLkgEfuseBitLSB;
sInput_FuseValues.ucBitLength = getASICProfilingInfo->ucLkgEfuseLength;

sOutput_FuseValues.sEfuse = sInput_FuseValues;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&sOutput_FuseValues);

if (result)
return result;

ul_FT_Lkg_V0NORM = le32_to_cpu(sOutput_FuseValues.ulEfuseValue)((__uint32_t)(sOutput_FuseValues.ulEfuseValue));
fLn_MaxDivMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin)((__uint32_t)(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin
)), 10000);
fMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeMin)((__uint32_t)(getASICProfilingInfo->ulLkgEncodeMin)), 10000);

fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM,
	fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength);
fLkg_FT = fFT_Lkg_V0NORM;

/*-------------------------------------------
* PART 2 - Grabbing all required values
*-------------------------------------------
*/
fSM_A0 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A0)((__uint32_t)(getASICProfilingInfo->ulSM_A0)), 1000000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign)));
fSM_A1 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A1)((__uint32_t)(getASICProfilingInfo->ulSM_A1)), 1000000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign)));
fSM_A2 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A2)((__uint32_t)(getASICProfilingInfo->ulSM_A2)), 100000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign)));
fSM_A3 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A3)((__uint32_t)(getASICProfilingInfo->ulSM_A3)), 1000000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign)));
fSM_A4 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A4)((__uint32_t)(getASICProfilingInfo->ulSM_A4)), 1000000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign)));
fSM_A5 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A5)((__uint32_t)(getASICProfilingInfo->ulSM_A5)), 1000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign)));
fSM_A6 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A6)((__uint32_t)(getASICProfilingInfo->ulSM_A6)), 1000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign)));
fSM_A7 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A7)((__uint32_t)(getASICProfilingInfo->ulSM_A7)), 1000),
	ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign)));

fMargin_RO_a = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_a)((__uint32_t)(getASICProfilingInfo->ulMargin_RO_a)));
fMargin_RO_b = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_b)((__uint32_t)(getASICProfilingInfo->ulMargin_RO_b)));
fMargin_RO_c = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_c)((__uint32_t)(getASICProfilingInfo->ulMargin_RO_c)));

fMargin_fixed = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_fixed)((__uint32_t)(getASICProfilingInfo->ulMargin_fixed)));

fMargin_FMAX_mean = GetScaledFraction(
le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_mean)((__uint32_t)(getASICProfilingInfo->ulMargin_Fmax_mean)), 10000);
fMargin_Plat_mean = GetScaledFraction(
le32_to_cpu(getASICProfilingInfo->ulMargin_plat_mean)((__uint32_t)(getASICProfilingInfo->ulMargin_plat_mean)), 10000);
fMargin_FMAX_sigma = GetScaledFraction(
le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_sigma)((__uint32_t)(getASICProfilingInfo->ulMargin_Fmax_sigma)), 10000);
fMargin_Plat_sigma = GetScaledFraction(
le32_to_cpu(getASICProfilingInfo->ulMargin_plat_sigma)((__uint32_t)(getASICProfilingInfo->ulMargin_plat_sigma)), 10000);

fMargin_DC_sigma = GetScaledFraction(
le32_to_cpu(getASICProfilingInfo->ulMargin_DC_sigma)((__uint32_t)(getASICProfilingInfo->ulMargin_DC_sigma)), 100);
fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000));

fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100));
fCACb_fused = fDivide(fCACb_fused, ConvertToFraction(100));
fKt_Beta_fused = fDivide(fKt_Beta_fused, ConvertToFraction(100));
fKv_m_fused =  fNegate(fDivide(fKv_m_fused, ConvertToFraction(100)));
fKv_b_fused = fDivide(fKv_b_fused, ConvertToFraction(10));

fSclk = GetScaledFraction(sclk, 100);

fV_max = fDivide(GetScaledFraction(
		 le32_to_cpu(getASICProfilingInfo->ulMaxVddc)((__uint32_t)(getASICProfilingInfo->ulMaxVddc)), 1000), ConvertToFraction(4));
fT_prod = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulBoardCoreTemp)((__uint32_t)(getASICProfilingInfo->ulBoardCoreTemp)), 10);
fLKG_Factor = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulEvvLkgFactor)((__uint32_t)(getASICProfilingInfo->ulEvvLkgFactor)), 100);
fT_FT = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLeakageTemp)((__uint32_t)(getASICProfilingInfo->ulLeakageTemp)), 10);
fV_FT = fDivide(GetScaledFraction(
		le32_to_cpu(getASICProfilingInfo->ulLeakageVoltage)((__uint32_t)(getASICProfilingInfo->ulLeakageVoltage)), 1000), ConvertToFraction(4));
fV_min = fDivide(GetScaledFraction(
		 le32_to_cpu(getASICProfilingInfo->ulMinVddc)((__uint32_t)(getASICProfilingInfo->ulMinVddc)), 1000), ConvertToFraction(4));

/*-----------------------
* PART 3
*-----------------------
*/

fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5));
fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b);
fC_Term = fAdd(fMargin_RO_c,
	fAdd(fMultiply(fSM_A0, fLkg_FT),
	fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)),
	fAdd(fMultiply(fSM_A3, fSclk),
	fSubtract(fSM_A7, fRO_fused)))));

fVDDC_base = fSubtract(fRO_fused,
	fSubtract(fMargin_RO_c,
			fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk))));
fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0, fSclk), fSM_A2));

repeat = fSubtract(fVDDC_base,
	fDivide(fMargin_DC_sigma, ConvertToFraction(1000)));

fRO_DC_margin = fAdd(fMultiply(fMargin_RO_a,
	fGetSquare(repeat)),
	fAdd(fMultiply(fMargin_RO_b, repeat),
	fMargin_RO_c));

fDC_SCLK = fSubtract(fRO_fused,
	fSubtract(fRO_DC_margin,
	fSubtract(fSM_A3,
	fMultiply(fSM_A2, repeat))));
fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0, repeat), fSM_A1));

fSigma_DC = fSubtract(fSclk, fDC_SCLK);

fMicro_FMAX = fMultiply(fSclk, fMargin_FMAX_mean);
fMicro_CR = fMultiply(fSclk, fMargin_Plat_mean);
fSigma_FMAX = fMultiply(fSclk, fMargin_FMAX_sigma);
fSigma_CR = fMultiply(fSclk, fMargin_Plat_sigma);

fSquared_Sigma_DC = fGetSquare(fSigma_DC);
fSquared_Sigma_CR = fGetSquare(fSigma_CR);
fSquared_Sigma_FMAX = fGetSquare(fSigma_FMAX);

fSclk_margin = fAdd(fMicro_FMAX,
	fAdd(fMicro_CR,
	fAdd(fMargin_fixed,
	fSqrt(fAdd(fSquared_Sigma_FMAX,
	fAdd(fSquared_Sigma_DC, fSquared_Sigma_CR))))));
/*
fA_Term = fSM_A4 * (fSclk + fSclk_margin) + fSM_A5;
fB_Term = fSM_A2 * (fSclk + fSclk_margin) + fSM_A6;
fC_Term = fRO_DC_margin + fSM_A0 * fLkg_FT + fSM_A1 * fLkg_FT * (fSclk + fSclk_margin) + fSM_A3 * (fSclk + fSclk_margin) + fSM_A7 - fRO_fused;
*/

fA_Term = fAdd(fMultiply(fSM_A4, fAdd(fSclk, fSclk_margin)), fSM_A5);
fB_Term = fAdd(fMultiply(fSM_A2, fAdd(fSclk, fSclk_margin)), fSM_A6);
fC_Term = fAdd(fRO_DC_margin,
	fAdd(fMultiply(fSM_A0, fLkg_FT),
	fAdd(fMultiply(fMultiply(fSM_A1, fLkg_FT),
	fAdd(fSclk, fSclk_margin)),
	fAdd(fMultiply(fSM_A3,
	fAdd(fSclk, fSclk_margin)),
	fSubtract(fSM_A7, fRO_fused)))));

SolveQuadracticEqn(fA_Term, fB_Term, fC_Term, fRoots);

if (GreaterThan(fRoots[0], fRoots[1]))
fEVV_V = fRoots[1];
else
fEVV_V = fRoots[0];

if (GreaterThan(fV_min, fEVV_V))
fEVV_V = fV_min;
else if (GreaterThan(fEVV_V, fV_max))
fEVV_V = fSubtract(fV_max, fStepSize);

fEVV_V = fRoundUpByStepSize(fEVV_V, fStepSize, 0);

/*-----------------
* PART 4
*-----------------
*/

fV_x = fV_min;

while (GreaterThan(fAdd(fV_max, fStepSize), fV_x)) {
fTDP_Power_left = fMultiply(fMultiply(fMultiply(fAdd(
		fMultiply(fCACm_fused, fV_x), fCACb_fused), fSclk),
		fGetSquare(fV_x)), fDerateTDP);

fTDP_Power_right = fMultiply(fFT_Lkg_V0NORM, fMultiply(fLKG_Factor,
		fMultiply(fExponential(fMultiply(fAdd(fMultiply(fKv_m_fused,
		fT_prod), fKv_b_fused), fV_x)), fV_x)));
fTDP_Power_right = fMultiply(fTDP_Power_right, fExponential(fMultiply(
		fKt_Beta_fused, fT_prod)));
fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
		fAdd(fMultiply(fKv_m_fused, fT_prod), fKv_b_fused), fV_FT)));
fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
		fKt_Beta_fused, fT_FT)));

fTDP_Power = fAdd(fTDP_Power_left, fTDP_Power_right);

fTDP_Current = fDivide(fTDP_Power, fV_x);

fV_NL = fAdd(fV_x, fDivide(fMultiply(fTDP_Current, fRLL_LoadLine),
		ConvertToFraction(10)));

fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0);

if (GreaterThan(fV_max, fV_NL) &&
	(GreaterThan(fV_NL, fEVV_V) ||
	Equal(fV_NL, fEVV_V))) {
	fV_NL = fMultiply(fV_NL, ConvertToFraction(1000));

	*voltage = (uint16_t)fV_NL.partial.real;
	break;
} else
	fV_x = fAdd(fV_x, fStepSize);
}

return result;
1104}

1106/**
* atomctrl_get_voltage_evv_on_sclk: gets voltage via call to ATOM COMMAND table.
* @hwmgr:              input: pointer to hwManager
* @voltage_type:       input: type of EVV voltage VDDC or VDDGFX
* @sclk:               input: in 10Khz unit. DPM state SCLK frequency
*		         which is define in PPTable SCLK/VDDC dependence
*			 table associated with this virtual_voltage_Id
* @virtual_voltage_Id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
* @voltage: 	        output: real voltage level in unit of mv
*/
1116int atomctrl_get_voltage_evv_on_sclk(
struct pp_hwmgr *hwmgr,
uint8_t voltage_type,
uint32_t sclk, uint16_t virtual_voltage_Id,
uint16_t *voltage)
1121{
struct amdgpu_device *adev = hwmgr->adev;
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
int result;

get_voltage_info_param_space.ucVoltageType   =
voltage_type;
get_voltage_info_param_space.ucVoltageMode   =
ATOM_GET_VOLTAGE_EVV_VOLTAGE0x09;
get_voltage_info_param_space.usVoltageLevel  =
cpu_to_le16(virtual_voltage_Id)((__uint16_t)(virtual_voltage_Id));
get_voltage_info_param_space.ulSCLKFreq      =
cpu_to_le32(sclk)((__uint32_t)(sclk));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, GetVoltageInfo
) / sizeof(USHORT)),
	(uint32_t *)&get_voltage_info_param_space);

*voltage = result ? 0 :
	le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)((__uint16_t)(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
 (&get_voltage_info_param_space))->usVoltageLevel))
		(&get_voltage_info_param_space))->usVoltageLevel)((__uint16_t)(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
 (&get_voltage_info_param_space))->usVoltageLevel));

return result;
1144}

1146/**
* atomctrl_get_voltage_evv: gets voltage via call to ATOM COMMAND table.
* @hwmgr:              input: pointer to hwManager
* @virtual_voltage_id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
* @voltage: 	       output: real voltage level in unit of mv
*/
1152int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
	     uint16_t virtual_voltage_id,
	     uint16_t *voltage)
1155{
struct amdgpu_device *adev = hwmgr->adev;
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
int result;
int entry_id;

/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
	/* found */
	break;
}
}

if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
       pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n")do { } while(0);
       return -EINVAL22;
}

get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC1;
get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE0x09;
get_voltage_info_param_space.usVoltageLevel = virtual_voltage_id;
get_voltage_info_param_space.ulSCLKFreq =
cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk)((__uint32_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->
entries[entry_id].clk));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, GetVoltageInfo
) / sizeof(USHORT)),
	(uint32_t *)&get_voltage_info_param_space);

if (0 != result)
return result;

*voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)((__uint16_t)(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
 (&get_voltage_info_param_space))->usVoltageLevel))
		(&get_voltage_info_param_space))->usVoltageLevel)((__uint16_t)(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
 (&get_voltage_info_param_space))->usVoltageLevel));

return result;
1191}

1193/*
* Get the mpll reference clock in 10KHz
*/
1196uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
1197{
ATOM_COMMON_TABLE_HEADER *fw_info;
uint32_t clock;
u8 frev, crev;
u16 size;

fw_info = (ATOM_COMMON_TABLE_HEADER *)
smu_atom_get_data_table(hwmgr->adev,
		GetIndexIntoMasterTable(DATA, FirmwareInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, FirmwareInfo
) / sizeof(USHORT)),
		&size, &frev, &crev);

if (fw_info == NULL((void *)0))
clock = 2700;
else {
if ((fw_info->ucTableFormatRevision == 2) &&
	(le16_to_cpu(fw_info->usStructureSize)((__uint16_t)(fw_info->usStructureSize)) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) {
	ATOM_FIRMWARE_INFO_V2_1 *fwInfo_2_1 =
		(ATOM_FIRMWARE_INFO_V2_1 *)fw_info;
	clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock)((__uint16_t)(fwInfo_2_1->usMemoryReferenceClock)));
} else {
	ATOM_FIRMWARE_INFO *fwInfo_0_0 =
		(ATOM_FIRMWARE_INFO *)fw_info;
	clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock)((__uint16_t)(fwInfo_0_0->usReferenceClock)));
}
}

return clock;
1224}

1226/*
* Get the asic internal spread spectrum table
*/
1229static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
1230{
ATOM_ASIC_INTERNAL_SS_INFO *table = NULL((void *)0);
u8 frev, crev;
u16 size;

table = (ATOM_ASIC_INTERNAL_SS_INFO *)
smu_atom_get_data_table(device,
	GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, ASIC_InternalSS_Info
) / sizeof(USHORT)),
	&size, &frev, &crev);

return table;
1241}

1243bool_Bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr)
1244{
ATOM_ASIC_INTERNAL_SS_INFO *table =
asic_internal_ss_get_ss_table(hwmgr->adev);

if (table)
return true1;
else
return false0;
1252}

1254/*
* Get the asic internal spread spectrum assignment
*/
1257static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
const uint8_t clockSource,
const uint32_t clockSpeed,
pp_atomctrl_internal_ss_info *ssEntry)
1261{
ATOM_ASIC_INTERNAL_SS_INFO *table;
ATOM_ASIC_SS_ASSIGNMENT *ssInfo;
int entry_found = 0;

memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info))__builtin_memset((ssEntry), (0x00), (sizeof(pp_atomctrl_internal_ss_info
)));

table = asic_internal_ss_get_ss_table(hwmgr->adev);

if (NULL((void *)0) == table)
return -1;

ssInfo = &table->asSpreadSpectrum[0];

while (((uint8_t *)ssInfo - (uint8_t *)table) <
le16_to_cpu(table->sHeader.usStructureSize)((__uint16_t)(table->sHeader.usStructureSize))) {
if ((clockSource == ssInfo->ucClockIndication) &&
	((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange)((__uint32_t)(ssInfo->ulTargetClockRange)))) {
	entry_found = 1;
	break;
}

ssInfo = (ATOM_ASIC_SS_ASSIGNMENT *)((uint8_t *)ssInfo +
		sizeof(ATOM_ASIC_SS_ASSIGNMENT));
}

if (entry_found) {
ssEntry->speed_spectrum_percentage =
	le16_to_cpu(ssInfo->usSpreadSpectrumPercentage)((__uint16_t)(ssInfo->usSpreadSpectrumPercentage));
ssEntry->speed_spectrum_rate = le16_to_cpu(ssInfo->usSpreadRateInKhz)((__uint16_t)(ssInfo->usSpreadRateInKhz));

if (((GET_DATA_TABLE_MAJOR_REVISION(table)((((ATOM_COMMON_TABLE_HEADER*)table)->ucTableFormatRevision
)&0x3F) == 2) &&
	(GET_DATA_TABLE_MINOR_REVISION(table)((((ATOM_COMMON_TABLE_HEADER*)table)->ucTableContentRevision
)&0x3F) >= 2)) ||
	(GET_DATA_TABLE_MAJOR_REVISION(table)((((ATOM_COMMON_TABLE_HEADER*)table)->ucTableFormatRevision
)&0x3F) == 3)) {
	ssEntry->speed_spectrum_rate /= 100;
}

switch (ssInfo->ucSpreadSpectrumMode) {
case 0:
	ssEntry->speed_spectrum_mode =
		pp_atomctrl_spread_spectrum_mode_down;
	break;
case 1:
	ssEntry->speed_spectrum_mode =
		pp_atomctrl_spread_spectrum_mode_center;
	break;
default:
	ssEntry->speed_spectrum_mode =
		pp_atomctrl_spread_spectrum_mode_down;
	break;
}
}

return entry_found ? 0 : 1;
1315}

1317/*
* Get the memory clock spread spectrum info
*/
1320int atomctrl_get_memory_clock_spread_spectrum(
struct pp_hwmgr *hwmgr,
const uint32_t memory_clock,
pp_atomctrl_internal_ss_info *ssInfo)
1324{
return asic_internal_ss_get_ss_asignment(hwmgr,
	ASIC_INTERNAL_MEMORY_SS1, memory_clock, ssInfo);
1327}

1329/*
* Get the engine clock spread spectrum info
*/
1332int atomctrl_get_engine_clock_spread_spectrum(
struct pp_hwmgr *hwmgr,
const uint32_t engine_clock,
pp_atomctrl_internal_ss_info *ssInfo)
1336{
return asic_internal_ss_get_ss_asignment(hwmgr,
	ASIC_INTERNAL_ENGINE_SS2, engine_clock, ssInfo);
1339}

1341int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
uint16_t end_index, uint32_t *efuse)
1343{
struct amdgpu_device *adev = hwmgr->adev;
uint32_t mask;
int result;
READ_EFUSE_VALUE_PARAMETER efuse_param;

if ((end_index - start_index)  == 31)
mask = 0xFFFFFFFF;
else
mask = (1 << ((end_index - start_index) + 1)) - 1;

efuse_param.sEfuse.usEfuseIndex = cpu_to_le16((start_index / 32) * 4)((__uint16_t)((start_index / 32) * 4));
efuse_param.sEfuse.ucBitShift = (uint8_t)
	(start_index - ((start_index / 32) * 32));
efuse_param.sEfuse.ucBitLength  = (uint8_t)
	((end_index - start_index) + 1);

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, ReadEfuseValue)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, ReadEfuseValue
) / sizeof(USHORT)),
	(uint32_t *)&efuse_param);
*efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue)((__uint32_t)(efuse_param.ulEfuseValue)) & mask;

return result;
1366}

1368int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
	      uint8_t level)
1370{
struct amdgpu_device *adev = hwmgr->adev;
DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
int result;

memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq =
memory_clock & SET_CLOCK_FREQ_MASK0x00FFFFFF;
memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag =
ADJUST_MC_SETTING_PARAM3;
memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, DynamicMemorySettings
) / sizeof(USHORT)),
(uint32_t *)&memory_clock_parameters);

return result;
1386}

1388int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
1390{
struct amdgpu_device *adev = hwmgr->adev;
int result;
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;

get_voltage_info_param_space.ucVoltageType = voltage_type;
get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE0x09;
get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id)((__uint16_t)(virtual_voltage_Id));
get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk)((__uint32_t)(sclk));

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, GetVoltageInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, GetVoltageInfo
) / sizeof(USHORT)),
	(uint32_t *)&get_voltage_info_param_space);

*voltage = result ? 0 :
le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel)((__uint32_t)(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)
(&get_voltage_info_param_space))->ulVoltageLevel));

return result;
1408}

1410int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table)
1411{

int i;
u8 frev, crev;
u16 size;

ATOM_SMU_INFO_V2_1 *psmu_info =
(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
	GetIndexIntoMasterTable(DATA, SMU_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, SMU_Info
) / sizeof(USHORT)),
	&size, &frev, &crev);


for (i = 0; i < psmu_info->ucSclkEntryNum; i++) {
table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting;
table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv;
table->entry[i].usFcw_pcc =
	le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc)((__uint16_t)(psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc)
);
table->entry[i].usFcw_trans_upper =
	le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper)((__uint16_t)(psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper
));
table->entry[i].usRcw_trans_lower =
	le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower)((__uint16_t)(psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower
));
}

return 0;
1435}

1437int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail)
1438{
ATOM_SMU_INFO_V2_1 *psmu_info =
(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
	GetIndexIntoMasterTable(DATA, SMU_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, SMU_Info
) / sizeof(USHORT)),
	NULL((void *)0), NULL((void *)0), NULL((void *)0));
if (!psmu_info)
return -1;

*shared_rail = psmu_info->ucSharePowerSource;

return 0;
1449}

1451int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
		  struct pp_atom_ctrl__avfs_parameters *param)
1453{
ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL((void *)0);

if (param == NULL((void *)0))
return -EINVAL22;

profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
	smu_atom_get_data_table(hwmgr->adev,
			GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, ASIC_ProfilingInfo
) / sizeof(USHORT)),
			NULL((void *)0), NULL((void *)0), NULL((void *)0));
if (!profile)
return -1;

param->ulAVFS_meanNsigma_Acontant0 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant0)((__uint32_t)(profile->ulAVFS_meanNsigma_Acontant0));
param->ulAVFS_meanNsigma_Acontant1 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant1)((__uint32_t)(profile->ulAVFS_meanNsigma_Acontant1));
param->ulAVFS_meanNsigma_Acontant2 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant2)((__uint32_t)(profile->ulAVFS_meanNsigma_Acontant2));
param->usAVFS_meanNsigma_DC_tol_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_DC_tol_sigma)((__uint16_t)(profile->usAVFS_meanNsigma_DC_tol_sigma));
param->usAVFS_meanNsigma_Platform_mean = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_mean)((__uint16_t)(profile->usAVFS_meanNsigma_Platform_mean));
param->usAVFS_meanNsigma_Platform_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_sigma)((__uint16_t)(profile->usAVFS_meanNsigma_Platform_sigma));
param->ulGB_VDROOP_TABLE_CKSOFF_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a0)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSOFF_a0));
param->ulGB_VDROOP_TABLE_CKSOFF_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a1)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSOFF_a1));
param->ulGB_VDROOP_TABLE_CKSOFF_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a2)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSOFF_a2));
param->ulGB_VDROOP_TABLE_CKSON_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a0)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSON_a0));
param->ulGB_VDROOP_TABLE_CKSON_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a1)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSON_a1));
param->ulGB_VDROOP_TABLE_CKSON_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a2)((__uint32_t)(profile->ulGB_VDROOP_TABLE_CKSON_a2));
param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1)((__uint32_t)(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1));
param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2)((__uint16_t)(profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2));
param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b)((__uint32_t)(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b));
param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_m1)((__uint32_t)(profile->ulAVFSGB_FUSE_TABLE_CKSON_m1));
param->usAVFSGB_FUSE_TABLE_CKSON_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSON_m2)((__uint16_t)(profile->usAVFSGB_FUSE_TABLE_CKSON_m2));
param->ulAVFSGB_FUSE_TABLE_CKSON_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_b)((__uint32_t)(profile->ulAVFSGB_FUSE_TABLE_CKSON_b));
param->usMaxVoltage_0_25mv = le16_to_cpu(profile->usMaxVoltage_0_25mv)((__uint16_t)(profile->usMaxVoltage_0_25mv));
param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF;
param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON;
param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF;
param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON;
param->usPSM_Age_ComFactor = le16_to_cpu(profile->usPSM_Age_ComFactor)((__uint16_t)(profile->usPSM_Age_ComFactor));
param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage;

return 0;
1493}

1495int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
		uint16_t *load_line)
1498{
ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);

const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;

PP_ASSERT_WITH_CODE((NULL != voltage_info),do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return -22
; } } while (0)
	"Could not find Voltage Table in BIOS.", return -EINVAL)do { if (!((((void *)0) != voltage_info))) { printk("\0014" "amdgpu: "
 "%s\n", "Could not find Voltage Table in BIOS."); return -22
; } } while (0);

voltage_object = atomctrl_lookup_voltage_type_v3
(voltage_info, voltage_type,  VOLTAGE_OBJ_SVID27);

*svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId;
*svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId;
*load_line = voltage_object->asSVID2Obj.usLoadLine_PSI;

return 0;
1515}

1517int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
1518{
struct amdgpu_device *adev = hwmgr->adev;
SET_VOLTAGE_PS_ALLOCATION allocation;
SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
	(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
int result;

voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID8;

result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
	GetIndexIntoMasterTable(COMMAND, SetVoltage)(__builtin_offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, SetVoltage
) / sizeof(USHORT)),
	(uint32_t *)voltage_parameters);

*virtual_voltage_id = voltage_parameters->usVoltageLevel;

return result;
1534}

1536int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
			uint16_t *vddc, uint16_t *vddci,
			uint16_t virtual_voltage_id,
			uint16_t efuse_voltage_id)
1540{
int i, j;
int ix;
u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
ATOM_ASIC_PROFILING_INFO_V2_1 *profile;

*vddc = 0;
*vddci = 0;

ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, ASIC_ProfilingInfo
) / sizeof(USHORT));

profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
	smu_atom_get_data_table(hwmgr->adev,
			ix,
			NULL((void *)0), NULL((void *)0), NULL((void *)0));
if (!profile)
return -EINVAL22;

if ((profile->asHeader.ucTableFormatRevision >= 2) &&
(profile->asHeader.ucTableContentRevision >= 1) &&
(profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
if (profile->ucElbVDDC_Num > 0) {
	for (i = 0; i < profile->ucElbVDDC_Num; i++) {
		if (vddc_id_buf[i] == virtual_voltage_id) {
			for (j = 0; j < profile->ucLeakageBinNum; j++) {
				if (efuse_voltage_id <= leakage_bin[j]) {
					*vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
					break;
				}
			}
			break;
		}
	}
}

vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
vddci_buf   = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
if (profile->ucElbVDDCI_Num > 0) {
	for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
		if (vddci_id_buf[i] == virtual_voltage_id) {
			for (j = 0; j < profile->ucLeakageBinNum; j++) {
				if (efuse_voltage_id <= leakage_bin[j]) {
					*vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
					break;
				}
			}
			break;
		}
	}
}
}

return 0;
1596}

1598void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
					uint32_t *min_vddc)
1600{
void *profile;

profile = smu_atom_get_data_table(hwmgr->adev,
			GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, ASIC_ProfilingInfo
) / sizeof(USHORT)),
			NULL((void *)0), NULL((void *)0), NULL((void *)0));

if (profile) {
switch (hwmgr->chip_id) {
case CHIP_TONGA:
case CHIP_FIJI:
	*max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMaxVddc)((__uint32_t)(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->
ulMaxVddc)) / 4;
	*min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMinVddc)((__uint32_t)(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->
ulMinVddc)) / 4;
	return;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
	*max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMaxVddc)((__uint32_t)(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->
ulMaxVddc)) / 100;
	*min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMinVddc)((__uint32_t)(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->
ulMinVddc)) / 100;
	return;
default:
	break;
}
}
*max_vddc = 0;
*min_vddc = 0;
1626}

1628int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
			       AtomCtrl_HiLoLeakageOffsetTable *table)
1630{
ATOM_GFX_INFO_V2_3 *gfxinfo = smu_atom_get_data_table(hwmgr->adev,
			GetIndexIntoMasterTable(DATA, GFX_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, GFX_Info
) / sizeof(USHORT)),
			NULL((void *)0), NULL((void *)0), NULL((void *)0));
if (!gfxinfo)
return -ENOENT2;

table->usHiLoLeakageThreshold = gfxinfo->usHiLoLeakageThreshold;
table->usEdcDidtLoDpm7TableOffset = gfxinfo->usEdcDidtLoDpm7TableOffset;
table->usEdcDidtHiDpm7TableOffset = gfxinfo->usEdcDidtHiDpm7TableOffset;

return 0;
1642}

1644static AtomCtrl_EDCLeakgeTable *get_edc_leakage_table(struct pp_hwmgr *hwmgr,
				      uint16_t offset)
1646{
void *table_address;
char *temp;

table_address = smu_atom_get_data_table(hwmgr->adev,
	GetIndexIntoMasterTable(DATA, GFX_Info)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, GFX_Info
) / sizeof(USHORT)),
	NULL((void *)0), NULL((void *)0), NULL((void *)0));
if (!table_address)
return NULL((void *)0);

temp = (char *)table_address;
table_address += offset;

return (AtomCtrl_EDCLeakgeTable *)temp;
1660}

1662int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
		   AtomCtrl_EDCLeakgeTable *table,
		   uint16_t offset)
1665{
uint32_t length, i;
AtomCtrl_EDCLeakgeTable *leakage_table =
get_edc_leakage_table(hwmgr, offset);

if (!leakage_table)
return -ENOENT2;

length = sizeof(leakage_table->DIDT_REG) /
 sizeof(leakage_table->DIDT_REG[0]);
for (i = 0; i < length; i++)
table->DIDT_REG[i] = leakage_table->DIDT_REG[i];

return 0;
1679}

←

/usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppevvmath.h

1/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
23#include <asm/div64.h>

25#define SHIFT_AMOUNT16 16 /* We multiply all original integers with 2^SHIFT_AMOUNT to get the fInt representation */

27#define PRECISION5 5 /* Change this value to change the number of decimal places in the final output - 5 is a good default */

29#define SHIFTED_2(2 << 16) (2 << SHIFT_AMOUNT16)
30#define PPMAX(1 << (16 - 1)) - 1 (1 << (SHIFT_AMOUNT16 - 1)) - 1 /* 32767 - Might change in the future */

32/* -------------------------------------------------------------------------------
* NEW TYPE - fINT
* -------------------------------------------------------------------------------
* A variable of type fInt can be accessed in 3 ways using the dot (.) operator
* fInt A;
* A.full => The full number as it is. Generally not easy to read
* A.partial.real => Only the integer portion
* A.partial.decimal => Only the fractional portion
*/
41typedef union _fInt {
  int full;
  struct _partial {
      unsigned int decimal: SHIFT_AMOUNT16; /*Needs to always be unsigned*/
      int real: 32 - SHIFT_AMOUNT16;
  } partial;
47} fInt;

49/* -------------------------------------------------------------------------------
* Function Declarations
*  -------------------------------------------------------------------------------
*/
53static fInt ConvertToFraction(int);                       /* Use this to convert an INT to a FINT */
54static fInt Convert_ULONG_ToFraction(uint32_t);           /* Use this to convert an uint32_t to a FINT */
55static fInt GetScaledFraction(int, int);                  /* Use this to convert an INT to a FINT after scaling it by a factor */
56static int ConvertBackToInteger(fInt);                    /* Convert a FINT back to an INT that is scaled by 1000 (i.e. last 3 digits are the decimal digits) */

58static fInt fNegate(fInt);                                /* Returns -1 * input fInt value */
59static fInt fAdd (fInt, fInt);                            /* Returns the sum of two fInt numbers */
60static fInt fSubtract (fInt A, fInt B);                   /* Returns A-B - Sometimes easier than Adding negative numbers */
61static fInt fMultiply (fInt, fInt);                       /* Returns the product of two fInt numbers */
62static fInt fDivide (fInt A, fInt B);                     /* Returns A/B */
63static fInt fGetSquare(fInt);                             /* Returns the square of a fInt number */
64static fInt fSqrt(fInt);                                  /* Returns the Square Root of a fInt number */

66static int uAbs(int);                                     /* Returns the Absolute value of the Int */
67static int uPow(int base, int exponent);                  /* Returns base^exponent an INT */

69static void SolveQuadracticEqn(fInt, fInt, fInt, fInt[]); /* Returns the 2 roots via the array */
70static bool_Bool Equal(fInt, fInt);                            /* Returns true if two fInts are equal to each other */
71static bool_Bool GreaterThan(fInt A, fInt B);                  /* Returns true if A > B */

73static fInt fExponential(fInt exponent);                  /* Can be used to calculate e^exponent */
74static fInt fNaturalLog(fInt value);                      /* Can be used to calculate ln(value) */

76/* Fuse decoding functions
* -------------------------------------------------------------------------------------
*/
79static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength);
80static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength);
81static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength);

83/* Internal Support Functions - Use these ONLY for testing or adding to internal functions
* -------------------------------------------------------------------------------------
* Some of the following functions take two INTs as their input - This is unsafe for a variety of reasons.
*/
87static fInt Divide (int, int);                            /* Divide two INTs and return result as FINT */
88static fInt fNegate(fInt);

90static int uGetScaledDecimal (fInt);                      /* Internal function */
91static int GetReal (fInt A);                              /* Internal function */

93/* -------------------------------------------------------------------------------------
* TROUBLESHOOTING INFORMATION
* -------------------------------------------------------------------------------------
* 1) ConvertToFraction - InputOutOfRangeException: Only accepts numbers smaller than MAX (default: 32767)
* 2) fAdd - OutputOutOfRangeException: Output bigger than MAX (default: 32767)
* 3) fMultiply - OutputOutOfRangeException:
* 4) fGetSquare - OutputOutOfRangeException:
* 5) fDivide - DivideByZeroException
* 6) fSqrt - NegativeSquareRootException: Input cannot be a negative number
*/

104/* -------------------------------------------------------------------------------------
* START OF CODE
* -------------------------------------------------------------------------------------
*/
108static fInt fExponential(fInt exponent)        /*Can be used to calculate e^exponent*/
109{
uint32_t i;
bool_Bool bNegated = false0;

fInt fPositiveOne = ConvertToFraction(1);
fInt fZERO = ConvertToFraction(0);

fInt lower_bound = Divide(78, 10000);
fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
fInt error_term;

static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};

if (GreaterThan(fZERO, exponent)) {
exponent = fNegate(exponent);
bNegated = true1;
}

while (GreaterThan(exponent, lower_bound)) {
for (i = 0; i < 11; i++) {
	if (GreaterThan(exponent, GetScaledFraction(k_array[i], 10000))) {
		exponent = fSubtract(exponent, GetScaledFraction(k_array[i], 10000));
		solution = fMultiply(solution, GetScaledFraction(expk_array[i], 10000));
	}
}
}

error_term = fAdd(fPositiveOne, exponent);

solution = fMultiply(solution, error_term);

if (bNegated)
solution = fDivide(fPositiveOne, solution);

return solution;
145}

147static fInt fNaturalLog(fInt value)
148{
uint32_t i;
fInt upper_bound = Divide(8, 1000);
fInt fNegativeOne = ConvertToFraction(-1);
fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
fInt error_term;

static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};

while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
for (i = 0; i < 10; i++) {
	if (GreaterThan(value, GetScaledFraction(k_array[i], 10000))) {
		value = fDivide(value, GetScaledFraction(k_array[i], 10000));
		solution = fAdd(solution, GetScaledFraction(logk_array[i], 10000));
	}
}
}

error_term = fAdd(fNegativeOne, value);

return (fAdd(solution, error_term));
170}

172static fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength)
173{
fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);

fInt f_decoded_value;

f_decoded_value = fDivide(f_fuse_value, f_bit_max_value);
f_decoded_value = fMultiply(f_decoded_value, f_range);
f_decoded_value = fAdd(f_decoded_value, f_min);

return f_decoded_value;
184}


187static fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength)
188{
fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);

fInt f_CONSTANT_NEG13 = ConvertToFraction(-13);
14
←
Passing the value -13 via 1st parameter 'X'→
15
←
Calling 'ConvertToFraction'→
fInt f_CONSTANT1 = ConvertToFraction(1);

fInt f_decoded_value;

f_decoded_value = fSubtract(fDivide(f_bit_max_value, f_fuse_value), f_CONSTANT1);
f_decoded_value = fNaturalLog(f_decoded_value);
f_decoded_value = fMultiply(f_decoded_value, fDivide(f_range, f_CONSTANT_NEG13));
f_decoded_value = fAdd(f_decoded_value, f_average);

return f_decoded_value;
203}

205static fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength)
206{
fInt fLeakage;
fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);

fLeakage = fMultiply(ln_max_div_min, Convert_ULONG_ToFraction(leakageID_fuse));
fLeakage = fDivide(fLeakage, f_bit_max_value);
fLeakage = fExponential(fLeakage);
fLeakage = fMultiply(fLeakage, f_min);

return fLeakage;
216}

218static fInt ConvertToFraction(int X) /*Add all range checking here. Is it possible to make fInt a private declaration? */
219{
fInt temp;

if (X <= PPMAX(1 << (16 - 1)) - 1)
16
←
Taking true branch→
temp.full = (X << SHIFT_AMOUNT16);
17
←
The result of the left shift is undefined because the left operand is negative
else
temp.full = 0;

return temp;
228}

230static fInt fNegate(fInt X)
231{
fInt CONSTANT_NEGONE = ConvertToFraction(-1);
return (fMultiply(X, CONSTANT_NEGONE));
234}

236static fInt Convert_ULONG_ToFraction(uint32_t X)
237{
fInt temp;

if (X <= PPMAX(1 << (16 - 1)) - 1)
temp.full = (X << SHIFT_AMOUNT16);
else
temp.full = 0;

return temp;
246}

248static fInt GetScaledFraction(int X, int factor)
249{
int times_shifted, factor_shifted;
bool_Bool bNEGATED;
fInt fValue;

times_shifted = 0;
factor_shifted = 0;
bNEGATED = false0;

if (X < 0) {
X = -1*X;
bNEGATED = true1;
}

if (factor < 0) {
factor = -1*factor;
bNEGATED = !bNEGATED; /*If bNEGATED = true due to X < 0, this will cover the case of negative cancelling negative */
}

if ((X > PPMAX(1 << (16 - 1)) - 1) || factor > PPMAX(1 << (16 - 1)) - 1) {
if ((X/factor) <= PPMAX(1 << (16 - 1)) - 1) {
	while (X > PPMAX(1 << (16 - 1)) - 1) {
		X = X >> 1;
		times_shifted++;
	}

	while (factor > PPMAX(1 << (16 - 1)) - 1) {
		factor = factor >> 1;
		factor_shifted++;
	}
} else {
	fValue.full = 0;
	return fValue;
}
}

if (factor == 1)
return ConvertToFraction(X);

fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor));

fValue.full = fValue.full << times_shifted;
fValue.full = fValue.full >> factor_shifted;

return fValue;
294}

296/* Addition using two fInts */
297static fInt fAdd (fInt X, fInt Y)
298{
fInt Sum;

Sum.full = X.full + Y.full;

return Sum;
304}

306/* Addition using two fInts */
307static fInt fSubtract (fInt X, fInt Y)
308{
fInt Difference;

Difference.full = X.full - Y.full;

return Difference;
314}

316static bool_Bool Equal(fInt A, fInt B)
317{
if (A.full == B.full)
return true1;
else
return false0;
322}

324static bool_Bool GreaterThan(fInt A, fInt B)
325{
if (A.full > B.full)
return true1;
else
return false0;
330}

332static fInt fMultiply (fInt X, fInt Y) /* Uses 64-bit integers (int64_t) */
333{
fInt Product;
int64_t tempProduct;

/*The following is for a very specific common case: Non-zero number with ONLY fractional portion*/
/* TEMPORARILY DISABLED - CAN BE USED TO IMPROVE PRECISION
bool X_LessThanOne, Y_LessThanOne;

X_LessThanOne = (X.partial.real == 0 && X.partial.decimal != 0 && X.full >= 0);
Y_LessThanOne = (Y.partial.real == 0 && Y.partial.decimal != 0 && Y.full >= 0);

if (X_LessThanOne && Y_LessThanOne) {
Product.full = X.full * Y.full;
return Product
}*/

tempProduct = ((int64_t)X.full) * ((int64_t)Y.full); /*Q(16,16)*Q(16,16) = Q(32, 32) - Might become a negative number! */
tempProduct = tempProduct >> 16; /*Remove lagging 16 bits - Will lose some precision from decimal; */
Product.full = (int)tempProduct; /*The int64_t will lose the leading 16 bits that were part of the integer portion */

return Product;
354}

356static fInt fDivide (fInt X, fInt Y)
357{
fInt fZERO, fQuotient;
int64_t longlongX, longlongY;

fZERO = ConvertToFraction(0);

if (Equal(Y, fZERO))
return fZERO;

longlongX = (int64_t)X.full;
longlongY = (int64_t)Y.full;

longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */

div64_s64(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */

fQuotient.full = (int)longlongX;
return fQuotient;
375}

377static int ConvertBackToInteger (fInt A) /*THIS is the function that will be used to check with the Golden settings table*/
378{
fInt fullNumber, scaledDecimal, scaledReal;

scaledReal.full = GetReal(A) * uPow(10, PRECISION5-1); /* DOUBLE CHECK THISSSS!!! */

scaledDecimal.full = uGetScaledDecimal(A);

fullNumber = fAdd(scaledDecimal,scaledReal);

return fullNumber.full;
388}

390static fInt fGetSquare(fInt A)
391{
return fMultiply(A,A);
393}

395/* x_new = x_old - (x_old^2 - C) / (2 * x_old) */
396static fInt fSqrt(fInt num)
397{
fInt F_divide_Fprime, Fprime;
fInt test;
fInt twoShifted;
int seed, counter, error;
fInt x_new, x_old, C, y;

fInt fZERO = ConvertToFraction(0);

/* (0 > num) is the same as (num < 0), i.e., num is negative */

if (GreaterThan(fZERO, num) || Equal(fZERO, num))
return fZERO;

C = num;

if (num.partial.real > 3000)
seed = 60;
else if (num.partial.real > 1000)
seed = 30;
else if (num.partial.real > 100)
seed = 10;
else
seed = 2;

counter = 0;

if (Equal(num, fZERO)) /*Square Root of Zero is zero */
return fZERO;

twoShifted = ConvertToFraction(2);
x_new = ConvertToFraction(seed);

do {
counter++;

x_old.full = x_new.full;

test = fGetSquare(x_old); /*1.75*1.75 is reverting back to 1 when shifted down */
y = fSubtract(test, C); /*y = f(x) = x^2 - C; */

Fprime = fMultiply(twoShifted, x_old);
F_divide_Fprime = fDivide(y, Fprime);

x_new = fSubtract(x_old, F_divide_Fprime);

error = ConvertBackToInteger(x_new) - ConvertBackToInteger(x_old);

if (counter > 20) /*20 is already way too many iterations. If we dont have an answer by then, we never will*/
	return x_new;

} while (uAbs(error) > 0);

return (x_new);
451}

453static void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[])
454{
fInt *pRoots = &Roots[0];
fInt temp, root_first, root_second;
fInt f_CONSTANT10, f_CONSTANT100;

f_CONSTANT100 = ConvertToFraction(100);
f_CONSTANT10 = ConvertToFraction(10);

while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) {
A = fDivide(A, f_CONSTANT10);
B = fDivide(B, f_CONSTANT10);
C = fDivide(C, f_CONSTANT10);
}

temp = fMultiply(ConvertToFraction(4), A); /* root = 4*A */
temp = fMultiply(temp, C); /* root = 4*A*C */
temp = fSubtract(fGetSquare(B), temp); /* root = b^2 - 4AC */
temp = fSqrt(temp); /*root = Sqrt (b^2 - 4AC); */

root_first = fSubtract(fNegate(B), temp); /* b - Sqrt(b^2 - 4AC) */
root_second = fAdd(fNegate(B), temp); /* b + Sqrt(b^2 - 4AC) */

root_first = fDivide(root_first, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
root_first = fDivide(root_first, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */

root_second = fDivide(root_second, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
root_second = fDivide(root_second, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */

*(pRoots + 0) = root_first;
*(pRoots + 1) = root_second;
484}

486/* -----------------------------------------------------------------------------
* SUPPORT FUNCTIONS
* -----------------------------------------------------------------------------
*/

491/* Conversion Functions */
492static int GetReal (fInt A)
493{
return (A.full >> SHIFT_AMOUNT16);
495}

497static fInt Divide (int X, int Y)
498{
fInt A, B, Quotient;

A.full = X << SHIFT_AMOUNT16;
B.full = Y << SHIFT_AMOUNT16;

Quotient = fDivide(A, B);

return Quotient;
507}

509static int uGetScaledDecimal (fInt A) /*Converts the fractional portion to whole integers - Costly function */
510{
int dec[PRECISION5];
int i, scaledDecimal = 0, tmp = A.partial.decimal;

for (i = 0; i < PRECISION5; i++) {
dec[i] = tmp / (1 << SHIFT_AMOUNT16);
tmp = tmp - ((1 << SHIFT_AMOUNT16)*dec[i]);
tmp *= 10;
scaledDecimal = scaledDecimal + dec[i]*uPow(10, PRECISION5 - 1 -i);
}

return scaledDecimal;
522}

524static int uPow(int base, int power)
525{
if (power == 0)
return 1;
else
return (base)*uPow(base, power - 1);
530}

532static int uAbs(int X)
533{
if (X < 0)
return (X * -1);
else
return X;
538}

540static fInt fRoundUpByStepSize(fInt A, fInt fStepSize, bool_Bool error_term)
541{
fInt solution;

solution = fDivide(A, fStepSize);
solution.partial.decimal = 0; /*All fractional digits changes to 0 */

if (error_term)
solution.partial.real += 1; /*Error term of 1 added */

solution = fMultiply(solution, fStepSize);
solution = fAdd(solution, fStepSize);

return solution;
554}
