Bug Summary

File:dev/usb/if_ure.c
Warning:line 274, column 6
Assigned value is garbage or undefined

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_ure.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/usb/if_ure.c
1/* $OpenBSD: if_ure.c,v 1.33 2023/09/09 14:23:37 kevlo Exp $ */
2/*-
3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "bpfilter.h"
30#include "vlan.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/sockio.h>
35#include <sys/rwlock.h>
36#include <sys/mbuf.h>
37#include <sys/kernel.h>
38#include <sys/socket.h>
39#include <sys/device.h>
40
41#include <machine/bus.h>
42
43#include <net/if.h>
44#include <net/if_media.h>
45
46#if NBPFILTER1 > 0
47#include <net/bpf.h>
48#endif
49
50#include <netinet/in.h>
51#include <netinet/if_ether.h>
52
53#include <dev/mii/mii.h>
54#include <dev/mii/miivar.h>
55
56#include <dev/usb/usb.h>
57#include <dev/usb/usbdi.h>
58#include <dev/usb/usbdi_util.h>
59#include <dev/usb/usbdivar.h>
60#include <dev/usb/usbdevs.h>
61
62#include <dev/ic/rtl81x9reg.h>
63#include <dev/usb/if_urereg.h>
64
65#ifdef URE_DEBUG
66#define DPRINTF(x) do { if (uredebug) printf x; } while (0)
67#define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0)
68int uredebug = 0;
69#else
70#define DPRINTF(x)
71#define DPRINTFN(n,x)
72#endif
73
74const struct usb_devno ure_devs[] = {
75 { USB_VENDOR_ASUS0x0b05, USB_PRODUCT_ASUS_RTL81560x18d1 },
76 { USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL8152B0x047a },
77 { USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL81530x048a },
78 { USB_VENDOR_CISCOLINKSYS0x13b1, USB_PRODUCT_CISCOLINKSYS_USB3GIGV10x0041 },
79 { USB_VENDOR_CLEVO0x30da, USB_PRODUCT_CLEVO_RTL8153B0x5101 },
80 { USB_VENDOR_CLUB3D0x2d1c, USB_PRODUCT_CLUB3D_RTL81530x8153 },
81 { USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_10x7e34 },
82 { USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_20xa710 },
83 { USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_10x0419 },
84 { USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_20x0425 },
85 { USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8153B0x4013 },
86 { USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8156B0x4017 },
87 { USB_VENDOR_IOI0x0f21, USB_PRODUCT_IOI_RTL81530x8153 },
88 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_DOCK_ETHERNET0x3062 },
89 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINK0x720a },
90 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPLUS0x3054 },
91 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPRO0x304f },
92 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_10x3069 },
93 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_20x3098 },
94 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_30x309b },
95 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_40x309c },
96 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_50x309d },
97 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_60x7214 },
98 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_70x721e },
99 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_80x8153 },
100 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_90xa359 },
101 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_10x7205 },
102 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_20x720b },
103 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_30x720c },
104 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TABLETDOCK0x3052 },
105 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCK0xa3c1 },
106 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCKGEN20x3082 },
107 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3GFXDOCK0x3065 },
108 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_USBCDOCKGEN20xa387 },
109 { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_WIGIGDOCK0x3057 },
110 { USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL81530x9819 },
111 { USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL8153B0x9820 },
112 { USB_VENDOR_LUXSHARE0x208e, USB_PRODUCT_LUXSHARE_RTL81530xd003 },
113 { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH0x07ab },
114 { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH20x07c6 },
115 { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_SURFETH0x0927 },
116 { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_WINDEVETH0x0c5e },
117 { USB_VENDOR_NVIDIA0x0955, USB_PRODUCT_NVIDIA_TEGRAETH0x09ff },
118 { USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8152B0x0007 },
119 { USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8153B0x0031 },
120 { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81520x8152 },
121 { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL8152B0x8050 },
122 { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81530x8153 },
123 { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81560x8156 },
124 { USB_VENDOR_SAMSUNG20x04e8, USB_PRODUCT_SAMSUNG2_RTL81530xa101 },
125 { USB_VENDOR_TOSHIBA0x0930, USB_PRODUCT_TOSHIBA_RTL8153B0x0416 },
126 { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_EU3000x0601 },
127 { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_10x0602 },
128 { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_20x0603 },
129 { USB_VENDOR_TRENDNET0x20f4, USB_PRODUCT_TRENDNET_RTL81560xe02b },
130 { USB_VENDOR_TTL0x1025, USB_PRODUCT_TTL_RTL81530x104e },
131 { USB_VENDOR_TWINHEAD0x14ff, USB_PRODUCT_TWINHEAD_RTL8153B0x1400 },
132 { USB_VENDOR_XIAOMI0x2717, USB_PRODUCT_XIAOMI_RTL8152B0x0011 },
133};
134
135int ure_match(struct device *, void *, void *);
136void ure_attach(struct device *, struct device *, void *);
137int ure_detach(struct device *, int);
138
139struct cfdriver ure_cd = {
140 NULL((void *)0), "ure", DV_IFNET
141};
142
143const struct cfattach ure_ca = {
144 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach
145};
146
147int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
148 void *, int);
149int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
150 int);
151int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
152 int);
153uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
154uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
155uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
156int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
157int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
158int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
159uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
160void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
161
162void ure_init(void *);
163void ure_stop(struct ure_softc *);
164void ure_start(struct ifnet *);
165void ure_reset(struct ure_softc *);
166void ure_watchdog(struct ifnet *);
167
168void ure_miibus_statchg(struct device *);
169int ure_miibus_readreg(struct device *, int, int);
170void ure_miibus_writereg(struct device *, int, int, int);
171void ure_lock_mii(struct ure_softc *);
172void ure_unlock_mii(struct ure_softc *);
173
174int ure_encap_txpkt(struct mbuf *, char *, uint32_t);
175int ure_encap_xfer(struct ifnet *, struct ure_softc *,
176 struct ure_chain *);
177void ure_rxeof(struct usbd_xfer *, void *, usbd_status);
178void ure_txeof(struct usbd_xfer *, void *, usbd_status);
179int ure_xfer_list_init(struct ure_softc *, struct ure_chain *,
180 uint32_t, int);
181void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int);
182
183void ure_tick_task(void *);
184void ure_tick(void *);
185
186void ure_ifmedia_init(struct ifnet *);
187int ure_ifmedia_upd(struct ifnet *);
188void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
189void ure_add_media_types(struct ure_softc *);
190void ure_link_state(struct ure_softc *);
191int ure_get_link_status(struct ure_softc *);
192void ure_iff(struct ure_softc *);
193void ure_rxvlan(struct ure_softc *);
194int ure_ioctl(struct ifnet *, u_long, caddr_t);
195void ure_rtl8152_init(struct ure_softc *);
196void ure_rtl8153_init(struct ure_softc *);
197void ure_rtl8153b_init(struct ure_softc *);
198void ure_rtl8152_nic_reset(struct ure_softc *);
199void ure_rtl8153_nic_reset(struct ure_softc *);
200uint16_t ure_rtl8153_phy_status(struct ure_softc *, int);
201void ure_wait_for_flash(struct ure_softc *);
202void ure_reset_bmu(struct ure_softc *);
203void ure_disable_teredo(struct ure_softc *);
204
205#define URE_SETBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) \
206 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
207#define URE_SETBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) \
208 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
209#define URE_SETBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) \
210 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
211
212#define URE_CLRBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~
(x))
\
213 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
214#define URE_CLRBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~
(x))
\
215 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
216#define URE_CLRBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~
(x))
\
217 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
218
219int
220ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
221 void *buf, int len)
222{
223 usb_device_request_t req;
224 usbd_status err;
225
226 if (usbd_is_dying(sc->ure_udev))
8
Assuming the condition is true
9
Taking true branch
227 return 0;
228
229 if (rw == URE_CTL_WRITE0x02)
230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
231 else
232 req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00);
233 req.bRequest = UR_SET_ADDRESS0x05;
234 USETW(req.wValue, val)(*(u_int16_t *)(req.wValue) = (val));
235 USETW(req.wIndex, index)(*(u_int16_t *)(req.wIndex) = (index));
236 USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));
237
238 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n",
239 rw, val, index, len));
240 err = usbd_do_request(sc->ure_udev, &req, buf);
241 if (err) {
242 DPRINTF(("ure_ctl: error %d\n", err));
243 return -1;
244 }
245
246 return 0;
247}
248
249int
250ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
251 void *buf, int len)
252{
253 return (ure_ctl(sc, URE_CTL_READ0x01, addr, index, buf, len));
7
Calling 'ure_ctl'
10
Returning from 'ure_ctl'
254}
255
256int
257ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
258 void *buf, int len)
259{
260 return (ure_ctl(sc, URE_CTL_WRITE0x02, addr, index, buf, len));
261}
262
263uint8_t
264ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
265{
266 uint32_t val;
267 uint8_t temp[4];
268 uint8_t shift;
269
270 shift = (reg & 3) << 3;
271 reg &= ~3;
272
273 ure_read_mem(sc, reg, index, &temp, 4);
6
Calling 'ure_read_mem'
11
Returning from 'ure_read_mem'
274 val = UGETDW(temp)(*(u_int32_t *)(temp));
12
Assigned value is garbage or undefined
275 val >>= shift;
276
277 return (val & 0xff);
278}
279
280uint16_t
281ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
282{
283 uint32_t val;
284 uint8_t temp[4];
285 uint8_t shift;
286
287 shift = (reg & 2) << 3;
288 reg &= ~3;
289
290 ure_read_mem(sc, reg, index, &temp, 4);
291 val = UGETDW(temp)(*(u_int32_t *)(temp));
292 val >>= shift;
293
294 return (val & 0xffff);
295}
296
297uint32_t
298ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
299{
300 uint8_t temp[4];
301
302 ure_read_mem(sc, reg, index, &temp, 4);
303 return (UGETDW(temp)(*(u_int32_t *)(temp)));
304}
305
306int
307ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
308{
309 uint16_t byen;
310 uint8_t temp[4];
311 uint8_t shift;
312
313 byen = URE_BYTE_EN_BYTE0x11;
314 shift = reg & 3;
315 val &= 0xff;
316
317 if (reg & 3) {
318 byen <<= shift;
319 val <<= (shift << 3);
320 reg &= ~3;
321 }
322
323 USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
324 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
325}
326
327int
328ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
329{
330 uint16_t byen;
331 uint8_t temp[4];
332 uint8_t shift;
333
334 byen = URE_BYTE_EN_WORD0x33;
335 shift = reg & 2;
336 val &= 0xffff;
337
338 if (reg & 2) {
339 byen <<= shift;
340 val <<= (shift << 3);
341 reg &= ~3;
342 }
343
344 USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
345 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
346}
347
348int
349ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
350{
351 uint8_t temp[4];
352
353 USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
354 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD0xff, &temp, 4));
355}
356
357uint16_t
358ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
359{
360 uint16_t reg;
361
362 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000);
363 reg = (addr & 0x0fff) | 0xb000;
364
365 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA0x0100));
366}
367
368void
369ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
370{
371 uint16_t reg;
372
373 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000);
374 reg = (addr & 0x0fff) | 0xb000;
375
376 ure_write_2(sc, reg, URE_MCU_TYPE_PLA0x0100, data);
377}
378
379int
380ure_miibus_readreg(struct device *dev, int phy, int reg)
381{
382 struct ure_softc *sc = (void *)dev;
383 uint16_t val;
384
385 if (usbd_is_dying(sc->ure_udev))
1
Assuming the condition is false
2
Taking false branch
386 return 0;
387
388 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */
389 if (reg == RL_GMEDIASTAT0x006C)
3
Assuming 'reg' is equal to RL_GMEDIASTAT
4
Taking true branch
390 return ure_read_1(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100);
5
Calling 'ure_read_1'
391
392 ure_lock_mii(sc);
393 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII0xa400 + reg * 2);
394 ure_unlock_mii(sc);
395
396 return val; /* letoh16? */
397}
398
399void
400ure_miibus_writereg(struct device *dev, int phy, int reg, int val)
401{
402 struct ure_softc *sc = (void *)dev;
403
404 ure_lock_mii(sc);
405 ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + reg * 2, val); /* htole16? */
406 ure_unlock_mii(sc);
407}
408
409void
410ure_miibus_statchg(struct device *dev)
411{
412 struct ure_softc *sc = (void *)dev;
413 struct mii_data *mii = &sc->ure_mii;
414 struct ifnet *ifp = &sc->ure_ac.ac_if;
415
416 if ((ifp->if_flags & IFF_RUNNING0x40) == 0)
417 return;
418
419 sc->ure_flags &= ~URE_FLAG_LINK0x0001;
420 if ((mii->mii_media_status & (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) ==
421 (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) {
422 switch (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL)) {
423 case IFM_10_T3:
424 case IFM_100_TX6:
425 sc->ure_flags |= URE_FLAG_LINK0x0001;
426 break;
427 case IFM_1000_T16:
428 if ((sc->ure_flags & URE_FLAG_81520x1000) != 0)
429 break;
430 sc->ure_flags |= URE_FLAG_LINK0x0001;
431 break;
432 default:
433 break;
434 }
435 }
436
437 /* Lost link, do nothing. */
438 if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0)
439 return;
440
441 /*
442 * After a link change the media settings are getting reset on the
443 * hardware, and need to be re-initialized again for communication
444 * to continue work.
445 */
446 ure_ifmedia_init(ifp);
447}
448
449void
450ure_ifmedia_init(struct ifnet *ifp)
451{
452 struct ure_softc *sc = ifp->if_softc;
453 uint32_t reg = 0;
454
455 /* Set MAC address. */
456 ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0);
457 ure_write_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_SIX_BYTES0x3f,
458 sc->ure_ac.ac_enaddr, 8);
459 ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);
460
461 if (!(sc->ure_flags & URE_FLAG_81520x1000)) {
462 if (sc->ure_flags & URE_FLAG_8156B0x8000)
463 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4ee, 0x0000, ure_read_2(sc, 0xd4ee, 0x0000
) & ~(0x1ff))
464 URE_RX_AGGR_NUM_MASK)ure_write_2(sc, 0xd4ee, 0x0000, ure_read_2(sc, 0xd4ee, 0x0000
) & ~(0x1ff))
;
465
466 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4) -
467 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN8;
468 if (sc->ure_flags &
469 (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
470 ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000,
471 reg / 8);
472
473 ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000,
474 (sc->ure_flags & URE_FLAG_8153B0x2000) ? 158 : 80);
475 ure_write_2(sc, URE_USB_PM_CTRL_STATUS0xd432,
476 URE_MCU_TYPE_USB0x0000, 1875);
477 } else {
478 ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000,
479 reg / 4);
480 switch (sc->ure_udev->speed) {
481 case USB_SPEED_SUPER4:
482 reg = URE_COALESCE_SUPER85000U / 8;
483 break;
484 case USB_SPEED_HIGH3:
485 reg = URE_COALESCE_HIGH250000U / 8;
486 break;
487 default:
488 reg = URE_COALESCE_SLOW524280U / 8;
489 break;
490 }
491 ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000,
492 reg);
493 }
494
495 if (sc->ure_chip & URE_CHIP_VER_74200x80) {
496 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4,ure_write_2(sc, 0xe0ce, 0x0100, ure_read_2(sc, 0xe0ce, 0x0100
) | (0x0040))
497 URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN)ure_write_2(sc, 0xe0ce, 0x0100, ure_read_2(sc, 0xe0ce, 0x0100
) | (0x0040))
;
498 }
499
500 if ((sc->ure_chip & URE_CHIP_VER_60100x40) ||
501 (sc->ure_flags & URE_FLAG_8156B0x8000)) {
502 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) & ~(0x0002))
503 URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) & ~(0x0002))
;
504 usbd_delay_ms(sc->ure_udev, 1);
505 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
506 URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
;
507 }
508 }
509
510 /* Reset the packet filter. */
511 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100
) & ~(0x0001))
;
512 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100
) | (0x0001))
;
513
514 /* Enable transmit and receive. */
515 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) | (0x08 | 0x04))
;
516
517 if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
518 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN0xd437, URE_MCU_TYPE_USB0x0000,
519 URE_OWN_UPDATE0x01 | URE_OWN_CLEAR0x02);
520 }
521
522 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) & ~(0x0008))
;
523}
524
525int
526ure_ifmedia_upd(struct ifnet *ifp)
527{
528 struct ure_softc *sc = ifp->if_softc;
529 struct mii_data *mii = &sc->ure_mii;
530 struct ifmedia *ifm = &sc->ure_ifmedia;
531 int anar, gig, err, reg;
532
533 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
534 if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
535 return (EINVAL22);
536
537 if (!(sc->ure_chip & URE_CHIP_VER_74200x80)) {
538 reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL0xa5d4);
539 reg &= ~URE_ADV_2500TFDX0x0080;
540 }
541
542 anar = gig = 0;
543 switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
544 case IFM_AUTO0ULL:
545 anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
546 gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
547 if (!(sc->ure_chip & URE_CHIP_VER_74200x80))
548 reg |= URE_ADV_2500TFDX0x0080;
549 break;
550 case IFM_2500_T34:
551 anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
552 gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
553 reg |= URE_ADV_2500TFDX0x0080;
554 ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(2500)((((2500) * 1000ULL) * 1000ULL));
555 break;
556 case IFM_1000_T16:
557 anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
558 gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
559 ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL)));
560 break;
561 case IFM_100_TX6:
562 anar |= ANAR_TX0x0080 | ANAR_TX_FD0x0100;
563 ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(100)((((100) * 1000ULL) * 1000ULL));
564 break;
565 case IFM_10_T3:
566 anar |= ANAR_100x0020 | ANAR_10_FD0x0040;
567 ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(10)((((10) * 1000ULL) * 1000ULL));
568 break;
569 default:
570 printf("%s: unsupported media type\n",
571 sc->ure_dev.dv_xname);
572 return (EINVAL22);
573 }
574
575 ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_ANAR0x04 * 2,
576 anar | ANAR_PAUSE_ASYM(2 << 10) | ANAR_FC0x0400);
577 ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_100T2CR0x09 * 2, gig);
578 if (!(sc->ure_chip & URE_CHIP_VER_74200x80))
579 ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL0xa5d4, reg);
580 ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_BMCR0x00,
581 BMCR_AUTOEN0x1000 | BMCR_STARTNEG0x0200);
582
583 return (0);
584 }
585
586 if (mii->mii_instance) {
587 struct mii_softc *miisc;
588 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)for((miisc) = ((&mii->mii_phys)->lh_first); (miisc)
!= ((void *)0); (miisc) = ((miisc)->mii_list.le_next))
589 PHY_RESET(miisc)(*(miisc)->mii_funcs->pf_reset)((miisc));
590 }
591
592 err = mii_mediachg(mii);
593 if (err == ENXIO6)
594 return (0);
595 else
596 return (err);
597}
598
599void
600ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
601{
602 struct ure_softc *sc = ifp->if_softc;
603 struct mii_data *mii = &sc->ure_mii;
604 uint16_t status = 0;
605
606 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
607 ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
608 if (ure_get_link_status(sc)) {
609 ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;
610 status = ure_read_2(sc, URE_PLA_PHYSTATUS0xe908,
611 URE_MCU_TYPE_PLA0x0100);
612 if ((status & URE_PHYSTATUS_FDX0x0001) ||
613 (status & URE_PHYSTATUS_2500MBPS0x0400))
614 ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL;
615 else
616 ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL;
617 if (status & URE_PHYSTATUS_10MBPS0x0004)
618 ifmr->ifm_active |= IFM_10_T3;
619 else if (status & URE_PHYSTATUS_100MBPS0x0008)
620 ifmr->ifm_active |= IFM_100_TX6;
621 else if (status & URE_PHYSTATUS_1000MBPS0x0010)
622 ifmr->ifm_active |= IFM_1000_T16;
623 else if (status & URE_PHYSTATUS_2500MBPS0x0400)
624 ifmr->ifm_active |= IFM_2500_T34;
625 }
626 return;
627 }
628
629 mii_pollstat(mii);
630 ifmr->ifm_active = mii->mii_media_active;
631 ifmr->ifm_status = mii->mii_media_status;
632}
633
634void
635ure_add_media_types(struct ure_softc *sc)
636{
637 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0));
638 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
639 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 0, NULL((void *)0));
640 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0,
641 NULL((void *)0));
642 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0));
643 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0,
644 NULL((void *)0));
645 if (!(sc->ure_chip & URE_CHIP_VER_74200x80)) {
646 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0));
647 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34 | IFM_FDX0x0000010000000000ULL,
648 0, NULL((void *)0));
649 }
650}
651
652void
653ure_link_state(struct ure_softc *sc)
654{
655 struct ifnet *ifp = &sc->ure_ac.ac_if;
656 int link = LINK_STATE_DOWN2;
657
658 if (ure_get_link_status(sc))
659 link = LINK_STATE_UP4;
660
661 if (ifp->if_link_stateif_data.ifi_link_state != link) {
662 ifp->if_link_stateif_data.ifi_link_state = link;
663 if_link_state_change(ifp);
664 }
665}
666
667int
668ure_get_link_status(struct ure_softc *sc)
669{
670 if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
671 URE_PHYSTATUS_LINK0x0002) {
672 sc->ure_flags |= URE_FLAG_LINK0x0001;
673 return (1);
674 } else {
675 sc->ure_flags &= ~URE_FLAG_LINK0x0001;
676 return (0);
677 }
678}
679
680void
681ure_iff(struct ure_softc *sc)
682{
683 struct ifnet *ifp = &sc->ure_ac.ac_if;
684 struct ether_multi *enm;
685 struct ether_multistep step;
686 uint32_t hashes[2] = { 0, 0 };
687 uint32_t hash;
688 uint32_t rxmode;
689
690 if (usbd_is_dying(sc->ure_udev))
691 return;
692
693 rxmode = ure_read_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100);
694 rxmode &= ~URE_RCR_ACPT_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008);
695 ifp->if_flags &= ~IFF_ALLMULTI0x200;
696
697 /*
698 * Always accept frames destined to our station address.
699 * Always accept broadcast frames.
700 */
701 rxmode |= URE_RCR_APM0x00000002 | URE_RCR_AB0x00000008;
702
703 if (ifp->if_flags & IFF_PROMISC0x100 || sc->ure_ac.ac_multirangecnt > 0) {
704 ifp->if_flags |= IFF_ALLMULTI0x200;
705 rxmode |= URE_RCR_AM0x00000004;
706 if (ifp->if_flags & IFF_PROMISC0x100)
707 rxmode |= URE_RCR_AAP0x00000001;
708 hashes[0] = hashes[1] = 0xffffffff;
709 } else {
710 rxmode |= URE_RCR_AM0x00000004;
711
712 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm)do { (step).e_enm = ((&(&sc->ure_ac)->ac_multiaddrs
)->lh_first); do { if ((((enm)) = ((step)).e_enm) != ((void
*)0)) ((step)).e_enm = ((((enm)))->enm_list.le_next); } while
( 0); } while ( 0)
;
713 while (enm != NULL((void *)0)) {
714 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN6)
715 >> 26;
716 if (hash < 32)
717 hashes[0] |= (1 << hash);
718 else
719 hashes[1] |= (1 << (hash - 32));
720
721 ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
(((enm))->enm_list.le_next); } while ( 0)
;
722 }
723
724 hash = swap32(hashes[0])(__uint32_t)(__builtin_constant_p(hashes[0]) ? (__uint32_t)((
(__uint32_t)(hashes[0]) & 0xff) << 24 | ((__uint32_t
)(hashes[0]) & 0xff00) << 8 | ((__uint32_t)(hashes[
0]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[0]) &
0xff000000) >> 24) : __swap32md(hashes[0]))
;
725 hashes[0] = swap32(hashes[1])(__uint32_t)(__builtin_constant_p(hashes[1]) ? (__uint32_t)((
(__uint32_t)(hashes[1]) & 0xff) << 24 | ((__uint32_t
)(hashes[1]) & 0xff00) << 8 | ((__uint32_t)(hashes[
1]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[1]) &
0xff000000) >> 24) : __swap32md(hashes[1]))
;
726 hashes[1] = hash;
727 }
728
729 ure_write_mem(sc, URE_PLA_MAR0xcd00, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_DWORD0xff,
730 hashes, sizeof(hashes));
731 ure_write_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100, rxmode);
732}
733
734void
735ure_rxvlan(struct ure_softc *sc)
736{
737 struct ifnet *ifp = &sc->ure_ac.ac_if;
738 uint16_t reg;
739
740 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
741 reg = ure_read_2(sc, URE_PLA_RCR10xc012, URE_MCU_TYPE_PLA0x0100);
742 reg &= ~(URE_INNER_VLAN0x0040 | URE_OUTER_VLAN0x0080);
743 if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
744 reg |= (URE_INNER_VLAN0x0040 | URE_OUTER_VLAN0x0080);
745 ure_write_2(sc, URE_PLA_RCR10xc012, URE_MCU_TYPE_PLA0x0100, reg);
746 } else {
747 reg = ure_read_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100);
748 reg &= ~URE_CPCR_RX_VLAN0x0040;
749 if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
750 reg |= URE_CPCR_RX_VLAN0x0040;
751 ure_write_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100, reg);
752 }
753}
754
755void
756ure_reset(struct ure_softc *sc)
757{
758 int i;
759
760 if (sc->ure_flags & URE_FLAG_81560x4000) {
761 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) & ~(0x04))
;
762 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) & ~(0x01))
763 BMU_RESET_EP_IN)ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) & ~(0x01))
;
764 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) | (0x0008))
765 URE_CDC_ECM_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) | (0x0008))
;
766 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) & ~(0x08))
;
767 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) | (0x01))
768 BMU_RESET_EP_IN)ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) | (0x01))
;
769 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0008))
770 URE_CDC_ECM_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0008))
;
771 } else {
772 ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, URE_CR_RST0x10);
773
774 for (i = 0; i < URE_TIMEOUT1000; i++) {
775 if (!(ure_read_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100) &
776 URE_CR_RST0x10))
777 break;
778 DELAY(100)(*delay_func)(100);
779 }
780 if (i == URE_TIMEOUT1000)
781 printf("%s: reset never completed\n",
782 sc->ure_dev.dv_xname);
783 }
784}
785
786void
787ure_watchdog(struct ifnet *ifp)
788{
789 struct ure_softc *sc = ifp->if_softc;
790 struct ure_chain *c;
791 usbd_status err;
792 int i, s;
793
794 ifp->if_timer = 0;
795
796 if (usbd_is_dying(sc->ure_udev))
797 return;
798
799 if ((ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) != (IFF_RUNNING0x40|IFF_UP0x1))
800 return;
801
802 sc = ifp->if_softc;
803 s = splnet()splraise(0x4);
804
805 ifp->if_oerrorsif_data.ifi_oerrors++;
806 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname));
807
808 for (i = 0; i < URE_TX_LIST_CNT1; i++) {
809 c = &sc->ure_cdata.ure_tx_chain[i];
810 if (c->uc_cnt > 0) {
811 usbd_get_xfer_status(c->uc_xfer, NULL((void *)0), NULL((void *)0), NULL((void *)0),
812 &err);
813 ure_txeof(c->uc_xfer, c, err);
814 }
815 }
816
817 if (ifq_is_oactive(&ifp->if_snd))
818 ifq_restart(&ifp->if_snd);
819 splx(s)spllower(s);
820}
821
822void
823ure_init(void *xsc)
824{
825 struct ure_softc *sc = xsc;
826 struct ure_chain *c;
827 struct ifnet *ifp = &sc->ure_ac.ac_if;
828 usbd_status err;
829 int s, i;
830
831 s = splnet()splraise(0x4);
832
833 /* Cancel pending I/O. */
834 ure_stop(sc);
835
836 if (sc->ure_flags & URE_FLAG_81520x1000)
837 ure_rtl8152_nic_reset(sc);
838 else
839 ure_rtl8153_nic_reset(sc);
840
841 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain,
842 sc->ure_rxbufsz, URE_RX_LIST_CNT1) == ENOBUFS55) {
843 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname);
844 splx(s)spllower(s);
845 return;
846 }
847
848 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain,
849 sc->ure_txbufsz, URE_TX_LIST_CNT1) == ENOBUFS55) {
850 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname);
851 splx(s)spllower(s);
852 return;
853 }
854
855 /* Initialize the SLIST we are using for the multiple tx buffers */
856 SLIST_INIT(&sc->ure_cdata.ure_tx_free){ ((&sc->ure_cdata.ure_tx_free)->slh_first) = ((void
*)0); }
;
857 for (i = 0; i < URE_TX_LIST_CNT1; i++)
858 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free,do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next
= (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc
->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata
.ure_tx_chain[i]); } while (0)
859 &sc->ure_cdata.ure_tx_chain[i], uc_list)do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next
= (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc
->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata
.ure_tx_chain[i]); } while (0)
;
860
861 /* Setup MAC address, and enable TX/RX. */
862 ure_ifmedia_init(ifp);
863
864 /* Load the multicast filter. */
865 ure_iff(sc);
866
867 /* Open RX and TX pipes. */
868 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX0],
869 USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_RX0]);
870 if (err) {
871 printf("%s: open rx pipe failed: %s\n",
872 sc->ure_dev.dv_xname, usbd_errstr(err));
873 splx(s)spllower(s);
874 return;
875 }
876
877 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX1],
878 USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_TX1]);
879 if (err) {
880 printf("%s: open tx pipe failed: %s\n",
881 sc->ure_dev.dv_xname, usbd_errstr(err));
882 splx(s)spllower(s);
883 return;
884 }
885
886 /* Start up the receive pipe. */
887 for (i = 0; i < URE_RX_LIST_CNT1; i++) {
888 c = &sc->ure_cdata.ure_rx_chain[i];
889 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX0],
890 c, c->uc_buf, c->uc_bufmax,
891 USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
892 USBD_NO_TIMEOUT0, ure_rxeof);
893 usbd_transfer(c->uc_xfer);
894 }
895
896 ure_ifmedia_upd(ifp);
897
898 /* Indicate we are up and running. */
899 sc->ure_flags &= ~URE_FLAG_LINK0x0001;
900 ifp->if_flags |= IFF_RUNNING0x40;
901 ifq_clr_oactive(&ifp->if_snd);
902
903 timeout_add_sec(&sc->ure_stat_ch, 1);
904
905 splx(s)spllower(s);
906}
907
908void
909ure_start(struct ifnet *ifp)
910{
911 struct ure_softc *sc = ifp->if_softc;
912 struct ure_cdata *cd = &sc->ure_cdata;
913 struct ure_chain *c;
914 struct mbuf *m = NULL((void *)0);
915 uint32_t new_buflen;
916 int s, mlen;
917
918 if (!(sc->ure_flags & URE_FLAG_LINK0x0001) ||
919 (ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) !=
920 (IFF_RUNNING0x40|IFF_UP0x1)) {
921 return;
922 }
923
924 s = splnet()splraise(0x4);
925
926 c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
927 while (c != NULL((void *)0)) {
928 m = ifq_deq_begin(&ifp->if_snd);
929 if (m == NULL((void *)0))
930 break;
931
932 mlen = m->m_pkthdrM_dat.MH.MH_pkthdr.len;
933
934 /* Discard packet larger than buffer. */
935 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) {
936 ifq_deq_commit(&ifp->if_snd, m);
937 m_freem(m);
938 ifp->if_oerrorsif_data.ifi_oerrors++;
939 continue;
940 }
941
942 /*
943 * If packet larger than remaining space, send buffer and
944 * continue.
945 */
946 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN)((((c->uc_buflen)+((4)-1))/(4))*(4));
947 if (new_buflen + sizeof(struct ure_txpkt) + mlen >=
948 c->uc_bufmax) {
949 ifq_deq_rollback(&ifp->if_snd, m);
950 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free
)->slh_first->uc_list.sle_next; } while (0)
;
951 if (ure_encap_xfer(ifp, sc, c)) {
952 SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
(0)
953 uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
(0)
;
954 break;
955 }
956 c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
957 continue;
958 }
959
960 /* Append packet to current buffer. */
961 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen,
962 c->uc_bufmax - new_buflen);
963 if (mlen <= 0) {
964 ifq_deq_rollback(&ifp->if_snd, m);
965 break;
966 }
967
968 ifq_deq_commit(&ifp->if_snd, m);
969 c->uc_cnt += 1;
970 c->uc_buflen = new_buflen + mlen;
971
972#if NBPFILTER1 > 0
973 if (ifp->if_bpf)
974 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
975#endif
976
977 m_freem(m);
978 }
979
980 if (c != NULL((void *)0)) {
981 /* Send current buffer unless empty */
982 if (c->uc_buflen > 0 && c->uc_cnt > 0) {
983 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free
)->slh_first->uc_list.sle_next; } while (0)
;
984 if (ure_encap_xfer(ifp, sc, c)) {
985 SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
(0)
986 uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
(0)
;
987 }
988 c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
989 }
990 }
991
992 ifp->if_timer = 5;
993 if (c == NULL((void *)0))
994 ifq_set_oactive(&ifp->if_snd);
995 splx(s)spllower(s);
996}
997
998void
999ure_tick(void *xsc)
1000{
1001 struct ure_softc *sc = xsc;
1002
1003 if (sc == NULL((void *)0))
1004 return;
1005
1006 if (usbd_is_dying(sc->ure_udev))
1007 return;
1008
1009 usb_add_task(sc->ure_udev, &sc->ure_tick_task);
1010}
1011
1012void
1013ure_stop(struct ure_softc *sc)
1014{
1015 struct ure_cdata *cd;
1016 struct ifnet *ifp;
1017 usbd_status err;
1018
1019 ure_reset(sc);
1020
1021 ifp = &sc->ure_ac.ac_if;
1022 ifp->if_timer = 0;
1023 ifp->if_flags &= ~IFF_RUNNING0x40;
1024 ifq_clr_oactive(&ifp->if_snd);
1025
1026 timeout_del(&sc->ure_stat_ch);
1027 sc->ure_flags &= ~URE_FLAG_LINK0x0001;
1028
1029 if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0)) {
1030 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX0]);
1031 if (err) {
1032 printf("%s: close rx pipe failed: %s\n",
1033 sc->ure_dev.dv_xname, usbd_errstr(err));
1034 }
1035 sc->ure_ep[URE_ENDPT_RX0] = NULL((void *)0);
1036 }
1037
1038 if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0)) {
1039 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX1]);
1040 if (err) {
1041 printf("%s: close tx pipe failed: %s\n",
1042 sc->ure_dev.dv_xname, usbd_errstr(err));
1043 }
1044 sc->ure_ep[URE_ENDPT_TX1] = NULL((void *)0);
1045 }
1046
1047 cd = &sc->ure_cdata;
1048 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT1);
1049 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT1);
1050}
1051
1052int
1053ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch,
1054 uint32_t bufsize, int listlen)
1055{
1056 struct ure_chain *c;
1057 int i;
1058
1059 for (i = 0; i < listlen; i++) {
1060 c = &ch[i];
1061 c->uc_sc = sc;
1062 c->uc_idx = i;
1063 c->uc_buflen = 0;
1064 c->uc_bufmax = bufsize;
1065 c->uc_cnt = 0;
1066 if (c->uc_xfer == NULL((void *)0)) {
1067 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev);
1068 if (c->uc_xfer == NULL((void *)0))
1069 return (ENOBUFS55);
1070 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax);
1071 if (c->uc_buf == NULL((void *)0)) {
1072 usbd_free_xfer(c->uc_xfer);
1073 c->uc_xfer = NULL((void *)0);
1074 return (ENOBUFS55);
1075 }
1076 }
1077 }
1078
1079 return (0);
1080}
1081
1082void
1083ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen)
1084{
1085 int i;
1086
1087 for (i = 0; i < listlen; i++) {
1088 if (ch[i].uc_buf != NULL((void *)0)) {
1089 ch[i].uc_buf = NULL((void *)0);
1090 }
1091 ch[i].uc_cnt = 0;
1092 if (ch[i].uc_xfer != NULL((void *)0)) {
1093 usbd_free_xfer(ch[i].uc_xfer);
1094 ch[i].uc_xfer = NULL((void *)0);
1095 }
1096 }
1097}
1098
1099void
1100ure_rtl8152_init(struct ure_softc *sc)
1101{
1102 uint32_t pwrctrl;
1103
1104 /* Disable ALDPS. */
1105 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 |
1106 URE_DIS_SDSAVE0x0010);
1107 usbd_delay_ms(sc->ure_udev, 20);
1108
1109 if (sc->ure_chip & URE_CHIP_VER_4C000x01)
1110 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
1111 URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
;
1112
1113 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT)ure_write_2(sc, 0xd800, 0x0000, ure_read_2(sc, 0xd800, 0x0000
) & ~(0x0100))
;
1114 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000
) & ~(0x0001))
1115 URE_RESUME_INDICATE)ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000
) & ~(0x0001))
;
1116
1117 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100
) | (0x0080 | 0x0040))
1118 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH)ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100
) | (0x0080 | 0x0040))
;
1119 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100);
1120 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK0x0f0f0f0f;
1121 pwrctrl |= URE_MCU_CLK_RATIO0x07010f07 | URE_D3_CLK_GATED_EN0x00004000;
1122 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, pwrctrl);
1123 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR0xe022, URE_MCU_TYPE_PLA0x0100,
1124 URE_GPHY_STS_MSK0x0001 | URE_SPEED_DOWN_MSK0x0002 | URE_SPDWN_RXDV_MSK0x0004 |
1125 URE_SPDWN_LINKCHG_MSK0x0008);
1126
1127 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001))
;
1128
1129 /* Enable Rx aggregation. */
1130 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
1131 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
;
1132}
1133
1134void
1135ure_rtl8153_init(struct ure_softc *sc)
1136{
1137 uint16_t reg;
1138 uint8_t u1u2[8];
1139 int i;
1140
1141 memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2)));
1142 ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2,
1143 sizeof(u1u2));
1144
1145 for (i = 0; i < 500; i++) {
1146 if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) &
1147 URE_AUTOLOAD_DONE0x0002)
1148 break;
1149 usbd_delay_ms(sc->ure_udev, 20);
1150 }
1151 if (i == 500)
1152 printf("%s: timeout waiting for chip autoload\n",
1153 sc->ure_dev.dv_xname);
1154
1155 ure_rtl8153_phy_status(sc, 0);
1156
1157 if (sc->ure_chip & (URE_CHIP_VER_5C000x04 | URE_CHIP_VER_5C100x08 |
1158 URE_CHIP_VER_5C200x10)) {
1159 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG0xbc06,
1160 URE_CKADSEL_L0x0100 | URE_ADC_EN0x0080 | URE_EN_EMI_L0x0040);
1161 }
1162
1163 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON3);
1164
1165 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001))
;
1166
1167 if (sc->ure_chip & URE_CHIP_VER_5C100x08) {
1168 reg = ure_read_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000);
1169 reg &= ~URE_PWD_DN_SCALE_MASK0x3ffe;
1170 reg |= URE_PWD_DN_SCALE(96)((96) << 1);
1171 ure_write_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000, reg);
1172
1173 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000
) | (0x0002 | 0x0001))
1174 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND)ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000
) | (0x0002 | 0x0001))
;
1175 } else if (sc->ure_chip & URE_CHIP_VER_5C200x10) {
1176 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100
) & ~(0x0002))
1177 URE_ECM_ALDPS)ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100
) & ~(0x0002))
;
1178 }
1179 if (sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) {
1180 if (ure_read_2(sc, URE_USB_BURST_SIZE0xcfc0, URE_MCU_TYPE_USB0x0000))
1181 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) | (0x0001))
1182 URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) | (0x0001))
;
1183 else
1184 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) & ~(0x0001))
1185 URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) & ~(0x0001))
;
1186 }
1187
1188 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC)ure_write_1(sc, 0xb466, 0x0000, ure_read_1(sc, 0xb466, 0x0000
) | (0x0001))
;
1189
1190 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN)ure_write_2(sc, 0xe43c, 0x0000, ure_read_2(sc, 0xe43c, 0x0000
) & ~(0x0001))
;
1191
1192 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
1193 URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
;
1194
1195 if ((sc->ure_chip & URE_CHIP_VER_5C100x08) &&
1196 sc->ure_udev->speed != USB_SPEED_SUPER4)
1197 reg = URE_LPM_TIMER_500MS0x04;
1198 else
1199 reg = URE_LPM_TIMER_500US0x0c;
1200 ure_write_1(sc, URE_USB_LPM_CTRL0xd41a, URE_MCU_TYPE_USB0x0000,
1201 URE_FIFO_EMPTY_1FB0x30 | URE_ROK_EXIT_LPM0x02 | reg);
1202
1203 reg = ure_read_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000);
1204 reg &= ~URE_SEN_VAL_MASK0xf800;
1205 reg |= URE_SEN_VAL_NORMAL0xa000 | URE_SEL_RXIDLE0x0100;
1206 ure_write_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000, reg);
1207
1208 ure_write_2(sc, URE_USB_CONNECT_TIMER0xcbf8, URE_MCU_TYPE_USB0x0000, 0x0001);
1209
1210 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001 | 0x0008))
1211 URE_PWR_EN | URE_PHASE2_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001 | 0x0008))
;
1212 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000
) & ~(0x0001))
;
1213
1214 memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2)));
1215 ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2,
1216 sizeof(u1u2));
1217
1218 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0);
1219 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, 0);
1220 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL30xe0cc, URE_MCU_TYPE_PLA0x0100, 0);
1221 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL40xe0ce, URE_MCU_TYPE_PLA0x0100, 0);
1222
1223 /* Enable Rx aggregation. */
1224 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
1225 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
;
1226
1227 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001))
;
1228}
1229
1230void
1231ure_rtl8153b_init(struct ure_softc *sc)
1232{
1233 uint16_t reg;
1234 int i;
1235
1236 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1237 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd26b, 0x0000, ure_read_1(sc, 0xd26b, 0x0000
) & ~(0x0001))
1238 URE_EN_ALL_SPEED)ure_write_1(sc, 0xd26b, 0x0000, ure_read_1(sc, 0xd26b, 0x0000
) & ~(0x0001))
;
1239 ure_write_2(sc, URE_USB_SPEED_OPTION0xd32a, URE_MCU_TYPE_USB0x0000, 0);
1240 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfee, 0x0000, ure_read_2(sc, 0xcfee, 0x0000
) | (0x0020))
1241 URE_BYPASS_MAC_RESET)ure_write_2(sc, 0xcfee, 0x0000, ure_read_2(sc, 0xcfee, 0x0000
) | (0x0020))
;
1242
1243 if (sc->ure_flags & URE_FLAG_8156B0x8000)
1244 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0008))
1245 URE_RX_DETECT8)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0008))
;
1246 }
1247
1248 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001))
;
1249
1250 if (sc->ure_flags & URE_FLAG_8156B0x8000)
1251 ure_wait_for_flash(sc);
1252
1253 for (i = 0; i < 500; i++) {
1254 if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) &
1255 URE_AUTOLOAD_DONE0x0002)
1256 break;
1257 usbd_delay_ms(sc->ure_udev, 20);
1258 }
1259 if (i == 500)
1260 printf("%s: timeout waiting for chip autoload\n",
1261 sc->ure_dev.dv_xname);
1262
1263 ure_rtl8153_phy_status(sc, 0);
1264 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON3);
1265
1266 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001))
;
1267
1268 /* MSC timer, 32760 ms. */
1269 ure_write_2(sc, URE_USB_MSC_TIMER0xcbfc, URE_MCU_TYPE_USB0x0000, 4095);
1270
1271 if (!(sc->ure_flags & URE_FLAG_8153B0x2000)) {
1272 /* U1/U2/L1 idle timer, 500 us. */
1273 ure_write_2(sc, URE_USB_U1U2_TIMER0xd4da, URE_MCU_TYPE_USB0x0000, 500);
1274 }
1275
1276 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001))
;
1277 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000
) & ~(0x0001))
;
1278
1279 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000
) & ~(0x0010 | 0x0020))
1280 URE_UPS_EN | URE_USP_PREWAKE)ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000
) & ~(0x0010 | 0x0020))
;
1281 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB,ure_write_1(sc, 0xcfff, 0x0000, ure_read_1(sc, 0xcfff, 0x0000
) & ~(0x01 | 0x80))
1282 URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS)ure_write_1(sc, 0xcfff, 0x0000, ure_read_1(sc, 0xcfff, 0x0000
) & ~(0x01 | 0x80))
;
1283
1284 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100
) & ~(0x01))
1285 URE_UPCOMING_RUNTIME_D3)ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100
) & ~(0x01))
;
1286 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100
) & ~(0x01))
1287 URE_LINK_CHG_EVENT)ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100
) & ~(0x01))
;
1288 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100
) & ~(0x0100))
1289 URE_LINK_CHANGE_FLAG)ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100
) & ~(0x0100))
;
1290
1291 ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0);
1292 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100
) & ~(0x0008))
1293 URE_LINK_OFF_WAKE_EN)ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100
) & ~(0x0008))
;
1294 ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);
1295
1296 if (sc->ure_flags & URE_FLAG_8153B0x2000) {
1297 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100);
1298 if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
1299 URE_PHYSTATUS_LINK0x0002)
1300 reg |= URE_CUR_LINK_OK0x8000;
1301 else
1302 reg &= ~URE_CUR_LINK_OK0x8000;
1303 ure_write_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100,
1304 reg | URE_POLL_LINK_CHG0x0001);
1305 }
1306
1307 if (sc->ure_udev->speed == USB_SPEED_SUPER4) {
1308 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
1309 LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
;
1310 }
1311
1312 if (sc->ure_flags & URE_FLAG_8156B0x8000) {
1313 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN)ure_write_2(sc, 0xc010, 0x0100, ure_read_2(sc, 0xc010, 0x0100
) & ~(0x00000800))
;
1314 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe854, 0x0100, ure_read_2(sc, 0xe854, 0x0100
) | (0x0001))
1315 URE_FLOW_CTRL_EN)ure_write_2(sc, 0xe854, 0x0100, ure_read_2(sc, 0xe854, 0x0100
) | (0x0001))
;
1316
1317 /* Enable fc timer and set timer to 600 ms. */
1318 ure_write_2(sc, URE_USB_FC_TIMER0xd340, URE_MCU_TYPE_USB0x0000,
1319 URE_CTRL_TIMER_EN0x8000 | 75);
1320
1321 reg = ure_read_2(sc, URE_USB_FW_CTRL0xd334, URE_MCU_TYPE_USB0x0000);
1322 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL0xdc6a, URE_MCU_TYPE_PLA0x0100) &
1323 URE_DACK_DET_EN0x8000))
1324 reg |= URE_FLOW_CTRL_PATCH_20x0100;
1325 reg &= ~URE_AUTO_SPEEDUP0x0008;
1326 ure_write_2(sc, URE_USB_FW_CTRL0xd334, URE_MCU_TYPE_USB0x0000, reg);
1327
1328 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
1329 URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
;
1330 }
1331
1332 /* MAC clock speed down. */
1333 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1334 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0x0403);
1335 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100);
1336 reg &= ~URE_EEE_SPDWN_RATIO_MASK0x00ff;
1337 reg |= URE_MAC_CLK_SPDWN_EN0x8000 | 0x0003;
1338 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, reg);
1339
1340 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
1341 URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
;
1342
1343 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100);
1344 if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
1345 URE_PHYSTATUS_LINK0x0002)
1346 reg |= URE_CUR_LINK_OK0x8000;
1347 else
1348 reg &= ~URE_CUR_LINK_OK0x8000;
1349 ure_write_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100,
1350 reg | URE_POLL_LINK_CHG0x0001);
1351 } else
1352 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100
) | (0x8000))
1353 URE_MAC_CLK_SPDWN_EN)ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100
) | (0x8000))
;
1354
1355 /* Enable Rx aggregation. */
1356 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
1357 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
;
1358
1359 if (sc->ure_flags & URE_FLAG_81560x4000)
1360 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd4b4, 0x0000, ure_read_1(sc, 0xd4b4, 0x0000
) | (0x02))
1361 URE_ACT_ODMA)ure_write_1(sc, 0xd4b4, 0x0000, ure_read_1(sc, 0xd4b4, 0x0000
) | (0x02))
;
1362
1363 if (!(sc->ure_flags & URE_FLAG_8153B0x2000)) {
1364 /*
1365 * Select force mode through 0xa5b4 bit 15
1366 * 0: MDIO force mode
1367 * 1: MMD force mode
1368 */
1369 reg = ure_ocp_reg_read(sc, 0xa5b4);
1370 if (reg & 0x8000)
1371 ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000);
1372 }
1373
1374 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001))
;
1375}
1376
1377void
1378ure_rtl8152_nic_reset(struct ure_softc *sc)
1379{
1380 uint32_t rx_fifo1, rx_fifo2;
1381 int i;
1382
1383 /* Disable ALDPS. */
1384 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 |
1385 URE_DIS_SDSAVE0x0010);
1386 usbd_delay_ms(sc->ure_udev, 20);
1387
1388 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100
) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008)
))
;
1389
1390 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) | (0x0008))
;
1391 ure_disable_teredo(sc);
1392 ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);
1393 ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, 0);
1394
1395 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100
) & ~(0x80))
;
1396 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) & ~(0x4000))
;
1397 for (i = 0; i < URE_TIMEOUT1000; i++) {
1398 if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
1399 URE_LINK_LIST_READY0x02)
1400 break;
1401 usbd_delay_ms(sc->ure_udev, 1);
1402 }
1403 if (i == URE_TIMEOUT1000)
1404 printf("%s: timeout waiting for OOB control\n",
1405 sc->ure_dev.dv_xname);
1406 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000))
;
1407 for (i = 0; i < URE_TIMEOUT1000; i++) {
1408 if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
1409 URE_LINK_LIST_READY0x02)
1410 break;
1411 usbd_delay_ms(sc->ure_udev, 1);
1412 }
1413 if (i == URE_TIMEOUT1000)
1414 printf("%s: timeout waiting for OOB control\n",
1415 sc->ure_dev.dv_xname);
1416
1417 ure_reset(sc);
1418
1419 /* Configure Rx FIFO threshold. */
1420 ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100,
1421 URE_RXFIFO_THR1_NORMAL0x00080002);
1422 if (sc->ure_udev->speed == USB_SPEED_FULL2) {
1423 rx_fifo1 = URE_RXFIFO_THR2_FULL0x00000060;
1424 rx_fifo2 = URE_RXFIFO_THR3_FULL0x00000078;
1425 } else {
1426 rx_fifo1 = URE_RXFIFO_THR2_HIGH0x00000038;
1427 rx_fifo2 = URE_RXFIFO_THR3_HIGH0x00000048;
1428 }
1429 ure_write_4(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100, rx_fifo1);
1430 ure_write_4(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100, rx_fifo2);
1431
1432 /* Configure Tx FIFO threshold. */
1433 ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100,
1434 URE_TXFIFO_THR_NORMAL0x00400008);
1435
1436 ure_write_1(sc, URE_USB_TX_AGG0xd40a, URE_MCU_TYPE_USB0x0000,
1437 URE_TX_AGG_MAX_THRESHOLD0x03);
1438 ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000, URE_RX_THR_HIGH0x7a120180);
1439 ure_write_4(sc, URE_USB_TX_DMA0xd434, URE_MCU_TYPE_USB0x0000,
1440 URE_TEST_MODE_DISABLE0x00000001 | URE_TX_SIZE_ADJUST10x00000100);
1441
1442 ure_rxvlan(sc);
1443 ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100,
1444 ETHER_MAX_LEN1518 + ETHER_VLAN_ENCAP_LEN4);
1445 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080))
;
1446
1447 /* Enable ALDPS. */
1448 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010,
1449 URE_ENPWRSAVE0x8000 | URE_ENPDNPS0x0200 | URE_LINKENA0x0100 | URE_DIS_SDSAVE0x0010);
1450}
1451
1452void
1453ure_rtl8153_nic_reset(struct ure_softc *sc)
1454{
1455 struct ifnet *ifp = &sc->ure_ac.ac_if;
1456 uint32_t reg = 0;
1457 uint8_t u1u2[8] = { 0 };
1458 int i;
1459
1460 if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1461 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001))
1462 LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001))
;
1463 } else {
1464 memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2)));
1465 ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f,
1466 u1u2, sizeof(u1u2));
1467 }
1468 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001))
;
1469
1470 /* Disable ALDPS. */
1471 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430,
1472 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) & ~URE_EN_ALDPS0x0004);
1473 for (i = 0; i < 20; i++) {
1474 usbd_delay_ms(sc->ure_udev, 1);
1475 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA0x0100) & 0x0100)
1476 break;
1477 }
1478
1479 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) | (0x0008))
;
1480 ure_disable_teredo(sc);
1481
1482 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100
) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008)
))
;
1483
1484 ure_reset(sc);
1485 ure_reset_bmu(sc);
1486
1487 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100
) & ~(0x80))
;
1488 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) & ~(0x4000))
;
1489
1490 if (!(sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))) {
1491 for (i = 0; i < URE_TIMEOUT1000; i++) {
1492 if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
1493 URE_LINK_LIST_READY0x02)
1494 break;
1495 usbd_delay_ms(sc->ure_udev, 1);
1496 }
1497 if (i == URE_TIMEOUT1000)
1498 printf("%s: timeout waiting for OOB control\n",
1499 sc->ure_dev.dv_xname);
1500 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000))
1501 URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000))
;
1502 for (i = 0; i < URE_TIMEOUT1000; i++) {
1503 if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
1504 URE_LINK_LIST_READY0x02)
1505 break;
1506 usbd_delay_ms(sc->ure_udev, 1);
1507 }
1508 if (i == URE_TIMEOUT1000)
1509 printf("%s: timeout waiting for OOB control\n",
1510 sc->ure_dev.dv_xname);
1511 }
1512
1513 ure_rxvlan(sc);
1514
1515 ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100,
1516 URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4));
1517 ure_write_1(sc, URE_PLA_MTPS0xe615, URE_MCU_TYPE_PLA0x0100, MTPS_JUMBO192);
1518
1519 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1520 ure_write_2(sc, URE_PLA_RX_FIFO_FULL0xc0a6, URE_MCU_TYPE_PLA0x0100,
1521 (sc->ure_flags & URE_FLAG_81560x4000) ? 1024 : 512);
1522 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY0xc0aa, URE_MCU_TYPE_PLA0x0100,
1523 (sc->ure_flags & URE_FLAG_81560x4000) ? 2048 : 1024);
1524
1525 /* Tx share fifo free credit full threshold. */
1526 ure_write_2(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100, 8);
1527 ure_write_2(sc, URE_PLA_TXFIFO_FULL0xe61a, URE_MCU_TYPE_PLA0x0100, 128);
1528
1529 if (sc->ure_flags & URE_FLAG_81560x4000)
1530 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b4, 0x0000, ure_read_2(sc, 0xd4b4, 0x0000
) | (0x02))
1531 URE_ACT_ODMA)ure_write_2(sc, 0xd4b4, 0x0000, ure_read_2(sc, 0xd4b4, 0x0000
) | (0x02))
;
1532
1533 /* FIFO settings */
1534 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL0xc0a2, URE_MCU_TYPE_PLA0x0100);
1535 reg &= ~URE_RXFIFO_FULL_MASK0x0fff;
1536 ure_write_2(sc, URE_PLA_RXFIFO_FULL0xc0a2, URE_MCU_TYPE_PLA0x0100,
1537 reg | 0x0008);
1538
1539 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
1540 URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
;
1541
1542 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd32a, 0x0000, ure_read_2(sc, 0xd32a, 0x0000
) & ~(0x0100 | 0x0200))
1543 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF)ure_write_2(sc, 0xd32a, 0x0000, ure_read_2(sc, 0xd32a, 0x0000
) & ~(0x0100 | 0x0200))
;
1544
1545 ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000,
1546 0x00600400);
1547 } else {
1548 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080))
1549 URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080))
;
1550 ure_reset(sc);
1551
1552 /* Configure Rx FIFO threshold. */
1553 ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100,
1554 URE_RXFIFO_THR1_NORMAL0x00080002);
1555 ure_write_2(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100,
1556 URE_RXFIFO_THR2_NORMAL0x00a0);
1557 ure_write_2(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100,
1558 URE_RXFIFO_THR3_NORMAL0x0110);
1559
1560 /* Configure Tx FIFO threshold. */
1561 ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100,
1562 URE_TXFIFO_THR_NORMAL20x01000008);
1563
1564 if (sc->ure_flags & URE_FLAG_8153B0x2000) {
1565 ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000,
1566 URE_RX_THR_B0x00010001);
1567
1568 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
1569 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
;
1570 } else {
1571 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xe90a, 0x0100, ure_read_1(sc, 0xe90a, 0x0100
) | (0x01))
1572 URE_LANWAKE_CLR_EN)ure_write_1(sc, 0xe90a, 0x0100, ure_read_1(sc, 0xe90a, 0x0100
) | (0x01))
;
1573 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG,ure_write_1(sc, 0xe007, 0x0100, ure_read_1(sc, 0xe007, 0x0100
) & ~(0x80))
1574 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN)ure_write_1(sc, 0xe007, 0x0100, ure_read_1(sc, 0xe007, 0x0100
) & ~(0x80))
;
1575 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb426, 0x0000, ure_read_2(sc, 0xb426, 0x0000
) & ~(0x0002))
1576 URE_DELAY_PHY_PWR_CHG)ure_write_2(sc, 0xb426, 0x0000, ure_read_2(sc, 0xb426, 0x0000
) & ~(0x0002))
;
1577 }
1578 }
1579
1580 /* Enable ALDPS. */
1581 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430,
1582 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) | URE_EN_ALDPS0x0004);
1583
1584 if ((sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) ||
1585 (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)))
1586 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0001))
1587 URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0001))
;
1588
1589 if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1590 if (sc->ure_udev->speed == USB_SPEED_SUPER4)
1591 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
1592 LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
;
1593 } else {
1594 memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2)));
1595 ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f,
1596 u1u2, sizeof(u1u2));
1597 }
1598}
1599
1600uint16_t
1601ure_rtl8153_phy_status(struct ure_softc *sc, int desired)
1602{
1603 uint16_t reg;
1604 int i;
1605
1606 for (i = 0; i < 500; i++) {
1607 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS0xa420) &
1608 URE_PHY_STAT_MASK0x0007;
1609 if (desired) {
1610 if (reg == desired)
1611 break;
1612 } else {
1613 if (reg == URE_PHY_STAT_LAN_ON3 ||
1614 reg == URE_PHY_STAT_PWRDN5 ||
1615 reg == URE_PHY_STAT_EXT_INIT2)
1616 break;
1617 }
1618 usbd_delay_ms(sc->ure_udev, 20);
1619 }
1620 if (i == 500)
1621 printf("%s: timeout waiting for phy to stabilize\n",
1622 sc->ure_dev.dv_xname);
1623
1624 return reg;
1625}
1626
1627void
1628ure_wait_for_flash(struct ure_softc *sc)
1629{
1630 int i;
1631
1632 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL0xd3ae, URE_MCU_TYPE_PLA0x0100) &
1633 URE_GPHY_FLASH0x0002) &&
1634 !(ure_read_2(sc, URE_USB_GPHY_CTRL0xd284, URE_MCU_TYPE_USB0x0000) &
1635 URE_BYPASS_FLASH0x0020)) {
1636 for (i = 0; i < 100; i++) {
1637 if (ure_read_2(sc, URE_USB_GPHY_CTRL0xd284,
1638 URE_MCU_TYPE_USB0x0000) & URE_GPHY_PATCH_DONE0x0004)
1639 break;
1640 DELAY(1000)(*delay_func)(1000);
1641 }
1642 if (i == 100)
1643 printf("%s: timeout waiting for loading flash\n",
1644 sc->ure_dev.dv_xname);
1645 }
1646}
1647
1648void
1649ure_reset_bmu(struct ure_softc *sc)
1650{
1651 uint8_t reg;
1652
1653 reg = ure_read_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000);
1654 reg &= ~(BMU_RESET_EP_IN0x01 | BMU_RESET_EP_OUT0x02);
1655 ure_write_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000, reg);
1656 reg |= BMU_RESET_EP_IN0x01 | BMU_RESET_EP_OUT0x02;
1657 ure_write_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000, reg);
1658}
1659
1660void
1661ure_disable_teredo(struct ure_softc *sc)
1662{
1663 if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
1664 ure_write_1(sc, URE_PLA_TEREDO_CFG0xc0bc, URE_MCU_TYPE_PLA0x0100, 0xff);
1665 else {
1666 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001))
1667 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK |ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001))
1668 URE_OOB_TEREDO_EN)ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001))
;
1669 }
1670 ure_write_2(sc, URE_PLA_WDT6_CTRL0xe428, URE_MCU_TYPE_PLA0x0100, URE_WDT6_SET_MODE0x0010);
1671 ure_write_2(sc, URE_PLA_REALWOW_TIMER0xd2e8, URE_MCU_TYPE_PLA0x0100, 0);
1672 ure_write_4(sc, URE_PLA_TEREDO_TIMER0xd2cc, URE_MCU_TYPE_PLA0x0100, 0);
1673}
1674
1675int
1676ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1677{
1678 struct ure_softc *sc = ifp->if_softc;
1679 struct ifreq *ifr = (struct ifreq *)data;
1680 int s, error = 0;
1681
1682 s = splnet()splraise(0x4);
1683
1684 switch (cmd) {
1685 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12)))
:
1686 ifp->if_flags |= IFF_UP0x1;
1687 if (!(ifp->if_flags & IFF_RUNNING0x40))
1688 ure_init(sc);
1689 break;
1690
1691 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16)))
:
1692 if (ifp->if_flags & IFF_UP0x1) {
1693 if (ifp->if_flags & IFF_RUNNING0x40)
1694 error = ENETRESET52;
1695 else
1696 ure_init(sc);
1697 } else {
1698 if (ifp->if_flags & IFF_RUNNING0x40)
1699 ure_stop(sc);
1700 }
1701 break;
1702
1703 case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
8) | ((56)))
:
1704 case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
8) | ((55)))
:
1705 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
1706 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd);
1707 else
1708 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media,
1709 cmd);
1710 break;
1711
1712 default:
1713 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data);
1714 }
1715
1716 if (error == ENETRESET52) {
1717 if (ifp->if_flags & IFF_RUNNING0x40)
1718 ure_iff(sc);
1719 error = 0;
1720 }
1721
1722 splx(s)spllower(s);
1723
1724 return (error);
1725}
1726
1727int
1728ure_match(struct device *parent, void *match, void *aux)
1729{
1730 struct usb_attach_arg *uaa = aux;
1731
1732 if (uaa->iface == NULL((void *)0) || uaa->configno != 1)
1733 return (UMATCH_NONE0);
1734
1735 return (usb_lookup(ure_devs, uaa->vendor, uaa->product)usbd_match_device((const struct usb_devno *)(ure_devs), sizeof
(ure_devs) / sizeof ((ure_devs)[0]), sizeof ((ure_devs)[0]),
(uaa->vendor), (uaa->product))
!= NULL((void *)0) ?
1736 UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0);
1737}
1738
1739void
1740ure_attach(struct device *parent, struct device *self, void *aux)
1741{
1742 struct ure_softc *sc = (struct ure_softc *)self;
1743 struct usb_attach_arg *uaa = aux;
1744 usb_interface_descriptor_t *id;
1745 usb_endpoint_descriptor_t *ed;
1746 u_char eaddr[8]; /* 4byte padded */
1747 struct ifnet *ifp;
1748 int i, mii_flags = 0, s;
1749 uint16_t ver;
1750
1751 sc->ure_udev = uaa->device;
1752 sc->ure_iface = uaa->iface;
1753
1754 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc,((&sc->ure_tick_task)->fun = (ure_tick_task), (&
sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task
)->type = (0), (&sc->ure_tick_task)->state = 0x0
)
1755 USB_TASK_TYPE_GENERIC)((&sc->ure_tick_task)->fun = (ure_tick_task), (&
sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task
)->type = (0), (&sc->ure_tick_task)->state = 0x0
)
;
1756
1757 id = usbd_get_interface_descriptor(sc->ure_iface);
1758
1759 for (i = 0; i < id->bNumEndpoints; i++) {
1760 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i);
1761 if (!ed) {
1762 printf("%s: couldn't get ep %d\n",
1763 sc->ure_dev.dv_xname, i);
1764 return;
1765 }
1766 if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80 &&
1767 UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) {
1768 sc->ure_ed[URE_ENDPT_RX0] = ed->bEndpointAddress;
1769 } else if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_OUT0x00 &&
1770 UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) {
1771 sc->ure_ed[URE_ENDPT_TX1] = ed->bEndpointAddress;
1772 }
1773 }
1774
1775 sc->ure_txbufsz = URE_TX_BUFSZ16384;
1776 sc->ure_rxbufsz = URE_8153_RX_BUFSZ32768;
1777
1778 s = splnet()splraise(0x4);
1779
1780 sc->ure_phyno = 0;
1781 printf("%s: ", sc->ure_dev.dv_xname);
1782
1783 ver = ure_read_2(sc, URE_PLA_TCR10xe612, URE_MCU_TYPE_PLA0x0100) & URE_VERSION_MASK0x7cf0;
1784 switch (ver) {
1785 case 0x4c00:
1786 sc->ure_flags = URE_FLAG_81520x1000;
1787 sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384;
1788 sc->ure_chip |= URE_CHIP_VER_4C000x01;
1789 printf("RTL8152 (0x4c00)");
1790 break;
1791 case 0x4c10:
1792 sc->ure_flags = URE_FLAG_81520x1000;
1793 sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384;
1794 sc->ure_chip |= URE_CHIP_VER_4C100x02;
1795 printf("RTL8152 (0x4c10)");
1796 break;
1797 case 0x5c00:
1798 sc->ure_chip |= URE_CHIP_VER_5C000x04;
1799 printf("RTL8153 (0x5c00)");
1800 break;
1801 case 0x5c10:
1802 sc->ure_chip |= URE_CHIP_VER_5C100x08;
1803 printf("RTL8153 (0x5c10)");
1804 break;
1805 case 0x5c20:
1806 sc->ure_chip |= URE_CHIP_VER_5C200x10;
1807 printf("RTL8153 (0x5c20)");
1808 break;
1809 case 0x5c30:
1810 sc->ure_chip |= URE_CHIP_VER_5C300x20;
1811 printf("RTL8153 (0x5c30)");
1812 break;
1813 case 0x6000:
1814 sc->ure_flags = URE_FLAG_8153B0x2000;
1815 printf("RTL8153B (0x6000)");
1816 break;
1817 case 0x6010:
1818 sc->ure_flags = URE_FLAG_8153B0x2000;
1819 printf("RTL8153B (0x6010)");
1820 break;
1821 case 0x7020:
1822 sc->ure_flags = URE_FLAG_81560x4000;
1823 printf("RTL8156 (0x7020)");
1824 break;
1825 case 0x7030:
1826 sc->ure_flags = URE_FLAG_81560x4000;
1827 printf("RTL8156 (0x7030)");
1828 break;
1829 case 0x7410:
1830 sc->ure_flags = URE_FLAG_8156B0x8000;
1831 printf("RTL8156B (0x7410)");
1832 break;
1833 case 0x7420:
1834 sc->ure_flags = URE_FLAG_8156B0x8000;
1835 sc->ure_chip = URE_CHIP_VER_74200x80;
1836 printf("RTL8153D (0x7420)");
1837 break;
1838 default:
1839 printf(", unknown ver %02x", ver);
1840 break;
1841 }
1842
1843 if (sc->ure_flags & URE_FLAG_81520x1000)
1844 ure_rtl8152_init(sc);
1845 else if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 |
1846 URE_FLAG_8156B0x8000))
1847 ure_rtl8153b_init(sc);
1848 else
1849 ure_rtl8153_init(sc);
1850
1851 if (sc->ure_chip & URE_CHIP_VER_4C000x01)
1852 ure_read_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100, eaddr,
1853 sizeof(eaddr));
1854 else
1855 ure_read_mem(sc, URE_PLA_BACKUP0xd000, URE_MCU_TYPE_PLA0x0100, eaddr,
1856 sizeof(eaddr));
1857
1858 printf(", address %s\n", ether_sprintf(eaddr));
1859
1860 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN6);
1861
1862 ifp = &sc->ure_ac.ac_if;
1863 ifp->if_softc = sc;
1864 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ16);
1865 ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
1866 ifp->if_ioctl = ure_ioctl;
1867 ifp->if_start = ure_start;
1868 ifp->if_watchdog = ure_watchdog;
1869
1870 ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_IPv40x00000001 |
1871 IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004;
1872
1873#if NVLAN1 > 0
1874 ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1875#endif
1876
1877 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
1878 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK0xff00000000000000ULL, ure_ifmedia_upd,
1879 ure_ifmedia_sts);
1880 ure_add_media_types(sc);
1881 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
1882 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
1883 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media;
1884 } else {
1885 rw_init(&sc->ure_mii_lock, "uremii")_rw_init_flags(&sc->ure_mii_lock, "uremii", 0, ((void *
)0))
;
1886
1887 sc->ure_mii.mii_ifp = ifp;
1888 sc->ure_mii.mii_readreg = ure_miibus_readreg;
1889 sc->ure_mii.mii_writereg = ure_miibus_writereg;
1890 sc->ure_mii.mii_statchg = ure_miibus_statchg;
1891 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP0x0010;
1892
1893 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd,
1894 ure_ifmedia_sts);
1895 if (!(sc->ure_flags & URE_FLAG_81520x1000))
1896 mii_flags |= MIIF_DOPAUSE0x0100;
1897 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno,
1898 MII_OFFSET_ANY-1, mii_flags);
1899 if (LIST_FIRST(&sc->ure_mii.mii_phys)((&sc->ure_mii.mii_phys)->lh_first) == NULL((void *)0)) {
1900 ifmedia_add(&sc->ure_mii.mii_media,
1901 IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL, 0, NULL((void *)0));
1902 ifmedia_set(&sc->ure_mii.mii_media,
1903 IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL);
1904 } else
1905 ifmedia_set(&sc->ure_mii.mii_media,
1906 IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
1907 }
1908
1909 if_attach(ifp);
1910 ether_ifattach(ifp);
1911
1912 timeout_set(&sc->ure_stat_ch, ure_tick, sc);
1913
1914 splx(s)spllower(s);
1915}
1916
1917int
1918ure_detach(struct device *self, int flags)
1919{
1920 struct ure_softc *sc = (struct ure_softc *)self;
1921 struct ifnet *ifp = &sc->ure_ac.ac_if;
1922 int s;
1923
1924 if (timeout_initialized(&sc->ure_stat_ch)((&sc->ure_stat_ch)->to_flags & 0x04))
1925 timeout_del(&sc->ure_stat_ch);
1926
1927 if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0))
1928 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX1]);
1929 if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0))
1930 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX0]);
1931
1932 usb_rem_task(sc->ure_udev, &sc->ure_tick_task);
1933
1934 s = splusb()splraise(0x2);
1935
1936 if (--sc->ure_refcnt >= 0) {
1937 usb_detach_wait(&sc->ure_dev);
1938 }
1939
1940 if (ifp->if_flags & IFF_RUNNING0x40)
1941 ure_stop(sc);
1942
1943 mii_detach(&sc->ure_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);
1944 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY((uint64_t) -1));
1945 if (ifp->if_softc != NULL((void *)0)) {
1946 ether_ifdetach(ifp);
1947 if_detach(ifp);
1948 }
1949
1950 splx(s)spllower(s);
1951
1952 return 0;
1953}
1954
1955void
1956ure_tick_task(void *xsc)
1957{
1958 struct ure_softc *sc = xsc;
1959 struct mii_data *mii;
1960 int s;
1961
1962 if (sc == NULL((void *)0))
1963 return;
1964
1965 if (usbd_is_dying(sc->ure_udev))
1966 return;
1967 mii = &sc->ure_mii;
1968
1969 s = splnet()splraise(0x4);
1970 if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
1971 ure_link_state(sc);
1972 else {
1973 mii_tick(mii);
1974 if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0)
1975 ure_miibus_statchg(&sc->ure_dev);
1976 }
1977 timeout_add_sec(&sc->ure_stat_ch, 1);
1978 splx(s)spllower(s);
1979}
1980
1981void
1982ure_lock_mii(struct ure_softc *sc)
1983{
1984 sc->ure_refcnt++;
1985 rw_enter_write(&sc->ure_mii_lock);
1986}
1987
1988void
1989ure_unlock_mii(struct ure_softc *sc)
1990{
1991 rw_exit_write(&sc->ure_mii_lock);
1992 if (--sc->ure_refcnt < 0)
1993 usb_detach_wakeup(&sc->ure_dev);
1994}
1995
1996void
1997ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1998{
1999 struct ure_chain *c = (struct ure_chain *)priv;
2000 struct ure_softc *sc = c->uc_sc;
2001 struct ifnet *ifp = &sc->ure_ac.ac_if;
2002 u_char *buf = c->uc_buf;
2003 uint32_t cflags, rxvlan, total_len;
2004 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
2005 struct mbuf *m;
2006 int pktlen = 0, s;
2007 struct ure_rxpkt rxhdr;
2008
2009 if (usbd_is_dying(sc->ure_udev))
2010 return;
2011
2012 if (!(ifp->if_flags & IFF_RUNNING0x40))
2013 return;
2014
2015 if (status != USBD_NORMAL_COMPLETION) {
2016 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
2017 return;
2018 if (usbd_ratecheck(&sc->ure_rx_notice)) {
2019 printf("%s: usb errors on rx: %s\n",
2020 sc->ure_dev.dv_xname, usbd_errstr(status));
2021 }
2022 if (status == USBD_STALLED)
2023 usbd_clear_endpoint_stall_async(
2024 sc->ure_ep[URE_ENDPT_RX0]);
2025 goto done;
2026 }
2027
2028 usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &total_len, NULL((void *)0));
2029 DPRINTFN(3, ("received %d bytes\n", total_len));
2030
2031 do {
2032 if (total_len < sizeof(rxhdr)) {
2033 DPRINTF(("too few bytes left for a packet header\n"));
2034 ifp->if_ierrorsif_data.ifi_ierrors++;
2035 goto done;
2036 }
2037
2038 buf += roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8));
2039
2040 memcpy(&rxhdr, buf, sizeof(rxhdr))__builtin_memcpy((&rxhdr), (buf), (sizeof(rxhdr)));
2041 total_len -= sizeof(rxhdr);
2042
2043 pktlen = letoh32(rxhdr.ure_pktlen)((__uint32_t)(rxhdr.ure_pktlen)) & URE_RXPKT_LEN_MASK0x7fff;
2044 DPRINTFN(4, ("next packet is %d bytes\n", pktlen));
2045 if (pktlen > total_len) {
2046 DPRINTF(("not enough bytes left for next packet\n"));
2047 ifp->if_ierrorsif_data.ifi_ierrors++;
2048 goto done;
2049 }
2050
2051 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8));
2052 buf += sizeof(rxhdr);
2053
2054 m = m_devget(buf, pktlen - ETHER_CRC_LEN4, ETHER_ALIGN2);
2055 if (m == NULL((void *)0)) {
2056 DPRINTF(("unable to allocate mbuf for next packet\n"));
2057 ifp->if_ierrorsif_data.ifi_ierrors++;
2058 goto done;
2059 }
2060
2061 cflags = letoh32(rxhdr.ure_csum)((__uint32_t)(rxhdr.ure_csum));
2062 rxvlan = letoh32(rxhdr.ure_vlan)((__uint32_t)(rxhdr.ure_vlan));
2063
2064 /* Check IP header checksum. */
2065 if ((rxvlan & URE_RXPKT_IPV4(1 << 19)) &&
2066 !(cflags & URE_RXPKT_IPSUMBAD(1 << 23)))
2067 m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;
2068
2069 /* Check TCP/UDP checksum. */
2070 if ((rxvlan & (URE_RXPKT_IPV4(1 << 19) | URE_RXPKT_IPV6(1 << 20))) &&
2071 (((rxvlan & URE_RXPKT_TCP(1 << 22)) &&
2072 !(cflags & URE_RXPKT_TCPSUMBAD(1 << 21))) ||
2073 ((rxvlan & URE_RXPKT_UDP(1 << 23)) &&
2074 !(cflags & URE_RXPKT_UDPSUMBAD(1 << 22)))))
2075 m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 |
2076 M_UDP_CSUM_IN_OK0x0080;
2077#if NVLAN1 > 0
2078 if (rxvlan & URE_RXPKT_VLAN_TAG(1 << 16)) {
2079 m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag =
2080 swap16(rxvlan & URE_RXPKT_VLAN_DATA)(__uint16_t)(__builtin_constant_p(rxvlan & 0xffff) ? (__uint16_t
)(((__uint16_t)(rxvlan & 0xffff) & 0xffU) << 8 |
((__uint16_t)(rxvlan & 0xffff) & 0xff00U) >> 8
) : __swap16md(rxvlan & 0xffff))
;
2081 m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
2082 }
2083#endif
2084
2085 ml_enqueue(&ml, m);
2086 } while (total_len > 0);
2087
2088done:
2089 s = splnet()splraise(0x4);
2090 if_input(ifp, &ml);
2091 splx(s)spllower(s);
2092 memset(c->uc_buf, 0, sc->ure_rxbufsz)__builtin_memset((c->uc_buf), (0), (sc->ure_rxbufsz));
2093
2094 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX0], c, c->uc_buf,
2095 sc->ure_rxbufsz, USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
2096 USBD_NO_TIMEOUT0, ure_rxeof);
2097 usbd_transfer(xfer);
2098}
2099
2100
2101void
2102ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2103{
2104 struct ure_softc *sc;
2105 struct ure_chain *c;
2106 struct ifnet *ifp;
2107 int s;
2108
2109 c = priv;
2110 sc = c->uc_sc;
2111 ifp = &sc->ure_ac.ac_if;
2112
2113 if (usbd_is_dying(sc->ure_udev))
2114 return;
2115
2116 if (status != USBD_NORMAL_COMPLETION)
2117 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname,
2118 __func__, c->uc_idx, usbd_errstr(status)));
2119
2120 s = splnet()splraise(0x4);
2121
2122 c->uc_cnt = 0;
2123 c->uc_buflen = 0;
2124
2125 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list)do { (c)->uc_list.sle_next = (&sc->ure_cdata.ure_tx_free
)->slh_first; (&sc->ure_cdata.ure_tx_free)->slh_first
= (c); } while (0)
;
2126
2127 if (status != USBD_NORMAL_COMPLETION) {
2128 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
2129 splx(s)spllower(s);
2130 return;
2131 }
2132
2133 ifp->if_oerrorsif_data.ifi_oerrors++;
2134 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname,
2135 usbd_errstr(status));
2136
2137 if (status == USBD_STALLED)
2138 usbd_clear_endpoint_stall_async(
2139 sc->ure_ep[URE_ENDPT_TX1]);
2140 splx(s)spllower(s);
2141 return;
2142 }
2143
2144 ifp->if_timer = 0;
2145 if (ifq_is_oactive(&ifp->if_snd))
2146 ifq_restart(&ifp->if_snd);
2147 splx(s)spllower(s);
2148}
2149
2150int
2151ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen)
2152{
2153 struct ure_txpkt txhdr;
2154 uint32_t len = sizeof(txhdr), cflags = 0;
2155
2156 if (len + m->m_pkthdrM_dat.MH.MH_pkthdr.len > maxlen)
2157 return (-1);
2158
2159 if ((m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &
2160 (M_IPV4_CSUM_OUT0x0001 | M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004)) != 0) {
2161 cflags |= URE_TXPKT_IPV4(1 << 29);
2162 if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002)
2163 cflags |= URE_TXPKT_TCP(1 << 30);
2164 if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004)
2165 cflags |= URE_TXPKT_UDP(1U << 31);
2166 }
2167
2168#if NVLAN1 > 0
2169 if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020)
2170 cflags |= URE_TXPKT_VLAN_TAG(1 << 16) | swap16(m->m_pkthdr.ether_vtag)(__uint16_t)(__builtin_constant_p(m->M_dat.MH.MH_pkthdr.ether_vtag
) ? (__uint16_t)(((__uint16_t)(m->M_dat.MH.MH_pkthdr.ether_vtag
) & 0xffU) << 8 | ((__uint16_t)(m->M_dat.MH.MH_pkthdr
.ether_vtag) & 0xff00U) >> 8) : __swap16md(m->M_dat
.MH.MH_pkthdr.ether_vtag))
;
2171#endif
2172
2173 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS |((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1U << 31)
| (1 << 30)))
2174 URE_TXPKT_TX_LS)((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1U << 31)
| (1 << 30)))
;
2175 txhdr.ure_vlan = htole32(cflags)((__uint32_t)(cflags));
2176 memcpy(buf, &txhdr, len)__builtin_memcpy((buf), (&txhdr), (len));
2177
2178 m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, buf + len);
2179 len += m->m_pkthdrM_dat.MH.MH_pkthdr.len;
2180
2181 return (len);
2182}
2183
2184int
2185ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c)
2186{
2187 usbd_status err;
2188
2189 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX1], c, c->uc_buf,
2190 c->uc_buflen, USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, 10000,
2191 ure_txeof);
2192
2193 err = usbd_transfer(c->uc_xfer);
2194 if (err != USBD_IN_PROGRESS) {
2195 c->uc_cnt = 0;
2196 c->uc_buflen = 0;
2197 ure_stop(sc);
2198 return (EIO5);
2199 }
2200
2201 return (0);
2202}