Bug Summary

File:dev/pci/drm/amd/amdgpu/dce_v11_0.c
Warning:line 1285, column 3
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dce_v11_0.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/dce_v11_0.c
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "vid.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v11_0.h"
39
40#include "dce/dce_11_0_d.h"
41#include "dce/dce_11_0_sh_mask.h"
42#include "dce/dce_11_0_enum.h"
43#include "oss/oss_3_0_d.h"
44#include "oss/oss_3_0_sh_mask.h"
45#include "gmc/gmc_8_1_d.h"
46#include "gmc/gmc_8_1_sh_mask.h"
47
48#include "ivsrcid/ivsrcid_vislands30.h"
49
50static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
51static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
52
53static const u32 crtc_offsets[] =
54{
55 CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c),
56 CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c),
57 CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c),
58 CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c),
59 CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c),
60 CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c),
61 CRTC6_REGISTER_OFFSET(0x479c - 0x1b9c)
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET(0x1898 - 0x1898),
67 HPD1_REGISTER_OFFSET(0x18a0 - 0x1898),
68 HPD2_REGISTER_OFFSET(0x18a8 - 0x1898),
69 HPD3_REGISTER_OFFSET(0x18b0 - 0x1898),
70 HPD4_REGISTER_OFFSET(0x18b8 - 0x1898),
71 HPD5_REGISTER_OFFSET(0x18c0 - 0x1898)
72};
73
74static const uint32_t dig_offsets[] = {
75 DIG0_REGISTER_OFFSET(0x4a00 - 0x4a00),
76 DIG1_REGISTER_OFFSET(0x4b00 - 0x4a00),
77 DIG2_REGISTER_OFFSET(0x4c00 - 0x4a00),
78 DIG3_REGISTER_OFFSET(0x4d00 - 0x4a00),
79 DIG4_REGISTER_OFFSET(0x4e00 - 0x4a00),
80 DIG5_REGISTER_OFFSET(0x4f00 - 0x4a00),
81 DIG6_REGISTER_OFFSET(0x5400 - 0x4a00),
82 DIG7_REGISTER_OFFSET(0x5600 - 0x4a00),
83 DIG8_REGISTER_OFFSET(0x5700 - 0x4a00)
84};
85
86static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92} interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS0x1857,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK0x8,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK0x4,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK0x20000
97}, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE0x1858,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK0x8,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK0x4,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK0x20000
102}, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE20x1859,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK0x8,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK0x4,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK0x20000
107}, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE30x185a,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK0x8,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK0x4,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK0x20000
112}, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE40x185b,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK0x8,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK0x4,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK0x20000
117}, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE50x185c,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK0x8,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK0x4,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK0x20000
122} };
123
124static const u32 cz_golden_settings_a11[] =
125{
126 mmCRTC_DOUBLE_BUFFER_CONTROL0x1bb6, 0x00010101, 0x00010000,
127 mmFBC_MISC0x2a2, 0x1f311fff, 0x14300000,
128};
129
130static const u32 cz_mgcg_cgcg_init[] =
131{
132 mmXDMA_CLOCK_GATING_CNTL0x3e4, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL0x3e6, 0x00000101, 0x00000000,
134};
135
136static const u32 stoney_golden_settings_a11[] =
137{
138 mmCRTC_DOUBLE_BUFFER_CONTROL0x1bb6, 0x00010101, 0x00010000,
139 mmFBC_MISC0x2a2, 0x1f311fff, 0x14302000,
140};
141
142static const u32 polaris11_golden_settings_a11[] =
143{
144 mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000,
145 mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070,
146 mmFBC_DEBUG10x287, 0xffffffff, 0x00000008,
147 mmFBC_MISC0x2a2, 0x9f313fff, 0x14302008,
148 mmHDMI_CONTROL0x4a09, 0x313f031f, 0x00000011,
149};
150
151static const u32 polaris10_golden_settings_a11[] =
152{
153 mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000,
154 mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070,
155 mmFBC_MISC0x2a2, 0x9f313fff, 0x14302008,
156 mmHDMI_CONTROL0x4a09, 0x313f031f, 0x00000011,
157};
158
159static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
160{
161 switch (adev->asic_type) {
162 case CHIP_CARRIZO:
163 amdgpu_device_program_register_sequence(adev,
164 cz_mgcg_cgcg_init,
165 ARRAY_SIZE(cz_mgcg_cgcg_init)(sizeof((cz_mgcg_cgcg_init)) / sizeof((cz_mgcg_cgcg_init)[0])
)
);
166 amdgpu_device_program_register_sequence(adev,
167 cz_golden_settings_a11,
168 ARRAY_SIZE(cz_golden_settings_a11)(sizeof((cz_golden_settings_a11)) / sizeof((cz_golden_settings_a11
)[0]))
);
169 break;
170 case CHIP_STONEY:
171 amdgpu_device_program_register_sequence(adev,
172 stoney_golden_settings_a11,
173 ARRAY_SIZE(stoney_golden_settings_a11)(sizeof((stoney_golden_settings_a11)) / sizeof((stoney_golden_settings_a11
)[0]))
);
174 break;
175 case CHIP_POLARIS11:
176 case CHIP_POLARIS12:
177 amdgpu_device_program_register_sequence(adev,
178 polaris11_golden_settings_a11,
179 ARRAY_SIZE(polaris11_golden_settings_a11)(sizeof((polaris11_golden_settings_a11)) / sizeof((polaris11_golden_settings_a11
)[0]))
);
180 break;
181 case CHIP_POLARIS10:
182 case CHIP_VEGAM:
183 amdgpu_device_program_register_sequence(adev,
184 polaris10_golden_settings_a11,
185 ARRAY_SIZE(polaris10_golden_settings_a11)(sizeof((polaris10_golden_settings_a11)) / sizeof((polaris10_golden_settings_a11
)[0]))
);
186 break;
187 default:
188 break;
189 }
190}
191
192static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
193 u32 block_offset, u32 reg)
194{
195 unsigned long flags;
196 u32 r;
197
198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock)
; } while (0)
;
199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0);
200 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset)amdgpu_device_rreg(adev, (0x17a9 + block_offset), 0);
201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock
); } while (0)
;
202
203 return r;
204}
205
206static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
207 u32 block_offset, u32 reg, u32 v)
208{
209 unsigned long flags;
210
211 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock)
; } while (0)
;
212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0);
213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v)amdgpu_device_wreg(adev, (0x17a9 + block_offset), (v), 0);
214 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock
); } while (0)
;
215}
216
217static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
218{
219 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
220 return 0;
221 else
222 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba6 + crtc_offsets[crtc]), 0);
223}
224
225static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
226{
227 unsigned i;
228
229 /* Enable pflip interrupts */
230 for (i = 0; i < adev->mode_info.num_crtc; i++)
231 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
232}
233
234static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
235{
236 unsigned i;
237
238 /* Disable pflip interrupts */
239 for (i = 0; i < adev->mode_info.num_crtc; i++)
240 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
241}
242
243/**
244 * dce_v11_0_page_flip - pageflip callback.
245 *
246 * @adev: amdgpu_device pointer
247 * @crtc_id: crtc to cleanup pageflip on
248 * @crtc_base: new address of the crtc (GPU MC address)
249 * @async: asynchronous flip
250 *
251 * Triggers the actual pageflip by updating the primary
252 * surface base address.
253 */
254static void dce_v11_0_page_flip(struct amdgpu_device *adev,
255 int crtc_id, u64 crtc_base, bool_Bool async)
256{
257 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
258 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
259 u32 tmp;
260
261 /* flip immediate for async, default is vsync */
262 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), 0)
;
263 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x10) | (0x10 & ((async ? 1 : 0) << 0x4
)))
264 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0)(((tmp) & ~0x10) | (0x10 & ((async ? 1 : 0) << 0x4
)))
;
265 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
266 /* update pitch */
267 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb->pitches[0] / fb->format->cpp[0]), 0)
268 fb->pitches[0] / fb->format->cpp[0])amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb->pitches[0] / fb->format->cpp[0]), 0)
;
269 /* update the scanout addresses */
270 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((crtc_base) >> 16) >> 16))), 0)
271 upper_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((crtc_base) >> 16) >> 16))), 0)
;
272 /* writing to the low address triggers the update */
273 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), (((u32)(crtc_base))), 0)
274 lower_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), (((u32)(crtc_base))), 0)
;
275 /* post the write */
276 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), 0)
;
277}
278
279static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
280 u32 *vbl, u32 *position)
281{
282 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
283 return -EINVAL22;
284
285 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1b8d + crtc_offsets[crtc]), 0);
286 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba4 + crtc_offsets[crtc]), 0);
287
288 return 0;
289}
290
291/**
292 * dce_v11_0_hpd_sense - hpd sense callback.
293 *
294 * @adev: amdgpu_device pointer
295 * @hpd: hpd (hotplug detect) pin
296 *
297 * Checks if a digital monitor is connected (evergreen+).
298 * Returns true if connected, false if not connected.
299 */
300static bool_Bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
301 enum amdgpu_hpd_id hpd)
302{
303 bool_Bool connected = false0;
304
305 if (hpd >= adev->mode_info.num_hpd)
306 return connected;
307
308 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1898 + hpd_offsets[hpd]), 0) &
309 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK0x2)
310 connected = true1;
311
312 return connected;
313}
314
315/**
316 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
317 *
318 * @adev: amdgpu_device pointer
319 * @hpd: hpd (hotplug detect) pin
320 *
321 * Set the polarity of the hpd pin (evergreen+).
322 */
323static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
324 enum amdgpu_hpd_id hpd)
325{
326 u32 tmp;
327 bool_Bool connected = dce_v11_0_hpd_sense(adev, hpd);
328
329 if (hpd >= adev->mode_info.num_hpd)
330 return;
331
332 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
333 if (connected)
334 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
335 else
336 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
337 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
)
;
338}
339
340/**
341 * dce_v11_0_hpd_init - hpd setup callback.
342 *
343 * @adev: amdgpu_device pointer
344 *
345 * Setup the hpd pins used by the card (evergreen+).
346 * Enable the pin, set the polarity, and enable the hpd interrupts.
347 */
348static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
349{
350 struct drm_device *dev = adev_to_drm(adev);
351 struct drm_connector *connector;
352 struct drm_connector_list_iter iter;
353 u32 tmp;
354
355 drm_connector_list_iter_begin(dev, &iter);
356 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
357 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
358
359 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
360 continue;
361
362 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14 ||
363 connector->connector_type == DRM_MODE_CONNECTOR_LVDS7) {
364 /* don't try to enable hpd on eDP or LVDS avoid breaking the
365 * aux dp channel on imac and help (but not completely fix)
366 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
367 * also avoid interrupt storms during dpms.
368 */
369 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0)
;
370 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10))
)
;
371 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0)
;
372 continue;
373 }
374
375 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0)
;
376 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1)(((tmp) & ~0x10000000) | (0x10000000 & ((1) << 0x1c
)))
;
377 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0)
;
378
379 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189c + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0)
;
380 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff) | (0xff & ((50) << 0x0)))
381 DC_HPD_CONNECT_INT_DELAY,(((tmp) & ~0xff) | (0xff & ((50) << 0x0)))
382 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff) | (0xff & ((50) << 0x0)));
383 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)))
384 DC_HPD_DISCONNECT_INT_DELAY,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)))
385 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)))
;
386 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189c + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0)
;
387
388 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
389 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
390 }
391 drm_connector_list_iter_end(&iter);
392}
393
394/**
395 * dce_v11_0_hpd_fini - hpd tear down callback.
396 *
397 * @adev: amdgpu_device pointer
398 *
399 * Tear down the hpd pins used by the card (evergreen+).
400 * Disable the hpd interrupts.
401 */
402static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
403{
404 struct drm_device *dev = adev_to_drm(adev);
405 struct drm_connector *connector;
406 struct drm_connector_list_iter iter;
407 u32 tmp;
408
409 drm_connector_list_iter_begin(dev, &iter);
410 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
411 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
412
413 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
414 continue;
415
416 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0)
;
417 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c
)))
;
418 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0)
;
419
420 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
421 }
422 drm_connector_list_iter_end(&iter);
423}
424
425static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
426{
427 return mmDC_GPIO_HPD_A0x488d;
428}
429
430static bool_Bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
431{
432 u32 crtc_hung = 0;
433 u32 crtc_status[6];
434 u32 i, j, tmp;
435
436 for (i = 0; i < adev->mode_info.num_crtc; i++) {
437 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0);
438 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)(((tmp) & 0x1) >> 0x0)) {
439 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0);
440 crtc_hung |= (1 << i);
441 }
442 }
443
444 for (j = 0; j < 10; j++) {
445 for (i = 0; i < adev->mode_info.num_crtc; i++) {
446 if (crtc_hung & (1 << i)) {
447 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0);
448 if (tmp != crtc_status[i])
449 crtc_hung &= ~(1 << i);
450 }
451 }
452 if (crtc_hung == 0)
453 return false0;
454 udelay(100);
455 }
456
457 return true1;
458}
459
460static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
461 bool_Bool render)
462{
463 u32 tmp;
464
465 /* Lockout access through VGA aperture*/
466 tmp = RREG32(mmVGA_HDP_CONTROL)amdgpu_device_rreg(adev, (0xca), 0);
467 if (render)
468 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0)(((tmp) & ~0x10) | (0x10 & ((0) << 0x4)));
469 else
470 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
471 WREG32(mmVGA_HDP_CONTROL, tmp)amdgpu_device_wreg(adev, (0xca), (tmp), 0);
472
473 /* disable VGA render */
474 tmp = RREG32(mmVGA_RENDER_CONTROL)amdgpu_device_rreg(adev, (0xc0), 0);
475 if (render)
476 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1)(((tmp) & ~0x30000) | (0x30000 & ((1) << 0x10))
)
;
477 else
478 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0)(((tmp) & ~0x30000) | (0x30000 & ((0) << 0x10))
)
;
479 WREG32(mmVGA_RENDER_CONTROL, tmp)amdgpu_device_wreg(adev, (0xc0), (tmp), 0);
480}
481
482static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
483{
484 int num_crtc = 0;
485
486 switch (adev->asic_type) {
487 case CHIP_CARRIZO:
488 num_crtc = 3;
489 break;
490 case CHIP_STONEY:
491 num_crtc = 2;
492 break;
493 case CHIP_POLARIS10:
494 case CHIP_VEGAM:
495 num_crtc = 6;
496 break;
497 case CHIP_POLARIS11:
498 case CHIP_POLARIS12:
499 num_crtc = 5;
500 break;
501 default:
502 num_crtc = 0;
503 }
504 return num_crtc;
505}
506
507void dce_v11_0_disable_dce(struct amdgpu_device *adev)
508{
509 /*Disable VGA render and enabled crtc, if has DCE engine*/
510 if (amdgpu_atombios_has_dce_engine_info(adev)) {
511 u32 tmp;
512 int crtc_enabled, i;
513
514 dce_v11_0_set_vga_render_state(adev, false0);
515
516 /*Disable crtc*/
517 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) &
0x1) >> 0x0)
519 CRTC_CONTROL, CRTC_MASTER_EN)(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) &
0x1) >> 0x0)
;
520 if (crtc_enabled) {
521 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (1), 0);
522 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0);
523 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
524 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp)amdgpu_device_wreg(adev, (0x1b9c + crtc_offsets[i]), (tmp), 0
)
;
525 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (0), 0);
526 }
527 }
528 }
529}
530
531static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
532{
533 struct drm_device *dev = encoder->dev;
534 struct amdgpu_device *adev = drm_to_adev(dev);
535 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
536 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );})
;
537 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
538 int bpc = 0;
539 u32 tmp = 0;
540 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
541
542 if (connector) {
543 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
544 bpc = amdgpu_connector_get_monitor_bpc(connector);
545 dither = amdgpu_connector->dither;
546 }
547
548 /* LVDS/eDP FMT is set up by atom */
549 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))
550 return;
551
552 /* not needed for analog */
553 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15) ||
554 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16))
555 return;
556
557 if (bpc == 0)
558 return;
559
560 switch (bpc) {
561 case 6:
562 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
563 /* XXX sort out optimal dither settings */
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0)(((tmp) & ~0x1800) | (0x1800 & ((0) << 0xb)));
568 } else {
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4)));
571 }
572 break;
573 case 8:
574 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
575 /* XXX sort out optimal dither settings */
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe)));
579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1)(((tmp) & ~0x1800) | (0x1800 & ((1) << 0xb)));
581 } else {
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4)));
584 }
585 break;
586 case 10:
587 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
588 /* XXX sort out optimal dither settings */
589 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
590 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
591 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe)));
592 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
593 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2)(((tmp) & ~0x1800) | (0x1800 & ((2) << 0xb)));
594 } else {
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2)(((tmp) & ~0x30) | (0x30 & ((2) << 0x4)));
597 }
598 break;
599 default:
600 /* not needed */
601 break;
602 }
603
604 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1bf2 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
605}
606
607
608/* display watermark setup */
609/**
610 * dce_v11_0_line_buffer_adjust - Set up the line buffer
611 *
612 * @adev: amdgpu_device pointer
613 * @amdgpu_crtc: the selected display controller
614 * @mode: the current display mode on the selected display
615 * controller
616 *
617 * Setup up the line buffer allocation for
618 * the selected display controller (CIK).
619 * Returns the line buffer size in pixels.
620 */
621static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
622 struct amdgpu_crtc *amdgpu_crtc,
623 struct drm_display_mode *mode)
624{
625 u32 tmp, buffer_alloc, i, mem_cfg;
626 u32 pipe_offset = amdgpu_crtc->crtc_id;
627 /*
628 * Line Buffer Setup
629 * There are 6 line buffers, one for each display controllers.
630 * There are 3 partitions per LB. Select the number of partitions
631 * to enable based on the display width. For display widths larger
632 * than 4096, you need use to use 2 display controllers and combine
633 * them using the stereo blender.
634 */
635 if (amdgpu_crtc->base.enabled && mode) {
636 if (mode->crtc_hdisplay < 1920) {
637 mem_cfg = 1;
638 buffer_alloc = 2;
639 } else if (mode->crtc_hdisplay < 2560) {
640 mem_cfg = 2;
641 buffer_alloc = 2;
642 } else if (mode->crtc_hdisplay < 4096) {
643 mem_cfg = 0;
644 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
645 } else {
646 DRM_DEBUG_KMS("Mode too big for LB!\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Mode too big for LB!\n");
647 mem_cfg = 0;
648 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
649 }
650 } else {
651 mem_cfg = 1;
652 buffer_alloc = 0;
653 }
654
655 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset
), 0)
;
656 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg)(((tmp) & ~0x300000) | (0x300000 & ((mem_cfg) <<
0x14)))
;
657 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
658
659 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0);
660 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc)(((tmp) & ~0x7) | (0x7 & ((buffer_alloc) << 0x0
)))
;
661 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp)amdgpu_device_wreg(adev, (0x321 + pipe_offset), (tmp), 0);
662
663 for (i = 0; i < adev->usec_timeout; i++) {
664 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0);
665 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)(((tmp) & 0x10) >> 0x4))
666 break;
667 udelay(1);
668 }
669
670 if (amdgpu_crtc->base.enabled && mode) {
671 switch (mem_cfg) {
672 case 0:
673 default:
674 return 4096 * 2;
675 case 1:
676 return 1920 * 2;
677 case 2:
678 return 2560 * 2;
679 }
680 }
681
682 /* controller not enabled, so no lb used */
683 return 0;
684}
685
686/**
687 * cik_get_number_of_dram_channels - get the number of dram channels
688 *
689 * @adev: amdgpu_device pointer
690 *
691 * Look up the number of video ram channels (CIK).
692 * Used for display watermark bandwidth calculations
693 * Returns the number of dram channels
694 */
695static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
696{
697 u32 tmp = RREG32(mmMC_SHARED_CHMAP)amdgpu_device_rreg(adev, (0x801), 0);
698
699 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)(((tmp) & 0xf000) >> 0xc)) {
700 case 0:
701 default:
702 return 1;
703 case 1:
704 return 2;
705 case 2:
706 return 4;
707 case 3:
708 return 8;
709 case 4:
710 return 3;
711 case 5:
712 return 6;
713 case 6:
714 return 10;
715 case 7:
716 return 12;
717 case 8:
718 return 16;
719 }
720}
721
722struct dce10_wm_params {
723 u32 dram_channels; /* number of dram channels */
724 u32 yclk; /* bandwidth per dram data pin in kHz */
725 u32 sclk; /* engine clock in kHz */
726 u32 disp_clk; /* display clock in kHz */
727 u32 src_width; /* viewport width */
728 u32 active_time; /* active display time in ns */
729 u32 blank_time; /* blank time in ns */
730 bool_Bool interlaced; /* mode is interlaced */
731 fixed20_12 vsc; /* vertical scale ratio */
732 u32 num_heads; /* number of active crtcs */
733 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
734 u32 lb_size; /* line buffer allocated to pipe */
735 u32 vtaps; /* vertical scaler taps */
736};
737
738/**
739 * dce_v11_0_dram_bandwidth - get the dram bandwidth
740 *
741 * @wm: watermark calculation data
742 *
743 * Calculate the raw dram bandwidth (CIK).
744 * Used for display watermark bandwidth calculations
745 * Returns the dram bandwidth in MBytes/s
746 */
747static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
748{
749 /* Calculate raw DRAM Bandwidth */
750 fixed20_12 dram_efficiency; /* 0.7 */
751 fixed20_12 yclk, dram_channels, bandwidth;
752 fixed20_12 a;
753
754 a.full = dfixed_const(1000)(u32)(((1000) << 12));
755 yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12));
756 yclk.full = dfixed_div(yclk, a);
757 dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12));
758 a.full = dfixed_const(10)(u32)(((10) << 12));
759 dram_efficiency.full = dfixed_const(7)(u32)(((7) << 12));
760 dram_efficiency.full = dfixed_div(dram_efficiency, a);
761 bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >>
12)
;
762 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency)((u64)((u64)(bandwidth).full * (dram_efficiency).full + 2048)
>> 12)
;
763
764 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
765}
766
767/**
768 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
769 *
770 * @wm: watermark calculation data
771 *
772 * Calculate the dram bandwidth used for display (CIK).
773 * Used for display watermark bandwidth calculations
774 * Returns the dram bandwidth for display in MBytes/s
775 */
776static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
777{
778 /* Calculate DRAM Bandwidth and the part allocated to display. */
779 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
780 fixed20_12 yclk, dram_channels, bandwidth;
781 fixed20_12 a;
782
783 a.full = dfixed_const(1000)(u32)(((1000) << 12));
784 yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12));
785 yclk.full = dfixed_div(yclk, a);
786 dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12));
787 a.full = dfixed_const(10)(u32)(((10) << 12));
788 disp_dram_allocation.full = dfixed_const(3)(u32)(((3) << 12)); /* XXX worse case value 0.3 */
789 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
790 bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >>
12)
;
791 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation)((u64)((u64)(bandwidth).full * (disp_dram_allocation).full + 2048
) >> 12)
;
792
793 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
794}
795
796/**
797 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
798 *
799 * @wm: watermark calculation data
800 *
801 * Calculate the data return bandwidth used for display (CIK).
802 * Used for display watermark bandwidth calculations
803 * Returns the data return bandwidth in MBytes/s
804 */
805static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
806{
807 /* Calculate the display Data return Bandwidth */
808 fixed20_12 return_efficiency; /* 0.8 */
809 fixed20_12 sclk, bandwidth;
810 fixed20_12 a;
811
812 a.full = dfixed_const(1000)(u32)(((1000) << 12));
813 sclk.full = dfixed_const(wm->sclk)(u32)(((wm->sclk) << 12));
814 sclk.full = dfixed_div(sclk, a);
815 a.full = dfixed_const(10)(u32)(((10) << 12));
816 return_efficiency.full = dfixed_const(8)(u32)(((8) << 12));
817 return_efficiency.full = dfixed_div(return_efficiency, a);
818 a.full = dfixed_const(32)(u32)(((32) << 12));
819 bandwidth.full = dfixed_mul(a, sclk)((u64)((u64)(a).full * (sclk).full + 2048) >> 12);
820 bandwidth.full = dfixed_mul(bandwidth, return_efficiency)((u64)((u64)(bandwidth).full * (return_efficiency).full + 2048
) >> 12)
;
821
822 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
823}
824
825/**
826 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
827 *
828 * @wm: watermark calculation data
829 *
830 * Calculate the dmif bandwidth used for display (CIK).
831 * Used for display watermark bandwidth calculations
832 * Returns the dmif bandwidth in MBytes/s
833 */
834static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
835{
836 /* Calculate the DMIF Request Bandwidth */
837 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
838 fixed20_12 disp_clk, bandwidth;
839 fixed20_12 a, b;
840
841 a.full = dfixed_const(1000)(u32)(((1000) << 12));
842 disp_clk.full = dfixed_const(wm->disp_clk)(u32)(((wm->disp_clk) << 12));
843 disp_clk.full = dfixed_div(disp_clk, a);
844 a.full = dfixed_const(32)(u32)(((32) << 12));
845 b.full = dfixed_mul(a, disp_clk)((u64)((u64)(a).full * (disp_clk).full + 2048) >> 12);
846
847 a.full = dfixed_const(10)(u32)(((10) << 12));
848 disp_clk_request_efficiency.full = dfixed_const(8)(u32)(((8) << 12));
849 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
850
851 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency)((u64)((u64)(b).full * (disp_clk_request_efficiency).full + 2048
) >> 12)
;
852
853 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
854}
855
856/**
857 * dce_v11_0_available_bandwidth - get the min available bandwidth
858 *
859 * @wm: watermark calculation data
860 *
861 * Calculate the min available bandwidth used for display (CIK).
862 * Used for display watermark bandwidth calculations
863 * Returns the min available bandwidth in MBytes/s
864 */
865static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
866{
867 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
868 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
869 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
870 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
871
872 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth))(((dram_bandwidth)<((((data_return_bandwidth)<(dmif_req_bandwidth
))?(data_return_bandwidth):(dmif_req_bandwidth))))?(dram_bandwidth
):((((data_return_bandwidth)<(dmif_req_bandwidth))?(data_return_bandwidth
):(dmif_req_bandwidth))))
;
873}
874
875/**
876 * dce_v11_0_average_bandwidth - get the average available bandwidth
877 *
878 * @wm: watermark calculation data
879 *
880 * Calculate the average available bandwidth used for display (CIK).
881 * Used for display watermark bandwidth calculations
882 * Returns the average available bandwidth in MBytes/s
883 */
884static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
885{
886 /* Calculate the display mode Average Bandwidth
887 * DisplayMode should contain the source and destination dimensions,
888 * timing, etc.
889 */
890 fixed20_12 bpp;
891 fixed20_12 line_time;
892 fixed20_12 src_width;
893 fixed20_12 bandwidth;
894 fixed20_12 a;
895
896 a.full = dfixed_const(1000)(u32)(((1000) << 12));
897 line_time.full = dfixed_const(wm->active_time + wm->blank_time)(u32)(((wm->active_time + wm->blank_time) << 12));
898 line_time.full = dfixed_div(line_time, a);
899 bpp.full = dfixed_const(wm->bytes_per_pixel)(u32)(((wm->bytes_per_pixel) << 12));
900 src_width.full = dfixed_const(wm->src_width)(u32)(((wm->src_width) << 12));
901 bandwidth.full = dfixed_mul(src_width, bpp)((u64)((u64)(src_width).full * (bpp).full + 2048) >> 12
)
;
902 bandwidth.full = dfixed_mul(bandwidth, wm->vsc)((u64)((u64)(bandwidth).full * (wm->vsc).full + 2048) >>
12)
;
903 bandwidth.full = dfixed_div(bandwidth, line_time);
904
905 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
906}
907
908/**
909 * dce_v11_0_latency_watermark - get the latency watermark
910 *
911 * @wm: watermark calculation data
912 *
913 * Calculate the latency watermark (CIK).
914 * Used for display watermark bandwidth calculations
915 * Returns the latency watermark in ns
916 */
917static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
918{
919 /* First calculate the latency in ns */
920 u32 mc_latency = 2000; /* 2000 ns. */
921 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
922 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
923 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
924 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
925 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
926 (wm->num_heads * cursor_line_pair_return_time);
927 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
928 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
929 u32 tmp, dmif_size = 12288;
930 fixed20_12 a, b, c;
931
932 if (wm->num_heads == 0)
933 return 0;
934
935 a.full = dfixed_const(2)(u32)(((2) << 12));
936 b.full = dfixed_const(1)(u32)(((1) << 12));
937 if ((wm->vsc.full > a.full) ||
938 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
939 (wm->vtaps >= 5) ||
940 ((wm->vsc.full >= a.full) && wm->interlaced))
941 max_src_lines_per_dst_line = 4;
942 else
943 max_src_lines_per_dst_line = 2;
944
945 a.full = dfixed_const(available_bandwidth)(u32)(((available_bandwidth) << 12));
946 b.full = dfixed_const(wm->num_heads)(u32)(((wm->num_heads) << 12));
947 a.full = dfixed_div(a, b);
948 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
949 tmp = min(dfixed_trunc(a), tmp)(((((a).full >> 12))<(tmp))?(((a).full >> 12))
:(tmp))
;
950
951 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)(((tmp)<(wm->disp_clk * wm->bytes_per_pixel / 1000))
?(tmp):(wm->disp_clk * wm->bytes_per_pixel / 1000))
;
952
953 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel)(u32)(((max_src_lines_per_dst_line * wm->src_width * wm->
bytes_per_pixel) << 12))
;
954 b.full = dfixed_const(1000)(u32)(((1000) << 12));
955 c.full = dfixed_const(lb_fill_bw)(u32)(((lb_fill_bw) << 12));
956 b.full = dfixed_div(c, b);
957 a.full = dfixed_div(a, b);
958 line_fill_time = dfixed_trunc(a)((a).full >> 12);
959
960 if (line_fill_time < wm->active_time)
961 return latency;
962 else
963 return latency + (line_fill_time - wm->active_time);
964
965}
966
967/**
968 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
969 * average and available dram bandwidth
970 *
971 * @wm: watermark calculation data
972 *
973 * Check if the display average bandwidth fits in the display
974 * dram bandwidth (CIK).
975 * Used for display watermark bandwidth calculations
976 * Returns true if the display fits, false if not.
977 */
978static bool_Bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
979{
980 if (dce_v11_0_average_bandwidth(wm) <=
981 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
982 return true1;
983 else
984 return false0;
985}
986
987/**
988 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
989 * average and available bandwidth
990 *
991 * @wm: watermark calculation data
992 *
993 * Check if the display average bandwidth fits in the display
994 * available bandwidth (CIK).
995 * Used for display watermark bandwidth calculations
996 * Returns true if the display fits, false if not.
997 */
998static bool_Bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
999{
1000 if (dce_v11_0_average_bandwidth(wm) <=
1001 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1002 return true1;
1003 else
1004 return false0;
1005}
1006
1007/**
1008 * dce_v11_0_check_latency_hiding - check latency hiding
1009 *
1010 * @wm: watermark calculation data
1011 *
1012 * Check latency hiding (CIK).
1013 * Used for display watermark bandwidth calculations
1014 * Returns true if the display fits, false if not.
1015 */
1016static bool_Bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1017{
1018 u32 lb_partitions = wm->lb_size / wm->src_width;
1019 u32 line_time = wm->active_time + wm->blank_time;
1020 u32 latency_tolerant_lines;
1021 u32 latency_hiding;
1022 fixed20_12 a;
1023
1024 a.full = dfixed_const(1)(u32)(((1) << 12));
1025 if (wm->vsc.full > a.full)
1026 latency_tolerant_lines = 1;
1027 else {
1028 if (lb_partitions <= (wm->vtaps + 1))
1029 latency_tolerant_lines = 1;
1030 else
1031 latency_tolerant_lines = 2;
1032 }
1033
1034 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1035
1036 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1037 return true1;
1038 else
1039 return false0;
1040}
1041
1042/**
1043 * dce_v11_0_program_watermarks - program display watermarks
1044 *
1045 * @adev: amdgpu_device pointer
1046 * @amdgpu_crtc: the selected display controller
1047 * @lb_size: line buffer size
1048 * @num_heads: number of display controllers in use
1049 *
1050 * Calculate and program the display watermarks for the
1051 * selected display controller (CIK).
1052 */
1053static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1054 struct amdgpu_crtc *amdgpu_crtc,
1055 u32 lb_size, u32 num_heads)
1056{
1057 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1058 struct dce10_wm_params wm_low, wm_high;
1059 u32 active_time;
1060 u32 line_time = 0;
1061 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1062 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1063
1064 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1065 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1066 (u32)mode->clock);
1067 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1068 (u32)mode->clock);
1069 line_time = min(line_time, (u32)65535)(((line_time)<((u32)65535))?(line_time):((u32)65535));
1070
1071 /* watermark for high clocks */
1072 if (adev->pm.dpm_enabled) {
1073 wm_high.yclk =
1074 amdgpu_dpm_get_mclk(adev, false0) * 10;
1075 wm_high.sclk =
1076 amdgpu_dpm_get_sclk(adev, false0) * 10;
1077 } else {
1078 wm_high.yclk = adev->pm.current_mclk * 10;
1079 wm_high.sclk = adev->pm.current_sclk * 10;
1080 }
1081
1082 wm_high.disp_clk = mode->clock;
1083 wm_high.src_width = mode->crtc_hdisplay;
1084 wm_high.active_time = active_time;
1085 wm_high.blank_time = line_time - wm_high.active_time;
1086 wm_high.interlaced = false0;
1087 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1088 wm_high.interlaced = true1;
1089 wm_high.vsc = amdgpu_crtc->vsc;
1090 wm_high.vtaps = 1;
1091 if (amdgpu_crtc->rmx_type != RMX_OFF)
1092 wm_high.vtaps = 2;
1093 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1094 wm_high.lb_size = lb_size;
1095 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1096 wm_high.num_heads = num_heads;
1097
1098 /* set for high clocks */
1099 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535)(((dce_v11_0_latency_watermark(&wm_high))<((u32)65535)
)?(dce_v11_0_latency_watermark(&wm_high)):((u32)65535))
;
1100
1101 /* possibly force display priority to high */
1102 /* should really do this at mode validation time... */
1103 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1104 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1105 !dce_v11_0_check_latency_hiding(&wm_high) ||
1106 (adev->mode_info.disp_priority == 2)) {
1107 DRM_DEBUG_KMS("force priority to high\n")___drm_dbg(((void *)0), DRM_UT_KMS, "force priority to high\n"
)
;
1108 }
1109
1110 /* watermark for low clocks */
1111 if (adev->pm.dpm_enabled) {
1112 wm_low.yclk =
1113 amdgpu_dpm_get_mclk(adev, true1) * 10;
1114 wm_low.sclk =
1115 amdgpu_dpm_get_sclk(adev, true1) * 10;
1116 } else {
1117 wm_low.yclk = adev->pm.current_mclk * 10;
1118 wm_low.sclk = adev->pm.current_sclk * 10;
1119 }
1120
1121 wm_low.disp_clk = mode->clock;
1122 wm_low.src_width = mode->crtc_hdisplay;
1123 wm_low.active_time = active_time;
1124 wm_low.blank_time = line_time - wm_low.active_time;
1125 wm_low.interlaced = false0;
1126 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1127 wm_low.interlaced = true1;
1128 wm_low.vsc = amdgpu_crtc->vsc;
1129 wm_low.vtaps = 1;
1130 if (amdgpu_crtc->rmx_type != RMX_OFF)
1131 wm_low.vtaps = 2;
1132 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1133 wm_low.lb_size = lb_size;
1134 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1135 wm_low.num_heads = num_heads;
1136
1137 /* set for low clocks */
1138 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535)(((dce_v11_0_latency_watermark(&wm_low))<((u32)65535))
?(dce_v11_0_latency_watermark(&wm_low)):((u32)65535))
;
1139
1140 /* possibly force display priority to high */
1141 /* should really do this at mode validation time... */
1142 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1143 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1144 !dce_v11_0_check_latency_hiding(&wm_low) ||
1145 (adev->mode_info.disp_priority == 2)) {
1146 DRM_DEBUG_KMS("force priority to high\n")___drm_dbg(((void *)0), DRM_UT_KMS, "force priority to high\n"
)
;
1147 }
1148 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay)(((lb_size) + ((mode->crtc_hdisplay) - 1)) / (mode->crtc_hdisplay
))
;
1149 }
1150
1151 /* select wm A */
1152 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), 0)
;
1153 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1)(((wm_mask) & ~0x300) | (0x300 & ((1) << 0x8)));
1154 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
1155 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), 0)
;
1156 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_a)
<< 0x0)))
;
1157 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) <<
0x10)))
;
1158 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
1159 /* select wm B */
1160 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2)(((wm_mask) & ~0x300) | (0x300 & ((2) << 0x8)));
1161 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
1162 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), 0)
;
1163 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_b)
<< 0x0)))
;
1164 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) <<
0x10)))
;
1165 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
1166 /* restore original selection */
1167 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (wm_mask), 0)
;
1168
1169 /* save values for DPM */
1170 amdgpu_crtc->line_time = line_time;
1171 amdgpu_crtc->wm_high = latency_watermark_a;
1172 amdgpu_crtc->wm_low = latency_watermark_b;
1173 /* Save number of lines the linebuffer leads before the scanout */
1174 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1175}
1176
1177/**
1178 * dce_v11_0_bandwidth_update - program display watermarks
1179 *
1180 * @adev: amdgpu_device pointer
1181 *
1182 * Calculate and program the display watermarks and line
1183 * buffer allocation (CIK).
1184 */
1185static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1186{
1187 struct drm_display_mode *mode = NULL((void *)0);
1188 u32 num_heads = 0, lb_size;
1189 int i;
1190
1191 amdgpu_display_update_priority(adev);
1192
1193 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1194 if (adev->mode_info.crtcs[i]->base.enabled)
1195 num_heads++;
1196 }
1197 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1198 mode = &adev->mode_info.crtcs[i]->base.mode;
1199 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1200 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1201 lb_size, num_heads);
1202 }
1203}
1204
1205static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1206{
1207 int i;
1208 u32 offset, tmp;
1209
1210 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1211 offset = adev->mode_info.audio.pin[i].offset;
1212 tmp = RREG32_AUDIO_ENDPT(offset,adev->audio_endpt_rreg(adev, (offset), (0x56))
1213 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)adev->audio_endpt_rreg(adev, (offset), (0x56));
1214 if (((tmp &
1215 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK0xc0000000) >>
1216 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT0x1e) == 1)
1217 adev->mode_info.audio.pin[i].connected = false0;
1218 else
1219 adev->mode_info.audio.pin[i].connected = true1;
1220 }
1221}
1222
1223static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1224{
1225 int i;
1226
1227 dce_v11_0_audio_get_connected_pins(adev);
1228
1229 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1230 if (adev->mode_info.audio.pin[i].connected)
1231 return &adev->mode_info.audio.pin[i];
1232 }
1233 DRM_ERROR("No connected audio pins found!\n")__drm_err("No connected audio pins found!\n");
1234 return NULL((void *)0);
1235}
1236
1237static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1238{
1239 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1240 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1241 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1242 u32 tmp;
1243
1244 if (!dig || !dig->afmt || !dig->afmt->pin)
1245 return;
1246
1247 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a45 + dig->afmt->offset), 0
)
;
1248 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id)(((tmp) & ~0x7) | (0x7 & ((dig->afmt->pin->id
) << 0x0)))
;
1249 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a45 + dig->afmt->offset), (
tmp), 0)
;
1250}
1251
1252static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1253 struct drm_display_mode *mode)
1254{
1255 struct drm_device *dev = encoder->dev;
1256 struct amdgpu_device *adev = drm_to_adev(dev);
1257 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1258 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1259 struct drm_connector *connector;
1260 struct drm_connector_list_iter iter;
1261 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1262 u32 tmp;
1263 int interlace = 0;
1264
1265 if (!dig || !dig->afmt || !dig->afmt->pin)
1266 return;
1267
1268 drm_connector_list_iter_begin(dev, &iter);
1269 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1270 if (connector->encoder == encoder) {
1271 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
1272 break;
1273 }
1274 }
1275 drm_connector_list_iter_end(&iter);
1276
1277 if (!amdgpu_connector) {
1278 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1279 return;
1280 }
1281
1282 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1283 interlace = 1;
1284 if (connector->latency_present[interlace]) {
1285 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((connector->video_latency
[interlace]) << 0x0)))
Value stored to 'tmp' is never read
1286 VIDEO_LIPSYNC, connector->video_latency[interlace])(((0) & ~0xff) | (0xff & ((connector->video_latency
[interlace]) << 0x0)))
;
1287 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency
[interlace]) << 0x8)))
1288 AUDIO_LIPSYNC, connector->audio_latency[interlace])(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency
[interlace]) << 0x8)))
;
1289 } else {
1290 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((0) << 0x0)))
1291 VIDEO_LIPSYNC, 0)(((0) & ~0xff) | (0xff & ((0) << 0x0)));
1292 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((0) << 0x8)))
1293 AUDIO_LIPSYNC, 0)(((0) & ~0xff00) | (0xff00 & ((0) << 0x8)));
1294 }
1295 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x37), (tmp))
1296 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x37), (tmp))
;
1297}
1298
1299static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1300{
1301 struct drm_device *dev = encoder->dev;
1302 struct amdgpu_device *adev = drm_to_adev(dev);
1303 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1304 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1305 struct drm_connector *connector;
1306 struct drm_connector_list_iter iter;
1307 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1308 u32 tmp;
1309 u8 *sadb = NULL((void *)0);
1310 int sad_count;
1311
1312 if (!dig || !dig->afmt || !dig->afmt->pin)
1313 return;
1314
1315 drm_connector_list_iter_begin(dev, &iter);
1316 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1317 if (connector->encoder == encoder) {
1318 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
1319 break;
1320 }
1321 }
1322 drm_connector_list_iter_end(&iter);
1323
1324 if (!amdgpu_connector) {
1325 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1326 return;
1327 }
1328
1329 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1330 if (sad_count < 0) {
1331 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count)__drm_err("Couldn't read Speaker Allocation Data Block: %d\n"
, sad_count)
;
1332 sad_count = 0;
1333 }
1334
1335 /* program the speaker allocation */
1336 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset
), (0x25))
1337 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset
), (0x25))
;
1338 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11))
)
1339 DP_CONNECTION, 0)(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11))
)
;
1340 /* set HDMI mode */
1341 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
)
1342 HDMI_CONNECTION, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
)
;
1343 if (sad_count)
1344 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0)))
1345 SPEAKER_ALLOCATION, sadb[0])(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0)));
1346 else
1347 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0)))
1348 SPEAKER_ALLOCATION, 5)(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0))); /* stereo */
1349 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x25), (tmp))
1350 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x25), (tmp))
;
1351
1352 kfree(sadb);
1353}
1354
1355static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1356{
1357 struct drm_device *dev = encoder->dev;
1358 struct amdgpu_device *adev = drm_to_adev(dev);
1359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1360 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1361 struct drm_connector *connector;
1362 struct drm_connector_list_iter iter;
1363 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1364 struct cea_sad *sads;
1365 int i, sad_count;
1366
1367 static const u16 eld_reg_to_type[][2] = {
1368 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR00x28, HDMI_AUDIO_CODING_TYPE_PCM },
1369 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10x29, HDMI_AUDIO_CODING_TYPE_AC3 },
1370 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR20x2a, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR30x2b, HDMI_AUDIO_CODING_TYPE_MP3 },
1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR40x2c, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR50x2d, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR60x2e, HDMI_AUDIO_CODING_TYPE_DTS },
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR70x2f, HDMI_AUDIO_CODING_TYPE_ATRAC },
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR90x31, HDMI_AUDIO_CODING_TYPE_EAC3 },
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR100x32, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR110x33, HDMI_AUDIO_CODING_TYPE_MLP },
1379 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR130x35, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1380 };
1381
1382 if (!dig || !dig->afmt || !dig->afmt->pin)
1383 return;
1384
1385 drm_connector_list_iter_begin(dev, &iter);
1386 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1387 if (connector->encoder == encoder) {
1388 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
1389 break;
1390 }
1391 }
1392 drm_connector_list_iter_end(&iter);
1393
1394 if (!amdgpu_connector) {
1395 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1396 return;
1397 }
1398
1399 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1400 if (sad_count < 0)
1401 DRM_ERROR("Couldn't read SADs: %d\n", sad_count)__drm_err("Couldn't read SADs: %d\n", sad_count);
1402 if (sad_count <= 0)
1403 return;
1404 BUG_ON(!sads)((!(!sads)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/dce_v11_0.c"
, 1404, "!(!sads)"))
;
1405
1406 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type)(sizeof((eld_reg_to_type)) / sizeof((eld_reg_to_type)[0])); i++) {
1407 u32 tmp = 0;
1408 u8 stereo_freqs = 0;
1409 int max_channels = -1;
1410 int j;
1411
1412 for (j = 0; j < sad_count; j++) {
1413 struct cea_sad *sad = &sads[j];
1414
1415 if (sad->format == eld_reg_to_type[i][1]) {
1416 if (sad->channels > max_channels) {
1417 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0x7) | (0x7 & ((sad->channels) <<
0x0)))
1418 MAX_CHANNELS, sad->channels)(((tmp) & ~0x7) | (0x7 & ((sad->channels) <<
0x0)))
;
1419 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) <<
0x10)))
1420 DESCRIPTOR_BYTE_2, sad->byte2)(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) <<
0x10)))
;
1421 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) <<
0x8)))
1422 SUPPORTED_FREQUENCIES, sad->freq)(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) <<
0x8)))
;
1423 max_channels = sad->channels;
1424 }
1425
1426 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1427 stereo_freqs |= sad->freq;
1428 else
1429 break;
1430 }
1431 }
1432
1433 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs
) << 0x18)))
1434 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs)(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs
) << 0x18)))
;
1435 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (eld_reg_to_type[i][0]), (tmp))
;
1436 }
1437
1438 kfree(sads);
1439}
1440
1441static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1442 struct amdgpu_audio_pin *pin,
1443 bool_Bool enable)
1444{
1445 if (!pin)
1446 return;
1447
1448 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable
? 0x80000000 : 0))
1449 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0)adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable
? 0x80000000 : 0))
;
1450}
1451
1452static const u32 pin_offsets[] =
1453{
1454 AUD0_REGISTER_OFFSET(0x17a8 - 0x17a8),
1455 AUD1_REGISTER_OFFSET(0x17ac - 0x17a8),
1456 AUD2_REGISTER_OFFSET(0x17b0 - 0x17a8),
1457 AUD3_REGISTER_OFFSET(0x17b4 - 0x17a8),
1458 AUD4_REGISTER_OFFSET(0x17b8 - 0x17a8),
1459 AUD5_REGISTER_OFFSET(0x17bc - 0x17a8),
1460 AUD6_REGISTER_OFFSET(0x17c0 - 0x17a8),
1461 AUD7_REGISTER_OFFSET(0x17c4 - 0x17a8),
1462};
1463
1464static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1465{
1466 int i;
1467
1468 if (!amdgpu_audio)
1469 return 0;
1470
1471 adev->mode_info.audio.enabled = true1;
1472
1473 switch (adev->asic_type) {
1474 case CHIP_CARRIZO:
1475 case CHIP_STONEY:
1476 adev->mode_info.audio.num_pins = 7;
1477 break;
1478 case CHIP_POLARIS10:
1479 case CHIP_VEGAM:
1480 adev->mode_info.audio.num_pins = 8;
1481 break;
1482 case CHIP_POLARIS11:
1483 case CHIP_POLARIS12:
1484 adev->mode_info.audio.num_pins = 6;
1485 break;
1486 default:
1487 return -EINVAL22;
1488 }
1489
1490 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1491 adev->mode_info.audio.pin[i].channels = -1;
1492 adev->mode_info.audio.pin[i].rate = -1;
1493 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1494 adev->mode_info.audio.pin[i].status_bits = 0;
1495 adev->mode_info.audio.pin[i].category_code = 0;
1496 adev->mode_info.audio.pin[i].connected = false0;
1497 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1498 adev->mode_info.audio.pin[i].id = i;
1499 /* disable audio. it will be set up later */
1500 /* XXX remove once we switch to ip funcs */
1501 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
1502 }
1503
1504 return 0;
1505}
1506
1507static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1508{
1509 int i;
1510
1511 if (!amdgpu_audio)
1512 return;
1513
1514 if (!adev->mode_info.audio.enabled)
1515 return;
1516
1517 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1518 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
1519
1520 adev->mode_info.audio.enabled = false0;
1521}
1522
1523/*
1524 * update the N and CTS parameters for a given pixel clock rate
1525 */
1526static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1527{
1528 struct drm_device *dev = encoder->dev;
1529 struct amdgpu_device *adev = drm_to_adev(dev);
1530 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1531 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1532 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 u32 tmp;
1534
1535 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2e + dig->afmt->offset), 0
)
;
1536 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_32khz
) << 0xc)))
;
1537 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2e + dig->afmt->offset), (
tmp), 0)
;
1538 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2f + dig->afmt->offset), 0
)
;
1539 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_32khz) <<
0x0)))
;
1540 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2f + dig->afmt->offset), (
tmp), 0)
;
1541
1542 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a30 + dig->afmt->offset), 0
)
;
1543 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_44_1khz
) << 0xc)))
;
1544 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a30 + dig->afmt->offset), (
tmp), 0)
;
1545 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a31 + dig->afmt->offset), 0
)
;
1546 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_44_1khz) <<
0x0)))
;
1547 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a31 + dig->afmt->offset), (
tmp), 0)
;
1548
1549 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a32 + dig->afmt->offset), 0
)
;
1550 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_48khz
) << 0xc)))
;
1551 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a32 + dig->afmt->offset), (
tmp), 0)
;
1552 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a33 + dig->afmt->offset), 0
)
;
1553 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_48khz) <<
0x0)))
;
1554 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a33 + dig->afmt->offset), (
tmp), 0)
;
1555
1556}
1557
1558/*
1559 * build a HDMI Video Info Frame
1560 */
1561static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1562 void *buffer, size_t size)
1563{
1564 struct drm_device *dev = encoder->dev;
1565 struct amdgpu_device *adev = drm_to_adev(dev);
1566 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1567 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568 uint8_t *frame = buffer + 3;
1569 uint8_t *header = buffer;
1570
1571 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), (
frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16
) | (frame[0x3] << 24)), 0)
1572 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24))amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), (
frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16
) | (frame[0x3] << 24)), 0)
;
1573 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), (
frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16
) | (frame[0x7] << 24)), 0)
1574 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24))amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), (
frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16
) | (frame[0x7] << 24)), 0)
;
1575 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), (
frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16
) | (frame[0xB] << 24)), 0)
1576 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24))amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), (
frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16
) | (frame[0xB] << 24)), 0)
;
1577 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), (
frame[0xC] | (frame[0xD] << 8) | (header[1] << 24
)), 0)
1578 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24))amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), (
frame[0xC] | (frame[0xD] << 8) | (header[1] << 24
)), 0)
;
1579}
1580
1581static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1582{
1583 struct drm_device *dev = encoder->dev;
1584 struct amdgpu_device *adev = drm_to_adev(dev);
1585 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1586 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1587 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );})
;
1588 u32 dto_phase = 24 * 1000;
1589 u32 dto_modulo = clock;
1590 u32 tmp;
1591
1592 if (!dig || !dig->afmt)
1593 return;
1594
1595 /* XXX two dtos; generally use dto0 for hdmi */
1596 /* Express [24MHz / target pixel clock] as an exact rational
1597 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1598 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1599 */
1600 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE)amdgpu_device_rreg(adev, (0x16b), 0);
1601 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) <<
0x0)))
1602 amdgpu_crtc->crtc_id)(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) <<
0x0)))
;
1603 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp)amdgpu_device_wreg(adev, (0x16b), (tmp), 0);
1604 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase)amdgpu_device_wreg(adev, (0x16c), (dto_phase), 0);
1605 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo)amdgpu_device_wreg(adev, (0x16d), (dto_modulo), 0);
1606}
1607
1608/*
1609 * update the info frames with the data from the current display mode
1610 */
1611static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1612 struct drm_display_mode *mode)
1613{
1614 struct drm_device *dev = encoder->dev;
1615 struct amdgpu_device *adev = drm_to_adev(dev);
1616 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1617 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1618 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1619 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE4 + HDMI_AVI_INFOFRAME_SIZE13];
1620 struct hdmi_avi_infoframe frame;
1621 ssize_t err;
1622 u32 tmp;
1623 int bpc = 8;
1624
1625 if (!dig || !dig->afmt)
1626 return;
1627
1628 /* Silent, r600_hdmi_enable will raise WARN for us */
1629 if (!dig->afmt->enabled)
1630 return;
1631
1632 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1633 if (encoder->crtc) {
1634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );})
;
1635 bpc = amdgpu_crtc->bpc;
1636 }
1637
1638 /* disable audio prior to setting up hw */
1639 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1640 dce_v11_0_audio_enable(adev, dig->afmt->pin, false0);
1641
1642 dce_v11_0_audio_set_dto(encoder, mode->clock);
1643
1644 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0
)
;
1645 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1646 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), (
tmp), 0)
; /* send null packets when required */
1647
1648 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000)amdgpu_device_wreg(adev, (0x4a3a + dig->afmt->offset), (
0x1000), 0)
;
1649
1650 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a09 + dig->afmt->offset), 0
)
;
1651 switch (bpc) {
1652 case 0:
1653 case 6:
1654 case 8:
1655 case 16:
1656 default:
1657 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0)(((tmp) & ~0x1000000) | (0x1000000 & ((0) << 0x18
)))
;
1658 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0)(((tmp) & ~0x30000000) | (0x30000000 & ((0) << 0x1c
)))
;
1659 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n"
, connector->name, bpc)
1660 connector->name, bpc)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n"
, connector->name, bpc)
;
1661 break;
1662 case 10:
1663 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18
)))
;
1664 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1)(((tmp) & ~0x30000000) | (0x30000000 & ((1) << 0x1c
)))
;
1665 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n"
, connector->name)
1666 connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n"
, connector->name)
;
1667 break;
1668 case 12:
1669 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18
)))
;
1670 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2)(((tmp) & ~0x30000000) | (0x30000000 & ((2) << 0x1c
)))
;
1671 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n"
, connector->name)
1672 connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n"
, connector->name)
;
1673 break;
1674 }
1675 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a09 + dig->afmt->offset), (
tmp), 0)
;
1676
1677 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0
)
;
1678 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); /* send null packets when required */
1679 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); /* send general control packets */
1680 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5))); /* send general control packets every frame */
1681 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), (
tmp), 0)
;
1682
1683 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0
)
;
1684 /* enable audio info frames (frames won't be set until audio is enabled) */
1685 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
1686 /* required for audio info values to be updated */
1687 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5)));
1688 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), (
tmp), 0)
;
1689
1690 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a44 + dig->afmt->offset), 0
)
;
1691 /* required for audio info values to be updated */
1692 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)(((tmp) & ~0x80) | (0x80 & ((1) << 0x7)));
1693 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a44 + dig->afmt->offset), (
tmp), 0)
;
1694
1695 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0
)
;
1696 /* anything other than 0 */
1697 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2)(((tmp) & ~0x3f00) | (0x3f00 & ((2) << 0x8)));
1698 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), (
tmp), 0)
;
1699
1700 WREG32(mmHDMI_GC + dig->afmt->offset, 0)amdgpu_device_wreg(adev, (0x4a13 + dig->afmt->offset), (
0), 0)
; /* unset HDMI_GC_AVMUTE */
1701
1702 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0b + dig->afmt->offset), 0
)
;
1703 /* set the default audio delay */
1704 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4)));
1705 /* should be suffient for all audio modes and small enough for all hblanks */
1706 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3)(((tmp) & ~0x1f0000) | (0x1f0000 & ((3) << 0x10
)))
;
1707 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0b + dig->afmt->offset), (
tmp), 0)
;
1708
1709 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0
)
;
1710 /* allow 60958 channel status fields to be updated */
1711 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)(((tmp) & ~0x4000000) | (0x4000000 & ((1) << 0x1a
)))
;
1712 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), (
tmp), 0)
;
1713
1714 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0c + dig->afmt->offset), 0
)
;
1715 if (bpc > 8)
1716 /* clear SW CTS value */
1717 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
1718 else
1719 /* select SW CTS value */
1720 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
1721 /* allow hw to sent ACR packets when required */
1722 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1)(((tmp) & ~0x1000) | (0x1000 & ((1) << 0xc)));
1723 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0c + dig->afmt->offset), (
tmp), 0)
;
1724
1725 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1726
1727 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a38 + dig->afmt->offset), 0
)
;
1728 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1)(((tmp) & ~0xf00000) | (0xf00000 & ((1) << 0x14
)))
;
1729 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a38 + dig->afmt->offset), (
tmp), 0)
;
1730
1731 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a39 + dig->afmt->offset), 0
)
;
1732 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2)(((tmp) & ~0xf00000) | (0xf00000 & ((2) << 0x14
)))
;
1733 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a39 + dig->afmt->offset), (
tmp), 0)
;
1734
1735 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a3f + dig->afmt->offset), 0
)
;
1736 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3)(((tmp) & ~0xf) | (0xf & ((3) << 0x0)));
1737 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4)(((tmp) & ~0xf0) | (0xf0 & ((4) << 0x4)));
1738 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5)(((tmp) & ~0xf00) | (0xf00 & ((5) << 0x8)));
1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6)(((tmp) & ~0xf000) | (0xf000 & ((6) << 0xc)));
1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7)(((tmp) & ~0xf0000) | (0xf0000 & ((7) << 0x10))
)
;
1741 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8)(((tmp) & ~0xf00000) | (0xf00000 & ((8) << 0x14
)))
;
1742 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a3f + dig->afmt->offset), (
tmp), 0)
;
1743
1744 dce_v11_0_audio_write_speaker_allocation(encoder);
1745
1746 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), (
(0xff << 0x8)), 0)
1747 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT))amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), (
(0xff << 0x8)), 0)
;
1748
1749 dce_v11_0_afmt_audio_select_pin(encoder);
1750 dce_v11_0_audio_write_sad_regs(encoder);
1751 dce_v11_0_audio_write_latency_fields(encoder, mode);
1752
1753 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1754 if (err < 0) {
1755 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err)__drm_err("failed to setup AVI infoframe: %zd\n", err);
1756 return;
1757 }
1758
1759 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1760 if (err < 0) {
1761 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err)__drm_err("failed to pack AVI infoframe: %zd\n", err);
1762 return;
1763 }
1764
1765 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1766
1767 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0
)
;
1768 /* enable AVI info frames */
1769 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1770 /* required for audio info values to be updated */
1771 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1)));
1772 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), (
tmp), 0)
;
1773
1774 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0
)
;
1775 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2)(((tmp) & ~0x3f) | (0x3f & ((2) << 0x0)));
1776 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), (
tmp), 0)
;
1777
1778 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0
)
;
1779 /* send audio packets */
1780 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1781 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), (
tmp), 0)
;
1782
1783 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF)amdgpu_device_wreg(adev, (0x4a3b + dig->afmt->offset), (
0x00FFFFFF), 0)
;
1784 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF)amdgpu_device_wreg(adev, (0x4a3c + dig->afmt->offset), (
0x007FFFFF), 0)
;
1785 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3d + dig->afmt->offset), (
0x00000001), 0)
;
1786 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3e + dig->afmt->offset), (
0x00000001), 0)
;
1787
1788 /* enable audio after to setting up hw */
1789 dce_v11_0_audio_enable(adev, dig->afmt->pin, true1);
1790}
1791
1792static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool_Bool enable)
1793{
1794 struct drm_device *dev = encoder->dev;
1795 struct amdgpu_device *adev = drm_to_adev(dev);
1796 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
1797 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1798
1799 if (!dig || !dig->afmt)
1800 return;
1801
1802 /* Silent, r600_hdmi_enable will raise WARN for us */
1803 if (enable && dig->afmt->enabled)
1804 return;
1805 if (!enable && !dig->afmt->enabled)
1806 return;
1807
1808 if (!enable && dig->afmt->pin) {
1809 dce_v11_0_audio_enable(adev, dig->afmt->pin, false0);
1810 dig->afmt->pin = NULL((void *)0);
1811 }
1812
1813 dig->afmt->enabled = enable;
1814
1815 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n"
, enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder
->encoder_id)
1816 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id)___drm_dbg(((void *)0), DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n"
, enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder
->encoder_id)
;
1817}
1818
1819static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1820{
1821 int i;
1822
1823 for (i = 0; i < adev->mode_info.num_dig; i++)
1824 adev->mode_info.afmt[i] = NULL((void *)0);
1825
1826 /* DCE11 has audio blocks tied to DIG encoders */
1827 for (i = 0; i < adev->mode_info.num_dig; i++) {
1828 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL(0x0001 | 0x0004));
1829 if (adev->mode_info.afmt[i]) {
1830 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1831 adev->mode_info.afmt[i]->id = i;
1832 } else {
1833 int j;
1834 for (j = 0; j < i; j++) {
1835 kfree(adev->mode_info.afmt[j]);
1836 adev->mode_info.afmt[j] = NULL((void *)0);
1837 }
1838 return -ENOMEM12;
1839 }
1840 }
1841 return 0;
1842}
1843
1844static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1845{
1846 int i;
1847
1848 for (i = 0; i < adev->mode_info.num_dig; i++) {
1849 kfree(adev->mode_info.afmt[i]);
1850 adev->mode_info.afmt[i] = NULL((void *)0);
1851 }
1852}
1853
1854static const u32 vga_control_regs[6] =
1855{
1856 mmD1VGA_CONTROL0xcc,
1857 mmD2VGA_CONTROL0xce,
1858 mmD3VGA_CONTROL0xf8,
1859 mmD4VGA_CONTROL0xf9,
1860 mmD5VGA_CONTROL0xfa,
1861 mmD6VGA_CONTROL0xfb,
1862};
1863
1864static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool_Bool enable)
1865{
1866 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
1867 struct drm_device *dev = crtc->dev;
1868 struct amdgpu_device *adev = drm_to_adev(dev);
1869 u32 vga_control;
1870
1871 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id])amdgpu_device_rreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), 0)
& ~1;
1872 if (enable)
1873 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), (vga_control | 1), 0)
;
1874 else
1875 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), (vga_control), 0)
;
1876}
1877
1878static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool_Bool enable)
1879{
1880 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
1881 struct drm_device *dev = crtc->dev;
1882 struct amdgpu_device *adev = drm_to_adev(dev);
1883
1884 if (enable)
1885 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset
), (1), 0)
;
1886 else
1887 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset
), (0), 0)
;
1888}
1889
1890static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1891 struct drm_framebuffer *fb,
1892 int x, int y, int atomic)
1893{
1894 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
1895 struct drm_device *dev = crtc->dev;
1896 struct amdgpu_device *adev = drm_to_adev(dev);
1897 struct drm_framebuffer *target_fb;
1898 struct drm_gem_object *obj;
1899 struct amdgpu_bo *abo;
1900 uint64_t fb_location, tiling_flags;
1901 uint32_t fb_format, fb_pitch_pixels;
1902 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE)(((0) & ~0x3) | (0x3 & ((ENDIAN_NONE) << 0x0)));
1903 u32 pipe_config;
1904 u32 tmp, viewport_w, viewport_h;
1905 int r;
1906 bool_Bool bypass_lut = false0;
1907
1908 /* no fb bound */
1909 if (!atomic && !crtc->primary->fb) {
1910 DRM_DEBUG_KMS("No FB bound\n")___drm_dbg(((void *)0), DRM_UT_KMS, "No FB bound\n");
1911 return 0;
1912 }
1913
1914 if (atomic)
1915 target_fb = fb;
1916 else
1917 target_fb = crtc->primary->fb;
1918
1919 /* If atomic, assume fb object is pinned & idle & fenced and
1920 * just update base pointers
1921 */
1922 obj = target_fb->obj[0];
1923 abo = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );})
;
1924 r = amdgpu_bo_reserve(abo, false0);
1925 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
1926 return r;
1927
1928 if (!atomic) {
1929 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM0x4);
1930 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
1931 amdgpu_bo_unreserve(abo);
1932 return -EINVAL22;
1933 }
1934 }
1935 fb_location = amdgpu_bo_gpu_offset(abo);
1936
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1938 amdgpu_bo_unreserve(abo);
1939
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)(((__u64)(tiling_flags) >> 4) & 0x1f);
1941
1942 switch (target_fb->format->format) {
1943 case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
:
1944 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0)(((0) & ~0x3) | (0x3 & ((0) << 0x0)));
1945 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
))
;
1946 break;
1947 case DRM_FORMAT_XRGB4444((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
1948 case DRM_FORMAT_ARGB4444((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2)(((fb_format) & ~0x700) | (0x700 & ((2) << 0x8)
))
;
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1953 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
;
1954#endif
1955 break;
1956 case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
1957 case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
))
;
1960#ifdef __BIG_ENDIAN
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1962 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
;
1963#endif
1964 break;
1965 case DRM_FORMAT_BGRX5551((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
1966 case DRM_FORMAT_BGRA5551((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5)(((fb_format) & ~0x700) | (0x700 & ((5) << 0x8)
))
;
1969#ifdef __BIG_ENDIAN
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1971 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
;
1972#endif
1973 break;
1974 case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
1975 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1976 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8)
))
;
1977#ifdef __BIG_ENDIAN
1978 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1979 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
;
1980#endif
1981 break;
1982 case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
1983 case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
1984 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
1985 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
))
;
1986#ifdef __BIG_ENDIAN
1987 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
1988 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
;
1989#endif
1990 break;
1991 case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
1992 case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
1993 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8)
))
;
1995#ifdef __BIG_ENDIAN
1996 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
1997 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
;
1998#endif
1999 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2000 bypass_lut = true1;
2001 break;
2002 case DRM_FORMAT_BGRX1010102((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
2003 case DRM_FORMAT_BGRA1010102((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
2004 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4)(((fb_format) & ~0x700) | (0x700 & ((4) << 0x8)
))
;
2006#ifdef __BIG_ENDIAN
2007 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
2008 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
;
2009#endif
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2011 bypass_lut = true1;
2012 break;
2013 case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
2014 case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
2015 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
2016 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
))
;
2017 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2)(((fb_swap) & ~0x30) | (0x30 & ((2) << 0x4)));
2018 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2)(((fb_swap) & ~0x300) | (0x300 & ((2) << 0x8)));
2019#ifdef __BIG_ENDIAN
2020 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
2021 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
;
2022#endif
2023 break;
2024 default:
2025 DRM_ERROR("Unsupported screen format %p4cc\n",__drm_err("Unsupported screen format %p4cc\n", &target_fb
->format->format)
2026 &target_fb->format->format)__drm_err("Unsupported screen format %p4cc\n", &target_fb
->format->format)
;
2027 return -EINVAL22;
2028 }
2029
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_2D_TILED_THIN1) {
2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2032
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)(((__u64)(tiling_flags) >> 15) & 0x3);
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT)(((__u64)(tiling_flags) >> 17) & 0x3);
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT)(((__u64)(tiling_flags) >> 19) & 0x3);
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)(((__u64)(tiling_flags) >> 9) & 0x7);
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)(((__u64)(tiling_flags) >> 21) & 0x3);
2038
2039 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks)(((fb_format) & ~0xc) | (0xc & ((num_banks) << 0x2
)))
;
2040 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1
) << 0x14)))
2041 ARRAY_2D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1
) << 0x14)))
;
2042 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) <<
0xd)))
2043 tile_split)(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) <<
0xd)))
;
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw)(((fb_format) & ~0xc0) | (0xc0 & ((bankw) << 0x6
)))
;
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh)(((fb_format) & ~0x1800) | (0x1800 & ((bankh) <<
0xb)))
;
2046 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) <<
0x12)))
2047 mtaspect)(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) <<
0x12)))
;
2048 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY
) << 0x1d)))
2049 ADDR_SURF_MICRO_TILING_DISPLAY)(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY
) << 0x1d)))
;
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_1D_TILED_THIN1) {
2051 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1
) << 0x14)))
2052 ARRAY_1D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1
) << 0x14)))
;
2053 }
2054
2055 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config
) << 0x18)))
2056 pipe_config)(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config
) << 0x18)))
;
2057
2058 dce_v11_0_vga_enable(crtc, false0);
2059
2060 /* Make sure surface address is updated at vertical blank rather than
2061 * horizontal blank
2062 */
2063 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), 0)
;
2064 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)))
2065 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2066 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2067
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
2069 upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
;
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
2071 upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
;
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), ((u32)fb_location & 0xffffff00), 0)
2073 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), ((u32)fb_location & 0xffffff00), 0)
;
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset
), ((u32) fb_location & 0xffffff00), 0)
2075 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset
), ((u32) fb_location & 0xffffff00), 0)
;
2076 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format)amdgpu_device_wreg(adev, (0x1a01 + amdgpu_crtc->crtc_offset
), (fb_format), 0)
;
2077 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap)amdgpu_device_wreg(adev, (0x1a03 + amdgpu_crtc->crtc_offset
), (fb_swap), 0)
;
2078
2079 /*
2080 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2081 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2082 * retain the full precision throughout the pipeline.
2083 */
2084 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset
), 0)
;
2085 if (bypass_lut)
2086 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
2087 else
2088 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2090
2091 if (bypass_lut)
2092 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Bypassing hardware LUT due to 10 bit fb scanout.\n"
)
;
2093
2094 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a09 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0a + amdgpu_crtc->crtc_offset
), (0), 0)
;
2096 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0b + amdgpu_crtc->crtc_offset
), (0), 0)
;
2097 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0c + amdgpu_crtc->crtc_offset
), (0), 0)
;
2098 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width)amdgpu_device_wreg(adev, (0x1a0d + amdgpu_crtc->crtc_offset
), (target_fb->width), 0)
;
2099 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height)amdgpu_device_wreg(adev, (0x1a0e + amdgpu_crtc->crtc_offset
), (target_fb->height), 0)
;
2100
2101 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2102 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels)amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb_pitch_pixels), 0)
;
2103
2104 dce_v11_0_grph_enable(crtc, true1);
2105
2106 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset
), (target_fb->height), 0)
2107 target_fb->height)amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset
), (target_fb->height), 0)
;
2108
2109 x &= ~3;
2110 y &= ~1;
2111 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0)
2112 (x << 16) | y)amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0)
;
2113 viewport_w = crtc->mode.hdisplay;
2114 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2115 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset
), ((viewport_w << 16) | viewport_h), 0)
2116 (viewport_w << 16) | viewport_h)amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset
), ((viewport_w << 16) | viewport_h), 0)
;
2117
2118 /* set pageflip to happen anywhere in vblank interval */
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1bbe + amdgpu_crtc->crtc_offset
), (0), 0)
;
2120
2121 if (!atomic && fb && fb != crtc->primary->fb) {
2122 abo = gem_to_amdgpu_bo(fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((fb->obj[0])); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );})
;
2123 r = amdgpu_bo_reserve(abo, true1);
2124 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
2125 return r;
2126 amdgpu_bo_unpin(abo);
2127 amdgpu_bo_unreserve(abo);
2128 }
2129
2130 /* Bytes per pixel may have changed */
2131 dce_v11_0_bandwidth_update(adev);
2132
2133 return 0;
2134}
2135
2136static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2137 struct drm_display_mode *mode)
2138{
2139 struct drm_device *dev = crtc->dev;
2140 struct amdgpu_device *adev = drm_to_adev(dev);
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2142 u32 tmp;
2143
2144 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset
), 0)
;
2145 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
2146 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1)(((tmp) & ~0x8) | (0x8 & ((1) << 0x3)));
2147 else
2148 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0)(((tmp) & ~0x8) | (0x8 & ((0) << 0x3)));
2149 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2150}
2151
2152static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2153{
2154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2155 struct drm_device *dev = crtc->dev;
2156 struct amdgpu_device *adev = drm_to_adev(dev);
2157 u16 *r, *g, *b;
2158 int i;
2159 u32 tmp;
2160
2161 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id)___drm_dbg(((void *)0), DRM_UT_KMS, "%d\n", amdgpu_crtc->crtc_id
)
;
2162
2163 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset
), 0)
;
2164 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2165 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2166
2167 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset
), 0)
;
2168 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
2169 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2170
2171 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset
), 0)
;
2172 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2173 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2174
2175 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a80 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2176
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a81 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a82 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a83 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2180
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a84 + amdgpu_crtc->crtc_offset
), (0xffff), 0)
;
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a85 + amdgpu_crtc->crtc_offset
), (0xffff), 0)
;
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a86 + amdgpu_crtc->crtc_offset
), (0xffff), 0)
;
2184
2185 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a78 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2186 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007)amdgpu_device_wreg(adev, (0x1a7e + amdgpu_crtc->crtc_offset
), (0x00000007), 0)
;
2187
2188 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a79 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2189 r = crtc->gamma_store;
2190 g = r + crtc->gamma_size;
2191 b = g + crtc->gamma_size;
2192 for (i = 0; i < 256; i++) {
2193 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2194 ((*r++ & 0xffc0) << 14) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2195 ((*g++ & 0xffc0) << 4) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2196 (*b++ >> 6))amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
;
2197 }
2198
2199 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset
), 0)
;
2200 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2201 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0)(((tmp) & ~0x3000) | (0x3000 & ((0) << 0xc)));
2202 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0)(((tmp) & ~0x300) | (0x300 & ((0) << 0x8)));
2203 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2204
2205 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset
), 0)
;
2206 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2207 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2208
2209 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset
), 0)
;
2210 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0)));
2211 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2212
2213 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset
), 0)
;
2214 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0)));
2215 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2216
2217 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2218 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a50 + amdgpu_crtc->crtc_offset
), (0), 0)
;
2219 /* XXX this only needs to be programmed once per crtc at startup,
2220 * not sure where the best place for it is
2221 */
2222 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1abc + amdgpu_crtc->crtc_offset
), 0)
;
2223 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1)));
2224 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1abc + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2225}
2226
2227static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2228{
2229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
2230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2231
2232 switch (amdgpu_encoder->encoder_id) {
2233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
2234 if (dig->linkb)
2235 return 1;
2236 else
2237 return 0;
2238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
2239 if (dig->linkb)
2240 return 3;
2241 else
2242 return 2;
2243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
2244 if (dig->linkb)
2245 return 5;
2246 else
2247 return 4;
2248 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
2249 return 6;
2250 default:
2251 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id)__drm_err("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id
)
;
2252 return 0;
2253 }
2254}
2255
2256/**
2257 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2258 *
2259 * @crtc: drm crtc
2260 *
2261 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2262 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2263 * monitors a dedicated PPLL must be used. If a particular board has
2264 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2265 * as there is no need to program the PLL itself. If we are not able to
2266 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2267 * avoid messing up an existing monitor.
2268 *
2269 * Asic specific PLL information
2270 *
2271 * DCE 10.x
2272 * Tonga
2273 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2274 * CI
2275 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2276 *
2277 */
2278static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2279{
2280 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2281 struct drm_device *dev = crtc->dev;
2282 struct amdgpu_device *adev = drm_to_adev(dev);
2283 u32 pll_in_use;
2284 int pll;
2285
2286 if ((adev->asic_type == CHIP_POLARIS10) ||
2287 (adev->asic_type == CHIP_POLARIS11) ||
2288 (adev->asic_type == CHIP_POLARIS12) ||
2289 (adev->asic_type == CHIP_VEGAM)) {
2290 struct amdgpu_encoder *amdgpu_encoder =
2291 to_amdgpu_encoder(amdgpu_crtc->encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (amdgpu_crtc->encoder); (struct amdgpu_encoder *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_encoder, base) )
;})
;
2292 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2293
2294 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5))
)
2295 return ATOM_DP_DTO11;
2296
2297 switch (amdgpu_encoder->encoder_id) {
2298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
2299 if (dig->linkb)
2300 return ATOM_COMBOPHY_PLL121;
2301 else
2302 return ATOM_COMBOPHY_PLL020;
2303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
2304 if (dig->linkb)
2305 return ATOM_COMBOPHY_PLL323;
2306 else
2307 return ATOM_COMBOPHY_PLL222;
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
2309 if (dig->linkb)
2310 return ATOM_COMBOPHY_PLL525;
2311 else
2312 return ATOM_COMBOPHY_PLL424;
2313 default:
2314 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id)__drm_err("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id
)
;
2315 return ATOM_PPLL_INVALID0xFF;
2316 }
2317 }
2318
2319 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5))
) {
2320 if (adev->clock.dp_extclk)
2321 /* skip PPLL programming if using ext clock */
2322 return ATOM_PPLL_INVALID0xFF;
2323 else {
2324 /* use the same PPLL for all DP monitors */
2325 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2326 if (pll != ATOM_PPLL_INVALID0xFF)
2327 return pll;
2328 }
2329 } else {
2330 /* use the same PPLL for all monitors with the same clock */
2331 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2332 if (pll != ATOM_PPLL_INVALID0xFF)
2333 return pll;
2334 }
2335
2336 /* XXX need to determine what plls are available on each DCE11 part */
2337 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2338 if (adev->flags & AMD_IS_APU) {
2339 if (!(pll_in_use & (1 << ATOM_PPLL10)))
2340 return ATOM_PPLL10;
2341 if (!(pll_in_use & (1 << ATOM_PPLL02)))
2342 return ATOM_PPLL02;
2343 DRM_ERROR("unable to allocate a PPLL\n")__drm_err("unable to allocate a PPLL\n");
2344 return ATOM_PPLL_INVALID0xFF;
2345 } else {
2346 if (!(pll_in_use & (1 << ATOM_PPLL21)))
2347 return ATOM_PPLL21;
2348 if (!(pll_in_use & (1 << ATOM_PPLL10)))
2349 return ATOM_PPLL10;
2350 if (!(pll_in_use & (1 << ATOM_PPLL02)))
2351 return ATOM_PPLL02;
2352 DRM_ERROR("unable to allocate a PPLL\n")__drm_err("unable to allocate a PPLL\n");
2353 return ATOM_PPLL_INVALID0xFF;
2354 }
2355 return ATOM_PPLL_INVALID0xFF;
2356}
2357
2358static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool_Bool lock)
2359{
2360 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2361 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2362 uint32_t cur_lock;
2363
2364 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset
), 0)
;
2365 if (lock)
2366 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1)(((cur_lock) & ~0x10000) | (0x10000 & ((1) << 0x10
)))
;
2367 else
2368 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0)(((cur_lock) & ~0x10000) | (0x10000 & ((0) << 0x10
)))
;
2369 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock)amdgpu_device_wreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset
), (cur_lock), 0)
;
2370}
2371
2372static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2373{
2374 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2375 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2376 u32 tmp;
2377
2378 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), 0)
;
2379 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2380 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2381}
2382
2383static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2384{
2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2386 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2387 u32 tmp;
2388
2389 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset
), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >>
16))), 0)
2390 upper_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset
), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >>
16))), 0)
;
2391 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset
), (((u32)(amdgpu_crtc->cursor_addr))), 0)
2392 lower_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset
), (((u32)(amdgpu_crtc->cursor_addr))), 0)
;
2393
2394 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), 0)
;
2395 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
2396 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2)(((tmp) & ~0x300) | (0x300 & ((2) << 0x8)));
2397 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), (tmp), 0)
;
2398}
2399
2400static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2401 int x, int y)
2402{
2403 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2404 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2405 int xorigin = 0, yorigin = 0;
2406
2407 amdgpu_crtc->cursor_x = x;
2408 amdgpu_crtc->cursor_y = y;
2409
2410 /* avivo cursor are offset into the total surface */
2411 x += crtc->x;
2412 y += crtc->y;
2413 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y)___drm_dbg(((void *)0), DRM_UT_CORE, "x %d y %d c->x %d c->y %d\n"
, x, y, crtc->x, crtc->y)
;
2414
2415 if (x < 0) {
2416 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1)(((-x)<(amdgpu_crtc->max_cursor_width - 1))?(-x):(amdgpu_crtc
->max_cursor_width - 1))
;
2417 x = 0;
2418 }
2419 if (y < 0) {
2420 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1)(((-y)<(amdgpu_crtc->max_cursor_height - 1))?(-y):(amdgpu_crtc
->max_cursor_height - 1))
;
2421 y = 0;
2422 }
2423
2424 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y)amdgpu_device_wreg(adev, (0x1a6a + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0)
;
2425 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin)amdgpu_device_wreg(adev, (0x1a6b + amdgpu_crtc->crtc_offset
), ((xorigin << 16) | yorigin), 0)
;
2426 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset
), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc
->cursor_height - 1)), 0)
2427 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1))amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset
), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc
->cursor_height - 1)), 0)
;
2428
2429 return 0;
2430}
2431
2432static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2433 int x, int y)
2434{
2435 int ret;
2436
2437 dce_v11_0_lock_cursor(crtc, true1);
2438 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2439 dce_v11_0_lock_cursor(crtc, false0);
2440
2441 return ret;
2442}
2443
2444static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2445 struct drm_file *file_priv,
2446 uint32_t handle,
2447 uint32_t width,
2448 uint32_t height,
2449 int32_t hot_x,
2450 int32_t hot_y)
2451{
2452 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2453 struct drm_gem_object *obj;
2454 struct amdgpu_bo *aobj;
2455 int ret;
2456
2457 if (!handle) {
2458 /* turn off cursor */
2459 dce_v11_0_hide_cursor(crtc);
2460 obj = NULL((void *)0);
2461 goto unpin;
2462 }
2463
2464 if ((width > amdgpu_crtc->max_cursor_width) ||
2465 (height > amdgpu_crtc->max_cursor_height)) {
2466 DRM_ERROR("bad cursor width or height %d x %d\n", width, height)__drm_err("bad cursor width or height %d x %d\n", width, height
)
;
2467 return -EINVAL22;
2468 }
2469
2470 obj = drm_gem_object_lookup(file_priv, handle);
2471 if (!obj) {
2472 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id)__drm_err("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc->crtc_id)
;
2473 return -ENOENT2;
2474 }
2475
2476 aobj = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );})
;
2477 ret = amdgpu_bo_reserve(aobj, false0);
2478 if (ret != 0) {
2479 drm_gem_object_put(obj);
2480 return ret;
2481 }
2482
2483 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM0x4);
2484 amdgpu_bo_unreserve(aobj);
2485 if (ret) {
2486 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret)__drm_err("Failed to pin new cursor BO (%d)\n", ret);
2487 drm_gem_object_put(obj);
2488 return ret;
2489 }
2490 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2491
2492 dce_v11_0_lock_cursor(crtc, true1);
2493
2494 if (width != amdgpu_crtc->cursor_width ||
2495 height != amdgpu_crtc->cursor_height ||
2496 hot_x != amdgpu_crtc->cursor_hot_x ||
2497 hot_y != amdgpu_crtc->cursor_hot_y) {
2498 int x, y;
2499
2500 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2501 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2502
2503 dce_v11_0_cursor_move_locked(crtc, x, y);
2504
2505 amdgpu_crtc->cursor_width = width;
2506 amdgpu_crtc->cursor_height = height;
2507 amdgpu_crtc->cursor_hot_x = hot_x;
2508 amdgpu_crtc->cursor_hot_y = hot_y;
2509 }
2510
2511 dce_v11_0_show_cursor(crtc);
2512 dce_v11_0_lock_cursor(crtc, false0);
2513
2514unpin:
2515 if (amdgpu_crtc->cursor_bo) {
2516 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((amdgpu_crtc->cursor_bo)); (struct amdgpu_bo *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.base) );
})
;
2517 ret = amdgpu_bo_reserve(aobj, true1);
2518 if (likely(ret == 0)__builtin_expect(!!(ret == 0), 1)) {
2519 amdgpu_bo_unpin(aobj);
2520 amdgpu_bo_unreserve(aobj);
2521 }
2522 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2523 }
2524
2525 amdgpu_crtc->cursor_bo = obj;
2526 return 0;
2527}
2528
2529static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2530{
2531 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2532
2533 if (amdgpu_crtc->cursor_bo) {
2534 dce_v11_0_lock_cursor(crtc, true1);
2535
2536 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2537 amdgpu_crtc->cursor_y);
2538
2539 dce_v11_0_show_cursor(crtc);
2540
2541 dce_v11_0_lock_cursor(crtc, false0);
2542 }
2543}
2544
2545static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2546 u16 *blue, uint32_t size,
2547 struct drm_modeset_acquire_ctx *ctx)
2548{
2549 dce_v11_0_crtc_load_lut(crtc);
2550
2551 return 0;
2552}
2553
2554static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2555{
2556 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2557
2558 drm_crtc_cleanup(crtc);
2559 kfree(amdgpu_crtc);
2560}
2561
2562static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2563 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2564 .cursor_move = dce_v11_0_crtc_cursor_move,
2565 .gamma_set = dce_v11_0_crtc_gamma_set,
2566 .set_config = amdgpu_display_crtc_set_config,
2567 .destroy = dce_v11_0_crtc_destroy,
2568 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2569 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2570 .enable_vblank = amdgpu_enable_vblank_kms,
2571 .disable_vblank = amdgpu_disable_vblank_kms,
2572 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2573};
2574
2575static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2576{
2577 struct drm_device *dev = crtc->dev;
2578 struct amdgpu_device *adev = drm_to_adev(dev);
2579 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2580 unsigned type;
2581
2582 switch (mode) {
2583 case DRM_MODE_DPMS_ON0:
2584 amdgpu_crtc->enabled = true1;
2585 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE1);
2586 dce_v11_0_vga_enable(crtc, true1);
2587 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE0);
2588 dce_v11_0_vga_enable(crtc, false0);
2589 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2590 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2591 amdgpu_crtc->crtc_id);
2592 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2593 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2594 drm_crtc_vblank_on(crtc);
2595 dce_v11_0_crtc_load_lut(crtc);
2596 break;
2597 case DRM_MODE_DPMS_STANDBY1:
2598 case DRM_MODE_DPMS_SUSPEND2:
2599 case DRM_MODE_DPMS_OFF3:
2600 drm_crtc_vblank_off(crtc);
2601 if (amdgpu_crtc->enabled) {
2602 dce_v11_0_vga_enable(crtc, true1);
2603 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE1);
2604 dce_v11_0_vga_enable(crtc, false0);
2605 }
2606 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE0);
2607 amdgpu_crtc->enabled = false0;
2608 break;
2609 }
2610 /* adjust pm to dpms */
2611 amdgpu_dpm_compute_clocks(adev);
2612}
2613
2614static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2615{
2616 /* disable crtc pair power gating before programming */
2617 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE0);
2618 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE1);
2619 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3);
2620}
2621
2622static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2623{
2624 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON0);
2625 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE0);
2626}
2627
2628static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2629{
2630 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2631 struct drm_device *dev = crtc->dev;
2632 struct amdgpu_device *adev = drm_to_adev(dev);
2633 struct amdgpu_atom_ss ss;
2634 int i;
2635
2636 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3);
2637 if (crtc->primary->fb) {
2638 int r;
2639 struct amdgpu_bo *abo;
2640
2641 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((crtc->primary->fb->obj[0])); (struct amdgpu_bo *
)( (char *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.
base) );})
;
2642 r = amdgpu_bo_reserve(abo, true1);
2643 if (unlikely(r)__builtin_expect(!!(r), 0))
2644 DRM_ERROR("failed to reserve abo before unpin\n")__drm_err("failed to reserve abo before unpin\n");
2645 else {
2646 amdgpu_bo_unpin(abo);
2647 amdgpu_bo_unreserve(abo);
2648 }
2649 }
2650 /* disable the GRPH */
2651 dce_v11_0_grph_enable(crtc, false0);
2652
2653 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE1);
2654
2655 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2656 if (adev->mode_info.crtcs[i] &&
2657 adev->mode_info.crtcs[i]->enabled &&
2658 i != amdgpu_crtc->crtc_id &&
2659 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2660 /* one other crtc is using this pll don't turn
2661 * off the pll
2662 */
2663 goto done;
2664 }
2665 }
2666
2667 switch (amdgpu_crtc->pll_id) {
2668 case ATOM_PPLL02:
2669 case ATOM_PPLL10:
2670 case ATOM_PPLL21:
2671 /* disable the ppll */
2672 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2673 0, 0, ATOM_DISABLE0, 0, 0, 0, 0, 0, false0, &ss);
2674 break;
2675 case ATOM_COMBOPHY_PLL020:
2676 case ATOM_COMBOPHY_PLL121:
2677 case ATOM_COMBOPHY_PLL222:
2678 case ATOM_COMBOPHY_PLL323:
2679 case ATOM_COMBOPHY_PLL424:
2680 case ATOM_COMBOPHY_PLL525:
2681 /* disable the ppll */
2682 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID0xFF, amdgpu_crtc->pll_id,
2683 0, 0, ATOM_DISABLE0, 0, 0, 0, 0, 0, false0, &ss);
2684 break;
2685 default:
2686 break;
2687 }
2688done:
2689 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF;
2690 amdgpu_crtc->adjusted_clock = 0;
2691 amdgpu_crtc->encoder = NULL((void *)0);
2692 amdgpu_crtc->connector = NULL((void *)0);
2693}
2694
2695static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2696 struct drm_display_mode *mode,
2697 struct drm_display_mode *adjusted_mode,
2698 int x, int y, struct drm_framebuffer *old_fb)
2699{
2700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2701 struct drm_device *dev = crtc->dev;
2702 struct amdgpu_device *adev = drm_to_adev(dev);
2703
2704 if (!amdgpu_crtc->adjusted_clock)
2705 return -EINVAL22;
2706
2707 if ((adev->asic_type == CHIP_POLARIS10) ||
2708 (adev->asic_type == CHIP_POLARIS11) ||
2709 (adev->asic_type == CHIP_POLARIS12) ||
2710 (adev->asic_type == CHIP_VEGAM)) {
2711 struct amdgpu_encoder *amdgpu_encoder =
2712 to_amdgpu_encoder(amdgpu_crtc->encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (amdgpu_crtc->encoder); (struct amdgpu_encoder *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_encoder, base) )
;})
;
2713 int encoder_mode =
2714 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2715
2716 /* SetPixelClock calculates the plls and ss values now */
2717 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2718 amdgpu_crtc->pll_id,
2719 encoder_mode, amdgpu_encoder->encoder_id,
2720 adjusted_mode->clock, 0, 0, 0, 0,
2721 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2722 } else {
2723 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2724 }
2725 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2726 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2727 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2728 amdgpu_atombios_crtc_scaler_setup(crtc);
2729 dce_v11_0_cursor_reset(crtc);
2730 /* update the hw version fpr dpm */
2731 amdgpu_crtc->hw_mode = *adjusted_mode;
2732
2733 return 0;
2734}
2735
2736static bool_Bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2737 const struct drm_display_mode *mode,
2738 struct drm_display_mode *adjusted_mode)
2739{
2740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );})
;
2741 struct drm_device *dev = crtc->dev;
2742 struct drm_encoder *encoder;
2743
2744 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}))
{
2746 if (encoder->crtc == crtc) {
2747 amdgpu_crtc->encoder = encoder;
2748 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2749 break;
2750 }
2751 }
2752 if ((amdgpu_crtc->encoder == NULL((void *)0)) || (amdgpu_crtc->connector == NULL((void *)0))) {
2753 amdgpu_crtc->encoder = NULL((void *)0);
2754 amdgpu_crtc->connector = NULL((void *)0);
2755 return false0;
2756 }
2757 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2758 return false0;
2759 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2760 return false0;
2761 /* pick pll */
2762 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2763 /* if we can't get a PPLL for a non-DP encoder, fail */
2764 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID0xFF) &&
2765 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5))
)
2766 return false0;
2767
2768 return true1;
2769}
2770
2771static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2772 struct drm_framebuffer *old_fb)
2773{
2774 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2775}
2776
2777static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2778 struct drm_framebuffer *fb,
2779 int x, int y, enum mode_set_atomic state)
2780{
2781 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2782}
2783
2784static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2785 .dpms = dce_v11_0_crtc_dpms,
2786 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2787 .mode_set = dce_v11_0_crtc_mode_set,
2788 .mode_set_base = dce_v11_0_crtc_set_base,
2789 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2790 .prepare = dce_v11_0_crtc_prepare,
2791 .commit = dce_v11_0_crtc_commit,
2792 .disable = dce_v11_0_crtc_disable,
2793 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2794};
2795
2796static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2797{
2798 struct amdgpu_crtc *amdgpu_crtc;
2799
2800 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2801 (AMDGPUFB_CONN_LIMIT4 * sizeof(struct drm_connector *)), GFP_KERNEL(0x0001 | 0x0004));
2802 if (amdgpu_crtc == NULL((void *)0))
2803 return -ENOMEM12;
2804
2805 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2806
2807 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2808 amdgpu_crtc->crtc_id = index;
2809 adev->mode_info.crtcs[index] = amdgpu_crtc;
2810
2811 amdgpu_crtc->max_cursor_width = 128;
2812 amdgpu_crtc->max_cursor_height = 128;
2813 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2814 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2815
2816 switch (amdgpu_crtc->crtc_id) {
2817 case 0:
2818 default:
2819 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c);
2820 break;
2821 case 1:
2822 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c);
2823 break;
2824 case 2:
2825 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c);
2826 break;
2827 case 3:
2828 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c);
2829 break;
2830 case 4:
2831 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c);
2832 break;
2833 case 5:
2834 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c);
2835 break;
2836 }
2837
2838 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF;
2839 amdgpu_crtc->adjusted_clock = 0;
2840 amdgpu_crtc->encoder = NULL((void *)0);
2841 amdgpu_crtc->connector = NULL((void *)0);
2842 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2843
2844 return 0;
2845}
2846
2847static int dce_v11_0_early_init(void *handle)
2848{
2849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2850
2851 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2852 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2853
2854 dce_v11_0_set_display_funcs(adev);
2855
2856 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2857
2858 switch (adev->asic_type) {
2859 case CHIP_CARRIZO:
2860 adev->mode_info.num_hpd = 6;
2861 adev->mode_info.num_dig = 9;
2862 break;
2863 case CHIP_STONEY:
2864 adev->mode_info.num_hpd = 6;
2865 adev->mode_info.num_dig = 9;
2866 break;
2867 case CHIP_POLARIS10:
2868 case CHIP_VEGAM:
2869 adev->mode_info.num_hpd = 6;
2870 adev->mode_info.num_dig = 6;
2871 break;
2872 case CHIP_POLARIS11:
2873 case CHIP_POLARIS12:
2874 adev->mode_info.num_hpd = 5;
2875 adev->mode_info.num_dig = 5;
2876 break;
2877 default:
2878 /* FIXME: not supported yet */
2879 return -EINVAL22;
2880 }
2881
2882 dce_v11_0_set_irq_funcs(adev);
2883
2884 return 0;
2885}
2886
2887static int dce_v11_0_sw_init(void *handle)
2888{
2889 int r, i;
2890 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2891
2892 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2893 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i + 1, &adev->crtc_irq);
2894 if (r)
2895 return r;
2896 }
2897
2898 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8; i < 20; i += 2) {
2899 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i, &adev->pageflip_irq);
2900 if (r)
2901 return r;
2902 }
2903
2904 /* HPD hotplug */
2905 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
2906 if (r)
2907 return r;
2908
2909 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2910
2911 adev_to_drm(adev)->mode_config.async_page_flip = true1;
2912
2913 adev_to_drm(adev)->mode_config.max_width = 16384;
2914 adev_to_drm(adev)->mode_config.max_height = 16384;
2915
2916 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2917 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2918
2919 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true1;
2920
2921 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
2922
2923 r = amdgpu_display_modeset_create_props(adev);
2924 if (r)
2925 return r;
2926
2927 adev_to_drm(adev)->mode_config.max_width = 16384;
2928 adev_to_drm(adev)->mode_config.max_height = 16384;
2929
2930
2931 /* allocate crtcs */
2932 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2933 r = dce_v11_0_crtc_init(adev, i);
2934 if (r)
2935 return r;
2936 }
2937
2938 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2939 amdgpu_display_print_display_setup(adev_to_drm(adev));
2940 else
2941 return -EINVAL22;
2942
2943 /* setup afmt */
2944 r = dce_v11_0_afmt_init(adev);
2945 if (r)
2946 return r;
2947
2948 r = dce_v11_0_audio_init(adev);
2949 if (r)
2950 return r;
2951
2952 drm_kms_helper_poll_init(adev_to_drm(adev));
2953
2954 adev->mode_info.mode_config_initialized = true1;
2955 return 0;
2956}
2957
2958static int dce_v11_0_sw_fini(void *handle)
2959{
2960 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2961
2962 kfree(adev->mode_info.bios_hardcoded_edid);
2963
2964 drm_kms_helper_poll_fini(adev_to_drm(adev));
2965
2966 dce_v11_0_audio_fini(adev);
2967
2968 dce_v11_0_afmt_fini(adev);
2969
2970 drm_mode_config_cleanup(adev_to_drm(adev));
2971 adev->mode_info.mode_config_initialized = false0;
2972
2973 return 0;
2974}
2975
2976static int dce_v11_0_hw_init(void *handle)
2977{
2978 int i;
2979 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2980
2981 dce_v11_0_init_golden_registers(adev);
2982
2983 /* disable vga render */
2984 dce_v11_0_set_vga_render_state(adev, false0);
2985 /* init dig PHYs, disp eng pll */
2986 amdgpu_atombios_crtc_powergate_init(adev);
2987 amdgpu_atombios_encoder_init_dig(adev);
2988 if ((adev->asic_type == CHIP_POLARIS10) ||
2989 (adev->asic_type == CHIP_POLARIS11) ||
2990 (adev->asic_type == CHIP_POLARIS12) ||
2991 (adev->asic_type == CHIP_VEGAM)) {
2992 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2993 DCE_CLOCK_TYPE_DISPCLK0, ATOM_GCK_DFS8);
2994 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2995 DCE_CLOCK_TYPE_DPREFCLK1, ATOM_GCK_DFS8);
2996 } else {
2997 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2998 }
2999
3000 /* initialize hpd */
3001 dce_v11_0_hpd_init(adev);
3002
3003 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3004 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
3005 }
3006
3007 dce_v11_0_pageflip_interrupt_init(adev);
3008
3009 return 0;
3010}
3011
3012static int dce_v11_0_hw_fini(void *handle)
3013{
3014 int i;
3015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3016
3017 dce_v11_0_hpd_fini(adev);
3018
3019 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3020 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
3021 }
3022
3023 dce_v11_0_pageflip_interrupt_fini(adev);
3024
3025 return 0;
3026}
3027
3028static int dce_v11_0_suspend(void *handle)
3029{
3030 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3031 int r;
3032
3033 r = amdgpu_display_suspend_helper(adev);
3034 if (r)
3035 return r;
3036
3037 adev->mode_info.bl_level =
3038 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3039
3040 return dce_v11_0_hw_fini(handle);
3041}
3042
3043static int dce_v11_0_resume(void *handle)
3044{
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046 int ret;
3047
3048 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3049 adev->mode_info.bl_level);
3050
3051 ret = dce_v11_0_hw_init(handle);
3052
3053 /* turn on the BL */
3054 if (adev->mode_info.bl_encoder) {
3055 u8 bl_level = amdgpu_display_backlight_get_level(adev,(adev)->mode_info.funcs->backlight_get_level((adev->
mode_info.bl_encoder))
3056 adev->mode_info.bl_encoder)(adev)->mode_info.funcs->backlight_get_level((adev->
mode_info.bl_encoder))
;
3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,(adev)->mode_info.funcs->backlight_set_level((adev->
mode_info.bl_encoder), (bl_level))
3058 bl_level)(adev)->mode_info.funcs->backlight_set_level((adev->
mode_info.bl_encoder), (bl_level))
;
3059 }
3060 if (ret)
3061 return ret;
3062
3063 return amdgpu_display_resume_helper(adev);
3064}
3065
3066static bool_Bool dce_v11_0_is_idle(void *handle)
3067{
3068 return true1;
3069}
3070
3071static int dce_v11_0_wait_for_idle(void *handle)
3072{
3073 return 0;
3074}
3075
3076static int dce_v11_0_soft_reset(void *handle)
3077{
3078 u32 srbm_soft_reset = 0, tmp;
3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3080
3081 if (dce_v11_0_is_display_hung(adev))
3082 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK0x20;
3083
3084 if (srbm_soft_reset) {
3085 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
3086 tmp |= srbm_soft_reset;
3087 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
3088 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
3089 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
3090
3091 udelay(50);
3092
3093 tmp &= ~srbm_soft_reset;
3094 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
3095 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
3096
3097 /* Wait a little for things to settle down */
3098 udelay(50);
3099 }
3100 return 0;
3101}
3102
3103static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3104 int crtc,
3105 enum amdgpu_interrupt_state state)
3106{
3107 u32 lb_interrupt_mask;
3108
3109 if (crtc >= adev->mode_info.num_crtc) {
3110 DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc
)
;
3111 return;
3112 }
3113
3114 switch (state) {
3115 case AMDGPU_IRQ_STATE_DISABLE:
3116 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3117 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0
)))
3118 VBLANK_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0
)))
;
3119 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0)
;
3120 break;
3121 case AMDGPU_IRQ_STATE_ENABLE:
3122 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3123 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0
)))
3124 VBLANK_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0
)))
;
3125 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0)
;
3126 break;
3127 default:
3128 break;
3129 }
3130}
3131
3132static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3133 int crtc,
3134 enum amdgpu_interrupt_state state)
3135{
3136 u32 lb_interrupt_mask;
3137
3138 if (crtc >= adev->mode_info.num_crtc) {
3139 DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc
)
;
3140 return;
3141 }
3142
3143 switch (state) {
3144 case AMDGPU_IRQ_STATE_DISABLE:
3145 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3146 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) <<
0x4)))
3147 VLINE_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) <<
0x4)))
;
3148 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0)
;
3149 break;
3150 case AMDGPU_IRQ_STATE_ENABLE:
3151 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3152 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) <<
0x4)))
3153 VLINE_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) <<
0x4)))
;
3154 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0)
;
3155 break;
3156 default:
3157 break;
3158 }
3159}
3160
3161static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3162 struct amdgpu_irq_src *source,
3163 unsigned hpd,
3164 enum amdgpu_interrupt_state state)
3165{
3166 u32 tmp;
3167
3168 if (hpd >= adev->mode_info.num_hpd) {
3169 DRM_DEBUG("invalid hdp %d\n", hpd)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid hdp %d\n", hpd);
3170 return 0;
3171 }
3172
3173 switch (state) {
3174 case AMDGPU_IRQ_STATE_DISABLE:
3175 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3176 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10))
)
;
3177 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
)
;
3178 break;
3179 case AMDGPU_IRQ_STATE_ENABLE:
3180 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3181 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
)
;
3182 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
)
;
3183 break;
3184 default:
3185 break;
3186 }
3187
3188 return 0;
3189}
3190
3191static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3192 struct amdgpu_irq_src *source,
3193 unsigned type,
3194 enum amdgpu_interrupt_state state)
3195{
3196 switch (type) {
3197 case AMDGPU_CRTC_IRQ_VBLANK1:
3198 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3199 break;
3200 case AMDGPU_CRTC_IRQ_VBLANK2:
3201 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3202 break;
3203 case AMDGPU_CRTC_IRQ_VBLANK3:
3204 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3205 break;
3206 case AMDGPU_CRTC_IRQ_VBLANK4:
3207 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3208 break;
3209 case AMDGPU_CRTC_IRQ_VBLANK5:
3210 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3211 break;
3212 case AMDGPU_CRTC_IRQ_VBLANK6:
3213 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3214 break;
3215 case AMDGPU_CRTC_IRQ_VLINE1:
3216 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3217 break;
3218 case AMDGPU_CRTC_IRQ_VLINE2:
3219 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3220 break;
3221 case AMDGPU_CRTC_IRQ_VLINE3:
3222 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3223 break;
3224 case AMDGPU_CRTC_IRQ_VLINE4:
3225 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3226 break;
3227 case AMDGPU_CRTC_IRQ_VLINE5:
3228 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3229 break;
3230 case AMDGPU_CRTC_IRQ_VLINE6:
3231 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3232 break;
3233 default:
3234 break;
3235 }
3236 return 0;
3237}
3238
3239static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3240 struct amdgpu_irq_src *src,
3241 unsigned type,
3242 enum amdgpu_interrupt_state state)
3243{
3244 u32 reg;
3245
3246 if (type >= adev->mode_info.num_crtc) {
3247 DRM_ERROR("invalid pageflip crtc %d\n", type)__drm_err("invalid pageflip crtc %d\n", type);
3248 return -EINVAL22;
3249 }
3250
3251 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type])amdgpu_device_rreg(adev, (0x1a17 + crtc_offsets[type]), 0);
3252 if (state == AMDGPU_IRQ_STATE_DISABLE)
3253 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg &
~0x1), 0)
3254 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg &
~0x1), 0)
;
3255 else
3256 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg |
0x1), 0)
3257 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg |
0x1), 0)
;
3258
3259 return 0;
3260}
3261
3262static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3263 struct amdgpu_irq_src *source,
3264 struct amdgpu_iv_entry *entry)
3265{
3266 unsigned long flags;
3267 unsigned crtc_id;
3268 struct amdgpu_crtc *amdgpu_crtc;
3269 struct amdgpu_flip_work *works;
3270
3271 crtc_id = (entry->src_id - 8) >> 1;
3272 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3273
3274 if (crtc_id >= adev->mode_info.num_crtc) {
3275 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id)__drm_err("invalid pageflip crtc %d\n", crtc_id);
3276 return -EINVAL22;
3277 }
3278
3279 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id])amdgpu_device_rreg(adev, (0x1a16 + crtc_offsets[crtc_id]), 0) &
3280 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK0x1)
3281 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100
), 0)
3282 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK)amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100
), 0)
;
3283
3284 /* IRQ could occur when in initial stage */
3285 if(amdgpu_crtc == NULL((void *)0))
3286 return 0;
3287
3288 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0)
;
3289 works = amdgpu_crtc->pflip_works;
3290 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3291 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3292 "AMDGPU_FLIP_SUBMITTED(%d)\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3293 amdgpu_crtc->pflip_status,___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3294 AMDGPU_FLIP_SUBMITTED)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
;
3295 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0)
;
3296 return 0;
3297 }
3298
3299 /* page flip completed. clean up */
3300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3301 amdgpu_crtc->pflip_works = NULL((void *)0);
3302
3303 /* wakeup usersapce */
3304 if(works->event)
3305 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3306
3307 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0)
;
3308
3309 drm_crtc_vblank_put(&amdgpu_crtc->base);
3310 schedule_work(&works->unpin_work);
3311
3312 return 0;
3313}
3314
3315static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3316 int hpd)
3317{
3318 u32 tmp;
3319
3320 if (hpd >= adev->mode_info.num_hpd) {
3321 DRM_DEBUG("invalid hdp %d\n", hpd)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid hdp %d\n", hpd);
3322 return;
3323 }
3324
3325 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3326 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
3327 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
)
;
3328}
3329
3330static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3331 int crtc)
3332{
3333 u32 tmp;
3334
3335 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3336 DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc
)
;
3337 return;
3338 }
3339
3340 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1acb + crtc_offsets[crtc]), 0);
3341 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
3342 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1acb + crtc_offsets[crtc]), (tmp)
, 0)
;
3343}
3344
3345static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3346 int crtc)
3347{
3348 u32 tmp;
3349
3350 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3351 DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc
)
;
3352 return;
3353 }
3354
3355 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac9 + crtc_offsets[crtc]), 0);
3356 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
3357 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1ac9 + crtc_offsets[crtc]), (tmp)
, 0)
;
3358}
3359
3360static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3361 struct amdgpu_irq_src *source,
3362 struct amdgpu_iv_entry *entry)
3363{
3364 unsigned crtc = entry->src_id - 1;
3365 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[crtc].reg)
, 0)
;
3366 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3367 crtc);
3368
3369 switch (entry->src_data[0]) {
3370 case 0: /* vblank */
3371 if (disp_int & interrupt_status_offsets[crtc].vblank)
3372 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3373 else
3374 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n"
)
;
3375
3376 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3377 drm_handle_vblank(adev_to_drm(adev), crtc);
3378 }
3379 DRM_DEBUG("IH: D%d vblank\n", crtc + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: D%d vblank\n", crtc
+ 1)
;
3380
3381 break;
3382 case 1: /* vline */
3383 if (disp_int & interrupt_status_offsets[crtc].vline)
3384 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3385 else
3386 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n"
)
;
3387
3388 DRM_DEBUG("IH: D%d vline\n", crtc + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: D%d vline\n", crtc +
1)
;
3389
3390 break;
3391 default:
3392 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])___drm_dbg(((void *)0), DRM_UT_CORE, "Unhandled interrupt: %d %d\n"
, entry->src_id, entry->src_data[0])
;
3393 break;
3394 }
3395
3396 return 0;
3397}
3398
3399static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3400 struct amdgpu_irq_src *source,
3401 struct amdgpu_iv_entry *entry)
3402{
3403 uint32_t disp_int, mask;
3404 unsigned hpd;
3405
3406 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3407 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])___drm_dbg(((void *)0), DRM_UT_CORE, "Unhandled interrupt: %d %d\n"
, entry->src_id, entry->src_data[0])
;
3408 return 0;
3409 }
3410
3411 hpd = entry->src_data[0];
3412 disp_int = RREG32(interrupt_status_offsets[hpd].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[hpd].reg),
0)
;
3413 mask = interrupt_status_offsets[hpd].hpd;
3414
3415 if (disp_int & mask) {
3416 dce_v11_0_hpd_int_ack(adev, hpd);
3417 schedule_work(&adev->hotplug_work);
3418 DRM_DEBUG("IH: HPD%d\n", hpd + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: HPD%d\n", hpd + 1);
3419 }
3420
3421 return 0;
3422}
3423
3424static int dce_v11_0_set_clockgating_state(void *handle,
3425 enum amd_clockgating_state state)
3426{
3427 return 0;
3428}
3429
3430static int dce_v11_0_set_powergating_state(void *handle,
3431 enum amd_powergating_state state)
3432{
3433 return 0;
3434}
3435
3436static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3437 .name = "dce_v11_0",
3438 .early_init = dce_v11_0_early_init,
3439 .late_init = NULL((void *)0),
3440 .sw_init = dce_v11_0_sw_init,
3441 .sw_fini = dce_v11_0_sw_fini,
3442 .hw_init = dce_v11_0_hw_init,
3443 .hw_fini = dce_v11_0_hw_fini,
3444 .suspend = dce_v11_0_suspend,
3445 .resume = dce_v11_0_resume,
3446 .is_idle = dce_v11_0_is_idle,
3447 .wait_for_idle = dce_v11_0_wait_for_idle,
3448 .soft_reset = dce_v11_0_soft_reset,
3449 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3450 .set_powergating_state = dce_v11_0_set_powergating_state,
3451};
3452
3453static void
3454dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3455 struct drm_display_mode *mode,
3456 struct drm_display_mode *adjusted_mode)
3457{
3458 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
3459
3460 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3461
3462 /* need to call this here rather than in prepare() since we need some crtc info */
3463 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);
3464
3465 /* set scaler clears this on some chips */
3466 dce_v11_0_set_interleave(encoder->crtc, mode);
3467
3468 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3) {
3469 dce_v11_0_afmt_enable(encoder, true1);
3470 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3471 }
3472}
3473
3474static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3475{
3476 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3477 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
3478 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3479
3480 if ((amdgpu_encoder->active_device &
3481 (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
<< 0x0000000B ) | (0x1L << 0x00000006 ))
| ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) ||
3482 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3483 ENCODER_OBJECT_ID_NONE0x00)) {
3484 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3485 if (dig) {
3486 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3487 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
<< 0x0000000B ) | (0x1L << 0x00000006 ))
)
3488 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3489 }
3490 }
3491
3492 amdgpu_atombios_scratch_regs_lock(adev, true1);
3493
3494 if (connector) {
3495 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );})
;
3496
3497 /* select the clock/data port if it uses a router */
3498 if (amdgpu_connector->router.cd_valid)
3499 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3500
3501 /* turn eDP panel on for mode set */
3502 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)
3503 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3504 ATOM_TRANSMITTER_ACTION_POWER_ON12);
3505 }
3506
3507 /* this is needed for the pll/ss setup to work correctly in some cases */
3508 amdgpu_atombios_encoder_set_crtc_source(encoder);
3509 /* set up the FMT blocks */
3510 dce_v11_0_program_fmt(encoder);
3511}
3512
3513static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3514{
3515 struct drm_device *dev = encoder->dev;
3516 struct amdgpu_device *adev = drm_to_adev(dev);
3517
3518 /* need to call this here as we need the crtc set up */
3519 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON0);
3520 amdgpu_atombios_scratch_regs_lock(adev, false0);
3521}
3522
3523static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3524{
3525 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
3526 struct amdgpu_encoder_atom_dig *dig;
3527
3528 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);
3529
3530 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3531 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3)
3532 dce_v11_0_afmt_enable(encoder, false0);
3533 dig = amdgpu_encoder->enc_priv;
3534 dig->dig_encoder = -1;
3535 }
3536 amdgpu_encoder->active_device = 0;
3537}
3538
3539/* these are handled by the primary encoders */
3540static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3541{
3542
3543}
3544
3545static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3546{
3547
3548}
3549
3550static void
3551dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3552 struct drm_display_mode *mode,
3553 struct drm_display_mode *adjusted_mode)
3554{
3555
3556}
3557
3558static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3559{
3560
3561}
3562
3563static void
3564dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3565{
3566
3567}
3568
3569static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3570 .dpms = dce_v11_0_ext_dpms,
3571 .prepare = dce_v11_0_ext_prepare,
3572 .mode_set = dce_v11_0_ext_mode_set,
3573 .commit = dce_v11_0_ext_commit,
3574 .disable = dce_v11_0_ext_disable,
3575 /* no detect for TMDS/LVDS yet */
3576};
3577
3578static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3579 .dpms = amdgpu_atombios_encoder_dpms,
3580 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3581 .prepare = dce_v11_0_encoder_prepare,
3582 .mode_set = dce_v11_0_encoder_mode_set,
3583 .commit = dce_v11_0_encoder_commit,
3584 .disable = dce_v11_0_encoder_disable,
3585 .detect = amdgpu_atombios_encoder_dig_detect,
3586};
3587
3588static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3589 .dpms = amdgpu_atombios_encoder_dpms,
3590 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3591 .prepare = dce_v11_0_encoder_prepare,
3592 .mode_set = dce_v11_0_encoder_mode_set,
3593 .commit = dce_v11_0_encoder_commit,
3594 .detect = amdgpu_atombios_encoder_dac_detect,
3595};
3596
3597static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3598{
3599 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
3600 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
3601 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3602 kfree(amdgpu_encoder->enc_priv);
3603 drm_encoder_cleanup(encoder);
3604 kfree(amdgpu_encoder);
3605}
3606
3607static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3608 .destroy = dce_v11_0_encoder_destroy,
3609};
3610
3611static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3612 uint32_t encoder_enum,
3613 uint32_t supported_device,
3614 u16 caps)
3615{
3616 struct drm_device *dev = adev_to_drm(adev);
3617 struct drm_encoder *encoder;
3618 struct amdgpu_encoder *amdgpu_encoder;
3619
3620 /* see if we already added it */
3621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}))
{
3622 amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );})
;
3623 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3624 amdgpu_encoder->devices |= supported_device;
3625 return;
3626 }
3627
3628 }
3629
3630 /* add a new one */
3631 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL(0x0001 | 0x0004));
3632 if (!amdgpu_encoder)
3633 return;
3634
3635 encoder = &amdgpu_encoder->base;
3636 switch (adev->mode_info.num_crtc) {
3637 case 1:
3638 encoder->possible_crtcs = 0x1;
3639 break;
3640 case 2:
3641 default:
3642 encoder->possible_crtcs = 0x3;
3643 break;
3644 case 3:
3645 encoder->possible_crtcs = 0x7;
3646 break;
3647 case 4:
3648 encoder->possible_crtcs = 0xf;
3649 break;
3650 case 5:
3651 encoder->possible_crtcs = 0x1f;
3652 break;
3653 case 6:
3654 encoder->possible_crtcs = 0x3f;
3655 break;
3656 }
3657
3658 amdgpu_encoder->enc_priv = NULL((void *)0);
3659
3660 amdgpu_encoder->encoder_enum = encoder_enum;
3661 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00;
3662 amdgpu_encoder->devices = supported_device;
3663 amdgpu_encoder->rmx_type = RMX_OFF;
3664 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3665 amdgpu_encoder->is_ext_encoder = false0;
3666 amdgpu_encoder->caps = caps;
3667
3668 switch (amdgpu_encoder->encoder_id) {
3669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
3670 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
3671 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3672 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3673 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3674 break;
3675 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
3676 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
3677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
3678 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
3679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
3680 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
3681 amdgpu_encoder->rmx_type = RMX_FULL;
3682 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3683 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
3684 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3685 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) {
3686 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3687 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3688 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3689 } else {
3690 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3691 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
3692 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3693 }
3694 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3695 break;
3696 case ENCODER_OBJECT_ID_SI170B0x08:
3697 case ENCODER_OBJECT_ID_CH73030x09:
3698 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA0x0C:
3699 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB0x0D:
3700 case ENCODER_OBJECT_ID_TITFP5130x0E:
3701 case ENCODER_OBJECT_ID_VT16230x10:
3702 case ENCODER_OBJECT_ID_HDMI_SI19300x11:
3703 case ENCODER_OBJECT_ID_TRAVIS0x23:
3704 case ENCODER_OBJECT_ID_NUTMEG0x22:
3705 /* these are handled by the primary encoders */
3706 amdgpu_encoder->is_ext_encoder = true1;
3707 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
3708 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3709 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
3710 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 ))))
3711 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3712 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3713 else
3714 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3715 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
3716 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3717 break;
3718 }
3719}
3720
3721static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3722 .bandwidth_update = &dce_v11_0_bandwidth_update,
3723 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3724 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3725 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3726 .hpd_sense = &dce_v11_0_hpd_sense,
3727 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3728 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3729 .page_flip = &dce_v11_0_page_flip,
3730 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3731 .add_encoder = &dce_v11_0_encoder_add,
3732 .add_connector = &amdgpu_connector_add,
3733};
3734
3735static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3736{
3737 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3738}
3739
3740static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3741 .set = dce_v11_0_set_crtc_irq_state,
3742 .process = dce_v11_0_crtc_irq,
3743};
3744
3745static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3746 .set = dce_v11_0_set_pageflip_irq_state,
3747 .process = dce_v11_0_pageflip_irq,
3748};
3749
3750static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3751 .set = dce_v11_0_set_hpd_irq_state,
3752 .process = dce_v11_0_hpd_irq,
3753};
3754
3755static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3756{
3757 if (adev->mode_info.num_crtc > 0)
3758 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3759 else
3760 adev->crtc_irq.num_types = 0;
3761 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3762
3763 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3764 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3765
3766 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3767 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3768}
3769
3770const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3771{
3772 .type = AMD_IP_BLOCK_TYPE_DCE,
3773 .major = 11,
3774 .minor = 0,
3775 .rev = 0,
3776 .funcs = &dce_v11_0_ip_funcs,
3777};
3778
3779const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3780{
3781 .type = AMD_IP_BLOCK_TYPE_DCE,
3782 .major = 11,
3783 .minor = 2,
3784 .rev = 0,
3785 .funcs = &dce_v11_0_ip_funcs,
3786};