| File: | dev/pci/drm/i915/gem/i915_gem_ttm_move.c |
| Warning: | line 57, column 3 Access to field 'caching' results in a dereference of a null pointer (loaded from variable 'ttm') |
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| 1 | // SPDX-License-Identifier: MIT | ||||
| 2 | /* | ||||
| 3 | * Copyright © 2021 Intel Corporation | ||||
| 4 | */ | ||||
| 5 | |||||
| 6 | #include <drm/ttm/ttm_bo_driver.h> | ||||
| 7 | |||||
| 8 | #include "i915_deps.h" | ||||
| 9 | #include "i915_drv.h" | ||||
| 10 | #include "intel_memory_region.h" | ||||
| 11 | #include "intel_region_ttm.h" | ||||
| 12 | |||||
| 13 | #include "gem/i915_gem_object.h" | ||||
| 14 | #include "gem/i915_gem_region.h" | ||||
| 15 | #include "gem/i915_gem_ttm.h" | ||||
| 16 | #include "gem/i915_gem_ttm_move.h" | ||||
| 17 | |||||
| 18 | #include "gt/intel_engine_pm.h" | ||||
| 19 | #include "gt/intel_gt.h" | ||||
| 20 | #include "gt/intel_migrate.h" | ||||
| 21 | |||||
| 22 | /** | ||||
| 23 | * DOC: Selftest failure modes for failsafe migration: | ||||
| 24 | * | ||||
| 25 | * For fail_gpu_migration, the gpu blit scheduled is always a clear blit | ||||
| 26 | * rather than a copy blit, and then we force the failure paths as if | ||||
| 27 | * the blit fence returned an error. | ||||
| 28 | * | ||||
| 29 | * For fail_work_allocation we fail the kmalloc of the async worker, we | ||||
| 30 | * sync the gpu blit. If it then fails, or fail_gpu_migration is set to | ||||
| 31 | * true, then a memcpy operation is performed sync. | ||||
| 32 | */ | ||||
| 33 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)0 | ||||
| 34 | static bool_Bool fail_gpu_migration; | ||||
| 35 | static bool_Bool fail_work_allocation; | ||||
| 36 | static bool_Bool ban_memcpy; | ||||
| 37 | |||||
| 38 | void i915_ttm_migrate_set_failure_modes(bool_Bool gpu_migration, | ||||
| 39 | bool_Bool work_allocation) | ||||
| 40 | { | ||||
| 41 | fail_gpu_migration = gpu_migration; | ||||
| 42 | fail_work_allocation = work_allocation; | ||||
| 43 | } | ||||
| 44 | |||||
| 45 | void i915_ttm_migrate_set_ban_memcpy(bool_Bool ban) | ||||
| 46 | { | ||||
| 47 | ban_memcpy = ban; | ||||
| 48 | } | ||||
| 49 | #endif | ||||
| 50 | |||||
| 51 | static enum i915_cache_level | ||||
| 52 | i915_ttm_cache_level(struct drm_i915_privateinteldrm_softc *i915, struct ttm_resource *res, | ||||
| 53 | struct ttm_tt *ttm) | ||||
| 54 | { | ||||
| 55 | return ((HAS_LLC(i915)((&(i915)->__info)->has_llc) || HAS_SNOOP(i915)((&(i915)->__info)->has_snoop)) && | ||||
| 56 | !i915_ttm_gtt_binds_lmem(res) && | ||||
| 57 | ttm->caching == ttm_cached) ? I915_CACHE_LLC : | ||||
| |||||
| 58 | I915_CACHE_NONE; | ||||
| 59 | } | ||||
| 60 | |||||
| 61 | static struct intel_memory_region * | ||||
| 62 | i915_ttm_region(struct ttm_device *bdev, int ttm_mem_type) | ||||
| 63 | { | ||||
| 64 | struct drm_i915_privateinteldrm_softc *i915 = container_of(bdev, typeof(*i915), bdev)({ const __typeof( ((typeof(*i915) *)0)->bdev ) *__mptr = ( bdev); (typeof(*i915) *)( (char *)__mptr - __builtin_offsetof (typeof(*i915), bdev) );}); | ||||
| 65 | |||||
| 66 | /* There's some room for optimization here... */ | ||||
| 67 | GEM_BUG_ON(ttm_mem_type != I915_PL_SYSTEM &&((void)0) | ||||
| 68 | ttm_mem_type < I915_PL_LMEM0)((void)0); | ||||
| 69 | if (ttm_mem_type == I915_PL_SYSTEM0) | ||||
| 70 | return intel_memory_region_lookup(i915, INTEL_MEMORY_SYSTEM, | ||||
| 71 | 0); | ||||
| 72 | |||||
| 73 | return intel_memory_region_lookup(i915, INTEL_MEMORY_LOCAL, | ||||
| 74 | ttm_mem_type - I915_PL_LMEM03); | ||||
| 75 | } | ||||
| 76 | |||||
| 77 | /** | ||||
| 78 | * i915_ttm_adjust_domains_after_move - Adjust the GEM domains after a | ||||
| 79 | * TTM move | ||||
| 80 | * @obj: The gem object | ||||
| 81 | */ | ||||
| 82 | void i915_ttm_adjust_domains_after_move(struct drm_i915_gem_object *obj) | ||||
| 83 | { | ||||
| 84 | struct ttm_buffer_object *bo = i915_gem_to_ttm(obj); | ||||
| 85 | |||||
| 86 | if (i915_ttm_cpu_maps_iomem(bo->resource) || bo->ttm->caching != ttm_cached) { | ||||
| 87 | obj->write_domain = I915_GEM_DOMAIN_WC0x00000080; | ||||
| 88 | obj->read_domains = I915_GEM_DOMAIN_WC0x00000080; | ||||
| 89 | } else { | ||||
| 90 | obj->write_domain = I915_GEM_DOMAIN_CPU0x00000001; | ||||
| 91 | obj->read_domains = I915_GEM_DOMAIN_CPU0x00000001; | ||||
| 92 | } | ||||
| 93 | } | ||||
| 94 | |||||
| 95 | /** | ||||
| 96 | * i915_ttm_adjust_gem_after_move - Adjust the GEM state after a TTM move | ||||
| 97 | * @obj: The gem object | ||||
| 98 | * | ||||
| 99 | * Adjusts the GEM object's region, mem_flags and cache coherency after a | ||||
| 100 | * TTM move. | ||||
| 101 | */ | ||||
| 102 | void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj) | ||||
| 103 | { | ||||
| 104 | struct ttm_buffer_object *bo = i915_gem_to_ttm(obj); | ||||
| 105 | unsigned int cache_level; | ||||
| 106 | unsigned int i; | ||||
| 107 | |||||
| 108 | /* | ||||
| 109 | * If object was moved to an allowable region, update the object | ||||
| 110 | * region to consider it migrated. Note that if it's currently not | ||||
| 111 | * in an allowable region, it's evicted and we don't update the | ||||
| 112 | * object region. | ||||
| 113 | */ | ||||
| 114 | if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) { | ||||
| 115 | for (i = 0; i < obj->mm.n_placements; ++i) { | ||||
| 116 | struct intel_memory_region *mr = obj->mm.placements[i]; | ||||
| 117 | |||||
| 118 | if (intel_region_to_ttm_type(mr) == bo->resource->mem_type && | ||||
| 119 | mr != obj->mm.region) { | ||||
| 120 | i915_gem_object_release_memory_region(obj); | ||||
| 121 | i915_gem_object_init_memory_region(obj, mr); | ||||
| 122 | break; | ||||
| 123 | } | ||||
| 124 | } | ||||
| 125 | } | ||||
| 126 | |||||
| 127 | obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE(1UL << (0)) | I915_BO_FLAG_IOMEM(1UL << (1))); | ||||
| 128 | |||||
| 129 | obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM(1UL << (1)) : | ||||
| 130 | I915_BO_FLAG_STRUCT_PAGE(1UL << (0)); | ||||
| 131 | |||||
| 132 | cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource, | ||||
| 133 | bo->ttm); | ||||
| 134 | i915_gem_object_set_cache_coherency(obj, cache_level); | ||||
| 135 | } | ||||
| 136 | |||||
| 137 | /** | ||||
| 138 | * i915_ttm_move_notify - Prepare an object for move | ||||
| 139 | * @bo: The ttm buffer object. | ||||
| 140 | * | ||||
| 141 | * This function prepares an object for move by removing all GPU bindings, | ||||
| 142 | * removing all CPU mapings and finally releasing the pages sg-table. | ||||
| 143 | * | ||||
| 144 | * Return: 0 if successful, negative error code on error. | ||||
| 145 | */ | ||||
| 146 | int i915_ttm_move_notify(struct ttm_buffer_object *bo) | ||||
| 147 | { | ||||
| 148 | struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); | ||||
| 149 | int ret; | ||||
| 150 | |||||
| 151 | /* | ||||
| 152 | * Note: The async unbinding here will actually transform the | ||||
| 153 | * blocking wait for unbind into a wait before finally submitting | ||||
| 154 | * evict / migration blit and thus stall the migration timeline | ||||
| 155 | * which may not be good for overall throughput. We should make | ||||
| 156 | * sure we await the unbind fences *after* the migration blit | ||||
| 157 | * instead of *before* as we currently do. | ||||
| 158 | */ | ||||
| 159 | ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE(1UL << (0)) | | ||||
| 160 | I915_GEM_OBJECT_UNBIND_ASYNC(1UL << (4))); | ||||
| 161 | if (ret) | ||||
| 162 | return ret; | ||||
| 163 | |||||
| 164 | ret = __i915_gem_object_put_pages(obj); | ||||
| 165 | if (ret) | ||||
| 166 | return ret; | ||||
| 167 | |||||
| 168 | return 0; | ||||
| 169 | } | ||||
| 170 | |||||
| 171 | static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo, | ||||
| 172 | bool_Bool clear, | ||||
| 173 | struct ttm_resource *dst_mem, | ||||
| 174 | struct ttm_tt *dst_ttm, | ||||
| 175 | struct sg_table *dst_st, | ||||
| 176 | const struct i915_deps *deps) | ||||
| 177 | { | ||||
| 178 | struct drm_i915_privateinteldrm_softc *i915 = container_of(bo->bdev, typeof(*i915),({ const __typeof( ((typeof(*i915) *)0)->bdev ) *__mptr = ( bo->bdev); (typeof(*i915) *)( (char *)__mptr - __builtin_offsetof (typeof(*i915), bdev) );}) | ||||
| 179 | bdev)({ const __typeof( ((typeof(*i915) *)0)->bdev ) *__mptr = ( bo->bdev); (typeof(*i915) *)( (char *)__mptr - __builtin_offsetof (typeof(*i915), bdev) );}); | ||||
| 180 | struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); | ||||
| 181 | struct i915_request *rq; | ||||
| 182 | struct ttm_tt *src_ttm = bo->ttm; | ||||
| 183 | enum i915_cache_level src_level, dst_level; | ||||
| 184 | int ret; | ||||
| 185 | |||||
| 186 | if (!to_gt(i915)->migrate.context || intel_gt_is_wedged(to_gt(i915))) | ||||
| 187 | return ERR_PTR(-EINVAL22); | ||||
| 188 | |||||
| 189 | /* With fail_gpu_migration, we always perform a GPU clear. */ | ||||
| 190 | if (I915_SELFTEST_ONLY(fail_gpu_migration)0) | ||||
| 191 | clear = true1; | ||||
| 192 | |||||
| 193 | dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm); | ||||
| 194 | if (clear) { | ||||
| 195 | if (bo->type == ttm_bo_type_kernel && | ||||
| 196 | !I915_SELFTEST_ONLY(fail_gpu_migration)0) | ||||
| 197 | return ERR_PTR(-EINVAL22); | ||||
| 198 | |||||
| 199 | intel_engine_pm_get(to_gt(i915)->migrate.context->engine); | ||||
| 200 | ret = intel_context_migrate_clear(to_gt(i915)->migrate.context, deps, | ||||
| 201 | dst_st->sgl, dst_level, | ||||
| 202 | i915_ttm_gtt_binds_lmem(dst_mem), | ||||
| 203 | 0, &rq); | ||||
| 204 | } else { | ||||
| 205 | struct i915_refct_sgt *src_rsgt = | ||||
| 206 | i915_ttm_resource_get_st(obj, bo->resource); | ||||
| 207 | |||||
| 208 | if (IS_ERR(src_rsgt)) | ||||
| 209 | return ERR_CAST(src_rsgt); | ||||
| 210 | |||||
| 211 | src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm); | ||||
| 212 | intel_engine_pm_get(to_gt(i915)->migrate.context->engine); | ||||
| 213 | ret = intel_context_migrate_copy(to_gt(i915)->migrate.context, | ||||
| 214 | deps, src_rsgt->table.sgl, | ||||
| 215 | src_level, | ||||
| 216 | i915_ttm_gtt_binds_lmem(bo->resource), | ||||
| 217 | dst_st->sgl, dst_level, | ||||
| 218 | i915_ttm_gtt_binds_lmem(dst_mem), | ||||
| 219 | &rq); | ||||
| 220 | |||||
| 221 | i915_refct_sgt_put(src_rsgt); | ||||
| 222 | } | ||||
| 223 | |||||
| 224 | intel_engine_pm_put(to_gt(i915)->migrate.context->engine); | ||||
| 225 | |||||
| 226 | if (ret && rq) { | ||||
| 227 | i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT(0x7fffffff)); | ||||
| 228 | i915_request_put(rq); | ||||
| 229 | } | ||||
| 230 | |||||
| 231 | return ret ? ERR_PTR(ret) : &rq->fence; | ||||
| 232 | } | ||||
| 233 | |||||
| 234 | /** | ||||
| 235 | * struct i915_ttm_memcpy_arg - argument for the bo memcpy functionality. | ||||
| 236 | * @_dst_iter: Storage space for the destination kmap iterator. | ||||
| 237 | * @_src_iter: Storage space for the source kmap iterator. | ||||
| 238 | * @dst_iter: Pointer to the destination kmap iterator. | ||||
| 239 | * @src_iter: Pointer to the source kmap iterator. | ||||
| 240 | * @clear: Whether to clear instead of copy. | ||||
| 241 | * @src_rsgt: Refcounted scatter-gather list of source memory. | ||||
| 242 | * @dst_rsgt: Refcounted scatter-gather list of destination memory. | ||||
| 243 | */ | ||||
| 244 | struct i915_ttm_memcpy_arg { | ||||
| 245 | union { | ||||
| 246 | struct ttm_kmap_iter_tt tt; | ||||
| 247 | struct ttm_kmap_iter_iomap io; | ||||
| 248 | } _dst_iter, | ||||
| 249 | _src_iter; | ||||
| 250 | struct ttm_kmap_iter *dst_iter; | ||||
| 251 | struct ttm_kmap_iter *src_iter; | ||||
| 252 | unsigned long num_pages; | ||||
| 253 | bool_Bool clear; | ||||
| 254 | struct i915_refct_sgt *src_rsgt; | ||||
| 255 | struct i915_refct_sgt *dst_rsgt; | ||||
| 256 | }; | ||||
| 257 | |||||
| 258 | /** | ||||
| 259 | * struct i915_ttm_memcpy_work - Async memcpy worker under a dma-fence. | ||||
| 260 | * @fence: The dma-fence. | ||||
| 261 | * @work: The work struct use for the memcpy work. | ||||
| 262 | * @lock: The fence lock. Not used to protect anything else ATM. | ||||
| 263 | * @irq_work: Low latency worker to signal the fence since it can't be done | ||||
| 264 | * from the callback for lockdep reasons. | ||||
| 265 | * @cb: Callback for the accelerated migration fence. | ||||
| 266 | * @arg: The argument for the memcpy functionality. | ||||
| 267 | * @i915: The i915 pointer. | ||||
| 268 | * @obj: The GEM object. | ||||
| 269 | * @memcpy_allowed: Instead of processing the @arg, and falling back to memcpy | ||||
| 270 | * or memset, we wedge the device and set the @obj unknown_state, to prevent | ||||
| 271 | * further access to the object with the CPU or GPU. On some devices we might | ||||
| 272 | * only be permitted to use the blitter engine for such operations. | ||||
| 273 | */ | ||||
| 274 | struct i915_ttm_memcpy_work { | ||||
| 275 | struct dma_fence fence; | ||||
| 276 | struct work_struct work; | ||||
| 277 | spinlock_t lock; | ||||
| 278 | struct irq_work irq_work; | ||||
| 279 | struct dma_fence_cb cb; | ||||
| 280 | struct i915_ttm_memcpy_arg arg; | ||||
| 281 | struct drm_i915_privateinteldrm_softc *i915; | ||||
| 282 | struct drm_i915_gem_object *obj; | ||||
| 283 | bool_Bool memcpy_allowed; | ||||
| 284 | }; | ||||
| 285 | |||||
| 286 | static void i915_ttm_move_memcpy(struct i915_ttm_memcpy_arg *arg) | ||||
| 287 | { | ||||
| 288 | STUB()do { printf("%s: stub\n", __func__); } while(0); | ||||
| 289 | #ifdef notyet | ||||
| 290 | ttm_move_memcpy(arg->clear, arg->num_pages, | ||||
| 291 | arg->dst_iter, arg->src_iter); | ||||
| 292 | #endif | ||||
| 293 | } | ||||
| 294 | |||||
| 295 | static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg *arg, | ||||
| 296 | struct ttm_buffer_object *bo, bool_Bool clear, | ||||
| 297 | struct ttm_resource *dst_mem, | ||||
| 298 | struct ttm_tt *dst_ttm, | ||||
| 299 | struct i915_refct_sgt *dst_rsgt) | ||||
| 300 | { | ||||
| 301 | STUB()do { printf("%s: stub\n", __func__); } while(0); | ||||
| 302 | #ifdef notyet | ||||
| 303 | struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); | ||||
| 304 | struct intel_memory_region *dst_reg, *src_reg; | ||||
| 305 | |||||
| 306 | dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type); | ||||
| 307 | src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type); | ||||
| 308 | GEM_BUG_ON(!dst_reg || !src_reg)((void)0); | ||||
| 309 | |||||
| 310 | arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ? | ||||
| 311 | ttm_kmap_iter_tt_init(&arg->_dst_iter.tt, dst_ttm) : | ||||
| 312 | ttm_kmap_iter_iomap_init(&arg->_dst_iter.io, &dst_reg->iomap, | ||||
| 313 | &dst_rsgt->table, dst_reg->region.start); | ||||
| 314 | |||||
| 315 | arg->src_iter = !i915_ttm_cpu_maps_iomem(bo->resource) ? | ||||
| 316 | ttm_kmap_iter_tt_init(&arg->_src_iter.tt, bo->ttm) : | ||||
| 317 | ttm_kmap_iter_iomap_init(&arg->_src_iter.io, &src_reg->iomap, | ||||
| 318 | &obj->ttm.cached_io_rsgt->table, | ||||
| 319 | src_reg->region.start); | ||||
| 320 | arg->clear = clear; | ||||
| 321 | arg->num_pages = bo->base.size >> PAGE_SHIFT12; | ||||
| 322 | |||||
| 323 | arg->dst_rsgt = i915_refct_sgt_get(dst_rsgt); | ||||
| 324 | arg->src_rsgt = clear ? NULL((void *)0) : | ||||
| 325 | i915_ttm_resource_get_st(obj, bo->resource); | ||||
| 326 | #endif | ||||
| 327 | } | ||||
| 328 | |||||
| 329 | static void i915_ttm_memcpy_release(struct i915_ttm_memcpy_arg *arg) | ||||
| 330 | { | ||||
| 331 | i915_refct_sgt_put(arg->src_rsgt); | ||||
| 332 | i915_refct_sgt_put(arg->dst_rsgt); | ||||
| 333 | } | ||||
| 334 | |||||
| 335 | static void __memcpy_work(struct work_struct *work) | ||||
| 336 | { | ||||
| 337 | struct i915_ttm_memcpy_work *copy_work = | ||||
| 338 | container_of(work, typeof(*copy_work), work)({ const __typeof( ((typeof(*copy_work) *)0)->work ) *__mptr = (work); (typeof(*copy_work) *)( (char *)__mptr - __builtin_offsetof (typeof(*copy_work), work) );}); | ||||
| 339 | struct i915_ttm_memcpy_arg *arg = ©_work->arg; | ||||
| 340 | bool_Bool cookie; | ||||
| 341 | |||||
| 342 | /* | ||||
| 343 | * FIXME: We need to take a closer look here. We should be able to plonk | ||||
| 344 | * this into the fence critical section. | ||||
| 345 | */ | ||||
| 346 | if (!copy_work->memcpy_allowed) { | ||||
| 347 | struct intel_gt *gt; | ||||
| 348 | unsigned int id; | ||||
| 349 | |||||
| 350 | for_each_gt(gt, copy_work->i915, id)for ((id) = 0; (id) < 4; (id)++) if (!(((gt) = (copy_work-> i915)->gt[(id)]))) {} else | ||||
| 351 | intel_gt_set_wedged(gt); | ||||
| 352 | } | ||||
| 353 | |||||
| 354 | cookie = dma_fence_begin_signalling(); | ||||
| 355 | |||||
| 356 | if (copy_work->memcpy_allowed) { | ||||
| 357 | i915_ttm_move_memcpy(arg); | ||||
| 358 | } else { | ||||
| 359 | /* | ||||
| 360 | * Prevent further use of the object. Any future GTT binding or | ||||
| 361 | * CPU access is not allowed once we signal the fence. Outside | ||||
| 362 | * of the fence critical section, we then also then wedge the gpu | ||||
| 363 | * to indicate the device is not functional. | ||||
| 364 | * | ||||
| 365 | * The below dma_fence_signal() is our write-memory-barrier. | ||||
| 366 | */ | ||||
| 367 | copy_work->obj->mm.unknown_state = true1; | ||||
| 368 | } | ||||
| 369 | |||||
| 370 | dma_fence_end_signalling(cookie); | ||||
| 371 | |||||
| 372 | dma_fence_signal(©_work->fence); | ||||
| 373 | |||||
| 374 | i915_ttm_memcpy_release(arg); | ||||
| 375 | i915_gem_object_put(copy_work->obj); | ||||
| 376 | dma_fence_put(©_work->fence); | ||||
| 377 | } | ||||
| 378 | |||||
| 379 | static void __memcpy_irq_work(struct irq_work *irq_work) | ||||
| 380 | { | ||||
| 381 | struct i915_ttm_memcpy_work *copy_work = | ||||
| 382 | container_of(irq_work, typeof(*copy_work), irq_work)({ const __typeof( ((typeof(*copy_work) *)0)->irq_work ) * __mptr = (irq_work); (typeof(*copy_work) *)( (char *)__mptr - __builtin_offsetof(typeof(*copy_work), irq_work) );}); | ||||
| 383 | struct i915_ttm_memcpy_arg *arg = ©_work->arg; | ||||
| 384 | |||||
| 385 | dma_fence_signal(©_work->fence); | ||||
| 386 | i915_ttm_memcpy_release(arg); | ||||
| 387 | i915_gem_object_put(copy_work->obj); | ||||
| 388 | dma_fence_put(©_work->fence); | ||||
| 389 | } | ||||
| 390 | |||||
| 391 | static void __memcpy_cb(struct dma_fence *fence, struct dma_fence_cb *cb) | ||||
| 392 | { | ||||
| 393 | struct i915_ttm_memcpy_work *copy_work = | ||||
| 394 | container_of(cb, typeof(*copy_work), cb)({ const __typeof( ((typeof(*copy_work) *)0)->cb ) *__mptr = (cb); (typeof(*copy_work) *)( (char *)__mptr - __builtin_offsetof (typeof(*copy_work), cb) );}); | ||||
| 395 | |||||
| 396 | if (unlikely(fence->error || I915_SELFTEST_ONLY(fail_gpu_migration))__builtin_expect(!!(fence->error || 0), 0)) { | ||||
| 397 | INIT_WORK(©_work->work, __memcpy_work); | ||||
| 398 | queue_work(system_unbound_wq, ©_work->work); | ||||
| 399 | } else { | ||||
| 400 | init_irq_work(©_work->irq_work, __memcpy_irq_work); | ||||
| 401 | irq_work_queue(©_work->irq_work); | ||||
| 402 | } | ||||
| 403 | } | ||||
| 404 | |||||
| 405 | static const char *get_driver_name(struct dma_fence *fence) | ||||
| 406 | { | ||||
| 407 | return "i915_ttm_memcpy_work"; | ||||
| 408 | } | ||||
| 409 | |||||
| 410 | static const char *get_timeline_name(struct dma_fence *fence) | ||||
| 411 | { | ||||
| 412 | return "unbound"; | ||||
| 413 | } | ||||
| 414 | |||||
| 415 | static const struct dma_fence_ops dma_fence_memcpy_ops = { | ||||
| 416 | .get_driver_name = get_driver_name, | ||||
| 417 | .get_timeline_name = get_timeline_name, | ||||
| 418 | }; | ||||
| 419 | |||||
| 420 | static struct dma_fence * | ||||
| 421 | i915_ttm_memcpy_work_arm(struct i915_ttm_memcpy_work *work, | ||||
| 422 | struct dma_fence *dep) | ||||
| 423 | { | ||||
| 424 | int ret; | ||||
| 425 | |||||
| 426 | mtx_init(&work->lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&work-> lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9) ? 0x9 : ((0x9)))); } while (0); | ||||
| 427 | dma_fence_init(&work->fence, &dma_fence_memcpy_ops, &work->lock, 0, 0); | ||||
| 428 | dma_fence_get(&work->fence); | ||||
| 429 | ret = dma_fence_add_callback(dep, &work->cb, __memcpy_cb); | ||||
| 430 | if (ret) { | ||||
| 431 | if (ret != -ENOENT2) | ||||
| 432 | dma_fence_wait(dep, false0); | ||||
| 433 | |||||
| 434 | return ERR_PTR(I915_SELFTEST_ONLY(fail_gpu_migration)0 ? -EINVAL22 : | ||||
| 435 | dep->error); | ||||
| 436 | } | ||||
| 437 | |||||
| 438 | return &work->fence; | ||||
| 439 | } | ||||
| 440 | |||||
| 441 | static bool_Bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo, | ||||
| 442 | struct ttm_resource *dst_mem) | ||||
| 443 | { | ||||
| 444 | if (i915_gem_object_needs_ccs_pages(i915_ttm_to_gem(bo))) | ||||
| 445 | return false0; | ||||
| 446 | |||||
| 447 | if (!(i915_ttm_resource_mappable(bo->resource) && | ||||
| 448 | i915_ttm_resource_mappable(dst_mem))) | ||||
| 449 | return false0; | ||||
| 450 | |||||
| 451 | return I915_SELFTEST_ONLY(ban_memcpy)0 ? false0 : true1; | ||||
| 452 | } | ||||
| 453 | |||||
| 454 | static struct dma_fence * | ||||
| 455 | __i915_ttm_move(struct ttm_buffer_object *bo, | ||||
| 456 | const struct ttm_operation_ctx *ctx, bool_Bool clear, | ||||
| 457 | struct ttm_resource *dst_mem, struct ttm_tt *dst_ttm, | ||||
| 458 | struct i915_refct_sgt *dst_rsgt, bool_Bool allow_accel, | ||||
| 459 | const struct i915_deps *move_deps) | ||||
| 460 | { | ||||
| 461 | const bool_Bool memcpy_allowed = i915_ttm_memcpy_allowed(bo, dst_mem); | ||||
| 462 | struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); | ||||
| 463 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(bo->base.dev); | ||||
| 464 | struct i915_ttm_memcpy_work *copy_work = NULL((void *)0); | ||||
| 465 | struct i915_ttm_memcpy_arg _arg, *arg = &_arg; | ||||
| 466 | struct dma_fence *fence = ERR_PTR(-EINVAL22); | ||||
| 467 | |||||
| 468 | if (allow_accel
| ||||
| 469 | fence = i915_ttm_accel_move(bo, clear, dst_mem, dst_ttm, | ||||
| 470 | &dst_rsgt->table, move_deps); | ||||
| 471 | |||||
| 472 | /* | ||||
| 473 | * We only need to intercept the error when moving to lmem. | ||||
| 474 | * When moving to system, TTM or shmem will provide us with | ||||
| 475 | * cleared pages. | ||||
| 476 | */ | ||||
| 477 | if (!IS_ERR(fence) && !i915_ttm_gtt_binds_lmem(dst_mem) && | ||||
| 478 | !I915_SELFTEST_ONLY(fail_gpu_migration ||0 | ||||
| 479 | fail_work_allocation)0) | ||||
| 480 | goto out; | ||||
| 481 | } | ||||
| 482 | |||||
| 483 | /* If we've scheduled gpu migration. Try to arm error intercept. */ | ||||
| 484 | if (!IS_ERR(fence)) { | ||||
| 485 | struct dma_fence *dep = fence; | ||||
| 486 | |||||
| 487 | if (!I915_SELFTEST_ONLY(fail_work_allocation)0) | ||||
| 488 | copy_work = kzalloc(sizeof(*copy_work), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 489 | |||||
| 490 | if (copy_work) { | ||||
| 491 | copy_work->i915 = i915; | ||||
| 492 | copy_work->memcpy_allowed = memcpy_allowed; | ||||
| 493 | copy_work->obj = i915_gem_object_get(obj); | ||||
| 494 | arg = ©_work->arg; | ||||
| 495 | if (memcpy_allowed) | ||||
| 496 | i915_ttm_memcpy_init(arg, bo, clear, dst_mem, | ||||
| 497 | dst_ttm, dst_rsgt); | ||||
| 498 | |||||
| 499 | fence = i915_ttm_memcpy_work_arm(copy_work, dep); | ||||
| 500 | } else { | ||||
| 501 | dma_fence_wait(dep, false0); | ||||
| 502 | fence = ERR_PTR(I915_SELFTEST_ONLY(fail_gpu_migration)0 ? | ||||
| 503 | -EINVAL22 : fence->error); | ||||
| 504 | } | ||||
| 505 | dma_fence_put(dep); | ||||
| 506 | |||||
| 507 | if (!IS_ERR(fence)) | ||||
| 508 | goto out; | ||||
| 509 | } else { | ||||
| 510 | int err = PTR_ERR(fence); | ||||
| 511 | |||||
| 512 | if (err == -EINTR4 || err == -ERESTARTSYS4 || err == -EAGAIN35) | ||||
| 513 | return fence; | ||||
| 514 | |||||
| 515 | if (move_deps) { | ||||
| 516 | err = i915_deps_sync(move_deps, ctx); | ||||
| 517 | if (err) | ||||
| 518 | return ERR_PTR(err); | ||||
| 519 | } | ||||
| 520 | } | ||||
| 521 | |||||
| 522 | /* Error intercept failed or no accelerated migration to start with */ | ||||
| 523 | |||||
| 524 | if (memcpy_allowed) { | ||||
| 525 | if (!copy_work) | ||||
| 526 | i915_ttm_memcpy_init(arg, bo, clear, dst_mem, dst_ttm, | ||||
| 527 | dst_rsgt); | ||||
| 528 | i915_ttm_move_memcpy(arg); | ||||
| 529 | i915_ttm_memcpy_release(arg); | ||||
| 530 | } | ||||
| 531 | if (copy_work) | ||||
| 532 | i915_gem_object_put(copy_work->obj); | ||||
| 533 | kfree(copy_work); | ||||
| 534 | |||||
| 535 | return memcpy_allowed ? NULL((void *)0) : ERR_PTR(-EIO5); | ||||
| 536 | out: | ||||
| 537 | if (!fence && copy_work) { | ||||
| 538 | i915_ttm_memcpy_release(arg); | ||||
| 539 | i915_gem_object_put(copy_work->obj); | ||||
| 540 | kfree(copy_work); | ||||
| 541 | } | ||||
| 542 | |||||
| 543 | return fence; | ||||
| 544 | } | ||||
| 545 | |||||
| 546 | /** | ||||
| 547 | * i915_ttm_move - The TTM move callback used by i915. | ||||
| 548 | * @bo: The buffer object. | ||||
| 549 | * @evict: Whether this is an eviction. | ||||
| 550 | * @dst_mem: The destination ttm resource. | ||||
| 551 | * @hop: If we need multihop, what temporary memory type to move to. | ||||
| 552 | * | ||||
| 553 | * Return: 0 if successful, negative error code otherwise. | ||||
| 554 | */ | ||||
| 555 | int i915_ttm_move(struct ttm_buffer_object *bo, bool_Bool evict, | ||||
| 556 | struct ttm_operation_ctx *ctx, | ||||
| 557 | struct ttm_resource *dst_mem, | ||||
| 558 | struct ttm_place *hop) | ||||
| 559 | { | ||||
| 560 | struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); | ||||
| 561 | struct ttm_resource_manager *dst_man = | ||||
| 562 | ttm_manager_type(bo->bdev, dst_mem->mem_type); | ||||
| 563 | struct dma_fence *migration_fence = NULL((void *)0); | ||||
| 564 | struct ttm_tt *ttm = bo->ttm; | ||||
| |||||
| 565 | struct i915_refct_sgt *dst_rsgt; | ||||
| 566 | bool_Bool clear; | ||||
| 567 | int ret; | ||||
| 568 | |||||
| 569 | if (GEM_WARN_ON(i915_ttm_is_ghost_object(bo))({ __builtin_expect(!!(!!(i915_ttm_is_ghost_object(bo))), 0); })) { | ||||
| 570 | ttm_bo_move_null(bo, dst_mem); | ||||
| 571 | return 0; | ||||
| 572 | } | ||||
| 573 | |||||
| 574 | ret = i915_ttm_move_notify(bo); | ||||
| 575 | if (ret
| ||||
| 576 | return ret; | ||||
| 577 | |||||
| 578 | if (obj->mm.madv != I915_MADV_WILLNEED0) { | ||||
| 579 | i915_ttm_purge(obj); | ||||
| 580 | ttm_resource_free(bo, &dst_mem); | ||||
| 581 | return 0; | ||||
| 582 | } | ||||
| 583 | |||||
| 584 | /* Populate ttm with pages if needed. Typically system memory. */ | ||||
| 585 | if (ttm && (dst_man->use_tt || (ttm->page_flags & TTM_TT_FLAG_SWAPPED(1 << 0)))) { | ||||
| 586 | ret = ttm_tt_populate(bo->bdev, ttm, ctx); | ||||
| 587 | if (ret) | ||||
| 588 | return ret; | ||||
| 589 | } | ||||
| 590 | |||||
| 591 | dst_rsgt = i915_ttm_resource_get_st(obj, dst_mem); | ||||
| 592 | if (IS_ERR(dst_rsgt)) | ||||
| 593 | return PTR_ERR(dst_rsgt); | ||||
| 594 | |||||
| 595 | clear = !i915_ttm_cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm)); | ||||
| 596 | if (!(clear
| ||||
| 597 | struct i915_deps deps; | ||||
| 598 | |||||
| 599 | i915_deps_init(&deps, GFP_KERNEL(0x0001 | 0x0004) | __GFP_NORETRY0 | __GFP_NOWARN0); | ||||
| 600 | ret = i915_deps_add_resv(&deps, bo->base.resv, ctx); | ||||
| 601 | if (ret) { | ||||
| 602 | i915_refct_sgt_put(dst_rsgt); | ||||
| 603 | return ret; | ||||
| 604 | } | ||||
| 605 | |||||
| 606 | migration_fence = __i915_ttm_move(bo, ctx, clear, dst_mem, ttm, | ||||
| 607 | dst_rsgt, true1, &deps); | ||||
| 608 | i915_deps_fini(&deps); | ||||
| 609 | } | ||||
| 610 | |||||
| 611 | /* We can possibly get an -ERESTARTSYS here */ | ||||
| 612 | if (IS_ERR(migration_fence)) { | ||||
| 613 | i915_refct_sgt_put(dst_rsgt); | ||||
| 614 | return PTR_ERR(migration_fence); | ||||
| 615 | } | ||||
| 616 | |||||
| 617 | if (migration_fence) { | ||||
| 618 | if (I915_SELFTEST_ONLY(evict && fail_gpu_migration)0) | ||||
| 619 | ret = -EIO5; /* never feed non-migrate fences into ttm */ | ||||
| 620 | else | ||||
| 621 | ret = ttm_bo_move_accel_cleanup(bo, migration_fence, evict, | ||||
| 622 | true1, dst_mem); | ||||
| 623 | if (ret) { | ||||
| 624 | dma_fence_wait(migration_fence, false0); | ||||
| 625 | ttm_bo_move_sync_cleanup(bo, dst_mem); | ||||
| 626 | } | ||||
| 627 | dma_fence_put(migration_fence); | ||||
| 628 | } else { | ||||
| 629 | ttm_bo_move_sync_cleanup(bo, dst_mem); | ||||
| 630 | } | ||||
| 631 | |||||
| 632 | i915_ttm_adjust_domains_after_move(obj); | ||||
| 633 | i915_ttm_free_cached_io_rsgt(obj); | ||||
| 634 | |||||
| 635 | if (i915_ttm_gtt_binds_lmem(dst_mem) || i915_ttm_cpu_maps_iomem(dst_mem)) { | ||||
| 636 | obj->ttm.cached_io_rsgt = dst_rsgt; | ||||
| 637 | obj->ttm.get_io_page.sg_pos = dst_rsgt->table.sgl; | ||||
| 638 | obj->ttm.get_io_page.sg_idx = 0; | ||||
| 639 | } else { | ||||
| 640 | i915_refct_sgt_put(dst_rsgt); | ||||
| 641 | } | ||||
| 642 | |||||
| 643 | i915_ttm_adjust_lru(obj); | ||||
| 644 | i915_ttm_adjust_gem_after_move(obj); | ||||
| 645 | return 0; | ||||
| 646 | } | ||||
| 647 | |||||
| 648 | /** | ||||
| 649 | * i915_gem_obj_copy_ttm - Copy the contents of one ttm-based gem object to | ||||
| 650 | * another | ||||
| 651 | * @dst: The destination object | ||||
| 652 | * @src: The source object | ||||
| 653 | * @allow_accel: Allow using the blitter. Otherwise TTM memcpy is used. | ||||
| 654 | * @intr: Whether to perform waits interruptible: | ||||
| 655 | * | ||||
| 656 | * Note: The caller is responsible for assuring that the underlying | ||||
| 657 | * TTM objects are populated if needed and locked. | ||||
| 658 | * | ||||
| 659 | * Return: Zero on success. Negative error code on error. If @intr == true, | ||||
| 660 | * then it may return -ERESTARTSYS or -EINTR. | ||||
| 661 | */ | ||||
| 662 | int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst, | ||||
| 663 | struct drm_i915_gem_object *src, | ||||
| 664 | bool_Bool allow_accel, bool_Bool intr) | ||||
| 665 | { | ||||
| 666 | struct ttm_buffer_object *dst_bo = i915_gem_to_ttm(dst); | ||||
| 667 | struct ttm_buffer_object *src_bo = i915_gem_to_ttm(src); | ||||
| 668 | struct ttm_operation_ctx ctx = { | ||||
| 669 | .interruptible = intr, | ||||
| 670 | }; | ||||
| 671 | struct i915_refct_sgt *dst_rsgt; | ||||
| 672 | struct dma_fence *copy_fence; | ||||
| 673 | struct i915_deps deps; | ||||
| 674 | int ret; | ||||
| 675 | |||||
| 676 | assert_object_held(dst)do { (void)(&((dst)->base.resv)->lock.base); } while (0); | ||||
| 677 | assert_object_held(src)do { (void)(&((src)->base.resv)->lock.base); } while (0); | ||||
| 678 | i915_deps_init(&deps, GFP_KERNEL(0x0001 | 0x0004) | __GFP_NORETRY0 | __GFP_NOWARN0); | ||||
| 679 | |||||
| 680 | ret = dma_resv_reserve_fences(src_bo->base.resv, 1); | ||||
| 681 | if (ret) | ||||
| 682 | return ret; | ||||
| 683 | |||||
| 684 | ret = dma_resv_reserve_fences(dst_bo->base.resv, 1); | ||||
| 685 | if (ret) | ||||
| 686 | return ret; | ||||
| 687 | |||||
| 688 | ret = i915_deps_add_resv(&deps, dst_bo->base.resv, &ctx); | ||||
| 689 | if (ret) | ||||
| 690 | return ret; | ||||
| 691 | |||||
| 692 | ret = i915_deps_add_resv(&deps, src_bo->base.resv, &ctx); | ||||
| 693 | if (ret) | ||||
| 694 | return ret; | ||||
| 695 | |||||
| 696 | dst_rsgt = i915_ttm_resource_get_st(dst, dst_bo->resource); | ||||
| 697 | copy_fence = __i915_ttm_move(src_bo, &ctx, false0, dst_bo->resource, | ||||
| 698 | dst_bo->ttm, dst_rsgt, allow_accel, | ||||
| 699 | &deps); | ||||
| 700 | |||||
| 701 | i915_deps_fini(&deps); | ||||
| 702 | i915_refct_sgt_put(dst_rsgt); | ||||
| 703 | if (IS_ERR_OR_NULL(copy_fence)) | ||||
| 704 | return PTR_ERR_OR_ZERO(copy_fence); | ||||
| 705 | |||||
| 706 | dma_resv_add_fence(dst_bo->base.resv, copy_fence, DMA_RESV_USAGE_WRITE); | ||||
| 707 | dma_resv_add_fence(src_bo->base.resv, copy_fence, DMA_RESV_USAGE_READ); | ||||
| 708 | dma_fence_put(copy_fence); | ||||
| 709 | |||||
| 710 | return 0; | ||||
| 711 | } |
| 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
| 3 | /* |
| 4 | * |
| 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
| 33 | #include <uapi/drm/i915_drm.h> |
| 34 | |
| 35 | #include <linux/pm_qos.h> |
| 36 | |
| 37 | #include <drm/ttm/ttm_device.h> |
| 38 | |
| 39 | #include "vga.h" |
| 40 | |
| 41 | struct inteldrm_softc; |
| 42 | #define drm_i915_privateinteldrm_softc inteldrm_softc |
| 43 | |
| 44 | #include "display/intel_display.h" |
| 45 | #include "display/intel_display_core.h" |
| 46 | |
| 47 | #include "gem/i915_gem_context_types.h" |
| 48 | #include "gem/i915_gem_lmem.h" |
| 49 | #include "gem/i915_gem_shrinker.h" |
| 50 | #include "gem/i915_gem_stolen.h" |
| 51 | |
| 52 | #include "gt/intel_engine.h" |
| 53 | #include "gt/intel_gt_types.h" |
| 54 | #include "gt/intel_region_lmem.h" |
| 55 | #include "gt/intel_workarounds.h" |
| 56 | #include "gt/uc/intel_uc.h" |
| 57 | |
| 58 | #include "i915_drm_client.h" |
| 59 | #include "i915_gem.h" |
| 60 | #include "i915_gpu_error.h" |
| 61 | #include "i915_params.h" |
| 62 | #include "i915_perf_types.h" |
| 63 | #include "i915_scheduler.h" |
| 64 | #include "i915_utils.h" |
| 65 | #include "intel_device_info.h" |
| 66 | #include "intel_memory_region.h" |
| 67 | #include "intel_pch.h" |
| 68 | #include "intel_runtime_pm.h" |
| 69 | #include "intel_step.h" |
| 70 | #include "intel_uncore.h" |
| 71 | #include "intel_wopcm.h" |
| 72 | |
| 73 | struct drm_i915_clock_gating_funcs; |
| 74 | struct drm_i915_gem_object; |
| 75 | struct drm_i915_privateinteldrm_softc; |
| 76 | struct intel_connector; |
| 77 | struct intel_dp; |
| 78 | struct intel_encoder; |
| 79 | struct intel_limit; |
| 80 | struct intel_overlay_error_state; |
| 81 | struct vlv_s0ix_state; |
| 82 | |
| 83 | #include "drm.h" |
| 84 | #include "vga.h" |
| 85 | |
| 86 | #include <dev/ic/mc6845reg.h> |
| 87 | #include <dev/ic/pcdisplayvar.h> |
| 88 | #include <dev/ic/vgareg.h> |
| 89 | #include <dev/ic/vgavar.h> |
| 90 | |
| 91 | #include <sys/task.h> |
| 92 | #include <dev/pci/vga_pcivar.h> |
| 93 | #include <dev/wscons/wsconsio.h> |
| 94 | #include <dev/wscons/wsdisplayvar.h> |
| 95 | #include <dev/rasops/rasops.h> |
| 96 | |
| 97 | /* Threshold == 5 for long IRQs, 50 for short */ |
| 98 | #define HPD_STORM_DEFAULT_THRESHOLD50 50 |
| 99 | |
| 100 | #define I915_GEM_GPU_DOMAINS(0x00000002 | 0x00000004 | 0x00000008 | 0x00000010 | 0x00000020 ) \ |
| 101 | (I915_GEM_DOMAIN_RENDER0x00000002 | \ |
| 102 | I915_GEM_DOMAIN_SAMPLER0x00000004 | \ |
| 103 | I915_GEM_DOMAIN_COMMAND0x00000008 | \ |
| 104 | I915_GEM_DOMAIN_INSTRUCTION0x00000010 | \ |
| 105 | I915_GEM_DOMAIN_VERTEX0x00000020) |
| 106 | |
| 107 | #define I915_COLOR_UNEVICTABLE(-1) (-1) /* a non-vma sharing the address space */ |
| 108 | |
| 109 | #define GEM_QUIRK_PIN_SWIZZLED_PAGES(1UL << (0)) BIT(0)(1UL << (0)) |
| 110 | |
| 111 | struct i915_suspend_saved_registers { |
| 112 | u32 saveDSPARB; |
| 113 | u32 saveSWF0[16]; |
| 114 | u32 saveSWF1[16]; |
| 115 | u32 saveSWF3[3]; |
| 116 | u16 saveGCDGMBUS; |
| 117 | }; |
| 118 | |
| 119 | #define MAX_L3_SLICES2 2 |
| 120 | struct intel_l3_parity { |
| 121 | u32 *remap_info[MAX_L3_SLICES2]; |
| 122 | struct work_struct error_work; |
| 123 | int which_slice; |
| 124 | }; |
| 125 | |
| 126 | struct i915_gem_mm { |
| 127 | /* |
| 128 | * Shortcut for the stolen region. This points to either |
| 129 | * INTEL_REGION_STOLEN_SMEM for integrated platforms, or |
| 130 | * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't |
| 131 | * support stolen. |
| 132 | */ |
| 133 | struct intel_memory_region *stolen_region; |
| 134 | /** Memory allocator for GTT stolen memory */ |
| 135 | struct drm_mm stolen; |
| 136 | /** Protects the usage of the GTT stolen memory allocator. This is |
| 137 | * always the inner lock when overlapping with struct_mutex. */ |
| 138 | struct rwlock stolen_lock; |
| 139 | |
| 140 | /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ |
| 141 | spinlock_t obj_lock; |
| 142 | |
| 143 | /** |
| 144 | * List of objects which are purgeable. |
| 145 | */ |
| 146 | struct list_head purge_list; |
| 147 | |
| 148 | /** |
| 149 | * List of objects which have allocated pages and are shrinkable. |
| 150 | */ |
| 151 | struct list_head shrink_list; |
| 152 | |
| 153 | /** |
| 154 | * List of objects which are pending destruction. |
| 155 | */ |
| 156 | struct llist_head free_list; |
| 157 | struct work_struct free_work; |
| 158 | /** |
| 159 | * Count of objects pending destructions. Used to skip needlessly |
| 160 | * waiting on an RCU barrier if no objects are waiting to be freed. |
| 161 | */ |
| 162 | atomic_t free_count; |
| 163 | |
| 164 | /** |
| 165 | * tmpfs instance used for shmem backed objects |
| 166 | */ |
| 167 | struct vfsmount *gemfs; |
| 168 | |
| 169 | struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; |
| 170 | |
| 171 | struct notifier_block oom_notifier; |
| 172 | struct notifier_block vmap_notifier; |
| 173 | struct shrinker shrinker; |
| 174 | |
| 175 | #ifdef CONFIG_MMU_NOTIFIER |
| 176 | /** |
| 177 | * notifier_lock for mmu notifiers, memory may not be allocated |
| 178 | * while holding this lock. |
| 179 | */ |
| 180 | rwlock_t notifier_lock; |
| 181 | #endif |
| 182 | |
| 183 | /* shrinker accounting, also useful for userland debugging */ |
| 184 | u64 shrink_memory; |
| 185 | u32 shrink_count; |
| 186 | }; |
| 187 | |
| 188 | #define I915_IDLE_ENGINES_TIMEOUT(200) (200) /* in ms */ |
| 189 | |
| 190 | unsigned long i915_fence_context_timeout(const struct drm_i915_privateinteldrm_softc *i915, |
| 191 | u64 context); |
| 192 | |
| 193 | static inline unsigned long |
| 194 | i915_fence_timeout(const struct drm_i915_privateinteldrm_softc *i915) |
| 195 | { |
| 196 | return i915_fence_context_timeout(i915, U64_MAX0xffffffffffffffffULL); |
| 197 | } |
| 198 | |
| 199 | #define HAS_HW_SAGV_WM(i915)(((&(i915)->__runtime)->display.ip.ver) >= 13 && !((&(i915)->__info)->is_dgfx)) (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 13 && !IS_DGFX(i915)((&(i915)->__info)->is_dgfx)) |
| 200 | |
| 201 | struct i915_virtual_gpu { |
| 202 | struct rwlock lock; /* serialises sending of g2v_notify command pkts */ |
| 203 | bool_Bool active; |
| 204 | u32 caps; |
| 205 | u32 *initial_mmio; |
| 206 | u8 *initial_cfg_space; |
| 207 | struct list_head entry; |
| 208 | }; |
| 209 | |
| 210 | struct i915_selftest_stash { |
| 211 | atomic_t counter; |
| 212 | struct ida mock_region_instances; |
| 213 | }; |
| 214 | |
| 215 | |
| 216 | struct inteldrm_softc { |
| 217 | #ifdef __OpenBSD__1 |
| 218 | struct device sc_dev; |
| 219 | bus_dma_tag_t dmat; |
| 220 | bus_space_tag_t bst; |
| 221 | struct agp_map *agph; |
| 222 | bus_space_handle_t opregion_ioh; |
| 223 | bus_space_handle_t opregion_rvda_ioh; |
| 224 | bus_size_t opregion_rvda_size; |
| 225 | #endif |
| 226 | |
| 227 | struct drm_device drm; |
| 228 | |
| 229 | struct intel_display display; |
| 230 | |
| 231 | /* FIXME: Device release actions should all be moved to drmm_ */ |
| 232 | bool_Bool do_release; |
| 233 | |
| 234 | /* i915 device parameters */ |
| 235 | struct i915_params params; |
| 236 | |
| 237 | const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ |
| 238 | struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ |
| 239 | struct intel_driver_caps caps; |
| 240 | |
| 241 | /** |
| 242 | * Data Stolen Memory - aka "i915 stolen memory" gives us the start and |
| 243 | * end of stolen which we can optionally use to create GEM objects |
| 244 | * backed by stolen memory. Note that stolen_usable_size tells us |
| 245 | * exactly how much of this we are actually allowed to use, given that |
| 246 | * some portion of it is in fact reserved for use by hardware functions. |
| 247 | */ |
| 248 | struct resource dsm; |
| 249 | /** |
| 250 | * Reseved portion of Data Stolen Memory |
| 251 | */ |
| 252 | struct resource dsm_reserved; |
| 253 | |
| 254 | /* |
| 255 | * Stolen memory is segmented in hardware with different portions |
| 256 | * offlimits to certain functions. |
| 257 | * |
| 258 | * The drm_mm is initialised to the total accessible range, as found |
| 259 | * from the PCI config. On Broadwell+, this is further restricted to |
| 260 | * avoid the first page! The upper end of stolen memory is reserved for |
| 261 | * hardware functions and similarly removed from the accessible range. |
| 262 | */ |
| 263 | resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ |
| 264 | |
| 265 | #ifdef __OpenBSD__1 |
| 266 | pci_chipset_tag_t pc; |
| 267 | pcitag_t tag; |
| 268 | struct extent *memex; |
| 269 | pci_intr_handle_t ih; |
| 270 | irqreturn_t(*irq_handler) (int, void *); |
| 271 | void *irqh; |
| 272 | |
| 273 | struct vga_pci_bar bar; |
| 274 | struct vga_pci_bar *vga_regs; |
| 275 | |
| 276 | const struct pci_device_id *id; |
| 277 | |
| 278 | int console; |
| 279 | int primary; |
| 280 | int nscreens; |
| 281 | void (*switchcb)(void *, int, int); |
| 282 | void *switchcbarg; |
| 283 | void *switchcookie; |
| 284 | struct task switchtask; |
| 285 | struct rasops_info ro; |
| 286 | |
| 287 | struct task burner_task; |
| 288 | int burner_fblank; |
| 289 | |
| 290 | struct backlight_device *backlight; |
| 291 | |
| 292 | union flush { |
| 293 | struct { |
| 294 | bus_space_tag_t bst; |
| 295 | bus_space_handle_t bsh; |
| 296 | } i9xx; |
| 297 | struct { |
| 298 | bus_dma_segment_t seg; |
| 299 | caddr_t kva; |
| 300 | } i8xx; |
| 301 | } ifp; |
| 302 | struct vm_page *pgs; |
| 303 | #endif |
| 304 | |
| 305 | struct intel_uncore uncore; |
| 306 | struct intel_uncore_mmio_debug mmio_debug; |
| 307 | |
| 308 | struct i915_virtual_gpu vgpu; |
| 309 | |
| 310 | struct intel_gvt *gvt; |
| 311 | |
| 312 | struct intel_wopcm wopcm; |
| 313 | |
| 314 | struct pci_dev *bridge_dev; |
| 315 | |
| 316 | struct rb_root uabi_engines; |
| 317 | unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASSI915_ENGINE_CLASS_COMPUTE + 1]; |
| 318 | |
| 319 | struct resource mch_res; |
| 320 | |
| 321 | /* protects the irq masks */ |
| 322 | spinlock_t irq_lock; |
| 323 | |
| 324 | bool_Bool display_irqs_enabled; |
| 325 | |
| 326 | /* Sideband mailbox protection */ |
| 327 | struct rwlock sb_lock; |
| 328 | struct pm_qos_request sb_qos; |
| 329 | |
| 330 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
| 331 | union { |
| 332 | u32 irq_mask; |
| 333 | u32 de_irq_mask[I915_MAX_PIPES]; |
| 334 | }; |
| 335 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
| 336 | |
| 337 | bool_Bool preserve_bios_swizzle; |
| 338 | |
| 339 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| 340 | unsigned int skl_preferred_vco_freq; |
| 341 | |
| 342 | unsigned int max_dotclk_freq; |
| 343 | unsigned int hpll_freq; |
| 344 | unsigned int czclk_freq; |
| 345 | |
| 346 | /** |
| 347 | * wq - Driver workqueue for GEM. |
| 348 | * |
| 349 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| 350 | * locks, for otherwise the flushing done in the pageflip code will |
| 351 | * result in deadlocks. |
| 352 | */ |
| 353 | struct workqueue_struct *wq; |
| 354 | |
| 355 | /* pm private clock gating functions */ |
| 356 | const struct drm_i915_clock_gating_funcs *clock_gating_funcs; |
| 357 | |
| 358 | /* PCH chipset type */ |
| 359 | enum intel_pch pch_type; |
| 360 | unsigned short pch_id; |
| 361 | |
| 362 | unsigned long gem_quirks; |
| 363 | |
| 364 | struct drm_atomic_state *modeset_restore_state; |
| 365 | struct drm_modeset_acquire_ctx reset_ctx; |
| 366 | |
| 367 | struct i915_gem_mm mm; |
| 368 | |
| 369 | /* Kernel Modesetting */ |
| 370 | |
| 371 | struct list_head global_obj_list; |
| 372 | |
| 373 | bool_Bool mchbar_need_disable; |
| 374 | |
| 375 | struct intel_l3_parity l3_parity; |
| 376 | |
| 377 | /* |
| 378 | * HTI (aka HDPORT) state read during initial hw readout. Most |
| 379 | * platforms don't have HTI, so this will just stay 0. Those that do |
| 380 | * will use this later to figure out which PLLs and PHYs are unavailable |
| 381 | * for driver usage. |
| 382 | */ |
| 383 | u32 hti_state; |
| 384 | |
| 385 | /* |
| 386 | * edram size in MB. |
| 387 | * Cannot be determined by PCIID. You must always read a register. |
| 388 | */ |
| 389 | u32 edram_size_mb; |
| 390 | |
| 391 | struct i915_gpu_error gpu_error; |
| 392 | |
| 393 | /* |
| 394 | * Shadows for CHV DPLL_MD regs to keep the state |
| 395 | * checker somewhat working in the presence hardware |
| 396 | * crappiness (can't read out DPLL_MD for pipes B & C). |
| 397 | */ |
| 398 | u32 chv_dpll_md[I915_MAX_PIPES]; |
| 399 | u32 bxt_phy_grc; |
| 400 | |
| 401 | u32 suspend_count; |
| 402 | struct i915_suspend_saved_registers regfile; |
| 403 | struct vlv_s0ix_state *vlv_s0ix_state; |
| 404 | |
| 405 | struct dram_info { |
| 406 | bool_Bool wm_lv_0_adjust_needed; |
| 407 | u8 num_channels; |
| 408 | bool_Bool symmetric_memory; |
| 409 | enum intel_dram_type { |
| 410 | INTEL_DRAM_UNKNOWN, |
| 411 | INTEL_DRAM_DDR3, |
| 412 | INTEL_DRAM_DDR4, |
| 413 | INTEL_DRAM_LPDDR3, |
| 414 | INTEL_DRAM_LPDDR4, |
| 415 | INTEL_DRAM_DDR5, |
| 416 | INTEL_DRAM_LPDDR5, |
| 417 | } type; |
| 418 | u8 num_qgv_points; |
| 419 | u8 num_psf_gv_points; |
| 420 | } dram_info; |
| 421 | |
| 422 | struct intel_runtime_pm runtime_pm; |
| 423 | |
| 424 | struct i915_perf perf; |
| 425 | |
| 426 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
| 427 | struct intel_gt gt0; |
| 428 | |
| 429 | /* |
| 430 | * i915->gt[0] == &i915->gt0 |
| 431 | */ |
| 432 | #define I915_MAX_GT4 4 |
| 433 | struct intel_gt *gt[I915_MAX_GT4]; |
| 434 | |
| 435 | struct kobject *sysfs_gt; |
| 436 | |
| 437 | /* Quick lookup of media GT (current platforms only have one) */ |
| 438 | struct intel_gt *media_gt; |
| 439 | |
| 440 | struct { |
| 441 | struct i915_gem_contexts { |
| 442 | spinlock_t lock; /* locks list */ |
| 443 | struct list_head list; |
| 444 | } contexts; |
| 445 | |
| 446 | /* |
| 447 | * We replace the local file with a global mappings as the |
| 448 | * backing storage for the mmap is on the device and not |
| 449 | * on the struct file, and we do not want to prolong the |
| 450 | * lifetime of the local fd. To minimise the number of |
| 451 | * anonymous inodes we create, we use a global singleton to |
| 452 | * share the global mapping. |
| 453 | */ |
| 454 | struct file *mmap_singleton; |
| 455 | } gem; |
| 456 | |
| 457 | u8 pch_ssc_use; |
| 458 | |
| 459 | /* For i915gm/i945gm vblank irq workaround */ |
| 460 | u8 vblank_enabled; |
| 461 | |
| 462 | bool_Bool irq_enabled; |
| 463 | |
| 464 | /* |
| 465 | * DG2: Mask of PHYs that were not calibrated by the firmware |
| 466 | * and should not be used. |
| 467 | */ |
| 468 | u8 snps_phy_failed_calibration; |
| 469 | |
| 470 | struct i915_pmu pmu; |
| 471 | |
| 472 | struct i915_drm_clients clients; |
| 473 | |
| 474 | /* The TTM device structure. */ |
| 475 | struct ttm_device bdev; |
| 476 | |
| 477 | I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) |
| 478 | |
| 479 | /* |
| 480 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
| 481 | * will be rejected. Instead look for a better place. |
| 482 | */ |
| 483 | }; |
| 484 | |
| 485 | static inline struct drm_i915_privateinteldrm_softc *to_i915(const struct drm_device *dev) |
| 486 | { |
| 487 | return container_of(dev, struct drm_i915_private, drm)({ const __typeof( ((struct inteldrm_softc *)0)->drm ) *__mptr = (dev); (struct inteldrm_softc *)( (char *)__mptr - __builtin_offsetof (struct inteldrm_softc, drm) );}); |
| 488 | } |
| 489 | |
| 490 | static inline struct drm_i915_privateinteldrm_softc *kdev_to_i915(struct device *kdev) |
| 491 | { |
| 492 | return dev_get_drvdata(kdev); |
| 493 | } |
| 494 | |
| 495 | static inline struct drm_i915_privateinteldrm_softc *pdev_to_i915(struct pci_dev *pdev) |
| 496 | { |
| 497 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 498 | return NULL((void *)0); |
| 499 | #ifdef notyet |
| 500 | return pci_get_drvdata(pdev); |
| 501 | #endif |
| 502 | } |
| 503 | |
| 504 | static inline struct intel_gt *to_gt(struct drm_i915_privateinteldrm_softc *i915) |
| 505 | { |
| 506 | return &i915->gt0; |
| 507 | } |
| 508 | |
| 509 | /* Simple iterator over all initialised engines */ |
| 510 | #define for_each_engine(engine__, dev_priv__, id__)for ((id__) = 0; (id__) < I915_NUM_ENGINES; (id__)++) if ( !((engine__) = (dev_priv__)->engine[(id__)])) {} else \ |
| 511 | for ((id__) = 0; \ |
| 512 | (id__) < I915_NUM_ENGINES; \ |
| 513 | (id__)++) \ |
| 514 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)])if (!((engine__) = (dev_priv__)->engine[(id__)])) {} else |
| 515 | |
| 516 | /* Iterator over subset of engines selected by mask */ |
| 517 | #define for_each_engine_masked(engine__, gt__, mask__, tmp__)for ((tmp__) = (mask__) & (gt__)->info.engine_mask; (tmp__ ) ? ((engine__) = (gt__)->engine[({ int __idx = ffs(tmp__) - 1; tmp__ &= ~(1UL << (__idx)); __idx; })]), 1 : 0 ;) \ |
| 518 | for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ |
| 519 | (tmp__) ? \ |
| 520 | ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)({ int __idx = ffs(tmp__) - 1; tmp__ &= ~(1UL << (__idx )); __idx; })]), 1 : \ |
| 521 | 0;) |
| 522 | |
| 523 | #define rb_to_uabi_engine(rb)(rb ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (rb); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof(struct intel_engine_cs, uabi_node) );}) : ((void *)0)) \ |
| 524 | rb_entry_safe(rb, struct intel_engine_cs, uabi_node)(rb ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (rb); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof(struct intel_engine_cs, uabi_node) );}) : ((void *)0)) |
| 525 | |
| 526 | #define for_each_uabi_engine(engine__, i915__)for ((engine__) = (linux_root_RB_MINMAX((struct linux_root *) (&(i915__)->uabi_engines), -1) ? ({ const __typeof( (( struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_MINMAX ((struct linux_root *)(&(i915__)->uabi_engines), -1)); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof (struct intel_engine_cs, uabi_node) );}) : ((void *)0)); (engine__ ); (engine__) = (linux_root_RB_NEXT((&(engine__)->uabi_node )) ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_NEXT((&(engine__)->uabi_node ))); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof (struct intel_engine_cs, uabi_node) );}) : ((void *)0))) \ |
| 527 | for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines))(linux_root_RB_MINMAX((struct linux_root *)(&(i915__)-> uabi_engines), -1) ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_MINMAX((struct linux_root *)(&(i915__)->uabi_engines), -1)); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof(struct intel_engine_cs, uabi_node) );}) : ((void *)0));\ |
| 528 | (engine__); \ |
| 529 | (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))(linux_root_RB_NEXT((&(engine__)->uabi_node)) ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_NEXT((&(engine__)->uabi_node))); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof(struct intel_engine_cs, uabi_node) );}) : ((void *)0))) |
| 530 | |
| 531 | #define for_each_uabi_class_engine(engine__, class__, i915__)for ((engine__) = intel_engine_lookup_user((i915__), (class__ ), 0); (engine__) && (engine__)->uabi_class == (class__ ); (engine__) = (linux_root_RB_NEXT((&(engine__)->uabi_node )) ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_NEXT((&(engine__)->uabi_node ))); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof (struct intel_engine_cs, uabi_node) );}) : ((void *)0))) \ |
| 532 | for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ |
| 533 | (engine__) && (engine__)->uabi_class == (class__); \ |
| 534 | (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))(linux_root_RB_NEXT((&(engine__)->uabi_node)) ? ({ const __typeof( ((struct intel_engine_cs *)0)->uabi_node ) *__mptr = (linux_root_RB_NEXT((&(engine__)->uabi_node))); (struct intel_engine_cs *)( (char *)__mptr - __builtin_offsetof(struct intel_engine_cs, uabi_node) );}) : ((void *)0))) |
| 535 | |
| 536 | #define INTEL_INFO(dev_priv)(&(dev_priv)->__info) (&(dev_priv)->__info) |
| 537 | #define RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime) (&(dev_priv)->__runtime) |
| 538 | #define DRIVER_CAPS(dev_priv)(&(dev_priv)->caps) (&(dev_priv)->caps) |
| 539 | |
| 540 | #define INTEL_DEVID(dev_priv)((&(dev_priv)->__runtime)->device_id) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->device_id) |
| 541 | |
| 542 | #define IP_VER(ver, rel)((ver) << 8 | (rel)) ((ver) << 8 | (rel)) |
| 543 | |
| 544 | #define GRAPHICS_VER(i915)((&(i915)->__runtime)->graphics.ip.ver) (RUNTIME_INFO(i915)(&(i915)->__runtime)->graphics.ip.ver) |
| 545 | #define GRAPHICS_VER_FULL(i915)(((&(i915)->__runtime)->graphics.ip.ver) << 8 | ((&(i915)->__runtime)->graphics.ip.rel)) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \(((&(i915)->__runtime)->graphics.ip.ver) << 8 | ((&(i915)->__runtime)->graphics.ip.rel)) |
| 546 | RUNTIME_INFO(i915)->graphics.ip.rel)(((&(i915)->__runtime)->graphics.ip.ver) << 8 | ((&(i915)->__runtime)->graphics.ip.rel)) |
| 547 | #define IS_GRAPHICS_VER(i915, from, until)(((&(i915)->__runtime)->graphics.ip.ver) >= (from ) && ((&(i915)->__runtime)->graphics.ip.ver ) <= (until)) \ |
| 548 | (GRAPHICS_VER(i915)((&(i915)->__runtime)->graphics.ip.ver) >= (from) && GRAPHICS_VER(i915)((&(i915)->__runtime)->graphics.ip.ver) <= (until)) |
| 549 | |
| 550 | #define MEDIA_VER(i915)((&(i915)->__runtime)->media.ip.ver) (RUNTIME_INFO(i915)(&(i915)->__runtime)->media.ip.ver) |
| 551 | #define MEDIA_VER_FULL(i915)(((&(i915)->__runtime)->media.ip.ver) << 8 | ( (&(i915)->__runtime)->media.ip.rel)) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \(((&(i915)->__runtime)->media.ip.ver) << 8 | ( (&(i915)->__runtime)->media.ip.rel)) |
| 552 | RUNTIME_INFO(i915)->media.ip.rel)(((&(i915)->__runtime)->media.ip.ver) << 8 | ( (&(i915)->__runtime)->media.ip.rel)) |
| 553 | #define IS_MEDIA_VER(i915, from, until)(((&(i915)->__runtime)->media.ip.ver) >= (from) && ((&(i915)->__runtime)->media.ip.ver) <= (until) ) \ |
| 554 | (MEDIA_VER(i915)((&(i915)->__runtime)->media.ip.ver) >= (from) && MEDIA_VER(i915)((&(i915)->__runtime)->media.ip.ver) <= (until)) |
| 555 | |
| 556 | #define DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) (RUNTIME_INFO(i915)(&(i915)->__runtime)->display.ip.ver) |
| 557 | #define IS_DISPLAY_VER(i915, from, until)(((&(i915)->__runtime)->display.ip.ver) >= (from ) && ((&(i915)->__runtime)->display.ip.ver) <= (until)) \ |
| 558 | (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= (from) && DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) <= (until)) |
| 559 | |
| 560 | #define INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) ((dev_priv)->drm.pdev->revision) |
| 561 | |
| 562 | #define HAS_DSB(dev_priv)((&(dev_priv)->__info)->display.has_dsb) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_dsb) |
| 563 | |
| 564 | #define INTEL_DISPLAY_STEP(__i915)((&(__i915)->__runtime)->step.display_step) (RUNTIME_INFO(__i915)(&(__i915)->__runtime)->step.display_step) |
| 565 | #define INTEL_GRAPHICS_STEP(__i915)((&(__i915)->__runtime)->step.graphics_step) (RUNTIME_INFO(__i915)(&(__i915)->__runtime)->step.graphics_step) |
| 566 | #define INTEL_MEDIA_STEP(__i915)((&(__i915)->__runtime)->step.media_step) (RUNTIME_INFO(__i915)(&(__i915)->__runtime)->step.media_step) |
| 567 | #define INTEL_BASEDIE_STEP(__i915)((&(__i915)->__runtime)->step.basedie_step) (RUNTIME_INFO(__i915)(&(__i915)->__runtime)->step.basedie_step) |
| 568 | |
| 569 | #define IS_DISPLAY_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until )) \ |
| 570 | (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE)({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), \ |
| 571 | INTEL_DISPLAY_STEP(__i915)((&(__i915)->__runtime)->step.display_step) >= (since) && INTEL_DISPLAY_STEP(__i915)((&(__i915)->__runtime)->step.display_step) < (until)) |
| 572 | |
| 573 | #define IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until )) \ |
| 574 | (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE)({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), \ |
| 575 | INTEL_GRAPHICS_STEP(__i915)((&(__i915)->__runtime)->step.graphics_step) >= (since) && INTEL_GRAPHICS_STEP(__i915)((&(__i915)->__runtime)->step.graphics_step) < (until)) |
| 576 | |
| 577 | #define IS_MEDIA_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.media_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.media_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.media_step) >= (since) && ((& (__i915)->__runtime)->step.media_step) < (until)) \ |
| 578 | (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE)({ int __ret = !!((((&(__i915)->__runtime)->step.media_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.media_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), \ |
| 579 | INTEL_MEDIA_STEP(__i915)((&(__i915)->__runtime)->step.media_step) >= (since) && INTEL_MEDIA_STEP(__i915)((&(__i915)->__runtime)->step.media_step) < (until)) |
| 580 | |
| 581 | #define IS_BASEDIE_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.basedie_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.basedie_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.basedie_step) >= (since) && (( &(__i915)->__runtime)->step.basedie_step) < (until )) \ |
| 582 | (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE)({ int __ret = !!((((&(__i915)->__runtime)->step.basedie_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.basedie_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), \ |
| 583 | INTEL_BASEDIE_STEP(__i915)((&(__i915)->__runtime)->step.basedie_step) >= (since) && INTEL_BASEDIE_STEP(__i915)((&(__i915)->__runtime)->step.basedie_step) < (until)) |
| 584 | |
| 585 | static __always_inlineinline __attribute__((__always_inline__)) unsigned int |
| 586 | __platform_mask_index(const struct intel_runtime_info *info, |
| 587 | enum intel_platform p) |
| 588 | { |
| 589 | const unsigned int pbits = |
| 590 | BITS_PER_TYPE(info->platform_mask[0])(8 * sizeof(info->platform_mask[0])) - INTEL_SUBPLATFORM_BITS(3); |
| 591 | |
| 592 | /* Expand the platform_mask array if this fails. */ |
| 593 | BUILD_BUG_ON(INTEL_MAX_PLATFORMS >extern char _ctassert[(!(INTEL_MAX_PLATFORMS > pbits * (sizeof ((info->platform_mask)) / sizeof((info->platform_mask)[ 0])))) ? 1 : -1 ] __attribute__((__unused__)) |
| 594 | pbits * ARRAY_SIZE(info->platform_mask))extern char _ctassert[(!(INTEL_MAX_PLATFORMS > pbits * (sizeof ((info->platform_mask)) / sizeof((info->platform_mask)[ 0])))) ? 1 : -1 ] __attribute__((__unused__)); |
| 595 | |
| 596 | return p / pbits; |
| 597 | } |
| 598 | |
| 599 | static __always_inlineinline __attribute__((__always_inline__)) unsigned int |
| 600 | __platform_mask_bit(const struct intel_runtime_info *info, |
| 601 | enum intel_platform p) |
| 602 | { |
| 603 | const unsigned int pbits = |
| 604 | BITS_PER_TYPE(info->platform_mask[0])(8 * sizeof(info->platform_mask[0])) - INTEL_SUBPLATFORM_BITS(3); |
| 605 | |
| 606 | return p % pbits + INTEL_SUBPLATFORM_BITS(3); |
| 607 | } |
| 608 | |
| 609 | static inline u32 |
| 610 | intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) |
| 611 | { |
| 612 | const unsigned int pi = __platform_mask_index(info, p); |
| 613 | |
| 614 | return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK((1UL << ((3))) - 1); |
| 615 | } |
| 616 | |
| 617 | static __always_inlineinline __attribute__((__always_inline__)) bool_Bool |
| 618 | IS_PLATFORM(const struct drm_i915_privateinteldrm_softc *i915, enum intel_platform p) |
| 619 | { |
| 620 | const struct intel_runtime_info *info = RUNTIME_INFO(i915)(&(i915)->__runtime); |
| 621 | const unsigned int pi = __platform_mask_index(info, p); |
| 622 | const unsigned int pb = __platform_mask_bit(info, p); |
| 623 | |
| 624 | #ifdef notyet |
| 625 | BUILD_BUG_ON(!__builtin_constant_p(p))extern char _ctassert[(!(!__builtin_constant_p(p))) ? 1 : -1 ] __attribute__((__unused__)); |
| 626 | #endif |
| 627 | |
| 628 | return info->platform_mask[pi] & BIT(pb)(1UL << (pb)); |
| 629 | } |
| 630 | |
| 631 | static __always_inlineinline __attribute__((__always_inline__)) bool_Bool |
| 632 | IS_SUBPLATFORM(const struct drm_i915_privateinteldrm_softc *i915, |
| 633 | enum intel_platform p, unsigned int s) |
| 634 | { |
| 635 | const struct intel_runtime_info *info = RUNTIME_INFO(i915)(&(i915)->__runtime); |
| 636 | const unsigned int pi = __platform_mask_index(info, p); |
| 637 | const unsigned int pb = __platform_mask_bit(info, p); |
| 638 | const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0])(8 * sizeof(info->platform_mask[0])) - 1; |
| 639 | const u32 mask = info->platform_mask[pi]; |
| 640 | |
| 641 | #ifdef notyet |
| 642 | BUILD_BUG_ON(!__builtin_constant_p(p))extern char _ctassert[(!(!__builtin_constant_p(p))) ? 1 : -1 ] __attribute__((__unused__)); |
| 643 | BUILD_BUG_ON(!__builtin_constant_p(s))extern char _ctassert[(!(!__builtin_constant_p(s))) ? 1 : -1 ] __attribute__((__unused__)); |
| 644 | BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS)extern char _ctassert[(!((s) >= (3))) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 645 | #endif |
| 646 | |
| 647 | /* Shift and test on the MSB position so sign flag can be used. */ |
| 648 | return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb)(1UL << (msb)); |
| 649 | } |
| 650 | |
| 651 | #define IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->is_mobile) |
| 652 | #define IS_DGFX(dev_priv)((&(dev_priv)->__info)->is_dgfx) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->is_dgfx) |
| 653 | |
| 654 | #define IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) IS_PLATFORM(dev_priv, INTEL_I830) |
| 655 | #define IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G) IS_PLATFORM(dev_priv, INTEL_I845G) |
| 656 | #define IS_I85X(dev_priv)IS_PLATFORM(dev_priv, INTEL_I85X) IS_PLATFORM(dev_priv, INTEL_I85X) |
| 657 | #define IS_I865G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I865G) IS_PLATFORM(dev_priv, INTEL_I865G) |
| 658 | #define IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) IS_PLATFORM(dev_priv, INTEL_I915G) |
| 659 | #define IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM) IS_PLATFORM(dev_priv, INTEL_I915GM) |
| 660 | #define IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) IS_PLATFORM(dev_priv, INTEL_I945G) |
| 661 | #define IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) IS_PLATFORM(dev_priv, INTEL_I945GM) |
| 662 | #define IS_I965G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965G) IS_PLATFORM(dev_priv, INTEL_I965G) |
| 663 | #define IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) IS_PLATFORM(dev_priv, INTEL_I965GM) |
| 664 | #define IS_G45(dev_priv)IS_PLATFORM(dev_priv, INTEL_G45) IS_PLATFORM(dev_priv, INTEL_G45) |
| 665 | #define IS_GM45(dev_priv)IS_PLATFORM(dev_priv, INTEL_GM45) IS_PLATFORM(dev_priv, INTEL_GM45) |
| 666 | #define IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) (IS_G45(dev_priv)IS_PLATFORM(dev_priv, INTEL_G45) || IS_GM45(dev_priv)IS_PLATFORM(dev_priv, INTEL_GM45)) |
| 667 | #define IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) |
| 668 | #define IS_G33(dev_priv)IS_PLATFORM(dev_priv, INTEL_G33) IS_PLATFORM(dev_priv, INTEL_G33) |
| 669 | #define IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) |
| 670 | #define IS_IRONLAKE_M(dev_priv)(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && ((&(dev_priv )->__info)->is_mobile)) \ |
| 671 | (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile)) |
| 672 | #define IS_SANDYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) |
| 673 | #define IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) |
| 674 | #define IS_IVB_GT1(dev_priv)(IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) && (&(dev_priv )->__info)->gt == 1) (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) && \ |
| 675 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 1) |
| 676 | #define IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) |
| 677 | #define IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) |
| 678 | #define IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) IS_PLATFORM(dev_priv, INTEL_HASWELL) |
| 679 | #define IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) IS_PLATFORM(dev_priv, INTEL_BROADWELL) |
| 680 | #define IS_SKYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SKYLAKE) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) |
| 681 | #define IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) IS_PLATFORM(dev_priv, INTEL_BROXTON) |
| 682 | #define IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) |
| 683 | #define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) |
| 684 | #define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) |
| 685 | #define IS_COMETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COMETLAKE) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) |
| 686 | #define IS_ICELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ICELAKE) IS_PLATFORM(dev_priv, INTEL_ICELAKE) |
| 687 | #define IS_JSL_EHL(dev_priv)(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || IS_PLATFORM(dev_priv , INTEL_ELKHARTLAKE)) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ |
| 688 | IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) |
| 689 | #define IS_TIGERLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) |
| 690 | #define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) |
| 691 | #define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1) IS_PLATFORM(dev_priv, INTEL_DG1) |
| 692 | #define IS_ALDERLAKE_S(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) |
| 693 | #define IS_ALDERLAKE_P(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) |
| 694 | #define IS_XEHPSDV(dev_priv)IS_PLATFORM(dev_priv, INTEL_XEHPSDV) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) |
| 695 | #define IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2) IS_PLATFORM(dev_priv, INTEL_DG2) |
| 696 | #define IS_PONTEVECCHIO(dev_priv)IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) |
| 697 | #define IS_METEORLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_METEORLAKE) IS_PLATFORM(dev_priv, INTEL_METEORLAKE) |
| 698 | |
| 699 | #define IS_METEORLAKE_M(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, 0) \ |
| 700 | IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M0) |
| 701 | #define IS_METEORLAKE_P(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, 1) \ |
| 702 | IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P1) |
| 703 | #define IS_DG2_G10(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_DG2, 0) \ |
| 704 | IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G100) |
| 705 | #define IS_DG2_G11(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_DG2, 1) \ |
| 706 | IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G111) |
| 707 | #define IS_DG2_G12(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_DG2, 2) \ |
| 708 | IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G122) |
| 709 | #define IS_ADLS_RPLS(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, 0) \ |
| 710 | IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL0) |
| 711 | #define IS_ADLP_N(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, 1) \ |
| 712 | IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N1) |
| 713 | #define IS_ADLP_RPLP(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, 0) \ |
| 714 | IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL0) |
| 715 | #define IS_HSW_EARLY_SDV(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (((&(dev_priv )->__runtime)->device_id) & 0xFF00) == 0x0C00) (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && \ |
| 716 | (INTEL_DEVID(dev_priv)((&(dev_priv)->__runtime)->device_id) & 0xFF00) == 0x0C00) |
| 717 | #define IS_BDW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, (0)) \ |
| 718 | IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT(0)) |
| 719 | #define IS_BDW_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, (1)) \ |
| 720 | IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX(1)) |
| 721 | #define IS_BDW_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_BROADWELL) && (&(dev_priv )->__info)->gt == 3) (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) && \ |
| 722 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 3) |
| 723 | #define IS_HSW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0)) \ |
| 724 | IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT(0)) |
| 725 | #define IS_HSW_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (&(dev_priv )->__info)->gt == 3) (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && \ |
| 726 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 3) |
| 727 | #define IS_HSW_GT1(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (&(dev_priv )->__info)->gt == 1) (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && \ |
| 728 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 1) |
| 729 | /* ULX machines are also considered ULT. */ |
| 730 | #define IS_HSW_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (1)) \ |
| 731 | IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX(1)) |
| 732 | #define IS_SKL_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, (0)) \ |
| 733 | IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT(0)) |
| 734 | #define IS_SKL_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, (1)) \ |
| 735 | IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX(1)) |
| 736 | #define IS_KBL_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, (0)) \ |
| 737 | IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT(0)) |
| 738 | #define IS_KBL_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, (1)) \ |
| 739 | IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX(1)) |
| 740 | #define IS_SKL_GT2(dev_priv)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 2) (IS_SKYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && \ |
| 741 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 2) |
| 742 | #define IS_SKL_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 3) (IS_SKYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && \ |
| 743 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 3) |
| 744 | #define IS_SKL_GT4(dev_priv)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 4) (IS_SKYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && \ |
| 745 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 4) |
| 746 | #define IS_KBL_GT2(dev_priv)(IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && (&(dev_priv )->__info)->gt == 2) (IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && \ |
| 747 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 2) |
| 748 | #define IS_KBL_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && (&(dev_priv )->__info)->gt == 3) (IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && \ |
| 749 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 3) |
| 750 | #define IS_CFL_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, (0)) \ |
| 751 | IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT(0)) |
| 752 | #define IS_CFL_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, (1)) \ |
| 753 | IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX(1)) |
| 754 | #define IS_CFL_GT2(dev_priv)(IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) && (&(dev_priv )->__info)->gt == 2) (IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) && \ |
| 755 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 2) |
| 756 | #define IS_CFL_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) && (&(dev_priv )->__info)->gt == 3) (IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) && \ |
| 757 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 3) |
| 758 | |
| 759 | #define IS_CML_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, (0)) \ |
| 760 | IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT(0)) |
| 761 | #define IS_CML_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, (1)) \ |
| 762 | IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX(1)) |
| 763 | #define IS_CML_GT2(dev_priv)(IS_PLATFORM(dev_priv, INTEL_COMETLAKE) && (&(dev_priv )->__info)->gt == 2) (IS_COMETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COMETLAKE) && \ |
| 764 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gt == 2) |
| 765 | |
| 766 | #define IS_ICL_WITH_PORT_F(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, (0)) \ |
| 767 | IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF(0)) |
| 768 | |
| 769 | #define IS_TGL_UY(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, (0)) \ |
| 770 | IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY(0)) |
| 771 | |
| 772 | #define IS_SKL_GRAPHICS_STEP(p, since, until)(IS_PLATFORM(p, INTEL_SKYLAKE) && (({ int __ret = !!( (((&(p)->__runtime)->step.graphics_step) == STEP_NONE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) (IS_SKYLAKE(p)IS_PLATFORM(p, INTEL_SKYLAKE) && IS_GRAPHICS_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) |
| 773 | |
| 774 | #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until)(IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && (({ int __ret = !!((((&(dev_priv)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(dev_priv)-> __runtime)->step.graphics_step) >= (since) && ( (&(dev_priv)->__runtime)->step.graphics_step) < ( until))) \ |
| 775 | (IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && IS_GRAPHICS_STEP(dev_priv, since, until)(({ int __ret = !!((((&(dev_priv)->__runtime)->step .graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(dev_priv)-> __runtime)->step.graphics_step) >= (since) && ( (&(dev_priv)->__runtime)->step.graphics_step) < ( until))) |
| 776 | #define IS_KBL_DISPLAY_STEP(dev_priv, since, until)(IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && (({ int __ret = !!((((&(dev_priv)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(dev_priv)-> __runtime)->step.display_step) >= (since) && (( &(dev_priv)->__runtime)->step.display_step) < (until ))) \ |
| 777 | (IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && IS_DISPLAY_STEP(dev_priv, since, until)(({ int __ret = !!((((&(dev_priv)->__runtime)->step .display_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(dev_priv)-> __runtime)->step.display_step) >= (since) && (( &(dev_priv)->__runtime)->step.display_step) < (until ))) |
| 778 | |
| 779 | #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until)((IS_PLATFORM(p, INTEL_JASPERLAKE) || IS_PLATFORM(p, INTEL_ELKHARTLAKE )) && (({ int __ret = !!((((&(p)->__runtime)-> step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) \ |
| 780 | (IS_JSL_EHL(p)(IS_PLATFORM(p, INTEL_JASPERLAKE) || IS_PLATFORM(p, INTEL_ELKHARTLAKE )) && IS_GRAPHICS_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) |
| 781 | #define IS_JSL_EHL_DISPLAY_STEP(p, since, until)((IS_PLATFORM(p, INTEL_JASPERLAKE) || IS_PLATFORM(p, INTEL_ELKHARTLAKE )) && (({ int __ret = !!((((&(p)->__runtime)-> step.display_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) \ |
| 782 | (IS_JSL_EHL(p)(IS_PLATFORM(p, INTEL_JASPERLAKE) || IS_PLATFORM(p, INTEL_ELKHARTLAKE )) && IS_DISPLAY_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) |
| 783 | |
| 784 | #define IS_TGL_DISPLAY_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_TIGERLAKE) && (({ int __ret = !!((((&(__i915)->__runtime)->step.display_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) \ |
| 785 | (IS_TIGERLAKE(__i915)IS_PLATFORM(__i915, INTEL_TIGERLAKE) && \ |
| 786 | IS_DISPLAY_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) |
| 787 | |
| 788 | #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until)(IS_SUBPLATFORM(__i915, INTEL_TIGERLAKE, (0)) && (({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 789 | (IS_TGL_UY(__i915)IS_SUBPLATFORM(__i915, INTEL_TIGERLAKE, (0)) && \ |
| 790 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 791 | |
| 792 | #define IS_TGL_GRAPHICS_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_TIGERLAKE) && !IS_SUBPLATFORM (__i915, INTEL_TIGERLAKE, (0))) && (({ int __ret = !! ((((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 793 | (IS_TIGERLAKE(__i915)IS_PLATFORM(__i915, INTEL_TIGERLAKE) && !IS_TGL_UY(__i915)IS_SUBPLATFORM(__i915, INTEL_TIGERLAKE, (0))) && \ |
| 794 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 795 | |
| 796 | #define IS_RKL_DISPLAY_STEP(p, since, until)(IS_PLATFORM(p, INTEL_ROCKETLAKE) && (({ int __ret = ! !((((&(p)->__runtime)->step.display_step) == STEP_NONE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) \ |
| 797 | (IS_ROCKETLAKE(p)IS_PLATFORM(p, INTEL_ROCKETLAKE) && IS_DISPLAY_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) |
| 798 | |
| 799 | #define IS_DG1_GRAPHICS_STEP(p, since, until)(IS_PLATFORM(p, INTEL_DG1) && (({ int __ret = !!((((& (p)->__runtime)->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(p)-> drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) \ |
| 800 | (IS_DG1(p)IS_PLATFORM(p, INTEL_DG1) && IS_GRAPHICS_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.graphics_step) >= (since) && ((&(p) ->__runtime)->step.graphics_step) < (until))) |
| 801 | #define IS_DG1_DISPLAY_STEP(p, since, until)(IS_PLATFORM(p, INTEL_DG1) && (({ int __ret = !!((((& (p)->__runtime)->step.display_step) == STEP_NONE)); if ( __ret) printf("%s %s: " "%s", dev_driver_string(((&(p)-> drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) \ |
| 802 | (IS_DG1(p)IS_PLATFORM(p, INTEL_DG1) && IS_DISPLAY_STEP(p, since, until)(({ int __ret = !!((((&(p)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(p)->drm))->dev), "", "drm_WARN_ON(" "((&(p)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(p)->__runtime )->step.display_step) >= (since) && ((&(p)-> __runtime)->step.display_step) < (until))) |
| 803 | |
| 804 | #define IS_ADLS_DISPLAY_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_ALDERLAKE_S) && (({ int __ret = !!((((&(__i915)->__runtime)->step.display_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) \ |
| 805 | (IS_ALDERLAKE_S(__i915)IS_PLATFORM(__i915, INTEL_ALDERLAKE_S) && \ |
| 806 | IS_DISPLAY_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) |
| 807 | |
| 808 | #define IS_ADLS_GRAPHICS_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_ALDERLAKE_S) && (({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 809 | (IS_ALDERLAKE_S(__i915)IS_PLATFORM(__i915, INTEL_ALDERLAKE_S) && \ |
| 810 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 811 | |
| 812 | #define IS_ADLP_DISPLAY_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_ALDERLAKE_P) && (({ int __ret = !!((((&(__i915)->__runtime)->step.display_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) \ |
| 813 | (IS_ALDERLAKE_P(__i915)IS_PLATFORM(__i915, INTEL_ALDERLAKE_P) && \ |
| 814 | IS_DISPLAY_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) |
| 815 | |
| 816 | #define IS_ADLP_GRAPHICS_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_ALDERLAKE_P) && (({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 817 | (IS_ALDERLAKE_P(__i915)IS_PLATFORM(__i915, INTEL_ALDERLAKE_P) && \ |
| 818 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 819 | |
| 820 | #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_XEHPSDV) && (({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 821 | (IS_XEHPSDV(__i915)IS_PLATFORM(__i915, INTEL_XEHPSDV) && IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 822 | |
| 823 | /* |
| 824 | * DG2 hardware steppings are a bit unusual. The hardware design was forked to |
| 825 | * create three variants (G10, G11, and G12) which each have distinct |
| 826 | * workaround sets. The G11 and G12 forks of the DG2 design reset the GT |
| 827 | * stepping back to "A0" for their first iterations, even though they're more |
| 828 | * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of |
| 829 | * functionality and workarounds. However the display stepping does not reset |
| 830 | * in the same manner --- a specific stepping like "B0" has a consistent |
| 831 | * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. |
| 832 | * |
| 833 | * TLDR: All GT workarounds and stepping-specific logic must be applied in |
| 834 | * relation to a specific subplatform (G10/G11/G12), whereas display workarounds |
| 835 | * and stepping-specific logic will be applied with a general DG2-wide stepping |
| 836 | * number. |
| 837 | */ |
| 838 | #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until)(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_variant) && (({ int __ret = !!((((&(__i915)->__runtime )->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(__i915)->drm))->dev), "" , "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 839 | (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ |
| 840 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 841 | |
| 842 | #define IS_DG2_DISPLAY_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_DG2) && (({ int __ret = !! ((((&(__i915)->__runtime)->step.display_step) == STEP_NONE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) \ |
| 843 | (IS_DG2(__i915)IS_PLATFORM(__i915, INTEL_DG2) && \ |
| 844 | IS_DISPLAY_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.display_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.display_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.display_step) >= (since) && (( &(__i915)->__runtime)->step.display_step) < (until ))) |
| 845 | |
| 846 | #define IS_PVC_BD_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_PONTEVECCHIO) && (({ int __ret = !!((((&(__i915)->__runtime)->step.basedie_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.basedie_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.basedie_step) >= (since) && (( &(__i915)->__runtime)->step.basedie_step) < (until ))) \ |
| 847 | (IS_PONTEVECCHIO(__i915)IS_PLATFORM(__i915, INTEL_PONTEVECCHIO) && \ |
| 848 | IS_BASEDIE_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.basedie_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.basedie_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.basedie_step) >= (since) && (( &(__i915)->__runtime)->step.basedie_step) < (until ))) |
| 849 | |
| 850 | #define IS_PVC_CT_STEP(__i915, since, until)(IS_PLATFORM(__i915, INTEL_PONTEVECCHIO) && (({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) \ |
| 851 | (IS_PONTEVECCHIO(__i915)IS_PLATFORM(__i915, INTEL_PONTEVECCHIO) && \ |
| 852 | IS_GRAPHICS_STEP(__i915, since, until)(({ int __ret = !!((((&(__i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(__i915)->drm))->dev), "", "drm_WARN_ON(" "((&(__i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(__i915)-> __runtime)->step.graphics_step) >= (since) && ( (&(__i915)->__runtime)->step.graphics_step) < (until ))) |
| 853 | |
| 854 | #define IS_LP(dev_priv)((&(dev_priv)->__info)->is_lp) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->is_lp) |
| 855 | #define IS_GEN9_LP(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) == 9 && ((&(dev_priv)->__info)->is_lp)) (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) == 9 && IS_LP(dev_priv)((&(dev_priv)->__info)->is_lp)) |
| 856 | #define IS_GEN9_BC(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) == 9 && !((&(dev_priv)->__info)->is_lp)) (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) == 9 && !IS_LP(dev_priv)((&(dev_priv)->__info)->is_lp)) |
| 857 | |
| 858 | #define __HAS_ENGINE(engine_mask, id)((engine_mask) & (1UL << (id))) ((engine_mask) & BIT(id)(1UL << (id))) |
| 859 | #define HAS_ENGINE(gt, id)(((gt)->info.engine_mask) & (1UL << (id))) __HAS_ENGINE((gt)->info.engine_mask, id)(((gt)->info.engine_mask) & (1UL << (id))) |
| 860 | |
| 861 | #define ENGINE_INSTANCES_MASK(gt, first, count)({ unsigned int first__ = (first); unsigned int count__ = (count ); ((gt)->info.engine_mask & (((~0UL) >> (64 - ( first__ + count__ - 1) - 1)) & ((~0UL) << (first__) ))) >> first__; }) ({ \ |
| 862 | unsigned int first__ = (first); \ |
| 863 | unsigned int count__ = (count); \ |
| 864 | ((gt)->info.engine_mask & \ |
| 865 | GENMASK(first__ + count__ - 1, first__)(((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ( (~0UL) << (first__)))) >> first__; \ |
| 866 | }) |
| 867 | #define RCS_MASK(gt)({ unsigned int first__ = (RCS0); unsigned int count__ = (1); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) \ |
| 868 | ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)({ unsigned int first__ = (RCS0); unsigned int count__ = (1); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) |
| 869 | #define BCS_MASK(gt)({ unsigned int first__ = (BCS0); unsigned int count__ = (9); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) \ |
| 870 | ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)({ unsigned int first__ = (BCS0); unsigned int count__ = (9); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) |
| 871 | #define VDBOX_MASK(gt)({ unsigned int first__ = (VCS0); unsigned int count__ = (8); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) \ |
| 872 | ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)({ unsigned int first__ = (VCS0); unsigned int count__ = (8); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) |
| 873 | #define VEBOX_MASK(gt)({ unsigned int first__ = (VECS0); unsigned int count__ = (4) ; ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) \ |
| 874 | ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)({ unsigned int first__ = (VECS0); unsigned int count__ = (4) ; ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) |
| 875 | #define CCS_MASK(gt)({ unsigned int first__ = (CCS0); unsigned int count__ = (4); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) \ |
| 876 | ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)({ unsigned int first__ = (CCS0); unsigned int count__ = (4); ((gt)->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << (first__)))) >> first__; }) |
| 877 | |
| 878 | #define HAS_MEDIA_RATIO_MODE(dev_priv)((&(dev_priv)->__info)->has_media_ratio_mode) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_media_ratio_mode) |
| 879 | |
| 880 | /* |
| 881 | * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution |
| 882 | * All later gens can run the final buffer from the ppgtt |
| 883 | */ |
| 884 | #define CMDPARSER_USES_GGTT(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) == 7) (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) == 7) |
| 885 | |
| 886 | #define HAS_LLC(dev_priv)((&(dev_priv)->__info)->has_llc) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_llc) |
| 887 | #define HAS_4TILE(dev_priv)((&(dev_priv)->__info)->has_4tile) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_4tile) |
| 888 | #define HAS_SNOOP(dev_priv)((&(dev_priv)->__info)->has_snoop) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_snoop) |
| 889 | #define HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb) ((dev_priv)->edram_size_mb) |
| 890 | #define HAS_SECURE_BATCHES(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) < 6 ) (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) < 6) |
| 891 | #define HAS_WT(dev_priv)((dev_priv)->edram_size_mb) HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb) |
| 892 | |
| 893 | #define HWS_NEEDS_PHYSICAL(dev_priv)((&(dev_priv)->__info)->hws_needs_physical) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->hws_needs_physical) |
| 894 | |
| 895 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv)((&(dev_priv)->__info)->has_logical_ring_contexts) \ |
| 896 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_logical_ring_contexts) |
| 897 | #define HAS_LOGICAL_RING_ELSQ(dev_priv)((&(dev_priv)->__info)->has_logical_ring_elsq) \ |
| 898 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_logical_ring_elsq) |
| 899 | |
| 900 | #define HAS_EXECLISTS(dev_priv)((&(dev_priv)->__info)->has_logical_ring_contexts) HAS_LOGICAL_RING_CONTEXTS(dev_priv)((&(dev_priv)->__info)->has_logical_ring_contexts) |
| 901 | |
| 902 | #define INTEL_PPGTT(dev_priv)((&(dev_priv)->__runtime)->ppgtt_type) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->ppgtt_type) |
| 903 | #define HAS_PPGTT(dev_priv)(((&(dev_priv)->__runtime)->ppgtt_type) != INTEL_PPGTT_NONE ) \ |
| 904 | (INTEL_PPGTT(dev_priv)((&(dev_priv)->__runtime)->ppgtt_type) != INTEL_PPGTT_NONE) |
| 905 | #define HAS_FULL_PPGTT(dev_priv)(((&(dev_priv)->__runtime)->ppgtt_type) >= INTEL_PPGTT_FULL ) \ |
| 906 | (INTEL_PPGTT(dev_priv)((&(dev_priv)->__runtime)->ppgtt_type) >= INTEL_PPGTT_FULL) |
| 907 | |
| 908 | #define HAS_PAGE_SIZES(dev_priv, sizes)({ ((void)0); ((sizes) & ~(&(dev_priv)->__runtime) ->page_sizes) == 0; }) ({ \ |
| 909 | GEM_BUG_ON((sizes) == 0)((void)0); \ |
| 910 | ((sizes) & ~RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->page_sizes) == 0; \ |
| 911 | }) |
| 912 | |
| 913 | #define HAS_OVERLAY(dev_priv)((&(dev_priv)->__info)->display.has_overlay) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_overlay) |
| 914 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv)((&(dev_priv)->__info)->display.overlay_needs_physical ) \ |
| 915 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.overlay_needs_physical) |
| 916 | |
| 917 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 918 | #define HAS_BROKEN_CS_TLB(dev_priv)(IS_PLATFORM(dev_priv, INTEL_I830) || IS_PLATFORM(dev_priv, INTEL_I845G )) (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) || IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G)) |
| 919 | |
| 920 | #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)(IS_PLATFORM(dev_priv, INTEL_BROADWELL) || ((&(dev_priv)-> __runtime)->graphics.ip.ver) == 9) \ |
| 921 | (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) == 9) |
| 922 | |
| 923 | /* WaRsDisableCoarsePowerGating:skl,cnl */ |
| 924 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)((IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 3) || (IS_PLATFORM(dev_priv, INTEL_SKYLAKE ) && (&(dev_priv)->__info)->gt == 4)) \ |
| 925 | (IS_SKL_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 3) || IS_SKL_GT4(dev_priv)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (&(dev_priv )->__info)->gt == 4)) |
| 926 | |
| 927 | #define HAS_GMBUS_IRQ(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) >= 4 ) (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
| 928 | #define HAS_GMBUS_BURST_READ(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) >= 11 || IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_PLATFORM(dev_priv , INTEL_KABYLAKE)) (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11 || \ |
| 929 | IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || \ |
| 930 | IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE)) |
| 931 | |
| 932 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 933 | * rows, which changed the alignment requirements and fence programming. |
| 934 | */ |
| 935 | #define HAS_128_BYTE_Y_TILING(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) != 2 && !(IS_PLATFORM(dev_priv, INTEL_I915G) || IS_PLATFORM(dev_priv , INTEL_I915GM))) (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) != 2 && \ |
| 936 | !(IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM))) |
| 937 | #define SUPPORTS_TV(dev_priv)((&(dev_priv)->__info)->display.supports_tv) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.supports_tv) |
| 938 | #define I915_HAS_HOTPLUG(dev_priv)((&(dev_priv)->__info)->display.has_hotplug) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_hotplug) |
| 939 | |
| 940 | #define HAS_FW_BLC(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) > 2) (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) > 2) |
| 941 | #define HAS_FBC(dev_priv)((&(dev_priv)->__runtime)->fbc_mask != 0) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->fbc_mask != 0) |
| 942 | #define HAS_CUR_FBC(dev_priv)(!((&(dev_priv)->__info)->display.has_gmch) && ((&(dev_priv)->__runtime)->display.ip.ver) >= 7 ) (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 7) |
| 943 | |
| 944 | #define HAS_IPS(dev_priv)(IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0)) || IS_PLATFORM( dev_priv, INTEL_BROADWELL)) (IS_HSW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0)) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 945 | |
| 946 | #define HAS_DP_MST(dev_priv)((&(dev_priv)->__info)->display.has_dp_mst) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_dp_mst) |
| 947 | #define HAS_DP20(dev_priv)(IS_PLATFORM(dev_priv, INTEL_DG2) || ((&(dev_priv)->__runtime )->display.ip.ver) >= 14) (IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2) || DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 14) |
| 948 | |
| 949 | #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) >= 9 || IS_PLATFORM(dev_priv, INTEL_BROADWELL)) (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9 || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 950 | |
| 951 | #define HAS_CDCLK_CRAWL(dev_priv)((&(dev_priv)->__info)->display.has_cdclk_crawl) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_cdclk_crawl) |
| 952 | #define HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_ddi) |
| 953 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv)((&(dev_priv)->__info)->display.has_fpga_dbg) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_fpga_dbg) |
| 954 | #define HAS_PSR(dev_priv)((&(dev_priv)->__info)->display.has_psr) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_psr) |
| 955 | #define HAS_PSR_HW_TRACKING(dev_priv)((&(dev_priv)->__info)->display.has_psr_hw_tracking ) \ |
| 956 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_psr_hw_tracking) |
| 957 | #define HAS_PSR2_SEL_FETCH(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) >= 12 ) (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
| 958 | #define HAS_TRANSCODER(dev_priv, trans)(((&(dev_priv)->__runtime)->cpu_transcoder_mask & (1UL << (trans))) != 0) ((RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->cpu_transcoder_mask & BIT(trans)(1UL << (trans))) != 0) |
| 959 | |
| 960 | #define HAS_RC6(dev_priv)((&(dev_priv)->__info)->has_rc6) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_rc6) |
| 961 | #define HAS_RC6p(dev_priv)((&(dev_priv)->__info)->has_rc6p) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_rc6p) |
| 962 | #define HAS_RC6pp(dev_priv)(0) (false0) /* HW was never validated */ |
| 963 | |
| 964 | #define HAS_RPS(dev_priv)((&(dev_priv)->__info)->has_rps) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_rps) |
| 965 | |
| 966 | #define HAS_DMC(dev_priv)((&(dev_priv)->__runtime)->has_dmc) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->has_dmc) |
| 967 | |
| 968 | #define HAS_HECI_PXP(dev_priv)((&(dev_priv)->__info)->has_heci_pxp) \ |
| 969 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_heci_pxp) |
| 970 | |
| 971 | #define HAS_HECI_GSCFI(dev_priv)((&(dev_priv)->__info)->has_heci_gscfi) \ |
| 972 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_heci_gscfi) |
| 973 | |
| 974 | #define HAS_HECI_GSC(dev_priv)(((&(dev_priv)->__info)->has_heci_pxp) || ((&(dev_priv )->__info)->has_heci_gscfi)) (HAS_HECI_PXP(dev_priv)((&(dev_priv)->__info)->has_heci_pxp) || HAS_HECI_GSCFI(dev_priv)((&(dev_priv)->__info)->has_heci_gscfi)) |
| 975 | |
| 976 | #define HAS_MSO(i915)(((&(i915)->__runtime)->display.ip.ver) >= 12) (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 12) |
| 977 | |
| 978 | #define HAS_RUNTIME_PM(dev_priv)((&(dev_priv)->__info)->has_runtime_pm) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_runtime_pm) |
| 979 | #define HAS_64BIT_RELOC(dev_priv)((&(dev_priv)->__info)->has_64bit_reloc) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_64bit_reloc) |
| 980 | |
| 981 | /* |
| 982 | * Set this flag, when platform requires 64K GTT page sizes or larger for |
| 983 | * device local memory access. |
| 984 | */ |
| 985 | #define HAS_64K_PAGES(dev_priv)((&(dev_priv)->__info)->has_64k_pages) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_64k_pages) |
| 986 | |
| 987 | /* |
| 988 | * Set this flag when platform doesn't allow both 64k pages and 4k pages in |
| 989 | * the same PT. this flag means we need to support compact PT layout for the |
| 990 | * ppGTT when using the 64K GTT pages. |
| 991 | */ |
| 992 | #define NEEDS_COMPACT_PT(dev_priv)((&(dev_priv)->__info)->needs_compact_pt) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->needs_compact_pt) |
| 993 | |
| 994 | #define HAS_IPC(dev_priv)((&(dev_priv)->__info)->display.has_ipc) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_ipc) |
| 995 | |
| 996 | #define HAS_REGION(i915, i)((&(i915)->__runtime)->memory_regions & (i)) (RUNTIME_INFO(i915)(&(i915)->__runtime)->memory_regions & (i)) |
| 997 | #define HAS_LMEM(i915)((&(i915)->__runtime)->memory_regions & ((1UL << (INTEL_REGION_LMEM_0)))) HAS_REGION(i915, REGION_LMEM)((&(i915)->__runtime)->memory_regions & ((1UL << (INTEL_REGION_LMEM_0)))) |
| 998 | |
| 999 | #define HAS_EXTRA_GT_LIST(dev_priv)((&(dev_priv)->__info)->extra_gt_list) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->extra_gt_list) |
| 1000 | |
| 1001 | /* |
| 1002 | * Platform has the dedicated compression control state for each lmem surfaces |
| 1003 | * stored in lmem to support the 3D and media compression formats. |
| 1004 | */ |
| 1005 | #define HAS_FLAT_CCS(dev_priv)((&(dev_priv)->__info)->has_flat_ccs) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_flat_ccs) |
| 1006 | |
| 1007 | #define HAS_GT_UC(dev_priv)((&(dev_priv)->__info)->has_gt_uc) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_gt_uc) |
| 1008 | |
| 1009 | #define HAS_POOLED_EU(dev_priv)((&(dev_priv)->__runtime)->has_pooled_eu) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->has_pooled_eu) |
| 1010 | |
| 1011 | #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)((&(dev_priv)->__info)->has_global_mocs) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_global_mocs) |
| 1012 | |
| 1013 | #define HAS_PXP(dev_priv)((0 && (&(dev_priv)->__info)->has_pxp) && ({ unsigned int first__ = (VCS0); unsigned int count__ = (8) ; ((to_gt(dev_priv))->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << ( first__)))) >> first__; })) ((IS_ENABLED(CONFIG_DRM_I915_PXP)0 && \ |
| 1014 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_pxp) && \ |
| 1015 | VDBOX_MASK(to_gt(dev_priv))({ unsigned int first__ = (VCS0); unsigned int count__ = (8); ((to_gt(dev_priv))->info.engine_mask & (((~0UL) >> (64 - (first__ + count__ - 1) - 1)) & ((~0UL) << ( first__)))) >> first__; })) |
| 1016 | |
| 1017 | #define HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.has_gmch) |
| 1018 | |
| 1019 | #define HAS_LSPCON(dev_priv)((((&(dev_priv)->__runtime)->display.ip.ver) >= ( 9) && ((&(dev_priv)->__runtime)->display.ip .ver) <= (10))) (IS_DISPLAY_VER(dev_priv, 9, 10)(((&(dev_priv)->__runtime)->display.ip.ver) >= ( 9) && ((&(dev_priv)->__runtime)->display.ip .ver) <= (10))) |
| 1020 | |
| 1021 | #define HAS_L3_CCS_READ(i915)((&(i915)->__info)->has_l3_ccs_read) (INTEL_INFO(i915)(&(i915)->__info)->has_l3_ccs_read) |
| 1022 | |
| 1023 | /* DPF == dynamic parity feature */ |
| 1024 | #define HAS_L3_DPF(dev_priv)((&(dev_priv)->__info)->has_l3_dpf) (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_l3_dpf) |
| 1025 | #define NUM_L3_SLICES(dev_priv)((IS_PLATFORM(dev_priv, INTEL_HASWELL) && (&(dev_priv )->__info)->gt == 3) ? 2 : ((&(dev_priv)->__info )->has_l3_dpf)) (IS_HSW_GT3(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (&(dev_priv )->__info)->gt == 3) ? \ |
| 1026 | 2 : HAS_L3_DPF(dev_priv)((&(dev_priv)->__info)->has_l3_dpf)) |
| 1027 | |
| 1028 | #define GT_FREQUENCY_MULTIPLIER50 50 |
| 1029 | #define GEN9_FREQ_SCALER3 3 |
| 1030 | |
| 1031 | #define INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__runtime)->pipe_mask)) (hweight8(RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->pipe_mask)) |
| 1032 | |
| 1033 | #define HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0) (RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->pipe_mask != 0) |
| 1034 | |
| 1035 | #define HAS_VRR(i915)(((&(i915)->__runtime)->display.ip.ver) >= 11) (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 11) |
| 1036 | |
| 1037 | #define HAS_ASYNC_FLIPS(i915)(((&(i915)->__runtime)->display.ip.ver) >= 5) (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 5) |
| 1038 | |
| 1039 | /* Only valid when HAS_DISPLAY() is true */ |
| 1040 | #define INTEL_DISPLAY_ENABLED(dev_priv)(({ int __ret = !!((!((&(dev_priv)->__runtime)->pipe_mask != 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__runtime)->pipe_mask != 0)" ")"); __builtin_expect(!!(__ret), 0); }), !(dev_priv)->params .disable_display && !intel_opregion_headless_sku(dev_priv )) \ |
| 1041 | (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv))({ int __ret = !!((!((&(dev_priv)->__runtime)->pipe_mask != 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(dev_priv)->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__runtime)->pipe_mask != 0)" ")"); __builtin_expect(!!(__ret), 0); }), \ |
| 1042 | !(dev_priv)->params.disable_display && \ |
| 1043 | !intel_opregion_headless_sku(dev_priv)) |
| 1044 | |
| 1045 | #define HAS_GUC_DEPRIVILEGE(dev_priv)((&(dev_priv)->__info)->has_guc_deprivilege) \ |
| 1046 | (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->has_guc_deprivilege) |
| 1047 | |
| 1048 | #define HAS_D12_PLANE_MINIMIZATION(dev_priv)(IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) || IS_PLATFORM(dev_priv , INTEL_ALDERLAKE_S)) (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) || \ |
| 1049 | IS_ALDERLAKE_S(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)) |
| 1050 | |
| 1051 | #define HAS_MBUS_JOINING(i915)(IS_PLATFORM(i915, INTEL_ALDERLAKE_P) || ((&(i915)->__runtime )->display.ip.ver) >= 14) (IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P) || DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 14) |
| 1052 | |
| 1053 | #define HAS_3D_PIPELINE(i915)((&(i915)->__info)->has_3d_pipeline) (INTEL_INFO(i915)(&(i915)->__info)->has_3d_pipeline) |
| 1054 | |
| 1055 | #define HAS_ONE_EU_PER_FUSE_BIT(i915)((&(i915)->__info)->has_one_eu_per_fuse_bit) (INTEL_INFO(i915)(&(i915)->__info)->has_one_eu_per_fuse_bit) |
| 1056 | |
| 1057 | /* intel_device_info.c */ |
| 1058 | static inline struct intel_device_info * |
| 1059 | mkwrite_device_info(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 1060 | { |
| 1061 | return (struct intel_device_info *)INTEL_INFO(dev_priv)(&(dev_priv)->__info); |
| 1062 | } |
| 1063 | |
| 1064 | static inline enum i915_map_type |
| 1065 | i915_coherent_map_type(struct drm_i915_privateinteldrm_softc *i915, |
| 1066 | struct drm_i915_gem_object *obj, bool_Bool always_coherent) |
| 1067 | { |
| 1068 | if (i915_gem_object_is_lmem(obj)) |
| 1069 | return I915_MAP_WC; |
| 1070 | if (HAS_LLC(i915)((&(i915)->__info)->has_llc) || always_coherent) |
| 1071 | return I915_MAP_WB; |
| 1072 | else |
| 1073 | return I915_MAP_WC; |
| 1074 | } |
| 1075 | |
| 1076 | #endif |