| File: | dev/ic/athn.c |
| Warning: | line 2053, column 3 Value stored to 'dtim_count' is never read |
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| 1 | /* $OpenBSD: athn.c,v 1.111 2021/04/15 18:25:43 stsp Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> |
| 5 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for any |
| 8 | * purpose with or without fee is hereby granted, provided that the above |
| 9 | * copyright notice and this permission notice appear in all copies. |
| 10 | * |
| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 18 | */ |
| 19 | |
| 20 | /* |
| 21 | * Driver for Atheros 802.11a/g/n chipsets. |
| 22 | */ |
| 23 | |
| 24 | #include "athn_usb.h" |
| 25 | #include "bpfilter.h" |
| 26 | |
| 27 | #include <sys/param.h> |
| 28 | #include <sys/sockio.h> |
| 29 | #include <sys/mbuf.h> |
| 30 | #include <sys/kernel.h> |
| 31 | #include <sys/socket.h> |
| 32 | #include <sys/systm.h> |
| 33 | #include <sys/malloc.h> |
| 34 | #include <sys/queue.h> |
| 35 | #include <sys/timeout.h> |
| 36 | #include <sys/conf.h> |
| 37 | #include <sys/device.h> |
| 38 | #include <sys/stdint.h> /* uintptr_t */ |
| 39 | #include <sys/endian.h> |
| 40 | |
| 41 | #include <machine/bus.h> |
| 42 | #include <machine/intr.h> |
| 43 | |
| 44 | #if NBPFILTER1 > 0 |
| 45 | #include <net/bpf.h> |
| 46 | #endif |
| 47 | #include <net/if.h> |
| 48 | #include <net/if_dl.h> |
| 49 | #include <net/if_media.h> |
| 50 | |
| 51 | #include <netinet/in.h> |
| 52 | #include <netinet/if_ether.h> |
| 53 | |
| 54 | #include <net80211/ieee80211_var.h> |
| 55 | #include <net80211/ieee80211_amrr.h> |
| 56 | #include <net80211/ieee80211_ra.h> |
| 57 | #include <net80211/ieee80211_radiotap.h> |
| 58 | |
| 59 | #include <dev/ic/athnreg.h> |
| 60 | #include <dev/ic/athnvar.h> |
| 61 | |
| 62 | #ifdef ATHN_DEBUG |
| 63 | int athn_debug = 0; |
| 64 | #endif |
| 65 | |
| 66 | void athn_radiotap_attach(struct athn_softc *); |
| 67 | void athn_get_chanlist(struct athn_softc *); |
| 68 | const char * athn_get_mac_name(struct athn_softc *); |
| 69 | const char * athn_get_rf_name(struct athn_softc *); |
| 70 | void athn_led_init(struct athn_softc *); |
| 71 | void athn_set_led(struct athn_softc *, int); |
| 72 | void athn_btcoex_init(struct athn_softc *); |
| 73 | void athn_btcoex_enable(struct athn_softc *); |
| 74 | void athn_btcoex_disable(struct athn_softc *); |
| 75 | void athn_set_rxfilter(struct athn_softc *, uint32_t); |
| 76 | void athn_get_chipid(struct athn_softc *); |
| 77 | int athn_reset_power_on(struct athn_softc *); |
| 78 | int athn_reset(struct athn_softc *, int); |
| 79 | void athn_init_pll(struct athn_softc *, |
| 80 | const struct ieee80211_channel *); |
| 81 | int athn_set_power_awake(struct athn_softc *); |
| 82 | void athn_set_power_sleep(struct athn_softc *); |
| 83 | void athn_write_serdes(struct athn_softc *, |
| 84 | const struct athn_serdes *); |
| 85 | void athn_config_pcie(struct athn_softc *); |
| 86 | void athn_config_nonpcie(struct athn_softc *); |
| 87 | int athn_set_chan(struct athn_softc *, struct ieee80211_channel *, |
| 88 | struct ieee80211_channel *); |
| 89 | int athn_switch_chan(struct athn_softc *, |
| 90 | struct ieee80211_channel *, struct ieee80211_channel *); |
| 91 | void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *); |
| 92 | void athn_reset_key(struct athn_softc *, int); |
| 93 | int athn_set_key(struct ieee80211com *, struct ieee80211_node *, |
| 94 | struct ieee80211_key *); |
| 95 | void athn_delete_key(struct ieee80211com *, struct ieee80211_node *, |
| 96 | struct ieee80211_key *); |
| 97 | void athn_iter_calib(void *, struct ieee80211_node *); |
| 98 | int athn_cap_noisefloor(struct athn_softc *, int); |
| 99 | int athn_nf_hist_mid(int *, int); |
| 100 | void athn_filter_noisefloor(struct athn_softc *); |
| 101 | void athn_start_noisefloor_calib(struct athn_softc *, int); |
| 102 | void athn_calib_to(void *); |
| 103 | int athn_init_calib(struct athn_softc *, |
| 104 | struct ieee80211_channel *, struct ieee80211_channel *); |
| 105 | uint8_t athn_chan2fbin(struct ieee80211_channel *); |
| 106 | int athn_interpolate(int, int, int, int, int); |
| 107 | void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, |
| 108 | int *); |
| 109 | void athn_init_dma(struct athn_softc *); |
| 110 | void athn_rx_start(struct athn_softc *); |
| 111 | void athn_inc_tx_trigger_level(struct athn_softc *); |
| 112 | int athn_stop_rx_dma(struct athn_softc *); |
| 113 | int athn_rx_abort(struct athn_softc *); |
| 114 | void athn_tx_reclaim(struct athn_softc *, int); |
| 115 | int athn_tx_pending(struct athn_softc *, int); |
| 116 | void athn_stop_tx_dma(struct athn_softc *, int); |
| 117 | int athn_txtime(struct athn_softc *, int, int, u_int); |
| 118 | void athn_set_sta_timers(struct athn_softc *); |
| 119 | void athn_set_hostap_timers(struct athn_softc *); |
| 120 | void athn_set_opmode(struct athn_softc *); |
| 121 | void athn_set_bss(struct athn_softc *, struct ieee80211_node *); |
| 122 | void athn_enable_interrupts(struct athn_softc *); |
| 123 | void athn_disable_interrupts(struct athn_softc *); |
| 124 | void athn_init_qos(struct athn_softc *); |
| 125 | int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *, |
| 126 | struct ieee80211_channel *, int); |
| 127 | struct ieee80211_node *athn_node_alloc(struct ieee80211com *); |
| 128 | void athn_newassoc(struct ieee80211com *, struct ieee80211_node *, |
| 129 | int); |
| 130 | int athn_media_change(struct ifnet *); |
| 131 | void athn_next_scan(void *); |
| 132 | int athn_newstate(struct ieee80211com *, enum ieee80211_state, |
| 133 | int); |
| 134 | void athn_updateedca(struct ieee80211com *); |
| 135 | int athn_clock_rate(struct athn_softc *); |
| 136 | int athn_chan_sifs(struct ieee80211_channel *); |
| 137 | void athn_setsifs(struct athn_softc *); |
| 138 | int athn_acktimeout(struct ieee80211_channel *, int); |
| 139 | void athn_setacktimeout(struct athn_softc *, |
| 140 | struct ieee80211_channel *, int); |
| 141 | void athn_setctstimeout(struct athn_softc *, |
| 142 | struct ieee80211_channel *, int); |
| 143 | void athn_setclockrate(struct athn_softc *); |
| 144 | void athn_updateslot(struct ieee80211com *); |
| 145 | void athn_start(struct ifnet *); |
| 146 | void athn_watchdog(struct ifnet *); |
| 147 | void athn_set_multi(struct athn_softc *); |
| 148 | int athn_ioctl(struct ifnet *, u_long, caddr_t); |
| 149 | int athn_init(struct ifnet *); |
| 150 | void athn_stop(struct ifnet *, int); |
| 151 | void athn_init_tx_queues(struct athn_softc *); |
| 152 | int32_t athn_ani_get_rssi(struct athn_softc *); |
| 153 | void athn_ani_ofdm_err_trigger(struct athn_softc *); |
| 154 | void athn_ani_cck_err_trigger(struct athn_softc *); |
| 155 | void athn_ani_lower_immunity(struct athn_softc *); |
| 156 | void athn_ani_restart(struct athn_softc *); |
| 157 | void athn_ani_monitor(struct athn_softc *); |
| 158 | |
| 159 | /* Extern functions. */ |
| 160 | int ar5416_attach(struct athn_softc *); |
| 161 | int ar9280_attach(struct athn_softc *); |
| 162 | int ar9285_attach(struct athn_softc *); |
| 163 | int ar9287_attach(struct athn_softc *); |
| 164 | int ar9380_attach(struct athn_softc *); |
| 165 | int ar5416_init_calib(struct athn_softc *, |
| 166 | struct ieee80211_channel *, struct ieee80211_channel *); |
| 167 | int ar9285_init_calib(struct athn_softc *, |
| 168 | struct ieee80211_channel *, struct ieee80211_channel *); |
| 169 | int ar9003_init_calib(struct athn_softc *); |
| 170 | void ar9285_pa_calib(struct athn_softc *); |
| 171 | void ar9271_pa_calib(struct athn_softc *); |
| 172 | void ar9287_1_3_enable_async_fifo(struct athn_softc *); |
| 173 | void ar9287_1_3_setup_async_fifo(struct athn_softc *); |
| 174 | void ar9003_reset_txsring(struct athn_softc *); |
| 175 | |
| 176 | struct cfdriver athn_cd = { |
| 177 | NULL((void *)0), "athn", DV_IFNET |
| 178 | }; |
| 179 | |
| 180 | void |
| 181 | athn_config_ht(struct athn_softc *sc) |
| 182 | { |
| 183 | struct ieee80211com *ic = &sc->sc_ic; |
| 184 | int i, ntxstreams, nrxstreams; |
| 185 | |
| 186 | if ((sc->flags & ATHN_FLAG_11N(1 << 11)) == 0) |
| 187 | return; |
| 188 | |
| 189 | /* Set HT capabilities. */ |
| 190 | ic->ic_htcaps = (IEEE80211_HTCAP_SMPS_DIS3 << |
| 191 | IEEE80211_HTCAP_SMPS_SHIFT2); |
| 192 | #ifdef notyet |
| 193 | ic->ic_htcaps |= IEEE80211_HTCAP_CBW20_400x00000002 | |
| 194 | IEEE80211_HTCAP_SGI400x00000040 | |
| 195 | IEEE80211_HTCAP_DSSSCCK400x00001000; |
| 196 | #endif |
| 197 | ic->ic_htxcaps = 0; |
| 198 | #ifdef notyet |
| 199 | if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140) || AR_SREV_9287_10_OR_LATER(sc)((sc)->mac_ver >= 0x180)) |
| 200 | ic->ic_htcaps |= IEEE80211_HTCAP_SGI200x00000020; |
| 201 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 202 | ic->ic_htcaps |= IEEE80211_HTCAP_LDPC0x00000001; |
| 203 | if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080)) { |
| 204 | ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC0x00000080; |
| 205 | ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT8; |
| 206 | } |
| 207 | #endif |
| 208 | ntxstreams = sc->ntxchains; |
| 209 | nrxstreams = sc->nrxchains; |
| 210 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 211 | ntxstreams = MIN(ntxstreams, 2)(((ntxstreams)<(2))?(ntxstreams):(2)); |
| 212 | nrxstreams = MIN(nrxstreams, 2)(((nrxstreams)<(2))?(nrxstreams):(2)); |
| 213 | } |
| 214 | /* Set supported HT rates. */ |
| 215 | if (ic->ic_userflags & IEEE80211_F_NOMIMO0x00000008) |
| 216 | ntxstreams = nrxstreams = 1; |
| 217 | memset(ic->ic_sup_mcs, 0, sizeof(ic->ic_sup_mcs))__builtin_memset((ic->ic_sup_mcs), (0), (sizeof(ic->ic_sup_mcs ))); |
| 218 | for (i = 0; i < nrxstreams; i++) |
| 219 | ic->ic_sup_mcs[i] = 0xff; |
| 220 | ic->ic_tx_mcs_set = IEEE80211_TX_MCS_SET_DEFINED0x01; |
| 221 | if (ntxstreams != nrxstreams) { |
| 222 | ic->ic_tx_mcs_set |= IEEE80211_TX_RX_MCS_NOT_EQUAL0x02; |
| 223 | ic->ic_tx_mcs_set |= (ntxstreams - 1) << 2; |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | int |
| 228 | athn_attach(struct athn_softc *sc) |
| 229 | { |
| 230 | struct ieee80211com *ic = &sc->sc_ic; |
| 231 | struct ifnet *ifp = &ic->ic_ific_ac.ac_if; |
| 232 | int error; |
| 233 | |
| 234 | /* Read hardware revision. */ |
| 235 | athn_get_chipid(sc); |
| 236 | |
| 237 | if ((error = athn_reset_power_on(sc)) != 0) { |
| 238 | printf("%s: could not reset chip\n", sc->sc_dev.dv_xname); |
| 239 | return (error); |
| 240 | } |
| 241 | |
| 242 | if ((error = athn_set_power_awake(sc)) != 0) { |
| 243 | printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); |
| 244 | return (error); |
| 245 | } |
| 246 | |
| 247 | if (AR_SREV_5416(sc)((sc)->mac_ver == 0x00d || (sc)->mac_ver == 0x00c) || AR_SREV_9160(sc)((sc)->mac_ver == 0x040)) |
| 248 | error = ar5416_attach(sc); |
| 249 | else if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080)) |
| 250 | error = ar9280_attach(sc); |
| 251 | else if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0)) |
| 252 | error = ar9285_attach(sc); |
| 253 | #if NATHN_USB1 > 0 |
| 254 | else if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 255 | error = ar9285_attach(sc); |
| 256 | #endif |
| 257 | else if (AR_SREV_9287(sc)((sc)->mac_ver == 0x180)) |
| 258 | error = ar9287_attach(sc); |
| 259 | else if (AR_SREV_9380(sc)((sc)->mac_ver == 0x1c0) || AR_SREV_9485(sc)((sc)->mac_ver == 0x240)) |
| 260 | error = ar9380_attach(sc); |
| 261 | else |
| 262 | error = ENOTSUP91; |
| 263 | if (error != 0) { |
| 264 | printf("%s: could not attach chip\n", sc->sc_dev.dv_xname); |
| 265 | return (error); |
| 266 | } |
| 267 | |
| 268 | /* We can put the chip in sleep state now. */ |
| 269 | athn_set_power_sleep(sc); |
| 270 | |
| 271 | if (!(sc->flags & ATHN_FLAG_USB(1 << 1))) { |
| 272 | error = sc->ops.dma_alloc(sc); |
| 273 | if (error != 0) { |
| 274 | printf("%s: could not allocate DMA resources\n", |
| 275 | sc->sc_dev.dv_xname); |
| 276 | return (error); |
| 277 | } |
| 278 | /* Steal one Tx buffer for beacons. */ |
| 279 | sc->bcnbuf = SIMPLEQ_FIRST(&sc->txbufs)((&sc->txbufs)->sqh_first); |
| 280 | SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list)do { if (((&sc->txbufs)->sqh_first = (&sc->txbufs )->sqh_first->bf_list.sqe_next) == ((void *)0)) (&sc ->txbufs)->sqh_last = &(&sc->txbufs)->sqh_first ; } while (0); |
| 281 | } |
| 282 | |
| 283 | if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) { |
| 284 | DPRINTF(("found RF switch connected to GPIO pin %d\n", |
| 285 | sc->rfsilent_pin)); |
| 286 | } |
| 287 | DPRINTF(("%d key cache entries\n", sc->kc_entries)); |
| 288 | /* |
| 289 | * In HostAP mode, the number of STAs that we can handle is |
| 290 | * limited by the number of entries in the HW key cache. |
| 291 | * TKIP keys would consume 2 entries in this cache but we |
| 292 | * only use the hardware crypto engine for CCMP. |
| 293 | */ |
| 294 | ic->ic_max_nnodes = sc->kc_entries - IEEE80211_WEP_NKID4; |
| 295 | if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE512) |
| 296 | ic->ic_max_nnodes = IEEE80211_CACHE_SIZE512; |
| 297 | |
| 298 | DPRINTF(("using %s loop power control\n", |
| 299 | (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed")); |
| 300 | |
| 301 | DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n", |
| 302 | sc->txchainmask, sc->rxchainmask)); |
| 303 | /* Count the number of bits set (in lowest 3 bits). */ |
| 304 | sc->ntxchains = |
| 305 | ((sc->txchainmask >> 2) & 1) + |
| 306 | ((sc->txchainmask >> 1) & 1) + |
| 307 | ((sc->txchainmask >> 0) & 1); |
| 308 | sc->nrxchains = |
| 309 | ((sc->rxchainmask >> 2) & 1) + |
| 310 | ((sc->rxchainmask >> 1) & 1) + |
| 311 | ((sc->rxchainmask >> 0) & 1); |
| 312 | |
| 313 | if (AR_SINGLE_CHIP(sc)((sc)->mac_ver >= 0x080)) { |
| 314 | printf("%s: %s rev %d (%dT%dR), ROM rev %d, address %s\n", |
| 315 | sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, |
| 316 | sc->ntxchains, sc->nrxchains, sc->eep_rev, |
| 317 | ether_sprintf(ic->ic_myaddr)); |
| 318 | } else { |
| 319 | printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, " |
| 320 | "address %s\n", |
| 321 | sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, |
| 322 | athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains, |
| 323 | sc->eep_rev, ether_sprintf(ic->ic_myaddr)); |
| 324 | } |
| 325 | |
| 326 | timeout_set(&sc->scan_to, athn_next_scan, sc); |
| 327 | timeout_set(&sc->calib_to, athn_calib_to, sc); |
| 328 | |
| 329 | sc->amrr.amrr_min_success_threshold = 1; |
| 330 | sc->amrr.amrr_max_success_threshold = 15; |
| 331 | |
| 332 | ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ |
| 333 | ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ |
| 334 | ic->ic_state = IEEE80211_S_INIT; |
| 335 | |
| 336 | /* Set device capabilities. */ |
| 337 | ic->ic_caps = |
| 338 | IEEE80211_C_WEP0x00000001 | /* WEP. */ |
| 339 | IEEE80211_C_RSN0x00001000 | /* WPA/RSN. */ |
| 340 | #ifndef IEEE80211_STA_ONLY |
| 341 | IEEE80211_C_HOSTAP0x00000008 | /* Host AP mode supported. */ |
| 342 | IEEE80211_C_APPMGT0x00000020 | /* Host AP power saving supported. */ |
| 343 | #endif |
| 344 | IEEE80211_C_MONITOR0x00000200 | /* Monitor mode supported. */ |
| 345 | IEEE80211_C_SHSLOT0x00000080 | /* Short slot time supported. */ |
| 346 | IEEE80211_C_SHPREAMBLE0x00000100 | /* Short preamble supported. */ |
| 347 | IEEE80211_C_PMGT0x00000004; /* Power saving supported. */ |
| 348 | |
| 349 | athn_config_ht(sc); |
| 350 | |
| 351 | /* Set supported rates. */ |
| 352 | if (sc->flags & ATHN_FLAG_11G(1 << 10)) { |
| 353 | ic->ic_sup_rates[IEEE80211_MODE_11B] = |
| 354 | ieee80211_std_rateset_11b; |
| 355 | ic->ic_sup_rates[IEEE80211_MODE_11G] = |
| 356 | ieee80211_std_rateset_11g; |
| 357 | } |
| 358 | if (sc->flags & ATHN_FLAG_11A(1 << 9)) { |
| 359 | ic->ic_sup_rates[IEEE80211_MODE_11A] = |
| 360 | ieee80211_std_rateset_11a; |
| 361 | } |
| 362 | |
| 363 | /* Get the list of authorized/supported channels. */ |
| 364 | athn_get_chanlist(sc); |
| 365 | |
| 366 | /* IBSS channel undefined for now. */ |
| 367 | ic->ic_ibss_chan = &ic->ic_channels[0]; |
| 368 | |
| 369 | ifp->if_softc = sc; |
| 370 | ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000; |
| 371 | ifp->if_ioctl = athn_ioctl; |
| 372 | ifp->if_start = athn_start; |
| 373 | ifp->if_watchdog = athn_watchdog; |
| 374 | memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ)__builtin_memcpy((ifp->if_xname), (sc->sc_dev.dv_xname) , (16)); |
| 375 | |
| 376 | if_attach(ifp); |
| 377 | ieee80211_ifattach(ifp); |
| 378 | ic->ic_node_alloc = athn_node_alloc; |
| 379 | ic->ic_newassoc = athn_newassoc; |
| 380 | ic->ic_updateslot = athn_updateslot; |
| 381 | ic->ic_updateedca = athn_updateedca; |
| 382 | ic->ic_set_key = athn_set_key; |
| 383 | ic->ic_delete_key = athn_delete_key; |
| 384 | |
| 385 | /* Override 802.11 state transition machine. */ |
| 386 | sc->sc_newstate = ic->ic_newstate; |
| 387 | ic->ic_newstate = athn_newstate; |
| 388 | ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status); |
| 389 | |
| 390 | #if NBPFILTER1 > 0 |
| 391 | athn_radiotap_attach(sc); |
| 392 | #endif |
| 393 | |
| 394 | return (0); |
| 395 | } |
| 396 | |
| 397 | void |
| 398 | athn_detach(struct athn_softc *sc) |
| 399 | { |
| 400 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; |
| 401 | int qid; |
| 402 | |
| 403 | timeout_del(&sc->scan_to); |
| 404 | timeout_del(&sc->calib_to); |
| 405 | |
| 406 | if (!(sc->flags & ATHN_FLAG_USB(1 << 1))) { |
| 407 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 408 | athn_tx_reclaim(sc, qid); |
| 409 | |
| 410 | /* Free Tx/Rx DMA resources. */ |
| 411 | sc->ops.dma_free(sc); |
| 412 | } |
| 413 | /* Free ROM copy. */ |
| 414 | if (sc->eep != NULL((void *)0)) |
| 415 | free(sc->eep, M_DEVBUF2, 0); |
| 416 | |
| 417 | ieee80211_ifdetach(ifp); |
| 418 | if_detach(ifp); |
| 419 | } |
| 420 | |
| 421 | #if NBPFILTER1 > 0 |
| 422 | /* |
| 423 | * Attach the interface to 802.11 radiotap. |
| 424 | */ |
| 425 | void |
| 426 | athn_radiotap_attach(struct athn_softc *sc) |
| 427 | { |
| 428 | bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_ific_ac.ac_if, DLT_IEEE802_11_RADIO127, |
| 429 | sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN64); |
| 430 | |
| 431 | sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); |
| 432 | sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len)); |
| 433 | sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_TSFT | 1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL | 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | 1 << IEEE80211_RADIOTAP_ANTENNA))); |
| 434 | |
| 435 | sc->sc_txtap_len = sizeof(sc->sc_txtapu); |
| 436 | sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len)); |
| 437 | sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL ))); |
| 438 | } |
| 439 | #endif |
| 440 | |
| 441 | void |
| 442 | athn_get_chanlist(struct athn_softc *sc) |
| 443 | { |
| 444 | struct ieee80211com *ic = &sc->sc_ic; |
| 445 | uint8_t chan; |
| 446 | int i; |
| 447 | |
| 448 | if (sc->flags & ATHN_FLAG_11G(1 << 10)) { |
| 449 | for (i = 1; i <= 14; i++) { |
| 450 | chan = i; |
| 451 | ic->ic_channels[chan].ic_freq = |
| 452 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ0x0080); |
| 453 | ic->ic_channels[chan].ic_flags = |
| 454 | IEEE80211_CHAN_CCK0x0020 | IEEE80211_CHAN_OFDM0x0040 | |
| 455 | IEEE80211_CHAN_DYN0x0400 | IEEE80211_CHAN_2GHZ0x0080; |
| 456 | if (sc->flags & ATHN_FLAG_11N(1 << 11)) |
| 457 | ic->ic_channels[chan].ic_flags |= |
| 458 | IEEE80211_CHAN_HT0x2000; |
| 459 | } |
| 460 | } |
| 461 | if (sc->flags & ATHN_FLAG_11A(1 << 9)) { |
| 462 | for (i = 0; i < nitems(athn_5ghz_chans)(sizeof((athn_5ghz_chans)) / sizeof((athn_5ghz_chans)[0])); i++) { |
| 463 | chan = athn_5ghz_chans[i]; |
| 464 | ic->ic_channels[chan].ic_freq = |
| 465 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ0x0100); |
| 466 | ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A(0x0100 | 0x0040); |
| 467 | if (sc->flags & ATHN_FLAG_11N(1 << 11)) |
| 468 | ic->ic_channels[chan].ic_flags |= |
| 469 | IEEE80211_CHAN_HT0x2000; |
| 470 | } |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | void |
| 475 | athn_rx_start(struct athn_softc *sc) |
| 476 | { |
| 477 | struct ieee80211com *ic = &sc->sc_ic; |
| 478 | uint32_t rfilt; |
| 479 | |
| 480 | /* Setup Rx DMA descriptors. */ |
| 481 | sc->ops.rx_enable(sc); |
| 482 | |
| 483 | /* Set Rx filter. */ |
| 484 | rfilt = AR_RX_FILTER_UCAST0x00000001 | AR_RX_FILTER_BCAST0x00000004 | AR_RX_FILTER_MCAST0x00000002; |
| 485 | /* Want Compressed Block Ack Requests. */ |
| 486 | rfilt |= AR_RX_FILTER_COMPR_BAR0x00000400; |
| 487 | rfilt |= AR_RX_FILTER_BEACON0x00000010; |
| 488 | if (ic->ic_opmode != IEEE80211_M_STA) { |
| 489 | rfilt |= AR_RX_FILTER_PROBEREQ0x00000080; |
| 490 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
| 491 | rfilt |= AR_RX_FILTER_PROM0x00000020; |
| 492 | #ifndef IEEE80211_STA_ONLY |
| 493 | if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080) && |
| 494 | ic->ic_opmode == IEEE80211_M_HOSTAP) |
| 495 | rfilt |= AR_RX_FILTER_PSPOLL0x00004000; |
| 496 | #endif |
| 497 | } |
| 498 | athn_set_rxfilter(sc, rfilt); |
| 499 | |
| 500 | /* Set BSSID mask. */ |
| 501 | AR_WRITE(sc, AR_BSSMSKL, 0xffffffff)(sc)->ops.write((sc), (0x80e0), (0xffffffff)); |
| 502 | AR_WRITE(sc, AR_BSSMSKU, 0xffff)(sc)->ops.write((sc), (0x80e4), (0xffff)); |
| 503 | |
| 504 | athn_set_opmode(sc); |
| 505 | |
| 506 | /* Set multicast filter. */ |
| 507 | AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff)(sc)->ops.write((sc), (0x8040), (0xffffffff)); |
| 508 | AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff)(sc)->ops.write((sc), (0x8044), (0xffffffff)); |
| 509 | |
| 510 | AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0)); |
| 511 | AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0)); |
| 512 | AR_WRITE(sc, AR_MIBC, 0)(sc)->ops.write((sc), (0x0040), (0)); |
| 513 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000)); |
| 514 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000)); |
| 515 | |
| 516 | /* XXX ANI. */ |
| 517 | AR_WRITE(sc, AR_PHY_ERR_1, 0)(sc)->ops.write((sc), (0x812c), (0)); |
| 518 | AR_WRITE(sc, AR_PHY_ERR_2, 0)(sc)->ops.write((sc), (0x8134), (0)); |
| 519 | |
| 520 | /* Disable HW crypto for now. */ |
| 521 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) | (0x00000008 | 0x00000010))); |
| 522 | |
| 523 | /* Start PCU Rx. */ |
| 524 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) & ~(0x00000020 | 0x02000000))); |
| 525 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 526 | } |
| 527 | |
| 528 | void |
| 529 | athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) |
| 530 | { |
| 531 | AR_WRITE(sc, AR_RX_FILTER, rfilt)(sc)->ops.write((sc), (0x803c), (rfilt)); |
| 532 | |
| 533 | #ifdef notyet |
| 534 | reg = AR_READ(sc, AR_PHY_ERR)(sc)->ops.read((sc), (0x810c)); |
| 535 | reg &= (AR_PHY_ERR_RADAR0x00000020 | AR_PHY_ERR_OFDM_TIMING0x00020000 | |
| 536 | AR_PHY_ERR_CCK_TIMING0x02000000); |
| 537 | AR_WRITE(sc, AR_PHY_ERR, reg)(sc)->ops.write((sc), (0x810c), (reg)); |
| 538 | if (reg != 0) |
| 539 | AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), ( 0x0034)) | (0x00000010))); |
| 540 | else |
| 541 | AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), ( 0x0034)) & ~(0x00000010))); |
| 542 | #else |
| 543 | AR_WRITE(sc, AR_PHY_ERR, 0)(sc)->ops.write((sc), (0x810c), (0)); |
| 544 | AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), ( 0x0034)) & ~(0x00000010))); |
| 545 | #endif |
| 546 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 547 | } |
| 548 | |
| 549 | int |
| 550 | athn_intr(void *xsc) |
| 551 | { |
| 552 | struct athn_softc *sc = xsc; |
| 553 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; |
| 554 | |
| 555 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) != |
| 556 | (IFF_UP0x1 | IFF_RUNNING0x40)) |
| 557 | return (0); |
| 558 | |
| 559 | return (sc->ops.intr(sc)); |
| 560 | } |
| 561 | |
| 562 | void |
| 563 | athn_get_chipid(struct athn_softc *sc) |
| 564 | { |
| 565 | uint32_t reg; |
| 566 | |
| 567 | reg = AR_READ(sc, AR_SREV)(sc)->ops.read((sc), (0x4020)); |
| 568 | if (MS(reg, AR_SREV_ID)(((uint32_t)(reg) & 0x000000ff) >> 0) == 0xff) { |
| 569 | sc->mac_ver = MS(reg, AR_SREV_VERSION2)(((uint32_t)(reg) & 0xfffc0000) >> 12); |
| 570 | sc->mac_rev = MS(reg, AR_SREV_REVISION2)(((uint32_t)(reg) & 0x00000f00) >> 8); |
| 571 | if (!(reg & AR_SREV_TYPE2_HOST_MODE0x00002000)) |
| 572 | sc->flags |= ATHN_FLAG_PCIE(1 << 0); |
| 573 | } else { |
| 574 | sc->mac_ver = MS(reg, AR_SREV_VERSION)(((uint32_t)(reg) & 0x000000f0) >> 4); |
| 575 | sc->mac_rev = MS(reg, AR_SREV_REVISION)(((uint32_t)(reg) & 0x00000007) >> 0); |
| 576 | if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE0x00c) |
| 577 | sc->flags |= ATHN_FLAG_PCIE(1 << 0); |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | const char * |
| 582 | athn_get_mac_name(struct athn_softc *sc) |
| 583 | { |
| 584 | switch (sc->mac_ver) { |
| 585 | case AR_SREV_VERSION_5416_PCI0x00d: |
| 586 | return ("AR5416"); |
| 587 | case AR_SREV_VERSION_5416_PCIE0x00c: |
| 588 | return ("AR5418"); |
| 589 | case AR_SREV_VERSION_91600x040: |
| 590 | return ("AR9160"); |
| 591 | case AR_SREV_VERSION_92800x080: |
| 592 | return ("AR9280"); |
| 593 | case AR_SREV_VERSION_92850x0c0: |
| 594 | return ("AR9285"); |
| 595 | case AR_SREV_VERSION_92710x140: |
| 596 | return ("AR9271"); |
| 597 | case AR_SREV_VERSION_92870x180: |
| 598 | return ("AR9287"); |
| 599 | case AR_SREV_VERSION_93800x1c0: |
| 600 | return ("AR9380"); |
| 601 | case AR_SREV_VERSION_94850x240: |
| 602 | return ("AR9485"); |
| 603 | } |
| 604 | return ("unknown"); |
| 605 | } |
| 606 | |
| 607 | /* |
| 608 | * Return RF chip name (not for single-chip solutions). |
| 609 | */ |
| 610 | const char * |
| 611 | athn_get_rf_name(struct athn_softc *sc) |
| 612 | { |
| 613 | KASSERT(!AR_SINGLE_CHIP(sc))((!((sc)->mac_ver >= 0x080)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/ic/athn.c", 613, "!AR_SINGLE_CHIP(sc)")); |
| 614 | |
| 615 | switch (sc->rf_rev) { |
| 616 | case AR_RAD5133_SREV_MAJOR0xc0: /* Dual-band 3T3R. */ |
| 617 | return ("AR5133"); |
| 618 | case AR_RAD2133_SREV_MAJOR0xd0: /* Single-band 3T3R. */ |
| 619 | return ("AR2133"); |
| 620 | case AR_RAD5122_SREV_MAJOR0xe0: /* Dual-band 2T2R. */ |
| 621 | return ("AR5122"); |
| 622 | case AR_RAD2122_SREV_MAJOR0xf0: /* Single-band 2T2R. */ |
| 623 | return ("AR2122"); |
| 624 | } |
| 625 | return ("unknown"); |
| 626 | } |
| 627 | |
| 628 | int |
| 629 | athn_reset_power_on(struct athn_softc *sc) |
| 630 | { |
| 631 | int ntries; |
| 632 | |
| 633 | /* Set force wake. */ |
| 634 | AR_WRITE(sc, AR_RTC_FORCE_WAKE,(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002)) |
| 635 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT)(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002)); |
| 636 | |
| 637 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 638 | /* Make sure no DMA is active by doing an AHB reset. */ |
| 639 | AR_WRITE(sc, AR_RC, AR_RC_AHB)(sc)->ops.write((sc), (0x4000), (0x00000001)); |
| 640 | } |
| 641 | /* RTC reset and clear. */ |
| 642 | AR_WRITE(sc, AR_RTC_RESET, 0)(sc)->ops.write((sc), (0x7040), (0)); |
| 643 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 644 | DELAY(2)(*delay_func)(2); |
| 645 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 646 | AR_WRITE(sc, AR_RC, 0)(sc)->ops.write((sc), (0x4000), (0)); |
| 647 | AR_WRITE(sc, AR_RTC_RESET, 1)(sc)->ops.write((sc), (0x7040), (1)); |
| 648 | |
| 649 | /* Poll until RTC is ON. */ |
| 650 | for (ntries = 0; ntries < 1000; ntries++) { |
| 651 | if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) == |
| 652 | AR_RTC_STATUS_ON0x00000002) |
| 653 | break; |
| 654 | DELAY(10)(*delay_func)(10); |
| 655 | } |
| 656 | if (ntries == 1000) { |
| 657 | DPRINTF(("RTC not waking up\n")); |
| 658 | return (ETIMEDOUT60); |
| 659 | } |
| 660 | return (athn_reset(sc, 0)); |
| 661 | } |
| 662 | |
| 663 | int |
| 664 | athn_reset(struct athn_softc *sc, int cold) |
| 665 | { |
| 666 | int ntries; |
| 667 | |
| 668 | /* Set force wake. */ |
| 669 | AR_WRITE(sc, AR_RTC_FORCE_WAKE,(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002)) |
| 670 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT)(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002)); |
| 671 | |
| 672 | if (AR_READ(sc, AR_INTR_SYNC_CAUSE)(sc)->ops.read((sc), (0x4028)) & |
| 673 | (AR_INTR_SYNC_LOCAL_TIMEOUT0x00002000 | AR_INTR_SYNC_RADM_CPL_TIMEOUT0x00001000)) { |
| 674 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x402c), (0)); |
| 675 | AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |(sc)->ops.write((sc), (0x4000), (0x00000100 | (!((sc)-> mac_ver >= 0x1c0) ? 0x00000001 : 0))) |
| 676 | (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0))(sc)->ops.write((sc), (0x4000), (0x00000100 | (!((sc)-> mac_ver >= 0x1c0) ? 0x00000001 : 0))); |
| 677 | } else if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 678 | AR_WRITE(sc, AR_RC, AR_RC_AHB)(sc)->ops.write((sc), (0x4000), (0x00000001)); |
| 679 | |
| 680 | AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |(sc)->ops.write((sc), (0x7000), (0x00000001 | (cold ? 0x00000002 : 0))) |
| 681 | (cold ? AR_RTC_RC_MAC_COLD : 0))(sc)->ops.write((sc), (0x7000), (0x00000001 | (cold ? 0x00000002 : 0))); |
| 682 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 683 | DELAY(50)(*delay_func)(50); |
| 684 | AR_WRITE(sc, AR_RTC_RC, 0)(sc)->ops.write((sc), (0x7000), (0)); |
| 685 | for (ntries = 0; ntries < 1000; ntries++) { |
| 686 | if (!(AR_READ(sc, AR_RTC_RC)(sc)->ops.read((sc), (0x7000)) & |
| 687 | (AR_RTC_RC_MAC_WARM0x00000001 | AR_RTC_RC_MAC_COLD0x00000002))) |
| 688 | break; |
| 689 | DELAY(10)(*delay_func)(10); |
| 690 | } |
| 691 | if (ntries == 1000) { |
| 692 | DPRINTF(("RTC stuck in MAC reset\n")); |
| 693 | return (ETIMEDOUT60); |
| 694 | } |
| 695 | AR_WRITE(sc, AR_RC, 0)(sc)->ops.write((sc), (0x4000), (0)); |
| 696 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 697 | return (0); |
| 698 | } |
| 699 | |
| 700 | int |
| 701 | athn_set_power_awake(struct athn_softc *sc) |
| 702 | { |
| 703 | int ntries, error; |
| 704 | |
| 705 | /* Do a Power-On-Reset if shutdown. */ |
| 706 | if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) == |
| 707 | AR_RTC_STATUS_SHUTDOWN0x00000001) { |
| 708 | if ((error = athn_reset_power_on(sc)) != 0) |
| 709 | return (error); |
| 710 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 711 | athn_init_pll(sc, NULL((void *)0)); |
| 712 | } |
| 713 | AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), ( 0x704c)) | (0x00000001))); |
| 714 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 715 | DELAY(50)(*delay_func)(50); /* Give chip the chance to awake. */ |
| 716 | |
| 717 | /* Poll until RTC is ON. */ |
| 718 | for (ntries = 0; ntries < 4000; ntries++) { |
| 719 | if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) == |
| 720 | AR_RTC_STATUS_ON0x00000002) |
| 721 | break; |
| 722 | DELAY(50)(*delay_func)(50); |
| 723 | AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), ( 0x704c)) | (0x00000001))); |
| 724 | } |
| 725 | if (ntries == 4000) { |
| 726 | DPRINTF(("RTC not waking up\n")); |
| 727 | return (ETIMEDOUT60); |
| 728 | } |
| 729 | |
| 730 | AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), ( 0x8004)) & ~(0x00040000))); |
| 731 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 732 | return (0); |
| 733 | } |
| 734 | |
| 735 | void |
| 736 | athn_set_power_sleep(struct athn_softc *sc) |
| 737 | { |
| 738 | AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), ( 0x8004)) | (0x00040000))); |
| 739 | /* Allow the MAC to go to sleep. */ |
| 740 | AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), ( 0x704c)) & ~(0x00000001))); |
| 741 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 742 | AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF)(sc)->ops.write((sc), (0x4000), (0x00000001 | 0x00000100)); |
| 743 | /* |
| 744 | * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode |
| 745 | * results in high power consumption on AR5416 chipsets. |
| 746 | */ |
| 747 | if (!AR_SREV_5416(sc)((sc)->mac_ver == 0x00d || (sc)->mac_ver == 0x00c) && !AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 748 | AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN)(sc)->ops.write((sc), (0x7040), ((sc)->ops.read((sc), ( 0x7040)) & ~(0x00000001))); |
| 749 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 750 | } |
| 751 | |
| 752 | void |
| 753 | athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) |
| 754 | { |
| 755 | uint32_t pll; |
| 756 | |
| 757 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 758 | if (AR_SREV_9485(sc)((sc)->mac_ver == 0x240)) |
| 759 | AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666)(sc)->ops.write((sc), (0x703c), (0x886666)); |
| 760 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5)(((uint32_t)(0x5) << 10) & 0x00003c00); |
| 761 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c)(((uint32_t)(0x2c) << 0) & 0x000003ff); |
| 762 | } else if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080)) { |
| 763 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05)(((uint32_t)(0x05) << 10) & 0x00003c00); |
| 764 | if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) { |
| 765 | if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK(1 << 4)) |
| 766 | pll = 0x142c; |
| 767 | else if (AR_SREV_9280_20(sc)(((sc)->mac_ver == 0x080) && (sc)->mac_rev >= 1)) |
| 768 | pll = 0x2850; |
| 769 | else |
| 770 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x28)(((uint32_t)(0x28) << 0) & 0x000003ff); |
| 771 | } else |
| 772 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c)(((uint32_t)(0x2c) << 0) & 0x000003ff); |
| 773 | } else if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) { |
| 774 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05)(((uint32_t)(0x05) << 10) & 0x00003c00); |
| 775 | if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) |
| 776 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x50)(((uint32_t)(0x50) << 0) & 0x000003ff); |
| 777 | else |
| 778 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x58)(((uint32_t)(0x58) << 0) & 0x000003ff); |
| 779 | } else { |
| 780 | pll = AR_RTC_PLL_REFDIV_50x000000c0 | AR_RTC_PLL_DIV20x00000020; |
| 781 | if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) |
| 782 | pll |= SM(AR_RTC_PLL_DIV, 0x0a)(((uint32_t)(0x0a) << 0) & 0x0000001f); |
| 783 | else |
| 784 | pll |= SM(AR_RTC_PLL_DIV, 0x0b)(((uint32_t)(0x0b) << 0) & 0x0000001f); |
| 785 | } |
| 786 | DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll)); |
| 787 | AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll)(sc)->ops.write((sc), (0x7014), (pll)); |
| 788 | if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) { |
| 789 | /* Switch core clock to 117MHz. */ |
| 790 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 791 | DELAY(500)(*delay_func)(500); |
| 792 | AR_WRITE(sc, AR9271_CLOCK_CONTROL, 0x304)(sc)->ops.write((sc), (0x050040), (0x304)); |
| 793 | } |
| 794 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 795 | DELAY(100)(*delay_func)(100); |
| 796 | AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK)(sc)->ops.write((sc), (0x7048), (0x00000002)); |
| 797 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 798 | } |
| 799 | |
| 800 | void |
| 801 | athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) |
| 802 | { |
| 803 | int i; |
| 804 | |
| 805 | /* Write sequence to Serializer/Deserializer. */ |
| 806 | for (i = 0; i < serdes->nvals; i++) |
| 807 | AR_WRITE(sc, serdes->regs[i], serdes->vals[i])(sc)->ops.write((sc), (serdes->regs[i]), (serdes->vals [i])); |
| 808 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 809 | } |
| 810 | |
| 811 | void |
| 812 | athn_config_pcie(struct athn_softc *sc) |
| 813 | { |
| 814 | /* Disable PLL when in L0s as well as receiver clock when in L1. */ |
| 815 | athn_write_serdes(sc, sc->serdes); |
| 816 | |
| 817 | DELAY(1000)(*delay_func)(1000); |
| 818 | /* Allow forcing of PCIe core into L1 state. */ |
| 819 | AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA)(sc)->ops.write((sc), (0x4014), ((sc)->ops.read((sc), ( 0x4014)) | (0x00080000))); |
| 820 | |
| 821 | #ifndef ATHN_PCIE_WAEN |
| 822 | AR_WRITE(sc, AR_WA, sc->workaround)(sc)->ops.write((sc), (0x4004), (sc->workaround)); |
| 823 | #else |
| 824 | AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN)(sc)->ops.write((sc), (0x4004), (ATHN_PCIE_WAEN)); |
| 825 | #endif |
| 826 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 827 | } |
| 828 | |
| 829 | /* |
| 830 | * Serializer/Deserializer programming for non-PCIe devices. |
| 831 | */ |
| 832 | static const uint32_t ar_nonpcie_serdes_regs[] = { |
| 833 | AR_PCIE_SERDES0x4040, |
| 834 | AR_PCIE_SERDES0x4040, |
| 835 | AR_PCIE_SERDES0x4040, |
| 836 | AR_PCIE_SERDES0x4040, |
| 837 | AR_PCIE_SERDES0x4040, |
| 838 | AR_PCIE_SERDES0x4040, |
| 839 | AR_PCIE_SERDES0x4040, |
| 840 | AR_PCIE_SERDES0x4040, |
| 841 | AR_PCIE_SERDES0x4040, |
| 842 | AR_PCIE_SERDES20x4044, |
| 843 | }; |
| 844 | |
| 845 | static const uint32_t ar_nonpcie_serdes_vals[] = { |
| 846 | 0x9248fc00, |
| 847 | 0x24924924, |
| 848 | 0x28000029, |
| 849 | 0x57160824, |
| 850 | 0x25980579, |
| 851 | 0x00000000, |
| 852 | 0x1aaabe40, |
| 853 | 0xbe105554, |
| 854 | 0x000e1007, |
| 855 | 0x00000000 |
| 856 | }; |
| 857 | |
| 858 | static const struct athn_serdes ar_nonpcie_serdes = { |
| 859 | nitems(ar_nonpcie_serdes_vals)(sizeof((ar_nonpcie_serdes_vals)) / sizeof((ar_nonpcie_serdes_vals )[0])), |
| 860 | ar_nonpcie_serdes_regs, |
| 861 | ar_nonpcie_serdes_vals |
| 862 | }; |
| 863 | |
| 864 | void |
| 865 | athn_config_nonpcie(struct athn_softc *sc) |
| 866 | { |
| 867 | athn_write_serdes(sc, &ar_nonpcie_serdes); |
| 868 | } |
| 869 | |
| 870 | int |
| 871 | athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c, |
| 872 | struct ieee80211_channel *extc) |
| 873 | { |
| 874 | struct athn_ops *ops = &sc->ops; |
| 875 | int error, qid; |
| 876 | |
| 877 | /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ |
| 878 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 879 | if (athn_tx_pending(sc, qid)) |
| 880 | return (EBUSY16); |
| 881 | |
| 882 | /* Request RF Bus grant. */ |
| 883 | if ((error = ops->rf_bus_request(sc)) != 0) |
| 884 | return (error); |
| 885 | |
| 886 | ops->set_phy(sc, c, extc); |
| 887 | |
| 888 | /* Change the synthesizer. */ |
| 889 | if ((error = ops->set_synth(sc, c, extc)) != 0) |
| 890 | return (error); |
| 891 | |
| 892 | sc->curchan = c; |
| 893 | sc->curchanext = extc; |
| 894 | |
| 895 | /* Set transmit power values for new channel. */ |
| 896 | ops->set_txpower(sc, c, extc); |
| 897 | |
| 898 | /* Release the RF Bus grant. */ |
| 899 | ops->rf_bus_release(sc); |
| 900 | |
| 901 | /* Write delta slope coeffs for modes where OFDM may be used. */ |
| 902 | if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) |
| 903 | ops->set_delta_slope(sc, c, extc); |
| 904 | |
| 905 | ops->spur_mitigate(sc, c, extc); |
| 906 | |
| 907 | return (0); |
| 908 | } |
| 909 | |
| 910 | int |
| 911 | athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c, |
| 912 | struct ieee80211_channel *extc) |
| 913 | { |
| 914 | int error, qid; |
| 915 | |
| 916 | /* Disable interrupts. */ |
| 917 | athn_disable_interrupts(sc); |
| 918 | |
| 919 | /* Stop all Tx queues. */ |
| 920 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 921 | athn_stop_tx_dma(sc, qid); |
| 922 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 923 | athn_tx_reclaim(sc, qid); |
| 924 | |
| 925 | /* Stop Rx. */ |
| 926 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) | (0x00000020 | 0x02000000))); |
| 927 | AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC)(sc)->ops.write((sc), (0x0040), (0x00000002)); |
| 928 | AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC)(sc)->ops.write((sc), (0x0040), (0x00000004)); |
| 929 | AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0)); |
| 930 | AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0)); |
| 931 | athn_set_rxfilter(sc, 0); |
| 932 | error = athn_stop_rx_dma(sc); |
| 933 | if (error != 0) |
| 934 | goto reset; |
| 935 | |
| 936 | #ifdef notyet |
| 937 | /* AR9280 needs a full reset. */ |
| 938 | if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080)) |
| 939 | #endif |
| 940 | goto reset; |
| 941 | |
| 942 | /* If band or bandwidth changes, we need to do a full reset. */ |
| 943 | if (c->ic_flags != sc->curchan->ic_flags || |
| 944 | ((extc != NULL((void *)0)) ^ (sc->curchanext != NULL((void *)0)))) { |
| 945 | DPRINTFN(2, ("channel band switch\n")); |
| 946 | goto reset; |
| 947 | } |
| 948 | error = athn_set_power_awake(sc); |
| 949 | if (error != 0) |
| 950 | goto reset; |
| 951 | |
| 952 | error = athn_set_chan(sc, c, extc); |
| 953 | if (error != 0) { |
| 954 | reset: /* Error found, try a full reset. */ |
| 955 | DPRINTFN(3, ("needs a full reset\n")); |
| 956 | error = athn_hw_reset(sc, c, extc, 0); |
| 957 | if (error != 0) /* Hopeless case. */ |
| 958 | return (error); |
| 959 | } |
| 960 | athn_rx_start(sc); |
| 961 | |
| 962 | /* Re-enable interrupts. */ |
| 963 | athn_enable_interrupts(sc); |
| 964 | return (0); |
| 965 | } |
| 966 | |
| 967 | void |
| 968 | athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) |
| 969 | { |
| 970 | #define COEFF_SCALE_SHIFT 24 |
| 971 | uint32_t exp, man; |
| 972 | |
| 973 | /* exponent = 14 - floor(log2(coeff)) */ |
| 974 | for (exp = 31; exp > 0; exp--) |
| 975 | if (coeff & (1 << exp)) |
| 976 | break; |
| 977 | exp = 14 - (exp - COEFF_SCALE_SHIFT); |
| 978 | |
| 979 | /* mantissa = floor(coeff * 2^exponent + 0.5) */ |
| 980 | man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); |
| 981 | |
| 982 | *mantissa = man >> (COEFF_SCALE_SHIFT - exp); |
| 983 | *exponent = exp - 16; |
| 984 | #undef COEFF_SCALE_SHIFT |
| 985 | } |
| 986 | |
| 987 | void |
| 988 | athn_reset_key(struct athn_softc *sc, int entry) |
| 989 | { |
| 990 | /* |
| 991 | * NB: Key cache registers access special memory area that requires |
| 992 | * two 32-bit writes to actually update the values in the internal |
| 993 | * memory. Consequently, writes must be grouped by pair. |
| 994 | * |
| 995 | * All writes to registers with an offset of 0x0 or 0x8 write to a |
| 996 | * temporary register. A write to a register with an offset of 0x4 |
| 997 | * or 0xc writes concatenates the written value with the value in |
| 998 | * the temporary register and writes the result to key cache memory. |
| 999 | * The actual written memory area is 50 bits wide. |
| 1000 | */ |
| 1001 | AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 0)), (0) ); |
| 1002 | AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 4)), (0) ); |
| 1003 | |
| 1004 | AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 8)), (0) ); |
| 1005 | AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 12)), (0 )); |
| 1006 | |
| 1007 | AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 16)), (0 )); |
| 1008 | AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 20)), (7 )); |
| 1009 | |
| 1010 | AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 24)), (0 )); |
| 1011 | AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 28)), (0 )); |
| 1012 | |
| 1013 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1014 | } |
| 1015 | |
| 1016 | int |
| 1017 | athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, |
| 1018 | struct ieee80211_key *k) |
| 1019 | { |
| 1020 | struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; |
| 1021 | const uint8_t *key, *addr; |
| 1022 | uintptr_t entry; |
| 1023 | uint32_t lo, hi, unicast; |
| 1024 | |
| 1025 | if (k->k_cipher != IEEE80211_CIPHER_CCMP) { |
| 1026 | /* Use software crypto for ciphers other than CCMP. */ |
| 1027 | return ieee80211_set_key(ic, ni, k); |
| 1028 | } |
| 1029 | |
| 1030 | if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001)) { |
| 1031 | #ifndef IEEE80211_STA_ONLY |
| 1032 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) |
| 1033 | entry = IEEE80211_WEP_NKID4 + IEEE80211_AID(ni->ni_associd)((ni->ni_associd) &~ 0xc000); |
| 1034 | else |
| 1035 | #endif |
| 1036 | entry = IEEE80211_WEP_NKID4; |
| 1037 | if (entry >= sc->kc_entries - IEEE80211_WEP_NKID4) |
| 1038 | return ENOSPC28; |
| 1039 | } else { |
| 1040 | entry = k->k_id; |
| 1041 | if (entry >= IEEE80211_WEP_NKID4) |
| 1042 | return ENOSPC28; |
| 1043 | } |
| 1044 | k->k_priv = (void *)entry; |
| 1045 | |
| 1046 | /* NB: See note about key cache registers access above. */ |
| 1047 | key = k->k_key; |
| 1048 | |
| 1049 | AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 0)), ((( &key[ 0])[0] | (&key[ 0])[1] << 8 | (&key[ 0 ])[2] << 16 | (&key[ 0])[3] << 24))); |
| 1050 | AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 4)), ((( &key[ 4])[0] | (&key[ 4])[1] << 8))); |
| 1051 | |
| 1052 | AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 8)), ((( &key[ 6])[0] | (&key[ 6])[1] << 8 | (&key[ 6 ])[2] << 16 | (&key[ 6])[3] << 24))); |
| 1053 | AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 12)), (( (&key[10])[0] | (&key[10])[1] << 8))); |
| 1054 | |
| 1055 | AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 16)), (( (&key[12])[0] | (&key[12])[1] << 8 | (&key[ 12])[2] << 16 | (&key[12])[3] << 24))); |
| 1056 | AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CCM)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 20)), (6 )); |
| 1057 | |
| 1058 | unicast = AR_KEYTABLE_VALID0x00008000; |
| 1059 | if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001)) { |
| 1060 | addr = ni->ni_macaddr; |
| 1061 | lo = LE_READ_4(&addr[0])((&addr[0])[0] | (&addr[0])[1] << 8 | (&addr [0])[2] << 16 | (&addr[0])[3] << 24); |
| 1062 | hi = LE_READ_2(&addr[4])((&addr[4])[0] | (&addr[4])[1] << 8); |
| 1063 | lo = lo >> 1 | hi << 31; |
| 1064 | hi = hi >> 1; |
| 1065 | } else { |
| 1066 | #ifndef IEEE80211_STA_ONLY |
| 1067 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
| 1068 | uint8_t groupaddr[ETHER_ADDR_LEN6]; |
| 1069 | IEEE80211_ADDR_COPY(groupaddr, ic->ic_myaddr)__builtin_memcpy((groupaddr), (ic->ic_myaddr), (6)); |
| 1070 | groupaddr[0] |= 0x01; |
| 1071 | lo = LE_READ_4(&groupaddr[0])((&groupaddr[0])[0] | (&groupaddr[0])[1] << 8 | (&groupaddr[0])[2] << 16 | (&groupaddr[0])[3] << 24); |
| 1072 | hi = LE_READ_2(&groupaddr[4])((&groupaddr[4])[0] | (&groupaddr[4])[1] << 8); |
| 1073 | lo = lo >> 1 | hi << 31; |
| 1074 | hi = hi >> 1; |
| 1075 | /* |
| 1076 | * KEYTABLE_VALID indicates that the address |
| 1077 | * is a unicast address which must match the |
| 1078 | * transmitter address when decrypting frames. |
| 1079 | * Not setting KEYTABLE_VALID allows hardware to |
| 1080 | * use this key for multicast frame decryption. |
| 1081 | */ |
| 1082 | unicast = 0; |
| 1083 | } else |
| 1084 | #endif |
| 1085 | lo = hi = 0; |
| 1086 | } |
| 1087 | AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 24)), (lo )); |
| 1088 | AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | unicast)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 28)), (hi | unicast)); |
| 1089 | |
| 1090 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1091 | |
| 1092 | /* Enable HW crypto. */ |
| 1093 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) & ~(0x00000008 | 0x00000010))); |
| 1094 | |
| 1095 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1096 | return (0); |
| 1097 | } |
| 1098 | |
| 1099 | void |
| 1100 | athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, |
| 1101 | struct ieee80211_key *k) |
| 1102 | { |
| 1103 | struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; |
| 1104 | uintptr_t entry; |
| 1105 | |
| 1106 | if (k->k_cipher == IEEE80211_CIPHER_CCMP) { |
| 1107 | entry = (uintptr_t)k->k_priv; |
| 1108 | athn_reset_key(sc, entry); |
| 1109 | explicit_bzero(k, sizeof(*k)); |
| 1110 | } else |
| 1111 | ieee80211_delete_key(ic, ni, k); |
| 1112 | } |
| 1113 | |
| 1114 | void |
| 1115 | athn_led_init(struct athn_softc *sc) |
| 1116 | { |
| 1117 | struct athn_ops *ops = &sc->ops; |
| 1118 | |
| 1119 | ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT0); |
| 1120 | /* LED off, active low. */ |
| 1121 | athn_set_led(sc, 0); |
| 1122 | } |
| 1123 | |
| 1124 | void |
| 1125 | athn_set_led(struct athn_softc *sc, int on) |
| 1126 | { |
| 1127 | struct athn_ops *ops = &sc->ops; |
| 1128 | |
| 1129 | sc->led_state = on; |
| 1130 | ops->gpio_write(sc, sc->led_pin, !sc->led_state); |
| 1131 | } |
| 1132 | |
| 1133 | #ifdef ATHN_BT_COEXISTENCE |
| 1134 | void |
| 1135 | athn_btcoex_init(struct athn_softc *sc) |
| 1136 | { |
| 1137 | struct athn_ops *ops = &sc->ops; |
| 1138 | uint32_t reg; |
| 1139 | |
| 1140 | if (sc->flags & ATHN_FLAG_BTCOEX2WIRE(1 << 7)) { |
| 1141 | /* Connect bt_active to baseband. */ |
| 1142 | AR_CLRBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004 | 0x00000008))) |
| 1143 | AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004 | 0x00000008))) |
| 1144 | AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004 | 0x00000008))); |
| 1145 | AR_SETBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00001000))) |
| 1146 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00001000))); |
| 1147 | |
| 1148 | reg = AR_READ(sc, AR_GPIO_INPUT_MUX1)(sc)->ops.read((sc), (AR_GPIO_INPUT_MUX1)); |
| 1149 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) & 0x000f0000)) |
| 1150 | AR_GPIO_BTACTIVE_PIN)(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) & 0x000f0000)); |
| 1151 | AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg)(sc)->ops.write((sc), (AR_GPIO_INPUT_MUX1), (reg)); |
| 1152 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1153 | |
| 1154 | ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN6); |
| 1155 | } else { /* 3-wire. */ |
| 1156 | AR_SETBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000 ))) |
| 1157 | AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000 ))) |
| 1158 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000 ))); |
| 1159 | |
| 1160 | reg = AR_READ(sc, AR_GPIO_INPUT_MUX1)(sc)->ops.read((sc), (AR_GPIO_INPUT_MUX1)); |
| 1161 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) & 0x000f0000)) |
| 1162 | AR_GPIO_BTACTIVE_PIN)(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) & 0x000f0000)); |
| 1163 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,(((reg) & ~0x00000f00) | (((uint32_t)(7) << 8) & 0x00000f00)) |
| 1164 | AR_GPIO_BTPRIORITY_PIN)(((reg) & ~0x00000f00) | (((uint32_t)(7) << 8) & 0x00000f00)); |
| 1165 | AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg)(sc)->ops.write((sc), (AR_GPIO_INPUT_MUX1), (reg)); |
| 1166 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1167 | |
| 1168 | ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN6); |
| 1169 | ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN7); |
| 1170 | } |
| 1171 | } |
| 1172 | |
| 1173 | void |
| 1174 | athn_btcoex_enable(struct athn_softc *sc) |
| 1175 | { |
| 1176 | struct athn_ops *ops = &sc->ops; |
| 1177 | uint32_t reg; |
| 1178 | |
| 1179 | if (sc->flags & ATHN_FLAG_BTCOEX3WIRE(1 << 8)) { |
| 1180 | AR_WRITE(sc, AR_BT_COEX_MODE,(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1181 | SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1182 | SM(AR_BT_PRIORITY_TIME, 2) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1183 | SM(AR_BT_FIRST_SLOT_TIME, 5) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1184 | SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1185 | AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)) |
| 1186 | AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY)(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10 ) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000 ) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t )(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200 | 0x00001000 | 0x00020000)); |
| 1187 | AR_WRITE(sc, AR_BT_COEX_WEIGHT,(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) << 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) & 0xffff0000))) |
| 1188 | SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) << 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) & 0xffff0000))) |
| 1189 | SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT))(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) << 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) & 0xffff0000))); |
| 1190 | AR_WRITE(sc, AR_BT_COEX_MODE2,(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) << 0) & 0x000000ff) | 0x00010000 | 0x00100000)) |
| 1191 | SM(AR_BT_BCN_MISS_THRESH, 50) |(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) << 0) & 0x000000ff) | 0x00010000 | 0x00100000)) |
| 1192 | AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT)(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) << 0) & 0x000000ff) | 0x00010000 | 0x00100000)); |
| 1193 | |
| 1194 | AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE)(sc)->ops.write((sc), (0x80fc), ((sc)->ops.read((sc), ( 0x80fc)) | (0x00020000))); |
| 1195 | AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX)(sc)->ops.write((sc), (0x8120), ((sc)->ops.read((sc), ( 0x8120)) & ~(0x00100000))); |
| 1196 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1197 | |
| 1198 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5, |
| 1199 | AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL4); |
| 1200 | |
| 1201 | } else { /* 2-wire. */ |
| 1202 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5, |
| 1203 | AR_GPIO_OUTPUT_MUX_AS_TX_FRAME3); |
| 1204 | } |
| 1205 | reg = AR_READ(sc, AR_GPIO_PDPU)(sc)->ops.read((sc), (AR_GPIO_PDPU)); |
| 1206 | reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN5 * 2)); |
| 1207 | reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN5 * 2); |
| 1208 | AR_WRITE(sc, AR_GPIO_PDPU, reg)(sc)->ops.write((sc), (AR_GPIO_PDPU), (reg)); |
| 1209 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1210 | |
| 1211 | /* Disable PCIe Active State Power Management (ASPM). */ |
| 1212 | if (sc->sc_disable_aspm != NULL((void *)0)) |
| 1213 | sc->sc_disable_aspm(sc); |
| 1214 | |
| 1215 | /* XXX Start periodic timer. */ |
| 1216 | } |
| 1217 | |
| 1218 | void |
| 1219 | athn_btcoex_disable(struct athn_softc *sc) |
| 1220 | { |
| 1221 | struct athn_ops *ops = &sc->ops; |
| 1222 | |
| 1223 | ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN5, 0); |
| 1224 | |
| 1225 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5, |
| 1226 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT0); |
| 1227 | |
| 1228 | if (sc->flags & ATHN_FLAG_BTCOEX3WIRE(1 << 8)) { |
| 1229 | AR_WRITE(sc, AR_BT_COEX_MODE,(sc)->ops.write((sc), (0x8170), ((((uint32_t)(3) << 10 ) & 0x00000c00) | 0x00001000)) |
| 1230 | SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET)(sc)->ops.write((sc), (0x8170), ((((uint32_t)(3) << 10 ) & 0x00000c00) | 0x00001000)); |
| 1231 | AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0)(sc)->ops.write((sc), (0x8174), (0)); |
| 1232 | AR_WRITE(sc, AR_BT_COEX_MODE2, 0)(sc)->ops.write((sc), (0x817c), (0)); |
| 1233 | /* XXX Stop periodic timer. */ |
| 1234 | } |
| 1235 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1236 | /* XXX Restore ASPM setting? */ |
| 1237 | } |
| 1238 | #endif |
| 1239 | |
| 1240 | void |
| 1241 | athn_iter_calib(void *arg, struct ieee80211_node *ni) |
| 1242 | { |
| 1243 | struct athn_softc *sc = arg; |
| 1244 | struct athn_node *an = (struct athn_node *)ni; |
| 1245 | |
| 1246 | if ((ni->ni_flags & IEEE80211_NODE_HT0x0400) == 0) |
| 1247 | ieee80211_amrr_choose(&sc->amrr, ni, &an->amn); |
| 1248 | } |
| 1249 | |
| 1250 | int |
| 1251 | athn_cap_noisefloor(struct athn_softc *sc, int nf) |
| 1252 | { |
| 1253 | int16_t min, max; |
| 1254 | |
| 1255 | if (nf == 0 || nf == -1) /* invalid measurement */ |
| 1256 | return AR_DEFAULT_NOISE_FLOOR(-100); |
| 1257 | |
| 1258 | if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080 ) != 0)) { |
| 1259 | min = sc->cca_min_2g; |
| 1260 | max = sc->cca_max_2g; |
| 1261 | } else { |
| 1262 | min = sc->cca_min_5g; |
| 1263 | max = sc->cca_max_5g; |
| 1264 | } |
| 1265 | |
| 1266 | if (nf < min) |
| 1267 | return min; |
| 1268 | if (nf > max) |
| 1269 | return max; |
| 1270 | |
| 1271 | return nf; |
| 1272 | } |
| 1273 | |
| 1274 | int |
| 1275 | athn_nf_hist_mid(int *nf_vals, int nvalid) |
| 1276 | { |
| 1277 | int nf_sorted[ATHN_NF_CAL_HIST_MAX5]; |
| 1278 | int i, j, nf; |
| 1279 | |
| 1280 | if (nvalid <= 1) |
| 1281 | return nf_vals[0]; |
| 1282 | |
| 1283 | for (i = 0; i < nvalid; i++) |
| 1284 | nf_sorted[i] = nf_vals[i]; |
| 1285 | |
| 1286 | for (i = 0; i < nvalid; i++) { |
| 1287 | for (j = 1; j < nvalid - i; j++) { |
| 1288 | if (nf_sorted[j] > nf_sorted[j - 1]) { |
| 1289 | nf = nf_sorted[j]; |
| 1290 | nf_sorted[j] = nf_sorted[j - 1]; |
| 1291 | nf_sorted[j - 1] = nf; |
| 1292 | } |
| 1293 | } |
| 1294 | } |
| 1295 | |
| 1296 | return nf_sorted[nvalid / 2]; |
| 1297 | } |
| 1298 | |
| 1299 | void |
| 1300 | athn_filter_noisefloor(struct athn_softc *sc) |
| 1301 | { |
| 1302 | int nf_vals[ATHN_NF_CAL_HIST_MAX5]; |
| 1303 | int nf_ext_vals[ATHN_NF_CAL_HIST_MAX5]; |
| 1304 | int i, cur, n; |
| 1305 | |
| 1306 | for (i = 0; i < sc->nrxchains; i++) { |
| 1307 | if (sc->nf_hist_cur > 0) |
| 1308 | cur = sc->nf_hist_cur - 1; |
| 1309 | else |
| 1310 | cur = ATHN_NF_CAL_HIST_MAX5 - 1; |
| 1311 | for (n = 0; n < sc->nf_hist_nvalid; n++) { |
| 1312 | nf_vals[n] = sc->nf_hist[cur].nf[i]; |
| 1313 | nf_ext_vals[n] = sc->nf_hist[cur].nf_ext[i]; |
| 1314 | if (++cur >= ATHN_NF_CAL_HIST_MAX5) |
| 1315 | cur = 0; |
| 1316 | } |
| 1317 | sc->nf_priv[i] = athn_cap_noisefloor(sc, |
| 1318 | athn_nf_hist_mid(nf_vals, sc->nf_hist_nvalid)); |
| 1319 | sc->nf_ext_priv[i] = athn_cap_noisefloor(sc, |
| 1320 | athn_nf_hist_mid(nf_ext_vals, sc->nf_hist_nvalid)); |
| 1321 | } |
| 1322 | } |
| 1323 | |
| 1324 | void |
| 1325 | athn_start_noisefloor_calib(struct athn_softc *sc, int reset_history) |
| 1326 | { |
| 1327 | extern int ticks; |
| 1328 | |
| 1329 | if (reset_history) |
| 1330 | sc->nf_hist_nvalid = 0; |
| 1331 | |
| 1332 | sc->nf_calib_pending = 1; |
| 1333 | sc->nf_calib_ticks = ticks; |
| 1334 | |
| 1335 | sc->ops.noisefloor_calib(sc); |
| 1336 | } |
| 1337 | |
| 1338 | void |
| 1339 | athn_calib_to(void *arg) |
| 1340 | { |
| 1341 | extern int ticks; |
| 1342 | struct athn_softc *sc = arg; |
| 1343 | struct athn_ops *ops = &sc->ops; |
| 1344 | struct ieee80211com *ic = &sc->sc_ic; |
| 1345 | int s; |
| 1346 | |
| 1347 | s = splnet()splraise(0x4); |
| 1348 | |
| 1349 | /* Do periodic (every 4 minutes) PA calibration. */ |
| 1350 | if (AR_SREV_9285_11_OR_LATER(sc)((sc)->mac_ver > 0x0c0 || (((sc)->mac_ver == 0x0c0) && (sc)->mac_rev >= 1)) && |
| 1351 | !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0) && |
| 1352 | (ticks - (sc->pa_calib_ticks + 240 * hz)) >= 0) { |
| 1353 | sc->pa_calib_ticks = ticks; |
| 1354 | if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 1355 | ar9271_pa_calib(sc); |
| 1356 | else |
| 1357 | ar9285_pa_calib(sc); |
| 1358 | } |
| 1359 | |
| 1360 | /* Do periodic (every 4 minutes) NF calibration. */ |
| 1361 | if (sc->nf_calib_pending && ops->get_noisefloor(sc)) { |
| 1362 | if (sc->nf_hist_nvalid < ATHN_NF_CAL_HIST_MAX5) |
| 1363 | sc->nf_hist_nvalid++; |
| 1364 | athn_filter_noisefloor(sc); |
| 1365 | ops->apply_noisefloor(sc); |
| 1366 | sc->nf_calib_pending = 0; |
| 1367 | } |
| 1368 | if (ticks - (sc->nf_calib_ticks + 240 * hz) >= 0) |
| 1369 | athn_start_noisefloor_calib(sc, 0); |
| 1370 | |
| 1371 | /* Do periodic (every 30 seconds) temperature compensation. */ |
| 1372 | if ((sc->flags & ATHN_FLAG_OLPC(1 << 2)) && |
| 1373 | ticks >= sc->olpc_ticks + 30 * hz) { |
| 1374 | sc->olpc_ticks = ticks; |
| 1375 | ops->olpc_temp_compensation(sc); |
| 1376 | } |
| 1377 | |
| 1378 | #ifdef notyet |
| 1379 | /* XXX ANI. */ |
| 1380 | athn_ani_monitor(sc); |
| 1381 | #endif |
| 1382 | |
| 1383 | /* Do periodic (every 30 seconds) ADC/IQ calibration. */ |
| 1384 | if (sc->cur_calib_mask != 0) { |
| 1385 | ops->next_calib(sc); |
| 1386 | sc->iqcal_ticks = ticks; |
| 1387 | } else if (sc->sup_calib_mask != 0 && |
| 1388 | ticks >= sc->iqcal_ticks + 30 * hz) { |
| 1389 | memset(&sc->calib, 0, sizeof(sc->calib))__builtin_memset((&sc->calib), (0), (sizeof(sc->calib ))); |
| 1390 | sc->cur_calib_mask = sc->sup_calib_mask; |
| 1391 | ops->do_calib(sc); |
| 1392 | sc->iqcal_ticks = ticks; |
| 1393 | } |
| 1394 | |
| 1395 | if (ic->ic_fixed_rate == -1) { |
| 1396 | if (ic->ic_opmode == IEEE80211_M_STA) |
| 1397 | athn_iter_calib(sc, ic->ic_bss); |
| 1398 | else |
| 1399 | ieee80211_iterate_nodes(ic, athn_iter_calib, sc); |
| 1400 | } |
| 1401 | timeout_add_msec(&sc->calib_to, 500); |
| 1402 | splx(s)spllower(s); |
| 1403 | } |
| 1404 | |
| 1405 | int |
| 1406 | athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, |
| 1407 | struct ieee80211_channel *extc) |
| 1408 | { |
| 1409 | struct athn_ops *ops = &sc->ops; |
| 1410 | int error; |
| 1411 | |
| 1412 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 1413 | error = ar9003_init_calib(sc); |
| 1414 | else if (AR_SREV_9285_10_OR_LATER(sc)((sc)->mac_ver >= 0x0c0)) |
| 1415 | error = ar9285_init_calib(sc, c, extc); |
| 1416 | else |
| 1417 | error = ar5416_init_calib(sc, c, extc); |
| 1418 | if (error != 0) |
| 1419 | return (error); |
| 1420 | |
| 1421 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 1422 | /* Do PA calibration. */ |
| 1423 | if (AR_SREV_9285_11_OR_LATER(sc)((sc)->mac_ver > 0x0c0 || (((sc)->mac_ver == 0x0c0) && (sc)->mac_rev >= 1))) { |
| 1424 | extern int ticks; |
| 1425 | sc->pa_calib_ticks = ticks; |
| 1426 | if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 1427 | ar9271_pa_calib(sc); |
| 1428 | else |
| 1429 | ar9285_pa_calib(sc); |
| 1430 | } |
| 1431 | } |
| 1432 | |
| 1433 | /* Do noisefloor calibration. */ |
| 1434 | ops->init_noisefloor_calib(sc); |
| 1435 | |
| 1436 | if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) { |
| 1437 | /* Support IQ calibration. */ |
| 1438 | sc->sup_calib_mask = ATHN_CAL_IQ(1 << 0); |
| 1439 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 1440 | /* Support temperature compensation calibration. */ |
| 1441 | sc->sup_calib_mask |= ATHN_CAL_TEMP(1 << 3); |
| 1442 | } else if (IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0) || extc != NULL((void *)0)) { |
| 1443 | /* |
| 1444 | * ADC gain calibration causes uplink throughput |
| 1445 | * drops in HT40 mode on AR9287. |
| 1446 | */ |
| 1447 | if (!AR_SREV_9287(sc)((sc)->mac_ver == 0x180)) { |
| 1448 | /* Support ADC gain calibration. */ |
| 1449 | sc->sup_calib_mask |= ATHN_CAL_ADC_GAIN(1 << 1); |
| 1450 | } |
| 1451 | /* Support ADC DC offset calibration. */ |
| 1452 | sc->sup_calib_mask |= ATHN_CAL_ADC_DC(1 << 2); |
| 1453 | } |
| 1454 | } |
| 1455 | return (0); |
| 1456 | } |
| 1457 | |
| 1458 | /* |
| 1459 | * Adaptive noise immunity. |
| 1460 | */ |
| 1461 | int32_t |
| 1462 | athn_ani_get_rssi(struct athn_softc *sc) |
| 1463 | { |
| 1464 | return (0); /* XXX */ |
| 1465 | } |
| 1466 | |
| 1467 | void |
| 1468 | athn_ani_ofdm_err_trigger(struct athn_softc *sc) |
| 1469 | { |
| 1470 | struct athn_ani *ani = &sc->ani; |
| 1471 | struct athn_ops *ops = &sc->ops; |
| 1472 | int32_t rssi; |
| 1473 | |
| 1474 | /* First, raise noise immunity level, up to max. */ |
| 1475 | if (ani->noise_immunity_level < 4) { |
| 1476 | ani->noise_immunity_level++; |
| 1477 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
| 1478 | return; |
| 1479 | } |
| 1480 | |
| 1481 | /* Then, raise our spur immunity level, up to max. */ |
| 1482 | if (ani->spur_immunity_level < 7) { |
| 1483 | ani->spur_immunity_level++; |
| 1484 | ops->set_spur_immunity_level(sc, ani->spur_immunity_level); |
| 1485 | return; |
| 1486 | } |
| 1487 | |
| 1488 | #ifndef IEEE80211_STA_ONLY |
| 1489 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
| 1490 | if (ani->firstep_level < 2) { |
| 1491 | ani->firstep_level++; |
| 1492 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1493 | } |
| 1494 | return; |
| 1495 | } |
| 1496 | #endif |
| 1497 | rssi = athn_ani_get_rssi(sc); |
| 1498 | if (rssi > ATHN_ANI_RSSI_THR_HIGH40) { |
| 1499 | /* |
| 1500 | * Beacon RSSI is high, turn off OFDM weak signal detection |
| 1501 | * or raise first step level as last resort. |
| 1502 | */ |
| 1503 | if (ani->ofdm_weak_signal) { |
| 1504 | ani->ofdm_weak_signal = 0; |
| 1505 | ops->disable_ofdm_weak_signal(sc); |
| 1506 | ani->spur_immunity_level = 0; |
| 1507 | ops->set_spur_immunity_level(sc, 0); |
| 1508 | } else if (ani->firstep_level < 2) { |
| 1509 | ani->firstep_level++; |
| 1510 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1511 | } |
| 1512 | } else if (rssi > ATHN_ANI_RSSI_THR_LOW7) { |
| 1513 | /* |
| 1514 | * Beacon RSSI is in mid range, we need OFDM weak signal |
| 1515 | * detection but we can raise first step level. |
| 1516 | */ |
| 1517 | if (!ani->ofdm_weak_signal) { |
| 1518 | ani->ofdm_weak_signal = 1; |
| 1519 | ops->enable_ofdm_weak_signal(sc); |
| 1520 | } |
| 1521 | if (ani->firstep_level < 2) { |
| 1522 | ani->firstep_level++; |
| 1523 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1524 | } |
| 1525 | } else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080 ) != 0)) { |
| 1526 | /* |
| 1527 | * Beacon RSSI is low, if in b/g mode, turn off OFDM weak |
| 1528 | * signal detection and zero first step level to maximize |
| 1529 | * CCK sensitivity. |
| 1530 | */ |
| 1531 | if (ani->ofdm_weak_signal) { |
| 1532 | ani->ofdm_weak_signal = 0; |
| 1533 | ops->disable_ofdm_weak_signal(sc); |
| 1534 | } |
| 1535 | if (ani->firstep_level > 0) { |
| 1536 | ani->firstep_level = 0; |
| 1537 | ops->set_firstep_level(sc, 0); |
| 1538 | } |
| 1539 | } |
| 1540 | } |
| 1541 | |
| 1542 | void |
| 1543 | athn_ani_cck_err_trigger(struct athn_softc *sc) |
| 1544 | { |
| 1545 | struct athn_ani *ani = &sc->ani; |
| 1546 | struct athn_ops *ops = &sc->ops; |
| 1547 | int32_t rssi; |
| 1548 | |
| 1549 | /* Raise noise immunity level, up to max. */ |
| 1550 | if (ani->noise_immunity_level < 4) { |
| 1551 | ani->noise_immunity_level++; |
| 1552 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
| 1553 | return; |
| 1554 | } |
| 1555 | |
| 1556 | #ifndef IEEE80211_STA_ONLY |
| 1557 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
| 1558 | if (ani->firstep_level < 2) { |
| 1559 | ani->firstep_level++; |
| 1560 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1561 | } |
| 1562 | return; |
| 1563 | } |
| 1564 | #endif |
| 1565 | rssi = athn_ani_get_rssi(sc); |
| 1566 | if (rssi > ATHN_ANI_RSSI_THR_LOW7) { |
| 1567 | /* |
| 1568 | * Beacon RSSI is in mid or high range, raise first step |
| 1569 | * level. |
| 1570 | */ |
| 1571 | if (ani->firstep_level < 2) { |
| 1572 | ani->firstep_level++; |
| 1573 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1574 | } |
| 1575 | } else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080 ) != 0)) { |
| 1576 | /* |
| 1577 | * Beacon RSSI is low, zero first step level to maximize |
| 1578 | * CCK sensitivity. |
| 1579 | */ |
| 1580 | if (ani->firstep_level > 0) { |
| 1581 | ani->firstep_level = 0; |
| 1582 | ops->set_firstep_level(sc, 0); |
| 1583 | } |
| 1584 | } |
| 1585 | } |
| 1586 | |
| 1587 | void |
| 1588 | athn_ani_lower_immunity(struct athn_softc *sc) |
| 1589 | { |
| 1590 | struct athn_ani *ani = &sc->ani; |
| 1591 | struct athn_ops *ops = &sc->ops; |
| 1592 | int32_t rssi; |
| 1593 | |
| 1594 | #ifndef IEEE80211_STA_ONLY |
| 1595 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
| 1596 | if (ani->firstep_level > 0) { |
| 1597 | ani->firstep_level--; |
| 1598 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1599 | } |
| 1600 | return; |
| 1601 | } |
| 1602 | #endif |
| 1603 | rssi = athn_ani_get_rssi(sc); |
| 1604 | if (rssi > ATHN_ANI_RSSI_THR_HIGH40) { |
| 1605 | /* |
| 1606 | * Beacon RSSI is high, leave OFDM weak signal detection |
| 1607 | * off or it may oscillate. |
| 1608 | */ |
| 1609 | } else if (rssi > ATHN_ANI_RSSI_THR_LOW7) { |
| 1610 | /* |
| 1611 | * Beacon RSSI is in mid range, turn on OFDM weak signal |
| 1612 | * detection or lower first step level. |
| 1613 | */ |
| 1614 | if (!ani->ofdm_weak_signal) { |
| 1615 | ani->ofdm_weak_signal = 1; |
| 1616 | ops->enable_ofdm_weak_signal(sc); |
| 1617 | return; |
| 1618 | } |
| 1619 | if (ani->firstep_level > 0) { |
| 1620 | ani->firstep_level--; |
| 1621 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1622 | return; |
| 1623 | } |
| 1624 | } else { |
| 1625 | /* Beacon RSSI is low, lower first step level. */ |
| 1626 | if (ani->firstep_level > 0) { |
| 1627 | ani->firstep_level--; |
| 1628 | ops->set_firstep_level(sc, ani->firstep_level); |
| 1629 | return; |
| 1630 | } |
| 1631 | } |
| 1632 | /* |
| 1633 | * Lower spur immunity level down to zero, or if all else fails, |
| 1634 | * lower noise immunity level down to zero. |
| 1635 | */ |
| 1636 | if (ani->spur_immunity_level > 0) { |
| 1637 | ani->spur_immunity_level--; |
| 1638 | ops->set_spur_immunity_level(sc, ani->spur_immunity_level); |
| 1639 | } else if (ani->noise_immunity_level > 0) { |
| 1640 | ani->noise_immunity_level--; |
| 1641 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
| 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | void |
| 1646 | athn_ani_restart(struct athn_softc *sc) |
| 1647 | { |
| 1648 | struct athn_ani *ani = &sc->ani; |
| 1649 | |
| 1650 | AR_WRITE(sc, AR_PHY_ERR_1, 0)(sc)->ops.write((sc), (0x812c), (0)); |
| 1651 | AR_WRITE(sc, AR_PHY_ERR_2, 0)(sc)->ops.write((sc), (0x8134), (0)); |
| 1652 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000)); |
| 1653 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000)); |
| 1654 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1655 | |
| 1656 | ani->listen_time = 0; |
| 1657 | ani->ofdm_phy_err_count = 0; |
| 1658 | ani->cck_phy_err_count = 0; |
| 1659 | } |
| 1660 | |
| 1661 | void |
| 1662 | athn_ani_monitor(struct athn_softc *sc) |
| 1663 | { |
| 1664 | struct athn_ani *ani = &sc->ani; |
| 1665 | uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; |
| 1666 | int32_t cycdelta, txfdelta, rxfdelta; |
| 1667 | int32_t listen_time; |
| 1668 | |
| 1669 | txfcnt = AR_READ(sc, AR_TFCNT)(sc)->ops.read((sc), (0x80ec)); /* Tx frame count. */ |
| 1670 | rxfcnt = AR_READ(sc, AR_RFCNT)(sc)->ops.read((sc), (0x80f0)); /* Rx frame count. */ |
| 1671 | cyccnt = AR_READ(sc, AR_CCCNT)(sc)->ops.read((sc), (0x80f8)); /* Cycle count. */ |
| 1672 | |
| 1673 | if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { |
| 1674 | cycdelta = cyccnt - ani->cyccnt; |
| 1675 | txfdelta = txfcnt - ani->txfcnt; |
| 1676 | rxfdelta = rxfcnt - ani->rxfcnt; |
| 1677 | |
| 1678 | listen_time = (cycdelta - txfdelta - rxfdelta) / |
| 1679 | (athn_clock_rate(sc) * 1000); |
| 1680 | } else |
| 1681 | listen_time = 0; |
| 1682 | |
| 1683 | ani->cyccnt = cyccnt; |
| 1684 | ani->txfcnt = txfcnt; |
| 1685 | ani->rxfcnt = rxfcnt; |
| 1686 | |
| 1687 | if (listen_time < 0) { |
| 1688 | athn_ani_restart(sc); |
| 1689 | return; |
| 1690 | } |
| 1691 | ani->listen_time += listen_time; |
| 1692 | |
| 1693 | phy1 = AR_READ(sc, AR_PHY_ERR_1)(sc)->ops.read((sc), (0x812c)); |
| 1694 | phy2 = AR_READ(sc, AR_PHY_ERR_2)(sc)->ops.read((sc), (0x8134)); |
| 1695 | |
| 1696 | if (phy1 < ani->ofdm_phy_err_base) { |
| 1697 | AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base)(sc)->ops.write((sc), (0x812c), (ani->ofdm_phy_err_base )); |
| 1698 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000)); |
| 1699 | } |
| 1700 | if (phy2 < ani->cck_phy_err_base) { |
| 1701 | AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base)(sc)->ops.write((sc), (0x8134), (ani->cck_phy_err_base) ); |
| 1702 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000)); |
| 1703 | } |
| 1704 | if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { |
| 1705 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1706 | return; |
| 1707 | } |
| 1708 | ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; |
| 1709 | ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; |
| 1710 | |
| 1711 | if (ani->listen_time > 5 * ATHN_ANI_PERIOD100) { |
| 1712 | /* Check to see if we need to lower immunity. */ |
| 1713 | if (ani->ofdm_phy_err_count <= |
| 1714 | ani->listen_time * ani->ofdm_trig_low / 1000 && |
| 1715 | ani->cck_phy_err_count <= |
| 1716 | ani->listen_time * ani->cck_trig_low / 1000) |
| 1717 | athn_ani_lower_immunity(sc); |
| 1718 | athn_ani_restart(sc); |
| 1719 | |
| 1720 | } else if (ani->listen_time > ATHN_ANI_PERIOD100) { |
| 1721 | /* Check to see if we need to raise immunity. */ |
| 1722 | if (ani->ofdm_phy_err_count > |
| 1723 | ani->listen_time * ani->ofdm_trig_high / 1000) { |
| 1724 | athn_ani_ofdm_err_trigger(sc); |
| 1725 | athn_ani_restart(sc); |
| 1726 | } else if (ani->cck_phy_err_count > |
| 1727 | ani->listen_time * ani->cck_trig_high / 1000) { |
| 1728 | athn_ani_cck_err_trigger(sc); |
| 1729 | athn_ani_restart(sc); |
| 1730 | } |
| 1731 | } |
| 1732 | } |
| 1733 | |
| 1734 | uint8_t |
| 1735 | athn_chan2fbin(struct ieee80211_channel *c) |
| 1736 | { |
| 1737 | if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0)) |
| 1738 | return (c->ic_freq - 2300); |
| 1739 | else |
| 1740 | return ((c->ic_freq - 4800) / 5); |
| 1741 | } |
| 1742 | |
| 1743 | int |
| 1744 | athn_interpolate(int x, int x1, int y1, int x2, int y2) |
| 1745 | { |
| 1746 | if (x1 == x2) /* Prevents division by zero. */ |
| 1747 | return (y1); |
| 1748 | /* Linear interpolation. */ |
| 1749 | return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1)); |
| 1750 | } |
| 1751 | |
| 1752 | void |
| 1753 | athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, |
| 1754 | int *lo, int *hi) |
| 1755 | { |
| 1756 | int i; |
| 1757 | |
| 1758 | for (i = 0; i < npiers; i++) |
| 1759 | if (pierfreq[i] == AR_BCHAN_UNUSED0xff || |
| 1760 | pierfreq[i] > fbin) |
| 1761 | break; |
| 1762 | *hi = i; |
| 1763 | *lo = *hi - 1; |
| 1764 | if (*lo == -1) |
| 1765 | *lo = *hi; |
| 1766 | else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED0xff) |
| 1767 | *hi = *lo; |
| 1768 | } |
| 1769 | |
| 1770 | void |
| 1771 | athn_init_dma(struct athn_softc *sc) |
| 1772 | { |
| 1773 | uint32_t reg; |
| 1774 | |
| 1775 | if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 1776 | /* Set AHB not to do cacheline prefetches. */ |
| 1777 | AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN)(sc)->ops.write((sc), (0x4024), ((sc)->ops.read((sc), ( 0x4024)) | (0x00000004))); |
| 1778 | } |
| 1779 | reg = AR_READ(sc, AR_TXCFG)(sc)->ops.read((sc), (0x0030)); |
| 1780 | /* Let MAC DMA reads be in 128-byte chunks. */ |
| 1781 | reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B)(((reg) & ~0x00000007) | (((uint32_t)(5) << 0) & 0x00000007)); |
| 1782 | |
| 1783 | /* Set initial Tx trigger level. */ |
| 1784 | if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0) || AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 1785 | reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B)(((reg) & ~0x000003f0) | (((uint32_t)((256 / 64)) << 4) & 0x000003f0)); |
| 1786 | else if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 1787 | reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B)(((reg) & ~0x000003f0) | (((uint32_t)((512 / 64)) << 4) & 0x000003f0)); |
| 1788 | AR_WRITE(sc, AR_TXCFG, reg)(sc)->ops.write((sc), (0x0030), (reg)); |
| 1789 | |
| 1790 | /* Let MAC DMA writes be in 128-byte chunks. */ |
| 1791 | reg = AR_READ(sc, AR_RXCFG)(sc)->ops.read((sc), (0x0034)); |
| 1792 | reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B)(((reg) & ~0x00000007) | (((uint32_t)(5) << 0) & 0x00000007)); |
| 1793 | AR_WRITE(sc, AR_RXCFG, reg)(sc)->ops.write((sc), (0x0034), (reg)); |
| 1794 | |
| 1795 | /* Setup Rx FIFO threshold to hold off Tx activities. */ |
| 1796 | AR_WRITE(sc, AR_RXFIFO_CFG, 512)(sc)->ops.write((sc), (0x8114), (512)); |
| 1797 | |
| 1798 | /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ |
| 1799 | if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0)) { |
| 1800 | AR_WRITE(sc, AR_PCU_TXBUF_CTRL,(sc)->ops.write((sc), (0x8340), ((1792 / 2))) |
| 1801 | AR9285_PCU_TXBUF_CTRL_USABLE_SIZE)(sc)->ops.write((sc), (0x8340), ((1792 / 2))); |
| 1802 | } else if (!AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) { |
| 1803 | AR_WRITE(sc, AR_PCU_TXBUF_CTRL,(sc)->ops.write((sc), (0x8340), (1792)) |
| 1804 | AR_PCU_TXBUF_CTRL_USABLE_SIZE)(sc)->ops.write((sc), (0x8340), (1792)); |
| 1805 | } |
| 1806 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1807 | |
| 1808 | /* Reset Tx status ring. */ |
| 1809 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 1810 | ar9003_reset_txsring(sc); |
| 1811 | } |
| 1812 | |
| 1813 | void |
| 1814 | athn_inc_tx_trigger_level(struct athn_softc *sc) |
| 1815 | { |
| 1816 | uint32_t reg, ftrig; |
| 1817 | |
| 1818 | reg = AR_READ(sc, AR_TXCFG)(sc)->ops.read((sc), (0x0030)); |
| 1819 | ftrig = MS(reg, AR_TXCFG_FTRIG)(((uint32_t)(reg) & 0x000003f0) >> 4); |
| 1820 | /* |
| 1821 | * NB: The AR9285 and all single-stream parts have an issue that |
| 1822 | * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. |
| 1823 | */ |
| 1824 | if (ftrig == ((AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0) || AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) ? 0x1f : 0x3f)) |
| 1825 | return; /* Already at max. */ |
| 1826 | reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1)(((reg) & ~0x000003f0) | (((uint32_t)(ftrig + 1) << 4) & 0x000003f0)); |
| 1827 | AR_WRITE(sc, AR_TXCFG, reg)(sc)->ops.write((sc), (0x0030), (reg)); |
| 1828 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1829 | } |
| 1830 | |
| 1831 | int |
| 1832 | athn_stop_rx_dma(struct athn_softc *sc) |
| 1833 | { |
| 1834 | int ntries; |
| 1835 | |
| 1836 | AR_WRITE(sc, AR_CR, AR_CR_RXD)(sc)->ops.write((sc), (0x0008), (0x00000020)); |
| 1837 | /* Wait for Rx enable bit to go low. */ |
| 1838 | for (ntries = 0; ntries < 100; ntries++) { |
| 1839 | if (!(AR_READ(sc, AR_CR)(sc)->ops.read((sc), (0x0008)) & AR_CR_RXE(((sc)->mac_ver > 0x1c0 || (((sc)->mac_ver == 0x1c0) && (sc)->mac_rev >= 2)) ? 0x000c : 0x0004))) |
| 1840 | return (0); |
| 1841 | DELAY(100)(*delay_func)(100); |
| 1842 | } |
| 1843 | DPRINTF(("Rx DMA failed to stop\n")); |
| 1844 | return (ETIMEDOUT60); |
| 1845 | } |
| 1846 | |
| 1847 | int |
| 1848 | athn_rx_abort(struct athn_softc *sc) |
| 1849 | { |
| 1850 | int ntries; |
| 1851 | |
| 1852 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) | (0x00000020 | 0x02000000))); |
| 1853 | for (ntries = 0; ntries < 1000; ntries++) { |
| 1854 | if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE)(((uint32_t)((sc)->ops.read((sc), (0x806c))) & 0x01f00000 ) >> 20) == 0) |
| 1855 | return (0); |
| 1856 | DELAY(10)(*delay_func)(10); |
| 1857 | } |
| 1858 | DPRINTF(("Rx failed to go idle in 10ms\n")); |
| 1859 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) & ~(0x00000020 | 0x02000000))); |
| 1860 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1861 | return (ETIMEDOUT60); |
| 1862 | } |
| 1863 | |
| 1864 | void |
| 1865 | athn_tx_reclaim(struct athn_softc *sc, int qid) |
| 1866 | { |
| 1867 | struct athn_txq *txq = &sc->txq[qid]; |
| 1868 | struct athn_tx_buf *bf; |
| 1869 | |
| 1870 | /* Reclaim all buffers queued in the specified Tx queue. */ |
| 1871 | /* NB: Tx DMA must be stopped. */ |
| 1872 | while ((bf = SIMPLEQ_FIRST(&txq->head)((&txq->head)->sqh_first)) != NULL((void *)0)) { |
| 1873 | SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list)do { if (((&txq->head)->sqh_first = (&txq->head )->sqh_first->bf_list.sqe_next) == ((void *)0)) (&txq ->head)->sqh_last = &(&txq->head)->sqh_first ; } while (0); |
| 1874 | |
| 1875 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (bf-> bf_map), (0), (bf->bf_map->dm_mapsize), (0x08)) |
| 1876 | bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (bf-> bf_map), (0), (bf->bf_map->dm_mapsize), (0x08)); |
| 1877 | bus_dmamap_unload(sc->sc_dmat, bf->bf_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (bf-> bf_map)); |
| 1878 | m_freem(bf->bf_m); |
| 1879 | bf->bf_m = NULL((void *)0); |
| 1880 | bf->bf_ni = NULL((void *)0); /* Nodes already freed! */ |
| 1881 | |
| 1882 | /* Link Tx buffer back to global free list. */ |
| 1883 | SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list)do { (bf)->bf_list.sqe_next = ((void *)0); *(&sc->txbufs )->sqh_last = (bf); (&sc->txbufs)->sqh_last = & (bf)->bf_list.sqe_next; } while (0); |
| 1884 | } |
| 1885 | } |
| 1886 | |
| 1887 | int |
| 1888 | athn_tx_pending(struct athn_softc *sc, int qid) |
| 1889 | { |
| 1890 | return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT)(((uint32_t)((sc)->ops.read((sc), ((0x0a00 + (qid) * 4)))) & 0x00000003) >> 0) != 0 || |
| 1891 | (AR_READ(sc, AR_Q_TXE)(sc)->ops.read((sc), (0x0840)) & (1 << qid)) != 0); |
| 1892 | } |
| 1893 | |
| 1894 | void |
| 1895 | athn_stop_tx_dma(struct athn_softc *sc, int qid) |
| 1896 | { |
| 1897 | uint32_t tsflo; |
| 1898 | int ntries, i; |
| 1899 | |
| 1900 | AR_WRITE(sc, AR_Q_TXD, 1 << qid)(sc)->ops.write((sc), (0x0880), (1 << qid)); |
| 1901 | for (ntries = 0; ntries < 40; ntries++) { |
| 1902 | if (!athn_tx_pending(sc, qid)) |
| 1903 | break; |
| 1904 | DELAY(100)(*delay_func)(100); |
| 1905 | } |
| 1906 | if (ntries == 40) { |
| 1907 | for (i = 0; i < 2; i++) { |
| 1908 | tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)) / 1024; |
| 1909 | AR_WRITE(sc, AR_QUIET2,(sc)->ops.write((sc), (0x8100), ((((uint32_t)(10) << 16) & 0xffff0000))) |
| 1910 | SM(AR_QUIET2_QUIET_DUR, 10))(sc)->ops.write((sc), (0x8100), ((((uint32_t)(10) << 16) & 0xffff0000))); |
| 1911 | AR_WRITE(sc, AR_QUIET_PERIOD, 100)(sc)->ops.write((sc), ((0x8200 + (14) * 4)), (100)); |
| 1912 | AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo)(sc)->ops.write((sc), ((0x8200 + (6) * 4)), (tsflo)); |
| 1913 | AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), ( 0x8240)) | (0x00000040))); |
| 1914 | if (AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)) / 1024 == tsflo) |
| 1915 | break; |
| 1916 | } |
| 1917 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) | (0x00400000))); |
| 1918 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1919 | DELAY(200)(*delay_func)(200); |
| 1920 | AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), ( 0x8240)) & ~(0x00000040))); |
| 1921 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1922 | |
| 1923 | for (ntries = 0; ntries < 40; ntries++) { |
| 1924 | if (!athn_tx_pending(sc, qid)) |
| 1925 | break; |
| 1926 | DELAY(100)(*delay_func)(100); |
| 1927 | } |
| 1928 | |
| 1929 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) & ~(0x00400000))); |
| 1930 | } |
| 1931 | AR_WRITE(sc, AR_Q_TXD, 0)(sc)->ops.write((sc), (0x0880), (0)); |
| 1932 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 1933 | } |
| 1934 | |
| 1935 | int |
| 1936 | athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) |
| 1937 | { |
| 1938 | struct ieee80211com *ic = &sc->sc_ic; |
| 1939 | #define divround(a, b) (((a) + (b) - 1) / (b)) |
| 1940 | int txtime; |
| 1941 | |
| 1942 | if (athn_rates[ridx].hwrate & 0x80) { /* MCS */ |
| 1943 | /* Assumes a 20MHz channel, HT-mixed frame format, no STBC. */ |
| 1944 | txtime = 8 + 8 + 4 + 4 + 4 * 4 + 8 /* HT PLCP */ |
| 1945 | + 4 * ((8 * len + 16 + 6) / (athn_rates[ridx].rate * 2)); |
| 1946 | if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0 )) |
| 1947 | txtime += 6; /* aSignalExtension */ |
| 1948 | } else if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { |
| 1949 | txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); |
| 1950 | /* SIFS is 10us for 11g but Signal Extension adds 6us. */ |
| 1951 | txtime = 16 + 4 + 4 * txtime + 16; |
| 1952 | } else { |
| 1953 | txtime = divround(16 * len, athn_rates[ridx].rate); |
| 1954 | if (ridx != ATHN_RIDX_CCK10 && (flags & IEEE80211_F_SHPREAMBLE0x00040000)) |
| 1955 | txtime += 72 + 24; |
| 1956 | else |
| 1957 | txtime += 144 + 48; |
| 1958 | txtime += 10; /* 10us SIFS. */ |
| 1959 | } |
| 1960 | return (txtime); |
| 1961 | #undef divround |
| 1962 | } |
| 1963 | |
| 1964 | void |
| 1965 | athn_init_tx_queues(struct athn_softc *sc) |
| 1966 | { |
| 1967 | int qid; |
| 1968 | |
| 1969 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) { |
| 1970 | SIMPLEQ_INIT(&sc->txq[qid].head)do { (&sc->txq[qid].head)->sqh_first = ((void *)0); (&sc->txq[qid].head)->sqh_last = &(&sc-> txq[qid].head)->sqh_first; } while (0); |
| 1971 | sc->txq[qid].lastds = NULL((void *)0); |
| 1972 | sc->txq[qid].wait = NULL((void *)0); |
| 1973 | sc->txq[qid].queued = 0; |
| 1974 | |
| 1975 | AR_WRITE(sc, AR_DRETRY_LIMIT(qid),(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t )(32) << 8) & 0x00003f00) | (((uint32_t)(32) << 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f ))) |
| 1976 | SM(AR_D_RETRY_LIMIT_STA_SH, 32) |(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t )(32) << 8) & 0x00003f00) | (((uint32_t)(32) << 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f ))) |
| 1977 | SM(AR_D_RETRY_LIMIT_STA_LG, 32) |(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t )(32) << 8) & 0x00003f00) | (((uint32_t)(32) << 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f ))) |
| 1978 | SM(AR_D_RETRY_LIMIT_FR_SH, 10))(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t )(32) << 8) & 0x00003f00) | (((uint32_t)(32) << 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f ))); |
| 1979 | AR_WRITE(sc, AR_QMISC(qid),(sc)->ops.write((sc), ((0x09c0 + (qid) * 4)), (0x00000800) ) |
| 1980 | AR_Q_MISC_DCU_EARLY_TERM_REQ)(sc)->ops.write((sc), ((0x09c0 + (qid) * 4)), (0x00000800) ); |
| 1981 | AR_WRITE(sc, AR_DMISC(qid),(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t )(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100) ) |
| 1982 | SM(AR_D_MISC_BKOFF_THRESH, 2) |(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t )(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100) ) |
| 1983 | AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN)(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t )(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100) ); |
| 1984 | } |
| 1985 | |
| 1986 | /* Init beacon queue. */ |
| 1987 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020 ))) |
| 1988 | AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE |(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020 ))) |
| 1989 | AR_Q_MISC_CBR_INCR_DIS1)(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020 ))); |
| 1990 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops. read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000) | 0x00010000 | 0x00200000))) |
| 1991 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops. read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000) | 0x00010000 | 0x00200000))) |
| 1992 | AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops. read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000) | 0x00010000 | 0x00200000))) |
| 1993 | AR_D_MISC_BEACON_USE |(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops. read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000) | 0x00010000 | 0x00200000))) |
| 1994 | AR_D_MISC_POST_FR_BKOFF_DIS)(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops. read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000) | 0x00010000 | 0x00200000))); |
| 1995 | AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)( 0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10 ) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000 ))) |
| 1996 | SM(AR_D_LCL_IFS_CWMIN, 0) |(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)( 0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10 ) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000 ))) |
| 1997 | SM(AR_D_LCL_IFS_CWMAX, 0) |(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)( 0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10 ) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000 ))) |
| 1998 | SM(AR_D_LCL_IFS_AIFS, 1))(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)( 0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10 ) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000 ))); |
| 1999 | |
| 2000 | /* Init CAB (Content After Beacon) queue. */ |
| 2001 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040 ))) |
| 2002 | AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040 ))) |
| 2003 | AR_Q_MISC_CBR_INCR_DIS0)(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040 ))); |
| 2004 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops. read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000)))) |
| 2005 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops. read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000)))) |
| 2006 | AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL))(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops. read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17 ) & 0x00060000)))); |
| 2007 | |
| 2008 | /* Init PS-Poll queue. */ |
| 2009 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),(sc)->ops.write((sc), ((0x09c0 + (1) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (1) * 4))) | (0x00000020))) |
| 2010 | AR_Q_MISC_CBR_INCR_DIS1)(sc)->ops.write((sc), ((0x09c0 + (1) * 4)), ((sc)->ops. read((sc), ((0x09c0 + (1) * 4))) | (0x00000020))); |
| 2011 | |
| 2012 | /* Init UAPSD queue. */ |
| 2013 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),(sc)->ops.write((sc), ((0x1100 + (5) * 4)), ((sc)->ops. read((sc), ((0x1100 + (5) * 4))) | (0x00200000))) |
| 2014 | AR_D_MISC_POST_FR_BKOFF_DIS)(sc)->ops.write((sc), ((0x1100 + (5) * 4)), ((sc)->ops. read((sc), ((0x1100 + (5) * 4))) | (0x00200000))); |
| 2015 | |
| 2016 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 2017 | /* Enable MAC descriptor CRC check. */ |
| 2018 | AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN)(sc)->ops.write((sc), (0x0a44), (0x00000001)); |
| 2019 | } |
| 2020 | /* Enable DESC interrupts for all Tx queues. */ |
| 2021 | AR_WRITE(sc, AR_IMR_S0, 0x00ff0000)(sc)->ops.write((sc), (0x00a4), (0x00ff0000)); |
| 2022 | /* Enable EOL interrupts for all Tx queues except UAPSD. */ |
| 2023 | AR_WRITE(sc, AR_IMR_S1, 0x00df0000)(sc)->ops.write((sc), (0x00a8), (0x00df0000)); |
| 2024 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2025 | } |
| 2026 | |
| 2027 | void |
| 2028 | athn_set_sta_timers(struct athn_softc *sc) |
| 2029 | { |
| 2030 | struct ieee80211com *ic = &sc->sc_ic; |
| 2031 | uint32_t tsfhi, tsflo, tsftu, reg; |
| 2032 | uint32_t intval, next_tbtt, next_dtim; |
| 2033 | int dtim_period, dtim_count, rem_dtim_count; |
| 2034 | |
| 2035 | tsfhi = AR_READ(sc, AR_TSF_U32)(sc)->ops.read((sc), (0x8050)); |
| 2036 | tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)); |
| 2037 | tsftu = AR_TSF_TO_TU(tsfhi, tsflo)((tsfhi) << 22 | (tsflo) >> 10) + AR_FUDGE2; |
| 2038 | |
| 2039 | /* Beacon interval in TU. */ |
| 2040 | intval = ic->ic_bss->ni_intval; |
| 2041 | |
| 2042 | next_tbtt = roundup(tsftu, intval)((((tsftu)+((intval)-1))/(intval))*(intval)); |
| 2043 | #ifdef notyet |
| 2044 | dtim_period = ic->ic_dtim_period; |
| 2045 | if (dtim_period <= 0) |
| 2046 | #endif |
| 2047 | dtim_period = 1; /* Assume all TIMs are DTIMs. */ |
| 2048 | |
| 2049 | #ifdef notyet |
| 2050 | dtim_count = ic->ic_dtim_count; |
| 2051 | if (dtim_count >= dtim_period) /* Should not happen. */ |
| 2052 | #endif |
| 2053 | dtim_count = 0; /* Assume last TIM was a DTIM. */ |
Value stored to 'dtim_count' is never read | |
| 2054 | |
| 2055 | /* Compute number of remaining TIMs until next DTIM. */ |
| 2056 | rem_dtim_count = 0; /* XXX */ |
| 2057 | next_dtim = next_tbtt + rem_dtim_count * intval; |
| 2058 | |
| 2059 | AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (0) * 4)), (next_tbtt * 1024 )); |
| 2060 | AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (8) * 4)), (intval * 1024 )); |
| 2061 | AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (9) * 4)), (intval * 1024 )); |
| 2062 | |
| 2063 | /* |
| 2064 | * Set the number of consecutive beacons to miss before raising |
| 2065 | * a BMISS interrupt to 10. |
| 2066 | */ |
| 2067 | reg = AR_READ(sc, AR_RSSI_THR)(sc)->ops.read((sc), (0x8018)); |
| 2068 | reg = RW(reg, AR_RSSI_THR_BM_THR, 10)(((reg) & ~0x0000ff00) | (((uint32_t)(10) << 8) & 0x0000ff00)); |
| 2069 | AR_WRITE(sc, AR_RSSI_THR, reg)(sc)->ops.write((sc), (0x8018), (reg)); |
| 2070 | |
| 2071 | AR_WRITE(sc, AR_NEXT_DTIM,(sc)->ops.write((sc), ((0x8200 + (5) * 4)), ((next_dtim - 3 ) * 1024)) |
| 2072 | (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (5) * 4)), ((next_dtim - 3 ) * 1024)); |
| 2073 | AR_WRITE(sc, AR_NEXT_TIM,(sc)->ops.write((sc), ((0x8200 + (4) * 4)), ((next_tbtt - 3 ) * 1024)) |
| 2074 | (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (4) * 4)), ((next_tbtt - 3 ) * 1024)); |
| 2075 | |
| 2076 | /* CAB timeout is in 1/8 TU. */ |
| 2077 | AR_WRITE(sc, AR_SLEEP1,(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) << 21) & 0xffe00000) | 0x00080000)) |
| 2078 | SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) << 21) & 0xffe00000) | 0x00080000)) |
| 2079 | AR_SLEEP1_ASSUME_DTIM)(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) << 21) & 0xffe00000) | 0x00080000)); |
| 2080 | AR_WRITE(sc, AR_SLEEP2,(sc)->ops.write((sc), (0x80d8), ((((uint32_t)(1) << 21 ) & 0xffe00000))) |
| 2081 | SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL))(sc)->ops.write((sc), (0x80d8), ((((uint32_t)(1) << 21 ) & 0xffe00000))); |
| 2082 | |
| 2083 | AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (12) * 4)), (intval * 1024 )); |
| 2084 | AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (13) * 4)), (dtim_period * intval * 1024)); |
| 2085 | |
| 2086 | AR_SETBITS(sc, AR_TIMER_MODE,(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), ( 0x8240)) | (0x00000001 | 0x00000010 | 0x00000020))) |
| 2087 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), ( 0x8240)) | (0x00000001 | 0x00000010 | 0x00000020))); |
| 2088 | |
| 2089 | /* Set TSF out-of-range threshold (fixed at 16k us). */ |
| 2090 | AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240)(sc)->ops.write((sc), (0x813c), (0x4240)); |
| 2091 | |
| 2092 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2093 | } |
| 2094 | |
| 2095 | #ifndef IEEE80211_STA_ONLY |
| 2096 | void |
| 2097 | athn_set_hostap_timers(struct athn_softc *sc) |
| 2098 | { |
| 2099 | struct ieee80211com *ic = &sc->sc_ic; |
| 2100 | uint32_t intval, next_tbtt; |
| 2101 | |
| 2102 | /* Beacon interval in TU. */ |
| 2103 | intval = ic->ic_bss->ni_intval; |
| 2104 | next_tbtt = intval; |
| 2105 | |
| 2106 | AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (0) * 4)), (next_tbtt * 1024 )); |
| 2107 | AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,(sc)->ops.write((sc), ((0x8200 + (1) * 4)), ((next_tbtt - 2 ) * 1024)) |
| 2108 | (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (1) * 4)), ((next_tbtt - 2 ) * 1024)); |
| 2109 | AR_WRITE(sc, AR_NEXT_CFP,(sc)->ops.write((sc), ((0x8200 + (2) * 4)), ((next_tbtt - 10 ) * 1024)) |
| 2110 | (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (2) * 4)), ((next_tbtt - 10 ) * 1024)); |
| 2111 | |
| 2112 | AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (8) * 4)), (intval * 1024 )); |
| 2113 | AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (9) * 4)), (intval * 1024 )); |
| 2114 | AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (10) * 4)), (intval * 1024 )); |
| 2115 | AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (15) * 4)), (intval * 1024 )); |
| 2116 | |
| 2117 | AR_WRITE(sc, AR_TIMER_MODE,(sc)->ops.write((sc), (0x8240), (0x00000001 | 0x00000002 | 0x00000004)) |
| 2118 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN)(sc)->ops.write((sc), (0x8240), (0x00000001 | 0x00000002 | 0x00000004)); |
| 2119 | |
| 2120 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2121 | } |
| 2122 | #endif |
| 2123 | |
| 2124 | void |
| 2125 | athn_set_opmode(struct athn_softc *sc) |
| 2126 | { |
| 2127 | uint32_t reg; |
| 2128 | |
| 2129 | switch (sc->sc_ic.ic_opmode) { |
| 2130 | #ifndef IEEE80211_STA_ONLY |
| 2131 | case IEEE80211_M_HOSTAP: |
| 2132 | reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004)); |
| 2133 | reg &= ~AR_STA_ID1_ADHOC0x00020000; |
| 2134 | reg |= AR_STA_ID1_STA_AP0x00010000 | AR_STA_ID1_KSRCH_MODE0x10000000; |
| 2135 | AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg)); |
| 2136 | |
| 2137 | AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION)(sc)->ops.write((sc), (0x0014), ((sc)->ops.read((sc), ( 0x0014)) & ~(0x00000020))); |
| 2138 | break; |
| 2139 | case IEEE80211_M_IBSS: |
| 2140 | case IEEE80211_M_AHDEMO: |
| 2141 | reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004)); |
| 2142 | reg &= ~AR_STA_ID1_STA_AP0x00010000; |
| 2143 | reg |= AR_STA_ID1_ADHOC0x00020000 | AR_STA_ID1_KSRCH_MODE0x10000000; |
| 2144 | AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg)); |
| 2145 | |
| 2146 | AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION)(sc)->ops.write((sc), (0x0014), ((sc)->ops.read((sc), ( 0x0014)) | (0x00000020))); |
| 2147 | break; |
| 2148 | #endif |
| 2149 | default: |
| 2150 | reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004)); |
| 2151 | reg &= ~(AR_STA_ID1_ADHOC0x00020000 | AR_STA_ID1_STA_AP0x00010000); |
| 2152 | reg |= AR_STA_ID1_KSRCH_MODE0x10000000; |
| 2153 | AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg)); |
| 2154 | break; |
| 2155 | } |
| 2156 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2157 | } |
| 2158 | |
| 2159 | void |
| 2160 | athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) |
| 2161 | { |
| 2162 | const uint8_t *bssid = ni->ni_bssid; |
| 2163 | |
| 2164 | AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]))(sc)->ops.write((sc), (0x8008), (((&bssid[0])[0] | (& bssid[0])[1] << 8 | (&bssid[0])[2] << 16 | (& bssid[0])[3] << 24))); |
| 2165 | AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |(sc)->ops.write((sc), (0x800c), (((&bssid[4])[0] | (& bssid[4])[1] << 8) | (((uint32_t)(((ni->ni_associd) & ~ 0xc000)) << 16) & 0x07ff0000))) |
| 2166 | SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)))(sc)->ops.write((sc), (0x800c), (((&bssid[4])[0] | (& bssid[4])[1] << 8) | (((uint32_t)(((ni->ni_associd) & ~ 0xc000)) << 16) & 0x07ff0000))); |
| 2167 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2168 | } |
| 2169 | |
| 2170 | void |
| 2171 | athn_enable_interrupts(struct athn_softc *sc) |
| 2172 | { |
| 2173 | uint32_t mask2; |
| 2174 | |
| 2175 | athn_disable_interrupts(sc); /* XXX */ |
| 2176 | |
| 2177 | AR_WRITE(sc, AR_IMR, sc->imask)(sc)->ops.write((sc), (0x00a0), (sc->imask)); |
| 2178 | |
| 2179 | mask2 = AR_READ(sc, AR_IMR_S2)(sc)->ops.read((sc), (0x00ac)); |
| 2180 | mask2 &= ~(AR_IMR_S2_TIM0x01000000 | AR_IMR_S2_DTIM0x20000000 | AR_IMR_S2_DTIMSYNC0x04000000 | |
| 2181 | AR_IMR_S2_CABEND0x02000000 | AR_IMR_S2_CABTO0x10000000 | AR_IMR_S2_TSFOOR0x40000000); |
| 2182 | mask2 |= AR_IMR_S2_GTT0x00800000 | AR_IMR_S2_CST0x00400000; |
| 2183 | AR_WRITE(sc, AR_IMR_S2, mask2)(sc)->ops.write((sc), (0x00ac), (mask2)); |
| 2184 | |
| 2185 | AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER)(sc)->ops.write((sc), (0x00b8), ((sc)->ops.read((sc), ( 0x00b8)) & ~(0x00000010))); |
| 2186 | |
| 2187 | AR_WRITE(sc, AR_IER, AR_IER_ENABLE)(sc)->ops.write((sc), (0x0024), (0x00000001)); |
| 2188 | |
| 2189 | AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ)(sc)->ops.write((sc), (0x403c), (0x00000002)); |
| 2190 | AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ)(sc)->ops.write((sc), (0x4030), (0x00000002)); |
| 2191 | |
| 2192 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync)(sc)->ops.write((sc), (0x402c), (sc->isync)); |
| 2193 | AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync)(sc)->ops.write((sc), (0x4034), (sc->isync)); |
| 2194 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2195 | } |
| 2196 | |
| 2197 | void |
| 2198 | athn_disable_interrupts(struct athn_softc *sc) |
| 2199 | { |
| 2200 | AR_WRITE(sc, AR_IER, 0)(sc)->ops.write((sc), (0x0024), (0)); |
| 2201 | (void)AR_READ(sc, AR_IER)(sc)->ops.read((sc), (0x0024)); |
| 2202 | |
| 2203 | AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0)(sc)->ops.write((sc), (0x403c), (0)); |
| 2204 | (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE)(sc)->ops.read((sc), (0x403c)); |
| 2205 | |
| 2206 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x402c), (0)); |
| 2207 | (void)AR_READ(sc, AR_INTR_SYNC_ENABLE)(sc)->ops.read((sc), (0x402c)); |
| 2208 | |
| 2209 | AR_WRITE(sc, AR_IMR, 0)(sc)->ops.write((sc), (0x00a0), (0)); |
| 2210 | |
| 2211 | AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), ( 0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000))) |
| 2212 | AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), ( 0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000))) |
| 2213 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST)(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), ( 0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000))); |
| 2214 | |
| 2215 | AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER)(sc)->ops.write((sc), (0x00b8), ((sc)->ops.read((sc), ( 0x00b8)) & ~(0x00000010))); |
| 2216 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2217 | } |
| 2218 | |
| 2219 | void |
| 2220 | athn_init_qos(struct athn_softc *sc) |
| 2221 | { |
| 2222 | /* Initialize QoS settings. */ |
| 2223 | AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa)(sc)->ops.write((sc), (0x8118), (0x100aa)); |
| 2224 | AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210)(sc)->ops.write((sc), (0x811c), (0x3210)); |
| 2225 | AR_WRITE(sc, AR_QOS_NO_ACK,(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0 ) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f ) | (((uint32_t)(0) << 7) & 0x00000180))) |
| 2226 | SM(AR_QOS_NO_ACK_TWO_BIT, 2) |(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0 ) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f ) | (((uint32_t)(0) << 7) & 0x00000180))) |
| 2227 | SM(AR_QOS_NO_ACK_BIT_OFF, 5) |(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0 ) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f ) | (((uint32_t)(0) << 7) & 0x00000180))) |
| 2228 | SM(AR_QOS_NO_ACK_BYTE_OFF, 0))(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0 ) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f ) | (((uint32_t)(0) << 7) & 0x00000180))); |
| 2229 | AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL)(sc)->ops.write((sc), (0x81ec), (0x000000ff)); |
| 2230 | /* Initialize TXOP for all TIDs. */ |
| 2231 | AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff)(sc)->ops.write((sc), (0x81f0), (0xffffffff)); |
| 2232 | AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff)(sc)->ops.write((sc), (0x81f4), (0xffffffff)); |
| 2233 | AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff)(sc)->ops.write((sc), (0x81f8), (0xffffffff)); |
| 2234 | AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff)(sc)->ops.write((sc), (0x81fc), (0xffffffff)); |
| 2235 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2236 | } |
| 2237 | |
| 2238 | int |
| 2239 | athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c, |
| 2240 | struct ieee80211_channel *extc, int init) |
| 2241 | { |
| 2242 | struct ieee80211com *ic = &sc->sc_ic; |
| 2243 | struct athn_ops *ops = &sc->ops; |
| 2244 | uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; |
| 2245 | int i, error; |
| 2246 | |
| 2247 | /* XXX not if already awake */ |
| 2248 | if ((error = athn_set_power_awake(sc)) != 0) { |
| 2249 | printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); |
| 2250 | return (error); |
| 2251 | } |
| 2252 | |
| 2253 | /* Preserve the antenna on a channel switch. */ |
| 2254 | if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)(sc)->ops.read((sc), (0x8058))) == 0) |
| 2255 | def_ant = 1; |
| 2256 | /* Preserve other registers. */ |
| 2257 | sta_id1 = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004)) & AR_STA_ID1_BASE_RATE_11B0x02000000; |
| 2258 | cfg_led = AR_READ(sc, AR_CFG_LED)(sc)->ops.read((sc), (0x1f04)) & (AR_CFG_LED_ASSOC_CTL_M0x00000c00 | |
| 2259 | AR_CFG_LED_MODE_SEL_M0x00000380 | AR_CFG_LED_BLINK_THRESH_SEL_M0x00000070 | |
| 2260 | AR_CFG_LED_BLINK_SLOW0x00000008); |
| 2261 | |
| 2262 | /* Mark PHY as inactive. */ |
| 2263 | ops->disable_phy(sc); |
| 2264 | |
| 2265 | if (init && AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) { |
| 2266 | AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,(sc)->ops.write((sc), (0x050044), (0x00000020)) |
| 2267 | AR9271_RADIO_RF_RST)(sc)->ops.write((sc), (0x050044), (0x00000020)); |
| 2268 | DELAY(50)(*delay_func)(50); |
| 2269 | } |
| 2270 | if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080) && (sc->flags & ATHN_FLAG_OLPC(1 << 2))) { |
| 2271 | /* Save TSF before it gets cleared. */ |
| 2272 | tsfhi = AR_READ(sc, AR_TSF_U32)(sc)->ops.read((sc), (0x8050)); |
| 2273 | tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)); |
| 2274 | |
| 2275 | /* NB: RTC reset clears TSF. */ |
| 2276 | error = athn_reset_power_on(sc); |
| 2277 | } else |
| 2278 | error = athn_reset(sc, 0); |
| 2279 | if (error != 0) { |
| 2280 | printf("%s: could not reset chip (error=%d)\n", |
| 2281 | sc->sc_dev.dv_xname, error); |
| 2282 | return (error); |
| 2283 | } |
| 2284 | |
| 2285 | /* XXX not if already awake */ |
| 2286 | if ((error = athn_set_power_awake(sc)) != 0) { |
| 2287 | printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); |
| 2288 | return (error); |
| 2289 | } |
| 2290 | |
| 2291 | athn_init_pll(sc, c); |
| 2292 | ops->set_rf_mode(sc, c); |
| 2293 | |
| 2294 | if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) { |
| 2295 | /* Check that the radio is not disabled by hardware switch. */ |
| 2296 | reg = ops->gpio_read(sc, sc->rfsilent_pin); |
| 2297 | if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED(1 << 6)) |
| 2298 | reg = !reg; |
| 2299 | if (!reg) { |
| 2300 | printf("%s: radio is disabled by hardware switch\n", |
| 2301 | sc->sc_dev.dv_xname); |
| 2302 | return (EPERM1); |
| 2303 | } |
| 2304 | } |
| 2305 | if (init && AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) { |
| 2306 | AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,(sc)->ops.write((sc), (0x050044), (0x00004000)) |
| 2307 | AR9271_GATE_MAC_CTL)(sc)->ops.write((sc), (0x050044), (0x00004000)); |
| 2308 | DELAY(50)(*delay_func)(50); |
| 2309 | } |
| 2310 | if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080) && (sc->flags & ATHN_FLAG_OLPC(1 << 2))) { |
| 2311 | /* Restore TSF if it got cleared. */ |
| 2312 | AR_WRITE(sc, AR_TSF_L32, tsflo)(sc)->ops.write((sc), (0x804c), (tsflo)); |
| 2313 | AR_WRITE(sc, AR_TSF_U32, tsfhi)(sc)->ops.write((sc), (0x8050), (tsfhi)); |
| 2314 | } |
| 2315 | |
| 2316 | if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080)) |
| 2317 | AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)-> ops.read((sc), (sc->gpio_input_en_off)) | (0x00020000))); |
| 2318 | |
| 2319 | if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) && (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 2320 | ar9287_1_3_enable_async_fifo(sc); |
| 2321 | |
| 2322 | /* Write init values to hardware. */ |
| 2323 | ops->hw_init(sc, c, extc); |
| 2324 | |
| 2325 | /* |
| 2326 | * Only >=AR9280 2.0 parts are capable of encrypting unicast |
| 2327 | * management frames using CCMP. |
| 2328 | */ |
| 2329 | if (AR_SREV_9280_20_OR_LATER(sc)((sc)->mac_ver > 0x080 || (((sc)->mac_ver == 0x080) && (sc)->mac_rev >= 1))) { |
| 2330 | reg = AR_READ(sc, AR_AES_MUTE_MASK1)(sc)->ops.read((sc), (0x8060)); |
| 2331 | /* Do not mask the subtype field in management frames. */ |
| 2332 | reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff)(((reg) & ~0x00ff0000) | (((uint32_t)(0xff) << 16) & 0x00ff0000)); |
| 2333 | reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20 )) << 24) & 0xff000000)) |
| 2334 | ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT |(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20 )) << 24) & 0xff000000)) |
| 2335 | IEEE80211_FC1_MORE_DATA))(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20 )) << 24) & 0xff000000)); |
| 2336 | AR_WRITE(sc, AR_AES_MUTE_MASK1, reg)(sc)->ops.write((sc), (0x8060), (reg)); |
| 2337 | } else if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) { |
| 2338 | /* Disable hardware crypto for management frames. */ |
| 2339 | AR_CLRBITS(sc, AR_PCU_MISC_MODE2,(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), ( 0x8344)) & ~(0x00000002))) |
| 2340 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE)(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), ( 0x8344)) & ~(0x00000002))); |
| 2341 | AR_SETBITS(sc, AR_PCU_MISC_MODE2,(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), ( 0x8344)) | (0x00000004))) |
| 2342 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT)(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), ( 0x8344)) | (0x00000004))); |
| 2343 | } |
| 2344 | |
| 2345 | if (ic->ic_curmode != IEEE80211_MODE_11B) |
| 2346 | ops->set_delta_slope(sc, c, extc); |
| 2347 | |
| 2348 | ops->spur_mitigate(sc, c, extc); |
| 2349 | ops->init_from_rom(sc, c, extc); |
| 2350 | |
| 2351 | /* XXX */ |
| 2352 | AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]))(sc)->ops.write((sc), (0x8000), (((&ic->ic_myaddr[0 ])[0] | (&ic->ic_myaddr[0])[1] << 8 | (&ic-> ic_myaddr[0])[2] << 16 | (&ic->ic_myaddr[0])[3] << 24))); |
| 2353 | AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |(sc)->ops.write((sc), (0x8004), (((&ic->ic_myaddr[4 ])[0] | (&ic->ic_myaddr[4])[1] << 8) | sta_id1 | 0x00800000 | 0x08000000)) |
| 2354 | sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE)(sc)->ops.write((sc), (0x8004), (((&ic->ic_myaddr[4 ])[0] | (&ic->ic_myaddr[4])[1] << 8) | sta_id1 | 0x00800000 | 0x08000000)); |
| 2355 | |
| 2356 | athn_set_opmode(sc); |
| 2357 | |
| 2358 | AR_WRITE(sc, AR_BSSMSKL, 0xffffffff)(sc)->ops.write((sc), (0x80e0), (0xffffffff)); |
| 2359 | AR_WRITE(sc, AR_BSSMSKU, 0xffff)(sc)->ops.write((sc), (0x80e4), (0xffff)); |
| 2360 | |
| 2361 | /* Restore previous antenna. */ |
| 2362 | AR_WRITE(sc, AR_DEF_ANTENNA, def_ant)(sc)->ops.write((sc), (0x8058), (def_ant)); |
| 2363 | |
| 2364 | AR_WRITE(sc, AR_BSS_ID0, 0)(sc)->ops.write((sc), (0x8008), (0)); |
| 2365 | AR_WRITE(sc, AR_BSS_ID1, 0)(sc)->ops.write((sc), (0x800c), (0)); |
| 2366 | |
| 2367 | AR_WRITE(sc, AR_ISR, 0xffffffff)(sc)->ops.write((sc), (0x0080), (0xffffffff)); |
| 2368 | |
| 2369 | AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7))(sc)->ops.write((sc), (0x8018), ((((uint32_t)(7) << 8 ) & 0x0000ff00))); |
| 2370 | |
| 2371 | if ((error = ops->set_synth(sc, c, extc)) != 0) { |
| 2372 | printf("%s: could not set channel\n", sc->sc_dev.dv_xname); |
| 2373 | return (error); |
| 2374 | } |
| 2375 | sc->curchan = c; |
| 2376 | sc->curchanext = extc; |
| 2377 | |
| 2378 | for (i = 0; i < AR_NUM_DCU10; i++) |
| 2379 | AR_WRITE(sc, AR_DQCUMASK(i), 1 << i)(sc)->ops.write((sc), ((0x1000 + (i) * 4)), (1 << i) ); |
| 2380 | |
| 2381 | athn_init_tx_queues(sc); |
| 2382 | |
| 2383 | /* Initialize interrupt mask. */ |
| 2384 | sc->imask = |
| 2385 | AR_IMR_TXDESC0x00000080 | AR_IMR_TXEOL0x00000400 | |
| 2386 | AR_IMR_RXERR0x00000004 | AR_IMR_RXEOL0x00000010 | AR_IMR_RXORN0x00000020 | |
| 2387 | AR_IMR_RXMINTR0x01000000 | AR_IMR_RXINTM0x80000000 | |
| 2388 | AR_IMR_GENTMR0x10000000 | AR_IMR_BCNMISC0x00800000; |
| 2389 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 2390 | sc->imask |= AR_IMR_RXERR0x00000004 | AR_IMR_HP_RXOK0x00000001; |
| 2391 | #ifndef IEEE80211_STA_ONLY |
| 2392 | if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) |
| 2393 | sc->imask |= AR_IMR_MIB0x00001000; |
| 2394 | #endif |
| 2395 | AR_WRITE(sc, AR_IMR, sc->imask)(sc)->ops.write((sc), (0x00a0), (sc->imask)); |
| 2396 | AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT)(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), ( 0x00ac)) | (0x00800000))); |
| 2397 | AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff)(sc)->ops.write((sc), (0x4028), (0xffffffff)); |
| 2398 | sc->isync = AR_INTR_SYNC_DEFAULT(0x00000020 | 0x00000040 | 0x00000100 | 0x00000200 | 0x00000400 | 0x00000800 | 0x00001000 | 0x00002000 | 0x00020000); |
| 2399 | if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) |
| 2400 | sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin)(1 << (18 + (sc->rfsilent_pin))); |
| 2401 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync)(sc)->ops.write((sc), (0x402c), (sc->isync)); |
| 2402 | AR_WRITE(sc, AR_INTR_SYNC_MASK, 0)(sc)->ops.write((sc), (0x4034), (0)); |
| 2403 | if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) { |
| 2404 | AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0)(sc)->ops.write((sc), (0x40d4), (0)); |
| 2405 | AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0)(sc)->ops.write((sc), (0x40c8), (0)); |
| 2406 | AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x40c4), (0)); |
| 2407 | AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0)(sc)->ops.write((sc), (0x40cc), (0)); |
| 2408 | } |
| 2409 | |
| 2410 | athn_init_qos(sc); |
| 2411 | |
| 2412 | AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA)(sc)->ops.write((sc), (0x8120), ((sc)->ops.read((sc), ( 0x8120)) | (0x00000004))); |
| 2413 | |
| 2414 | athn_setsifs(sc); |
| 2415 | athn_updateslot(ic); |
| 2416 | athn_setclockrate(sc); |
| 2417 | if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) && (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 2418 | ar9287_1_3_setup_async_fifo(sc); |
| 2419 | |
| 2420 | /* Disable sequence number generation in hardware. */ |
| 2421 | AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), ( 0x8004)) | (0x20000000))); |
| 2422 | |
| 2423 | athn_init_dma(sc); |
| 2424 | |
| 2425 | /* Program observation bus to see MAC interrupts. */ |
| 2426 | AR_WRITE(sc, sc->obs_off, 8)(sc)->ops.write((sc), (sc->obs_off), (8)); |
| 2427 | |
| 2428 | /* Setup Rx interrupt mitigation. */ |
| 2429 | AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500))(sc)->ops.write((sc), (0x002c), ((((uint32_t)(2000) << 16) & 0xffff0000) | (((uint32_t)(500) << 0) & 0x0000ffff ))); |
| 2430 | |
| 2431 | /* Setup Tx interrupt mitigation. */ |
| 2432 | AR_WRITE(sc, AR_TIMT, SM(AR_TIMT_FIRST, 2000) | SM(AR_TIMT_LAST, 500))(sc)->ops.write((sc), (0x0028), ((((uint32_t)(2000) << 16) & 0xffff0000) | (((uint32_t)(500) << 0) & 0x0000ffff ))); |
| 2433 | |
| 2434 | /* Set maximum interrupt rate threshold (in micro seconds). */ |
| 2435 | AR_WRITE(sc, AR_MIRT, SM(AR_MIRT_RATE_THRES, 2000))(sc)->ops.write((sc), (0x0020), ((((uint32_t)(2000) << 0) & 0x0000ffff))); |
| 2436 | |
| 2437 | ops->init_baseband(sc); |
| 2438 | |
| 2439 | if ((error = athn_init_calib(sc, c, extc)) != 0) { |
| 2440 | printf("%s: could not initialize calibration\n", |
| 2441 | sc->sc_dev.dv_xname); |
| 2442 | return (error); |
| 2443 | } |
| 2444 | |
| 2445 | ops->set_rxchains(sc); |
| 2446 | |
| 2447 | AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ)(sc)->ops.write((sc), (0x1f04), (cfg_led | 3)); |
| 2448 | |
| 2449 | if (sc->flags & ATHN_FLAG_USB(1 << 1)) { |
| 2450 | if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) |
| 2451 | AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB)(sc)->ops.write((sc), (0x0014), (0x00000008 | 0x00000002)); |
| 2452 | else |
| 2453 | AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD)(sc)->ops.write((sc), (0x0014), (0x00000001 | 0x00000004)); |
| 2454 | } |
| 2455 | #if BYTE_ORDER1234 == BIG_ENDIAN4321 |
| 2456 | else { |
| 2457 | /* Default is LE, turn on swapping for BE. */ |
| 2458 | AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD)(sc)->ops.write((sc), (0x0014), (0x00000001 | 0x00000004)); |
| 2459 | } |
| 2460 | #endif |
| 2461 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2462 | |
| 2463 | return (0); |
| 2464 | } |
| 2465 | |
| 2466 | struct ieee80211_node * |
| 2467 | athn_node_alloc(struct ieee80211com *ic) |
| 2468 | { |
| 2469 | struct athn_node *an; |
| 2470 | |
| 2471 | an = malloc(sizeof(struct athn_node), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008); |
| 2472 | if (an && (ic->ic_flags & IEEE80211_F_HTON0x02000000)) |
| 2473 | ieee80211_ra_node_init(&an->rn); |
| 2474 | return (struct ieee80211_node *)an; |
| 2475 | } |
| 2476 | |
| 2477 | void |
| 2478 | athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) |
| 2479 | { |
| 2480 | struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; |
| 2481 | struct athn_node *an = (void *)ni; |
| 2482 | struct ieee80211_rateset *rs = &ni->ni_rates; |
| 2483 | uint8_t rate; |
| 2484 | int ridx, i, j; |
| 2485 | |
| 2486 | if ((ni->ni_flags & IEEE80211_NODE_HT0x0400) == 0) |
| 2487 | ieee80211_amrr_node_init(&sc->amrr, &an->amn); |
| 2488 | else if (ic->ic_opmode == IEEE80211_M_STA) |
| 2489 | ieee80211_ra_node_init(&an->rn); |
| 2490 | |
| 2491 | /* Start at lowest available bit-rate, AMRR will raise. */ |
| 2492 | ni->ni_txrate = 0; |
| 2493 | |
| 2494 | for (i = 0; i < rs->rs_nrates; i++) { |
| 2495 | rate = rs->rs_rates[i] & IEEE80211_RATE_VAL0x7f; |
| 2496 | |
| 2497 | /* Map 802.11 rate to HW rate index. */ |
| 2498 | for (ridx = 0; ridx <= ATHN_RIDX_MAX27; ridx++) |
| 2499 | if (athn_rates[ridx].rate == rate) |
| 2500 | break; |
| 2501 | an->ridx[i] = ridx; |
| 2502 | DPRINTFN(2, ("rate %d index %d\n", rate, ridx)); |
| 2503 | |
| 2504 | /* Compute fallback rate for retries. */ |
| 2505 | an->fallback[i] = i; |
| 2506 | for (j = i - 1; j >= 0; j--) { |
| 2507 | if (athn_rates[an->ridx[j]].phy == |
| 2508 | athn_rates[an->ridx[i]].phy) { |
| 2509 | an->fallback[i] = j; |
| 2510 | break; |
| 2511 | } |
| 2512 | } |
| 2513 | DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i])); |
| 2514 | } |
| 2515 | |
| 2516 | /* In 11n mode, start at lowest available bit-rate, MiRA will raise. */ |
| 2517 | ni->ni_txmcs = 0; |
| 2518 | |
| 2519 | for (i = 0; i <= ATHN_MCS_MAX15; i++) { |
| 2520 | /* Map MCS index to HW rate index. */ |
| 2521 | ridx = ATHN_NUM_LEGACY_RATES15 + i; |
| 2522 | an->ridx[ridx] = ATHN_RIDX_MCS012 + i; |
| 2523 | |
| 2524 | DPRINTFN(2, ("mcs %d index %d ", i, ridx)); |
| 2525 | /* Compute fallback rate for retries. */ |
| 2526 | if (i == 0 || i == 8) { |
| 2527 | /* MCS 0 and 8 fall back to the lowest legacy rate. */ |
| 2528 | if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)(((ni->ni_chan)->ic_flags & 0x0100) != 0)) |
| 2529 | an->fallback[ridx] = ATHN_RIDX_OFDM64; |
| 2530 | else |
| 2531 | an->fallback[ridx] = ATHN_RIDX_CCK10; |
| 2532 | } else { |
| 2533 | /* Other MCS fall back to next supported lower MCS. */ |
| 2534 | an->fallback[ridx] = ATHN_NUM_LEGACY_RATES15 + i; |
| 2535 | for (j = i - 1; j >= 0; j--) { |
| 2536 | if (!isset(ni->ni_rxmcs, j)((ni->ni_rxmcs)[(j)>>3] & (1<<((j)&(8 - 1))))) |
| 2537 | continue; |
| 2538 | an->fallback[ridx] = ATHN_NUM_LEGACY_RATES15 + j; |
| 2539 | break; |
| 2540 | } |
| 2541 | } |
| 2542 | DPRINTFN(2, (" fallback to %d\n", an->fallback[ridx])); |
| 2543 | } |
| 2544 | } |
| 2545 | |
| 2546 | int |
| 2547 | athn_media_change(struct ifnet *ifp) |
| 2548 | { |
| 2549 | struct athn_softc *sc = ifp->if_softc; |
| 2550 | struct ieee80211com *ic = &sc->sc_ic; |
| 2551 | uint8_t rate, ridx; |
| 2552 | int error; |
| 2553 | |
| 2554 | error = ieee80211_media_change(ifp); |
| 2555 | if (error != ENETRESET52) |
| 2556 | return (error); |
| 2557 | |
| 2558 | if (ic->ic_fixed_rate != -1) { |
| 2559 | rate = ic->ic_sup_rates[ic->ic_curmode]. |
| 2560 | rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL0x7f; |
| 2561 | /* Map 802.11 rate to HW rate index. */ |
| 2562 | for (ridx = 0; ridx <= ATHN_RIDX_MAX27; ridx++) |
| 2563 | if (athn_rates[ridx].rate == rate) |
| 2564 | break; |
| 2565 | sc->fixed_ridx = ridx; |
| 2566 | } |
| 2567 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == |
| 2568 | (IFF_UP0x1 | IFF_RUNNING0x40)) { |
| 2569 | athn_stop(ifp, 0); |
| 2570 | error = athn_init(ifp); |
| 2571 | } |
| 2572 | return (error); |
| 2573 | } |
| 2574 | |
| 2575 | void |
| 2576 | athn_next_scan(void *arg) |
| 2577 | { |
| 2578 | struct athn_softc *sc = arg; |
| 2579 | struct ieee80211com *ic = &sc->sc_ic; |
| 2580 | int s; |
| 2581 | |
| 2582 | s = splnet()splraise(0x4); |
| 2583 | if (ic->ic_state == IEEE80211_S_SCAN) |
| 2584 | ieee80211_next_scan(&ic->ic_ific_ac.ac_if); |
| 2585 | splx(s)spllower(s); |
| 2586 | } |
| 2587 | |
| 2588 | int |
| 2589 | athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) |
| 2590 | { |
| 2591 | struct ifnet *ifp = &ic->ic_ific_ac.ac_if; |
| 2592 | struct athn_softc *sc = ifp->if_softc; |
| 2593 | uint32_t reg; |
| 2594 | int error; |
| 2595 | |
| 2596 | timeout_del(&sc->calib_to); |
| 2597 | |
| 2598 | switch (nstate) { |
| 2599 | case IEEE80211_S_INIT: |
| 2600 | athn_set_led(sc, 0); |
| 2601 | break; |
| 2602 | case IEEE80211_S_SCAN: |
| 2603 | /* Make the LED blink while scanning. */ |
| 2604 | athn_set_led(sc, !sc->led_state); |
| 2605 | error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0)); |
| 2606 | if (error != 0) |
| 2607 | return (error); |
| 2608 | timeout_add_msec(&sc->scan_to, 200); |
| 2609 | break; |
| 2610 | case IEEE80211_S_AUTH: |
| 2611 | athn_set_led(sc, 0); |
| 2612 | error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0)); |
| 2613 | if (error != 0) |
| 2614 | return (error); |
| 2615 | break; |
| 2616 | case IEEE80211_S_ASSOC: |
| 2617 | break; |
| 2618 | case IEEE80211_S_RUN: |
| 2619 | athn_set_led(sc, 1); |
| 2620 | #ifndef IEEE80211_STA_ONLY |
| 2621 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
| 2622 | error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0)); |
| 2623 | if (error != 0) |
| 2624 | return (error); |
| 2625 | } else |
| 2626 | #endif |
| 2627 | if (ic->ic_opmode == IEEE80211_M_MONITOR) { |
| 2628 | error = athn_switch_chan(sc, ic->ic_ibss_chan, NULL((void *)0)); |
| 2629 | if (error != 0) |
| 2630 | return (error); |
| 2631 | break; |
| 2632 | } |
| 2633 | |
| 2634 | /* Fake a join to initialize the Tx rate. */ |
| 2635 | athn_newassoc(ic, ic->ic_bss, 1); |
| 2636 | |
| 2637 | athn_set_bss(sc, ic->ic_bss); |
| 2638 | athn_disable_interrupts(sc); |
| 2639 | #ifndef IEEE80211_STA_ONLY |
| 2640 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
| 2641 | athn_set_hostap_timers(sc); |
| 2642 | /* Enable software beacon alert interrupts. */ |
| 2643 | sc->imask |= AR_IMR_SWBA0x00010000; |
| 2644 | } else |
| 2645 | #endif |
| 2646 | { |
| 2647 | athn_set_sta_timers(sc); |
| 2648 | /* Enable beacon miss interrupts. */ |
| 2649 | sc->imask |= AR_IMR_BMISS0x00040000; |
| 2650 | |
| 2651 | /* Stop receiving beacons from other BSS. */ |
| 2652 | reg = AR_READ(sc, AR_RX_FILTER)(sc)->ops.read((sc), (0x803c)); |
| 2653 | reg = (reg & ~AR_RX_FILTER_BEACON0x00000010) | |
| 2654 | AR_RX_FILTER_MYBEACON0x00000200; |
| 2655 | AR_WRITE(sc, AR_RX_FILTER, reg)(sc)->ops.write((sc), (0x803c), (reg)); |
| 2656 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2657 | } |
| 2658 | athn_enable_interrupts(sc); |
| 2659 | |
| 2660 | if (sc->sup_calib_mask != 0) { |
| 2661 | memset(&sc->calib, 0, sizeof(sc->calib))__builtin_memset((&sc->calib), (0), (sizeof(sc->calib ))); |
| 2662 | sc->cur_calib_mask = sc->sup_calib_mask; |
| 2663 | sc->ops.do_calib(sc); |
| 2664 | } |
| 2665 | /* XXX Start ANI. */ |
| 2666 | |
| 2667 | athn_start_noisefloor_calib(sc, 1); |
| 2668 | timeout_add_msec(&sc->calib_to, 500); |
| 2669 | break; |
| 2670 | } |
| 2671 | |
| 2672 | return (sc->sc_newstate(ic, nstate, arg)); |
| 2673 | } |
| 2674 | |
| 2675 | void |
| 2676 | athn_updateedca(struct ieee80211com *ic) |
| 2677 | { |
| 2678 | #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ |
| 2679 | struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; |
| 2680 | const struct ieee80211_edca_ac_params *ac; |
| 2681 | int aci, qid; |
| 2682 | |
| 2683 | for (aci = 0; aci < EDCA_NUM_AC4; aci++) { |
| 2684 | ac = &ic->ic_edca_ac[aci]; |
| 2685 | qid = athn_ac2qid[aci]; |
| 2686 | |
| 2687 | AR_WRITE(sc, AR_DLCL_IFS(qid),(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t )(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) | (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) & 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) & 0x0ff00000))) |
| 2688 | SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t )(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) | (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) & 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) & 0x0ff00000))) |
| 2689 | SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t )(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) | (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) & 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) & 0x0ff00000))) |
| 2690 | SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn))(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t )(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) | (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) & 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) & 0x0ff00000))); |
| 2691 | if (ac->ac_txoplimit != 0) { |
| 2692 | AR_WRITE(sc, AR_DCHNTIME(qid),(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t )(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff) | 0x00100000)) |
| 2693 | SM(AR_D_CHNTIME_DUR,(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t )(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff) | 0x00100000)) |
| 2694 | IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) |(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t )(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff) | 0x00100000)) |
| 2695 | AR_D_CHNTIME_EN)(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t )(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff) | 0x00100000)); |
| 2696 | } else |
| 2697 | AR_WRITE(sc, AR_DCHNTIME(qid), 0)(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), (0)); |
| 2698 | } |
| 2699 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2700 | #undef ATHN_EXP2 |
| 2701 | } |
| 2702 | |
| 2703 | int |
| 2704 | athn_clock_rate(struct athn_softc *sc) |
| 2705 | { |
| 2706 | struct ieee80211com *ic = &sc->sc_ic; |
| 2707 | int clockrate; /* MHz. */ |
| 2708 | |
| 2709 | /* |
| 2710 | * AR9287 v1.3+ MAC runs at 117MHz (instead of 88/44MHz) when |
| 2711 | * ASYNC FIFO is enabled. |
| 2712 | */ |
| 2713 | if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) && (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) |
| 2714 | clockrate = 117; |
| 2715 | else if (ic->ic_bss->ni_chan != IEEE80211_CHAN_ANYC((struct ieee80211_channel *) ((void *)0)) && |
| 2716 | IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0100) != 0 )) { |
| 2717 | if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK(1 << 4)) |
| 2718 | clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM44; |
| 2719 | else |
| 2720 | clockrate = AR_CLOCK_RATE_5GHZ_OFDM40; |
| 2721 | } else if (ic->ic_curmode == IEEE80211_MODE_11B) { |
| 2722 | clockrate = AR_CLOCK_RATE_CCK22; |
| 2723 | } else |
| 2724 | clockrate = AR_CLOCK_RATE_2GHZ_OFDM44; |
| 2725 | if (sc->curchanext != NULL((void *)0)) |
| 2726 | clockrate *= 2; |
| 2727 | |
| 2728 | return (clockrate); |
| 2729 | } |
| 2730 | |
| 2731 | int |
| 2732 | athn_chan_sifs(struct ieee80211_channel *c) |
| 2733 | { |
| 2734 | return IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0) ? IEEE80211_DUR_DS_SIFS10 : 16; |
| 2735 | } |
| 2736 | |
| 2737 | void |
| 2738 | athn_setsifs(struct athn_softc *sc) |
| 2739 | { |
| 2740 | int sifs = athn_chan_sifs(sc->sc_ic.ic_bss->ni_chan); |
| 2741 | AR_WRITE(sc, AR_D_GBL_IFS_SIFS, (sifs - 2) * athn_clock_rate(sc))(sc)->ops.write((sc), (0x1030), ((sifs - 2) * athn_clock_rate (sc))); |
| 2742 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2743 | } |
| 2744 | |
| 2745 | int |
| 2746 | athn_acktimeout(struct ieee80211_channel *c, int slot) |
| 2747 | { |
| 2748 | int sifs = athn_chan_sifs(c); |
| 2749 | int ackto = sifs + slot; |
| 2750 | |
| 2751 | /* Workaround for early ACK timeouts. */ |
| 2752 | if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0)) |
| 2753 | ackto += 64 - sifs - slot; |
| 2754 | |
| 2755 | return ackto; |
| 2756 | } |
| 2757 | |
| 2758 | void |
| 2759 | athn_setacktimeout(struct athn_softc *sc, struct ieee80211_channel *c, int slot) |
| 2760 | { |
| 2761 | int ackto = athn_acktimeout(c, slot); |
| 2762 | uint32_t reg = AR_READ(sc, AR_TIME_OUT)(sc)->ops.read((sc), (0x8014)); |
| 2763 | reg = RW(reg, AR_TIME_OUT_ACK, ackto * athn_clock_rate(sc))(((reg) & ~0x00003fff) | (((uint32_t)(ackto * athn_clock_rate (sc)) << 0) & 0x00003fff)); |
| 2764 | AR_WRITE(sc, AR_TIME_OUT, reg)(sc)->ops.write((sc), (0x8014), (reg)); |
| 2765 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2766 | } |
| 2767 | |
| 2768 | void |
| 2769 | athn_setctstimeout(struct athn_softc *sc, struct ieee80211_channel *c, int slot) |
| 2770 | { |
| 2771 | int ctsto = athn_acktimeout(c, slot); |
| 2772 | int sifs = athn_chan_sifs(c); |
| 2773 | uint32_t reg = AR_READ(sc, AR_TIME_OUT)(sc)->ops.read((sc), (0x8014)); |
| 2774 | |
| 2775 | /* Workaround for early CTS timeouts. */ |
| 2776 | if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0)) |
| 2777 | ctsto += 48 - sifs - slot; |
| 2778 | |
| 2779 | reg = RW(reg, AR_TIME_OUT_CTS, ctsto * athn_clock_rate(sc))(((reg) & ~0x3fff0000) | (((uint32_t)(ctsto * athn_clock_rate (sc)) << 16) & 0x3fff0000)); |
| 2780 | AR_WRITE(sc, AR_TIME_OUT, reg)(sc)->ops.write((sc), (0x8014), (reg)); |
| 2781 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2782 | } |
| 2783 | |
| 2784 | void |
| 2785 | athn_setclockrate(struct athn_softc *sc) |
| 2786 | { |
| 2787 | int clockrate = athn_clock_rate(sc); |
| 2788 | uint32_t reg = AR_READ(sc, AR_USEC)(sc)->ops.read((sc), (0x801c)); |
| 2789 | reg = RW(reg, AR_USEC_USEC, clockrate - 1)(((reg) & ~0x0000007f) | (((uint32_t)(clockrate - 1) << 0) & 0x0000007f)); |
| 2790 | AR_WRITE(sc, AR_USEC, reg)(sc)->ops.write((sc), (0x801c), (reg)); |
| 2791 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2792 | } |
| 2793 | |
| 2794 | void |
| 2795 | athn_updateslot(struct ieee80211com *ic) |
| 2796 | { |
| 2797 | struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; |
| 2798 | int slot; |
| 2799 | |
| 2800 | slot = (ic->ic_flags & IEEE80211_F_SHSLOT0x00020000) ? |
| 2801 | IEEE80211_DUR_DS_SHSLOT9 : IEEE80211_DUR_DS_SLOT20; |
| 2802 | AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc))(sc)->ops.write((sc), (0x1070), (slot * athn_clock_rate(sc ))); |
| 2803 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2804 | |
| 2805 | athn_setacktimeout(sc, ic->ic_bss->ni_chan, slot); |
| 2806 | athn_setctstimeout(sc, ic->ic_bss->ni_chan, slot); |
| 2807 | } |
| 2808 | |
| 2809 | void |
| 2810 | athn_start(struct ifnet *ifp) |
| 2811 | { |
| 2812 | struct athn_softc *sc = ifp->if_softc; |
| 2813 | struct ieee80211com *ic = &sc->sc_ic; |
| 2814 | struct ieee80211_node *ni; |
| 2815 | struct mbuf *m; |
| 2816 | |
| 2817 | if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd)) |
| 2818 | return; |
| 2819 | |
| 2820 | for (;;) { |
| 2821 | if (SIMPLEQ_EMPTY(&sc->txbufs)(((&sc->txbufs)->sqh_first) == ((void *)0))) { |
| 2822 | ifq_set_oactive(&ifp->if_snd); |
| 2823 | break; |
| 2824 | } |
| 2825 | /* Send pending management frames first. */ |
| 2826 | m = mq_dequeue(&ic->ic_mgtq); |
| 2827 | if (m != NULL((void *)0)) { |
| 2828 | ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie; |
| 2829 | goto sendit; |
| 2830 | } |
| 2831 | if (ic->ic_state != IEEE80211_S_RUN) |
| 2832 | break; |
| 2833 | |
| 2834 | m = mq_dequeue(&ic->ic_pwrsaveq); |
| 2835 | if (m != NULL((void *)0)) { |
| 2836 | ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie; |
| 2837 | goto sendit; |
| 2838 | } |
| 2839 | if (ic->ic_state != IEEE80211_S_RUN) |
| 2840 | break; |
| 2841 | |
| 2842 | /* Encapsulate and send data frames. */ |
| 2843 | m = ifq_dequeue(&ifp->if_snd); |
| 2844 | if (m == NULL((void *)0)) |
| 2845 | break; |
| 2846 | #if NBPFILTER1 > 0 |
| 2847 | if (ifp->if_bpf != NULL((void *)0)) |
| 2848 | bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1)); |
| 2849 | #endif |
| 2850 | if ((m = ieee80211_encap(ifp, m, &ni)) == NULL((void *)0)) |
| 2851 | continue; |
| 2852 | sendit: |
| 2853 | #if NBPFILTER1 > 0 |
| 2854 | if (ic->ic_rawbpf != NULL((void *)0)) |
| 2855 | bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT(1 << 1)); |
| 2856 | #endif |
| 2857 | if (sc->ops.tx(sc, m, ni, 0) != 0) { |
| 2858 | ieee80211_release_node(ic, ni); |
| 2859 | ifp->if_oerrorsif_data.ifi_oerrors++; |
| 2860 | continue; |
| 2861 | } |
| 2862 | |
| 2863 | sc->sc_tx_timer = 5; |
| 2864 | ifp->if_timer = 1; |
| 2865 | } |
| 2866 | } |
| 2867 | |
| 2868 | void |
| 2869 | athn_watchdog(struct ifnet *ifp) |
| 2870 | { |
| 2871 | struct athn_softc *sc = ifp->if_softc; |
| 2872 | |
| 2873 | ifp->if_timer = 0; |
| 2874 | |
| 2875 | if (sc->sc_tx_timer > 0) { |
| 2876 | if (--sc->sc_tx_timer == 0) { |
| 2877 | printf("%s: device timeout\n", sc->sc_dev.dv_xname); |
| 2878 | athn_stop(ifp, 1); |
| 2879 | (void)athn_init(ifp); |
| 2880 | ifp->if_oerrorsif_data.ifi_oerrors++; |
| 2881 | return; |
| 2882 | } |
| 2883 | ifp->if_timer = 1; |
| 2884 | } |
| 2885 | |
| 2886 | ieee80211_watchdog(ifp); |
| 2887 | } |
| 2888 | |
| 2889 | void |
| 2890 | athn_set_multi(struct athn_softc *sc) |
| 2891 | { |
| 2892 | struct arpcom *ac = &sc->sc_ic.ic_ac; |
| 2893 | struct ifnet *ifp = &ac->ac_if; |
| 2894 | struct ether_multi *enm; |
| 2895 | struct ether_multistep step; |
| 2896 | const uint8_t *addr; |
| 2897 | uint32_t val, lo, hi; |
| 2898 | uint8_t bit; |
| 2899 | |
| 2900 | if (ac->ac_multirangecnt > 0) |
| 2901 | ifp->if_flags |= IFF_ALLMULTI0x200; |
| 2902 | |
| 2903 | if ((ifp->if_flags & (IFF_ALLMULTI0x200 | IFF_PROMISC0x100)) != 0) { |
| 2904 | lo = hi = 0xffffffff; |
| 2905 | goto done; |
| 2906 | } |
| 2907 | lo = hi = 0; |
| 2908 | ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first ); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step )).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while ( 0); |
| 2909 | while (enm != NULL((void *)0)) { |
| 2910 | addr = enm->enm_addrlo; |
| 2911 | /* Calculate the XOR value of all eight 6-bit words. */ |
| 2912 | val = addr[0] | addr[1] << 8 | addr[2] << 16; |
| 2913 | bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
| 2914 | val = addr[3] | addr[4] << 8 | addr[5] << 16; |
| 2915 | bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
| 2916 | bit &= 0x3f; |
| 2917 | if (bit < 32) |
| 2918 | lo |= 1 << bit; |
| 2919 | else |
| 2920 | hi |= 1 << (bit - 32); |
| 2921 | ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm = (((enm))->enm_list.le_next); } while ( 0); |
| 2922 | } |
| 2923 | done: |
| 2924 | AR_WRITE(sc, AR_MCAST_FIL0, lo)(sc)->ops.write((sc), (0x8040), (lo)); |
| 2925 | AR_WRITE(sc, AR_MCAST_FIL1, hi)(sc)->ops.write((sc), (0x8044), (hi)); |
| 2926 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 2927 | } |
| 2928 | |
| 2929 | int |
| 2930 | athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) |
| 2931 | { |
| 2932 | struct athn_softc *sc = ifp->if_softc; |
| 2933 | struct ieee80211com *ic = &sc->sc_ic; |
| 2934 | struct ifreq *ifr; |
| 2935 | int s, error = 0; |
| 2936 | |
| 2937 | s = splnet()splraise(0x4); |
| 2938 | |
| 2939 | switch (cmd) { |
| 2940 | case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((12))): |
| 2941 | ifp->if_flags |= IFF_UP0x1; |
| 2942 | /* FALLTHROUGH */ |
| 2943 | case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((16))): |
| 2944 | if (ifp->if_flags & IFF_UP0x1) { |
| 2945 | if ((ifp->if_flags & IFF_RUNNING0x40) && |
| 2946 | ((ifp->if_flags ^ sc->sc_if_flags) & |
| 2947 | (IFF_ALLMULTI0x200 | IFF_PROMISC0x100)) != 0) { |
| 2948 | athn_set_multi(sc); |
| 2949 | } else if (!(ifp->if_flags & IFF_RUNNING0x40)) |
| 2950 | error = athn_init(ifp); |
| 2951 | } else { |
| 2952 | if (ifp->if_flags & IFF_RUNNING0x40) |
| 2953 | athn_stop(ifp, 1); |
| 2954 | } |
| 2955 | sc->sc_if_flags = ifp->if_flags; |
| 2956 | break; |
| 2957 | |
| 2958 | case SIOCADDMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((49))): |
| 2959 | case SIOCDELMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((50))): |
| 2960 | ifr = (struct ifreq *)data; |
| 2961 | error = (cmd == SIOCADDMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((49)))) ? |
| 2962 | ether_addmulti(ifr, &ic->ic_ac) : |
| 2963 | ether_delmulti(ifr, &ic->ic_ac); |
| 2964 | if (error == ENETRESET52) { |
| 2965 | athn_set_multi(sc); |
| 2966 | error = 0; |
| 2967 | } |
| 2968 | break; |
| 2969 | |
| 2970 | case SIOCS80211CHANNEL((unsigned long)0x80000000 | ((sizeof(struct ieee80211chanreq ) & 0x1fff) << 16) | ((('i')) << 8) | ((238)) ): |
| 2971 | error = ieee80211_ioctl(ifp, cmd, data); |
| 2972 | if (error == ENETRESET52 && |
| 2973 | ic->ic_opmode == IEEE80211_M_MONITOR) { |
| 2974 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == |
| 2975 | (IFF_UP0x1 | IFF_RUNNING0x40)) |
| 2976 | athn_switch_chan(sc, ic->ic_ibss_chan, NULL((void *)0)); |
| 2977 | error = 0; |
| 2978 | } |
| 2979 | break; |
| 2980 | |
| 2981 | default: |
| 2982 | error = ieee80211_ioctl(ifp, cmd, data); |
| 2983 | } |
| 2984 | |
| 2985 | if (error == ENETRESET52) { |
| 2986 | error = 0; |
| 2987 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == |
| 2988 | (IFF_UP0x1 | IFF_RUNNING0x40)) { |
| 2989 | athn_stop(ifp, 0); |
| 2990 | error = athn_init(ifp); |
| 2991 | } |
| 2992 | } |
| 2993 | |
| 2994 | splx(s)spllower(s); |
| 2995 | return (error); |
| 2996 | } |
| 2997 | |
| 2998 | int |
| 2999 | athn_init(struct ifnet *ifp) |
| 3000 | { |
| 3001 | struct athn_softc *sc = ifp->if_softc; |
| 3002 | struct athn_ops *ops = &sc->ops; |
| 3003 | struct ieee80211com *ic = &sc->sc_ic; |
| 3004 | struct ieee80211_channel *c, *extc; |
| 3005 | int i, error; |
| 3006 | |
| 3007 | c = ic->ic_bss->ni_chan = ic->ic_ibss_chan; |
| 3008 | extc = NULL((void *)0); |
| 3009 | |
| 3010 | /* In case a new MAC address has been configured. */ |
| 3011 | IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl))__builtin_memcpy((ic->ic_myaddr), (((caddr_t)((ifp->if_sadl )->sdl_data + (ifp->if_sadl)->sdl_nlen))), (6)); |
| 3012 | |
| 3013 | /* For CardBus, power on the socket. */ |
| 3014 | if (sc->sc_enable != NULL((void *)0)) { |
| 3015 | if ((error = sc->sc_enable(sc)) != 0) { |
| 3016 | printf("%s: could not enable device\n", |
| 3017 | sc->sc_dev.dv_xname); |
| 3018 | goto fail; |
| 3019 | } |
| 3020 | if ((error = athn_reset_power_on(sc)) != 0) { |
| 3021 | printf("%s: could not power on device\n", |
| 3022 | sc->sc_dev.dv_xname); |
| 3023 | goto fail; |
| 3024 | } |
| 3025 | } |
| 3026 | if (!(sc->flags & ATHN_FLAG_PCIE(1 << 0))) |
| 3027 | athn_config_nonpcie(sc); |
| 3028 | else |
| 3029 | athn_config_pcie(sc); |
| 3030 | |
| 3031 | ops->enable_antenna_diversity(sc); |
| 3032 | |
| 3033 | #ifdef ATHN_BT_COEXISTENCE |
| 3034 | /* Configure bluetooth coexistence for combo chips. */ |
| 3035 | if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8))) |
| 3036 | athn_btcoex_init(sc); |
| 3037 | #endif |
| 3038 | |
| 3039 | /* Configure LED. */ |
| 3040 | athn_led_init(sc); |
| 3041 | |
| 3042 | /* Configure hardware radio switch. */ |
| 3043 | if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) |
| 3044 | ops->rfsilent_init(sc); |
| 3045 | |
| 3046 | if ((error = athn_hw_reset(sc, c, extc, 1)) != 0) { |
| 3047 | printf("%s: unable to reset hardware; reset status %d\n", |
| 3048 | sc->sc_dev.dv_xname, error); |
| 3049 | goto fail; |
| 3050 | } |
| 3051 | |
| 3052 | athn_config_ht(sc); |
| 3053 | |
| 3054 | /* Enable Rx. */ |
| 3055 | athn_rx_start(sc); |
| 3056 | |
| 3057 | /* Reset HW key cache entries. */ |
| 3058 | for (i = 0; i < sc->kc_entries; i++) |
| 3059 | athn_reset_key(sc, i); |
| 3060 | |
| 3061 | /* Enable interrupts. */ |
| 3062 | athn_enable_interrupts(sc); |
| 3063 | |
| 3064 | #ifdef ATHN_BT_COEXISTENCE |
| 3065 | /* Enable bluetooth coexistence for combo chips. */ |
| 3066 | if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8))) |
| 3067 | athn_btcoex_enable(sc); |
| 3068 | #endif |
| 3069 | |
| 3070 | ifq_clr_oactive(&ifp->if_snd); |
| 3071 | ifp->if_flags |= IFF_RUNNING0x40; |
| 3072 | |
| 3073 | #ifdef notyet |
| 3074 | if (ic->ic_flags & IEEE80211_F_WEPON0x00000100) { |
| 3075 | /* Configure WEP keys. */ |
| 3076 | for (i = 0; i < IEEE80211_WEP_NKID4; i++) |
| 3077 | athn_set_key(ic, NULL((void *)0), &ic->ic_nw_keys[i]); |
| 3078 | } |
| 3079 | #endif |
| 3080 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
| 3081 | ieee80211_new_state(ic, IEEE80211_S_RUN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_RUN), (-1))); |
| 3082 | else |
| 3083 | ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1))); |
| 3084 | |
| 3085 | return (0); |
| 3086 | fail: |
| 3087 | athn_stop(ifp, 1); |
| 3088 | return (error); |
| 3089 | } |
| 3090 | |
| 3091 | void |
| 3092 | athn_stop(struct ifnet *ifp, int disable) |
| 3093 | { |
| 3094 | struct athn_softc *sc = ifp->if_softc; |
| 3095 | struct ieee80211com *ic = &sc->sc_ic; |
| 3096 | int qid, i; |
| 3097 | |
| 3098 | ifp->if_timer = sc->sc_tx_timer = 0; |
| 3099 | ifp->if_flags &= ~IFF_RUNNING0x40; |
| 3100 | ifq_clr_oactive(&ifp->if_snd); |
| 3101 | |
| 3102 | timeout_del(&sc->scan_to); |
| 3103 | |
| 3104 | ieee80211_new_state(ic, IEEE80211_S_INIT, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_INIT), (-1))); |
| 3105 | |
| 3106 | #ifdef ATHN_BT_COEXISTENCE |
| 3107 | /* Disable bluetooth coexistence for combo chips. */ |
| 3108 | if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8))) |
| 3109 | athn_btcoex_disable(sc); |
| 3110 | #endif |
| 3111 | |
| 3112 | /* Disable interrupts. */ |
| 3113 | athn_disable_interrupts(sc); |
| 3114 | /* Acknowledge interrupts (avoids interrupt storms). */ |
| 3115 | AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff)(sc)->ops.write((sc), (0x4028), (0xffffffff)); |
| 3116 | AR_WRITE(sc, AR_INTR_SYNC_MASK, 0)(sc)->ops.write((sc), (0x4034), (0)); |
| 3117 | |
| 3118 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 3119 | athn_stop_tx_dma(sc, qid); |
| 3120 | /* XXX call athn_hw_reset if Tx still pending? */ |
| 3121 | for (qid = 0; qid < ATHN_QID_COUNT8; qid++) |
| 3122 | athn_tx_reclaim(sc, qid); |
| 3123 | |
| 3124 | /* Stop Rx. */ |
| 3125 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), ( 0x8048)) | (0x00000020 | 0x02000000))); |
| 3126 | AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC)(sc)->ops.write((sc), (0x0040), (0x00000002)); |
| 3127 | AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC)(sc)->ops.write((sc), (0x0040), (0x00000004)); |
| 3128 | AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0)); |
| 3129 | AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0)); |
| 3130 | AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc)); |
| 3131 | athn_set_rxfilter(sc, 0); |
| 3132 | athn_stop_rx_dma(sc); |
| 3133 | |
| 3134 | /* Reset HW key cache entries. */ |
| 3135 | for (i = 0; i < sc->kc_entries; i++) |
| 3136 | athn_reset_key(sc, i); |
| 3137 | |
| 3138 | athn_reset(sc, 0); |
| 3139 | athn_init_pll(sc, NULL((void *)0)); |
| 3140 | athn_set_power_awake(sc); |
| 3141 | athn_reset(sc, 1); |
| 3142 | athn_init_pll(sc, NULL((void *)0)); |
| 3143 | |
| 3144 | athn_set_power_sleep(sc); |
| 3145 | |
| 3146 | /* For CardBus, power down the socket. */ |
| 3147 | if (disable && sc->sc_disable != NULL((void *)0)) |
| 3148 | sc->sc_disable(sc); |
| 3149 | } |
| 3150 | |
| 3151 | void |
| 3152 | athn_suspend(struct athn_softc *sc) |
| 3153 | { |
| 3154 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; |
| 3155 | |
| 3156 | if (ifp->if_flags & IFF_RUNNING0x40) |
| 3157 | athn_stop(ifp, 1); |
| 3158 | } |
| 3159 | |
| 3160 | void |
| 3161 | athn_wakeup(struct athn_softc *sc) |
| 3162 | { |
| 3163 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; |
| 3164 | |
| 3165 | if (ifp->if_flags & IFF_UP0x1) |
| 3166 | athn_init(ifp); |
| 3167 | } |