/usr/src/sys/dev/pci/if

Bug Summary

File:	dev/pci/if_ngbe.c
Warning:	line 2697, column 25 Dereference of null pointer
Annotated Source Code

Press '?' to see keyboard shortcuts
Show analyzer invocation
clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_ngbe.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/if_ngbe.c
1/*	$OpenBSD: if_ngbe.c,v 1.2 2023/11/10 15:51:20 bluhm Exp $	*/

3/*
* Copyright (c) 2015-2017 Beijing WangXun Technology Co., Ltd.
* Copyright (c) 2023 Kevin Lo <kevlo@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/

20#include "bpfilter.h"
21#include "vlan.h"

23#include <sys/param.h>
24#include <sys/systm.h>
25#include <sys/sockio.h>
26#include <sys/mbuf.h>
27#include <sys/malloc.h>
28#include <sys/kernel.h>
29#include <sys/socket.h>
30#include <sys/device.h>
31#include <sys/endian.h>
32#include <sys/intrmap.h>

34#include <net/if.h>
35#include <net/if_media.h>
36#include <net/toeplitz.h>

38#include <netinet/in.h>
39#include <netinet/if_ether.h>
40#include <netinet/ip.h>
41#include <netinet/ip6.h>

43#if NBPFILTER1 > 0
44#include <net/bpf.h>
45#endif

47#include <machine/bus.h>
48#include <machine/intr.h>

50#include <dev/mii/mii.h>

52#include <dev/pci/pcivar.h>
53#include <dev/pci/pcireg.h>
54#include <dev/pci/pcidevs.h>

56#include <dev/pci/if_ngbereg.h>

58const struct pci_matchid ngbe_devices[] = {
{ PCI_VENDOR_WANGXUN0x8088, PCI_PRODUCT_WANGXUN_WX1860A20x0101 },
{ PCI_VENDOR_WANGXUN0x8088, PCI_PRODUCT_WANGXUN_WX1860AL10x010b }
61};

63int			ngbe_match(struct device *, void *, void *);
64void			ngbe_attach(struct device *, struct device *, void *);
65int			ngbe_detach(struct device *, int);
66void			ngbe_init(void *);
67int			ngbe_ioctl(struct ifnet *, u_long, caddr_t);
68int			ngbe_media_change(struct ifnet *);
69void			ngbe_media_status(struct ifnet *, struct ifmediareq *);
70int			ngbe_rxfill(struct rx_ring *);
71int			ngbe_rxrinfo(struct ngbe_softc *, struct if_rxrinfo *);
72void			ngbe_start(struct ifqueue *);
73void			ngbe_stop(struct ngbe_softc *);
74void			ngbe_update_link_status(struct ngbe_softc *);
75void			ngbe_watchdog(struct ifnet *);
76int			ngbe_allocate_pci_resources(struct ngbe_softc *);
77void			ngbe_free_pci_resources(struct ngbe_softc *);
78int			ngbe_allocate_msix(struct ngbe_softc *);
79void			ngbe_setup_interface(struct ngbe_softc *);
80int			ngbe_setup_msix(struct ngbe_softc *);
81int			ngbe_dma_malloc(struct ngbe_softc *, bus_size_t,
	    struct ngbe_dma_alloc *);
83void			ngbe_dma_free(struct ngbe_softc *,
	    struct ngbe_dma_alloc *);
85int			ngbe_allocate_isb(struct ngbe_softc *);
86void			ngbe_free_isb(struct ngbe_softc *);
87int			ngbe_allocate_queues(struct ngbe_softc *);
88void			ngbe_free_receive_structures(struct ngbe_softc *);
89void			ngbe_free_receive_buffers(struct rx_ring *);
90void			ngbe_free_transmit_structures(struct ngbe_softc *);
91void			ngbe_free_transmit_buffers(struct tx_ring *);
92int			ngbe_allocate_receive_buffers(struct rx_ring *);
93int			ngbe_allocate_transmit_buffers(struct tx_ring *);
94int			ngbe_setup_receive_ring(struct rx_ring *);
95int			ngbe_setup_transmit_ring(struct tx_ring *);
96int			ngbe_setup_receive_structures(struct ngbe_softc *);
97int			ngbe_setup_transmit_structures(struct ngbe_softc *);
98uint8_t *		ngbe_addr_list_itr(struct ngbe_hw *, uint8_t **,
	    uint32_t *);
100void			ngbe_iff(struct ngbe_softc *);
101int			ngbe_initialize_receive_unit(struct ngbe_softc *);
102void			ngbe_initialize_rss_mapping(struct ngbe_softc *);
103int			ngbe_initialize_transmit_unit(struct ngbe_softc *);
104int			ngbe_intr_link(void *);
105int			ngbe_intr_queue(void *);
106void			ngbe_init_eeprom_params(struct ngbe_hw *);
107int			ngbe_init_hw(struct ngbe_softc *);
108void			ngbe_init_ops(struct ngbe_hw *);
109void			ngbe_init_rx_addrs(struct ngbe_softc *);
110void			ngbe_init_shared_code(struct ngbe_softc *);
111void			ngbe_init_thermal_sensor_thresh(struct ngbe_hw *);
112void			ngbe_init_uta_tables(struct ngbe_hw *);
113void			ngbe_fc_autoneg(struct ngbe_softc *);
114int			ngbe_fc_autoneg_copper(struct ngbe_softc *);
115int			ngbe_fc_enable(struct ngbe_softc *);
116int			ngbe_fmgr_cmd_op(struct ngbe_hw *, uint32_t, uint32_t);
117uint32_t		ngbe_flash_read_dword(struct ngbe_hw *, uint32_t);
118uint8_t			ngbe_calculate_checksum(uint8_t *, uint32_t);
119int			ngbe_check_flash_load(struct ngbe_softc *, uint32_t);
120int			ngbe_check_internal_phy_id(struct ngbe_softc *);
121int			ngbe_check_mac_link(struct ngbe_hw *, uint32_t *, int *,
	    int);
123int			ngbe_check_mng_access(struct ngbe_hw *);
124int			ngbe_check_reset_blocked(struct ngbe_softc *);
125void			ngbe_clear_hw_cntrs(struct ngbe_hw *);
126void			ngbe_clear_vfta(struct ngbe_hw *);
127void			ngbe_configure_ivars(struct ngbe_softc *);
128void			ngbe_configure_pb(struct ngbe_softc *);
129void			ngbe_disable_intr(struct ngbe_softc *);
130int			ngbe_disable_pcie_master(struct ngbe_softc *);
131void			ngbe_disable_queue(struct ngbe_softc *, uint32_t);
132void			ngbe_disable_rx(struct ngbe_hw *);
133void			ngbe_disable_sec_rx_path(struct ngbe_hw *);
134int			ngbe_eepromcheck_cap(struct ngbe_softc *, uint16_t,
	    uint32_t *);
136void			ngbe_enable_intr(struct ngbe_softc *);
137void			ngbe_enable_queue(struct ngbe_softc *, uint32_t);
138void			ngbe_enable_rx(struct ngbe_hw *);
139void			ngbe_enable_rx_dma(struct ngbe_hw *, uint32_t);
140void			ngbe_enable_sec_rx_path(struct ngbe_hw *);
141int			ngbe_encap(struct tx_ring *, struct mbuf *);
142int			ngbe_get_buf(struct rx_ring *, int);
143void			ngbe_get_bus_info(struct ngbe_softc *);
144void			ngbe_get_copper_link_capabilities(struct ngbe_hw *,
	    uint32_t *, int *);
146int			ngbe_get_eeprom_semaphore(struct ngbe_softc *);
147void			ngbe_get_hw_control(struct ngbe_hw *);
148void			ngbe_release_hw_control(struct ngbe_softc *);
149void			ngbe_get_mac_addr(struct ngbe_hw *, uint8_t *);
150enum ngbe_media_type	ngbe_get_media_type(struct ngbe_hw *);
151void			ngbe_gphy_dis_eee(struct ngbe_hw *);
152void			ngbe_gphy_efuse_calibration(struct ngbe_softc *);
153void			ngbe_gphy_wait_mdio_access_on(struct ngbe_hw *);
154void			ngbe_handle_phy_event(struct ngbe_softc *);
155int			ngbe_host_interface_command(struct ngbe_softc *,
	    uint32_t *, uint32_t, uint32_t, int);
157int			ngbe_hpbthresh(struct ngbe_softc *);
158int			ngbe_lpbthresh(struct ngbe_softc *);
159int			ngbe_mng_present(struct ngbe_hw *);
160int			ngbe_mta_vector(struct ngbe_hw *, uint8_t *);
161int			ngbe_negotiate_fc(struct ngbe_softc *, uint32_t,
	    uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);
163int			ngbe_non_sfp_link_config(struct ngbe_softc *);
164void			ngbe_pbthresh_setup(struct ngbe_softc *);
165void			ngbe_phy_check_event(struct ngbe_softc *);
166int			ngbe_phy_check_overtemp(struct ngbe_hw *);
167void			ngbe_phy_get_advertised_pause(struct ngbe_hw *,
	    uint8_t *);
169void			ngbe_phy_get_lp_advertised_pause(struct ngbe_hw *,
	    uint8_t *);
171int			ngbe_phy_identify(struct ngbe_softc *);
172int			ngbe_phy_init(struct ngbe_softc *);
173void			ngbe_phy_led_ctrl(struct ngbe_softc *);
174int			ngbe_phy_led_oem_chk(struct ngbe_softc *, uint32_t *);
175int			ngbe_phy_read_reg(struct ngbe_hw *, uint32_t, uint32_t,
	    uint16_t *);
177int			ngbe_phy_write_reg(struct ngbe_hw *, uint32_t, uint32_t,
	    uint16_t);
179int			ngbe_phy_reset(struct ngbe_softc *);
180int			ngbe_phy_set_pause_advertisement(struct ngbe_hw *,
	    uint16_t);
182int			ngbe_phy_setup(struct ngbe_softc *);
183int			ngbe_phy_setup_link(struct ngbe_softc *, uint32_t, int);
184uint16_t		ngbe_read_pci_cfg_word(struct ngbe_softc *, uint32_t);
185void			ngbe_release_eeprom_semaphore(struct ngbe_hw *);
186int			ngbe_acquire_swfw_sync(struct ngbe_softc *, uint32_t);
187void			ngbe_release_swfw_sync(struct ngbe_softc *, uint32_t);
188void			ngbe_reset(struct ngbe_softc *);
189int			ngbe_reset_hw(struct ngbe_softc *);
190void			ngbe_reset_misc(struct ngbe_hw *);
191int			ngbe_set_fw_drv_ver(struct ngbe_softc *, uint8_t,
	    uint8_t, uint8_t, uint8_t);
193void			ngbe_set_ivar(struct ngbe_softc *, uint16_t, uint16_t,
	    int8_t);
195void			ngbe_set_lan_id_multi_port_pcie(struct ngbe_hw *);
196void			ngbe_set_mta(struct ngbe_hw *, uint8_t *);
197void			ngbe_set_pci_config_data(struct ngbe_hw *, uint16_t);
198int			ngbe_set_rar(struct ngbe_softc *, uint32_t, uint8_t *,
	    uint64_t, uint32_t);
200void			ngbe_set_rx_drop_en(struct ngbe_softc *);
201void			ngbe_set_rxpba(struct ngbe_hw *, int, uint32_t, int);
202int			ngbe_setup_copper_link(struct ngbe_softc *, uint32_t,
	    int);
204int			ngbe_setup_fc(struct ngbe_softc *);
205void			ngbe_setup_gpie(struct ngbe_hw *);
206void			ngbe_setup_isb(struct ngbe_softc *);
207void			ngbe_setup_psrtype(struct ngbe_hw *);
208void			ngbe_setup_vlan_hw_support(struct ngbe_softc *);
209int			ngbe_start_hw(struct ngbe_softc *);
210int			ngbe_stop_adapter(struct ngbe_softc *);
211void			ngbe_rx_checksum(uint32_t, struct mbuf *);
212void			ngbe_rxeof(struct rx_ring *);
213void			ngbe_rxrefill(void *);
214int			ngbe_tx_ctx_setup(struct tx_ring *, struct mbuf *,
	    uint32_t *, uint32_t *);
216void			ngbe_txeof(struct tx_ring *);
217void			ngbe_update_mc_addr_list(struct ngbe_hw *, uint8_t *,
	    uint32_t, ngbe_mc_addr_itr, int);
219int			ngbe_validate_mac_addr(uint8_t *);

221struct cfdriver ngbe_cd = {
NULL((void *)0), "ngbe", DV_IFNET
223};

225const struct cfattach ngbe_ca = {
sizeof(struct ngbe_softc), ngbe_match, ngbe_attach, ngbe_detach
227};

229int
230ngbe_match(struct device *parent, void *match, void *aux)
231{
return pci_matchbyid((struct pci_attach_args *)aux, ngbe_devices,
   nitems(ngbe_devices)(sizeof((ngbe_devices)) / sizeof((ngbe_devices)[0])));
234}

236void
237ngbe_attach(struct device *parent, struct device *self, void *aux)
238{
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
struct ngbe_softc *sc = (struct ngbe_softc *)self;
struct ngbe_hw *hw = &sc->hw;
uint32_t eeprom_cksum_devcap, devcap, led_conf;
int error;

sc->osdep.os_sc = sc;
sc->osdep.os_pa = *pa;

/* Setup PCI resources. */
if (ngbe_allocate_pci_resources(sc))
goto fail1;

sc->num_tx_desc = NGBE_DEFAULT_TXD512;
sc->num_rx_desc = NGBE_DEFAULT_RXD512;

/* Allocate Tx/Rx queues. */
if (ngbe_allocate_queues(sc))
goto fail1;

/* Allocate multicast array memory. */
sc->mta = mallocarray(ETHER_ADDR_LEN6, NGBE_SP_RAR_ENTRIES32, M_DEVBUF2,
   M_NOWAIT0x0002);
if (sc->mta == NULL((void *)0)) {
printf(": can not allocate multicast setup array\n");
goto fail1;
}

/* Allocate interrupt status resources. */
if (ngbe_allocate_isb(sc))
goto fail2;

hw->mac.autoneg = 1;
hw->phy.autoneg_advertised = NGBE_LINK_SPEED_AUTONEG(1 | 2 | 8);
hw->phy.force_speed = NGBE_LINK_SPEED_UNKNOWN0;

/* Initialize the shared code. */
ngbe_init_shared_code(sc);

sc->hw.mac.ops.set_lan_id(&sc->hw);

/* Check if flash load is done after hw power up. */
error = ngbe_check_flash_load(sc, NGBE_SPI_ILDR_STATUS_PERST0x00000001);
if (error)
goto fail3;
error = ngbe_check_flash_load(sc, NGBE_SPI_ILDR_STATUS_PWRRST0x00000002);
if (error)
goto fail3;

hw->phy.reset_if_overtemp = 1;
error = sc->hw.mac.ops.reset_hw(sc);
hw->phy.reset_if_overtemp = 0;
if (error) {
printf(": HW reset failed\n");
goto fail3;
}

eeprom_cksum_devcap = devcap = 0;
if (hw->bus.lan_id == 0) {
NGBE_WRITE_REG(hw, NGBE_CALSUM_CAP_STATUS, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10224
), (0)));
NGBE_WRITE_REG(hw, NGBE_EEPROM_VERSION_STORE_REG, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1022c
), (0)));
} else
eeprom_cksum_devcap = NGBE_READ_REG(hw, NGBE_CALSUM_CAP_STATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10224
)));

hw->eeprom.ops.init_params(hw);
hw->mac.ops.release_swfw_sync(sc, NGBE_MNG_SWFW_SYNC_SW_MB0x0004);
if (hw->bus.lan_id == 0 || eeprom_cksum_devcap == 0) {
/* Make sure the EEPROM is good */
if (hw->eeprom.ops.eeprom_chksum_cap_st(sc, NGBE_CALSUM_COMMAND0xe9,
    &devcap)) {
	printf(": eeprom checksum is not valid\n");
	goto fail3;
}
}

led_conf = 0;
if (hw->eeprom.ops.phy_led_oem_chk(sc, &led_conf))
sc->led_conf = -1;
else
sc->led_conf = led_conf;

memcpy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN)__builtin_memcpy((sc->sc_ac.ac_enaddr), (sc->hw.mac.addr
), (6));

error = ngbe_allocate_msix(sc);
if (error)
goto fail3;

ngbe_setup_interface(sc);

/* Reset the hardware with the new settings */
error = hw->mac.ops.start_hw(sc);
if (error) {
printf(": HW init failed\n");
goto fail3;
}

/* Pick up the PCI bus settings for reporting later */
hw->mac.ops.get_bus_info(sc);

hw->mac.ops.set_fw_drv_ver(sc, 0xff, 0xff, 0xff, 0xff);

printf(", address %s\n", ether_sprintf(sc->hw.mac.addr));
return;

343fail3:
ngbe_free_isb(sc);
345fail2:
ngbe_free_transmit_structures(sc);
ngbe_free_receive_structures(sc);
free(sc->mta, M_DEVBUF2, ETHER_ADDR_LEN6 * NGBE_SP_RAR_ENTRIES32);
349fail1:
ngbe_free_pci_resources(sc);
351}

353int
354ngbe_detach(struct device *self, int flags)
355{
struct ngbe_softc *sc = (struct ngbe_softc *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;

ngbe_stop(sc);
ngbe_release_hw_control(sc);

ether_ifdetach(ifp);
if_detach(ifp);

ngbe_free_pci_resources(sc);

ngbe_free_transmit_structures(sc);                                     
ngbe_free_receive_structures(sc); 
ngbe_free_isb(sc);
free(sc->mta, M_DEVBUF2, ETHER_ADDR_LEN6 * NGBE_SP_RAR_ENTRIES32);

return 0;
373}

375static inline uint32_t
376NGBE_READ_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask)
377{
uint32_t val;

val = NGBE_READ_REG(hw, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (reg)));
if (val == NGBE_FAILED_READ_REG0xffffffff)
return val;
return val & mask;
384}

386static inline void
387NGBE_WRITE_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask,
  uint32_t field)
389{
uint32_t val;

val = NGBE_READ_REG(hw, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (reg)));
if (val == NGBE_FAILED_READ_REG0xffffffff)
return;
val = ((val & ~mask) | (field & mask));
NGBE_WRITE_REG(hw, reg, val)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (reg), (
val)));
397}

399static inline uint32_t
400ngbe_misc_isb(struct ngbe_softc *sc, enum ngbe_isb_idx idx)
401{
return htole32(sc->isb_base[idx])((__uint32_t)(sc->isb_base[idx]));
403}

405void
406ngbe_init(void *arg)
407{
struct ngbe_softc *sc = (struct ngbe_softc *)arg;
struct ngbe_hw *hw = &sc->hw;
struct ifnet *ifp = &sc->sc_ac.ac_if;
int i, s;

s = splnet()splraise(0x4);

ngbe_stop(sc);

ngbe_setup_isb(sc);

/* Setup the receive address. */                                
hw->mac.ops.set_rar(sc, 0, hw->mac.addr, 0, NGBE_PSR_MAC_SWC_AD_H_AV0x80000000);

/* Get the latest mac address, user can use a LAA. */
bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN6);

hw->mac.ops.set_rar(sc, 0, hw->mac.addr, 0, 1);

ngbe_configure_pb(sc);

/* Program promiscuous mode and multicast filters. */
ngbe_iff(sc);

ngbe_setup_vlan_hw_support(sc);

/* Prepare transmit descriptors and buffers. */
if (ngbe_setup_transmit_structures(sc)) {
printf("%s: could not setup transmit structures\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
ngbe_stop(sc);
splx(s)spllower(s);
return;
}
if (ngbe_initialize_transmit_unit(sc)) {
ngbe_stop(sc);
splx(s)spllower(s);
return;
}

/* Prepare receive descriptors and buffers. */
if (ngbe_setup_receive_structures(sc)) {
printf("%s: could not setup receive structures\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
ngbe_stop(sc);
splx(s)spllower(s);
return;
}
if (ngbe_initialize_receive_unit(sc)) {
ngbe_stop(sc);
splx(s)spllower(s);
return;
}

ngbe_get_hw_control(hw);
ngbe_setup_gpie(hw);
ngbe_configure_ivars(sc);

if (ngbe_non_sfp_link_config(sc)) {
ngbe_stop(sc);
splx(s)spllower(s);
return;
}

/* Select GMII */
NGBE_WRITE_REG(hw, NGBE_MAC_TX_CFG,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x60000000)))
   (NGBE_READ_REG(hw, NGBE_MAC_TX_CFG) & ~NGBE_MAC_TX_CFG_SPEED_MASK) |((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x60000000)))
   NGBE_MAC_TX_CFG_SPEED_1G)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x60000000)));

/* Clear any pending interrupts, may auto mask */
NGBE_READ_REG(hw, NGBE_PX_IC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x00120
)));
NGBE_READ_REG(hw, NGBE_PX_MISC_IC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x00100
)));
ngbe_enable_intr(sc);

switch (hw->bus.lan_id) {
case 0:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN0_UP0x8, NGBE_MIS_PRB_CTL_LAN0_UP0x8);
break;
case 1:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN1_UP0x4, NGBE_MIS_PRB_CTL_LAN1_UP0x4);
break;
case 2:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN2_UP0x2, NGBE_MIS_PRB_CTL_LAN2_UP0x2);
break;
case 3:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN3_UP0x1, NGBE_MIS_PRB_CTL_LAN3_UP0x1);
break;
}

NGBE_WRITE_REG_MASK(hw, NGBE_CFG_PORT_CTL0x14400, NGBE_CFG_PORT_CTL_PFRSTD0x00004000,
   NGBE_CFG_PORT_CTL_PFRSTD0x00004000);

/* Now inform the stack we're ready */
ifp->if_flags |= IFF_RUNNING0x40;
for (i = 0; i < sc->sc_nqueues; i++)
ifq_clr_oactive(ifp->if_ifqs[i]);
splx(s)spllower(s);
509}

511int
512ngbe_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data)
513{
struct ngbe_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;

s = splnet()splraise(0x4);

switch (cmd) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	ngbe_init(sc);
break;
case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		ngbe_init(sc);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		ngbe_stop(sc);
}
break;
case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
break;
case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
error = ngbe_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data);
break;
default:
error = ether_ioctl(ifp, &sc->sc_ac, cmd, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40) {
	ngbe_disable_intr(sc);
	ngbe_iff(sc);
	ngbe_enable_intr(sc);
}
error = 0;
}

splx(s)spllower(s);
return error;
559}

561int
562ngbe_media_change(struct ifnet *ifp)
563{
struct ngbe_softc *sc = ifp->if_softc;
struct ngbe_hw *hw = &sc->hw;
struct ifmedia *ifm = &sc->sc_media;
uint32_t advertised = 0;

if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
return EINVAL22;

switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
case IFM_AUTO0ULL:
case IFM_1000_T16:
advertised |= NGBE_LINK_SPEED_AUTONEG(1 | 2 | 8);
break;
case IFM_100_TX6:
advertised |= NGBE_LINK_SPEED_100_FULL1;
break;
case IFM_10_T3:
advertised |= NGBE_LINK_SPEED_10_FULL8;
break;
default:
return EINVAL22;
}

hw->mac.autotry_restart = true1;
hw->mac.ops.setup_link(sc, advertised, 1);

return 0;
591}

593void
594ngbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
595{
struct ngbe_softc *sc = ifp->if_softc;

ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL;

ngbe_update_link_status(sc);

if (!LINK_STATE_IS_UP(ifp->if_link_state)((ifp->if_data.ifi_link_state) >= 4 || (ifp->if_data
.ifi_link_state) == 0))
return;

ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;

switch (sc->link_speed) {
case NGBE_LINK_SPEED_1GB_FULL2:
ifmr->ifm_active |= IFM_1000_T16 | IFM_FDX0x0000010000000000ULL;
break;
case NGBE_LINK_SPEED_100_FULL1:
ifmr->ifm_active |= IFM_100_TX6 | IFM_FDX0x0000010000000000ULL;
break;
case NGBE_LINK_SPEED_10_FULL8:
ifmr->ifm_active |= IFM_10_T3 | IFM_FDX0x0000010000000000ULL;
break;
}

switch (sc->hw.fc.current_mode) {
case ngbe_fc_tx_pause:
ifmr->ifm_active |= IFM_FLOW0x0000040000000000ULL | IFM_ETH_TXPAUSE0x0000000000040000ULL;
break;
case ngbe_fc_rx_pause:
ifmr->ifm_active |= IFM_FLOW0x0000040000000000ULL | IFM_ETH_RXPAUSE0x0000000000020000ULL;
break;
case ngbe_fc_full:
ifmr->ifm_active |= IFM_FLOW0x0000040000000000ULL | IFM_ETH_RXPAUSE0x0000000000020000ULL |
    IFM_ETH_TXPAUSE0x0000000000040000ULL;
break;
default:
ifmr->ifm_active &= ~(IFM_FLOW0x0000040000000000ULL | IFM_ETH_RXPAUSE0x0000000000020000ULL |
    IFM_ETH_TXPAUSE0x0000000000040000ULL);
break;
}
636}

638int
639ngbe_rxfill(struct rx_ring *rxr)
640{
struct ngbe_softc *sc = rxr->sc;
int i, post = 0;
u_int slots;

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x08)) 
   rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x08));

i = rxr->last_desc_filled;
for (slots = if_rxr_get(&rxr->rx_ring, sc->num_rx_desc); slots > 0;
   slots--) {
if (++i == sc->num_rx_desc)
	i = 0;

if (ngbe_get_buf(rxr, i) != 0)
	break;

rxr->last_desc_filled = i;
post = 1;
}

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x04))
   rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x04));

if_rxr_put(&rxr->rx_ring, slots)do { (&rxr->rx_ring)->rxr_alive -= (slots); } while
 (0);

return post;
667}

669int
670ngbe_rxrinfo(struct ngbe_softc *sc, struct if_rxrinfo *ifri)
671{
struct if_rxring_info *ifr;
struct rx_ring *rxr;
int error, i, n = 0;

if ((ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_DEVBUF2,
   M_WAITOK0x0001 | M_CANFAIL0x0004 | M_ZERO0x0008)) == NULL((void *)0))
return ENOMEM12;

for (i = 0; i < sc->sc_nqueues; i++) {
rxr = &sc->rx_rings[i];
ifr[n].ifr_size = MCLBYTES(1 << 11);
snprintf(ifr[n].ifr_name, sizeof(ifr[n].ifr_name), "%d", i);
ifr[n].ifr_info = rxr->rx_ring;
n++;
}

error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr);
free(ifr, M_DEVBUF2, sc->sc_nqueues * sizeof(*ifr));

return error;
692}

694void
695ngbe_start(struct ifqueue *ifq)
696{
struct ifnet *ifp = ifq->ifq_if;
struct ngbe_softc *sc = ifp->if_softc;
struct tx_ring *txr = ifq->ifq_softc_ifq_ptr._ifq_softc;
struct mbuf *m;
unsigned int prod, free, used;
int post = 0;

if (!sc->link_up)
1
Assuming field 'link_up' is not equal to 0→
2
←
Taking false branch→
return;

prod = txr->next_avail_desc;
free = txr->next_to_clean;
if (free <= prod)
3
←
Assuming 'free' is > 'prod'→
4
←
Taking false branch→
free += sc->num_tx_desc;
free -= prod;

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x08))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x08));

for (;;) {
5
←
Loop condition is true.  Entering loop body→
if (free <= NGBE_MAX_SCATTER32 + 2) {
6
←
Assuming the condition is false→
7
←
Taking false branch→
	ifq_set_oactive(ifq);
	break;
}

m = ifq_dequeue(ifq);
if (m == NULL((void *)0))
8
←
Assuming 'm' is not equal to NULL→
9
←
Taking false branch→
	break;

used = ngbe_encap(txr, m);
10
←
Calling 'ngbe_encap'→
if (used == 0) {
	m_freem(m);
	continue;
}

free -= used;

734#if NBPFILTER1 > 0
if (ifp->if_bpf)
	bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
737#endif

/* Set timeout in case hardware has problems transmitting */
txr->watchdog_timer = NGBE_TX_TIMEOUT5;
ifp->if_timer = NGBE_TX_TIMEOUT5;

post = 1;
}

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x04))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x04));

if (post)
NGBE_WRITE_REG(&sc->hw, NGBE_PX_TR_WP(txr->me),((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x03008 + ((txr->me) * 0x40))), (txr->
next_avail_desc)))
    txr->next_avail_desc)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x03008 + ((txr->me) * 0x40))), (txr->
next_avail_desc)));
752}

754void
755ngbe_stop(struct ngbe_softc *sc)
756{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct ngbe_hw *hw = &sc->hw;
uint32_t rxdctl;
int i, wait_loop = NGBE_MAX_RX_DESC_POLL10;

/* Tell the stack that the interface is no longer active. */
ifp->if_flags &= ~IFF_RUNNING0x40;
ifp->if_timer = 0;

ngbe_disable_pcie_master(sc);
/* Disable receives */
hw->mac.ops.disable_rx(hw);

for (i = 0; i < sc->sc_nqueues; i++) {
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    NGBE_PX_RR_CFG_RR_EN0x00000001, 0);
do {
	DELAY(10)(*delay_func)(10);
	rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40)))));
} while (--wait_loop && (rxdctl & NGBE_PX_RR_CFG_RR_EN0x00000001));
if (!wait_loop) {
	printf("%s: Rx queue %d not cleared within "
	    "the polling period\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	return;
}
}

ngbe_disable_intr(sc);

switch (hw->bus.lan_id) {
case 0:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN0_UP0x8, 0);
break;
case 1:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN1_UP0x4, 0);
break;
case 2:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN2_UP0x2, 0);
break;
case 3:
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_PRB_CTL0x10010,
    NGBE_MIS_PRB_CTL_LAN3_UP0x1, 0);
break;
}

NGBE_WRITE_REG_MASK(hw, NGBE_MAC_TX_CFG0x11000, NGBE_MAC_TX_CFG_TE0x00000001, 0);
for (i = 0; i < sc->sc_nqueues; i++)
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), NGBE_PX_TR_CFG_SWFLSH)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03010
 + ((i) * 0x40))), (0x04000000)));
NGBE_WRITE_REG_MASK(hw, NGBE_TDM_CTL0x18000, NGBE_TDM_CTL_TE0x1, 0);

ngbe_reset(sc);

hw->mac.ops.set_rar(sc, 0, hw->mac.addr, 0, NGBE_PSR_MAC_SWC_AD_H_AV0x80000000);

intr_barrier(sc->tag);
for (i = 0; i < sc->sc_nqueues; i++) {
struct ifqueue *ifq = ifp->if_ifqs[i];
ifq_barrier(ifq);
ifq_clr_oactive(ifq);

if (sc->queues[i].tag != NULL((void *)0))
	intr_barrier(sc->queues[i].tag);
timeout_del(&sc->rx_rings[i].rx_refill);
}

ngbe_free_transmit_structures(sc);
ngbe_free_receive_structures(sc);

ngbe_update_link_status(sc);
829}

831void
832ngbe_update_link_status(struct ngbe_softc *sc)
833{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct ngbe_hw *hw = &sc->hw;
uint32_t reg, speed = 0;
int link_state = LINK_STATE_DOWN2;

hw->mac.ops.check_link(hw, &sc->link_speed, &sc->link_up, 0);

ifp->if_baudrateif_data.ifi_baudrate = 0;
if (sc->link_up) {
link_state = LINK_STATE_FULL_DUPLEX6;

switch (sc->link_speed) {
case NGBE_LINK_SPEED_UNKNOWN0:
	ifp->if_baudrateif_data.ifi_baudrate = 0;
	break;
case NGBE_LINK_SPEED_1GB_FULL2:
	ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL)));
	speed = 2;
	break;
case NGBE_LINK_SPEED_100_FULL1:
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(100)((((100) * 1000ULL) * 1000ULL));
	speed = 1;
	break;
case NGBE_LINK_SPEED_10_FULL8:
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(10)((((10) * 1000ULL) * 1000ULL));
	break;
}
NGBE_WRITE_REG_MASK(hw, NGBE_CFG_LAN_SPEED0x14440, 0x3, speed);

/* Update any flow control changes */
hw->mac.ops.fc_enable(sc);

ngbe_set_rx_drop_en(sc);

if (sc->link_speed & (NGBE_LINK_SPEED_1GB_FULL2 |
    NGBE_LINK_SPEED_100_FULL1 | NGBE_LINK_SPEED_10_FULL8)) {
	NGBE_WRITE_REG(hw, NGBE_MAC_TX_CFG,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x00000001 | 0x60000000)))
	    (NGBE_READ_REG(hw, NGBE_MAC_TX_CFG) &((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x00000001 | 0x60000000)))
	    ~NGBE_MAC_TX_CFG_SPEED_MASK) | NGBE_MAC_TX_CFG_TE |((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x00000001 | 0x60000000)))
	    NGBE_MAC_TX_CFG_SPEED_1G)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
), ((((((struct ngbe_osdep *)(hw)->back)->os_memt)->
read_4((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11000
))) & ~0x60000000) | 0x00000001 | 0x60000000)));
}

reg = NGBE_READ_REG(hw, NGBE_MAC_RX_CFG)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11004
)));
NGBE_WRITE_REG(hw, NGBE_MAC_RX_CFG, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11004
), (reg)));
NGBE_WRITE_REG(hw, NGBE_MAC_PKT_FLT, NGBE_MAC_PKT_FLT_PR)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11008
), (0x00000001)));
reg = NGBE_READ_REG(hw, NGBE_MAC_WDG_TIMEOUT)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1100c
)));
NGBE_WRITE_REG(hw, NGBE_MAC_WDG_TIMEOUT, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1100c
), (reg)));
}

if (ifp->if_link_stateif_data.ifi_link_state != link_state) {
ifp->if_link_stateif_data.ifi_link_state = link_state;
if_link_state_change(ifp);
}
887}

889void
890ngbe_watchdog(struct ifnet *ifp)
891{
struct ngbe_softc *sc = ifp->if_softc;
struct tx_ring *txr = sc->tx_rings;
int i, tx_hang = 0;

/*
* The timer is set to 5 every time ixgbe_start() queues a packet.
* Anytime all descriptors are clean the timer is set to 0.
*/
for (i = 0; i < sc->sc_nqueues; i++, txr++) {
if (txr->watchdog_timer == 0 || --txr->watchdog_timer)
	continue;
else {
	tx_hang = 1;
	break;
}
}
if (!tx_hang)
return;

printf("%s: watchdog timeout\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
ifp->if_oerrorsif_data.ifi_oerrors++;

ifp->if_flags &= ~IFF_RUNNING0x40;
ngbe_init(sc);
916}

918int
919ngbe_allocate_pci_resources(struct ngbe_softc *sc)
920{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
pcireg_t memtype;

memtype = PCI_MAPREG_TYPE_MEM0x00000000 | PCI_MAPREG_MEM_TYPE_64BIT0x00000004;
if (pci_mapreg_map(pa, NGBE_PCIREG0x10, memtype, 0, &os->os_memt,
   &os->os_memh, &os->os_membase, &os->os_memsize, 0)) {
printf(": unable to map registers\n");
return ENXIO6;
}
sc->hw.back = os;

if (ngbe_setup_msix(sc))
return EINVAL22;

return 0;
937}

939void
940ngbe_free_pci_resources(struct ngbe_softc *sc)
941{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;

if (sc->tag)
pci_intr_disestablish(pa->pa_pc, sc->tag);
sc->tag = NULL((void *)0);
if (os->os_membase)
bus_space_unmap(os->os_memt, os->os_memh, os->os_memsize);
os->os_membase = 0;
951}

953int
954ngbe_allocate_msix(struct ngbe_softc *sc)
955{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
struct ngbe_queue *nq;
pci_intr_handle_t ih;
int i, error = 0;

for (i = 0, nq = sc->queues; i < sc->sc_nqueues; i++, nq++) {
if (pci_intr_map_msix(pa, i, &ih)) {
	printf(": unable to map msi-x vector %d", i);
	error = ENXIO6;
	goto fail;
}

nq->tag = pci_intr_establish_cpu(pa->pa_pc, ih,
    IPL_NET0x4 | IPL_MPSAFE0x100, intrmap_cpu(sc->sc_intrmap, i),
    ngbe_intr_queue, nq, nq->name);
if (nq->tag == NULL((void *)0)) {
	printf(": unable to establish interrupt %d\n", i);
	error = ENXIO6;
	goto fail;
}

nq->msix = i;
}

/* Now the link status/control last MSI-X vector */
if (pci_intr_map_msix(pa, i, &ih)) {
printf(": unable to map link vector\n");
error = ENXIO6;
goto fail;
}

sc->tag = pci_intr_establish(pa->pa_pc, ih, IPL_NET0x4 | IPL_MPSAFE0x100,
ngbe_intr_link, sc, sc->sc_dev.dv_xname);
if (sc->tag == NULL((void *)0)) {
printf(": unable to establish link interrupt\n");
error = ENXIO6;
goto fail;
}

sc->linkvec = i;
printf(", %s, %d queue%s", pci_intr_string(pa->pa_pc, ih), i,
   (i > 1) ? "s" : "");

return 0;
1001fail:
for (nq = sc->queues; i > 0; i--, nq++) {
if (nq->tag == NULL((void *)0))
	continue;
pci_intr_disestablish(pa->pa_pc, nq->tag);
nq->tag = NULL((void *)0);
}

return error;
1010}

1012void
1013ngbe_setup_interface(struct ngbe_softc *sc)
1014{
struct ifnet *ifp = &sc->sc_ac.ac_if;
int i;

strlcpy(ifp->if_xname, DEVNAME(sc)((sc)->sc_dev.dv_xname), IFNAMSIZ16);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_xflags = IFXF_MPSAFE0x1;
ifp->if_ioctl = ngbe_ioctl;
ifp->if_qstart = ngbe_start;
ifp->if_watchdog = ngbe_watchdog;
ifp->if_hardmtu = NGBE_MAX_JUMBO_FRAME_SIZE9432 - ETHER_HDR_LEN((6 * 2) + 2) - 
   ETHER_CRC_LEN4;
ifq_init_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010;

1031#if NVLAN1 > 0
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1033#endif

/* Initialize ifmedia structures. */
ifmedia_init(&sc->sc_media, IFM_IMASK0xff00000000000000ULL, ngbe_media_change,
   ngbe_media_status);
ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));

ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
ifmedia_set(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media;

if_attach(ifp);
ether_ifattach(ifp);

if_attach_queues(ifp, sc->sc_nqueues);
if_attach_iqueues(ifp, sc->sc_nqueues);
for (i = 0; i < sc->sc_nqueues; i++) {
struct ifqueue *ifq = ifp->if_ifqs[i];
struct ifiqueue *ifiq = ifp->if_iqs[i];
struct tx_ring *txr = &sc->tx_rings[i];
struct rx_ring *rxr = &sc->rx_rings[i];

ifq->ifq_softc_ifq_ptr._ifq_softc = txr;
txr->ifq = ifq;

ifiq->ifiq_softc_ifiq_ptr._ifiq_softc = rxr;
rxr->ifiq = ifiq;
}
1063}

1065int
1066ngbe_setup_msix(struct ngbe_softc *sc)
1067{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
int nmsix;

nmsix = pci_intr_msix_count(pa);
if (nmsix <= 1) {
printf(": not enough msi-x vectors\n");
return EINVAL22;
}

/* Give one vector to events. */
nmsix--;

sc->sc_intrmap = intrmap_create(&sc->sc_dev, nmsix, NGBE_MAX_VECTORS8,
   INTRMAP_POWEROF2(1 << 0));
sc->sc_nqueues = intrmap_count(sc->sc_intrmap);

return 0;
1086}

1088int
1089ngbe_dma_malloc(struct ngbe_softc *sc, bus_size_t size,
  struct ngbe_dma_alloc *dma)
1091{
struct ngbe_osdep *os = &sc->osdep;

dma->dma_tag = os->os_pa.pa_dmat;

if (bus_dmamap_create(dma->dma_tag, size, 1, size, 0, BUS_DMA_NOWAIT,(*(dma->dma_tag)->_dmamap_create)((dma->dma_tag), (size
), (1), (size), (0), (0x0001), (&dma->dma_map))
   &dma->dma_map)(*(dma->dma_tag)->_dmamap_create)((dma->dma_tag), (size
), (1), (size), (0), (0x0001), (&dma->dma_map)))
return 1;
if (bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg,(*(dma->dma_tag)->_dmamem_alloc)((dma->dma_tag), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0001))
   1, &dma->dma_nseg, BUS_DMA_NOWAIT)(*(dma->dma_tag)->_dmamem_alloc)((dma->dma_tag), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0001)))
goto destroy;
if (bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size,(*(dma->dma_tag)->_dmamem_map)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0001 | 0x0004))
   &dma->dma_vaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)(*(dma->dma_tag)->_dmamem_map)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0001 | 0x0004)))
goto free;
if (bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,(*(dma->dma_tag)->_dmamap_load)((dma->dma_tag), (dma
->dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0001
))
   NULL, BUS_DMA_NOWAIT)(*(dma->dma_tag)->_dmamap_load)((dma->dma_tag), (dma
->dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0001
)))
goto unmap;

dma->dma_size = size;

return 0;
1112unmap:
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size)(*(dma->dma_tag)->_dmamem_unmap)((dma->dma_tag), (dma
->dma_vaddr), (size));
1114free:
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg)(*(dma->dma_tag)->_dmamem_free)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg));
1116destroy:
bus_dmamap_destroy(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_destroy)((dma->dma_tag), (
dma->dma_map));
dma->dma_map = NULL((void *)0);
dma->dma_tag = NULL((void *)0);
return 1;
1121}

1123void
1124ngbe_dma_free(struct ngbe_softc *sc, struct ngbe_dma_alloc *dma)
1125{
if (dma->dma_tag == NULL((void *)0))
return;

if (dma->dma_map != NULL((void *)0)) {
bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0,(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08))
    dma->dma_map->dm_mapsize,(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08));
bus_dmamap_unload(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_unload)((dma->dma_tag), (dma
->dma_map));
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size)(*(dma->dma_tag)->_dmamem_unmap)((dma->dma_tag), (dma
->dma_vaddr), (dma->dma_size));
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg)(*(dma->dma_tag)->_dmamem_free)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg));
bus_dmamap_destroy(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_destroy)((dma->dma_tag), (
dma->dma_map));
dma->dma_map = NULL((void *)0);
}
1139}

1141int
1142ngbe_allocate_isb(struct ngbe_softc *sc)
1143{
int isize;

isize = sizeof(uint32_t) * NGBE_ISB_MAX;
if (ngbe_dma_malloc(sc, isize, &sc->isbdma)) {
printf("%s: unable to allocate interrupt status resources\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ENOMEM12;
}
sc->isb_base = (uint32_t *)sc->isbdma.dma_vaddr;
bzero((void *)sc->isb_base, isize)__builtin_bzero(((void *)sc->isb_base), (isize));

return 0;
1156}

1158void
1159ngbe_free_isb(struct ngbe_softc *sc)
1160{
ngbe_dma_free(sc, &sc->isbdma);
1162}

1164int
1165ngbe_allocate_queues(struct ngbe_softc *sc)
1166{
struct ngbe_queue *nq;
struct tx_ring *txr;
struct rx_ring *rxr;
int i, rsize, rxconf, tsize, txconf;

/* Allocate the top level queue structs. */
sc->queues = mallocarray(sc->sc_nqueues, sizeof(struct ngbe_queue),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->queues == NULL((void *)0)) {
printf("%s: unable to allocate queue\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

/* Allocate the Tx ring. */
sc->tx_rings = mallocarray(sc->sc_nqueues, sizeof(struct tx_ring),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->tx_rings == NULL((void *)0)) {
printf("%s: unable to allocate Tx ring\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

/* Allocate the Rx ring. */
sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->rx_rings == NULL((void *)0)) {
printf("%s: unable to allocate Rx ring\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto rx_fail;
}

txconf = rxconf = 0;

/* Set up the Tx queues. */
tsize = roundup2(sc->num_tx_desc * sizeof(union ngbe_tx_desc),(((sc->num_tx_desc * sizeof(union ngbe_tx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1))
   PAGE_SIZE)(((sc->num_tx_desc * sizeof(union ngbe_tx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1));
for (i = 0; i < sc->sc_nqueues; i++, txconf++) {
txr = &sc->tx_rings[i];
txr->sc = sc;
txr->me = i;

if (ngbe_dma_malloc(sc, tsize, &txr->txdma)) {
	printf("%s: unable to allocate Tx descriptor\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto err_tx_desc;
}
txr->tx_base = (union ngbe_tx_desc *)txr->txdma.dma_vaddr;
bzero((void *)txr->tx_base, tsize)__builtin_bzero(((void *)txr->tx_base), (tsize));
}

/* Set up the Rx queues. */
rsize = roundup2(sc->num_rx_desc * sizeof(union ngbe_rx_desc),(((sc->num_rx_desc * sizeof(union ngbe_rx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1))
   PAGE_SIZE)(((sc->num_rx_desc * sizeof(union ngbe_rx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1));
for (i = 0; i < sc->sc_nqueues; i++, rxconf++) {
rxr = &sc->rx_rings[i];
rxr->sc = sc;
rxr->me = i;
timeout_set(&rxr->rx_refill, ngbe_rxrefill, rxr);

if (ngbe_dma_malloc(sc, rsize, &rxr->rxdma)) {
	printf("%s: unable to allocate Rx descriptor\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto err_rx_desc;
}
rxr->rx_base = (union ngbe_rx_desc *)rxr->rxdma.dma_vaddr;
bzero((void *)rxr->rx_base, rsize)__builtin_bzero(((void *)rxr->rx_base), (rsize));
}

/* Set up the queue holding structs. */
for (i = 0; i < sc->sc_nqueues; i++) {
nq = &sc->queues[i];
nq->sc = sc;
nq->txr = &sc->tx_rings[i];
nq->rxr = &sc->rx_rings[i];
snprintf(nq->name, sizeof(nq->name), "%s:%d", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
}

return 0;

1244err_rx_desc:
for (rxr = sc->rx_rings; rxconf > 0; rxr++, rxconf--)
ngbe_dma_free(sc, &rxr->rxdma);
1247err_tx_desc:
for (txr = sc->tx_rings; txconf > 0; txr++, txconf--)
ngbe_dma_free(sc, &txr->txdma);
free(sc->rx_rings, M_DEVBUF2, sc->sc_nqueues * sizeof(struct rx_ring));
sc->rx_rings = NULL((void *)0);
1252rx_fail:
free(sc->tx_rings, M_DEVBUF2, sc->sc_nqueues * sizeof(struct tx_ring));
sc->tx_rings = NULL((void *)0);
1255fail:
return ENOMEM12;
1257}

1259void
1260ngbe_free_receive_structures(struct ngbe_softc *sc)
1261{
struct rx_ring *rxr;
int i;

for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++)
if_rxr_init(&rxr->rx_ring, 0, 0);

for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++)
ngbe_free_receive_buffers(rxr);
1270}

1272void
1273ngbe_free_receive_buffers(struct rx_ring *rxr)
1274{
struct ngbe_softc *sc;
struct ngbe_rx_buf *rxbuf;
int i;

sc = rxr->sc;
if (rxr->rx_buffers != NULL((void *)0)) {
for (i = 0; i < sc->num_rx_desc; i++) {
	rxbuf = &rxr->rx_buffers[i];
	if (rxbuf->buf != NULL((void *)0)) {
		bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
		    0, rxbuf->map->dm_mapsize,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
		    BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
));
		bus_dmamap_unload(rxr->rxdma.dma_tag,(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map))
		    rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map));
		m_freem(rxbuf->buf);
		rxbuf->buf = NULL((void *)0);
	}
	bus_dmamap_destroy(rxr->rxdma.dma_tag, rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_destroy)((rxr->rxdma
.dma_tag), (rxbuf->map));
	rxbuf->map = NULL((void *)0);
}
free(rxr->rx_buffers, M_DEVBUF2,
    sc->num_rx_desc * sizeof(struct ngbe_rx_buf));
rxr->rx_buffers = NULL((void *)0);
}
1299}

1301void
1302ngbe_free_transmit_structures(struct ngbe_softc *sc)
1303{
struct tx_ring *txr = sc->tx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, txr++)
ngbe_free_transmit_buffers(txr);
1309}

1311void
1312ngbe_free_transmit_buffers(struct tx_ring *txr)
1313{
struct ngbe_softc *sc = txr->sc;
struct ngbe_tx_buf *tx_buffer;
int i;

if (txr->tx_buffers == NULL((void *)0))
return;

tx_buffer = txr->tx_buffers;
for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) {
if (tx_buffer->map != NULL((void *)0) && tx_buffer->map->dm_nsegs > 0) {
	bus_dmamap_sync(txr->txdma.dma_tag, tx_buffer->map,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (tx_buffer->map), (0), (tx_buffer->map->dm_mapsize
), (0x08))
	    0, tx_buffer->map->dm_mapsize,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (tx_buffer->map), (0), (tx_buffer->map->dm_mapsize
), (0x08))
	    BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (tx_buffer->map), (0), (tx_buffer->map->dm_mapsize
), (0x08));
	bus_dmamap_unload(txr->txdma.dma_tag, tx_buffer->map)(*(txr->txdma.dma_tag)->_dmamap_unload)((txr->txdma.
dma_tag), (tx_buffer->map));
}
if (tx_buffer->m_head != NULL((void *)0)) {
	m_freem(tx_buffer->m_head);
	tx_buffer->m_head = NULL((void *)0);
}
if (tx_buffer->map != NULL((void *)0)) {
	bus_dmamap_destroy(txr->txdma.dma_tag, tx_buffer->map)(*(txr->txdma.dma_tag)->_dmamap_destroy)((txr->txdma
.dma_tag), (tx_buffer->map));
	tx_buffer->map = NULL((void *)0);
}
}

if (txr->tx_buffers != NULL((void *)0))
free(txr->tx_buffers, M_DEVBUF2,
    sc->num_tx_desc * sizeof(struct ngbe_tx_buf));
txr->tx_buffers = NULL((void *)0);
txr->txtag = NULL((void *)0);
1344}

1346int
1347ngbe_allocate_receive_buffers(struct rx_ring *rxr)
1348{
struct ngbe_softc *sc = rxr->sc;
struct ngbe_rx_buf *rxbuf;
int i, error;

rxr->rx_buffers = mallocarray(sc->num_rx_desc,
   sizeof(struct ngbe_rx_buf), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (rxr->rx_buffers == NULL((void *)0)) {
printf("%s: unable to allocate rx_buffer memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}

rxbuf = rxr->rx_buffers;
for (i = 0; i < sc->num_rx_desc; i++, rxbuf++) {
error = bus_dmamap_create(rxr->rxdma.dma_tag,(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9432), (1), (9432), (0), (0x0001), (&rxbuf->
map))
    NGBE_MAX_JUMBO_FRAME_SIZE, 1, NGBE_MAX_JUMBO_FRAME_SIZE, 0,(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9432), (1), (9432), (0), (0x0001), (&rxbuf->
map))
    BUS_DMA_NOWAIT, &rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9432), (1), (9432), (0), (0x0001), (&rxbuf->
map));
if (error) {
	printf("%s: unable to create RX DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}
}
bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   rxr->rxdma.dma_map->dm_mapsize,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04));

return 0;
1378fail:
return error;
1380}

1382int
1383ngbe_allocate_transmit_buffers(struct tx_ring *txr)
1384{
struct ngbe_softc *sc = txr->sc;
struct ngbe_tx_buf *txbuf;
int error, i;

txr->tx_buffers = mallocarray(sc->num_tx_desc,
   sizeof(struct ngbe_tx_buf), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (txr->tx_buffers == NULL((void *)0)) {
printf("%s: unable to allocate tx_buffer memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}
txr->txtag = txr->txdma.dma_tag;

/* Create the descriptor buffer dma maps. */
for (i = 0; i < sc->num_tx_desc; i++) {
txbuf = &txr->tx_buffers[i];
error = bus_dmamap_create(txr->txdma.dma_tag, NGBE_TSO_SIZE,(*(txr->txdma.dma_tag)->_dmamap_create)((txr->txdma.
dma_tag), (32767), (32), ((1 << 12)), (0), (0x0001), (&
txbuf->map))
    NGBE_MAX_SCATTER, PAGE_SIZE, 0, BUS_DMA_NOWAIT,(*(txr->txdma.dma_tag)->_dmamap_create)((txr->txdma.
dma_tag), (32767), (32), ((1 << 12)), (0), (0x0001), (&
txbuf->map))
    &txbuf->map)(*(txr->txdma.dma_tag)->_dmamap_create)((txr->txdma.
dma_tag), (32767), (32), ((1 << 12)), (0), (0x0001), (&
txbuf->map));
if (error != 0) {
	printf("%s: unable to create TX DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}
}

return 0;
1413fail:
return error;
1415}

1417int
1418ngbe_setup_receive_ring(struct rx_ring *rxr)
1419{
struct ngbe_softc *sc = rxr->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
int rsize;

rsize = roundup2(sc->num_rx_desc * sizeof(union ngbe_rx_desc),(((sc->num_rx_desc * sizeof(union ngbe_rx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1))
   PAGE_SIZE)(((sc->num_rx_desc * sizeof(union ngbe_rx_desc)) + ((1 <<
 12)) - 1) & ~(((1 << 12)) - 1));

/* Clear the ring contents. */
bzero((void *)rxr->rx_base, rsize)__builtin_bzero(((void *)rxr->rx_base), (rsize));

if (ngbe_allocate_receive_buffers(rxr))
return ENOMEM12;

/* Setup our descriptor indices. */
rxr->next_to_check = 0;
rxr->last_desc_filled = sc->num_rx_desc - 1;

if_rxr_init(&rxr->rx_ring, 2 * ((ifp->if_hardmtu / MCLBYTES(1 << 11)) + 1),
   sc->num_rx_desc - 1);

ngbe_rxfill(rxr);
if (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) == 0) {
printf("%s: unable to fill any rx descriptors\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ENOBUFS55;
}

return 0;
1447}

1449int
1450ngbe_setup_transmit_ring(struct tx_ring *txr)
1451{
struct ngbe_softc *sc = txr->sc;

/* Now allocate transmit buffers for the ring. */
if (ngbe_allocate_transmit_buffers(txr))
return ENOMEM12;

/* Clear the old ring contents */
bzero((void *)txr->tx_base,__builtin_bzero(((void *)txr->tx_base), ((sizeof(union ngbe_tx_desc
)) * sc->num_tx_desc))
   (sizeof(union ngbe_tx_desc)) * sc->num_tx_desc)__builtin_bzero(((void *)txr->tx_base), ((sizeof(union ngbe_tx_desc
)) * sc->num_tx_desc));

/* Reset indices. */
txr->next_avail_desc = 0;
txr->next_to_clean = 0;

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   txr->txdma.dma_map->dm_mapsize,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04));

return 0;
1471}

1473int
1474ngbe_setup_receive_structures(struct ngbe_softc *sc)
1475{
struct rx_ring *rxr = sc->rx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, rxr++) {
if (ngbe_setup_receive_ring(rxr))
	goto fail;
}

return 0;
1485fail:
ngbe_free_receive_structures(sc);
return ENOBUFS55;
1488}

1490int
1491ngbe_setup_transmit_structures(struct ngbe_softc *sc)
1492{
struct tx_ring *txr = sc->tx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, txr++) {
if (ngbe_setup_transmit_ring(txr))
	goto fail;
}

return 0;
1502fail:
ngbe_free_transmit_structures(sc);
return ENOBUFS55;
1505}

1507uint8_t *
1508ngbe_addr_list_itr(struct ngbe_hw *hw, uint8_t **mc_addr_ptr, uint32_t *vmdq)
1509{
uint8_t *addr = *mc_addr_ptr;
uint8_t *newptr;
*vmdq = 0;

newptr = addr + ETHER_ADDR_LEN6;
*mc_addr_ptr = newptr;
return addr;
1517}

1519void 
1520ngbe_iff(struct ngbe_softc *sc)
1521{
struct ngbe_hw *hw = &sc->hw;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct arpcom *ac = &sc->sc_ac;
struct ether_multi *enm;
struct ether_multistep step;
uint32_t fctrl, vlanctrl;
uint8_t *mta, *update_ptr;
int mcnt = 0;

mta = sc->mta;
bzero(mta, sizeof(uint8_t) * ETHER_ADDR_LEN * NGBE_SP_RAR_ENTRIES)__builtin_bzero((mta), (sizeof(uint8_t) * 6 * 32));

fctrl = NGBE_READ_REG_MASK(hw, NGBE_PSR_CTL0x15000,
   ~(NGBE_PSR_CTL_UPE0x00000200 | NGBE_PSR_CTL_MPE0x00000100));
vlanctrl = NGBE_READ_REG_MASK(hw, NGBE_PSR_VLAN_CTL0x15088,
   ~(NGBE_PSR_VLAN_CTL_VFE0x40000000 | NGBE_PSR_VLAN_CTL_CFIEN0x20000000));
ifp->if_flags &= ~IFF_ALLMULTI0x200;

/* Set all bits that we expect to always be set */
fctrl |= NGBE_PSR_CTL_BAM0x00000400 | NGBE_PSR_CTL_MFE0x00000080;
vlanctrl |= NGBE_PSR_VLAN_CTL_VFE0x40000000;

hw->addr_ctrl.user_set_promisc = 0;
if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0 ||
   ac->ac_multicnt > NGBE_SP_RAR_ENTRIES32) {
ifp->if_flags |= IFF_ALLMULTI0x200;
fctrl |= NGBE_PSR_CTL_MPE0x00000100;
if (ifp->if_flags & IFF_PROMISC0x100) {
	fctrl |= NGBE_PSR_CTL_UPE0x00000200;
	vlanctrl &= ~NGBE_PSR_VLAN_CTL_VFE0x40000000;
}
} else {
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	bcopy(enm->enm_addrlo, &mta[mcnt * ETHER_ADDR_LEN6],
	    ETHER_ADDR_LEN6);
	mcnt++;

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}

update_ptr = mta;
hw->mac.ops.update_mc_addr_list(hw, update_ptr, mcnt,
    ngbe_addr_list_itr, 1);
}

NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_CTL, vlanctrl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15088
), (vlanctrl)));
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, fctrl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
), (fctrl)));
1570}

1572int
1573ngbe_initialize_receive_unit(struct ngbe_softc *sc)
1574{
struct ngbe_hw *hw = &sc->hw;
struct rx_ring *rxr = sc->rx_rings;
uint32_t bufsz, mhadd, rxctrl, rxdctl, srrctl;
int i, wait_loop = NGBE_MAX_RX_DESC_POLL10;
int error = 0;

/* Disable receives while setting up the descriptors */
hw->mac.ops.disable_rx(hw);

ngbe_setup_psrtype(hw);

/* Enable hw crc stripping */
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL0x17000, NGBE_RSEC_CTL_CRC_STRIP0x00000004,
   NGBE_RSEC_CTL_CRC_STRIP0x00000004);

if (sc->sc_nqueues > 1) {
NGBE_WRITE_REG_MASK(hw, NGBE_PSR_CTL0x15000, NGBE_PSR_CTL_PCSD0x00002000,
    NGBE_PSR_CTL_PCSD0x00002000);
ngbe_initialize_rss_mapping(sc);
}

mhadd = NGBE_READ_REG(hw, NGBE_PSR_MAX_SZ)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15020
)));
if (mhadd != NGBE_MAX_JUMBO_FRAME_SIZE9432)
NGBE_WRITE_REG(hw, NGBE_PSR_MAX_SZ, NGBE_MAX_JUMBO_FRAME_SIZE)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15020
), (9432)));

bufsz = MCLBYTES(1 << 11) >> NGBE_PX_RR_CFG_BSIZEPKT_SHIFT2;

for (i = 0; i < sc->sc_nqueues; i++, rxr++) {
uint64_t rdba = rxr->rxdma.dma_map->dm_segs[0].ds_addr;

/* Disable queue to avoid issues while updating state */
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    NGBE_PX_RR_CFG_RR_EN0x00000001, 0);

/* Hardware may take up to 100us to actually disable Rx queue */
do {
	DELAY(10)(*delay_func)(10);
	rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40)))));
} while (--wait_loop && (rxdctl & NGBE_PX_RR_CFG_RR_EN0x00000001));
if (!wait_loop) {
	printf("%s: Rx queue %d not cleared within "
	    "the polling period\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	error = ETIMEDOUT60;
	goto out;
}

NGBE_WRITE_REG(hw, NGBE_PX_RR_BAL(i),((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01000
 + ((i) * 0x40))), ((rdba & 0x00000000ffffffffULL))))
    (rdba & 0x00000000ffffffffULL))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01000
 + ((i) * 0x40))), ((rdba & 0x00000000ffffffffULL))));
NGBE_WRITE_REG(hw, NGBE_PX_RR_BAH(i), (rdba >> 32))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01004
 + ((i) * 0x40))), ((rdba >> 32))));

rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40)))));
rxdctl |=
    (sc->num_rx_desc / 128) << NGBE_PX_RR_CFG_RR_SIZE_SHIFT1;
rxdctl |= 0x1 << NGBE_PX_RR_CFG_RR_THER_SHIFT16;
NGBE_WRITE_REG(hw, NGBE_PX_RR_CFG(i), rxdctl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40))), (rxdctl)));

/* Reset head and tail pointers */
NGBE_WRITE_REG(hw, NGBE_PX_RR_RP(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x0100c
 + ((i) * 0x40))), (0)));
NGBE_WRITE_REG(hw, NGBE_PX_RR_WP(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01008
 + ((i) * 0x40))), (0)));

/* Set up the SRRCTL register */
srrctl = NGBE_READ_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    ~(NGBE_PX_RR_CFG_RR_HDR_SZ0x0000f000 | NGBE_PX_RR_CFG_RR_BUF_SZ0x00000f00 |
    NGBE_PX_RR_CFG_SPLIT_MODE0x04000000));
srrctl |= bufsz;
NGBE_WRITE_REG(hw, NGBE_PX_RR_CFG(i), srrctl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40))), (srrctl)));

/* Enable receive descriptor ring */
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    NGBE_PX_RR_CFG_RR_EN0x00000001, NGBE_PX_RR_CFG_RR_EN0x00000001);

do {
	msec_delay(1)(*delay_func)(1000 * (1));
	rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01010
 + ((i) * 0x40)))));
} while (--wait_loop && !(rxdctl & NGBE_PX_RR_CFG_RR_EN0x00000001));
if (!wait_loop) {
	printf("%s: Rx queue %d not set within "
	    "the polling period\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	error = ETIMEDOUT60;
	goto out;
}
NGBE_WRITE_REG(hw, NGBE_PX_RR_WP(i), rxr->last_desc_filled)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x01008
 + ((i) * 0x40))), (rxr->last_desc_filled)));
}

/* Enable all receives */
rxctrl = NGBE_READ_REG(hw, NGBE_RDB_PB_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19000
)));
rxctrl |= NGBE_RDB_PB_CTL_PBEN0x80000000;
hw->mac.ops.enable_rx_dma(hw, rxctrl);
1663out:
return error;
1665}

1667void
1668ngbe_initialize_rss_mapping(struct ngbe_softc *sc)
1669{
struct ngbe_hw *hw = &sc->hw;
uint32_t reta = 0, rss_field, rss_key[10];
int i, j, queue_id;

/* Set up the redirection table */
for (i = 0, j = 0; i < 128; i++, j++) {
if (j == sc->sc_nqueues)
	j = 0;
queue_id = j;
/*
 * The low 8 bits are for hash value (n+0);
 * The next 8 bits are for hash value (n+1), etc.
 */
reta = reta >> 8;
reta = reta | (((uint32_t)queue_id) << 24);
if ((i & 3) == 3) {
	NGBE_WRITE_REG(hw, NGBE_RDB_RSSTBL(i >> 2), reta)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x19400
 + ((i >> 2) * 4))), (reta)));
	reta = 0;
}
}

/* Set up random bits */
stoeplitz_to_key(&rss_key, sizeof(rss_key));

/* Fill out hash function seeds */
for (i = 0; i < 10; i++)
NGBE_WRITE_REG(hw, NGBE_RDB_RSSRK(i), rss_key[i])((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x19480
 + ((i) * 4))), (rss_key[i])));

/* Perform hash on these packet types */
rss_field = NGBE_RDB_RA_CTL_RSS_EN0x00000004 | NGBE_RDB_RA_CTL_RSS_IPV40x00020000 |
   NGBE_RDB_RA_CTL_RSS_IPV4_TCP0x00010000 | NGBE_RDB_RA_CTL_RSS_IPV60x00100000 |
   NGBE_RDB_RA_CTL_RSS_IPV6_TCP0x00200000;

NGBE_WRITE_REG(hw, NGBE_RDB_RA_CTL, rss_field)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x194f4
), (rss_field)));
1704}

1706int
1707ngbe_initialize_transmit_unit(struct ngbe_softc *sc)
1708{
struct ngbe_hw *hw = &sc->hw;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct tx_ring *txr;
uint64_t tdba;
uint32_t txdctl;
int i, wait_loop = NGBE_MAX_RX_DESC_POLL10;;
int error = 0;

/* TDM_CTL.TE must be before Tx queues are enabled */
NGBE_WRITE_REG_MASK(hw, NGBE_TDM_CTL0x18000, NGBE_TDM_CTL_TE0x1,
   NGBE_TDM_CTL_TE0x1);

/* Setup the base and length of the Tx descriptor ring. */
for (i = 0; i < sc->sc_nqueues; i++) {
txr = &sc->tx_rings[i];
tdba = txr->txdma.dma_map->dm_segs[0].ds_addr;

/* Disable queue to avoid issues while updating state */
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), NGBE_PX_TR_CFG_SWFLSH)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03010
 + ((i) * 0x40))), (0x04000000)));
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));

NGBE_WRITE_REG(hw, NGBE_PX_TR_BAL(i),((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03000
 + ((i) * 0x40))), ((tdba & 0x00000000ffffffffULL))))
    (tdba & 0x00000000ffffffffULL))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03000
 + ((i) * 0x40))), ((tdba & 0x00000000ffffffffULL))));
NGBE_WRITE_REG(hw, NGBE_PX_TR_BAH(i), (tdba >> 32))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03004
 + ((i) * 0x40))), ((tdba >> 32))));

/* Reset head and tail pointers */
NGBE_WRITE_REG(hw, NGBE_PX_TR_RP(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x0300c
 + ((i) * 0x40))), (0)));
NGBE_WRITE_REG(hw, NGBE_PX_TR_WP(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03008
 + ((i) * 0x40))), (0)));

txr->watchdog_timer = 0;

txdctl = NGBE_PX_TR_CFG_ENABLE(1);
txdctl |= 4 << NGBE_PX_TR_CFG_TR_SIZE_SHIFT1;
txdctl |= 0x20 << NGBE_PX_TR_CFG_WTHRESH_SHIFT16;

/* Enable queue */
NGBE_WRITE_REG(hw, NGBE_PX_TR_CFG(i), txdctl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03010
 + ((i) * 0x40))), (txdctl)));

/* Poll to verify queue is enabled */
do {
	msec_delay(1)(*delay_func)(1000 * (1));
	txdctl = NGBE_READ_REG(hw, NGBE_PX_TR_CFG(i))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x03010
 + ((i) * 0x40)))));
} while (--wait_loop && !(txdctl & NGBE_PX_TR_CFG_ENABLE(1)));
if (!wait_loop) {
	printf("%s: Tx queue %d not set within "
	    "the polling period\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	error = ETIMEDOUT60;
	goto out;
}
}

ifp->if_timer = 0;

NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_BUF_AE0x1d00c, 0x3ff, 0x10);
NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_CTL0x1d000, 0x2, 0);
NGBE_WRITE_REG_MASK(hw, NGBE_TSEC_CTL0x1d000, 0x1, 1);

/* Enable mac transmitter */
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_TX_CFG0x11000, NGBE_MAC_TX_CFG_TE0x00000001,
   NGBE_MAC_TX_CFG_TE0x00000001);
1769out:
return error;
1771}

1773int
1774ngbe_intr_link(void *arg)
1775{
struct ngbe_softc *sc = (struct ngbe_softc *)arg;
uint32_t eicr;

eicr = ngbe_misc_isb(sc, NGBE_ISB_MISC);
if (eicr & (NGBE_PX_MISC_IC_PHY0x00040000 | NGBE_PX_MISC_IC_GPIO0x04000000)) {
KERNEL_LOCK()_kernel_lock();
ngbe_handle_phy_event(sc);
ngbe_update_link_status(sc);
KERNEL_UNLOCK()_kernel_unlock();
}
ngbe_enable_queue(sc, sc->linkvec);
return 1;
1788}

1790int
1791ngbe_intr_queue(void *arg)
1792{
struct ngbe_queue *nq = arg;
struct ngbe_softc *sc = nq->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct rx_ring *rxr = nq->rxr;
struct tx_ring *txr = nq->txr;

if (ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40))) {
ngbe_rxeof(rxr);
ngbe_txeof(txr);
ngbe_rxrefill(rxr);
}

ngbe_enable_queue(sc, nq->msix);

return 1;
1808}

1810void
1811ngbe_init_eeprom_params(struct ngbe_hw *hw)
1812{
struct ngbe_eeprom_info *eeprom = &hw->eeprom;

if (eeprom->type == ngbe_eeprom_uninitialized) {
eeprom->type = ngbe_eeprom_none;

if (!(NGBE_READ_REG(hw, NGBE_SPI_STATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1010c
))) &
    NGBE_SPI_STATUS_FLASH_BYPASS0x80000000))
	eeprom->type = ngbe_flash;
}

eeprom->sw_region_offset = 0x80;
1824}

1826int
1827ngbe_init_hw(struct ngbe_softc *sc)
1828{
struct ngbe_hw *hw = &sc->hw;
int status;

/* Reset the hardware */
status = hw->mac.ops.reset_hw(sc);

if (!status)
status = hw->mac.ops.start_hw(sc);

return status;
1839}

1841void
1842ngbe_init_ops(struct ngbe_hw *hw)
1843{
struct ngbe_mac_info *mac = &hw->mac;
struct ngbe_phy_info *phy = &hw->phy;
struct ngbe_eeprom_info *eeprom = &hw->eeprom;

phy->ops.reset = ngbe_phy_reset;
phy->ops.read_reg = ngbe_phy_read_reg;
phy->ops.write_reg = ngbe_phy_write_reg;
phy->ops.setup_link = ngbe_phy_setup_link;
phy->ops.phy_led_ctrl = ngbe_phy_led_ctrl;
phy->ops.check_overtemp = ngbe_phy_check_overtemp;
phy->ops.identify = ngbe_phy_identify;
phy->ops.init = ngbe_phy_init;
phy->ops.check_event = ngbe_phy_check_event;
phy->ops.get_adv_pause = ngbe_phy_get_advertised_pause;
phy->ops.get_lp_adv_pause = ngbe_phy_get_lp_advertised_pause;
phy->ops.set_adv_pause = ngbe_phy_set_pause_advertisement;
phy->ops.setup_once = ngbe_phy_setup;

/* MAC */
mac->ops.init_hw = ngbe_init_hw;
mac->ops.clear_hw_cntrs = ngbe_clear_hw_cntrs;
mac->ops.get_mac_addr = ngbe_get_mac_addr;
mac->ops.stop_adapter = ngbe_stop_adapter;
mac->ops.get_bus_info = ngbe_get_bus_info;
mac->ops.set_lan_id = ngbe_set_lan_id_multi_port_pcie;
mac->ops.acquire_swfw_sync = ngbe_acquire_swfw_sync;
mac->ops.release_swfw_sync = ngbe_release_swfw_sync;
mac->ops.reset_hw = ngbe_reset_hw;
mac->ops.get_media_type = ngbe_get_media_type;
mac->ops.disable_sec_rx_path = ngbe_disable_sec_rx_path;
mac->ops.enable_sec_rx_path = ngbe_enable_sec_rx_path;
mac->ops.enable_rx_dma = ngbe_enable_rx_dma;
mac->ops.start_hw = ngbe_start_hw;

/* RAR, Multicast, VLAN */
mac->ops.set_rar = ngbe_set_rar;
mac->ops.init_rx_addrs = ngbe_init_rx_addrs;
mac->ops.update_mc_addr_list = ngbe_update_mc_addr_list;
mac->ops.enable_rx = ngbe_enable_rx;
mac->ops.disable_rx = ngbe_disable_rx;
mac->ops.clear_vfta = ngbe_clear_vfta;
mac->ops.init_uta_tables = ngbe_init_uta_tables;

/* Flow Control */
mac->ops.fc_enable = ngbe_fc_enable;
mac->ops.setup_fc = ngbe_setup_fc;

/* Link */
mac->ops.check_link = ngbe_check_mac_link;
mac->ops.setup_rxpba = ngbe_set_rxpba;

mac->mcft_size = NGBE_SP_MC_TBL_SIZE128;
mac->vft_size = NGBE_SP_VFT_TBL_SIZE128;
mac->num_rar_entries = NGBE_SP_RAR_ENTRIES32;
mac->rx_pb_size = NGBE_SP_RX_PB_SIZE42;
mac->max_rx_queues = NGBE_SP_MAX_RX_QUEUES8;
mac->max_tx_queues = NGBE_SP_MAX_TX_QUEUES8;

/* EEPROM */
eeprom->ops.init_params = ngbe_init_eeprom_params;
eeprom->ops.eeprom_chksum_cap_st = ngbe_eepromcheck_cap;
eeprom->ops.phy_led_oem_chk = ngbe_phy_led_oem_chk;

/* Manageability interface */
mac->ops.set_fw_drv_ver = ngbe_set_fw_drv_ver;
mac->ops.init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1910}

1912void
1913ngbe_init_rx_addrs(struct ngbe_softc *sc)
1914{
struct ngbe_hw *hw = &sc->hw;
uint32_t rar_entries = hw->mac.num_rar_entries;
uint32_t i, psrctl;

/*
* If the current mac address is valid, assume it is a software
* override to the permanent address.
* Otherwise, use the permanent address from the eeprom.
*/
if (ngbe_validate_mac_addr(hw->mac.addr)) {
/* Get the MAC address from the RAR0 for later reference */
hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
}
hw->addr_ctrl.overflow_promisc = 0;
hw->addr_ctrl.rar_used_count = 1;

/* Zero out the other receive addresses. */
for (i = 1; i < rar_entries; i++) {
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, i)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16210
), (i)));
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_L, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16200
), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_H, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16204
), (0)));
}

/* Clear the MTA */
hw->addr_ctrl.mta_in_use = 0;
psrctl = NGBE_READ_REG(hw, NGBE_PSR_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
)));
psrctl &= ~(NGBE_PSR_CTL_MO0x00000060 | NGBE_PSR_CTL_MFE0x00000080);
psrctl |= hw->mac.mc_filter_type << NGBE_PSR_CTL_MO_SHIFT5;
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
), (psrctl)));

for (i = 0; i < hw->mac.mcft_size; i++)
NGBE_WRITE_REG(hw, NGBE_PSR_MC_TBL(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15200
 + ((i) * 4))), (0)));

hw->mac.ops.init_uta_tables(hw);
1949}

1951void
1952ngbe_init_shared_code(struct ngbe_softc *sc)
1953{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
struct ngbe_hw *hw = &sc->hw;

hw->subsystem_device_id = PCI_PRODUCT(pci_conf_read(pa->pa_pc,(((pci_conf_read(pa->pa_pc, pa->pa_tag, 0x2c)) >>
 16) & 0xffff)
   pa->pa_tag, PCI_SUBSYS_ID_REG))(((pci_conf_read(pa->pa_pc, pa->pa_tag, 0x2c)) >>
 16) & 0xffff);  

hw->phy.type = ngbe_phy_internal;

NGBE_WRITE_REG(hw, NGBE_MDIO_CLAUSE_SELECT, 0xf)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11220
), (0xf)));

ngbe_init_ops(hw);

/* Default flow control settings. */
hw->fc.requested_mode = ngbe_fc_full;
hw->fc.current_mode = ngbe_fc_full;

hw->fc.pause_time = NGBE_DEFAULT_FCPAUSE0xffff;
hw->fc.disable_fc_autoneg = 0;
1973}

1975void
1976ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1977{
/* Only support thermal sensors attached to SP physical port 0 */
if (hw->bus.lan_id)
return;

NGBE_WRITE_REG(hw, NGBE_TS_INT_EN, NGBE_TS_INT_EN_DALARM_INT_EN |((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10314
), (0x00000002 | 0x00000001)))
   NGBE_TS_INT_EN_ALARM_INT_EN)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10314
), (0x00000002 | 0x00000001)));
NGBE_WRITE_REG(hw, NGBE_TS_EN, NGBE_TS_EN_ENA)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10304
), (0x00000001)));

NGBE_WRITE_REG(hw, NGBE_TS_ALARM_THRE, 0x344)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1030c
), (0x344)));
NGBE_WRITE_REG(hw, NGBE_TS_DALARM_THRE, 0x330)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10310
), (0x330)));
1988}

1990void
1991ngbe_init_uta_tables(struct ngbe_hw *hw)
1992{
int i;

for (i = 0; i < 128; i++)
NGBE_WRITE_REG(hw, NGBE_PSR_UC_TBL(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15400
 + ((i) * 4))), (0)));
1997}

1999void
2000ngbe_fc_autoneg(struct ngbe_softc *sc)
2001{
struct ngbe_hw *hw = &sc->hw;
uint32_t speed;
int link_up;
int error = EINVAL22;

/*
* AN should have completed when the cable was plugged in.
* Look for reasons to bail out.  Bail out if:
* - FC autoneg is disabled, or if
* - link is not up.
*/
if (hw->fc.disable_fc_autoneg) {
printf("%s: flow control autoneg is disabled\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto out;
}

hw->mac.ops.check_link(hw, &speed, &link_up, 0);
if (!link_up)
goto out;

switch (hw->phy.media_type) {
/* Autoneg flow control on fiber adapters */
case ngbe_media_type_fiber:
break;

/* Autoneg flow control on copper adapters */
case ngbe_media_type_copper:
error = ngbe_fc_autoneg_copper(sc);
break;
default:
break;
}
2034out:
if (error) {
hw->fc.fc_was_autonegged = 0;
hw->fc.current_mode = hw->fc.requested_mode;
} else
hw->fc.fc_was_autonegged = 1;
2040}

2042int
2043ngbe_fc_autoneg_copper(struct ngbe_softc *sc)
2044{
struct ngbe_hw *hw = &sc->hw;
uint8_t technology_ability_reg, lp_technology_ability_reg;

technology_ability_reg = lp_technology_ability_reg = 0;
if (!((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080)) {
hw->phy.ops.get_adv_pause(hw, &technology_ability_reg);
hw->phy.ops.get_lp_adv_pause(hw, &lp_technology_ability_reg);
}

return ngbe_negotiate_fc(sc, (uint32_t)technology_ability_reg,
   (uint32_t)lp_technology_ability_reg, NGBE_TAF_SYM_PAUSE0x1,
   NGBE_TAF_ASM_PAUSE0x2, NGBE_TAF_SYM_PAUSE0x1, NGBE_TAF_ASM_PAUSE0x2);
2057}

2059int
2060ngbe_fc_enable(struct ngbe_softc *sc)
2061{
struct ngbe_hw *hw = &sc->hw;
uint32_t mflcn, fccfg;
uint32_t fcrtl, fcrth;
uint32_t reg;
int error = 0;

/* Validate the water mark configuration */
if (!hw->fc.pause_time) {
error = EINVAL22;
goto out;
}

/* Low water mark of zero causes XOFF floods */
if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
if (!hw->fc.low_water ||
    hw->fc.low_water >= hw->fc.high_water) {
	printf("%s: invalid water mark configuration\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	error = EINVAL22;
	goto out;
}
}

/* Negotiate the fc mode to use */
ngbe_fc_autoneg(sc);

/* Disable any previous flow control settings */
mflcn = NGBE_READ_REG(hw, NGBE_MAC_RX_FLOW_CTRL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11090
)));
mflcn &= ~NGBE_MAC_RX_FLOW_CTRL_RFE0x00000001;

fccfg = NGBE_READ_REG(hw, NGBE_RDB_RFCC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x192a4
)));
fccfg &= ~NGBE_RDB_RFCC_RFCE_802_3X0x00000008;

/*
* The possible values of fc.current_mode are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
*    but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
*    we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
switch (hw->fc.current_mode) {
case ngbe_fc_none:
/*
 * Flow control is disabled by software override or autoneg.
 * The code below will actually disable it in the HW.
 */
break;
case ngbe_fc_rx_pause:
/*
 * Rx Flow control is enabled and Tx Flow control is
 * disabled by software override. Since there really
 * isn't a way to advertise that we are capable of RX
 * Pause ONLY, we will advertise that we support both
 * symmetric and asymmetric Rx PAUSE.  Later, we will
 * disable the adapter's ability to send PAUSE frames.
 */
mflcn |= NGBE_MAC_RX_FLOW_CTRL_RFE0x00000001;
break;
case ngbe_fc_tx_pause:
/*
 * Tx Flow control is enabled, and Rx Flow control is
 * disabled by software override.
 */
fccfg |= NGBE_RDB_RFCC_RFCE_802_3X0x00000008;
break;
case ngbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
mflcn |= NGBE_MAC_RX_FLOW_CTRL_RFE0x00000001;
fccfg |= NGBE_RDB_RFCC_RFCE_802_3X0x00000008;
break;
default:
printf("%s: flow control param set incorrectly\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = EINVAL22;
goto out;
}

/* Set 802.3x based flow control settings. */
NGBE_WRITE_REG(hw, NGBE_MAC_RX_FLOW_CTRL, mflcn)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11090
), (mflcn)));
NGBE_WRITE_REG(hw, NGBE_RDB_RFCC, fccfg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x192a4
), (fccfg)));

/* Set up and enable Rx high/low water mark thresholds, enable XON. */
if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
/* 32Byte granularity */
fcrtl = (hw->fc.low_water << 10) | NGBE_RDB_RFCL_XONE0x80000000;
NGBE_WRITE_REG(hw, NGBE_RDB_RFCL, fcrtl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19220
), (fcrtl)));
fcrth = (hw->fc.high_water << 10) | NGBE_RDB_RFCH_XOFFE0x80000000;
} else {
NGBE_WRITE_REG(hw, NGBE_RDB_RFCL, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19220
), (0)));
/*
 * In order to prevent Tx hangs when the internal Tx
 * switch is enabled we must set the high water mark
 * to the Rx packet buffer size - 24KB.  This allows
 * the Tx switch to function even under heavy Rx
 * workloads.
 */
fcrth = NGBE_READ_REG(hw, NGBE_RDB_PB_SZ)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19020
))) - 24576;
}

NGBE_WRITE_REG(hw, NGBE_RDB_RFCH, fcrth)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19260
), (fcrth)));

/* Configure pause time (2 TCs per register) */
reg = hw->fc.pause_time * 0x00010000;
NGBE_WRITE_REG(hw, NGBE_RDB_RFCV, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19200
), (reg)));

/* Configure flow control refresh threshold value */
NGBE_WRITE_REG(hw, NGBE_RDB_RFCRT, hw->fc.pause_time / 2)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x192a0
), (hw->fc.pause_time / 2)));
2171out:
return error;
2173}

2175int
2176ngbe_fmgr_cmd_op(struct ngbe_hw *hw, uint32_t cmd, uint32_t cmd_addr)
2177{
uint32_t val;
int timeout = 0;

val = (cmd << SPI_CLK_CMD_OFFSET28) | cmd_addr |
   (SPI_CLK_DIV3 << SPI_CLK_DIV_OFFSET25);
NGBE_WRITE_REG(hw, NGBE_SPI_CMD, val)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10104
), (val)));
for (;;) {
if (NGBE_READ_REG(hw, NGBE_SPI_STATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1010c
))) & 0x1)
	break;
if (timeout == SPI_TIME_OUT_VALUE10000)
	return ETIMEDOUT60;

timeout++;
DELAY(10)(*delay_func)(10);
}

return 0;
2195}

2197uint32_t
2198ngbe_flash_read_dword(struct ngbe_hw *hw, uint32_t addr)
2199{
int status = ngbe_fmgr_cmd_op(hw, SPI_CMD_READ_DWORD1, addr);
if (status)
return status;

return NGBE_READ_REG(hw, NGBE_SPI_DATA)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10108
)));
2205}

2207uint8_t
2208ngbe_calculate_checksum(uint8_t *buffer, uint32_t length)
2209{
uint32_t i;
uint8_t sum = 0;

if (!buffer)
return 0;

for (i = 0; i < length; i++)
sum += buffer[i];
return (uint8_t)(0 - sum);
2219}

2221int
2222ngbe_check_flash_load(struct ngbe_softc *sc, uint32_t check_bit)
2223{
struct ngbe_hw *hw = &sc->hw;
uint32_t reg = 0;
int i, error = 0;

/* if there's flash existing */
if (!(NGBE_READ_REG(hw, NGBE_SPI_STATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1010c
))) &
   NGBE_SPI_STATUS_FLASH_BYPASS0x80000000)) {
/* wait hw load flash done */
for (i = 0; i < NGBE_MAX_FLASH_LOAD_POLL_TIME10; i++) {
	reg = NGBE_READ_REG(hw, NGBE_SPI_ILDR_STATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10120
)));
	if (!(reg & check_bit))
		break;
	msec_delay(200)(*delay_func)(1000 * (200));
}
if (i == NGBE_MAX_FLASH_LOAD_POLL_TIME10) {
	error = ETIMEDOUT60;
	printf("%s: hardware loading flash failed\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
}
}
return error;
2245}

2247int
2248ngbe_check_internal_phy_id(struct ngbe_softc *sc)
2249{
struct ngbe_hw *hw = &sc->hw;
uint16_t phy_id, phy_id_high, phy_id_low;

ngbe_gphy_wait_mdio_access_on(hw);

ngbe_phy_read_reg(hw, NGBE_MDI_PHY_ID1_OFFSET2, 0, &phy_id_high);
phy_id = phy_id_high << 6;
ngbe_phy_read_reg(hw, NGBE_MDI_PHY_ID2_OFFSET3, 0, &phy_id_low);
phy_id |= (phy_id_low & NGBE_MDI_PHY_ID_MASK0xfffffc00) >> 10;

if (NGBE_INTERNAL_PHY_ID0x000732 != phy_id) {
printf("%s: internal phy id 0x%x not supported\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), phy_id);
return ENOTSUP91;
} else
hw->phy.id = (uint32_t)phy_id;

return 0;
2268}

2270int
2271ngbe_check_mac_link(struct ngbe_hw *hw, uint32_t *speed, int *link_up,
  int link_up_wait_to_complete)
2273{
uint32_t status = 0;
uint16_t speed_sta, value = 0;
int i;

if ((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080) {
*link_up = 1;
*speed = NGBE_LINK_SPEED_1GB_FULL2;
return status;
}

if (link_up_wait_to_complete) {
for (i = 0; i < NGBE_LINK_UP_TIME90; i++) {
	status = hw->phy.ops.read_reg(hw,
	    NGBE_MDIO_AUTO_NEG_STATUS0x1a,
	    NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, &value);
	if (!status && (value & 0x4)) {
		*link_up = 1;
		break;
	} else
		*link_up = 0;
	msec_delay(100)(*delay_func)(1000 * (100));
}
} else {
status = hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_STATUS0x1a,
    NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, &value);
if (!status && (value & 0x4))
	*link_up = 1;
else
	*link_up = 0;
}

speed_sta = value & 0x38;
if (*link_up) {
if (speed_sta == 0x28)
	*speed = NGBE_LINK_SPEED_1GB_FULL2;
else if (speed_sta == 0x18)
	*speed = NGBE_LINK_SPEED_100_FULL1;
else if (speed_sta == 0x8)
	*speed = NGBE_LINK_SPEED_10_FULL8;
} else
*speed = NGBE_LINK_SPEED_UNKNOWN0;

return status;
2317}

2319int
2320ngbe_check_mng_access(struct ngbe_hw *hw)
2321{
if (!ngbe_mng_present(hw))
return 0;
return 1;
2325}

2327int
2328ngbe_check_reset_blocked(struct ngbe_softc *sc)
2329{
uint32_t mmngc;

mmngc = NGBE_READ_REG(&sc->hw, NGBE_MIS_ST)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x10028)));
if (mmngc & NGBE_MIS_ST_MNG_VETO0x00000100) {
printf("%s: MNG_VETO bit detected\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return 1;
}

return 0;
2339}

2341void
2342ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
2343{
uint16_t i;

NGBE_READ_REG(hw, NGBE_RX_CRC_ERROR_FRAMES_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11928
)));
NGBE_READ_REG(hw, NGBE_RX_LEN_ERROR_FRAMES_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11978
)));
NGBE_READ_REG(hw, NGBE_RDB_LXONTXC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1921c
)));
NGBE_READ_REG(hw, NGBE_RDB_LXOFFTXC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19218
)));
NGBE_READ_REG(hw, NGBE_MAC_LXOFFRXC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11988
)));

for (i = 0; i < 8; i++) {
NGBE_WRITE_REG_MASK(hw, NGBE_MMC_CONTROL0x11800, NGBE_MMC_CONTROL_UP0x700,
    i << 16);
NGBE_READ_REG(hw, NGBE_MAC_PXOFFRXC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x119dc
)));
}

NGBE_READ_REG(hw, NGBE_PX_GPRC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x12504
)));
NGBE_READ_REG(hw, NGBE_PX_GPTC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x18308
)));
NGBE_READ_REG(hw, NGBE_PX_GORC_MSB)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1250c
)));
NGBE_READ_REG(hw, NGBE_PX_GOTC_MSB)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x18310
)));

NGBE_READ_REG(hw, NGBE_RX_BC_FRAMES_GOOD_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11918
)));
NGBE_READ_REG(hw, NGBE_RX_UNDERSIZE_FRAMES_GOOD)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11938
)));
NGBE_READ_REG(hw, NGBE_RX_OVERSIZE_FRAMES_GOOD)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1193c
)));
NGBE_READ_REG(hw, NGBE_RX_FRAME_CNT_GOOD_BAD_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11900
)));
NGBE_READ_REG(hw, NGBE_TX_FRAME_CNT_GOOD_BAD_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1181c
)));
NGBE_READ_REG(hw, NGBE_TX_MC_FRAMES_GOOD_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1182c
)));
NGBE_READ_REG(hw, NGBE_TX_BC_FRAMES_GOOD_LOW)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11824
)));
NGBE_READ_REG(hw, NGBE_RDM_DRP_PKT)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x12500
)));
2371}

2373void
2374ngbe_clear_vfta(struct ngbe_hw *hw)
2375{
uint32_t offset;

for (offset = 0; offset < hw->mac.vft_size; offset++) {
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_TBL(offset), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x16000
 + ((offset) * 4))), (0)));
/* Errata 5 */
hw->mac.vft_shadow[offset] = 0;
}

for (offset = 0; offset < NGBE_PSR_VLAN_SWC_ENTRIES32; offset++) {
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC_IDX, offset)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16230
), (offset)));
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16220
), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_VLAN_SWC_VM_L, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16224
), (0)));
}
2389}

2391void
2392ngbe_configure_ivars(struct ngbe_softc *sc)
2393{
struct ngbe_queue *nq = sc->queues;
uint32_t newitr;
int i;

/* Populate MSIX to EITR select */
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITRSEL, 0)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00180), (0)));

newitr = (4000000 / NGBE_MAX_INTS_PER_SEC8000) & NGBE_MAX_EITR0x00007ffc;
newitr |= NGBE_PX_ITR_CNT_WDIS0x80000000;

for (i = 0; i < sc->sc_nqueues; i++, nq++) {
/* Rx queue entry */
ngbe_set_ivar(sc, i, nq->msix, 0);
/* Tx queue entry */
ngbe_set_ivar(sc, i, nq->msix, 1);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITR(nq->msix), newitr)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x00200 + (nq->msix) * 4)), (newitr)));
}

/* For the Link interrupt */
ngbe_set_ivar(sc, 0, sc->linkvec, -1);
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ITR(sc->linkvec), 1950)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x00200 + (sc->linkvec) * 4)), (1950)));
2415}

2417void
2418ngbe_configure_pb(struct ngbe_softc *sc)
2419{
struct ngbe_hw *hw = &sc->hw;

hw->mac.ops.setup_rxpba(hw, 0, 0, PBA_STRATEGY_EQUAL0);
ngbe_pbthresh_setup(sc);
2424}

2426void
2427ngbe_disable_intr(struct ngbe_softc *sc)
2428{
struct ngbe_queue *nq;
int i;

NGBE_WRITE_REG(&sc->hw, NGBE_PX_MISC_IEN, 0)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00108), (0)));
for (i = 0, nq = sc->queues; i < sc->sc_nqueues; i++, nq++)
ngbe_disable_queue(sc, nq->msix);
NGBE_WRITE_FLUSH(&sc->hw)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x10000)));
2436}

2438int
2439ngbe_disable_pcie_master(struct ngbe_softc *sc)
2440{
int i, error = 0;

/* Exit if master requests are blocked */
if (!(NGBE_READ_REG(&sc->hw, NGBE_PX_TRANSACTION_PENDING)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00168)))))
goto out;

/* Poll for master request bit to clear */
for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT800; i++) {
DELAY(100)(*delay_func)(100);
if (!(NGBE_READ_REG(&sc->hw, NGBE_PX_TRANSACTION_PENDING)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00168)))))
	goto out;
}
printf("%s: PCIe transaction pending bit did not clear\n",
   DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ETIMEDOUT60;
2456out:
return error;
2458}

2460void
2461ngbe_disable_queue(struct ngbe_softc *sc, uint32_t vector)
2462{
uint64_t queue = 1ULL << vector;
uint32_t mask;

mask = (queue & 0xffffffff);
if (mask)
NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMS, mask)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00140), (mask)));
2469}

2471void
2472ngbe_disable_rx(struct ngbe_hw *hw)
2473{
uint32_t rxctrl, psrctrl;

rxctrl = NGBE_READ_REG(hw, NGBE_RDB_PB_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19000
)));
if (rxctrl & NGBE_RDB_PB_CTL_PBEN0x80000000) {
psrctrl = NGBE_READ_REG(hw, NGBE_PSR_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
)));
if (psrctrl & NGBE_PSR_CTL_SW_EN0x00040000) {
	psrctrl &= ~NGBE_PSR_CTL_SW_EN0x00040000;
	NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctrl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
), (psrctrl)));
	hw->mac.set_lben = 1;
} else
	hw->mac.set_lben = 0;
rxctrl &= ~NGBE_RDB_PB_CTL_PBEN0x80000000;
NGBE_WRITE_REG(hw, NGBE_RDB_PB_CTL, rxctrl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19000
), (rxctrl)));

NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG0x11004, NGBE_MAC_RX_CFG_RE0x00000001,
    0);
}
2491}

2493void
2494ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
2495{
uint32_t secrxreg;
int i;

NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL0x17000, NGBE_RSEC_CTL_RX_DIS0x00000002,
   NGBE_RSEC_CTL_RX_DIS0x00000002);
for (i = 0; i < 40; i++) {
secrxreg = NGBE_READ_REG(hw, NGBE_RSEC_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x17004
)));
if (secrxreg & NGBE_RSEC_ST_RSEC_RDY0x00000001)
	break;
else
	DELAY(1000)(*delay_func)(1000);
}
2508}

2510int
2511ngbe_eepromcheck_cap(struct ngbe_softc *sc, uint16_t offset, uint32_t *data)
2512{
struct ngbe_hw *hw = &sc->hw;
struct ngbe_hic_read_shadow_ram buffer;
uint32_t tmp;
int status;

buffer.hdr.req.cmd = FW_EEPROM_CHECK_STATUS0xe9;
buffer.hdr.req.buf_lenh = 0;
buffer.hdr.req.buf_lenl = 0;
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM0xff;

/* Convert offset from words to bytes */
buffer.address = 0;
/* one word */
buffer.length = 0;

status = ngbe_host_interface_command(sc, (uint32_t *)&buffer,
   sizeof(buffer), NGBE_HI_COMMAND_TIMEOUT5000, 0);
if (status)
return status;

if (ngbe_check_mng_access(hw)) {
tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 1)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((1) << 2)))));
if (tmp == NGBE_CHECKSUM_CAP_ST_PASS0x80658383)
	status = 0;
else
	status = EINVAL22;
} else
status = EINVAL22;

return status;
2543}

2545void
2546ngbe_enable_intr(struct ngbe_softc *sc)
2547{
struct ngbe_hw *hw = &sc->hw;
struct ngbe_queue *nq;
uint32_t mask;
int i;

/* Enable misc interrupt */
mask = NGBE_PX_MISC_IEN_MASK(0x00000100 | 0x00000400 | 0x00001000 | 0x00020000 | 0x00040000
 | 0x00080000 | 0x00100000 | 0x00800000 | 0x04000000 | 0x08000000
 | 0x40000000 | 0x80000000);

mask |= NGBE_PX_MISC_IEN_OVER_HEAT0x10000000;
NGBE_WRITE_REG(hw, NGBE_GPIO_DDR, 0x1)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x14804
), (0x1)));
NGBE_WRITE_REG(hw, NGBE_GPIO_INTEN, 0x3)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x14830
), (0x3)));
NGBE_WRITE_REG(hw, NGBE_GPIO_INTTYPE_LEVEL, 0x0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x14838
), (0x0)));

NGBE_WRITE_REG(hw, NGBE_GPIO_POLARITY, 0x3)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1483c
), (0x3)));

NGBE_WRITE_REG(hw, NGBE_PX_MISC_IEN, mask)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x00108
), (mask)));

/* Enable all queues */
for (i = 0, nq = sc->queues; i < sc->sc_nqueues; i++, nq++)
ngbe_enable_queue(sc, nq->msix);
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));

ngbe_enable_queue(sc, sc->linkvec);
2571}

2573void
2574ngbe_enable_queue(struct ngbe_softc *sc, uint32_t vector)
2575{
uint64_t queue = 1ULL << vector;
uint32_t mask;

mask = (queue & 0xffffffff);
if (mask)
NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMC, mask)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00150), (mask)));
2582}

2584void
2585ngbe_enable_rx(struct ngbe_hw *hw)
2586{
uint32_t val;

/* Enable mac receiver */
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG0x11004, NGBE_MAC_RX_CFG_RE0x00000001,
   NGBE_MAC_RX_CFG_RE0x00000001);

NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL0x17000, 0x2, 0);

NGBE_WRITE_REG_MASK(hw, NGBE_RDB_PB_CTL0x19000, NGBE_RDB_PB_CTL_PBEN0x80000000,
   NGBE_RDB_PB_CTL_PBEN0x80000000);

if (hw->mac.set_lben) {
val = NGBE_READ_REG(hw, NGBE_PSR_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
)));
val |= NGBE_PSR_CTL_SW_EN0x00040000;
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, val)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
), (val)));
hw->mac.set_lben = 0;
}
2604}

2606void
2607ngbe_enable_rx_dma(struct ngbe_hw *hw, uint32_t reg)
2608{
/*
* Workaround for emerald silicon errata when enabling the Rx datapath.
* If traffic is incoming before we enable the Rx unit, it could hang
* the Rx DMA unit.  Therefore, make sure the security engine is
* completely disabled prior to enabling the Rx unit.
*/
hw->mac.ops.disable_sec_rx_path(hw);

if (reg & NGBE_RDB_PB_CTL_PBEN0x80000000)
hw->mac.ops.enable_rx(hw);
else
hw->mac.ops.disable_rx(hw);

hw->mac.ops.enable_sec_rx_path(hw);
2623}

2625void
2626ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
2627{
NGBE_WRITE_REG_MASK(hw, NGBE_RSEC_CTL0x17000, NGBE_RSEC_CTL_RX_DIS0x00000002, 0);
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));
2630}

2632int
2633ngbe_encap(struct tx_ring *txr, struct mbuf *m)
2634{
struct ngbe_softc *sc = txr->sc;
uint32_t olinfo_status = 0, cmd_type_len;
int i, j, ntxc;
int first, last = 0;
bus_dmamap_t map;
struct ngbe_tx_buf *txbuf;
union ngbe_tx_desc *txd = NULL((void *)0);
11
←
'txd' initialized to a null pointer value→

/* Basic descriptor defines */
cmd_type_len = NGBE_TXD_DTYP_DATA0x00000000 | NGBE_TXD_IFCS0x02000000;

/*
* Important to capture the first descriptor
* used because it will contain the index of
* the one we tell the hardware to report back
*/
first = txr->next_avail_desc;
txbuf = &txr->tx_buffers[first];
map = txbuf->map;

/*
* Set the appropriate offload context
* this will becomes the first descriptor.
*/
ntxc = ngbe_tx_ctx_setup(txr, m, &cmd_type_len, &olinfo_status);
if (ntxc == -1)
12
←
Taking false branch→
goto fail;

/*
* Map the packet for DMA.
*/
switch (bus_dmamap_load_mbuf(txr->txdma.dma_tag, map, m,(*(txr->txdma.dma_tag)->_dmamap_load_mbuf)((txr->txdma
.dma_tag), (map), (m), (0x0001))
13
←
Control jumps to 'case 0:'  at line 2668→
   BUS_DMA_NOWAIT)(*(txr->txdma.dma_tag)->_dmamap_load_mbuf)((txr->txdma
.dma_tag), (map), (m), (0x0001))) {
case 0:
break;
14
←
 Execution continues on line 2680→
case EFBIG27:
if (m_defrag(m, M_NOWAIT0x0002) == 0 &&
    bus_dmamap_load_mbuf(txr->txdma.dma_tag, map, m,(*(txr->txdma.dma_tag)->_dmamap_load_mbuf)((txr->txdma
.dma_tag), (map), (m), (0x0001))
    BUS_DMA_NOWAIT)(*(txr->txdma.dma_tag)->_dmamap_load_mbuf)((txr->txdma
.dma_tag), (map), (m), (0x0001)) == 0)
	break;
/* FALLTHROUGH */
default:
return 0;
}

i = txr->next_avail_desc + ntxc;
if (i >= sc->num_tx_desc)
15
←
Assuming 'i' is < field 'num_tx_desc'→
16
←
Taking false branch→
i -= sc->num_tx_desc;

for (j = 0; j < map->dm_nsegs; j++) {
17
←
Assuming 'j' is >= field 'dm_nsegs'→
18
←
Loop condition is false. Execution continues on line 2697→
txd = &txr->tx_base[i];

txd->read.buffer_addr = htole64(map->dm_segs[j].ds_addr)((__uint64_t)(map->dm_segs[j].ds_addr));
txd->read.cmd_type_len =
    htole32(cmd_type_len | map->dm_segs[j].ds_len)((__uint32_t)(cmd_type_len | map->dm_segs[j].ds_len));
txd->read.olinfo_status = htole32(olinfo_status)((__uint32_t)(olinfo_status));
last = i;

if (++i == sc->num_tx_desc)
	i = 0;
}

txd->read.cmd_type_len |= htole32(NGBE_TXD_EOP | NGBE_TXD_RS)((__uint32_t)(0x01000000 | 0x08000000));
19
←
Dereference of null pointer

bus_dmamap_sync(txr->txdma.dma_tag, map, 0, map->dm_mapsize,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x04));

/* Set the index of the descriptor that will be marked done */
txbuf->m_head = m;
txbuf->eop_index = last;

txr->next_avail_desc = i;

return ntxc + j;

2710fail:
bus_dmamap_unload(txr->txdma.dma_tag, txbuf->map)(*(txr->txdma.dma_tag)->_dmamap_unload)((txr->txdma.
dma_tag), (txbuf->map));
return 0;
2713}

2715int
2716ngbe_get_buf(struct rx_ring *rxr, int i)
2717{
struct ngbe_softc *sc = rxr->sc;
struct ngbe_rx_buf *rxbuf;
struct mbuf *m;
union ngbe_rx_desc *rxdesc;
int error;

rxbuf = &rxr->rx_buffers[i];
rxdesc = &rxr->rx_base[i];
if (rxbuf->buf) {
printf("%s: slot %d already has an mbuf\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
return ENOBUFS55;
}

m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN)m_clget((((void *)0)), (0x0002), ((1 << 11) + 2));
if (!m)
return ENOBUFS55;

m->m_datam_hdr.mh_data += (m->m_extM_dat.MH.MH_dat.MH_ext.ext_size - (MCLBYTES(1 << 11) + ETHER_ALIGN2));
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = MCLBYTES(1 << 11) + ETHER_ALIGN2;

error = bus_dmamap_load_mbuf(rxr->rxdma.dma_tag, rxbuf->map, m,(*(rxr->rxdma.dma_tag)->_dmamap_load_mbuf)((rxr->rxdma
.dma_tag), (rxbuf->map), (m), (0x0001))
   BUS_DMA_NOWAIT)(*(rxr->rxdma.dma_tag)->_dmamap_load_mbuf)((rxr->rxdma
.dma_tag), (rxbuf->map), (m), (0x0001));
if (error) {
m_freem(m);
return error;
}

bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x01
))
   rxbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x01
));
rxbuf->buf = m;

rxdesc->read.pkt_addr = htole64(rxbuf->map->dm_segs[0].ds_addr)((__uint64_t)(rxbuf->map->dm_segs[0].ds_addr));

return 0;
2752}

2754void
2755ngbe_get_bus_info(struct ngbe_softc *sc)
2756{
struct ngbe_hw *hw = &sc->hw;
uint16_t link_status;

/* Get the negotiated link width and speed from PCI config space */
link_status = ngbe_read_pci_cfg_word(sc, NGBE_PCI_LINK_STATUS0xb2);

ngbe_set_pci_config_data(hw, link_status);
2764}

2766void
2767ngbe_get_copper_link_capabilities(struct ngbe_hw *hw, uint32_t *speed,
  int *autoneg)
2769{
*speed = 0;

if (hw->mac.autoneg)
*autoneg = 1;
else
*autoneg = 0;

*speed = NGBE_LINK_SPEED_10_FULL8 | NGBE_LINK_SPEED_100_FULL1 |
   NGBE_LINK_SPEED_1GB_FULL2;
2779}

2781int
2782ngbe_get_eeprom_semaphore(struct ngbe_softc *sc)
2783{
struct ngbe_hw *hw = &sc->hw;
uint32_t swsm;
int i, timeout = 2000;
int status = ETIMEDOUT60;

/* Get SMBI software semaphore between device drivers first */
for (i = 0; i < timeout; i++) {
/*
 * If the SMBI bit is 0 when we read it, then the bit will be
 * set and we have the semaphore.
 */
swsm = NGBE_READ_REG(hw, NGBE_MIS_SWSM)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1002c
)));
if (!(swsm & NGBE_MIS_SWSM_SMBI1)) {
	status = 0;
	break;
}	
DELAY(50)(*delay_func)(50);
}

if (i == timeout) {
printf("%s: cannot access the eeprom - SMBI semaphore not "
    "granted\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
/*
 * this release is particularly important because our attempts
 * above to get the semaphore may have succeeded, and if there
 * was a timeout, we should unconditionally clear the semaphore
 * bits to free the driver to make progress.
 */
ngbe_release_eeprom_semaphore(hw);
DELAY(50)(*delay_func)(50);

/* 
 * One last try if the SMBI bit is 0 when we read it,
 * then the bit will be set and we have the semaphore.
 */
swsm = NGBE_READ_REG(hw, NGBE_MIS_SWSM)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1002c
)));
if (!(swsm & NGBE_MIS_SWSM_SMBI1))
	status = 0;
}

return status;
2825}

2827void
2828ngbe_get_hw_control(struct ngbe_hw *hw)
2829{
/* Let firmware know the driver has taken over */
NGBE_WRITE_REG_MASK(hw, NGBE_CFG_PORT_CTL0x14400,
   NGBE_CFG_PORT_CTL_DRV_LOAD0x00000008, NGBE_CFG_PORT_CTL_DRV_LOAD0x00000008);
2833}

2835void
2836ngbe_release_hw_control(struct ngbe_softc *sc)
2837{
/* Let firmware take over control of hw. */
NGBE_WRITE_REG_MASK(&sc->hw, NGBE_CFG_PORT_CTL0x14400,
   NGBE_CFG_PORT_CTL_DRV_LOAD0x00000008, 0);
2841}

2843void
2844ngbe_get_mac_addr(struct ngbe_hw *hw, uint8_t *mac_addr)
2845{
uint32_t rar_high, rar_low;
int i;

NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16210
), (0)));
rar_high = NGBE_READ_REG(hw, NGBE_PSR_MAC_SWC_AD_H)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16204
)));
rar_low = NGBE_READ_REG(hw, NGBE_PSR_MAC_SWC_AD_L)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16200
)));

for (i = 0; i < 2; i++)
mac_addr[i] = (uint8_t)(rar_high >> (1 - i) * 8);

for (i = 0; i < 4; i++)
mac_addr[i + 2] = (uint8_t)(rar_low >> (3 - i) * 8);
2858}

2860enum ngbe_media_type
2861ngbe_get_media_type(struct ngbe_hw *hw)
2862{
enum ngbe_media_type media_type = ngbe_media_type_copper;

return media_type;
2866}

2868void
2869ngbe_gphy_dis_eee(struct ngbe_hw *hw)
2870{
uint16_t val = 0;

hw->phy.ops.write_reg(hw, 0x11, 0xa4b, 0x1110);
hw->phy.ops.write_reg(hw, MII_MMDACR0x0d, 0x0, MMDACR_FN_ADDRESS(0 << 14) | 0x07);
hw->phy.ops.write_reg(hw, MII_MMDAADR0x0e, 0x0, 0x003c);
hw->phy.ops.write_reg(hw, MII_MMDACR0x0d, 0x0, MMDACR_FN_DATANPI(1 << 14) | 0x07);
hw->phy.ops.write_reg(hw, MII_MMDAADR0x0e, 0x0, 0);

/* Disable 10/100M Half Duplex */
msec_delay(100)(*delay_func)(1000 * (100));
hw->phy.ops.read_reg(hw, MII_ANAR0x04, 0, &val);
val &= ~(ANAR_TX0x0080 | ANAR_100x0020);
hw->phy.ops.write_reg(hw, MII_ANAR0x04, 0x0, val);
2884}

2886void
2887ngbe_gphy_efuse_calibration(struct ngbe_softc *sc)
2888{
struct ngbe_hw *hw = &sc->hw;
uint32_t efuse[2];

ngbe_gphy_wait_mdio_access_on(hw);

efuse[0] = sc->gphy_efuse[0];
efuse[1] = sc->gphy_efuse[1];

if (!efuse[0] && !efuse[1])
efuse[0] = efuse[1] = 0xffffffff;

/* Calibration */
efuse[0] |= 0xf0000100;
efuse[1] |= 0xff807fff;

/* EODR, Efuse Output Data Register */
ngbe_phy_write_reg(hw, 16, 0xa46, (efuse[0] >> 0) & 0xffff);
ngbe_phy_write_reg(hw, 17, 0xa46, (efuse[0] >> 16) & 0xffff);
ngbe_phy_write_reg(hw, 18, 0xa46, (efuse[1] >> 0) & 0xffff);
ngbe_phy_write_reg(hw, 19, 0xa46, (efuse[1] >> 16) & 0xffff);

/* Set efuse ready */
ngbe_phy_write_reg(hw, 20, 0xa46, 0x01);
ngbe_gphy_wait_mdio_access_on(hw);
ngbe_phy_write_reg(hw, 27, NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, 0x8011);
ngbe_phy_write_reg(hw, 28, NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, 0x5737);
ngbe_gphy_dis_eee(hw);
2916}

2918void
2919ngbe_gphy_wait_mdio_access_on(struct ngbe_hw *hw)
2920{
uint16_t val = 0;
int i;

for (i = 0; i < 100; i++) {
ngbe_phy_read_reg(hw, 29, NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, &val);
if (val & 0x20)
	break;
DELAY(1000)(*delay_func)(1000);
}
2930}

2932void
2933ngbe_handle_phy_event(struct ngbe_softc *sc)
2934{
struct ngbe_hw *hw = &sc->hw;
uint32_t reg;

reg = NGBE_READ_REG(hw, NGBE_GPIO_INTSTATUS)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x14840
)));
NGBE_WRITE_REG(hw, NGBE_GPIO_EOI, reg)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1484c
), (reg)));
if (!((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080))
hw->phy.ops.check_event(sc);
2942}

2944int
2945ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer,
  uint32_t length, uint32_t timeout, int return_data)
2947{
struct ngbe_hw *hw = &sc->hw;
uint32_t hicr, i, bi, dword_len;
uint32_t hdr_size = sizeof(struct ngbe_hic_hdr);
uint32_t buf[64] = {};
uint16_t buf_len;
int status = 0;

if (length == 0 || length > NGBE_HI_MAX_BLOCK_BYTE_LENGTH256) {
printf("%s: buffer length failure\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return EINVAL22;
}

if (hw->mac.ops.acquire_swfw_sync(sc, NGBE_MNG_SWFW_SYNC_SW_MB0x0004))
return EINVAL22;

/* Calculate length in DWORDs. We must be multiple of DWORD */
if ((length % (sizeof(uint32_t))) != 0) {
printf("%s: buffer length failure, not aligned to dword\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
status = EINVAL22;
goto rel_out;
      }

if (ngbe_check_mng_access(hw)) {
hicr = NGBE_READ_REG(hw, NGBE_MNG_MBOX_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1e044
)));
if ((hicr & NGBE_MNG_MBOX_CTL_FWRDY0x4))
	printf("%s: fwrdy is set before command\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
}

dword_len = length >> 2;

/* 
* The device driver writes the relevant command block 
* into the ram area.
*/
for (i = 0; i < dword_len; i++) {
if (ngbe_check_mng_access(hw)) {
	NGBE_WRITE_REG_ARRAY(hw, NGBE_MNG_MBOX, i,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((i) << 2))), (((__uint32_t)(buffer[i])))))
	    htole32(buffer[i]))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((i) << 2))), (((__uint32_t)(buffer[i])))));
} else {
	status = EINVAL22;
	goto rel_out;
}
}

/* Setting this bit tells the ARC that a new command is pending. */
if (ngbe_check_mng_access(hw)) {
NGBE_WRITE_REG_MASK(hw, NGBE_MNG_MBOX_CTL0x1e044,
    NGBE_MNG_MBOX_CTL_SWRDY0x1, NGBE_MNG_MBOX_CTL_SWRDY0x1);
} else {
status = EINVAL22;
goto rel_out;
}

for (i = 0; i < timeout; i++) {
if (ngbe_check_mng_access(hw)) {
	hicr = NGBE_READ_REG(hw, NGBE_MNG_MBOX_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1e044
)));
	if ((hicr & NGBE_MNG_MBOX_CTL_FWRDY0x4))
		break;
}
msec_delay(1)(*delay_func)(1000 * (1));
}

buf[0] = NGBE_READ_REG(hw, NGBE_MNG_MBOX)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1e100
)));
/* Check command completion */
if (timeout != 0 && i == timeout) {
printf("%s: command has failed with no status valid\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
if ((buffer[0] & 0xff) != (~buf[0] >> 24)) {
	status = EINVAL22;
	goto rel_out;
}
}

if (!return_data)
goto rel_out;

/* Calculate length in DWORDs */
dword_len = hdr_size >> 2;

/* First pull in the header so we know the buffer length */
for (bi = 0; bi < dword_len; bi++) {
if (ngbe_check_mng_access(hw)) {
	buffer[bi] = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, bi)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((bi) << 2)))));
	le32_to_cpus(&buffer[bi])do { *((uint32_t *)(&buffer[bi])) = (((__uint32_t)(*(const
 uint32_t *)((&buffer[bi]))))); } while (0);
} else {
	status = EINVAL22;
	goto rel_out;
}
}

/* If there is any thing in data position pull it in */
buf_len = ((struct ngbe_hic_hdr *)buffer)->buf_len;
if (buf_len == 0)
goto rel_out;

if (length < buf_len + hdr_size) {
printf("%s: buffer not large enough for reply message\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
status = EINVAL22;
goto rel_out;
}

/* Calculate length in DWORDs, add 3 for odd lengths */
dword_len = (buf_len + 3) >> 2;

/* Pull in the rest of the buffer (bi is where we left off) */
for (; bi <= dword_len; bi++) {
if (ngbe_check_mng_access(hw)) {
	buffer[bi] = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, bi)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((bi) << 2)))));
	le32_to_cpus(&buffer[bi])do { *((uint32_t *)(&buffer[bi])) = (((__uint32_t)(*(const
 uint32_t *)((&buffer[bi]))))); } while (0);
} else {
	status = EINVAL22;
	goto rel_out;
}
}

3066rel_out:
hw->mac.ops.release_swfw_sync(sc, NGBE_MNG_SWFW_SYNC_SW_MB0x0004);
return status;
3069}

3071int
3072ngbe_hpbthresh(struct ngbe_softc *sc)
3073{
uint32_t dv_id, rx_pba;
int kb, link, marker, tc;

/* Calculate max LAN frame size */
tc = link = sc->sc_ac.ac_if.if_mtuif_data.ifi_mtu + ETHER_HDR_LEN((6 * 2) + 2) + ETHER_CRC_LEN4 +
   NGBE_ETH_FRAMING20;

/* Calculate delay value for device */
dv_id = NGBE_DV(link, tc)((36 * ((link * 8) + 672 + (2 * 5556) + (2 * (4096 + (2 * 1024
) + 12800)) + 6144) / 25 + 1) + 2 * (tc * 8));

/* Delay value is calculated in bit times convert to KB */
kb = NGBE_BT2KB(dv_id)((dv_id + (8 * 1024 - 1)) / (8 * 1024));
rx_pba = NGBE_READ_REG(&sc->hw, NGBE_RDB_PB_SZ)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x19020))) >> NGBE_RDB_PB_SZ_SHIFT10;

marker = rx_pba - kb;

return marker;
3091}

3093int
3094ngbe_lpbthresh(struct ngbe_softc *sc)
3095{
uint32_t dv_id;
int tc;

/* Calculate max LAN frame size */
tc = sc->sc_ac.ac_if.if_mtuif_data.ifi_mtu + ETHER_HDR_LEN((6 * 2) + 2) + ETHER_CRC_LEN4;

/* Calculate delay value for device */
dv_id = NGBE_LOW_DV(tc)(2 * (2 * (tc * 8) + (36 * 10000 / 25) + 1));

/* Delay value is calculated in bit times convert to KB */
return NGBE_BT2KB(dv_id)((dv_id + (8 * 1024 - 1)) / (8 * 1024));
3107}

3109int
3110ngbe_mng_present(struct ngbe_hw *hw)
3111{
uint32_t fwsm;

fwsm = NGBE_READ_REG(hw, NGBE_MIS_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10028
)));

return fwsm & NGBE_MIS_ST_MNG_INIT_DN0x00000001;
3117}

3119int
3120ngbe_mta_vector(struct ngbe_hw *hw, uint8_t *mc_addr)
3121{
uint32_t vector = 0;
int rshift;

/* pick bits [47:32] of the address. */
vector = mc_addr[4] | (((uint16_t)mc_addr[5]) << 8);
switch (hw->mac.mc_filter_type) {
case 0:	/* bits 47:36 */
case 1:	/* bits 46:35 */
case 2:	/* bits 45:34 */
rshift = 4 - hw->mac.mc_filter_type;
break;
case 3:	/* bits 43:32 */
rshift = 0;
break;
default:	/* Invalid mc_filter_type */
vector = rshift = 0;
break;
}
vector = (vector >> rshift) & 0x0fff;

return vector;
3143}

3145int
3146ngbe_negotiate_fc(struct ngbe_softc *sc, uint32_t adv_reg, uint32_t lp_reg,
  uint32_t adv_sym, uint32_t adv_asm, uint32_t lp_sym, uint32_t lp_asm)
3148{
struct ngbe_hw *hw = &sc->hw;

if ((!(adv_reg)) || (!(lp_reg)))
return EINVAL22;

if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
/*
 * Now we need to check if the user selected Rx ONLY
 * of pause frames.  In this case, we had to advertise
 * FULL flow control because we could not advertise RX
 * ONLY. Hence, we must now check to see if we need to
 * turn OFF the TRANSMISSION of PAUSE frames.
 */
if (hw->fc.requested_mode == ngbe_fc_full)
	hw->fc.current_mode = ngbe_fc_full;
else
	hw->fc.current_mode = ngbe_fc_rx_pause;

} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
   (lp_reg & lp_sym) && (lp_reg & lp_asm))
   	hw->fc.current_mode = ngbe_fc_tx_pause;
else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
   !(lp_reg & lp_sym) && (lp_reg & lp_asm))
   	hw->fc.current_mode = ngbe_fc_rx_pause;
else
hw->fc.current_mode = ngbe_fc_none;

return 0;
3177}

3179int
3180ngbe_non_sfp_link_config(struct ngbe_softc *sc)
3181{
struct ngbe_hw *hw = &sc->hw;
uint32_t speed;
int error;

if (hw->mac.autoneg)
speed = hw->phy.autoneg_advertised;
else
speed = hw->phy.force_speed;

msec_delay(50)(*delay_func)(1000 * (50));
if (hw->phy.type == ngbe_phy_internal) {
error = hw->phy.ops.setup_once(sc);
if (error)
	return error;
}

error = hw->mac.ops.setup_link(sc, speed, 0);
return error;
3200}

3202void
3203ngbe_pbthresh_setup(struct ngbe_softc *sc)
3204{
struct ngbe_hw *hw = &sc->hw;

hw->fc.high_water = ngbe_hpbthresh(sc);
hw->fc.low_water = ngbe_lpbthresh(sc);

/* Low water marks must not be larger than high water marks */
if (hw->fc.low_water > hw->fc.high_water)
hw->fc.low_water = 0;
3213}

3215void
3216ngbe_phy_check_event(struct ngbe_softc *sc)
3217{
struct ngbe_hw *hw = &sc->hw;
uint16_t value = 0;

hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_LSC0x1d,
   NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, &value);
3223}

3225int
3226ngbe_phy_check_overtemp(struct ngbe_hw *hw)
3227{
uint32_t ts_state;
int status = 0;

/* Check that the LASI temp alarm status was triggered */
ts_state = NGBE_READ_REG(hw, NGBE_TS_ALARM_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10318
)));

if (ts_state & NGBE_TS_ALARM_ST_ALARM0x00000001)
status = 1;

return status;
3238}

3240void
3241ngbe_phy_get_advertised_pause(struct ngbe_hw *hw, uint8_t *pause_bit)
3242{
uint16_t value;

hw->phy.ops.read_reg(hw, 4, 0, &value);
*pause_bit = (uint8_t)((value >> 10) & 0x3);
3247}

3249void
3250ngbe_phy_get_lp_advertised_pause(struct ngbe_hw *hw, uint8_t *pause_bit)
3251{
uint16_t value;

hw->phy.ops.read_reg(hw, NGBE_MDIO_AUTO_NEG_LSC0x1d,
   NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43, &value);
hw->phy.ops.read_reg(hw, MII_BMSR0x01, 0, &value);
value = (value & BMSR_ACOMP0x0020) ? 1 : 0;

/* If AN complete then check lp adv pause */
hw->phy.ops.read_reg(hw, MII_ANLPAR0x05, 0, &value);
*pause_bit = (uint8_t)((value >> 10) & 0x3);
3262}

3264int
3265ngbe_phy_identify(struct ngbe_softc *sc)
3266{
struct ngbe_hw *hw = &sc->hw;
int error;

switch(hw->phy.type) {
case ngbe_phy_internal:
error = ngbe_check_internal_phy_id(sc);
break;
default:
error = ENOTSUP91;
}

return error;
3279}

3281int
3282ngbe_phy_init(struct ngbe_softc *sc)
3283{
struct ngbe_hw *hw = &sc->hw;
uint16_t value;
uint8_t lan_id = hw->bus.lan_id;
int error;

/* Set fwsw semaphore mask for phy first */
if (!hw->phy.phy_semaphore_mask)
hw->phy.phy_semaphore_mask = NGBE_MNG_SWFW_SYNC_SW_PHY0x0001;

/* Init phy.addr according to HW design */
hw->phy.addr = 0;

/* Identify the PHY or SFP module */
error = hw->phy.ops.identify(sc);
if (error == ENOTSUP91)
return error;

/* Enable interrupts, only link status change and an done is allowed */
if (hw->phy.type == ngbe_phy_internal) {
value = NGBE_INTPHY_INT_LSC0x0010 | NGBE_INTPHY_INT_ANC0x0008;
hw->phy.ops.write_reg(hw, 0x12, 0xa42, value);
sc->gphy_efuse[0] =
    ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8);
sc->gphy_efuse[1] =
    ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8 + 4);
}

return error;
3312}

3314void
3315ngbe_phy_led_ctrl(struct ngbe_softc *sc)
3316{
struct ngbe_hw *hw = &sc->hw;
uint16_t value;

if (sc->led_conf != -1)
value = sc->led_conf & 0xffff;
else
value = 0x205b;
hw->phy.ops.write_reg(hw, 16, 0xd04, value);
hw->phy.ops.write_reg(hw, 17, 0xd04, 0);

hw->phy.ops.read_reg(hw, 18, 0xd04, &value);
if (sc->led_conf != -1) {
value &= ~0x73;
value |= sc->led_conf >> 16;
} else {
value &= 0xfffc;
/* Act led blinking mode set to 60ms */
value |= 0x2;
}
hw->phy.ops.write_reg(hw, 18, 0xd04, value);
3337}

3339int
3340ngbe_phy_led_oem_chk(struct ngbe_softc *sc, uint32_t *data)
3341{
struct ngbe_hw *hw = &sc->hw;
struct ngbe_hic_read_shadow_ram buffer;
uint32_t tmp;
int status;

buffer.hdr.req.cmd = FW_PHY_LED_CONF0xf1;
buffer.hdr.req.buf_lenh = 0;
buffer.hdr.req.buf_lenl = 0;
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM0xff;

/* Convert offset from words to bytes */
buffer.address = 0;
/* One word */
buffer.length = 0;

status = ngbe_host_interface_command(sc, (uint32_t *)&buffer,
   sizeof(buffer), NGBE_HI_COMMAND_TIMEOUT5000, 0);
if (status)
return status;

if (ngbe_check_mng_access(hw)) {
tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 1)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((1) << 2)))));
if (tmp == NGBE_CHECKSUM_CAP_ST_PASS0x80658383) {
	tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 2)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x1e100
 + ((2) << 2)))));
	*data = tmp;
	status = 0;
} else if (tmp == NGBE_CHECKSUM_CAP_ST_FAIL0x70657376) {
	*data = tmp;
	status = EINVAL22;
} else
	status = EINVAL22;
} else {
status = EINVAL22;
return status;
}

return status;
3379}

3381int
3382ngbe_phy_read_reg(struct ngbe_hw *hw, uint32_t off, uint32_t page,
  uint16_t *data)
3384{
*data = 0;

if (!((page == NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43) &&
   ((off == NGBE_MDIO_AUTO_NEG_STATUS0x1a) ||
   (off == NGBE_MDIO_AUTO_NEG_LSC0x1d)))) {
NGBE_WRITE_REG(hw,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)))
    NGBE_PHY_CONFIG(NGBE_INTERNAL_PHY_PAGE_SELECT_OFFSET),((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)))
    page)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)));
}
*data = NGBE_READ_REG(hw, NGBE_PHY_CONFIG(off))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((off) * 4))))) & 0xffff;

return 0;
3397}

3399int
3400ngbe_phy_write_reg(struct ngbe_hw *hw, uint32_t off, uint32_t page,
  uint16_t data)
3402{
if (!((page == NGBE_INTERNAL_PHY_PAGE_OFFSET0xa43) &&
   ((off == NGBE_MDIO_AUTO_NEG_STATUS0x1a) ||
   (off == NGBE_MDIO_AUTO_NEG_LSC0x1d)))) {
NGBE_WRITE_REG(hw,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)))
    NGBE_PHY_CONFIG(NGBE_INTERNAL_PHY_PAGE_SELECT_OFFSET),((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)))
    page)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((31) * 4))), (page)));
}
NGBE_WRITE_REG(hw, NGBE_PHY_CONFIG(off), data)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x14000
 + ((off) * 4))), (data)));

return 0;
3413}

3415int
3416ngbe_phy_reset(struct ngbe_softc *sc)
3417{
struct ngbe_hw *hw = &sc->hw;
uint16_t value;
int i, status;

/* only support internal phy */
if (hw->phy.type != ngbe_phy_internal) {
printf("%s: operation not supported\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return EINVAL22;
}

/* Don't reset PHY if it's shut down due to overtemp. */
if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw) != 0) {
printf("%s: overtemp! skip phy reset\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return EINVAL22;
}

/* Blocked by MNG FW so bail */
status = ngbe_check_reset_blocked(sc);
if (status)
return status;

value = NGBE_MDI_PHY_RESET0x8000;
status = hw->phy.ops.write_reg(hw, 0, 0, value);
for (i = 0; i < NGBE_PHY_RST_WAIT_PERIOD50; i++) {
status = hw->phy.ops.read_reg(hw, 0, 0, &value);
if (!(value & NGBE_MDI_PHY_RESET0x8000))
	break;
msec_delay(1)(*delay_func)(1000 * (1));
}

if (i == NGBE_PHY_RST_WAIT_PERIOD50) {
printf("%s: phy mode reset did not complete\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ETIMEDOUT60;
}

return status;
3454}

3456int
3457ngbe_phy_set_pause_advertisement(struct ngbe_hw *hw, uint16_t pause_bit)
3458{
uint16_t value;
int status;

status = hw->phy.ops.read_reg(hw, MII_ANAR0x04, 0, &value);
value &= ~0xc00;
value |= pause_bit;
status = hw->phy.ops.write_reg(hw, MII_ANAR0x04, 0, value);
return status;
3467}

3469int
3470ngbe_phy_setup(struct ngbe_softc *sc)
3471{
struct ngbe_hw *hw = &sc->hw;
uint16_t value = 0;
int i;

for (i = 0; i < 15; i++) {
if (!NGBE_READ_REG_MASK(hw, NGBE_MIS_ST0x10028,
    NGBE_MIS_ST_GPHY_IN_RST(hw->bus.lan_id)(0x00000200 << (hw->bus.lan_id))))
	break;
msec_delay(1)(*delay_func)(1000 * (1));
}
if (i == 15) {
printf("%s: gphy reset exceeds maximum time\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ETIMEDOUT60;
}

ngbe_gphy_efuse_calibration(sc);
hw->phy.ops.write_reg(hw, 20, 0xa46, 2);
ngbe_gphy_wait_mdio_access_on(hw);

for (i = 0; i < 100; i++) {
hw->phy.ops.read_reg(hw, 16, 0xa42, &value);
if ((value & 0x7) == 3)
	break;
DELAY(1000)(*delay_func)(1000);
}
if (i == 100) {
printf("%s: phy reset exceeds maximum time\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ETIMEDOUT60;
}

return 0;
3503}

3505int
3506ngbe_phy_setup_link(struct ngbe_softc *sc, uint32_t speed, int need_restart)
3507{
struct ngbe_hw *hw = &sc->hw;
uint16_t value = 0;
int status;

if (!hw->mac.autoneg) {
status = hw->phy.ops.reset(sc);
if (status) {
	printf("%s: phy reset failed\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return status;
}

switch (speed) {
case NGBE_LINK_SPEED_1GB_FULL2:
	value = NGBE_MDI_PHY_SPEED_SELECT10x0040;
	break;
case NGBE_LINK_SPEED_100_FULL1:
     		value = NGBE_MDI_PHY_SPEED_SELECT00x2000;
	break;
case NGBE_LINK_SPEED_10_FULL8:
	value = 0;
	break;
default:
	value = NGBE_MDI_PHY_SPEED_SELECT00x2000 |
	    NGBE_MDI_PHY_SPEED_SELECT10x0040;
	printf("%s: unknown speed = 0x%x\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), speed);
	break;
}
/* duplex full */
value |= NGBE_MDI_PHY_DUPLEX0x0100;
hw->phy.ops.write_reg(hw, 0, 0, value);

goto skip_an;
}

/* Disable 10/100M Half Duplex */
hw->phy.ops.read_reg(hw, 4, 0, &value);
value &= 0xff5f;
hw->phy.ops.write_reg(hw, 4, 0, value);

/* Set advertise enable according to input speed */
hw->phy.ops.read_reg(hw, 9, 0, &value);
if (!(speed & NGBE_LINK_SPEED_1GB_FULL2))
value &= 0xfdff;
else 
value |= 0x200;
hw->phy.ops.write_reg(hw, 9, 0, value);

hw->phy.ops.read_reg(hw, 4, 0, &value);
if (!(speed & NGBE_LINK_SPEED_100_FULL1))
value &= 0xfeff;
else
value |= 0x100;
hw->phy.ops.write_reg(hw, 4, 0, value);

hw->phy.ops.read_reg(hw, 4, 0, &value);
if (!(speed & NGBE_LINK_SPEED_10_FULL8))
value &= 0xffbf;
else
value |= 0x40;
hw->phy.ops.write_reg(hw, 4, 0, value);

/* Restart AN and wait AN done interrupt */
value = NGBE_MDI_PHY_RESTART_AN0x0200 | NGBE_MDI_PHY_ANE0x1000;
hw->phy.ops.write_reg(hw, 0, 0, value);

3574skip_an:
hw->phy.ops.phy_led_ctrl(sc);
hw->phy.ops.check_event(sc);

return 0;
3579}

3581uint16_t
3582ngbe_read_pci_cfg_word(struct ngbe_softc *sc, uint32_t reg)
3583{
struct ngbe_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
uint32_t value;
int high = 0;

if (reg & 0x2) {
high = 1;
reg &= ~0x2;
}
value = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);

if (high)
value >>= 16;

return (value & 0xffff);
3599}

3601void
3602ngbe_release_eeprom_semaphore(struct ngbe_hw *hw)
3603{
if (ngbe_check_mng_access(hw)) {
NGBE_WRITE_REG_MASK(hw, NGBE_MIS_SWSM0x1002c, NGBE_MIS_SWSM_SMBI1, 0);
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));
}
3608}

3610int
3611ngbe_acquire_swfw_sync(struct ngbe_softc *sc, uint32_t mask)
3612{
struct ngbe_hw *hw = &sc->hw;
uint32_t gssr = 0;
uint32_t swmask = mask;
uint32_t fwmask = mask << 16;
int i, timeout = 200;

for (i = 0; i < timeout; i++) {
/*
 * SW NVM semaphore bit is used for access to all
 * SW_FW_SYNC bits (not just NVM)
 */
if (ngbe_get_eeprom_semaphore(sc))
	return 1;
if (ngbe_check_mng_access(hw)) {
	gssr = NGBE_READ_REG(hw, NGBE_MNG_SWFW_SYNC)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1e008
)));
	if (!(gssr & (fwmask | swmask))) {
		gssr |= swmask;
		NGBE_WRITE_REG(hw, NGBE_MNG_SWFW_SYNC, gssr)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1e008
), (gssr)));
		ngbe_release_eeprom_semaphore(hw);
		return 0;
	} else {
		/* Resource is currently in use by FW or SW */
		ngbe_release_eeprom_semaphore(hw);
		msec_delay(5)(*delay_func)(1000 * (5));
	}
}
}

printf("%s: semaphore failed\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));

/* If time expired clear the bits holding the lock and retry */
if (gssr & (fwmask | swmask))
ngbe_release_swfw_sync(sc, gssr & (fwmask | swmask));

msec_delay(5)(*delay_func)(1000 * (5));
return 1;
3649}

3651void
3652ngbe_release_swfw_sync(struct ngbe_softc *sc, uint32_t mask)
3653{
struct ngbe_hw *hw = &sc->hw;

ngbe_get_eeprom_semaphore(sc);
if (ngbe_check_mng_access(hw))
NGBE_WRITE_REG_MASK(hw, NGBE_MNG_SWFW_SYNC0x1e008, mask, 0);

ngbe_release_eeprom_semaphore(hw);
3661}

3663void
3664ngbe_reset(struct ngbe_softc *sc)
3665{
struct ngbe_hw *hw = &sc->hw;
int error;

error = hw->mac.ops.init_hw(sc);
switch (error) {
case 0:
break;
default:
printf("%s: hardware error\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
break;
}
3677}

3679int
3680ngbe_reset_hw(struct ngbe_softc *sc)
3681{
struct ngbe_hw *hw = &sc->hw;
struct ngbe_mac_info *mac = &hw->mac;
uint32_t i, reset_status, rst_delay;
uint32_t reset = 0;
int status = 0;

status = hw->mac.ops.stop_adapter(sc);
if (status)
goto reset_hw_out;

/* Identify PHY and related function pointers */
if (!((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080)) {
status = hw->phy.ops.init(sc);
if (status)
	goto reset_hw_out;
}

if (ngbe_get_media_type(hw) == ngbe_media_type_copper) {
mac->ops.setup_link = ngbe_setup_copper_link;
mac->ops.get_link_capabilities =
    ngbe_get_copper_link_capabilities;
}

/*
* Issue global reset to the MAC.  Needs to be SW reset if link is up.
* If link reset is used when link is up, it might reset the PHY when
* mng is using it.  If link is down or the flag to force full link
* reset is set, then perform link reset.
*/
if (hw->force_full_reset) {
	rst_delay = (NGBE_READ_REG(hw, NGBE_MIS_RST_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10030
))) &
    NGBE_MIS_RST_ST_RST_INIT0x0000ff00) >> NGBE_MIS_RST_ST_RST_INI_SHIFT8;
if (hw->reset_type == NGBE_SW_RESET) {
	for (i = 0; i < rst_delay + 20; i++) {
		reset_status =
		    NGBE_READ_REG(hw, NGBE_MIS_RST_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10030
)));
		if (!(reset_status &
		    NGBE_MIS_RST_ST_DEV_RST_ST_MASK0x00180000))
			break;
		msec_delay(100)(*delay_func)(1000 * (100));
	}
	
	if (reset_status & NGBE_MIS_RST_ST_DEV_RST_ST_MASK0x00180000) {
		status = ETIMEDOUT60;
		printf("%s: software reset polling failed to "
		    "complete\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
		goto reset_hw_out;
	}
	status = ngbe_check_flash_load(sc,
	    NGBE_SPI_ILDR_STATUS_SW_RESET0x00000800);
	if (status)
		goto reset_hw_out;
} else if (hw->reset_type == NGBE_GLOBAL_RESET) {
	msec_delay(100 * rst_delay + 2000)(*delay_func)(1000 * (100 * rst_delay + 2000));
}
} else {
if (hw->bus.lan_id == 0)
	reset = NGBE_MIS_RST_LAN0_RST0x00000002;
else if (hw->bus.lan_id == 1)
	reset = NGBE_MIS_RST_LAN1_RST0x00000004;
else if (hw->bus.lan_id == 2)
	reset = NGBE_MIS_RST_LAN2_RST0x00000008;
else if (hw->bus.lan_id == 3)
	reset = NGBE_MIS_RST_LAN3_RST0x00000010;

NGBE_WRITE_REG(hw, NGBE_MIS_RST,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1000c
), (reset | ((((struct ngbe_osdep *)(hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(hw)->back)->os_memh
), (0x1000c))))))
    reset | NGBE_READ_REG(hw, NGBE_MIS_RST))((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1000c
), (reset | ((((struct ngbe_osdep *)(hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(hw)->back)->os_memh
), (0x1000c))))));
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));
msec_delay(15)(*delay_func)(1000 * (15));
}

ngbe_reset_misc(hw);

/* Store the permanent mac address */
hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);

/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table.  Also reset num_rar_entries to 32,
* since we modify this value when programming the SAN MAC address.
*/
hw->mac.num_rar_entries = NGBE_SP_RAR_ENTRIES32;
hw->mac.ops.init_rx_addrs(sc);

3766reset_hw_out:
return status;
3768}

3770void
3771ngbe_reset_misc(struct ngbe_hw *hw)
3772{
int i;

/* Receive packets of size > 2048 */
NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_CFG0x11004, NGBE_MAC_RX_CFG_JE0x00000100,
   NGBE_MAC_RX_CFG_JE0x00000100);

/* Clear counters on read */
NGBE_WRITE_REG_MASK(hw, NGBE_MMC_CONTROL0x11800, NGBE_MMC_CONTROL_RSTONRD0x4,
   NGBE_MMC_CONTROL_RSTONRD0x4);

NGBE_WRITE_REG_MASK(hw, NGBE_MAC_RX_FLOW_CTRL0x11090,
   NGBE_MAC_RX_FLOW_CTRL_RFE0x00000001, NGBE_MAC_RX_FLOW_CTRL_RFE0x00000001);

NGBE_WRITE_REG(hw, NGBE_MAC_PKT_FLT, NGBE_MAC_PKT_FLT_PR)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11008
), (0x00000001)));

NGBE_WRITE_REG_MASK(hw, NGBE_MIS_RST_ST0x10030, NGBE_MIS_RST_ST_RST_INIT0x0000ff00,
   0x1e00);

/* errata 4: initialize mng flex tbl and wakeup flex tbl */
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_SEL, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1582c
), (0)));
for (i = 0; i < 16; i++) {
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_DW_L(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15a00
 + ((i) * 16))), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_DW_H(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15a04
 + ((i) * 16))), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_MNG_FLEX_MSK(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15a08
 + ((i) * 16))), (0)));
}
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_SEL, 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15b8c
), (0)));
for (i = 0; i < 16; i++) {
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_DW_L(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15c00
 + ((i) * 16))), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_DW_H(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15c04
 + ((i) * 16))), (0)));
NGBE_WRITE_REG(hw, NGBE_PSR_LAN_FLEX_MSK(i), 0)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x15c08
 + ((i) * 16))), (0)));
}

/* Set pause frame dst mac addr */
NGBE_WRITE_REG(hw, NGBE_RDB_PFCMACDAL, 0xc2000001)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19210
), (0xc2000001)));
NGBE_WRITE_REG(hw, NGBE_RDB_PFCMACDAH, 0x0180)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19214
), (0x0180)));

NGBE_WRITE_REG(hw, NGBE_MDIO_CLAUSE_SELECT, 0xf)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x11220
), (0xf)));

ngbe_init_thermal_sensor_thresh(hw);
3812}

3814int
3815ngbe_set_fw_drv_ver(struct ngbe_softc *sc, uint8_t maj, uint8_t min,
  uint8_t build, uint8_t sub)
3817{
struct ngbe_hw *hw = &sc->hw;
struct ngbe_hic_drv_info fw_cmd;
int i, error = 0;

fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO0xdd;
fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN0x5;
fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED0x0;
fw_cmd.port_num = (uint8_t)hw->bus.lan_id;
fw_cmd.ver_maj = maj;
fw_cmd.ver_min = min;
fw_cmd.ver_build = build;
fw_cmd.ver_sub = sub;
fw_cmd.hdr.checksum = 0;
fw_cmd.hdr.checksum = ngbe_calculate_checksum((uint8_t *)&fw_cmd,
   (FW_CEM_HDR_LEN0x4 + fw_cmd.hdr.buf_len));
fw_cmd.pad = 0;
fw_cmd.pad2 = 0;

DELAY(5000)(*delay_func)(5000);
for (i = 0; i <= FW_CEM_MAX_RETRIES3; i++) {
error = ngbe_host_interface_command(sc, (uint32_t *)&fw_cmd,
    sizeof(fw_cmd), NGBE_HI_COMMAND_TIMEOUT5000, 1);
if (error)
	continue;

if (fw_cmd.hdr.cmd_or_resp.ret_status ==
    FW_CEM_RESP_STATUS_SUCCESS0x1)
	error = 0;
else
	error = EINVAL22;
break;
}

return error;
3852}

3854void
3855ngbe_set_ivar(struct ngbe_softc *sc, uint16_t entry, uint16_t vector, int8_t
3856type)
3857{
struct ngbe_hw *hw = &sc->hw;
uint32_t ivar, index;

vector |= NGBE_PX_IVAR_ALLOC_VAL0x80;

if (type == -1) {
/* other causes */
index = 0;
ivar = NGBE_READ_REG(hw, NGBE_PX_MISC_IVAR)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x004fc
)));
ivar &= ~((uint32_t)0xff << index);
ivar |= ((uint32_t)vector << index);
NGBE_WRITE_REG(hw, NGBE_PX_MISC_IVAR, ivar)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x004fc
), (ivar)));
} else {
/* Tx or Rx causes */
index = ((16 * (entry & 1)) + (8 * type));
ivar = NGBE_READ_REG(hw, NGBE_PX_IVAR(entry >> 1))((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x00500
 + (entry >> 1) * 4))));
ivar &= ~((uint32_t)0xff << index);
ivar |= ((uint32_t)vector << index);
NGBE_WRITE_REG(hw, NGBE_PX_IVAR(entry >> 1), ivar)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x00500
 + (entry >> 1) * 4)), (ivar)));
}
3878}

3880void
3881ngbe_set_lan_id_multi_port_pcie(struct ngbe_hw *hw)
3882{
struct ngbe_bus_info *bus = &hw->bus;
uint32_t reg = 0;

reg = NGBE_READ_REG(hw, NGBE_CFG_PORT_ST)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x14404
)));
bus->lan_id = NGBE_CFG_PORT_ST_LAN_ID(reg)((0x00000300 & (reg)) >> 8);
3888}

3890void
3891ngbe_set_mta(struct ngbe_hw *hw, uint8_t *mc_addr)
3892{
uint32_t vector, vector_bit, vector_reg;

hw->addr_ctrl.mta_in_use++;

vector = ngbe_mta_vector(hw, mc_addr);

/*
* The MTA is a register array of 128 32-bit registers. It is treated
* like an array of 4096 bits.  We want to set bit
* BitArray[vector_value]. So we figure out what register the bit is
* in, read it, OR in the new bit, then write back the new value.  The
* register is determined by the upper 7 bits of the vector value and
* the bit within that register are determined by the lower 5 bits of
* the value.
*/
vector_reg = (vector >> 5) & 0x7f;
vector_bit = vector & 0x1f;
hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
3911}

3913void
3914ngbe_set_pci_config_data(struct ngbe_hw *hw, uint16_t link_status)
3915{
if (hw->bus.type == ngbe_bus_type_unknown)
hw->bus.type = ngbe_bus_type_pci_express;

switch (link_status & NGBE_PCI_LINK_WIDTH0x3f0) {
case NGBE_PCI_LINK_WIDTH_10x10:
hw->bus.width = ngbe_bus_width_pcie_x1;
break;
case NGBE_PCI_LINK_WIDTH_20x20:
hw->bus.width = ngbe_bus_width_pcie_x2;
break;
case NGBE_PCI_LINK_WIDTH_40x40:
hw->bus.width = ngbe_bus_width_pcie_x4;
break;
case NGBE_PCI_LINK_WIDTH_80x80:
hw->bus.width = ngbe_bus_width_pcie_x8;
break;
default:
hw->bus.width = ngbe_bus_width_unknown;
break;
}

switch (link_status & NGBE_PCI_LINK_SPEED0xf) {
case NGBE_PCI_LINK_SPEED_25000x1:
hw->bus.speed = ngbe_bus_speed_2500;
break;
case NGBE_PCI_LINK_SPEED_50000x2:
hw->bus.speed = ngbe_bus_speed_5000;
break;
case NGBE_PCI_LINK_SPEED_80000x3:
hw->bus.speed = ngbe_bus_speed_8000;
break;
default:
hw->bus.speed = ngbe_bus_speed_unknown;
break;
}
3951}

3953int
3954ngbe_set_rar(struct ngbe_softc *sc, uint32_t index, uint8_t *addr,
  uint64_t pools, uint32_t enable_addr)
3956{
struct ngbe_hw *hw = &sc->hw;
uint32_t rar_entries = hw->mac.num_rar_entries;
uint32_t rar_low, rar_high;

/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
printf("%s: RAR index %d is out of range\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), index);
return EINVAL22;
}

/* Select the MAC address */
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_IDX, index)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16210
), (index)));

/* Setup VMDq pool mapping */
NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_VM, pools & 0xffffffff)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16208
), (pools & 0xffffffff)));

/*
* HW expects these in little endian so we reverse the byte
* order from network order (big endian) to little endian
*
* Some parts put the VMDq setting in the extra RAH bits,
* so save everything except the lower 16 bits that hold part
* of the address and the address valid bit.
*/
rar_low = ((uint32_t)addr[5] | ((uint32_t)addr[4] << 8) |
   ((uint32_t)addr[3] << 16) | ((uint32_t)addr[2] << 24));
rar_high = ((uint32_t)addr[1] | ((uint32_t)addr[0] << 8));
if (enable_addr != 0)
rar_high |= NGBE_PSR_MAC_SWC_AD_H_AV0x80000000;

NGBE_WRITE_REG(hw, NGBE_PSR_MAC_SWC_AD_L, rar_low)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x16200
), (rar_low)));
NGBE_WRITE_REG_MASK(hw, NGBE_PSR_MAC_SWC_AD_H0x16204,
   (NGBE_PSR_MAC_SWC_AD_H_AD(~0)(((~0) & 0xffff)) | NGBE_PSR_MAC_SWC_AD_H_ADTYPE(~0)(((~0) & 0x1) << 30) |
   NGBE_PSR_MAC_SWC_AD_H_AV0x80000000), rar_high);

return 0;
3994}

3996void
3997ngbe_set_rx_drop_en(struct ngbe_softc *sc)
3998{
uint32_t srrctl;
int i;

if ((sc->sc_nqueues > 1) &&
   !(sc->hw.fc.current_mode & ngbe_fc_tx_pause)) {
for (i = 0; i < sc->sc_nqueues; i++) {
	srrctl = NGBE_READ_REG(&sc->hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01010 + ((i) * 0x40)))));
	srrctl |= NGBE_PX_RR_CFG_DROP_EN0x40000000;
	NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_CFG(i), srrctl)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01010 + ((i) * 0x40))), (srrctl)));
}
	
} else {
for (i = 0; i < sc->sc_nqueues; i++) {
	srrctl = NGBE_READ_REG(&sc->hw, NGBE_PX_RR_CFG(i))((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01010 + ((i) * 0x40)))));
	srrctl &= ~NGBE_PX_RR_CFG_DROP_EN0x40000000;
	NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_CFG(i), srrctl)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01010 + ((i) * 0x40))), (srrctl)));
}
}
4017}

4019void
4020ngbe_set_rxpba(struct ngbe_hw *hw, int num_pb, uint32_t headroom, int strategy)
4021{
uint32_t pbsize = hw->mac.rx_pb_size;
uint32_t txpktsize, txpbthresh, rxpktsize = 0;

/* Reserve headroom */
pbsize -= headroom;

if (!num_pb)
num_pb = 1;

/*
* Divide remaining packet buffer space amongst the number of packet
* buffers requested using supplied strategy.
*/
switch (strategy) {
case PBA_STRATEGY_EQUAL0:
rxpktsize = (pbsize / num_pb) << NGBE_RDB_PB_SZ_SHIFT10;
NGBE_WRITE_REG(hw, NGBE_RDB_PB_SZ, rxpktsize)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x19020
), (rxpktsize)));
break;
default:
break;
}

/* Only support an equally distributed Tx packet buffer strategy. */
txpktsize = NGBE_TDB_PB_SZ_MAX0x00005000 / num_pb;
txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX0xa;

NGBE_WRITE_REG(hw, NGBE_TDB_PB_SZ, txpktsize)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x1cc00
), (txpktsize)));
NGBE_WRITE_REG(hw, NGBE_TDM_PB_THRE, txpbthresh)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x18020
), (txpbthresh)));
4050}

4052int
4053ngbe_setup_copper_link(struct ngbe_softc *sc, uint32_t speed, int need_restart)
4054{
struct ngbe_hw *hw = &sc->hw;
int status = 0;

/* Setup the PHY according to input speed */
if (!((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080))
status = hw->phy.ops.setup_link(sc, speed, need_restart);

return status;
4063}

4065int
4066ngbe_setup_fc(struct ngbe_softc *sc)
4067{
struct ngbe_hw *hw = &sc->hw;
uint16_t pcap_backplane = 0;
int error = 0;

/* Validate the requested mode */
if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
printf("%s: ngbe_fc_rx_pause not valid in strict IEEE mode\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = EINVAL22;
goto out;
}

/*
* Gig parts do not have a word in the EEPROM to determine the
* default flow control setting, so we explicitly set it to full.
*/
if (hw->fc.requested_mode == ngbe_fc_default)
hw->fc.requested_mode = ngbe_fc_full;

/*
* The possible values of fc.requested_mode are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
*    but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
*    we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
switch (hw->fc.requested_mode) {
case ngbe_fc_none:
/* Flow control completely disabled by software override. */
break;
case ngbe_fc_tx_pause:
/* 
 * Tx Flow control is enabled, and Rx Flow control is
 * disabled by software override.
 */
pcap_backplane |= NGBE_SR_AN_MMD_ADV_REG1_PAUSE_ASM0x800;
break;
case ngbe_fc_rx_pause:
/*
 * Rx Flow control is enabled and Tx Flow control is
 * disabled by software override. Since there really
 * isn't a way to advertise that we are capable of RX
 * Pause ONLY, we will advertise that we support both
 * symmetric and asymmetric Rx PAUSE, as such we fall
 * through to the fc_full statement.  Later, we will
 * disable the adapter's ability to send PAUSE frames.
 */
case ngbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
pcap_backplane |= NGBE_SR_AN_MMD_ADV_REG1_PAUSE_SYM0x400 |
    NGBE_SR_AN_MMD_ADV_REG1_PAUSE_ASM0x800;
break;
default:
printf("%s: flow control param set incorrectly\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = EINVAL22;
goto out;
}

/* AUTOC restart handles negotiation of 1G on backplane and copper. */
if ((hw->phy.media_type == ngbe_media_type_copper) &&
   !((hw->subsystem_device_id & OEM_MASK0x00ff) == RGMII_FPGA0x0080))
error = hw->phy.ops.set_adv_pause(hw, pcap_backplane);
4133out:
return error;
4135}

4137void
4138ngbe_setup_gpie(struct ngbe_hw *hw)
4139{
uint32_t gpie;

gpie = NGBE_PX_GPIE_MODEL0x00000001;

/*
* use EIAM to auto-mask when MSI-X interrupt is asserted
* this saves a register write for every interrupt.
*/
NGBE_WRITE_REG(hw, NGBE_PX_GPIE, gpie)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x00118
), (gpie)));
4149}

4151void
4152ngbe_setup_isb(struct ngbe_softc *sc)
4153{
uint64_t idba = sc->isbdma.dma_map->dm_segs[0].ds_addr;

/* Set ISB address */
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ISB_ADDR_L,((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00160), ((idba & 0x00000000ffffffffULL
))))
   (idba & 0x00000000ffffffffULL))((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00160), ((idba & 0x00000000ffffffffULL
))));
NGBE_WRITE_REG(&sc->hw, NGBE_PX_ISB_ADDR_H, (idba >> 32))((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), (0x00164), ((idba >> 32))));
4160}

4162void
4163ngbe_setup_psrtype(struct ngbe_hw *hw)
4164{
uint32_t psrtype;

/* PSRTYPE must be initialized in adapters */
psrtype = NGBE_RDB_PL_CFG_L4HDR0x2 | NGBE_RDB_PL_CFG_L3HDR0x4 |
   NGBE_RDB_PL_CFG_L2HDR0x8 | NGBE_RDB_PL_CFG_TUN_TUNHDR0x10 |
   NGBE_RDB_PL_CFG_TUN_OUTER_L2HDR0x20;

NGBE_WRITE_REG(hw, NGBE_RDB_PL_CFG(0), psrtype)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), ((0x19300
 + ((0) * 4))), (psrtype)));
4173}

4175void
4176ngbe_setup_vlan_hw_support(struct ngbe_softc *sc)
4177{
struct ngbe_hw *hw = &sc->hw;
int i;

for (i = 0; i < sc->sc_nqueues; i++) {
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    NGBE_PX_RR_CFG_VLAN0x80000000, NGBE_PX_RR_CFG_VLAN0x80000000);
}
4185}

4187int
4188ngbe_start_hw(struct ngbe_softc *sc)
4189{
struct ngbe_hw *hw = &sc->hw;
int error;

/* Set the media type */
hw->phy.media_type = hw->mac.ops.get_media_type(hw);

/* Clear the VLAN filter table */
hw->mac.ops.clear_vfta(hw);

/* Clear statistics registers */
hw->mac.ops.clear_hw_cntrs(hw);

NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));

/* Setup flow control */
error = hw->mac.ops.setup_fc(sc);

/* Clear adapter stopped flag */
hw->adapter_stopped = 0;

/* We need to run link autotry after the driver loads */
hw->mac.autotry_restart = 1;

return error;
4214}

4216int
4217ngbe_stop_adapter(struct ngbe_softc *sc)
4218{
struct ngbe_hw *hw = &sc->hw;
int i;

/*
* Set the adapter_stopped flag so other driver functions stop touching
* the hardware.
*/
hw->adapter_stopped = 1;

/* Disable the receive unit. */
hw->mac.ops.disable_rx(hw);

/* Clear any pending interrupts, flush previous writes. */
NGBE_WRITE_REG(hw, NGBE_PX_MISC_IC, 0xffffffff)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x00100
), (0xffffffff)));

NGBE_WRITE_REG(hw, NGBE_BME_CTL, 0x3)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x12020
), (0x3)));

/* Disable the transmit unit.  Each queue must be disabled. */
for (i = 0; i < hw->mac.max_tx_queues; i++) {
NGBE_WRITE_REG_MASK(hw, NGBE_PX_TR_CFG(i)(0x03010 + ((i) * 0x40)),
    NGBE_PX_TR_CFG_SWFLSH0x04000000 | NGBE_PX_TR_CFG_ENABLE(1),
    NGBE_PX_TR_CFG_SWFLSH0x04000000);
}

/* Disable the receive unit by stopping each queue */
for (i = 0; i < hw->mac.max_rx_queues; i++) {
NGBE_WRITE_REG_MASK(hw, NGBE_PX_RR_CFG(i)(0x01010 + ((i) * 0x40)),
    NGBE_PX_RR_CFG_RR_EN0x00000001, 0);
}

/* Flush all queues disables. */
NGBE_WRITE_FLUSH(hw)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x10000
)));
msec_delay(2)(*delay_func)(1000 * (2));

return ngbe_disable_pcie_master(sc);
4254}

4256void
4257ngbe_rx_checksum(uint32_t staterr, struct mbuf *m)
4258{
if (staterr & NGBE_RXD_STAT_IPCS0x00000100) {
if (!(staterr & NGBE_RXD_ERR_IPE0x80000000))
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK0x0008;
else
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = 0;
}
if (staterr & NGBE_RXD_STAT_L4CS0x00000080) {
if (!(staterr & NGBE_RXD_ERR_TCPE0x40000000))
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |=
	    M_TCP_CSUM_IN_OK0x0020 | M_UDP_CSUM_IN_OK0x0080;
}
4270}

4272void
4273ngbe_rxeof(struct rx_ring *rxr)
4274{
struct ngbe_softc *sc = rxr->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct mbuf *mp, *m;
struct ngbe_rx_buf *rxbuf, *nxbuf;
union ngbe_rx_desc *rxdesc;
uint32_t staterr = 0;
uint16_t len, vtag;
uint8_t eop = 0;
int i, nextp;

if (!ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40)))
return;

i = rxr->next_to_check;
while (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) > 0) {
uint32_t hash;
uint16_t hashtype;

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x02))
    i * sizeof(union ngbe_rx_desc), sizeof(union ngbe_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x02))
    BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x02));

rxdesc = &rxr->rx_base[i];
staterr = letoh32(rxdesc->wb.upper.status_error)((__uint32_t)(rxdesc->wb.upper.status_error));
if (!ISSET(staterr, NGBE_RXD_STAT_DD)((staterr) & (0x00000001))) {
	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01))
	    i * sizeof(union ngbe_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01))
	    sizeof(union ngbe_rx_desc), BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01));
	break;
}

/* Zero out the receive descriptors status. */
rxdesc->wb.upper.status_error = 0;
rxbuf = &rxr->rx_buffers[i];

/* Pull the mbuf off the ring. */
bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
    rxbuf->map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
));
bus_dmamap_unload(rxr->rxdma.dma_tag, rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map));

mp = rxbuf->buf;
len = letoh16(rxdesc->wb.upper.length)((__uint16_t)(rxdesc->wb.upper.length));
vtag = letoh16(rxdesc->wb.upper.vlan)((__uint16_t)(rxdesc->wb.upper.vlan));
eop = ((staterr & NGBE_RXD_STAT_EOP0x00000002) != 0);
hash = letoh32(rxdesc->wb.lower.hi_dword.rss)((__uint32_t)(rxdesc->wb.lower.hi_dword.rss));
hashtype = le16toh(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info)((__uint16_t)(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info)) &
    NGBE_RXD_RSSTYPE_MASK0x0000000f;

if (staterr & NGBE_RXD_ERR_RXE0x20000000) {
	if (rxbuf->fmp) {
		m_freem(rxbuf->fmp);
		rxbuf->fmp = NULL((void *)0);
	}

	m_freem(mp);
	rxbuf->buf = NULL((void *)0);
	goto next_desc;
}

if (mp == NULL((void *)0)) {
	panic("%s: ngbe_rxeof: NULL mbuf in slot %d "
	    "(nrx %d, filled %d)", DEVNAME(sc)((sc)->sc_dev.dv_xname), i,
	    if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive), rxr->last_desc_filled);
}

if (!eop) {
	/*
	 * Figure out the next descriptor of this frame.
	 */
	nextp = i + 1;
	if (nextp == sc->num_rx_desc)
		nextp = 0;
	nxbuf = &rxr->rx_buffers[nextp];
	/* prefetch(nxbuf); */
}

mp->m_lenm_hdr.mh_len = len;

m = rxbuf->fmp;
rxbuf->buf = rxbuf->fmp = NULL((void *)0);

if (m != NULL((void *)0))
	m->m_pkthdrM_dat.MH.MH_pkthdr.len += mp->m_lenm_hdr.mh_len;
else {
	m = mp;
	m->m_pkthdrM_dat.MH.MH_pkthdr.len = mp->m_lenm_hdr.mh_len;
4362#if NVLAN1 > 0
	if (staterr & NGBE_RXD_STAT_VP0x00000020) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = vtag;
		m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
	}
4367#endif
}

/* Pass the head pointer on */
if (eop == 0) {
	nxbuf->fmp = m;
	m = NULL((void *)0);
	mp->m_nextm_hdr.mh_next = nxbuf->buf;
} else {
	ngbe_rx_checksum(staterr, m);

	if (hashtype != NGBE_RXD_RSSTYPE_NONE0x00000000) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.ph_flowid = hash;
		SET(m->m_pkthdr.csum_flags, M_FLOWID)((m->M_dat.MH.MH_pkthdr.csum_flags) |= (0x4000));
	}

	ml_enqueue(&ml, m);
}
4385next_desc:
if_rxr_put(&rxr->rx_ring, 1)do { (&rxr->rx_ring)->rxr_alive -= (1); } while (0);
bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01))
    i * sizeof(union ngbe_rx_desc), sizeof(union ngbe_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01))
    BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union ngbe_rx_desc)),
 (sizeof(union ngbe_rx_desc)), (0x01));

/* Advance our pointers to the next descriptor. */
if (++i == sc->num_rx_desc)
	i = 0;
}
rxr->next_to_check = i;

if (ifiq_input(rxr->ifiq, &ml))
if_rxr_livelocked(&rxr->rx_ring);

if (!(staterr & NGBE_RXD_STAT_DD0x00000001))
return;
4402}

4404void
4405ngbe_rxrefill(void *xrxr)
4406{
struct rx_ring *rxr = xrxr;
struct ngbe_softc *sc = rxr->sc;

if (ngbe_rxfill(rxr))
NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_WP(rxr->me),((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01008 + ((rxr->me) * 0x40))), (rxr->
last_desc_filled)))
    rxr->last_desc_filled)((((struct ngbe_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct ngbe_osdep *)(&sc->hw)->back
)->os_memh), ((0x01008 + ((rxr->me) * 0x40))), (rxr->
last_desc_filled)));
else if (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) == 0)
timeout_add(&rxr->rx_refill, 1);
4415}

4417int
4418ngbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *m, uint32_t *cmd_type_len,
  uint32_t *olinfo_status)
4420{
struct ngbe_tx_context_desc *txd;
struct ngbe_tx_buf *tx_buffer;
uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0;
int ctxd = txr->next_avail_desc;
int offload = 0;

/* Indicate the whole packet as payload when not doing TSO */
*olinfo_status |= m->m_pkthdrM_dat.MH.MH_pkthdr.len << NGBE_TXD_PAYLEN_SHIFT13;

4430#if NVLAN1 > 0
if (ISSET(m->m_flags, M_VLANTAG)((m->m_hdr.mh_flags) & (0x0020))) {
uint32_t vtag = m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag;
vlan_macip_lens |= (vtag << NGBE_TXD_VLAN_SHIFT16);
*cmd_type_len |= NGBE_TXD_VLE0x40000000;
offload |= 1;
}
4437#endif

if (!offload)
return 0;

txd = (struct ngbe_tx_context_desc *)&txr->tx_base[ctxd];
tx_buffer = &txr->tx_buffers[ctxd];

type_tucmd_mlhl |= NGBE_TXD_DTYP_CTXT0x00100000;

/* Now copy bits into descriptor */
txd->vlan_macip_lens = htole32(vlan_macip_lens)((__uint32_t)(vlan_macip_lens));
txd->type_tucmd_mlhl = htole32(type_tucmd_mlhl)((__uint32_t)(type_tucmd_mlhl));
txd->seqnum_seed = htole32(0)((__uint32_t)(0));
txd->mss_l4len_idx = htole32(0)((__uint32_t)(0));

tx_buffer->m_head = NULL((void *)0);
tx_buffer->eop_index = -1;

return 1;
4457}

4459void
4460ngbe_txeof(struct tx_ring *txr)
4461{
struct ngbe_softc *sc = txr->sc;
struct ifqueue *ifq = txr->ifq;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct ngbe_tx_buf *tx_buffer;
union ngbe_tx_desc *tx_desc;
unsigned int prod, cons, last;

if (!ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40)))
return;

prod = txr->next_avail_desc;
cons = txr->next_to_clean;

if (prod == cons)
return;

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x02))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x02));

for (;;) {
tx_buffer = &txr->tx_buffers[cons];
last = tx_buffer->eop_index;
tx_desc = (union ngbe_tx_desc *)&txr->tx_base[last];

if (!ISSET(tx_desc->wb.status, NGBE_TXD_STAT_DD)((tx_desc->wb.status) & (0x00000001)))
	break;

bus_dmamap_sync(txr->txdma.dma_tag, tx_buffer->map,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (tx_buffer->map), (0), (tx_buffer->map->dm_mapsize
), (0x08))
    0, tx_buffer->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (tx_buffer->map), (0), (tx_buffer->map->dm_mapsize
), (0x08));
bus_dmamap_unload(txr->txdma.dma_tag, tx_buffer->map)(*(txr->txdma.dma_tag)->_dmamap_unload)((txr->txdma.
dma_tag), (tx_buffer->map));
m_freem(tx_buffer->m_head);

tx_buffer->m_head = NULL((void *)0);
tx_buffer->eop_index = -1;

cons = last + 1;
if (cons == sc->num_tx_desc)
	cons = 0;
if (prod == cons) {
	/* All clean, turn off the timer */
	ifp->if_timer = 0;
	break;
}
}

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01))
   0, txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01));

txr->next_to_clean = cons;

if (ifq_is_oactive(ifq))
ifq_restart(ifq);
4514}

4516void
4517ngbe_update_mc_addr_list(struct ngbe_hw *hw, uint8_t *mc_addr_list,
  uint32_t mc_addr_count, ngbe_mc_addr_itr next, int clear)
4519{
uint32_t i, psrctl, vmdq;

/*
* Set the new number of MC addresses that we are being requested to
* use.
*/
hw->addr_ctrl.num_mc_addrs = mc_addr_count;
hw->addr_ctrl.mta_in_use = 0;

/* Clear mta_shadow */
if (clear)
memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow))__builtin_memset((&hw->mac.mta_shadow), (0), (sizeof(hw
->mac.mta_shadow)));

/* Update mta_shadow */
for (i = 0; i < mc_addr_count; i++)
	ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));

/* Enable mta */
for (i = 0; i < hw->mac.mcft_size; i++)
NGBE_WRITE_REG_ARRAY(hw, NGBE_PSR_MC_TBL(0), i,((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (((0x15200
 + ((0) * 4)) + ((i) << 2))), (hw->mac.mta_shadow[i]
)))
    hw->mac.mta_shadow[i])((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (((0x15200
 + ((0) * 4)) + ((i) << 2))), (hw->mac.mta_shadow[i]
)));

if (hw->addr_ctrl.mta_in_use > 0) {
psrctl = NGBE_READ_REG(hw, NGBE_PSR_CTL)((((struct ngbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
)));
psrctl &= ~(NGBE_PSR_CTL_MO0x00000060 | NGBE_PSR_CTL_MFE0x00000080);
psrctl |= NGBE_PSR_CTL_MFE0x00000080 |
    (hw->mac.mc_filter_type << NGBE_PSR_CTL_MO_SHIFT5);
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, psrctl)((((struct ngbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ngbe_osdep *)(hw)->back)->os_memh), (0x15000
), (psrctl)));
}
4549}

4551int
4552ngbe_validate_mac_addr(uint8_t *mac_addr)
4553{
uint32_t status = 0;

/* Make sure it is not a multicast address */
if (NGBE_IS_MULTICAST(mac_addr)(int)(((uint8_t *)(mac_addr))[0] & ((uint8_t)0x01)))
status = EINVAL22;
/* Not a broadcast address */
else if (NGBE_IS_BROADCAST(mac_addr)((((uint8_t *)(mac_addr))[0] == ((uint8_t)0xff)) && (
((uint8_t *)(mac_addr))[1] == ((uint8_t)0xff))))
status = EINVAL22;
/* Reject the zero address */
else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
   mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
status = EINVAL22;

return status;
4568}