/usr/src/sys/dev/pci/if

Bug Summary

File:	dev/pci/if_iwx.c
Warning:	line 765, column 6 Branch condition evaluates to a garbage value
Annotated Source Code

Press '?' to see keyboard shortcuts
Show analyzer invocation
clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_iwx.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/if_iwx.c
1/*	$OpenBSD: if_iwx.c,v 1.180 2023/12/30 16:55:44 stsp Exp $	*/

3/*
* Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
*   Author: Stefan Sperling <stsp@openbsd.org>
* Copyright (c) 2014 Fixup Software Ltd.
* Copyright (c) 2017, 2019, 2020 Stefan Sperling <stsp@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/

22/*-
* Based on BSD-licensed source modules in the Linux iwlwifi driver,
* which were used as the reference documentation for this implementation.
*
******************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license.  When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2017 Intel Deutschland GmbH
* Copyright(c) 2018 - 2019 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* BSD LICENSE
*
* Copyright(c) 2017 Intel Deutschland GmbH
* Copyright(c) 2018 - 2019 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
*  * Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*  * Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in
*    the documentation and/or other materials provided with the
*    distribution.
*  * Neither the name Intel Corporation nor the names of its
*    contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************
*/

80/*-
* Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/

96#include "bpfilter.h"

98#include <sys/param.h>
99#include <sys/conf.h>
100#include <sys/kernel.h>
101#include <sys/malloc.h>
102#include <sys/mbuf.h>
103#include <sys/mutex.h>
104#include <sys/proc.h>
105#include <sys/rwlock.h>
106#include <sys/socket.h>
107#include <sys/sockio.h>
108#include <sys/systm.h>
109#include <sys/endian.h>

111#include <sys/refcnt.h>
112#include <sys/task.h>
113#include <machine/bus.h>
114#include <machine/intr.h>

116#include <dev/pci/pcireg.h>
117#include <dev/pci/pcivar.h>
118#include <dev/pci/pcidevs.h>

120#if NBPFILTER1 > 0
121#include <net/bpf.h>
122#endif
123#include <net/if.h>
124#include <net/if_dl.h>
125#include <net/if_media.h>

127#include <netinet/in.h>
128#include <netinet/if_ether.h>

130#include <net80211/ieee80211_var.h>
131#include <net80211/ieee80211_radiotap.h>
132#include <net80211/ieee80211_priv.h> /* for SEQ_LT */
133#undef DPRINTF /* defined in ieee80211_priv.h */

135#define DEVNAME(_s)((_s)->sc_dev.dv_xname)	((_s)->sc_dev.dv_xname)

137#define IC2IFP(_ic_)(&(_ic_)->ic_ac.ac_if) (&(_ic_)->ic_ific_ac.ac_if)

139#define le16_to_cpup(_a_)(((__uint16_t)(*(const uint16_t *)(_a_)))) (le16toh(*(const uint16_t *)(_a_))((__uint16_t)(*(const uint16_t *)(_a_))))
140#define le32_to_cpup(_a_)(((__uint32_t)(*(const uint32_t *)(_a_)))) (le32toh(*(const uint32_t *)(_a_))((__uint32_t)(*(const uint32_t *)(_a_))))

142#ifdef IWX_DEBUG
143#define DPRINTF(x)do { ; } while (0)	do { if (iwx_debug > 0) printf x; } while (0)
144#define DPRINTFN(n, x)do { ; } while (0)	do { if (iwx_debug >= (n)) printf x; } while (0)
145int iwx_debug = 1;
146#else
147#define DPRINTF(x)do { ; } while (0)	do { ; } while (0)
148#define DPRINTFN(n, x)do { ; } while (0)	do { ; } while (0)
149#endif

151#include <dev/pci/if_iwxreg.h>
152#include <dev/pci/if_iwxvar.h>

154const uint8_t iwx_nvm_channels_8000[] = {
/* 2.4 GHz */
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
/* 5 GHz */
36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
149, 153, 157, 161, 165, 169, 173, 177, 181
161};

163static const uint8_t iwx_nvm_channels_uhb[] = {
/* 2.4 GHz */
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
/* 5 GHz */
36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
149, 153, 157, 161, 165, 169, 173, 177, 181,
/* 6-7 GHz */
1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
175};

177#define IWX_NUM_2GHZ_CHANNELS14	14
178#define IWX_NUM_5GHZ_CHANNELS37	37

180const struct iwx_rate {
uint16_t rate;
uint8_t plcp;
uint8_t ht_plcp;
184} iwx_rates[] = {
/* Legacy */		/* HT */
{   2,	IWX_RATE_1M_PLCP10,	IWX_RATE_HT_SISO_MCS_INV_PLCP0x20  },
{   4,	IWX_RATE_2M_PLCP20,	IWX_RATE_HT_SISO_MCS_INV_PLCP0x20 },
{  11,	IWX_RATE_5M_PLCP55,	IWX_RATE_HT_SISO_MCS_INV_PLCP0x20  },
{  22,	IWX_RATE_11M_PLCP110,	IWX_RATE_HT_SISO_MCS_INV_PLCP0x20 },
{  12,	IWX_RATE_6M_PLCP13,	IWX_RATE_HT_SISO_MCS_0_PLCP0 },
{  18,	IWX_RATE_9M_PLCP15,	IWX_RATE_HT_SISO_MCS_INV_PLCP0x20  },
{  24,	IWX_RATE_12M_PLCP5,	IWX_RATE_HT_SISO_MCS_1_PLCP1 },
{  26,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_8_PLCP0x8 },
{  36,	IWX_RATE_18M_PLCP7,	IWX_RATE_HT_SISO_MCS_2_PLCP2 },
{  48,	IWX_RATE_24M_PLCP9,	IWX_RATE_HT_SISO_MCS_3_PLCP3 },
{  52,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_9_PLCP0x9 },
{  72,	IWX_RATE_36M_PLCP11,	IWX_RATE_HT_SISO_MCS_4_PLCP4 },
{  78,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_10_PLCP0xA },
{  96,	IWX_RATE_48M_PLCP1,	IWX_RATE_HT_SISO_MCS_5_PLCP5 },
{ 104,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_11_PLCP0xB },
{ 108,	IWX_RATE_54M_PLCP3,	IWX_RATE_HT_SISO_MCS_6_PLCP6 },
{ 128,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_SISO_MCS_7_PLCP7 },
{ 156,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_12_PLCP0xC },
{ 208,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_13_PLCP0xD },
{ 234,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_14_PLCP0xE },
{ 260,	IWX_RATE_INVM_PLCP0xff,	IWX_RATE_HT_MIMO2_MCS_15_PLCP0xF },
207};
208#define IWX_RIDX_CCK0	0
209#define IWX_RIDX_OFDM4	4
210#define IWX_RIDX_MAX((sizeof((iwx_rates)) / sizeof((iwx_rates)[0]))-1)	(nitems(iwx_rates)(sizeof((iwx_rates)) / sizeof((iwx_rates)[0]))-1)
211#define IWX_RIDX_IS_CCK(_i_)((_i_) < 4) ((_i_) < IWX_RIDX_OFDM4)
212#define IWX_RIDX_IS_OFDM(_i_)((_i_) >= 4) ((_i_) >= IWX_RIDX_OFDM4)
213#define IWX_RVAL_IS_OFDM(_i_)((_i_) >= 12 && (_i_) != 22) ((_i_) >= 12 && (_i_) != 22)

215/* Convert an MCS index into an iwx_rates[] index. */
216const int iwx_mcs2ridx[] = {
IWX_RATE_MCS_0_INDEX,
IWX_RATE_MCS_1_INDEX,
IWX_RATE_MCS_2_INDEX,
IWX_RATE_MCS_3_INDEX,
IWX_RATE_MCS_4_INDEX,
IWX_RATE_MCS_5_INDEX,
IWX_RATE_MCS_6_INDEX,
IWX_RATE_MCS_7_INDEX,
IWX_RATE_MCS_8_INDEX,
IWX_RATE_MCS_9_INDEX,
IWX_RATE_MCS_10_INDEX,
IWX_RATE_MCS_11_INDEX,
IWX_RATE_MCS_12_INDEX,
IWX_RATE_MCS_13_INDEX,
IWX_RATE_MCS_14_INDEX,
IWX_RATE_MCS_15_INDEX,
233};

235uint8_t	iwx_lookup_cmd_ver(struct iwx_softc *, uint8_t, uint8_t);
236uint8_t	iwx_lookup_notif_ver(struct iwx_softc *, uint8_t, uint8_t);
237int	iwx_is_mimo_ht_plcp(uint8_t);
238int	iwx_store_cscheme(struct iwx_softc *, uint8_t *, size_t);
239int	iwx_alloc_fw_monitor_block(struct iwx_softc *, uint8_t, uint8_t);
240int	iwx_alloc_fw_monitor(struct iwx_softc *, uint8_t);
241int	iwx_apply_debug_destination(struct iwx_softc *);
242void	iwx_set_ltr(struct iwx_softc *);
243int	iwx_ctxt_info_init(struct iwx_softc *, const struct iwx_fw_sects *);
244int	iwx_ctxt_info_gen3_init(struct iwx_softc *,
   const struct iwx_fw_sects *);
246void	iwx_ctxt_info_free_fw_img(struct iwx_softc *);
247void	iwx_ctxt_info_free_paging(struct iwx_softc *);
248int	iwx_init_fw_sec(struct iwx_softc *, const struct iwx_fw_sects *,
   struct iwx_context_info_dram *);
250void	iwx_fw_version_str(char *, size_t, uint32_t, uint32_t, uint32_t);
251int	iwx_firmware_store_section(struct iwx_softc *, enum iwx_ucode_type,
   uint8_t *, size_t);
253int	iwx_set_default_calib(struct iwx_softc *, const void *);
254void	iwx_fw_info_free(struct iwx_fw_info *);
255int	iwx_read_firmware(struct iwx_softc *);
256uint32_t iwx_prph_addr_mask(struct iwx_softc *);
257uint32_t iwx_read_prph_unlocked(struct iwx_softc *, uint32_t);
258uint32_t iwx_read_prph(struct iwx_softc *, uint32_t);
259void	iwx_write_prph_unlocked(struct iwx_softc *, uint32_t, uint32_t);
260void	iwx_write_prph(struct iwx_softc *, uint32_t, uint32_t);
261uint32_t iwx_read_umac_prph_unlocked(struct iwx_softc *, uint32_t);
262uint32_t iwx_read_umac_prph(struct iwx_softc *, uint32_t);
263void	iwx_write_umac_prph_unlocked(struct iwx_softc *, uint32_t, uint32_t);
264void	iwx_write_umac_prph(struct iwx_softc *, uint32_t, uint32_t);
265int	iwx_read_mem(struct iwx_softc *, uint32_t, void *, int);
266int	iwx_write_mem(struct iwx_softc *, uint32_t, const void *, int);
267int	iwx_write_mem32(struct iwx_softc *, uint32_t, uint32_t);
268int	iwx_poll_bit(struct iwx_softc *, int, uint32_t, uint32_t, int);
269int	iwx_nic_lock(struct iwx_softc *);
270void	iwx_nic_assert_locked(struct iwx_softc *);
271void	iwx_nic_unlock(struct iwx_softc *);
272int	iwx_set_bits_mask_prph(struct iwx_softc *, uint32_t, uint32_t,
   uint32_t);
274int	iwx_set_bits_prph(struct iwx_softc *, uint32_t, uint32_t);
275int	iwx_clear_bits_prph(struct iwx_softc *, uint32_t, uint32_t);
276int	iwx_dma_contig_alloc(bus_dma_tag_t, struct iwx_dma_info *, bus_size_t,
   bus_size_t);
278void	iwx_dma_contig_free(struct iwx_dma_info *);
279int	iwx_alloc_rx_ring(struct iwx_softc *, struct iwx_rx_ring *);
280void	iwx_disable_rx_dma(struct iwx_softc *);
281void	iwx_reset_rx_ring(struct iwx_softc *, struct iwx_rx_ring *);
282void	iwx_free_rx_ring(struct iwx_softc *, struct iwx_rx_ring *);
283int	iwx_alloc_tx_ring(struct iwx_softc *, struct iwx_tx_ring *, int);
284void	iwx_reset_tx_ring(struct iwx_softc *, struct iwx_tx_ring *);
285void	iwx_free_tx_ring(struct iwx_softc *, struct iwx_tx_ring *);
286void	iwx_enable_rfkill_int(struct iwx_softc *);
287int	iwx_check_rfkill(struct iwx_softc *);
288void	iwx_enable_interrupts(struct iwx_softc *);
289void	iwx_enable_fwload_interrupt(struct iwx_softc *);
290void	iwx_restore_interrupts(struct iwx_softc *);
291void	iwx_disable_interrupts(struct iwx_softc *);
292void	iwx_ict_reset(struct iwx_softc *);
293int	iwx_set_hw_ready(struct iwx_softc *);
294int	iwx_prepare_card_hw(struct iwx_softc *);
295int	iwx_force_power_gating(struct iwx_softc *);
296void	iwx_apm_config(struct iwx_softc *);
297int	iwx_apm_init(struct iwx_softc *);
298void	iwx_apm_stop(struct iwx_softc *);
299int	iwx_allow_mcast(struct iwx_softc *);
300void	iwx_init_msix_hw(struct iwx_softc *);
301void	iwx_conf_msix_hw(struct iwx_softc *, int);
302int	iwx_clear_persistence_bit(struct iwx_softc *);
303int	iwx_start_hw(struct iwx_softc *);
304void	iwx_stop_device(struct iwx_softc *);
305void	iwx_nic_config(struct iwx_softc *);
306int	iwx_nic_rx_init(struct iwx_softc *);
307int	iwx_nic_init(struct iwx_softc *);
308int	iwx_enable_txq(struct iwx_softc *, int, int, int, int);
309int	iwx_disable_txq(struct iwx_softc *sc, int, int, uint8_t);
310void	iwx_post_alive(struct iwx_softc *);
311int	iwx_schedule_session_protection(struct iwx_softc *, struct iwx_node *,
   uint32_t);
313void	iwx_unprotect_session(struct iwx_softc *, struct iwx_node *);
314void	iwx_init_channel_map(struct iwx_softc *, uint16_t *, uint32_t *, int);
315void	iwx_setup_ht_rates(struct iwx_softc *);
316void	iwx_setup_vht_rates(struct iwx_softc *);
317int	iwx_mimo_enabled(struct iwx_softc *);
318void	iwx_mac_ctxt_task(void *);
319void	iwx_phy_ctxt_task(void *);
320void	iwx_updatechan(struct ieee80211com *);
321void	iwx_updateprot(struct ieee80211com *);
322void	iwx_updateslot(struct ieee80211com *);
323void	iwx_updateedca(struct ieee80211com *);
324void	iwx_updatedtim(struct ieee80211com *);
325void	iwx_init_reorder_buffer(struct iwx_reorder_buffer *, uint16_t,
   uint16_t);
327void	iwx_clear_reorder_buffer(struct iwx_softc *, struct iwx_rxba_data *);
328int	iwx_ampdu_rx_start(struct ieee80211com *, struct ieee80211_node *,
   uint8_t);
330void	iwx_ampdu_rx_stop(struct ieee80211com *, struct ieee80211_node *,
   uint8_t);
332int	iwx_ampdu_tx_start(struct ieee80211com *, struct ieee80211_node *,
   uint8_t);
334void	iwx_rx_ba_session_expired(void *);
335void	iwx_rx_bar_frame_release(struct iwx_softc *, struct iwx_rx_packet *,
   struct mbuf_list *);
337void	iwx_reorder_timer_expired(void *);
338void	iwx_sta_rx_agg(struct iwx_softc *, struct ieee80211_node *, uint8_t,
   uint16_t, uint16_t, int, int);
340void	iwx_sta_tx_agg_start(struct iwx_softc *, struct ieee80211_node *,
   uint8_t);
342void	iwx_ba_task(void *);

344void	iwx_set_mac_addr_from_csr(struct iwx_softc *, struct iwx_nvm_data *);
345int	iwx_is_valid_mac_addr(const uint8_t *);
346void	iwx_flip_hw_address(uint32_t, uint32_t, uint8_t *);
347int	iwx_nvm_get(struct iwx_softc *);
348int	iwx_load_firmware(struct iwx_softc *);
349int	iwx_start_fw(struct iwx_softc *);
350int	iwx_pnvm_handle_section(struct iwx_softc *, const uint8_t *, size_t);
351int	iwx_pnvm_parse(struct iwx_softc *, const uint8_t *, size_t);
352void	iwx_ctxt_info_gen3_set_pnvm(struct iwx_softc *);
353int	iwx_load_pnvm(struct iwx_softc *);
354int	iwx_send_tx_ant_cfg(struct iwx_softc *, uint8_t);
355int	iwx_send_phy_cfg_cmd(struct iwx_softc *);
356int	iwx_load_ucode_wait_alive(struct iwx_softc *);
357int	iwx_send_dqa_cmd(struct iwx_softc *);
358int	iwx_run_init_mvm_ucode(struct iwx_softc *, int);
359int	iwx_config_ltr(struct iwx_softc *);
360void	iwx_update_rx_desc(struct iwx_softc *, struct iwx_rx_ring *, int);
361int	iwx_rx_addbuf(struct iwx_softc *, int, int);
362int	iwx_rxmq_get_signal_strength(struct iwx_softc *, struct iwx_rx_mpdu_desc *);
363void	iwx_rx_rx_phy_cmd(struct iwx_softc *, struct iwx_rx_packet *,
   struct iwx_rx_data *);
365int	iwx_get_noise(const struct iwx_statistics_rx_non_phy *);
366int	iwx_rx_hwdecrypt(struct iwx_softc *, struct mbuf *, uint32_t,
   struct ieee80211_rxinfo *);
368int	iwx_ccmp_decap(struct iwx_softc *, struct mbuf *,
   struct ieee80211_node *, struct ieee80211_rxinfo *);
370void	iwx_rx_frame(struct iwx_softc *, struct mbuf *, int, uint32_t, int, int,
   uint32_t, struct ieee80211_rxinfo *, struct mbuf_list *);
372void	iwx_clear_tx_desc(struct iwx_softc *, struct iwx_tx_ring *, int);
373void	iwx_txd_done(struct iwx_softc *, struct iwx_tx_data *);
374void	iwx_txq_advance(struct iwx_softc *, struct iwx_tx_ring *, uint16_t);
375void	iwx_rx_tx_cmd(struct iwx_softc *, struct iwx_rx_packet *,
   struct iwx_rx_data *);
377void	iwx_clear_oactive(struct iwx_softc *, struct iwx_tx_ring *);
378void	iwx_rx_bmiss(struct iwx_softc *, struct iwx_rx_packet *,
   struct iwx_rx_data *);
380int	iwx_binding_cmd(struct iwx_softc *, struct iwx_node *, uint32_t);
381uint8_t	iwx_get_vht_ctrl_pos(struct ieee80211com *, struct ieee80211_channel *);
382int	iwx_phy_ctxt_cmd_uhb_v3_v4(struct iwx_softc *, struct iwx_phy_ctxt *,
   uint8_t, uint8_t, uint32_t, uint8_t, uint8_t, int);
384int	iwx_phy_ctxt_cmd_v3_v4(struct iwx_softc *, struct iwx_phy_ctxt *,
   uint8_t, uint8_t, uint32_t, uint8_t, uint8_t, int);
386int	iwx_phy_ctxt_cmd(struct iwx_softc *, struct iwx_phy_ctxt *, uint8_t,
   uint8_t, uint32_t, uint32_t, uint8_t, uint8_t);
388int	iwx_send_cmd(struct iwx_softc *, struct iwx_host_cmd *);
389int	iwx_send_cmd_pdu(struct iwx_softc *, uint32_t, uint32_t, uint16_t,
   const void *);
391int	iwx_send_cmd_status(struct iwx_softc *, struct iwx_host_cmd *,
   uint32_t *);
393int	iwx_send_cmd_pdu_status(struct iwx_softc *, uint32_t, uint16_t,
   const void *, uint32_t *);
395void	iwx_free_resp(struct iwx_softc *, struct iwx_host_cmd *);
396void	iwx_cmd_done(struct iwx_softc *, int, int, int);
397uint32_t iwx_fw_rateidx_ofdm(uint8_t);
398uint32_t iwx_fw_rateidx_cck(uint8_t);
399const struct iwx_rate *iwx_tx_fill_cmd(struct iwx_softc *, struct iwx_node *,
   struct ieee80211_frame *, uint16_t *, uint32_t *);
401void	iwx_tx_update_byte_tbl(struct iwx_softc *, struct iwx_tx_ring *, int,
   uint16_t, uint16_t);
403int	iwx_tx(struct iwx_softc *, struct mbuf *, struct ieee80211_node *);
404int	iwx_flush_sta_tids(struct iwx_softc *, int, uint16_t);
405int	iwx_drain_sta(struct iwx_softc *sc, struct iwx_node *, int);
406int	iwx_flush_sta(struct iwx_softc *, struct iwx_node *);
407int	iwx_beacon_filter_send_cmd(struct iwx_softc *,
   struct iwx_beacon_filter_cmd *);
409int	iwx_update_beacon_abort(struct iwx_softc *, struct iwx_node *, int);
410void	iwx_power_build_cmd(struct iwx_softc *, struct iwx_node *,
   struct iwx_mac_power_cmd *);
412int	iwx_power_mac_update_mode(struct iwx_softc *, struct iwx_node *);
413int	iwx_power_update_device(struct iwx_softc *);
414int	iwx_enable_beacon_filter(struct iwx_softc *, struct iwx_node *);
415int	iwx_disable_beacon_filter(struct iwx_softc *);
416int	iwx_add_sta_cmd(struct iwx_softc *, struct iwx_node *, int);
417int	iwx_rm_sta_cmd(struct iwx_softc *, struct iwx_node *);
418int	iwx_rm_sta(struct iwx_softc *, struct iwx_node *);
419int	iwx_fill_probe_req(struct iwx_softc *, struct iwx_scan_probe_req *);
420int	iwx_config_umac_scan_reduced(struct iwx_softc *);
421uint16_t iwx_scan_umac_flags_v2(struct iwx_softc *, int);
422void	iwx_scan_umac_dwell_v10(struct iwx_softc *,
   struct iwx_scan_general_params_v10 *, int);
424void	iwx_scan_umac_fill_general_p_v10(struct iwx_softc *,
   struct iwx_scan_general_params_v10 *, uint16_t, int);
426void	iwx_scan_umac_fill_ch_p_v6(struct iwx_softc *,
   struct iwx_scan_channel_params_v6 *, uint32_t, int);
428int	iwx_umac_scan_v14(struct iwx_softc *, int);
429void	iwx_mcc_update(struct iwx_softc *, struct iwx_mcc_chub_notif *);
430uint8_t	iwx_ridx2rate(struct ieee80211_rateset *, int);
431int	iwx_rval2ridx(int);
432void	iwx_ack_rates(struct iwx_softc *, struct iwx_node *, int *, int *);
433void	iwx_mac_ctxt_cmd_common(struct iwx_softc *, struct iwx_node *,
   struct iwx_mac_ctx_cmd *, uint32_t);
435void	iwx_mac_ctxt_cmd_fill_sta(struct iwx_softc *, struct iwx_node *,
   struct iwx_mac_data_sta *, int);
437int	iwx_mac_ctxt_cmd(struct iwx_softc *, struct iwx_node *, uint32_t, int);
438int	iwx_clear_statistics(struct iwx_softc *);
439void	iwx_add_task(struct iwx_softc *, struct taskq *, struct task *);
440void	iwx_del_task(struct iwx_softc *, struct taskq *, struct task *);
441int	iwx_scan(struct iwx_softc *);
442int	iwx_bgscan(struct ieee80211com *);
443void	iwx_bgscan_done(struct ieee80211com *,
   struct ieee80211_node_switch_bss_arg *, size_t);
445void	iwx_bgscan_done_task(void *);
446int	iwx_umac_scan_abort(struct iwx_softc *);
447int	iwx_scan_abort(struct iwx_softc *);
448int	iwx_enable_mgmt_queue(struct iwx_softc *);
449int	iwx_disable_mgmt_queue(struct iwx_softc *);
450int	iwx_rs_rval2idx(uint8_t);
451uint16_t iwx_rs_ht_rates(struct iwx_softc *, struct ieee80211_node *, int);
452uint16_t iwx_rs_vht_rates(struct iwx_softc *, struct ieee80211_node *, int);
453int	iwx_rs_init_v3(struct iwx_softc *, struct iwx_node *);
454int	iwx_rs_init_v4(struct iwx_softc *, struct iwx_node *);
455int	iwx_rs_init(struct iwx_softc *, struct iwx_node *);
456int	iwx_enable_data_tx_queues(struct iwx_softc *);
457int	iwx_phy_send_rlc(struct iwx_softc *, struct iwx_phy_ctxt *,
   uint8_t, uint8_t);
459int	iwx_phy_ctxt_update(struct iwx_softc *, struct iwx_phy_ctxt *,
   struct ieee80211_channel *, uint8_t, uint8_t, uint32_t, uint8_t,
   uint8_t);
462int	iwx_auth(struct iwx_softc *);
463int	iwx_deauth(struct iwx_softc *);
464int	iwx_run(struct iwx_softc *);
465int	iwx_run_stop(struct iwx_softc *);
466struct ieee80211_node *iwx_node_alloc(struct ieee80211com *);
467int	iwx_set_key(struct ieee80211com *, struct ieee80211_node *,
   struct ieee80211_key *);
469void	iwx_setkey_task(void *);
470void	iwx_delete_key(struct ieee80211com *,
   struct ieee80211_node *, struct ieee80211_key *);
472int	iwx_media_change(struct ifnet *);
473void	iwx_newstate_task(void *);
474int	iwx_newstate(struct ieee80211com *, enum ieee80211_state, int);
475void	iwx_endscan(struct iwx_softc *);
476void	iwx_fill_sf_command(struct iwx_softc *, struct iwx_sf_cfg_cmd *,
   struct ieee80211_node *);
478int	iwx_sf_config(struct iwx_softc *, int);
479int	iwx_send_bt_init_conf(struct iwx_softc *);
480int	iwx_send_soc_conf(struct iwx_softc *);
481int	iwx_send_update_mcc_cmd(struct iwx_softc *, const char *);
482int	iwx_send_temp_report_ths_cmd(struct iwx_softc *);
483int	iwx_init_hw(struct iwx_softc *);
484int	iwx_init(struct ifnet *);
485void	iwx_start(struct ifnet *);
486void	iwx_stop(struct ifnet *);
487void	iwx_watchdog(struct ifnet *);
488int	iwx_ioctl(struct ifnet *, u_long, caddr_t);
489const char *iwx_desc_lookup(uint32_t);
490void	iwx_nic_error(struct iwx_softc *);
491void	iwx_dump_driver_status(struct iwx_softc *);
492void	iwx_nic_umac_error(struct iwx_softc *);
493int	iwx_detect_duplicate(struct iwx_softc *, struct mbuf *,
   struct iwx_rx_mpdu_desc *, struct ieee80211_rxinfo *);
495int	iwx_is_sn_less(uint16_t, uint16_t, uint16_t);
496void	iwx_release_frames(struct iwx_softc *, struct ieee80211_node *,
   struct iwx_rxba_data *, struct iwx_reorder_buffer *, uint16_t,
   struct mbuf_list *);
499int	iwx_oldsn_workaround(struct iwx_softc *, struct ieee80211_node *,
   int, struct iwx_reorder_buffer *, uint32_t, uint32_t);
501int	iwx_rx_reorder(struct iwx_softc *, struct mbuf *, int,
   struct iwx_rx_mpdu_desc *, int, int, uint32_t,
   struct ieee80211_rxinfo *, struct mbuf_list *);
504void	iwx_rx_mpdu_mq(struct iwx_softc *, struct mbuf *, void *, size_t,
   struct mbuf_list *);
506int	iwx_rx_pkt_valid(struct iwx_rx_packet *);
507void	iwx_rx_pkt(struct iwx_softc *, struct iwx_rx_data *,
   struct mbuf_list *);
509void	iwx_notif_intr(struct iwx_softc *);
510int	iwx_intr(void *);
511int	iwx_intr_msix(void *);
512int	iwx_match(struct device *, void *, void *);
513int	iwx_preinit(struct iwx_softc *);
514void	iwx_attach_hook(struct device *);
515const struct iwx_device_cfg *iwx_find_device_cfg(struct iwx_softc *);
516void	iwx_attach(struct device *, struct device *, void *);
517void	iwx_init_task(void *);
518int	iwx_activate(struct device *, int);
519void	iwx_resume(struct iwx_softc *);
520int	iwx_wakeup(struct iwx_softc *);

522#if NBPFILTER1 > 0
523void	iwx_radiotap_attach(struct iwx_softc *);
524#endif

526uint8_t
527iwx_lookup_cmd_ver(struct iwx_softc *sc, uint8_t grp, uint8_t cmd)
528{
const struct iwx_fw_cmd_version *entry;
int i;

for (i = 0; i < sc->n_cmd_versions; i++) {
entry = &sc->cmd_versions[i];
if (entry->group == grp && entry->cmd == cmd)
	return entry->cmd_ver;
}

return IWX_FW_CMD_VER_UNKNOWN99;
539}

541uint8_t
542iwx_lookup_notif_ver(struct iwx_softc *sc, uint8_t grp, uint8_t cmd)
543{
const struct iwx_fw_cmd_version *entry;
int i;

for (i = 0; i < sc->n_cmd_versions; i++) {
entry = &sc->cmd_versions[i];
if (entry->group == grp && entry->cmd == cmd)
	return entry->notif_ver;
}

return IWX_FW_CMD_VER_UNKNOWN99;
554}

556int
557iwx_is_mimo_ht_plcp(uint8_t ht_plcp)
558{
switch (ht_plcp) {
case IWX_RATE_HT_MIMO2_MCS_8_PLCP0x8:
case IWX_RATE_HT_MIMO2_MCS_9_PLCP0x9:
case IWX_RATE_HT_MIMO2_MCS_10_PLCP0xA:
case IWX_RATE_HT_MIMO2_MCS_11_PLCP0xB:
case IWX_RATE_HT_MIMO2_MCS_12_PLCP0xC:
case IWX_RATE_HT_MIMO2_MCS_13_PLCP0xD:
case IWX_RATE_HT_MIMO2_MCS_14_PLCP0xE:
case IWX_RATE_HT_MIMO2_MCS_15_PLCP0xF:
return 1;
default:
break;
}

return 0;
574}

576int
577iwx_store_cscheme(struct iwx_softc *sc, uint8_t *data, size_t dlen)
578{
struct iwx_fw_cscheme_list *l = (void *)data;

if (dlen < sizeof(*l) ||
   dlen < sizeof(l->size) + l->size * sizeof(*l->cs))
return EINVAL22;

/* we don't actually store anything for now, always use s/w crypto */

return 0;
588}

590int
591iwx_ctxt_info_alloc_dma(struct iwx_softc *sc,
  const struct iwx_fw_onesect *sec, struct iwx_dma_info *dram)
593{
int err = iwx_dma_contig_alloc(sc->sc_dmat, dram, sec->fws_len, 0);
if (err) {
printf("%s: could not allocate context info DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
return err;
}

memcpy(dram->vaddr, sec->fws_data, sec->fws_len)__builtin_memcpy((dram->vaddr), (sec->fws_data), (sec->
fws_len));

return 0;
604}

606void iwx_ctxt_info_free_paging(struct iwx_softc *sc)
607{
struct iwx_self_init_dram *dram = &sc->init_dram;
int i;

if (!dram->paging)
return;

/* free paging*/
for (i = 0; i < dram->paging_cnt; i++)
iwx_dma_contig_free(&dram->paging[i]);

free(dram->paging, M_DEVBUF2, dram->paging_cnt * sizeof(*dram->paging));
dram->paging_cnt = 0;
dram->paging = NULL((void *)0);
621}

623int
624iwx_get_num_sections(const struct iwx_fw_sects *fws, int start)
625{
int i = 0;

while (start < fws->fw_count &&
      fws->fw_sect[start].fws_devoff != IWX_CPU1_CPU2_SEPARATOR_SECTION0xFFFFCCCC &&
      fws->fw_sect[start].fws_devoff != IWX_PAGING_SEPARATOR_SECTION0xAAAABBBB) {
start++;
i++;
}

return i;
636}

638int
639iwx_init_fw_sec(struct iwx_softc *sc, const struct iwx_fw_sects *fws,
  struct iwx_context_info_dram *ctxt_dram)
641{
struct iwx_self_init_dram *dram = &sc->init_dram;
int i, ret, fw_cnt = 0;

KASSERT(dram->paging == NULL)((dram->paging == ((void *)0)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_iwx.c", 645, "dram->paging == NULL"
));

dram->lmac_cnt = iwx_get_num_sections(fws, 0);
/* add 1 due to separator */
dram->umac_cnt = iwx_get_num_sections(fws, dram->lmac_cnt + 1);
/* add 2 due to separators */
dram->paging_cnt = iwx_get_num_sections(fws,
   dram->lmac_cnt + dram->umac_cnt + 2);

dram->fw = mallocarray(dram->umac_cnt + dram->lmac_cnt,
   sizeof(*dram->fw), M_DEVBUF2,  M_ZERO0x0008 | M_NOWAIT0x0002);
if (!dram->fw) {
printf("%s: could not allocate memory for firmware sections\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ENOMEM12;
}

dram->paging = mallocarray(dram->paging_cnt, sizeof(*dram->paging),
   M_DEVBUF2, M_ZERO0x0008 | M_NOWAIT0x0002);
if (!dram->paging) {
printf("%s: could not allocate memory for firmware paging\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
return ENOMEM12;
}

/* initialize lmac sections */
for (i = 0; i < dram->lmac_cnt; i++) {
ret = iwx_ctxt_info_alloc_dma(sc, &fws->fw_sect[i],
				   &dram->fw[fw_cnt]);
if (ret)
	return ret;
ctxt_dram->lmac_img[i] =
	htole64(dram->fw[fw_cnt].paddr)((__uint64_t)(dram->fw[fw_cnt].paddr));
DPRINTF(("%s: firmware LMAC section %d at 0x%llx size %lld\n", __func__, i,do { ; } while (0)
    (unsigned long long)dram->fw[fw_cnt].paddr,do { ; } while (0)
    (unsigned long long)dram->fw[fw_cnt].size))do { ; } while (0);
fw_cnt++;
}

/* initialize umac sections */
for (i = 0; i < dram->umac_cnt; i++) {
/* access FW with +1 to make up for lmac separator */
ret = iwx_ctxt_info_alloc_dma(sc,
    &fws->fw_sect[fw_cnt + 1], &dram->fw[fw_cnt]);
if (ret)
	return ret;
ctxt_dram->umac_img[i] =
	htole64(dram->fw[fw_cnt].paddr)((__uint64_t)(dram->fw[fw_cnt].paddr));
DPRINTF(("%s: firmware UMAC section %d at 0x%llx size %lld\n", __func__, i,do { ; } while (0)
	(unsigned long long)dram->fw[fw_cnt].paddr,do { ; } while (0)
	(unsigned long long)dram->fw[fw_cnt].size))do { ; } while (0);
fw_cnt++;
}

/*
* Initialize paging.
* Paging memory isn't stored in dram->fw as the umac and lmac - it is
* stored separately.
* This is since the timing of its release is different -
* while fw memory can be released on alive, the paging memory can be
* freed only when the device goes down.
* Given that, the logic here in accessing the fw image is a bit
* different - fw_cnt isn't changing so loop counter is added to it.
*/
for (i = 0; i < dram->paging_cnt; i++) {
/* access FW with +2 to make up for lmac & umac separators */
int fw_idx = fw_cnt + i + 2;

ret = iwx_ctxt_info_alloc_dma(sc,
    &fws->fw_sect[fw_idx], &dram->paging[i]);
if (ret)
	return ret;

ctxt_dram->virtual_img[i] = htole64(dram->paging[i].paddr)((__uint64_t)(dram->paging[i].paddr));
DPRINTF(("%s: firmware paging section %d at 0x%llx size %lld\n", __func__, i,do { ; } while (0)
    (unsigned long long)dram->paging[i].paddr,do { ; } while (0)
    (unsigned long long)dram->paging[i].size))do { ; } while (0);
}

return 0;
725}

727void
728iwx_fw_version_str(char *buf, size_t bufsize,
  uint32_t major, uint32_t minor, uint32_t api)
730{
/*
* Starting with major version 35 the Linux driver prints the minor
* version in hexadecimal.
*/
if (major >= 35)
snprintf(buf, bufsize, "%u.%08x.%u", major, minor, api);
else
snprintf(buf, bufsize, "%u.%u.%u", major, minor, api);
739}

741int
742iwx_alloc_fw_monitor_block(struct iwx_softc *sc, uint8_t max_power,
  uint8_t min_power)
744{
struct iwx_dma_info *fw_mon = &sc->fw_mon;
uint32_t size = 0;
uint8_t power;
int err;
1
'err' declared without an initial value→

if (fw_mon->size)
2
←
Assuming field 'size' is 0→
3
←
Taking false branch→
return 0;

for (power = max_power; power >= min_power; power--) {
4
←
Assuming 'power' is < 'min_power'→
5
←
Loop condition is false. Execution continues on line 765→
size = (1 << power);

err = iwx_dma_contig_alloc(sc->sc_dmat, fw_mon, size, 0);
if (err)
	continue;

DPRINTF(("%s: allocated 0x%08x bytes for firmware monitor.\n",do { ; } while (0)
	 DEVNAME(sc), size))do { ; } while (0);
break;
}

if (err) {
6
←
Branch condition evaluates to a garbage value
fw_mon->size = 0;
return err;
}

if (power != max_power)
DPRINTF(("%s: Sorry - debug buffer is only %luK while you requested %luK\n",do { ; } while (0)
	DEVNAME(sc), (unsigned long)(1 << (power - 10)),do { ; } while (0)
	(unsigned long)(1 << (max_power - 10))))do { ; } while (0);

return 0;
776}

778int
779iwx_alloc_fw_monitor(struct iwx_softc *sc, uint8_t max_power)
780{
if (!max_power) {
/* default max_power is maximum */
max_power = 26;
} else {
max_power += 11;
}

if (max_power > 26) {
 DPRINTF(("%s: External buffer size for monitor is too big %d, "do { ; } while (0)
     "check the FW TLV\n", DEVNAME(sc), max_power))do { ; } while (0);
return 0;
}

if (sc->fw_mon.size)
return 0;

return iwx_alloc_fw_monitor_block(sc, max_power, 11);
798}

800int
801iwx_apply_debug_destination(struct iwx_softc *sc)
802{
struct iwx_fw_dbg_dest_tlv_v1 *dest_v1;
int i, err;
uint8_t mon_mode, size_power, base_shift, end_shift;
uint32_t base_reg, end_reg;

dest_v1 = sc->sc_fw.dbg_dest_tlv_v1;
mon_mode = dest_v1->monitor_mode;
size_power = dest_v1->size_power;
base_reg = le32toh(dest_v1->base_reg)((__uint32_t)(dest_v1->base_reg));
end_reg = le32toh(dest_v1->end_reg)((__uint32_t)(dest_v1->end_reg));
base_shift = dest_v1->base_shift;
end_shift = dest_v1->end_shift;

DPRINTF(("%s: applying debug destination %d\n", DEVNAME(sc), mon_mode))do { ; } while (0);

if (mon_mode == EXTERNAL_MODE) {
err = iwx_alloc_fw_monitor(sc, size_power);
if (err)
	return err;
}

if (!iwx_nic_lock(sc))
return EBUSY16;

for (i = 0; i < sc->sc_fw.n_dest_reg; i++) {
uint32_t addr, val;
uint8_t op;

addr = le32toh(dest_v1->reg_ops[i].addr)((__uint32_t)(dest_v1->reg_ops[i].addr));
val = le32toh(dest_v1->reg_ops[i].val)((__uint32_t)(dest_v1->reg_ops[i].val));
op = dest_v1->reg_ops[i].op;

DPRINTF(("%s: op=%u addr=%u val=%u\n", __func__, op, addr, val))do { ; } while (0);
switch (op) {
case CSR_ASSIGN:
	IWX_WRITE(sc, addr, val)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((addr)), ((val
))));
	break;
case CSR_SETBIT:
	IWX_SETBITS(sc, addr, (1 << val))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((addr)), (((
((sc)->sc_st)->read_4(((sc)->sc_sh), ((addr)))) | ((
<< val))))));
	break;
case CSR_CLEARBIT:
	IWX_CLRBITS(sc, addr, (1 << val))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((addr)), (((
((sc)->sc_st)->read_4(((sc)->sc_sh), ((addr)))) &
 ~((1 << val))))));
	break;
case PRPH_ASSIGN:
	iwx_write_prph(sc, addr, val);
	break;
case PRPH_SETBIT:
	err = iwx_set_bits_prph(sc, addr, (1 << val));
	if (err)
		return err;
	break;
case PRPH_CLEARBIT:
	err = iwx_clear_bits_prph(sc, addr, (1 << val));
	if (err)
		return err;
	break;
case PRPH_BLOCKBIT:
	if (iwx_read_prph(sc, addr) & (1 << val))
		goto monitor;
	break;
default:
	DPRINTF(("%s: FW debug - unknown OP %d\n",do { ; } while (0)
	    DEVNAME(sc), op))do { ; } while (0);
	break;
}
}

870monitor:
if (mon_mode == EXTERNAL_MODE && sc->fw_mon.size) {
iwx_write_prph(sc, le32toh(base_reg)((__uint32_t)(base_reg)),
    sc->fw_mon.paddr >> base_shift);
iwx_write_prph(sc, end_reg,
    (sc->fw_mon.paddr + sc->fw_mon.size - 256)
    >> end_shift);
}

iwx_nic_unlock(sc);
return 0;
881}

883void
884iwx_set_ltr(struct iwx_softc *sc)
885{
uint32_t ltr_val = IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ0x80000000 |
   ((IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC2 <<
   IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_SHIFT24) &
   IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_MASK0x1c000000) |
   ((250 << IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_SHIFT16) &
   IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_MASK0x03ff0000) |
   IWX_CSR_LTR_LONG_VAL_AD_SNOOP_REQ0x00008000 |
   ((IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC2 <<
   IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_SHIFT8) &
   IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_MASK0x00001c00) |
   (250 & IWX_CSR_LTR_LONG_VAL_AD_SNOOP_VAL0x000003ff);

/*
* To workaround hardware latency issues during the boot process,
* initialize the LTR to ~250 usec (see ltr_val above).
* The firmware initializes this again later (to a smaller value).
*/
if (!sc->sc_integrated) {
IWX_WRITE(sc, IWX_CSR_LTR_LONG_VAL_AD, ltr_val)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0d4))), (
(ltr_val))));
} else if (sc->sc_integrated &&
   sc->sc_device_family == IWX_DEVICE_FAMILY_220001) {
iwx_write_prph(sc, IWX_HPM_MAC_LTR_CSR0xa0348c,
    IWX_HPM_MAC_LRT_ENABLE_ALL0xf);
iwx_write_prph(sc, IWX_HPM_UMAC_LTR0xa03480, ltr_val);
}
911}

913int
914iwx_ctxt_info_init(struct iwx_softc *sc, const struct iwx_fw_sects *fws)
915{
struct iwx_context_info *ctxt_info;
struct iwx_context_info_rbd_cfg *rx_cfg;
uint32_t control_flags = 0;
uint64_t paddr;
int err;

ctxt_info = sc->ctxt_info_dma.vaddr;
memset(ctxt_info, 0, sizeof(*ctxt_info))__builtin_memset((ctxt_info), (0), (sizeof(*ctxt_info)));

ctxt_info->version.version = 0;
ctxt_info->version.mac_id =
htole16((uint16_t)IWX_READ(sc, IWX_CSR_HW_REV))((__uint16_t)((uint16_t)(((sc)->sc_st)->read_4(((sc)->
sc_sh), (((0x028)))))));
/* size is in DWs */
ctxt_info->version.size = htole16(sizeof(*ctxt_info) / 4)((__uint16_t)(sizeof(*ctxt_info) / 4));

KASSERT(IWX_RX_QUEUE_CB_SIZE(IWX_MQ_RX_TABLE_SIZE) < 0xF)((((sizeof(512) <= 4) ? (fls(512) - 1) : (flsl(512) - 1)) <
 0xF) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_iwx.c"
, 931, "IWX_RX_QUEUE_CB_SIZE(IWX_MQ_RX_TABLE_SIZE) < 0xF")
);
control_flags = IWX_CTXT_INFO_TFD_FORMAT_LONG |
	(IWX_RX_QUEUE_CB_SIZE(IWX_MQ_RX_TABLE_SIZE)((sizeof(512) <= 4) ? (fls(512) - 1) : (flsl(512) - 1)) <<
	 IWX_CTXT_INFO_RB_CB_SIZE_POS) |
	(IWX_CTXT_INFO_RB_SIZE_4K << IWX_CTXT_INFO_RB_SIZE_POS);
ctxt_info->control.control_flags = htole32(control_flags)((__uint32_t)(control_flags));

/* initialize RX default queue */
rx_cfg = &ctxt_info->rbd_cfg;
rx_cfg->free_rbd_addr = htole64(sc->rxq.free_desc_dma.paddr)((__uint64_t)(sc->rxq.free_desc_dma.paddr));
rx_cfg->used_rbd_addr = htole64(sc->rxq.used_desc_dma.paddr)((__uint64_t)(sc->rxq.used_desc_dma.paddr));
rx_cfg->status_wr_ptr = htole64(sc->rxq.stat_dma.paddr)((__uint64_t)(sc->rxq.stat_dma.paddr));

/* initialize TX command queue */
ctxt_info->hcmd_cfg.cmd_queue_addr =
   htole64(sc->txq[IWX_DQA_CMD_QUEUE].desc_dma.paddr)((__uint64_t)(sc->txq[0].desc_dma.paddr));
ctxt_info->hcmd_cfg.cmd_queue_size =
IWX_TFD_QUEUE_CB_SIZE(IWX_TX_RING_COUNT)(((sizeof((256)) <= 4) ? (fls((256)) - 1) : (flsl((256)) -
 1)) - 3);

/* allocate ucode sections in dram and set addresses */
err = iwx_init_fw_sec(sc, fws, &ctxt_info->dram);
if (err) {
iwx_ctxt_info_free_fw_img(sc);
return err;
}

/* Configure debug, if exists */
if (sc->sc_fw.dbg_dest_tlv_v1) {
err = iwx_apply_debug_destination(sc);
if (err) {
	iwx_ctxt_info_free_fw_img(sc);
	return err;
}
}

/*
* Write the context info DMA base address. The device expects a
* 64-bit address but a simple bus_space_write_8 to this register
* won't work on some devices, such as the AX201.
*/
paddr = sc->ctxt_info_dma.paddr;
IWX_WRITE(sc, IWX_CSR_CTXT_INFO_BA, paddr & 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x40)), ((paddr
 & 0xffffffff))));
IWX_WRITE(sc, IWX_CSR_CTXT_INFO_BA + 4, paddr >> 32)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x40 + 4)),
 ((paddr >> 32))));

/* kick FW self load */
if (!iwx_nic_lock(sc)) {
iwx_ctxt_info_free_fw_img(sc);
return EBUSY16;
}

iwx_set_ltr(sc);
iwx_write_prph(sc, IWX_UREG_CPU_INIT_RUN(0xa05c44), 1);
iwx_nic_unlock(sc);

/* Context info will be released upon alive or failure to get one */

return 0;
988}

990int
991iwx_ctxt_info_gen3_init(struct iwx_softc *sc, const struct iwx_fw_sects *fws)
992{
struct iwx_context_info_gen3 *ctxt_info_gen3;
struct iwx_prph_scratch *prph_scratch;
struct iwx_prph_scratch_ctrl_cfg *prph_sc_ctrl;
uint16_t cb_size;
uint32_t control_flags, scratch_size;
uint64_t paddr;
int err;

if (sc->sc_fw.iml == NULL((void *)0) || sc->sc_fw.iml_len == 0) {
printf("%s: no image loader found in firmware file\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
iwx_ctxt_info_free_fw_img(sc);
return EINVAL22;
}

err = iwx_dma_contig_alloc(sc->sc_dmat, &sc->iml_dma,
   sc->sc_fw.iml_len, 0);
if (err) {
printf("%s: could not allocate DMA memory for "
    "firmware image loader\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
iwx_ctxt_info_free_fw_img(sc);
return ENOMEM12;
}

prph_scratch = sc->prph_scratch_dma.vaddr;
memset(prph_scratch, 0, sizeof(*prph_scratch))__builtin_memset((prph_scratch), (0), (sizeof(*prph_scratch))
);
prph_sc_ctrl = &prph_scratch->ctrl_cfg;
prph_sc_ctrl->version.version = 0;
prph_sc_ctrl->version.mac_id = htole16(IWX_READ(sc, IWX_CSR_HW_REV))((__uint16_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
((0x028)))))));
prph_sc_ctrl->version.size = htole16(sizeof(*prph_scratch) / 4)((__uint16_t)(sizeof(*prph_scratch) / 4));

control_flags = IWX_PRPH_SCRATCH_RB_SIZE_4K(1 << 16) |
   IWX_PRPH_SCRATCH_MTR_MODE(1 << 17) |
   (IWX_PRPH_MTR_FORMAT_256B0xC0000 & IWX_PRPH_SCRATCH_MTR_FORMAT((1 << 18) | (1 << 19)));
if (sc->sc_imr_enabled)
control_flags |= IWX_PRPH_SCRATCH_IMR_DEBUG_EN(1 << 1);
prph_sc_ctrl->control.control_flags = htole32(control_flags)((__uint32_t)(control_flags));

/* initialize RX default queue */
prph_sc_ctrl->rbd_cfg.free_rbd_addr =
   htole64(sc->rxq.free_desc_dma.paddr)((__uint64_t)(sc->rxq.free_desc_dma.paddr));

/* allocate ucode sections in dram and set addresses */
err = iwx_init_fw_sec(sc, fws, &prph_scratch->dram);
if (err) {
iwx_dma_contig_free(&sc->iml_dma);
iwx_ctxt_info_free_fw_img(sc);
return err;
}

ctxt_info_gen3 = sc->ctxt_info_dma.vaddr;
memset(ctxt_info_gen3, 0, sizeof(*ctxt_info_gen3))__builtin_memset((ctxt_info_gen3), (0), (sizeof(*ctxt_info_gen3
)));
ctxt_info_gen3->prph_info_base_addr = htole64(sc->prph_info_dma.paddr)((__uint64_t)(sc->prph_info_dma.paddr));
ctxt_info_gen3->prph_scratch_base_addr =
   htole64(sc->prph_scratch_dma.paddr)((__uint64_t)(sc->prph_scratch_dma.paddr));
scratch_size = sizeof(*prph_scratch);
ctxt_info_gen3->prph_scratch_size = htole32(scratch_size)((__uint32_t)(scratch_size));
ctxt_info_gen3->cr_head_idx_arr_base_addr =
   htole64(sc->rxq.stat_dma.paddr)((__uint64_t)(sc->rxq.stat_dma.paddr));
ctxt_info_gen3->tr_tail_idx_arr_base_addr =
   htole64(sc->prph_info_dma.paddr + PAGE_SIZE / 2)((__uint64_t)(sc->prph_info_dma.paddr + (1 << 12) / 2
));
ctxt_info_gen3->cr_tail_idx_arr_base_addr =
   htole64(sc->prph_info_dma.paddr + 3 * PAGE_SIZE / 4)((__uint64_t)(sc->prph_info_dma.paddr + 3 * (1 << 12
) / 4));
ctxt_info_gen3->mtr_base_addr =
   htole64(sc->txq[IWX_DQA_CMD_QUEUE].desc_dma.paddr)((__uint64_t)(sc->txq[0].desc_dma.paddr));
ctxt_info_gen3->mcr_base_addr = htole64(sc->rxq.used_desc_dma.paddr)((__uint64_t)(sc->rxq.used_desc_dma.paddr));
cb_size = IWX_TFD_QUEUE_CB_SIZE(IWX_TX_RING_COUNT)(((sizeof((256)) <= 4) ? (fls((256)) - 1) : (flsl((256)) -
 1)) - 3);
ctxt_info_gen3->mtr_size = htole16(cb_size)((__uint16_t)(cb_size));
cb_size = IWX_RX_QUEUE_CB_SIZE(IWX_MQ_RX_TABLE_SIZE)((sizeof(512) <= 4) ? (fls(512) - 1) : (flsl(512) - 1));
ctxt_info_gen3->mcr_size = htole16(cb_size)((__uint16_t)(cb_size));

memcpy(sc->iml_dma.vaddr, sc->sc_fw.iml, sc->sc_fw.iml_len)__builtin_memcpy((sc->iml_dma.vaddr), (sc->sc_fw.iml), (
sc->sc_fw.iml_len));

paddr = sc->ctxt_info_dma.paddr;
IWX_WRITE(sc, IWX_CSR_CTXT_INFO_ADDR, paddr & 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x118)), ((
paddr & 0xffffffff))));
IWX_WRITE(sc, IWX_CSR_CTXT_INFO_ADDR + 4, paddr >> 32)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x118 + 4))
, ((paddr >> 32))));

paddr = sc->iml_dma.paddr;
IWX_WRITE(sc, IWX_CSR_IML_DATA_ADDR, paddr & 0xffffffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x120)), ((
paddr & 0xffffffff))));
IWX_WRITE(sc, IWX_CSR_IML_DATA_ADDR + 4, paddr >> 32)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x120 + 4))
, ((paddr >> 32))));
IWX_WRITE(sc, IWX_CSR_IML_SIZE_ADDR, sc->sc_fw.iml_len)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x128)), ((
sc->sc_fw.iml_len))));

IWX_SETBITS(sc, IWX_CSR_CTXT_INFO_BOOT_CTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0)), ((((
(sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0)))) | ((1 <<
 1))))))
    IWX_CSR_AUTO_FUNC_BOOT_ENA)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((0x0)), ((((
(sc)->sc_st)->read_4(((sc)->sc_sh), ((0x0)))) | ((1 <<
 1))))));

/* kick FW self load */
if (!iwx_nic_lock(sc)) {
iwx_dma_contig_free(&sc->iml_dma);
iwx_ctxt_info_free_fw_img(sc);
return EBUSY16;
}
iwx_set_ltr(sc);
iwx_write_umac_prph(sc, IWX_UREG_CPU_INIT_RUN(0xa05c44), 1);
iwx_nic_unlock(sc);

/* Context info will be released upon alive or failure to get one */
return 0;
1090}

1092void
1093iwx_ctxt_info_free_fw_img(struct iwx_softc *sc)
1094{
struct iwx_self_init_dram *dram = &sc->init_dram;
int i;

if (!dram->fw)
return;

for (i = 0; i < dram->lmac_cnt + dram->umac_cnt; i++)
iwx_dma_contig_free(&dram->fw[i]);

free(dram->fw, M_DEVBUF2,
   (dram->lmac_cnt + dram->umac_cnt) * sizeof(*dram->fw));
dram->lmac_cnt = 0;
dram->umac_cnt = 0;
dram->fw = NULL((void *)0);
1109}

1111int
1112iwx_firmware_store_section(struct iwx_softc *sc, enum iwx_ucode_type type,
  uint8_t *data, size_t dlen)
1114{
struct iwx_fw_sects *fws;
struct iwx_fw_onesect *fwone;

if (type >= IWX_UCODE_TYPE_MAX)
return EINVAL22;
if (dlen < sizeof(uint32_t))
return EINVAL22;

fws = &sc->sc_fw.fw_sects[type];
DPRINTF(("%s: ucode type %d section %d\n", DEVNAME(sc), type, fws->fw_count))do { ; } while (0);
if (fws->fw_count >= IWX_UCODE_SECT_MAX57)
return EINVAL22;

fwone = &fws->fw_sect[fws->fw_count];

/* first 32bit are device load offset */
memcpy(&fwone->fws_devoff, data, sizeof(uint32_t))__builtin_memcpy((&fwone->fws_devoff), (data), (sizeof
(uint32_t)));

/* rest is data */
fwone->fws_data = data + sizeof(uint32_t);
fwone->fws_len = dlen - sizeof(uint32_t);

fws->fw_count++;
fws->fw_totlen += fwone->fws_len;

return 0;
1141}

1143#define IWX_DEFAULT_SCAN_CHANNELS40	40
1144/* Newer firmware might support more channels. Raise this value if needed. */
1145#define IWX_MAX_SCAN_CHANNELS67		67 /* as of iwx-cc-a0-62 firmware */

1147struct iwx_tlv_calib_data {
uint32_t ucode_type;
struct iwx_tlv_calib_ctrl calib;
1150} __packed__attribute__((__packed__));

1152int
1153iwx_set_default_calib(struct iwx_softc *sc, const void *data)
1154{
const struct iwx_tlv_calib_data *def_calib = data;
uint32_t ucode_type = le32toh(def_calib->ucode_type)((__uint32_t)(def_calib->ucode_type));

if (ucode_type >= IWX_UCODE_TYPE_MAX)
return EINVAL22;

sc->sc_default_calib[ucode_type].flow_trigger =
   def_calib->calib.flow_trigger;
sc->sc_default_calib[ucode_type].event_trigger =
   def_calib->calib.event_trigger;

return 0;
1167}

1169void
1170iwx_fw_info_free(struct iwx_fw_info *fw)
1171{
free(fw->fw_rawdata, M_DEVBUF2, fw->fw_rawsize);
fw->fw_rawdata = NULL((void *)0);
fw->fw_rawsize = 0;
/* don't touch fw->fw_status */
memset(fw->fw_sects, 0, sizeof(fw->fw_sects))__builtin_memset((fw->fw_sects), (0), (sizeof(fw->fw_sects
)));
free(fw->iml, M_DEVBUF2, fw->iml_len);
fw->iml = NULL((void *)0);
fw->iml_len = 0;
1180}

1182#define IWX_FW_ADDR_CACHE_CONTROL0xC0000000 0xC0000000

1184int
1185iwx_read_firmware(struct iwx_softc *sc)
1186{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_fw_info *fw = &sc->sc_fw;
struct iwx_tlv_ucode_header *uhdr;
struct iwx_ucode_tlv tlv;
uint32_t tlv_type;
uint8_t *data;
int err;
size_t len;

if (fw->fw_status == IWX_FW_STATUS_DONE2)
return 0;

while (fw->fw_status == IWX_FW_STATUS_INPROGRESS1)
tsleep_nsec(&sc->sc_fw, 0, "iwxfwp", INFSLP0xffffffffffffffffULL);
fw->fw_status = IWX_FW_STATUS_INPROGRESS1;

if (fw->fw_rawdata != NULL((void *)0))
iwx_fw_info_free(fw);

err = loadfirmware(sc->sc_fwname,
   (u_char **)&fw->fw_rawdata, &fw->fw_rawsize);
if (err) {
printf("%s: could not read firmware %s (error %d)\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_fwname, err);
goto out;
}

if (ic->ic_ific_ac.ac_if.if_flags & IFF_DEBUG0x4)
printf("%s: using firmware %s\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_fwname);

sc->sc_capaflags = 0;
sc->sc_capa_n_scan_channels = IWX_DEFAULT_SCAN_CHANNELS40;
memset(sc->sc_enabled_capa, 0, sizeof(sc->sc_enabled_capa))__builtin_memset((sc->sc_enabled_capa), (0), (sizeof(sc->
sc_enabled_capa)));
memset(sc->sc_ucode_api, 0, sizeof(sc->sc_ucode_api))__builtin_memset((sc->sc_ucode_api), (0), (sizeof(sc->sc_ucode_api
)));
sc->n_cmd_versions = 0;

uhdr = (void *)fw->fw_rawdata;
if (*(uint32_t *)fw->fw_rawdata != 0
   || le32toh(uhdr->magic)((__uint32_t)(uhdr->magic)) != IWX_TLV_UCODE_MAGIC0x0a4c5749) {
printf("%s: invalid firmware %s\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_fwname);
err = EINVAL22;
goto out;
}

iwx_fw_version_str(sc->sc_fwver, sizeof(sc->sc_fwver),
   IWX_UCODE_MAJOR(le32toh(uhdr->ver))(((((__uint32_t)(uhdr->ver))) & 0xFF000000) >> 24
),
   IWX_UCODE_MINOR(le32toh(uhdr->ver))(((((__uint32_t)(uhdr->ver))) & 0x00FF0000) >> 16
),
   IWX_UCODE_API(le32toh(uhdr->ver))(((((__uint32_t)(uhdr->ver))) & 0x0000FF00) >> 8
));

data = uhdr->data;
len = fw->fw_rawsize - sizeof(*uhdr);

while (len >= sizeof(tlv)) {
size_t tlv_len;
void *tlv_data;

memcpy(&tlv, data, sizeof(tlv))__builtin_memcpy((&tlv), (data), (sizeof(tlv)));
tlv_len = le32toh(tlv.length)((__uint32_t)(tlv.length));
tlv_type = le32toh(tlv.type)((__uint32_t)(tlv.type));

len -= sizeof(tlv);
data += sizeof(tlv);
tlv_data = data;

if (len < tlv_len) {
	printf("%s: firmware too short: %zu bytes\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), len);
	err = EINVAL22;
	goto parse_out;
}

switch (tlv_type) {
case IWX_UCODE_TLV_PROBE_MAX_LEN6:
	if (tlv_len < sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	sc->sc_capa_max_probe_len
	    = le32toh(*(uint32_t *)tlv_data)((__uint32_t)(*(uint32_t *)tlv_data));
	if (sc->sc_capa_max_probe_len >
	    IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE512) {
		err = EINVAL22;
		goto parse_out;
	}
	break;
case IWX_UCODE_TLV_PAN7:
	if (tlv_len) {
		err = EINVAL22;
		goto parse_out;
	}
	sc->sc_capaflags |= IWX_UCODE_TLV_FLAGS_PAN(1 << 0);
	break;
case IWX_UCODE_TLV_FLAGS18:
	if (tlv_len < sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	/*
	 * Apparently there can be many flags, but Linux driver
	 * parses only the first one, and so do we.
	 *
	 * XXX: why does this override IWX_UCODE_TLV_PAN?
	 * Intentional or a bug?  Observations from
	 * current firmware file:
	 *  1) TLV_PAN is parsed first
	 *  2) TLV_FLAGS contains TLV_FLAGS_PAN
	 * ==> this resets TLV_PAN to itself... hnnnk
	 */
	sc->sc_capaflags = le32toh(*(uint32_t *)tlv_data)((__uint32_t)(*(uint32_t *)tlv_data));
	break;
case IWX_UCODE_TLV_CSCHEME28:
	err = iwx_store_cscheme(sc, tlv_data, tlv_len);
	if (err)
		goto parse_out;
	break;
case IWX_UCODE_TLV_NUM_OF_CPU27: {
	uint32_t num_cpu;
	if (tlv_len != sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	num_cpu = le32toh(*(uint32_t *)tlv_data)((__uint32_t)(*(uint32_t *)tlv_data));
	if (num_cpu < 1 || num_cpu > 2) {
		err = EINVAL22;
		goto parse_out;
	}
	break;
}
case IWX_UCODE_TLV_SEC_RT19:
	err = iwx_firmware_store_section(sc,
	    IWX_UCODE_TYPE_REGULAR, tlv_data, tlv_len);
	if (err)
		goto parse_out;
	break;
case IWX_UCODE_TLV_SEC_INIT20:
	err = iwx_firmware_store_section(sc,
	    IWX_UCODE_TYPE_INIT, tlv_data, tlv_len);
	if (err)
		goto parse_out;
	break;
case IWX_UCODE_TLV_SEC_WOWLAN21:
	err = iwx_firmware_store_section(sc,
	    IWX_UCODE_TYPE_WOW, tlv_data, tlv_len);
	if (err)
		goto parse_out;
	break;
case IWX_UCODE_TLV_DEF_CALIB22:
	if (tlv_len != sizeof(struct iwx_tlv_calib_data)) {
		err = EINVAL22;
		goto parse_out;
	}
	err = iwx_set_default_calib(sc, tlv_data);
	if (err)
		goto parse_out;
	break;
case IWX_UCODE_TLV_PHY_SKU23:
	if (tlv_len != sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data)((__uint32_t)(*(uint32_t *)tlv_data));
	break;

case IWX_UCODE_TLV_API_CHANGES_SET29: {
	struct iwx_ucode_api *api;
	int idx, i;
	if (tlv_len != sizeof(*api)) {
		err = EINVAL22;
		goto parse_out;
	}
	api = (struct iwx_ucode_api *)tlv_data;
	idx = le32toh(api->api_index)((__uint32_t)(api->api_index));
	if (idx >= howmany(IWX_NUM_UCODE_TLV_API, 32)(((128) + ((32) - 1)) / (32))) {
		err = EINVAL22;
		goto parse_out;
	}
	for (i = 0; i < 32; i++) {
		if ((le32toh(api->api_flags)((__uint32_t)(api->api_flags)) & (1 << i)) == 0)
			continue;
		setbit(sc->sc_ucode_api, i + (32 * idx))((sc->sc_ucode_api)[(i + (32 * idx))>>3] |= 1<<
((i + (32 * idx))&(8 -1)));
	}
	break;
}

case IWX_UCODE_TLV_ENABLED_CAPABILITIES30: {
	struct iwx_ucode_capa *capa;
	int idx, i;
	if (tlv_len != sizeof(*capa)) {
		err = EINVAL22;
		goto parse_out;
	}
	capa = (struct iwx_ucode_capa *)tlv_data;
	idx = le32toh(capa->api_index)((__uint32_t)(capa->api_index));
	if (idx >= howmany(IWX_NUM_UCODE_TLV_CAPA, 32)(((128) + ((32) - 1)) / (32))) {
		goto parse_out;
	}
	for (i = 0; i < 32; i++) {
		if ((le32toh(capa->api_capa)((__uint32_t)(capa->api_capa)) & (1 << i)) == 0)
			continue;
		setbit(sc->sc_enabled_capa, i + (32 * idx))((sc->sc_enabled_capa)[(i + (32 * idx))>>3] |= 1<<
((i + (32 * idx))&(8 -1)));
	}
	break;
}

case IWX_UCODE_TLV_SDIO_ADMA_ADDR35:
case IWX_UCODE_TLV_FW_GSCAN_CAPA50:
	/* ignore, not used by current driver */
	break;

case IWX_UCODE_TLV_SEC_RT_USNIFFER34:
	err = iwx_firmware_store_section(sc,
	    IWX_UCODE_TYPE_REGULAR_USNIFFER, tlv_data,
	    tlv_len);
	if (err)
		goto parse_out;
	break;

case IWX_UCODE_TLV_PAGING32:
	if (tlv_len != sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	break;

case IWX_UCODE_TLV_N_SCAN_CHANNELS31:
	if (tlv_len != sizeof(uint32_t)) {
		err = EINVAL22;
		goto parse_out;
	}
	sc->sc_capa_n_scan_channels =
	  le32toh(*(uint32_t *)tlv_data)((__uint32_t)(*(uint32_t *)tlv_data));
	if (sc->sc_capa_n_scan_channels > IWX_MAX_SCAN_CHANNELS67) {
		err = ERANGE34;
		goto parse_out;
	}
	break;

case IWX_UCODE_TLV_FW_VERSION36:
	if (tlv_len != sizeof(uint32_t) * 3) {
		err = EINVAL22;
		goto parse_out;
	}

	iwx_fw_version_str(sc->sc_fwver, sizeof(sc->sc_fwver),
	    le32toh(((uint32_t *)tlv_data)[0])((__uint32_t)(((uint32_t *)tlv_data)[0])),
	    le32toh(((uint32_t *)tlv_data)[1])((__uint32_t)(((uint32_t *)tlv_data)[1])),
	    le32toh(((uint32_t *)tlv_data)[2])((__uint32_t)(((uint32_t *)tlv_data)[2])));
	break;

case IWX_UCODE_TLV_FW_DBG_DEST38: {
	struct iwx_fw_dbg_dest_tlv_v1 *dest_v1 = NULL((void *)0);

	fw->dbg_dest_ver = (uint8_t *)tlv_data;
	if (*fw->dbg_dest_ver != 0) {
		err = EINVAL22;
		goto parse_out;
	}

	if (fw->dbg_dest_tlv_init)
		break;
	fw->dbg_dest_tlv_init = true1;

	dest_v1 = (void *)tlv_data;
	fw->dbg_dest_tlv_v1 = dest_v1;
	fw->n_dest_reg = tlv_len -
	    offsetof(struct iwx_fw_dbg_dest_tlv_v1, reg_ops)__builtin_offsetof(struct iwx_fw_dbg_dest_tlv_v1, reg_ops);
	fw->n_dest_reg /= sizeof(dest_v1->reg_ops[0]);
	DPRINTF(("%s: found debug dest; n_dest_reg=%d\n", __func__, fw->n_dest_reg))do { ; } while (0);
	break;
}

case IWX_UCODE_TLV_FW_DBG_CONF39: {
	struct iwx_fw_dbg_conf_tlv *conf = (void *)tlv_data;

	if (!fw->dbg_dest_tlv_init ||
	    conf->id >= nitems(fw->dbg_conf_tlv)(sizeof((fw->dbg_conf_tlv)) / sizeof((fw->dbg_conf_tlv)
[0])) ||
	    fw->dbg_conf_tlv[conf->id] != NULL((void *)0))
		break;

	DPRINTF(("Found debug configuration: %d\n", conf->id))do { ; } while (0);
	fw->dbg_conf_tlv[conf->id] = conf;
	fw->dbg_conf_tlv_len[conf->id] = tlv_len;
	break;
}

case IWX_UCODE_TLV_UMAC_DEBUG_ADDRS54: {
	struct iwx_umac_debug_addrs *dbg_ptrs =
		(void *)tlv_data;

	if (tlv_len != sizeof(*dbg_ptrs)) {
		err = EINVAL22;
		goto parse_out;
	}
	if (sc->sc_device_family < IWX_DEVICE_FAMILY_220001)
		break;
	sc->sc_uc.uc_umac_error_event_table =
		le32toh(dbg_ptrs->error_info_addr)((__uint32_t)(dbg_ptrs->error_info_addr)) &
		~IWX_FW_ADDR_CACHE_CONTROL0xC0000000;
	sc->sc_uc.error_event_table_tlv_status |=
		IWX_ERROR_EVENT_TABLE_UMAC(1 << 2);
	break;
}

case IWX_UCODE_TLV_LMAC_DEBUG_ADDRS55: {
	struct iwx_lmac_debug_addrs *dbg_ptrs =
		(void *)tlv_data;

	if (tlv_len != sizeof(*dbg_ptrs)) {
		err = EINVAL22;
		goto parse_out;
	}
	if (sc->sc_device_family < IWX_DEVICE_FAMILY_220001)
		break;
	sc->sc_uc.uc_lmac_error_event_table[0] =
		le32toh(dbg_ptrs->error_event_table_ptr)((__uint32_t)(dbg_ptrs->error_event_table_ptr)) &
		~IWX_FW_ADDR_CACHE_CONTROL0xC0000000;
	sc->sc_uc.error_event_table_tlv_status |=
		IWX_ERROR_EVENT_TABLE_LMAC1(1 << 0);
	break;
}

case IWX_UCODE_TLV_FW_MEM_SEG51:
	break;

case IWX_UCODE_TLV_IML52:
	if (sc->sc_fw.iml != NULL((void *)0)) {
		free(fw->iml, M_DEVBUF2, fw->iml_len);
		fw->iml_len = 0;
	}
	sc->sc_fw.iml = malloc(tlv_len, M_DEVBUF2,
	    M_WAIT0x0001 | M_CANFAIL0x0004 | M_ZERO0x0008);
	if (sc->sc_fw.iml == NULL((void *)0)) {
		err = ENOMEM12;
		goto parse_out;
	}
	memcpy(sc->sc_fw.iml, tlv_data, tlv_len)__builtin_memcpy((sc->sc_fw.iml), (tlv_data), (tlv_len));
	sc->sc_fw.iml_len = tlv_len;
	break;

case IWX_UCODE_TLV_CMD_VERSIONS48:
	if (tlv_len % sizeof(struct iwx_fw_cmd_version)) {
		tlv_len /= sizeof(struct iwx_fw_cmd_version);
		tlv_len *= sizeof(struct iwx_fw_cmd_version);
	}
	if (sc->n_cmd_versions != 0) {
		err = EINVAL22;
		goto parse_out;
	}
	if (tlv_len > sizeof(sc->cmd_versions)) {
		err = EINVAL22;
		goto parse_out;
	}
	memcpy(&sc->cmd_versions[0], tlv_data, tlv_len)__builtin_memcpy((&sc->cmd_versions[0]), (tlv_data), (
tlv_len));
	sc->n_cmd_versions = tlv_len / sizeof(struct iwx_fw_cmd_version);
	break;

case IWX_UCODE_TLV_FW_RECOVERY_INFO57:
	break;

case IWX_UCODE_TLV_FW_FSEQ_VERSION60:
case IWX_UCODE_TLV_PHY_INTEGRATION_VERSION61:
case IWX_UCODE_TLV_FW_NUM_STATIONS(0x100 + 0):
case IWX_UCODE_TLV_FW_NUM_BEACONS(0x100 + 2):
	break;

/* undocumented TLVs found in iwx-cc-a0-46 image */
case 58:
case 0x1000003:
case 0x1000004:
	break;

/* undocumented TLVs found in iwx-cc-a0-48 image */
case 0x1000000:
case 0x1000002:
	break;

case IWX_UCODE_TLV_TYPE_DEBUG_INFO(0x1000005 + 0):
case IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION(0x1000005 + 1):
case IWX_UCODE_TLV_TYPE_HCMD(0x1000005 + 2):
case IWX_UCODE_TLV_TYPE_REGIONS(0x1000005 + 3):
case IWX_UCODE_TLV_TYPE_TRIGGERS(0x1000005 + 4):
case IWX_UCODE_TLV_TYPE_CONF_SET(0x1000005 + 5):
case IWX_UCODE_TLV_SEC_TABLE_ADDR66:
case IWX_UCODE_TLV_D3_KEK_KCK_ADDR67:
case IWX_UCODE_TLV_CURRENT_PC68:
	break;

/* undocumented TLV found in iwx-cc-a0-67 image */
case 0x100000b:
	break;

/* undocumented TLV found in iwx-ty-a0-gf-a0-73 image */
case 0x101:
	break;

/* undocumented TLV found in iwx-ty-a0-gf-a0-77 image */
case 0x100000c:
	break;

default:
	err = EINVAL22;
	goto parse_out;
}

/*
 * Check for size_t overflow and ignore missing padding at
 * end of firmware file.
 */
if (roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4)) > len)
	break;

len -= roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
data += roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
}

KASSERT(err == 0)((err == 0) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_iwx.c"
, 1603, "err == 0"));

parse_out:
if (err) {
printf("%s: firmware parse error %d, "
    "section type %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), err, tlv_type);
}

out:
if (err) {
fw->fw_status = IWX_FW_STATUS_NONE0;
if (fw->fw_rawdata != NULL((void *)0))
	iwx_fw_info_free(fw);
} else
fw->fw_status = IWX_FW_STATUS_DONE2;
wakeup(&sc->sc_fw);

return err;
1621}

1623uint32_t
1624iwx_prph_addr_mask(struct iwx_softc *sc)
1625{
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
return 0x00ffffff;
else
return 0x000fffff;
1630}

1632uint32_t
1633iwx_read_prph_unlocked(struct iwx_softc *sc, uint32_t addr)
1634{
uint32_t mask = iwx_prph_addr_mask(sc);
IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_RADDR, ((addr & mask) | (3 << 24)))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x048
))), ((((addr & mask) | (3 << 24))))));
IWX_BARRIER_READ_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->
sc_sz, 0x01 | 0x02);
return IWX_READ(sc, IWX_HBUS_TARG_PRPH_RDAT)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((((0x400)+0x050
)))));
1639}

1641uint32_t
1642iwx_read_prph(struct iwx_softc *sc, uint32_t addr)
1643{
iwx_nic_assert_locked(sc);
return iwx_read_prph_unlocked(sc, addr);
1646}

1648void
1649iwx_write_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1650{
uint32_t mask = iwx_prph_addr_mask(sc);
IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_WADDR, ((addr & mask) | (3 << 24)))(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x044
))), ((((addr & mask) | (3 << 24))))));
IWX_BARRIER_WRITE(sc)bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->
sc_sz, 0x02);
IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_WDAT, val)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x04c
))), ((val))));
1655}

1657void
1658iwx_write_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1659{
iwx_nic_assert_locked(sc);
iwx_write_prph_unlocked(sc, addr, val);
1662}

1664void
1665iwx_write_prph64(struct iwx_softc *sc, uint64_t addr, uint64_t val)
1666{
iwx_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
iwx_write_prph(sc, (uint32_t)addr + 4, val >> 32);
1669}

1671uint32_t
1672iwx_read_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr)
1673{
return iwx_read_prph_unlocked(sc, addr + sc->sc_umac_prph_offset);
1675}

1677uint32_t
1678iwx_read_umac_prph(struct iwx_softc *sc, uint32_t addr)
1679{
return iwx_read_prph(sc, addr + sc->sc_umac_prph_offset);
1681}

1683void
1684iwx_write_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1685{
iwx_write_prph_unlocked(sc, addr + sc->sc_umac_prph_offset, val);
1687}

1689void
1690iwx_write_umac_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1691{
iwx_write_prph(sc, addr + sc->sc_umac_prph_offset, val);
1693}

1695int
1696iwx_read_mem(struct iwx_softc *sc, uint32_t addr, void *buf, int dwords)
1697{
int offs, err = 0;
uint32_t *vals = buf;

if (iwx_nic_lock(sc)) {
IWX_WRITE(sc, IWX_HBUS_TARG_MEM_RADDR, addr)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x00c
))), ((addr))));
for (offs = 0; offs < dwords; offs++)
	vals[offs] = le32toh(IWX_READ(sc, IWX_HBUS_TARG_MEM_RDAT))((__uint32_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x400)+0x01c)))))));
iwx_nic_unlock(sc);
} else {
err = EBUSY16;
}
return err;
1710}

1712int
1713iwx_write_mem(struct iwx_softc *sc, uint32_t addr, const void *buf, int dwords)
1714{
int offs;
const uint32_t *vals = buf;

if (iwx_nic_lock(sc)) {
IWX_WRITE(sc, IWX_HBUS_TARG_MEM_WADDR, addr)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x010
))), ((addr))));
/* WADDR auto-increments */
for (offs = 0; offs < dwords; offs++) {
	uint32_t val = vals ? vals[offs] : 0;
	IWX_WRITE(sc, IWX_HBUS_TARG_MEM_WDAT, val)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x400)+0x018
))), ((val))));
}
iwx_nic_unlock(sc);
} else {
return EBUSY16;
}
return 0;
1730}

1732int
1733iwx_write_mem32(struct iwx_softc *sc, uint32_t addr, uint32_t val)
1734{
return iwx_write_mem(sc, addr, &val, 1);
1736}

1738int
1739iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,
  int timo)
1741{
for (;;) {
if ((IWX_READ(sc, reg)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((reg)))) & mask) == (bits & mask)) {
	return 1;
}
if (timo < 10) {
	return 0;
}
timo -= 10;
DELAY(10)(*delay_func)(10);
}
1752}

1754int
1755iwx_nic_lock(struct iwx_softc *sc)
1756{
if (sc->sc_nic_locks > 0) {
iwx_nic_assert_locked(sc);
sc->sc_nic_locks++;
return 1; /* already locked */
}

IWX_SETBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x00000008))))))
   IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x00000008))))));

DELAY(2)(*delay_func)(2);

if (iwx_poll_bit(sc, IWX_CSR_GP_CNTRL(0x024),
   IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN(0x00000001),
   IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY(0x00000001)
    | IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP(0x00000010), 150000)) {
sc->sc_nic_locks++;
return 1;
}

printf("%s: acquiring device failed\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return 0;
1778}

1780void
1781iwx_nic_assert_locked(struct iwx_softc *sc)
1782{
if (sc->sc_nic_locks <= 0)
panic("%s: nic locks counter %d", DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_nic_locks);
1785}

1787void
1788iwx_nic_unlock(struct iwx_softc *sc)
1789{
if (sc->sc_nic_locks > 0) {
if (--sc->sc_nic_locks == 0)
	IWX_CLRBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000008))))))
	    IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000008))))));
} else
printf("%s: NIC already unlocked\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1796}

1798int
1799iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits,
  uint32_t mask)
1801{
uint32_t val;

if (iwx_nic_lock(sc)) {
val = iwx_read_prph(sc, reg) & mask;
val |= bits;
iwx_write_prph(sc, reg, val);
iwx_nic_unlock(sc);
return 0;
}
return EBUSY16;
1812}

1814int
1815iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)
1816{
return iwx_set_bits_mask_prph(sc, reg, bits, ~0);
1818}

1820int
1821iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)
1822{
return iwx_set_bits_mask_prph(sc, reg, 0, ~bits);
1824}

1826int
1827iwx_dma_contig_alloc(bus_dma_tag_t tag, struct iwx_dma_info *dma,
  bus_size_t size, bus_size_t alignment)
1829{
int nsegs, err;
caddr_t va;

dma->tag = tag;
dma->size = size;

err = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT,(*(tag)->_dmamap_create)((tag), (size), (1), (size), (0), (
0x0001), (&dma->map))
   &dma->map)(*(tag)->_dmamap_create)((tag), (size), (1), (size), (0), (
0x0001), (&dma->map));
if (err)
goto fail;

err = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs,(*(tag)->_dmamem_alloc)((tag), (size), (alignment), (0), (
&dma->seg), (1), (&nsegs), (0x0001 | 0x1000))
   BUS_DMA_NOWAIT | BUS_DMA_ZERO)(*(tag)->_dmamem_alloc)((tag), (size), (alignment), (0), (
&dma->seg), (1), (&nsegs), (0x0001 | 0x1000));
if (err)
goto fail;

if (nsegs > 1) {
err = ENOMEM12;
goto fail;
}

err = bus_dmamem_map(tag, &dma->seg, 1, size, &va,(*(tag)->_dmamem_map)((tag), (&dma->seg), (1), (size
), (&va), (0x0001 | 0x0004))
   BUS_DMA_NOWAIT | BUS_DMA_COHERENT)(*(tag)->_dmamem_map)((tag), (&dma->seg), (1), (size
), (&va), (0x0001 | 0x0004));
if (err)
goto fail;
dma->vaddr = va;

err = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL,(*(tag)->_dmamap_load)((tag), (dma->map), (dma->vaddr
), (size), (((void *)0)), (0x0001))
   BUS_DMA_NOWAIT)(*(tag)->_dmamap_load)((tag), (dma->map), (dma->vaddr
), (size), (((void *)0)), (0x0001));
if (err)
goto fail;

bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE)(*(tag)->_dmamap_sync)((tag), (dma->map), (0), (size), (
0x04));
dma->paddr = dma->map->dm_segs[0].ds_addr;

return 0;

1867fail:	iwx_dma_contig_free(dma);
return err;
1869}

1871void
1872iwx_dma_contig_free(struct iwx_dma_info *dma)
1873{
if (dma->map != NULL((void *)0)) {
if (dma->vaddr != NULL((void *)0)) {
	bus_dmamap_sync(dma->tag, dma->map, 0, dma->size,(*(dma->tag)->_dmamap_sync)((dma->tag), (dma->map
), (0), (dma->size), (0x02 | 0x08))
	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(dma->tag)->_dmamap_sync)((dma->tag), (dma->map
), (0), (dma->size), (0x02 | 0x08));
	bus_dmamap_unload(dma->tag, dma->map)(*(dma->tag)->_dmamap_unload)((dma->tag), (dma->map
));
	bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size)(*(dma->tag)->_dmamem_unmap)((dma->tag), (dma->vaddr
), (dma->size));
	bus_dmamem_free(dma->tag, &dma->seg, 1)(*(dma->tag)->_dmamem_free)((dma->tag), (&dma->
seg), (1));
	dma->vaddr = NULL((void *)0);
}
bus_dmamap_destroy(dma->tag, dma->map)(*(dma->tag)->_dmamap_destroy)((dma->tag), (dma->
map));
dma->map = NULL((void *)0);
}
1886}

1888int
1889iwx_alloc_rx_ring(struct iwx_softc *sc, struct iwx_rx_ring *ring)
1890{
bus_size_t size;
int i, err;

ring->cur = 0;

/* Allocate RX descriptors (256-byte aligned). */
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
size = sizeof(struct iwx_rx_transfer_desc);
else
size = sizeof(uint64_t);
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->free_desc_dma,
   size * IWX_RX_MQ_RING_COUNT512, 256);
if (err) {
printf("%s: could not allocate RX ring DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}
ring->desc = ring->free_desc_dma.vaddr;

/* Allocate RX status area (16-byte aligned). */
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
size = sizeof(uint16_t);
else
size = sizeof(*ring->stat);
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, size, 16);
if (err) {
printf("%s: could not allocate RX status DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}
ring->stat = ring->stat_dma.vaddr;

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
size = sizeof(struct iwx_rx_completion_desc);
else
size = sizeof(uint32_t);
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->used_desc_dma,
   size * IWX_RX_MQ_RING_COUNT512, 256);
if (err) {
printf("%s: could not allocate RX ring DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

for (i = 0; i < IWX_RX_MQ_RING_COUNT512; i++) {
struct iwx_rx_data *data = &ring->data[i];

memset(data, 0, sizeof(*data))__builtin_memset((data), (0), (sizeof(*data)));
err = bus_dmamap_create(sc->sc_dmat, IWX_RBUF_SIZE, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (4096
), (1), (4096), (0), (0x0001 | 0x0002), (&data->map))
    IWX_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (4096
), (1), (4096), (0), (0x0001 | 0x0002), (&data->map))
    &data->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (4096
), (1), (4096), (0), (0x0001 | 0x0002), (&data->map));
if (err) {
	printf("%s: could not create RX buf DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}

err = iwx_rx_addbuf(sc, IWX_RBUF_SIZE4096, i);
if (err)
	goto fail;
}
return 0;

1954fail:	iwx_free_rx_ring(sc, ring);
return err;
1956}

1958void
1959iwx_disable_rx_dma(struct iwx_softc *sc)
1960{
int ntries;

if (iwx_nic_lock(sc)) {
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
	iwx_write_umac_prph(sc, IWX_RFH_RXF_DMA_CFG_GEN30xA07880, 0);
else
	iwx_write_prph(sc, IWX_RFH_RXF_DMA_CFG0xA09820, 0);
for (ntries = 0; ntries < 1000; ntries++) {
	if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
		if (iwx_read_umac_prph(sc,
		    IWX_RFH_GEN_STATUS_GEN30xA07824) & IWX_RXF_DMA_IDLE(1U << 31))
			break;
	} else {
		if (iwx_read_prph(sc, IWX_RFH_GEN_STATUS0xA09808) &
		    IWX_RXF_DMA_IDLE(1U << 31))
			break;
	}
	DELAY(10)(*delay_func)(10);
}
iwx_nic_unlock(sc);
}
1982}

1984void
1985iwx_reset_rx_ring(struct iwx_softc *sc, struct iwx_rx_ring *ring)
1986{
ring->cur = 0;
bus_dmamap_sync(sc->sc_dmat, ring->stat_dma.map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
stat_dma.map), (0), (ring->stat_dma.size), (0x04))
   ring->stat_dma.size, BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
stat_dma.map), (0), (ring->stat_dma.size), (0x04));
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
uint16_t *status = sc->rxq.stat_dma.vaddr;
*status = 0;
} else
memset(ring->stat, 0, sizeof(*ring->stat))__builtin_memset((ring->stat), (0), (sizeof(*ring->stat
)));
bus_dmamap_sync(sc->sc_dmat, ring->stat_dma.map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
stat_dma.map), (0), (ring->stat_dma.size), (0x08))
   ring->stat_dma.size, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
stat_dma.map), (0), (ring->stat_dma.size), (0x08));

1998}

2000void
2001iwx_free_rx_ring(struct iwx_softc *sc, struct iwx_rx_ring *ring)
2002{
int i;

iwx_dma_contig_free(&ring->free_desc_dma);
iwx_dma_contig_free(&ring->stat_dma);
iwx_dma_contig_free(&ring->used_desc_dma);

for (i = 0; i < IWX_RX_MQ_RING_COUNT512; i++) {
struct iwx_rx_data *data = &ring->data[i];

if (data->m != NULL((void *)0)) {
	bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02))
	    data->map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map));
	m_freem(data->m);
	data->m = NULL((void *)0);
}
if (data->map != NULL((void *)0))
	bus_dmamap_destroy(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (data
->map));
}
2022}

2024int
2025iwx_alloc_tx_ring(struct iwx_softc *sc, struct iwx_tx_ring *ring, int qid)
2026{
bus_addr_t paddr;
bus_size_t size;
int i, err;
size_t bc_tbl_size;
bus_size_t bc_align;

ring->qid = qid;
ring->queued = 0;
ring->cur = 0;
ring->cur_hw = 0;
ring->tail = 0;
ring->tail_hw = 0;

/* Allocate TX descriptors (256-byte aligned). */
size = IWX_TX_RING_COUNT(256) * sizeof(struct iwx_tfh_tfd);
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256);
if (err) {
printf("%s: could not allocate TX ring DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}
ring->desc = ring->desc_dma.vaddr;

/*
* The hardware supports up to 512 Tx rings which is more
* than we currently need.
*
* In DQA mode we use 1 command queue + 1 default queue for
* management, control, and non-QoS data frames.
* The command is queue sc->txq[0], our default queue is sc->txq[1].
*
* Tx aggregation requires additional queues, one queue per TID for
* which aggregation is enabled. We map TID 0-7 to sc->txq[2:9].
* Firmware may assign its own internal IDs for these queues
* depending on which TID gets aggregation enabled first.
* The driver maintains a table mapping driver-side queue IDs
* to firmware-side queue IDs.
*/

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
bc_tbl_size = sizeof(struct iwx_gen3_bc_tbl_entry) *
    IWX_TFD_QUEUE_BC_SIZE_GEN3_AX2101024;
bc_align = 128;
} else {
bc_tbl_size = sizeof(struct iwx_agn_scd_bc_tbl);
bc_align = 64;
}
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->bc_tbl, bc_tbl_size,
   bc_align);
if (err) {
printf("%s: could not allocate byte count table DMA memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

size = IWX_TX_RING_COUNT(256) * sizeof(struct iwx_device_cmd);
err = iwx_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, size,
   IWX_FIRST_TB_SIZE_ALIGN((20 + (64 - 1)) & ~(64 - 1)));
if (err) {
printf("%s: could not allocate cmd DMA memory\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}
ring->cmd = ring->cmd_dma.vaddr;

paddr = ring->cmd_dma.paddr;
for (i = 0; i < IWX_TX_RING_COUNT(256); i++) {
struct iwx_tx_data *data = &ring->data[i];
size_t mapsize;

data->cmd_paddr = paddr;
paddr += sizeof(struct iwx_device_cmd);

/* FW commands may require more mapped space than packets. */
if (qid == IWX_DQA_CMD_QUEUE0)
	mapsize = (sizeof(struct iwx_cmd_header) +
	    IWX_MAX_CMD_PAYLOAD_SIZE(4096 - sizeof(struct iwx_cmd_header_wide)));
else
	mapsize = MCLBYTES(1 << 11);
err = bus_dmamap_create(sc->sc_dmat, mapsize,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mapsize
), (25 - 2), (mapsize), (0), (0x0001), (&data->map))
    IWX_TFH_NUM_TBS - 2, mapsize, 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mapsize
), (25 - 2), (mapsize), (0), (0x0001), (&data->map))
    &data->map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mapsize
), (25 - 2), (mapsize), (0), (0x0001), (&data->map));
if (err) {
	printf("%s: could not create TX buf DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}
}
KASSERT(paddr == ring->cmd_dma.paddr + size)((paddr == ring->cmd_dma.paddr + size) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/if_iwx.c", 2114, "paddr == ring->cmd_dma.paddr + size"
));
return 0;

2117fail:	iwx_free_tx_ring(sc, ring);
return err;
2119}

2121void
2122iwx_reset_tx_ring(struct iwx_softc *sc, struct iwx_tx_ring *ring)
2123{
int i;

for (i = 0; i < IWX_TX_RING_COUNT(256); i++) {
struct iwx_tx_data *data = &ring->data[i];

if (data->m != NULL((void *)0)) {
	bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
	    data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08));
	bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map));
	m_freem(data->m);
	data->m = NULL((void *)0);
}
}

/* Clear byte count table. */
memset(ring->bc_tbl.vaddr, 0, ring->bc_tbl.size)__builtin_memset((ring->bc_tbl.vaddr), (0), (ring->bc_tbl
.size));

/* Clear TX descriptors. */
memset(ring->desc, 0, ring->desc_dma.size)__builtin_memset((ring->desc), (0), (ring->desc_dma.size
));
bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
desc_dma.map), (0), (ring->desc_dma.size), (0x04))
   ring->desc_dma.size, BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
desc_dma.map), (0), (ring->desc_dma.size), (0x04));
sc->qfullmsk &= ~(1 << ring->qid);
sc->qenablemsk &= ~(1 << ring->qid);
for (i = 0; i < nitems(sc->aggqid)(sizeof((sc->aggqid)) / sizeof((sc->aggqid)[0])); i++) {
if (sc->aggqid[i] == ring->qid) {
	sc->aggqid[i] = 0;
	break;
}
}
ring->queued = 0;
ring->cur = 0;
ring->cur_hw = 0;
ring->tail = 0;
ring->tail_hw = 0;
ring->tid = 0;
2159}

2161void
2162iwx_free_tx_ring(struct iwx_softc *sc, struct iwx_tx_ring *ring)
2163{
int i;

iwx_dma_contig_free(&ring->desc_dma);
iwx_dma_contig_free(&ring->cmd_dma);
iwx_dma_contig_free(&ring->bc_tbl);

for (i = 0; i < IWX_TX_RING_COUNT(256); i++) {
struct iwx_tx_data *data = &ring->data[i];

if (data->m != NULL((void *)0)) {
	bus_dmamap_sync(sc->sc_dmat, data->map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08))
	    data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (data->map->dm_mapsize), (0x08));
	bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map));
	m_freem(data->m);
	data->m = NULL((void *)0);
}
if (data->map != NULL((void *)0))
	bus_dmamap_destroy(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (data
->map));
}
2183}

2185void
2186iwx_enable_rfkill_int(struct iwx_softc *sc)
2187{
if (!sc->sc_msix) {
sc->sc_intmask = IWX_CSR_INT_BIT_RF_KILL(1 << 7);
IWX_WRITE(sc, IWX_CSR_INT_MASK, sc->sc_intmask)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x00c))), (
(sc->sc_intmask))));
} else {
IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((sc->sc_fh_init_mask))))
    sc->sc_fh_init_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((sc->sc_fh_init_mask))));
IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL))))
    ~IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL))));
sc->sc_hw_mask = IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL;
}

IWX_SETBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x04000000))))))
   IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x04000000))))));
2201}

2203int
2204iwx_check_rfkill(struct iwx_softc *sc)
2205{
uint32_t v;
int rv;

/*
* "documentation" is not really helpful here:
*  27:	HW_RF_KILL_SW
*	Indicates state of (platform's) hardware RF-Kill switch
*
* But apparently when it's off, it's on ...
*/
v = IWX_READ(sc, IWX_CSR_GP_CNTRL)(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))));
rv = (v & IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW(0x08000000)) == 0;
if (rv) {
sc->sc_flags |= IWX_FLAG_RFKILL0x02;
} else {
sc->sc_flags &= ~IWX_FLAG_RFKILL0x02;
}

return rv;
2225}

2227void
2228iwx_enable_interrupts(struct iwx_softc *sc)
2229{
if (!sc->sc_msix) {
sc->sc_intmask = IWX_CSR_INI_SET_MASK((1U << 31) | (1 << 29) | (1 << 27) | (1 <<
 25) | (1 << 7) | (1 << 3) | (1 << 1) | (1 <<
 0) | (1 << 28));
IWX_WRITE(sc, IWX_CSR_INT_MASK, sc->sc_intmask)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x00c))), (
(sc->sc_intmask))));
} else {
/*
 * fh/hw_mask keeps all the unmasked causes.
 * Unlike msi, in msix cause is enabled when it is unset.
 */
sc->sc_hw_mask = sc->sc_hw_init_mask;
sc->sc_fh_mask = sc->sc_fh_init_mask;
IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((~sc->sc_fh_mask))))
    ~sc->sc_fh_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((~sc->sc_fh_mask))));
IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~sc->sc_hw_mask))))
    ~sc->sc_hw_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~sc->sc_hw_mask))));
}
2245}

2247void
2248iwx_enable_fwload_interrupt(struct iwx_softc *sc)
2249{
if (!sc->sc_msix) {
sc->sc_intmask = IWX_CSR_INT_BIT_ALIVE(1 << 0) | IWX_CSR_INT_BIT_FH_RX(1U << 31);
IWX_WRITE(sc, IWX_CSR_INT_MASK, sc->sc_intmask)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x00c))), (
(sc->sc_intmask))));
} else {
IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~IWX_MSIX_HW_INT_CAUSES_REG_ALIVE))))
    ~IWX_MSIX_HW_INT_CAUSES_REG_ALIVE)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~IWX_MSIX_HW_INT_CAUSES_REG_ALIVE))));
sc->sc_hw_mask = IWX_MSIX_HW_INT_CAUSES_REG_ALIVE;
/*
 * Leave all the FH causes enabled to get the ALIVE
 * notification.
 */
IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((~sc->sc_fh_init_mask))))
    ~sc->sc_fh_init_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((~sc->sc_fh_init_mask))));
sc->sc_fh_mask = sc->sc_fh_init_mask;
}
2265}

2267void
2268iwx_restore_interrupts(struct iwx_softc *sc)
2269{
IWX_WRITE(sc, IWX_CSR_INT_MASK, sc->sc_intmask)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x00c))), (
(sc->sc_intmask))));
2271}

2273void
2274iwx_disable_interrupts(struct iwx_softc *sc)
2275{
if (!sc->sc_msix) {
IWX_WRITE(sc, IWX_CSR_INT_MASK, 0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x00c))), (
(0))));

/* acknowledge all interrupts */
IWX_WRITE(sc, IWX_CSR_INT, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x008))), (
(~0))));
IWX_WRITE(sc, IWX_CSR_FH_INT_STATUS, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x010))), (
(~0))));
} else {
IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((sc->sc_fh_init_mask))))
    sc->sc_fh_init_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((sc->sc_fh_init_mask))));
IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((sc->sc_hw_init_mask))))
    sc->sc_hw_init_mask)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((sc->sc_hw_init_mask))));
}
2288}

2290void
2291iwx_ict_reset(struct iwx_softc *sc)
2292{
iwx_disable_interrupts(sc);

memset(sc->ict_dma.vaddr, 0, IWX_ICT_SIZE)__builtin_memset((sc->ict_dma.vaddr), (0), (4096));
sc->ict_cur = 0;

/* Set physical address of ICT (4KB aligned). */
IWX_WRITE(sc, IWX_CSR_DRAM_INT_TBL_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A0))), (
((1U << 31) | (1 << 27) | (1 << 28) | sc->
ict_dma.paddr >> 12))))
   IWX_CSR_DRAM_INT_TBL_ENABLE(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A0))), (
((1U << 31) | (1 << 27) | (1 << 28) | sc->
ict_dma.paddr >> 12))))
   | IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A0))), (
((1U << 31) | (1 << 27) | (1 << 28) | sc->
ict_dma.paddr >> 12))))
   | IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A0))), (
((1U << 31) | (1 << 27) | (1 << 28) | sc->
ict_dma.paddr >> 12))))
   | sc->ict_dma.paddr >> IWX_ICT_PADDR_SHIFT)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A0))), (
((1U << 31) | (1 << 27) | (1 << 28) | sc->
ict_dma.paddr >> 12))));

/* Switch to ICT interrupt mode in driver. */
sc->sc_flags |= IWX_FLAG_USE_ICT0x01;

IWX_WRITE(sc, IWX_CSR_INT, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x008))), (
(~0))));
iwx_enable_interrupts(sc);
2310}

2312#define IWX_HW_READY_TIMEOUT 50
2313int
2314iwx_set_hw_ready(struct iwx_softc *sc)
2315{
int ready;

IWX_SETBITS(sc, IWX_CSR_HW_IF_CONFIG_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x00400000))))))
   IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x00400000))))));

ready = iwx_poll_bit(sc, IWX_CSR_HW_IF_CONFIG_REG(0x000),
   IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY(0x00400000),
   IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY(0x00400000),
   IWX_HW_READY_TIMEOUT);
if (ready)
IWX_SETBITS(sc, IWX_CSR_MBOX_SET_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x088))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x088)))))
 | (0x20)))))
    IWX_CSR_MBOX_SET_REG_OS_ALIVE)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x088))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x088)))))
 | (0x20)))));

return ready;
2330}
2331#undef IWX_HW_READY_TIMEOUT

2333int
2334iwx_prepare_card_hw(struct iwx_softc *sc)
2335{
int t = 0;
int ntries;

if (iwx_set_hw_ready(sc))
return 0;

IWX_SETBITS(sc, IWX_CSR_DBG_LINK_PWR_MGMT_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 | ((0x80000000))))))
   IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 | ((0x80000000))))));
DELAY(1000)(*delay_func)(1000);

for (ntries = 0; ntries < 10; ntries++) {
/* If HW is not ready, prepare the conditions to check again */
IWX_SETBITS(sc, IWX_CSR_HW_IF_CONFIG_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x08000000))))))
    IWX_CSR_HW_IF_CONFIG_REG_PREPARE)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x08000000))))));

do {
	if (iwx_set_hw_ready(sc))
		return 0;
	DELAY(200)(*delay_func)(200);
	t += 200;
} while (t < 150000);
DELAY(25000)(*delay_func)(25000);
}

return ETIMEDOUT60;
2361}

2363int
2364iwx_force_power_gating(struct iwx_softc *sc)
2365{
int err;

err = iwx_set_bits_prph(sc, IWX_HPM_HIPM_GEN_CFG0xa03458,
   IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE(1 << 10));
if (err)
return err;
DELAY(20)(*delay_func)(20);
err = iwx_set_bits_prph(sc, IWX_HPM_HIPM_GEN_CFG0xa03458,
   IWX_HPM_HIPM_GEN_CFG_CR_PG_EN(1 << 0) |
   IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN(1 << 1));
if (err)
return err;
DELAY(20)(*delay_func)(20);
err = iwx_clear_bits_prph(sc, IWX_HPM_HIPM_GEN_CFG0xa03458,
   IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE(1 << 10));
return err;
2382}

2384void
2385iwx_apm_config(struct iwx_softc *sc)
2386{
pcireg_t lctl, cap;

/*
* L0S states have been found to be unstable with our devices
* and in newer hardware they are not officially supported at
* all, so we must always set the L0S_DISABLED bit.
*/
IWX_SETBITS(sc, IWX_CSR_GIO_REG, IWX_CSR_GIO_REG_VAL_L0S_DISABLED)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x03C))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x03C)))))
 | ((0x00000002))))));

lctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
   sc->sc_cap_off + PCI_PCIE_LCSR0x10);
sc->sc_pm_support = !(lctl & PCI_PCIE_LCSR_ASPM_L0S0x00000001);
cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
   sc->sc_cap_off + PCI_PCIE_DCSR20x28);
sc->sc_ltr_enabled = (cap & PCI_PCIE_DCSR2_LTREN0x00000400) ? 1 : 0;
DPRINTF(("%s: L1 %sabled - LTR %sabled\n",do { ; } while (0)
   DEVNAME(sc),do { ; } while (0)
   (lctl & PCI_PCIE_LCSR_ASPM_L1) ? "En" : "Dis",do { ; } while (0)
   sc->sc_ltr_enabled ? "En" : "Dis"))do { ; } while (0);
2406}

2408/*
* Start up NIC's basic functionality after it has been reset
* e.g. after platform boot or shutdown.
* NOTE:  This does not load uCode nor start the embedded processor
*/
2413int
2414iwx_apm_init(struct iwx_softc *sc)
2415{
int err = 0;

/*
* Disable L0s without affecting L1;
*  don't wait for ICH L0s (ICH bug W/A)
*/
IWX_SETBITS(sc, IWX_CSR_GIO_CHICKEN_BITS,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x100))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x100)))))
 | ((0x00800000))))))
   IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x100))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x100)))))
 | ((0x00800000))))));

/* Set FH wait threshold to maximum (HW error during stress W/A) */
IWX_SETBITS(sc, IWX_CSR_DBG_HPET_MEM_REG, IWX_CSR_DBG_HPET_MEM_REG_VAL)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x240))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x240)))))
 | ((0xFFFF0000))))));

/*
* Enable HAP INTA (interrupt from management bus) to
* wake device's PCI Express link L1a -> L0s
*/
IWX_SETBITS(sc, IWX_CSR_HW_IF_CONFIG_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x00080000))))))
   IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x00080000))))));

iwx_apm_config(sc);

/*
* Set "initialization complete" bit to move adapter from
* D0U* --> D0A* (powered-up active) state.
*/
IWX_SETBITS(sc, IWX_CSR_GP_CNTRL, IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x00000004))))));

/*
* Wait for clock stabilization; once stabilized, access to
* device-internal resources is supported, e.g. iwx_write_prph()
* and accesses to uCode SRAM.
*/
if (!iwx_poll_bit(sc, IWX_CSR_GP_CNTRL(0x024),
   IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY(0x00000001),
   IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY(0x00000001), 25000)) {
printf("%s: timeout waiting for clock stabilization\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
err = ETIMEDOUT60;
goto out;
}
out:
if (err)
printf("%s: apm init error %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), err);
return err;
2460}

2462void
2463iwx_apm_stop(struct iwx_softc *sc)
2464{
IWX_SETBITS(sc, IWX_CSR_DBG_LINK_PWR_MGMT_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 | ((0x80000000))))))
   IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 | ((0x80000000))))));
IWX_SETBITS(sc, IWX_CSR_HW_IF_CONFIG_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x08000000) | (0x10000000))))))
   IWX_CSR_HW_IF_CONFIG_REG_PREPARE |(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x08000000) | (0x10000000))))))
   IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))))
 | ((0x08000000) | (0x10000000))))));
DELAY(1000)(*delay_func)(1000);
IWX_CLRBITS(sc, IWX_CSR_DBG_LINK_PWR_MGMT_REG,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 & ~((0x80000000))))))
   IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x250))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x250)))))
 & ~((0x80000000))))));
DELAY(5000)(*delay_func)(5000);

/* stop device's busmaster DMA activity */
IWX_SETBITS(sc, IWX_CSR_RESET, IWX_CSR_RESET_REG_FLAG_STOP_MASTER)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x020))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x020)))))
 | ((0x00000200))))));

if (!iwx_poll_bit(sc, IWX_CSR_RESET(0x020),
   IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED(0x00000100),
   IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED(0x00000100), 100))
printf("%s: timeout waiting for master\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));

/*
* Clear "initialization complete" bit to move adapter from
* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
*/
IWX_CLRBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000004))))))
   IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000004))))));
2489}

2491void
2492iwx_init_msix_hw(struct iwx_softc *sc)
2493{
iwx_conf_msix_hw(sc, 0);

if (!sc->sc_msix)
return;

sc->sc_fh_init_mask = ~IWX_READ(sc, IWX_CSR_MSIX_FH_INT_MASK_AD)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((((0x2000) + 0x804
)))));
sc->sc_fh_mask = sc->sc_fh_init_mask;
sc->sc_hw_init_mask = ~IWX_READ(sc, IWX_CSR_MSIX_HW_INT_MASK_AD)(((sc)->sc_st)->read_4(((sc)->sc_sh), ((((0x2000) + 0x80C
)))));
sc->sc_hw_mask = sc->sc_hw_init_mask;
2503}

2505void
2506iwx_conf_msix_hw(struct iwx_softc *sc, int stopped)
2507{
int vector = 0;

if (!sc->sc_msix) {
/* Newer chips default to MSIX. */
if (!stopped && iwx_nic_lock(sc)) {
	iwx_write_umac_prph(sc, IWX_UREG_CHICK0xa05c00,
	    IWX_UREG_CHICK_MSI_ENABLE(1 << 24));
	iwx_nic_unlock(sc);
}
return;
}

if (!stopped && iwx_nic_lock(sc)) {
iwx_write_umac_prph(sc, IWX_UREG_CHICK0xa05c00,
    IWX_UREG_CHICK_MSIX_ENABLE(1 << 25));
iwx_nic_unlock(sc);
}

/* Disable all interrupts */
IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), ((~0))));
IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), ((~0))));

/* Map fallback-queue (command/mgmt) to a single vector */
IWX_WRITE_1(sc, IWX_CSR_MSIX_RX_IVAR(0),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x880) + (0)))), ((vector | (1 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x880) + (0)))), ((vector | (1 << 7)))));
/* Map RSS queue (data) to the same vector */
IWX_WRITE_1(sc, IWX_CSR_MSIX_RX_IVAR(1),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x880) + (1)))), ((vector | (1 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x880) + (1)))), ((vector | (1 << 7)))));

/* Enable the RX queues cause interrupts */
IWX_CLRBITS(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_Q0 | IWX_MSIX_FH_INT_CAUSES_Q1
)))))
   IWX_MSIX_FH_INT_CAUSES_Q0 | IWX_MSIX_FH_INT_CAUSES_Q1)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_Q0 | IWX_MSIX_FH_INT_CAUSES_Q1
)))));

/* Map non-RX causes to the same vector */
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM)))), ((vector | (1
 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM)))), ((vector | (1
 << 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM)))), ((vector | (1
 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM)))), ((vector | (1
 << 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_S2D),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_S2D)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_S2D)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_FH_ERR),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_FH_ERR)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_FH_ERR)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_ALIVE),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_ALIVE)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_ALIVE)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_WAKEUP),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_WAKEUP)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_WAKEUP)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE)))), ((vector |
 (1 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE)))), ((vector |
 (1 << 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_CT_KILL),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_CT_KILL)))), ((vector | (1
 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_CT_KILL)))), ((vector | (1
 << 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_RF_KILL),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_RF_KILL)))), ((vector | (1
 << 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_RF_KILL)))), ((vector | (1
 << 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_PERIODIC),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_PERIODIC)))), ((vector | (
<< 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_PERIODIC)))), ((vector | (
<< 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_SW_ERR),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_SW_ERR)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_SW_ERR)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_SCD),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_SCD)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_SCD)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_FH_TX),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_FH_TX)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_FH_TX)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_HW_ERR),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_HW_ERR)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_HW_ERR)))), ((vector | (1 <<
 7)))));
IWX_WRITE_1(sc, IWX_CSR_MSIX_IVAR(IWX_MSIX_IVAR_CAUSE_REG_HAP),(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_HAP)))), ((vector | (1 <<
 7)))))
   vector | IWX_MSIX_NON_AUTO_CLEAR_CAUSE)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((((0x2000) +
 0x890) + (IWX_MSIX_IVAR_CAUSE_REG_HAP)))), ((vector | (1 <<
 7)))));

/* Enable non-RX causes interrupts */
IWX_CLRBITS(sc, IWX_CSR_MSIX_FH_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
 | IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM | IWX_MSIX_FH_INT_CAUSES_S2D
 | IWX_MSIX_FH_INT_CAUSES_FH_ERR)))))
   IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
 | IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM | IWX_MSIX_FH_INT_CAUSES_S2D
 | IWX_MSIX_FH_INT_CAUSES_FH_ERR)))))
   IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
 | IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM | IWX_MSIX_FH_INT_CAUSES_S2D
 | IWX_MSIX_FH_INT_CAUSES_FH_ERR)))))
   IWX_MSIX_FH_INT_CAUSES_S2D |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
 | IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM | IWX_MSIX_FH_INT_CAUSES_S2D
 | IWX_MSIX_FH_INT_CAUSES_FH_ERR)))))
   IWX_MSIX_FH_INT_CAUSES_FH_ERR)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x804))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x804))))) & ~(IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
 | IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM | IWX_MSIX_FH_INT_CAUSES_S2D
 | IWX_MSIX_FH_INT_CAUSES_FH_ERR)))));
IWX_CLRBITS(sc, IWX_CSR_MSIX_HW_INT_MASK_AD,(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_ALIVE |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_SCD |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_FH_TX |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR |(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))))
   IWX_MSIX_HW_INT_CAUSES_REG_HAP)(((sc)->sc_st)->write_4(((sc)->sc_sh), ((((0x2000) +
 0x80C))), (((((sc)->sc_st)->read_4(((sc)->sc_sh), (
(((0x2000) + 0x80C))))) & ~(IWX_MSIX_HW_INT_CAUSES_REG_ALIVE
 | IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP | IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE
 | IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL | IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL
 | IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC | IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR
 | IWX_MSIX_HW_INT_CAUSES_REG_SCD | IWX_MSIX_HW_INT_CAUSES_REG_FH_TX
 | IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR | IWX_MSIX_HW_INT_CAUSES_REG_HAP
)))));
2591}

2593int
2594iwx_clear_persistence_bit(struct iwx_softc *sc)
2595{
uint32_t hpm, wprot;

hpm = iwx_read_prph_unlocked(sc, IWX_HPM_DEBUG0xa03440);
if (hpm != 0xa5a5a5a0 && (hpm & IWX_PERSISTENCE_BIT(1 << 12))) {
wprot = iwx_read_prph_unlocked(sc, IWX_PREG_PRPH_WPROT_220000xa04d00);
if (wprot & IWX_PREG_WFPM_ACCESS(1 << 12)) {
	printf("%s: cannot clear persistence bit\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return EPERM1;
}
iwx_write_prph_unlocked(sc, IWX_HPM_DEBUG0xa03440,
    hpm & ~IWX_PERSISTENCE_BIT(1 << 12));
}

return 0;
2611}

2613int
2614iwx_start_hw(struct iwx_softc *sc)
2615{
int err;

err = iwx_prepare_card_hw(sc);
if (err)
return err;

if (sc->sc_device_family == IWX_DEVICE_FAMILY_220001) {
err = iwx_clear_persistence_bit(sc);
if (err)
	return err;
}

/* Reset the entire device */
IWX_SETBITS(sc, IWX_CSR_RESET, IWX_CSR_RESET_REG_FLAG_SW_RESET)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x020))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x020)))))
 | ((0x00000080))))));
DELAY(5000)(*delay_func)(5000);

if (sc->sc_device_family == IWX_DEVICE_FAMILY_220001 &&
   sc->sc_integrated) {
IWX_SETBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x00000004))))))
    IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 | ((0x00000004))))));
DELAY(20)(*delay_func)(20);
if (!iwx_poll_bit(sc, IWX_CSR_GP_CNTRL(0x024),
    IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY(0x00000001),
    IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY(0x00000001), 25000)) {
	printf("%s: timeout waiting for clock stabilization\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return ETIMEDOUT60;
}

err = iwx_force_power_gating(sc);
if (err)
	return err;

/* Reset the entire device */
IWX_SETBITS(sc, IWX_CSR_RESET, IWX_CSR_RESET_REG_FLAG_SW_RESET)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x020))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x020)))))
 | ((0x00000080))))));
DELAY(5000)(*delay_func)(5000);
}

err = iwx_apm_init(sc);
if (err)
return err;

iwx_init_msix_hw(sc);

iwx_enable_rfkill_int(sc);
iwx_check_rfkill(sc);

return 0;
2664}

2666void
2667iwx_stop_device(struct iwx_softc *sc)
2668{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni = ic->ic_bss;
int i;

iwx_disable_interrupts(sc);
sc->sc_flags &= ~IWX_FLAG_USE_ICT0x01;

iwx_disable_rx_dma(sc);
iwx_reset_rx_ring(sc, &sc->rxq);
for (i = 0; i < nitems(sc->txq)(sizeof((sc->txq)) / sizeof((sc->txq)[0])); i++)
iwx_reset_tx_ring(sc, &sc->txq[i]);
for (i = 0; i < IEEE80211_NUM_TID16; i++) {
struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[i];
if (ba->ba_state != IEEE80211_BA_AGREED2)
	continue;
ieee80211_delba_request(ic, ni, 0, 1, i);
}

/* Make sure (redundant) we've released our request to stay awake */
IWX_CLRBITS(sc, IWX_CSR_GP_CNTRL,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000008))))))
   IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x024))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x024)))))
 & ~((0x00000008))))));
if (sc->sc_nic_locks > 0)
printf("%s: %d active NIC locks forcefully cleared\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_nic_locks);
sc->sc_nic_locks = 0;

/* Stop the device, and put it in low power state */
iwx_apm_stop(sc);

/* Reset the on-board processor. */
IWX_SETBITS(sc, IWX_CSR_RESET, IWX_CSR_RESET_REG_FLAG_SW_RESET)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x020))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x020)))))
 | ((0x00000080))))));
DELAY(5000)(*delay_func)(5000);

/*
* Upon stop, the IVAR table gets erased, so msi-x won't
* work. This causes a bug in RF-KILL flows, since the interrupt
* that enables radio won't fire on the correct irq, and the
* driver won't be able to handle the interrupt.
* Configure the IVAR table again after reset.
*/
iwx_conf_msix_hw(sc, 1);

/*
* Upon stop, the APM issues an interrupt if HW RF kill is set.
* Clear the interrupt again.
*/
iwx_disable_interrupts(sc);

/* Even though we stop the HW we still want the RF kill interrupt. */
iwx_enable_rfkill_int(sc);
iwx_check_rfkill(sc);

iwx_prepare_card_hw(sc);

iwx_ctxt_info_free_paging(sc);
iwx_dma_contig_free(&sc->pnvm_dma);
2725}

2727void
2728iwx_nic_config(struct iwx_softc *sc)
2729{
uint8_t radio_cfg_type, radio_cfg_step, radio_cfg_dash;
uint32_t mask, val, reg_val = 0;

radio_cfg_type = (sc->sc_fw_phy_config & IWX_FW_PHY_CFG_RADIO_TYPE(0x3 << 0)) >>
   IWX_FW_PHY_CFG_RADIO_TYPE_POS0;
radio_cfg_step = (sc->sc_fw_phy_config & IWX_FW_PHY_CFG_RADIO_STEP(0x3 << 2)) >>
   IWX_FW_PHY_CFG_RADIO_STEP_POS2;
radio_cfg_dash = (sc->sc_fw_phy_config & IWX_FW_PHY_CFG_RADIO_DASH(0x3 << 4)) >>
   IWX_FW_PHY_CFG_RADIO_DASH_POS4;

reg_val |= IWX_CSR_HW_REV_STEP(sc->sc_hw_rev)(((sc->sc_hw_rev) & 0x000000C) >> 2) <<
   IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP(2);
reg_val |= IWX_CSR_HW_REV_DASH(sc->sc_hw_rev)(((sc->sc_hw_rev) & 0x0000003) >> 0) <<
   IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH(0);

/* radio configuration */
reg_val |= radio_cfg_type << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE(10);
reg_val |= radio_cfg_step << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP(14);
reg_val |= radio_cfg_dash << IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH(12);

mask = IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH(0x00000003) |
   IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP(0x0000000C) |
   IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP(0x0000C000) |
   IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH(0x00003000) |
   IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE(0x00000C00) |
   IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI(0x00000200) |
   IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI(0x00000100);

val = IWX_READ(sc, IWX_CSR_HW_IF_CONFIG_REG)(((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x000)))));
val &= ~mask;
val |= reg_val;
IWX_WRITE(sc, IWX_CSR_HW_IF_CONFIG_REG, val)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x000))), (
(val))));
2762}

2764int
2765iwx_nic_rx_init(struct iwx_softc *sc)
2766{
IWX_WRITE_1(sc, IWX_CSR_INT_COALESCING, IWX_HOST_INT_TIMEOUT_DEF)(((sc)->sc_st)->write_1(((sc)->sc_sh), (((0x004))), (
((0x40)))));

/*
* We don't configure the RFH; the firmware will do that.
* Rx descriptors are set when firmware sends an ALIVE interrupt.
*/
return 0;
2774}

2776int
2777iwx_nic_init(struct iwx_softc *sc)
2778{
int err;

iwx_apm_init(sc);
if (sc->sc_device_family < IWX_DEVICE_FAMILY_AX2102)
iwx_nic_config(sc);

err = iwx_nic_rx_init(sc);
if (err)
return err;

IWX_SETBITS(sc, IWX_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x0A8))), (
((((sc)->sc_st)->read_4(((sc)->sc_sh), (((0x0A8)))))
 | (0x800fffff)))));

return 0;
2792}

2794/* Map a TID to an ieee80211_edca_ac category. */
2795const uint8_t iwx_tid_to_ac[IWX_MAX_TID_COUNT8] = {
EDCA_AC_BE,
EDCA_AC_BK,
EDCA_AC_BK,
EDCA_AC_BE,
EDCA_AC_VI,
EDCA_AC_VI,
EDCA_AC_VO,
EDCA_AC_VO,
2804};

2806/* Map ieee80211_edca_ac categories to firmware Tx FIFO. */
2807const uint8_t iwx_ac_to_tx_fifo[] = {
IWX_GEN2_EDCA_TX_FIFO_BE,
IWX_GEN2_EDCA_TX_FIFO_BK,
IWX_GEN2_EDCA_TX_FIFO_VI,
IWX_GEN2_EDCA_TX_FIFO_VO,
2812};

2814int
2815iwx_enable_txq(struct iwx_softc *sc, int sta_id, int qid, int tid,
  int num_slots)
2817{
struct iwx_rx_packet *pkt;
struct iwx_tx_queue_cfg_rsp *resp;
struct iwx_tx_queue_cfg_cmd cmd_v0;
struct iwx_scd_queue_cfg_cmd cmd_v3;
struct iwx_host_cmd hcmd = {
.flags = IWX_CMD_WANT_RESP,
.resp_pkt_len = sizeof(*pkt) + sizeof(*resp),
};
struct iwx_tx_ring *ring = &sc->txq[qid];
int err, fwqid, cmd_ver;
uint32_t wr_idx;
size_t resp_len;

iwx_reset_tx_ring(sc, ring);

cmd_ver = iwx_lookup_cmd_ver(sc, IWX_DATA_PATH_GROUP0x5,
   IWX_SCD_QUEUE_CONFIG_CMD0x17);
if (cmd_ver == 0 || cmd_ver == IWX_FW_CMD_VER_UNKNOWN99) {
memset(&cmd_v0, 0, sizeof(cmd_v0))__builtin_memset((&cmd_v0), (0), (sizeof(cmd_v0)));
cmd_v0.sta_id = sta_id;
cmd_v0.tid = tid;
cmd_v0.flags = htole16(IWX_TX_QUEUE_CFG_ENABLE_QUEUE)((__uint16_t)((1 << 0)));
cmd_v0.cb_size = htole32(IWX_TFD_QUEUE_CB_SIZE(num_slots))((__uint32_t)((((sizeof(num_slots) <= 4) ? (fls(num_slots)
 - 1) : (flsl(num_slots) - 1)) - 3)));
cmd_v0.byte_cnt_addr = htole64(ring->bc_tbl.paddr)((__uint64_t)(ring->bc_tbl.paddr));
cmd_v0.tfdq_addr = htole64(ring->desc_dma.paddr)((__uint64_t)(ring->desc_dma.paddr));
hcmd.id = IWX_SCD_QUEUE_CFG0x1d;
hcmd.data[0] = &cmd_v0;
hcmd.len[0] = sizeof(cmd_v0);
} else if (cmd_ver == 3) {
memset(&cmd_v3, 0, sizeof(cmd_v3))__builtin_memset((&cmd_v3), (0), (sizeof(cmd_v3)));
cmd_v3.operation = htole32(IWX_SCD_QUEUE_ADD)((__uint32_t)(0));
cmd_v3.u.add.tfdq_dram_addr = htole64(ring->desc_dma.paddr)((__uint64_t)(ring->desc_dma.paddr));
cmd_v3.u.add.bc_dram_addr = htole64(ring->bc_tbl.paddr)((__uint64_t)(ring->bc_tbl.paddr));
cmd_v3.u.add.cb_size = htole32(IWX_TFD_QUEUE_CB_SIZE(num_slots))((__uint32_t)((((sizeof(num_slots) <= 4) ? (fls(num_slots)
 - 1) : (flsl(num_slots) - 1)) - 3)));
cmd_v3.u.add.flags = htole32(0)((__uint32_t)(0));
cmd_v3.u.add.sta_mask = htole32(1 << sta_id)((__uint32_t)(1 << sta_id));
cmd_v3.u.add.tid = tid;
hcmd.id = IWX_WIDE_ID(IWX_DATA_PATH_GROUP,((0x5 << 8) | 0x17)
    IWX_SCD_QUEUE_CONFIG_CMD)((0x5 << 8) | 0x17);
hcmd.data[0] = &cmd_v3;
hcmd.len[0] = sizeof(cmd_v3);
} else {
printf("%s: unsupported SCD_QUEUE_CFG command version %d\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), cmd_ver);
return ENOTSUP91;
}

err = iwx_send_cmd(sc, &hcmd);
if (err)
return err;

pkt = hcmd.resp_pkt;
if (!pkt || (pkt->hdr.flags & IWX_CMD_FAILED_MSK0x40)) {
err = EIO5;
goto out;
}

resp_len = iwx_rx_packet_payload_len(pkt);
if (resp_len != sizeof(*resp)) {
err = EIO5;
goto out;
}

resp = (void *)pkt->data;
fwqid = le16toh(resp->queue_number)((__uint16_t)(resp->queue_number));
wr_idx = le16toh(resp->write_pointer)((__uint16_t)(resp->write_pointer));

/* Unlike iwlwifi, we do not support dynamic queue ID assignment. */
if (fwqid != qid) {
err = EIO5;
goto out;
}

if (wr_idx != ring->cur_hw) {
err = EIO5;
goto out;
}

sc->qenablemsk |= (1 << qid);
ring->tid = tid;
2898out:
iwx_free_resp(sc, &hcmd);
return err;
2901}

2903int
2904iwx_disable_txq(struct iwx_softc *sc, int sta_id, int qid, uint8_t tid)
2905{
struct iwx_rx_packet *pkt;
struct iwx_tx_queue_cfg_rsp *resp;
struct iwx_tx_queue_cfg_cmd cmd_v0;
struct iwx_scd_queue_cfg_cmd cmd_v3;
struct iwx_host_cmd hcmd = {
.flags = IWX_CMD_WANT_RESP,
.resp_pkt_len = sizeof(*pkt) + sizeof(*resp),
};
struct iwx_tx_ring *ring = &sc->txq[qid];
int err, cmd_ver;

cmd_ver = iwx_lookup_cmd_ver(sc, IWX_DATA_PATH_GROUP0x5,
   IWX_SCD_QUEUE_CONFIG_CMD0x17);
if (cmd_ver == 0 || cmd_ver == IWX_FW_CMD_VER_UNKNOWN99) {
memset(&cmd_v0, 0, sizeof(cmd_v0))__builtin_memset((&cmd_v0), (0), (sizeof(cmd_v0)));
cmd_v0.sta_id = sta_id;
cmd_v0.tid = tid;
cmd_v0.flags = htole16(0)((__uint16_t)(0)); /* clear "queue enabled" flag */
cmd_v0.cb_size = htole32(0)((__uint32_t)(0));
cmd_v0.byte_cnt_addr = htole64(0)((__uint64_t)(0));
cmd_v0.tfdq_addr = htole64(0)((__uint64_t)(0));
hcmd.id = IWX_SCD_QUEUE_CFG0x1d;
hcmd.data[0] = &cmd_v0;
hcmd.len[0] = sizeof(cmd_v0);
} else if (cmd_ver == 3) {
memset(&cmd_v3, 0, sizeof(cmd_v3))__builtin_memset((&cmd_v3), (0), (sizeof(cmd_v3)));
cmd_v3.operation = htole32(IWX_SCD_QUEUE_REMOVE)((__uint32_t)(1));
cmd_v3.u.remove.sta_mask = htole32(1 << sta_id)((__uint32_t)(1 << sta_id));
cmd_v3.u.remove.tid = tid;
hcmd.id = IWX_WIDE_ID(IWX_DATA_PATH_GROUP,((0x5 << 8) | 0x17)
    IWX_SCD_QUEUE_CONFIG_CMD)((0x5 << 8) | 0x17);
hcmd.data[0] = &cmd_v3;
hcmd.len[0] = sizeof(cmd_v3);
} else {
printf("%s: unsupported SCD_QUEUE_CFG command version %d\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname), cmd_ver);
return ENOTSUP91;
}

err = iwx_send_cmd(sc, &hcmd);
if (err)
return err;

pkt = hcmd.resp_pkt;
if (!pkt || (pkt->hdr.flags & IWX_CMD_FAILED_MSK0x40)) {
err = EIO5;
goto out;
}

sc->qenablemsk &= ~(1 << qid);
iwx_reset_tx_ring(sc, ring);
2957out:
iwx_free_resp(sc, &hcmd);
return err;
2960}

2962void
2963iwx_post_alive(struct iwx_softc *sc)
2964{
int txcmd_ver;

iwx_ict_reset(sc);

txcmd_ver = iwx_lookup_notif_ver(sc, IWX_LONG_GROUP0x1, IWX_TX_CMD0x1c) ;
if (txcmd_ver != IWX_FW_CMD_VER_UNKNOWN99 && txcmd_ver > 6)
sc->sc_rate_n_flags_version = 2;
else
sc->sc_rate_n_flags_version = 1;

txcmd_ver = iwx_lookup_cmd_ver(sc, IWX_LONG_GROUP0x1, IWX_TX_CMD0x1c);
2976}

2978int
2979iwx_schedule_session_protection(struct iwx_softc *sc, struct iwx_node *in,
  uint32_t duration_tu)
2981{
struct iwx_session_prot_cmd cmd = {
.id_and_color = htole32(IWX_FW_CMD_ID_AND_COLOR(in->in_id,((__uint32_t)(((in->in_id << (0)) | (in->in_color
 << (8)))))
    in->in_color))((__uint32_t)(((in->in_id << (0)) | (in->in_color
 << (8))))),
.action = htole32(IWX_FW_CTXT_ACTION_ADD)((__uint32_t)(1)),
.conf_id = htole32(IWX_SESSION_PROTECT_CONF_ASSOC)((__uint32_t)(IWX_SESSION_PROTECT_CONF_ASSOC)),
.duration_tu = htole32(duration_tu)((__uint32_t)(duration_tu)),
};
uint32_t cmd_id;
int err;

cmd_id = iwx_cmd_id(IWX_SESSION_PROTECTION_CMD0x05, IWX_MAC_CONF_GROUP0x3, 0);
err = iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd);
if (!err)
sc->sc_flags |= IWX_FLAG_TE_ACTIVE0x40;
return err;
2997}

2999void
3000iwx_unprotect_session(struct iwx_softc *sc, struct iwx_node *in)
3001{
struct iwx_session_prot_cmd cmd = {
.id_and_color = htole32(IWX_FW_CMD_ID_AND_COLOR(in->in_id,((__uint32_t)(((in->in_id << (0)) | (in->in_color
 << (8)))))
    in->in_color))((__uint32_t)(((in->in_id << (0)) | (in->in_color
 << (8))))),
.action = htole32(IWX_FW_CTXT_ACTION_REMOVE)((__uint32_t)(3)),
.conf_id = htole32(IWX_SESSION_PROTECT_CONF_ASSOC)((__uint32_t)(IWX_SESSION_PROTECT_CONF_ASSOC)),
.duration_tu = 0,
};
uint32_t cmd_id;

/* Do nothing if the time event has already ended. */
if ((sc->sc_flags & IWX_FLAG_TE_ACTIVE0x40) == 0)
return;

cmd_id = iwx_cmd_id(IWX_SESSION_PROTECTION_CMD0x05, IWX_MAC_CONF_GROUP0x3, 0);
if (iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd) == 0)
sc->sc_flags &= ~IWX_FLAG_TE_ACTIVE0x40;
3018}

3020/*
* NVM read access and content parsing.  We do not support
* external NVM or writing NVM.
*/

3025uint8_t
3026iwx_fw_valid_tx_ant(struct iwx_softc *sc)
3027{
uint8_t tx_ant;

tx_ant = ((sc->sc_fw_phy_config & IWX_FW_PHY_CFG_TX_CHAIN(0xf << 16))
   >> IWX_FW_PHY_CFG_TX_CHAIN_POS16);

if (sc->sc_nvm.valid_tx_ant)
tx_ant &= sc->sc_nvm.valid_tx_ant;

return tx_ant;
3037}

3039uint8_t
3040iwx_fw_valid_rx_ant(struct iwx_softc *sc)
3041{
uint8_t rx_ant;

rx_ant = ((sc->sc_fw_phy_config & IWX_FW_PHY_CFG_RX_CHAIN(0xf << 20))
   >> IWX_FW_PHY_CFG_RX_CHAIN_POS20);

if (sc->sc_nvm.valid_rx_ant)
rx_ant &= sc->sc_nvm.valid_rx_ant;

return rx_ant;
3051}

3053void
3054iwx_init_channel_map(struct iwx_softc *sc, uint16_t *channel_profile_v3,
  uint32_t *channel_profile_v4, int nchan_profile)
3056{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_nvm_data *data = &sc->sc_nvm;
int ch_idx;
struct ieee80211_channel *channel;
uint32_t ch_flags;
int is_5ghz;
int flags, hw_value;
int nchan;
const uint8_t *nvm_channels;

if (sc->sc_uhb_supported) {
nchan = nitems(iwx_nvm_channels_uhb)(sizeof((iwx_nvm_channels_uhb)) / sizeof((iwx_nvm_channels_uhb
)[0]));
nvm_channels = iwx_nvm_channels_uhb;
} else {
nchan = nitems(iwx_nvm_channels_8000)(sizeof((iwx_nvm_channels_8000)) / sizeof((iwx_nvm_channels_8000
)[0]));
nvm_channels = iwx_nvm_channels_8000;
}

for (ch_idx = 0; ch_idx < nchan && ch_idx < nchan_profile; ch_idx++) {
if (channel_profile_v4)
	ch_flags = le32_to_cpup(channel_profile_v4 + ch_idx)(((__uint32_t)(*(const uint32_t *)(channel_profile_v4 + ch_idx
))));
else
	ch_flags = le16_to_cpup(channel_profile_v3 + ch_idx)(((__uint16_t)(*(const uint16_t *)(channel_profile_v3 + ch_idx
))));

/* net80211 cannot handle 6 GHz channel numbers yet */
if (ch_idx >= IWX_NUM_2GHZ_CHANNELS14 + IWX_NUM_5GHZ_CHANNELS37)
	break;

is_5ghz = ch_idx >= IWX_NUM_2GHZ_CHANNELS14;
if (is_5ghz && !data->sku_cap_band_52GHz_enable)
	ch_flags &= ~IWX_NVM_CHANNEL_VALID(1 << 0);

hw_value = nvm_channels[ch_idx];
channel = &ic->ic_channels[hw_value];

if (!(ch_flags & IWX_NVM_CHANNEL_VALID(1 << 0))) {
	channel->ic_freq = 0;
	channel->ic_flags = 0;
	continue;
}

if (!is_5ghz) {
	flags = IEEE80211_CHAN_2GHZ0x0080;
	channel->ic_flags
	    = IEEE80211_CHAN_CCK0x0020
	    | IEEE80211_CHAN_OFDM0x0040
	    | IEEE80211_CHAN_DYN0x0400
	    | IEEE80211_CHAN_2GHZ0x0080;
} else {
	flags = IEEE80211_CHAN_5GHZ0x0100;
	channel->ic_flags =
	    IEEE80211_CHAN_A(0x0100 | 0x0040);
}
channel->ic_freq = ieee80211_ieee2mhz(hw_value, flags);

if (!(ch_flags & IWX_NVM_CHANNEL_ACTIVE(1 << 3)))
	channel->ic_flags |= IEEE80211_CHAN_PASSIVE0x0200;

if (data->sku_cap_11n_enable) {
	channel->ic_flags |= IEEE80211_CHAN_HT0x2000;
	if (ch_flags & IWX_NVM_CHANNEL_40MHZ(1 << 9))
		channel->ic_flags |= IEEE80211_CHAN_40MHZ0x8000;
}

if (is_5ghz && data->sku_cap_11ac_enable) {
	channel->ic_flags |= IEEE80211_CHAN_VHT0x4000;
	if (ch_flags & IWX_NVM_CHANNEL_80MHZ(1 << 10))
		channel->ic_xflags |= IEEE80211_CHANX_80MHZ0x00000001;
}
}
3127}

3129int
3130iwx_mimo_enabled(struct iwx_softc *sc)
3131{
struct ieee80211com *ic = &sc->sc_ic;

return !sc->sc_nvm.sku_cap_mimo_disable &&
   (ic->ic_userflags & IEEE80211_F_NOMIMO0x00000008) == 0;
3136}

3138void
3139iwx_setup_ht_rates(struct iwx_softc *sc)
3140{
struct ieee80211com *ic = &sc->sc_ic;
uint8_t rx_ant;

/* TX is supported with the same MCS as RX. */
ic->ic_tx_mcs_set = IEEE80211_TX_MCS_SET_DEFINED0x01;

memset(ic->ic_sup_mcs, 0, sizeof(ic->ic_sup_mcs))__builtin_memset((ic->ic_sup_mcs), (0), (sizeof(ic->ic_sup_mcs
)));
ic->ic_sup_mcs[0] = 0xff;		/* MCS 0-7 */

if (!iwx_mimo_enabled(sc))
return;

rx_ant = iwx_fw_valid_rx_ant(sc);
if ((rx_ant & IWX_ANT_AB((1 << 0) | (1 << 1))) == IWX_ANT_AB((1 << 0) | (1 << 1)) ||
   (rx_ant & IWX_ANT_BC((1 << 1) | (1 << 2))) == IWX_ANT_BC((1 << 1) | (1 << 2)))
ic->ic_sup_mcs[1] = 0xff;	/* MCS 8-15 */
3157}

3159void
3160iwx_setup_vht_rates(struct iwx_softc *sc)
3161{
struct ieee80211com *ic = &sc->sc_ic;
uint8_t rx_ant = iwx_fw_valid_rx_ant(sc);
int n;

ic->ic_vht_rxmcs = (IEEE80211_VHT_MCS_0_92 <<
   IEEE80211_VHT_MCS_FOR_SS_SHIFT(1)(2*((1)-1)));

if (iwx_mimo_enabled(sc) &&
   ((rx_ant & IWX_ANT_AB((1 << 0) | (1 << 1))) == IWX_ANT_AB((1 << 0) | (1 << 1)) ||
   (rx_ant & IWX_ANT_BC((1 << 1) | (1 << 2))) == IWX_ANT_BC((1 << 1) | (1 << 2)))) {
ic->ic_vht_rxmcs |= (IEEE80211_VHT_MCS_0_92 <<
    IEEE80211_VHT_MCS_FOR_SS_SHIFT(2)(2*((2)-1)));
} else {
ic->ic_vht_rxmcs |= (IEEE80211_VHT_MCS_SS_NOT_SUPP3 <<
    IEEE80211_VHT_MCS_FOR_SS_SHIFT(2)(2*((2)-1)));
}

for (n = 3; n <= IEEE80211_VHT_NUM_SS8; n++) {
ic->ic_vht_rxmcs |= (IEEE80211_VHT_MCS_SS_NOT_SUPP3 <<
    IEEE80211_VHT_MCS_FOR_SS_SHIFT(n)(2*((n)-1)));
}

ic->ic_vht_txmcs = ic->ic_vht_rxmcs;
3185}

3187void
3188iwx_init_reorder_buffer(struct iwx_reorder_buffer *reorder_buf,
  uint16_t ssn, uint16_t buf_size)
3190{
reorder_buf->head_sn = ssn;
reorder_buf->num_stored = 0;
reorder_buf->buf_size = buf_size;
reorder_buf->last_amsdu = 0;
reorder_buf->last_sub_index = 0;
reorder_buf->removed = 0;
reorder_buf->valid = 0;
reorder_buf->consec_oldsn_drops = 0;
reorder_buf->consec_oldsn_ampdu_gp2 = 0;
reorder_buf->consec_oldsn_prev_drop = 0;
3201}

3203void
3204iwx_clear_reorder_buffer(struct iwx_softc *sc, struct iwx_rxba_data *rxba)
3205{
int i;
struct iwx_reorder_buffer *reorder_buf = &rxba->reorder_buf;
struct iwx_reorder_buf_entry *entry;

for (i = 0; i < reorder_buf->buf_size; i++) {
entry = &rxba->entries[i];
ml_purge(&entry->frames);
timerclear(&entry->reorder_time)(&entry->reorder_time)->tv_sec = (&entry->reorder_time
)->tv_usec = 0;
}

reorder_buf->removed = 1;
timeout_del(&reorder_buf->reorder_timer);
timerclear(&rxba->last_rx)(&rxba->last_rx)->tv_sec = (&rxba->last_rx)->
tv_usec = 0;
timeout_del(&rxba->session_timer);
rxba->baid = IWX_RX_REORDER_DATA_INVALID_BAID0x7f;
3221}

3223#define RX_REORDER_BUF_TIMEOUT_MQ_USEC(100000ULL) (100000ULL)

3225void
3226iwx_rx_ba_session_expired(void *arg)
3227{
struct iwx_rxba_data *rxba = arg;
struct iwx_softc *sc = rxba->sc;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni = ic->ic_bss;
struct timeval now, timeout, expiry;
int s;

s = splnet()splraise(0x4);
if ((sc->sc_flags & IWX_FLAG_SHUTDOWN0x100) == 0 &&
   ic->ic_state == IEEE80211_S_RUN &&
   rxba->baid != IWX_RX_REORDER_DATA_INVALID_BAID0x7f) {
getmicrouptime(&now);
USEC_TO_TIMEVAL(RX_REORDER_BUF_TIMEOUT_MQ_USEC(100000ULL), &timeout);
timeradd(&rxba->last_rx, &timeout, &expiry)do { (&expiry)->tv_sec = (&rxba->last_rx)->tv_sec
 + (&timeout)->tv_sec; (&expiry)->tv_usec = (&
rxba->last_rx)->tv_usec + (&timeout)->tv_usec; if
 ((&expiry)->tv_usec >= 1000000) { (&expiry)->
tv_sec++; (&expiry)->tv_usec -= 1000000; } } while (0);
if (timercmp(&now, &expiry, <)(((&now)->tv_sec == (&expiry)->tv_sec) ? ((&
now)->tv_usec < (&expiry)->tv_usec) : ((&now
)->tv_sec < (&expiry)->tv_sec))) {
	timeout_add_usec(&rxba->session_timer, rxba->timeout);
} else {
	ic->ic_stats.is_ht_rx_ba_timeout++;
	ieee80211_delba_request(ic, ni,
	    IEEE80211_REASON_TIMEOUT, 0, rxba->tid);
}
}
splx(s)spllower(s);
3251}

3253void
3254iwx_rx_bar_frame_release(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
  struct mbuf_list *ml)
3256{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni = ic->ic_bss;
struct iwx_bar_frame_release *release = (void *)pkt->data;
struct iwx_reorder_buffer *buf;
struct iwx_rxba_data *rxba;
unsigned int baid, nssn, sta_id, tid;

if (iwx_rx_packet_payload_len(pkt) < sizeof(*release))
return;

baid = (le32toh(release->ba_info)((__uint32_t)(release->ba_info)) & IWX_BAR_FRAME_RELEASE_BAID_MASK0x3f000000) >>
   IWX_BAR_FRAME_RELEASE_BAID_SHIFT24;
if (baid == IWX_RX_REORDER_DATA_INVALID_BAID0x7f ||
   baid >= nitems(sc->sc_rxba_data)(sizeof((sc->sc_rxba_data)) / sizeof((sc->sc_rxba_data)
[0])))
return;

rxba = &sc->sc_rxba_data[baid];
if (rxba->baid == IWX_RX_REORDER_DATA_INVALID_BAID0x7f)
return;

tid = le32toh(release->sta_tid)((__uint32_t)(release->sta_tid)) & IWX_BAR_FRAME_RELEASE_TID_MASK0x0000000f;
sta_id = (le32toh(release->sta_tid)((__uint32_t)(release->sta_tid)) &
   IWX_BAR_FRAME_RELEASE_STA_MASK0x000001f0) >> IWX_BAR_FRAME_RELEASE_STA_SHIFT4;
if (tid != rxba->tid || rxba->sta_id != IWX_STATION_ID0)
return;

nssn = le32toh(release->ba_info)((__uint32_t)(release->ba_info)) & IWX_BAR_FRAME_RELEASE_NSSN_MASK0x00000fff;
buf = &rxba->reorder_buf;
iwx_release_frames(sc, ni, rxba, buf, nssn, ml);
3286}

3288void
3289iwx_reorder_timer_expired(void *arg)
3290{
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct iwx_reorder_buffer *buf = arg;
struct iwx_rxba_data *rxba = iwx_rxba_data_from_reorder_buf(buf);
struct iwx_reorder_buf_entry *entries = &rxba->entries[0];
struct iwx_softc *sc = rxba->sc;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni = ic->ic_bss;
int i, s;
uint16_t sn = 0, index = 0;
int expired = 0;
int cont = 0;
struct timeval now, timeout, expiry;

if (!buf->num_stored || buf->removed)
return;

s = splnet()splraise(0x4);
getmicrouptime(&now);
USEC_TO_TIMEVAL(RX_REORDER_BUF_TIMEOUT_MQ_USEC(100000ULL), &timeout);

for (i = 0; i < buf->buf_size ; i++) {
index = (buf->head_sn + i) % buf->buf_size;

if (ml_empty(&entries[index].frames)((&entries[index].frames)->ml_len == 0)) {
	/*
	 * If there is a hole and the next frame didn't expire
	 * we want to break and not advance SN.
	 */
	cont = 0;
	continue;
}
timeradd(&entries[index].reorder_time, &timeout, &expiry)do { (&expiry)->tv_sec = (&entries[index].reorder_time
)->tv_sec + (&timeout)->tv_sec; (&expiry)->tv_usec
 = (&entries[index].reorder_time)->tv_usec + (&timeout
)->tv_usec; if ((&expiry)->tv_usec >= 1000000) {
 (&expiry)->tv_sec++; (&expiry)->tv_usec -= 1000000
; } } while (0);
if (!cont && timercmp(&now, &expiry, <)(((&now)->tv_sec == (&expiry)->tv_sec) ? ((&
now)->tv_usec < (&expiry)->tv_usec) : ((&now
)->tv_sec < (&expiry)->tv_sec)))
	break;

expired = 1;
/* continue until next hole after this expired frame */
cont = 1;
sn = (buf->head_sn + (i + 1)) & 0xfff;
}

if (expired) {
/* SN is set to the last expired frame + 1 */
iwx_release_frames(sc, ni, rxba, buf, sn, &ml);
if_input(&sc->sc_ic.ic_ific_ac.ac_if, &ml);
ic->ic_stats.is_ht_rx_ba_window_gap_timeout++;
} else {
/*
 * If no frame expired and there are stored frames, index is now
 * pointing to the first unexpired frame - modify reorder timeout
 * accordingly.
 */
timeout_add_usec(&buf->reorder_timer,
    RX_REORDER_BUF_TIMEOUT_MQ_USEC(100000ULL));
}

splx(s)spllower(s);
3348}

3350#define IWX_MAX_RX_BA_SESSIONS16 16

3352struct iwx_rxba_data *
3353iwx_find_rxba_data(struct iwx_softc *sc, uint8_t tid)
3354{
int i;

for (i = 0; i < nitems(sc->sc_rxba_data)(sizeof((sc->sc_rxba_data)) / sizeof((sc->sc_rxba_data)
[0])); i++) {
if (sc->sc_rxba_data[i].baid ==
    IWX_RX_REORDER_DATA_INVALID_BAID0x7f)
	continue;
if (sc->sc_rxba_data[i].tid == tid)
	return &sc->sc_rxba_data[i];
}

return NULL((void *)0);
3366}

3368int
3369iwx_sta_rx_agg_baid_cfg_cmd(struct iwx_softc *sc, struct ieee80211_node *ni,
  uint8_t tid, uint16_t ssn, uint16_t winsize, int timeout_val, int start,
  uint8_t *baid)
3372{
struct iwx_rx_baid_cfg_cmd cmd;
uint32_t new_baid = 0;
int err;

splassert(IPL_NET)do { if (splassert_ctl > 0) { splassert_check(0x4, __func__
); } } while (0);

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));

if (start) {
cmd.action = IWX_RX_BAID_ACTION_ADD0;
cmd.alloc.sta_id_mask = htole32(1 << IWX_STATION_ID)((__uint32_t)(1 << 0));
cmd.alloc.tid = tid;
cmd.alloc.ssn = htole16(ssn)((__uint16_t)(ssn));
cmd.alloc.win_size = htole16(winsize)((__uint16_t)(winsize));
} else {
struct iwx_rxba_data *rxba;

rxba = iwx_find_rxba_data(sc, tid);
if (rxba == NULL((void *)0))
	return ENOENT2;
*baid = rxba->baid;

cmd.action = IWX_RX_BAID_ACTION_REMOVE2;
if (iwx_lookup_cmd_ver(sc, IWX_DATA_PATH_GROUP0x5,
    IWX_RX_BAID_ALLOCATION_CONFIG_CMD0x16) == 1) {
	cmd.remove_v1.baid = rxba->baid;
} else {
	cmd.remove.sta_id_mask = htole32(1 << IWX_STATION_ID)((__uint32_t)(1 << 0));
	cmd.remove.tid = tid;
}
}

err = iwx_send_cmd_pdu_status(sc, IWX_WIDE_ID(IWX_DATA_PATH_GROUP,((0x5 << 8) | 0x16)
   IWX_RX_BAID_ALLOCATION_CONFIG_CMD)((0x5 << 8) | 0x16), sizeof(cmd), &cmd, &new_baid);
if (err)
return err;

if (start) {
if (new_baid >= nitems(sc->sc_rxba_data)(sizeof((sc->sc_rxba_data)) / sizeof((sc->sc_rxba_data)
[0])))
	return ERANGE34;
*baid = new_baid;
}

return 0;
3417}

3419int
3420iwx_sta_rx_agg_sta_cmd(struct iwx_softc *sc, struct ieee80211_node *ni,
  uint8_t tid, uint16_t ssn, uint16_t winsize, int timeout_val, int start,
  uint8_t *baid)
3423{
struct iwx_add_sta_cmd cmd;
struct iwx_node *in = (void *)ni;
int err;
uint32_t status;

splassert(IPL_NET)do { if (splassert_ctl > 0) { splassert_check(0x4, __func__
); } } while (0);

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));

cmd.sta_id = IWX_STATION_ID0;
cmd.mac_id_n_color
   = htole32(IWX_FW_CMD_ID_AND_COLOR(in->in_id, in->in_color))((__uint32_t)(((in->in_id << (0)) | (in->in_color
 << (8)))));
cmd.add_modify = IWX_STA_MODE_MODIFY1;

if (start) {
cmd.add_immediate_ba_tid = (uint8_t)tid;
cmd.add_immediate_ba_ssn = htole16(ssn)((__uint16_t)(ssn));
cmd.rx_ba_window = htole16(winsize)((__uint16_t)(winsize));
} else {
struct iwx_rxba_data *rxba;

rxba = iwx_find_rxba_data(sc, tid);
if (rxba == NULL((void *)0))
	return ENOENT2;
*baid = rxba->baid;

cmd.remove_immediate_ba_tid = (uint8_t)tid;
}
cmd.modify_mask = start ? IWX_STA_MODIFY_ADD_BA_TID(1 << 3) :
   IWX_STA_MODIFY_REMOVE_BA_TID(1 << 4);

status = IWX_ADD_STA_SUCCESS0x1;
err = iwx_send_cmd_pdu_status(sc, IWX_ADD_STA0x18, sizeof(cmd), &cmd,
   &status);
if (err)
return err;

if ((status & IWX_ADD_STA_STATUS_MASK0xFF) != IWX_ADD_STA_SUCCESS0x1)
return EIO5;

if (!(status & IWX_ADD_STA_BAID_VALID_MASK0x8000))
return EINVAL22;

if (start) {
*baid = (status & IWX_ADD_STA_BAID_MASK0x7F00) >>
    IWX_ADD_STA_BAID_SHIFT8;
if (*baid == IWX_RX_REORDER_DATA_INVALID_BAID0x7f ||
    *baid >= nitems(sc->sc_rxba_data)(sizeof((sc->sc_rxba_data)) / sizeof((sc->sc_rxba_data)
[0])))
	return ERANGE34;
}

return 0;
3476}

3478void
3479iwx_sta_rx_agg(struct iwx_softc *sc, struct ieee80211_node *ni, uint8_t tid,
  uint16_t ssn, uint16_t winsize, int timeout_val, int start)
3481{
struct ieee80211com *ic = &sc->sc_ic;
int err, s;
struct iwx_rxba_data *rxba = NULL((void *)0);
uint8_t baid = 0;

s = splnet()splraise(0x4);

if (start && sc->sc_rx_ba_sessions >= IWX_MAX_RX_BA_SESSIONS16) {
ieee80211_addba_req_refuse(ic, ni, tid);
splx(s)spllower(s);
return;
}

if (isset(sc->sc_enabled_capa, IWX_UCODE_TLV_CAPA_BAID_ML_SUPPORT)((sc->sc_enabled_capa)[(63)>>3] & (1<<((63
)&(8 -1))))) {
err = iwx_sta_rx_agg_baid_cfg_cmd(sc, ni, tid, ssn, winsize,
    timeout_val, start, &baid);
} else {
err = iwx_sta_rx_agg_sta_cmd(sc, ni, tid, ssn, winsize,
    timeout_val, start, &baid);
}
if (err) {
ieee80211_addba_req_refuse(ic, ni, tid);
splx(s)spllower(s);
return;
}

rxba = &sc->sc_rxba_data[baid];

/* Deaggregation is done in hardware. */
if (start) {
if (rxba->baid != IWX_RX_REORDER_DATA_INVALID_BAID0x7f) {
	ieee80211_addba_req_refuse(ic, ni, tid);
	splx(s)spllower(s);
	return;
}
rxba->sta_id = IWX_STATION_ID0;
rxba->tid = tid;
rxba->baid = baid;
rxba->timeout = timeout_val;
getmicrouptime(&rxba->last_rx);
iwx_init_reorder_buffer(&rxba->reorder_buf, ssn,
    winsize);
if (timeout_val != 0) {
	struct ieee80211_rx_ba *ba;
	timeout_add_usec(&rxba->session_timer,
	    timeout_val);
	/* XXX disable net80211's BA timeout handler */
	ba = &ni->ni_rx_ba[tid];
	ba->ba_timeout_val = 0;
}
} else
iwx_clear_reorder_buffer(sc, rxba);

if (start) {
sc->sc_rx_ba_sessions++;
ieee80211_addba_req_accept(ic, ni, tid);
} else if (sc->sc_rx_ba_sessions > 0)
sc->sc_rx_ba_sessions--;

splx(s)spllower(s);
3542}

3544void
3545iwx_mac_ctxt_task(void *arg)
3546{
struct iwx_softc *sc = arg;
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_node *in = (void *)ic->ic_bss;
int err, s = splnet()splraise(0x4);

if ((sc->sc_flags & IWX_FLAG_SHUTDOWN0x100) ||
   ic->ic_state != IEEE80211_S_RUN) {
refcnt_rele_wake(&sc->task_refs);
splx(s)spllower(s);
return;
}

err = iwx_mac_ctxt_cmd(sc, in, IWX_FW_CTXT_ACTION_MODIFY2, 1);
if (err)
printf("%s: failed to update MAC\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));

iwx_unprotect_session(sc, in);

refcnt_rele_wake(&sc->task_refs);
splx(s)spllower(s);
3567}

3569void
3570iwx_phy_ctxt_task(void *arg)
3571{
struct iwx_softc *sc = arg;
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_node *in = (void *)ic->ic_bss;
struct ieee80211_node *ni = &in->in_ni;
uint8_t chains, sco, vht_chan_width;
int err, s = splnet()splraise(0x4);

if ((sc->sc_flags & IWX_FLAG_SHUTDOWN0x100) ||
   ic->ic_state != IEEE80211_S_RUN ||
   in->in_phyctxt == NULL((void *)0)) {
refcnt_rele_wake(&sc->task_refs);
splx(s)spllower(s);
return;
}

chains = iwx_mimo_enabled(sc) ? 2 : 1;
if ((ni->ni_flags & IEEE80211_NODE_HT0x0400) &&
   IEEE80211_CHAN_40MHZ_ALLOWED(ni->ni_chan)(((ni->ni_chan)->ic_flags & 0x8000) != 0) &&
   ieee80211_node_supports_ht_chan40(ni))
sco = (ni->ni_htop0 & IEEE80211_HTOP0_SCO_MASK0x03);
else
sco = IEEE80211_HTOP0_SCO_SCN0;
if ((ni->ni_flags & IEEE80211_NODE_VHT0x10000) &&
   IEEE80211_CHAN_80MHZ_ALLOWED(in->in_ni.ni_chan)(((in->in_ni.ni_chan)->ic_xflags & 0x00000001) != 0
) &&
   ieee80211_node_supports_vht_chan80(ni))
vht_chan_width = IEEE80211_VHTOP0_CHAN_WIDTH_801;
else
vht_chan_width = IEEE80211_VHTOP0_CHAN_WIDTH_HT0;
if (in->in_phyctxt->sco != sco ||
   in->in_phyctxt->vht_chan_width != vht_chan_width) {
err = iwx_phy_ctxt_update(sc, in->in_phyctxt,
    in->in_phyctxt->channel, chains, chains, 0, sco,
    vht_chan_width);
if (err)
	printf("%s: failed to update PHY\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
}

refcnt_rele_wake(&sc->task_refs);
splx(s)spllower(s);
3611}

3613void
3614iwx_updatechan(struct ieee80211com *ic)
3615{
struct iwx_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;

if (ic->ic_state == IEEE80211_S_RUN &&
   !task_pending(&sc->newstate_task)((&sc->newstate_task)->t_flags & 1))
iwx_add_task(sc, systq, &sc->phy_ctxt_task);
3621}

3623void
3624iwx_updateprot(struct ieee80211com *ic)
3625{
struct iwx_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;

if (ic->ic_state == IEEE80211_S_RUN &&
   !task_pending(&sc->newstate_task)((&sc->newstate_task)->t_flags & 1))
iwx_add_task(sc, systq, &sc->mac_ctxt_task);
3631}

3633void
3634iwx_updateslot(struct ieee80211com *ic)
3635{
struct iwx_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;

if (ic->ic_state == IEEE80211_S_RUN &&
   !task_pending(&sc->newstate_task)((&sc->newstate_task)->t_flags & 1))
iwx_add_task(sc, systq, &sc->mac_ctxt_task);
3641}

3643void
3644iwx_updateedca(struct ieee80211com *ic)
3645{
struct iwx_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;

if (ic->ic_state == IEEE80211_S_RUN &&
   !task_pending(&sc->newstate_task)((&sc->newstate_task)->t_flags & 1))
iwx_add_task(sc, systq, &sc->mac_ctxt_task);
3651}

3653void
3654iwx_updatedtim(struct ieee80211com *ic)
3655{
struct iwx_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;

if (ic->ic_state == IEEE80211_S_RUN &&
   !task_pending(&sc->newstate_task)((&sc->newstate_task)->t_flags & 1))
iwx_add_task(sc, systq, &sc->mac_ctxt_task);
3661}

3663void
3664iwx_sta_tx_agg_start(struct iwx_softc *sc, struct ieee80211_node *ni,
  uint8_t tid)
3666{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_tx_ba *ba;
int err, qid;
struct iwx_tx_ring *ring;

/* Ensure we can map this TID to an aggregation queue. */
if (tid >= IWX_MAX_TID_COUNT8)
return;

ba = &ni->ni_tx_ba[tid];
if (ba->ba_state != IEEE80211_BA_REQUESTED1)
return;

qid = sc->aggqid[tid];
if (qid == 0) {
/* Firmware should pick the next unused Tx queue. */
qid = fls(sc->qenablemsk);
}

/*
* Simply enable the queue.
* Firmware handles Tx Ba session setup and teardown.
*/
if ((sc->qenablemsk & (1 << qid)) == 0) {
if (!iwx_nic_lock(sc)) {
	ieee80211_addba_resp_refuse(ic, ni, tid,
	    IEEE80211_STATUS_UNSPECIFIED);
	return;
}
err = iwx_enable_txq(sc, IWX_STATION_ID0, qid, tid,
    IWX_TX_RING_COUNT(256));
iwx_nic_unlock(sc);
if (err) {
	printf("%s: could not enable Tx queue %d "
	    "(error %d)\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), qid, err);
	ieee80211_addba_resp_refuse(ic, ni, tid,
	    IEEE80211_STATUS_UNSPECIFIED);
	return;
}

ba->ba_winstart = 0;
} else
ba->ba_winstart = ni->ni_qos_txseqs[tid];

ba->ba_winend = (ba->ba_winstart + ba->ba_winsize - 1) & 0xfff;

ring = &sc->txq[qid];
ba->ba_timeout_val = 0;
ieee80211_addba_resp_accept(ic, ni, tid);
sc->aggqid[tid] = qid;
3717}

3719void
3720iwx_ba_task(void *arg)
3721{
struct iwx_softc *sc = arg;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni = ic->ic_bss;
int s = splnet()splraise(0x4);
int tid;

for (tid = 0; tid < IWX_MAX_TID_COUNT8; tid++) {
if (sc->sc_flags & IWX_FLAG_SHUTDOWN0x100)
	break;
if (sc->ba_rx.start_tidmask & (1 << tid)) {
	struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid];
	iwx_sta_rx_agg(sc, ni, tid, ba->ba_winstart,
	    ba->ba_winsize, ba->ba_timeout_val, 1);
	sc->ba_rx.start_tidmask &= ~(1 << tid);
} else if (sc->ba_rx.stop_tidmask & (1 << tid)) {
	iwx_sta_rx_agg(sc, ni, tid, 0, 0, 0, 0);
	sc->ba_rx.stop_tidmask &= ~(1 << tid);
}
}

for (tid = 0; tid < IWX_MAX_TID_COUNT8; tid++) {
if (sc->sc_flags & IWX_FLAG_SHUTDOWN0x100)
	break;
if (sc->ba_tx.start_tidmask & (1 << tid)) {
	iwx_sta_tx_agg_start(sc, ni, tid);
	sc->ba_tx.start_tidmask &= ~(1 << tid);
}
}

refcnt_rele_wake(&sc->task_refs);
splx(s)spllower(s);
3753}

3755/*
* This function is called by upper layer when an ADDBA request is received
* from another STA and before the ADDBA response is sent.
*/
3759int
3760iwx_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
  uint8_t tid)
3762{
struct iwx_softc *sc = IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_softc;

if (sc->sc_rx_ba_sessions >= IWX_MAX_RX_BA_SESSIONS16 ||
   tid >= IWX_MAX_TID_COUNT8)
return ENOSPC28;

if (sc->ba_rx.start_tidmask & (1 << tid))
return EBUSY16;

sc->ba_rx.start_tidmask |= (1 << tid);
iwx_add_task(sc, systq, &sc->ba_task);

return EBUSY16;
3776}

3778/*
* This function is called by upper layer on teardown of an HT-immediate
* Block Ack agreement (eg. upon receipt of a DELBA frame).
*/
3782void
3783iwx_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
  uint8_t tid)
3785{
struct iwx_softc *sc = IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_softc;

if (tid >= IWX_MAX_TID_COUNT8 || sc->ba_rx.stop_tidmask & (1 << tid))
return;

sc->ba_rx.stop_tidmask |= (1 << tid);
iwx_add_task(sc, systq, &sc->ba_task);
3793}

3795int
3796iwx_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
  uint8_t tid)
3798{
struct iwx_softc *sc = IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_softc;
struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];

/*
* Require a firmware version which uses an internal AUX queue.
* The value of IWX_FIRST_AGG_TX_QUEUE would be incorrect otherwise.
*/
if (sc->first_data_qid != IWX_DQA_CMD_QUEUE0 + 1)
return ENOTSUP91;

/* Ensure we can map this TID to an aggregation queue. */
if (tid >= IWX_MAX_TID_COUNT8)
return EINVAL22;

/* We only support a fixed Tx aggregation window size, for now. */
if (ba->ba_winsize != IWX_FRAME_LIMIT64)
return ENOTSUP91;

/* Is firmware already using an agg queue with this TID? */
if (sc->aggqid[tid] != 0)
return ENOSPC28;

/* Are we already processing an ADDBA request? */
if (sc->ba_tx.start_tidmask & (1 << tid))
return EBUSY16;

sc->ba_tx.start_tidmask |= (1 << tid);
iwx_add_task(sc, systq, &sc->ba_task);

return EBUSY16;
3829}

3831void
3832iwx_set_mac_addr_from_csr(struct iwx_softc *sc, struct iwx_nvm_data *data)
3833{
uint32_t mac_addr0, mac_addr1;

memset(data->hw_addr, 0, sizeof(data->hw_addr))__builtin_memset((data->hw_addr), (0), (sizeof(data->hw_addr
)));

if (!iwx_nic_lock(sc))
return;

mac_addr0 = htole32(IWX_READ(sc, IWX_CSR_MAC_ADDR0_STRAP(sc)))((__uint32_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
((((sc)->mac_addr_from_csr) + 0x08)))))));
mac_addr1 = htole32(IWX_READ(sc, IWX_CSR_MAC_ADDR1_STRAP(sc)))((__uint32_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
((((sc)->mac_addr_from_csr) + 0x0c)))))));

iwx_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);

/* If OEM fused a valid address, use it instead of the one in OTP. */
if (iwx_is_valid_mac_addr(data->hw_addr)) {
iwx_nic_unlock(sc);
return;
}

mac_addr0 = htole32(IWX_READ(sc, IWX_CSR_MAC_ADDR0_OTP(sc)))((__uint32_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
((((sc)->mac_addr_from_csr) + 0x00)))))));
mac_addr1 = htole32(IWX_READ(sc, IWX_CSR_MAC_ADDR1_OTP(sc)))((__uint32_t)((((sc)->sc_st)->read_4(((sc)->sc_sh), (
((((sc)->mac_addr_from_csr) + 0x04)))))));

iwx_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);

iwx_nic_unlock(sc);
3858}

3860int
3861iwx_is_valid_mac_addr(const uint8_t *addr)
3862{
static const uint8_t reserved_mac[] = {
0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
};

return (memcmp(reserved_mac, addr, ETHER_ADDR_LEN)__builtin_memcmp((reserved_mac), (addr), (6)) != 0 &&
   memcmp(etherbroadcastaddr, addr, sizeof(etherbroadcastaddr))__builtin_memcmp((etherbroadcastaddr), (addr), (sizeof(etherbroadcastaddr
))) != 0 &&
   memcmp(etheranyaddr, addr, sizeof(etheranyaddr))__builtin_memcmp((etheranyaddr), (addr), (sizeof(etheranyaddr
))) != 0 &&
   !ETHER_IS_MULTICAST(addr)(*(addr) & 0x01));
3871}

3873void
3874iwx_flip_hw_address(uint32_t mac_addr0, uint32_t mac_addr1, uint8_t *dest)
3875{
const uint8_t *hw_addr;

hw_addr = (const uint8_t *)&mac_addr0;
dest[0] = hw_addr[3];
dest[1] = hw_addr[2];
dest[2] = hw_addr[1];
dest[3] = hw_addr[0];

hw_addr = (const uint8_t *)&mac_addr1;
dest[4] = hw_addr[1];
dest[5] = hw_addr[0];
3887}

3889int
3890iwx_nvm_get(struct iwx_softc *sc)
3891{
struct iwx_nvm_get_info cmd = {};
struct iwx_nvm_data *nvm = &sc->sc_nvm;
struct iwx_host_cmd hcmd = {
.flags = IWX_CMD_WANT_RESP | IWX_CMD_SEND_IN_RFKILL,
.data = { &cmd, },
.len = { sizeof(cmd) },
.id = IWX_WIDE_ID(IWX_REGULATORY_AND_NVM_GROUP,((0xc << 8) | 0x02)
    IWX_NVM_GET_INFO)((0xc << 8) | 0x02)
};
int err;
uint32_t mac_flags;
/*
* All the values in iwx_nvm_get_info_rsp v4 are the same as
* in v3, except for the channel profile part of the
* regulatory.  So we can just access the new struct, with the
* exception of the latter.
*/
struct iwx_nvm_get_info_rsp *rsp;
struct iwx_nvm_get_info_rsp_v3 *rsp_v3;
int v4 = isset(sc->sc_ucode_api, IWX_UCODE_TLV_API_REGULATORY_NVM_INFO)((sc->sc_ucode_api)[(48)>>3] & (1<<((48)&
(8 -1))));
size_t resp_len = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);

hcmd.resp_pkt_len = sizeof(struct iwx_rx_packet) + resp_len;
err = iwx_send_cmd(sc, &hcmd);
if (err)
return err;

if (iwx_rx_packet_payload_len(hcmd.resp_pkt) != resp_len) {
err = EIO5;
goto out;
}

memset(nvm, 0, sizeof(*nvm))__builtin_memset((nvm), (0), (sizeof(*nvm)));

iwx_set_mac_addr_from_csr(sc, nvm);
if (!iwx_is_valid_mac_addr(nvm->hw_addr)) {
printf("%s: no valid mac address was found\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
err = EINVAL22;
goto out;
}

rsp = (void *)hcmd.resp_pkt->data;

/* Initialize general data */
nvm->nvm_version = le16toh(rsp->general.nvm_version)((__uint16_t)(rsp->general.nvm_version));
nvm->n_hw_addrs = rsp->general.n_hw_addrs;

/* Initialize MAC sku data */
mac_flags = le32toh(rsp->mac_sku.mac_sku_flags)((__uint32_t)(rsp->mac_sku.mac_sku_flags));
nvm->sku_cap_11ac_enable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED(1 << 3));
nvm->sku_cap_11n_enable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED(1 << 2));
nvm->sku_cap_11ax_enable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED(1 << 4));
nvm->sku_cap_band_24GHz_enable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED(1 << 0));
nvm->sku_cap_band_52GHz_enable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED(1 << 1));
nvm->sku_cap_mimo_disable =
!!(mac_flags & IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED(1 << 5));

/* Initialize PHY sku data */
nvm->valid_tx_ant = (uint8_t)le32toh(rsp->phy_sku.tx_chains)((__uint32_t)(rsp->phy_sku.tx_chains));
nvm->valid_rx_ant = (uint8_t)le32toh(rsp->phy_sku.rx_chains)((__uint32_t)(rsp->phy_sku.rx_chains));

if (le32toh(rsp->regulatory.lar_enabled)((__uint32_t)(rsp->regulatory.lar_enabled)) &&
   isset(sc->sc_enabled_capa, IWX_UCODE_TLV_CAPA_LAR_SUPPORT)((sc->sc_enabled_capa)[(1)>>3] & (1<<((1)&
(8 -1))))) {
nvm->lar_enabled = 1;
}

if (v4) {
iwx_init_channel_map(sc, NULL((void *)0),
    rsp->regulatory.channel_profile, IWX_NUM_CHANNELS110);
} else {
rsp_v3 = (void *)rsp;
iwx_init_channel_map(sc, rsp_v3->regulatory.channel_profile,
    NULL((void *)0), IWX_NUM_CHANNELS_V151);
}
3971out:
iwx_free_resp(sc, &hcmd);
return err;
3974}

3976int
3977iwx_load_firmware(struct iwx_softc *sc)
3978{
struct iwx_fw_sects *fws;
int err;

splassert(IPL_NET)do { if (splassert_ctl > 0) { splassert_check(0x4, __func__
); } } while (0);

sc->sc_uc.uc_intr = 0;
sc->sc_uc.uc_ok = 0;

fws = &sc->sc_fw.fw_sects[IWX_UCODE_TYPE_REGULAR];
if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
err = iwx_ctxt_info_gen3_init(sc, fws);
else
err = iwx_ctxt_info_init(sc, fws);
if (err) {
printf("%s: could not init context info\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return err;
}

/* wait for the firmware to load */
err = tsleep_nsec(&sc->sc_uc, 0, "iwxuc", SEC_TO_NSEC(1));
if (err || !sc->sc_uc.uc_ok) {
printf("%s: could not load firmware, %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), err);
iwx_ctxt_info_free_paging(sc);
}

iwx_dma_contig_free(&sc->iml_dma);
iwx_ctxt_info_free_fw_img(sc);

if (!sc->sc_uc.uc_ok)
return EINVAL22;

return err;
4011}

4013int
4014iwx_start_fw(struct iwx_softc *sc)
4015{
int err;

IWX_WRITE(sc, IWX_CSR_INT, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x008))), (
(~0))));

iwx_disable_interrupts(sc);

/* make sure rfkill handshake bits are cleared */
IWX_WRITE(sc, IWX_CSR_UCODE_DRV_GP1_CLR, IWX_CSR_UCODE_SW_BIT_RFKILL)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x05c))), (
((0x00000002)))));
IWX_WRITE(sc, IWX_CSR_UCODE_DRV_GP1_CLR,(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x05c))), (
((0x00000004)))))
   IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x05c))), (
((0x00000004)))));

/* clear (again), then enable firmware load interrupt */
IWX_WRITE(sc, IWX_CSR_INT, ~0)(((sc)->sc_st)->write_4(((sc)->sc_sh), (((0x008))), (
(~0))));

err = iwx_nic_init(sc);
if (err) {
printf("%s: unable to init nic\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
return err;
}

iwx_enable_fwload_interrupt(sc);

return iwx_load_firmware(sc);
4039}

4041int
4042iwx_pnvm_handle_section(struct iwx_softc *sc, const uint8_t *data,
  size_t len)
4044{
const struct iwx_ucode_tlv *tlv;
uint32_t sha1 = 0;
uint16_t mac_type = 0, rf_id = 0;
uint8_t *pnvm_data = NULL((void *)0), *tmp;
int hw_match = 0;
uint32_t size = 0;
int err;

while (len >= sizeof(*tlv)) {
uint32_t tlv_len, tlv_type;

len -= sizeof(*tlv);
tlv = (const void *)data;

tlv_len = le32toh(tlv->length)((__uint32_t)(tlv->length));
tlv_type = le32toh(tlv->type)((__uint32_t)(tlv->type));

if (len < tlv_len) {
	printf("%s: invalid TLV len: %zd/%u\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), len, tlv_len);
	err = EINVAL22;
	goto out;
}

data += sizeof(*tlv);

switch (tlv_type) {
case IWX_UCODE_TLV_PNVM_VERSION62:
	if (tlv_len < sizeof(uint32_t))
		break;

	sha1 = le32_to_cpup((const uint32_t *)data)(((__uint32_t)(*(const uint32_t *)((const uint32_t *)data))));
	break;
case IWX_UCODE_TLV_HW_TYPE58:
	if (tlv_len < 2 * sizeof(uint16_t))
		break;

	if (hw_match)
		break;

	mac_type = le16_to_cpup((const uint16_t *)data)(((__uint16_t)(*(const uint16_t *)((const uint16_t *)data))));
	rf_id = le16_to_cpup((const uint16_t *)(data +(((__uint16_t)(*(const uint16_t *)((const uint16_t *)(data + sizeof
(uint16_t))))))
	    sizeof(uint16_t)))(((__uint16_t)(*(const uint16_t *)((const uint16_t *)(data + sizeof
(uint16_t))))));

	if (mac_type == IWX_CSR_HW_REV_TYPE(sc->sc_hw_rev)(((sc->sc_hw_rev) & 0x000FFF0) >> 4) &&
	    rf_id == IWX_CSR_HW_RFID_TYPE(sc->sc_hw_rf_id)(((sc->sc_hw_rf_id) & 0x0FFF000) >> 12))
		hw_match = 1;
	break;
case IWX_UCODE_TLV_SEC_RT19: {
	const struct iwx_pnvm_section *section;
	uint32_t data_len;

	section = (const void *)data;
	data_len = tlv_len - sizeof(*section);

	/* TODO: remove, this is a deprecated separator */
	if (le32_to_cpup((const uint32_t *)data)(((__uint32_t)(*(const uint32_t *)((const uint32_t *)data)))) == 0xddddeeee)
		break;

	tmp = malloc(size + data_len, M_DEVBUF2,
	    M_WAITOK0x0001 | M_CANFAIL0x0004 | M_ZERO0x0008);
	if (tmp == NULL((void *)0)) {
		err = ENOMEM12;
		goto out;
	}
	memcpy(tmp, pnvm_data, size)__builtin_memcpy((tmp), (pnvm_data), (size));
	memcpy(tmp + size, section->data, data_len)__builtin_memcpy((tmp + size), (section->data), (data_len)
);
	free(pnvm_data, M_DEVBUF2, size);
	pnvm_data = tmp;
	size += data_len;
	break;
}
case IWX_UCODE_TLV_PNVM_SKU64:
	/* New PNVM section started, stop parsing. */
	goto done;
default:
	break;
}

if (roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4)) > len)
	break;
len -= roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
data += roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
}
4129done:
if (!hw_match || size == 0) {
err = ENOENT2;
goto out;
}

err = iwx_dma_contig_alloc(sc->sc_dmat, &sc->pnvm_dma, size, 0);
if (err) {
printf("%s: could not allocate DMA memory for PNVM\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
err = ENOMEM12;
goto out;
}
memcpy(sc->pnvm_dma.vaddr, pnvm_data, size)__builtin_memcpy((sc->pnvm_dma.vaddr), (pnvm_data), (size)
);
iwx_ctxt_info_gen3_set_pnvm(sc);
sc->sc_pnvm_ver = sha1;
4145out:
free(pnvm_data, M_DEVBUF2, size);
return err;
4148}

4150int
4151iwx_pnvm_parse(struct iwx_softc *sc, const uint8_t *data, size_t len)
4152{
const struct iwx_ucode_tlv *tlv;

while (len >= sizeof(*tlv)) {
uint32_t tlv_len, tlv_type;

len -= sizeof(*tlv);
tlv = (const void *)data;

tlv_len = le32toh(tlv->length)((__uint32_t)(tlv->length));
tlv_type = le32toh(tlv->type)((__uint32_t)(tlv->type));

if (len < tlv_len || roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4)) > len)
	return EINVAL22;

if (tlv_type == IWX_UCODE_TLV_PNVM_SKU64) {
	const struct iwx_sku_id *sku_id =
		(const void *)(data + sizeof(*tlv));

	data += sizeof(*tlv) + roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
	len -= roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));

	if (sc->sc_sku_id[0] == le32toh(sku_id->data[0])((__uint32_t)(sku_id->data[0])) &&
	    sc->sc_sku_id[1] == le32toh(sku_id->data[1])((__uint32_t)(sku_id->data[1])) &&
	    sc->sc_sku_id[2] == le32toh(sku_id->data[2])((__uint32_t)(sku_id->data[2])) &&
	    iwx_pnvm_handle_section(sc, data, len) == 0)
		return 0;
} else {
	data += sizeof(*tlv) + roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
	len -= roundup(tlv_len, 4)((((tlv_len)+((4)-1))/(4))*(4));
}
}

return ENOENT2;
4186}

4188/* Make AX210 firmware loading context point at PNVM image in DMA memory. */
4189void
4190iwx_ctxt_info_gen3_set_pnvm(struct iwx_softc *sc)
4191{
struct iwx_prph_scratch *prph_scratch;
struct iwx_prph_scratch_ctrl_cfg *prph_sc_ctrl;

prph_scratch = sc->prph_scratch_dma.vaddr;
prph_sc_ctrl = &prph_scratch->ctrl_cfg;

prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = htole64(sc->pnvm_dma.paddr)((__uint64_t)(sc->pnvm_dma.paddr));
prph_sc_ctrl->pnvm_cfg.pnvm_size = htole32(sc->pnvm_dma.size)((__uint32_t)(sc->pnvm_dma.size));

bus_dmamap_sync(sc->sc_dmat, sc->pnvm_dma.map, 0, sc->pnvm_dma.size,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
pnvm_dma.map), (0), (sc->pnvm_dma.size), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
pnvm_dma.map), (0), (sc->pnvm_dma.size), (0x04));
4203}

4205/*
* Load platform-NVM (non-volatile-memory) data from the filesystem.
* This data apparently contains regulatory information and affects device
* channel configuration.
* The SKU of AX210 devices tells us which PNVM file section is needed.
* Pre-AX210 devices store NVM data onboard.
*/
4212int
4213iwx_load_pnvm(struct iwx_softc *sc)
4214{
const int wait_flags = IWX_PNVM_COMPLETE0x04;
int s, err = 0;
u_char *pnvm_data = NULL((void *)0);
size_t pnvm_size = 0;

if (sc->sc_sku_id[0] == 0 &&
   sc->sc_sku_id[1] == 0 &&
   sc->sc_sku_id[2] == 0)
return 0;

if (sc->sc_pnvm_name) {
if (sc->pnvm_dma.vaddr == NULL((void *)0)) {
	err = loadfirmware(sc->sc_pnvm_name,
	    &pnvm_data, &pnvm_size);
	if (err) {
		printf("%s: could not read %s (error %d)\n",
		    DEVNAME(sc)((sc)->sc_dev.dv_xname), sc->sc_pnvm_name, err);
		return err;
	}

	err = iwx_pnvm_parse(sc, pnvm_data, pnvm_size);
	if (err && err != ENOENT2) {
		free(pnvm_data, M_DEVBUF2, pnvm_size);
		return err;
	}
} else
	iwx_ctxt_info_gen3_set_pnvm(sc);
}

s = splnet()splraise(0x4);

if (!iwx_nic_lock(sc)) {
splx(s)spllower(s);
free(pnvm_data, M_DEVBUF2, pnvm_size);
return EBUSY16;
}

/*
* If we don't have a platform NVM file simply ask firmware
* to proceed without it.
*/

iwx_write_umac_prph(sc, IWX_UREG_DOORBELL_TO_ISR60xa05c04,
   IWX_UREG_DOORBELL_TO_ISR6_PNVM(1 << 20));

/* Wait for the pnvm complete notification from firmware. */
while ((sc->sc_init_complete & wait_flags) != wait_flags) {
err = tsleep_nsec(&sc->sc_init_complete, 0, "iwxinit",
    SEC_TO_NSEC(2));
if (err)
	break;
}

splx(s)spllower(s);
iwx_nic_unlock(sc);
free(pnvm_data, M_DEVBUF2, pnvm_size);
return err;
4272}

4274int
4275iwx_send_tx_ant_cfg(struct iwx_softc *sc, uint8_t valid_tx_ant)
4276{
struct iwx_tx_ant_cfg_cmd tx_ant_cmd = {
.valid = htole32(valid_tx_ant)((__uint32_t)(valid_tx_ant)),
};

return iwx_send_cmd_pdu(sc, IWX_TX_ANT_CONFIGURATION_CMD0x98,
   0, sizeof(tx_ant_cmd), &tx_ant_cmd);
4283}

4285int
4286iwx_send_phy_cfg_cmd(struct iwx_softc *sc)
4287{
struct iwx_phy_cfg_cmd phy_cfg_cmd;

phy_cfg_cmd.phy_cfg = htole32(sc->sc_fw_phy_config)((__uint32_t)(sc->sc_fw_phy_config));
phy_cfg_cmd.calib_control.event_trigger =
   sc->sc_default_calib[IWX_UCODE_TYPE_REGULAR].event_trigger;
phy_cfg_cmd.calib_control.flow_trigger =
   sc->sc_default_calib[IWX_UCODE_TYPE_REGULAR].flow_trigger;

return iwx_send_cmd_pdu(sc, IWX_PHY_CONFIGURATION_CMD0x6a, 0,
   sizeof(phy_cfg_cmd), &phy_cfg_cmd);
4298}

4300int
4301iwx_send_dqa_cmd(struct iwx_softc *sc)
4302{
struct iwx_dqa_enable_cmd dqa_cmd = {
.cmd_queue = htole32(IWX_DQA_CMD_QUEUE)((__uint32_t)(0)),
};
uint32_t cmd_id;

cmd_id = iwx_cmd_id(IWX_DQA_ENABLE_CMD0x00, IWX_DATA_PATH_GROUP0x5, 0);
return iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
4310}

4312int
4313iwx_load_ucode_wait_alive(struct iwx_softc *sc)
4314{
int err;

err = iwx_read_firmware(sc);
if (err)
return err;

err = iwx_start_fw(sc);
if (err)
return err;

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
err = iwx_load_pnvm(sc);
if (err)
	return err;
}

iwx_post_alive(sc);

return 0;
4334}

4336int
4337iwx_run_init_mvm_ucode(struct iwx_softc *sc, int readnvm)
4338{
const int wait_flags = IWX_INIT_COMPLETE0x01;
struct iwx_nvm_access_complete_cmd nvm_complete = {};
struct iwx_init_extended_cfg_cmd init_cfg = {
.init_flags = htole32(IWX_INIT_NVM)((__uint32_t)((1 << 1))),
};
int err, s;

if ((sc->sc_flags & IWX_FLAG_RFKILL0x02) && !readnvm) {
printf("%s: radio is disabled by hardware switch\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
return EPERM1;
}

s = splnet()splraise(0x4);
sc->sc_init_complete = 0;
err = iwx_load_ucode_wait_alive(sc);
if (err) {
printf("%s: failed to load init firmware\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
splx(s)spllower(s);
return err;
}

/*
* Send init config command to mark that we are sending NVM
* access commands
*/
err = iwx_send_cmd_pdu(sc, IWX_WIDE_ID(IWX_SYSTEM_GROUP,((0x2 << 8) | 0x03)
   IWX_INIT_EXTENDED_CFG_CMD)((0x2 << 8) | 0x03), 0, sizeof(init_cfg), &init_cfg);
if (err) {
splx(s)spllower(s);
return err;
}

err = iwx_send_cmd_pdu(sc, IWX_WIDE_ID(IWX_REGULATORY_AND_NVM_GROUP,((0xc << 8) | 0x00)
   IWX_NVM_ACCESS_COMPLETE)((0xc << 8) | 0x00), 0, sizeof(nvm_complete), &nvm_complete);
if (err) {
splx(s)spllower(s);
return err;
}

/* Wait for the init complete notification from the firmware. */
while ((sc->sc_init_complete & wait_flags) != wait_flags) {
err = tsleep_nsec(&sc->sc_init_complete, 0, "iwxinit",
    SEC_TO_NSEC(2));
if (err) {
	splx(s)spllower(s);
	return err;
}
}
splx(s)spllower(s);
if (readnvm) {
err = iwx_nvm_get(sc);
if (err) {
	printf("%s: failed to read nvm\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return err;
}
if (IEEE80211_ADDR_EQ(etheranyaddr, sc->sc_ic.ic_myaddr)(__builtin_memcmp((etheranyaddr), (sc->sc_ic.ic_myaddr), (
6)) == 0))
	IEEE80211_ADDR_COPY(sc->sc_ic.ic_myaddr,__builtin_memcpy((sc->sc_ic.ic_myaddr), (sc->sc_nvm.hw_addr
), (6))
	    sc->sc_nvm.hw_addr)__builtin_memcpy((sc->sc_ic.ic_myaddr), (sc->sc_nvm.hw_addr
), (6));

}
return 0;
4401}

4403int
4404iwx_config_ltr(struct iwx_softc *sc)
4405{
struct iwx_ltr_config_cmd cmd = {
.flags = htole32(IWX_LTR_CFG_FLAG_FEATURE_ENABLE)((__uint32_t)(0x00000001)),
};

if (!sc->sc_ltr_enabled)
return 0;

return iwx_send_cmd_pdu(sc, IWX_LTR_CONFIG0xee, 0, sizeof(cmd), &cmd);
4414}

4416void
4417iwx_update_rx_desc(struct iwx_softc *sc, struct iwx_rx_ring *ring, int idx)
4418{
struct iwx_rx_data *data = &ring->data[idx];

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
struct iwx_rx_transfer_desc *desc = ring->desc;
desc[idx].rbid = htole16(idx & 0xffff)((__uint16_t)(idx & 0xffff));
desc[idx].addr = htole64(data->map->dm_segs[0].ds_addr)((__uint64_t)(data->map->dm_segs[0].ds_addr));
bus_dmamap_sync(sc->sc_dmat, ring->free_desc_dma.map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(*desc)), (sizeof(*desc)), (
0x04))
    idx * sizeof(*desc), sizeof(*desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(*desc)), (sizeof(*desc)), (
0x04))
    BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(*desc)), (sizeof(*desc)), (
0x04));
} else {
((uint64_t *)ring->desc)[idx] =
    htole64(data->map->dm_segs[0].ds_addr | (idx & 0x0fff))((__uint64_t)(data->map->dm_segs[0].ds_addr | (idx &
 0x0fff)));
bus_dmamap_sync(sc->sc_dmat, ring->free_desc_dma.map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(uint64_t)), (sizeof(uint64_t
)), (0x04))
    idx * sizeof(uint64_t), sizeof(uint64_t),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(uint64_t)), (sizeof(uint64_t
)), (0x04))
    BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
free_desc_dma.map), (idx * sizeof(uint64_t)), (sizeof(uint64_t
)), (0x04));
}
4435}

4437int
4438iwx_rx_addbuf(struct iwx_softc *sc, int size, int idx)
4439{
struct iwx_rx_ring *ring = &sc->rxq;
struct iwx_rx_data *data = &ring->data[idx];
struct mbuf *m;
int err;
int fatal = 0;

m = m_gethdr(M_DONTWAIT0x0002, MT_DATA1);
if (m == NULL((void *)0))
return ENOBUFS55;

if (size <= MCLBYTES(1 << 11)) {
MCLGET(m, M_DONTWAIT)(void) m_clget((m), (0x0002), (1 << 11));
} else {
MCLGETL(m, M_DONTWAIT, IWX_RBUF_SIZE)m_clget((m), (0x0002), (4096));
}
if ((m->m_flagsm_hdr.mh_flags & M_EXT0x0001) == 0) {
m_freem(m);
return ENOBUFS55;
}

if (data->m != NULL((void *)0)) {
bus_dmamap_unload(sc->sc_dmat, data->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (data
->map));
fatal = 1;
}

m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_extM_dat.MH.MH_dat.MH_ext.ext_size;
err = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
data->map), (m), (0x0200|0x0001))
   BUS_DMA_READ|BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
data->map), (m), (0x0200|0x0001));
if (err) {
/* XXX */
if (fatal)
	panic("%s: could not load RX mbuf", DEVNAME(sc)((sc)->sc_dev.dv_xname));
m_freem(m);
return err;
}
data->m = m;
bus_dmamap_sync(sc->sc_dmat, data->map, 0, size, BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (size), (0x01));

/* Update RX descriptor. */
iwx_update_rx_desc(sc, ring, idx);

return 0;
4482}

4484int
4485iwx_rxmq_get_signal_strength(struct iwx_softc *sc,
  struct iwx_rx_mpdu_desc *desc)
4487{
int energy_a, energy_b;

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
energy_a = desc->v3.energy_a;
energy_b = desc->v3.energy_b;
} else {
energy_a = desc->v1.energy_a;
energy_b = desc->v1.energy_b;
}
energy_a = energy_a ? -energy_a : -256;
energy_b = energy_b ? -energy_b : -256;
return MAX(energy_a, energy_b)(((energy_a)>(energy_b))?(energy_a):(energy_b));
4500}

4502void
4503iwx_rx_rx_phy_cmd(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
  struct iwx_rx_data *data)
4505{
struct iwx_rx_phy_info *phy_info = (void *)pkt->data;

bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*pkt),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (sizeof(*pkt)), (sizeof(*phy_info)), (0x02))
   sizeof(*phy_info), BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (sizeof(*pkt)), (sizeof(*phy_info)), (0x02));

memcpy(&sc->sc_last_phy_info, phy_info, sizeof(sc->sc_last_phy_info))__builtin_memcpy((&sc->sc_last_phy_info), (phy_info), (
sizeof(sc->sc_last_phy_info)));
4512}

4514/*
* Retrieve the average noise (in dBm) among receivers.
*/
4517int
4518iwx_get_noise(const struct iwx_statistics_rx_non_phy *stats)
4519{
int i, total, nbant, noise;

total = nbant = noise = 0;
for (i = 0; i < 3; i++) {
noise = letoh32(stats->beacon_silence_rssi[i])((__uint32_t)(stats->beacon_silence_rssi[i])) & 0xff;
if (noise) {
	total += noise;
	nbant++;
}
}

/* There should be at least one antenna but check anyway. */
return (nbant == 0) ? -127 : (total / nbant) - 107;
4533}

4535int
4536iwx_ccmp_decap(struct iwx_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
  struct ieee80211_rxinfo *rxi)
4538{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_key *k;
struct ieee80211_frame *wh;
uint64_t pn, *prsc;
uint8_t *ivp;
uint8_t tid;
int hdrlen, hasqos;

wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
hdrlen = ieee80211_get_hdrlen(wh);
ivp = (uint8_t *)wh + hdrlen;

/* find key for decryption */
k = ieee80211_get_rxkey(ic, m, ni);
if (k == NULL((void *)0) || k->k_cipher != IEEE80211_CIPHER_CCMP)
return 1;

/* Check that ExtIV bit is be set. */
if (!(ivp[3] & IEEE80211_WEP_EXTIV0x20))
return 1;

hasqos = ieee80211_has_qos(wh);
tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID0x000f : 0;
prsc = &k->k_rsc[tid];

/* Extract the 48-bit PN from the CCMP header. */
pn = (uint64_t)ivp[0]       |
    (uint64_t)ivp[1] <<  8 |
    (uint64_t)ivp[4] << 16 |
    (uint64_t)ivp[5] << 24 |
    (uint64_t)ivp[6] << 32 |
    (uint64_t)ivp[7] << 40;
if (rxi->rxi_flags & IEEE80211_RXI_HWDEC_SAME_PN0x00000004) {
if (pn < *prsc) {
	ic->ic_stats.is_ccmp_replays++;
	return 1;
}
} else if (pn <= *prsc) {
ic->ic_stats.is_ccmp_replays++;
return 1;
}
/* Last seen packet number is updated in ieee80211_inputm(). */

/*
* Some firmware versions strip the MIC, and some don't. It is not
* clear which of the capability flags could tell us what to expect.
* For now, keep things simple and just leave the MIC in place if
* it is present.
*
* The IV will be stripped by ieee80211_inputm().
*/
return 0;
4591}

4593int
4594iwx_rx_hwdecrypt(struct iwx_softc *sc, struct mbuf *m, uint32_t rx_pkt_status,
  struct ieee80211_rxinfo *rxi)
4596{
struct ieee80211com *ic = &sc->sc_ic;
struct ifnet *ifp = IC2IFP(ic)(&(ic)->ic_ac.ac_if);
struct ieee80211_frame *wh;
struct ieee80211_node *ni;
int ret = 0;
uint8_t type, subtype;

wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));

type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
if (type == IEEE80211_FC0_TYPE_CTL0x04)
return 0;

subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK0xf0;
if (ieee80211_has_qos(wh) && (subtype & IEEE80211_FC0_SUBTYPE_NODATA0x40))
return 0;

ni = ieee80211_find_rxnode(ic, wh);
/* Handle hardware decryption. */
if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c) != IEEE80211_FC0_TYPE_CTL0x04)
   && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) &&
   (ni->ni_flags & IEEE80211_NODE_RXPROT0x0008) &&
   ((!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
   ni->ni_rsncipher == IEEE80211_CIPHER_CCMP) ||
   (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
   ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) {
if ((rx_pkt_status & IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK(7 << 8)) !=
    IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC(2 << 8)) {
	ic->ic_stats.is_ccmp_dec_errs++;
	ret = 1;
	goto out;
}
/* Check whether decryption was successful or not. */
if ((rx_pkt_status &
    (IWX_RX_MPDU_RES_STATUS_DEC_DONE(1 << 11) |
    IWX_RX_MPDU_RES_STATUS_MIC_OK(1 << 6))) !=
    (IWX_RX_MPDU_RES_STATUS_DEC_DONE(1 << 11) |
    IWX_RX_MPDU_RES_STATUS_MIC_OK(1 << 6))) {
	ic->ic_stats.is_ccmp_dec_errs++;
	ret = 1;
	goto out;
}
rxi->rxi_flags |= IEEE80211_RXI_HWDEC0x00000001;
}
4641out:
if (ret)
ifp->if_ierrorsif_data.ifi_ierrors++;
ieee80211_release_node(ic, ni);
return ret;
4646}

4648void
4649iwx_rx_frame(struct iwx_softc *sc, struct mbuf *m, int chanidx,
  uint32_t rx_pkt_status, int is_shortpre, int rate_n_flags,
  uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,
  struct mbuf_list *ml)
4653{
struct ieee80211com *ic = &sc->sc_ic;
struct ifnet *ifp = IC2IFP(ic)(&(ic)->ic_ac.ac_if);
struct ieee80211_frame *wh;
struct ieee80211_node *ni;

if (chanidx < 0 || chanidx >= nitems(ic->ic_channels)(sizeof((ic->ic_channels)) / sizeof((ic->ic_channels)[0
])))
chanidx = ieee80211_chan2ieee(ic, ic->ic_ibss_chan);

wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
ni = ieee80211_find_rxnode(ic, wh);
if ((rxi->rxi_flags & IEEE80211_RXI_HWDEC0x00000001) &&
   iwx_ccmp_decap(sc, m, ni, rxi) != 0) {
ifp->if_ierrorsif_data.ifi_ierrors++;
m_freem(m);
ieee80211_release_node(ic, ni);
return;
}

4672#if NBPFILTER1 > 0
if (sc->sc_drvbpf != NULL((void *)0)) {
struct iwx_rx_radiotap_header *tap = &sc->sc_rxtapsc_rxtapu.th;
uint16_t chan_flags;
int have_legacy_rate = 1;
uint8_t mcs, rate;

tap->wr_flags = 0;
if (is_shortpre)
	tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
tap->wr_chan_freq =
    htole16(ic->ic_channels[chanidx].ic_freq)((__uint16_t)(ic->ic_channels[chanidx].ic_freq));
chan_flags = ic->ic_channels[chanidx].ic_flags;
if (ic->ic_curmode != IEEE80211_MODE_11N &&
    ic->ic_curmode != IEEE80211_MODE_11AC) {
	chan_flags &= ~IEEE80211_CHAN_HT0x2000;
	chan_flags &= ~IEEE80211_CHAN_40MHZ0x8000;
}
if (ic->ic_curmode != IEEE80211_MODE_11AC)
	chan_flags &= ~IEEE80211_CHAN_VHT0x4000;
tap->wr_chan_flags = htole16(chan_flags)((__uint16_t)(chan_flags));
tap->wr_dbm_antsignal = (int8_t)rxi->rxi_rssi;
tap->wr_dbm_antnoise = (int8_t)sc->sc_noise;
tap->wr_tsft = device_timestamp;
if (sc->sc_rate_n_flags_version >= 2) {
	uint32_t mod_type = (rate_n_flags &
	    IWX_RATE_MCS_MOD_TYPE_MSK(0x7 << 8));
	const struct ieee80211_rateset *rs = NULL((void *)0);
	uint32_t ridx;
	have_legacy_rate = (mod_type == IWX_RATE_MCS_CCK_MSK(0 << 8) ||
	    mod_type == IWX_RATE_MCS_LEGACY_OFDM_MSK(1 << 8));
	mcs = (rate_n_flags & IWX_RATE_HT_MCS_CODE_MSK0x7);
	ridx = (rate_n_flags & IWX_RATE_LEGACY_RATE_MSK0x7);
	if (mod_type == IWX_RATE_MCS_CCK_MSK(0 << 8))
		rs = &ieee80211_std_rateset_11b;
	else if (mod_type == IWX_RATE_MCS_LEGACY_OFDM_MSK(1 << 8))
		rs = &ieee80211_std_rateset_11a;
	if (rs && ridx < rs->rs_nrates) {
		rate = (rs->rs_rates[ridx] &
		    IEEE80211_RATE_VAL0x7f);
	} else
		rate = 0;
} else {
	have_legacy_rate = ((rate_n_flags &
	    (IWX_RATE_MCS_HT_MSK_V1(1 << 8) |
	    IWX_RATE_MCS_VHT_MSK_V1(1 << 26))) == 0);
	mcs = (rate_n_flags &
	    (IWX_RATE_HT_MCS_RATE_CODE_MSK_V10x7 |
	    IWX_RATE_HT_MCS_NSS_MSK_V1(3 << 3)));
	rate = (rate_n_flags & IWX_RATE_LEGACY_RATE_MSK_V10xff);
}
if (!have_legacy_rate) {
	tap->wr_rate = (0x80 | mcs);
} else {
	switch (rate) {
	/* CCK rates. */
	case  10: tap->wr_rate =   2; break;
	case  20: tap->wr_rate =   4; break;
	case  55: tap->wr_rate =  11; break;
	case 110: tap->wr_rate =  22; break;
	/* OFDM rates. */
	case 0xd: tap->wr_rate =  12; break;
	case 0xf: tap->wr_rate =  18; break;
	case 0x5: tap->wr_rate =  24; break;
	case 0x7: tap->wr_rate =  36; break;
	case 0x9: tap->wr_rate =  48; break;
	case 0xb: tap->wr_rate =  72; break;
	case 0x1: tap->wr_rate =  96; break;
	case 0x3: tap->wr_rate = 108; break;
	/* Unknown rate: should not happen. */
	default:  tap->wr_rate =   0;
	}
}

bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len,
    m, BPF_DIRECTION_IN(1 << 0));
}
4749#endif
ieee80211_inputm(IC2IFP(ic)(&(ic)->ic_ac.ac_if), m, ni, rxi, ml);
ieee80211_release_node(ic, ni);
4752}

4754/*
* Drop duplicate 802.11 retransmissions
* (IEEE 802.11-2012: 9.3.2.10 "Duplicate detection and recovery")
* and handle pseudo-duplicate frames which result from deaggregation
* of A-MSDU frames in hardware.
*/
4760int
4761iwx_detect_duplicate(struct iwx_softc *sc, struct mbuf *m,
  struct iwx_rx_mpdu_desc *desc, struct ieee80211_rxinfo *rxi)
4763{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_node *in = (void *)ic->ic_bss;
struct iwx_rxq_dup_data *dup_data = &in->dup_data;
uint8_t tid = IWX_MAX_TID_COUNT8, subframe_idx;
struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK0xf0;
int hasqos = ieee80211_has_qos(wh);
uint16_t seq;

if (type == IEEE80211_FC0_TYPE_CTL0x04 ||
   (hasqos && (subtype & IEEE80211_FC0_SUBTYPE_NODATA0x40)) ||
   IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01))
return 0;

if (hasqos) {
tid = (ieee80211_get_qos(wh) & IEEE80211_QOS_TID0x000f);
if (tid > IWX_MAX_TID_COUNT8)
	tid = IWX_MAX_TID_COUNT8;
}

/* If this wasn't a part of an A-MSDU the sub-frame index will be 0 */
subframe_idx = desc->amsdu_info &
IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK0x7f;

seq = letoh16(*(u_int16_t *)wh->i_seq)((__uint16_t)(*(u_int16_t *)wh->i_seq)) >> IEEE80211_SEQ_SEQ_SHIFT4;
if ((wh->i_fc[1] & IEEE80211_FC1_RETRY0x08) &&
   dup_data->last_seq[tid] == seq &&
   dup_data->last_sub_frame[tid] >= subframe_idx)
return 1;

/*
* Allow the same frame sequence number for all A-MSDU subframes
* following the first subframe.
* Otherwise these subframes would be discarded as replays.
*/
if (dup_data->last_seq[tid] == seq &&
   subframe_idx > dup_data->last_sub_frame[tid] &&
   (desc->mac_flags2 & IWX_RX_MPDU_MFLG2_AMSDU0x40)) {
rxi->rxi_flags |= IEEE80211_RXI_SAME_SEQ0x00000008;
}

dup_data->last_seq[tid] = seq;
dup_data->last_sub_frame[tid] = subframe_idx;

return 0;
4810}

4812/*
* Returns true if sn2 - buffer_size < sn1 < sn2.
* To be used only in order to compare reorder buffer head with NSSN.
* We fully trust NSSN unless it is behind us due to reorder timeout.
* Reorder timeout can only bring us up to buffer_size SNs ahead of NSSN.
*/
4818int
4819iwx_is_sn_less(uint16_t sn1, uint16_t sn2, uint16_t buffer_size)
4820{
return SEQ_LT(sn1, sn2)((((u_int16_t)(sn1) - (u_int16_t)(sn2)) & 0xfff) > 2048
) && !SEQ_LT(sn1, sn2 - buffer_size)((((u_int16_t)(sn1) - (u_int16_t)(sn2 - buffer_size)) & 0xfff
) > 2048);
4822}

4824void
4825iwx_release_frames(struct iwx_softc *sc, struct ieee80211_node *ni,
  struct iwx_rxba_data *rxba, struct iwx_reorder_buffer *reorder_buf,
  uint16_t nssn, struct mbuf_list *ml)
4828{
struct iwx_reorder_buf_entry *entries = &rxba->entries[0];
uint16_t ssn = reorder_buf->head_sn;

/* ignore nssn smaller than head sn - this can happen due to timeout */
if (iwx_is_sn_less(nssn, ssn, reorder_buf->buf_size))
goto set_timer;

while (iwx_is_sn_less(ssn, nssn, reorder_buf->buf_size)) {
int index = ssn % reorder_buf->buf_size;
struct mbuf *m;
int chanidx, is_shortpre;
uint32_t rx_pkt_status, rate_n_flags, device_timestamp;
struct ieee80211_rxinfo *rxi;

/* This data is the same for all A-MSDU subframes. */
chanidx = entries[index].chanidx;
rx_pkt_status = entries[index].rx_pkt_status;
is_shortpre = entries[index].is_shortpre;
rate_n_flags = entries[index].rate_n_flags;
device_timestamp = entries[index].device_timestamp;
rxi = &entries[index].rxi;

/*
 * Empty the list. Will have more than one frame for A-MSDU.
 * Empty list is valid as well since nssn indicates frames were
 * received.
 */
while ((m = ml_dequeue(&entries[index].frames)) != NULL((void *)0)) {
	iwx_rx_frame(sc, m, chanidx, rx_pkt_status, is_shortpre,
	    rate_n_flags, device_timestamp, rxi, ml);
	reorder_buf->num_stored--;

	/*
	 * Allow the same frame sequence number and CCMP PN for
	 * all A-MSDU subframes following the first subframe.
	 * Otherwise they would be discarded as replays.
	 */
	rxi->rxi_flags |= IEEE80211_RXI_SAME_SEQ0x00000008;
	rxi->rxi_flags |= IEEE80211_RXI_HWDEC_SAME_PN0x00000004;
}

ssn = (ssn + 1) & 0xfff;
}
reorder_buf->head_sn = nssn;

4874set_timer:
if (reorder_buf->num_stored && !reorder_buf->removed) {
timeout_add_usec(&reorder_buf->reorder_timer,
    RX_REORDER_BUF_TIMEOUT_MQ_USEC(100000ULL));
} else
timeout_del(&reorder_buf->reorder_timer);
4880}

4882int
4883iwx_oldsn_workaround(struct iwx_softc *sc, struct ieee80211_node *ni, int tid,
  struct iwx_reorder_buffer *buffer, uint32_t reorder_data, uint32_t gp2)
4885{
struct ieee80211com *ic = &sc->sc_ic;

if (gp2 != buffer->consec_oldsn_ampdu_gp2) {
/* we have a new (A-)MPDU ... */

/*
 * reset counter to 0 if we didn't have any oldsn in
 * the last A-MPDU (as detected by GP2 being identical)
 */
if (!buffer->consec_oldsn_prev_drop)
	buffer->consec_oldsn_drops = 0;

/* either way, update our tracking state */
buffer->consec_oldsn_ampdu_gp2 = gp2;
} else if (buffer->consec_oldsn_prev_drop) {
/*
 * tracking state didn't change, and we had an old SN
 * indication before - do nothing in this case, we
 * already noted this one down and are waiting for the
 * next A-MPDU (by GP2)
 */
return 0;
}

/* return unless this MPDU has old SN */
if (!(reorder_data & IWX_RX_MPDU_REORDER_BA_OLD_SN0x80000000))
return 0;

/* update state */
buffer->consec_oldsn_prev_drop = 1;
buffer->consec_oldsn_drops++;

/* if limit is reached, send del BA and reset state */
if (buffer->consec_oldsn_drops == IWX_AMPDU_CONSEC_DROPS_DELBA10) {
ieee80211_delba_request(ic, ni, IEEE80211_REASON_UNSPECIFIED,
    0, tid);
buffer->consec_oldsn_prev_drop = 0;
buffer->consec_oldsn_drops = 0;
return 1;
}

return 0;
4928}

4930/*
* Handle re-ordering of frames which were de-aggregated in hardware.
* Returns 1 if the MPDU was consumed (buffered or dropped).
* Returns 0 if the MPDU should be passed to upper layer.
*/
4935int
4936iwx_rx_reorder(struct iwx_softc *sc, struct mbuf *m, int chanidx,
  struct iwx_rx_mpdu_desc *desc, int is_shortpre, int rate_n_flags,
  uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,
  struct mbuf_list *ml)
4940{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_frame *wh;
struct ieee80211_node *ni;
struct iwx_rxba_data *rxba;
struct iwx_reorder_buffer *buffer;
uint32_t reorder_data = le32toh(desc->reorder_data)((__uint32_t)(desc->reorder_data));
int is_amsdu = (desc->mac_flags2 & IWX_RX_MPDU_MFLG2_AMSDU0x40);
int last_subframe =
(desc->amsdu_info & IWX_RX_MPDU_AMSDU_LAST_SUBFRAME0x80);
uint8_t tid;
uint8_t subframe_idx = (desc->amsdu_info &
   IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK0x7f);
struct iwx_reorder_buf_entry *entries;
int index;
uint16_t nssn, sn;
uint8_t baid, type, subtype;
int hasqos;

wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
hasqos = ieee80211_has_qos(wh);
tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID0x000f : 0;

type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK0xf0;

/*
* We are only interested in Block Ack requests and unicast QoS data.
*/
if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01))
return 0;
if (hasqos) {
if (subtype & IEEE80211_FC0_SUBTYPE_NODATA0x40)
	return 0;
} else {
if (type != IEEE80211_FC0_TYPE_CTL0x04 ||
    subtype != IEEE80211_FC0_SUBTYPE_BAR0x80)
	return 0;
}

baid = (reorder_data & IWX_RX_MPDU_REORDER_BAID_MASK0x7f000000) >>
IWX_RX_MPDU_REORDER_BAID_SHIFT24;
if (baid == IWX_RX_REORDER_DATA_INVALID_BAID0x7f ||
   baid >= nitems(sc->sc_rxba_data)(sizeof((sc->sc_rxba_data)) / sizeof((sc->sc_rxba_data)
[0])))
return 0;

rxba = &sc->sc_rxba_data[baid];
if (rxba->baid == IWX_RX_REORDER_DATA_INVALID_BAID0x7f ||
   tid != rxba->tid || rxba->sta_id != IWX_STATION_ID0)
return 0;

if (rxba->timeout != 0)
getmicrouptime(&rxba->last_rx);

/* Bypass A-MPDU re-ordering in net80211. */
rxi->rxi_flags |= IEEE80211_RXI_AMPDU_DONE0x00000002;

nssn = reorder_data & IWX_RX_MPDU_REORDER_NSSN_MASK0x00000fff;
sn = (reorder_data & IWX_RX_MPDU_REORDER_SN_MASK0x00fff000) >>
IWX_RX_MPDU_REORDER_SN_SHIFT12;

buffer = &rxba->reorder_buf;
entries = &rxba->entries[0];

if (!buffer->valid) {
if (reorder_data & IWX_RX_MPDU_REORDER_BA_OLD_SN0x80000000)
	return 0;
buffer->valid = 1;
}

ni = ieee80211_find_rxnode(ic, wh);
if (type == IEEE80211_FC0_TYPE_CTL0x04 &&
   subtype == IEEE80211_FC0_SUBTYPE_BAR0x80) {
iwx_release_frames(sc, ni, rxba, buffer, nssn, ml);
goto drop;
}

/*
* If there was a significant jump in the nssn - adjust.
* If the SN is smaller than the NSSN it might need to first go into
* the reorder buffer, in which case we just release up to it and the
* rest of the function will take care of storing it and releasing up to
* the nssn.
*/
if (!iwx_is_sn_less(nssn, buffer->head_sn + buffer->buf_size,
   buffer->buf_size) ||
   !SEQ_LT(sn, buffer->head_sn + buffer->buf_size)((((u_int16_t)(sn) - (u_int16_t)(buffer->head_sn + buffer->
buf_size)) & 0xfff) > 2048)) {
uint16_t min_sn = SEQ_LT(sn, nssn)((((u_int16_t)(sn) - (u_int16_t)(nssn)) & 0xfff) > 2048
) ? sn : nssn;
ic->ic_stats.is_ht_rx_frame_above_ba_winend++;
iwx_release_frames(sc, ni, rxba, buffer, min_sn, ml);
}

if (iwx_oldsn_workaround(sc, ni, tid, buffer, reorder_data,
   device_timestamp)) {
 /* BA session will be torn down. */
ic->ic_stats.is_ht_rx_ba_window_jump++;
goto drop;

}

/* drop any outdated packets */
if (SEQ_LT(sn, buffer->head_sn)((((u_int16_t)(sn) - (u_int16_t)(buffer->head_sn)) & 0xfff
) > 2048)) {
ic->ic_stats.is_ht_rx_frame_below_ba_winstart++;
goto drop;
}

/* release immediately if allowed by nssn and no stored frames */
if (!buffer->num_stored && SEQ_LT(sn, nssn)((((u_int16_t)(sn) - (u_int16_t)(nssn)) & 0xfff) > 2048
)) {
if (iwx_is_sn_less(buffer->head_sn, nssn, buffer->buf_size) &&
   (!is_amsdu || last_subframe))
	buffer->head_sn = nssn;
ieee80211_release_node(ic, ni);
return 0;
}

/*
* release immediately if there are no stored frames, and the sn is
* equal to the head.
* This can happen due to reorder timer, where NSSN is behind head_sn.
* When we released everything, and we got the next frame in the
* sequence, according to the NSSN we can't release immediately,
* while technically there is no hole and we can move forward.
*/
if (!buffer->num_stored && sn == buffer->head_sn) {
if (!is_amsdu || last_subframe)
	buffer->head_sn = (buffer->head_sn + 1) & 0xfff;
ieee80211_release_node(ic, ni);
return 0;
}

index = sn % buffer->buf_size;

/*
* Check if we already stored this frame
* As AMSDU is either received or not as whole, logic is simple:
* If we have frames in that position in the buffer and the last frame
* originated from AMSDU had a different SN then it is a retransmission.
* If it is the same SN then if the subframe index is incrementing it
* is the same AMSDU - otherwise it is a retransmission.
*/
if (!ml_empty(&entries[index].frames)((&entries[index].frames)->ml_len == 0)) {
if (!is_amsdu) {
	ic->ic_stats.is_ht_rx_ba_no_buf++;
	goto drop;
} else if (sn != buffer->last_amsdu ||
    buffer->last_sub_index >= subframe_idx) {
	ic->ic_stats.is_ht_rx_ba_no_buf++;
	goto drop;
}
} else {
/* This data is the same for all A-MSDU subframes. */
entries[index].chanidx = chanidx;
entries[index].is_shortpre = is_shortpre;
entries[index].rate_n_flags = rate_n_flags;
entries[index].device_timestamp = device_timestamp;
memcpy(&entries[index].rxi, rxi, sizeof(entries[index].rxi))__builtin_memcpy((&entries[index].rxi), (rxi), (sizeof(entries
[index].rxi)));
}

/* put in reorder buffer */
ml_enqueue(&entries[index].frames, m);
buffer->num_stored++;
getmicrouptime(&entries[index].reorder_time);

if (is_amsdu) {
buffer->last_amsdu = sn;
buffer->last_sub_index = subframe_idx;
}

/*
* We cannot trust NSSN for AMSDU sub-frames that are not the last.
* The reason is that NSSN advances on the first sub-frame, and may
* cause the reorder buffer to advance before all the sub-frames arrive.
* Example: reorder buffer contains SN 0 & 2, and we receive AMSDU with
* SN 1. NSSN for first sub frame will be 3 with the result of driver
* releasing SN 0,1, 2. When sub-frame 1 arrives - reorder buffer is
* already ahead and it will be dropped.
* If the last sub-frame is not on this queue - we will get frame
* release notification with up to date NSSN.
*/
if (!is_amsdu || last_subframe)
iwx_release_frames(sc, ni, rxba, buffer, nssn, ml);

ieee80211_release_node(ic, ni);
return 1;

5125drop:
m_freem(m);
ieee80211_release_node(ic, ni);
return 1;
5129}

5131void
5132iwx_rx_mpdu_mq(struct iwx_softc *sc, struct mbuf *m, void *pktdata,
  size_t maxlen, struct mbuf_list *ml)
5134{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_rxinfo rxi;
struct iwx_rx_mpdu_desc *desc;
uint32_t len, hdrlen, rate_n_flags, device_timestamp;
int rssi;
uint8_t chanidx;
uint16_t phy_info;
size_t desc_size;

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102)
desc_size = sizeof(*desc);
else
desc_size = IWX_RX_DESC_SIZE_V1((sizeof(struct iwx_rx_mpdu_desc) - sizeof(struct iwx_rx_mpdu_desc_v3
)) + sizeof(struct iwx_rx_mpdu_desc_v1));

if (maxlen < desc_size) {
m_freem(m);
return; /* drop */
}

desc = (struct iwx_rx_mpdu_desc *)pktdata;

if (!(desc->status & htole16(IWX_RX_MPDU_RES_STATUS_CRC_OK)((__uint16_t)((1 << 0)))) ||
   !(desc->status & htole16(IWX_RX_MPDU_RES_STATUS_OVERRUN_OK)((__uint16_t)((1 << 1))))) {
m_freem(m);
return; /* drop */
}

len = le16toh(desc->mpdu_len)((__uint16_t)(desc->mpdu_len));
if (ic->ic_opmode == IEEE80211_M_MONITOR) {
/* Allow control frames in monitor mode. */
if (len < sizeof(struct ieee80211_frame_cts)) {
	ic->ic_stats.is_rx_tooshort++;
	IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_ierrorsif_data.ifi_ierrors++;
	m_freem(m);
	return;
}
} else if (len < sizeof(struct ieee80211_frame)) {
ic->ic_stats.is_rx_tooshort++;
IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_ierrorsif_data.ifi_ierrors++;
m_freem(m);
return;
}
if (len > maxlen - desc_size) {
IC2IFP(ic)(&(ic)->ic_ac.ac_if)->if_ierrorsif_data.ifi_ierrors++;
m_freem(m);
return;
}

m->m_datam_hdr.mh_data = pktdata + desc_size;
m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = len;

/* Account for padding following the frame header. */
if (desc->mac_flags2 & IWX_RX_MPDU_MFLG2_PAD0x20) {
struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
if (type == IEEE80211_FC0_TYPE_CTL0x04) {
	switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK0xf0) {
	case IEEE80211_FC0_SUBTYPE_CTS0xc0:
		hdrlen = sizeof(struct ieee80211_frame_cts);
		break;
	case IEEE80211_FC0_SUBTYPE_ACK0xd0:
		hdrlen = sizeof(struct ieee80211_frame_ack);
		break;
	default:
		hdrlen = sizeof(struct ieee80211_frame_min);
		break;
	}
} else
	hdrlen = ieee80211_get_hdrlen(wh);

if ((le16toh(desc->status)((__uint16_t)(desc->status)) &
    IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK(7 << 8)) ==
    IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC(2 << 8)) {
	/* Padding is inserted after the IV. */
	hdrlen += IEEE80211_CCMP_HDRLEN8;
}

memmove(m->m_data + 2, m->m_data, hdrlen)__builtin_memmove((m->m_hdr.mh_data + 2), (m->m_hdr.mh_data
), (hdrlen));
m_adj(m, 2);
}

memset(&rxi, 0, sizeof(rxi))__builtin_memset((&rxi), (0), (sizeof(rxi)));

/*
* Hardware de-aggregates A-MSDUs and copies the same MAC header
* in place for each subframe. But it leaves the 'A-MSDU present'
* bit set in the frame header. We need to clear this bit ourselves.
* (XXX This workaround is not required on AX200/AX201 devices that
* have been tested by me, but it's unclear when this problem was
* fixed in the hardware. It definitely affects the 9k generation.
* Leaving this in place for now since some 9k/AX200 hybrids seem
* to exist that we may eventually add support for.)
*
* And we must allow the same CCMP PN for subframes following the
* first subframe. Otherwise they would be discarded as replays.
*/
if (desc->mac_flags2 & IWX_RX_MPDU_MFLG2_AMSDU0x40) {
struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
uint8_t subframe_idx = (desc->amsdu_info &
    IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK0x7f);
if (subframe_idx > 0)
	rxi.rxi_flags |= IEEE80211_RXI_HWDEC_SAME_PN0x00000004;
if (ieee80211_has_qos(wh) && ieee80211_has_addr4(wh) &&
    m->m_lenm_hdr.mh_len >= sizeof(struct ieee80211_qosframe_addr4)) {
	struct ieee80211_qosframe_addr4 *qwh4 = mtod(m,((struct ieee80211_qosframe_addr4 *)((m)->m_hdr.mh_data))
	    struct ieee80211_qosframe_addr4 *)((struct ieee80211_qosframe_addr4 *)((m)->m_hdr.mh_data));
	qwh4->i_qos[0] &= htole16(~IEEE80211_QOS_AMSDU)((__uint16_t)(~0x0080));
} else if (ieee80211_has_qos(wh) &&
    m->m_lenm_hdr.mh_len >= sizeof(struct ieee80211_qosframe)) {
	struct ieee80211_qosframe *qwh = mtod(m,((struct ieee80211_qosframe *)((m)->m_hdr.mh_data))
	    struct ieee80211_qosframe *)((struct ieee80211_qosframe *)((m)->m_hdr.mh_data));
	qwh->i_qos[0] &= htole16(~IEEE80211_QOS_AMSDU)((__uint16_t)(~0x0080));
}
}

/*
* Verify decryption before duplicate detection. The latter uses
* the TID supplied in QoS frame headers and this TID is implicitly
* verified as part of the CCMP nonce.
*/
if (iwx_rx_hwdecrypt(sc, m, le16toh(desc->status)((__uint16_t)(desc->status)), &rxi)) {
m_freem(m);
return;
}

if (iwx_detect_duplicate(sc, m, desc, &rxi)) {
m_freem(m);
return;
}

if (sc->sc_device_family >= IWX_DEVICE_FAMILY_AX2102) {
rate_n_flags = le32toh(desc->v3.rate_n_flags)((__uint32_t)(desc->v3.rate_n_flags));
chanidx = desc->v3.channel;
device_timestamp = le32toh(desc->v3.gp2_on_air_rise)((__uint32_t)(desc->v3.gp2_on_air_rise));
} else {
rate_n_flags = le32toh(desc->v1.rate_n_flags)((__uint32_t)(desc->v1.rate_n_flags));
chanidx = desc->v1.channel;
device_timestamp = le32toh(desc->v1.gp2_on_air_rise)((__uint32_t)(desc->v1.gp2_on_air_rise));
}

phy_info = le16toh(desc->phy_info)((__uint16_t)(desc->phy_info));

rssi = iwx_rxmq_get_signal_strength(sc, desc);
rssi = (0 - IWX_MIN_DBM-100) + rssi;	/* normalize */
rssi = MIN(rssi, ic->ic_max_rssi)(((rssi)<(ic->ic_max_rssi))?(rssi):(ic->ic_max_rssi)
);	/* clip to max. 100% */

rxi.rxi_rssi = rssi;
rxi.rxi_tstamp = device_timestamp;
rxi.rxi_chan = chanidx;

if (iwx_rx_reorder(sc, m, chanidx, desc,
   (phy_info & IWX_RX_MPDU_PHY_SHORT_PREAMBLE(1 << 7)),
   rate_n_flags, device_timestamp, &rxi, ml))
return;

iwx_rx_frame(sc, m, chanidx, le16toh(desc->status)((__uint16_t)(desc->status)),
   (phy_info & IWX_RX_MPDU_PHY_SHORT_PREAMBLE(1 << 7)),
   rate_n_flags, device_timestamp, &rxi, ml);
5293}

5295void
5296iwx_clear_tx_desc(struct iwx_softc *sc, struct iwx_tx_ring *ring, int idx)
5297{
struct iwx_tfh_tfd *desc = &ring->desc[idx];
uint8_t num_tbs = le16toh(desc->num_tbs)((__uint16_t)(desc->num_tbs)) & 0x1f;
int i;

/* First TB is never cleared - it is bidirectional DMA data. */
for (i = 1; i < num_tbs; i++) {
struct iwx_tfh_tb *tb = &desc->tbs[i];
memset(tb, 0, sizeof(*tb))__builtin_memset((tb), (0), (sizeof(*tb)));
}
desc->num_tbs = htole16(1)((__uint16_t)(1));

bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
desc_dma.map), ((char *)(void *)desc - (char *)(void *)ring->
desc_dma.vaddr), (sizeof(*desc)), (0x04))
   (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
desc_dma.map), ((char *)(void *)desc - (char *)(void *)ring->
desc_dma.vaddr), (sizeof(*desc)), (0x04))
   sizeof(*desc), BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (ring->
desc_dma.map), ((char *)(void *)desc - (char *)(void *)ring->
desc_dma.vaddr), (sizeof(*desc)), (0x04));
5312}

5314void
5315iwx_txd_done(struct iwx_softc *sc, struct iwx_tx_data *txd)
5316{
struct ieee80211com *ic = &sc->sc_ic;

bus_dmamap_sync(sc->sc_dmat, txd->map, 0, txd->map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txd->
map), (0), (txd->map->dm_mapsize), (0x08))
   BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txd->
map), (0), (txd->map->dm_mapsize), (0x08));
bus_dmamap_unload(sc->sc_dmat, txd->map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (txd
->map));
m_freem(txd->m);
txd->m = NULL((void *)0);

KASSERT(txd->in)((txd->in) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_iwx.c"
, 5325, "txd->in"));
ieee80211_release_node(ic, &txd->in->in_ni);
txd->in = NULL((void *)0);
5328}

5330void
5331iwx_txq_advance(struct iwx_softc *sc, struct iwx_tx_ring *ring, uint16_t idx)
5332{
struct iwx_tx_data *txd;

while (ring->tail_hw != idx) {
txd = &ring->data[ring->tail];
if (txd->m != NULL((void *)0)) {
	iwx_clear_tx_desc(sc, ring, ring->tail);
	iwx_tx_update_byte_tbl(sc, ring, ring->tail, 0, 0);
	iwx_txd_done(sc, txd);
	ring->queued--;
}
ring->tail = (ring->tail + 1) % IWX_TX_RING_COUNT(256);
ring->tail_hw = (ring->tail_hw + 1) % sc->max_tfd_queue_size;
}
5346}

5348void
5349iwx_rx_tx_cmd(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
  struct iwx_rx_data *data)
5351{
struct ieee80211com *ic = &sc->sc_ic;
struct ifnet *ifp = IC2IFP(ic)(&(ic)->ic_ac.ac_if);
struct iwx_cmd_header *cmd_hdr = &pkt->hdr;
int qid = cmd_hdr->qid, status, txfail;
struct iwx_tx_ring *ring = &sc->txq[qid];
struct iwx_tx_resp *tx_resp = (void *)pkt->data;
uint32_t ssn;
uint32_t len = iwx_rx_packet_len(pkt);

bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWX_RBUF_SIZE,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (4096), (0x02))
   BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (0), (4096), (0x02));

/* Sanity checks. */
if (sizeof(*tx_resp) > len)
return;
if (qid < IWX_FIRST_AGG_TX_QUEUE(1 + 1) && tx_resp->frame_count > 1)
return;
if (qid >= IWX_FIRST_AGG_TX_QUEUE(1 + 1) && sizeof(*tx_resp) + sizeof(ssn) +
   tx_resp->frame_count * sizeof(tx_resp->status) > len)
return;

sc->sc_tx_timer[qid] = 0;

if (tx_resp->frame_count > 1) /* A-MPDU */
return;

status = le16toh(tx_resp->status.status)((__uint16_t)(tx_resp->status.status)) & IWX_TX_STATUS_MSK0x000000ff;
txfail = (status != IWX_TX_STATUS_SUCCESS0x01 &&
   status != IWX_TX_STATUS_DIRECT_DONE0x02);

if (txfail)
ifp->if_oerrorsif_data.ifi_oerrors++;

/*
* On hardware supported by iwx(4) the SSN counter corresponds
* to a Tx ring index rather than a sequence number.
* Frames up to this index (non-inclusive) can now be freed.
*/
memcpy(&ssn, &tx_resp->status + tx_resp->frame_count, sizeof(ssn))__builtin_memcpy((&ssn), (&tx_resp->status + tx_resp
->frame_count), (sizeof(ssn)));
ssn = le32toh(ssn)((__uint32_t)(ssn));
if (ssn < sc->max_tfd_queue_size) {
iwx_txq_advance(sc, ring, ssn);
iwx_clear_oactive(sc, ring);
}
5396}

5398void
5399iwx_clear_oactive(struct iwx_softc *sc, struct iwx_tx_ring *ring)
5400{
struct ieee80211com *ic = &sc->sc_ic;
struct ifnet *ifp = IC2IFP(ic)(&(ic)->ic_ac.ac_if);

if (ring->queued < IWX_TX_RING_LOMARK192) {
sc->qfullmsk &= ~(1 << ring->qid);
if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) {
	ifq_clr_oactive(&ifp->if_snd);
	/*
	 * Well, we're in interrupt context, but then again
	 * I guess net80211 does all sorts of stunts in
	 * interrupt context, so maybe this is no biggie.
	 */
	(*ifp->if_start)(ifp);
}
}
5416}

5418void
5419iwx_rx_compressed_ba(struct iwx_softc *sc, struct iwx_rx_packet *pkt)
5420{
struct iwx_compressed_ba_notif *ba_res = (void *)pkt->data;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni;
struct ieee80211_tx_ba *ba;
struct iwx_node *in;
struct iwx_tx_ring *ring;
uint16_t i, tfd_cnt, ra_tid_cnt, idx;
int qid;

if (ic->ic_state != IEEE80211_S_RUN)
return;

if (iwx_rx_packet_payload_len(pkt) < sizeof(*ba_res))
return;

if (ba_res->sta_id != IWX_STATION_ID0)
return;

ni = ic->ic_bss;
in = (void *)ni;

tfd_cnt = le16toh(ba_res->tfd_cnt)((__uint16_t)(ba_res->tfd_cnt));
ra_tid_cnt = le16toh(ba_res->ra_tid_cnt)((__uint16_t)(ba_res->ra_tid_cnt));
if (!tfd_cnt || iwx_rx_packet_payload_len(pkt) < (sizeof(*ba_res) +
   sizeof(ba_res->ra_tid[0]) * ra_tid_cnt +
   sizeof(ba_res->tfd[0]) * tfd_cnt))
return;

for (i = 0; i < tfd_cnt; i++) {
struct iwx_compressed_ba_tfd *ba_tfd = &ba_res->tfd[i];
uint8_t tid;

tid = ba_tfd->tid;
if (tid >= nitems(sc->aggqid)(sizeof((sc->aggqid)) / sizeof((sc->aggqid)[0])))
	continue;

qid = sc->aggqid[tid];
if (qid != htole16(ba_tfd->q_num)((__uint16_t)(ba_tfd->q_num)))
	continue;

ring = &sc->txq[qid];

ba = &ni->ni_tx_ba[tid];
if (ba->ba_state != IEEE80211_BA_AGREED2)
	continue;

idx = le16toh(ba_tfd->tfd_index)((__uint16_t)(ba_tfd->tfd_index));
sc->sc_tx_timer[qid] = 0;
iwx_txq_advance(sc, ring, idx);
iwx_clear_oactive(sc, ring);
}
5472}

5474void
5475iwx_rx_bmiss(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
  struct iwx_rx_data *data)
5477{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_missed_beacons_notif *mbn = (void *)pkt->data;
uint32_t missed;

if ((ic->ic_opmode != IEEE80211_M_STA) ||
   (ic->ic_state != IEEE80211_S_RUN))
return;

bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*pkt),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (sizeof(*pkt)), (sizeof(*mbn)), (0x02))
   sizeof(*mbn), BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (data->
map), (sizeof(*pkt)), (sizeof(*mbn)), (0x02));

missed = le32toh(mbn->consec_missed_beacons_since_last_rx)((__uint32_t)(mbn->consec_missed_beacons_since_last_rx));
if (missed > ic->ic_bmissthres && ic->ic_mgt_timer == 0) {
if (ic->ic_ific_ac.ac_if.if_flags & IFF_DEBUG0x4)
	printf("%s: receiving no beacons from %s; checking if "
	    "this AP is still responding to probe requests\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), ether_sprintf(ic->ic_bss->ni_macaddr));
/*
 * Rather than go directly to scan state, try to send a
 * directed probe request first. If that fails then the
 * state machine will drop us into scanning after timing
 * out waiting for a probe response.
 */
IEEE80211_SEND_MGMT(ic, ic->ic_bss,((*(ic)->ic_send_mgmt)(ic, ic->ic_bss, 0x40, 0, 0))
    IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0)((*(ic)->ic_send_mgmt)(ic, ic->ic_bss, 0x40, 0, 0));
}

5505}

5507int
5508iwx_binding_cmd(struct iwx_softc *sc, struct iwx_node *in, uint32_t action)
5509{
struct iwx_binding_cmd cmd;
struct iwx_phy_ctxt *phyctxt = in->in_phyctxt;
uint32_t mac_id = IWX_FW_CMD_ID_AND_COLOR(in->in_id, in->in_color)((in->in_id << (0)) | (in->in_color << (8))
);
int i, err, active = (sc->sc_flags & IWX_FLAG_BINDING_ACTIVE0x10);
uint32_t status;

if (action == IWX_FW_CTXT_ACTION_ADD1 && active)
panic("binding already added");
if (action == IWX_FW_CTXT_ACTION_REMOVE3 && !active)
panic("binding already removed");

if (phyctxt == NULL((void *)0)) /* XXX race with iwx_stop() */
return EINVAL22;

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));

cmd.id_and_color
   = htole32(IWX_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color))((__uint32_t)(((phyctxt->id << (0)) | (phyctxt->color
 << (8)))));
cmd.action = htole32(action)((__uint32_t)(action));
cmd.phy = htole32(IWX_FW_CMD_ID_AND_COLOR(phyctxt->id, phyctxt->color))((__uint32_t)(((phyctxt->id << (0)) | (phyctxt->color
 << (8)))));

cmd.macs[0] = htole32(mac_id)((__uint32_t)(mac_id));
for (i = 1; i < IWX_MAX_MACS_IN_BINDING(3); i++)
cmd.macs[i] = htole32(IWX_FW_CTXT_INVALID)((__uint32_t)((0xffffffff)));

if (IEEE80211_IS_CHAN_2GHZ(phyctxt->channel)(((phyctxt->channel)->ic_flags & 0x0080) != 0) ||
   !isset(sc->sc_enabled_capa, IWX_UCODE_TLV_CAPA_CDB_SUPPORT)((sc->sc_enabled_capa)[(40)>>3] & (1<<((40
)&(8 -1)))))
cmd.lmac_id = htole32(IWX_LMAC_24G_INDEX)((__uint32_t)(0));
else
cmd.lmac_id = htole32(IWX_LMAC_5G_INDEX)((__uint32_t)(1));

status = 0;
err = iwx_send_cmd_pdu_status(sc, IWX_BINDING_CONTEXT_CMD0x2b, sizeof(cmd),
   &cmd, &status);
if (err == 0 && status != 0)
err = EIO5;

return err;
5548}

5550uint8_t
5551iwx_get_vht_ctrl_pos(struct ieee80211com *ic, struct ieee80211_channel *chan)
5552{
int center_idx = ic->ic_bss->ni_vht_chan_center_freq_idx0;
int primary_idx = ic->ic_bss->ni_primary_chan;
/*
* The FW is expected to check the control channel position only
* when in HT/VHT and the channel width is not 20MHz. Return
* this value as the default one:
*/
uint8_t pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);

switch (primary_idx - center_idx) {
case -6:
pos = IWX_PHY_VHT_CTRL_POS_2_BELOW(0x1);
break;
case -2:
pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
break;
case 2:
pos = IWX_PHY_VHT_CTRL_POS_1_ABOVE(0x4);
break;
case 6:
pos = IWX_PHY_VHT_CTRL_POS_2_ABOVE(0x5);
break;
default:
break;
}

return pos;
5580}

5582int
5583iwx_phy_ctxt_cmd_uhb_v3_v4(struct iwx_softc *sc, struct iwx_phy_ctxt *ctxt,
  uint8_t chains_static, uint8_t chains_dynamic, uint32_t action, uint8_t sco,
  uint8_t vht_chan_width, int cmdver)
5586{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_phy_context_cmd_uhb cmd;
uint8_t active_cnt, idle_cnt;
struct ieee80211_channel *chan = ctxt->channel;

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));
cmd.id_and_color = htole32(IWX_FW_CMD_ID_AND_COLOR(ctxt->id,((__uint32_t)(((ctxt->id << (0)) | (ctxt->color <<
 (8)))))
   ctxt->color))((__uint32_t)(((ctxt->id << (0)) | (ctxt->color <<
 (8)))));
cmd.action = htole32(action)((__uint32_t)(action));

if (IEEE80211_IS_CHAN_2GHZ(ctxt->channel)(((ctxt->channel)->ic_flags & 0x0080) != 0) ||
   !isset(sc->sc_enabled_capa, IWX_UCODE_TLV_CAPA_CDB_SUPPORT)((sc->sc_enabled_capa)[(40)>>3] & (1<<((40
)&(8 -1)))))
cmd.lmac_id = htole32(IWX_LMAC_24G_INDEX)((__uint32_t)(0));
else
cmd.lmac_id = htole32(IWX_LMAC_5G_INDEX)((__uint32_t)(1));

cmd.ci.band = IEEE80211_IS_CHAN_2GHZ(chan)(((chan)->ic_flags & 0x0080) != 0) ?
   IWX_PHY_BAND_24(1) : IWX_PHY_BAND_5(0);
cmd.ci.channel = htole32(ieee80211_chan2ieee(ic, chan))((__uint32_t)(ieee80211_chan2ieee(ic, chan)));
if (vht_chan_width == IEEE80211_VHTOP0_CHAN_WIDTH_801) {
cmd.ci.ctrl_pos = iwx_get_vht_ctrl_pos(ic, chan);
cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE80(0x2);
} else if (chan->ic_flags & IEEE80211_CHAN_40MHZ0x8000) {
if (sco == IEEE80211_HTOP0_SCO_SCA1) {
	/* secondary chan above -> control chan below */
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE40(0x1);
} else if (sco == IEEE80211_HTOP0_SCO_SCB3) {
	/* secondary chan below -> control chan above */
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_ABOVE(0x4);
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE40(0x1);
} else {
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE20(0x0);
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
}
} else {
cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE20(0x0);
cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
}

if (cmdver < 4 && iwx_lookup_cmd_ver(sc, IWX_DATA_PATH_GROUP0x5,
   IWX_RLC_CONFIG_CMD0x08) != 2) {
idle_cnt = chains_static;
active_cnt = chains_dynamic;
cmd.rxchain_info = htole32(iwx_fw_valid_rx_ant(sc) <<((__uint32_t)(iwx_fw_valid_rx_ant(sc) << (1)))
    IWX_PHY_RX_CHAIN_VALID_POS)((__uint32_t)(iwx_fw_valid_rx_ant(sc) << (1)));
cmd.rxchain_info |= htole32(idle_cnt <<((__uint32_t)(idle_cnt << (10)))
    IWX_PHY_RX_CHAIN_CNT_POS)((__uint32_t)(idle_cnt << (10)));
cmd.rxchain_info |= htole32(active_cnt <<((__uint32_t)(active_cnt << (12)))
    IWX_PHY_RX_CHAIN_MIMO_CNT_POS)((__uint32_t)(active_cnt << (12)));
}

return iwx_send_cmd_pdu(sc, IWX_PHY_CONTEXT_CMD0x8, 0, sizeof(cmd), &cmd);
5640}

5642int
5643iwx_phy_ctxt_cmd_v3_v4(struct iwx_softc *sc, struct iwx_phy_ctxt *ctxt,
  uint8_t chains_static, uint8_t chains_dynamic, uint32_t action, uint8_t sco,
  uint8_t vht_chan_width, int cmdver)
5646{
struct ieee80211com *ic = &sc->sc_ic;
struct iwx_phy_context_cmd cmd;
uint8_t active_cnt, idle_cnt;
struct ieee80211_channel *chan = ctxt->channel;

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));
cmd.id_and_color = htole32(IWX_FW_CMD_ID_AND_COLOR(ctxt->id,((__uint32_t)(((ctxt->id << (0)) | (ctxt->color <<
 (8)))))
   ctxt->color))((__uint32_t)(((ctxt->id << (0)) | (ctxt->color <<
 (8)))));
cmd.action = htole32(action)((__uint32_t)(action));

if (IEEE80211_IS_CHAN_2GHZ(ctxt->channel)(((ctxt->channel)->ic_flags & 0x0080) != 0) ||
   !isset(sc->sc_enabled_capa, IWX_UCODE_TLV_CAPA_CDB_SUPPORT)((sc->sc_enabled_capa)[(40)>>3] & (1<<((40
)&(8 -1)))))
cmd.lmac_id = htole32(IWX_LMAC_24G_INDEX)((__uint32_t)(0));
else
cmd.lmac_id = htole32(IWX_LMAC_5G_INDEX)((__uint32_t)(1));

cmd.ci.band = IEEE80211_IS_CHAN_2GHZ(chan)(((chan)->ic_flags & 0x0080) != 0) ?
   IWX_PHY_BAND_24(1) : IWX_PHY_BAND_5(0);
cmd.ci.channel = ieee80211_chan2ieee(ic, chan);
if (vht_chan_width == IEEE80211_VHTOP0_CHAN_WIDTH_801) {
cmd.ci.ctrl_pos = iwx_get_vht_ctrl_pos(ic, chan);
cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE80(0x2);
} else if (chan->ic_flags & IEEE80211_CHAN_40MHZ0x8000) {
if (sco == IEEE80211_HTOP0_SCO_SCA1) {
	/* secondary chan above -> control chan below */
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE40(0x1);
} else if (sco == IEEE80211_HTOP0_SCO_SCB3) {
	/* secondary chan below -> control chan above */
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_ABOVE(0x4);
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE40(0x1);
} else {
	cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE20(0x0);
	cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
}
} else {
cmd.ci.width = IWX_PHY_VHT_CHANNEL_MODE20(0x0);
cmd.ci.ctrl_pos = IWX_PHY_VHT_CTRL_POS_1_BELOW(0x0);
}

if (cmdver < 4 && iwx_lookup_cmd_ver(sc, IWX_DATA_PATH_GROUP0x5,
   IWX_RLC_CONFIG_CMD0x08) != 2) {
idle_cnt = chains_static;
active_cnt = chains_dynamic;
cmd.rxchain_info = htole32(iwx_fw_valid_rx_ant(sc) <<((__uint32_t)(iwx_fw_valid_rx_ant(sc) << (1)))
    IWX_PHY_RX_CHAIN_VALID_POS)((__uint32_t)(iwx_fw_valid_rx_ant(sc) << (1)));
cmd.rxchain_info |= htole32(idle_cnt <<((__uint32_t)(idle_cnt << (10)))
    IWX_PHY_RX_CHAIN_CNT_POS)((__uint32_t)(idle_cnt << (10)));
cmd.rxchain_info |= htole32(active_cnt <<((__uint32_t)(active_cnt << (12)))
    IWX_PHY_RX_CHAIN_MIMO_CNT_POS)((__uint32_t)(active_cnt << (12)));
}

return iwx_send_cmd_pdu(sc, IWX_PHY_CONTEXT_CMD0x8, 0, sizeof(cmd), &cmd);
5700}

5702int
5703iwx_phy_ctxt_cmd(struct iwx_softc *sc, struct iwx_phy_ctxt *ctxt,
  uint8_t chains_static, uint8_t chains_dynamic, uint32_t action,
  uint32_t apply_time, uint8_t sco, uint8_t vht_chan_width)
5706{
int cmdver;

cmdver = iwx_lookup_cmd_ver(sc, IWX_LONG_GROUP0x1, IWX_PHY_CONTEXT_CMD0x8);
if (cmdver != 3 && cmdver != 4) {
5711